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kvm: x86: Add has_payload and payload to kvm_queued_exception
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
3b8a5df6 139unsigned int __read_mostly lapic_timer_advance_ns = 1000;
d0659d94 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 141EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 142
52004014
FW		 143static bool __read_mostly vector_hashing = true;
144module_param(vector_hashing, bool, S_IRUGO);
145
c4ae60e4
LA		 146bool __read_mostly enable_vmware_backdoor = false;
147module_param(enable_vmware_backdoor, bool, S_IRUGO);
148EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
149
6c86eedc
WL		 150static bool __read_mostly force_emulation_prefix = false;
151module_param(force_emulation_prefix, bool, S_IRUGO);
152
18863bdd
AK		 153#define KVM_NR_SHARED_MSRS 16
154
155struct kvm_shared_msrs_global {
156 int nr;
2bf78fa7 157 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 158};
159
160struct kvm_shared_msrs {
161 struct user_return_notifier urn;
162 bool registered;
2bf78fa7
SY		 163 struct kvm_shared_msr_values {
164 u64 host;
165 u64 curr;
166 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 167};
168
169static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 170static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 171
417bc304 172struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 173 { "pf_fixed", VCPU_STAT(pf_fixed) },
174 { "pf_guest", VCPU_STAT(pf_guest) },
175 { "tlb_flush", VCPU_STAT(tlb_flush) },
176 { "invlpg", VCPU_STAT(invlpg) },
177 { "exits", VCPU_STAT(exits) },
178 { "io_exits", VCPU_STAT(io_exits) },
179 { "mmio_exits", VCPU_STAT(mmio_exits) },
180 { "signal_exits", VCPU_STAT(signal_exits) },
181 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 182 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 183 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 184 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 185 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 186 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 187 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 188 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 189 { "request_irq", VCPU_STAT(request_irq_exits) },
190 { "irq_exits", VCPU_STAT(irq_exits) },
191 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 192 { "fpu_reload", VCPU_STAT(fpu_reload) },
193 { "insn_emulation", VCPU_STAT(insn_emulation) },
194 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 195 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 196 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 197 { "req_event", VCPU_STAT(req_event) },
c595ceee 198 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 199 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
200 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
201 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
202 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
203 { "mmu_flooded", VM_STAT(mmu_flooded) },
204 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 205 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 206 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 207 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 208 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 209 { "max_mmu_page_hash_collisions",
210 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 211 { NULL }
212};
213
2acf923e
DC		 214u64 __read_mostly host_xcr0;
215
b6785def 216static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 217
af585b92
GN		 218static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
219{
220 int i;
221 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
222 vcpu->arch.apf.gfns[i] = ~0;
223}
224
18863bdd
AK		 225static void kvm_on_user_return(struct user_return_notifier *urn)
226{
227 unsigned slot;
18863bdd
AK		 228 struct kvm_shared_msrs *locals
229 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 230 struct kvm_shared_msr_values *values;
1650b4eb
IA		 231 unsigned long flags;
232
233 /*
234 * Disabling irqs at this point since the following code could be
235 * interrupted and executed through kvm_arch_hardware_disable()
236 */
237 local_irq_save(flags);
238 if (locals->registered) {
239 locals->registered = false;
240 user_return_notifier_unregister(urn);
241 }
242 local_irq_restore(flags);
18863bdd 243 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 244 values = &locals->values[slot];
245 if (values->host != values->curr) {
246 wrmsrl(shared_msrs_global.msrs[slot], values->host);
247 values->curr = values->host;
18863bdd
AK		 248 }
249 }
18863bdd
AK		 250}
251
2bf78fa7 252static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 253{
18863bdd 254 u64 value;
013f6a5d
MT		 255 unsigned int cpu = smp_processor_id();
256 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 257
2bf78fa7
SY		 258 /* only read, and nobody should modify it at this time,
259 * so don't need lock */
260 if (slot >= shared_msrs_global.nr) {
261 printk(KERN_ERR "kvm: invalid MSR slot!");
262 return;
263 }
264 rdmsrl_safe(msr, &value);
265 smsr->values[slot].host = value;
266 smsr->values[slot].curr = value;
267}
268
269void kvm_define_shared_msr(unsigned slot, u32 msr)
270{
0123be42 271 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 272 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 273 if (slot >= shared_msrs_global.nr)
274 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 275}
276EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
277
278static void kvm_shared_msr_cpu_online(void)
279{
280 unsigned i;
18863bdd
AK		 281
282 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 283 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 284}
285
8b3c3104 286int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 287{
013f6a5d
MT		 288 unsigned int cpu = smp_processor_id();
289 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 290 int err;
18863bdd 291
2bf78fa7 292 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 293 return 0;
2bf78fa7 294 smsr->values[slot].curr = value;
8b3c3104
AH		 295 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
296 if (err)
297 return 1;
298
18863bdd
AK		 299 if (!smsr->registered) {
300 smsr->urn.on_user_return = kvm_on_user_return;
301 user_return_notifier_register(&smsr->urn);
302 smsr->registered = true;
303 }
8b3c3104 304 return 0;
18863bdd
AK		 305}
306EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
307
13a34e06 308static void drop_user_return_notifiers(void)
3548bab5 309{
013f6a5d
MT		 310 unsigned int cpu = smp_processor_id();
311 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 312
313 if (smsr->registered)
314 kvm_on_user_return(&smsr->urn);
315}
316
6866b83e
CO		 317u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
318{
8a5a87d9 319 return vcpu->arch.apic_base;
6866b83e
CO		 320}
321EXPORT_SYMBOL_GPL(kvm_get_apic_base);
322
58871649
JM		 323enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
324{
325 return kvm_apic_mode(kvm_get_apic_base(vcpu));
326}
327EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
328
58cb628d
JK		 329int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
330{
58871649
JM		 331 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
332 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 333 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
334 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 335
58871649 336 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 337 return 1;
58871649
JM		 338 if (!msr_info->host_initiated) {
339 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
340 return 1;
341 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
342 return 1;
343 }
58cb628d
JK		 344
345 kvm_lapic_set_base(vcpu, msr_info->data);
346 return 0;
6866b83e
CO		 347}
348EXPORT_SYMBOL_GPL(kvm_set_apic_base);
349
2605fc21 350asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 351{
352 /* Fault while not rebooting. We want the trace. */
353 BUG();
354}
355EXPORT_SYMBOL_GPL(kvm_spurious_fault);
356
3fd28fce
ED		 357#define EXCPT_BENIGN 0
358#define EXCPT_CONTRIBUTORY 1
359#define EXCPT_PF 2
360
361static int exception_class(int vector)
362{
363 switch (vector) {
364 case PF_VECTOR:
365 return EXCPT_PF;
366 case DE_VECTOR:
367 case TS_VECTOR:
368 case NP_VECTOR:
369 case SS_VECTOR:
370 case GP_VECTOR:
371 return EXCPT_CONTRIBUTORY;
372 default:
373 break;
374 }
375 return EXCPT_BENIGN;
376}
377
d6e8c854
NA		 378#define EXCPT_FAULT 0
379#define EXCPT_TRAP 1
380#define EXCPT_ABORT 2
381#define EXCPT_INTERRUPT 3
382
383static int exception_type(int vector)
384{
385 unsigned int mask;
386
387 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
388 return EXCPT_INTERRUPT;
389
390 mask = 1 << vector;
391
392 /* #DB is trap, as instruction watchpoints are handled elsewhere */
393 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
394 return EXCPT_TRAP;
395
396 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
397 return EXCPT_ABORT;
398
399 /* Reserved exceptions will result in fault */
400 return EXCPT_FAULT;
401}
402
3fd28fce 403static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 404 unsigned nr, bool has_error, u32 error_code,
405 bool reinject)
3fd28fce
ED		 406{
407 u32 prev_nr;
408 int class1, class2;
409
3842d135
AK		 410 kvm_make_request(KVM_REQ_EVENT, vcpu);
411
664f8e26 412 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 413 queue:
3ffb2468
NA		 414 if (has_error && !is_protmode(vcpu))
415 has_error = false;
664f8e26
WL		 416 if (reinject) {
417 /*
418 * On vmentry, vcpu->arch.exception.pending is only
419 * true if an event injection was blocked by
420 * nested_run_pending. In that case, however,
421 * vcpu_enter_guest requests an immediate exit,
422 * and the guest shouldn't proceed far enough to
423 * need reinjection.
424 */
425 WARN_ON_ONCE(vcpu->arch.exception.pending);
426 vcpu->arch.exception.injected = true;
427 } else {
428 vcpu->arch.exception.pending = true;
429 vcpu->arch.exception.injected = false;
430 }
3fd28fce
ED		 431 vcpu->arch.exception.has_error_code = has_error;
432 vcpu->arch.exception.nr = nr;
433 vcpu->arch.exception.error_code = error_code;
c851436a
JM		 434 vcpu->arch.exception.has_payload = false;
435 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 436 return;
437 }
438
439 /* to check exception */
440 prev_nr = vcpu->arch.exception.nr;
441 if (prev_nr == DF_VECTOR) {
442 /* triple fault -> shutdown */
a8eeb04a 443 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 444 return;
445 }
446 class1 = exception_class(prev_nr);
447 class2 = exception_class(nr);
448 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
449 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 450 /*
451 * Generate double fault per SDM Table 5-5. Set
452 * exception.pending = true so that the double fault
453 * can trigger a nested vmexit.
454 */
3fd28fce 455 vcpu->arch.exception.pending = true;
664f8e26 456 vcpu->arch.exception.injected = false;
3fd28fce
ED		 457 vcpu->arch.exception.has_error_code = true;
458 vcpu->arch.exception.nr = DF_VECTOR;
459 vcpu->arch.exception.error_code = 0;
c851436a
JM		 460 vcpu->arch.exception.has_payload = false;
461 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 462 } else
463 /* replace previous exception with a new one in a hope
464 that instruction re-execution will regenerate lost
465 exception */
466 goto queue;
467}
468
298101da
AK		 469void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
470{
ce7ddec4 471 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 472}
473EXPORT_SYMBOL_GPL(kvm_queue_exception);
474
ce7ddec4
JR		 475void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
476{
477 kvm_multiple_exception(vcpu, nr, false, 0, true);
478}
479EXPORT_SYMBOL_GPL(kvm_requeue_exception);
480
6affcbed 481int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 482{
db8fcefa
AP		 483 if (err)
484 kvm_inject_gp(vcpu, 0);
485 else
6affcbed
KH		 486 return kvm_skip_emulated_instruction(vcpu);
487
488 return 1;
db8fcefa
AP		 489}
490EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 491
6389ee94 492void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 493{
494 ++vcpu->stat.pf_guest;
adfe20fb
WL		 495 vcpu->arch.exception.nested_apf =
496 is_guest_mode(vcpu) && fault->async_page_fault;
497 if (vcpu->arch.exception.nested_apf)
498 vcpu->arch.apf.nested_apf_token = fault->address;
499 else
500 vcpu->arch.cr2 = fault->address;
6389ee94 501 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 502}
27d6c865 503EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 504
ef54bcfe 505static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 506{
6389ee94
AK		 507 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
508 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 509 else
44dd3ffa 510 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 511
512 return fault->nested_page_fault;
d4f8cf66
JR		 513}
514
3419ffc8
SY		 515void kvm_inject_nmi(struct kvm_vcpu *vcpu)
516{
7460fb4a
AK		 517 atomic_inc(&vcpu->arch.nmi_queued);
518 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 519}
520EXPORT_SYMBOL_GPL(kvm_inject_nmi);
521
298101da
AK		 522void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
523{
ce7ddec4 524 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 525}
526EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
527
ce7ddec4
JR		 528void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
529{
530 kvm_multiple_exception(vcpu, nr, true, error_code, true);
531}
532EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
533
0a79b009
AK		 534/*
535 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
536 * a #GP and return false.
537 */
538bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 539{
0a79b009
AK		 540 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
541 return true;
542 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
543 return false;
298101da 544}
0a79b009 545EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 546
16f8a6f9
NA		 547bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
548{
549 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
550 return true;
551
552 kvm_queue_exception(vcpu, UD_VECTOR);
553 return false;
554}
555EXPORT_SYMBOL_GPL(kvm_require_dr);
556
ec92fe44
JR		 557/*
558 * This function will be used to read from the physical memory of the currently
54bf36aa 559 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 560 * can read from guest physical or from the guest's guest physical memory.
561 */
562int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
563 gfn_t ngfn, void *data, int offset, int len,
564 u32 access)
565{
54987b7a 566 struct x86_exception exception;
ec92fe44
JR		 567 gfn_t real_gfn;
568 gpa_t ngpa;
569
570 ngpa = gfn_to_gpa(ngfn);
54987b7a 571 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 572 if (real_gfn == UNMAPPED_GVA)
573 return -EFAULT;
574
575 real_gfn = gpa_to_gfn(real_gfn);
576
54bf36aa 577 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 578}
579EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
580
69b0049a 581static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 582 void *data, int offset, int len, u32 access)
583{
584 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
585 data, offset, len, access);
586}
587
a03490ed
CO		 588/*
589 * Load the pae pdptrs. Return true is they are all valid.
590 */
ff03a073 591int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 592{
593 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
594 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
595 int i;
596 int ret;
ff03a073 597 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 598
ff03a073
JR		 599 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
600 offset * sizeof(u64), sizeof(pdpte),
601 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 602 if (ret < 0) {
603 ret = 0;
604 goto out;
605 }
606 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 607 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 608 (pdpte[i] &
44dd3ffa 609 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 610 ret = 0;
611 goto out;
612 }
613 }
614 ret = 1;
615
ff03a073 616 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 617 __set_bit(VCPU_EXREG_PDPTR,
618 (unsigned long *)&vcpu->arch.regs_avail);
619 __set_bit(VCPU_EXREG_PDPTR,
620 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 621out:
a03490ed
CO		 622
623 return ret;
624}
cc4b6871 625EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 626
9ed38ffa 627bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 628{
ff03a073 629 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 630 bool changed = true;
3d06b8bf
JR		 631 int offset;
632 gfn_t gfn;
d835dfec
AK		 633 int r;
634
d35b34a9 635 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
d835dfec
AK		 636 return false;
637
6de4f3ad
AK		 638 if (!test_bit(VCPU_EXREG_PDPTR,
639 (unsigned long *)&vcpu->arch.regs_avail))
640 return true;
641
a512177e
PB		 642 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
643 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 644 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
645 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 646 if (r < 0)
647 goto out;
ff03a073 648 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 649out:
d835dfec
AK		 650
651 return changed;
652}
9ed38ffa 653EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 654
49a9b07e 655int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 656{
aad82703 657 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 658 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 659
f9a48e6a
AK		 660 cr0 |= X86_CR0_ET;
661
ab344828 662#ifdef CONFIG_X86_64
0f12244f
GN		 663 if (cr0 & 0xffffffff00000000UL)
664 return 1;
ab344828
GN		 665#endif
666
667 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 668
0f12244f
GN		 669 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
670 return 1;
a03490ed 671
0f12244f
GN		 672 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
673 return 1;
a03490ed
CO		 674
675 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
676#ifdef CONFIG_X86_64
f6801dff 677 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 678 int cs_db, cs_l;
679
0f12244f
GN		 680 if (!is_pae(vcpu))
681 return 1;
a03490ed 682 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 683 if (cs_l)
684 return 1;
a03490ed
CO		 685 } else
686#endif
ff03a073 687 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 688 kvm_read_cr3(vcpu)))
0f12244f 689 return 1;
a03490ed
CO		 690 }
691
ad756a16
MJ		 692 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
693 return 1;
694
a03490ed 695 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 696
d170c419 697 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 698 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 699 kvm_async_pf_hash_reset(vcpu);
700 }
e5f3f027 701
aad82703
SY		 702 if ((cr0 ^ old_cr0) & update_bits)
703 kvm_mmu_reset_context(vcpu);
b18d5431 704
879ae188
LE		 705 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
706 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
707 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 708 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
709
0f12244f
GN		 710 return 0;
711}
2d3ad1f4 712EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 713
2d3ad1f4 714void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 715{
49a9b07e 716 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 717}
2d3ad1f4 718EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 719
42bdf991
MT		 720static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
721{
722 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
723 !vcpu->guest_xcr0_loaded) {
724 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 725 if (vcpu->arch.xcr0 != host_xcr0)
726 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 727 vcpu->guest_xcr0_loaded = 1;
728 }
729}
730
731static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
732{
733 if (vcpu->guest_xcr0_loaded) {
734 if (vcpu->arch.xcr0 != host_xcr0)
735 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
736 vcpu->guest_xcr0_loaded = 0;
737 }
738}
739
69b0049a 740static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 741{
56c103ec
LJ		 742 u64 xcr0 = xcr;
743 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 744 u64 valid_bits;
2acf923e
DC		 745
746 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
747 if (index != XCR_XFEATURE_ENABLED_MASK)
748 return 1;
d91cab78 749 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 750 return 1;
d91cab78 751 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 752 return 1;
46c34cb0
PB		 753
754 /*
755 * Do not allow the guest to set bits that we do not support
756 * saving. However, xcr0 bit 0 is always set, even if the
757 * emulated CPU does not support XSAVE (see fx_init).
758 */
d91cab78 759 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 760 if (xcr0 & ~valid_bits)
2acf923e 761 return 1;
46c34cb0 762
d91cab78
DH		 763 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
764 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 765 return 1;
766
d91cab78
DH		 767 if (xcr0 & XFEATURE_MASK_AVX512) {
768 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 769 return 1;
d91cab78 770 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 771 return 1;
772 }
2acf923e 773 vcpu->arch.xcr0 = xcr0;
56c103ec 774
d91cab78 775 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 776 kvm_update_cpuid(vcpu);
2acf923e
DC		 777 return 0;
778}
779
780int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
781{
764bcbc5
Z		 782 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
783 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 784 kvm_inject_gp(vcpu, 0);
785 return 1;
786 }
787 return 0;
788}
789EXPORT_SYMBOL_GPL(kvm_set_xcr);
790
a83b29c6 791int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 792{
fc78f519 793 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 794 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 795 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 796
0f12244f
GN		 797 if (cr4 & CR4_RESERVED_BITS)
798 return 1;
a03490ed 799
d6321d49 800 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 801 return 1;
802
d6321d49 803 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 804 return 1;
805
d6321d49 806 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 807 return 1;
808
d6321d49 809 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 810 return 1;
811
d6321d49 812 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 813 return 1;
814
fd8cb433 815 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 816 return 1;
817
ae3e61e1
PB		 818 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
819 return 1;
820
a03490ed 821 if (is_long_mode(vcpu)) {
0f12244f
GN		 822 if (!(cr4 & X86_CR4_PAE))
823 return 1;
a2edf57f
AK		 824 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
825 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 826 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
827 kvm_read_cr3(vcpu)))
0f12244f
GN		 828 return 1;
829
ad756a16 830 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 831 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 832 return 1;
833
834 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
835 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
836 return 1;
837 }
838
5e1746d6 839 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 840 return 1;
a03490ed 841
ad756a16
MJ		 842 if (((cr4 ^ old_cr4) & pdptr_bits) ||
843 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 844 kvm_mmu_reset_context(vcpu);
0f12244f 845
b9baba86 846 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 847 kvm_update_cpuid(vcpu);
2acf923e 848
0f12244f
GN		 849 return 0;
850}
2d3ad1f4 851EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 852
2390218b 853int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 854{
ade61e28 855 bool skip_tlb_flush = false;
ac146235 856#ifdef CONFIG_X86_64
c19986fe
JS		 857 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
858
ade61e28 859 if (pcid_enabled) {
208320ba
JS		 860 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
861 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 862 }
ac146235 863#endif
9d88fca7 864
9f8fe504 865 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 866 if (!skip_tlb_flush) {
867 kvm_mmu_sync_roots(vcpu);
ade61e28 868 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 869 }
0f12244f 870 return 0;
d835dfec
AK		 871 }
872
d1cd3ce9 873 if (is_long_mode(vcpu) &&
a780a3ea 874 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 875 return 1;
876 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 877 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 878 return 1;
a03490ed 879
ade61e28 880 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 881 vcpu->arch.cr3 = cr3;
aff48baa 882 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 883
0f12244f
GN		 884 return 0;
885}
2d3ad1f4 886EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 887
eea1cff9 888int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 889{
0f12244f
GN		 890 if (cr8 & CR8_RESERVED_BITS)
891 return 1;
35754c98 892 if (lapic_in_kernel(vcpu))
a03490ed
CO		 893 kvm_lapic_set_tpr(vcpu, cr8);
894 else
ad312c7c 895 vcpu->arch.cr8 = cr8;
0f12244f
GN		 896 return 0;
897}
2d3ad1f4 898EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 899
2d3ad1f4 900unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 901{
35754c98 902 if (lapic_in_kernel(vcpu))
a03490ed
CO		 903 return kvm_lapic_get_cr8(vcpu);
904 else
ad312c7c 905 return vcpu->arch.cr8;
a03490ed 906}
2d3ad1f4 907EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 908
ae561ede
NA		 909static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
910{
911 int i;
912
913 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
914 for (i = 0; i < KVM_NR_DB_REGS; i++)
915 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
916 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
917 }
918}
919
73aaf249
JK		 920static void kvm_update_dr6(struct kvm_vcpu *vcpu)
921{
922 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
923 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
924}
925
c8639010
JK		 926static void kvm_update_dr7(struct kvm_vcpu *vcpu)
927{
928 unsigned long dr7;
929
930 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
931 dr7 = vcpu->arch.guest_debug_dr7;
932 else
933 dr7 = vcpu->arch.dr7;
934 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 935 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
936 if (dr7 & DR7_BP_EN_MASK)
937 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 938}
939
6f43ed01
NA		 940static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
941{
942 u64 fixed = DR6_FIXED_1;
943
d6321d49 944 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 945 fixed |= DR6_RTM;
946 return fixed;
947}
948
338dbc97 949static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 950{
951 switch (dr) {
952 case 0 ... 3:
953 vcpu->arch.db[dr] = val;
954 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
955 vcpu->arch.eff_db[dr] = val;
956 break;
957 case 4:
020df079
GN		 958 /* fall through */
959 case 6:
338dbc97
GN		 960 if (val & 0xffffffff00000000ULL)
961 return -1; /* #GP */
6f43ed01 962 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 963 kvm_update_dr6(vcpu);
020df079
GN		 964 break;
965 case 5:
020df079
GN		 966 /* fall through */
967 default: /* 7 */
338dbc97
GN		 968 if (val & 0xffffffff00000000ULL)
969 return -1; /* #GP */
020df079 970 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 971 kvm_update_dr7(vcpu);
020df079
GN		 972 break;
973 }
974
975 return 0;
976}
338dbc97
GN		 977
978int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
979{
16f8a6f9 980 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 981 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 982 return 1;
983 }
984 return 0;
338dbc97 985}
020df079
GN		 986EXPORT_SYMBOL_GPL(kvm_set_dr);
987
16f8a6f9 988int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 989{
990 switch (dr) {
991 case 0 ... 3:
992 *val = vcpu->arch.db[dr];
993 break;
994 case 4:
020df079
GN		 995 /* fall through */
996 case 6:
73aaf249
JK		 997 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
998 *val = vcpu->arch.dr6;
999 else
1000 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1001 break;
1002 case 5:
020df079
GN		 1003 /* fall through */
1004 default: /* 7 */
1005 *val = vcpu->arch.dr7;
1006 break;
1007 }
338dbc97
GN		 1008 return 0;
1009}
020df079
GN		 1010EXPORT_SYMBOL_GPL(kvm_get_dr);
1011
022cd0e8
AK		 1012bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1013{
1014 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1015 u64 data;
1016 int err;
1017
c6702c9d 1018 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1019 if (err)
1020 return err;
1021 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1022 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1023 return err;
1024}
1025EXPORT_SYMBOL_GPL(kvm_rdpmc);
1026
043405e1
CO		 1027/*
1028 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1029 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1030 *
1031 * This list is modified at module load time to reflect the
e3267cbb 1032 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1033 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1034 * may depend on host virtualization features rather than host cpu features.
043405e1 1035 */
e3267cbb 1036
043405e1
CO		 1037static u32 msrs_to_save[] = {
1038 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1039 MSR_STAR,
043405e1
CO		 1040#ifdef CONFIG_X86_64
1041 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1042#endif
b3897a49 1043 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1044 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1045 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1046};
1047
1048static unsigned num_msrs_to_save;
1049
62ef68bb
PB		 1050static u32 emulated_msrs[] = {
1051 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1052 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1053 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1054 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1055 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1056 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1057 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1058 HV_X64_MSR_RESET,
11c4b1ca 1059 HV_X64_MSR_VP_INDEX,
9eec50b8 1060 HV_X64_MSR_VP_RUNTIME,
5c919412 1061 HV_X64_MSR_SCONTROL,
1f4b34f8 1062 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1063 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1064 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1065 HV_X64_MSR_TSC_EMULATION_STATUS,
1066
1067 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1068 MSR_KVM_PV_EOI_EN,
1069
ba904635 1070 MSR_IA32_TSC_ADJUST,
a3e06bbe 1071 MSR_IA32_TSCDEADLINE,
043405e1 1072 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1073 MSR_IA32_MCG_STATUS,
1074 MSR_IA32_MCG_CTL,
c45dcc71 1075 MSR_IA32_MCG_EXT_CTL,
64d60670 1076 MSR_IA32_SMBASE,
52797bf9 1077 MSR_SMI_COUNT,
db2336a8
KH		 1078 MSR_PLATFORM_INFO,
1079 MSR_MISC_FEATURES_ENABLES,
bc226f07 1080 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1081};
1082
62ef68bb
PB		 1083static unsigned num_emulated_msrs;
1084
801e459a
TL		 1085/*
1086 * List of msr numbers which are used to expose MSR-based features that
1087 * can be used by a hypervisor to validate requested CPU features.
1088 */
1089static u32 msr_based_features[] = {
1389309c
PB		 1090 MSR_IA32_VMX_BASIC,
1091 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1092 MSR_IA32_VMX_PINBASED_CTLS,
1093 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1094 MSR_IA32_VMX_PROCBASED_CTLS,
1095 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1096 MSR_IA32_VMX_EXIT_CTLS,
1097 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1098 MSR_IA32_VMX_ENTRY_CTLS,
1099 MSR_IA32_VMX_MISC,
1100 MSR_IA32_VMX_CR0_FIXED0,
1101 MSR_IA32_VMX_CR0_FIXED1,
1102 MSR_IA32_VMX_CR4_FIXED0,
1103 MSR_IA32_VMX_CR4_FIXED1,
1104 MSR_IA32_VMX_VMCS_ENUM,
1105 MSR_IA32_VMX_PROCBASED_CTLS2,
1106 MSR_IA32_VMX_EPT_VPID_CAP,
1107 MSR_IA32_VMX_VMFUNC,
1108
d1d93fa9 1109 MSR_F10H_DECFG,
518e7b94 1110 MSR_IA32_UCODE_REV,
cd283252 1111 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1112};
1113
1114static unsigned int num_msr_based_features;
1115
5b76a3cf
PB		 1116u64 kvm_get_arch_capabilities(void)
1117{
1118 u64 data;
1119
1120 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1121
1122 /*
1123 * If we're doing cache flushes (either "always" or "cond")
1124 * we will do one whenever the guest does a vmlaunch/vmresume.
1125 * If an outer hypervisor is doing the cache flush for us
1126 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1127 * capability to the guest too, and if EPT is disabled we're not
1128 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1129 * require a nested hypervisor to do a flush of its own.
1130 */
1131 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1132 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1133
1134 return data;
1135}
1136EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1137
66421c1e
WL		 1138static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1139{
1140 switch (msr->index) {
cd283252 1141 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1142 msr->data = kvm_get_arch_capabilities();
1143 break;
1144 case MSR_IA32_UCODE_REV:
cd283252 1145 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1146 break;
66421c1e
WL		 1147 default:
1148 if (kvm_x86_ops->get_msr_feature(msr))
1149 return 1;
1150 }
1151 return 0;
1152}
1153
801e459a
TL		 1154static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1155{
1156 struct kvm_msr_entry msr;
66421c1e 1157 int r;
801e459a
TL		 1158
1159 msr.index = index;
66421c1e
WL		 1160 r = kvm_get_msr_feature(&msr);
1161 if (r)
1162 return r;
801e459a
TL		 1163
1164 *data = msr.data;
1165
1166 return 0;
1167}
1168
384bb783 1169bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1170{
b69e8cae 1171 if (efer & efer_reserved_bits)
384bb783 1172 return false;
15c4a640 1173
1b4d56b8 1174 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1175 return false;
1b2fd70c 1176
1b4d56b8 1177 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1178 return false;
d8017474 1179
384bb783
JK		 1180 return true;
1181}
1182EXPORT_SYMBOL_GPL(kvm_valid_efer);
1183
1184static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1185{
1186 u64 old_efer = vcpu->arch.efer;
1187
1188 if (!kvm_valid_efer(vcpu, efer))
1189 return 1;
1190
1191 if (is_paging(vcpu)
1192 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1193 return 1;
1194
15c4a640 1195 efer &= ~EFER_LMA;
f6801dff 1196 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1197
a3d204e2
SY		 1198 kvm_x86_ops->set_efer(vcpu, efer);
1199
aad82703
SY		 1200 /* Update reserved bits */
1201 if ((efer ^ old_efer) & EFER_NX)
1202 kvm_mmu_reset_context(vcpu);
1203
b69e8cae 1204 return 0;
15c4a640
CO		 1205}
1206
f2b4b7dd
JR		 1207void kvm_enable_efer_bits(u64 mask)
1208{
1209 efer_reserved_bits &= ~mask;
1210}
1211EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1212
15c4a640
CO		 1213/*
1214 * Writes msr value into into the appropriate "register".
1215 * Returns 0 on success, non-0 otherwise.
1216 * Assumes vcpu_load() was already called.
1217 */
8fe8ab46 1218int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1219{
854e8bb1
NA		 1220 switch (msr->index) {
1221 case MSR_FS_BASE:
1222 case MSR_GS_BASE:
1223 case MSR_KERNEL_GS_BASE:
1224 case MSR_CSTAR:
1225 case MSR_LSTAR:
fd8cb433 1226 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1227 return 1;
1228 break;
1229 case MSR_IA32_SYSENTER_EIP:
1230 case MSR_IA32_SYSENTER_ESP:
1231 /*
1232 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1233 * non-canonical address is written on Intel but not on
1234 * AMD (which ignores the top 32-bits, because it does
1235 * not implement 64-bit SYSENTER).
1236 *
1237 * 64-bit code should hence be able to write a non-canonical
1238 * value on AMD. Making the address canonical ensures that
1239 * vmentry does not fail on Intel after writing a non-canonical
1240 * value, and that something deterministic happens if the guest
1241 * invokes 64-bit SYSENTER.
1242 */
fd8cb433 1243 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1244 }
8fe8ab46 1245 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1246}
854e8bb1 1247EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1248
313a3dc7
CO		 1249/*
1250 * Adapt set_msr() to msr_io()'s calling convention
1251 */
609e36d3
PB		 1252static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1253{
1254 struct msr_data msr;
1255 int r;
1256
1257 msr.index = index;
1258 msr.host_initiated = true;
1259 r = kvm_get_msr(vcpu, &msr);
1260 if (r)
1261 return r;
1262
1263 *data = msr.data;
1264 return 0;
1265}
1266
313a3dc7
CO		 1267static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1268{
8fe8ab46
WA		 1269 struct msr_data msr;
1270
1271 msr.data = *data;
1272 msr.index = index;
1273 msr.host_initiated = true;
1274 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1275}
1276
16e8d74d
MT		 1277#ifdef CONFIG_X86_64
1278struct pvclock_gtod_data {
1279 seqcount_t seq;
1280
1281 struct { /* extract of a clocksource struct */
1282 int vclock_mode;
a5a1d1c2
TG		 1283 u64 cycle_last;
1284 u64 mask;
16e8d74d
MT		 1285 u32 mult;
1286 u32 shift;
1287 } clock;
1288
cbcf2dd3
TG		 1289 u64 boot_ns;
1290 u64 nsec_base;
55dd00a7 1291 u64 wall_time_sec;
16e8d74d
MT		 1292};
1293
1294static struct pvclock_gtod_data pvclock_gtod_data;
1295
1296static void update_pvclock_gtod(struct timekeeper *tk)
1297{
1298 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1299 u64 boot_ns;
1300
876e7881 1301 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1302
1303 write_seqcount_begin(&vdata->seq);
1304
1305 /* copy pvclock gtod data */
876e7881
PZ		 1306 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1307 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1308 vdata->clock.mask = tk->tkr_mono.mask;
1309 vdata->clock.mult = tk->tkr_mono.mult;
1310 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1311
cbcf2dd3 1312 vdata->boot_ns = boot_ns;
876e7881 1313 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1314
55dd00a7
MT		 1315 vdata->wall_time_sec = tk->xtime_sec;
1316
16e8d74d
MT		 1317 write_seqcount_end(&vdata->seq);
1318}
1319#endif
1320
bab5bb39
NK		 1321void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1322{
1323 /*
1324 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1325 * vcpu_enter_guest. This function is only called from
1326 * the physical CPU that is running vcpu.
1327 */
1328 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1329}
16e8d74d 1330
18068523
GOC		 1331static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1332{
9ed3c444
AK		 1333 int version;
1334 int r;
50d0a0f9 1335 struct pvclock_wall_clock wc;
87aeb54f 1336 struct timespec64 boot;
18068523
GOC		 1337
1338 if (!wall_clock)
1339 return;
1340
9ed3c444
AK		 1341 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1342 if (r)
1343 return;
1344
1345 if (version & 1)
1346 ++version; /* first time write, random junk */
1347
1348 ++version;
18068523 1349
1dab1345
NK		 1350 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1351 return;
18068523 1352
50d0a0f9
GH		 1353 /*
1354 * The guest calculates current wall clock time by adding
34c238a1 1355 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1356 * wall clock specified here. guest system time equals host
1357 * system time for us, thus we must fill in host boot time here.
1358 */
87aeb54f 1359 getboottime64(&boot);
50d0a0f9 1360
4b648665 1361 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1362 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1363 boot = timespec64_sub(boot, ts);
4b648665 1364 }
87aeb54f 1365 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1366 wc.nsec = boot.tv_nsec;
1367 wc.version = version;
18068523
GOC		 1368
1369 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1370
1371 version++;
1372 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1373}
1374
50d0a0f9
GH		 1375static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1376{
b51012de
PB		 1377 do_shl32_div32(dividend, divisor);
1378 return dividend;
50d0a0f9
GH		 1379}
1380
3ae13faa 1381static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1382 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1383{
5f4e3f88 1384 uint64_t scaled64;
50d0a0f9
GH		 1385 int32_t shift = 0;
1386 uint64_t tps64;
1387 uint32_t tps32;
1388
3ae13faa
PB		 1389 tps64 = base_hz;
1390 scaled64 = scaled_hz;
50933623 1391 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1392 tps64 >>= 1;
1393 shift--;
1394 }
1395
1396 tps32 = (uint32_t)tps64;
50933623
JK		 1397 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1398 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1399 scaled64 >>= 1;
1400 else
1401 tps32 <<= 1;
50d0a0f9
GH		 1402 shift++;
1403 }
1404
5f4e3f88
ZA		 1405 *pshift = shift;
1406 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1407
3ae13faa
PB		 1408 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1409 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1410}
1411
d828199e 1412#ifdef CONFIG_X86_64
16e8d74d 1413static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1414#endif
16e8d74d 1415
c8076604 1416static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1417static unsigned long max_tsc_khz;
c8076604 1418
cc578287 1419static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1420{
cc578287
ZA		 1421 u64 v = (u64)khz * (1000000 + ppm);
1422 do_div(v, 1000000);
1423 return v;
1e993611
JR		 1424}
1425
381d585c
HZ		 1426static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1427{
1428 u64 ratio;
1429
1430 /* Guest TSC same frequency as host TSC? */
1431 if (!scale) {
1432 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1433 return 0;
1434 }
1435
1436 /* TSC scaling supported? */
1437 if (!kvm_has_tsc_control) {
1438 if (user_tsc_khz > tsc_khz) {
1439 vcpu->arch.tsc_catchup = 1;
1440 vcpu->arch.tsc_always_catchup = 1;
1441 return 0;
1442 } else {
1443 WARN(1, "user requested TSC rate below hardware speed\n");
1444 return -1;
1445 }
1446 }
1447
1448 /* TSC scaling required - calculate ratio */
1449 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1450 user_tsc_khz, tsc_khz);
1451
1452 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1453 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1454 user_tsc_khz);
1455 return -1;
1456 }
1457
1458 vcpu->arch.tsc_scaling_ratio = ratio;
1459 return 0;
1460}
1461
4941b8cb 1462static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1463{
cc578287
ZA		 1464 u32 thresh_lo, thresh_hi;
1465 int use_scaling = 0;
217fc9cf 1466
03ba32ca 1467 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1468 if (user_tsc_khz == 0) {
ad721883
HZ		 1469 /* set tsc_scaling_ratio to a safe value */
1470 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1471 return -1;
ad721883 1472 }
03ba32ca 1473
c285545f 1474 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1475 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1476 &vcpu->arch.virtual_tsc_shift,
1477 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1478 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1479
1480 /*
1481 * Compute the variation in TSC rate which is acceptable
1482 * within the range of tolerance and decide if the
1483 * rate being applied is within that bounds of the hardware
1484 * rate. If so, no scaling or compensation need be done.
1485 */
1486 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1487 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1488 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1489 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1490 use_scaling = 1;
1491 }
4941b8cb 1492 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1493}
1494
1495static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1496{
e26101b1 1497 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1498 vcpu->arch.virtual_tsc_mult,
1499 vcpu->arch.virtual_tsc_shift);
e26101b1 1500 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1501 return tsc;
1502}
1503
b0c39dc6
VK		 1504static inline int gtod_is_based_on_tsc(int mode)
1505{
1506 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1507}
1508
69b0049a 1509static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1510{
1511#ifdef CONFIG_X86_64
1512 bool vcpus_matched;
b48aa97e
MT		 1513 struct kvm_arch *ka = &vcpu->kvm->arch;
1514 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1515
1516 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1517 atomic_read(&vcpu->kvm->online_vcpus));
1518
7f187922
MT		 1519 /*
1520 * Once the masterclock is enabled, always perform request in
1521 * order to update it.
1522 *
1523 * In order to enable masterclock, the host clocksource must be TSC
1524 * and the vcpus need to have matched TSCs. When that happens,
1525 * perform request to enable masterclock.
1526 */
1527 if (ka->use_master_clock ||
b0c39dc6 1528 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1529 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1530
1531 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1532 atomic_read(&vcpu->kvm->online_vcpus),
1533 ka->use_master_clock, gtod->clock.vclock_mode);
1534#endif
1535}
1536
ba904635
WA		 1537static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1538{
e79f245d 1539 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1540 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1541}
1542
35181e86
HZ		 1543/*
1544 * Multiply tsc by a fixed point number represented by ratio.
1545 *
1546 * The most significant 64-N bits (mult) of ratio represent the
1547 * integral part of the fixed point number; the remaining N bits
1548 * (frac) represent the fractional part, ie. ratio represents a fixed
1549 * point number (mult + frac * 2^(-N)).
1550 *
1551 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1552 */
1553static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1554{
1555 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1556}
1557
1558u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1559{
1560 u64 _tsc = tsc;
1561 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1562
1563 if (ratio != kvm_default_tsc_scaling_ratio)
1564 _tsc = __scale_tsc(ratio, tsc);
1565
1566 return _tsc;
1567}
1568EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1569
07c1419a
HZ		 1570static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1571{
1572 u64 tsc;
1573
1574 tsc = kvm_scale_tsc(vcpu, rdtsc());
1575
1576 return target_tsc - tsc;
1577}
1578
4ba76538
HZ		 1579u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1580{
e79f245d
KA		 1581 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1582
1583 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1584}
1585EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1586
a545ab6a
LC		 1587static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1588{
1589 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1590 vcpu->arch.tsc_offset = offset;
1591}
1592
b0c39dc6
VK		 1593static inline bool kvm_check_tsc_unstable(void)
1594{
1595#ifdef CONFIG_X86_64
1596 /*
1597 * TSC is marked unstable when we're running on Hyper-V,
1598 * 'TSC page' clocksource is good.
1599 */
1600 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1601 return false;
1602#endif
1603 return check_tsc_unstable();
1604}
1605
8fe8ab46 1606void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1607{
1608 struct kvm *kvm = vcpu->kvm;
f38e098f 1609 u64 offset, ns, elapsed;
99e3e30a 1610 unsigned long flags;
b48aa97e 1611 bool matched;
0d3da0d2 1612 bool already_matched;
8fe8ab46 1613 u64 data = msr->data;
c5e8ec8e 1614 bool synchronizing = false;
99e3e30a 1615
038f8c11 1616 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1617 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1618 ns = ktime_get_boot_ns();
f38e098f 1619 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1620
03ba32ca 1621 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1622 if (data == 0 && msr->host_initiated) {
1623 /*
1624 * detection of vcpu initialization -- need to sync
1625 * with other vCPUs. This particularly helps to keep
1626 * kvm_clock stable after CPU hotplug
1627 */
1628 synchronizing = true;
1629 } else {
1630 u64 tsc_exp = kvm->arch.last_tsc_write +
1631 nsec_to_cycles(vcpu, elapsed);
1632 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1633 /*
1634 * Special case: TSC write with a small delta (1 second)
1635 * of virtual cycle time against real time is
1636 * interpreted as an attempt to synchronize the CPU.
1637 */
1638 synchronizing = data < tsc_exp + tsc_hz &&
1639 data + tsc_hz > tsc_exp;
1640 }
c5e8ec8e 1641 }
f38e098f
ZA		 1642
1643 /*
5d3cb0f6
ZA		 1644 * For a reliable TSC, we can match TSC offsets, and for an unstable
1645 * TSC, we add elapsed time in this computation. We could let the
1646 * compensation code attempt to catch up if we fall behind, but
1647 * it's better to try to match offsets from the beginning.
1648 */
c5e8ec8e 1649 if (synchronizing &&
5d3cb0f6 1650 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1651 if (!kvm_check_tsc_unstable()) {
e26101b1 1652 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1653 pr_debug("kvm: matched tsc offset for %llu\n", data);
1654 } else {
857e4099 1655 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1656 data += delta;
07c1419a 1657 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1658 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1659 }
b48aa97e 1660 matched = true;
0d3da0d2 1661 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1662 } else {
1663 /*
1664 * We split periods of matched TSC writes into generations.
1665 * For each generation, we track the original measured
1666 * nanosecond time, offset, and write, so if TSCs are in
1667 * sync, we can match exact offset, and if not, we can match
4a969980 1668 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1669 *
1670 * These values are tracked in kvm->arch.cur_xxx variables.
1671 */
1672 kvm->arch.cur_tsc_generation++;
1673 kvm->arch.cur_tsc_nsec = ns;
1674 kvm->arch.cur_tsc_write = data;
1675 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1676 matched = false;
0d3da0d2 1677 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1678 kvm->arch.cur_tsc_generation, data);
f38e098f 1679 }
e26101b1
ZA		 1680
1681 /*
1682 * We also track th most recent recorded KHZ, write and time to
1683 * allow the matching interval to be extended at each write.
1684 */
f38e098f
ZA		 1685 kvm->arch.last_tsc_nsec = ns;
1686 kvm->arch.last_tsc_write = data;
5d3cb0f6 1687 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1688
b183aa58 1689 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1690
1691 /* Keep track of which generation this VCPU has synchronized to */
1692 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1693 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1694 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1695
d6321d49 1696 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1697 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1698
a545ab6a 1699 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1700 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1701
1702 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1703 if (!matched) {
b48aa97e 1704 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1705 } else if (!already_matched) {
1706 kvm->arch.nr_vcpus_matched_tsc++;
1707 }
b48aa97e
MT		 1708
1709 kvm_track_tsc_matching(vcpu);
1710 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1711}
e26101b1 1712
99e3e30a
ZA		 1713EXPORT_SYMBOL_GPL(kvm_write_tsc);
1714
58ea6767
HZ		 1715static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1716 s64 adjustment)
1717{
ea26e4ec 1718 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1719}
1720
1721static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1722{
1723 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1724 WARN_ON(adjustment < 0);
1725 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1726 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1727}
1728
d828199e
MT		 1729#ifdef CONFIG_X86_64
1730
a5a1d1c2 1731static u64 read_tsc(void)
d828199e 1732{
a5a1d1c2 1733 u64 ret = (u64)rdtsc_ordered();
03b9730b 1734 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1735
1736 if (likely(ret >= last))
1737 return ret;
1738
1739 /*
1740 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1741 * predictable (it's just a function of time and the likely is
d828199e
MT		 1742 * very likely) and there's a data dependence, so force GCC
1743 * to generate a branch instead. I don't barrier() because
1744 * we don't actually need a barrier, and if this function
1745 * ever gets inlined it will generate worse code.
1746 */
1747 asm volatile ("");
1748 return last;
1749}
1750
b0c39dc6 1751static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1752{
1753 long v;
1754 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1755 u64 tsc_pg_val;
1756
1757 switch (gtod->clock.vclock_mode) {
1758 case VCLOCK_HVCLOCK:
1759 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1760 tsc_timestamp);
1761 if (tsc_pg_val != U64_MAX) {
1762 /* TSC page valid */
1763 *mode = VCLOCK_HVCLOCK;
1764 v = (tsc_pg_val - gtod->clock.cycle_last) &
1765 gtod->clock.mask;
1766 } else {
1767 /* TSC page invalid */
1768 *mode = VCLOCK_NONE;
1769 }
1770 break;
1771 case VCLOCK_TSC:
1772 *mode = VCLOCK_TSC;
1773 *tsc_timestamp = read_tsc();
1774 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1775 gtod->clock.mask;
1776 break;
1777 default:
1778 *mode = VCLOCK_NONE;
1779 }
d828199e 1780
b0c39dc6
VK		 1781 if (*mode == VCLOCK_NONE)
1782 *tsc_timestamp = v = 0;
d828199e 1783
d828199e
MT		 1784 return v * gtod->clock.mult;
1785}
1786
b0c39dc6 1787static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1788{
cbcf2dd3 1789 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1790 unsigned long seq;
d828199e 1791 int mode;
cbcf2dd3 1792 u64 ns;
d828199e 1793
d828199e
MT		 1794 do {
1795 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1796 ns = gtod->nsec_base;
b0c39dc6 1797 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1798 ns >>= gtod->clock.shift;
cbcf2dd3 1799 ns += gtod->boot_ns;
d828199e 1800 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1801 *t = ns;
d828199e
MT		 1802
1803 return mode;
1804}
1805
899a31f5 1806static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1807{
1808 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1809 unsigned long seq;
1810 int mode;
1811 u64 ns;
1812
1813 do {
1814 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1815 ts->tv_sec = gtod->wall_time_sec;
1816 ns = gtod->nsec_base;
b0c39dc6 1817 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1818 ns >>= gtod->clock.shift;
1819 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1820
1821 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1822 ts->tv_nsec = ns;
1823
1824 return mode;
1825}
1826
b0c39dc6
VK		 1827/* returns true if host is using TSC based clocksource */
1828static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1829{
d828199e 1830 /* checked again under seqlock below */
b0c39dc6 1831 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1832 return false;
1833
b0c39dc6
VK		 1834 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1835 tsc_timestamp));
d828199e 1836}
55dd00a7 1837
b0c39dc6 1838/* returns true if host is using TSC based clocksource */
899a31f5 1839static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1840 u64 *tsc_timestamp)
55dd00a7
MT		 1841{
1842 /* checked again under seqlock below */
b0c39dc6 1843 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1844 return false;
1845
b0c39dc6 1846 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1847}
d828199e
MT		 1848#endif
1849
1850/*
1851 *
b48aa97e
MT		 1852 * Assuming a stable TSC across physical CPUS, and a stable TSC
1853 * across virtual CPUs, the following condition is possible.
1854 * Each numbered line represents an event visible to both
d828199e
MT		 1855 * CPUs at the next numbered event.
1856 *
1857 * "timespecX" represents host monotonic time. "tscX" represents
1858 * RDTSC value.
1859 *
1860 * VCPU0 on CPU0 | VCPU1 on CPU1
1861 *
1862 * 1. read timespec0,tsc0
1863 * 2. | timespec1 = timespec0 + N
1864 * | tsc1 = tsc0 + M
1865 * 3. transition to guest | transition to guest
1866 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1867 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1868 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1869 *
1870 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1871 *
1872 * - ret0 < ret1
1873 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1874 * ...
1875 * - 0 < N - M => M < N
1876 *
1877 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1878 * always the case (the difference between two distinct xtime instances
1879 * might be smaller then the difference between corresponding TSC reads,
1880 * when updating guest vcpus pvclock areas).
1881 *
1882 * To avoid that problem, do not allow visibility of distinct
1883 * system_timestamp/tsc_timestamp values simultaneously: use a master
1884 * copy of host monotonic time values. Update that master copy
1885 * in lockstep.
1886 *
b48aa97e 1887 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1888 *
1889 */
1890
1891static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1892{
1893#ifdef CONFIG_X86_64
1894 struct kvm_arch *ka = &kvm->arch;
1895 int vclock_mode;
b48aa97e
MT		 1896 bool host_tsc_clocksource, vcpus_matched;
1897
1898 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1899 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1900
1901 /*
1902 * If the host uses TSC clock, then passthrough TSC as stable
1903 * to the guest.
1904 */
b48aa97e 1905 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1906 &ka->master_kernel_ns,
1907 &ka->master_cycle_now);
1908
16a96021 1909 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1910 && !ka->backwards_tsc_observed
54750f2c 1911 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1912
d828199e
MT		 1913 if (ka->use_master_clock)
1914 atomic_set(&kvm_guest_has_master_clock, 1);
1915
1916 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1917 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1918 vcpus_matched);
d828199e
MT		 1919#endif
1920}
1921
2860c4b1
PB		 1922void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1923{
1924 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1925}
1926
2e762ff7
MT		 1927static void kvm_gen_update_masterclock(struct kvm *kvm)
1928{
1929#ifdef CONFIG_X86_64
1930 int i;
1931 struct kvm_vcpu *vcpu;
1932 struct kvm_arch *ka = &kvm->arch;
1933
1934 spin_lock(&ka->pvclock_gtod_sync_lock);
1935 kvm_make_mclock_inprogress_request(kvm);
1936 /* no guest entries from this point */
1937 pvclock_update_vm_gtod_copy(kvm);
1938
1939 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1940 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1941
1942 /* guest entries allowed */
1943 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1944 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1945
1946 spin_unlock(&ka->pvclock_gtod_sync_lock);
1947#endif
1948}
1949
e891a32e 1950u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1951{
108b249c 1952 struct kvm_arch *ka = &kvm->arch;
8b953440 1953 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1954 u64 ret;
108b249c 1955
8b953440
PB		 1956 spin_lock(&ka->pvclock_gtod_sync_lock);
1957 if (!ka->use_master_clock) {
1958 spin_unlock(&ka->pvclock_gtod_sync_lock);
1959 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1960 }
1961
8b953440
PB		 1962 hv_clock.tsc_timestamp = ka->master_cycle_now;
1963 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1964 spin_unlock(&ka->pvclock_gtod_sync_lock);
1965
e2c2206a
WL		 1966 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1967 get_cpu();
1968
e70b57a6
WL		 1969 if (__this_cpu_read(cpu_tsc_khz)) {
1970 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1971 &hv_clock.tsc_shift,
1972 &hv_clock.tsc_to_system_mul);
1973 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1974 } else
1975 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1976
1977 put_cpu();
1978
1979 return ret;
108b249c
PB		 1980}
1981
0d6dd2ff
PB		 1982static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1983{
1984 struct kvm_vcpu_arch *vcpu = &v->arch;
1985 struct pvclock_vcpu_time_info guest_hv_clock;
1986
4e335d9e 1987 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1988 &guest_hv_clock, sizeof(guest_hv_clock))))
1989 return;
1990
1991 /* This VCPU is paused, but it's legal for a guest to read another
1992 * VCPU's kvmclock, so we really have to follow the specification where
1993 * it says that version is odd if data is being modified, and even after
1994 * it is consistent.
1995 *
1996 * Version field updates must be kept separate. This is because
1997 * kvm_write_guest_cached might use a "rep movs" instruction, and
1998 * writes within a string instruction are weakly ordered. So there
1999 * are three writes overall.
2000 *
2001 * As a small optimization, only write the version field in the first
2002 * and third write. The vcpu->pv_time cache is still valid, because the
2003 * version field is the first in the struct.
2004 */
2005 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2006
51c4b8bb
LA		 2007 if (guest_hv_clock.version & 1)
2008 ++guest_hv_clock.version; /* first time write, random junk */
2009
0d6dd2ff 2010 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2011 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2012 &vcpu->hv_clock,
2013 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2014
2015 smp_wmb();
2016
2017 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2018 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2019
2020 if (vcpu->pvclock_set_guest_stopped_request) {
2021 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2022 vcpu->pvclock_set_guest_stopped_request = false;
2023 }
2024
2025 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2026
4e335d9e
PB		 2027 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2028 &vcpu->hv_clock,
2029 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2030
2031 smp_wmb();
2032
2033 vcpu->hv_clock.version++;
4e335d9e
PB		 2034 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2035 &vcpu->hv_clock,
2036 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2037}
2038
34c238a1 2039static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2040{
78db6a50 2041 unsigned long flags, tgt_tsc_khz;
18068523 2042 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2043 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2044 s64 kernel_ns;
d828199e 2045 u64 tsc_timestamp, host_tsc;
51d59c6b 2046 u8 pvclock_flags;
d828199e
MT		 2047 bool use_master_clock;
2048
2049 kernel_ns = 0;
2050 host_tsc = 0;
18068523 2051
d828199e
MT		 2052 /*
2053 * If the host uses TSC clock, then passthrough TSC as stable
2054 * to the guest.
2055 */
2056 spin_lock(&ka->pvclock_gtod_sync_lock);
2057 use_master_clock = ka->use_master_clock;
2058 if (use_master_clock) {
2059 host_tsc = ka->master_cycle_now;
2060 kernel_ns = ka->master_kernel_ns;
2061 }
2062 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2063
2064 /* Keep irq disabled to prevent changes to the clock */
2065 local_irq_save(flags);
78db6a50
PB		 2066 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2067 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2068 local_irq_restore(flags);
2069 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2070 return 1;
2071 }
d828199e 2072 if (!use_master_clock) {
4ea1636b 2073 host_tsc = rdtsc();
108b249c 2074 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2075 }
2076
4ba76538 2077 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2078
c285545f
ZA		 2079 /*
2080 * We may have to catch up the TSC to match elapsed wall clock
2081 * time for two reasons, even if kvmclock is used.
2082 * 1) CPU could have been running below the maximum TSC rate
2083 * 2) Broken TSC compensation resets the base at each VCPU
2084 * entry to avoid unknown leaps of TSC even when running
2085 * again on the same CPU. This may cause apparent elapsed
2086 * time to disappear, and the guest to stand still or run
2087 * very slowly.
2088 */
2089 if (vcpu->tsc_catchup) {
2090 u64 tsc = compute_guest_tsc(v, kernel_ns);
2091 if (tsc > tsc_timestamp) {
f1e2b260 2092 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2093 tsc_timestamp = tsc;
2094 }
50d0a0f9
GH		 2095 }
2096
18068523
GOC		 2097 local_irq_restore(flags);
2098
0d6dd2ff 2099 /* With all the info we got, fill in the values */
18068523 2100
78db6a50
PB		 2101 if (kvm_has_tsc_control)
2102 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2103
2104 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2105 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2106 &vcpu->hv_clock.tsc_shift,
2107 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2108 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2109 }
2110
1d5f066e 2111 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2112 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2113 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2114
d828199e 2115 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2116 pvclock_flags = 0;
d828199e
MT		 2117 if (use_master_clock)
2118 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2119
78c0337a
MT		 2120 vcpu->hv_clock.flags = pvclock_flags;
2121
095cf55d
PB		 2122 if (vcpu->pv_time_enabled)
2123 kvm_setup_pvclock_page(v);
2124 if (v == kvm_get_vcpu(v->kvm, 0))
2125 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2126 return 0;
c8076604
GH		 2127}
2128
0061d53d
MT		 2129/*
2130 * kvmclock updates which are isolated to a given vcpu, such as
2131 * vcpu->cpu migration, should not allow system_timestamp from
2132 * the rest of the vcpus to remain static. Otherwise ntp frequency
2133 * correction applies to one vcpu's system_timestamp but not
2134 * the others.
2135 *
2136 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2137 * We need to rate-limit these requests though, as they can
2138 * considerably slow guests that have a large number of vcpus.
2139 * The time for a remote vcpu to update its kvmclock is bound
2140 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2141 */
2142
7e44e449
AJ		 2143#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2144
2145static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2146{
2147 int i;
7e44e449
AJ		 2148 struct delayed_work *dwork = to_delayed_work(work);
2149 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2150 kvmclock_update_work);
2151 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2152 struct kvm_vcpu *vcpu;
2153
2154 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2155 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2156 kvm_vcpu_kick(vcpu);
2157 }
2158}
2159
7e44e449
AJ		 2160static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2161{
2162 struct kvm *kvm = v->kvm;
2163
105b21bb 2164 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2165 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2166 KVMCLOCK_UPDATE_DELAY);
2167}
2168
332967a3
AJ		 2169#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2170
2171static void kvmclock_sync_fn(struct work_struct *work)
2172{
2173 struct delayed_work *dwork = to_delayed_work(work);
2174 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2175 kvmclock_sync_work);
2176 struct kvm *kvm = container_of(ka, struct kvm, arch);
2177
630994b3
MT		 2178 if (!kvmclock_periodic_sync)
2179 return;
2180
332967a3
AJ		 2181 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2182 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2183 KVMCLOCK_SYNC_PERIOD);
2184}
2185
9ffd986c 2186static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2187{
890ca9ae
HY		 2188 u64 mcg_cap = vcpu->arch.mcg_cap;
2189 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2190 u32 msr = msr_info->index;
2191 u64 data = msr_info->data;
890ca9ae 2192
15c4a640 2193 switch (msr) {
15c4a640 2194 case MSR_IA32_MCG_STATUS:
890ca9ae 2195 vcpu->arch.mcg_status = data;
15c4a640 2196 break;
c7ac679c 2197 case MSR_IA32_MCG_CTL:
44883f01
PB		 2198 if (!(mcg_cap & MCG_CTL_P) &&
2199 (data || !msr_info->host_initiated))
890ca9ae
HY		 2200 return 1;
2201 if (data != 0 && data != ~(u64)0)
44883f01 2202 return 1;
890ca9ae
HY		 2203 vcpu->arch.mcg_ctl = data;
2204 break;
2205 default:
2206 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2207 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2208 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2209 /* only 0 or all 1s can be written to IA32_MCi_CTL
2210 * some Linux kernels though clear bit 10 in bank 4 to
2211 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2212 * this to avoid an uncatched #GP in the guest
2213 */
890ca9ae 2214 if ((offset & 0x3) == 0 &&
114be429 2215 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2216 return -1;
9ffd986c
WL		 2217 if (!msr_info->host_initiated &&
2218 (offset & 0x3) == 1 && data != 0)
2219 return -1;
890ca9ae
HY		 2220 vcpu->arch.mce_banks[offset] = data;
2221 break;
2222 }
2223 return 1;
2224 }
2225 return 0;
2226}
2227
ffde22ac
ES		 2228static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2229{
2230 struct kvm *kvm = vcpu->kvm;
2231 int lm = is_long_mode(vcpu);
2232 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2233 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2234 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2235 : kvm->arch.xen_hvm_config.blob_size_32;
2236 u32 page_num = data & ~PAGE_MASK;
2237 u64 page_addr = data & PAGE_MASK;
2238 u8 *page;
2239 int r;
2240
2241 r = -E2BIG;
2242 if (page_num >= blob_size)
2243 goto out;
2244 r = -ENOMEM;
ff5c2c03
SL		 2245 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2246 if (IS_ERR(page)) {
2247 r = PTR_ERR(page);
ffde22ac 2248 goto out;
ff5c2c03 2249 }
54bf36aa 2250 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2251 goto out_free;
2252 r = 0;
2253out_free:
2254 kfree(page);
2255out:
2256 return r;
2257}
2258
344d9588
GN		 2259static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2260{
2261 gpa_t gpa = data & ~0x3f;
2262
52a5c155
WL		 2263 /* Bits 3:5 are reserved, Should be zero */
2264 if (data & 0x38)
344d9588
GN		 2265 return 1;
2266
2267 vcpu->arch.apf.msr_val = data;
2268
2269 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2270 kvm_clear_async_pf_completion_queue(vcpu);
2271 kvm_async_pf_hash_reset(vcpu);
2272 return 0;
2273 }
2274
4e335d9e 2275 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2276 sizeof(u32)))
344d9588
GN		 2277 return 1;
2278
6adba527 2279 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2280 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2281 kvm_async_pf_wakeup_all(vcpu);
2282 return 0;
2283}
2284
12f9a48f
GC		 2285static void kvmclock_reset(struct kvm_vcpu *vcpu)
2286{
0b79459b 2287 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2288}
2289
f38a7b75
WL		 2290static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2291{
2292 ++vcpu->stat.tlb_flush;
2293 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2294}
2295
c9aaa895
GC		 2296static void record_steal_time(struct kvm_vcpu *vcpu)
2297{
2298 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2299 return;
2300
4e335d9e 2301 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2302 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2303 return;
2304
f38a7b75
WL		 2305 /*
2306 * Doing a TLB flush here, on the guest's behalf, can avoid
2307 * expensive IPIs.
2308 */
2309 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2310 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2311
35f3fae1
WL		 2312 if (vcpu->arch.st.steal.version & 1)
2313 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2314
2315 vcpu->arch.st.steal.version += 1;
2316
4e335d9e 2317 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2318 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2319
2320 smp_wmb();
2321
c54cdf14
LC		 2322 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2323 vcpu->arch.st.last_steal;
2324 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2325
4e335d9e 2326 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2327 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2328
2329 smp_wmb();
2330
2331 vcpu->arch.st.steal.version += 1;
c9aaa895 2332
4e335d9e 2333 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2334 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2335}
2336
8fe8ab46 2337int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2338{
5753785f 2339 bool pr = false;
8fe8ab46
WA		 2340 u32 msr = msr_info->index;
2341 u64 data = msr_info->data;
5753785f 2342
15c4a640 2343 switch (msr) {
2e32b719 2344 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2345 case MSR_IA32_UCODE_WRITE:
2346 case MSR_VM_HSAVE_PA:
2347 case MSR_AMD64_PATCH_LOADER:
2348 case MSR_AMD64_BU_CFG2:
405a353a 2349 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2350 break;
2351
518e7b94
WL		 2352 case MSR_IA32_UCODE_REV:
2353 if (msr_info->host_initiated)
2354 vcpu->arch.microcode_version = data;
2355 break;
15c4a640 2356 case MSR_EFER:
b69e8cae 2357 return set_efer(vcpu, data);
8f1589d9
AP		 2358 case MSR_K7_HWCR:
2359 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2360 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2361 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2362 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2363 if (data != 0) {
a737f256
CD		 2364 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2365 data);
8f1589d9
AP		 2366 return 1;
2367 }
15c4a640 2368 break;
f7c6d140
AP		 2369 case MSR_FAM10H_MMIO_CONF_BASE:
2370 if (data != 0) {
a737f256
CD		 2371 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2372 "0x%llx\n", data);
f7c6d140
AP		 2373 return 1;
2374 }
15c4a640 2375 break;
b5e2fec0
AG		 2376 case MSR_IA32_DEBUGCTLMSR:
2377 if (!data) {
2378 /* We support the non-activated case already */
2379 break;
2380 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2381 /* Values other than LBR and BTF are vendor-specific,
2382 thus reserved and should throw a #GP */
2383 return 1;
2384 }
a737f256
CD		 2385 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2386 __func__, data);
b5e2fec0 2387 break;
9ba075a6 2388 case 0x200 ... 0x2ff:
ff53604b 2389 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2390 case MSR_IA32_APICBASE:
58cb628d 2391 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2392 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2393 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2394 case MSR_IA32_TSCDEADLINE:
2395 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2396 break;
ba904635 2397 case MSR_IA32_TSC_ADJUST:
d6321d49 2398 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2399 if (!msr_info->host_initiated) {
d913b904 2400 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2401 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2402 }
2403 vcpu->arch.ia32_tsc_adjust_msr = data;
2404 }
2405 break;
15c4a640 2406 case MSR_IA32_MISC_ENABLE:
ad312c7c 2407 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2408 break;
64d60670
PB		 2409 case MSR_IA32_SMBASE:
2410 if (!msr_info->host_initiated)
2411 return 1;
2412 vcpu->arch.smbase = data;
2413 break;
dd259935
PB		 2414 case MSR_IA32_TSC:
2415 kvm_write_tsc(vcpu, msr_info);
2416 break;
52797bf9
LA		 2417 case MSR_SMI_COUNT:
2418 if (!msr_info->host_initiated)
2419 return 1;
2420 vcpu->arch.smi_count = data;
2421 break;
11c6bffa 2422 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2423 case MSR_KVM_WALL_CLOCK:
2424 vcpu->kvm->arch.wall_clock = data;
2425 kvm_write_wall_clock(vcpu->kvm, data);
2426 break;
11c6bffa 2427 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2428 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2429 struct kvm_arch *ka = &vcpu->kvm->arch;
2430
12f9a48f 2431 kvmclock_reset(vcpu);
18068523 2432
54750f2c
MT		 2433 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2434 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2435
2436 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2437 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2438
2439 ka->boot_vcpu_runs_old_kvmclock = tmp;
2440 }
2441
18068523 2442 vcpu->arch.time = data;
0061d53d 2443 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2444
2445 /* we verify if the enable bit is set... */
2446 if (!(data & 1))
2447 break;
2448
4e335d9e 2449 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2450 &vcpu->arch.pv_time, data & ~1ULL,
2451 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2452 vcpu->arch.pv_time_enabled = false;
2453 else
2454 vcpu->arch.pv_time_enabled = true;
32cad84f 2455
18068523
GOC		 2456 break;
2457 }
344d9588
GN		 2458 case MSR_KVM_ASYNC_PF_EN:
2459 if (kvm_pv_enable_async_pf(vcpu, data))
2460 return 1;
2461 break;
c9aaa895
GC		 2462 case MSR_KVM_STEAL_TIME:
2463
2464 if (unlikely(!sched_info_on()))
2465 return 1;
2466
2467 if (data & KVM_STEAL_RESERVED_MASK)
2468 return 1;
2469
4e335d9e 2470 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2471 data & KVM_STEAL_VALID_BITS,
2472 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2473 return 1;
2474
2475 vcpu->arch.st.msr_val = data;
2476
2477 if (!(data & KVM_MSR_ENABLED))
2478 break;
2479
c9aaa895
GC		 2480 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2481
2482 break;
ae7a2a3f 2483 case MSR_KVM_PV_EOI_EN:
72bbf935 2484 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2485 return 1;
2486 break;
c9aaa895 2487
890ca9ae
HY		 2488 case MSR_IA32_MCG_CTL:
2489 case MSR_IA32_MCG_STATUS:
81760dcc 2490 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2491 return set_msr_mce(vcpu, msr_info);
71db6023 2492
6912ac32
WH		 2493 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2494 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2495 pr = true; /* fall through */
2496 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2497 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2498 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2499 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2500
2501 if (pr || data != 0)
a737f256
CD		 2502 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2503 "0x%x data 0x%llx\n", msr, data);
5753785f 2504 break;
84e0cefa
JS		 2505 case MSR_K7_CLK_CTL:
2506 /*
2507 * Ignore all writes to this no longer documented MSR.
2508 * Writes are only relevant for old K7 processors,
2509 * all pre-dating SVM, but a recommended workaround from
4a969980 2510 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2511 * affected processor models on the command line, hence
2512 * the need to ignore the workaround.
2513 */
2514 break;
55cd8e5a 2515 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2516 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2517 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2518 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2519 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2520 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2521 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2522 return kvm_hv_set_msr_common(vcpu, msr, data,
2523 msr_info->host_initiated);
91c9c3ed 2524 case MSR_IA32_BBL_CR_CTL3:
2525 /* Drop writes to this legacy MSR -- see rdmsr
2526 * counterpart for further detail.
2527 */
fab0aa3b
EM		 2528 if (report_ignored_msrs)
2529 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2530 msr, data);
91c9c3ed 2531 break;
2b036c6b 2532 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2533 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2534 return 1;
2535 vcpu->arch.osvw.length = data;
2536 break;
2537 case MSR_AMD64_OSVW_STATUS:
d6321d49 2538 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2539 return 1;
2540 vcpu->arch.osvw.status = data;
2541 break;
db2336a8
KH		 2542 case MSR_PLATFORM_INFO:
2543 if (!msr_info->host_initiated ||
db2336a8
KH		 2544 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2545 cpuid_fault_enabled(vcpu)))
2546 return 1;
2547 vcpu->arch.msr_platform_info = data;
2548 break;
2549 case MSR_MISC_FEATURES_ENABLES:
2550 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2551 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2552 !supports_cpuid_fault(vcpu)))
2553 return 1;
2554 vcpu->arch.msr_misc_features_enables = data;
2555 break;
15c4a640 2556 default:
ffde22ac
ES		 2557 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2558 return xen_hvm_config(vcpu, data);
c6702c9d 2559 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2560 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2561 if (!ignore_msrs) {
ae0f5499 2562 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2563 msr, data);
ed85c068
AP		 2564 return 1;
2565 } else {
fab0aa3b
EM		 2566 if (report_ignored_msrs)
2567 vcpu_unimpl(vcpu,
2568 "ignored wrmsr: 0x%x data 0x%llx\n",
2569 msr, data);
ed85c068
AP		 2570 break;
2571 }
15c4a640
CO		 2572 }
2573 return 0;
2574}
2575EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2576
2577
2578/*
2579 * Reads an msr value (of 'msr_index') into 'pdata'.
2580 * Returns 0 on success, non-0 otherwise.
2581 * Assumes vcpu_load() was already called.
2582 */
609e36d3 2583int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2584{
609e36d3 2585 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2586}
ff651cb6 2587EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2588
44883f01 2589static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2590{
2591 u64 data;
890ca9ae
HY		 2592 u64 mcg_cap = vcpu->arch.mcg_cap;
2593 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2594
2595 switch (msr) {
15c4a640
CO		 2596 case MSR_IA32_P5_MC_ADDR:
2597 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2598 data = 0;
2599 break;
15c4a640 2600 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2601 data = vcpu->arch.mcg_cap;
2602 break;
c7ac679c 2603 case MSR_IA32_MCG_CTL:
44883f01 2604 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2605 return 1;
2606 data = vcpu->arch.mcg_ctl;
2607 break;
2608 case MSR_IA32_MCG_STATUS:
2609 data = vcpu->arch.mcg_status;
2610 break;
2611 default:
2612 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2613 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2614 u32 offset = msr - MSR_IA32_MC0_CTL;
2615 data = vcpu->arch.mce_banks[offset];
2616 break;
2617 }
2618 return 1;
2619 }
2620 *pdata = data;
2621 return 0;
2622}
2623
609e36d3 2624int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2625{
609e36d3 2626 switch (msr_info->index) {
890ca9ae 2627 case MSR_IA32_PLATFORM_ID:
15c4a640 2628 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2629 case MSR_IA32_DEBUGCTLMSR:
2630 case MSR_IA32_LASTBRANCHFROMIP:
2631 case MSR_IA32_LASTBRANCHTOIP:
2632 case MSR_IA32_LASTINTFROMIP:
2633 case MSR_IA32_LASTINTTOIP:
60af2ecd 2634 case MSR_K8_SYSCFG:
3afb1121
PB		 2635 case MSR_K8_TSEG_ADDR:
2636 case MSR_K8_TSEG_MASK:
60af2ecd 2637 case MSR_K7_HWCR:
61a6bd67 2638 case MSR_VM_HSAVE_PA:
1fdbd48c 2639 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2640 case MSR_AMD64_NB_CFG:
f7c6d140 2641 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2642 case MSR_AMD64_BU_CFG2:
0c2df2a1 2643 case MSR_IA32_PERF_CTL:
405a353a 2644 case MSR_AMD64_DC_CFG:
609e36d3 2645 msr_info->data = 0;
15c4a640 2646 break;
c51eb52b 2647 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2648 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2649 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2650 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2651 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2652 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2653 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2654 msr_info->data = 0;
5753785f 2655 break;
742bc670 2656 case MSR_IA32_UCODE_REV:
518e7b94 2657 msr_info->data = vcpu->arch.microcode_version;
742bc670 2658 break;
dd259935
PB		 2659 case MSR_IA32_TSC:
2660 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2661 break;
9ba075a6 2662 case MSR_MTRRcap:
9ba075a6 2663 case 0x200 ... 0x2ff:
ff53604b 2664 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2665 case 0xcd: /* fsb frequency */
609e36d3 2666 msr_info->data = 3;
15c4a640 2667 break;
7b914098
JS		 2668 /*
2669 * MSR_EBC_FREQUENCY_ID
2670 * Conservative value valid for even the basic CPU models.
2671 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2672 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2673 * and 266MHz for model 3, or 4. Set Core Clock
2674 * Frequency to System Bus Frequency Ratio to 1 (bits
2675 * 31:24) even though these are only valid for CPU
2676 * models > 2, however guests may end up dividing or
2677 * multiplying by zero otherwise.
2678 */
2679 case MSR_EBC_FREQUENCY_ID:
609e36d3 2680 msr_info->data = 1 << 24;
7b914098 2681 break;
15c4a640 2682 case MSR_IA32_APICBASE:
609e36d3 2683 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2684 break;
0105d1a5 2685 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2686 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2687 break;
a3e06bbe 2688 case MSR_IA32_TSCDEADLINE:
609e36d3 2689 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2690 break;
ba904635 2691 case MSR_IA32_TSC_ADJUST:
609e36d3 2692 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2693 break;
15c4a640 2694 case MSR_IA32_MISC_ENABLE:
609e36d3 2695 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2696 break;
64d60670
PB		 2697 case MSR_IA32_SMBASE:
2698 if (!msr_info->host_initiated)
2699 return 1;
2700 msr_info->data = vcpu->arch.smbase;
15c4a640 2701 break;
52797bf9
LA		 2702 case MSR_SMI_COUNT:
2703 msr_info->data = vcpu->arch.smi_count;
2704 break;
847f0ad8
AG		 2705 case MSR_IA32_PERF_STATUS:
2706 /* TSC increment by tick */
609e36d3 2707 msr_info->data = 1000ULL;
847f0ad8 2708 /* CPU multiplier */
b0996ae4 2709 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2710 break;
15c4a640 2711 case MSR_EFER:
609e36d3 2712 msr_info->data = vcpu->arch.efer;
15c4a640 2713 break;
18068523 2714 case MSR_KVM_WALL_CLOCK:
11c6bffa 2715 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2716 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2717 break;
2718 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2719 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2720 msr_info->data = vcpu->arch.time;
18068523 2721 break;
344d9588 2722 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2723 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2724 break;
c9aaa895 2725 case MSR_KVM_STEAL_TIME:
609e36d3 2726 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2727 break;
1d92128f 2728 case MSR_KVM_PV_EOI_EN:
609e36d3 2729 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2730 break;
890ca9ae
HY		 2731 case MSR_IA32_P5_MC_ADDR:
2732 case MSR_IA32_P5_MC_TYPE:
2733 case MSR_IA32_MCG_CAP:
2734 case MSR_IA32_MCG_CTL:
2735 case MSR_IA32_MCG_STATUS:
81760dcc 2736 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2737 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2738 msr_info->host_initiated);
84e0cefa
JS		 2739 case MSR_K7_CLK_CTL:
2740 /*
2741 * Provide expected ramp-up count for K7. All other
2742 * are set to zero, indicating minimum divisors for
2743 * every field.
2744 *
2745 * This prevents guest kernels on AMD host with CPU
2746 * type 6, model 8 and higher from exploding due to
2747 * the rdmsr failing.
2748 */
609e36d3 2749 msr_info->data = 0x20000000;
84e0cefa 2750 break;
55cd8e5a 2751 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2752 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2753 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2754 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2755 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2756 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2757 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2758 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2759 msr_info->index, &msr_info->data,
2760 msr_info->host_initiated);
55cd8e5a 2761 break;
91c9c3ed 2762 case MSR_IA32_BBL_CR_CTL3:
2763 /* This legacy MSR exists but isn't fully documented in current
2764 * silicon. It is however accessed by winxp in very narrow
2765 * scenarios where it sets bit #19, itself documented as
2766 * a "reserved" bit. Best effort attempt to source coherent
2767 * read data here should the balance of the register be
2768 * interpreted by the guest:
2769 *
2770 * L2 cache control register 3: 64GB range, 256KB size,
2771 * enabled, latency 0x1, configured
2772 */
609e36d3 2773 msr_info->data = 0xbe702111;
91c9c3ed 2774 break;
2b036c6b 2775 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2776 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2777 return 1;
609e36d3 2778 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2779 break;
2780 case MSR_AMD64_OSVW_STATUS:
d6321d49 2781 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2782 return 1;
609e36d3 2783 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2784 break;
db2336a8 2785 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2786 if (!msr_info->host_initiated &&
2787 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2788 return 1;
db2336a8
KH		 2789 msr_info->data = vcpu->arch.msr_platform_info;
2790 break;
2791 case MSR_MISC_FEATURES_ENABLES:
2792 msr_info->data = vcpu->arch.msr_misc_features_enables;
2793 break;
15c4a640 2794 default:
c6702c9d 2795 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2796 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2797 if (!ignore_msrs) {
ae0f5499
BD		 2798 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2799 msr_info->index);
ed85c068
AP		 2800 return 1;
2801 } else {
fab0aa3b
EM		 2802 if (report_ignored_msrs)
2803 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2804 msr_info->index);
609e36d3 2805 msr_info->data = 0;
ed85c068
AP		 2806 }
2807 break;
15c4a640 2808 }
15c4a640
CO		 2809 return 0;
2810}
2811EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2812
313a3dc7
CO		 2813/*
2814 * Read or write a bunch of msrs. All parameters are kernel addresses.
2815 *
2816 * @return number of msrs set successfully.
2817 */
2818static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2819 struct kvm_msr_entry *entries,
2820 int (*do_msr)(struct kvm_vcpu *vcpu,
2821 unsigned index, u64 *data))
2822{
801e459a 2823 int i;
313a3dc7 2824
313a3dc7
CO		 2825 for (i = 0; i < msrs->nmsrs; ++i)
2826 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2827 break;
2828
313a3dc7
CO		 2829 return i;
2830}
2831
2832/*
2833 * Read or write a bunch of msrs. Parameters are user addresses.
2834 *
2835 * @return number of msrs set successfully.
2836 */
2837static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2838 int (*do_msr)(struct kvm_vcpu *vcpu,
2839 unsigned index, u64 *data),
2840 int writeback)
2841{
2842 struct kvm_msrs msrs;
2843 struct kvm_msr_entry *entries;
2844 int r, n;
2845 unsigned size;
2846
2847 r = -EFAULT;
2848 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2849 goto out;
2850
2851 r = -E2BIG;
2852 if (msrs.nmsrs >= MAX_IO_MSRS)
2853 goto out;
2854
313a3dc7 2855 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2856 entries = memdup_user(user_msrs->entries, size);
2857 if (IS_ERR(entries)) {
2858 r = PTR_ERR(entries);
313a3dc7 2859 goto out;
ff5c2c03 2860 }
313a3dc7
CO		 2861
2862 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2863 if (r < 0)
2864 goto out_free;
2865
2866 r = -EFAULT;
2867 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2868 goto out_free;
2869
2870 r = n;
2871
2872out_free:
7a73c028 2873 kfree(entries);
313a3dc7
CO		 2874out:
2875 return r;
2876}
2877
4d5422ce
WL		 2878static inline bool kvm_can_mwait_in_guest(void)
2879{
2880 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2881 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2882 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2883}
2884
784aa3d7 2885int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2886{
4d5422ce 2887 int r = 0;
018d00d2
ZX		 2888
2889 switch (ext) {
2890 case KVM_CAP_IRQCHIP:
2891 case KVM_CAP_HLT:
2892 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2893 case KVM_CAP_SET_TSS_ADDR:
07716717 2894 case KVM_CAP_EXT_CPUID:
9c15bb1d 2895 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2896 case KVM_CAP_CLOCKSOURCE:
7837699f 2897 case KVM_CAP_PIT:
a28e4f5a 2898 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2899 case KVM_CAP_MP_STATE:
ed848624 2900 case KVM_CAP_SYNC_MMU:
a355c85c 2901 case KVM_CAP_USER_NMI:
52d939a0 2902 case KVM_CAP_REINJECT_CONTROL:
4925663a 2903 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2904 case KVM_CAP_IOEVENTFD:
f848a5a8 2905 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2906 case KVM_CAP_PIT2:
e9f42757 2907 case KVM_CAP_PIT_STATE2:
b927a3ce 2908 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2909 case KVM_CAP_XEN_HVM:
3cfc3092 2910 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2911 case KVM_CAP_HYPERV:
10388a07 2912 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2913 case KVM_CAP_HYPERV_SPIN:
5c919412 2914 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2915 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2916 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2917 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 2918 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 2919 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 2920 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
ab9f4ecb 2921 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2922 case KVM_CAP_DEBUGREGS:
d2be1651 2923 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2924 case KVM_CAP_XSAVE:
344d9588 2925 case KVM_CAP_ASYNC_PF:
92a1f12d 2926 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2927 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2928 case KVM_CAP_READONLY_MEM:
5f66b620 2929 case KVM_CAP_HYPERV_TIME:
100943c5 2930 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2931 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2932 case KVM_CAP_ENABLE_CAP_VM:
2933 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2934 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2935 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2936 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2937 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 2938 case KVM_CAP_MSR_PLATFORM_INFO:
018d00d2
ZX		 2939 r = 1;
2940 break;
01643c51
KH		 2941 case KVM_CAP_SYNC_REGS:
2942 r = KVM_SYNC_X86_VALID_FIELDS;
2943 break;
e3fd9a93
PB		 2944 case KVM_CAP_ADJUST_CLOCK:
2945 r = KVM_CLOCK_TSC_STABLE;
2946 break;
4d5422ce 2947 case KVM_CAP_X86_DISABLE_EXITS:
766d3571 2948 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 2949 if(kvm_can_mwait_in_guest())
2950 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 2951 break;
6d396b55
PB		 2952 case KVM_CAP_X86_SMM:
2953 /* SMBASE is usually relocated above 1M on modern chipsets,
2954 * and SMM handlers might indeed rely on 4G segment limits,
2955 * so do not report SMM to be available if real mode is
2956 * emulated via vm86 mode. Still, do not go to great lengths
2957 * to avoid userspace's usage of the feature, because it is a
2958 * fringe case that is not enabled except via specific settings
2959 * of the module parameters.
2960 */
bc226f07 2961 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 2962 break;
774ead3a
AK		 2963 case KVM_CAP_VAPIC:
2964 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2965 break;
f725230a 2966 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2967 r = KVM_SOFT_MAX_VCPUS;
2968 break;
2969 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2970 r = KVM_MAX_VCPUS;
2971 break;
a988b910 2972 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2973 r = KVM_USER_MEM_SLOTS;
a988b910 2974 break;
a68a6a72
MT		 2975 case KVM_CAP_PV_MMU: /* obsolete */
2976 r = 0;
2f333bcb 2977 break;
890ca9ae
HY		 2978 case KVM_CAP_MCE:
2979 r = KVM_MAX_MCE_BANKS;
2980 break;
2d5b5a66 2981 case KVM_CAP_XCRS:
d366bf7e 2982 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2983 break;
92a1f12d
JR		 2984 case KVM_CAP_TSC_CONTROL:
2985 r = kvm_has_tsc_control;
2986 break;
37131313
RK		 2987 case KVM_CAP_X2APIC_API:
2988 r = KVM_X2APIC_API_VALID_FLAGS;
2989 break;
8fcc4b59
JM		 2990 case KVM_CAP_NESTED_STATE:
2991 r = kvm_x86_ops->get_nested_state ?
2992 kvm_x86_ops->get_nested_state(NULL, 0, 0) : 0;
2993 break;
018d00d2 2994 default:
018d00d2
ZX		 2995 break;
2996 }
2997 return r;
2998
2999}
3000
043405e1
CO		 3001long kvm_arch_dev_ioctl(struct file *filp,
3002 unsigned int ioctl, unsigned long arg)
3003{
3004 void __user *argp = (void __user *)arg;
3005 long r;
3006
3007 switch (ioctl) {
3008 case KVM_GET_MSR_INDEX_LIST: {
3009 struct kvm_msr_list __user *user_msr_list = argp;
3010 struct kvm_msr_list msr_list;
3011 unsigned n;
3012
3013 r = -EFAULT;
3014 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
3015 goto out;
3016 n = msr_list.nmsrs;
62ef68bb 3017 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 3018 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
3019 goto out;
3020 r = -E2BIG;
e125e7b6 3021 if (n < msr_list.nmsrs)
043405e1
CO		 3022 goto out;
3023 r = -EFAULT;
3024 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3025 num_msrs_to_save * sizeof(u32)))
3026 goto out;
e125e7b6 3027 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3028 &emulated_msrs,
62ef68bb 3029 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3030 goto out;
3031 r = 0;
3032 break;
3033 }
9c15bb1d
BP		 3034 case KVM_GET_SUPPORTED_CPUID:
3035 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3036 struct kvm_cpuid2 __user *cpuid_arg = argp;
3037 struct kvm_cpuid2 cpuid;
3038
3039 r = -EFAULT;
3040 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3041 goto out;
9c15bb1d
BP		 3042
3043 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3044 ioctl);
674eea0f
AK		 3045 if (r)
3046 goto out;
3047
3048 r = -EFAULT;
3049 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3050 goto out;
3051 r = 0;
3052 break;
3053 }
890ca9ae 3054 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3055 r = -EFAULT;
c45dcc71
AR		 3056 if (copy_to_user(argp, &kvm_mce_cap_supported,
3057 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3058 goto out;
3059 r = 0;
3060 break;
801e459a
TL		 3061 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3062 struct kvm_msr_list __user *user_msr_list = argp;
3063 struct kvm_msr_list msr_list;
3064 unsigned int n;
3065
3066 r = -EFAULT;
3067 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3068 goto out;
3069 n = msr_list.nmsrs;
3070 msr_list.nmsrs = num_msr_based_features;
3071 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3072 goto out;
3073 r = -E2BIG;
3074 if (n < msr_list.nmsrs)
3075 goto out;
3076 r = -EFAULT;
3077 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3078 num_msr_based_features * sizeof(u32)))
3079 goto out;
3080 r = 0;
3081 break;
3082 }
3083 case KVM_GET_MSRS:
3084 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3085 break;
890ca9ae 3086 }
043405e1
CO		 3087 default:
3088 r = -EINVAL;
3089 }
3090out:
3091 return r;
3092}
3093
f5f48ee1
SY		 3094static void wbinvd_ipi(void *garbage)
3095{
3096 wbinvd();
3097}
3098
3099static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3100{
e0f0bbc5 3101 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3102}
3103
313a3dc7
CO		 3104void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3105{
f5f48ee1
SY		 3106 /* Address WBINVD may be executed by guest */
3107 if (need_emulate_wbinvd(vcpu)) {
3108 if (kvm_x86_ops->has_wbinvd_exit())
3109 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3110 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3111 smp_call_function_single(vcpu->cpu,
3112 wbinvd_ipi, NULL, 1);
3113 }
3114
313a3dc7 3115 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3116
0dd6a6ed
ZA		 3117 /* Apply any externally detected TSC adjustments (due to suspend) */
3118 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3119 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3120 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3121 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3122 }
8f6055cb 3123
b0c39dc6 3124 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3125 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3126 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3127 if (tsc_delta < 0)
3128 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3129
b0c39dc6 3130 if (kvm_check_tsc_unstable()) {
07c1419a 3131 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3132 vcpu->arch.last_guest_tsc);
a545ab6a 3133 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3134 vcpu->arch.tsc_catchup = 1;
c285545f 3135 }
a749e247
PB		 3136
3137 if (kvm_lapic_hv_timer_in_use(vcpu))
3138 kvm_lapic_restart_hv_timer(vcpu);
3139
d98d07ca
MT		 3140 /*
3141 * On a host with synchronized TSC, there is no need to update
3142 * kvmclock on vcpu->cpu migration
3143 */
3144 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3145 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3146 if (vcpu->cpu != cpu)
1bd2009e 3147 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3148 vcpu->cpu = cpu;
6b7d7e76 3149 }
c9aaa895 3150
c9aaa895 3151 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3152}
3153
0b9f6c46
PX		 3154static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3155{
3156 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3157 return;
3158
fa55eedd 3159 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3160
4e335d9e 3161 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3162 &vcpu->arch.st.steal.preempted,
3163 offsetof(struct kvm_steal_time, preempted),
3164 sizeof(vcpu->arch.st.steal.preempted));
3165}
3166
313a3dc7
CO		 3167void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3168{
cc0d907c 3169 int idx;
de63ad4c
LM		 3170
3171 if (vcpu->preempted)
3172 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3173
931f261b
AA		 3174 /*
3175 * Disable page faults because we're in atomic context here.
3176 * kvm_write_guest_offset_cached() would call might_fault()
3177 * that relies on pagefault_disable() to tell if there's a
3178 * bug. NOTE: the write to guest memory may not go through if
3179 * during postcopy live migration or if there's heavy guest
3180 * paging.
3181 */
3182 pagefault_disable();
cc0d907c
AA		 3183 /*
3184 * kvm_memslots() will be called by
3185 * kvm_write_guest_offset_cached() so take the srcu lock.
3186 */
3187 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3188 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3189 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3190 pagefault_enable();
02daab21 3191 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3192 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3193 /*
0e0a53c5
PB		 3194 * Here dr6 is either zero or, if the guest has run and userspace
3195 * has not set any breakpoints or watchpoints, it can be set to
3196 * the guest dr6 (stored in vcpu->arch.dr6). do_debug expects dr6
3197 * to be cleared after it runs, so clear the host register. However,
3198 * MOV to DR can be expensive when running nested, omit it if
3199 * vcpu->arch.dr6 is already zero: in that case, the host dr6 cannot
3200 * currently be nonzero.
efdab992 3201 */
0e0a53c5
PB		 3202 if (vcpu->arch.dr6)
3203 set_debugreg(0, 6);
313a3dc7
CO		 3204}
3205
313a3dc7
CO		 3206static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3207 struct kvm_lapic_state *s)
3208{
fa59cc00 3209 if (vcpu->arch.apicv_active)
d62caabb
AS		 3210 kvm_x86_ops->sync_pir_to_irr(vcpu);
3211
a92e2543 3212 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3213}
3214
3215static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3216 struct kvm_lapic_state *s)
3217{
a92e2543
RK		 3218 int r;
3219
3220 r = kvm_apic_set_state(vcpu, s);
3221 if (r)
3222 return r;
cb142eb7 3223 update_cr8_intercept(vcpu);
313a3dc7
CO		 3224
3225 return 0;
3226}
3227
127a457a
MG		 3228static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3229{
3230 return (!lapic_in_kernel(vcpu) ||
3231 kvm_apic_accept_pic_intr(vcpu));
3232}
3233
782d422b
MG		 3234/*
3235 * if userspace requested an interrupt window, check that the
3236 * interrupt window is open.
3237 *
3238 * No need to exit to userspace if we already have an interrupt queued.
3239 */
3240static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3241{
3242 return kvm_arch_interrupt_allowed(vcpu) &&
3243 !kvm_cpu_has_interrupt(vcpu) &&
3244 !kvm_event_needs_reinjection(vcpu) &&
3245 kvm_cpu_accept_dm_intr(vcpu);
3246}
3247
f77bc6a4
ZX		 3248static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3249 struct kvm_interrupt *irq)
3250{
02cdb50f 3251 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3252 return -EINVAL;
1c1a9ce9
SR		 3253
3254 if (!irqchip_in_kernel(vcpu->kvm)) {
3255 kvm_queue_interrupt(vcpu, irq->irq, false);
3256 kvm_make_request(KVM_REQ_EVENT, vcpu);
3257 return 0;
3258 }
3259
3260 /*
3261 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3262 * fail for in-kernel 8259.
3263 */
3264 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3265 return -ENXIO;
f77bc6a4 3266
1c1a9ce9
SR		 3267 if (vcpu->arch.pending_external_vector != -1)
3268 return -EEXIST;
f77bc6a4 3269
1c1a9ce9 3270 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3271 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3272 return 0;
3273}
3274
c4abb7c9
JK		 3275static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3276{
c4abb7c9 3277 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3278
3279 return 0;
3280}
3281
f077825a
PB		 3282static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3283{
64d60670
PB		 3284 kvm_make_request(KVM_REQ_SMI, vcpu);
3285
f077825a
PB		 3286 return 0;
3287}
3288
b209749f
AK		 3289static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3290 struct kvm_tpr_access_ctl *tac)
3291{
3292 if (tac->flags)
3293 return -EINVAL;
3294 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3295 return 0;
3296}
3297
890ca9ae
HY		 3298static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3299 u64 mcg_cap)
3300{
3301 int r;
3302 unsigned bank_num = mcg_cap & 0xff, bank;
3303
3304 r = -EINVAL;
a9e38c3e 3305 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3306 goto out;
c45dcc71 3307 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3308 goto out;
3309 r = 0;
3310 vcpu->arch.mcg_cap = mcg_cap;
3311 /* Init IA32_MCG_CTL to all 1s */
3312 if (mcg_cap & MCG_CTL_P)
3313 vcpu->arch.mcg_ctl = ~(u64)0;
3314 /* Init IA32_MCi_CTL to all 1s */
3315 for (bank = 0; bank < bank_num; bank++)
3316 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3317
3318 if (kvm_x86_ops->setup_mce)
3319 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3320out:
3321 return r;
3322}
3323
3324static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3325 struct kvm_x86_mce *mce)
3326{
3327 u64 mcg_cap = vcpu->arch.mcg_cap;
3328 unsigned bank_num = mcg_cap & 0xff;
3329 u64 *banks = vcpu->arch.mce_banks;
3330
3331 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3332 return -EINVAL;
3333 /*
3334 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3335 * reporting is disabled
3336 */
3337 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3338 vcpu->arch.mcg_ctl != ~(u64)0)
3339 return 0;
3340 banks += 4 * mce->bank;
3341 /*
3342 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3343 * reporting is disabled for the bank
3344 */
3345 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3346 return 0;
3347 if (mce->status & MCI_STATUS_UC) {
3348 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3349 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3350 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3351 return 0;
3352 }
3353 if (banks[1] & MCI_STATUS_VAL)
3354 mce->status |= MCI_STATUS_OVER;
3355 banks[2] = mce->addr;
3356 banks[3] = mce->misc;
3357 vcpu->arch.mcg_status = mce->mcg_status;
3358 banks[1] = mce->status;
3359 kvm_queue_exception(vcpu, MC_VECTOR);
3360 } else if (!(banks[1] & MCI_STATUS_VAL)
3361 || !(banks[1] & MCI_STATUS_UC)) {
3362 if (banks[1] & MCI_STATUS_VAL)
3363 mce->status |= MCI_STATUS_OVER;
3364 banks[2] = mce->addr;
3365 banks[3] = mce->misc;
3366 banks[1] = mce->status;
3367 } else
3368 banks[1] |= MCI_STATUS_OVER;
3369 return 0;
3370}
3371
3cfc3092
JK		 3372static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3373 struct kvm_vcpu_events *events)
3374{
7460fb4a 3375 process_nmi(vcpu);
664f8e26
WL		 3376 /*
3377 * FIXME: pass injected and pending separately. This is only
3378 * needed for nested virtualization, whose state cannot be
3379 * migrated yet. For now we can combine them.
3380 */
03b82a30 3381 events->exception.injected =
664f8e26
WL		 3382 (vcpu->arch.exception.pending ||
3383 vcpu->arch.exception.injected) &&
03b82a30 3384 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3385 events->exception.nr = vcpu->arch.exception.nr;
3386 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3387 events->exception.pad = 0;
3cfc3092
JK		 3388 events->exception.error_code = vcpu->arch.exception.error_code;
3389
03b82a30 3390 events->interrupt.injected =
04140b41 3391 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3392 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3393 events->interrupt.soft = 0;
37ccdcbe 3394 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3395
3396 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3397 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3398 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3399 events->nmi.pad = 0;
3cfc3092 3400
66450a21 3401 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3402
f077825a
PB		 3403 events->smi.smm = is_smm(vcpu);
3404 events->smi.pending = vcpu->arch.smi_pending;
3405 events->smi.smm_inside_nmi =
3406 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3407 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3408
dab4b911 3409 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3410 | KVM_VCPUEVENT_VALID_SHADOW
3411 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3412 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3413}
3414
6ef4e07e
XG		 3415static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3416
3cfc3092
JK		 3417static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3418 struct kvm_vcpu_events *events)
3419{
dab4b911 3420 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3421 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3422 | KVM_VCPUEVENT_VALID_SHADOW
3423 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3424 return -EINVAL;
3425
78e546c8 3426 if (events->exception.injected &&
28d06353
JM		 3427 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3428 is_guest_mode(vcpu)))
78e546c8
PB		 3429 return -EINVAL;
3430
28bf2888
DH		 3431 /* INITs are latched while in SMM */
3432 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3433 (events->smi.smm || events->smi.pending) &&
3434 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3435 return -EINVAL;
3436
7460fb4a 3437 process_nmi(vcpu);
664f8e26 3438 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3439 vcpu->arch.exception.pending = events->exception.injected;
3440 vcpu->arch.exception.nr = events->exception.nr;
3441 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3442 vcpu->arch.exception.error_code = events->exception.error_code;
c851436a
JM		 3443 vcpu->arch.exception.has_payload = false;
3444 vcpu->arch.exception.payload = 0;
3cfc3092 3445
04140b41 3446 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3447 vcpu->arch.interrupt.nr = events->interrupt.nr;
3448 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3449 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3450 kvm_x86_ops->set_interrupt_shadow(vcpu,
3451 events->interrupt.shadow);
3cfc3092
JK		 3452
3453 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3454 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3455 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3456 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3457
66450a21 3458 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3459 lapic_in_kernel(vcpu))
66450a21 3460 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3461
f077825a 3462 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3463 u32 hflags = vcpu->arch.hflags;
f077825a 3464 if (events->smi.smm)
6ef4e07e 3465 hflags |= HF_SMM_MASK;
f077825a 3466 else
6ef4e07e
XG		 3467 hflags &= ~HF_SMM_MASK;
3468 kvm_set_hflags(vcpu, hflags);
3469
f077825a 3470 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3471
3472 if (events->smi.smm) {
3473 if (events->smi.smm_inside_nmi)
3474 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3475 else
f4ef1910
WL		 3476 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3477 if (lapic_in_kernel(vcpu)) {
3478 if (events->smi.latched_init)
3479 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3480 else
3481 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3482 }
f077825a
PB		 3483 }
3484 }
3485
3842d135
AK		 3486 kvm_make_request(KVM_REQ_EVENT, vcpu);
3487
3cfc3092
JK		 3488 return 0;
3489}
3490
a1efbe77
JK		 3491static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3492 struct kvm_debugregs *dbgregs)
3493{
73aaf249
JK		 3494 unsigned long val;
3495
a1efbe77 3496 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3497 kvm_get_dr(vcpu, 6, &val);
73aaf249 3498 dbgregs->dr6 = val;
a1efbe77
JK		 3499 dbgregs->dr7 = vcpu->arch.dr7;
3500 dbgregs->flags = 0;
97e69aa6 3501 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3502}
3503
3504static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3505 struct kvm_debugregs *dbgregs)
3506{
3507 if (dbgregs->flags)
3508 return -EINVAL;
3509
d14bdb55
PB		 3510 if (dbgregs->dr6 & ~0xffffffffull)
3511 return -EINVAL;
3512 if (dbgregs->dr7 & ~0xffffffffull)
3513 return -EINVAL;
3514
a1efbe77 3515 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3516 kvm_update_dr0123(vcpu);
a1efbe77 3517 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3518 kvm_update_dr6(vcpu);
a1efbe77 3519 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3520 kvm_update_dr7(vcpu);
a1efbe77 3521
a1efbe77
JK		 3522 return 0;
3523}
3524
df1daba7
PB		 3525#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3526
3527static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3528{
c47ada30 3529 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3530 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3531 u64 valid;
3532
3533 /*
3534 * Copy legacy XSAVE area, to avoid complications with CPUID
3535 * leaves 0 and 1 in the loop below.
3536 */
3537 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3538
3539 /* Set XSTATE_BV */
00c87e9a 3540 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3541 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3542
3543 /*
3544 * Copy each region from the possibly compacted offset to the
3545 * non-compacted offset.
3546 */
d91cab78 3547 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3548 while (valid) {
3549 u64 feature = valid & -valid;
3550 int index = fls64(feature) - 1;
3551 void *src = get_xsave_addr(xsave, feature);
3552
3553 if (src) {
3554 u32 size, offset, ecx, edx;
3555 cpuid_count(XSTATE_CPUID, index,
3556 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3557 if (feature == XFEATURE_MASK_PKRU)
3558 memcpy(dest + offset, &vcpu->arch.pkru,
3559 sizeof(vcpu->arch.pkru));
3560 else
3561 memcpy(dest + offset, src, size);
3562
df1daba7
PB		 3563 }
3564
3565 valid -= feature;
3566 }
3567}
3568
3569static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3570{
c47ada30 3571 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3572 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3573 u64 valid;
3574
3575 /*
3576 * Copy legacy XSAVE area, to avoid complications with CPUID
3577 * leaves 0 and 1 in the loop below.
3578 */
3579 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3580
3581 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3582 xsave->header.xfeatures = xstate_bv;
782511b0 3583 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3584 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3585
3586 /*
3587 * Copy each region from the non-compacted offset to the
3588 * possibly compacted offset.
3589 */
d91cab78 3590 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3591 while (valid) {
3592 u64 feature = valid & -valid;
3593 int index = fls64(feature) - 1;
3594 void *dest = get_xsave_addr(xsave, feature);
3595
3596 if (dest) {
3597 u32 size, offset, ecx, edx;
3598 cpuid_count(XSTATE_CPUID, index,
3599 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3600 if (feature == XFEATURE_MASK_PKRU)
3601 memcpy(&vcpu->arch.pkru, src + offset,
3602 sizeof(vcpu->arch.pkru));
3603 else
3604 memcpy(dest, src + offset, size);
ee4100da 3605 }
df1daba7
PB		 3606
3607 valid -= feature;
3608 }
3609}
3610
2d5b5a66
SY		 3611static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3612 struct kvm_xsave *guest_xsave)
3613{
d366bf7e 3614 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3615 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3616 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3617 } else {
2d5b5a66 3618 memcpy(guest_xsave->region,
7366ed77 3619 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3620 sizeof(struct fxregs_state));
2d5b5a66 3621 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3622 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3623 }
3624}
3625
a575813b
WL		 3626#define XSAVE_MXCSR_OFFSET 24
3627
2d5b5a66
SY		 3628static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3629 struct kvm_xsave *guest_xsave)
3630{
3631 u64 xstate_bv =
3632 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3633 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3634
d366bf7e 3635 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3636 /*
3637 * Here we allow setting states that are not present in
3638 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3639 * with old userspace.
3640 */
a575813b
WL		 3641 if (xstate_bv & ~kvm_supported_xcr0() ||
3642 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3643 return -EINVAL;
df1daba7 3644 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3645 } else {
a575813b
WL		 3646 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3647 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3648 return -EINVAL;
7366ed77 3649 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3650 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3651 }
3652 return 0;
3653}
3654
3655static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3656 struct kvm_xcrs *guest_xcrs)
3657{
d366bf7e 3658 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3659 guest_xcrs->nr_xcrs = 0;
3660 return;
3661 }
3662
3663 guest_xcrs->nr_xcrs = 1;
3664 guest_xcrs->flags = 0;
3665 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3666 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3667}
3668
3669static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3670 struct kvm_xcrs *guest_xcrs)
3671{
3672 int i, r = 0;
3673
d366bf7e 3674 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3675 return -EINVAL;
3676
3677 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3678 return -EINVAL;
3679
3680 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3681 /* Only support XCR0 currently */
c67a04cb 3682 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3683 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3684 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3685 break;
3686 }
3687 if (r)
3688 r = -EINVAL;
3689 return r;
3690}
3691
1c0b28c2
EM		 3692/*
3693 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3694 * stopped by the hypervisor. This function will be called from the host only.
3695 * EINVAL is returned when the host attempts to set the flag for a guest that
3696 * does not support pv clocks.
3697 */
3698static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3699{
0b79459b 3700 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3701 return -EINVAL;
51d59c6b 3702 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3703 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3704 return 0;
3705}
3706
5c919412
AS		 3707static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3708 struct kvm_enable_cap *cap)
3709{
57b119da
VK		 3710 int r;
3711 uint16_t vmcs_version;
3712 void __user *user_ptr;
3713
5c919412
AS		 3714 if (cap->flags)
3715 return -EINVAL;
3716
3717 switch (cap->cap) {
efc479e6
RK		 3718 case KVM_CAP_HYPERV_SYNIC2:
3719 if (cap->args[0])
3720 return -EINVAL;
5c919412 3721 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3722 if (!irqchip_in_kernel(vcpu->kvm))
3723 return -EINVAL;
efc479e6
RK		 3724 return kvm_hv_activate_synic(vcpu, cap->cap ==
3725 KVM_CAP_HYPERV_SYNIC2);
57b119da
VK		 3726 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3727 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3728 if (!r) {
3729 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3730 if (copy_to_user(user_ptr, &vmcs_version,
3731 sizeof(vmcs_version)))
3732 r = -EFAULT;
3733 }
3734 return r;
3735
5c919412
AS		 3736 default:
3737 return -EINVAL;
3738 }
3739}
3740
313a3dc7
CO		 3741long kvm_arch_vcpu_ioctl(struct file *filp,
3742 unsigned int ioctl, unsigned long arg)
3743{
3744 struct kvm_vcpu *vcpu = filp->private_data;
3745 void __user *argp = (void __user *)arg;
3746 int r;
d1ac91d8
AK		 3747 union {
3748 struct kvm_lapic_state *lapic;
3749 struct kvm_xsave *xsave;
3750 struct kvm_xcrs *xcrs;
3751 void *buffer;
3752 } u;
3753
9b062471
CD		 3754 vcpu_load(vcpu);
3755
d1ac91d8 3756 u.buffer = NULL;
313a3dc7
CO		 3757 switch (ioctl) {
3758 case KVM_GET_LAPIC: {
2204ae3c 3759 r = -EINVAL;
bce87cce 3760 if (!lapic_in_kernel(vcpu))
2204ae3c 3761 goto out;
d1ac91d8 3762 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3763
b772ff36 3764 r = -ENOMEM;
d1ac91d8 3765 if (!u.lapic)
b772ff36 3766 goto out;
d1ac91d8 3767 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3768 if (r)
3769 goto out;
3770 r = -EFAULT;
d1ac91d8 3771 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3772 goto out;
3773 r = 0;
3774 break;
3775 }
3776 case KVM_SET_LAPIC: {
2204ae3c 3777 r = -EINVAL;
bce87cce 3778 if (!lapic_in_kernel(vcpu))
2204ae3c 3779 goto out;
ff5c2c03 3780 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3781 if (IS_ERR(u.lapic)) {
3782 r = PTR_ERR(u.lapic);
3783 goto out_nofree;
3784 }
ff5c2c03 3785
d1ac91d8 3786 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3787 break;
3788 }
f77bc6a4
ZX		 3789 case KVM_INTERRUPT: {
3790 struct kvm_interrupt irq;
3791
3792 r = -EFAULT;
3793 if (copy_from_user(&irq, argp, sizeof irq))
3794 goto out;
3795 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3796 break;
3797 }
c4abb7c9
JK		 3798 case KVM_NMI: {
3799 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3800 break;
3801 }
f077825a
PB		 3802 case KVM_SMI: {
3803 r = kvm_vcpu_ioctl_smi(vcpu);
3804 break;
3805 }
313a3dc7
CO		 3806 case KVM_SET_CPUID: {
3807 struct kvm_cpuid __user *cpuid_arg = argp;
3808 struct kvm_cpuid cpuid;
3809
3810 r = -EFAULT;
3811 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3812 goto out;
3813 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3814 break;
3815 }
07716717
DK		 3816 case KVM_SET_CPUID2: {
3817 struct kvm_cpuid2 __user *cpuid_arg = argp;
3818 struct kvm_cpuid2 cpuid;
3819
3820 r = -EFAULT;
3821 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3822 goto out;
3823 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3824 cpuid_arg->entries);
07716717
DK		 3825 break;
3826 }
3827 case KVM_GET_CPUID2: {
3828 struct kvm_cpuid2 __user *cpuid_arg = argp;
3829 struct kvm_cpuid2 cpuid;
3830
3831 r = -EFAULT;
3832 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3833 goto out;
3834 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3835 cpuid_arg->entries);
07716717
DK		 3836 if (r)
3837 goto out;
3838 r = -EFAULT;
3839 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3840 goto out;
3841 r = 0;
3842 break;
3843 }
801e459a
TL		 3844 case KVM_GET_MSRS: {
3845 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3846 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3847 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3848 break;
801e459a
TL		 3849 }
3850 case KVM_SET_MSRS: {
3851 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3852 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3853 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3854 break;
801e459a 3855 }
b209749f
AK		 3856 case KVM_TPR_ACCESS_REPORTING: {
3857 struct kvm_tpr_access_ctl tac;
3858
3859 r = -EFAULT;
3860 if (copy_from_user(&tac, argp, sizeof tac))
3861 goto out;
3862 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3863 if (r)
3864 goto out;
3865 r = -EFAULT;
3866 if (copy_to_user(argp, &tac, sizeof tac))
3867 goto out;
3868 r = 0;
3869 break;
3870 };
b93463aa
AK		 3871 case KVM_SET_VAPIC_ADDR: {
3872 struct kvm_vapic_addr va;
7301d6ab 3873 int idx;
b93463aa
AK		 3874
3875 r = -EINVAL;
35754c98 3876 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3877 goto out;
3878 r = -EFAULT;
3879 if (copy_from_user(&va, argp, sizeof va))
3880 goto out;
7301d6ab 3881 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3882 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3883 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3884 break;
3885 }
890ca9ae
HY		 3886 case KVM_X86_SETUP_MCE: {
3887 u64 mcg_cap;
3888
3889 r = -EFAULT;
3890 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3891 goto out;
3892 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3893 break;
3894 }
3895 case KVM_X86_SET_MCE: {
3896 struct kvm_x86_mce mce;
3897
3898 r = -EFAULT;
3899 if (copy_from_user(&mce, argp, sizeof mce))
3900 goto out;
3901 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3902 break;
3903 }
3cfc3092
JK		 3904 case KVM_GET_VCPU_EVENTS: {
3905 struct kvm_vcpu_events events;
3906
3907 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3908
3909 r = -EFAULT;
3910 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3911 break;
3912 r = 0;
3913 break;
3914 }
3915 case KVM_SET_VCPU_EVENTS: {
3916 struct kvm_vcpu_events events;
3917
3918 r = -EFAULT;
3919 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3920 break;
3921
3922 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3923 break;
3924 }
a1efbe77
JK		 3925 case KVM_GET_DEBUGREGS: {
3926 struct kvm_debugregs dbgregs;
3927
3928 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3929
3930 r = -EFAULT;
3931 if (copy_to_user(argp, &dbgregs,
3932 sizeof(struct kvm_debugregs)))
3933 break;
3934 r = 0;
3935 break;
3936 }
3937 case KVM_SET_DEBUGREGS: {
3938 struct kvm_debugregs dbgregs;
3939
3940 r = -EFAULT;
3941 if (copy_from_user(&dbgregs, argp,
3942 sizeof(struct kvm_debugregs)))
3943 break;
3944
3945 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3946 break;
3947 }
2d5b5a66 3948 case KVM_GET_XSAVE: {
d1ac91d8 3949 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3950 r = -ENOMEM;
d1ac91d8 3951 if (!u.xsave)
2d5b5a66
SY		 3952 break;
3953
d1ac91d8 3954 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3955
3956 r = -EFAULT;
d1ac91d8 3957 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3958 break;
3959 r = 0;
3960 break;
3961 }
3962 case KVM_SET_XSAVE: {
ff5c2c03 3963 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3964 if (IS_ERR(u.xsave)) {
3965 r = PTR_ERR(u.xsave);
3966 goto out_nofree;
3967 }
2d5b5a66 3968
d1ac91d8 3969 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3970 break;
3971 }
3972 case KVM_GET_XCRS: {
d1ac91d8 3973 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3974 r = -ENOMEM;
d1ac91d8 3975 if (!u.xcrs)
2d5b5a66
SY		 3976 break;
3977
d1ac91d8 3978 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3979
3980 r = -EFAULT;
d1ac91d8 3981 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3982 sizeof(struct kvm_xcrs)))
3983 break;
3984 r = 0;
3985 break;
3986 }
3987 case KVM_SET_XCRS: {
ff5c2c03 3988 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3989 if (IS_ERR(u.xcrs)) {
3990 r = PTR_ERR(u.xcrs);
3991 goto out_nofree;
3992 }
2d5b5a66 3993
d1ac91d8 3994 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3995 break;
3996 }
92a1f12d
JR		 3997 case KVM_SET_TSC_KHZ: {
3998 u32 user_tsc_khz;
3999
4000 r = -EINVAL;
92a1f12d
JR		 4001 user_tsc_khz = (u32)arg;
4002
4003 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4004 goto out;
4005
cc578287
ZA		 4006 if (user_tsc_khz == 0)
4007 user_tsc_khz = tsc_khz;
4008
381d585c
HZ		 4009 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4010 r = 0;
92a1f12d 4011
92a1f12d
JR		 4012 goto out;
4013 }
4014 case KVM_GET_TSC_KHZ: {
cc578287 4015 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4016 goto out;
4017 }
1c0b28c2
EM		 4018 case KVM_KVMCLOCK_CTRL: {
4019 r = kvm_set_guest_paused(vcpu);
4020 goto out;
4021 }
5c919412
AS		 4022 case KVM_ENABLE_CAP: {
4023 struct kvm_enable_cap cap;
4024
4025 r = -EFAULT;
4026 if (copy_from_user(&cap, argp, sizeof(cap)))
4027 goto out;
4028 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4029 break;
4030 }
8fcc4b59
JM		 4031 case KVM_GET_NESTED_STATE: {
4032 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4033 u32 user_data_size;
4034
4035 r = -EINVAL;
4036 if (!kvm_x86_ops->get_nested_state)
4037 break;
4038
4039 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4040 r = -EFAULT;
8fcc4b59 4041 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4042 break;
8fcc4b59
JM		 4043
4044 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4045 user_data_size);
4046 if (r < 0)
26b471c7 4047 break;
8fcc4b59
JM		 4048
4049 if (r > user_data_size) {
4050 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4051 r = -EFAULT;
4052 else
4053 r = -E2BIG;
4054 break;
8fcc4b59 4055 }
26b471c7 4056
8fcc4b59
JM		 4057 r = 0;
4058 break;
4059 }
4060 case KVM_SET_NESTED_STATE: {
4061 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4062 struct kvm_nested_state kvm_state;
4063
4064 r = -EINVAL;
4065 if (!kvm_x86_ops->set_nested_state)
4066 break;
4067
26b471c7 4068 r = -EFAULT;
8fcc4b59 4069 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4070 break;
8fcc4b59 4071
26b471c7 4072 r = -EINVAL;
8fcc4b59 4073 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4074 break;
8fcc4b59
JM		 4075
4076 if (kvm_state.flags &
8cab6507
VK		 4077 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4078 | KVM_STATE_NESTED_EVMCS))
26b471c7 4079 break;
8fcc4b59
JM		 4080
4081 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4082 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4083 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4084 break;
8fcc4b59
JM		 4085
4086 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4087 break;
4088 }
313a3dc7
CO		 4089 default:
4090 r = -EINVAL;
4091 }
4092out:
d1ac91d8 4093 kfree(u.buffer);
9b062471
CD		 4094out_nofree:
4095 vcpu_put(vcpu);
313a3dc7
CO		 4096 return r;
4097}
4098
1499fa80 4099vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4100{
4101 return VM_FAULT_SIGBUS;
4102}
4103
1fe779f8
CO		 4104static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4105{
4106 int ret;
4107
4108 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4109 return -EINVAL;
1fe779f8
CO		 4110 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4111 return ret;
4112}
4113
b927a3ce
SY		 4114static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4115 u64 ident_addr)
4116{
2ac52ab8 4117 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4118}
4119
1fe779f8
CO		 4120static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4121 u32 kvm_nr_mmu_pages)
4122{
4123 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4124 return -EINVAL;
4125
79fac95e 4126 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4127
4128 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4129 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4130
79fac95e 4131 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4132 return 0;
4133}
4134
4135static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4136{
39de71ec 4137 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4138}
4139
1fe779f8
CO		 4140static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4141{
90bca052 4142 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4143 int r;
4144
4145 r = 0;
4146 switch (chip->chip_id) {
4147 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4148 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4149 sizeof(struct kvm_pic_state));
4150 break;
4151 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4152 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4153 sizeof(struct kvm_pic_state));
4154 break;
4155 case KVM_IRQCHIP_IOAPIC:
33392b49 4156 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4157 break;
4158 default:
4159 r = -EINVAL;
4160 break;
4161 }
4162 return r;
4163}
4164
4165static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4166{
90bca052 4167 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4168 int r;
4169
4170 r = 0;
4171 switch (chip->chip_id) {
4172 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4173 spin_lock(&pic->lock);
4174 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4175 sizeof(struct kvm_pic_state));
90bca052 4176 spin_unlock(&pic->lock);
1fe779f8
CO		 4177 break;
4178 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4179 spin_lock(&pic->lock);
4180 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4181 sizeof(struct kvm_pic_state));
90bca052 4182 spin_unlock(&pic->lock);
1fe779f8
CO		 4183 break;
4184 case KVM_IRQCHIP_IOAPIC:
33392b49 4185 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4186 break;
4187 default:
4188 r = -EINVAL;
4189 break;
4190 }
90bca052 4191 kvm_pic_update_irq(pic);
1fe779f8
CO		 4192 return r;
4193}
4194
e0f63cb9
SY		 4195static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4196{
34f3941c
RK		 4197 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4198
4199 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4200
4201 mutex_lock(&kps->lock);
4202 memcpy(ps, &kps->channels, sizeof(*ps));
4203 mutex_unlock(&kps->lock);
2da29bcc 4204 return 0;
e0f63cb9
SY		 4205}
4206
4207static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4208{
0185604c 4209 int i;
09edea72
RK		 4210 struct kvm_pit *pit = kvm->arch.vpit;
4211
4212 mutex_lock(&pit->pit_state.lock);
34f3941c 4213 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4214 for (i = 0; i < 3; i++)
09edea72
RK		 4215 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4216 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4217 return 0;
e9f42757
BK		 4218}
4219
4220static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4221{
e9f42757
BK		 4222 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4223 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4224 sizeof(ps->channels));
4225 ps->flags = kvm->arch.vpit->pit_state.flags;
4226 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4227 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4228 return 0;
e9f42757
BK		 4229}
4230
4231static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4232{
2da29bcc 4233 int start = 0;
0185604c 4234 int i;
e9f42757 4235 u32 prev_legacy, cur_legacy;
09edea72
RK		 4236 struct kvm_pit *pit = kvm->arch.vpit;
4237
4238 mutex_lock(&pit->pit_state.lock);
4239 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4240 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4241 if (!prev_legacy && cur_legacy)
4242 start = 1;
09edea72
RK		 4243 memcpy(&pit->pit_state.channels, &ps->channels,
4244 sizeof(pit->pit_state.channels));
4245 pit->pit_state.flags = ps->flags;
0185604c 4246 for (i = 0; i < 3; i++)
09edea72 4247 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4248 start && i == 0);
09edea72 4249 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4250 return 0;
e0f63cb9
SY		 4251}
4252
52d939a0
MT		 4253static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4254 struct kvm_reinject_control *control)
4255{
71474e2f
RK		 4256 struct kvm_pit *pit = kvm->arch.vpit;
4257
4258 if (!pit)
52d939a0 4259 return -ENXIO;
b39c90b6 4260
71474e2f
RK		 4261 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4262 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4263 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4264 */
4265 mutex_lock(&pit->pit_state.lock);
4266 kvm_pit_set_reinject(pit, control->pit_reinject);
4267 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4268
52d939a0
MT		 4269 return 0;
4270}
4271
95d4c16c 4272/**
60c34612
TY		 4273 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4274 * @kvm: kvm instance
4275 * @log: slot id and address to which we copy the log
95d4c16c 4276 *
e108ff2f
PB		 4277 * Steps 1-4 below provide general overview of dirty page logging. See
4278 * kvm_get_dirty_log_protect() function description for additional details.
4279 *
4280 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4281 * always flush the TLB (step 4) even if previous step failed and the dirty
4282 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4283 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4284 * writes will be marked dirty for next log read.
95d4c16c 4285 *
60c34612
TY		 4286 * 1. Take a snapshot of the bit and clear it if needed.
4287 * 2. Write protect the corresponding page.
e108ff2f
PB		 4288 * 3. Copy the snapshot to the userspace.
4289 * 4. Flush TLB's if needed.
5bb064dc 4290 */
60c34612 4291int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4292{
60c34612 4293 bool is_dirty = false;
e108ff2f 4294 int r;
5bb064dc 4295
79fac95e 4296 mutex_lock(&kvm->slots_lock);
5bb064dc 4297
88178fd4
KH		 4298 /*
4299 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4300 */
4301 if (kvm_x86_ops->flush_log_dirty)
4302 kvm_x86_ops->flush_log_dirty(kvm);
4303
e108ff2f 4304 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4305
4306 /*
4307 * All the TLBs can be flushed out of mmu lock, see the comments in
4308 * kvm_mmu_slot_remove_write_access().
4309 */
e108ff2f 4310 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4311 if (is_dirty)
4312 kvm_flush_remote_tlbs(kvm);
4313
79fac95e 4314 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4315 return r;
4316}
4317
aa2fbe6d
YZ		 4318int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4319 bool line_status)
23d43cf9
CD		 4320{
4321 if (!irqchip_in_kernel(kvm))
4322 return -ENXIO;
4323
4324 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4325 irq_event->irq, irq_event->level,
4326 line_status);
23d43cf9
CD		 4327 return 0;
4328}
4329
90de4a18
NA		 4330static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4331 struct kvm_enable_cap *cap)
4332{
4333 int r;
4334
4335 if (cap->flags)
4336 return -EINVAL;
4337
4338 switch (cap->cap) {
4339 case KVM_CAP_DISABLE_QUIRKS:
4340 kvm->arch.disabled_quirks = cap->args[0];
4341 r = 0;
4342 break;
49df6397
SR		 4343 case KVM_CAP_SPLIT_IRQCHIP: {
4344 mutex_lock(&kvm->lock);
b053b2ae
SR		 4345 r = -EINVAL;
4346 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4347 goto split_irqchip_unlock;
49df6397
SR		 4348 r = -EEXIST;
4349 if (irqchip_in_kernel(kvm))
4350 goto split_irqchip_unlock;
557abc40 4351 if (kvm->created_vcpus)
49df6397
SR		 4352 goto split_irqchip_unlock;
4353 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4354 if (r)
49df6397
SR		 4355 goto split_irqchip_unlock;
4356 /* Pairs with irqchip_in_kernel. */
4357 smp_wmb();
49776faf 4358 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4359 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4360 r = 0;
4361split_irqchip_unlock:
4362 mutex_unlock(&kvm->lock);
4363 break;
4364 }
37131313
RK		 4365 case KVM_CAP_X2APIC_API:
4366 r = -EINVAL;
4367 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4368 break;
4369
4370 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4371 kvm->arch.x2apic_format = true;
c519265f
RK		 4372 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4373 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4374
4375 r = 0;
4376 break;
4d5422ce
WL		 4377 case KVM_CAP_X86_DISABLE_EXITS:
4378 r = -EINVAL;
4379 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4380 break;
4381
4382 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4383 kvm_can_mwait_in_guest())
4384 kvm->arch.mwait_in_guest = true;
766d3571 4385 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4386 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4387 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4388 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4389 r = 0;
4390 break;
6fbbde9a
DS		 4391 case KVM_CAP_MSR_PLATFORM_INFO:
4392 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4393 r = 0;
4394 break;
90de4a18
NA		 4395 default:
4396 r = -EINVAL;
4397 break;
4398 }
4399 return r;
4400}
4401
1fe779f8
CO		 4402long kvm_arch_vm_ioctl(struct file *filp,
4403 unsigned int ioctl, unsigned long arg)
4404{
4405 struct kvm *kvm = filp->private_data;
4406 void __user *argp = (void __user *)arg;
367e1319 4407 int r = -ENOTTY;
f0d66275
DH		 4408 /*
4409 * This union makes it completely explicit to gcc-3.x
4410 * that these two variables' stack usage should be
4411 * combined, not added together.
4412 */
4413 union {
4414 struct kvm_pit_state ps;
e9f42757 4415 struct kvm_pit_state2 ps2;
c5ff41ce 4416 struct kvm_pit_config pit_config;
f0d66275 4417 } u;
1fe779f8
CO		 4418
4419 switch (ioctl) {
4420 case KVM_SET_TSS_ADDR:
4421 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4422 break;
b927a3ce
SY		 4423 case KVM_SET_IDENTITY_MAP_ADDR: {
4424 u64 ident_addr;
4425
1af1ac91
DH		 4426 mutex_lock(&kvm->lock);
4427 r = -EINVAL;
4428 if (kvm->created_vcpus)
4429 goto set_identity_unlock;
b927a3ce
SY		 4430 r = -EFAULT;
4431 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4432 goto set_identity_unlock;
b927a3ce 4433 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4434set_identity_unlock:
4435 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4436 break;
4437 }
1fe779f8
CO		 4438 case KVM_SET_NR_MMU_PAGES:
4439 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4440 break;
4441 case KVM_GET_NR_MMU_PAGES:
4442 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4443 break;
3ddea128 4444 case KVM_CREATE_IRQCHIP: {
3ddea128 4445 mutex_lock(&kvm->lock);
09941366 4446
3ddea128 4447 r = -EEXIST;
35e6eaa3 4448 if (irqchip_in_kernel(kvm))
3ddea128 4449 goto create_irqchip_unlock;
09941366 4450
3e515705 4451 r = -EINVAL;
557abc40 4452 if (kvm->created_vcpus)
3e515705 4453 goto create_irqchip_unlock;
09941366
RK		 4454
4455 r = kvm_pic_init(kvm);
4456 if (r)
3ddea128 4457 goto create_irqchip_unlock;
09941366
RK		 4458
4459 r = kvm_ioapic_init(kvm);
4460 if (r) {
09941366 4461 kvm_pic_destroy(kvm);
3ddea128 4462 goto create_irqchip_unlock;
09941366
RK		 4463 }
4464
399ec807
AK		 4465 r = kvm_setup_default_irq_routing(kvm);
4466 if (r) {
72bb2fcd 4467 kvm_ioapic_destroy(kvm);
09941366 4468 kvm_pic_destroy(kvm);
71ba994c 4469 goto create_irqchip_unlock;
399ec807 4470 }
49776faf 4471 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4472 smp_wmb();
49776faf 4473 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4474 create_irqchip_unlock:
4475 mutex_unlock(&kvm->lock);
1fe779f8 4476 break;
3ddea128 4477 }
7837699f 4478 case KVM_CREATE_PIT:
c5ff41ce
JK		 4479 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4480 goto create_pit;
4481 case KVM_CREATE_PIT2:
4482 r = -EFAULT;
4483 if (copy_from_user(&u.pit_config, argp,
4484 sizeof(struct kvm_pit_config)))
4485 goto out;
4486 create_pit:
250715a6 4487 mutex_lock(&kvm->lock);
269e05e4
AK		 4488 r = -EEXIST;
4489 if (kvm->arch.vpit)
4490 goto create_pit_unlock;
7837699f 4491 r = -ENOMEM;
c5ff41ce 4492 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4493 if (kvm->arch.vpit)
4494 r = 0;
269e05e4 4495 create_pit_unlock:
250715a6 4496 mutex_unlock(&kvm->lock);
7837699f 4497 break;
1fe779f8
CO		 4498 case KVM_GET_IRQCHIP: {
4499 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4500 struct kvm_irqchip *chip;
1fe779f8 4501
ff5c2c03
SL		 4502 chip = memdup_user(argp, sizeof(*chip));
4503 if (IS_ERR(chip)) {
4504 r = PTR_ERR(chip);
1fe779f8 4505 goto out;
ff5c2c03
SL		 4506 }
4507
1fe779f8 4508 r = -ENXIO;
826da321 4509 if (!irqchip_kernel(kvm))
f0d66275
DH		 4510 goto get_irqchip_out;
4511 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4512 if (r)
f0d66275 4513 goto get_irqchip_out;
1fe779f8 4514 r = -EFAULT;
f0d66275
DH		 4515 if (copy_to_user(argp, chip, sizeof *chip))
4516 goto get_irqchip_out;
1fe779f8 4517 r = 0;
f0d66275
DH		 4518 get_irqchip_out:
4519 kfree(chip);
1fe779f8
CO		 4520 break;
4521 }
4522 case KVM_SET_IRQCHIP: {
4523 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4524 struct kvm_irqchip *chip;
1fe779f8 4525
ff5c2c03
SL		 4526 chip = memdup_user(argp, sizeof(*chip));
4527 if (IS_ERR(chip)) {
4528 r = PTR_ERR(chip);
1fe779f8 4529 goto out;
ff5c2c03
SL		 4530 }
4531
1fe779f8 4532 r = -ENXIO;
826da321 4533 if (!irqchip_kernel(kvm))
f0d66275
DH		 4534 goto set_irqchip_out;
4535 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4536 if (r)
f0d66275 4537 goto set_irqchip_out;
1fe779f8 4538 r = 0;
f0d66275
DH		 4539 set_irqchip_out:
4540 kfree(chip);
1fe779f8
CO		 4541 break;
4542 }
e0f63cb9 4543 case KVM_GET_PIT: {
e0f63cb9 4544 r = -EFAULT;
f0d66275 4545 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4546 goto out;
4547 r = -ENXIO;
4548 if (!kvm->arch.vpit)
4549 goto out;
f0d66275 4550 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4551 if (r)
4552 goto out;
4553 r = -EFAULT;
f0d66275 4554 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4555 goto out;
4556 r = 0;
4557 break;
4558 }
4559 case KVM_SET_PIT: {
e0f63cb9 4560 r = -EFAULT;
f0d66275 4561 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4562 goto out;
4563 r = -ENXIO;
4564 if (!kvm->arch.vpit)
4565 goto out;
f0d66275 4566 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4567 break;
4568 }
e9f42757
BK		 4569 case KVM_GET_PIT2: {
4570 r = -ENXIO;
4571 if (!kvm->arch.vpit)
4572 goto out;
4573 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4574 if (r)
4575 goto out;
4576 r = -EFAULT;
4577 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4578 goto out;
4579 r = 0;
4580 break;
4581 }
4582 case KVM_SET_PIT2: {
4583 r = -EFAULT;
4584 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4585 goto out;
4586 r = -ENXIO;
4587 if (!kvm->arch.vpit)
4588 goto out;
4589 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4590 break;
4591 }
52d939a0
MT		 4592 case KVM_REINJECT_CONTROL: {
4593 struct kvm_reinject_control control;
4594 r = -EFAULT;
4595 if (copy_from_user(&control, argp, sizeof(control)))
4596 goto out;
4597 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4598 break;
4599 }
d71ba788
PB		 4600 case KVM_SET_BOOT_CPU_ID:
4601 r = 0;
4602 mutex_lock(&kvm->lock);
557abc40 4603 if (kvm->created_vcpus)
d71ba788
PB		 4604 r = -EBUSY;
4605 else
4606 kvm->arch.bsp_vcpu_id = arg;
4607 mutex_unlock(&kvm->lock);
4608 break;
ffde22ac 4609 case KVM_XEN_HVM_CONFIG: {
51776043 4610 struct kvm_xen_hvm_config xhc;
ffde22ac 4611 r = -EFAULT;
51776043 4612 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4613 goto out;
4614 r = -EINVAL;
51776043 4615 if (xhc.flags)
ffde22ac 4616 goto out;
51776043 4617 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4618 r = 0;
4619 break;
4620 }
afbcf7ab 4621 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4622 struct kvm_clock_data user_ns;
4623 u64 now_ns;
afbcf7ab
GC		 4624
4625 r = -EFAULT;
4626 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4627 goto out;
4628
4629 r = -EINVAL;
4630 if (user_ns.flags)
4631 goto out;
4632
4633 r = 0;
0bc48bea
RK		 4634 /*
4635 * TODO: userspace has to take care of races with VCPU_RUN, so
4636 * kvm_gen_update_masterclock() can be cut down to locked
4637 * pvclock_update_vm_gtod_copy().
4638 */
4639 kvm_gen_update_masterclock(kvm);
e891a32e 4640 now_ns = get_kvmclock_ns(kvm);
108b249c 4641 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4642 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4643 break;
4644 }
4645 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4646 struct kvm_clock_data user_ns;
4647 u64 now_ns;
4648
e891a32e 4649 now_ns = get_kvmclock_ns(kvm);
108b249c 4650 user_ns.clock = now_ns;
e3fd9a93 4651 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4652 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4653
4654 r = -EFAULT;
4655 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4656 goto out;
4657 r = 0;
4658 break;
4659 }
90de4a18
NA		 4660 case KVM_ENABLE_CAP: {
4661 struct kvm_enable_cap cap;
afbcf7ab 4662
90de4a18
NA		 4663 r = -EFAULT;
4664 if (copy_from_user(&cap, argp, sizeof(cap)))
4665 goto out;
4666 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4667 break;
4668 }
5acc5c06
BS		 4669 case KVM_MEMORY_ENCRYPT_OP: {
4670 r = -ENOTTY;
4671 if (kvm_x86_ops->mem_enc_op)
4672 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4673 break;
4674 }
69eaedee
BS		 4675 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4676 struct kvm_enc_region region;
4677
4678 r = -EFAULT;
4679 if (copy_from_user(&region, argp, sizeof(region)))
4680 goto out;
4681
4682 r = -ENOTTY;
4683 if (kvm_x86_ops->mem_enc_reg_region)
4684 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4685 break;
4686 }
4687 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4688 struct kvm_enc_region region;
4689
4690 r = -EFAULT;
4691 if (copy_from_user(&region, argp, sizeof(region)))
4692 goto out;
4693
4694 r = -ENOTTY;
4695 if (kvm_x86_ops->mem_enc_unreg_region)
4696 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4697 break;
4698 }
faeb7833
RK		 4699 case KVM_HYPERV_EVENTFD: {
4700 struct kvm_hyperv_eventfd hvevfd;
4701
4702 r = -EFAULT;
4703 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4704 goto out;
4705 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4706 break;
4707 }
1fe779f8 4708 default:
ad6260da 4709 r = -ENOTTY;
1fe779f8
CO		 4710 }
4711out:
4712 return r;
4713}
4714
a16b043c 4715static void kvm_init_msr_list(void)
043405e1
CO		 4716{
4717 u32 dummy[2];
4718 unsigned i, j;
4719
62ef68bb 4720 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4721 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4722 continue;
93c4adc7
PB		 4723
4724 /*
4725 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4726 * to the guests in some cases.
93c4adc7
PB		 4727 */
4728 switch (msrs_to_save[i]) {
4729 case MSR_IA32_BNDCFGS:
503234b3 4730 if (!kvm_mpx_supported())
93c4adc7
PB		 4731 continue;
4732 break;
9dbe6cf9
PB		 4733 case MSR_TSC_AUX:
4734 if (!kvm_x86_ops->rdtscp_supported())
4735 continue;
4736 break;
93c4adc7
PB		 4737 default:
4738 break;
4739 }
4740
043405e1
CO		 4741 if (j < i)
4742 msrs_to_save[j] = msrs_to_save[i];
4743 j++;
4744 }
4745 num_msrs_to_save = j;
62ef68bb
PB		 4746
4747 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4748 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4749 continue;
62ef68bb
PB		 4750
4751 if (j < i)
4752 emulated_msrs[j] = emulated_msrs[i];
4753 j++;
4754 }
4755 num_emulated_msrs = j;
801e459a
TL		 4756
4757 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4758 struct kvm_msr_entry msr;
4759
4760 msr.index = msr_based_features[i];
66421c1e 4761 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4762 continue;
4763
4764 if (j < i)
4765 msr_based_features[j] = msr_based_features[i];
4766 j++;
4767 }
4768 num_msr_based_features = j;
043405e1
CO		 4769}
4770
bda9020e
MT		 4771static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4772 const void *v)
bbd9b64e 4773{
70252a10
AK		 4774 int handled = 0;
4775 int n;
4776
4777 do {
4778 n = min(len, 8);
bce87cce 4779 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4780 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4781 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4782 break;
4783 handled += n;
4784 addr += n;
4785 len -= n;
4786 v += n;
4787 } while (len);
bbd9b64e 4788
70252a10 4789 return handled;
bbd9b64e
CO		 4790}
4791
bda9020e 4792static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4793{
70252a10
AK		 4794 int handled = 0;
4795 int n;
4796
4797 do {
4798 n = min(len, 8);
bce87cce 4799 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4800 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4801 addr, n, v))
4802 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4803 break;
e39d200f 4804 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4805 handled += n;
4806 addr += n;
4807 len -= n;
4808 v += n;
4809 } while (len);
bbd9b64e 4810
70252a10 4811 return handled;
bbd9b64e
CO		 4812}
4813
2dafc6c2
GN		 4814static void kvm_set_segment(struct kvm_vcpu *vcpu,
4815 struct kvm_segment *var, int seg)
4816{
4817 kvm_x86_ops->set_segment(vcpu, var, seg);
4818}
4819
4820void kvm_get_segment(struct kvm_vcpu *vcpu,
4821 struct kvm_segment *var, int seg)
4822{
4823 kvm_x86_ops->get_segment(vcpu, var, seg);
4824}
4825
54987b7a
PB		 4826gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4827 struct x86_exception *exception)
02f59dc9
JR		 4828{
4829 gpa_t t_gpa;
02f59dc9
JR		 4830
4831 BUG_ON(!mmu_is_nested(vcpu));
4832
4833 /* NPT walks are always user-walks */
4834 access |= PFERR_USER_MASK;
44dd3ffa 4835 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4836
4837 return t_gpa;
4838}
4839
ab9ae313
AK		 4840gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4841 struct x86_exception *exception)
1871c602
GN		 4842{
4843 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4844 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4845}
4846
ab9ae313
AK		 4847 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4848 struct x86_exception *exception)
1871c602
GN		 4849{
4850 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4851 access |= PFERR_FETCH_MASK;
ab9ae313 4852 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4853}
4854
ab9ae313
AK		 4855gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4856 struct x86_exception *exception)
1871c602
GN		 4857{
4858 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4859 access |= PFERR_WRITE_MASK;
ab9ae313 4860 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4861}
4862
4863/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4864gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4865 struct x86_exception *exception)
1871c602 4866{
ab9ae313 4867 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4868}
4869
4870static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4871 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4872 struct x86_exception *exception)
bbd9b64e
CO		 4873{
4874 void *data = val;
10589a46 4875 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4876
4877 while (bytes) {
14dfe855 4878 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4879 exception);
bbd9b64e 4880 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4881 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4882 int ret;
4883
bcc55cba 4884 if (gpa == UNMAPPED_GVA)
ab9ae313 4885 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4886 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4887 offset, toread);
10589a46 4888 if (ret < 0) {
c3cd7ffa 4889 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4890 goto out;
4891 }
bbd9b64e 4892
77c2002e
IE		 4893 bytes -= toread;
4894 data += toread;
4895 addr += toread;
bbd9b64e 4896 }
10589a46 4897out:
10589a46 4898 return r;
bbd9b64e 4899}
77c2002e 4900
1871c602 4901/* used for instruction fetching */
0f65dd70
AK		 4902static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4903 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4904 struct x86_exception *exception)
1871c602 4905{
0f65dd70 4906 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4907 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4908 unsigned offset;
4909 int ret;
0f65dd70 4910
44583cba
PB		 4911 /* Inline kvm_read_guest_virt_helper for speed. */
4912 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4913 exception);
4914 if (unlikely(gpa == UNMAPPED_GVA))
4915 return X86EMUL_PROPAGATE_FAULT;
4916
4917 offset = addr & (PAGE_SIZE-1);
4918 if (WARN_ON(offset + bytes > PAGE_SIZE))
4919 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4920 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4921 offset, bytes);
44583cba
PB		 4922 if (unlikely(ret < 0))
4923 return X86EMUL_IO_NEEDED;
4924
4925 return X86EMUL_CONTINUE;
1871c602
GN		 4926}
4927
ce14e868 4928int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 4929 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4930 struct x86_exception *exception)
1871c602
GN		 4931{
4932 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4933
1871c602 4934 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4935 exception);
1871c602 4936}
064aea77 4937EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4938
ce14e868
PB		 4939static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
4940 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 4941 struct x86_exception *exception, bool system)
1871c602 4942{
0f65dd70 4943 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 4944 u32 access = 0;
4945
4946 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4947 access |= PFERR_USER_MASK;
4948
4949 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 4950}
4951
7a036a6f
RK		 4952static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4953 unsigned long addr, void *val, unsigned int bytes)
4954{
4955 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4956 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4957
4958 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4959}
4960
ce14e868
PB		 4961static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4962 struct kvm_vcpu *vcpu, u32 access,
4963 struct x86_exception *exception)
77c2002e
IE		 4964{
4965 void *data = val;
4966 int r = X86EMUL_CONTINUE;
4967
4968 while (bytes) {
14dfe855 4969 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 4970 access,
ab9ae313 4971 exception);
77c2002e
IE		 4972 unsigned offset = addr & (PAGE_SIZE-1);
4973 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4974 int ret;
4975
bcc55cba 4976 if (gpa == UNMAPPED_GVA)
ab9ae313 4977 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4978 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4979 if (ret < 0) {
c3cd7ffa 4980 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4981 goto out;
4982 }
4983
4984 bytes -= towrite;
4985 data += towrite;
4986 addr += towrite;
4987 }
4988out:
4989 return r;
4990}
ce14e868
PB		 4991
4992static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 4993 unsigned int bytes, struct x86_exception *exception,
4994 bool system)
ce14e868
PB		 4995{
4996 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 4997 u32 access = PFERR_WRITE_MASK;
4998
4999 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5000 access |= PFERR_USER_MASK;
ce14e868
PB		 5001
5002 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5003 access, exception);
ce14e868
PB		 5004}
5005
5006int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5007 unsigned int bytes, struct x86_exception *exception)
5008{
c595ceee
PB		 5009 /* kvm_write_guest_virt_system can pull in tons of pages. */
5010 vcpu->arch.l1tf_flush_l1d = true;
5011
ce14e868
PB		 5012 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5013 PFERR_WRITE_MASK, exception);
5014}
6a4d7550 5015EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5016
082d06ed
WL		 5017int handle_ud(struct kvm_vcpu *vcpu)
5018{
6c86eedc 5019 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5020 enum emulation_result er;
6c86eedc
WL		 5021 char sig[5]; /* ud2; .ascii "kvm" */
5022 struct x86_exception e;
5023
5024 if (force_emulation_prefix &&
3c9fa24c
PB		 5025 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5026 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5027 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5028 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5029 emul_type = 0;
5030 }
082d06ed 5031
0ce97a2b 5032 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5033 if (er == EMULATE_USER_EXIT)
5034 return 0;
5035 if (er != EMULATE_DONE)
5036 kvm_queue_exception(vcpu, UD_VECTOR);
5037 return 1;
5038}
5039EXPORT_SYMBOL_GPL(handle_ud);
5040
0f89b207
TL		 5041static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5042 gpa_t gpa, bool write)
5043{
5044 /* For APIC access vmexit */
5045 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5046 return 1;
5047
5048 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5049 trace_vcpu_match_mmio(gva, gpa, write, true);
5050 return 1;
5051 }
5052
5053 return 0;
5054}
5055
af7cc7d1
XG		 5056static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5057 gpa_t *gpa, struct x86_exception *exception,
5058 bool write)
5059{
97d64b78
AK		 5060 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5061 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5062
be94f6b7
HH		 5063 /*
5064 * currently PKRU is only applied to ept enabled guest so
5065 * there is no pkey in EPT page table for L1 guest or EPT
5066 * shadow page table for L2 guest.
5067 */
97d64b78 5068 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5069 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5070 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5071 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5072 (gva & (PAGE_SIZE - 1));
4f022648 5073 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5074 return 1;
5075 }
5076
af7cc7d1
XG		 5077 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5078
5079 if (*gpa == UNMAPPED_GVA)
5080 return -1;
5081
0f89b207 5082 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5083}
5084
3200f405 5085int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5086 const void *val, int bytes)
bbd9b64e
CO		 5087{
5088 int ret;
5089
54bf36aa 5090 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5091 if (ret < 0)
bbd9b64e 5092 return 0;
0eb05bf2 5093 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5094 return 1;
5095}
5096
77d197b2
XG		 5097struct read_write_emulator_ops {
5098 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5099 int bytes);
5100 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5101 void *val, int bytes);
5102 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5103 int bytes, void *val);
5104 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5105 void *val, int bytes);
5106 bool write;
5107};
5108
5109static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5110{
5111 if (vcpu->mmio_read_completed) {
77d197b2 5112 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5113 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5114 vcpu->mmio_read_completed = 0;
5115 return 1;
5116 }
5117
5118 return 0;
5119}
5120
5121static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5122 void *val, int bytes)
5123{
54bf36aa 5124 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5125}
5126
5127static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5128 void *val, int bytes)
5129{
5130 return emulator_write_phys(vcpu, gpa, val, bytes);
5131}
5132
5133static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5134{
e39d200f 5135 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5136 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5137}
5138
5139static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5140 void *val, int bytes)
5141{
e39d200f 5142 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5143 return X86EMUL_IO_NEEDED;
5144}
5145
5146static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5147 void *val, int bytes)
5148{
f78146b0
AK		 5149 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5150
87da7e66 5151 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5152 return X86EMUL_CONTINUE;
5153}
5154
0fbe9b0b 5155static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5156 .read_write_prepare = read_prepare,
5157 .read_write_emulate = read_emulate,
5158 .read_write_mmio = vcpu_mmio_read,
5159 .read_write_exit_mmio = read_exit_mmio,
5160};
5161
0fbe9b0b 5162static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5163 .read_write_emulate = write_emulate,
5164 .read_write_mmio = write_mmio,
5165 .read_write_exit_mmio = write_exit_mmio,
5166 .write = true,
5167};
5168
22388a3c
XG		 5169static int emulator_read_write_onepage(unsigned long addr, void *val,
5170 unsigned int bytes,
5171 struct x86_exception *exception,
5172 struct kvm_vcpu *vcpu,
0fbe9b0b 5173 const struct read_write_emulator_ops *ops)
bbd9b64e 5174{
af7cc7d1
XG		 5175 gpa_t gpa;
5176 int handled, ret;
22388a3c 5177 bool write = ops->write;
f78146b0 5178 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5179 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5180
5181 /*
5182 * If the exit was due to a NPF we may already have a GPA.
5183 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5184 * Note, this cannot be used on string operations since string
5185 * operation using rep will only have the initial GPA from the NPF
5186 * occurred.
5187 */
5188 if (vcpu->arch.gpa_available &&
5189 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5190 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5191 gpa = vcpu->arch.gpa_val;
5192 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5193 } else {
5194 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5195 if (ret < 0)
5196 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5197 }
10589a46 5198
618232e2 5199 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5200 return X86EMUL_CONTINUE;
5201
bbd9b64e
CO		 5202 /*
5203 * Is this MMIO handled locally?
5204 */
22388a3c 5205 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5206 if (handled == bytes)
bbd9b64e 5207 return X86EMUL_CONTINUE;
bbd9b64e 5208
70252a10
AK		 5209 gpa += handled;
5210 bytes -= handled;
5211 val += handled;
5212
87da7e66
XG		 5213 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5214 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5215 frag->gpa = gpa;
5216 frag->data = val;
5217 frag->len = bytes;
f78146b0 5218 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5219}
5220
52eb5a6d
XL		 5221static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5222 unsigned long addr,
22388a3c
XG		 5223 void *val, unsigned int bytes,
5224 struct x86_exception *exception,
0fbe9b0b 5225 const struct read_write_emulator_ops *ops)
bbd9b64e 5226{
0f65dd70 5227 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5228 gpa_t gpa;
5229 int rc;
5230
5231 if (ops->read_write_prepare &&
5232 ops->read_write_prepare(vcpu, val, bytes))
5233 return X86EMUL_CONTINUE;
5234
5235 vcpu->mmio_nr_fragments = 0;
0f65dd70 5236
bbd9b64e
CO		 5237 /* Crossing a page boundary? */
5238 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5239 int now;
bbd9b64e
CO		 5240
5241 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5242 rc = emulator_read_write_onepage(addr, val, now, exception,
5243 vcpu, ops);
5244
bbd9b64e
CO		 5245 if (rc != X86EMUL_CONTINUE)
5246 return rc;
5247 addr += now;
bac15531
NA		 5248 if (ctxt->mode != X86EMUL_MODE_PROT64)
5249 addr = (u32)addr;
bbd9b64e
CO		 5250 val += now;
5251 bytes -= now;
5252 }
22388a3c 5253
f78146b0
AK		 5254 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5255 vcpu, ops);
5256 if (rc != X86EMUL_CONTINUE)
5257 return rc;
5258
5259 if (!vcpu->mmio_nr_fragments)
5260 return rc;
5261
5262 gpa = vcpu->mmio_fragments[0].gpa;
5263
5264 vcpu->mmio_needed = 1;
5265 vcpu->mmio_cur_fragment = 0;
5266
87da7e66 5267 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5268 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5269 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5270 vcpu->run->mmio.phys_addr = gpa;
5271
5272 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5273}
5274
5275static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5276 unsigned long addr,
5277 void *val,
5278 unsigned int bytes,
5279 struct x86_exception *exception)
5280{
5281 return emulator_read_write(ctxt, addr, val, bytes,
5282 exception, &read_emultor);
5283}
5284
52eb5a6d 5285static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5286 unsigned long addr,
5287 const void *val,
5288 unsigned int bytes,
5289 struct x86_exception *exception)
5290{
5291 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5292 exception, &write_emultor);
bbd9b64e 5293}
bbd9b64e 5294
daea3e73
AK		 5295#define CMPXCHG_TYPE(t, ptr, old, new) \
5296 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5297
5298#ifdef CONFIG_X86_64
5299# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5300#else
5301# define CMPXCHG64(ptr, old, new) \
9749a6c0 5302 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5303#endif
5304
0f65dd70
AK		 5305static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5306 unsigned long addr,
bbd9b64e
CO		 5307 const void *old,
5308 const void *new,
5309 unsigned int bytes,
0f65dd70 5310 struct x86_exception *exception)
bbd9b64e 5311{
0f65dd70 5312 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5313 gpa_t gpa;
5314 struct page *page;
5315 char *kaddr;
5316 bool exchanged;
2bacc55c 5317
daea3e73
AK		 5318 /* guests cmpxchg8b have to be emulated atomically */
5319 if (bytes > 8 || (bytes & (bytes - 1)))
5320 goto emul_write;
10589a46 5321
daea3e73 5322 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5323
daea3e73
AK		 5324 if (gpa == UNMAPPED_GVA ||
5325 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5326 goto emul_write;
2bacc55c 5327
daea3e73
AK		 5328 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5329 goto emul_write;
72dc67a6 5330
54bf36aa 5331 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5332 if (is_error_page(page))
c19b8bd6 5333 goto emul_write;
72dc67a6 5334
8fd75e12 5335 kaddr = kmap_atomic(page);
daea3e73
AK		 5336 kaddr += offset_in_page(gpa);
5337 switch (bytes) {
5338 case 1:
5339 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5340 break;
5341 case 2:
5342 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5343 break;
5344 case 4:
5345 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5346 break;
5347 case 8:
5348 exchanged = CMPXCHG64(kaddr, old, new);
5349 break;
5350 default:
5351 BUG();
2bacc55c 5352 }
8fd75e12 5353 kunmap_atomic(kaddr);
daea3e73
AK		 5354 kvm_release_page_dirty(page);
5355
5356 if (!exchanged)
5357 return X86EMUL_CMPXCHG_FAILED;
5358
54bf36aa 5359 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5360 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5361
5362 return X86EMUL_CONTINUE;
4a5f48f6 5363
3200f405 5364emul_write:
daea3e73 5365 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5366
0f65dd70 5367 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5368}
5369
cf8f70bf
GN		 5370static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5371{
cbfc6c91 5372 int r = 0, i;
cf8f70bf 5373
cbfc6c91
WL		 5374 for (i = 0; i < vcpu->arch.pio.count; i++) {
5375 if (vcpu->arch.pio.in)
5376 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5377 vcpu->arch.pio.size, pd);
5378 else
5379 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5380 vcpu->arch.pio.port, vcpu->arch.pio.size,
5381 pd);
5382 if (r)
5383 break;
5384 pd += vcpu->arch.pio.size;
5385 }
cf8f70bf
GN		 5386 return r;
5387}
5388
6f6fbe98
XG		 5389static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5390 unsigned short port, void *val,
5391 unsigned int count, bool in)
cf8f70bf 5392{
cf8f70bf 5393 vcpu->arch.pio.port = port;
6f6fbe98 5394 vcpu->arch.pio.in = in;
7972995b 5395 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5396 vcpu->arch.pio.size = size;
5397
5398 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5399 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5400 return 1;
5401 }
5402
5403 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5404 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5405 vcpu->run->io.size = size;
5406 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5407 vcpu->run->io.count = count;
5408 vcpu->run->io.port = port;
5409
5410 return 0;
5411}
5412
6f6fbe98
XG		 5413static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5414 int size, unsigned short port, void *val,
5415 unsigned int count)
cf8f70bf 5416{
ca1d4a9e 5417 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5418 int ret;
ca1d4a9e 5419
6f6fbe98
XG		 5420 if (vcpu->arch.pio.count)
5421 goto data_avail;
cf8f70bf 5422
cbfc6c91
WL		 5423 memset(vcpu->arch.pio_data, 0, size * count);
5424
6f6fbe98
XG		 5425 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5426 if (ret) {
5427data_avail:
5428 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5429 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5430 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5431 return 1;
5432 }
5433
cf8f70bf
GN		 5434 return 0;
5435}
5436
6f6fbe98
XG		 5437static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5438 int size, unsigned short port,
5439 const void *val, unsigned int count)
5440{
5441 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5442
5443 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5444 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5445 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5446}
5447
bbd9b64e
CO		 5448static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5449{
5450 return kvm_x86_ops->get_segment_base(vcpu, seg);
5451}
5452
3cb16fe7 5453static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5454{
3cb16fe7 5455 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5456}
5457
ae6a2375 5458static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5459{
5460 if (!need_emulate_wbinvd(vcpu))
5461 return X86EMUL_CONTINUE;
5462
5463 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5464 int cpu = get_cpu();
5465
5466 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5467 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5468 wbinvd_ipi, NULL, 1);
2eec7343 5469 put_cpu();
f5f48ee1 5470 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5471 } else
5472 wbinvd();
f5f48ee1
SY		 5473 return X86EMUL_CONTINUE;
5474}
5cb56059
JS		 5475
5476int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5477{
6affcbed
KH		 5478 kvm_emulate_wbinvd_noskip(vcpu);
5479 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5480}
f5f48ee1
SY		 5481EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5482
5cb56059
JS		 5483
5484
bcaf5cc5
AK		 5485static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5486{
5cb56059 5487 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5488}
5489
52eb5a6d
XL		 5490static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5491 unsigned long *dest)
bbd9b64e 5492{
16f8a6f9 5493 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5494}
5495
52eb5a6d
XL		 5496static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5497 unsigned long value)
bbd9b64e 5498{
338dbc97 5499
717746e3 5500 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5501}
5502
52a46617 5503static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5504{
52a46617 5505 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5506}
5507
717746e3 5508static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5509{
717746e3 5510 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5511 unsigned long value;
5512
5513 switch (cr) {
5514 case 0:
5515 value = kvm_read_cr0(vcpu);
5516 break;
5517 case 2:
5518 value = vcpu->arch.cr2;
5519 break;
5520 case 3:
9f8fe504 5521 value = kvm_read_cr3(vcpu);
52a46617
GN		 5522 break;
5523 case 4:
5524 value = kvm_read_cr4(vcpu);
5525 break;
5526 case 8:
5527 value = kvm_get_cr8(vcpu);
5528 break;
5529 default:
a737f256 5530 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5531 return 0;
5532 }
5533
5534 return value;
5535}
5536
717746e3 5537static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5538{
717746e3 5539 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5540 int res = 0;
5541
52a46617
GN		 5542 switch (cr) {
5543 case 0:
49a9b07e 5544 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5545 break;
5546 case 2:
5547 vcpu->arch.cr2 = val;
5548 break;
5549 case 3:
2390218b 5550 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5551 break;
5552 case 4:
a83b29c6 5553 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5554 break;
5555 case 8:
eea1cff9 5556 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5557 break;
5558 default:
a737f256 5559 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5560 res = -1;
52a46617 5561 }
0f12244f
GN		 5562
5563 return res;
52a46617
GN		 5564}
5565
717746e3 5566static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5567{
717746e3 5568 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5569}
5570
4bff1e86 5571static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5572{
4bff1e86 5573 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5574}
5575
4bff1e86 5576static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5577{
4bff1e86 5578 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5579}
5580
1ac9d0cf
AK		 5581static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5582{
5583 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5584}
5585
5586static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5587{
5588 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5589}
5590
4bff1e86
AK		 5591static unsigned long emulator_get_cached_segment_base(
5592 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5593{
4bff1e86 5594 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5595}
5596
1aa36616
AK		 5597static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5598 struct desc_struct *desc, u32 *base3,
5599 int seg)
2dafc6c2
GN		 5600{
5601 struct kvm_segment var;
5602
4bff1e86 5603 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5604 *selector = var.selector;
2dafc6c2 5605
378a8b09
GN		 5606 if (var.unusable) {
5607 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5608 if (base3)
5609 *base3 = 0;
2dafc6c2 5610 return false;
378a8b09 5611 }
2dafc6c2
GN		 5612
5613 if (var.g)
5614 var.limit >>= 12;
5615 set_desc_limit(desc, var.limit);
5616 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5617#ifdef CONFIG_X86_64
5618 if (base3)
5619 *base3 = var.base >> 32;
5620#endif
2dafc6c2
GN		 5621 desc->type = var.type;
5622 desc->s = var.s;
5623 desc->dpl = var.dpl;
5624 desc->p = var.present;
5625 desc->avl = var.avl;
5626 desc->l = var.l;
5627 desc->d = var.db;
5628 desc->g = var.g;
5629
5630 return true;
5631}
5632
1aa36616
AK		 5633static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5634 struct desc_struct *desc, u32 base3,
5635 int seg)
2dafc6c2 5636{
4bff1e86 5637 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5638 struct kvm_segment var;
5639
1aa36616 5640 var.selector = selector;
2dafc6c2 5641 var.base = get_desc_base(desc);
5601d05b
GN		 5642#ifdef CONFIG_X86_64
5643 var.base |= ((u64)base3) << 32;
5644#endif
2dafc6c2
GN		 5645 var.limit = get_desc_limit(desc);
5646 if (desc->g)
5647 var.limit = (var.limit << 12) | 0xfff;
5648 var.type = desc->type;
2dafc6c2
GN		 5649 var.dpl = desc->dpl;
5650 var.db = desc->d;
5651 var.s = desc->s;
5652 var.l = desc->l;
5653 var.g = desc->g;
5654 var.avl = desc->avl;
5655 var.present = desc->p;
5656 var.unusable = !var.present;
5657 var.padding = 0;
5658
5659 kvm_set_segment(vcpu, &var, seg);
5660 return;
5661}
5662
717746e3
AK		 5663static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5664 u32 msr_index, u64 *pdata)
5665{
609e36d3
PB		 5666 struct msr_data msr;
5667 int r;
5668
5669 msr.index = msr_index;
5670 msr.host_initiated = false;
5671 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5672 if (r)
5673 return r;
5674
5675 *pdata = msr.data;
5676 return 0;
717746e3
AK		 5677}
5678
5679static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5680 u32 msr_index, u64 data)
5681{
8fe8ab46
WA		 5682 struct msr_data msr;
5683
5684 msr.data = data;
5685 msr.index = msr_index;
5686 msr.host_initiated = false;
5687 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5688}
5689
64d60670
PB		 5690static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5691{
5692 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5693
5694 return vcpu->arch.smbase;
5695}
5696
5697static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5698{
5699 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5700
5701 vcpu->arch.smbase = smbase;
5702}
5703
67f4d428
NA		 5704static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5705 u32 pmc)
5706{
c6702c9d 5707 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5708}
5709
222d21aa
AK		 5710static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5711 u32 pmc, u64 *pdata)
5712{
c6702c9d 5713 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5714}
5715
6c3287f7
AK		 5716static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5717{
5718 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5719}
5720
2953538e 5721static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5722 struct x86_instruction_info *info,
c4f035c6
AK		 5723 enum x86_intercept_stage stage)
5724{
2953538e 5725 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5726}
5727
e911eb3b
YZ		 5728static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5729 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5730{
e911eb3b 5731 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5732}
5733
dd856efa
AK		 5734static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5735{
5736 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5737}
5738
5739static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5740{
5741 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5742}
5743
801806d9
NA		 5744static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5745{
5746 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5747}
5748
6ed071f0
LP		 5749static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5750{
5751 return emul_to_vcpu(ctxt)->arch.hflags;
5752}
5753
5754static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5755{
5756 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5757}
5758
0234bf88
LP		 5759static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5760{
5761 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5762}
5763
0225fb50 5764static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5765 .read_gpr = emulator_read_gpr,
5766 .write_gpr = emulator_write_gpr,
ce14e868
PB		 5767 .read_std = emulator_read_std,
5768 .write_std = emulator_write_std,
7a036a6f 5769 .read_phys = kvm_read_guest_phys_system,
1871c602 5770 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5771 .read_emulated = emulator_read_emulated,
5772 .write_emulated = emulator_write_emulated,
5773 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5774 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5775 .pio_in_emulated = emulator_pio_in_emulated,
5776 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5777 .get_segment = emulator_get_segment,
5778 .set_segment = emulator_set_segment,
5951c442 5779 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5780 .get_gdt = emulator_get_gdt,
160ce1f1 5781 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5782 .set_gdt = emulator_set_gdt,
5783 .set_idt = emulator_set_idt,
52a46617
GN		 5784 .get_cr = emulator_get_cr,
5785 .set_cr = emulator_set_cr,
9c537244 5786 .cpl = emulator_get_cpl,
35aa5375
GN		 5787 .get_dr = emulator_get_dr,
5788 .set_dr = emulator_set_dr,
64d60670
PB		 5789 .get_smbase = emulator_get_smbase,
5790 .set_smbase = emulator_set_smbase,
717746e3
AK		 5791 .set_msr = emulator_set_msr,
5792 .get_msr = emulator_get_msr,
67f4d428 5793 .check_pmc = emulator_check_pmc,
222d21aa 5794 .read_pmc = emulator_read_pmc,
6c3287f7 5795 .halt = emulator_halt,
bcaf5cc5 5796 .wbinvd = emulator_wbinvd,
d6aa1000 5797 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5798 .intercept = emulator_intercept,
bdb42f5a 5799 .get_cpuid = emulator_get_cpuid,
801806d9 5800 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5801 .get_hflags = emulator_get_hflags,
5802 .set_hflags = emulator_set_hflags,
0234bf88 5803 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5804};
5805
95cb2295
GN		 5806static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5807{
37ccdcbe 5808 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5809 /*
5810 * an sti; sti; sequence only disable interrupts for the first
5811 * instruction. So, if the last instruction, be it emulated or
5812 * not, left the system with the INT_STI flag enabled, it
5813 * means that the last instruction is an sti. We should not
5814 * leave the flag on in this case. The same goes for mov ss
5815 */
37ccdcbe
PB		 5816 if (int_shadow & mask)
5817 mask = 0;
6addfc42 5818 if (unlikely(int_shadow || mask)) {
95cb2295 5819 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5820 if (!mask)
5821 kvm_make_request(KVM_REQ_EVENT, vcpu);
5822 }
95cb2295
GN		 5823}
5824
ef54bcfe 5825static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5826{
5827 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5828 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5829 return kvm_propagate_fault(vcpu, &ctxt->exception);
5830
5831 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5832 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5833 ctxt->exception.error_code);
54b8486f 5834 else
da9cb575 5835 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5836 return false;
54b8486f
GN		 5837}
5838
8ec4722d
MG		 5839static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5840{
adf52235 5841 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5842 int cs_db, cs_l;
5843
8ec4722d
MG		 5844 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5845
adf52235 5846 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5847 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5848
adf52235
TY		 5849 ctxt->eip = kvm_rip_read(vcpu);
5850 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5851 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5852 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5853 cs_db ? X86EMUL_MODE_PROT32 :
5854 X86EMUL_MODE_PROT16;
a584539b 5855 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5856 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5857 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5858
dd856efa 5859 init_decode_cache(ctxt);
7ae441ea 5860 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5861}
5862
71f9833b 5863int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5864{
9d74191a 5865 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5866 int ret;
5867
5868 init_emulate_ctxt(vcpu);
5869
9dac77fa
AK		 5870 ctxt->op_bytes = 2;
5871 ctxt->ad_bytes = 2;
5872 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5873 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5874
5875 if (ret != X86EMUL_CONTINUE)
5876 return EMULATE_FAIL;
5877
9dac77fa 5878 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5879 kvm_rip_write(vcpu, ctxt->eip);
5880 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5881
63995653
MG		 5882 return EMULATE_DONE;
5883}
5884EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5885
e2366171 5886static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5887{
fc3a9157
JR		 5888 int r = EMULATE_DONE;
5889
6d77dbfc
GN		 5890 ++vcpu->stat.insn_emulation_fail;
5891 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5892
5893 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5894 return EMULATE_FAIL;
5895
a2b9e6c1 5896 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5897 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5898 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5899 vcpu->run->internal.ndata = 0;
1f4dcb3b 5900 r = EMULATE_USER_EXIT;
fc3a9157 5901 }
e2366171 5902
6d77dbfc 5903 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5904
5905 return r;
6d77dbfc
GN		 5906}
5907
93c05d3e 5908static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5909 bool write_fault_to_shadow_pgtable,
5910 int emulation_type)
a6f177ef 5911{
95b3cf69 5912 gpa_t gpa = cr2;
ba049e93 5913 kvm_pfn_t pfn;
a6f177ef 5914
384bf221 5915 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 5916 return false;
5917
6c3dfeb6
SC		 5918 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
5919 return false;
5920
44dd3ffa 5921 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 5922 /*
5923 * Write permission should be allowed since only
5924 * write access need to be emulated.
5925 */
5926 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5927
95b3cf69
XG		 5928 /*
5929 * If the mapping is invalid in guest, let cpu retry
5930 * it to generate fault.
5931 */
5932 if (gpa == UNMAPPED_GVA)
5933 return true;
5934 }
a6f177ef 5935
8e3d9d06
XG		 5936 /*
5937 * Do not retry the unhandleable instruction if it faults on the
5938 * readonly host memory, otherwise it will goto a infinite loop:
5939 * retry instruction -> write #PF -> emulation fail -> retry
5940 * instruction -> ...
5941 */
5942 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5943
5944 /*
5945 * If the instruction failed on the error pfn, it can not be fixed,
5946 * report the error to userspace.
5947 */
5948 if (is_error_noslot_pfn(pfn))
5949 return false;
5950
5951 kvm_release_pfn_clean(pfn);
5952
5953 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 5954 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 5955 unsigned int indirect_shadow_pages;
5956
5957 spin_lock(&vcpu->kvm->mmu_lock);
5958 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5959 spin_unlock(&vcpu->kvm->mmu_lock);
5960
5961 if (indirect_shadow_pages)
5962 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5963
a6f177ef 5964 return true;
8e3d9d06 5965 }
a6f177ef 5966
95b3cf69
XG		 5967 /*
5968 * if emulation was due to access to shadowed page table
5969 * and it failed try to unshadow page and re-enter the
5970 * guest to let CPU execute the instruction.
5971 */
5972 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5973
5974 /*
5975 * If the access faults on its page table, it can not
5976 * be fixed by unprotecting shadow page and it should
5977 * be reported to userspace.
5978 */
5979 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5980}
5981
1cb3f3ae
XG		 5982static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5983 unsigned long cr2, int emulation_type)
5984{
5985 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5986 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5987
5988 last_retry_eip = vcpu->arch.last_retry_eip;
5989 last_retry_addr = vcpu->arch.last_retry_addr;
5990
5991 /*
5992 * If the emulation is caused by #PF and it is non-page_table
5993 * writing instruction, it means the VM-EXIT is caused by shadow
5994 * page protected, we can zap the shadow page and retry this
5995 * instruction directly.
5996 *
5997 * Note: if the guest uses a non-page-table modifying instruction
5998 * on the PDE that points to the instruction, then we will unmap
5999 * the instruction and go to an infinite loop. So, we cache the
6000 * last retried eip and the last fault address, if we meet the eip
6001 * and the address again, we can break out of the potential infinite
6002 * loop.
6003 */
6004 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6005
384bf221 6006 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6007 return false;
6008
6c3dfeb6
SC		 6009 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6010 return false;
6011
1cb3f3ae
XG		 6012 if (x86_page_table_writing_insn(ctxt))
6013 return false;
6014
6015 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6016 return false;
6017
6018 vcpu->arch.last_retry_eip = ctxt->eip;
6019 vcpu->arch.last_retry_addr = cr2;
6020
44dd3ffa 6021 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6022 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6023
22368028 6024 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6025
6026 return true;
6027}
6028
716d51ab
GN		 6029static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6030static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6031
64d60670 6032static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6033{
64d60670 6034 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6035 /* This is a good place to trace that we are exiting SMM. */
6036 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6037
c43203ca
PB		 6038 /* Process a latched INIT or SMI, if any. */
6039 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6040 }
699023e2
PB		 6041
6042 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6043}
6044
6045static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
6046{
6047 unsigned changed = vcpu->arch.hflags ^ emul_flags;
6048
a584539b 6049 vcpu->arch.hflags = emul_flags;
64d60670
PB		 6050
6051 if (changed & HF_SMM_MASK)
6052 kvm_smm_changed(vcpu);
a584539b
PB		 6053}
6054
4a1e10d5
PB		 6055static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6056 unsigned long *db)
6057{
6058 u32 dr6 = 0;
6059 int i;
6060 u32 enable, rwlen;
6061
6062 enable = dr7;
6063 rwlen = dr7 >> 16;
6064 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6065 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6066 dr6 |= (1 << i);
6067 return dr6;
6068}
6069
c8401dda 6070static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6071{
6072 struct kvm_run *kvm_run = vcpu->run;
6073
c8401dda
PB		 6074 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6075 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6076 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6077 kvm_run->debug.arch.exception = DB_VECTOR;
6078 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6079 *r = EMULATE_USER_EXIT;
6080 } else {
6081 /*
6082 * "Certain debug exceptions may clear bit 0-3. The
6083 * remaining contents of the DR6 register are never
6084 * cleared by the processor".
6085 */
6086 vcpu->arch.dr6 &= ~15;
6087 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
6088 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 6089 }
6090}
6091
6affcbed
KH		 6092int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6093{
6094 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6095 int r = EMULATE_DONE;
6096
6097 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6098
6099 /*
6100 * rflags is the old, "raw" value of the flags. The new value has
6101 * not been saved yet.
6102 *
6103 * This is correct even for TF set by the guest, because "the
6104 * processor will not generate this exception after the instruction
6105 * that sets the TF flag".
6106 */
6107 if (unlikely(rflags & X86_EFLAGS_TF))
6108 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6109 return r == EMULATE_DONE;
6110}
6111EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6112
4a1e10d5
PB		 6113static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6114{
4a1e10d5
PB		 6115 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6116 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6117 struct kvm_run *kvm_run = vcpu->run;
6118 unsigned long eip = kvm_get_linear_rip(vcpu);
6119 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6120 vcpu->arch.guest_debug_dr7,
6121 vcpu->arch.eff_db);
6122
6123 if (dr6 != 0) {
6f43ed01 6124 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6125 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6126 kvm_run->debug.arch.exception = DB_VECTOR;
6127 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6128 *r = EMULATE_USER_EXIT;
6129 return true;
6130 }
6131 }
6132
4161a569
NA		 6133 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6134 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6135 unsigned long eip = kvm_get_linear_rip(vcpu);
6136 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6137 vcpu->arch.dr7,
6138 vcpu->arch.db);
6139
6140 if (dr6 != 0) {
6141 vcpu->arch.dr6 &= ~15;
6f43ed01 6142 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6143 kvm_queue_exception(vcpu, DB_VECTOR);
6144 *r = EMULATE_DONE;
6145 return true;
6146 }
6147 }
6148
6149 return false;
6150}
6151
04789b66
LA		 6152static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6153{
2d7921c4
AM		 6154 switch (ctxt->opcode_len) {
6155 case 1:
6156 switch (ctxt->b) {
6157 case 0xe4: /* IN */
6158 case 0xe5:
6159 case 0xec:
6160 case 0xed:
6161 case 0xe6: /* OUT */
6162 case 0xe7:
6163 case 0xee:
6164 case 0xef:
6165 case 0x6c: /* INS */
6166 case 0x6d:
6167 case 0x6e: /* OUTS */
6168 case 0x6f:
6169 return true;
6170 }
6171 break;
6172 case 2:
6173 switch (ctxt->b) {
6174 case 0x33: /* RDPMC */
6175 return true;
6176 }
6177 break;
04789b66
LA		 6178 }
6179
6180 return false;
6181}
6182
51d8b661
AP		 6183int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6184 unsigned long cr2,
dc25e89e
AP		 6185 int emulation_type,
6186 void *insn,
6187 int insn_len)
bbd9b64e 6188{
95cb2295 6189 int r;
9d74191a 6190 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6191 bool writeback = true;
93c05d3e 6192 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6193
c595ceee
PB		 6194 vcpu->arch.l1tf_flush_l1d = true;
6195
93c05d3e
XG		 6196 /*
6197 * Clear write_fault_to_shadow_pgtable here to ensure it is
6198 * never reused.
6199 */
6200 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6201 kvm_clear_exception_queue(vcpu);
8d7d8102 6202
571008da 6203 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6204 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6205
6206 /*
6207 * We will reenter on the same instruction since
6208 * we do not set complete_userspace_io. This does not
6209 * handle watchpoints yet, those would be handled in
6210 * the emulate_ops.
6211 */
d391f120
VK		 6212 if (!(emulation_type & EMULTYPE_SKIP) &&
6213 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6214 return r;
6215
9d74191a
TY		 6216 ctxt->interruptibility = 0;
6217 ctxt->have_exception = false;
e0ad0b47 6218 ctxt->exception.vector = -1;
9d74191a 6219 ctxt->perm_ok = false;
bbd9b64e 6220
b51e974f 6221 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6222
9d74191a 6223 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6224
e46479f8 6225 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6226 ++vcpu->stat.insn_emulation;
1d2887e2 6227 if (r != EMULATION_OK) {
4005996e
AK		 6228 if (emulation_type & EMULTYPE_TRAP_UD)
6229 return EMULATE_FAIL;
991eebf9
GN		 6230 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6231 emulation_type))
bbd9b64e 6232 return EMULATE_DONE;
6ea6e843
PB		 6233 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6234 return EMULATE_DONE;
6d77dbfc
GN		 6235 if (emulation_type & EMULTYPE_SKIP)
6236 return EMULATE_FAIL;
e2366171 6237 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6238 }
6239 }
6240
04789b66
LA		 6241 if ((emulation_type & EMULTYPE_VMWARE) &&
6242 !is_vmware_backdoor_opcode(ctxt))
6243 return EMULATE_FAIL;
6244
ba8afb6b 6245 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6246 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6247 if (ctxt->eflags & X86_EFLAGS_RF)
6248 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6249 return EMULATE_DONE;
6250 }
6251
1cb3f3ae
XG		 6252 if (retry_instruction(ctxt, cr2, emulation_type))
6253 return EMULATE_DONE;
6254
7ae441ea 6255 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6256 changes registers values during IO operation */
7ae441ea
GN		 6257 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6258 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6259 emulator_invalidate_register_cache(ctxt);
7ae441ea 6260 }
4d2179e1 6261
5cd21917 6262restart:
0f89b207
TL		 6263 /* Save the faulting GPA (cr2) in the address field */
6264 ctxt->exception.address = cr2;
6265
9d74191a 6266 r = x86_emulate_insn(ctxt);
bbd9b64e 6267
775fde86
JR		 6268 if (r == EMULATION_INTERCEPTED)
6269 return EMULATE_DONE;
6270
d2ddd1c4 6271 if (r == EMULATION_FAILED) {
991eebf9
GN		 6272 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6273 emulation_type))
c3cd7ffa
GN		 6274 return EMULATE_DONE;
6275
e2366171 6276 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6277 }
6278
9d74191a 6279 if (ctxt->have_exception) {
d2ddd1c4 6280 r = EMULATE_DONE;
ef54bcfe
PB		 6281 if (inject_emulated_exception(vcpu))
6282 return r;
d2ddd1c4 6283 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6284 if (!vcpu->arch.pio.in) {
6285 /* FIXME: return into emulator if single-stepping. */
3457e419 6286 vcpu->arch.pio.count = 0;
0912c977 6287 } else {
7ae441ea 6288 writeback = false;
716d51ab
GN		 6289 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6290 }
ac0a48c3 6291 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6292 } else if (vcpu->mmio_needed) {
6293 if (!vcpu->mmio_is_write)
6294 writeback = false;
ac0a48c3 6295 r = EMULATE_USER_EXIT;
716d51ab 6296 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6297 } else if (r == EMULATION_RESTART)
5cd21917 6298 goto restart;
d2ddd1c4
GN		 6299 else
6300 r = EMULATE_DONE;
f850e2e6 6301
7ae441ea 6302 if (writeback) {
6addfc42 6303 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6304 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6305 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6306 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6307 if (r == EMULATE_DONE &&
6308 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6309 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6310 if (!ctxt->have_exception ||
6311 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6312 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6313
6314 /*
6315 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6316 * do nothing, and it will be requested again as soon as
6317 * the shadow expires. But we still need to check here,
6318 * because POPF has no interrupt shadow.
6319 */
6320 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6321 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6322 } else
6323 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6324
6325 return r;
de7d789a 6326}
c60658d1
SC		 6327
6328int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6329{
6330 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6331}
6332EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6333
6334int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6335 void *insn, int insn_len)
6336{
6337 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6338}
6339EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6340
dca7f128
SC		 6341static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6342 unsigned short port)
de7d789a 6343{
cf8f70bf 6344 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6345 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6346 size, port, &val, 1);
cf8f70bf 6347 /* do not return to emulator after return from userspace */
7972995b 6348 vcpu->arch.pio.count = 0;
de7d789a
CO		 6349 return ret;
6350}
de7d789a 6351
8370c3d0
TL		 6352static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6353{
6354 unsigned long val;
6355
6356 /* We should only ever be called with arch.pio.count equal to 1 */
6357 BUG_ON(vcpu->arch.pio.count != 1);
6358
6359 /* For size less than 4 we merge, else we zero extend */
6360 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6361 : 0;
6362
6363 /*
6364 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6365 * the copy and tracing
6366 */
6367 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6368 vcpu->arch.pio.port, &val, 1);
6369 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6370
6371 return 1;
6372}
6373
dca7f128
SC		 6374static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6375 unsigned short port)
8370c3d0
TL		 6376{
6377 unsigned long val;
6378 int ret;
6379
6380 /* For size less than 4 we merge, else we zero extend */
6381 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6382
6383 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6384 &val, 1);
6385 if (ret) {
6386 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6387 return ret;
6388 }
6389
6390 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6391
6392 return 0;
6393}
dca7f128
SC		 6394
6395int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6396{
6397 int ret = kvm_skip_emulated_instruction(vcpu);
6398
6399 /*
6400 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6401 * KVM_EXIT_DEBUG here.
6402 */
6403 if (in)
6404 return kvm_fast_pio_in(vcpu, size, port) && ret;
6405 else
6406 return kvm_fast_pio_out(vcpu, size, port) && ret;
6407}
6408EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6409
251a5fd6 6410static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6411{
0a3aee0d 6412 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6413 return 0;
8cfdc000
ZA		 6414}
6415
6416static void tsc_khz_changed(void *data)
c8076604 6417{
8cfdc000
ZA		 6418 struct cpufreq_freqs *freq = data;
6419 unsigned long khz = 0;
6420
6421 if (data)
6422 khz = freq->new;
6423 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6424 khz = cpufreq_quick_get(raw_smp_processor_id());
6425 if (!khz)
6426 khz = tsc_khz;
0a3aee0d 6427 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6428}
6429
5fa4ec9c 6430#ifdef CONFIG_X86_64
0092e434
VK		 6431static void kvm_hyperv_tsc_notifier(void)
6432{
0092e434
VK		 6433 struct kvm *kvm;
6434 struct kvm_vcpu *vcpu;
6435 int cpu;
6436
6437 spin_lock(&kvm_lock);
6438 list_for_each_entry(kvm, &vm_list, vm_list)
6439 kvm_make_mclock_inprogress_request(kvm);
6440
6441 hyperv_stop_tsc_emulation();
6442
6443 /* TSC frequency always matches when on Hyper-V */
6444 for_each_present_cpu(cpu)
6445 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6446 kvm_max_guest_tsc_khz = tsc_khz;
6447
6448 list_for_each_entry(kvm, &vm_list, vm_list) {
6449 struct kvm_arch *ka = &kvm->arch;
6450
6451 spin_lock(&ka->pvclock_gtod_sync_lock);
6452
6453 pvclock_update_vm_gtod_copy(kvm);
6454
6455 kvm_for_each_vcpu(cpu, vcpu, kvm)
6456 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6457
6458 kvm_for_each_vcpu(cpu, vcpu, kvm)
6459 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6460
6461 spin_unlock(&ka->pvclock_gtod_sync_lock);
6462 }
6463 spin_unlock(&kvm_lock);
0092e434 6464}
5fa4ec9c 6465#endif
0092e434 6466
c8076604
GH		 6467static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6468 void *data)
6469{
6470 struct cpufreq_freqs *freq = data;
6471 struct kvm *kvm;
6472 struct kvm_vcpu *vcpu;
6473 int i, send_ipi = 0;
6474
8cfdc000
ZA		 6475 /*
6476 * We allow guests to temporarily run on slowing clocks,
6477 * provided we notify them after, or to run on accelerating
6478 * clocks, provided we notify them before. Thus time never
6479 * goes backwards.
6480 *
6481 * However, we have a problem. We can't atomically update
6482 * the frequency of a given CPU from this function; it is
6483 * merely a notifier, which can be called from any CPU.
6484 * Changing the TSC frequency at arbitrary points in time
6485 * requires a recomputation of local variables related to
6486 * the TSC for each VCPU. We must flag these local variables
6487 * to be updated and be sure the update takes place with the
6488 * new frequency before any guests proceed.
6489 *
6490 * Unfortunately, the combination of hotplug CPU and frequency
6491 * change creates an intractable locking scenario; the order
6492 * of when these callouts happen is undefined with respect to
6493 * CPU hotplug, and they can race with each other. As such,
6494 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6495 * undefined; you can actually have a CPU frequency change take
6496 * place in between the computation of X and the setting of the
6497 * variable. To protect against this problem, all updates of
6498 * the per_cpu tsc_khz variable are done in an interrupt
6499 * protected IPI, and all callers wishing to update the value
6500 * must wait for a synchronous IPI to complete (which is trivial
6501 * if the caller is on the CPU already). This establishes the
6502 * necessary total order on variable updates.
6503 *
6504 * Note that because a guest time update may take place
6505 * anytime after the setting of the VCPU's request bit, the
6506 * correct TSC value must be set before the request. However,
6507 * to ensure the update actually makes it to any guest which
6508 * starts running in hardware virtualization between the set
6509 * and the acquisition of the spinlock, we must also ping the
6510 * CPU after setting the request bit.
6511 *
6512 */
6513
c8076604
GH		 6514 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6515 return 0;
6516 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6517 return 0;
8cfdc000
ZA		 6518
6519 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6520
2f303b74 6521 spin_lock(&kvm_lock);
c8076604 6522 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6523 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6524 if (vcpu->cpu != freq->cpu)
6525 continue;
c285545f 6526 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6527 if (vcpu->cpu != smp_processor_id())
8cfdc000 6528 send_ipi = 1;
c8076604
GH		 6529 }
6530 }
2f303b74 6531 spin_unlock(&kvm_lock);
c8076604
GH		 6532
6533 if (freq->old < freq->new && send_ipi) {
6534 /*
6535 * We upscale the frequency. Must make the guest
6536 * doesn't see old kvmclock values while running with
6537 * the new frequency, otherwise we risk the guest sees
6538 * time go backwards.
6539 *
6540 * In case we update the frequency for another cpu
6541 * (which might be in guest context) send an interrupt
6542 * to kick the cpu out of guest context. Next time
6543 * guest context is entered kvmclock will be updated,
6544 * so the guest will not see stale values.
6545 */
8cfdc000 6546 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6547 }
6548 return 0;
6549}
6550
6551static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6552 .notifier_call = kvmclock_cpufreq_notifier
6553};
6554
251a5fd6 6555static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6556{
251a5fd6
SAS		 6557 tsc_khz_changed(NULL);
6558 return 0;
8cfdc000
ZA		 6559}
6560
b820cc0c
ZA		 6561static void kvm_timer_init(void)
6562{
c285545f 6563 max_tsc_khz = tsc_khz;
460dd42e 6564
b820cc0c 6565 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6566#ifdef CONFIG_CPU_FREQ
6567 struct cpufreq_policy policy;
758f588d
BP		 6568 int cpu;
6569
c285545f 6570 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6571 cpu = get_cpu();
6572 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6573 if (policy.cpuinfo.max_freq)
6574 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6575 put_cpu();
c285545f 6576#endif
b820cc0c
ZA		 6577 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6578 CPUFREQ_TRANSITION_NOTIFIER);
6579 }
c285545f 6580 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6581
73c1b41e 6582 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6583 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6584}
6585
dd60d217
AK		 6586DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6587EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6588
f5132b01 6589int kvm_is_in_guest(void)
ff9d07a0 6590{
086c9855 6591 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6592}
6593
6594static int kvm_is_user_mode(void)
6595{
6596 int user_mode = 3;
dcf46b94 6597
086c9855
AS		 6598 if (__this_cpu_read(current_vcpu))
6599 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6600
ff9d07a0
ZY		 6601 return user_mode != 0;
6602}
6603
6604static unsigned long kvm_get_guest_ip(void)
6605{
6606 unsigned long ip = 0;
dcf46b94 6607
086c9855
AS		 6608 if (__this_cpu_read(current_vcpu))
6609 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6610
ff9d07a0
ZY		 6611 return ip;
6612}
6613
6614static struct perf_guest_info_callbacks kvm_guest_cbs = {
6615 .is_in_guest = kvm_is_in_guest,
6616 .is_user_mode = kvm_is_user_mode,
6617 .get_guest_ip = kvm_get_guest_ip,
6618};
6619
ce88decf
XG		 6620static void kvm_set_mmio_spte_mask(void)
6621{
6622 u64 mask;
6623 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6624
6625 /*
6626 * Set the reserved bits and the present bit of an paging-structure
6627 * entry to generate page fault with PFER.RSV = 1.
6628 */
28a1f3ac
JS		 6629
6630 /*
6631 * Mask the uppermost physical address bit, which would be reserved as
6632 * long as the supported physical address width is less than 52.
6633 */
6634 mask = 1ull << 51;
885032b9 6635
885032b9 6636 /* Set the present bit. */
ce88decf
XG		 6637 mask |= 1ull;
6638
ce88decf
XG		 6639 /*
6640 * If reserved bit is not supported, clear the present bit to disable
6641 * mmio page fault.
6642 */
7288bde1 6643 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
ce88decf 6644 mask &= ~1ull;
ce88decf 6645
dcdca5fe 6646 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6647}
6648
16e8d74d
MT		 6649#ifdef CONFIG_X86_64
6650static void pvclock_gtod_update_fn(struct work_struct *work)
6651{
d828199e
MT		 6652 struct kvm *kvm;
6653
6654 struct kvm_vcpu *vcpu;
6655 int i;
6656
2f303b74 6657 spin_lock(&kvm_lock);
d828199e
MT		 6658 list_for_each_entry(kvm, &vm_list, vm_list)
6659 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6660 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6661 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6662 spin_unlock(&kvm_lock);
16e8d74d
MT		 6663}
6664
6665static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6666
6667/*
6668 * Notification about pvclock gtod data update.
6669 */
6670static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6671 void *priv)
6672{
6673 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6674 struct timekeeper *tk = priv;
6675
6676 update_pvclock_gtod(tk);
6677
6678 /* disable master clock if host does not trust, or does not
b0c39dc6 6679 * use, TSC based clocksource.
16e8d74d 6680 */
b0c39dc6 6681 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6682 atomic_read(&kvm_guest_has_master_clock) != 0)
6683 queue_work(system_long_wq, &pvclock_gtod_work);
6684
6685 return 0;
6686}
6687
6688static struct notifier_block pvclock_gtod_notifier = {
6689 .notifier_call = pvclock_gtod_notify,
6690};
6691#endif
6692
f8c16bba 6693int kvm_arch_init(void *opaque)
043405e1 6694{
b820cc0c 6695 int r;
6b61edf7 6696 struct kvm_x86_ops *ops = opaque;
f8c16bba 6697
f8c16bba
ZX		 6698 if (kvm_x86_ops) {
6699 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6700 r = -EEXIST;
6701 goto out;
f8c16bba
ZX		 6702 }
6703
6704 if (!ops->cpu_has_kvm_support()) {
6705 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6706 r = -EOPNOTSUPP;
6707 goto out;
f8c16bba
ZX		 6708 }
6709 if (ops->disabled_by_bios()) {
6710 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6711 r = -EOPNOTSUPP;
6712 goto out;
f8c16bba
ZX		 6713 }
6714
013f6a5d
MT		 6715 r = -ENOMEM;
6716 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6717 if (!shared_msrs) {
6718 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6719 goto out;
6720 }
6721
97db56ce
AK		 6722 r = kvm_mmu_module_init();
6723 if (r)
013f6a5d 6724 goto out_free_percpu;
97db56ce 6725
ce88decf 6726 kvm_set_mmio_spte_mask();
97db56ce 6727
f8c16bba 6728 kvm_x86_ops = ops;
920c8377 6729
7b52345e 6730 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6731 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6732 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6733 kvm_timer_init();
c8076604 6734
ff9d07a0
ZY		 6735 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6736
d366bf7e 6737 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6738 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6739
c5cc421b 6740 kvm_lapic_init();
16e8d74d
MT		 6741#ifdef CONFIG_X86_64
6742 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6743
5fa4ec9c 6744 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6745 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6746#endif
6747
f8c16bba 6748 return 0;
56c6d28a 6749
013f6a5d
MT		 6750out_free_percpu:
6751 free_percpu(shared_msrs);
56c6d28a 6752out:
56c6d28a 6753 return r;
043405e1 6754}
8776e519 6755
f8c16bba
ZX		 6756void kvm_arch_exit(void)
6757{
0092e434 6758#ifdef CONFIG_X86_64
5fa4ec9c 6759 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6760 clear_hv_tscchange_cb();
6761#endif
cef84c30 6762 kvm_lapic_exit();
ff9d07a0
ZY		 6763 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6764
888d256e
JK		 6765 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6766 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6767 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6768 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6769#ifdef CONFIG_X86_64
6770 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6771#endif
f8c16bba 6772 kvm_x86_ops = NULL;
56c6d28a 6773 kvm_mmu_module_exit();
013f6a5d 6774 free_percpu(shared_msrs);
56c6d28a 6775}
f8c16bba 6776
5cb56059 6777int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6778{
6779 ++vcpu->stat.halt_exits;
35754c98 6780 if (lapic_in_kernel(vcpu)) {
a4535290 6781 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6782 return 1;
6783 } else {
6784 vcpu->run->exit_reason = KVM_EXIT_HLT;
6785 return 0;
6786 }
6787}
5cb56059
JS		 6788EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6789
6790int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6791{
6affcbed
KH		 6792 int ret = kvm_skip_emulated_instruction(vcpu);
6793 /*
6794 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6795 * KVM_EXIT_DEBUG here.
6796 */
6797 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6798}
8776e519
HB		 6799EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6800
8ef81a9a 6801#ifdef CONFIG_X86_64
55dd00a7
MT		 6802static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6803 unsigned long clock_type)
6804{
6805 struct kvm_clock_pairing clock_pairing;
899a31f5 6806 struct timespec64 ts;
80fbd89c 6807 u64 cycle;
55dd00a7
MT		 6808 int ret;
6809
6810 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6811 return -KVM_EOPNOTSUPP;
6812
6813 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6814 return -KVM_EOPNOTSUPP;
6815
6816 clock_pairing.sec = ts.tv_sec;
6817 clock_pairing.nsec = ts.tv_nsec;
6818 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6819 clock_pairing.flags = 0;
6820
6821 ret = 0;
6822 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6823 sizeof(struct kvm_clock_pairing)))
6824 ret = -KVM_EFAULT;
6825
6826 return ret;
6827}
8ef81a9a 6828#endif
55dd00a7 6829
6aef266c
SV		 6830/*
6831 * kvm_pv_kick_cpu_op: Kick a vcpu.
6832 *
6833 * @apicid - apicid of vcpu to be kicked.
6834 */
6835static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6836{
24d2166b 6837 struct kvm_lapic_irq lapic_irq;
6aef266c 6838
24d2166b
R		 6839 lapic_irq.shorthand = 0;
6840 lapic_irq.dest_mode = 0;
ebd28fcb 6841 lapic_irq.level = 0;
24d2166b 6842 lapic_irq.dest_id = apicid;
93bbf0b8 6843 lapic_irq.msi_redir_hint = false;
6aef266c 6844
24d2166b 6845 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6846 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6847}
6848
d62caabb
AS		 6849void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6850{
6851 vcpu->arch.apicv_active = false;
6852 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6853}
6854
8776e519
HB		 6855int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6856{
6857 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6858 int op_64_bit;
8776e519 6859
696ca779
RK		 6860 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6861 return kvm_hv_hypercall(vcpu);
55cd8e5a 6862
5fdbf976
MT		 6863 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6864 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6865 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6866 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6867 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6868
229456fc 6869 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6870
a449c7aa
NA		 6871 op_64_bit = is_64_bit_mode(vcpu);
6872 if (!op_64_bit) {
8776e519
HB		 6873 nr &= 0xFFFFFFFF;
6874 a0 &= 0xFFFFFFFF;
6875 a1 &= 0xFFFFFFFF;
6876 a2 &= 0xFFFFFFFF;
6877 a3 &= 0xFFFFFFFF;
6878 }
6879
07708c4a
JK		 6880 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6881 ret = -KVM_EPERM;
696ca779 6882 goto out;
07708c4a
JK		 6883 }
6884
8776e519 6885 switch (nr) {
b93463aa
AK		 6886 case KVM_HC_VAPIC_POLL_IRQ:
6887 ret = 0;
6888 break;
6aef266c
SV		 6889 case KVM_HC_KICK_CPU:
6890 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6891 ret = 0;
6892 break;
8ef81a9a 6893#ifdef CONFIG_X86_64
55dd00a7
MT		 6894 case KVM_HC_CLOCK_PAIRING:
6895 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6896 break;
4180bf1b
WL		 6897 case KVM_HC_SEND_IPI:
6898 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
6899 break;
8ef81a9a 6900#endif
8776e519
HB		 6901 default:
6902 ret = -KVM_ENOSYS;
6903 break;
6904 }
696ca779 6905out:
a449c7aa
NA		 6906 if (!op_64_bit)
6907 ret = (u32)ret;
5fdbf976 6908 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 6909
f11c3a8d 6910 ++vcpu->stat.hypercalls;
6356ee0c 6911 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 6912}
6913EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6914
b6785def 6915static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6916{
d6aa1000 6917 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6918 char instruction[3];
5fdbf976 6919 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6920
8776e519 6921 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6922
ce2e852e
DV		 6923 return emulator_write_emulated(ctxt, rip, instruction, 3,
6924 &ctxt->exception);
8776e519
HB		 6925}
6926
851ba692 6927static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6928{
782d422b
MG		 6929 return vcpu->run->request_interrupt_window &&
6930 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6931}
6932
851ba692 6933static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6934{
851ba692
AK		 6935 struct kvm_run *kvm_run = vcpu->run;
6936
91586a3b 6937 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6938 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6939 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6940 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6941 kvm_run->ready_for_interrupt_injection =
6942 pic_in_kernel(vcpu->kvm) ||
782d422b 6943 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6944}
6945
95ba8273
GN		 6946static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6947{
6948 int max_irr, tpr;
6949
6950 if (!kvm_x86_ops->update_cr8_intercept)
6951 return;
6952
bce87cce 6953 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6954 return;
6955
d62caabb
AS		 6956 if (vcpu->arch.apicv_active)
6957 return;
6958
8db3baa2
GN		 6959 if (!vcpu->arch.apic->vapic_addr)
6960 max_irr = kvm_lapic_find_highest_irr(vcpu);
6961 else
6962 max_irr = -1;
95ba8273
GN		 6963
6964 if (max_irr != -1)
6965 max_irr >>= 4;
6966
6967 tpr = kvm_lapic_get_cr8(vcpu);
6968
6969 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6970}
6971
b6b8a145 6972static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6973{
b6b8a145
JK		 6974 int r;
6975
95ba8273 6976 /* try to reinject previous events if any */
664f8e26 6977
1a680e35
LA		 6978 if (vcpu->arch.exception.injected)
6979 kvm_x86_ops->queue_exception(vcpu);
664f8e26 6980 /*
a042c26f
LA		 6981 * Do not inject an NMI or interrupt if there is a pending
6982 * exception. Exceptions and interrupts are recognized at
6983 * instruction boundaries, i.e. the start of an instruction.
6984 * Trap-like exceptions, e.g. #DB, have higher priority than
6985 * NMIs and interrupts, i.e. traps are recognized before an
6986 * NMI/interrupt that's pending on the same instruction.
6987 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
6988 * priority, but are only generated (pended) during instruction
6989 * execution, i.e. a pending fault-like exception means the
6990 * fault occurred on the *previous* instruction and must be
6991 * serviced prior to recognizing any new events in order to
6992 * fully complete the previous instruction.
664f8e26 6993 */
1a680e35
LA		 6994 else if (!vcpu->arch.exception.pending) {
6995 if (vcpu->arch.nmi_injected)
664f8e26 6996 kvm_x86_ops->set_nmi(vcpu);
1a680e35 6997 else if (vcpu->arch.interrupt.injected)
664f8e26 6998 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 6999 }
7000
1a680e35
LA		 7001 /*
7002 * Call check_nested_events() even if we reinjected a previous event
7003 * in order for caller to determine if it should require immediate-exit
7004 * from L2 to L1 due to pending L1 events which require exit
7005 * from L2 to L1.
7006 */
664f8e26
WL		 7007 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7008 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7009 if (r != 0)
7010 return r;
7011 }
7012
7013 /* try to inject new event if pending */
b59bb7bd 7014 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7015 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7016 vcpu->arch.exception.has_error_code,
7017 vcpu->arch.exception.error_code);
d6e8c854 7018
1a680e35 7019 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7020 vcpu->arch.exception.pending = false;
7021 vcpu->arch.exception.injected = true;
7022
d6e8c854
NA		 7023 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7024 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7025 X86_EFLAGS_RF);
7026
6bdf0662
NA		 7027 if (vcpu->arch.exception.nr == DB_VECTOR &&
7028 (vcpu->arch.dr7 & DR7_GD)) {
7029 vcpu->arch.dr7 &= ~DR7_GD;
7030 kvm_update_dr7(vcpu);
7031 }
7032
cfcd20e5 7033 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7034 }
7035
7036 /* Don't consider new event if we re-injected an event */
7037 if (kvm_event_needs_reinjection(vcpu))
7038 return 0;
7039
7040 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7041 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7042 vcpu->arch.smi_pending = false;
52797bf9 7043 ++vcpu->arch.smi_count;
ee2cd4b7 7044 enter_smm(vcpu);
c43203ca 7045 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7046 --vcpu->arch.nmi_pending;
7047 vcpu->arch.nmi_injected = true;
7048 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7049 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7050 /*
7051 * Because interrupts can be injected asynchronously, we are
7052 * calling check_nested_events again here to avoid a race condition.
7053 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7054 * proposal and current concerns. Perhaps we should be setting
7055 * KVM_REQ_EVENT only on certain events and not unconditionally?
7056 */
7057 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7058 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7059 if (r != 0)
7060 return r;
7061 }
95ba8273 7062 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7063 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7064 false);
7065 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7066 }
7067 }
ee2cd4b7 7068
b6b8a145 7069 return 0;
95ba8273
GN		 7070}
7071
7460fb4a
AK		 7072static void process_nmi(struct kvm_vcpu *vcpu)
7073{
7074 unsigned limit = 2;
7075
7076 /*
7077 * x86 is limited to one NMI running, and one NMI pending after it.
7078 * If an NMI is already in progress, limit further NMIs to just one.
7079 * Otherwise, allow two (and we'll inject the first one immediately).
7080 */
7081 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7082 limit = 1;
7083
7084 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7085 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7086 kvm_make_request(KVM_REQ_EVENT, vcpu);
7087}
7088
ee2cd4b7 7089static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7090{
7091 u32 flags = 0;
7092 flags |= seg->g << 23;
7093 flags |= seg->db << 22;
7094 flags |= seg->l << 21;
7095 flags |= seg->avl << 20;
7096 flags |= seg->present << 15;
7097 flags |= seg->dpl << 13;
7098 flags |= seg->s << 12;
7099 flags |= seg->type << 8;
7100 return flags;
7101}
7102
ee2cd4b7 7103static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7104{
7105 struct kvm_segment seg;
7106 int offset;
7107
7108 kvm_get_segment(vcpu, &seg, n);
7109 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7110
7111 if (n < 3)
7112 offset = 0x7f84 + n * 12;
7113 else
7114 offset = 0x7f2c + (n - 3) * 12;
7115
7116 put_smstate(u32, buf, offset + 8, seg.base);
7117 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7118 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7119}
7120
efbb288a 7121#ifdef CONFIG_X86_64
ee2cd4b7 7122static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7123{
7124 struct kvm_segment seg;
7125 int offset;
7126 u16 flags;
7127
7128 kvm_get_segment(vcpu, &seg, n);
7129 offset = 0x7e00 + n * 16;
7130
ee2cd4b7 7131 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7132 put_smstate(u16, buf, offset, seg.selector);
7133 put_smstate(u16, buf, offset + 2, flags);
7134 put_smstate(u32, buf, offset + 4, seg.limit);
7135 put_smstate(u64, buf, offset + 8, seg.base);
7136}
efbb288a 7137#endif
660a5d51 7138
ee2cd4b7 7139static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7140{
7141 struct desc_ptr dt;
7142 struct kvm_segment seg;
7143 unsigned long val;
7144 int i;
7145
7146 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7147 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7148 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7149 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7150
7151 for (i = 0; i < 8; i++)
7152 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7153
7154 kvm_get_dr(vcpu, 6, &val);
7155 put_smstate(u32, buf, 0x7fcc, (u32)val);
7156 kvm_get_dr(vcpu, 7, &val);
7157 put_smstate(u32, buf, 0x7fc8, (u32)val);
7158
7159 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7160 put_smstate(u32, buf, 0x7fc4, seg.selector);
7161 put_smstate(u32, buf, 0x7f64, seg.base);
7162 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7163 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7164
7165 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7166 put_smstate(u32, buf, 0x7fc0, seg.selector);
7167 put_smstate(u32, buf, 0x7f80, seg.base);
7168 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7169 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7170
7171 kvm_x86_ops->get_gdt(vcpu, &dt);
7172 put_smstate(u32, buf, 0x7f74, dt.address);
7173 put_smstate(u32, buf, 0x7f70, dt.size);
7174
7175 kvm_x86_ops->get_idt(vcpu, &dt);
7176 put_smstate(u32, buf, 0x7f58, dt.address);
7177 put_smstate(u32, buf, 0x7f54, dt.size);
7178
7179 for (i = 0; i < 6; i++)
ee2cd4b7 7180 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7181
7182 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7183
7184 /* revision id */
7185 put_smstate(u32, buf, 0x7efc, 0x00020000);
7186 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7187}
7188
ee2cd4b7 7189static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7190{
7191#ifdef CONFIG_X86_64
7192 struct desc_ptr dt;
7193 struct kvm_segment seg;
7194 unsigned long val;
7195 int i;
7196
7197 for (i = 0; i < 16; i++)
7198 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7199
7200 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7201 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7202
7203 kvm_get_dr(vcpu, 6, &val);
7204 put_smstate(u64, buf, 0x7f68, val);
7205 kvm_get_dr(vcpu, 7, &val);
7206 put_smstate(u64, buf, 0x7f60, val);
7207
7208 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7209 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7210 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7211
7212 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7213
7214 /* revision id */
7215 put_smstate(u32, buf, 0x7efc, 0x00020064);
7216
7217 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7218
7219 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7220 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7221 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7222 put_smstate(u32, buf, 0x7e94, seg.limit);
7223 put_smstate(u64, buf, 0x7e98, seg.base);
7224
7225 kvm_x86_ops->get_idt(vcpu, &dt);
7226 put_smstate(u32, buf, 0x7e84, dt.size);
7227 put_smstate(u64, buf, 0x7e88, dt.address);
7228
7229 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7230 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7231 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7232 put_smstate(u32, buf, 0x7e74, seg.limit);
7233 put_smstate(u64, buf, 0x7e78, seg.base);
7234
7235 kvm_x86_ops->get_gdt(vcpu, &dt);
7236 put_smstate(u32, buf, 0x7e64, dt.size);
7237 put_smstate(u64, buf, 0x7e68, dt.address);
7238
7239 for (i = 0; i < 6; i++)
ee2cd4b7 7240 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7241#else
7242 WARN_ON_ONCE(1);
7243#endif
7244}
7245
ee2cd4b7 7246static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7247{
660a5d51 7248 struct kvm_segment cs, ds;
18c3626e 7249 struct desc_ptr dt;
660a5d51
PB		 7250 char buf[512];
7251 u32 cr0;
7252
660a5d51 7253 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7254 memset(buf, 0, 512);
d6321d49 7255 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7256 enter_smm_save_state_64(vcpu, buf);
660a5d51 7257 else
ee2cd4b7 7258 enter_smm_save_state_32(vcpu, buf);
660a5d51 7259
0234bf88
LP		 7260 /*
7261 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7262 * vCPU state (e.g. leave guest mode) after we've saved the state into
7263 * the SMM state-save area.
7264 */
7265 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7266
7267 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7268 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7269
7270 if (kvm_x86_ops->get_nmi_mask(vcpu))
7271 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7272 else
7273 kvm_x86_ops->set_nmi_mask(vcpu, true);
7274
7275 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7276 kvm_rip_write(vcpu, 0x8000);
7277
7278 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7279 kvm_x86_ops->set_cr0(vcpu, cr0);
7280 vcpu->arch.cr0 = cr0;
7281
7282 kvm_x86_ops->set_cr4(vcpu, 0);
7283
18c3626e
PB		 7284 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7285 dt.address = dt.size = 0;
7286 kvm_x86_ops->set_idt(vcpu, &dt);
7287
660a5d51
PB		 7288 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7289
7290 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7291 cs.base = vcpu->arch.smbase;
7292
7293 ds.selector = 0;
7294 ds.base = 0;
7295
7296 cs.limit = ds.limit = 0xffffffff;
7297 cs.type = ds.type = 0x3;
7298 cs.dpl = ds.dpl = 0;
7299 cs.db = ds.db = 0;
7300 cs.s = ds.s = 1;
7301 cs.l = ds.l = 0;
7302 cs.g = ds.g = 1;
7303 cs.avl = ds.avl = 0;
7304 cs.present = ds.present = 1;
7305 cs.unusable = ds.unusable = 0;
7306 cs.padding = ds.padding = 0;
7307
7308 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7309 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7310 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7311 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7312 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7313 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7314
d6321d49 7315 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7316 kvm_x86_ops->set_efer(vcpu, 0);
7317
7318 kvm_update_cpuid(vcpu);
7319 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7320}
7321
ee2cd4b7 7322static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7323{
7324 vcpu->arch.smi_pending = true;
7325 kvm_make_request(KVM_REQ_EVENT, vcpu);
7326}
7327
2860c4b1
PB		 7328void kvm_make_scan_ioapic_request(struct kvm *kvm)
7329{
7330 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7331}
7332
3d81bc7e 7333static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7334{
3d81bc7e
YZ		 7335 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7336 return;
c7c9c56c 7337
6308630b 7338 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7339
b053b2ae 7340 if (irqchip_split(vcpu->kvm))
6308630b 7341 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7342 else {
fa59cc00 7343 if (vcpu->arch.apicv_active)
d62caabb 7344 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7345 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7346 }
e40ff1d6
LA		 7347
7348 if (is_guest_mode(vcpu))
7349 vcpu->arch.load_eoi_exitmap_pending = true;
7350 else
7351 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7352}
7353
7354static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7355{
7356 u64 eoi_exit_bitmap[4];
7357
7358 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7359 return;
7360
5c919412
AS		 7361 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7362 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7363 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7364}
7365
93065ac7
MH		 7366int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7367 unsigned long start, unsigned long end,
7368 bool blockable)
b1394e74
RK		 7369{
7370 unsigned long apic_address;
7371
7372 /*
7373 * The physical address of apic access page is stored in the VMCS.
7374 * Update it when it becomes invalid.
7375 */
7376 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7377 if (start <= apic_address && apic_address < end)
7378 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7379
7380 return 0;
b1394e74
RK		 7381}
7382
4256f43f
TC		 7383void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7384{
c24ae0dc
TC		 7385 struct page *page = NULL;
7386
35754c98 7387 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7388 return;
7389
4256f43f
TC		 7390 if (!kvm_x86_ops->set_apic_access_page_addr)
7391 return;
7392
c24ae0dc 7393 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7394 if (is_error_page(page))
7395 return;
c24ae0dc
TC		 7396 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7397
7398 /*
7399 * Do not pin apic access page in memory, the MMU notifier
7400 * will call us again if it is migrated or swapped out.
7401 */
7402 put_page(page);
4256f43f
TC		 7403}
7404EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7405
d264ee0c
SC		 7406void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7407{
7408 smp_send_reschedule(vcpu->cpu);
7409}
7410EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7411
9357d939 7412/*
362c698f 7413 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7414 * exiting to the userspace. Otherwise, the value will be returned to the
7415 * userspace.
7416 */
851ba692 7417static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7418{
7419 int r;
62a193ed
MG		 7420 bool req_int_win =
7421 dm_request_for_irq_injection(vcpu) &&
7422 kvm_cpu_accept_dm_intr(vcpu);
7423
730dca42 7424 bool req_immediate_exit = false;
b6c7a5dc 7425
2fa6e1e1 7426 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7427 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7428 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7429 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7430 kvm_mmu_unload(vcpu);
a8eeb04a 7431 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7432 __kvm_migrate_timers(vcpu);
d828199e
MT		 7433 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7434 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7435 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7436 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7437 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7438 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7439 if (unlikely(r))
7440 goto out;
7441 }
a8eeb04a 7442 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7443 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7444 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7445 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7446 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7447 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7448 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7449 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7450 r = 0;
7451 goto out;
7452 }
a8eeb04a 7453 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7454 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7455 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7456 r = 0;
7457 goto out;
7458 }
af585b92
GN		 7459 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7460 /* Page is swapped out. Do synthetic halt */
7461 vcpu->arch.apf.halted = true;
7462 r = 1;
7463 goto out;
7464 }
c9aaa895
GC		 7465 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7466 record_steal_time(vcpu);
64d60670
PB		 7467 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7468 process_smi(vcpu);
7460fb4a
AK		 7469 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7470 process_nmi(vcpu);
f5132b01 7471 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7472 kvm_pmu_handle_event(vcpu);
f5132b01 7473 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7474 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7475 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7476 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7477 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7478 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7479 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7480 vcpu->run->eoi.vector =
7481 vcpu->arch.pending_ioapic_eoi;
7482 r = 0;
7483 goto out;
7484 }
7485 }
3d81bc7e
YZ		 7486 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7487 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7488 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7489 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7490 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7491 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7492 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7493 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7494 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7495 r = 0;
7496 goto out;
7497 }
e516cebb
AS		 7498 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7499 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7500 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7501 r = 0;
7502 goto out;
7503 }
db397571
AS		 7504 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7505 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7506 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7507 r = 0;
7508 goto out;
7509 }
f3b138c5
AS		 7510
7511 /*
7512 * KVM_REQ_HV_STIMER has to be processed after
7513 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7514 * depend on the guest clock being up-to-date
7515 */
1f4b34f8
AS		 7516 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7517 kvm_hv_process_stimers(vcpu);
2f52d58c 7518 }
b93463aa 7519
b463a6f7 7520 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7521 ++vcpu->stat.req_event;
66450a21
JK		 7522 kvm_apic_accept_events(vcpu);
7523 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7524 r = 1;
7525 goto out;
7526 }
7527
b6b8a145
JK		 7528 if (inject_pending_event(vcpu, req_int_win) != 0)
7529 req_immediate_exit = true;
321c5658 7530 else {
cc3d967f 7531 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7532 *
cc3d967f
LP		 7533 * SMIs have three cases:
7534 * 1) They can be nested, and then there is nothing to
7535 * do here because RSM will cause a vmexit anyway.
7536 * 2) There is an ISA-specific reason why SMI cannot be
7537 * injected, and the moment when this changes can be
7538 * intercepted.
7539 * 3) Or the SMI can be pending because
7540 * inject_pending_event has completed the injection
7541 * of an IRQ or NMI from the previous vmexit, and
7542 * then we request an immediate exit to inject the
7543 * SMI.
c43203ca
PB		 7544 */
7545 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7546 if (!kvm_x86_ops->enable_smi_window(vcpu))
7547 req_immediate_exit = true;
321c5658
YS		 7548 if (vcpu->arch.nmi_pending)
7549 kvm_x86_ops->enable_nmi_window(vcpu);
7550 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7551 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7552 WARN_ON(vcpu->arch.exception.pending);
321c5658 7553 }
b463a6f7
AK		 7554
7555 if (kvm_lapic_enabled(vcpu)) {
7556 update_cr8_intercept(vcpu);
7557 kvm_lapic_sync_to_vapic(vcpu);
7558 }
7559 }
7560
d8368af8
AK		 7561 r = kvm_mmu_reload(vcpu);
7562 if (unlikely(r)) {
d905c069 7563 goto cancel_injection;
d8368af8
AK		 7564 }
7565
b6c7a5dc
HB		 7566 preempt_disable();
7567
7568 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7569
7570 /*
7571 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7572 * IPI are then delayed after guest entry, which ensures that they
7573 * result in virtual interrupt delivery.
7574 */
7575 local_irq_disable();
6b7e2d09
XG		 7576 vcpu->mode = IN_GUEST_MODE;
7577
01b71917
MT		 7578 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7579
0f127d12 7580 /*
b95234c8 7581 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7582 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7583 *
7584 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7585 * pairs with the memory barrier implicit in pi_test_and_set_on
7586 * (see vmx_deliver_posted_interrupt).
7587 *
7588 * 3) This also orders the write to mode from any reads to the page
7589 * tables done while the VCPU is running. Please see the comment
7590 * in kvm_flush_remote_tlbs.
6b7e2d09 7591 */
01b71917 7592 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7593
b95234c8
PB		 7594 /*
7595 * This handles the case where a posted interrupt was
7596 * notified with kvm_vcpu_kick.
7597 */
fa59cc00
LA		 7598 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7599 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7600
2fa6e1e1 7601 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7602 || need_resched() || signal_pending(current)) {
6b7e2d09 7603 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7604 smp_wmb();
6c142801
AK		 7605 local_irq_enable();
7606 preempt_enable();
01b71917 7607 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7608 r = 1;
d905c069 7609 goto cancel_injection;
6c142801
AK		 7610 }
7611
fc5b7f3b
DM		 7612 kvm_load_guest_xcr0(vcpu);
7613
c43203ca
PB		 7614 if (req_immediate_exit) {
7615 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 7616 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 7617 }
d6185f20 7618
8b89fe1f 7619 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7620 if (lapic_timer_advance_ns)
7621 wait_lapic_expire(vcpu);
6edaa530 7622 guest_enter_irqoff();
b6c7a5dc 7623
42dbaa5a 7624 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7625 set_debugreg(0, 7);
7626 set_debugreg(vcpu->arch.eff_db[0], 0);
7627 set_debugreg(vcpu->arch.eff_db[1], 1);
7628 set_debugreg(vcpu->arch.eff_db[2], 2);
7629 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7630 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7631 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7632 }
b6c7a5dc 7633
851ba692 7634 kvm_x86_ops->run(vcpu);
b6c7a5dc 7635
c77fb5fe
PB		 7636 /*
7637 * Do this here before restoring debug registers on the host. And
7638 * since we do this before handling the vmexit, a DR access vmexit
7639 * can (a) read the correct value of the debug registers, (b) set
7640 * KVM_DEBUGREG_WONT_EXIT again.
7641 */
7642 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7643 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7644 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7645 kvm_update_dr0123(vcpu);
7646 kvm_update_dr6(vcpu);
7647 kvm_update_dr7(vcpu);
7648 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7649 }
7650
24f1e32c
FW		 7651 /*
7652 * If the guest has used debug registers, at least dr7
7653 * will be disabled while returning to the host.
7654 * If we don't have active breakpoints in the host, we don't
7655 * care about the messed up debug address registers. But if
7656 * we have some of them active, restore the old state.
7657 */
59d8eb53 7658 if (hw_breakpoint_active())
24f1e32c 7659 hw_breakpoint_restore();
42dbaa5a 7660
4ba76538 7661 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7662
6b7e2d09 7663 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7664 smp_wmb();
a547c6db 7665
fc5b7f3b
DM		 7666 kvm_put_guest_xcr0(vcpu);
7667
dd60d217 7668 kvm_before_interrupt(vcpu);
a547c6db 7669 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7670 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7671
7672 ++vcpu->stat.exits;
7673
f2485b3e 7674 guest_exit_irqoff();
b6c7a5dc 7675
f2485b3e 7676 local_irq_enable();
b6c7a5dc
HB		 7677 preempt_enable();
7678
f656ce01 7679 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7680
b6c7a5dc
HB		 7681 /*
7682 * Profile KVM exit RIPs:
7683 */
7684 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7685 unsigned long rip = kvm_rip_read(vcpu);
7686 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7687 }
7688
cc578287
ZA		 7689 if (unlikely(vcpu->arch.tsc_always_catchup))
7690 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7691
5cfb1d5a
MT		 7692 if (vcpu->arch.apic_attention)
7693 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7694
618232e2 7695 vcpu->arch.gpa_available = false;
851ba692 7696 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7697 return r;
7698
7699cancel_injection:
7700 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7701 if (unlikely(vcpu->arch.apic_attention))
7702 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7703out:
7704 return r;
7705}
b6c7a5dc 7706
362c698f
PB		 7707static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7708{
bf9f6ac8
FW		 7709 if (!kvm_arch_vcpu_runnable(vcpu) &&
7710 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7711 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7712 kvm_vcpu_block(vcpu);
7713 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7714
7715 if (kvm_x86_ops->post_block)
7716 kvm_x86_ops->post_block(vcpu);
7717
9c8fd1ba
PB		 7718 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7719 return 1;
7720 }
362c698f
PB		 7721
7722 kvm_apic_accept_events(vcpu);
7723 switch(vcpu->arch.mp_state) {
7724 case KVM_MP_STATE_HALTED:
7725 vcpu->arch.pv.pv_unhalted = false;
7726 vcpu->arch.mp_state =
7727 KVM_MP_STATE_RUNNABLE;
7728 case KVM_MP_STATE_RUNNABLE:
7729 vcpu->arch.apf.halted = false;
7730 break;
7731 case KVM_MP_STATE_INIT_RECEIVED:
7732 break;
7733 default:
7734 return -EINTR;
7735 break;
7736 }
7737 return 1;
7738}
09cec754 7739
5d9bc648
PB		 7740static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7741{
0ad3bed6
PB		 7742 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7743 kvm_x86_ops->check_nested_events(vcpu, false);
7744
5d9bc648
PB		 7745 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7746 !vcpu->arch.apf.halted);
7747}
7748
362c698f 7749static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7750{
7751 int r;
f656ce01 7752 struct kvm *kvm = vcpu->kvm;
d7690175 7753
f656ce01 7754 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 7755 vcpu->arch.l1tf_flush_l1d = true;
d7690175 7756
362c698f 7757 for (;;) {
58f800d5 7758 if (kvm_vcpu_running(vcpu)) {
851ba692 7759 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7760 } else {
362c698f 7761 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7762 }
7763
09cec754
GN		 7764 if (r <= 0)
7765 break;
7766
72875d8a 7767 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7768 if (kvm_cpu_has_pending_timer(vcpu))
7769 kvm_inject_pending_timer_irqs(vcpu);
7770
782d422b
MG		 7771 if (dm_request_for_irq_injection(vcpu) &&
7772 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7773 r = 0;
7774 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7775 ++vcpu->stat.request_irq_exits;
362c698f 7776 break;
09cec754 7777 }
af585b92
GN		 7778
7779 kvm_check_async_pf_completion(vcpu);
7780
09cec754
GN		 7781 if (signal_pending(current)) {
7782 r = -EINTR;
851ba692 7783 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7784 ++vcpu->stat.signal_exits;
362c698f 7785 break;
09cec754
GN		 7786 }
7787 if (need_resched()) {
f656ce01 7788 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7789 cond_resched();
f656ce01 7790 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7791 }
b6c7a5dc
HB		 7792 }
7793
f656ce01 7794 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7795
7796 return r;
7797}
7798
716d51ab
GN		 7799static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7800{
7801 int r;
7802 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 7803 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 7804 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7805 if (r != EMULATE_DONE)
7806 return 0;
7807 return 1;
7808}
7809
7810static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7811{
7812 BUG_ON(!vcpu->arch.pio.count);
7813
7814 return complete_emulated_io(vcpu);
7815}
7816
f78146b0
AK		 7817/*
7818 * Implements the following, as a state machine:
7819 *
7820 * read:
7821 * for each fragment
87da7e66
XG		 7822 * for each mmio piece in the fragment
7823 * write gpa, len
7824 * exit
7825 * copy data
f78146b0
AK		 7826 * execute insn
7827 *
7828 * write:
7829 * for each fragment
87da7e66
XG		 7830 * for each mmio piece in the fragment
7831 * write gpa, len
7832 * copy data
7833 * exit
f78146b0 7834 */
716d51ab 7835static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7836{
7837 struct kvm_run *run = vcpu->run;
f78146b0 7838 struct kvm_mmio_fragment *frag;
87da7e66 7839 unsigned len;
5287f194 7840
716d51ab 7841 BUG_ON(!vcpu->mmio_needed);
5287f194 7842
716d51ab 7843 /* Complete previous fragment */
87da7e66
XG		 7844 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7845 len = min(8u, frag->len);
716d51ab 7846 if (!vcpu->mmio_is_write)
87da7e66
XG		 7847 memcpy(frag->data, run->mmio.data, len);
7848
7849 if (frag->len <= 8) {
7850 /* Switch to the next fragment. */
7851 frag++;
7852 vcpu->mmio_cur_fragment++;
7853 } else {
7854 /* Go forward to the next mmio piece. */
7855 frag->data += len;
7856 frag->gpa += len;
7857 frag->len -= len;
7858 }
7859
a08d3b3b 7860 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7861 vcpu->mmio_needed = 0;
0912c977
PB		 7862
7863 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7864 if (vcpu->mmio_is_write)
716d51ab
GN		 7865 return 1;
7866 vcpu->mmio_read_completed = 1;
7867 return complete_emulated_io(vcpu);
7868 }
87da7e66 7869
716d51ab
GN		 7870 run->exit_reason = KVM_EXIT_MMIO;
7871 run->mmio.phys_addr = frag->gpa;
7872 if (vcpu->mmio_is_write)
87da7e66
XG		 7873 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7874 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7875 run->mmio.is_write = vcpu->mmio_is_write;
7876 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7877 return 0;
5287f194
AK		 7878}
7879
822f312d
SAS		 7880/* Swap (qemu) user FPU context for the guest FPU context. */
7881static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7882{
7883 preempt_disable();
7884 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
7885 /* PKRU is separately restored in kvm_x86_ops->run. */
7886 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7887 ~XFEATURE_MASK_PKRU);
7888 preempt_enable();
7889 trace_kvm_fpu(1);
7890}
7891
7892/* When vcpu_run ends, restore user space FPU context. */
7893static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7894{
7895 preempt_disable();
7896 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
7897 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7898 preempt_enable();
7899 ++vcpu->stat.fpu_reload;
7900 trace_kvm_fpu(0);
7901}
7902
b6c7a5dc
HB		 7903int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7904{
7905 int r;
b6c7a5dc 7906
accb757d 7907 vcpu_load(vcpu);
20b7035c 7908 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7909 kvm_load_guest_fpu(vcpu);
7910
a4535290 7911 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7912 if (kvm_run->immediate_exit) {
7913 r = -EINTR;
7914 goto out;
7915 }
b6c7a5dc 7916 kvm_vcpu_block(vcpu);
66450a21 7917 kvm_apic_accept_events(vcpu);
72875d8a 7918 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7919 r = -EAGAIN;
a0595000
JS		 7920 if (signal_pending(current)) {
7921 r = -EINTR;
7922 vcpu->run->exit_reason = KVM_EXIT_INTR;
7923 ++vcpu->stat.signal_exits;
7924 }
ac9f6dc0 7925 goto out;
b6c7a5dc
HB		 7926 }
7927
01643c51
KH		 7928 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7929 r = -EINVAL;
7930 goto out;
7931 }
7932
7933 if (vcpu->run->kvm_dirty_regs) {
7934 r = sync_regs(vcpu);
7935 if (r != 0)
7936 goto out;
7937 }
7938
b6c7a5dc 7939 /* re-sync apic's tpr */
35754c98 7940 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7941 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7942 r = -EINVAL;
7943 goto out;
7944 }
7945 }
b6c7a5dc 7946
716d51ab
GN		 7947 if (unlikely(vcpu->arch.complete_userspace_io)) {
7948 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7949 vcpu->arch.complete_userspace_io = NULL;
7950 r = cui(vcpu);
7951 if (r <= 0)
5663d8f9 7952 goto out;
716d51ab
GN		 7953 } else
7954 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7955
460df4c1
PB		 7956 if (kvm_run->immediate_exit)
7957 r = -EINTR;
7958 else
7959 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7960
7961out:
5663d8f9 7962 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7963 if (vcpu->run->kvm_valid_regs)
7964 store_regs(vcpu);
f1d86e46 7965 post_kvm_run_save(vcpu);
20b7035c 7966 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7967
accb757d 7968 vcpu_put(vcpu);
b6c7a5dc
HB		 7969 return r;
7970}
7971
01643c51 7972static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7973{
7ae441ea
GN		 7974 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7975 /*
7976 * We are here if userspace calls get_regs() in the middle of
7977 * instruction emulation. Registers state needs to be copied
4a969980 7978 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7979 * that usually, but some bad designed PV devices (vmware
7980 * backdoor interface) need this to work
7981 */
dd856efa 7982 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7983 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7984 }
5fdbf976
MT		 7985 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7986 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7987 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7988 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7989 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7990 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7991 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7992 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7993#ifdef CONFIG_X86_64
5fdbf976
MT		 7994 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7995 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7996 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7997 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7998 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7999 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
8000 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
8001 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 8002#endif
8003
5fdbf976 8004 regs->rip = kvm_rip_read(vcpu);
91586a3b 8005 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8006}
b6c7a5dc 8007
01643c51
KH		 8008int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8009{
8010 vcpu_load(vcpu);
8011 __get_regs(vcpu, regs);
1fc9b76b 8012 vcpu_put(vcpu);
b6c7a5dc
HB		 8013 return 0;
8014}
8015
01643c51 8016static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8017{
7ae441ea
GN		 8018 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8019 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8020
5fdbf976
MT		 8021 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
8022 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
8023 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
8024 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
8025 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
8026 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
8027 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
8028 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 8029#ifdef CONFIG_X86_64
5fdbf976
MT		 8030 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
8031 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
8032 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
8033 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
8034 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
8035 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
8036 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
8037 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 8038#endif
8039
5fdbf976 8040 kvm_rip_write(vcpu, regs->rip);
d73235d1 8041 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8042
b4f14abd
JK		 8043 vcpu->arch.exception.pending = false;
8044
3842d135 8045 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8046}
3842d135 8047
01643c51
KH		 8048int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8049{
8050 vcpu_load(vcpu);
8051 __set_regs(vcpu, regs);
875656fe 8052 vcpu_put(vcpu);
b6c7a5dc
HB		 8053 return 0;
8054}
8055
b6c7a5dc
HB		 8056void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8057{
8058 struct kvm_segment cs;
8059
3e6e0aab 8060 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8061 *db = cs.db;
8062 *l = cs.l;
8063}
8064EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8065
01643c51 8066static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8067{
89a27f4d 8068 struct desc_ptr dt;
b6c7a5dc 8069
3e6e0aab
GT		 8070 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8071 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8072 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8073 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8074 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8075 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8076
3e6e0aab
GT		 8077 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8078 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8079
8080 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8081 sregs->idt.limit = dt.size;
8082 sregs->idt.base = dt.address;
b6c7a5dc 8083 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8084 sregs->gdt.limit = dt.size;
8085 sregs->gdt.base = dt.address;
b6c7a5dc 8086
4d4ec087 8087 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8088 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8089 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8090 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8091 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8092 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8093 sregs->apic_base = kvm_get_apic_base(vcpu);
8094
923c61bb 8095 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 8096
04140b41 8097 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8098 set_bit(vcpu->arch.interrupt.nr,
8099 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8100}
16d7a191 8101
01643c51
KH		 8102int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8103 struct kvm_sregs *sregs)
8104{
8105 vcpu_load(vcpu);
8106 __get_sregs(vcpu, sregs);
bcdec41c 8107 vcpu_put(vcpu);
b6c7a5dc
HB		 8108 return 0;
8109}
8110
62d9f0db
MT		 8111int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8112 struct kvm_mp_state *mp_state)
8113{
fd232561
CD		 8114 vcpu_load(vcpu);
8115
66450a21 8116 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8117 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8118 vcpu->arch.pv.pv_unhalted)
8119 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8120 else
8121 mp_state->mp_state = vcpu->arch.mp_state;
8122
fd232561 8123 vcpu_put(vcpu);
62d9f0db
MT		 8124 return 0;
8125}
8126
8127int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8128 struct kvm_mp_state *mp_state)
8129{
e83dff5e
CD		 8130 int ret = -EINVAL;
8131
8132 vcpu_load(vcpu);
8133
bce87cce 8134 if (!lapic_in_kernel(vcpu) &&
66450a21 8135 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8136 goto out;
66450a21 8137
28bf2888
DH		 8138 /* INITs are latched while in SMM */
8139 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8140 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8141 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8142 goto out;
28bf2888 8143
66450a21
JK		 8144 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8145 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8146 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8147 } else
8148 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8149 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8150
8151 ret = 0;
8152out:
8153 vcpu_put(vcpu);
8154 return ret;
62d9f0db
MT		 8155}
8156
7f3d35fd
KW		 8157int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8158 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8159{
9d74191a 8160 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8161 int ret;
e01c2426 8162
8ec4722d 8163 init_emulate_ctxt(vcpu);
c697518a 8164
7f3d35fd 8165 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8166 has_error_code, error_code);
c697518a 8167
c697518a 8168 if (ret)
19d04437 8169 return EMULATE_FAIL;
37817f29 8170
9d74191a
TY		 8171 kvm_rip_write(vcpu, ctxt->eip);
8172 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8173 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8174 return EMULATE_DONE;
37817f29
IE		 8175}
8176EXPORT_SYMBOL_GPL(kvm_task_switch);
8177
3140c156 8178static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8179{
74fec5b9
TL		 8180 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8181 (sregs->cr4 & X86_CR4_OSXSAVE))
8182 return -EINVAL;
8183
37b95951 8184 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8185 /*
8186 * When EFER.LME and CR0.PG are set, the processor is in
8187 * 64-bit mode (though maybe in a 32-bit code segment).
8188 * CR4.PAE and EFER.LMA must be set.
8189 */
37b95951 8190 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8191 || !(sregs->efer & EFER_LMA))
8192 return -EINVAL;
8193 } else {
8194 /*
8195 * Not in 64-bit mode: EFER.LMA is clear and the code
8196 * segment cannot be 64-bit.
8197 */
8198 if (sregs->efer & EFER_LMA || sregs->cs.l)
8199 return -EINVAL;
8200 }
8201
8202 return 0;
8203}
8204
01643c51 8205static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8206{
58cb628d 8207 struct msr_data apic_base_msr;
b6c7a5dc 8208 int mmu_reset_needed = 0;
c4d21882 8209 int cpuid_update_needed = 0;
63f42e02 8210 int pending_vec, max_bits, idx;
89a27f4d 8211 struct desc_ptr dt;
b4ef9d4e
CD		 8212 int ret = -EINVAL;
8213
f2981033 8214 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8215 goto out;
f2981033 8216
d3802286
JM		 8217 apic_base_msr.data = sregs->apic_base;
8218 apic_base_msr.host_initiated = true;
8219 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8220 goto out;
6d1068b3 8221
89a27f4d
GN		 8222 dt.size = sregs->idt.limit;
8223 dt.address = sregs->idt.base;
b6c7a5dc 8224 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8225 dt.size = sregs->gdt.limit;
8226 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8227 kvm_x86_ops->set_gdt(vcpu, &dt);
8228
ad312c7c 8229 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8230 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8231 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8232 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8233
2d3ad1f4 8234 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8235
f6801dff 8236 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8237 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8238
4d4ec087 8239 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8240 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8241 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8242
fc78f519 8243 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8244 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8245 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8246 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8247 if (cpuid_update_needed)
00b27a3e 8248 kvm_update_cpuid(vcpu);
63f42e02
XG		 8249
8250 idx = srcu_read_lock(&vcpu->kvm->srcu);
d35b34a9 8251 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
9f8fe504 8252 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8253 mmu_reset_needed = 1;
8254 }
63f42e02 8255 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8256
8257 if (mmu_reset_needed)
8258 kvm_mmu_reset_context(vcpu);
8259
a50abc3b 8260 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8261 pending_vec = find_first_bit(
8262 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8263 if (pending_vec < max_bits) {
66fd3f7f 8264 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8265 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8266 }
8267
3e6e0aab
GT		 8268 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8269 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8270 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8271 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8272 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8273 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8274
3e6e0aab
GT		 8275 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8276 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8277
5f0269f5
ME		 8278 update_cr8_intercept(vcpu);
8279
9c3e4aab 8280 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8281 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8282 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8283 !is_protmode(vcpu))
9c3e4aab
MT		 8284 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8285
3842d135
AK		 8286 kvm_make_request(KVM_REQ_EVENT, vcpu);
8287
b4ef9d4e
CD		 8288 ret = 0;
8289out:
01643c51
KH		 8290 return ret;
8291}
8292
8293int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8294 struct kvm_sregs *sregs)
8295{
8296 int ret;
8297
8298 vcpu_load(vcpu);
8299 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8300 vcpu_put(vcpu);
8301 return ret;
b6c7a5dc
HB		 8302}
8303
d0bfb940
JK		 8304int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8305 struct kvm_guest_debug *dbg)
b6c7a5dc 8306{
355be0b9 8307 unsigned long rflags;
ae675ef0 8308 int i, r;
b6c7a5dc 8309
66b56562
CD		 8310 vcpu_load(vcpu);
8311
4f926bf2
JK		 8312 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8313 r = -EBUSY;
8314 if (vcpu->arch.exception.pending)
2122ff5e 8315 goto out;
4f926bf2
JK		 8316 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8317 kvm_queue_exception(vcpu, DB_VECTOR);
8318 else
8319 kvm_queue_exception(vcpu, BP_VECTOR);
8320 }
8321
91586a3b
JK		 8322 /*
8323 * Read rflags as long as potentially injected trace flags are still
8324 * filtered out.
8325 */
8326 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8327
8328 vcpu->guest_debug = dbg->control;
8329 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8330 vcpu->guest_debug = 0;
8331
8332 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8333 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8334 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8335 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8336 } else {
8337 for (i = 0; i < KVM_NR_DB_REGS; i++)
8338 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8339 }
c8639010 8340 kvm_update_dr7(vcpu);
ae675ef0 8341
f92653ee
JK		 8342 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8343 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8344 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8345
91586a3b
JK		 8346 /*
8347 * Trigger an rflags update that will inject or remove the trace
8348 * flags.
8349 */
8350 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8351
a96036b8 8352 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8353
4f926bf2 8354 r = 0;
d0bfb940 8355
2122ff5e 8356out:
66b56562 8357 vcpu_put(vcpu);
b6c7a5dc
HB		 8358 return r;
8359}
8360
8b006791
ZX		 8361/*
8362 * Translate a guest virtual address to a guest physical address.
8363 */
8364int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8365 struct kvm_translation *tr)
8366{
8367 unsigned long vaddr = tr->linear_address;
8368 gpa_t gpa;
f656ce01 8369 int idx;
8b006791 8370
1da5b61d
CD		 8371 vcpu_load(vcpu);
8372
f656ce01 8373 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8374 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8375 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8376 tr->physical_address = gpa;
8377 tr->valid = gpa != UNMAPPED_GVA;
8378 tr->writeable = 1;
8379 tr->usermode = 0;
8b006791 8380
1da5b61d 8381 vcpu_put(vcpu);
8b006791
ZX		 8382 return 0;
8383}
8384
d0752060
HB		 8385int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8386{
1393123e 8387 struct fxregs_state *fxsave;
d0752060 8388
1393123e 8389 vcpu_load(vcpu);
d0752060 8390
1393123e 8391 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8392 memcpy(fpu->fpr, fxsave->st_space, 128);
8393 fpu->fcw = fxsave->cwd;
8394 fpu->fsw = fxsave->swd;
8395 fpu->ftwx = fxsave->twd;
8396 fpu->last_opcode = fxsave->fop;
8397 fpu->last_ip = fxsave->rip;
8398 fpu->last_dp = fxsave->rdp;
8399 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8400
1393123e 8401 vcpu_put(vcpu);
d0752060
HB		 8402 return 0;
8403}
8404
8405int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8406{
6a96bc7f
CD		 8407 struct fxregs_state *fxsave;
8408
8409 vcpu_load(vcpu);
8410
8411 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8412
d0752060
HB		 8413 memcpy(fxsave->st_space, fpu->fpr, 128);
8414 fxsave->cwd = fpu->fcw;
8415 fxsave->swd = fpu->fsw;
8416 fxsave->twd = fpu->ftwx;
8417 fxsave->fop = fpu->last_opcode;
8418 fxsave->rip = fpu->last_ip;
8419 fxsave->rdp = fpu->last_dp;
8420 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8421
6a96bc7f 8422 vcpu_put(vcpu);
d0752060
HB		 8423 return 0;
8424}
8425
01643c51
KH		 8426static void store_regs(struct kvm_vcpu *vcpu)
8427{
8428 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8429
8430 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8431 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8432
8433 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8434 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8435
8436 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8437 kvm_vcpu_ioctl_x86_get_vcpu_events(
8438 vcpu, &vcpu->run->s.regs.events);
8439}
8440
8441static int sync_regs(struct kvm_vcpu *vcpu)
8442{
8443 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8444 return -EINVAL;
8445
8446 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8447 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8448 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8449 }
8450 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8451 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8452 return -EINVAL;
8453 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8454 }
8455 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8456 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8457 vcpu, &vcpu->run->s.regs.events))
8458 return -EINVAL;
8459 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8460 }
8461
8462 return 0;
8463}
8464
0ee6a517 8465static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8466{
bf935b0b 8467 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8468 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8469 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8470 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8471
2acf923e
DC		 8472 /*
8473 * Ensure guest xcr0 is valid for loading
8474 */
d91cab78 8475 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8476
ad312c7c 8477 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8478}
d0752060 8479
e9b11c17
ZX		 8480void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8481{
bd768e14
IY		 8482 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8483
12f9a48f 8484 kvmclock_reset(vcpu);
7f1ea208 8485
e9b11c17 8486 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8487 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8488}
8489
8490struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8491 unsigned int id)
8492{
c447e76b
LL		 8493 struct kvm_vcpu *vcpu;
8494
b0c39dc6 8495 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8496 printk_once(KERN_WARNING
8497 "kvm: SMP vm created on host with unstable TSC; "
8498 "guest TSC will not be reliable\n");
c447e76b
LL		 8499
8500 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8501
c447e76b 8502 return vcpu;
26e5215f 8503}
e9b11c17 8504
26e5215f
AK		 8505int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8506{
19efffa2 8507 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8508 vcpu_load(vcpu);
d28bc9dd 8509 kvm_vcpu_reset(vcpu, false);
e1732991 8510 kvm_init_mmu(vcpu, false);
e9b11c17 8511 vcpu_put(vcpu);
ec7660cc 8512 return 0;
e9b11c17
ZX		 8513}
8514
31928aa5 8515void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8516{
8fe8ab46 8517 struct msr_data msr;
332967a3 8518 struct kvm *kvm = vcpu->kvm;
42897d86 8519
d3457c87
RK		 8520 kvm_hv_vcpu_postcreate(vcpu);
8521
ec7660cc 8522 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8523 return;
ec7660cc 8524 vcpu_load(vcpu);
8fe8ab46
WA		 8525 msr.data = 0x0;
8526 msr.index = MSR_IA32_TSC;
8527 msr.host_initiated = true;
8528 kvm_write_tsc(vcpu, &msr);
42897d86 8529 vcpu_put(vcpu);
ec7660cc 8530 mutex_unlock(&vcpu->mutex);
42897d86 8531
630994b3
MT		 8532 if (!kvmclock_periodic_sync)
8533 return;
8534
332967a3
AJ		 8535 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8536 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8537}
8538
d40ccc62 8539void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8540{
344d9588
GN		 8541 vcpu->arch.apf.msr_val = 0;
8542
ec7660cc 8543 vcpu_load(vcpu);
e9b11c17
ZX		 8544 kvm_mmu_unload(vcpu);
8545 vcpu_put(vcpu);
8546
8547 kvm_x86_ops->vcpu_free(vcpu);
8548}
8549
d28bc9dd 8550void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8551{
b7e31be3
RK		 8552 kvm_lapic_reset(vcpu, init_event);
8553
e69fab5d
PB		 8554 vcpu->arch.hflags = 0;
8555
c43203ca 8556 vcpu->arch.smi_pending = 0;
52797bf9 8557 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8558 atomic_set(&vcpu->arch.nmi_queued, 0);
8559 vcpu->arch.nmi_pending = 0;
448fa4a9 8560 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8561 kvm_clear_interrupt_queue(vcpu);
8562 kvm_clear_exception_queue(vcpu);
664f8e26 8563 vcpu->arch.exception.pending = false;
448fa4a9 8564
42dbaa5a 8565 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8566 kvm_update_dr0123(vcpu);
6f43ed01 8567 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8568 kvm_update_dr6(vcpu);
42dbaa5a 8569 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8570 kvm_update_dr7(vcpu);
42dbaa5a 8571
1119022c
NA		 8572 vcpu->arch.cr2 = 0;
8573
3842d135 8574 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8575 vcpu->arch.apf.msr_val = 0;
c9aaa895 8576 vcpu->arch.st.msr_val = 0;
3842d135 8577
12f9a48f
GC		 8578 kvmclock_reset(vcpu);
8579
af585b92
GN		 8580 kvm_clear_async_pf_completion_queue(vcpu);
8581 kvm_async_pf_hash_reset(vcpu);
8582 vcpu->arch.apf.halted = false;
3842d135 8583
a554d207
WL		 8584 if (kvm_mpx_supported()) {
8585 void *mpx_state_buffer;
8586
8587 /*
8588 * To avoid have the INIT path from kvm_apic_has_events() that be
8589 * called with loaded FPU and does not let userspace fix the state.
8590 */
f775b13e
RR		 8591 if (init_event)
8592 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8593 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8594 XFEATURE_MASK_BNDREGS);
8595 if (mpx_state_buffer)
8596 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8597 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8598 XFEATURE_MASK_BNDCSR);
8599 if (mpx_state_buffer)
8600 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8601 if (init_event)
8602 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8603 }
8604
64d60670 8605 if (!init_event) {
d28bc9dd 8606 kvm_pmu_reset(vcpu);
64d60670 8607 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8608
8609 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8610 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8611
8612 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8613 }
f5132b01 8614
66f7b72e
JS		 8615 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8616 vcpu->arch.regs_avail = ~0;
8617 vcpu->arch.regs_dirty = ~0;
8618
a554d207
WL		 8619 vcpu->arch.ia32_xss = 0;
8620
d28bc9dd 8621 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8622}
8623
2b4a273b 8624void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8625{
8626 struct kvm_segment cs;
8627
8628 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8629 cs.selector = vector << 8;
8630 cs.base = vector << 12;
8631 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8632 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8633}
8634
13a34e06 8635int kvm_arch_hardware_enable(void)
e9b11c17 8636{
ca84d1a2
ZA		 8637 struct kvm *kvm;
8638 struct kvm_vcpu *vcpu;
8639 int i;
0dd6a6ed
ZA		 8640 int ret;
8641 u64 local_tsc;
8642 u64 max_tsc = 0;
8643 bool stable, backwards_tsc = false;
18863bdd
AK		 8644
8645 kvm_shared_msr_cpu_online();
13a34e06 8646 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8647 if (ret != 0)
8648 return ret;
8649
4ea1636b 8650 local_tsc = rdtsc();
b0c39dc6 8651 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8652 list_for_each_entry(kvm, &vm_list, vm_list) {
8653 kvm_for_each_vcpu(i, vcpu, kvm) {
8654 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8655 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8656 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8657 backwards_tsc = true;
8658 if (vcpu->arch.last_host_tsc > max_tsc)
8659 max_tsc = vcpu->arch.last_host_tsc;
8660 }
8661 }
8662 }
8663
8664 /*
8665 * Sometimes, even reliable TSCs go backwards. This happens on
8666 * platforms that reset TSC during suspend or hibernate actions, but
8667 * maintain synchronization. We must compensate. Fortunately, we can
8668 * detect that condition here, which happens early in CPU bringup,
8669 * before any KVM threads can be running. Unfortunately, we can't
8670 * bring the TSCs fully up to date with real time, as we aren't yet far
8671 * enough into CPU bringup that we know how much real time has actually
108b249c 8672 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8673 * variables that haven't been updated yet.
8674 *
8675 * So we simply find the maximum observed TSC above, then record the
8676 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8677 * the adjustment will be applied. Note that we accumulate
8678 * adjustments, in case multiple suspend cycles happen before some VCPU
8679 * gets a chance to run again. In the event that no KVM threads get a
8680 * chance to run, we will miss the entire elapsed period, as we'll have
8681 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8682 * loose cycle time. This isn't too big a deal, since the loss will be
8683 * uniform across all VCPUs (not to mention the scenario is extremely
8684 * unlikely). It is possible that a second hibernate recovery happens
8685 * much faster than a first, causing the observed TSC here to be
8686 * smaller; this would require additional padding adjustment, which is
8687 * why we set last_host_tsc to the local tsc observed here.
8688 *
8689 * N.B. - this code below runs only on platforms with reliable TSC,
8690 * as that is the only way backwards_tsc is set above. Also note
8691 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8692 * have the same delta_cyc adjustment applied if backwards_tsc
8693 * is detected. Note further, this adjustment is only done once,
8694 * as we reset last_host_tsc on all VCPUs to stop this from being
8695 * called multiple times (one for each physical CPU bringup).
8696 *
4a969980 8697 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8698 * will be compensated by the logic in vcpu_load, which sets the TSC to
8699 * catchup mode. This will catchup all VCPUs to real time, but cannot
8700 * guarantee that they stay in perfect synchronization.
8701 */
8702 if (backwards_tsc) {
8703 u64 delta_cyc = max_tsc - local_tsc;
8704 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8705 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8706 kvm_for_each_vcpu(i, vcpu, kvm) {
8707 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8708 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8709 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8710 }
8711
8712 /*
8713 * We have to disable TSC offset matching.. if you were
8714 * booting a VM while issuing an S4 host suspend....
8715 * you may have some problem. Solving this issue is
8716 * left as an exercise to the reader.
8717 */
8718 kvm->arch.last_tsc_nsec = 0;
8719 kvm->arch.last_tsc_write = 0;
8720 }
8721
8722 }
8723 return 0;
e9b11c17
ZX		 8724}
8725
13a34e06 8726void kvm_arch_hardware_disable(void)
e9b11c17 8727{
13a34e06
RK		 8728 kvm_x86_ops->hardware_disable();
8729 drop_user_return_notifiers();
e9b11c17
ZX		 8730}
8731
8732int kvm_arch_hardware_setup(void)
8733{
9e9c3fe4
NA		 8734 int r;
8735
8736 r = kvm_x86_ops->hardware_setup();
8737 if (r != 0)
8738 return r;
8739
35181e86
HZ		 8740 if (kvm_has_tsc_control) {
8741 /*
8742 * Make sure the user can only configure tsc_khz values that
8743 * fit into a signed integer.
273ba457 8744 * A min value is not calculated because it will always
35181e86
HZ		 8745 * be 1 on all machines.
8746 */
8747 u64 max = min(0x7fffffffULL,
8748 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8749 kvm_max_guest_tsc_khz = max;
8750
ad721883 8751 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8752 }
ad721883 8753
9e9c3fe4
NA		 8754 kvm_init_msr_list();
8755 return 0;
e9b11c17
ZX		 8756}
8757
8758void kvm_arch_hardware_unsetup(void)
8759{
8760 kvm_x86_ops->hardware_unsetup();
8761}
8762
8763void kvm_arch_check_processor_compat(void *rtn)
8764{
8765 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8766}
8767
8768bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8769{
8770 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8771}
8772EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8773
8774bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8775{
8776 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8777}
8778
54e9818f 8779struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8780EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8781
e9b11c17
ZX		 8782int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8783{
8784 struct page *page;
e9b11c17
ZX		 8785 int r;
8786
b2a05fef 8787 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8788 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8789 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8790 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8791 else
a4535290 8792 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8793
8794 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8795 if (!page) {
8796 r = -ENOMEM;
8797 goto fail;
8798 }
ad312c7c 8799 vcpu->arch.pio_data = page_address(page);
e9b11c17 8800
cc578287 8801 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8802
e9b11c17
ZX		 8803 r = kvm_mmu_create(vcpu);
8804 if (r < 0)
8805 goto fail_free_pio_data;
8806
26de7988 8807 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8808 r = kvm_create_lapic(vcpu);
8809 if (r < 0)
8810 goto fail_mmu_destroy;
54e9818f
GN		 8811 } else
8812 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8813
890ca9ae
HY		 8814 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8815 GFP_KERNEL);
8816 if (!vcpu->arch.mce_banks) {
8817 r = -ENOMEM;
443c39bc 8818 goto fail_free_lapic;
890ca9ae
HY		 8819 }
8820 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8821
f1797359
WY		 8822 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8823 r = -ENOMEM;
f5f48ee1 8824 goto fail_free_mce_banks;
f1797359 8825 }
f5f48ee1 8826
0ee6a517 8827 fx_init(vcpu);
66f7b72e 8828
4344ee98 8829 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8830
5a4f55cd
EK		 8831 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8832
74545705
RK		 8833 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8834
af585b92 8835 kvm_async_pf_hash_reset(vcpu);
f5132b01 8836 kvm_pmu_init(vcpu);
af585b92 8837
1c1a9ce9 8838 vcpu->arch.pending_external_vector = -1;
de63ad4c 8839 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8840
5c919412
AS		 8841 kvm_hv_vcpu_init(vcpu);
8842
e9b11c17 8843 return 0;
0ee6a517 8844
f5f48ee1
SY		 8845fail_free_mce_banks:
8846 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8847fail_free_lapic:
8848 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8849fail_mmu_destroy:
8850 kvm_mmu_destroy(vcpu);
8851fail_free_pio_data:
ad312c7c 8852 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8853fail:
8854 return r;
8855}
8856
8857void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8858{
f656ce01
MT		 8859 int idx;
8860
1f4b34f8 8861 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8862 kvm_pmu_destroy(vcpu);
36cb93fd 8863 kfree(vcpu->arch.mce_banks);
e9b11c17 8864 kvm_free_lapic(vcpu);
f656ce01 8865 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8866 kvm_mmu_destroy(vcpu);
f656ce01 8867 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8868 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8869 if (!lapic_in_kernel(vcpu))
54e9818f 8870 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8871}
d19a9cd2 8872
e790d9ef
RK		 8873void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8874{
c595ceee 8875 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 8876 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8877}
8878
e08b9637 8879int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8880{
e08b9637
CO		 8881 if (type)
8882 return -EINVAL;
8883
6ef768fa 8884 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8885 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8886 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8887 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8888 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8889
5550af4d
SY		 8890 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8891 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8892 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8893 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8894 &kvm->arch.irq_sources_bitmap);
5550af4d 8895
038f8c11 8896 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8897 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8898 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8899
108b249c 8900 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8901 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8902
6fbbde9a
DS		 8903 kvm->arch.guest_can_read_msr_platform_info = true;
8904
7e44e449 8905 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8906 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8907
cbc0236a 8908 kvm_hv_init_vm(kvm);
0eb05bf2 8909 kvm_page_track_init(kvm);
13d268ca 8910 kvm_mmu_init_vm(kvm);
0eb05bf2 8911
03543133
SS		 8912 if (kvm_x86_ops->vm_init)
8913 return kvm_x86_ops->vm_init(kvm);
8914
d89f5eff 8915 return 0;
d19a9cd2
ZX		 8916}
8917
8918static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8919{
ec7660cc 8920 vcpu_load(vcpu);
d19a9cd2
ZX		 8921 kvm_mmu_unload(vcpu);
8922 vcpu_put(vcpu);
8923}
8924
8925static void kvm_free_vcpus(struct kvm *kvm)
8926{
8927 unsigned int i;
988a2cae 8928 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8929
8930 /*
8931 * Unpin any mmu pages first.
8932 */
af585b92
GN		 8933 kvm_for_each_vcpu(i, vcpu, kvm) {
8934 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8935 kvm_unload_vcpu_mmu(vcpu);
af585b92 8936 }
988a2cae
GN		 8937 kvm_for_each_vcpu(i, vcpu, kvm)
8938 kvm_arch_vcpu_free(vcpu);
8939
8940 mutex_lock(&kvm->lock);
8941 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8942 kvm->vcpus[i] = NULL;
d19a9cd2 8943
988a2cae
GN		 8944 atomic_set(&kvm->online_vcpus, 0);
8945 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8946}
8947
ad8ba2cd
SY		 8948void kvm_arch_sync_events(struct kvm *kvm)
8949{
332967a3 8950 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8951 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8952 kvm_free_pit(kvm);
ad8ba2cd
SY		 8953}
8954
1d8007bd 8955int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8956{
8957 int i, r;
25188b99 8958 unsigned long hva;
f0d648bd
PB		 8959 struct kvm_memslots *slots = kvm_memslots(kvm);
8960 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8961
8962 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8963 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8964 return -EINVAL;
9da0e4d5 8965
f0d648bd
PB		 8966 slot = id_to_memslot(slots, id);
8967 if (size) {
b21629da 8968 if (slot->npages)
f0d648bd
PB		 8969 return -EEXIST;
8970
8971 /*
8972 * MAP_SHARED to prevent internal slot pages from being moved
8973 * by fork()/COW.
8974 */
8975 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8976 MAP_SHARED | MAP_ANONYMOUS, 0);
8977 if (IS_ERR((void *)hva))
8978 return PTR_ERR((void *)hva);
8979 } else {
8980 if (!slot->npages)
8981 return 0;
8982
8983 hva = 0;
8984 }
8985
8986 old = *slot;
9da0e4d5 8987 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8988 struct kvm_userspace_memory_region m;
9da0e4d5 8989
1d8007bd
PB		 8990 m.slot = id | (i << 16);
8991 m.flags = 0;
8992 m.guest_phys_addr = gpa;
f0d648bd 8993 m.userspace_addr = hva;
1d8007bd 8994 m.memory_size = size;
9da0e4d5
PB		 8995 r = __kvm_set_memory_region(kvm, &m);
8996 if (r < 0)
8997 return r;
8998 }
8999
103c763c
EB		 9000 if (!size)
9001 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9002
9da0e4d5
PB		 9003 return 0;
9004}
9005EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9006
1d8007bd 9007int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9008{
9009 int r;
9010
9011 mutex_lock(&kvm->slots_lock);
1d8007bd 9012 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9013 mutex_unlock(&kvm->slots_lock);
9014
9015 return r;
9016}
9017EXPORT_SYMBOL_GPL(x86_set_memory_region);
9018
d19a9cd2
ZX		 9019void kvm_arch_destroy_vm(struct kvm *kvm)
9020{
27469d29
AH		 9021 if (current->mm == kvm->mm) {
9022 /*
9023 * Free memory regions allocated on behalf of userspace,
9024 * unless the the memory map has changed due to process exit
9025 * or fd copying.
9026 */
1d8007bd
PB		 9027 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9028 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9029 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9030 }
03543133
SS		 9031 if (kvm_x86_ops->vm_destroy)
9032 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9033 kvm_pic_destroy(kvm);
9034 kvm_ioapic_destroy(kvm);
d19a9cd2 9035 kvm_free_vcpus(kvm);
af1bae54 9036 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 9037 kvm_mmu_uninit_vm(kvm);
2beb6dad 9038 kvm_page_track_cleanup(kvm);
cbc0236a 9039 kvm_hv_destroy_vm(kvm);
d19a9cd2 9040}
0de10343 9041
5587027c 9042void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9043 struct kvm_memory_slot *dont)
9044{
9045 int i;
9046
d89cc617
TY		 9047 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9048 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9049 kvfree(free->arch.rmap[i]);
d89cc617 9050 free->arch.rmap[i] = NULL;
77d11309 9051 }
d89cc617
TY		 9052 if (i == 0)
9053 continue;
9054
9055 if (!dont || free->arch.lpage_info[i - 1] !=
9056 dont->arch.lpage_info[i - 1]) {
548ef284 9057 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9058 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9059 }
9060 }
21ebbeda
XG		 9061
9062 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9063}
9064
5587027c
AK		 9065int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9066 unsigned long npages)
db3fe4eb
TY		 9067{
9068 int i;
9069
d89cc617 9070 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9071 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9072 unsigned long ugfn;
9073 int lpages;
d89cc617 9074 int level = i + 1;
db3fe4eb
TY		 9075
9076 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9077 slot->base_gfn, level) + 1;
9078
d89cc617 9079 slot->arch.rmap[i] =
778e1cdd
KC		 9080 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9081 GFP_KERNEL);
d89cc617 9082 if (!slot->arch.rmap[i])
77d11309 9083 goto out_free;
d89cc617
TY		 9084 if (i == 0)
9085 continue;
77d11309 9086
778e1cdd 9087 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
92f94f1e 9088 if (!linfo)
db3fe4eb
TY		 9089 goto out_free;
9090
92f94f1e
XG		 9091 slot->arch.lpage_info[i - 1] = linfo;
9092
db3fe4eb 9093 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9094 linfo[0].disallow_lpage = 1;
db3fe4eb 9095 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9096 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9097 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9098 /*
9099 * If the gfn and userspace address are not aligned wrt each
9100 * other, or if explicitly asked to, disable large page
9101 * support for this slot
9102 */
9103 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9104 !kvm_largepages_enabled()) {
9105 unsigned long j;
9106
9107 for (j = 0; j < lpages; ++j)
92f94f1e 9108 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9109 }
9110 }
9111
21ebbeda
XG		 9112 if (kvm_page_track_create_memslot(slot, npages))
9113 goto out_free;
9114
db3fe4eb
TY		 9115 return 0;
9116
9117out_free:
d89cc617 9118 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9119 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9120 slot->arch.rmap[i] = NULL;
9121 if (i == 0)
9122 continue;
9123
548ef284 9124 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9125 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9126 }
9127 return -ENOMEM;
9128}
9129
15f46015 9130void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 9131{
e6dff7d1
TY		 9132 /*
9133 * memslots->generation has been incremented.
9134 * mmio generation may have reached its maximum value.
9135 */
54bf36aa 9136 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 9137}
9138
f7784b8e
MT		 9139int kvm_arch_prepare_memory_region(struct kvm *kvm,
9140 struct kvm_memory_slot *memslot,
09170a49 9141 const struct kvm_userspace_memory_region *mem,
7b6195a9 9142 enum kvm_mr_change change)
0de10343 9143{
f7784b8e
MT		 9144 return 0;
9145}
9146
88178fd4
KH		 9147static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9148 struct kvm_memory_slot *new)
9149{
9150 /* Still write protect RO slot */
9151 if (new->flags & KVM_MEM_READONLY) {
9152 kvm_mmu_slot_remove_write_access(kvm, new);
9153 return;
9154 }
9155
9156 /*
9157 * Call kvm_x86_ops dirty logging hooks when they are valid.
9158 *
9159 * kvm_x86_ops->slot_disable_log_dirty is called when:
9160 *
9161 * - KVM_MR_CREATE with dirty logging is disabled
9162 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9163 *
9164 * The reason is, in case of PML, we need to set D-bit for any slots
9165 * with dirty logging disabled in order to eliminate unnecessary GPA
9166 * logging in PML buffer (and potential PML buffer full VMEXT). This
9167 * guarantees leaving PML enabled during guest's lifetime won't have
9168 * any additonal overhead from PML when guest is running with dirty
9169 * logging disabled for memory slots.
9170 *
9171 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9172 * to dirty logging mode.
9173 *
9174 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9175 *
9176 * In case of write protect:
9177 *
9178 * Write protect all pages for dirty logging.
9179 *
9180 * All the sptes including the large sptes which point to this
9181 * slot are set to readonly. We can not create any new large
9182 * spte on this slot until the end of the logging.
9183 *
9184 * See the comments in fast_page_fault().
9185 */
9186 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9187 if (kvm_x86_ops->slot_enable_log_dirty)
9188 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9189 else
9190 kvm_mmu_slot_remove_write_access(kvm, new);
9191 } else {
9192 if (kvm_x86_ops->slot_disable_log_dirty)
9193 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9194 }
9195}
9196
f7784b8e 9197void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9198 const struct kvm_userspace_memory_region *mem,
8482644a 9199 const struct kvm_memory_slot *old,
f36f3f28 9200 const struct kvm_memory_slot *new,
8482644a 9201 enum kvm_mr_change change)
f7784b8e 9202{
8482644a 9203 int nr_mmu_pages = 0;
f7784b8e 9204
48c0e4e9
XG		 9205 if (!kvm->arch.n_requested_mmu_pages)
9206 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9207
48c0e4e9 9208 if (nr_mmu_pages)
0de10343 9209 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9210
3ea3b7fa
WL		 9211 /*
9212 * Dirty logging tracks sptes in 4k granularity, meaning that large
9213 * sptes have to be split. If live migration is successful, the guest
9214 * in the source machine will be destroyed and large sptes will be
9215 * created in the destination. However, if the guest continues to run
9216 * in the source machine (for example if live migration fails), small
9217 * sptes will remain around and cause bad performance.
9218 *
9219 * Scan sptes if dirty logging has been stopped, dropping those
9220 * which can be collapsed into a single large-page spte. Later
9221 * page faults will create the large-page sptes.
9222 */
9223 if ((change != KVM_MR_DELETE) &&
9224 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9225 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9226 kvm_mmu_zap_collapsible_sptes(kvm, new);
9227
c972f3b1 9228 /*
88178fd4 9229 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9230 *
88178fd4
KH		 9231 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9232 * been zapped so no dirty logging staff is needed for old slot. For
9233 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9234 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9235 *
9236 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9237 */
88178fd4 9238 if (change != KVM_MR_DELETE)
f36f3f28 9239 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9240}
1d737c8a 9241
2df72e9b 9242void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9243{
6ca18b69 9244 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9245}
9246
2df72e9b
MT		 9247void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9248 struct kvm_memory_slot *slot)
9249{
ae7cd873 9250 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9251}
9252
e6c67d8c
LA		 9253static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9254{
9255 return (is_guest_mode(vcpu) &&
9256 kvm_x86_ops->guest_apic_has_interrupt &&
9257 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9258}
9259
5d9bc648
PB		 9260static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9261{
9262 if (!list_empty_careful(&vcpu->async_pf.done))
9263 return true;
9264
9265 if (kvm_apic_has_events(vcpu))
9266 return true;
9267
9268 if (vcpu->arch.pv.pv_unhalted)
9269 return true;
9270
a5f01f8e
WL		 9271 if (vcpu->arch.exception.pending)
9272 return true;
9273
47a66eed
Z		 9274 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9275 (vcpu->arch.nmi_pending &&
9276 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9277 return true;
9278
47a66eed
Z		 9279 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9280 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9281 return true;
9282
5d9bc648 9283 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9284 (kvm_cpu_has_interrupt(vcpu) ||
9285 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9286 return true;
9287
1f4b34f8
AS		 9288 if (kvm_hv_has_stimer_pending(vcpu))
9289 return true;
9290
5d9bc648
PB		 9291 return false;
9292}
9293
1d737c8a
ZX		 9294int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9295{
5d9bc648 9296 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9297}
5736199a 9298
199b5763
LM		 9299bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9300{
de63ad4c 9301 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9302}
9303
b6d33834 9304int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9305{
b6d33834 9306 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9307}
78646121
GN		 9308
9309int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9310{
9311 return kvm_x86_ops->interrupt_allowed(vcpu);
9312}
229456fc 9313
82b32774 9314unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9315{
82b32774
NA		 9316 if (is_64_bit_mode(vcpu))
9317 return kvm_rip_read(vcpu);
9318 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9319 kvm_rip_read(vcpu));
9320}
9321EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9322
82b32774
NA		 9323bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9324{
9325 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9326}
9327EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9328
94fe45da
JK		 9329unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9330{
9331 unsigned long rflags;
9332
9333 rflags = kvm_x86_ops->get_rflags(vcpu);
9334 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9335 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9336 return rflags;
9337}
9338EXPORT_SYMBOL_GPL(kvm_get_rflags);
9339
6addfc42 9340static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9341{
9342 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9343 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9344 rflags |= X86_EFLAGS_TF;
94fe45da 9345 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9346}
9347
9348void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9349{
9350 __kvm_set_rflags(vcpu, rflags);
3842d135 9351 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9352}
9353EXPORT_SYMBOL_GPL(kvm_set_rflags);
9354
56028d08
GN		 9355void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9356{
9357 int r;
9358
44dd3ffa 9359 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9360 work->wakeup_all)
56028d08
GN		 9361 return;
9362
9363 r = kvm_mmu_reload(vcpu);
9364 if (unlikely(r))
9365 return;
9366
44dd3ffa
VK		 9367 if (!vcpu->arch.mmu->direct_map &&
9368 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9369 return;
9370
44dd3ffa 9371 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9372}
9373
af585b92
GN		 9374static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9375{
9376 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9377}
9378
9379static inline u32 kvm_async_pf_next_probe(u32 key)
9380{
9381 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9382}
9383
9384static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9385{
9386 u32 key = kvm_async_pf_hash_fn(gfn);
9387
9388 while (vcpu->arch.apf.gfns[key] != ~0)
9389 key = kvm_async_pf_next_probe(key);
9390
9391 vcpu->arch.apf.gfns[key] = gfn;
9392}
9393
9394static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9395{
9396 int i;
9397 u32 key = kvm_async_pf_hash_fn(gfn);
9398
9399 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9400 (vcpu->arch.apf.gfns[key] != gfn &&
9401 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9402 key = kvm_async_pf_next_probe(key);
9403
9404 return key;
9405}
9406
9407bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9408{
9409 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9410}
9411
9412static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9413{
9414 u32 i, j, k;
9415
9416 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9417 while (true) {
9418 vcpu->arch.apf.gfns[i] = ~0;
9419 do {
9420 j = kvm_async_pf_next_probe(j);
9421 if (vcpu->arch.apf.gfns[j] == ~0)
9422 return;
9423 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9424 /*
9425 * k lies cyclically in ]i,j]
9426 * | i.k.j |
9427 * |....j i.k.| or |.k..j i...|
9428 */
9429 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9430 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9431 i = j;
9432 }
9433}
9434
7c90705b
GN		 9435static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9436{
4e335d9e
PB		 9437
9438 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9439 sizeof(val));
7c90705b
GN		 9440}
9441
9a6e7c39
WL		 9442static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9443{
9444
9445 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9446 sizeof(u32));
9447}
9448
af585b92
GN		 9449void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9450 struct kvm_async_pf *work)
9451{
6389ee94
AK		 9452 struct x86_exception fault;
9453
7c90705b 9454 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9455 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9456
9457 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9458 (vcpu->arch.apf.send_user_only &&
9459 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9460 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9461 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9462 fault.vector = PF_VECTOR;
9463 fault.error_code_valid = true;
9464 fault.error_code = 0;
9465 fault.nested_page_fault = false;
9466 fault.address = work->arch.token;
adfe20fb 9467 fault.async_page_fault = true;
6389ee94 9468 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9469 }
af585b92
GN		 9470}
9471
9472void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9473 struct kvm_async_pf *work)
9474{
6389ee94 9475 struct x86_exception fault;
9a6e7c39 9476 u32 val;
6389ee94 9477
f2e10669 9478 if (work->wakeup_all)
7c90705b
GN		 9479 work->arch.token = ~0; /* broadcast wakeup */
9480 else
9481 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9482 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9483
9a6e7c39
WL		 9484 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9485 !apf_get_user(vcpu, &val)) {
9486 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9487 vcpu->arch.exception.pending &&
9488 vcpu->arch.exception.nr == PF_VECTOR &&
9489 !apf_put_user(vcpu, 0)) {
9490 vcpu->arch.exception.injected = false;
9491 vcpu->arch.exception.pending = false;
9492 vcpu->arch.exception.nr = 0;
9493 vcpu->arch.exception.has_error_code = false;
9494 vcpu->arch.exception.error_code = 0;
c851436a
JM		 9495 vcpu->arch.exception.has_payload = false;
9496 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 9497 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9498 fault.vector = PF_VECTOR;
9499 fault.error_code_valid = true;
9500 fault.error_code = 0;
9501 fault.nested_page_fault = false;
9502 fault.address = work->arch.token;
9503 fault.async_page_fault = true;
9504 kvm_inject_page_fault(vcpu, &fault);
9505 }
7c90705b 9506 }
e6d53e3b 9507 vcpu->arch.apf.halted = false;
a4fa1635 9508 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9509}
9510
9511bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9512{
9513 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9514 return true;
9515 else
9bc1f09f 9516 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9517}
9518
5544eb9b
PB		 9519void kvm_arch_start_assignment(struct kvm *kvm)
9520{
9521 atomic_inc(&kvm->arch.assigned_device_count);
9522}
9523EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9524
9525void kvm_arch_end_assignment(struct kvm *kvm)
9526{
9527 atomic_dec(&kvm->arch.assigned_device_count);
9528}
9529EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9530
9531bool kvm_arch_has_assigned_device(struct kvm *kvm)
9532{
9533 return atomic_read(&kvm->arch.assigned_device_count);
9534}
9535EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9536
e0f0bbc5
AW		 9537void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9538{
9539 atomic_inc(&kvm->arch.noncoherent_dma_count);
9540}
9541EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9542
9543void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9544{
9545 atomic_dec(&kvm->arch.noncoherent_dma_count);
9546}
9547EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9548
9549bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9550{
9551 return atomic_read(&kvm->arch.noncoherent_dma_count);
9552}
9553EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9554
14717e20
AW		 9555bool kvm_arch_has_irq_bypass(void)
9556{
9557 return kvm_x86_ops->update_pi_irte != NULL;
9558}
9559
87276880
FW		 9560int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9561 struct irq_bypass_producer *prod)
9562{
9563 struct kvm_kernel_irqfd *irqfd =
9564 container_of(cons, struct kvm_kernel_irqfd, consumer);
9565
14717e20 9566 irqfd->producer = prod;
87276880 9567
14717e20
AW		 9568 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9569 prod->irq, irqfd->gsi, 1);
87276880
FW		 9570}
9571
9572void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9573 struct irq_bypass_producer *prod)
9574{
9575 int ret;
9576 struct kvm_kernel_irqfd *irqfd =
9577 container_of(cons, struct kvm_kernel_irqfd, consumer);
9578
87276880
FW		 9579 WARN_ON(irqfd->producer != prod);
9580 irqfd->producer = NULL;
9581
9582 /*
9583 * When producer of consumer is unregistered, we change back to
9584 * remapped mode, so we can re-use the current implementation
bb3541f1 9585 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9586 * int this case doesn't want to receive the interrupts.
9587 */
9588 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9589 if (ret)
9590 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9591 " fails: %d\n", irqfd->consumer.token, ret);
9592}
9593
9594int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9595 uint32_t guest_irq, bool set)
9596{
9597 if (!kvm_x86_ops->update_pi_irte)
9598 return -EINVAL;
9599
9600 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9601}
9602
52004014
FW		 9603bool kvm_vector_hashing_enabled(void)
9604{
9605 return vector_hashing;
9606}
9607EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9608
229456fc 9609EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9610EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9611EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9612EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9613EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9614EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9615EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9616EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9617EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9618EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9619EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9620EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9621EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9622EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9623EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9624EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9625EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9626EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9627EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)