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KVM: No need to kick cpu if not in a guest mode
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
aec51dc4
AK		 40#include <trace/events/kvm.h>
41#undef TRACE_INCLUDE_FILE
229456fc
MT		 42#define CREATE_TRACE_POINTS
43#include "trace.h"
043405e1
CO		 44
45#include <asm/uaccess.h>
d825ed0a 46#include <asm/msr.h>
a5f61300 47#include <asm/desc.h>
0bed3b56 48#include <asm/mtrr.h>
890ca9ae 49#include <asm/mce.h>
043405e1 50
313a3dc7 51#define MAX_IO_MSRS 256
a03490ed
CO		 52#define CR0_RESERVED_BITS \
53 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
54 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
55 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
56#define CR4_RESERVED_BITS \
57 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
58 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
59 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
60 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
61
62#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 63
64#define KVM_MAX_MCE_BANKS 32
65#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
66
50a37eb4
JR		 67/* EFER defaults:
68 * - enable syscall per default because its emulated by KVM
69 * - enable LME and LMA per default on 64 bit KVM
70 */
71#ifdef CONFIG_X86_64
72static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
73#else
74static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
75#endif
313a3dc7 76
ba1389b7
AK		 77#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 79
674eea0f
AK		 80static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
81 struct kvm_cpuid_entry2 __user *entries);
82
97896d04 83struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 84EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 85
ed85c068
AP		 86int ignore_msrs = 0;
87module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
88
417bc304 89struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 90 { "pf_fixed", VCPU_STAT(pf_fixed) },
91 { "pf_guest", VCPU_STAT(pf_guest) },
92 { "tlb_flush", VCPU_STAT(tlb_flush) },
93 { "invlpg", VCPU_STAT(invlpg) },
94 { "exits", VCPU_STAT(exits) },
95 { "io_exits", VCPU_STAT(io_exits) },
96 { "mmio_exits", VCPU_STAT(mmio_exits) },
97 { "signal_exits", VCPU_STAT(signal_exits) },
98 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 99 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 100 { "halt_exits", VCPU_STAT(halt_exits) },
101 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 102 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 103 { "request_irq", VCPU_STAT(request_irq_exits) },
104 { "irq_exits", VCPU_STAT(irq_exits) },
105 { "host_state_reload", VCPU_STAT(host_state_reload) },
106 { "efer_reload", VCPU_STAT(efer_reload) },
107 { "fpu_reload", VCPU_STAT(fpu_reload) },
108 { "insn_emulation", VCPU_STAT(insn_emulation) },
109 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 110 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 111 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 112 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
113 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
114 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
115 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
116 { "mmu_flooded", VM_STAT(mmu_flooded) },
117 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 118 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 119 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 120 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 121 { "largepages", VM_STAT(lpages) },
417bc304
HB		 122 { NULL }
123};
124
5fb76f9b
CO		 125unsigned long segment_base(u16 selector)
126{
127 struct descriptor_table gdt;
a5f61300 128 struct desc_struct *d;
5fb76f9b
CO		 129 unsigned long table_base;
130 unsigned long v;
131
132 if (selector == 0)
133 return 0;
134
135 asm("sgdt %0" : "=m"(gdt));
136 table_base = gdt.base;
137
138 if (selector & 4) { /* from ldt */
139 u16 ldt_selector;
140
141 asm("sldt %0" : "=g"(ldt_selector));
142 table_base = segment_base(ldt_selector);
143 }
a5f61300
AK		 144 d = (struct desc_struct *)(table_base + (selector & ~7));
145 v = d->base0 | ((unsigned long)d->base1 << 16) |
146 ((unsigned long)d->base2 << 24);
5fb76f9b 147#ifdef CONFIG_X86_64
a5f61300
AK		 148 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
149 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 150#endif
151 return v;
152}
153EXPORT_SYMBOL_GPL(segment_base);
154
6866b83e
CO		 155u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
156{
157 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 158 return vcpu->arch.apic_base;
6866b83e 159 else
ad312c7c 160 return vcpu->arch.apic_base;
6866b83e
CO		 161}
162EXPORT_SYMBOL_GPL(kvm_get_apic_base);
163
164void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
165{
166 /* TODO: reserve bits check */
167 if (irqchip_in_kernel(vcpu->kvm))
168 kvm_lapic_set_base(vcpu, data);
169 else
ad312c7c 170 vcpu->arch.apic_base = data;
6866b83e
CO		 171}
172EXPORT_SYMBOL_GPL(kvm_set_apic_base);
173
298101da
AK		 174void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
175{
ad312c7c
ZX		 176 WARN_ON(vcpu->arch.exception.pending);
177 vcpu->arch.exception.pending = true;
178 vcpu->arch.exception.has_error_code = false;
179 vcpu->arch.exception.nr = nr;
298101da
AK		 180}
181EXPORT_SYMBOL_GPL(kvm_queue_exception);
182
c3c91fee
AK		 183void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
184 u32 error_code)
185{
186 ++vcpu->stat.pf_guest;
d8017474 187
71c4dfaf 188 if (vcpu->arch.exception.pending) {
6edf14d8
GN		 189 switch(vcpu->arch.exception.nr) {
190 case DF_VECTOR:
71c4dfaf
JR		 191 /* triple fault -> shutdown */
192 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
6edf14d8
GN		 193 return;
194 case PF_VECTOR:
195 vcpu->arch.exception.nr = DF_VECTOR;
196 vcpu->arch.exception.error_code = 0;
197 return;
198 default:
199 /* replace previous exception with a new one in a hope
200 that instruction re-execution will regenerate lost
201 exception */
202 vcpu->arch.exception.pending = false;
203 break;
71c4dfaf 204 }
c3c91fee 205 }
ad312c7c 206 vcpu->arch.cr2 = addr;
c3c91fee
AK		 207 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
208}
209
3419ffc8
SY		 210void kvm_inject_nmi(struct kvm_vcpu *vcpu)
211{
212 vcpu->arch.nmi_pending = 1;
213}
214EXPORT_SYMBOL_GPL(kvm_inject_nmi);
215
298101da
AK		 216void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
217{
ad312c7c
ZX		 218 WARN_ON(vcpu->arch.exception.pending);
219 vcpu->arch.exception.pending = true;
220 vcpu->arch.exception.has_error_code = true;
221 vcpu->arch.exception.nr = nr;
222 vcpu->arch.exception.error_code = error_code;
298101da
AK		 223}
224EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
225
226static void __queue_exception(struct kvm_vcpu *vcpu)
227{
ad312c7c
ZX		 228 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
229 vcpu->arch.exception.has_error_code,
230 vcpu->arch.exception.error_code);
298101da
AK		 231}
232
a03490ed
CO		 233/*
234 * Load the pae pdptrs. Return true is they are all valid.
235 */
236int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
237{
238 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
239 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
240 int i;
241 int ret;
ad312c7c 242 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 243
a03490ed
CO		 244 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
245 offset * sizeof(u64), sizeof(pdpte));
246 if (ret < 0) {
247 ret = 0;
248 goto out;
249 }
250 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 251 if (is_present_gpte(pdpte[i]) &&
20c466b5 252 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 253 ret = 0;
254 goto out;
255 }
256 }
257 ret = 1;
258
ad312c7c 259 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 260 __set_bit(VCPU_EXREG_PDPTR,
261 (unsigned long *)&vcpu->arch.regs_avail);
262 __set_bit(VCPU_EXREG_PDPTR,
263 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 264out:
a03490ed
CO		 265
266 return ret;
267}
cc4b6871 268EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 269
d835dfec
AK		 270static bool pdptrs_changed(struct kvm_vcpu *vcpu)
271{
ad312c7c 272 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 273 bool changed = true;
274 int r;
275
276 if (is_long_mode(vcpu) || !is_pae(vcpu))
277 return false;
278
6de4f3ad
AK		 279 if (!test_bit(VCPU_EXREG_PDPTR,
280 (unsigned long *)&vcpu->arch.regs_avail))
281 return true;
282
ad312c7c 283 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 284 if (r < 0)
285 goto out;
ad312c7c 286 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 287out:
d835dfec
AK		 288
289 return changed;
290}
291
2d3ad1f4 292void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 293{
294 if (cr0 & CR0_RESERVED_BITS) {
295 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 296 cr0, vcpu->arch.cr0);
c1a5d4f9 297 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 298 return;
299 }
300
301 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
302 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 303 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 304 return;
305 }
306
307 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
308 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
309 "and a clear PE flag\n");
c1a5d4f9 310 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 311 return;
312 }
313
314 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
315#ifdef CONFIG_X86_64
ad312c7c 316 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 317 int cs_db, cs_l;
318
319 if (!is_pae(vcpu)) {
320 printk(KERN_DEBUG "set_cr0: #GP, start paging "
321 "in long mode while PAE is disabled\n");
c1a5d4f9 322 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 323 return;
324 }
325 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
326 if (cs_l) {
327 printk(KERN_DEBUG "set_cr0: #GP, start paging "
328 "in long mode while CS.L == 1\n");
c1a5d4f9 329 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 330 return;
331
332 }
333 } else
334#endif
ad312c7c 335 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 336 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
337 "reserved bits\n");
c1a5d4f9 338 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 339 return;
340 }
341
342 }
343
344 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 345 vcpu->arch.cr0 = cr0;
a03490ed 346
a03490ed 347 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 348 return;
349}
2d3ad1f4 350EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 351
2d3ad1f4 352void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 353{
2d3ad1f4 354 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 355}
2d3ad1f4 356EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 357
2d3ad1f4 358void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 359{
a2edf57f
AK		 360 unsigned long old_cr4 = vcpu->arch.cr4;
361 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
362
a03490ed
CO		 363 if (cr4 & CR4_RESERVED_BITS) {
364 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 365 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 366 return;
367 }
368
369 if (is_long_mode(vcpu)) {
370 if (!(cr4 & X86_CR4_PAE)) {
371 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
372 "in long mode\n");
c1a5d4f9 373 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 374 return;
375 }
a2edf57f
AK		 376 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
377 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 378 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 379 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 380 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 381 return;
382 }
383
384 if (cr4 & X86_CR4_VMXE) {
385 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 386 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 387 return;
388 }
389 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 390 vcpu->arch.cr4 = cr4;
5a41accd 391 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 392 kvm_mmu_reset_context(vcpu);
a03490ed 393}
2d3ad1f4 394EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 395
2d3ad1f4 396void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 397{
ad312c7c 398 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 399 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 400 kvm_mmu_flush_tlb(vcpu);
401 return;
402 }
403
a03490ed
CO		 404 if (is_long_mode(vcpu)) {
405 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
406 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 407 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 408 return;
409 }
410 } else {
411 if (is_pae(vcpu)) {
412 if (cr3 & CR3_PAE_RESERVED_BITS) {
413 printk(KERN_DEBUG
414 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 415 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 416 return;
417 }
418 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
419 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
420 "reserved bits\n");
c1a5d4f9 421 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 422 return;
423 }
424 }
425 /*
426 * We don't check reserved bits in nonpae mode, because
427 * this isn't enforced, and VMware depends on this.
428 */
429 }
430
a03490ed
CO		 431 /*
432 * Does the new cr3 value map to physical memory? (Note, we
433 * catch an invalid cr3 even in real-mode, because it would
434 * cause trouble later on when we turn on paging anyway.)
435 *
436 * A real CPU would silently accept an invalid cr3 and would
437 * attempt to use it - with largely undefined (and often hard
438 * to debug) behavior on the guest side.
439 */
440 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 441 kvm_inject_gp(vcpu, 0);
a03490ed 442 else {
ad312c7c
ZX		 443 vcpu->arch.cr3 = cr3;
444 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 445 }
a03490ed 446}
2d3ad1f4 447EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 448
2d3ad1f4 449void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 450{
451 if (cr8 & CR8_RESERVED_BITS) {
452 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 453 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 454 return;
455 }
456 if (irqchip_in_kernel(vcpu->kvm))
457 kvm_lapic_set_tpr(vcpu, cr8);
458 else
ad312c7c 459 vcpu->arch.cr8 = cr8;
a03490ed 460}
2d3ad1f4 461EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 462
2d3ad1f4 463unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 464{
465 if (irqchip_in_kernel(vcpu->kvm))
466 return kvm_lapic_get_cr8(vcpu);
467 else
ad312c7c 468 return vcpu->arch.cr8;
a03490ed 469}
2d3ad1f4 470EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 471
d8017474
AG		 472static inline u32 bit(int bitno)
473{
474 return 1 << (bitno & 31);
475}
476
043405e1
CO		 477/*
478 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
479 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
480 *
481 * This list is modified at module load time to reflect the
482 * capabilities of the host cpu.
483 */
484static u32 msrs_to_save[] = {
485 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
486 MSR_K6_STAR,
487#ifdef CONFIG_X86_64
488 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
489#endif
af24a4e4 490 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 491 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 492};
493
494static unsigned num_msrs_to_save;
495
496static u32 emulated_msrs[] = {
497 MSR_IA32_MISC_ENABLE,
498};
499
15c4a640
CO		 500static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
501{
f2b4b7dd 502 if (efer & efer_reserved_bits) {
15c4a640
CO		 503 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
504 efer);
c1a5d4f9 505 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 506 return;
507 }
508
509 if (is_paging(vcpu)
ad312c7c 510 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 511 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 512 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 513 return;
514 }
515
1b2fd70c
AG		 516 if (efer & EFER_FFXSR) {
517 struct kvm_cpuid_entry2 *feat;
518
519 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
520 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
521 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
522 kvm_inject_gp(vcpu, 0);
523 return;
524 }
525 }
526
d8017474
AG		 527 if (efer & EFER_SVME) {
528 struct kvm_cpuid_entry2 *feat;
529
530 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
531 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
532 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
533 kvm_inject_gp(vcpu, 0);
534 return;
535 }
536 }
537
15c4a640
CO		 538 kvm_x86_ops->set_efer(vcpu, efer);
539
540 efer &= ~EFER_LMA;
ad312c7c 541 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 542
ad312c7c 543 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 544
545 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
546 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 547}
548
f2b4b7dd
JR		 549void kvm_enable_efer_bits(u64 mask)
550{
551 efer_reserved_bits &= ~mask;
552}
553EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
554
555
15c4a640
CO		 556/*
557 * Writes msr value into into the appropriate "register".
558 * Returns 0 on success, non-0 otherwise.
559 * Assumes vcpu_load() was already called.
560 */
561int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
562{
563 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
564}
565
313a3dc7
CO		 566/*
567 * Adapt set_msr() to msr_io()'s calling convention
568 */
569static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
570{
571 return kvm_set_msr(vcpu, index, *data);
572}
573
18068523
GOC		 574static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
575{
576 static int version;
50d0a0f9
GH		 577 struct pvclock_wall_clock wc;
578 struct timespec now, sys, boot;
18068523
GOC		 579
580 if (!wall_clock)
581 return;
582
583 version++;
584
18068523
GOC		 585 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
586
50d0a0f9
GH		 587 /*
588 * The guest calculates current wall clock time by adding
589 * system time (updated by kvm_write_guest_time below) to the
590 * wall clock specified here. guest system time equals host
591 * system time for us, thus we must fill in host boot time here.
592 */
593 now = current_kernel_time();
594 ktime_get_ts(&sys);
595 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
596
597 wc.sec = boot.tv_sec;
598 wc.nsec = boot.tv_nsec;
599 wc.version = version;
18068523
GOC		 600
601 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
602
603 version++;
604 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 605}
606
50d0a0f9
GH		 607static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
608{
609 uint32_t quotient, remainder;
610
611 /* Don't try to replace with do_div(), this one calculates
612 * "(dividend << 32) / divisor" */
613 __asm__ ( "divl %4"
614 : "=a" (quotient), "=d" (remainder)
615 : "0" (0), "1" (dividend), "r" (divisor) );
616 return quotient;
617}
618
619static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
620{
621 uint64_t nsecs = 1000000000LL;
622 int32_t shift = 0;
623 uint64_t tps64;
624 uint32_t tps32;
625
626 tps64 = tsc_khz * 1000LL;
627 while (tps64 > nsecs*2) {
628 tps64 >>= 1;
629 shift--;
630 }
631
632 tps32 = (uint32_t)tps64;
633 while (tps32 <= (uint32_t)nsecs) {
634 tps32 <<= 1;
635 shift++;
636 }
637
638 hv_clock->tsc_shift = shift;
639 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
640
641 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 642 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 643 hv_clock->tsc_to_system_mul);
644}
645
c8076604
GH		 646static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
647
18068523
GOC		 648static void kvm_write_guest_time(struct kvm_vcpu *v)
649{
650 struct timespec ts;
651 unsigned long flags;
652 struct kvm_vcpu_arch *vcpu = &v->arch;
653 void *shared_kaddr;
463656c0 654 unsigned long this_tsc_khz;
18068523
GOC		 655
656 if ((!vcpu->time_page))
657 return;
658
463656c0
AK		 659 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
660 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
661 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
662 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 663 }
463656c0 664 put_cpu_var(cpu_tsc_khz);
50d0a0f9 665
18068523
GOC		 666 /* Keep irq disabled to prevent changes to the clock */
667 local_irq_save(flags);
af24a4e4 668 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 669 ktime_get_ts(&ts);
670 local_irq_restore(flags);
671
672 /* With all the info we got, fill in the values */
673
674 vcpu->hv_clock.system_time = ts.tv_nsec +
675 (NSEC_PER_SEC * (u64)ts.tv_sec);
676 /*
677 * The interface expects us to write an even number signaling that the
678 * update is finished. Since the guest won't see the intermediate
50d0a0f9 679 * state, we just increase by 2 at the end.
18068523 680 */
50d0a0f9 681 vcpu->hv_clock.version += 2;
18068523
GOC		 682
683 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
684
685 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 686 sizeof(vcpu->hv_clock));
18068523
GOC		 687
688 kunmap_atomic(shared_kaddr, KM_USER0);
689
690 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
691}
692
c8076604
GH		 693static int kvm_request_guest_time_update(struct kvm_vcpu *v)
694{
695 struct kvm_vcpu_arch *vcpu = &v->arch;
696
697 if (!vcpu->time_page)
698 return 0;
699 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
700 return 1;
701}
702
9ba075a6
AK		 703static bool msr_mtrr_valid(unsigned msr)
704{
705 switch (msr) {
706 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
707 case MSR_MTRRfix64K_00000:
708 case MSR_MTRRfix16K_80000:
709 case MSR_MTRRfix16K_A0000:
710 case MSR_MTRRfix4K_C0000:
711 case MSR_MTRRfix4K_C8000:
712 case MSR_MTRRfix4K_D0000:
713 case MSR_MTRRfix4K_D8000:
714 case MSR_MTRRfix4K_E0000:
715 case MSR_MTRRfix4K_E8000:
716 case MSR_MTRRfix4K_F0000:
717 case MSR_MTRRfix4K_F8000:
718 case MSR_MTRRdefType:
719 case MSR_IA32_CR_PAT:
720 return true;
721 case 0x2f8:
722 return true;
723 }
724 return false;
725}
726
d6289b93
MT		 727static bool valid_pat_type(unsigned t)
728{
729 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
730}
731
732static bool valid_mtrr_type(unsigned t)
733{
734 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
735}
736
737static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
738{
739 int i;
740
741 if (!msr_mtrr_valid(msr))
742 return false;
743
744 if (msr == MSR_IA32_CR_PAT) {
745 for (i = 0; i < 8; i++)
746 if (!valid_pat_type((data >> (i * 8)) & 0xff))
747 return false;
748 return true;
749 } else if (msr == MSR_MTRRdefType) {
750 if (data & ~0xcff)
751 return false;
752 return valid_mtrr_type(data & 0xff);
753 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
754 for (i = 0; i < 8 ; i++)
755 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
756 return false;
757 return true;
758 }
759
760 /* variable MTRRs */
761 return valid_mtrr_type(data & 0xff);
762}
763
9ba075a6
AK		 764static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
765{
0bed3b56
SY		 766 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
767
d6289b93 768 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 769 return 1;
770
0bed3b56
SY		 771 if (msr == MSR_MTRRdefType) {
772 vcpu->arch.mtrr_state.def_type = data;
773 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
774 } else if (msr == MSR_MTRRfix64K_00000)
775 p[0] = data;
776 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
777 p[1 + msr - MSR_MTRRfix16K_80000] = data;
778 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
779 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
780 else if (msr == MSR_IA32_CR_PAT)
781 vcpu->arch.pat = data;
782 else { /* Variable MTRRs */
783 int idx, is_mtrr_mask;
784 u64 *pt;
785
786 idx = (msr - 0x200) / 2;
787 is_mtrr_mask = msr - 0x200 - 2 * idx;
788 if (!is_mtrr_mask)
789 pt =
790 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
791 else
792 pt =
793 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
794 *pt = data;
795 }
796
797 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 798 return 0;
799}
15c4a640 800
890ca9ae 801static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 802{
890ca9ae
HY		 803 u64 mcg_cap = vcpu->arch.mcg_cap;
804 unsigned bank_num = mcg_cap & 0xff;
805
15c4a640 806 switch (msr) {
15c4a640 807 case MSR_IA32_MCG_STATUS:
890ca9ae 808 vcpu->arch.mcg_status = data;
15c4a640 809 break;
c7ac679c 810 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 811 if (!(mcg_cap & MCG_CTL_P))
812 return 1;
813 if (data != 0 && data != ~(u64)0)
814 return -1;
815 vcpu->arch.mcg_ctl = data;
816 break;
817 default:
818 if (msr >= MSR_IA32_MC0_CTL &&
819 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
820 u32 offset = msr - MSR_IA32_MC0_CTL;
821 /* only 0 or all 1s can be written to IA32_MCi_CTL */
822 if ((offset & 0x3) == 0 &&
823 data != 0 && data != ~(u64)0)
824 return -1;
825 vcpu->arch.mce_banks[offset] = data;
826 break;
827 }
828 return 1;
829 }
830 return 0;
831}
832
833int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
834{
835 switch (msr) {
836 case MSR_EFER:
837 set_efer(vcpu, data);
c7ac679c 838 break;
8f1589d9
AP		 839 case MSR_K7_HWCR:
840 data &= ~(u64)0x40; /* ignore flush filter disable */
841 if (data != 0) {
842 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
843 data);
844 return 1;
845 }
846 break;
f7c6d140
AP		 847 case MSR_FAM10H_MMIO_CONF_BASE:
848 if (data != 0) {
849 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
850 "0x%llx\n", data);
851 return 1;
852 }
853 break;
c323c0e5
AP		 854 case MSR_AMD64_NB_CFG:
855 break;
b5e2fec0
AG		 856 case MSR_IA32_DEBUGCTLMSR:
857 if (!data) {
858 /* We support the non-activated case already */
859 break;
860 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
861 /* Values other than LBR and BTF are vendor-specific,
862 thus reserved and should throw a #GP */
863 return 1;
864 }
865 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
866 __func__, data);
867 break;
15c4a640
CO		 868 case MSR_IA32_UCODE_REV:
869 case MSR_IA32_UCODE_WRITE:
61a6bd67 870 case MSR_VM_HSAVE_PA:
6098ca93 871 case MSR_AMD64_PATCH_LOADER:
15c4a640 872 break;
9ba075a6
AK		 873 case 0x200 ... 0x2ff:
874 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 875 case MSR_IA32_APICBASE:
876 kvm_set_apic_base(vcpu, data);
877 break;
0105d1a5
GN		 878 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
879 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 880 case MSR_IA32_MISC_ENABLE:
ad312c7c 881 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 882 break;
18068523
GOC		 883 case MSR_KVM_WALL_CLOCK:
884 vcpu->kvm->arch.wall_clock = data;
885 kvm_write_wall_clock(vcpu->kvm, data);
886 break;
887 case MSR_KVM_SYSTEM_TIME: {
888 if (vcpu->arch.time_page) {
889 kvm_release_page_dirty(vcpu->arch.time_page);
890 vcpu->arch.time_page = NULL;
891 }
892
893 vcpu->arch.time = data;
894
895 /* we verify if the enable bit is set... */
896 if (!(data & 1))
897 break;
898
899 /* ...but clean it before doing the actual write */
900 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
901
18068523
GOC		 902 vcpu->arch.time_page =
903 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 904
905 if (is_error_page(vcpu->arch.time_page)) {
906 kvm_release_page_clean(vcpu->arch.time_page);
907 vcpu->arch.time_page = NULL;
908 }
909
c8076604 910 kvm_request_guest_time_update(vcpu);
18068523
GOC		 911 break;
912 }
890ca9ae
HY		 913 case MSR_IA32_MCG_CTL:
914 case MSR_IA32_MCG_STATUS:
915 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
916 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 917
918 /* Performance counters are not protected by a CPUID bit,
919 * so we should check all of them in the generic path for the sake of
920 * cross vendor migration.
921 * Writing a zero into the event select MSRs disables them,
922 * which we perfectly emulate ;-). Any other value should be at least
923 * reported, some guests depend on them.
924 */
925 case MSR_P6_EVNTSEL0:
926 case MSR_P6_EVNTSEL1:
927 case MSR_K7_EVNTSEL0:
928 case MSR_K7_EVNTSEL1:
929 case MSR_K7_EVNTSEL2:
930 case MSR_K7_EVNTSEL3:
931 if (data != 0)
932 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
933 "0x%x data 0x%llx\n", msr, data);
934 break;
935 /* at least RHEL 4 unconditionally writes to the perfctr registers,
936 * so we ignore writes to make it happy.
937 */
938 case MSR_P6_PERFCTR0:
939 case MSR_P6_PERFCTR1:
940 case MSR_K7_PERFCTR0:
941 case MSR_K7_PERFCTR1:
942 case MSR_K7_PERFCTR2:
943 case MSR_K7_PERFCTR3:
944 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
945 "0x%x data 0x%llx\n", msr, data);
946 break;
15c4a640 947 default:
ed85c068
AP		 948 if (!ignore_msrs) {
949 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
950 msr, data);
951 return 1;
952 } else {
953 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
954 msr, data);
955 break;
956 }
15c4a640
CO		 957 }
958 return 0;
959}
960EXPORT_SYMBOL_GPL(kvm_set_msr_common);
961
962
963/*
964 * Reads an msr value (of 'msr_index') into 'pdata'.
965 * Returns 0 on success, non-0 otherwise.
966 * Assumes vcpu_load() was already called.
967 */
968int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
969{
970 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
971}
972
9ba075a6
AK		 973static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
974{
0bed3b56
SY		 975 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
976
9ba075a6
AK		 977 if (!msr_mtrr_valid(msr))
978 return 1;
979
0bed3b56
SY		 980 if (msr == MSR_MTRRdefType)
981 *pdata = vcpu->arch.mtrr_state.def_type +
982 (vcpu->arch.mtrr_state.enabled << 10);
983 else if (msr == MSR_MTRRfix64K_00000)
984 *pdata = p[0];
985 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
986 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
987 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
988 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
989 else if (msr == MSR_IA32_CR_PAT)
990 *pdata = vcpu->arch.pat;
991 else { /* Variable MTRRs */
992 int idx, is_mtrr_mask;
993 u64 *pt;
994
995 idx = (msr - 0x200) / 2;
996 is_mtrr_mask = msr - 0x200 - 2 * idx;
997 if (!is_mtrr_mask)
998 pt =
999 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1000 else
1001 pt =
1002 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1003 *pdata = *pt;
1004 }
1005
9ba075a6
AK		 1006 return 0;
1007}
1008
890ca9ae 1009static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1010{
1011 u64 data;
890ca9ae
HY		 1012 u64 mcg_cap = vcpu->arch.mcg_cap;
1013 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1014
1015 switch (msr) {
15c4a640
CO		 1016 case MSR_IA32_P5_MC_ADDR:
1017 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1018 data = 0;
1019 break;
15c4a640 1020 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1021 data = vcpu->arch.mcg_cap;
1022 break;
c7ac679c 1023 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1024 if (!(mcg_cap & MCG_CTL_P))
1025 return 1;
1026 data = vcpu->arch.mcg_ctl;
1027 break;
1028 case MSR_IA32_MCG_STATUS:
1029 data = vcpu->arch.mcg_status;
1030 break;
1031 default:
1032 if (msr >= MSR_IA32_MC0_CTL &&
1033 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1034 u32 offset = msr - MSR_IA32_MC0_CTL;
1035 data = vcpu->arch.mce_banks[offset];
1036 break;
1037 }
1038 return 1;
1039 }
1040 *pdata = data;
1041 return 0;
1042}
1043
1044int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1045{
1046 u64 data;
1047
1048 switch (msr) {
890ca9ae 1049 case MSR_IA32_PLATFORM_ID:
15c4a640 1050 case MSR_IA32_UCODE_REV:
15c4a640 1051 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1052 case MSR_IA32_DEBUGCTLMSR:
1053 case MSR_IA32_LASTBRANCHFROMIP:
1054 case MSR_IA32_LASTBRANCHTOIP:
1055 case MSR_IA32_LASTINTFROMIP:
1056 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1057 case MSR_K8_SYSCFG:
1058 case MSR_K7_HWCR:
61a6bd67 1059 case MSR_VM_HSAVE_PA:
7fe29e0f
AS		 1060 case MSR_P6_EVNTSEL0:
1061 case MSR_P6_EVNTSEL1:
9e699624 1062 case MSR_K7_EVNTSEL0:
1fdbd48c 1063 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1064 case MSR_AMD64_NB_CFG:
f7c6d140 1065 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1066 data = 0;
1067 break;
9ba075a6
AK		 1068 case MSR_MTRRcap:
1069 data = 0x500 | KVM_NR_VAR_MTRR;
1070 break;
1071 case 0x200 ... 0x2ff:
1072 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1073 case 0xcd: /* fsb frequency */
1074 data = 3;
1075 break;
1076 case MSR_IA32_APICBASE:
1077 data = kvm_get_apic_base(vcpu);
1078 break;
0105d1a5
GN		 1079 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1080 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1081 break;
15c4a640 1082 case MSR_IA32_MISC_ENABLE:
ad312c7c 1083 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1084 break;
847f0ad8
AG		 1085 case MSR_IA32_PERF_STATUS:
1086 /* TSC increment by tick */
1087 data = 1000ULL;
1088 /* CPU multiplier */
1089 data |= (((uint64_t)4ULL) << 40);
1090 break;
15c4a640 1091 case MSR_EFER:
ad312c7c 1092 data = vcpu->arch.shadow_efer;
15c4a640 1093 break;
18068523
GOC		 1094 case MSR_KVM_WALL_CLOCK:
1095 data = vcpu->kvm->arch.wall_clock;
1096 break;
1097 case MSR_KVM_SYSTEM_TIME:
1098 data = vcpu->arch.time;
1099 break;
890ca9ae
HY		 1100 case MSR_IA32_P5_MC_ADDR:
1101 case MSR_IA32_P5_MC_TYPE:
1102 case MSR_IA32_MCG_CAP:
1103 case MSR_IA32_MCG_CTL:
1104 case MSR_IA32_MCG_STATUS:
1105 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1106 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1107 default:
ed85c068
AP		 1108 if (!ignore_msrs) {
1109 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1110 return 1;
1111 } else {
1112 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1113 data = 0;
1114 }
1115 break;
15c4a640
CO		 1116 }
1117 *pdata = data;
1118 return 0;
1119}
1120EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1121
313a3dc7
CO		 1122/*
1123 * Read or write a bunch of msrs. All parameters are kernel addresses.
1124 *
1125 * @return number of msrs set successfully.
1126 */
1127static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1128 struct kvm_msr_entry *entries,
1129 int (*do_msr)(struct kvm_vcpu *vcpu,
1130 unsigned index, u64 *data))
1131{
1132 int i;
1133
1134 vcpu_load(vcpu);
1135
3200f405 1136 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1137 for (i = 0; i < msrs->nmsrs; ++i)
1138 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1139 break;
3200f405 1140 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1141
1142 vcpu_put(vcpu);
1143
1144 return i;
1145}
1146
1147/*
1148 * Read or write a bunch of msrs. Parameters are user addresses.
1149 *
1150 * @return number of msrs set successfully.
1151 */
1152static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1153 int (*do_msr)(struct kvm_vcpu *vcpu,
1154 unsigned index, u64 *data),
1155 int writeback)
1156{
1157 struct kvm_msrs msrs;
1158 struct kvm_msr_entry *entries;
1159 int r, n;
1160 unsigned size;
1161
1162 r = -EFAULT;
1163 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1164 goto out;
1165
1166 r = -E2BIG;
1167 if (msrs.nmsrs >= MAX_IO_MSRS)
1168 goto out;
1169
1170 r = -ENOMEM;
1171 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1172 entries = vmalloc(size);
1173 if (!entries)
1174 goto out;
1175
1176 r = -EFAULT;
1177 if (copy_from_user(entries, user_msrs->entries, size))
1178 goto out_free;
1179
1180 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1181 if (r < 0)
1182 goto out_free;
1183
1184 r = -EFAULT;
1185 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1186 goto out_free;
1187
1188 r = n;
1189
1190out_free:
1191 vfree(entries);
1192out:
1193 return r;
1194}
1195
018d00d2
ZX		 1196int kvm_dev_ioctl_check_extension(long ext)
1197{
1198 int r;
1199
1200 switch (ext) {
1201 case KVM_CAP_IRQCHIP:
1202 case KVM_CAP_HLT:
1203 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1204 case KVM_CAP_SET_TSS_ADDR:
07716717 1205 case KVM_CAP_EXT_CPUID:
c8076604 1206 case KVM_CAP_CLOCKSOURCE:
7837699f 1207 case KVM_CAP_PIT:
a28e4f5a 1208 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1209 case KVM_CAP_MP_STATE:
ed848624 1210 case KVM_CAP_SYNC_MMU:
52d939a0 1211 case KVM_CAP_REINJECT_CONTROL:
4925663a 1212 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1213 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1214 case KVM_CAP_IRQFD:
c5ff41ce 1215 case KVM_CAP_PIT2:
018d00d2
ZX		 1216 r = 1;
1217 break;
542472b5
LV		 1218 case KVM_CAP_COALESCED_MMIO:
1219 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1220 break;
774ead3a
AK		 1221 case KVM_CAP_VAPIC:
1222 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1223 break;
f725230a
AK		 1224 case KVM_CAP_NR_VCPUS:
1225 r = KVM_MAX_VCPUS;
1226 break;
a988b910
AK		 1227 case KVM_CAP_NR_MEMSLOTS:
1228 r = KVM_MEMORY_SLOTS;
1229 break;
2f333bcb
MT		 1230 case KVM_CAP_PV_MMU:
1231 r = !tdp_enabled;
1232 break;
62c476c7 1233 case KVM_CAP_IOMMU:
19de40a8 1234 r = iommu_found();
62c476c7 1235 break;
890ca9ae
HY		 1236 case KVM_CAP_MCE:
1237 r = KVM_MAX_MCE_BANKS;
1238 break;
018d00d2
ZX		 1239 default:
1240 r = 0;
1241 break;
1242 }
1243 return r;
1244
1245}
1246
043405e1
CO		 1247long kvm_arch_dev_ioctl(struct file *filp,
1248 unsigned int ioctl, unsigned long arg)
1249{
1250 void __user *argp = (void __user *)arg;
1251 long r;
1252
1253 switch (ioctl) {
1254 case KVM_GET_MSR_INDEX_LIST: {
1255 struct kvm_msr_list __user *user_msr_list = argp;
1256 struct kvm_msr_list msr_list;
1257 unsigned n;
1258
1259 r = -EFAULT;
1260 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1261 goto out;
1262 n = msr_list.nmsrs;
1263 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1264 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1265 goto out;
1266 r = -E2BIG;
e125e7b6 1267 if (n < msr_list.nmsrs)
043405e1
CO		 1268 goto out;
1269 r = -EFAULT;
1270 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1271 num_msrs_to_save * sizeof(u32)))
1272 goto out;
e125e7b6 1273 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1274 &emulated_msrs,
1275 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1276 goto out;
1277 r = 0;
1278 break;
1279 }
674eea0f
AK		 1280 case KVM_GET_SUPPORTED_CPUID: {
1281 struct kvm_cpuid2 __user *cpuid_arg = argp;
1282 struct kvm_cpuid2 cpuid;
1283
1284 r = -EFAULT;
1285 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1286 goto out;
1287 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1288 cpuid_arg->entries);
674eea0f
AK		 1289 if (r)
1290 goto out;
1291
1292 r = -EFAULT;
1293 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1294 goto out;
1295 r = 0;
1296 break;
1297 }
890ca9ae
HY		 1298 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1299 u64 mce_cap;
1300
1301 mce_cap = KVM_MCE_CAP_SUPPORTED;
1302 r = -EFAULT;
1303 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1304 goto out;
1305 r = 0;
1306 break;
1307 }
043405e1
CO		 1308 default:
1309 r = -EINVAL;
1310 }
1311out:
1312 return r;
1313}
1314
313a3dc7
CO		 1315void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1316{
1317 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1318 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1319}
1320
1321void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1322{
1323 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1324 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1325}
1326
07716717 1327static int is_efer_nx(void)
313a3dc7 1328{
e286e86e 1329 unsigned long long efer = 0;
313a3dc7 1330
e286e86e 1331 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1332 return efer & EFER_NX;
1333}
1334
1335static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1336{
1337 int i;
1338 struct kvm_cpuid_entry2 *e, *entry;
1339
313a3dc7 1340 entry = NULL;
ad312c7c
ZX		 1341 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1342 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1343 if (e->function == 0x80000001) {
1344 entry = e;
1345 break;
1346 }
1347 }
07716717 1348 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1349 entry->edx &= ~(1 << 20);
1350 printk(KERN_INFO "kvm: guest NX capability removed\n");
1351 }
1352}
1353
07716717 1354/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1355static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1356 struct kvm_cpuid *cpuid,
1357 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1358{
1359 int r, i;
1360 struct kvm_cpuid_entry *cpuid_entries;
1361
1362 r = -E2BIG;
1363 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1364 goto out;
1365 r = -ENOMEM;
1366 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1367 if (!cpuid_entries)
1368 goto out;
1369 r = -EFAULT;
1370 if (copy_from_user(cpuid_entries, entries,
1371 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1372 goto out_free;
1373 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1374 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1375 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1376 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1377 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1378 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1379 vcpu->arch.cpuid_entries[i].index = 0;
1380 vcpu->arch.cpuid_entries[i].flags = 0;
1381 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1382 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1383 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1384 }
1385 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1386 cpuid_fix_nx_cap(vcpu);
1387 r = 0;
fc61b800 1388 kvm_apic_set_version(vcpu);
07716717
DK		 1389
1390out_free:
1391 vfree(cpuid_entries);
1392out:
1393 return r;
1394}
1395
1396static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1397 struct kvm_cpuid2 *cpuid,
1398 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1399{
1400 int r;
1401
1402 r = -E2BIG;
1403 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1404 goto out;
1405 r = -EFAULT;
ad312c7c 1406 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1407 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1408 goto out;
ad312c7c 1409 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1410 kvm_apic_set_version(vcpu);
313a3dc7
CO		 1411 return 0;
1412
1413out:
1414 return r;
1415}
1416
07716717 1417static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1418 struct kvm_cpuid2 *cpuid,
1419 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1420{
1421 int r;
1422
1423 r = -E2BIG;
ad312c7c 1424 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1425 goto out;
1426 r = -EFAULT;
ad312c7c 1427 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1428 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1429 goto out;
1430 return 0;
1431
1432out:
ad312c7c 1433 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1434 return r;
1435}
1436
07716717 1437static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1438 u32 index)
07716717
DK		 1439{
1440 entry->function = function;
1441 entry->index = index;
1442 cpuid_count(entry->function, entry->index,
19355475 1443 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1444 entry->flags = 0;
1445}
1446
7faa4ee1
AK		 1447#define F(x) bit(X86_FEATURE_##x)
1448
07716717
DK		 1449static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1450 u32 index, int *nent, int maxnent)
1451{
7faa4ee1 1452 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1453#ifdef CONFIG_X86_64
7faa4ee1
AK		 1454 unsigned f_lm = F(LM);
1455#else
1456 unsigned f_lm = 0;
07716717 1457#endif
7faa4ee1
AK		 1458
1459 /* cpuid 1.edx */
1460 const u32 kvm_supported_word0_x86_features =
1461 F(FPU) | F(VME) | F(DE) | F(PSE) |
1462 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1463 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1464 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1465 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1466 0 /* Reserved, DS, ACPI */ | F(MMX) |
1467 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1468 0 /* HTT, TM, Reserved, PBE */;
1469 /* cpuid 0x80000001.edx */
1470 const u32 kvm_supported_word1_x86_features =
1471 F(FPU) | F(VME) | F(DE) | F(PSE) |
1472 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1473 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1474 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1475 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1476 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1477 F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
1478 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1479 /* cpuid 1.ecx */
1480 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1481 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1482 0 /* DS-CPL, VMX, SMX, EST */ |
1483 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1484 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1485 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1486 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1487 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1488 /* cpuid 0x80000001.ecx */
07716717 1489 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1490 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1491 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1492 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1493 0 /* SKINIT */ | 0 /* WDT */;
07716717 1494
19355475 1495 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1496 get_cpu();
1497 do_cpuid_1_ent(entry, function, index);
1498 ++*nent;
1499
1500 switch (function) {
1501 case 0:
1502 entry->eax = min(entry->eax, (u32)0xb);
1503 break;
1504 case 1:
1505 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1506 entry->ecx &= kvm_supported_word4_x86_features;
07716717
DK		 1507 break;
1508 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1509 * may return different values. This forces us to get_cpu() before
1510 * issuing the first command, and also to emulate this annoying behavior
1511 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1512 case 2: {
1513 int t, times = entry->eax & 0xff;
1514
1515 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1516 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1517 for (t = 1; t < times && *nent < maxnent; ++t) {
1518 do_cpuid_1_ent(&entry[t], function, 0);
1519 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1520 ++*nent;
1521 }
1522 break;
1523 }
1524 /* function 4 and 0xb have additional index. */
1525 case 4: {
14af3f3c 1526 int i, cache_type;
07716717
DK		 1527
1528 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1529 /* read more entries until cache_type is zero */
14af3f3c
HH		 1530 for (i = 1; *nent < maxnent; ++i) {
1531 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1532 if (!cache_type)
1533 break;
14af3f3c
HH		 1534 do_cpuid_1_ent(&entry[i], function, i);
1535 entry[i].flags |=
07716717
DK		 1536 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1537 ++*nent;
1538 }
1539 break;
1540 }
1541 case 0xb: {
14af3f3c 1542 int i, level_type;
07716717
DK		 1543
1544 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1545 /* read more entries until level_type is zero */
14af3f3c 1546 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1547 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1548 if (!level_type)
1549 break;
14af3f3c
HH		 1550 do_cpuid_1_ent(&entry[i], function, i);
1551 entry[i].flags |=
07716717
DK		 1552 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1553 ++*nent;
1554 }
1555 break;
1556 }
1557 case 0x80000000:
1558 entry->eax = min(entry->eax, 0x8000001a);
1559 break;
1560 case 0x80000001:
1561 entry->edx &= kvm_supported_word1_x86_features;
1562 entry->ecx &= kvm_supported_word6_x86_features;
1563 break;
1564 }
1565 put_cpu();
1566}
1567
7faa4ee1
AK		 1568#undef F
1569
674eea0f 1570static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1571 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1572{
1573 struct kvm_cpuid_entry2 *cpuid_entries;
1574 int limit, nent = 0, r = -E2BIG;
1575 u32 func;
1576
1577 if (cpuid->nent < 1)
1578 goto out;
1579 r = -ENOMEM;
1580 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1581 if (!cpuid_entries)
1582 goto out;
1583
1584 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1585 limit = cpuid_entries[0].eax;
1586 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1587 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1588 &nent, cpuid->nent);
07716717
DK		 1589 r = -E2BIG;
1590 if (nent >= cpuid->nent)
1591 goto out_free;
1592
1593 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1594 limit = cpuid_entries[nent - 1].eax;
1595 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1596 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1597 &nent, cpuid->nent);
cb007648
MM		 1598 r = -E2BIG;
1599 if (nent >= cpuid->nent)
1600 goto out_free;
1601
07716717
DK		 1602 r = -EFAULT;
1603 if (copy_to_user(entries, cpuid_entries,
19355475 1604 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1605 goto out_free;
1606 cpuid->nent = nent;
1607 r = 0;
1608
1609out_free:
1610 vfree(cpuid_entries);
1611out:
1612 return r;
1613}
1614
313a3dc7
CO		 1615static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1616 struct kvm_lapic_state *s)
1617{
1618 vcpu_load(vcpu);
ad312c7c 1619 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1620 vcpu_put(vcpu);
1621
1622 return 0;
1623}
1624
1625static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1626 struct kvm_lapic_state *s)
1627{
1628 vcpu_load(vcpu);
ad312c7c 1629 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1630 kvm_apic_post_state_restore(vcpu);
1631 vcpu_put(vcpu);
1632
1633 return 0;
1634}
1635
f77bc6a4
ZX		 1636static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1637 struct kvm_interrupt *irq)
1638{
1639 if (irq->irq < 0 || irq->irq >= 256)
1640 return -EINVAL;
1641 if (irqchip_in_kernel(vcpu->kvm))
1642 return -ENXIO;
1643 vcpu_load(vcpu);
1644
66fd3f7f 1645 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1646
1647 vcpu_put(vcpu);
1648
1649 return 0;
1650}
1651
c4abb7c9
JK		 1652static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1653{
1654 vcpu_load(vcpu);
1655 kvm_inject_nmi(vcpu);
1656 vcpu_put(vcpu);
1657
1658 return 0;
1659}
1660
b209749f
AK		 1661static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1662 struct kvm_tpr_access_ctl *tac)
1663{
1664 if (tac->flags)
1665 return -EINVAL;
1666 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1667 return 0;
1668}
1669
890ca9ae
HY		 1670static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1671 u64 mcg_cap)
1672{
1673 int r;
1674 unsigned bank_num = mcg_cap & 0xff, bank;
1675
1676 r = -EINVAL;
1677 if (!bank_num)
1678 goto out;
1679 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1680 goto out;
1681 r = 0;
1682 vcpu->arch.mcg_cap = mcg_cap;
1683 /* Init IA32_MCG_CTL to all 1s */
1684 if (mcg_cap & MCG_CTL_P)
1685 vcpu->arch.mcg_ctl = ~(u64)0;
1686 /* Init IA32_MCi_CTL to all 1s */
1687 for (bank = 0; bank < bank_num; bank++)
1688 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1689out:
1690 return r;
1691}
1692
1693static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1694 struct kvm_x86_mce *mce)
1695{
1696 u64 mcg_cap = vcpu->arch.mcg_cap;
1697 unsigned bank_num = mcg_cap & 0xff;
1698 u64 *banks = vcpu->arch.mce_banks;
1699
1700 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1701 return -EINVAL;
1702 /*
1703 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1704 * reporting is disabled
1705 */
1706 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1707 vcpu->arch.mcg_ctl != ~(u64)0)
1708 return 0;
1709 banks += 4 * mce->bank;
1710 /*
1711 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1712 * reporting is disabled for the bank
1713 */
1714 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1715 return 0;
1716 if (mce->status & MCI_STATUS_UC) {
1717 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1718 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1719 printk(KERN_DEBUG "kvm: set_mce: "
1720 "injects mce exception while "
1721 "previous one is in progress!\n");
1722 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1723 return 0;
1724 }
1725 if (banks[1] & MCI_STATUS_VAL)
1726 mce->status |= MCI_STATUS_OVER;
1727 banks[2] = mce->addr;
1728 banks[3] = mce->misc;
1729 vcpu->arch.mcg_status = mce->mcg_status;
1730 banks[1] = mce->status;
1731 kvm_queue_exception(vcpu, MC_VECTOR);
1732 } else if (!(banks[1] & MCI_STATUS_VAL)
1733 || !(banks[1] & MCI_STATUS_UC)) {
1734 if (banks[1] & MCI_STATUS_VAL)
1735 mce->status |= MCI_STATUS_OVER;
1736 banks[2] = mce->addr;
1737 banks[3] = mce->misc;
1738 banks[1] = mce->status;
1739 } else
1740 banks[1] |= MCI_STATUS_OVER;
1741 return 0;
1742}
1743
313a3dc7
CO		 1744long kvm_arch_vcpu_ioctl(struct file *filp,
1745 unsigned int ioctl, unsigned long arg)
1746{
1747 struct kvm_vcpu *vcpu = filp->private_data;
1748 void __user *argp = (void __user *)arg;
1749 int r;
b772ff36 1750 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1751
1752 switch (ioctl) {
1753 case KVM_GET_LAPIC: {
b772ff36 1754 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1755
b772ff36
DH		 1756 r = -ENOMEM;
1757 if (!lapic)
1758 goto out;
1759 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1760 if (r)
1761 goto out;
1762 r = -EFAULT;
b772ff36 1763 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1764 goto out;
1765 r = 0;
1766 break;
1767 }
1768 case KVM_SET_LAPIC: {
b772ff36
DH		 1769 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1770 r = -ENOMEM;
1771 if (!lapic)
1772 goto out;
313a3dc7 1773 r = -EFAULT;
b772ff36 1774 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1775 goto out;
b772ff36 1776 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1777 if (r)
1778 goto out;
1779 r = 0;
1780 break;
1781 }
f77bc6a4
ZX		 1782 case KVM_INTERRUPT: {
1783 struct kvm_interrupt irq;
1784
1785 r = -EFAULT;
1786 if (copy_from_user(&irq, argp, sizeof irq))
1787 goto out;
1788 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1789 if (r)
1790 goto out;
1791 r = 0;
1792 break;
1793 }
c4abb7c9
JK		 1794 case KVM_NMI: {
1795 r = kvm_vcpu_ioctl_nmi(vcpu);
1796 if (r)
1797 goto out;
1798 r = 0;
1799 break;
1800 }
313a3dc7
CO		 1801 case KVM_SET_CPUID: {
1802 struct kvm_cpuid __user *cpuid_arg = argp;
1803 struct kvm_cpuid cpuid;
1804
1805 r = -EFAULT;
1806 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1807 goto out;
1808 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1809 if (r)
1810 goto out;
1811 break;
1812 }
07716717
DK		 1813 case KVM_SET_CPUID2: {
1814 struct kvm_cpuid2 __user *cpuid_arg = argp;
1815 struct kvm_cpuid2 cpuid;
1816
1817 r = -EFAULT;
1818 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1819 goto out;
1820 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1821 cpuid_arg->entries);
07716717
DK		 1822 if (r)
1823 goto out;
1824 break;
1825 }
1826 case KVM_GET_CPUID2: {
1827 struct kvm_cpuid2 __user *cpuid_arg = argp;
1828 struct kvm_cpuid2 cpuid;
1829
1830 r = -EFAULT;
1831 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1832 goto out;
1833 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1834 cpuid_arg->entries);
07716717
DK		 1835 if (r)
1836 goto out;
1837 r = -EFAULT;
1838 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1839 goto out;
1840 r = 0;
1841 break;
1842 }
313a3dc7
CO		 1843 case KVM_GET_MSRS:
1844 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1845 break;
1846 case KVM_SET_MSRS:
1847 r = msr_io(vcpu, argp, do_set_msr, 0);
1848 break;
b209749f
AK		 1849 case KVM_TPR_ACCESS_REPORTING: {
1850 struct kvm_tpr_access_ctl tac;
1851
1852 r = -EFAULT;
1853 if (copy_from_user(&tac, argp, sizeof tac))
1854 goto out;
1855 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1856 if (r)
1857 goto out;
1858 r = -EFAULT;
1859 if (copy_to_user(argp, &tac, sizeof tac))
1860 goto out;
1861 r = 0;
1862 break;
1863 };
b93463aa
AK		 1864 case KVM_SET_VAPIC_ADDR: {
1865 struct kvm_vapic_addr va;
1866
1867 r = -EINVAL;
1868 if (!irqchip_in_kernel(vcpu->kvm))
1869 goto out;
1870 r = -EFAULT;
1871 if (copy_from_user(&va, argp, sizeof va))
1872 goto out;
1873 r = 0;
1874 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1875 break;
1876 }
890ca9ae
HY		 1877 case KVM_X86_SETUP_MCE: {
1878 u64 mcg_cap;
1879
1880 r = -EFAULT;
1881 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1882 goto out;
1883 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1884 break;
1885 }
1886 case KVM_X86_SET_MCE: {
1887 struct kvm_x86_mce mce;
1888
1889 r = -EFAULT;
1890 if (copy_from_user(&mce, argp, sizeof mce))
1891 goto out;
1892 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1893 break;
1894 }
313a3dc7
CO		 1895 default:
1896 r = -EINVAL;
1897 }
1898out:
7a6ce84c 1899 kfree(lapic);
313a3dc7
CO		 1900 return r;
1901}
1902
1fe779f8
CO		 1903static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1904{
1905 int ret;
1906
1907 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1908 return -1;
1909 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1910 return ret;
1911}
1912
1913static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1914 u32 kvm_nr_mmu_pages)
1915{
1916 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1917 return -EINVAL;
1918
72dc67a6 1919 down_write(&kvm->slots_lock);
7c8a83b7 1920 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1921
1922 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1923 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1924
7c8a83b7 1925 spin_unlock(&kvm->mmu_lock);
72dc67a6 1926 up_write(&kvm->slots_lock);
1fe779f8
CO		 1927 return 0;
1928}
1929
1930static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1931{
f05e70ac 1932 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1933}
1934
e9f85cde
ZX		 1935gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1936{
1937 int i;
1938 struct kvm_mem_alias *alias;
1939
d69fb81f
ZX		 1940 for (i = 0; i < kvm->arch.naliases; ++i) {
1941 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1942 if (gfn >= alias->base_gfn
1943 && gfn < alias->base_gfn + alias->npages)
1944 return alias->target_gfn + gfn - alias->base_gfn;
1945 }
1946 return gfn;
1947}
1948
1fe779f8
CO		 1949/*
1950 * Set a new alias region. Aliases map a portion of physical memory into
1951 * another portion. This is useful for memory windows, for example the PC
1952 * VGA region.
1953 */
1954static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1955 struct kvm_memory_alias *alias)
1956{
1957 int r, n;
1958 struct kvm_mem_alias *p;
1959
1960 r = -EINVAL;
1961 /* General sanity checks */
1962 if (alias->memory_size & (PAGE_SIZE - 1))
1963 goto out;
1964 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1965 goto out;
1966 if (alias->slot >= KVM_ALIAS_SLOTS)
1967 goto out;
1968 if (alias->guest_phys_addr + alias->memory_size
1969 < alias->guest_phys_addr)
1970 goto out;
1971 if (alias->target_phys_addr + alias->memory_size
1972 < alias->target_phys_addr)
1973 goto out;
1974
72dc67a6 1975 down_write(&kvm->slots_lock);
a1708ce8 1976 spin_lock(&kvm->mmu_lock);
1fe779f8 1977
d69fb81f 1978 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1979 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1980 p->npages = alias->memory_size >> PAGE_SHIFT;
1981 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1982
1983 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1984 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1985 break;
d69fb81f 1986 kvm->arch.naliases = n;
1fe779f8 1987
a1708ce8 1988 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1989 kvm_mmu_zap_all(kvm);
1990
72dc67a6 1991 up_write(&kvm->slots_lock);
1fe779f8
CO		 1992
1993 return 0;
1994
1995out:
1996 return r;
1997}
1998
1999static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2000{
2001 int r;
2002
2003 r = 0;
2004 switch (chip->chip_id) {
2005 case KVM_IRQCHIP_PIC_MASTER:
2006 memcpy(&chip->chip.pic,
2007 &pic_irqchip(kvm)->pics[0],
2008 sizeof(struct kvm_pic_state));
2009 break;
2010 case KVM_IRQCHIP_PIC_SLAVE:
2011 memcpy(&chip->chip.pic,
2012 &pic_irqchip(kvm)->pics[1],
2013 sizeof(struct kvm_pic_state));
2014 break;
2015 case KVM_IRQCHIP_IOAPIC:
2016 memcpy(&chip->chip.ioapic,
2017 ioapic_irqchip(kvm),
2018 sizeof(struct kvm_ioapic_state));
2019 break;
2020 default:
2021 r = -EINVAL;
2022 break;
2023 }
2024 return r;
2025}
2026
2027static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2028{
2029 int r;
2030
2031 r = 0;
2032 switch (chip->chip_id) {
2033 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2034 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2035 memcpy(&pic_irqchip(kvm)->pics[0],
2036 &chip->chip.pic,
2037 sizeof(struct kvm_pic_state));
894a9c55 2038 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2039 break;
2040 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2041 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2042 memcpy(&pic_irqchip(kvm)->pics[1],
2043 &chip->chip.pic,
2044 sizeof(struct kvm_pic_state));
894a9c55 2045 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2046 break;
2047 case KVM_IRQCHIP_IOAPIC:
894a9c55 2048 mutex_lock(&kvm->irq_lock);
1fe779f8
CO		 2049 memcpy(ioapic_irqchip(kvm),
2050 &chip->chip.ioapic,
2051 sizeof(struct kvm_ioapic_state));
894a9c55 2052 mutex_unlock(&kvm->irq_lock);
1fe779f8
CO		 2053 break;
2054 default:
2055 r = -EINVAL;
2056 break;
2057 }
2058 kvm_pic_update_irq(pic_irqchip(kvm));
2059 return r;
2060}
2061
e0f63cb9
SY		 2062static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2063{
2064 int r = 0;
2065
894a9c55 2066 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2067 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2068 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2069 return r;
2070}
2071
2072static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2073{
2074 int r = 0;
2075
894a9c55 2076 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2077 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2078 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
894a9c55 2079 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2080 return r;
2081}
2082
52d939a0
MT		 2083static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2084 struct kvm_reinject_control *control)
2085{
2086 if (!kvm->arch.vpit)
2087 return -ENXIO;
894a9c55 2088 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2089 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2090 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2091 return 0;
2092}
2093
5bb064dc
ZX		 2094/*
2095 * Get (and clear) the dirty memory log for a memory slot.
2096 */
2097int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2098 struct kvm_dirty_log *log)
2099{
2100 int r;
2101 int n;
2102 struct kvm_memory_slot *memslot;
2103 int is_dirty = 0;
2104
72dc67a6 2105 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2106
2107 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2108 if (r)
2109 goto out;
2110
2111 /* If nothing is dirty, don't bother messing with page tables. */
2112 if (is_dirty) {
7c8a83b7 2113 spin_lock(&kvm->mmu_lock);
5bb064dc 2114 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2115 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2116 kvm_flush_remote_tlbs(kvm);
2117 memslot = &kvm->memslots[log->slot];
2118 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2119 memset(memslot->dirty_bitmap, 0, n);
2120 }
2121 r = 0;
2122out:
72dc67a6 2123 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2124 return r;
2125}
2126
1fe779f8
CO		 2127long kvm_arch_vm_ioctl(struct file *filp,
2128 unsigned int ioctl, unsigned long arg)
2129{
2130 struct kvm *kvm = filp->private_data;
2131 void __user *argp = (void __user *)arg;
2132 int r = -EINVAL;
f0d66275
DH		 2133 /*
2134 * This union makes it completely explicit to gcc-3.x
2135 * that these two variables' stack usage should be
2136 * combined, not added together.
2137 */
2138 union {
2139 struct kvm_pit_state ps;
2140 struct kvm_memory_alias alias;
c5ff41ce 2141 struct kvm_pit_config pit_config;
f0d66275 2142 } u;
1fe779f8
CO		 2143
2144 switch (ioctl) {
2145 case KVM_SET_TSS_ADDR:
2146 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2147 if (r < 0)
2148 goto out;
2149 break;
2150 case KVM_SET_MEMORY_REGION: {
2151 struct kvm_memory_region kvm_mem;
2152 struct kvm_userspace_memory_region kvm_userspace_mem;
2153
2154 r = -EFAULT;
2155 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2156 goto out;
2157 kvm_userspace_mem.slot = kvm_mem.slot;
2158 kvm_userspace_mem.flags = kvm_mem.flags;
2159 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2160 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2161 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2162 if (r)
2163 goto out;
2164 break;
2165 }
2166 case KVM_SET_NR_MMU_PAGES:
2167 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2168 if (r)
2169 goto out;
2170 break;
2171 case KVM_GET_NR_MMU_PAGES:
2172 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2173 break;
f0d66275 2174 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2175 r = -EFAULT;
f0d66275 2176 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2177 goto out;
f0d66275 2178 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2179 if (r)
2180 goto out;
2181 break;
1fe779f8
CO		 2182 case KVM_CREATE_IRQCHIP:
2183 r = -ENOMEM;
d7deeeb0
ZX		 2184 kvm->arch.vpic = kvm_create_pic(kvm);
2185 if (kvm->arch.vpic) {
1fe779f8
CO		 2186 r = kvm_ioapic_init(kvm);
2187 if (r) {
d7deeeb0
ZX		 2188 kfree(kvm->arch.vpic);
2189 kvm->arch.vpic = NULL;
1fe779f8
CO		 2190 goto out;
2191 }
2192 } else
2193 goto out;
399ec807
AK		 2194 r = kvm_setup_default_irq_routing(kvm);
2195 if (r) {
2196 kfree(kvm->arch.vpic);
2197 kfree(kvm->arch.vioapic);
2198 goto out;
2199 }
1fe779f8 2200 break;
7837699f 2201 case KVM_CREATE_PIT:
c5ff41ce
JK		 2202 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2203 goto create_pit;
2204 case KVM_CREATE_PIT2:
2205 r = -EFAULT;
2206 if (copy_from_user(&u.pit_config, argp,
2207 sizeof(struct kvm_pit_config)))
2208 goto out;
2209 create_pit:
108b5669 2210 down_write(&kvm->slots_lock);
269e05e4
AK		 2211 r = -EEXIST;
2212 if (kvm->arch.vpit)
2213 goto create_pit_unlock;
7837699f 2214 r = -ENOMEM;
c5ff41ce 2215 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2216 if (kvm->arch.vpit)
2217 r = 0;
269e05e4 2218 create_pit_unlock:
108b5669 2219 up_write(&kvm->slots_lock);
7837699f 2220 break;
4925663a 2221 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2222 case KVM_IRQ_LINE: {
2223 struct kvm_irq_level irq_event;
2224
2225 r = -EFAULT;
2226 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2227 goto out;
2228 if (irqchip_in_kernel(kvm)) {
4925663a 2229 __s32 status;
fa40a821 2230 mutex_lock(&kvm->irq_lock);
4925663a
GN		 2231 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2232 irq_event.irq, irq_event.level);
fa40a821 2233 mutex_unlock(&kvm->irq_lock);
4925663a
GN		 2234 if (ioctl == KVM_IRQ_LINE_STATUS) {
2235 irq_event.status = status;
2236 if (copy_to_user(argp, &irq_event,
2237 sizeof irq_event))
2238 goto out;
2239 }
1fe779f8
CO		 2240 r = 0;
2241 }
2242 break;
2243 }
2244 case KVM_GET_IRQCHIP: {
2245 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2246 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2247
f0d66275
DH		 2248 r = -ENOMEM;
2249 if (!chip)
1fe779f8 2250 goto out;
f0d66275
DH		 2251 r = -EFAULT;
2252 if (copy_from_user(chip, argp, sizeof *chip))
2253 goto get_irqchip_out;
1fe779f8
CO		 2254 r = -ENXIO;
2255 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2256 goto get_irqchip_out;
2257 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2258 if (r)
f0d66275 2259 goto get_irqchip_out;
1fe779f8 2260 r = -EFAULT;
f0d66275
DH		 2261 if (copy_to_user(argp, chip, sizeof *chip))
2262 goto get_irqchip_out;
1fe779f8 2263 r = 0;
f0d66275
DH		 2264 get_irqchip_out:
2265 kfree(chip);
2266 if (r)
2267 goto out;
1fe779f8
CO		 2268 break;
2269 }
2270 case KVM_SET_IRQCHIP: {
2271 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2272 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2273
f0d66275
DH		 2274 r = -ENOMEM;
2275 if (!chip)
1fe779f8 2276 goto out;
f0d66275
DH		 2277 r = -EFAULT;
2278 if (copy_from_user(chip, argp, sizeof *chip))
2279 goto set_irqchip_out;
1fe779f8
CO		 2280 r = -ENXIO;
2281 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2282 goto set_irqchip_out;
2283 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2284 if (r)
f0d66275 2285 goto set_irqchip_out;
1fe779f8 2286 r = 0;
f0d66275
DH		 2287 set_irqchip_out:
2288 kfree(chip);
2289 if (r)
2290 goto out;
1fe779f8
CO		 2291 break;
2292 }
e0f63cb9 2293 case KVM_GET_PIT: {
e0f63cb9 2294 r = -EFAULT;
f0d66275 2295 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2296 goto out;
2297 r = -ENXIO;
2298 if (!kvm->arch.vpit)
2299 goto out;
f0d66275 2300 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2301 if (r)
2302 goto out;
2303 r = -EFAULT;
f0d66275 2304 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2305 goto out;
2306 r = 0;
2307 break;
2308 }
2309 case KVM_SET_PIT: {
e0f63cb9 2310 r = -EFAULT;
f0d66275 2311 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2312 goto out;
2313 r = -ENXIO;
2314 if (!kvm->arch.vpit)
2315 goto out;
f0d66275 2316 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2317 if (r)
2318 goto out;
2319 r = 0;
2320 break;
2321 }
52d939a0
MT		 2322 case KVM_REINJECT_CONTROL: {
2323 struct kvm_reinject_control control;
2324 r = -EFAULT;
2325 if (copy_from_user(&control, argp, sizeof(control)))
2326 goto out;
2327 r = kvm_vm_ioctl_reinject(kvm, &control);
2328 if (r)
2329 goto out;
2330 r = 0;
2331 break;
2332 }
1fe779f8
CO		 2333 default:
2334 ;
2335 }
2336out:
2337 return r;
2338}
2339
a16b043c 2340static void kvm_init_msr_list(void)
043405e1
CO		 2341{
2342 u32 dummy[2];
2343 unsigned i, j;
2344
2345 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2346 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2347 continue;
2348 if (j < i)
2349 msrs_to_save[j] = msrs_to_save[i];
2350 j++;
2351 }
2352 num_msrs_to_save = j;
2353}
2354
bda9020e
MT		 2355static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2356 const void *v)
bbd9b64e 2357{
bda9020e
MT		 2358 if (vcpu->arch.apic &&
2359 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2360 return 0;
bbd9b64e 2361
bda9020e 2362 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2363}
2364
bda9020e 2365static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2366{
bda9020e
MT		 2367 if (vcpu->arch.apic &&
2368 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2369 return 0;
bbd9b64e 2370
bda9020e 2371 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2372}
2373
cded19f3
HE		 2374static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2375 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2376{
2377 void *data = val;
10589a46 2378 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2379
2380 while (bytes) {
ad312c7c 2381 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2382 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2383 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2384 int ret;
2385
10589a46
MT		 2386 if (gpa == UNMAPPED_GVA) {
2387 r = X86EMUL_PROPAGATE_FAULT;
2388 goto out;
2389 }
77c2002e 2390 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2391 if (ret < 0) {
2392 r = X86EMUL_UNHANDLEABLE;
2393 goto out;
2394 }
bbd9b64e 2395
77c2002e
IE		 2396 bytes -= toread;
2397 data += toread;
2398 addr += toread;
bbd9b64e 2399 }
10589a46 2400out:
10589a46 2401 return r;
bbd9b64e 2402}
77c2002e 2403
cded19f3
HE		 2404static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2405 struct kvm_vcpu *vcpu)
77c2002e
IE		 2406{
2407 void *data = val;
2408 int r = X86EMUL_CONTINUE;
2409
2410 while (bytes) {
2411 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2412 unsigned offset = addr & (PAGE_SIZE-1);
2413 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2414 int ret;
2415
2416 if (gpa == UNMAPPED_GVA) {
2417 r = X86EMUL_PROPAGATE_FAULT;
2418 goto out;
2419 }
2420 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2421 if (ret < 0) {
2422 r = X86EMUL_UNHANDLEABLE;
2423 goto out;
2424 }
2425
2426 bytes -= towrite;
2427 data += towrite;
2428 addr += towrite;
2429 }
2430out:
2431 return r;
2432}
2433
bbd9b64e 2434
bbd9b64e
CO		 2435static int emulator_read_emulated(unsigned long addr,
2436 void *val,
2437 unsigned int bytes,
2438 struct kvm_vcpu *vcpu)
2439{
bbd9b64e
CO		 2440 gpa_t gpa;
2441
2442 if (vcpu->mmio_read_completed) {
2443 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2444 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2445 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2446 vcpu->mmio_read_completed = 0;
2447 return X86EMUL_CONTINUE;
2448 }
2449
ad312c7c 2450 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2451
2452 /* For APIC access vmexit */
2453 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2454 goto mmio;
2455
77c2002e
IE		 2456 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2457 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2458 return X86EMUL_CONTINUE;
2459 if (gpa == UNMAPPED_GVA)
2460 return X86EMUL_PROPAGATE_FAULT;
2461
2462mmio:
2463 /*
2464 * Is this MMIO handled locally?
2465 */
aec51dc4
AK		 2466 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2467 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e 2468 return X86EMUL_CONTINUE;
aec51dc4
AK		 2469 }
2470
2471 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2472
2473 vcpu->mmio_needed = 1;
2474 vcpu->mmio_phys_addr = gpa;
2475 vcpu->mmio_size = bytes;
2476 vcpu->mmio_is_write = 0;
2477
2478 return X86EMUL_UNHANDLEABLE;
2479}
2480
3200f405 2481int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2482 const void *val, int bytes)
bbd9b64e
CO		 2483{
2484 int ret;
2485
2486 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2487 if (ret < 0)
bbd9b64e 2488 return 0;
ad218f85 2489 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2490 return 1;
2491}
2492
2493static int emulator_write_emulated_onepage(unsigned long addr,
2494 const void *val,
2495 unsigned int bytes,
2496 struct kvm_vcpu *vcpu)
2497{
10589a46
MT		 2498 gpa_t gpa;
2499
10589a46 2500 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2501
2502 if (gpa == UNMAPPED_GVA) {
c3c91fee 2503 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2504 return X86EMUL_PROPAGATE_FAULT;
2505 }
2506
2507 /* For APIC access vmexit */
2508 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2509 goto mmio;
2510
2511 if (emulator_write_phys(vcpu, gpa, val, bytes))
2512 return X86EMUL_CONTINUE;
2513
2514mmio:
aec51dc4 2515 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2516 /*
2517 * Is this MMIO handled locally?
2518 */
bda9020e 2519 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 2520 return X86EMUL_CONTINUE;
bbd9b64e
CO		 2521
2522 vcpu->mmio_needed = 1;
2523 vcpu->mmio_phys_addr = gpa;
2524 vcpu->mmio_size = bytes;
2525 vcpu->mmio_is_write = 1;
2526 memcpy(vcpu->mmio_data, val, bytes);
2527
2528 return X86EMUL_CONTINUE;
2529}
2530
2531int emulator_write_emulated(unsigned long addr,
2532 const void *val,
2533 unsigned int bytes,
2534 struct kvm_vcpu *vcpu)
2535{
2536 /* Crossing a page boundary? */
2537 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2538 int rc, now;
2539
2540 now = -addr & ~PAGE_MASK;
2541 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2542 if (rc != X86EMUL_CONTINUE)
2543 return rc;
2544 addr += now;
2545 val += now;
2546 bytes -= now;
2547 }
2548 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2549}
2550EXPORT_SYMBOL_GPL(emulator_write_emulated);
2551
2552static int emulator_cmpxchg_emulated(unsigned long addr,
2553 const void *old,
2554 const void *new,
2555 unsigned int bytes,
2556 struct kvm_vcpu *vcpu)
2557{
2558 static int reported;
2559
2560 if (!reported) {
2561 reported = 1;
2562 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2563 }
2bacc55c
MT		 2564#ifndef CONFIG_X86_64
2565 /* guests cmpxchg8b have to be emulated atomically */
2566 if (bytes == 8) {
10589a46 2567 gpa_t gpa;
2bacc55c 2568 struct page *page;
c0b49b0d 2569 char *kaddr;
2bacc55c
MT		 2570 u64 val;
2571
10589a46
MT		 2572 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2573
2bacc55c
MT		 2574 if (gpa == UNMAPPED_GVA ||
2575 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2576 goto emul_write;
2577
2578 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2579 goto emul_write;
2580
2581 val = *(u64 *)new;
72dc67a6 2582
2bacc55c 2583 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2584
c0b49b0d
AM		 2585 kaddr = kmap_atomic(page, KM_USER0);
2586 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2587 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2588 kvm_release_page_dirty(page);
2589 }
3200f405 2590emul_write:
2bacc55c
MT		 2591#endif
2592
bbd9b64e
CO		 2593 return emulator_write_emulated(addr, new, bytes, vcpu);
2594}
2595
2596static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2597{
2598 return kvm_x86_ops->get_segment_base(vcpu, seg);
2599}
2600
2601int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2602{
a7052897 2603 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2604 return X86EMUL_CONTINUE;
2605}
2606
2607int emulate_clts(struct kvm_vcpu *vcpu)
2608{
ad312c7c 2609 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2610 return X86EMUL_CONTINUE;
2611}
2612
2613int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2614{
2615 struct kvm_vcpu *vcpu = ctxt->vcpu;
2616
2617 switch (dr) {
2618 case 0 ... 3:
2619 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2620 return X86EMUL_CONTINUE;
2621 default:
b8688d51 2622 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2623 return X86EMUL_UNHANDLEABLE;
2624 }
2625}
2626
2627int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2628{
2629 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2630 int exception;
2631
2632 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2633 if (exception) {
2634 /* FIXME: better handling */
2635 return X86EMUL_UNHANDLEABLE;
2636 }
2637 return X86EMUL_CONTINUE;
2638}
2639
2640void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2641{
bbd9b64e 2642 u8 opcodes[4];
5fdbf976 2643 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2644 unsigned long rip_linear;
2645
f76c710d 2646 if (!printk_ratelimit())
bbd9b64e
CO		 2647 return;
2648
25be4608
GC		 2649 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2650
77c2002e 2651 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2652
2653 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2654 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2655}
2656EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2657
14af3f3c 2658static struct x86_emulate_ops emulate_ops = {
77c2002e 2659 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2660 .read_emulated = emulator_read_emulated,
2661 .write_emulated = emulator_write_emulated,
2662 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2663};
2664
5fdbf976
MT		 2665static void cache_all_regs(struct kvm_vcpu *vcpu)
2666{
2667 kvm_register_read(vcpu, VCPU_REGS_RAX);
2668 kvm_register_read(vcpu, VCPU_REGS_RSP);
2669 kvm_register_read(vcpu, VCPU_REGS_RIP);
2670 vcpu->arch.regs_dirty = ~0;
2671}
2672
bbd9b64e
CO		 2673int emulate_instruction(struct kvm_vcpu *vcpu,
2674 struct kvm_run *run,
2675 unsigned long cr2,
2676 u16 error_code,
571008da 2677 int emulation_type)
bbd9b64e 2678{
310b5d30 2679 int r, shadow_mask;
571008da 2680 struct decode_cache *c;
bbd9b64e 2681
26eef70c 2682 kvm_clear_exception_queue(vcpu);
ad312c7c 2683 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2684 /*
2685 * TODO: fix x86_emulate.c to use guest_read/write_register
2686 * instead of direct ->regs accesses, can save hundred cycles
2687 * on Intel for instructions that don't read/change RSP, for
2688 * for example.
2689 */
2690 cache_all_regs(vcpu);
bbd9b64e
CO		 2691
2692 vcpu->mmio_is_write = 0;
ad312c7c 2693 vcpu->arch.pio.string = 0;
bbd9b64e 2694
571008da 2695 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2696 int cs_db, cs_l;
2697 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2698
ad312c7c
ZX		 2699 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2700 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2701 vcpu->arch.emulate_ctxt.mode =
2702 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2703 ? X86EMUL_MODE_REAL : cs_l
2704 ? X86EMUL_MODE_PROT64 : cs_db
2705 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2706
ad312c7c 2707 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 2708
0cb5762e
AP		 2709 /* Only allow emulation of specific instructions on #UD
2710 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 2711 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 2712 if (emulation_type & EMULTYPE_TRAP_UD) {
2713 if (!c->twobyte)
2714 return EMULATE_FAIL;
2715 switch (c->b) {
2716 case 0x01: /* VMMCALL */
2717 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2718 return EMULATE_FAIL;
2719 break;
2720 case 0x34: /* sysenter */
2721 case 0x35: /* sysexit */
2722 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2723 return EMULATE_FAIL;
2724 break;
2725 case 0x05: /* syscall */
2726 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2727 return EMULATE_FAIL;
2728 break;
2729 default:
2730 return EMULATE_FAIL;
2731 }
2732
2733 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2734 return EMULATE_FAIL;
2735 }
571008da 2736
f2b5756b 2737 ++vcpu->stat.insn_emulation;
bbd9b64e 2738 if (r) {
f2b5756b 2739 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2740 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2741 return EMULATE_DONE;
2742 return EMULATE_FAIL;
2743 }
2744 }
2745
ba8afb6b
GN		 2746 if (emulation_type & EMULTYPE_SKIP) {
2747 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2748 return EMULATE_DONE;
2749 }
2750
ad312c7c 2751 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2752 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2753
2754 if (r == 0)
2755 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2756
ad312c7c 2757 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2758 return EMULATE_DO_MMIO;
2759
2760 if ((r || vcpu->mmio_is_write) && run) {
2761 run->exit_reason = KVM_EXIT_MMIO;
2762 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2763 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2764 run->mmio.len = vcpu->mmio_size;
2765 run->mmio.is_write = vcpu->mmio_is_write;
2766 }
2767
2768 if (r) {
2769 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2770 return EMULATE_DONE;
2771 if (!vcpu->mmio_needed) {
2772 kvm_report_emulation_failure(vcpu, "mmio");
2773 return EMULATE_FAIL;
2774 }
2775 return EMULATE_DO_MMIO;
2776 }
2777
ad312c7c 2778 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2779
2780 if (vcpu->mmio_is_write) {
2781 vcpu->mmio_needed = 0;
2782 return EMULATE_DO_MMIO;
2783 }
2784
2785 return EMULATE_DONE;
2786}
2787EXPORT_SYMBOL_GPL(emulate_instruction);
2788
de7d789a
CO		 2789static int pio_copy_data(struct kvm_vcpu *vcpu)
2790{
ad312c7c 2791 void *p = vcpu->arch.pio_data;
0f346074 2792 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2793 unsigned bytes;
0f346074 2794 int ret;
de7d789a 2795
ad312c7c
ZX		 2796 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2797 if (vcpu->arch.pio.in)
0f346074 2798 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2799 else
0f346074
IE		 2800 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2801 return ret;
de7d789a
CO		 2802}
2803
2804int complete_pio(struct kvm_vcpu *vcpu)
2805{
ad312c7c 2806 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2807 long delta;
2808 int r;
5fdbf976 2809 unsigned long val;
de7d789a
CO		 2810
2811 if (!io->string) {
5fdbf976
MT		 2812 if (io->in) {
2813 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2814 memcpy(&val, vcpu->arch.pio_data, io->size);
2815 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2816 }
de7d789a
CO		 2817 } else {
2818 if (io->in) {
2819 r = pio_copy_data(vcpu);
5fdbf976 2820 if (r)
de7d789a 2821 return r;
de7d789a
CO		 2822 }
2823
2824 delta = 1;
2825 if (io->rep) {
2826 delta *= io->cur_count;
2827 /*
2828 * The size of the register should really depend on
2829 * current address size.
2830 */
5fdbf976
MT		 2831 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2832 val -= delta;
2833 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2834 }
2835 if (io->down)
2836 delta = -delta;
2837 delta *= io->size;
5fdbf976
MT		 2838 if (io->in) {
2839 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2840 val += delta;
2841 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2842 } else {
2843 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2844 val += delta;
2845 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2846 }
de7d789a
CO		 2847 }
2848
de7d789a
CO		 2849 io->count -= io->cur_count;
2850 io->cur_count = 0;
2851
2852 return 0;
2853}
2854
bda9020e 2855static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 2856{
2857 /* TODO: String I/O for in kernel device */
bda9020e 2858 int r;
de7d789a 2859
ad312c7c 2860 if (vcpu->arch.pio.in)
bda9020e
MT		 2861 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2862 vcpu->arch.pio.size, pd);
de7d789a 2863 else
bda9020e
MT		 2864 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2865 vcpu->arch.pio.size, pd);
2866 return r;
de7d789a
CO		 2867}
2868
bda9020e 2869static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 2870{
ad312c7c
ZX		 2871 struct kvm_pio_request *io = &vcpu->arch.pio;
2872 void *pd = vcpu->arch.pio_data;
bda9020e 2873 int i, r = 0;
de7d789a 2874
de7d789a 2875 for (i = 0; i < io->cur_count; i++) {
bda9020e
MT		 2876 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
2877 io->port, io->size, pd)) {
2878 r = -EOPNOTSUPP;
2879 break;
2880 }
de7d789a
CO		 2881 pd += io->size;
2882 }
bda9020e 2883 return r;
de7d789a
CO		 2884}
2885
2886int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2887 int size, unsigned port)
2888{
5fdbf976 2889 unsigned long val;
de7d789a
CO		 2890
2891 vcpu->run->exit_reason = KVM_EXIT_IO;
2892 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2893 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2894 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2895 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2896 vcpu->run->io.port = vcpu->arch.pio.port = port;
2897 vcpu->arch.pio.in = in;
2898 vcpu->arch.pio.string = 0;
2899 vcpu->arch.pio.down = 0;
ad312c7c 2900 vcpu->arch.pio.rep = 0;
de7d789a 2901
229456fc
MT		 2902 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2903 size, 1);
2714d1d3 2904
5fdbf976
MT		 2905 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2906 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2907
bda9020e 2908 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 2909 complete_pio(vcpu);
2910 return 1;
2911 }
2912 return 0;
2913}
2914EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2915
2916int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2917 int size, unsigned long count, int down,
2918 gva_t address, int rep, unsigned port)
2919{
2920 unsigned now, in_page;
0f346074 2921 int ret = 0;
de7d789a
CO		 2922
2923 vcpu->run->exit_reason = KVM_EXIT_IO;
2924 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2925 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2926 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2927 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2928 vcpu->run->io.port = vcpu->arch.pio.port = port;
2929 vcpu->arch.pio.in = in;
2930 vcpu->arch.pio.string = 1;
2931 vcpu->arch.pio.down = down;
ad312c7c 2932 vcpu->arch.pio.rep = rep;
de7d789a 2933
229456fc
MT		 2934 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2935 size, count);
2714d1d3 2936
de7d789a
CO		 2937 if (!count) {
2938 kvm_x86_ops->skip_emulated_instruction(vcpu);
2939 return 1;
2940 }
2941
2942 if (!down)
2943 in_page = PAGE_SIZE - offset_in_page(address);
2944 else
2945 in_page = offset_in_page(address) + size;
2946 now = min(count, (unsigned long)in_page / size);
0f346074 2947 if (!now)
de7d789a 2948 now = 1;
de7d789a
CO		 2949 if (down) {
2950 /*
2951 * String I/O in reverse. Yuck. Kill the guest, fix later.
2952 */
2953 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2954 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2955 return 1;
2956 }
2957 vcpu->run->io.count = now;
ad312c7c 2958 vcpu->arch.pio.cur_count = now;
de7d789a 2959
ad312c7c 2960 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2961 kvm_x86_ops->skip_emulated_instruction(vcpu);
2962
0f346074 2963 vcpu->arch.pio.guest_gva = address;
de7d789a 2964
ad312c7c 2965 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2966 /* string PIO write */
2967 ret = pio_copy_data(vcpu);
0f346074
IE		 2968 if (ret == X86EMUL_PROPAGATE_FAULT) {
2969 kvm_inject_gp(vcpu, 0);
2970 return 1;
2971 }
bda9020e 2972 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 2973 complete_pio(vcpu);
ad312c7c 2974 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2975 ret = 1;
2976 }
bda9020e
MT		 2977 }
2978 /* no string PIO read support yet */
de7d789a
CO		 2979
2980 return ret;
2981}
2982EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2983
c8076604
GH		 2984static void bounce_off(void *info)
2985{
2986 /* nothing */
2987}
2988
2989static unsigned int ref_freq;
2990static unsigned long tsc_khz_ref;
2991
2992static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
2993 void *data)
2994{
2995 struct cpufreq_freqs *freq = data;
2996 struct kvm *kvm;
2997 struct kvm_vcpu *vcpu;
2998 int i, send_ipi = 0;
2999
3000 if (!ref_freq)
3001 ref_freq = freq->old;
3002
3003 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3004 return 0;
3005 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3006 return 0;
3007 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
3008
3009 spin_lock(&kvm_lock);
3010 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3011 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3012 if (vcpu->cpu != freq->cpu)
3013 continue;
3014 if (!kvm_request_guest_time_update(vcpu))
3015 continue;
3016 if (vcpu->cpu != smp_processor_id())
3017 send_ipi++;
3018 }
3019 }
3020 spin_unlock(&kvm_lock);
3021
3022 if (freq->old < freq->new && send_ipi) {
3023 /*
3024 * We upscale the frequency. Must make the guest
3025 * doesn't see old kvmclock values while running with
3026 * the new frequency, otherwise we risk the guest sees
3027 * time go backwards.
3028 *
3029 * In case we update the frequency for another cpu
3030 * (which might be in guest context) send an interrupt
3031 * to kick the cpu out of guest context. Next time
3032 * guest context is entered kvmclock will be updated,
3033 * so the guest will not see stale values.
3034 */
3035 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3036 }
3037 return 0;
3038}
3039
3040static struct notifier_block kvmclock_cpufreq_notifier_block = {
3041 .notifier_call = kvmclock_cpufreq_notifier
3042};
3043
f8c16bba 3044int kvm_arch_init(void *opaque)
043405e1 3045{
c8076604 3046 int r, cpu;
f8c16bba
ZX		 3047 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3048
f8c16bba
ZX		 3049 if (kvm_x86_ops) {
3050 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3051 r = -EEXIST;
3052 goto out;
f8c16bba
ZX		 3053 }
3054
3055 if (!ops->cpu_has_kvm_support()) {
3056 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3057 r = -EOPNOTSUPP;
3058 goto out;
f8c16bba
ZX		 3059 }
3060 if (ops->disabled_by_bios()) {
3061 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3062 r = -EOPNOTSUPP;
3063 goto out;
f8c16bba
ZX		 3064 }
3065
97db56ce
AK		 3066 r = kvm_mmu_module_init();
3067 if (r)
3068 goto out;
3069
3070 kvm_init_msr_list();
3071
f8c16bba 3072 kvm_x86_ops = ops;
56c6d28a 3073 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3074 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3075 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3076 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604
GH		 3077
3078 for_each_possible_cpu(cpu)
3079 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3080 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3081 tsc_khz_ref = tsc_khz;
3082 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3083 CPUFREQ_TRANSITION_NOTIFIER);
3084 }
3085
f8c16bba 3086 return 0;
56c6d28a
ZX		 3087
3088out:
56c6d28a 3089 return r;
043405e1 3090}
8776e519 3091
f8c16bba
ZX		 3092void kvm_arch_exit(void)
3093{
888d256e
JK		 3094 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3095 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3096 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3097 kvm_x86_ops = NULL;
56c6d28a
ZX		 3098 kvm_mmu_module_exit();
3099}
f8c16bba 3100
8776e519
HB		 3101int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3102{
3103 ++vcpu->stat.halt_exits;
3104 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3105 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3106 return 1;
3107 } else {
3108 vcpu->run->exit_reason = KVM_EXIT_HLT;
3109 return 0;
3110 }
3111}
3112EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3113
2f333bcb
MT		 3114static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3115 unsigned long a1)
3116{
3117 if (is_long_mode(vcpu))
3118 return a0;
3119 else
3120 return a0 | ((gpa_t)a1 << 32);
3121}
3122
8776e519
HB		 3123int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3124{
3125 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3126 int r = 1;
8776e519 3127
5fdbf976
MT		 3128 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3129 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3130 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3131 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3132 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3133
229456fc 3134 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3135
8776e519
HB		 3136 if (!is_long_mode(vcpu)) {
3137 nr &= 0xFFFFFFFF;
3138 a0 &= 0xFFFFFFFF;
3139 a1 &= 0xFFFFFFFF;
3140 a2 &= 0xFFFFFFFF;
3141 a3 &= 0xFFFFFFFF;
3142 }
3143
3144 switch (nr) {
b93463aa
AK		 3145 case KVM_HC_VAPIC_POLL_IRQ:
3146 ret = 0;
3147 break;
2f333bcb
MT		 3148 case KVM_HC_MMU_OP:
3149 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3150 break;
8776e519
HB		 3151 default:
3152 ret = -KVM_ENOSYS;
3153 break;
3154 }
5fdbf976 3155 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3156 ++vcpu->stat.hypercalls;
2f333bcb 3157 return r;
8776e519
HB		 3158}
3159EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3160
3161int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3162{
3163 char instruction[3];
3164 int ret = 0;
5fdbf976 3165 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3166
8776e519
HB		 3167
3168 /*
3169 * Blow out the MMU to ensure that no other VCPU has an active mapping
3170 * to ensure that the updated hypercall appears atomically across all
3171 * VCPUs.
3172 */
3173 kvm_mmu_zap_all(vcpu->kvm);
3174
8776e519 3175 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3176 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3177 != X86EMUL_CONTINUE)
3178 ret = -EFAULT;
3179
8776e519
HB		 3180 return ret;
3181}
3182
3183static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3184{
3185 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3186}
3187
3188void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3189{
3190 struct descriptor_table dt = { limit, base };
3191
3192 kvm_x86_ops->set_gdt(vcpu, &dt);
3193}
3194
3195void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3196{
3197 struct descriptor_table dt = { limit, base };
3198
3199 kvm_x86_ops->set_idt(vcpu, &dt);
3200}
3201
3202void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3203 unsigned long *rflags)
3204{
2d3ad1f4 3205 kvm_lmsw(vcpu, msw);
8776e519
HB		 3206 *rflags = kvm_x86_ops->get_rflags(vcpu);
3207}
3208
3209unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3210{
54e445ca
JR		 3211 unsigned long value;
3212
8776e519
HB		 3213 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3214 switch (cr) {
3215 case 0:
54e445ca
JR		 3216 value = vcpu->arch.cr0;
3217 break;
8776e519 3218 case 2:
54e445ca
JR		 3219 value = vcpu->arch.cr2;
3220 break;
8776e519 3221 case 3:
54e445ca
JR		 3222 value = vcpu->arch.cr3;
3223 break;
8776e519 3224 case 4:
54e445ca
JR		 3225 value = vcpu->arch.cr4;
3226 break;
152ff9be 3227 case 8:
54e445ca
JR		 3228 value = kvm_get_cr8(vcpu);
3229 break;
8776e519 3230 default:
b8688d51 3231 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3232 return 0;
3233 }
54e445ca
JR		 3234
3235 return value;
8776e519
HB		 3236}
3237
3238void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3239 unsigned long *rflags)
3240{
3241 switch (cr) {
3242 case 0:
2d3ad1f4 3243 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 3244 *rflags = kvm_x86_ops->get_rflags(vcpu);
3245 break;
3246 case 2:
ad312c7c 3247 vcpu->arch.cr2 = val;
8776e519
HB		 3248 break;
3249 case 3:
2d3ad1f4 3250 kvm_set_cr3(vcpu, val);
8776e519
HB		 3251 break;
3252 case 4:
2d3ad1f4 3253 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3254 break;
152ff9be 3255 case 8:
2d3ad1f4 3256 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3257 break;
8776e519 3258 default:
b8688d51 3259 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3260 }
3261}
3262
07716717
DK		 3263static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3264{
ad312c7c
ZX		 3265 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3266 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3267
3268 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3269 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3270 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3271 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3272 if (ej->function == e->function) {
3273 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3274 return j;
3275 }
3276 }
3277 return 0; /* silence gcc, even though control never reaches here */
3278}
3279
3280/* find an entry with matching function, matching index (if needed), and that
3281 * should be read next (if it's stateful) */
3282static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3283 u32 function, u32 index)
3284{
3285 if (e->function != function)
3286 return 0;
3287 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3288 return 0;
3289 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3290 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3291 return 0;
3292 return 1;
3293}
3294
d8017474
AG		 3295struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3296 u32 function, u32 index)
8776e519
HB		 3297{
3298 int i;
d8017474 3299 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3300
ad312c7c 3301 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3302 struct kvm_cpuid_entry2 *e;
3303
ad312c7c 3304 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3305 if (is_matching_cpuid_entry(e, function, index)) {
3306 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3307 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3308 best = e;
3309 break;
3310 }
3311 /*
3312 * Both basic or both extended?
3313 */
3314 if (((e->function ^ function) & 0x80000000) == 0)
3315 if (!best || e->function > best->function)
3316 best = e;
3317 }
d8017474
AG		 3318 return best;
3319}
3320
82725b20
DE		 3321int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3322{
3323 struct kvm_cpuid_entry2 *best;
3324
3325 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3326 if (best)
3327 return best->eax & 0xff;
3328 return 36;
3329}
3330
d8017474
AG		 3331void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3332{
3333 u32 function, index;
3334 struct kvm_cpuid_entry2 *best;
3335
3336 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3337 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3338 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3339 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3340 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3341 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3342 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3343 if (best) {
5fdbf976
MT		 3344 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3345 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3346 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3347 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3348 }
8776e519 3349 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3350 trace_kvm_cpuid(function,
3351 kvm_register_read(vcpu, VCPU_REGS_RAX),
3352 kvm_register_read(vcpu, VCPU_REGS_RBX),
3353 kvm_register_read(vcpu, VCPU_REGS_RCX),
3354 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3355}
3356EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3357
b6c7a5dc
HB		 3358/*
3359 * Check if userspace requested an interrupt window, and that the
3360 * interrupt window is open.
3361 *
3362 * No need to exit to userspace if we already have an interrupt queued.
3363 */
3364static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3365 struct kvm_run *kvm_run)
3366{
8061823a 3367 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
b6c7a5dc 3368 kvm_run->request_interrupt_window &&
5df56646 3369 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3370}
3371
3372static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3373 struct kvm_run *kvm_run)
3374{
3375 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3376 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3377 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3378 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3379 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3380 else
b6c7a5dc 3381 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3382 kvm_arch_interrupt_allowed(vcpu) &&
3383 !kvm_cpu_has_interrupt(vcpu) &&
3384 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3385}
3386
b93463aa
AK		 3387static void vapic_enter(struct kvm_vcpu *vcpu)
3388{
3389 struct kvm_lapic *apic = vcpu->arch.apic;
3390 struct page *page;
3391
3392 if (!apic || !apic->vapic_addr)
3393 return;
3394
3395 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3396
3397 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3398}
3399
3400static void vapic_exit(struct kvm_vcpu *vcpu)
3401{
3402 struct kvm_lapic *apic = vcpu->arch.apic;
3403
3404 if (!apic || !apic->vapic_addr)
3405 return;
3406
f8b78fa3 3407 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3408 kvm_release_page_dirty(apic->vapic_page);
3409 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3410 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3411}
3412
95ba8273
GN		 3413static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3414{
3415 int max_irr, tpr;
3416
3417 if (!kvm_x86_ops->update_cr8_intercept)
3418 return;
3419
8db3baa2
GN		 3420 if (!vcpu->arch.apic->vapic_addr)
3421 max_irr = kvm_lapic_find_highest_irr(vcpu);
3422 else
3423 max_irr = -1;
95ba8273
GN		 3424
3425 if (max_irr != -1)
3426 max_irr >>= 4;
3427
3428 tpr = kvm_lapic_get_cr8(vcpu);
3429
3430 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3431}
3432
6a8b1d13 3433static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
95ba8273
GN		 3434{
3435 /* try to reinject previous events if any */
3436 if (vcpu->arch.nmi_injected) {
3437 kvm_x86_ops->set_nmi(vcpu);
3438 return;
3439 }
3440
3441 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3442 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3443 return;
3444 }
3445
3446 /* try to inject new event if pending */
3447 if (vcpu->arch.nmi_pending) {
3448 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3449 vcpu->arch.nmi_pending = false;
3450 vcpu->arch.nmi_injected = true;
3451 kvm_x86_ops->set_nmi(vcpu);
3452 }
3453 } else if (kvm_cpu_has_interrupt(vcpu)) {
3454 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3455 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3456 false);
3457 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3458 }
3459 }
3460}
3461
d7690175 3462static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3463{
3464 int r;
6a8b1d13
GN		 3465 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3466 kvm_run->request_interrupt_window;
b6c7a5dc 3467
2e53d63a
MT		 3468 if (vcpu->requests)
3469 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3470 kvm_mmu_unload(vcpu);
3471
b6c7a5dc
HB		 3472 r = kvm_mmu_reload(vcpu);
3473 if (unlikely(r))
3474 goto out;
3475
2f52d58c
AK		 3476 if (vcpu->requests) {
3477 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3478 __kvm_migrate_timers(vcpu);
c8076604
GH		 3479 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3480 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3481 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3482 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3483 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3484 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3485 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3486 &vcpu->requests)) {
3487 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3488 r = 0;
3489 goto out;
3490 }
71c4dfaf
JR		 3491 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3492 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3493 r = 0;
3494 goto out;
3495 }
2f52d58c 3496 }
b93463aa 3497
b6c7a5dc
HB		 3498 preempt_disable();
3499
3500 kvm_x86_ops->prepare_guest_switch(vcpu);
3501 kvm_load_guest_fpu(vcpu);
3502
3503 local_irq_disable();
3504
32f88400
MT		 3505 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3506 smp_mb__after_clear_bit();
3507
d7690175 3508 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 3509 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 3510 local_irq_enable();
3511 preempt_enable();
3512 r = 1;
3513 goto out;
3514 }
3515
ad312c7c 3516 if (vcpu->arch.exception.pending)
298101da 3517 __queue_exception(vcpu);
eb9774f0 3518 else
95ba8273 3519 inject_pending_irq(vcpu, kvm_run);
b6c7a5dc 3520
6a8b1d13
GN		 3521 /* enable NMI/IRQ window open exits if needed */
3522 if (vcpu->arch.nmi_pending)
3523 kvm_x86_ops->enable_nmi_window(vcpu);
3524 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3525 kvm_x86_ops->enable_irq_window(vcpu);
3526
95ba8273 3527 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3528 update_cr8_intercept(vcpu);
3529 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3530 }
b93463aa 3531
3200f405
MT		 3532 up_read(&vcpu->kvm->slots_lock);
3533
b6c7a5dc
HB		 3534 kvm_guest_enter();
3535
42dbaa5a
JK		 3536 get_debugreg(vcpu->arch.host_dr6, 6);
3537 get_debugreg(vcpu->arch.host_dr7, 7);
3538 if (unlikely(vcpu->arch.switch_db_regs)) {
3539 get_debugreg(vcpu->arch.host_db[0], 0);
3540 get_debugreg(vcpu->arch.host_db[1], 1);
3541 get_debugreg(vcpu->arch.host_db[2], 2);
3542 get_debugreg(vcpu->arch.host_db[3], 3);
3543
3544 set_debugreg(0, 7);
3545 set_debugreg(vcpu->arch.eff_db[0], 0);
3546 set_debugreg(vcpu->arch.eff_db[1], 1);
3547 set_debugreg(vcpu->arch.eff_db[2], 2);
3548 set_debugreg(vcpu->arch.eff_db[3], 3);
3549 }
b6c7a5dc 3550
229456fc 3551 trace_kvm_entry(vcpu->vcpu_id);
b6c7a5dc
HB		 3552 kvm_x86_ops->run(vcpu, kvm_run);
3553
42dbaa5a
JK		 3554 if (unlikely(vcpu->arch.switch_db_regs)) {
3555 set_debugreg(0, 7);
3556 set_debugreg(vcpu->arch.host_db[0], 0);
3557 set_debugreg(vcpu->arch.host_db[1], 1);
3558 set_debugreg(vcpu->arch.host_db[2], 2);
3559 set_debugreg(vcpu->arch.host_db[3], 3);
3560 }
3561 set_debugreg(vcpu->arch.host_dr6, 6);
3562 set_debugreg(vcpu->arch.host_dr7, 7);
3563
32f88400 3564 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3565 local_irq_enable();
3566
3567 ++vcpu->stat.exits;
3568
3569 /*
3570 * We must have an instruction between local_irq_enable() and
3571 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3572 * the interrupt shadow. The stat.exits increment will do nicely.
3573 * But we need to prevent reordering, hence this barrier():
3574 */
3575 barrier();
3576
3577 kvm_guest_exit();
3578
3579 preempt_enable();
3580
3200f405
MT		 3581 down_read(&vcpu->kvm->slots_lock);
3582
b6c7a5dc
HB		 3583 /*
3584 * Profile KVM exit RIPs:
3585 */
3586 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3587 unsigned long rip = kvm_rip_read(vcpu);
3588 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3589 }
3590
298101da 3591
b93463aa
AK		 3592 kvm_lapic_sync_from_vapic(vcpu);
3593
b6c7a5dc 3594 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3595out:
3596 return r;
3597}
b6c7a5dc 3598
09cec754 3599
d7690175
MT		 3600static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3601{
3602 int r;
3603
3604 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3605 pr_debug("vcpu %d received sipi with vector # %x\n",
3606 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3607 kvm_lapic_reset(vcpu);
5f179287 3608 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3609 if (r)
3610 return r;
3611 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3612 }
3613
d7690175
MT		 3614 down_read(&vcpu->kvm->slots_lock);
3615 vapic_enter(vcpu);
3616
3617 r = 1;
3618 while (r > 0) {
af2152f5 3619 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3620 r = vcpu_enter_guest(vcpu, kvm_run);
3621 else {
3622 up_read(&vcpu->kvm->slots_lock);
3623 kvm_vcpu_block(vcpu);
3624 down_read(&vcpu->kvm->slots_lock);
3625 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3626 {
3627 switch(vcpu->arch.mp_state) {
3628 case KVM_MP_STATE_HALTED:
d7690175 3629 vcpu->arch.mp_state =
09cec754
GN		 3630 KVM_MP_STATE_RUNNABLE;
3631 case KVM_MP_STATE_RUNNABLE:
3632 break;
3633 case KVM_MP_STATE_SIPI_RECEIVED:
3634 default:
3635 r = -EINTR;
3636 break;
3637 }
3638 }
d7690175
MT		 3639 }
3640
09cec754
GN		 3641 if (r <= 0)
3642 break;
3643
3644 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3645 if (kvm_cpu_has_pending_timer(vcpu))
3646 kvm_inject_pending_timer_irqs(vcpu);
3647
3648 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3649 r = -EINTR;
3650 kvm_run->exit_reason = KVM_EXIT_INTR;
3651 ++vcpu->stat.request_irq_exits;
3652 }
3653 if (signal_pending(current)) {
3654 r = -EINTR;
3655 kvm_run->exit_reason = KVM_EXIT_INTR;
3656 ++vcpu->stat.signal_exits;
3657 }
3658 if (need_resched()) {
3659 up_read(&vcpu->kvm->slots_lock);
3660 kvm_resched(vcpu);
3661 down_read(&vcpu->kvm->slots_lock);
d7690175 3662 }
b6c7a5dc
HB		 3663 }
3664
d7690175 3665 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3666 post_kvm_run_save(vcpu, kvm_run);
3667
b93463aa
AK		 3668 vapic_exit(vcpu);
3669
b6c7a5dc
HB		 3670 return r;
3671}
3672
3673int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3674{
3675 int r;
3676 sigset_t sigsaved;
3677
3678 vcpu_load(vcpu);
3679
ac9f6dc0
AK		 3680 if (vcpu->sigset_active)
3681 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3682
a4535290 3683 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3684 kvm_vcpu_block(vcpu);
d7690175 3685 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3686 r = -EAGAIN;
3687 goto out;
b6c7a5dc
HB		 3688 }
3689
b6c7a5dc
HB		 3690 /* re-sync apic's tpr */
3691 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3692 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3693
ad312c7c 3694 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3695 r = complete_pio(vcpu);
3696 if (r)
3697 goto out;
3698 }
3699#if CONFIG_HAS_IOMEM
3700 if (vcpu->mmio_needed) {
3701 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3702 vcpu->mmio_read_completed = 1;
3703 vcpu->mmio_needed = 0;
3200f405
MT		 3704
3705 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3706 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3707 vcpu->arch.mmio_fault_cr2, 0,
3708 EMULTYPE_NO_DECODE);
3200f405 3709 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3710 if (r == EMULATE_DO_MMIO) {
3711 /*
3712 * Read-modify-write. Back to userspace.
3713 */
3714 r = 0;
3715 goto out;
3716 }
3717 }
3718#endif
5fdbf976
MT		 3719 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3720 kvm_register_write(vcpu, VCPU_REGS_RAX,
3721 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3722
3723 r = __vcpu_run(vcpu, kvm_run);
3724
3725out:
3726 if (vcpu->sigset_active)
3727 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3728
3729 vcpu_put(vcpu);
3730 return r;
3731}
3732
3733int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3734{
3735 vcpu_load(vcpu);
3736
5fdbf976
MT		 3737 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3738 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3739 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3740 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3741 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3742 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3743 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3744 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3745#ifdef CONFIG_X86_64
5fdbf976
MT		 3746 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3747 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3748 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3749 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3750 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3751 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3752 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3753 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3754#endif
3755
5fdbf976 3756 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3757 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3758
3759 /*
3760 * Don't leak debug flags in case they were set for guest debugging
3761 */
d0bfb940 3762 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3763 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3764
3765 vcpu_put(vcpu);
3766
3767 return 0;
3768}
3769
3770int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3771{
3772 vcpu_load(vcpu);
3773
5fdbf976
MT		 3774 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3775 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3776 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3777 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3778 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3779 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3780 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3781 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3782#ifdef CONFIG_X86_64
5fdbf976
MT		 3783 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3784 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3785 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3786 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3787 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3788 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3789 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3790 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3791
b6c7a5dc
HB		 3792#endif
3793
5fdbf976 3794 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3795 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3796
b6c7a5dc 3797
b4f14abd
JK		 3798 vcpu->arch.exception.pending = false;
3799
b6c7a5dc
HB		 3800 vcpu_put(vcpu);
3801
3802 return 0;
3803}
3804
3e6e0aab
GT		 3805void kvm_get_segment(struct kvm_vcpu *vcpu,
3806 struct kvm_segment *var, int seg)
b6c7a5dc 3807{
14af3f3c 3808 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3809}
3810
3811void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3812{
3813 struct kvm_segment cs;
3814
3e6e0aab 3815 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3816 *db = cs.db;
3817 *l = cs.l;
3818}
3819EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3820
3821int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3822 struct kvm_sregs *sregs)
3823{
3824 struct descriptor_table dt;
b6c7a5dc
HB		 3825
3826 vcpu_load(vcpu);
3827
3e6e0aab
GT		 3828 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3829 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3830 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3831 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3832 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3833 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3834
3e6e0aab
GT		 3835 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3836 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3837
3838 kvm_x86_ops->get_idt(vcpu, &dt);
3839 sregs->idt.limit = dt.limit;
3840 sregs->idt.base = dt.base;
3841 kvm_x86_ops->get_gdt(vcpu, &dt);
3842 sregs->gdt.limit = dt.limit;
3843 sregs->gdt.base = dt.base;
3844
3845 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3846 sregs->cr0 = vcpu->arch.cr0;
3847 sregs->cr2 = vcpu->arch.cr2;
3848 sregs->cr3 = vcpu->arch.cr3;
3849 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3850 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3851 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3852 sregs->apic_base = kvm_get_apic_base(vcpu);
3853
923c61bb 3854 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3855
36752c9b 3856 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3857 set_bit(vcpu->arch.interrupt.nr,
3858 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3859
b6c7a5dc
HB		 3860 vcpu_put(vcpu);
3861
3862 return 0;
3863}
3864
62d9f0db
MT		 3865int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3866 struct kvm_mp_state *mp_state)
3867{
3868 vcpu_load(vcpu);
3869 mp_state->mp_state = vcpu->arch.mp_state;
3870 vcpu_put(vcpu);
3871 return 0;
3872}
3873
3874int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3875 struct kvm_mp_state *mp_state)
3876{
3877 vcpu_load(vcpu);
3878 vcpu->arch.mp_state = mp_state->mp_state;
3879 vcpu_put(vcpu);
3880 return 0;
3881}
3882
3e6e0aab 3883static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3884 struct kvm_segment *var, int seg)
3885{
14af3f3c 3886 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3887}
3888
37817f29
IE		 3889static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3890 struct kvm_segment *kvm_desct)
3891{
3892 kvm_desct->base = seg_desc->base0;
3893 kvm_desct->base |= seg_desc->base1 << 16;
3894 kvm_desct->base |= seg_desc->base2 << 24;
3895 kvm_desct->limit = seg_desc->limit0;
3896 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3897 if (seg_desc->g) {
3898 kvm_desct->limit <<= 12;
3899 kvm_desct->limit |= 0xfff;
3900 }
37817f29
IE		 3901 kvm_desct->selector = selector;
3902 kvm_desct->type = seg_desc->type;
3903 kvm_desct->present = seg_desc->p;
3904 kvm_desct->dpl = seg_desc->dpl;
3905 kvm_desct->db = seg_desc->d;
3906 kvm_desct->s = seg_desc->s;
3907 kvm_desct->l = seg_desc->l;
3908 kvm_desct->g = seg_desc->g;
3909 kvm_desct->avl = seg_desc->avl;
3910 if (!selector)
3911 kvm_desct->unusable = 1;
3912 else
3913 kvm_desct->unusable = 0;
3914 kvm_desct->padding = 0;
3915}
3916
b8222ad2
AS		 3917static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3918 u16 selector,
3919 struct descriptor_table *dtable)
37817f29
IE		 3920{
3921 if (selector & 1 << 2) {
3922 struct kvm_segment kvm_seg;
3923
3e6e0aab 3924 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3925
3926 if (kvm_seg.unusable)
3927 dtable->limit = 0;
3928 else
3929 dtable->limit = kvm_seg.limit;
3930 dtable->base = kvm_seg.base;
3931 }
3932 else
3933 kvm_x86_ops->get_gdt(vcpu, dtable);
3934}
3935
3936/* allowed just for 8 bytes segments */
3937static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3938 struct desc_struct *seg_desc)
3939{
98899aa0 3940 gpa_t gpa;
37817f29
IE		 3941 struct descriptor_table dtable;
3942 u16 index = selector >> 3;
3943
b8222ad2 3944 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3945
3946 if (dtable.limit < index * 8 + 7) {
3947 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3948 return 1;
3949 }
98899aa0
MT		 3950 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3951 gpa += index * 8;
3952 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3953}
3954
3955/* allowed just for 8 bytes segments */
3956static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3957 struct desc_struct *seg_desc)
3958{
98899aa0 3959 gpa_t gpa;
37817f29
IE		 3960 struct descriptor_table dtable;
3961 u16 index = selector >> 3;
3962
b8222ad2 3963 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3964
3965 if (dtable.limit < index * 8 + 7)
3966 return 1;
98899aa0
MT		 3967 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3968 gpa += index * 8;
3969 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3970}
3971
3972static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3973 struct desc_struct *seg_desc)
3974{
3975 u32 base_addr;
3976
3977 base_addr = seg_desc->base0;
3978 base_addr |= (seg_desc->base1 << 16);
3979 base_addr |= (seg_desc->base2 << 24);
3980
98899aa0 3981 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3982}
3983
37817f29
IE		 3984static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3985{
3986 struct kvm_segment kvm_seg;
3987
3e6e0aab 3988 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3989 return kvm_seg.selector;
3990}
3991
3992static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3993 u16 selector,
3994 struct kvm_segment *kvm_seg)
3995{
3996 struct desc_struct seg_desc;
3997
3998 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3999 return 1;
4000 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4001 return 0;
4002}
4003
2259e3a7 4004static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4005{
4006 struct kvm_segment segvar = {
4007 .base = selector << 4,
4008 .limit = 0xffff,
4009 .selector = selector,
4010 .type = 3,
4011 .present = 1,
4012 .dpl = 3,
4013 .db = 0,
4014 .s = 1,
4015 .l = 0,
4016 .g = 0,
4017 .avl = 0,
4018 .unusable = 0,
4019 };
4020 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4021 return 0;
4022}
4023
3e6e0aab
GT		 4024int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4025 int type_bits, int seg)
37817f29
IE		 4026{
4027 struct kvm_segment kvm_seg;
4028
f4bbd9aa
AK		 4029 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4030 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4031 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4032 return 1;
4033 kvm_seg.type |= type_bits;
4034
4035 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4036 seg != VCPU_SREG_LDTR)
4037 if (!kvm_seg.s)
4038 kvm_seg.unusable = 1;
4039
3e6e0aab 4040 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4041 return 0;
4042}
4043
4044static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4045 struct tss_segment_32 *tss)
4046{
4047 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4048 tss->eip = kvm_rip_read(vcpu);
37817f29 4049 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4050 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4051 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4052 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4053 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4054 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4055 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4056 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4057 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4058 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4059 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4060 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4061 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4062 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4063 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4064 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4065}
4066
4067static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4068 struct tss_segment_32 *tss)
4069{
4070 kvm_set_cr3(vcpu, tss->cr3);
4071
5fdbf976 4072 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 4073 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4074
5fdbf976
MT		 4075 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4076 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4077 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4078 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4079 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4080 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4081 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4082 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4083
3e6e0aab 4084 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4085 return 1;
4086
3e6e0aab 4087 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4088 return 1;
4089
3e6e0aab 4090 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4091 return 1;
4092
3e6e0aab 4093 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4094 return 1;
4095
3e6e0aab 4096 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4097 return 1;
4098
3e6e0aab 4099 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4100 return 1;
4101
3e6e0aab 4102 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4103 return 1;
4104 return 0;
4105}
4106
4107static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4108 struct tss_segment_16 *tss)
4109{
5fdbf976 4110 tss->ip = kvm_rip_read(vcpu);
37817f29 4111 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4112 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4113 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4114 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4115 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4116 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4117 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4118 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4119 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4120
4121 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4122 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4123 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4124 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4125 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4126 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4127}
4128
4129static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4130 struct tss_segment_16 *tss)
4131{
5fdbf976 4132 kvm_rip_write(vcpu, tss->ip);
37817f29 4133 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4134 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4135 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4136 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4137 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4138 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4139 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4140 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4141 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4142
3e6e0aab 4143 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4144 return 1;
4145
3e6e0aab 4146 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4147 return 1;
4148
3e6e0aab 4149 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4150 return 1;
4151
3e6e0aab 4152 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4153 return 1;
4154
3e6e0aab 4155 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4156 return 1;
4157 return 0;
4158}
4159
8b2cf73c 4160static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4161 u16 old_tss_sel, u32 old_tss_base,
4162 struct desc_struct *nseg_desc)
37817f29
IE		 4163{
4164 struct tss_segment_16 tss_segment_16;
4165 int ret = 0;
4166
34198bf8
MT		 4167 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4168 sizeof tss_segment_16))
37817f29
IE		 4169 goto out;
4170
4171 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4172
34198bf8
MT		 4173 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4174 sizeof tss_segment_16))
37817f29 4175 goto out;
34198bf8
MT		 4176
4177 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4178 &tss_segment_16, sizeof tss_segment_16))
4179 goto out;
4180
b237ac37
GN		 4181 if (old_tss_sel != 0xffff) {
4182 tss_segment_16.prev_task_link = old_tss_sel;
4183
4184 if (kvm_write_guest(vcpu->kvm,
4185 get_tss_base_addr(vcpu, nseg_desc),
4186 &tss_segment_16.prev_task_link,
4187 sizeof tss_segment_16.prev_task_link))
4188 goto out;
4189 }
4190
37817f29
IE		 4191 if (load_state_from_tss16(vcpu, &tss_segment_16))
4192 goto out;
4193
4194 ret = 1;
4195out:
4196 return ret;
4197}
4198
8b2cf73c 4199static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4200 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4201 struct desc_struct *nseg_desc)
4202{
4203 struct tss_segment_32 tss_segment_32;
4204 int ret = 0;
4205
34198bf8
MT		 4206 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4207 sizeof tss_segment_32))
37817f29
IE		 4208 goto out;
4209
4210 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4211
34198bf8
MT		 4212 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4213 sizeof tss_segment_32))
4214 goto out;
4215
4216 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4217 &tss_segment_32, sizeof tss_segment_32))
37817f29 4218 goto out;
34198bf8 4219
b237ac37
GN		 4220 if (old_tss_sel != 0xffff) {
4221 tss_segment_32.prev_task_link = old_tss_sel;
4222
4223 if (kvm_write_guest(vcpu->kvm,
4224 get_tss_base_addr(vcpu, nseg_desc),
4225 &tss_segment_32.prev_task_link,
4226 sizeof tss_segment_32.prev_task_link))
4227 goto out;
4228 }
4229
37817f29
IE		 4230 if (load_state_from_tss32(vcpu, &tss_segment_32))
4231 goto out;
4232
4233 ret = 1;
4234out:
4235 return ret;
4236}
4237
4238int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4239{
4240 struct kvm_segment tr_seg;
4241 struct desc_struct cseg_desc;
4242 struct desc_struct nseg_desc;
4243 int ret = 0;
34198bf8
MT		 4244 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4245 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4246
34198bf8 4247 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4248
34198bf8
MT		 4249 /* FIXME: Handle errors. Failure to read either TSS or their
4250 * descriptors should generate a pagefault.
4251 */
37817f29
IE		 4252 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4253 goto out;
4254
34198bf8 4255 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4256 goto out;
4257
37817f29
IE		 4258 if (reason != TASK_SWITCH_IRET) {
4259 int cpl;
4260
4261 cpl = kvm_x86_ops->get_cpl(vcpu);
4262 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4263 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4264 return 1;
4265 }
4266 }
4267
4268 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
4269 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4270 return 1;
4271 }
4272
4273 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4274 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4275 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4276 }
4277
4278 if (reason == TASK_SWITCH_IRET) {
4279 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4280 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4281 }
4282
64a7ec06
GN		 4283 /* set back link to prev task only if NT bit is set in eflags
4284 note that old_tss_sel is not used afetr this point */
4285 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4286 old_tss_sel = 0xffff;
37817f29 4287
b237ac37
GN		 4288 /* set back link to prev task only if NT bit is set in eflags
4289 note that old_tss_sel is not used afetr this point */
4290 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4291 old_tss_sel = 0xffff;
4292
37817f29 4293 if (nseg_desc.type & 8)
b237ac37
GN		 4294 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4295 old_tss_base, &nseg_desc);
37817f29 4296 else
b237ac37
GN		 4297 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4298 old_tss_base, &nseg_desc);
37817f29
IE		 4299
4300 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4301 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4302 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4303 }
4304
4305 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4306 nseg_desc.type |= (1 << 1);
37817f29
IE		 4307 save_guest_segment_descriptor(vcpu, tss_selector,
4308 &nseg_desc);
4309 }
4310
4311 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4312 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4313 tr_seg.type = 11;
3e6e0aab 4314 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4315out:
37817f29
IE		 4316 return ret;
4317}
4318EXPORT_SYMBOL_GPL(kvm_task_switch);
4319
b6c7a5dc
HB		 4320int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4321 struct kvm_sregs *sregs)
4322{
4323 int mmu_reset_needed = 0;
923c61bb 4324 int pending_vec, max_bits;
b6c7a5dc
HB		 4325 struct descriptor_table dt;
4326
4327 vcpu_load(vcpu);
4328
4329 dt.limit = sregs->idt.limit;
4330 dt.base = sregs->idt.base;
4331 kvm_x86_ops->set_idt(vcpu, &dt);
4332 dt.limit = sregs->gdt.limit;
4333 dt.base = sregs->gdt.base;
4334 kvm_x86_ops->set_gdt(vcpu, &dt);
4335
ad312c7c
ZX		 4336 vcpu->arch.cr2 = sregs->cr2;
4337 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4338 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4339
2d3ad1f4 4340 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4341
ad312c7c 4342 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4343 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4344 kvm_set_apic_base(vcpu, sregs->apic_base);
4345
4346 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4347
ad312c7c 4348 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4349 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4350 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4351
ad312c7c 4352 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4353 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4354 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4355 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4356
4357 if (mmu_reset_needed)
4358 kvm_mmu_reset_context(vcpu);
4359
923c61bb
GN		 4360 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4361 pending_vec = find_first_bit(
4362 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4363 if (pending_vec < max_bits) {
66fd3f7f 4364 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4365 pr_debug("Set back pending irq %d\n", pending_vec);
4366 if (irqchip_in_kernel(vcpu->kvm))
4367 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4368 }
4369
3e6e0aab
GT		 4370 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4371 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4372 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4373 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4374 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4375 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4376
3e6e0aab
GT		 4377 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4378 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4379
9c3e4aab 4380 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4381 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4382 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4383 !(vcpu->arch.cr0 & X86_CR0_PE))
4384 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4385
b6c7a5dc
HB		 4386 vcpu_put(vcpu);
4387
4388 return 0;
4389}
4390
d0bfb940
JK		 4391int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4392 struct kvm_guest_debug *dbg)
b6c7a5dc 4393{
ae675ef0 4394 int i, r;
b6c7a5dc
HB		 4395
4396 vcpu_load(vcpu);
4397
ae675ef0
JK		 4398 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4399 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4400 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4401 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4402 vcpu->arch.switch_db_regs =
4403 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4404 } else {
4405 for (i = 0; i < KVM_NR_DB_REGS; i++)
4406 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4407 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4408 }
4409
b6c7a5dc
HB		 4410 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4411
d0bfb940
JK		 4412 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4413 kvm_queue_exception(vcpu, DB_VECTOR);
4414 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4415 kvm_queue_exception(vcpu, BP_VECTOR);
4416
b6c7a5dc
HB		 4417 vcpu_put(vcpu);
4418
4419 return r;
4420}
4421
d0752060
HB		 4422/*
4423 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4424 * we have asm/x86/processor.h
4425 */
4426struct fxsave {
4427 u16 cwd;
4428 u16 swd;
4429 u16 twd;
4430 u16 fop;
4431 u64 rip;
4432 u64 rdp;
4433 u32 mxcsr;
4434 u32 mxcsr_mask;
4435 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4436#ifdef CONFIG_X86_64
4437 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4438#else
4439 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4440#endif
4441};
4442
8b006791
ZX		 4443/*
4444 * Translate a guest virtual address to a guest physical address.
4445 */
4446int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4447 struct kvm_translation *tr)
4448{
4449 unsigned long vaddr = tr->linear_address;
4450 gpa_t gpa;
4451
4452 vcpu_load(vcpu);
72dc67a6 4453 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4454 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4455 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4456 tr->physical_address = gpa;
4457 tr->valid = gpa != UNMAPPED_GVA;
4458 tr->writeable = 1;
4459 tr->usermode = 0;
8b006791
ZX		 4460 vcpu_put(vcpu);
4461
4462 return 0;
4463}
4464
d0752060
HB		 4465int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4466{
ad312c7c 4467 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4468
4469 vcpu_load(vcpu);
4470
4471 memcpy(fpu->fpr, fxsave->st_space, 128);
4472 fpu->fcw = fxsave->cwd;
4473 fpu->fsw = fxsave->swd;
4474 fpu->ftwx = fxsave->twd;
4475 fpu->last_opcode = fxsave->fop;
4476 fpu->last_ip = fxsave->rip;
4477 fpu->last_dp = fxsave->rdp;
4478 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4479
4480 vcpu_put(vcpu);
4481
4482 return 0;
4483}
4484
4485int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4486{
ad312c7c 4487 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4488
4489 vcpu_load(vcpu);
4490
4491 memcpy(fxsave->st_space, fpu->fpr, 128);
4492 fxsave->cwd = fpu->fcw;
4493 fxsave->swd = fpu->fsw;
4494 fxsave->twd = fpu->ftwx;
4495 fxsave->fop = fpu->last_opcode;
4496 fxsave->rip = fpu->last_ip;
4497 fxsave->rdp = fpu->last_dp;
4498 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4499
4500 vcpu_put(vcpu);
4501
4502 return 0;
4503}
4504
4505void fx_init(struct kvm_vcpu *vcpu)
4506{
4507 unsigned after_mxcsr_mask;
4508
bc1a34f1
AA		 4509 /*
4510 * Touch the fpu the first time in non atomic context as if
4511 * this is the first fpu instruction the exception handler
4512 * will fire before the instruction returns and it'll have to
4513 * allocate ram with GFP_KERNEL.
4514 */
4515 if (!used_math())
d6e88aec 4516 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4517
d0752060
HB		 4518 /* Initialize guest FPU by resetting ours and saving into guest's */
4519 preempt_disable();
d6e88aec
AK		 4520 kvm_fx_save(&vcpu->arch.host_fx_image);
4521 kvm_fx_finit();
4522 kvm_fx_save(&vcpu->arch.guest_fx_image);
4523 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4524 preempt_enable();
4525
ad312c7c 4526 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4527 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4528 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4529 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4530 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4531}
4532EXPORT_SYMBOL_GPL(fx_init);
4533
4534void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4535{
4536 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4537 return;
4538
4539 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4540 kvm_fx_save(&vcpu->arch.host_fx_image);
4541 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4542}
4543EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4544
4545void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4546{
4547 if (!vcpu->guest_fpu_loaded)
4548 return;
4549
4550 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4551 kvm_fx_save(&vcpu->arch.guest_fx_image);
4552 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4553 ++vcpu->stat.fpu_reload;
d0752060
HB		 4554}
4555EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4556
4557void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4558{
7f1ea208
JR		 4559 if (vcpu->arch.time_page) {
4560 kvm_release_page_dirty(vcpu->arch.time_page);
4561 vcpu->arch.time_page = NULL;
4562 }
4563
e9b11c17
ZX		 4564 kvm_x86_ops->vcpu_free(vcpu);
4565}
4566
4567struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4568 unsigned int id)
4569{
26e5215f
AK		 4570 return kvm_x86_ops->vcpu_create(kvm, id);
4571}
e9b11c17 4572
26e5215f
AK		 4573int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4574{
4575 int r;
e9b11c17
ZX		 4576
4577 /* We do fxsave: this must be aligned. */
ad312c7c 4578 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4579
0bed3b56 4580 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4581 vcpu_load(vcpu);
4582 r = kvm_arch_vcpu_reset(vcpu);
4583 if (r == 0)
4584 r = kvm_mmu_setup(vcpu);
4585 vcpu_put(vcpu);
4586 if (r < 0)
4587 goto free_vcpu;
4588
26e5215f 4589 return 0;
e9b11c17
ZX		 4590free_vcpu:
4591 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4592 return r;
e9b11c17
ZX		 4593}
4594
d40ccc62 4595void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4596{
4597 vcpu_load(vcpu);
4598 kvm_mmu_unload(vcpu);
4599 vcpu_put(vcpu);
4600
4601 kvm_x86_ops->vcpu_free(vcpu);
4602}
4603
4604int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4605{
448fa4a9
JK		 4606 vcpu->arch.nmi_pending = false;
4607 vcpu->arch.nmi_injected = false;
4608
42dbaa5a
JK		 4609 vcpu->arch.switch_db_regs = 0;
4610 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4611 vcpu->arch.dr6 = DR6_FIXED_1;
4612 vcpu->arch.dr7 = DR7_FIXED_1;
4613
e9b11c17
ZX		 4614 return kvm_x86_ops->vcpu_reset(vcpu);
4615}
4616
4617void kvm_arch_hardware_enable(void *garbage)
4618{
4619 kvm_x86_ops->hardware_enable(garbage);
4620}
4621
4622void kvm_arch_hardware_disable(void *garbage)
4623{
4624 kvm_x86_ops->hardware_disable(garbage);
4625}
4626
4627int kvm_arch_hardware_setup(void)
4628{
4629 return kvm_x86_ops->hardware_setup();
4630}
4631
4632void kvm_arch_hardware_unsetup(void)
4633{
4634 kvm_x86_ops->hardware_unsetup();
4635}
4636
4637void kvm_arch_check_processor_compat(void *rtn)
4638{
4639 kvm_x86_ops->check_processor_compatibility(rtn);
4640}
4641
4642int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4643{
4644 struct page *page;
4645 struct kvm *kvm;
4646 int r;
4647
4648 BUG_ON(vcpu->kvm == NULL);
4649 kvm = vcpu->kvm;
4650
ad312c7c 4651 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 4652 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 4653 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4654 else
a4535290 4655 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4656
4657 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4658 if (!page) {
4659 r = -ENOMEM;
4660 goto fail;
4661 }
ad312c7c 4662 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4663
4664 r = kvm_mmu_create(vcpu);
4665 if (r < 0)
4666 goto fail_free_pio_data;
4667
4668 if (irqchip_in_kernel(kvm)) {
4669 r = kvm_create_lapic(vcpu);
4670 if (r < 0)
4671 goto fail_mmu_destroy;
4672 }
4673
890ca9ae
HY		 4674 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4675 GFP_KERNEL);
4676 if (!vcpu->arch.mce_banks) {
4677 r = -ENOMEM;
4678 goto fail_mmu_destroy;
4679 }
4680 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4681
e9b11c17
ZX		 4682 return 0;
4683
4684fail_mmu_destroy:
4685 kvm_mmu_destroy(vcpu);
4686fail_free_pio_data:
ad312c7c 4687 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4688fail:
4689 return r;
4690}
4691
4692void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4693{
4694 kvm_free_lapic(vcpu);
3200f405 4695 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4696 kvm_mmu_destroy(vcpu);
3200f405 4697 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4698 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4699}
d19a9cd2
ZX		 4700
4701struct kvm *kvm_arch_create_vm(void)
4702{
4703 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4704
4705 if (!kvm)
4706 return ERR_PTR(-ENOMEM);
4707
f05e70ac 4708 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4709 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4710
5550af4d
SY		 4711 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4712 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4713
53f658b3
MT		 4714 rdtscll(kvm->arch.vm_init_tsc);
4715
d19a9cd2
ZX		 4716 return kvm;
4717}
4718
4719static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4720{
4721 vcpu_load(vcpu);
4722 kvm_mmu_unload(vcpu);
4723 vcpu_put(vcpu);
4724}
4725
4726static void kvm_free_vcpus(struct kvm *kvm)
4727{
4728 unsigned int i;
988a2cae 4729 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 4730
4731 /*
4732 * Unpin any mmu pages first.
4733 */
988a2cae
GN		 4734 kvm_for_each_vcpu(i, vcpu, kvm)
4735 kvm_unload_vcpu_mmu(vcpu);
4736 kvm_for_each_vcpu(i, vcpu, kvm)
4737 kvm_arch_vcpu_free(vcpu);
4738
4739 mutex_lock(&kvm->lock);
4740 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4741 kvm->vcpus[i] = NULL;
d19a9cd2 4742
988a2cae
GN		 4743 atomic_set(&kvm->online_vcpus, 0);
4744 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 4745}
4746
ad8ba2cd
SY		 4747void kvm_arch_sync_events(struct kvm *kvm)
4748{
ba4cef31 4749 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4750}
4751
d19a9cd2
ZX		 4752void kvm_arch_destroy_vm(struct kvm *kvm)
4753{
6eb55818 4754 kvm_iommu_unmap_guest(kvm);
7837699f 4755 kvm_free_pit(kvm);
d7deeeb0
ZX		 4756 kfree(kvm->arch.vpic);
4757 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4758 kvm_free_vcpus(kvm);
4759 kvm_free_physmem(kvm);
3d45830c
AK		 4760 if (kvm->arch.apic_access_page)
4761 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4762 if (kvm->arch.ept_identity_pagetable)
4763 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4764 kfree(kvm);
4765}
0de10343
ZX		 4766
4767int kvm_arch_set_memory_region(struct kvm *kvm,
4768 struct kvm_userspace_memory_region *mem,
4769 struct kvm_memory_slot old,
4770 int user_alloc)
4771{
4772 int npages = mem->memory_size >> PAGE_SHIFT;
4773 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4774
4775 /*To keep backward compatibility with older userspace,
4776 *x86 needs to hanlde !user_alloc case.
4777 */
4778 if (!user_alloc) {
4779 if (npages && !old.rmap) {
604b38ac
AA		 4780 unsigned long userspace_addr;
4781
72dc67a6 4782 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4783 userspace_addr = do_mmap(NULL, 0,
4784 npages * PAGE_SIZE,
4785 PROT_READ | PROT_WRITE,
acee3c04 4786 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4787 0);
72dc67a6 4788 up_write(&current->mm->mmap_sem);
0de10343 4789
604b38ac
AA		 4790 if (IS_ERR((void *)userspace_addr))
4791 return PTR_ERR((void *)userspace_addr);
4792
4793 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4794 spin_lock(&kvm->mmu_lock);
4795 memslot->userspace_addr = userspace_addr;
4796 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4797 } else {
4798 if (!old.user_alloc && old.rmap) {
4799 int ret;
4800
72dc67a6 4801 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4802 ret = do_munmap(current->mm, old.userspace_addr,
4803 old.npages * PAGE_SIZE);
72dc67a6 4804 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4805 if (ret < 0)
4806 printk(KERN_WARNING
4807 "kvm_vm_ioctl_set_memory_region: "
4808 "failed to munmap memory\n");
4809 }
4810 }
4811 }
4812
7c8a83b7 4813 spin_lock(&kvm->mmu_lock);
f05e70ac 4814 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4815 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4816 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4817 }
4818
4819 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4820 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4821 kvm_flush_remote_tlbs(kvm);
4822
4823 return 0;
4824}
1d737c8a 4825
34d4cb8f
MT		 4826void kvm_arch_flush_shadow(struct kvm *kvm)
4827{
4828 kvm_mmu_zap_all(kvm);
8986ecc0 4829 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4830}
4831
1d737c8a
ZX		 4832int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4833{
a4535290 4834 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4835 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4836 || vcpu->arch.nmi_pending;
1d737c8a 4837}
5736199a 4838
5736199a
ZX		 4839void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4840{
32f88400
MT		 4841 int me;
4842 int cpu = vcpu->cpu;
5736199a
ZX		 4843
4844 if (waitqueue_active(&vcpu->wq)) {
4845 wake_up_interruptible(&vcpu->wq);
4846 ++vcpu->stat.halt_wakeup;
4847 }
32f88400
MT		 4848
4849 me = get_cpu();
4850 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4851 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4852 smp_send_reschedule(cpu);
e9571ed5 4853 put_cpu();
5736199a 4854}
78646121
GN		 4855
4856int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4857{
4858 return kvm_x86_ops->interrupt_allowed(vcpu);
4859}
229456fc
MT		 4860
4861EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4862EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4863EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4864EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4865EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
Linux 6.x block layer and io_uring tree(s)