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KVM: VMX: enable guest access to LMCE related MSRs
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 73u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
74EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 75
0f65dd70
AK		 76#define emul_to_vcpu(ctxt) \
77 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
78
50a37eb4
JR		 79/* EFER defaults:
80 * - enable syscall per default because its emulated by KVM
81 * - enable LME and LMA per default on 64 bit KVM
82 */
83#ifdef CONFIG_X86_64
1260edbe
LJ		 84static
85u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 86#else
1260edbe 87static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 88#endif
313a3dc7 89
ba1389b7
AK		 90#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
91#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 92
cb142eb7 93static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 94static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 95static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 96static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 97
893590c7 98struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 99EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 100
893590c7 101static bool __read_mostly ignore_msrs = 0;
476bc001 102module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 103
9ed96e87
MT		 104unsigned int min_timer_period_us = 500;
105module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
106
630994b3
MT		 107static bool __read_mostly kvmclock_periodic_sync = true;
108module_param(kvmclock_periodic_sync, bool, S_IRUGO);
109
893590c7 110bool __read_mostly kvm_has_tsc_control;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 112u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 113EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 114u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
115EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
116u64 __read_mostly kvm_max_tsc_scaling_ratio;
117EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 118u64 __read_mostly kvm_default_tsc_scaling_ratio;
119EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 120
cc578287 121/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 122static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 123module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
124
d0659d94 125/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 126unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 127module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
128
52004014
FW		 129static bool __read_mostly vector_hashing = true;
130module_param(vector_hashing, bool, S_IRUGO);
131
893590c7 132static bool __read_mostly backwards_tsc_observed = false;
16a96021 133
18863bdd
AK		 134#define KVM_NR_SHARED_MSRS 16
135
136struct kvm_shared_msrs_global {
137 int nr;
2bf78fa7 138 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 139};
140
141struct kvm_shared_msrs {
142 struct user_return_notifier urn;
143 bool registered;
2bf78fa7
SY		 144 struct kvm_shared_msr_values {
145 u64 host;
146 u64 curr;
147 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 148};
149
150static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 151static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 152
417bc304 153struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 154 { "pf_fixed", VCPU_STAT(pf_fixed) },
155 { "pf_guest", VCPU_STAT(pf_guest) },
156 { "tlb_flush", VCPU_STAT(tlb_flush) },
157 { "invlpg", VCPU_STAT(invlpg) },
158 { "exits", VCPU_STAT(exits) },
159 { "io_exits", VCPU_STAT(io_exits) },
160 { "mmio_exits", VCPU_STAT(mmio_exits) },
161 { "signal_exits", VCPU_STAT(signal_exits) },
162 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 163 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 164 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 165 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 166 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 167 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 168 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 169 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 170 { "request_irq", VCPU_STAT(request_irq_exits) },
171 { "irq_exits", VCPU_STAT(irq_exits) },
172 { "host_state_reload", VCPU_STAT(host_state_reload) },
173 { "efer_reload", VCPU_STAT(efer_reload) },
174 { "fpu_reload", VCPU_STAT(fpu_reload) },
175 { "insn_emulation", VCPU_STAT(insn_emulation) },
176 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 177 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 178 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 179 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
180 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
181 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
182 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
183 { "mmu_flooded", VM_STAT(mmu_flooded) },
184 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 185 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 186 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 187 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 188 { "largepages", VM_STAT(lpages) },
417bc304
HB		 189 { NULL }
190};
191
2acf923e
DC		 192u64 __read_mostly host_xcr0;
193
b6785def 194static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 195
af585b92
GN		 196static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
197{
198 int i;
199 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
200 vcpu->arch.apf.gfns[i] = ~0;
201}
202
18863bdd
AK		 203static void kvm_on_user_return(struct user_return_notifier *urn)
204{
205 unsigned slot;
18863bdd
AK		 206 struct kvm_shared_msrs *locals
207 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 208 struct kvm_shared_msr_values *values;
18863bdd
AK		 209
210 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 211 values = &locals->values[slot];
212 if (values->host != values->curr) {
213 wrmsrl(shared_msrs_global.msrs[slot], values->host);
214 values->curr = values->host;
18863bdd
AK		 215 }
216 }
217 locals->registered = false;
218 user_return_notifier_unregister(urn);
219}
220
2bf78fa7 221static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 222{
18863bdd 223 u64 value;
013f6a5d
MT		 224 unsigned int cpu = smp_processor_id();
225 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 226
2bf78fa7
SY		 227 /* only read, and nobody should modify it at this time,
228 * so don't need lock */
229 if (slot >= shared_msrs_global.nr) {
230 printk(KERN_ERR "kvm: invalid MSR slot!");
231 return;
232 }
233 rdmsrl_safe(msr, &value);
234 smsr->values[slot].host = value;
235 smsr->values[slot].curr = value;
236}
237
238void kvm_define_shared_msr(unsigned slot, u32 msr)
239{
0123be42 240 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 241 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 242 if (slot >= shared_msrs_global.nr)
243 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 244}
245EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
246
247static void kvm_shared_msr_cpu_online(void)
248{
249 unsigned i;
18863bdd
AK		 250
251 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 252 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 253}
254
8b3c3104 255int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 256{
013f6a5d
MT		 257 unsigned int cpu = smp_processor_id();
258 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 259 int err;
18863bdd 260
2bf78fa7 261 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 262 return 0;
2bf78fa7 263 smsr->values[slot].curr = value;
8b3c3104
AH		 264 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
265 if (err)
266 return 1;
267
18863bdd
AK		 268 if (!smsr->registered) {
269 smsr->urn.on_user_return = kvm_on_user_return;
270 user_return_notifier_register(&smsr->urn);
271 smsr->registered = true;
272 }
8b3c3104 273 return 0;
18863bdd
AK		 274}
275EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
276
13a34e06 277static void drop_user_return_notifiers(void)
3548bab5 278{
013f6a5d
MT		 279 unsigned int cpu = smp_processor_id();
280 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 281
282 if (smsr->registered)
283 kvm_on_user_return(&smsr->urn);
284}
285
6866b83e
CO		 286u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
287{
8a5a87d9 288 return vcpu->arch.apic_base;
6866b83e
CO		 289}
290EXPORT_SYMBOL_GPL(kvm_get_apic_base);
291
58cb628d
JK		 292int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
293{
294 u64 old_state = vcpu->arch.apic_base &
295 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
296 u64 new_state = msr_info->data &
297 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
298 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
299 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
300
301 if (!msr_info->host_initiated &&
302 ((msr_info->data & reserved_bits) != 0 ||
303 new_state == X2APIC_ENABLE ||
304 (new_state == MSR_IA32_APICBASE_ENABLE &&
305 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
306 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
307 old_state == 0)))
308 return 1;
309
310 kvm_lapic_set_base(vcpu, msr_info->data);
311 return 0;
6866b83e
CO		 312}
313EXPORT_SYMBOL_GPL(kvm_set_apic_base);
314
2605fc21 315asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 316{
317 /* Fault while not rebooting. We want the trace. */
318 BUG();
319}
320EXPORT_SYMBOL_GPL(kvm_spurious_fault);
321
3fd28fce
ED		 322#define EXCPT_BENIGN 0
323#define EXCPT_CONTRIBUTORY 1
324#define EXCPT_PF 2
325
326static int exception_class(int vector)
327{
328 switch (vector) {
329 case PF_VECTOR:
330 return EXCPT_PF;
331 case DE_VECTOR:
332 case TS_VECTOR:
333 case NP_VECTOR:
334 case SS_VECTOR:
335 case GP_VECTOR:
336 return EXCPT_CONTRIBUTORY;
337 default:
338 break;
339 }
340 return EXCPT_BENIGN;
341}
342
d6e8c854
NA		 343#define EXCPT_FAULT 0
344#define EXCPT_TRAP 1
345#define EXCPT_ABORT 2
346#define EXCPT_INTERRUPT 3
347
348static int exception_type(int vector)
349{
350 unsigned int mask;
351
352 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
353 return EXCPT_INTERRUPT;
354
355 mask = 1 << vector;
356
357 /* #DB is trap, as instruction watchpoints are handled elsewhere */
358 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
359 return EXCPT_TRAP;
360
361 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
362 return EXCPT_ABORT;
363
364 /* Reserved exceptions will result in fault */
365 return EXCPT_FAULT;
366}
367
3fd28fce 368static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 369 unsigned nr, bool has_error, u32 error_code,
370 bool reinject)
3fd28fce
ED		 371{
372 u32 prev_nr;
373 int class1, class2;
374
3842d135
AK		 375 kvm_make_request(KVM_REQ_EVENT, vcpu);
376
3fd28fce
ED		 377 if (!vcpu->arch.exception.pending) {
378 queue:
3ffb2468
NA		 379 if (has_error && !is_protmode(vcpu))
380 has_error = false;
3fd28fce
ED		 381 vcpu->arch.exception.pending = true;
382 vcpu->arch.exception.has_error_code = has_error;
383 vcpu->arch.exception.nr = nr;
384 vcpu->arch.exception.error_code = error_code;
3f0fd292 385 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 386 return;
387 }
388
389 /* to check exception */
390 prev_nr = vcpu->arch.exception.nr;
391 if (prev_nr == DF_VECTOR) {
392 /* triple fault -> shutdown */
a8eeb04a 393 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 394 return;
395 }
396 class1 = exception_class(prev_nr);
397 class2 = exception_class(nr);
398 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
399 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
400 /* generate double fault per SDM Table 5-5 */
401 vcpu->arch.exception.pending = true;
402 vcpu->arch.exception.has_error_code = true;
403 vcpu->arch.exception.nr = DF_VECTOR;
404 vcpu->arch.exception.error_code = 0;
405 } else
406 /* replace previous exception with a new one in a hope
407 that instruction re-execution will regenerate lost
408 exception */
409 goto queue;
410}
411
298101da
AK		 412void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
413{
ce7ddec4 414 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 415}
416EXPORT_SYMBOL_GPL(kvm_queue_exception);
417
ce7ddec4
JR		 418void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
419{
420 kvm_multiple_exception(vcpu, nr, false, 0, true);
421}
422EXPORT_SYMBOL_GPL(kvm_requeue_exception);
423
db8fcefa 424void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 425{
db8fcefa
AP		 426 if (err)
427 kvm_inject_gp(vcpu, 0);
428 else
429 kvm_x86_ops->skip_emulated_instruction(vcpu);
430}
431EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 432
6389ee94 433void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 434{
435 ++vcpu->stat.pf_guest;
6389ee94
AK		 436 vcpu->arch.cr2 = fault->address;
437 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 438}
27d6c865 439EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 440
ef54bcfe 441static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 442{
6389ee94
AK		 443 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
444 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 445 else
6389ee94 446 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 447
448 return fault->nested_page_fault;
d4f8cf66
JR		 449}
450
3419ffc8
SY		 451void kvm_inject_nmi(struct kvm_vcpu *vcpu)
452{
7460fb4a
AK		 453 atomic_inc(&vcpu->arch.nmi_queued);
454 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 455}
456EXPORT_SYMBOL_GPL(kvm_inject_nmi);
457
298101da
AK		 458void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
459{
ce7ddec4 460 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 461}
462EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
463
ce7ddec4
JR		 464void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
465{
466 kvm_multiple_exception(vcpu, nr, true, error_code, true);
467}
468EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
469
0a79b009
AK		 470/*
471 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
472 * a #GP and return false.
473 */
474bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 475{
0a79b009
AK		 476 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
477 return true;
478 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
479 return false;
298101da 480}
0a79b009 481EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 482
16f8a6f9
NA		 483bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
484{
485 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
486 return true;
487
488 kvm_queue_exception(vcpu, UD_VECTOR);
489 return false;
490}
491EXPORT_SYMBOL_GPL(kvm_require_dr);
492
ec92fe44
JR		 493/*
494 * This function will be used to read from the physical memory of the currently
54bf36aa 495 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 496 * can read from guest physical or from the guest's guest physical memory.
497 */
498int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
499 gfn_t ngfn, void *data, int offset, int len,
500 u32 access)
501{
54987b7a 502 struct x86_exception exception;
ec92fe44
JR		 503 gfn_t real_gfn;
504 gpa_t ngpa;
505
506 ngpa = gfn_to_gpa(ngfn);
54987b7a 507 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 508 if (real_gfn == UNMAPPED_GVA)
509 return -EFAULT;
510
511 real_gfn = gpa_to_gfn(real_gfn);
512
54bf36aa 513 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 514}
515EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
516
69b0049a 517static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 518 void *data, int offset, int len, u32 access)
519{
520 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
521 data, offset, len, access);
522}
523
a03490ed
CO		 524/*
525 * Load the pae pdptrs. Return true is they are all valid.
526 */
ff03a073 527int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 528{
529 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
530 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
531 int i;
532 int ret;
ff03a073 533 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 534
ff03a073
JR		 535 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
536 offset * sizeof(u64), sizeof(pdpte),
537 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 538 if (ret < 0) {
539 ret = 0;
540 goto out;
541 }
542 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 543 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 544 (pdpte[i] &
545 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 546 ret = 0;
547 goto out;
548 }
549 }
550 ret = 1;
551
ff03a073 552 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 553 __set_bit(VCPU_EXREG_PDPTR,
554 (unsigned long *)&vcpu->arch.regs_avail);
555 __set_bit(VCPU_EXREG_PDPTR,
556 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 557out:
a03490ed
CO		 558
559 return ret;
560}
cc4b6871 561EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 562
d835dfec
AK		 563static bool pdptrs_changed(struct kvm_vcpu *vcpu)
564{
ff03a073 565 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 566 bool changed = true;
3d06b8bf
JR		 567 int offset;
568 gfn_t gfn;
d835dfec
AK		 569 int r;
570
571 if (is_long_mode(vcpu) || !is_pae(vcpu))
572 return false;
573
6de4f3ad
AK		 574 if (!test_bit(VCPU_EXREG_PDPTR,
575 (unsigned long *)&vcpu->arch.regs_avail))
576 return true;
577
9f8fe504
AK		 578 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
579 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 580 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
581 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 582 if (r < 0)
583 goto out;
ff03a073 584 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 585out:
d835dfec
AK		 586
587 return changed;
588}
589
49a9b07e 590int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 591{
aad82703 592 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 593 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 594
f9a48e6a
AK		 595 cr0 |= X86_CR0_ET;
596
ab344828 597#ifdef CONFIG_X86_64
0f12244f
GN		 598 if (cr0 & 0xffffffff00000000UL)
599 return 1;
ab344828
GN		 600#endif
601
602 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 603
0f12244f
GN		 604 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
605 return 1;
a03490ed 606
0f12244f
GN		 607 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
608 return 1;
a03490ed
CO		 609
610 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
611#ifdef CONFIG_X86_64
f6801dff 612 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 613 int cs_db, cs_l;
614
0f12244f
GN		 615 if (!is_pae(vcpu))
616 return 1;
a03490ed 617 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 618 if (cs_l)
619 return 1;
a03490ed
CO		 620 } else
621#endif
ff03a073 622 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 623 kvm_read_cr3(vcpu)))
0f12244f 624 return 1;
a03490ed
CO		 625 }
626
ad756a16
MJ		 627 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
628 return 1;
629
a03490ed 630 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 631
d170c419 632 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 633 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 634 kvm_async_pf_hash_reset(vcpu);
635 }
e5f3f027 636
aad82703
SY		 637 if ((cr0 ^ old_cr0) & update_bits)
638 kvm_mmu_reset_context(vcpu);
b18d5431 639
879ae188
LE		 640 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
641 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
642 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 643 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
644
0f12244f
GN		 645 return 0;
646}
2d3ad1f4 647EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 648
2d3ad1f4 649void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 650{
49a9b07e 651 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 652}
2d3ad1f4 653EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 654
42bdf991
MT		 655static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
656{
657 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
658 !vcpu->guest_xcr0_loaded) {
659 /* kvm_set_xcr() also depends on this */
660 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
661 vcpu->guest_xcr0_loaded = 1;
662 }
663}
664
665static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
666{
667 if (vcpu->guest_xcr0_loaded) {
668 if (vcpu->arch.xcr0 != host_xcr0)
669 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
670 vcpu->guest_xcr0_loaded = 0;
671 }
672}
673
69b0049a 674static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 675{
56c103ec
LJ		 676 u64 xcr0 = xcr;
677 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 678 u64 valid_bits;
2acf923e
DC		 679
680 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
681 if (index != XCR_XFEATURE_ENABLED_MASK)
682 return 1;
d91cab78 683 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 684 return 1;
d91cab78 685 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 686 return 1;
46c34cb0
PB		 687
688 /*
689 * Do not allow the guest to set bits that we do not support
690 * saving. However, xcr0 bit 0 is always set, even if the
691 * emulated CPU does not support XSAVE (see fx_init).
692 */
d91cab78 693 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 694 if (xcr0 & ~valid_bits)
2acf923e 695 return 1;
46c34cb0 696
d91cab78
DH		 697 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
698 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 699 return 1;
700
d91cab78
DH		 701 if (xcr0 & XFEATURE_MASK_AVX512) {
702 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 703 return 1;
d91cab78 704 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 705 return 1;
706 }
2acf923e 707 vcpu->arch.xcr0 = xcr0;
56c103ec 708
d91cab78 709 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 710 kvm_update_cpuid(vcpu);
2acf923e
DC		 711 return 0;
712}
713
714int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
715{
764bcbc5
Z		 716 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
717 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 718 kvm_inject_gp(vcpu, 0);
719 return 1;
720 }
721 return 0;
722}
723EXPORT_SYMBOL_GPL(kvm_set_xcr);
724
a83b29c6 725int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 726{
fc78f519 727 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 728 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 729 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 730
0f12244f
GN		 731 if (cr4 & CR4_RESERVED_BITS)
732 return 1;
a03490ed 733
2acf923e
DC		 734 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
735 return 1;
736
c68b734f
YW		 737 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
738 return 1;
739
97ec8c06
FW		 740 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
741 return 1;
742
afcbf13f 743 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 744 return 1;
745
b9baba86
HH		 746 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
747 return 1;
748
a03490ed 749 if (is_long_mode(vcpu)) {
0f12244f
GN		 750 if (!(cr4 & X86_CR4_PAE))
751 return 1;
a2edf57f
AK		 752 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
753 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 754 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
755 kvm_read_cr3(vcpu)))
0f12244f
GN		 756 return 1;
757
ad756a16
MJ		 758 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
759 if (!guest_cpuid_has_pcid(vcpu))
760 return 1;
761
762 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
763 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
764 return 1;
765 }
766
5e1746d6 767 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 768 return 1;
a03490ed 769
ad756a16
MJ		 770 if (((cr4 ^ old_cr4) & pdptr_bits) ||
771 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 772 kvm_mmu_reset_context(vcpu);
0f12244f 773
b9baba86 774 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 775 kvm_update_cpuid(vcpu);
2acf923e 776
0f12244f
GN		 777 return 0;
778}
2d3ad1f4 779EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 780
2390218b 781int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 782{
ac146235 783#ifdef CONFIG_X86_64
9d88fca7 784 cr3 &= ~CR3_PCID_INVD;
ac146235 785#endif
9d88fca7 786
9f8fe504 787 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 788 kvm_mmu_sync_roots(vcpu);
77c3913b 789 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 790 return 0;
d835dfec
AK		 791 }
792
a03490ed 793 if (is_long_mode(vcpu)) {
d9f89b88
JK		 794 if (cr3 & CR3_L_MODE_RESERVED_BITS)
795 return 1;
796 } else if (is_pae(vcpu) && is_paging(vcpu) &&
797 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 798 return 1;
a03490ed 799
0f12244f 800 vcpu->arch.cr3 = cr3;
aff48baa 801 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 802 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 803 return 0;
804}
2d3ad1f4 805EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 806
eea1cff9 807int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 808{
0f12244f
GN		 809 if (cr8 & CR8_RESERVED_BITS)
810 return 1;
35754c98 811 if (lapic_in_kernel(vcpu))
a03490ed
CO		 812 kvm_lapic_set_tpr(vcpu, cr8);
813 else
ad312c7c 814 vcpu->arch.cr8 = cr8;
0f12244f
GN		 815 return 0;
816}
2d3ad1f4 817EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 818
2d3ad1f4 819unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 820{
35754c98 821 if (lapic_in_kernel(vcpu))
a03490ed
CO		 822 return kvm_lapic_get_cr8(vcpu);
823 else
ad312c7c 824 return vcpu->arch.cr8;
a03490ed 825}
2d3ad1f4 826EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 827
ae561ede
NA		 828static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
829{
830 int i;
831
832 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
833 for (i = 0; i < KVM_NR_DB_REGS; i++)
834 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
835 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
836 }
837}
838
73aaf249
JK		 839static void kvm_update_dr6(struct kvm_vcpu *vcpu)
840{
841 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
842 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
843}
844
c8639010
JK		 845static void kvm_update_dr7(struct kvm_vcpu *vcpu)
846{
847 unsigned long dr7;
848
849 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
850 dr7 = vcpu->arch.guest_debug_dr7;
851 else
852 dr7 = vcpu->arch.dr7;
853 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 854 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
855 if (dr7 & DR7_BP_EN_MASK)
856 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 857}
858
6f43ed01
NA		 859static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
860{
861 u64 fixed = DR6_FIXED_1;
862
863 if (!guest_cpuid_has_rtm(vcpu))
864 fixed |= DR6_RTM;
865 return fixed;
866}
867
338dbc97 868static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 869{
870 switch (dr) {
871 case 0 ... 3:
872 vcpu->arch.db[dr] = val;
873 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
874 vcpu->arch.eff_db[dr] = val;
875 break;
876 case 4:
020df079
GN		 877 /* fall through */
878 case 6:
338dbc97
GN		 879 if (val & 0xffffffff00000000ULL)
880 return -1; /* #GP */
6f43ed01 881 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 882 kvm_update_dr6(vcpu);
020df079
GN		 883 break;
884 case 5:
020df079
GN		 885 /* fall through */
886 default: /* 7 */
338dbc97
GN		 887 if (val & 0xffffffff00000000ULL)
888 return -1; /* #GP */
020df079 889 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 890 kvm_update_dr7(vcpu);
020df079
GN		 891 break;
892 }
893
894 return 0;
895}
338dbc97
GN		 896
897int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
898{
16f8a6f9 899 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 900 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 901 return 1;
902 }
903 return 0;
338dbc97 904}
020df079
GN		 905EXPORT_SYMBOL_GPL(kvm_set_dr);
906
16f8a6f9 907int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 908{
909 switch (dr) {
910 case 0 ... 3:
911 *val = vcpu->arch.db[dr];
912 break;
913 case 4:
020df079
GN		 914 /* fall through */
915 case 6:
73aaf249
JK		 916 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
917 *val = vcpu->arch.dr6;
918 else
919 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 920 break;
921 case 5:
020df079
GN		 922 /* fall through */
923 default: /* 7 */
924 *val = vcpu->arch.dr7;
925 break;
926 }
338dbc97
GN		 927 return 0;
928}
020df079
GN		 929EXPORT_SYMBOL_GPL(kvm_get_dr);
930
022cd0e8
AK		 931bool kvm_rdpmc(struct kvm_vcpu *vcpu)
932{
933 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
934 u64 data;
935 int err;
936
c6702c9d 937 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 938 if (err)
939 return err;
940 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
941 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
942 return err;
943}
944EXPORT_SYMBOL_GPL(kvm_rdpmc);
945
043405e1
CO		 946/*
947 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
948 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
949 *
950 * This list is modified at module load time to reflect the
e3267cbb 951 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 952 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
953 * may depend on host virtualization features rather than host cpu features.
043405e1 954 */
e3267cbb 955
043405e1
CO		 956static u32 msrs_to_save[] = {
957 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 958 MSR_STAR,
043405e1
CO		 959#ifdef CONFIG_X86_64
960 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
961#endif
b3897a49 962 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 963 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 964};
965
966static unsigned num_msrs_to_save;
967
62ef68bb
PB		 968static u32 emulated_msrs[] = {
969 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
970 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
971 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
972 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 973 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
974 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 975 HV_X64_MSR_RESET,
11c4b1ca 976 HV_X64_MSR_VP_INDEX,
9eec50b8 977 HV_X64_MSR_VP_RUNTIME,
5c919412 978 HV_X64_MSR_SCONTROL,
1f4b34f8 979 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 980 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
981 MSR_KVM_PV_EOI_EN,
982
ba904635 983 MSR_IA32_TSC_ADJUST,
a3e06bbe 984 MSR_IA32_TSCDEADLINE,
043405e1 985 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 986 MSR_IA32_MCG_STATUS,
987 MSR_IA32_MCG_CTL,
c45dcc71 988 MSR_IA32_MCG_EXT_CTL,
64d60670 989 MSR_IA32_SMBASE,
043405e1
CO		 990};
991
62ef68bb
PB		 992static unsigned num_emulated_msrs;
993
384bb783 994bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 995{
b69e8cae 996 if (efer & efer_reserved_bits)
384bb783 997 return false;
15c4a640 998
1b2fd70c
AG		 999 if (efer & EFER_FFXSR) {
1000 struct kvm_cpuid_entry2 *feat;
1001
1002 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1003 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1004 return false;
1b2fd70c
AG		 1005 }
1006
d8017474
AG		 1007 if (efer & EFER_SVME) {
1008 struct kvm_cpuid_entry2 *feat;
1009
1010 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1011 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1012 return false;
d8017474
AG		 1013 }
1014
384bb783
JK		 1015 return true;
1016}
1017EXPORT_SYMBOL_GPL(kvm_valid_efer);
1018
1019static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1020{
1021 u64 old_efer = vcpu->arch.efer;
1022
1023 if (!kvm_valid_efer(vcpu, efer))
1024 return 1;
1025
1026 if (is_paging(vcpu)
1027 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1028 return 1;
1029
15c4a640 1030 efer &= ~EFER_LMA;
f6801dff 1031 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1032
a3d204e2
SY		 1033 kvm_x86_ops->set_efer(vcpu, efer);
1034
aad82703
SY		 1035 /* Update reserved bits */
1036 if ((efer ^ old_efer) & EFER_NX)
1037 kvm_mmu_reset_context(vcpu);
1038
b69e8cae 1039 return 0;
15c4a640
CO		 1040}
1041
f2b4b7dd
JR		 1042void kvm_enable_efer_bits(u64 mask)
1043{
1044 efer_reserved_bits &= ~mask;
1045}
1046EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1047
15c4a640
CO		 1048/*
1049 * Writes msr value into into the appropriate "register".
1050 * Returns 0 on success, non-0 otherwise.
1051 * Assumes vcpu_load() was already called.
1052 */
8fe8ab46 1053int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1054{
854e8bb1
NA		 1055 switch (msr->index) {
1056 case MSR_FS_BASE:
1057 case MSR_GS_BASE:
1058 case MSR_KERNEL_GS_BASE:
1059 case MSR_CSTAR:
1060 case MSR_LSTAR:
1061 if (is_noncanonical_address(msr->data))
1062 return 1;
1063 break;
1064 case MSR_IA32_SYSENTER_EIP:
1065 case MSR_IA32_SYSENTER_ESP:
1066 /*
1067 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1068 * non-canonical address is written on Intel but not on
1069 * AMD (which ignores the top 32-bits, because it does
1070 * not implement 64-bit SYSENTER).
1071 *
1072 * 64-bit code should hence be able to write a non-canonical
1073 * value on AMD. Making the address canonical ensures that
1074 * vmentry does not fail on Intel after writing a non-canonical
1075 * value, and that something deterministic happens if the guest
1076 * invokes 64-bit SYSENTER.
1077 */
1078 msr->data = get_canonical(msr->data);
1079 }
8fe8ab46 1080 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1081}
854e8bb1 1082EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1083
313a3dc7
CO		 1084/*
1085 * Adapt set_msr() to msr_io()'s calling convention
1086 */
609e36d3
PB		 1087static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1088{
1089 struct msr_data msr;
1090 int r;
1091
1092 msr.index = index;
1093 msr.host_initiated = true;
1094 r = kvm_get_msr(vcpu, &msr);
1095 if (r)
1096 return r;
1097
1098 *data = msr.data;
1099 return 0;
1100}
1101
313a3dc7
CO		 1102static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1103{
8fe8ab46
WA		 1104 struct msr_data msr;
1105
1106 msr.data = *data;
1107 msr.index = index;
1108 msr.host_initiated = true;
1109 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1110}
1111
16e8d74d
MT		 1112#ifdef CONFIG_X86_64
1113struct pvclock_gtod_data {
1114 seqcount_t seq;
1115
1116 struct { /* extract of a clocksource struct */
1117 int vclock_mode;
1118 cycle_t cycle_last;
1119 cycle_t mask;
1120 u32 mult;
1121 u32 shift;
1122 } clock;
1123
cbcf2dd3
TG		 1124 u64 boot_ns;
1125 u64 nsec_base;
16e8d74d
MT		 1126};
1127
1128static struct pvclock_gtod_data pvclock_gtod_data;
1129
1130static void update_pvclock_gtod(struct timekeeper *tk)
1131{
1132 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1133 u64 boot_ns;
1134
876e7881 1135 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1136
1137 write_seqcount_begin(&vdata->seq);
1138
1139 /* copy pvclock gtod data */
876e7881
PZ		 1140 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1141 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1142 vdata->clock.mask = tk->tkr_mono.mask;
1143 vdata->clock.mult = tk->tkr_mono.mult;
1144 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1145
cbcf2dd3 1146 vdata->boot_ns = boot_ns;
876e7881 1147 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1148
1149 write_seqcount_end(&vdata->seq);
1150}
1151#endif
1152
bab5bb39
NK		 1153void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1154{
1155 /*
1156 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1157 * vcpu_enter_guest. This function is only called from
1158 * the physical CPU that is running vcpu.
1159 */
1160 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1161}
16e8d74d 1162
18068523
GOC		 1163static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1164{
9ed3c444
AK		 1165 int version;
1166 int r;
50d0a0f9 1167 struct pvclock_wall_clock wc;
923de3cf 1168 struct timespec boot;
18068523
GOC		 1169
1170 if (!wall_clock)
1171 return;
1172
9ed3c444
AK		 1173 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1174 if (r)
1175 return;
1176
1177 if (version & 1)
1178 ++version; /* first time write, random junk */
1179
1180 ++version;
18068523 1181
1dab1345
NK		 1182 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1183 return;
18068523 1184
50d0a0f9
GH		 1185 /*
1186 * The guest calculates current wall clock time by adding
34c238a1 1187 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1188 * wall clock specified here. guest system time equals host
1189 * system time for us, thus we must fill in host boot time here.
1190 */
923de3cf 1191 getboottime(&boot);
50d0a0f9 1192
4b648665
BR		 1193 if (kvm->arch.kvmclock_offset) {
1194 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1195 boot = timespec_sub(boot, ts);
1196 }
50d0a0f9
GH		 1197 wc.sec = boot.tv_sec;
1198 wc.nsec = boot.tv_nsec;
1199 wc.version = version;
18068523
GOC		 1200
1201 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1202
1203 version++;
1204 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1205}
1206
50d0a0f9
GH		 1207static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1208{
b51012de
PB		 1209 do_shl32_div32(dividend, divisor);
1210 return dividend;
50d0a0f9
GH		 1211}
1212
3ae13faa 1213static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1214 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1215{
5f4e3f88 1216 uint64_t scaled64;
50d0a0f9
GH		 1217 int32_t shift = 0;
1218 uint64_t tps64;
1219 uint32_t tps32;
1220
3ae13faa
PB		 1221 tps64 = base_hz;
1222 scaled64 = scaled_hz;
50933623 1223 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1224 tps64 >>= 1;
1225 shift--;
1226 }
1227
1228 tps32 = (uint32_t)tps64;
50933623
JK		 1229 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1230 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1231 scaled64 >>= 1;
1232 else
1233 tps32 <<= 1;
50d0a0f9
GH		 1234 shift++;
1235 }
1236
5f4e3f88
ZA		 1237 *pshift = shift;
1238 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1239
3ae13faa
PB		 1240 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1241 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1242}
1243
d828199e 1244#ifdef CONFIG_X86_64
16e8d74d 1245static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1246#endif
16e8d74d 1247
c8076604 1248static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1249static unsigned long max_tsc_khz;
c8076604 1250
cc578287 1251static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1252{
cc578287
ZA		 1253 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1254 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1255}
1256
cc578287 1257static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1258{
cc578287
ZA		 1259 u64 v = (u64)khz * (1000000 + ppm);
1260 do_div(v, 1000000);
1261 return v;
1e993611
JR		 1262}
1263
381d585c
HZ		 1264static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1265{
1266 u64 ratio;
1267
1268 /* Guest TSC same frequency as host TSC? */
1269 if (!scale) {
1270 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1271 return 0;
1272 }
1273
1274 /* TSC scaling supported? */
1275 if (!kvm_has_tsc_control) {
1276 if (user_tsc_khz > tsc_khz) {
1277 vcpu->arch.tsc_catchup = 1;
1278 vcpu->arch.tsc_always_catchup = 1;
1279 return 0;
1280 } else {
1281 WARN(1, "user requested TSC rate below hardware speed\n");
1282 return -1;
1283 }
1284 }
1285
1286 /* TSC scaling required - calculate ratio */
1287 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1288 user_tsc_khz, tsc_khz);
1289
1290 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1291 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1292 user_tsc_khz);
1293 return -1;
1294 }
1295
1296 vcpu->arch.tsc_scaling_ratio = ratio;
1297 return 0;
1298}
1299
4941b8cb 1300static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1301{
cc578287
ZA		 1302 u32 thresh_lo, thresh_hi;
1303 int use_scaling = 0;
217fc9cf 1304
03ba32ca 1305 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1306 if (user_tsc_khz == 0) {
ad721883
HZ		 1307 /* set tsc_scaling_ratio to a safe value */
1308 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1309 return -1;
ad721883 1310 }
03ba32ca 1311
c285545f 1312 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1313 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1314 &vcpu->arch.virtual_tsc_shift,
1315 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1316 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1317
1318 /*
1319 * Compute the variation in TSC rate which is acceptable
1320 * within the range of tolerance and decide if the
1321 * rate being applied is within that bounds of the hardware
1322 * rate. If so, no scaling or compensation need be done.
1323 */
1324 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1325 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1326 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1327 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1328 use_scaling = 1;
1329 }
4941b8cb 1330 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1331}
1332
1333static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1334{
e26101b1 1335 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1336 vcpu->arch.virtual_tsc_mult,
1337 vcpu->arch.virtual_tsc_shift);
e26101b1 1338 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1339 return tsc;
1340}
1341
69b0049a 1342static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1343{
1344#ifdef CONFIG_X86_64
1345 bool vcpus_matched;
b48aa97e
MT		 1346 struct kvm_arch *ka = &vcpu->kvm->arch;
1347 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1348
1349 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1350 atomic_read(&vcpu->kvm->online_vcpus));
1351
7f187922
MT		 1352 /*
1353 * Once the masterclock is enabled, always perform request in
1354 * order to update it.
1355 *
1356 * In order to enable masterclock, the host clocksource must be TSC
1357 * and the vcpus need to have matched TSCs. When that happens,
1358 * perform request to enable masterclock.
1359 */
1360 if (ka->use_master_clock ||
1361 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1362 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1363
1364 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1365 atomic_read(&vcpu->kvm->online_vcpus),
1366 ka->use_master_clock, gtod->clock.vclock_mode);
1367#endif
1368}
1369
ba904635
WA		 1370static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1371{
1372 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1373 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1374}
1375
35181e86
HZ		 1376/*
1377 * Multiply tsc by a fixed point number represented by ratio.
1378 *
1379 * The most significant 64-N bits (mult) of ratio represent the
1380 * integral part of the fixed point number; the remaining N bits
1381 * (frac) represent the fractional part, ie. ratio represents a fixed
1382 * point number (mult + frac * 2^(-N)).
1383 *
1384 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1385 */
1386static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1387{
1388 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1389}
1390
1391u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1392{
1393 u64 _tsc = tsc;
1394 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1395
1396 if (ratio != kvm_default_tsc_scaling_ratio)
1397 _tsc = __scale_tsc(ratio, tsc);
1398
1399 return _tsc;
1400}
1401EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1402
07c1419a
HZ		 1403static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1404{
1405 u64 tsc;
1406
1407 tsc = kvm_scale_tsc(vcpu, rdtsc());
1408
1409 return target_tsc - tsc;
1410}
1411
4ba76538
HZ		 1412u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1413{
1414 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1415}
1416EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1417
8fe8ab46 1418void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1419{
1420 struct kvm *kvm = vcpu->kvm;
f38e098f 1421 u64 offset, ns, elapsed;
99e3e30a 1422 unsigned long flags;
02626b6a 1423 s64 usdiff;
b48aa97e 1424 bool matched;
0d3da0d2 1425 bool already_matched;
8fe8ab46 1426 u64 data = msr->data;
99e3e30a 1427
038f8c11 1428 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1429 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1430 ns = get_kernel_ns();
f38e098f 1431 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1432
03ba32ca 1433 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1434 int faulted = 0;
1435
03ba32ca
MT		 1436 /* n.b - signed multiplication and division required */
1437 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1438#ifdef CONFIG_X86_64
03ba32ca 1439 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1440#else
03ba32ca 1441 /* do_div() only does unsigned */
8915aa27
MT		 1442 asm("1: idivl %[divisor]\n"
1443 "2: xor %%edx, %%edx\n"
1444 " movl $0, %[faulted]\n"
1445 "3:\n"
1446 ".section .fixup,\"ax\"\n"
1447 "4: movl $1, %[faulted]\n"
1448 " jmp 3b\n"
1449 ".previous\n"
1450
1451 _ASM_EXTABLE(1b, 4b)
1452
1453 : "=A"(usdiff), [faulted] "=r" (faulted)
1454 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1455
5d3cb0f6 1456#endif
03ba32ca
MT		 1457 do_div(elapsed, 1000);
1458 usdiff -= elapsed;
1459 if (usdiff < 0)
1460 usdiff = -usdiff;
8915aa27
MT		 1461
1462 /* idivl overflow => difference is larger than USEC_PER_SEC */
1463 if (faulted)
1464 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1465 } else
1466 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1467
1468 /*
5d3cb0f6
ZA		 1469 * Special case: TSC write with a small delta (1 second) of virtual
1470 * cycle time against real time is interpreted as an attempt to
1471 * synchronize the CPU.
1472 *
1473 * For a reliable TSC, we can match TSC offsets, and for an unstable
1474 * TSC, we add elapsed time in this computation. We could let the
1475 * compensation code attempt to catch up if we fall behind, but
1476 * it's better to try to match offsets from the beginning.
1477 */
02626b6a 1478 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1479 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1480 if (!check_tsc_unstable()) {
e26101b1 1481 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1482 pr_debug("kvm: matched tsc offset for %llu\n", data);
1483 } else {
857e4099 1484 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1485 data += delta;
07c1419a 1486 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1487 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1488 }
b48aa97e 1489 matched = true;
0d3da0d2 1490 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1491 } else {
1492 /*
1493 * We split periods of matched TSC writes into generations.
1494 * For each generation, we track the original measured
1495 * nanosecond time, offset, and write, so if TSCs are in
1496 * sync, we can match exact offset, and if not, we can match
4a969980 1497 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1498 *
1499 * These values are tracked in kvm->arch.cur_xxx variables.
1500 */
1501 kvm->arch.cur_tsc_generation++;
1502 kvm->arch.cur_tsc_nsec = ns;
1503 kvm->arch.cur_tsc_write = data;
1504 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1505 matched = false;
0d3da0d2 1506 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1507 kvm->arch.cur_tsc_generation, data);
f38e098f 1508 }
e26101b1
ZA		 1509
1510 /*
1511 * We also track th most recent recorded KHZ, write and time to
1512 * allow the matching interval to be extended at each write.
1513 */
f38e098f
ZA		 1514 kvm->arch.last_tsc_nsec = ns;
1515 kvm->arch.last_tsc_write = data;
5d3cb0f6 1516 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1517
b183aa58 1518 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1519
1520 /* Keep track of which generation this VCPU has synchronized to */
1521 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1522 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1523 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1524
ba904635
WA		 1525 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1526 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1527 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1528 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1529
1530 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1531 if (!matched) {
b48aa97e 1532 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1533 } else if (!already_matched) {
1534 kvm->arch.nr_vcpus_matched_tsc++;
1535 }
b48aa97e
MT		 1536
1537 kvm_track_tsc_matching(vcpu);
1538 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1539}
e26101b1 1540
99e3e30a
ZA		 1541EXPORT_SYMBOL_GPL(kvm_write_tsc);
1542
58ea6767
HZ		 1543static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1544 s64 adjustment)
1545{
1546 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1547}
1548
1549static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1550{
1551 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1552 WARN_ON(adjustment < 0);
1553 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1554 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1555}
1556
d828199e
MT		 1557#ifdef CONFIG_X86_64
1558
1559static cycle_t read_tsc(void)
1560{
03b9730b
AL		 1561 cycle_t ret = (cycle_t)rdtsc_ordered();
1562 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1563
1564 if (likely(ret >= last))
1565 return ret;
1566
1567 /*
1568 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1569 * predictable (it's just a function of time and the likely is
d828199e
MT		 1570 * very likely) and there's a data dependence, so force GCC
1571 * to generate a branch instead. I don't barrier() because
1572 * we don't actually need a barrier, and if this function
1573 * ever gets inlined it will generate worse code.
1574 */
1575 asm volatile ("");
1576 return last;
1577}
1578
1579static inline u64 vgettsc(cycle_t *cycle_now)
1580{
1581 long v;
1582 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1583
1584 *cycle_now = read_tsc();
1585
1586 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1587 return v * gtod->clock.mult;
1588}
1589
cbcf2dd3 1590static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1591{
cbcf2dd3 1592 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1593 unsigned long seq;
d828199e 1594 int mode;
cbcf2dd3 1595 u64 ns;
d828199e 1596
d828199e
MT		 1597 do {
1598 seq = read_seqcount_begin(&gtod->seq);
1599 mode = gtod->clock.vclock_mode;
cbcf2dd3 1600 ns = gtod->nsec_base;
d828199e
MT		 1601 ns += vgettsc(cycle_now);
1602 ns >>= gtod->clock.shift;
cbcf2dd3 1603 ns += gtod->boot_ns;
d828199e 1604 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1605 *t = ns;
d828199e
MT		 1606
1607 return mode;
1608}
1609
1610/* returns true if host is using tsc clocksource */
1611static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1612{
d828199e
MT		 1613 /* checked again under seqlock below */
1614 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1615 return false;
1616
cbcf2dd3 1617 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1618}
1619#endif
1620
1621/*
1622 *
b48aa97e
MT		 1623 * Assuming a stable TSC across physical CPUS, and a stable TSC
1624 * across virtual CPUs, the following condition is possible.
1625 * Each numbered line represents an event visible to both
d828199e
MT		 1626 * CPUs at the next numbered event.
1627 *
1628 * "timespecX" represents host monotonic time. "tscX" represents
1629 * RDTSC value.
1630 *
1631 * VCPU0 on CPU0 | VCPU1 on CPU1
1632 *
1633 * 1. read timespec0,tsc0
1634 * 2. | timespec1 = timespec0 + N
1635 * | tsc1 = tsc0 + M
1636 * 3. transition to guest | transition to guest
1637 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1638 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1639 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1640 *
1641 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1642 *
1643 * - ret0 < ret1
1644 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1645 * ...
1646 * - 0 < N - M => M < N
1647 *
1648 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1649 * always the case (the difference between two distinct xtime instances
1650 * might be smaller then the difference between corresponding TSC reads,
1651 * when updating guest vcpus pvclock areas).
1652 *
1653 * To avoid that problem, do not allow visibility of distinct
1654 * system_timestamp/tsc_timestamp values simultaneously: use a master
1655 * copy of host monotonic time values. Update that master copy
1656 * in lockstep.
1657 *
b48aa97e 1658 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1659 *
1660 */
1661
1662static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1663{
1664#ifdef CONFIG_X86_64
1665 struct kvm_arch *ka = &kvm->arch;
1666 int vclock_mode;
b48aa97e
MT		 1667 bool host_tsc_clocksource, vcpus_matched;
1668
1669 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1670 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1671
1672 /*
1673 * If the host uses TSC clock, then passthrough TSC as stable
1674 * to the guest.
1675 */
b48aa97e 1676 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1677 &ka->master_kernel_ns,
1678 &ka->master_cycle_now);
1679
16a96021 1680 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1681 && !backwards_tsc_observed
1682 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1683
d828199e
MT		 1684 if (ka->use_master_clock)
1685 atomic_set(&kvm_guest_has_master_clock, 1);
1686
1687 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1688 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1689 vcpus_matched);
d828199e
MT		 1690#endif
1691}
1692
2860c4b1
PB		 1693void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1694{
1695 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1696}
1697
2e762ff7
MT		 1698static void kvm_gen_update_masterclock(struct kvm *kvm)
1699{
1700#ifdef CONFIG_X86_64
1701 int i;
1702 struct kvm_vcpu *vcpu;
1703 struct kvm_arch *ka = &kvm->arch;
1704
1705 spin_lock(&ka->pvclock_gtod_sync_lock);
1706 kvm_make_mclock_inprogress_request(kvm);
1707 /* no guest entries from this point */
1708 pvclock_update_vm_gtod_copy(kvm);
1709
1710 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1711 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1712
1713 /* guest entries allowed */
1714 kvm_for_each_vcpu(i, vcpu, kvm)
1715 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1716
1717 spin_unlock(&ka->pvclock_gtod_sync_lock);
1718#endif
1719}
1720
34c238a1 1721static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1722{
78db6a50 1723 unsigned long flags, tgt_tsc_khz;
18068523 1724 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1725 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1726 s64 kernel_ns;
d828199e 1727 u64 tsc_timestamp, host_tsc;
0b79459b 1728 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1729 u8 pvclock_flags;
d828199e
MT		 1730 bool use_master_clock;
1731
1732 kernel_ns = 0;
1733 host_tsc = 0;
18068523 1734
d828199e
MT		 1735 /*
1736 * If the host uses TSC clock, then passthrough TSC as stable
1737 * to the guest.
1738 */
1739 spin_lock(&ka->pvclock_gtod_sync_lock);
1740 use_master_clock = ka->use_master_clock;
1741 if (use_master_clock) {
1742 host_tsc = ka->master_cycle_now;
1743 kernel_ns = ka->master_kernel_ns;
1744 }
1745 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1746
1747 /* Keep irq disabled to prevent changes to the clock */
1748 local_irq_save(flags);
78db6a50
PB		 1749 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1750 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1751 local_irq_restore(flags);
1752 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1753 return 1;
1754 }
d828199e 1755 if (!use_master_clock) {
4ea1636b 1756 host_tsc = rdtsc();
d828199e
MT		 1757 kernel_ns = get_kernel_ns();
1758 }
1759
4ba76538 1760 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1761
c285545f
ZA		 1762 /*
1763 * We may have to catch up the TSC to match elapsed wall clock
1764 * time for two reasons, even if kvmclock is used.
1765 * 1) CPU could have been running below the maximum TSC rate
1766 * 2) Broken TSC compensation resets the base at each VCPU
1767 * entry to avoid unknown leaps of TSC even when running
1768 * again on the same CPU. This may cause apparent elapsed
1769 * time to disappear, and the guest to stand still or run
1770 * very slowly.
1771 */
1772 if (vcpu->tsc_catchup) {
1773 u64 tsc = compute_guest_tsc(v, kernel_ns);
1774 if (tsc > tsc_timestamp) {
f1e2b260 1775 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1776 tsc_timestamp = tsc;
1777 }
50d0a0f9
GH		 1778 }
1779
18068523
GOC		 1780 local_irq_restore(flags);
1781
0b79459b 1782 if (!vcpu->pv_time_enabled)
c285545f 1783 return 0;
18068523 1784
78db6a50
PB		 1785 if (kvm_has_tsc_control)
1786 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1787
1788 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1789 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1790 &vcpu->hv_clock.tsc_shift,
1791 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1792 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1793 }
1794
1795 /* With all the info we got, fill in the values */
1d5f066e 1796 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1797 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1798 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1799
09a0c3f1
OH		 1800 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1801 &guest_hv_clock, sizeof(guest_hv_clock))))
1802 return 0;
1803
5dca0d91
RK		 1804 /* This VCPU is paused, but it's legal for a guest to read another
1805 * VCPU's kvmclock, so we really have to follow the specification where
1806 * it says that version is odd if data is being modified, and even after
1807 * it is consistent.
1808 *
1809 * Version field updates must be kept separate. This is because
1810 * kvm_write_guest_cached might use a "rep movs" instruction, and
1811 * writes within a string instruction are weakly ordered. So there
1812 * are three writes overall.
1813 *
1814 * As a small optimization, only write the version field in the first
1815 * and third write. The vcpu->pv_time cache is still valid, because the
1816 * version field is the first in the struct.
18068523 1817 */
5dca0d91
RK		 1818 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1819
1820 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1821 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1822 &vcpu->hv_clock,
1823 sizeof(vcpu->hv_clock.version));
1824
1825 smp_wmb();
78c0337a
MT		 1826
1827 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1828 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1829
1830 if (vcpu->pvclock_set_guest_stopped_request) {
1831 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1832 vcpu->pvclock_set_guest_stopped_request = false;
1833 }
1834
d828199e
MT		 1835 /* If the host uses TSC clocksource, then it is stable */
1836 if (use_master_clock)
1837 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1838
78c0337a
MT		 1839 vcpu->hv_clock.flags = pvclock_flags;
1840
ce1a5e60
DM		 1841 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1842
0b79459b
AH		 1843 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1844 &vcpu->hv_clock,
1845 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1846
1847 smp_wmb();
1848
1849 vcpu->hv_clock.version++;
1850 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1851 &vcpu->hv_clock,
1852 sizeof(vcpu->hv_clock.version));
8cfdc000 1853 return 0;
c8076604
GH		 1854}
1855
0061d53d
MT		 1856/*
1857 * kvmclock updates which are isolated to a given vcpu, such as
1858 * vcpu->cpu migration, should not allow system_timestamp from
1859 * the rest of the vcpus to remain static. Otherwise ntp frequency
1860 * correction applies to one vcpu's system_timestamp but not
1861 * the others.
1862 *
1863 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1864 * We need to rate-limit these requests though, as they can
1865 * considerably slow guests that have a large number of vcpus.
1866 * The time for a remote vcpu to update its kvmclock is bound
1867 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1868 */
1869
7e44e449
AJ		 1870#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1871
1872static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1873{
1874 int i;
7e44e449
AJ		 1875 struct delayed_work *dwork = to_delayed_work(work);
1876 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1877 kvmclock_update_work);
1878 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1879 struct kvm_vcpu *vcpu;
1880
1881 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1882 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1883 kvm_vcpu_kick(vcpu);
1884 }
1885}
1886
7e44e449
AJ		 1887static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1888{
1889 struct kvm *kvm = v->kvm;
1890
105b21bb 1891 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1892 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1893 KVMCLOCK_UPDATE_DELAY);
1894}
1895
332967a3
AJ		 1896#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1897
1898static void kvmclock_sync_fn(struct work_struct *work)
1899{
1900 struct delayed_work *dwork = to_delayed_work(work);
1901 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1902 kvmclock_sync_work);
1903 struct kvm *kvm = container_of(ka, struct kvm, arch);
1904
630994b3
MT		 1905 if (!kvmclock_periodic_sync)
1906 return;
1907
332967a3
AJ		 1908 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1909 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1910 KVMCLOCK_SYNC_PERIOD);
1911}
1912
890ca9ae 1913static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1914{
890ca9ae
HY		 1915 u64 mcg_cap = vcpu->arch.mcg_cap;
1916 unsigned bank_num = mcg_cap & 0xff;
1917
15c4a640 1918 switch (msr) {
15c4a640 1919 case MSR_IA32_MCG_STATUS:
890ca9ae 1920 vcpu->arch.mcg_status = data;
15c4a640 1921 break;
c7ac679c 1922 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1923 if (!(mcg_cap & MCG_CTL_P))
1924 return 1;
1925 if (data != 0 && data != ~(u64)0)
1926 return -1;
1927 vcpu->arch.mcg_ctl = data;
1928 break;
1929 default:
1930 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1931 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1932 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1933 /* only 0 or all 1s can be written to IA32_MCi_CTL
1934 * some Linux kernels though clear bit 10 in bank 4 to
1935 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1936 * this to avoid an uncatched #GP in the guest
1937 */
890ca9ae 1938 if ((offset & 0x3) == 0 &&
114be429 1939 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1940 return -1;
1941 vcpu->arch.mce_banks[offset] = data;
1942 break;
1943 }
1944 return 1;
1945 }
1946 return 0;
1947}
1948
ffde22ac
ES		 1949static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1950{
1951 struct kvm *kvm = vcpu->kvm;
1952 int lm = is_long_mode(vcpu);
1953 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1954 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1955 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1956 : kvm->arch.xen_hvm_config.blob_size_32;
1957 u32 page_num = data & ~PAGE_MASK;
1958 u64 page_addr = data & PAGE_MASK;
1959 u8 *page;
1960 int r;
1961
1962 r = -E2BIG;
1963 if (page_num >= blob_size)
1964 goto out;
1965 r = -ENOMEM;
ff5c2c03
SL		 1966 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1967 if (IS_ERR(page)) {
1968 r = PTR_ERR(page);
ffde22ac 1969 goto out;
ff5c2c03 1970 }
54bf36aa 1971 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1972 goto out_free;
1973 r = 0;
1974out_free:
1975 kfree(page);
1976out:
1977 return r;
1978}
1979
344d9588
GN		 1980static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1981{
1982 gpa_t gpa = data & ~0x3f;
1983
4a969980 1984 /* Bits 2:5 are reserved, Should be zero */
6adba527 1985 if (data & 0x3c)
344d9588
GN		 1986 return 1;
1987
1988 vcpu->arch.apf.msr_val = data;
1989
1990 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1991 kvm_clear_async_pf_completion_queue(vcpu);
1992 kvm_async_pf_hash_reset(vcpu);
1993 return 0;
1994 }
1995
8f964525
AH		 1996 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1997 sizeof(u32)))
344d9588
GN		 1998 return 1;
1999
6adba527 2000 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2001 kvm_async_pf_wakeup_all(vcpu);
2002 return 0;
2003}
2004
12f9a48f
GC		 2005static void kvmclock_reset(struct kvm_vcpu *vcpu)
2006{
0b79459b 2007 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2008}
2009
c9aaa895
GC		 2010static void record_steal_time(struct kvm_vcpu *vcpu)
2011{
2012 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2013 return;
2014
2015 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2016 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2017 return;
2018
35f3fae1
WL		 2019 if (vcpu->arch.st.steal.version & 1)
2020 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2021
2022 vcpu->arch.st.steal.version += 1;
2023
2024 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2025 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2026
2027 smp_wmb();
2028
c54cdf14
LC		 2029 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2030 vcpu->arch.st.last_steal;
2031 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1
WL		 2032
2033 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2034 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2035
2036 smp_wmb();
2037
2038 vcpu->arch.st.steal.version += 1;
c9aaa895
GC		 2039
2040 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2041 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2042}
2043
8fe8ab46 2044int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2045{
5753785f 2046 bool pr = false;
8fe8ab46
WA		 2047 u32 msr = msr_info->index;
2048 u64 data = msr_info->data;
5753785f 2049
15c4a640 2050 switch (msr) {
2e32b719
BP		 2051 case MSR_AMD64_NB_CFG:
2052 case MSR_IA32_UCODE_REV:
2053 case MSR_IA32_UCODE_WRITE:
2054 case MSR_VM_HSAVE_PA:
2055 case MSR_AMD64_PATCH_LOADER:
2056 case MSR_AMD64_BU_CFG2:
2057 break;
2058
15c4a640 2059 case MSR_EFER:
b69e8cae 2060 return set_efer(vcpu, data);
8f1589d9
AP		 2061 case MSR_K7_HWCR:
2062 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2063 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2064 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2065 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2066 if (data != 0) {
a737f256
CD		 2067 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2068 data);
8f1589d9
AP		 2069 return 1;
2070 }
15c4a640 2071 break;
f7c6d140
AP		 2072 case MSR_FAM10H_MMIO_CONF_BASE:
2073 if (data != 0) {
a737f256
CD		 2074 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2075 "0x%llx\n", data);
f7c6d140
AP		 2076 return 1;
2077 }
15c4a640 2078 break;
b5e2fec0
AG		 2079 case MSR_IA32_DEBUGCTLMSR:
2080 if (!data) {
2081 /* We support the non-activated case already */
2082 break;
2083 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2084 /* Values other than LBR and BTF are vendor-specific,
2085 thus reserved and should throw a #GP */
2086 return 1;
2087 }
a737f256
CD		 2088 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2089 __func__, data);
b5e2fec0 2090 break;
9ba075a6 2091 case 0x200 ... 0x2ff:
ff53604b 2092 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2093 case MSR_IA32_APICBASE:
58cb628d 2094 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2095 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2096 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2097 case MSR_IA32_TSCDEADLINE:
2098 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2099 break;
ba904635
WA		 2100 case MSR_IA32_TSC_ADJUST:
2101 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2102 if (!msr_info->host_initiated) {
d913b904 2103 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2104 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2105 }
2106 vcpu->arch.ia32_tsc_adjust_msr = data;
2107 }
2108 break;
15c4a640 2109 case MSR_IA32_MISC_ENABLE:
ad312c7c 2110 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2111 break;
64d60670
PB		 2112 case MSR_IA32_SMBASE:
2113 if (!msr_info->host_initiated)
2114 return 1;
2115 vcpu->arch.smbase = data;
2116 break;
11c6bffa 2117 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2118 case MSR_KVM_WALL_CLOCK:
2119 vcpu->kvm->arch.wall_clock = data;
2120 kvm_write_wall_clock(vcpu->kvm, data);
2121 break;
11c6bffa 2122 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2123 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2124 u64 gpa_offset;
54750f2c
MT		 2125 struct kvm_arch *ka = &vcpu->kvm->arch;
2126
12f9a48f 2127 kvmclock_reset(vcpu);
18068523 2128
54750f2c
MT		 2129 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2130 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2131
2132 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2133 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2134 &vcpu->requests);
2135
2136 ka->boot_vcpu_runs_old_kvmclock = tmp;
2137 }
2138
18068523 2139 vcpu->arch.time = data;
0061d53d 2140 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2141
2142 /* we verify if the enable bit is set... */
2143 if (!(data & 1))
2144 break;
2145
0b79459b 2146 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2147
0b79459b 2148 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2149 &vcpu->arch.pv_time, data & ~1ULL,
2150 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2151 vcpu->arch.pv_time_enabled = false;
2152 else
2153 vcpu->arch.pv_time_enabled = true;
32cad84f 2154
18068523
GOC		 2155 break;
2156 }
344d9588
GN		 2157 case MSR_KVM_ASYNC_PF_EN:
2158 if (kvm_pv_enable_async_pf(vcpu, data))
2159 return 1;
2160 break;
c9aaa895
GC		 2161 case MSR_KVM_STEAL_TIME:
2162
2163 if (unlikely(!sched_info_on()))
2164 return 1;
2165
2166 if (data & KVM_STEAL_RESERVED_MASK)
2167 return 1;
2168
2169 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2170 data & KVM_STEAL_VALID_BITS,
2171 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2172 return 1;
2173
2174 vcpu->arch.st.msr_val = data;
2175
2176 if (!(data & KVM_MSR_ENABLED))
2177 break;
2178
c9aaa895
GC		 2179 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2180
2181 break;
ae7a2a3f
MT		 2182 case MSR_KVM_PV_EOI_EN:
2183 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2184 return 1;
2185 break;
c9aaa895 2186
890ca9ae
HY		 2187 case MSR_IA32_MCG_CTL:
2188 case MSR_IA32_MCG_STATUS:
81760dcc 2189 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2190 return set_msr_mce(vcpu, msr, data);
71db6023 2191
6912ac32
WH		 2192 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2193 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2194 pr = true; /* fall through */
2195 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2196 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2197 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2198 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2199
2200 if (pr || data != 0)
a737f256
CD		 2201 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2202 "0x%x data 0x%llx\n", msr, data);
5753785f 2203 break;
84e0cefa
JS		 2204 case MSR_K7_CLK_CTL:
2205 /*
2206 * Ignore all writes to this no longer documented MSR.
2207 * Writes are only relevant for old K7 processors,
2208 * all pre-dating SVM, but a recommended workaround from
4a969980 2209 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2210 * affected processor models on the command line, hence
2211 * the need to ignore the workaround.
2212 */
2213 break;
55cd8e5a 2214 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2215 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2216 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2217 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2218 return kvm_hv_set_msr_common(vcpu, msr, data,
2219 msr_info->host_initiated);
91c9c3ed 2220 case MSR_IA32_BBL_CR_CTL3:
2221 /* Drop writes to this legacy MSR -- see rdmsr
2222 * counterpart for further detail.
2223 */
a737f256 2224 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2225 break;
2b036c6b
BO		 2226 case MSR_AMD64_OSVW_ID_LENGTH:
2227 if (!guest_cpuid_has_osvw(vcpu))
2228 return 1;
2229 vcpu->arch.osvw.length = data;
2230 break;
2231 case MSR_AMD64_OSVW_STATUS:
2232 if (!guest_cpuid_has_osvw(vcpu))
2233 return 1;
2234 vcpu->arch.osvw.status = data;
2235 break;
15c4a640 2236 default:
ffde22ac
ES		 2237 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2238 return xen_hvm_config(vcpu, data);
c6702c9d 2239 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2240 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2241 if (!ignore_msrs) {
a737f256
CD		 2242 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2243 msr, data);
ed85c068
AP		 2244 return 1;
2245 } else {
a737f256
CD		 2246 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2247 msr, data);
ed85c068
AP		 2248 break;
2249 }
15c4a640
CO		 2250 }
2251 return 0;
2252}
2253EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2254
2255
2256/*
2257 * Reads an msr value (of 'msr_index') into 'pdata'.
2258 * Returns 0 on success, non-0 otherwise.
2259 * Assumes vcpu_load() was already called.
2260 */
609e36d3 2261int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2262{
609e36d3 2263 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2264}
ff651cb6 2265EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2266
890ca9ae 2267static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2268{
2269 u64 data;
890ca9ae
HY		 2270 u64 mcg_cap = vcpu->arch.mcg_cap;
2271 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2272
2273 switch (msr) {
15c4a640
CO		 2274 case MSR_IA32_P5_MC_ADDR:
2275 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2276 data = 0;
2277 break;
15c4a640 2278 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2279 data = vcpu->arch.mcg_cap;
2280 break;
c7ac679c 2281 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2282 if (!(mcg_cap & MCG_CTL_P))
2283 return 1;
2284 data = vcpu->arch.mcg_ctl;
2285 break;
2286 case MSR_IA32_MCG_STATUS:
2287 data = vcpu->arch.mcg_status;
2288 break;
2289 default:
2290 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2291 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2292 u32 offset = msr - MSR_IA32_MC0_CTL;
2293 data = vcpu->arch.mce_banks[offset];
2294 break;
2295 }
2296 return 1;
2297 }
2298 *pdata = data;
2299 return 0;
2300}
2301
609e36d3 2302int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2303{
609e36d3 2304 switch (msr_info->index) {
890ca9ae 2305 case MSR_IA32_PLATFORM_ID:
15c4a640 2306 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2307 case MSR_IA32_DEBUGCTLMSR:
2308 case MSR_IA32_LASTBRANCHFROMIP:
2309 case MSR_IA32_LASTBRANCHTOIP:
2310 case MSR_IA32_LASTINTFROMIP:
2311 case MSR_IA32_LASTINTTOIP:
60af2ecd 2312 case MSR_K8_SYSCFG:
3afb1121
PB		 2313 case MSR_K8_TSEG_ADDR:
2314 case MSR_K8_TSEG_MASK:
60af2ecd 2315 case MSR_K7_HWCR:
61a6bd67 2316 case MSR_VM_HSAVE_PA:
1fdbd48c 2317 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2318 case MSR_AMD64_NB_CFG:
f7c6d140 2319 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2320 case MSR_AMD64_BU_CFG2:
0c2df2a1 2321 case MSR_IA32_PERF_CTL:
609e36d3 2322 msr_info->data = 0;
15c4a640 2323 break;
6912ac32
WH		 2324 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2325 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2326 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2327 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2328 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2329 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2330 msr_info->data = 0;
5753785f 2331 break;
742bc670 2332 case MSR_IA32_UCODE_REV:
609e36d3 2333 msr_info->data = 0x100000000ULL;
742bc670 2334 break;
9ba075a6 2335 case MSR_MTRRcap:
9ba075a6 2336 case 0x200 ... 0x2ff:
ff53604b 2337 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2338 case 0xcd: /* fsb frequency */
609e36d3 2339 msr_info->data = 3;
15c4a640 2340 break;
7b914098
JS		 2341 /*
2342 * MSR_EBC_FREQUENCY_ID
2343 * Conservative value valid for even the basic CPU models.
2344 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2345 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2346 * and 266MHz for model 3, or 4. Set Core Clock
2347 * Frequency to System Bus Frequency Ratio to 1 (bits
2348 * 31:24) even though these are only valid for CPU
2349 * models > 2, however guests may end up dividing or
2350 * multiplying by zero otherwise.
2351 */
2352 case MSR_EBC_FREQUENCY_ID:
609e36d3 2353 msr_info->data = 1 << 24;
7b914098 2354 break;
15c4a640 2355 case MSR_IA32_APICBASE:
609e36d3 2356 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2357 break;
0105d1a5 2358 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2359 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2360 break;
a3e06bbe 2361 case MSR_IA32_TSCDEADLINE:
609e36d3 2362 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2363 break;
ba904635 2364 case MSR_IA32_TSC_ADJUST:
609e36d3 2365 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2366 break;
15c4a640 2367 case MSR_IA32_MISC_ENABLE:
609e36d3 2368 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2369 break;
64d60670
PB		 2370 case MSR_IA32_SMBASE:
2371 if (!msr_info->host_initiated)
2372 return 1;
2373 msr_info->data = vcpu->arch.smbase;
15c4a640 2374 break;
847f0ad8
AG		 2375 case MSR_IA32_PERF_STATUS:
2376 /* TSC increment by tick */
609e36d3 2377 msr_info->data = 1000ULL;
847f0ad8 2378 /* CPU multiplier */
b0996ae4 2379 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2380 break;
15c4a640 2381 case MSR_EFER:
609e36d3 2382 msr_info->data = vcpu->arch.efer;
15c4a640 2383 break;
18068523 2384 case MSR_KVM_WALL_CLOCK:
11c6bffa 2385 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2386 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2387 break;
2388 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2389 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2390 msr_info->data = vcpu->arch.time;
18068523 2391 break;
344d9588 2392 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2393 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2394 break;
c9aaa895 2395 case MSR_KVM_STEAL_TIME:
609e36d3 2396 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2397 break;
1d92128f 2398 case MSR_KVM_PV_EOI_EN:
609e36d3 2399 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2400 break;
890ca9ae
HY		 2401 case MSR_IA32_P5_MC_ADDR:
2402 case MSR_IA32_P5_MC_TYPE:
2403 case MSR_IA32_MCG_CAP:
2404 case MSR_IA32_MCG_CTL:
2405 case MSR_IA32_MCG_STATUS:
81760dcc 2406 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2407 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2408 case MSR_K7_CLK_CTL:
2409 /*
2410 * Provide expected ramp-up count for K7. All other
2411 * are set to zero, indicating minimum divisors for
2412 * every field.
2413 *
2414 * This prevents guest kernels on AMD host with CPU
2415 * type 6, model 8 and higher from exploding due to
2416 * the rdmsr failing.
2417 */
609e36d3 2418 msr_info->data = 0x20000000;
84e0cefa 2419 break;
55cd8e5a 2420 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2421 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2422 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2423 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2424 return kvm_hv_get_msr_common(vcpu,
2425 msr_info->index, &msr_info->data);
55cd8e5a 2426 break;
91c9c3ed 2427 case MSR_IA32_BBL_CR_CTL3:
2428 /* This legacy MSR exists but isn't fully documented in current
2429 * silicon. It is however accessed by winxp in very narrow
2430 * scenarios where it sets bit #19, itself documented as
2431 * a "reserved" bit. Best effort attempt to source coherent
2432 * read data here should the balance of the register be
2433 * interpreted by the guest:
2434 *
2435 * L2 cache control register 3: 64GB range, 256KB size,
2436 * enabled, latency 0x1, configured
2437 */
609e36d3 2438 msr_info->data = 0xbe702111;
91c9c3ed 2439 break;
2b036c6b
BO		 2440 case MSR_AMD64_OSVW_ID_LENGTH:
2441 if (!guest_cpuid_has_osvw(vcpu))
2442 return 1;
609e36d3 2443 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2444 break;
2445 case MSR_AMD64_OSVW_STATUS:
2446 if (!guest_cpuid_has_osvw(vcpu))
2447 return 1;
609e36d3 2448 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2449 break;
15c4a640 2450 default:
c6702c9d 2451 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2452 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2453 if (!ignore_msrs) {
609e36d3 2454 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2455 return 1;
2456 } else {
609e36d3
PB		 2457 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2458 msr_info->data = 0;
ed85c068
AP		 2459 }
2460 break;
15c4a640 2461 }
15c4a640
CO		 2462 return 0;
2463}
2464EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2465
313a3dc7
CO		 2466/*
2467 * Read or write a bunch of msrs. All parameters are kernel addresses.
2468 *
2469 * @return number of msrs set successfully.
2470 */
2471static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2472 struct kvm_msr_entry *entries,
2473 int (*do_msr)(struct kvm_vcpu *vcpu,
2474 unsigned index, u64 *data))
2475{
f656ce01 2476 int i, idx;
313a3dc7 2477
f656ce01 2478 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2479 for (i = 0; i < msrs->nmsrs; ++i)
2480 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2481 break;
f656ce01 2482 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2483
313a3dc7
CO		 2484 return i;
2485}
2486
2487/*
2488 * Read or write a bunch of msrs. Parameters are user addresses.
2489 *
2490 * @return number of msrs set successfully.
2491 */
2492static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2493 int (*do_msr)(struct kvm_vcpu *vcpu,
2494 unsigned index, u64 *data),
2495 int writeback)
2496{
2497 struct kvm_msrs msrs;
2498 struct kvm_msr_entry *entries;
2499 int r, n;
2500 unsigned size;
2501
2502 r = -EFAULT;
2503 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2504 goto out;
2505
2506 r = -E2BIG;
2507 if (msrs.nmsrs >= MAX_IO_MSRS)
2508 goto out;
2509
313a3dc7 2510 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2511 entries = memdup_user(user_msrs->entries, size);
2512 if (IS_ERR(entries)) {
2513 r = PTR_ERR(entries);
313a3dc7 2514 goto out;
ff5c2c03 2515 }
313a3dc7
CO		 2516
2517 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2518 if (r < 0)
2519 goto out_free;
2520
2521 r = -EFAULT;
2522 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2523 goto out_free;
2524
2525 r = n;
2526
2527out_free:
7a73c028 2528 kfree(entries);
313a3dc7
CO		 2529out:
2530 return r;
2531}
2532
784aa3d7 2533int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2534{
2535 int r;
2536
2537 switch (ext) {
2538 case KVM_CAP_IRQCHIP:
2539 case KVM_CAP_HLT:
2540 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2541 case KVM_CAP_SET_TSS_ADDR:
07716717 2542 case KVM_CAP_EXT_CPUID:
9c15bb1d 2543 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2544 case KVM_CAP_CLOCKSOURCE:
7837699f 2545 case KVM_CAP_PIT:
a28e4f5a 2546 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2547 case KVM_CAP_MP_STATE:
ed848624 2548 case KVM_CAP_SYNC_MMU:
a355c85c 2549 case KVM_CAP_USER_NMI:
52d939a0 2550 case KVM_CAP_REINJECT_CONTROL:
4925663a 2551 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2552 case KVM_CAP_IOEVENTFD:
f848a5a8 2553 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2554 case KVM_CAP_PIT2:
e9f42757 2555 case KVM_CAP_PIT_STATE2:
b927a3ce 2556 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2557 case KVM_CAP_XEN_HVM:
afbcf7ab 2558 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2559 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2560 case KVM_CAP_HYPERV:
10388a07 2561 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2562 case KVM_CAP_HYPERV_SPIN:
5c919412 2563 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2564 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2565 case KVM_CAP_DEBUGREGS:
d2be1651 2566 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2567 case KVM_CAP_XSAVE:
344d9588 2568 case KVM_CAP_ASYNC_PF:
92a1f12d 2569 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2570 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2571 case KVM_CAP_READONLY_MEM:
5f66b620 2572 case KVM_CAP_HYPERV_TIME:
100943c5 2573 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2574 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2575 case KVM_CAP_ENABLE_CAP_VM:
2576 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2577 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2578 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2579#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2580 case KVM_CAP_ASSIGN_DEV_IRQ:
2581 case KVM_CAP_PCI_2_3:
2582#endif
018d00d2
ZX		 2583 r = 1;
2584 break;
6d396b55
PB		 2585 case KVM_CAP_X86_SMM:
2586 /* SMBASE is usually relocated above 1M on modern chipsets,
2587 * and SMM handlers might indeed rely on 4G segment limits,
2588 * so do not report SMM to be available if real mode is
2589 * emulated via vm86 mode. Still, do not go to great lengths
2590 * to avoid userspace's usage of the feature, because it is a
2591 * fringe case that is not enabled except via specific settings
2592 * of the module parameters.
2593 */
2594 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2595 break;
542472b5
LV		 2596 case KVM_CAP_COALESCED_MMIO:
2597 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2598 break;
774ead3a
AK		 2599 case KVM_CAP_VAPIC:
2600 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2601 break;
f725230a 2602 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2603 r = KVM_SOFT_MAX_VCPUS;
2604 break;
2605 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2606 r = KVM_MAX_VCPUS;
2607 break;
a988b910 2608 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2609 r = KVM_USER_MEM_SLOTS;
a988b910 2610 break;
a68a6a72
MT		 2611 case KVM_CAP_PV_MMU: /* obsolete */
2612 r = 0;
2f333bcb 2613 break;
4cee4b72 2614#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2615 case KVM_CAP_IOMMU:
a1b60c1c 2616 r = iommu_present(&pci_bus_type);
62c476c7 2617 break;
4cee4b72 2618#endif
890ca9ae
HY		 2619 case KVM_CAP_MCE:
2620 r = KVM_MAX_MCE_BANKS;
2621 break;
2d5b5a66 2622 case KVM_CAP_XCRS:
d366bf7e 2623 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2624 break;
92a1f12d
JR		 2625 case KVM_CAP_TSC_CONTROL:
2626 r = kvm_has_tsc_control;
2627 break;
018d00d2
ZX		 2628 default:
2629 r = 0;
2630 break;
2631 }
2632 return r;
2633
2634}
2635
043405e1
CO		 2636long kvm_arch_dev_ioctl(struct file *filp,
2637 unsigned int ioctl, unsigned long arg)
2638{
2639 void __user *argp = (void __user *)arg;
2640 long r;
2641
2642 switch (ioctl) {
2643 case KVM_GET_MSR_INDEX_LIST: {
2644 struct kvm_msr_list __user *user_msr_list = argp;
2645 struct kvm_msr_list msr_list;
2646 unsigned n;
2647
2648 r = -EFAULT;
2649 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2650 goto out;
2651 n = msr_list.nmsrs;
62ef68bb 2652 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2653 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2654 goto out;
2655 r = -E2BIG;
e125e7b6 2656 if (n < msr_list.nmsrs)
043405e1
CO		 2657 goto out;
2658 r = -EFAULT;
2659 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2660 num_msrs_to_save * sizeof(u32)))
2661 goto out;
e125e7b6 2662 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2663 &emulated_msrs,
62ef68bb 2664 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2665 goto out;
2666 r = 0;
2667 break;
2668 }
9c15bb1d
BP		 2669 case KVM_GET_SUPPORTED_CPUID:
2670 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2671 struct kvm_cpuid2 __user *cpuid_arg = argp;
2672 struct kvm_cpuid2 cpuid;
2673
2674 r = -EFAULT;
2675 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2676 goto out;
9c15bb1d
BP		 2677
2678 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2679 ioctl);
674eea0f
AK		 2680 if (r)
2681 goto out;
2682
2683 r = -EFAULT;
2684 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2685 goto out;
2686 r = 0;
2687 break;
2688 }
890ca9ae 2689 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2690 r = -EFAULT;
c45dcc71
AR		 2691 if (copy_to_user(argp, &kvm_mce_cap_supported,
2692 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2693 goto out;
2694 r = 0;
2695 break;
2696 }
043405e1
CO		 2697 default:
2698 r = -EINVAL;
2699 }
2700out:
2701 return r;
2702}
2703
f5f48ee1
SY		 2704static void wbinvd_ipi(void *garbage)
2705{
2706 wbinvd();
2707}
2708
2709static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2710{
e0f0bbc5 2711 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2712}
2713
2860c4b1
PB		 2714static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2715{
2716 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2717}
2718
313a3dc7
CO		 2719void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2720{
f5f48ee1
SY		 2721 /* Address WBINVD may be executed by guest */
2722 if (need_emulate_wbinvd(vcpu)) {
2723 if (kvm_x86_ops->has_wbinvd_exit())
2724 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2725 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2726 smp_call_function_single(vcpu->cpu,
2727 wbinvd_ipi, NULL, 1);
2728 }
2729
313a3dc7 2730 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2731
0dd6a6ed
ZA		 2732 /* Apply any externally detected TSC adjustments (due to suspend) */
2733 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2734 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2735 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2736 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2737 }
8f6055cb 2738
48434c20 2739 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2740 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2741 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2742 if (tsc_delta < 0)
2743 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a
YJ		 2744
2745 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2746 kvm_x86_ops->set_hv_timer(vcpu,
2747 kvm_get_lapic_tscdeadline_msr(vcpu)))
2748 kvm_lapic_switch_to_sw_timer(vcpu);
c285545f 2749 if (check_tsc_unstable()) {
07c1419a 2750 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2751 vcpu->arch.last_guest_tsc);
2752 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2753 vcpu->arch.tsc_catchup = 1;
c285545f 2754 }
d98d07ca
MT		 2755 /*
2756 * On a host with synchronized TSC, there is no need to update
2757 * kvmclock on vcpu->cpu migration
2758 */
2759 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2760 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2761 if (vcpu->cpu != cpu)
2762 kvm_migrate_timers(vcpu);
e48672fa 2763 vcpu->cpu = cpu;
6b7d7e76 2764 }
c9aaa895 2765
c9aaa895 2766 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2767}
2768
2769void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2770{
02daab21 2771 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2772 kvm_put_guest_fpu(vcpu);
4ea1636b 2773 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2774}
2775
313a3dc7
CO		 2776static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2777 struct kvm_lapic_state *s)
2778{
d62caabb
AS		 2779 if (vcpu->arch.apicv_active)
2780 kvm_x86_ops->sync_pir_to_irr(vcpu);
2781
ad312c7c 2782 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2783
2784 return 0;
2785}
2786
2787static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2788 struct kvm_lapic_state *s)
2789{
64eb0620 2790 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2791 update_cr8_intercept(vcpu);
313a3dc7
CO		 2792
2793 return 0;
2794}
2795
127a457a
MG		 2796static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2797{
2798 return (!lapic_in_kernel(vcpu) ||
2799 kvm_apic_accept_pic_intr(vcpu));
2800}
2801
782d422b
MG		 2802/*
2803 * if userspace requested an interrupt window, check that the
2804 * interrupt window is open.
2805 *
2806 * No need to exit to userspace if we already have an interrupt queued.
2807 */
2808static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2809{
2810 return kvm_arch_interrupt_allowed(vcpu) &&
2811 !kvm_cpu_has_interrupt(vcpu) &&
2812 !kvm_event_needs_reinjection(vcpu) &&
2813 kvm_cpu_accept_dm_intr(vcpu);
2814}
2815
f77bc6a4
ZX		 2816static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2817 struct kvm_interrupt *irq)
2818{
02cdb50f 2819 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2820 return -EINVAL;
1c1a9ce9
SR		 2821
2822 if (!irqchip_in_kernel(vcpu->kvm)) {
2823 kvm_queue_interrupt(vcpu, irq->irq, false);
2824 kvm_make_request(KVM_REQ_EVENT, vcpu);
2825 return 0;
2826 }
2827
2828 /*
2829 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2830 * fail for in-kernel 8259.
2831 */
2832 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2833 return -ENXIO;
f77bc6a4 2834
1c1a9ce9
SR		 2835 if (vcpu->arch.pending_external_vector != -1)
2836 return -EEXIST;
f77bc6a4 2837
1c1a9ce9 2838 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2839 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2840 return 0;
2841}
2842
c4abb7c9
JK		 2843static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2844{
c4abb7c9 2845 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2846
2847 return 0;
2848}
2849
f077825a
PB		 2850static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2851{
64d60670
PB		 2852 kvm_make_request(KVM_REQ_SMI, vcpu);
2853
f077825a
PB		 2854 return 0;
2855}
2856
b209749f
AK		 2857static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2858 struct kvm_tpr_access_ctl *tac)
2859{
2860 if (tac->flags)
2861 return -EINVAL;
2862 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2863 return 0;
2864}
2865
890ca9ae
HY		 2866static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2867 u64 mcg_cap)
2868{
2869 int r;
2870 unsigned bank_num = mcg_cap & 0xff, bank;
2871
2872 r = -EINVAL;
a9e38c3e 2873 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 2874 goto out;
c45dcc71 2875 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 2876 goto out;
2877 r = 0;
2878 vcpu->arch.mcg_cap = mcg_cap;
2879 /* Init IA32_MCG_CTL to all 1s */
2880 if (mcg_cap & MCG_CTL_P)
2881 vcpu->arch.mcg_ctl = ~(u64)0;
2882 /* Init IA32_MCi_CTL to all 1s */
2883 for (bank = 0; bank < bank_num; bank++)
2884 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 2885
2886 if (kvm_x86_ops->setup_mce)
2887 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 2888out:
2889 return r;
2890}
2891
2892static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2893 struct kvm_x86_mce *mce)
2894{
2895 u64 mcg_cap = vcpu->arch.mcg_cap;
2896 unsigned bank_num = mcg_cap & 0xff;
2897 u64 *banks = vcpu->arch.mce_banks;
2898
2899 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2900 return -EINVAL;
2901 /*
2902 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2903 * reporting is disabled
2904 */
2905 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2906 vcpu->arch.mcg_ctl != ~(u64)0)
2907 return 0;
2908 banks += 4 * mce->bank;
2909 /*
2910 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2911 * reporting is disabled for the bank
2912 */
2913 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2914 return 0;
2915 if (mce->status & MCI_STATUS_UC) {
2916 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2917 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2918 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2919 return 0;
2920 }
2921 if (banks[1] & MCI_STATUS_VAL)
2922 mce->status |= MCI_STATUS_OVER;
2923 banks[2] = mce->addr;
2924 banks[3] = mce->misc;
2925 vcpu->arch.mcg_status = mce->mcg_status;
2926 banks[1] = mce->status;
2927 kvm_queue_exception(vcpu, MC_VECTOR);
2928 } else if (!(banks[1] & MCI_STATUS_VAL)
2929 || !(banks[1] & MCI_STATUS_UC)) {
2930 if (banks[1] & MCI_STATUS_VAL)
2931 mce->status |= MCI_STATUS_OVER;
2932 banks[2] = mce->addr;
2933 banks[3] = mce->misc;
2934 banks[1] = mce->status;
2935 } else
2936 banks[1] |= MCI_STATUS_OVER;
2937 return 0;
2938}
2939
3cfc3092
JK		 2940static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2941 struct kvm_vcpu_events *events)
2942{
7460fb4a 2943 process_nmi(vcpu);
03b82a30
JK		 2944 events->exception.injected =
2945 vcpu->arch.exception.pending &&
2946 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2947 events->exception.nr = vcpu->arch.exception.nr;
2948 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2949 events->exception.pad = 0;
3cfc3092
JK		 2950 events->exception.error_code = vcpu->arch.exception.error_code;
2951
03b82a30
JK		 2952 events->interrupt.injected =
2953 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2954 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2955 events->interrupt.soft = 0;
37ccdcbe 2956 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2957
2958 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2959 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2960 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2961 events->nmi.pad = 0;
3cfc3092 2962
66450a21 2963 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2964
f077825a
PB		 2965 events->smi.smm = is_smm(vcpu);
2966 events->smi.pending = vcpu->arch.smi_pending;
2967 events->smi.smm_inside_nmi =
2968 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2969 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2970
dab4b911 2971 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2972 | KVM_VCPUEVENT_VALID_SHADOW
2973 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2974 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2975}
2976
2977static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2978 struct kvm_vcpu_events *events)
2979{
dab4b911 2980 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2981 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2982 | KVM_VCPUEVENT_VALID_SHADOW
2983 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2984 return -EINVAL;
2985
78e546c8
PB		 2986 if (events->exception.injected &&
2987 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
2988 return -EINVAL;
2989
7460fb4a 2990 process_nmi(vcpu);
3cfc3092
JK		 2991 vcpu->arch.exception.pending = events->exception.injected;
2992 vcpu->arch.exception.nr = events->exception.nr;
2993 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2994 vcpu->arch.exception.error_code = events->exception.error_code;
2995
2996 vcpu->arch.interrupt.pending = events->interrupt.injected;
2997 vcpu->arch.interrupt.nr = events->interrupt.nr;
2998 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2999 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3000 kvm_x86_ops->set_interrupt_shadow(vcpu,
3001 events->interrupt.shadow);
3cfc3092
JK		 3002
3003 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3004 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3005 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3006 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3007
66450a21 3008 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3009 lapic_in_kernel(vcpu))
66450a21 3010 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3011
f077825a
PB		 3012 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3013 if (events->smi.smm)
3014 vcpu->arch.hflags |= HF_SMM_MASK;
3015 else
3016 vcpu->arch.hflags &= ~HF_SMM_MASK;
3017 vcpu->arch.smi_pending = events->smi.pending;
3018 if (events->smi.smm_inside_nmi)
3019 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3020 else
3021 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3022 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3023 if (events->smi.latched_init)
3024 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3025 else
3026 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3027 }
3028 }
3029
3842d135
AK		 3030 kvm_make_request(KVM_REQ_EVENT, vcpu);
3031
3cfc3092
JK		 3032 return 0;
3033}
3034
a1efbe77
JK		 3035static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3036 struct kvm_debugregs *dbgregs)
3037{
73aaf249
JK		 3038 unsigned long val;
3039
a1efbe77 3040 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3041 kvm_get_dr(vcpu, 6, &val);
73aaf249 3042 dbgregs->dr6 = val;
a1efbe77
JK		 3043 dbgregs->dr7 = vcpu->arch.dr7;
3044 dbgregs->flags = 0;
97e69aa6 3045 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3046}
3047
3048static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3049 struct kvm_debugregs *dbgregs)
3050{
3051 if (dbgregs->flags)
3052 return -EINVAL;
3053
d14bdb55
PB		 3054 if (dbgregs->dr6 & ~0xffffffffull)
3055 return -EINVAL;
3056 if (dbgregs->dr7 & ~0xffffffffull)
3057 return -EINVAL;
3058
a1efbe77 3059 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3060 kvm_update_dr0123(vcpu);
a1efbe77 3061 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3062 kvm_update_dr6(vcpu);
a1efbe77 3063 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3064 kvm_update_dr7(vcpu);
a1efbe77 3065
a1efbe77
JK		 3066 return 0;
3067}
3068
df1daba7
PB		 3069#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3070
3071static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3072{
c47ada30 3073 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3074 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3075 u64 valid;
3076
3077 /*
3078 * Copy legacy XSAVE area, to avoid complications with CPUID
3079 * leaves 0 and 1 in the loop below.
3080 */
3081 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3082
3083 /* Set XSTATE_BV */
3084 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3085
3086 /*
3087 * Copy each region from the possibly compacted offset to the
3088 * non-compacted offset.
3089 */
d91cab78 3090 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3091 while (valid) {
3092 u64 feature = valid & -valid;
3093 int index = fls64(feature) - 1;
3094 void *src = get_xsave_addr(xsave, feature);
3095
3096 if (src) {
3097 u32 size, offset, ecx, edx;
3098 cpuid_count(XSTATE_CPUID, index,
3099 &size, &offset, &ecx, &edx);
3100 memcpy(dest + offset, src, size);
3101 }
3102
3103 valid -= feature;
3104 }
3105}
3106
3107static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3108{
c47ada30 3109 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3110 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3111 u64 valid;
3112
3113 /*
3114 * Copy legacy XSAVE area, to avoid complications with CPUID
3115 * leaves 0 and 1 in the loop below.
3116 */
3117 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3118
3119 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3120 xsave->header.xfeatures = xstate_bv;
782511b0 3121 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3122 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3123
3124 /*
3125 * Copy each region from the non-compacted offset to the
3126 * possibly compacted offset.
3127 */
d91cab78 3128 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3129 while (valid) {
3130 u64 feature = valid & -valid;
3131 int index = fls64(feature) - 1;
3132 void *dest = get_xsave_addr(xsave, feature);
3133
3134 if (dest) {
3135 u32 size, offset, ecx, edx;
3136 cpuid_count(XSTATE_CPUID, index,
3137 &size, &offset, &ecx, &edx);
3138 memcpy(dest, src + offset, size);
ee4100da 3139 }
df1daba7
PB		 3140
3141 valid -= feature;
3142 }
3143}
3144
2d5b5a66
SY		 3145static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3146 struct kvm_xsave *guest_xsave)
3147{
d366bf7e 3148 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3149 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3150 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3151 } else {
2d5b5a66 3152 memcpy(guest_xsave->region,
7366ed77 3153 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3154 sizeof(struct fxregs_state));
2d5b5a66 3155 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3156 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3157 }
3158}
3159
3160static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3161 struct kvm_xsave *guest_xsave)
3162{
3163 u64 xstate_bv =
3164 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3165
d366bf7e 3166 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3167 /*
3168 * Here we allow setting states that are not present in
3169 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3170 * with old userspace.
3171 */
4ff41732 3172 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3173 return -EINVAL;
df1daba7 3174 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3175 } else {
d91cab78 3176 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3177 return -EINVAL;
7366ed77 3178 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3179 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3180 }
3181 return 0;
3182}
3183
3184static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3185 struct kvm_xcrs *guest_xcrs)
3186{
d366bf7e 3187 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3188 guest_xcrs->nr_xcrs = 0;
3189 return;
3190 }
3191
3192 guest_xcrs->nr_xcrs = 1;
3193 guest_xcrs->flags = 0;
3194 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3195 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3196}
3197
3198static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3199 struct kvm_xcrs *guest_xcrs)
3200{
3201 int i, r = 0;
3202
d366bf7e 3203 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3204 return -EINVAL;
3205
3206 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3207 return -EINVAL;
3208
3209 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3210 /* Only support XCR0 currently */
c67a04cb 3211 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3212 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3213 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3214 break;
3215 }
3216 if (r)
3217 r = -EINVAL;
3218 return r;
3219}
3220
1c0b28c2
EM		 3221/*
3222 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3223 * stopped by the hypervisor. This function will be called from the host only.
3224 * EINVAL is returned when the host attempts to set the flag for a guest that
3225 * does not support pv clocks.
3226 */
3227static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3228{
0b79459b 3229 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3230 return -EINVAL;
51d59c6b 3231 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3232 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3233 return 0;
3234}
3235
5c919412
AS		 3236static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3237 struct kvm_enable_cap *cap)
3238{
3239 if (cap->flags)
3240 return -EINVAL;
3241
3242 switch (cap->cap) {
3243 case KVM_CAP_HYPERV_SYNIC:
3244 return kvm_hv_activate_synic(vcpu);
3245 default:
3246 return -EINVAL;
3247 }
3248}
3249
313a3dc7
CO		 3250long kvm_arch_vcpu_ioctl(struct file *filp,
3251 unsigned int ioctl, unsigned long arg)
3252{
3253 struct kvm_vcpu *vcpu = filp->private_data;
3254 void __user *argp = (void __user *)arg;
3255 int r;
d1ac91d8
AK		 3256 union {
3257 struct kvm_lapic_state *lapic;
3258 struct kvm_xsave *xsave;
3259 struct kvm_xcrs *xcrs;
3260 void *buffer;
3261 } u;
3262
3263 u.buffer = NULL;
313a3dc7
CO		 3264 switch (ioctl) {
3265 case KVM_GET_LAPIC: {
2204ae3c 3266 r = -EINVAL;
bce87cce 3267 if (!lapic_in_kernel(vcpu))
2204ae3c 3268 goto out;
d1ac91d8 3269 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3270
b772ff36 3271 r = -ENOMEM;
d1ac91d8 3272 if (!u.lapic)
b772ff36 3273 goto out;
d1ac91d8 3274 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3275 if (r)
3276 goto out;
3277 r = -EFAULT;
d1ac91d8 3278 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3279 goto out;
3280 r = 0;
3281 break;
3282 }
3283 case KVM_SET_LAPIC: {
2204ae3c 3284 r = -EINVAL;
bce87cce 3285 if (!lapic_in_kernel(vcpu))
2204ae3c 3286 goto out;
ff5c2c03 3287 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3288 if (IS_ERR(u.lapic))
3289 return PTR_ERR(u.lapic);
ff5c2c03 3290
d1ac91d8 3291 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3292 break;
3293 }
f77bc6a4
ZX		 3294 case KVM_INTERRUPT: {
3295 struct kvm_interrupt irq;
3296
3297 r = -EFAULT;
3298 if (copy_from_user(&irq, argp, sizeof irq))
3299 goto out;
3300 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3301 break;
3302 }
c4abb7c9
JK		 3303 case KVM_NMI: {
3304 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3305 break;
3306 }
f077825a
PB		 3307 case KVM_SMI: {
3308 r = kvm_vcpu_ioctl_smi(vcpu);
3309 break;
3310 }
313a3dc7
CO		 3311 case KVM_SET_CPUID: {
3312 struct kvm_cpuid __user *cpuid_arg = argp;
3313 struct kvm_cpuid cpuid;
3314
3315 r = -EFAULT;
3316 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3317 goto out;
3318 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3319 break;
3320 }
07716717
DK		 3321 case KVM_SET_CPUID2: {
3322 struct kvm_cpuid2 __user *cpuid_arg = argp;
3323 struct kvm_cpuid2 cpuid;
3324
3325 r = -EFAULT;
3326 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3327 goto out;
3328 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3329 cpuid_arg->entries);
07716717
DK		 3330 break;
3331 }
3332 case KVM_GET_CPUID2: {
3333 struct kvm_cpuid2 __user *cpuid_arg = argp;
3334 struct kvm_cpuid2 cpuid;
3335
3336 r = -EFAULT;
3337 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3338 goto out;
3339 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3340 cpuid_arg->entries);
07716717
DK		 3341 if (r)
3342 goto out;
3343 r = -EFAULT;
3344 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3345 goto out;
3346 r = 0;
3347 break;
3348 }
313a3dc7 3349 case KVM_GET_MSRS:
609e36d3 3350 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3351 break;
3352 case KVM_SET_MSRS:
3353 r = msr_io(vcpu, argp, do_set_msr, 0);
3354 break;
b209749f
AK		 3355 case KVM_TPR_ACCESS_REPORTING: {
3356 struct kvm_tpr_access_ctl tac;
3357
3358 r = -EFAULT;
3359 if (copy_from_user(&tac, argp, sizeof tac))
3360 goto out;
3361 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3362 if (r)
3363 goto out;
3364 r = -EFAULT;
3365 if (copy_to_user(argp, &tac, sizeof tac))
3366 goto out;
3367 r = 0;
3368 break;
3369 };
b93463aa
AK		 3370 case KVM_SET_VAPIC_ADDR: {
3371 struct kvm_vapic_addr va;
3372
3373 r = -EINVAL;
35754c98 3374 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3375 goto out;
3376 r = -EFAULT;
3377 if (copy_from_user(&va, argp, sizeof va))
3378 goto out;
fda4e2e8 3379 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3380 break;
3381 }
890ca9ae
HY		 3382 case KVM_X86_SETUP_MCE: {
3383 u64 mcg_cap;
3384
3385 r = -EFAULT;
3386 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3387 goto out;
3388 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3389 break;
3390 }
3391 case KVM_X86_SET_MCE: {
3392 struct kvm_x86_mce mce;
3393
3394 r = -EFAULT;
3395 if (copy_from_user(&mce, argp, sizeof mce))
3396 goto out;
3397 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3398 break;
3399 }
3cfc3092
JK		 3400 case KVM_GET_VCPU_EVENTS: {
3401 struct kvm_vcpu_events events;
3402
3403 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3404
3405 r = -EFAULT;
3406 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3407 break;
3408 r = 0;
3409 break;
3410 }
3411 case KVM_SET_VCPU_EVENTS: {
3412 struct kvm_vcpu_events events;
3413
3414 r = -EFAULT;
3415 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3416 break;
3417
3418 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3419 break;
3420 }
a1efbe77
JK		 3421 case KVM_GET_DEBUGREGS: {
3422 struct kvm_debugregs dbgregs;
3423
3424 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3425
3426 r = -EFAULT;
3427 if (copy_to_user(argp, &dbgregs,
3428 sizeof(struct kvm_debugregs)))
3429 break;
3430 r = 0;
3431 break;
3432 }
3433 case KVM_SET_DEBUGREGS: {
3434 struct kvm_debugregs dbgregs;
3435
3436 r = -EFAULT;
3437 if (copy_from_user(&dbgregs, argp,
3438 sizeof(struct kvm_debugregs)))
3439 break;
3440
3441 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3442 break;
3443 }
2d5b5a66 3444 case KVM_GET_XSAVE: {
d1ac91d8 3445 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3446 r = -ENOMEM;
d1ac91d8 3447 if (!u.xsave)
2d5b5a66
SY		 3448 break;
3449
d1ac91d8 3450 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3451
3452 r = -EFAULT;
d1ac91d8 3453 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3454 break;
3455 r = 0;
3456 break;
3457 }
3458 case KVM_SET_XSAVE: {
ff5c2c03 3459 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3460 if (IS_ERR(u.xsave))
3461 return PTR_ERR(u.xsave);
2d5b5a66 3462
d1ac91d8 3463 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3464 break;
3465 }
3466 case KVM_GET_XCRS: {
d1ac91d8 3467 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3468 r = -ENOMEM;
d1ac91d8 3469 if (!u.xcrs)
2d5b5a66
SY		 3470 break;
3471
d1ac91d8 3472 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3473
3474 r = -EFAULT;
d1ac91d8 3475 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3476 sizeof(struct kvm_xcrs)))
3477 break;
3478 r = 0;
3479 break;
3480 }
3481 case KVM_SET_XCRS: {
ff5c2c03 3482 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3483 if (IS_ERR(u.xcrs))
3484 return PTR_ERR(u.xcrs);
2d5b5a66 3485
d1ac91d8 3486 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3487 break;
3488 }
92a1f12d
JR		 3489 case KVM_SET_TSC_KHZ: {
3490 u32 user_tsc_khz;
3491
3492 r = -EINVAL;
92a1f12d
JR		 3493 user_tsc_khz = (u32)arg;
3494
3495 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3496 goto out;
3497
cc578287
ZA		 3498 if (user_tsc_khz == 0)
3499 user_tsc_khz = tsc_khz;
3500
381d585c
HZ		 3501 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3502 r = 0;
92a1f12d 3503
92a1f12d
JR		 3504 goto out;
3505 }
3506 case KVM_GET_TSC_KHZ: {
cc578287 3507 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3508 goto out;
3509 }
1c0b28c2
EM		 3510 case KVM_KVMCLOCK_CTRL: {
3511 r = kvm_set_guest_paused(vcpu);
3512 goto out;
3513 }
5c919412
AS		 3514 case KVM_ENABLE_CAP: {
3515 struct kvm_enable_cap cap;
3516
3517 r = -EFAULT;
3518 if (copy_from_user(&cap, argp, sizeof(cap)))
3519 goto out;
3520 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3521 break;
3522 }
313a3dc7
CO		 3523 default:
3524 r = -EINVAL;
3525 }
3526out:
d1ac91d8 3527 kfree(u.buffer);
313a3dc7
CO		 3528 return r;
3529}
3530
5b1c1493
CO		 3531int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3532{
3533 return VM_FAULT_SIGBUS;
3534}
3535
1fe779f8
CO		 3536static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3537{
3538 int ret;
3539
3540 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3541 return -EINVAL;
1fe779f8
CO		 3542 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3543 return ret;
3544}
3545
b927a3ce
SY		 3546static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3547 u64 ident_addr)
3548{
3549 kvm->arch.ept_identity_map_addr = ident_addr;
3550 return 0;
3551}
3552
1fe779f8
CO		 3553static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3554 u32 kvm_nr_mmu_pages)
3555{
3556 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3557 return -EINVAL;
3558
79fac95e 3559 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3560
3561 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3562 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3563
79fac95e 3564 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3565 return 0;
3566}
3567
3568static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3569{
39de71ec 3570 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3571}
3572
1fe779f8
CO		 3573static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3574{
3575 int r;
3576
3577 r = 0;
3578 switch (chip->chip_id) {
3579 case KVM_IRQCHIP_PIC_MASTER:
3580 memcpy(&chip->chip.pic,
3581 &pic_irqchip(kvm)->pics[0],
3582 sizeof(struct kvm_pic_state));
3583 break;
3584 case KVM_IRQCHIP_PIC_SLAVE:
3585 memcpy(&chip->chip.pic,
3586 &pic_irqchip(kvm)->pics[1],
3587 sizeof(struct kvm_pic_state));
3588 break;
3589 case KVM_IRQCHIP_IOAPIC:
eba0226b 3590 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3591 break;
3592 default:
3593 r = -EINVAL;
3594 break;
3595 }
3596 return r;
3597}
3598
3599static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3600{
3601 int r;
3602
3603 r = 0;
3604 switch (chip->chip_id) {
3605 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3606 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3607 memcpy(&pic_irqchip(kvm)->pics[0],
3608 &chip->chip.pic,
3609 sizeof(struct kvm_pic_state));
f4f51050 3610 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3611 break;
3612 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3613 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3614 memcpy(&pic_irqchip(kvm)->pics[1],
3615 &chip->chip.pic,
3616 sizeof(struct kvm_pic_state));
f4f51050 3617 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3618 break;
3619 case KVM_IRQCHIP_IOAPIC:
eba0226b 3620 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3621 break;
3622 default:
3623 r = -EINVAL;
3624 break;
3625 }
3626 kvm_pic_update_irq(pic_irqchip(kvm));
3627 return r;
3628}
3629
e0f63cb9
SY		 3630static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3631{
34f3941c
RK		 3632 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3633
3634 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3635
3636 mutex_lock(&kps->lock);
3637 memcpy(ps, &kps->channels, sizeof(*ps));
3638 mutex_unlock(&kps->lock);
2da29bcc 3639 return 0;
e0f63cb9
SY		 3640}
3641
3642static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3643{
0185604c 3644 int i;
09edea72
RK		 3645 struct kvm_pit *pit = kvm->arch.vpit;
3646
3647 mutex_lock(&pit->pit_state.lock);
34f3941c 3648 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3649 for (i = 0; i < 3; i++)
09edea72
RK		 3650 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3651 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3652 return 0;
e9f42757
BK		 3653}
3654
3655static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3656{
e9f42757
BK		 3657 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3658 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3659 sizeof(ps->channels));
3660 ps->flags = kvm->arch.vpit->pit_state.flags;
3661 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3662 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3663 return 0;
e9f42757
BK		 3664}
3665
3666static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3667{
2da29bcc 3668 int start = 0;
0185604c 3669 int i;
e9f42757 3670 u32 prev_legacy, cur_legacy;
09edea72
RK		 3671 struct kvm_pit *pit = kvm->arch.vpit;
3672
3673 mutex_lock(&pit->pit_state.lock);
3674 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3675 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3676 if (!prev_legacy && cur_legacy)
3677 start = 1;
09edea72
RK		 3678 memcpy(&pit->pit_state.channels, &ps->channels,
3679 sizeof(pit->pit_state.channels));
3680 pit->pit_state.flags = ps->flags;
0185604c 3681 for (i = 0; i < 3; i++)
09edea72 3682 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3683 start && i == 0);
09edea72 3684 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3685 return 0;
e0f63cb9
SY		 3686}
3687
52d939a0
MT		 3688static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3689 struct kvm_reinject_control *control)
3690{
71474e2f
RK		 3691 struct kvm_pit *pit = kvm->arch.vpit;
3692
3693 if (!pit)
52d939a0 3694 return -ENXIO;
b39c90b6 3695
71474e2f
RK		 3696 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3697 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3698 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3699 */
3700 mutex_lock(&pit->pit_state.lock);
3701 kvm_pit_set_reinject(pit, control->pit_reinject);
3702 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3703
52d939a0
MT		 3704 return 0;
3705}
3706
95d4c16c 3707/**
60c34612
TY		 3708 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3709 * @kvm: kvm instance
3710 * @log: slot id and address to which we copy the log
95d4c16c 3711 *
e108ff2f
PB		 3712 * Steps 1-4 below provide general overview of dirty page logging. See
3713 * kvm_get_dirty_log_protect() function description for additional details.
3714 *
3715 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3716 * always flush the TLB (step 4) even if previous step failed and the dirty
3717 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3718 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3719 * writes will be marked dirty for next log read.
95d4c16c 3720 *
60c34612
TY		 3721 * 1. Take a snapshot of the bit and clear it if needed.
3722 * 2. Write protect the corresponding page.
e108ff2f
PB		 3723 * 3. Copy the snapshot to the userspace.
3724 * 4. Flush TLB's if needed.
5bb064dc 3725 */
60c34612 3726int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3727{
60c34612 3728 bool is_dirty = false;
e108ff2f 3729 int r;
5bb064dc 3730
79fac95e 3731 mutex_lock(&kvm->slots_lock);
5bb064dc 3732
88178fd4
KH		 3733 /*
3734 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3735 */
3736 if (kvm_x86_ops->flush_log_dirty)
3737 kvm_x86_ops->flush_log_dirty(kvm);
3738
e108ff2f 3739 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3740
3741 /*
3742 * All the TLBs can be flushed out of mmu lock, see the comments in
3743 * kvm_mmu_slot_remove_write_access().
3744 */
e108ff2f 3745 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3746 if (is_dirty)
3747 kvm_flush_remote_tlbs(kvm);
3748
79fac95e 3749 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3750 return r;
3751}
3752
aa2fbe6d
YZ		 3753int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3754 bool line_status)
23d43cf9
CD		 3755{
3756 if (!irqchip_in_kernel(kvm))
3757 return -ENXIO;
3758
3759 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3760 irq_event->irq, irq_event->level,
3761 line_status);
23d43cf9
CD		 3762 return 0;
3763}
3764
90de4a18
NA		 3765static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3766 struct kvm_enable_cap *cap)
3767{
3768 int r;
3769
3770 if (cap->flags)
3771 return -EINVAL;
3772
3773 switch (cap->cap) {
3774 case KVM_CAP_DISABLE_QUIRKS:
3775 kvm->arch.disabled_quirks = cap->args[0];
3776 r = 0;
3777 break;
49df6397
SR		 3778 case KVM_CAP_SPLIT_IRQCHIP: {
3779 mutex_lock(&kvm->lock);
b053b2ae
SR		 3780 r = -EINVAL;
3781 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3782 goto split_irqchip_unlock;
49df6397
SR		 3783 r = -EEXIST;
3784 if (irqchip_in_kernel(kvm))
3785 goto split_irqchip_unlock;
557abc40 3786 if (kvm->created_vcpus)
49df6397
SR		 3787 goto split_irqchip_unlock;
3788 r = kvm_setup_empty_irq_routing(kvm);
3789 if (r)
3790 goto split_irqchip_unlock;
3791 /* Pairs with irqchip_in_kernel. */
3792 smp_wmb();
3793 kvm->arch.irqchip_split = true;
b053b2ae 3794 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3795 r = 0;
3796split_irqchip_unlock:
3797 mutex_unlock(&kvm->lock);
3798 break;
3799 }
90de4a18
NA		 3800 default:
3801 r = -EINVAL;
3802 break;
3803 }
3804 return r;
3805}
3806
1fe779f8
CO		 3807long kvm_arch_vm_ioctl(struct file *filp,
3808 unsigned int ioctl, unsigned long arg)
3809{
3810 struct kvm *kvm = filp->private_data;
3811 void __user *argp = (void __user *)arg;
367e1319 3812 int r = -ENOTTY;
f0d66275
DH		 3813 /*
3814 * This union makes it completely explicit to gcc-3.x
3815 * that these two variables' stack usage should be
3816 * combined, not added together.
3817 */
3818 union {
3819 struct kvm_pit_state ps;
e9f42757 3820 struct kvm_pit_state2 ps2;
c5ff41ce 3821 struct kvm_pit_config pit_config;
f0d66275 3822 } u;
1fe779f8
CO		 3823
3824 switch (ioctl) {
3825 case KVM_SET_TSS_ADDR:
3826 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3827 break;
b927a3ce
SY		 3828 case KVM_SET_IDENTITY_MAP_ADDR: {
3829 u64 ident_addr;
3830
3831 r = -EFAULT;
3832 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3833 goto out;
3834 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3835 break;
3836 }
1fe779f8
CO		 3837 case KVM_SET_NR_MMU_PAGES:
3838 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3839 break;
3840 case KVM_GET_NR_MMU_PAGES:
3841 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3842 break;
3ddea128
MT		 3843 case KVM_CREATE_IRQCHIP: {
3844 struct kvm_pic *vpic;
3845
3846 mutex_lock(&kvm->lock);
3847 r = -EEXIST;
3848 if (kvm->arch.vpic)
3849 goto create_irqchip_unlock;
3e515705 3850 r = -EINVAL;
557abc40 3851 if (kvm->created_vcpus)
3e515705 3852 goto create_irqchip_unlock;
1fe779f8 3853 r = -ENOMEM;
3ddea128
MT		 3854 vpic = kvm_create_pic(kvm);
3855 if (vpic) {
1fe779f8
CO		 3856 r = kvm_ioapic_init(kvm);
3857 if (r) {
175504cd 3858 mutex_lock(&kvm->slots_lock);
71ba994c 3859 kvm_destroy_pic(vpic);
175504cd 3860 mutex_unlock(&kvm->slots_lock);
3ddea128 3861 goto create_irqchip_unlock;
1fe779f8
CO		 3862 }
3863 } else
3ddea128 3864 goto create_irqchip_unlock;
399ec807
AK		 3865 r = kvm_setup_default_irq_routing(kvm);
3866 if (r) {
175504cd 3867 mutex_lock(&kvm->slots_lock);
3ddea128 3868 mutex_lock(&kvm->irq_lock);
72bb2fcd 3869 kvm_ioapic_destroy(kvm);
71ba994c 3870 kvm_destroy_pic(vpic);
3ddea128 3871 mutex_unlock(&kvm->irq_lock);
175504cd 3872 mutex_unlock(&kvm->slots_lock);
71ba994c 3873 goto create_irqchip_unlock;
399ec807 3874 }
71ba994c
PB		 3875 /* Write kvm->irq_routing before kvm->arch.vpic. */
3876 smp_wmb();
3877 kvm->arch.vpic = vpic;
3ddea128
MT		 3878 create_irqchip_unlock:
3879 mutex_unlock(&kvm->lock);
1fe779f8 3880 break;
3ddea128 3881 }
7837699f 3882 case KVM_CREATE_PIT:
c5ff41ce
JK		 3883 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3884 goto create_pit;
3885 case KVM_CREATE_PIT2:
3886 r = -EFAULT;
3887 if (copy_from_user(&u.pit_config, argp,
3888 sizeof(struct kvm_pit_config)))
3889 goto out;
3890 create_pit:
250715a6 3891 mutex_lock(&kvm->lock);
269e05e4
AK		 3892 r = -EEXIST;
3893 if (kvm->arch.vpit)
3894 goto create_pit_unlock;
7837699f 3895 r = -ENOMEM;
c5ff41ce 3896 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3897 if (kvm->arch.vpit)
3898 r = 0;
269e05e4 3899 create_pit_unlock:
250715a6 3900 mutex_unlock(&kvm->lock);
7837699f 3901 break;
1fe779f8
CO		 3902 case KVM_GET_IRQCHIP: {
3903 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3904 struct kvm_irqchip *chip;
1fe779f8 3905
ff5c2c03
SL		 3906 chip = memdup_user(argp, sizeof(*chip));
3907 if (IS_ERR(chip)) {
3908 r = PTR_ERR(chip);
1fe779f8 3909 goto out;
ff5c2c03
SL		 3910 }
3911
1fe779f8 3912 r = -ENXIO;
49df6397 3913 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3914 goto get_irqchip_out;
3915 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3916 if (r)
f0d66275 3917 goto get_irqchip_out;
1fe779f8 3918 r = -EFAULT;
f0d66275
DH		 3919 if (copy_to_user(argp, chip, sizeof *chip))
3920 goto get_irqchip_out;
1fe779f8 3921 r = 0;
f0d66275
DH		 3922 get_irqchip_out:
3923 kfree(chip);
1fe779f8
CO		 3924 break;
3925 }
3926 case KVM_SET_IRQCHIP: {
3927 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3928 struct kvm_irqchip *chip;
1fe779f8 3929
ff5c2c03
SL		 3930 chip = memdup_user(argp, sizeof(*chip));
3931 if (IS_ERR(chip)) {
3932 r = PTR_ERR(chip);
1fe779f8 3933 goto out;
ff5c2c03
SL		 3934 }
3935
1fe779f8 3936 r = -ENXIO;
49df6397 3937 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3938 goto set_irqchip_out;
3939 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3940 if (r)
f0d66275 3941 goto set_irqchip_out;
1fe779f8 3942 r = 0;
f0d66275
DH		 3943 set_irqchip_out:
3944 kfree(chip);
1fe779f8
CO		 3945 break;
3946 }
e0f63cb9 3947 case KVM_GET_PIT: {
e0f63cb9 3948 r = -EFAULT;
f0d66275 3949 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3950 goto out;
3951 r = -ENXIO;
3952 if (!kvm->arch.vpit)
3953 goto out;
f0d66275 3954 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3955 if (r)
3956 goto out;
3957 r = -EFAULT;
f0d66275 3958 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3959 goto out;
3960 r = 0;
3961 break;
3962 }
3963 case KVM_SET_PIT: {
e0f63cb9 3964 r = -EFAULT;
f0d66275 3965 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3966 goto out;
3967 r = -ENXIO;
3968 if (!kvm->arch.vpit)
3969 goto out;
f0d66275 3970 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3971 break;
3972 }
e9f42757
BK		 3973 case KVM_GET_PIT2: {
3974 r = -ENXIO;
3975 if (!kvm->arch.vpit)
3976 goto out;
3977 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3978 if (r)
3979 goto out;
3980 r = -EFAULT;
3981 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3982 goto out;
3983 r = 0;
3984 break;
3985 }
3986 case KVM_SET_PIT2: {
3987 r = -EFAULT;
3988 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3989 goto out;
3990 r = -ENXIO;
3991 if (!kvm->arch.vpit)
3992 goto out;
3993 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3994 break;
3995 }
52d939a0
MT		 3996 case KVM_REINJECT_CONTROL: {
3997 struct kvm_reinject_control control;
3998 r = -EFAULT;
3999 if (copy_from_user(&control, argp, sizeof(control)))
4000 goto out;
4001 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4002 break;
4003 }
d71ba788
PB		 4004 case KVM_SET_BOOT_CPU_ID:
4005 r = 0;
4006 mutex_lock(&kvm->lock);
557abc40 4007 if (kvm->created_vcpus)
d71ba788
PB		 4008 r = -EBUSY;
4009 else
4010 kvm->arch.bsp_vcpu_id = arg;
4011 mutex_unlock(&kvm->lock);
4012 break;
ffde22ac
ES		 4013 case KVM_XEN_HVM_CONFIG: {
4014 r = -EFAULT;
4015 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4016 sizeof(struct kvm_xen_hvm_config)))
4017 goto out;
4018 r = -EINVAL;
4019 if (kvm->arch.xen_hvm_config.flags)
4020 goto out;
4021 r = 0;
4022 break;
4023 }
afbcf7ab 4024 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4025 struct kvm_clock_data user_ns;
4026 u64 now_ns;
4027 s64 delta;
4028
4029 r = -EFAULT;
4030 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4031 goto out;
4032
4033 r = -EINVAL;
4034 if (user_ns.flags)
4035 goto out;
4036
4037 r = 0;
395c6b0a 4038 local_irq_disable();
759379dd 4039 now_ns = get_kernel_ns();
afbcf7ab 4040 delta = user_ns.clock - now_ns;
395c6b0a 4041 local_irq_enable();
afbcf7ab 4042 kvm->arch.kvmclock_offset = delta;
2e762ff7 4043 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4044 break;
4045 }
4046 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4047 struct kvm_clock_data user_ns;
4048 u64 now_ns;
4049
395c6b0a 4050 local_irq_disable();
759379dd 4051 now_ns = get_kernel_ns();
afbcf7ab 4052 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4053 local_irq_enable();
afbcf7ab 4054 user_ns.flags = 0;
97e69aa6 4055 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4056
4057 r = -EFAULT;
4058 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4059 goto out;
4060 r = 0;
4061 break;
4062 }
90de4a18
NA		 4063 case KVM_ENABLE_CAP: {
4064 struct kvm_enable_cap cap;
afbcf7ab 4065
90de4a18
NA		 4066 r = -EFAULT;
4067 if (copy_from_user(&cap, argp, sizeof(cap)))
4068 goto out;
4069 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4070 break;
4071 }
1fe779f8 4072 default:
c274e03a 4073 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4074 }
4075out:
4076 return r;
4077}
4078
a16b043c 4079static void kvm_init_msr_list(void)
043405e1
CO		 4080{
4081 u32 dummy[2];
4082 unsigned i, j;
4083
62ef68bb 4084 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4085 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4086 continue;
93c4adc7
PB		 4087
4088 /*
4089 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4090 * to the guests in some cases.
93c4adc7
PB		 4091 */
4092 switch (msrs_to_save[i]) {
4093 case MSR_IA32_BNDCFGS:
4094 if (!kvm_x86_ops->mpx_supported())
4095 continue;
4096 break;
9dbe6cf9
PB		 4097 case MSR_TSC_AUX:
4098 if (!kvm_x86_ops->rdtscp_supported())
4099 continue;
4100 break;
93c4adc7
PB		 4101 default:
4102 break;
4103 }
4104
043405e1
CO		 4105 if (j < i)
4106 msrs_to_save[j] = msrs_to_save[i];
4107 j++;
4108 }
4109 num_msrs_to_save = j;
62ef68bb
PB		 4110
4111 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4112 switch (emulated_msrs[i]) {
6d396b55
PB		 4113 case MSR_IA32_SMBASE:
4114 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4115 continue;
4116 break;
62ef68bb
PB		 4117 default:
4118 break;
4119 }
4120
4121 if (j < i)
4122 emulated_msrs[j] = emulated_msrs[i];
4123 j++;
4124 }
4125 num_emulated_msrs = j;
043405e1
CO		 4126}
4127
bda9020e
MT		 4128static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4129 const void *v)
bbd9b64e 4130{
70252a10
AK		 4131 int handled = 0;
4132 int n;
4133
4134 do {
4135 n = min(len, 8);
bce87cce 4136 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4137 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4138 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4139 break;
4140 handled += n;
4141 addr += n;
4142 len -= n;
4143 v += n;
4144 } while (len);
bbd9b64e 4145
70252a10 4146 return handled;
bbd9b64e
CO		 4147}
4148
bda9020e 4149static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4150{
70252a10
AK		 4151 int handled = 0;
4152 int n;
4153
4154 do {
4155 n = min(len, 8);
bce87cce 4156 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4157 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4158 addr, n, v))
4159 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4160 break;
4161 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4162 handled += n;
4163 addr += n;
4164 len -= n;
4165 v += n;
4166 } while (len);
bbd9b64e 4167
70252a10 4168 return handled;
bbd9b64e
CO		 4169}
4170
2dafc6c2
GN		 4171static void kvm_set_segment(struct kvm_vcpu *vcpu,
4172 struct kvm_segment *var, int seg)
4173{
4174 kvm_x86_ops->set_segment(vcpu, var, seg);
4175}
4176
4177void kvm_get_segment(struct kvm_vcpu *vcpu,
4178 struct kvm_segment *var, int seg)
4179{
4180 kvm_x86_ops->get_segment(vcpu, var, seg);
4181}
4182
54987b7a
PB		 4183gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4184 struct x86_exception *exception)
02f59dc9
JR		 4185{
4186 gpa_t t_gpa;
02f59dc9
JR		 4187
4188 BUG_ON(!mmu_is_nested(vcpu));
4189
4190 /* NPT walks are always user-walks */
4191 access |= PFERR_USER_MASK;
54987b7a 4192 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4193
4194 return t_gpa;
4195}
4196
ab9ae313
AK		 4197gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4198 struct x86_exception *exception)
1871c602
GN		 4199{
4200 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4201 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4202}
4203
ab9ae313
AK		 4204 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4205 struct x86_exception *exception)
1871c602
GN		 4206{
4207 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4208 access |= PFERR_FETCH_MASK;
ab9ae313 4209 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4210}
4211
ab9ae313
AK		 4212gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4213 struct x86_exception *exception)
1871c602
GN		 4214{
4215 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4216 access |= PFERR_WRITE_MASK;
ab9ae313 4217 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4218}
4219
4220/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4221gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4222 struct x86_exception *exception)
1871c602 4223{
ab9ae313 4224 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4225}
4226
4227static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4228 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4229 struct x86_exception *exception)
bbd9b64e
CO		 4230{
4231 void *data = val;
10589a46 4232 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4233
4234 while (bytes) {
14dfe855 4235 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4236 exception);
bbd9b64e 4237 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4238 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4239 int ret;
4240
bcc55cba 4241 if (gpa == UNMAPPED_GVA)
ab9ae313 4242 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4243 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4244 offset, toread);
10589a46 4245 if (ret < 0) {
c3cd7ffa 4246 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4247 goto out;
4248 }
bbd9b64e 4249
77c2002e
IE		 4250 bytes -= toread;
4251 data += toread;
4252 addr += toread;
bbd9b64e 4253 }
10589a46 4254out:
10589a46 4255 return r;
bbd9b64e 4256}
77c2002e 4257
1871c602 4258/* used for instruction fetching */
0f65dd70
AK		 4259static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4260 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4261 struct x86_exception *exception)
1871c602 4262{
0f65dd70 4263 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4264 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4265 unsigned offset;
4266 int ret;
0f65dd70 4267
44583cba
PB		 4268 /* Inline kvm_read_guest_virt_helper for speed. */
4269 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4270 exception);
4271 if (unlikely(gpa == UNMAPPED_GVA))
4272 return X86EMUL_PROPAGATE_FAULT;
4273
4274 offset = addr & (PAGE_SIZE-1);
4275 if (WARN_ON(offset + bytes > PAGE_SIZE))
4276 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4277 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4278 offset, bytes);
44583cba
PB		 4279 if (unlikely(ret < 0))
4280 return X86EMUL_IO_NEEDED;
4281
4282 return X86EMUL_CONTINUE;
1871c602
GN		 4283}
4284
064aea77 4285int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4286 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4287 struct x86_exception *exception)
1871c602 4288{
0f65dd70 4289 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4290 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4291
1871c602 4292 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4293 exception);
1871c602 4294}
064aea77 4295EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4296
0f65dd70
AK		 4297static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4298 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4299 struct x86_exception *exception)
1871c602 4300{
0f65dd70 4301 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4302 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4303}
4304
7a036a6f
RK		 4305static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4306 unsigned long addr, void *val, unsigned int bytes)
4307{
4308 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4309 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4310
4311 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4312}
4313
6a4d7550 4314int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4315 gva_t addr, void *val,
2dafc6c2 4316 unsigned int bytes,
bcc55cba 4317 struct x86_exception *exception)
77c2002e 4318{
0f65dd70 4319 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4320 void *data = val;
4321 int r = X86EMUL_CONTINUE;
4322
4323 while (bytes) {
14dfe855
JR		 4324 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4325 PFERR_WRITE_MASK,
ab9ae313 4326 exception);
77c2002e
IE		 4327 unsigned offset = addr & (PAGE_SIZE-1);
4328 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4329 int ret;
4330
bcc55cba 4331 if (gpa == UNMAPPED_GVA)
ab9ae313 4332 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4333 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4334 if (ret < 0) {
c3cd7ffa 4335 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4336 goto out;
4337 }
4338
4339 bytes -= towrite;
4340 data += towrite;
4341 addr += towrite;
4342 }
4343out:
4344 return r;
4345}
6a4d7550 4346EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4347
af7cc7d1
XG		 4348static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4349 gpa_t *gpa, struct x86_exception *exception,
4350 bool write)
4351{
97d64b78
AK		 4352 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4353 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4354
be94f6b7
HH		 4355 /*
4356 * currently PKRU is only applied to ept enabled guest so
4357 * there is no pkey in EPT page table for L1 guest or EPT
4358 * shadow page table for L2 guest.
4359 */
97d64b78 4360 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4361 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4362 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4363 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4364 (gva & (PAGE_SIZE - 1));
4f022648 4365 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4366 return 1;
4367 }
4368
af7cc7d1
XG		 4369 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4370
4371 if (*gpa == UNMAPPED_GVA)
4372 return -1;
4373
4374 /* For APIC access vmexit */
4375 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4376 return 1;
4377
4f022648
XG		 4378 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4379 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4380 return 1;
4f022648 4381 }
bebb106a 4382
af7cc7d1
XG		 4383 return 0;
4384}
4385
3200f405 4386int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4387 const void *val, int bytes)
bbd9b64e
CO		 4388{
4389 int ret;
4390
54bf36aa 4391 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4392 if (ret < 0)
bbd9b64e 4393 return 0;
0eb05bf2 4394 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4395 return 1;
4396}
4397
77d197b2
XG		 4398struct read_write_emulator_ops {
4399 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4400 int bytes);
4401 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4402 void *val, int bytes);
4403 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4404 int bytes, void *val);
4405 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4406 void *val, int bytes);
4407 bool write;
4408};
4409
4410static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4411{
4412 if (vcpu->mmio_read_completed) {
77d197b2 4413 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4414 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4415 vcpu->mmio_read_completed = 0;
4416 return 1;
4417 }
4418
4419 return 0;
4420}
4421
4422static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4423 void *val, int bytes)
4424{
54bf36aa 4425 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4426}
4427
4428static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4429 void *val, int bytes)
4430{
4431 return emulator_write_phys(vcpu, gpa, val, bytes);
4432}
4433
4434static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4435{
4436 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4437 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4438}
4439
4440static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4441 void *val, int bytes)
4442{
4443 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4444 return X86EMUL_IO_NEEDED;
4445}
4446
4447static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4448 void *val, int bytes)
4449{
f78146b0
AK		 4450 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4451
87da7e66 4452 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4453 return X86EMUL_CONTINUE;
4454}
4455
0fbe9b0b 4456static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4457 .read_write_prepare = read_prepare,
4458 .read_write_emulate = read_emulate,
4459 .read_write_mmio = vcpu_mmio_read,
4460 .read_write_exit_mmio = read_exit_mmio,
4461};
4462
0fbe9b0b 4463static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4464 .read_write_emulate = write_emulate,
4465 .read_write_mmio = write_mmio,
4466 .read_write_exit_mmio = write_exit_mmio,
4467 .write = true,
4468};
4469
22388a3c
XG		 4470static int emulator_read_write_onepage(unsigned long addr, void *val,
4471 unsigned int bytes,
4472 struct x86_exception *exception,
4473 struct kvm_vcpu *vcpu,
0fbe9b0b 4474 const struct read_write_emulator_ops *ops)
bbd9b64e 4475{
af7cc7d1
XG		 4476 gpa_t gpa;
4477 int handled, ret;
22388a3c 4478 bool write = ops->write;
f78146b0 4479 struct kvm_mmio_fragment *frag;
10589a46 4480
22388a3c 4481 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4482
af7cc7d1 4483 if (ret < 0)
bbd9b64e 4484 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4485
4486 /* For APIC access vmexit */
af7cc7d1 4487 if (ret)
bbd9b64e
CO		 4488 goto mmio;
4489
22388a3c 4490 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4491 return X86EMUL_CONTINUE;
4492
4493mmio:
4494 /*
4495 * Is this MMIO handled locally?
4496 */
22388a3c 4497 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4498 if (handled == bytes)
bbd9b64e 4499 return X86EMUL_CONTINUE;
bbd9b64e 4500
70252a10
AK		 4501 gpa += handled;
4502 bytes -= handled;
4503 val += handled;
4504
87da7e66
XG		 4505 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4506 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4507 frag->gpa = gpa;
4508 frag->data = val;
4509 frag->len = bytes;
f78146b0 4510 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4511}
4512
52eb5a6d
XL		 4513static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4514 unsigned long addr,
22388a3c
XG		 4515 void *val, unsigned int bytes,
4516 struct x86_exception *exception,
0fbe9b0b 4517 const struct read_write_emulator_ops *ops)
bbd9b64e 4518{
0f65dd70 4519 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4520 gpa_t gpa;
4521 int rc;
4522
4523 if (ops->read_write_prepare &&
4524 ops->read_write_prepare(vcpu, val, bytes))
4525 return X86EMUL_CONTINUE;
4526
4527 vcpu->mmio_nr_fragments = 0;
0f65dd70 4528
bbd9b64e
CO		 4529 /* Crossing a page boundary? */
4530 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4531 int now;
bbd9b64e
CO		 4532
4533 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4534 rc = emulator_read_write_onepage(addr, val, now, exception,
4535 vcpu, ops);
4536
bbd9b64e
CO		 4537 if (rc != X86EMUL_CONTINUE)
4538 return rc;
4539 addr += now;
bac15531
NA		 4540 if (ctxt->mode != X86EMUL_MODE_PROT64)
4541 addr = (u32)addr;
bbd9b64e
CO		 4542 val += now;
4543 bytes -= now;
4544 }
22388a3c 4545
f78146b0
AK		 4546 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4547 vcpu, ops);
4548 if (rc != X86EMUL_CONTINUE)
4549 return rc;
4550
4551 if (!vcpu->mmio_nr_fragments)
4552 return rc;
4553
4554 gpa = vcpu->mmio_fragments[0].gpa;
4555
4556 vcpu->mmio_needed = 1;
4557 vcpu->mmio_cur_fragment = 0;
4558
87da7e66 4559 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4560 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4561 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4562 vcpu->run->mmio.phys_addr = gpa;
4563
4564 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4565}
4566
4567static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4568 unsigned long addr,
4569 void *val,
4570 unsigned int bytes,
4571 struct x86_exception *exception)
4572{
4573 return emulator_read_write(ctxt, addr, val, bytes,
4574 exception, &read_emultor);
4575}
4576
52eb5a6d 4577static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4578 unsigned long addr,
4579 const void *val,
4580 unsigned int bytes,
4581 struct x86_exception *exception)
4582{
4583 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4584 exception, &write_emultor);
bbd9b64e 4585}
bbd9b64e 4586
daea3e73
AK		 4587#define CMPXCHG_TYPE(t, ptr, old, new) \
4588 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4589
4590#ifdef CONFIG_X86_64
4591# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4592#else
4593# define CMPXCHG64(ptr, old, new) \
9749a6c0 4594 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4595#endif
4596
0f65dd70
AK		 4597static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4598 unsigned long addr,
bbd9b64e
CO		 4599 const void *old,
4600 const void *new,
4601 unsigned int bytes,
0f65dd70 4602 struct x86_exception *exception)
bbd9b64e 4603{
0f65dd70 4604 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4605 gpa_t gpa;
4606 struct page *page;
4607 char *kaddr;
4608 bool exchanged;
2bacc55c 4609
daea3e73
AK		 4610 /* guests cmpxchg8b have to be emulated atomically */
4611 if (bytes > 8 || (bytes & (bytes - 1)))
4612 goto emul_write;
10589a46 4613
daea3e73 4614 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4615
daea3e73
AK		 4616 if (gpa == UNMAPPED_GVA ||
4617 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4618 goto emul_write;
2bacc55c 4619
daea3e73
AK		 4620 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4621 goto emul_write;
72dc67a6 4622
54bf36aa 4623 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4624 if (is_error_page(page))
c19b8bd6 4625 goto emul_write;
72dc67a6 4626
8fd75e12 4627 kaddr = kmap_atomic(page);
daea3e73
AK		 4628 kaddr += offset_in_page(gpa);
4629 switch (bytes) {
4630 case 1:
4631 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4632 break;
4633 case 2:
4634 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4635 break;
4636 case 4:
4637 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4638 break;
4639 case 8:
4640 exchanged = CMPXCHG64(kaddr, old, new);
4641 break;
4642 default:
4643 BUG();
2bacc55c 4644 }
8fd75e12 4645 kunmap_atomic(kaddr);
daea3e73
AK		 4646 kvm_release_page_dirty(page);
4647
4648 if (!exchanged)
4649 return X86EMUL_CMPXCHG_FAILED;
4650
54bf36aa 4651 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4652 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4653
4654 return X86EMUL_CONTINUE;
4a5f48f6 4655
3200f405 4656emul_write:
daea3e73 4657 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4658
0f65dd70 4659 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4660}
4661
cf8f70bf
GN		 4662static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4663{
4664 /* TODO: String I/O for in kernel device */
4665 int r;
4666
4667 if (vcpu->arch.pio.in)
e32edf4f 4668 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4669 vcpu->arch.pio.size, pd);
4670 else
e32edf4f 4671 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4672 vcpu->arch.pio.port, vcpu->arch.pio.size,
4673 pd);
4674 return r;
4675}
4676
6f6fbe98
XG		 4677static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4678 unsigned short port, void *val,
4679 unsigned int count, bool in)
cf8f70bf 4680{
cf8f70bf 4681 vcpu->arch.pio.port = port;
6f6fbe98 4682 vcpu->arch.pio.in = in;
7972995b 4683 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4684 vcpu->arch.pio.size = size;
4685
4686 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4687 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4688 return 1;
4689 }
4690
4691 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4692 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4693 vcpu->run->io.size = size;
4694 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4695 vcpu->run->io.count = count;
4696 vcpu->run->io.port = port;
4697
4698 return 0;
4699}
4700
6f6fbe98
XG		 4701static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4702 int size, unsigned short port, void *val,
4703 unsigned int count)
cf8f70bf 4704{
ca1d4a9e 4705 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4706 int ret;
ca1d4a9e 4707
6f6fbe98
XG		 4708 if (vcpu->arch.pio.count)
4709 goto data_avail;
cf8f70bf 4710
6f6fbe98
XG		 4711 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4712 if (ret) {
4713data_avail:
4714 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4715 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4716 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4717 return 1;
4718 }
4719
cf8f70bf
GN		 4720 return 0;
4721}
4722
6f6fbe98
XG		 4723static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4724 int size, unsigned short port,
4725 const void *val, unsigned int count)
4726{
4727 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4728
4729 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4730 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4731 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4732}
4733
bbd9b64e
CO		 4734static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4735{
4736 return kvm_x86_ops->get_segment_base(vcpu, seg);
4737}
4738
3cb16fe7 4739static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4740{
3cb16fe7 4741 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4742}
4743
5cb56059 4744int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4745{
4746 if (!need_emulate_wbinvd(vcpu))
4747 return X86EMUL_CONTINUE;
4748
4749 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4750 int cpu = get_cpu();
4751
4752 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4753 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4754 wbinvd_ipi, NULL, 1);
2eec7343 4755 put_cpu();
f5f48ee1 4756 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4757 } else
4758 wbinvd();
f5f48ee1
SY		 4759 return X86EMUL_CONTINUE;
4760}
5cb56059
JS		 4761
4762int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4763{
4764 kvm_x86_ops->skip_emulated_instruction(vcpu);
4765 return kvm_emulate_wbinvd_noskip(vcpu);
4766}
f5f48ee1
SY		 4767EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4768
5cb56059
JS		 4769
4770
bcaf5cc5
AK		 4771static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4772{
5cb56059 4773 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4774}
4775
52eb5a6d
XL		 4776static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4777 unsigned long *dest)
bbd9b64e 4778{
16f8a6f9 4779 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4780}
4781
52eb5a6d
XL		 4782static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4783 unsigned long value)
bbd9b64e 4784{
338dbc97 4785
717746e3 4786 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4787}
4788
52a46617 4789static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4790{
52a46617 4791 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4792}
4793
717746e3 4794static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4795{
717746e3 4796 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4797 unsigned long value;
4798
4799 switch (cr) {
4800 case 0:
4801 value = kvm_read_cr0(vcpu);
4802 break;
4803 case 2:
4804 value = vcpu->arch.cr2;
4805 break;
4806 case 3:
9f8fe504 4807 value = kvm_read_cr3(vcpu);
52a46617
GN		 4808 break;
4809 case 4:
4810 value = kvm_read_cr4(vcpu);
4811 break;
4812 case 8:
4813 value = kvm_get_cr8(vcpu);
4814 break;
4815 default:
a737f256 4816 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4817 return 0;
4818 }
4819
4820 return value;
4821}
4822
717746e3 4823static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4824{
717746e3 4825 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4826 int res = 0;
4827
52a46617
GN		 4828 switch (cr) {
4829 case 0:
49a9b07e 4830 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4831 break;
4832 case 2:
4833 vcpu->arch.cr2 = val;
4834 break;
4835 case 3:
2390218b 4836 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4837 break;
4838 case 4:
a83b29c6 4839 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4840 break;
4841 case 8:
eea1cff9 4842 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4843 break;
4844 default:
a737f256 4845 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4846 res = -1;
52a46617 4847 }
0f12244f
GN		 4848
4849 return res;
52a46617
GN		 4850}
4851
717746e3 4852static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4853{
717746e3 4854 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4855}
4856
4bff1e86 4857static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4858{
4bff1e86 4859 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4860}
4861
4bff1e86 4862static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4863{
4bff1e86 4864 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4865}
4866
1ac9d0cf
AK		 4867static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4868{
4869 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4870}
4871
4872static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4873{
4874 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4875}
4876
4bff1e86
AK		 4877static unsigned long emulator_get_cached_segment_base(
4878 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4879{
4bff1e86 4880 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4881}
4882
1aa36616
AK		 4883static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4884 struct desc_struct *desc, u32 *base3,
4885 int seg)
2dafc6c2
GN		 4886{
4887 struct kvm_segment var;
4888
4bff1e86 4889 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4890 *selector = var.selector;
2dafc6c2 4891
378a8b09
GN		 4892 if (var.unusable) {
4893 memset(desc, 0, sizeof(*desc));
2dafc6c2 4894 return false;
378a8b09 4895 }
2dafc6c2
GN		 4896
4897 if (var.g)
4898 var.limit >>= 12;
4899 set_desc_limit(desc, var.limit);
4900 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4901#ifdef CONFIG_X86_64
4902 if (base3)
4903 *base3 = var.base >> 32;
4904#endif
2dafc6c2
GN		 4905 desc->type = var.type;
4906 desc->s = var.s;
4907 desc->dpl = var.dpl;
4908 desc->p = var.present;
4909 desc->avl = var.avl;
4910 desc->l = var.l;
4911 desc->d = var.db;
4912 desc->g = var.g;
4913
4914 return true;
4915}
4916
1aa36616
AK		 4917static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4918 struct desc_struct *desc, u32 base3,
4919 int seg)
2dafc6c2 4920{
4bff1e86 4921 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4922 struct kvm_segment var;
4923
1aa36616 4924 var.selector = selector;
2dafc6c2 4925 var.base = get_desc_base(desc);
5601d05b
GN		 4926#ifdef CONFIG_X86_64
4927 var.base |= ((u64)base3) << 32;
4928#endif
2dafc6c2
GN		 4929 var.limit = get_desc_limit(desc);
4930 if (desc->g)
4931 var.limit = (var.limit << 12) | 0xfff;
4932 var.type = desc->type;
2dafc6c2
GN		 4933 var.dpl = desc->dpl;
4934 var.db = desc->d;
4935 var.s = desc->s;
4936 var.l = desc->l;
4937 var.g = desc->g;
4938 var.avl = desc->avl;
4939 var.present = desc->p;
4940 var.unusable = !var.present;
4941 var.padding = 0;
4942
4943 kvm_set_segment(vcpu, &var, seg);
4944 return;
4945}
4946
717746e3
AK		 4947static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4948 u32 msr_index, u64 *pdata)
4949{
609e36d3
PB		 4950 struct msr_data msr;
4951 int r;
4952
4953 msr.index = msr_index;
4954 msr.host_initiated = false;
4955 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4956 if (r)
4957 return r;
4958
4959 *pdata = msr.data;
4960 return 0;
717746e3
AK		 4961}
4962
4963static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4964 u32 msr_index, u64 data)
4965{
8fe8ab46
WA		 4966 struct msr_data msr;
4967
4968 msr.data = data;
4969 msr.index = msr_index;
4970 msr.host_initiated = false;
4971 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4972}
4973
64d60670
PB		 4974static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4975{
4976 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4977
4978 return vcpu->arch.smbase;
4979}
4980
4981static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4982{
4983 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4984
4985 vcpu->arch.smbase = smbase;
4986}
4987
67f4d428
NA		 4988static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4989 u32 pmc)
4990{
c6702c9d 4991 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4992}
4993
222d21aa
AK		 4994static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4995 u32 pmc, u64 *pdata)
4996{
c6702c9d 4997 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4998}
4999
6c3287f7
AK		 5000static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5001{
5002 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5003}
5004
5037f6f3
AK		 5005static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5006{
5007 preempt_disable();
5197b808 5008 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5009 /*
5010 * CR0.TS may reference the host fpu state, not the guest fpu state,
5011 * so it may be clear at this point.
5012 */
5013 clts();
5014}
5015
5016static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5017{
5018 preempt_enable();
5019}
5020
2953538e 5021static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5022 struct x86_instruction_info *info,
c4f035c6
AK		 5023 enum x86_intercept_stage stage)
5024{
2953538e 5025 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5026}
5027
0017f93a 5028static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5029 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5030{
0017f93a 5031 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5032}
5033
dd856efa
AK		 5034static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5035{
5036 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5037}
5038
5039static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5040{
5041 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5042}
5043
801806d9
NA		 5044static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5045{
5046 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5047}
5048
0225fb50 5049static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5050 .read_gpr = emulator_read_gpr,
5051 .write_gpr = emulator_write_gpr,
1871c602 5052 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5053 .write_std = kvm_write_guest_virt_system,
7a036a6f 5054 .read_phys = kvm_read_guest_phys_system,
1871c602 5055 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5056 .read_emulated = emulator_read_emulated,
5057 .write_emulated = emulator_write_emulated,
5058 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5059 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5060 .pio_in_emulated = emulator_pio_in_emulated,
5061 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5062 .get_segment = emulator_get_segment,
5063 .set_segment = emulator_set_segment,
5951c442 5064 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5065 .get_gdt = emulator_get_gdt,
160ce1f1 5066 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5067 .set_gdt = emulator_set_gdt,
5068 .set_idt = emulator_set_idt,
52a46617
GN		 5069 .get_cr = emulator_get_cr,
5070 .set_cr = emulator_set_cr,
9c537244 5071 .cpl = emulator_get_cpl,
35aa5375
GN		 5072 .get_dr = emulator_get_dr,
5073 .set_dr = emulator_set_dr,
64d60670
PB		 5074 .get_smbase = emulator_get_smbase,
5075 .set_smbase = emulator_set_smbase,
717746e3
AK		 5076 .set_msr = emulator_set_msr,
5077 .get_msr = emulator_get_msr,
67f4d428 5078 .check_pmc = emulator_check_pmc,
222d21aa 5079 .read_pmc = emulator_read_pmc,
6c3287f7 5080 .halt = emulator_halt,
bcaf5cc5 5081 .wbinvd = emulator_wbinvd,
d6aa1000 5082 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5083 .get_fpu = emulator_get_fpu,
5084 .put_fpu = emulator_put_fpu,
c4f035c6 5085 .intercept = emulator_intercept,
bdb42f5a 5086 .get_cpuid = emulator_get_cpuid,
801806d9 5087 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5088};
5089
95cb2295
GN		 5090static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5091{
37ccdcbe 5092 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5093 /*
5094 * an sti; sti; sequence only disable interrupts for the first
5095 * instruction. So, if the last instruction, be it emulated or
5096 * not, left the system with the INT_STI flag enabled, it
5097 * means that the last instruction is an sti. We should not
5098 * leave the flag on in this case. The same goes for mov ss
5099 */
37ccdcbe
PB		 5100 if (int_shadow & mask)
5101 mask = 0;
6addfc42 5102 if (unlikely(int_shadow || mask)) {
95cb2295 5103 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5104 if (!mask)
5105 kvm_make_request(KVM_REQ_EVENT, vcpu);
5106 }
95cb2295
GN		 5107}
5108
ef54bcfe 5109static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5110{
5111 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5112 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5113 return kvm_propagate_fault(vcpu, &ctxt->exception);
5114
5115 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5116 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5117 ctxt->exception.error_code);
54b8486f 5118 else
da9cb575 5119 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5120 return false;
54b8486f
GN		 5121}
5122
8ec4722d
MG		 5123static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5124{
adf52235 5125 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5126 int cs_db, cs_l;
5127
8ec4722d
MG		 5128 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5129
adf52235
TY		 5130 ctxt->eflags = kvm_get_rflags(vcpu);
5131 ctxt->eip = kvm_rip_read(vcpu);
5132 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5133 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5134 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5135 cs_db ? X86EMUL_MODE_PROT32 :
5136 X86EMUL_MODE_PROT16;
a584539b 5137 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5138 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5139 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5140 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5141
dd856efa 5142 init_decode_cache(ctxt);
7ae441ea 5143 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5144}
5145
71f9833b 5146int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5147{
9d74191a 5148 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5149 int ret;
5150
5151 init_emulate_ctxt(vcpu);
5152
9dac77fa
AK		 5153 ctxt->op_bytes = 2;
5154 ctxt->ad_bytes = 2;
5155 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5156 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5157
5158 if (ret != X86EMUL_CONTINUE)
5159 return EMULATE_FAIL;
5160
9dac77fa 5161 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5162 kvm_rip_write(vcpu, ctxt->eip);
5163 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5164
5165 if (irq == NMI_VECTOR)
7460fb4a 5166 vcpu->arch.nmi_pending = 0;
63995653
MG		 5167 else
5168 vcpu->arch.interrupt.pending = false;
5169
5170 return EMULATE_DONE;
5171}
5172EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5173
6d77dbfc
GN		 5174static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5175{
fc3a9157
JR		 5176 int r = EMULATE_DONE;
5177
6d77dbfc
GN		 5178 ++vcpu->stat.insn_emulation_fail;
5179 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5180 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5181 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5182 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5183 vcpu->run->internal.ndata = 0;
5184 r = EMULATE_FAIL;
5185 }
6d77dbfc 5186 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5187
5188 return r;
6d77dbfc
GN		 5189}
5190
93c05d3e 5191static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5192 bool write_fault_to_shadow_pgtable,
5193 int emulation_type)
a6f177ef 5194{
95b3cf69 5195 gpa_t gpa = cr2;
ba049e93 5196 kvm_pfn_t pfn;
a6f177ef 5197
991eebf9
GN		 5198 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5199 return false;
5200
95b3cf69
XG		 5201 if (!vcpu->arch.mmu.direct_map) {
5202 /*
5203 * Write permission should be allowed since only
5204 * write access need to be emulated.
5205 */
5206 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5207
95b3cf69
XG		 5208 /*
5209 * If the mapping is invalid in guest, let cpu retry
5210 * it to generate fault.
5211 */
5212 if (gpa == UNMAPPED_GVA)
5213 return true;
5214 }
a6f177ef 5215
8e3d9d06
XG		 5216 /*
5217 * Do not retry the unhandleable instruction if it faults on the
5218 * readonly host memory, otherwise it will goto a infinite loop:
5219 * retry instruction -> write #PF -> emulation fail -> retry
5220 * instruction -> ...
5221 */
5222 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5223
5224 /*
5225 * If the instruction failed on the error pfn, it can not be fixed,
5226 * report the error to userspace.
5227 */
5228 if (is_error_noslot_pfn(pfn))
5229 return false;
5230
5231 kvm_release_pfn_clean(pfn);
5232
5233 /* The instructions are well-emulated on direct mmu. */
5234 if (vcpu->arch.mmu.direct_map) {
5235 unsigned int indirect_shadow_pages;
5236
5237 spin_lock(&vcpu->kvm->mmu_lock);
5238 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5239 spin_unlock(&vcpu->kvm->mmu_lock);
5240
5241 if (indirect_shadow_pages)
5242 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5243
a6f177ef 5244 return true;
8e3d9d06 5245 }
a6f177ef 5246
95b3cf69
XG		 5247 /*
5248 * if emulation was due to access to shadowed page table
5249 * and it failed try to unshadow page and re-enter the
5250 * guest to let CPU execute the instruction.
5251 */
5252 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5253
5254 /*
5255 * If the access faults on its page table, it can not
5256 * be fixed by unprotecting shadow page and it should
5257 * be reported to userspace.
5258 */
5259 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5260}
5261
1cb3f3ae
XG		 5262static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5263 unsigned long cr2, int emulation_type)
5264{
5265 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5266 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5267
5268 last_retry_eip = vcpu->arch.last_retry_eip;
5269 last_retry_addr = vcpu->arch.last_retry_addr;
5270
5271 /*
5272 * If the emulation is caused by #PF and it is non-page_table
5273 * writing instruction, it means the VM-EXIT is caused by shadow
5274 * page protected, we can zap the shadow page and retry this
5275 * instruction directly.
5276 *
5277 * Note: if the guest uses a non-page-table modifying instruction
5278 * on the PDE that points to the instruction, then we will unmap
5279 * the instruction and go to an infinite loop. So, we cache the
5280 * last retried eip and the last fault address, if we meet the eip
5281 * and the address again, we can break out of the potential infinite
5282 * loop.
5283 */
5284 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5285
5286 if (!(emulation_type & EMULTYPE_RETRY))
5287 return false;
5288
5289 if (x86_page_table_writing_insn(ctxt))
5290 return false;
5291
5292 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5293 return false;
5294
5295 vcpu->arch.last_retry_eip = ctxt->eip;
5296 vcpu->arch.last_retry_addr = cr2;
5297
5298 if (!vcpu->arch.mmu.direct_map)
5299 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5300
22368028 5301 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5302
5303 return true;
5304}
5305
716d51ab
GN		 5306static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5307static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5308
64d60670 5309static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5310{
64d60670 5311 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5312 /* This is a good place to trace that we are exiting SMM. */
5313 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5314
c43203ca
PB		 5315 /* Process a latched INIT or SMI, if any. */
5316 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5317 }
699023e2
PB		 5318
5319 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5320}
5321
5322static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5323{
5324 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5325
a584539b 5326 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5327
5328 if (changed & HF_SMM_MASK)
5329 kvm_smm_changed(vcpu);
a584539b
PB		 5330}
5331
4a1e10d5
PB		 5332static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5333 unsigned long *db)
5334{
5335 u32 dr6 = 0;
5336 int i;
5337 u32 enable, rwlen;
5338
5339 enable = dr7;
5340 rwlen = dr7 >> 16;
5341 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5342 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5343 dr6 |= (1 << i);
5344 return dr6;
5345}
5346
6addfc42 5347static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5348{
5349 struct kvm_run *kvm_run = vcpu->run;
5350
5351 /*
6addfc42
PB		 5352 * rflags is the old, "raw" value of the flags. The new value has
5353 * not been saved yet.
663f4c61
PB		 5354 *
5355 * This is correct even for TF set by the guest, because "the
5356 * processor will not generate this exception after the instruction
5357 * that sets the TF flag".
5358 */
663f4c61
PB		 5359 if (unlikely(rflags & X86_EFLAGS_TF)) {
5360 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5361 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5362 DR6_RTM;
663f4c61
PB		 5363 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5364 kvm_run->debug.arch.exception = DB_VECTOR;
5365 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5366 *r = EMULATE_USER_EXIT;
5367 } else {
5368 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5369 /*
5370 * "Certain debug exceptions may clear bit 0-3. The
5371 * remaining contents of the DR6 register are never
5372 * cleared by the processor".
5373 */
5374 vcpu->arch.dr6 &= ~15;
6f43ed01 5375 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5376 kvm_queue_exception(vcpu, DB_VECTOR);
5377 }
5378 }
5379}
5380
4a1e10d5
PB		 5381static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5382{
4a1e10d5
PB		 5383 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5384 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5385 struct kvm_run *kvm_run = vcpu->run;
5386 unsigned long eip = kvm_get_linear_rip(vcpu);
5387 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5388 vcpu->arch.guest_debug_dr7,
5389 vcpu->arch.eff_db);
5390
5391 if (dr6 != 0) {
6f43ed01 5392 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5393 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5394 kvm_run->debug.arch.exception = DB_VECTOR;
5395 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5396 *r = EMULATE_USER_EXIT;
5397 return true;
5398 }
5399 }
5400
4161a569
NA		 5401 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5402 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5403 unsigned long eip = kvm_get_linear_rip(vcpu);
5404 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5405 vcpu->arch.dr7,
5406 vcpu->arch.db);
5407
5408 if (dr6 != 0) {
5409 vcpu->arch.dr6 &= ~15;
6f43ed01 5410 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5411 kvm_queue_exception(vcpu, DB_VECTOR);
5412 *r = EMULATE_DONE;
5413 return true;
5414 }
5415 }
5416
5417 return false;
5418}
5419
51d8b661
AP		 5420int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5421 unsigned long cr2,
dc25e89e
AP		 5422 int emulation_type,
5423 void *insn,
5424 int insn_len)
bbd9b64e 5425{
95cb2295 5426 int r;
9d74191a 5427 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5428 bool writeback = true;
93c05d3e 5429 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5430
93c05d3e
XG		 5431 /*
5432 * Clear write_fault_to_shadow_pgtable here to ensure it is
5433 * never reused.
5434 */
5435 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5436 kvm_clear_exception_queue(vcpu);
8d7d8102 5437
571008da 5438 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5439 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5440
5441 /*
5442 * We will reenter on the same instruction since
5443 * we do not set complete_userspace_io. This does not
5444 * handle watchpoints yet, those would be handled in
5445 * the emulate_ops.
5446 */
5447 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5448 return r;
5449
9d74191a
TY		 5450 ctxt->interruptibility = 0;
5451 ctxt->have_exception = false;
e0ad0b47 5452 ctxt->exception.vector = -1;
9d74191a 5453 ctxt->perm_ok = false;
bbd9b64e 5454
b51e974f 5455 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5456
9d74191a 5457 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5458
e46479f8 5459 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5460 ++vcpu->stat.insn_emulation;
1d2887e2 5461 if (r != EMULATION_OK) {
4005996e
AK		 5462 if (emulation_type & EMULTYPE_TRAP_UD)
5463 return EMULATE_FAIL;
991eebf9
GN		 5464 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5465 emulation_type))
bbd9b64e 5466 return EMULATE_DONE;
6d77dbfc
GN		 5467 if (emulation_type & EMULTYPE_SKIP)
5468 return EMULATE_FAIL;
5469 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5470 }
5471 }
5472
ba8afb6b 5473 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5474 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5475 if (ctxt->eflags & X86_EFLAGS_RF)
5476 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5477 return EMULATE_DONE;
5478 }
5479
1cb3f3ae
XG		 5480 if (retry_instruction(ctxt, cr2, emulation_type))
5481 return EMULATE_DONE;
5482
7ae441ea 5483 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5484 changes registers values during IO operation */
7ae441ea
GN		 5485 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5486 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5487 emulator_invalidate_register_cache(ctxt);
7ae441ea 5488 }
4d2179e1 5489
5cd21917 5490restart:
9d74191a 5491 r = x86_emulate_insn(ctxt);
bbd9b64e 5492
775fde86
JR		 5493 if (r == EMULATION_INTERCEPTED)
5494 return EMULATE_DONE;
5495
d2ddd1c4 5496 if (r == EMULATION_FAILED) {
991eebf9
GN		 5497 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5498 emulation_type))
c3cd7ffa
GN		 5499 return EMULATE_DONE;
5500
6d77dbfc 5501 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5502 }
5503
9d74191a 5504 if (ctxt->have_exception) {
d2ddd1c4 5505 r = EMULATE_DONE;
ef54bcfe
PB		 5506 if (inject_emulated_exception(vcpu))
5507 return r;
d2ddd1c4 5508 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5509 if (!vcpu->arch.pio.in) {
5510 /* FIXME: return into emulator if single-stepping. */
3457e419 5511 vcpu->arch.pio.count = 0;
0912c977 5512 } else {
7ae441ea 5513 writeback = false;
716d51ab
GN		 5514 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5515 }
ac0a48c3 5516 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5517 } else if (vcpu->mmio_needed) {
5518 if (!vcpu->mmio_is_write)
5519 writeback = false;
ac0a48c3 5520 r = EMULATE_USER_EXIT;
716d51ab 5521 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5522 } else if (r == EMULATION_RESTART)
5cd21917 5523 goto restart;
d2ddd1c4
GN		 5524 else
5525 r = EMULATE_DONE;
f850e2e6 5526
7ae441ea 5527 if (writeback) {
6addfc42 5528 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5529 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5530 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5531 if (vcpu->arch.hflags != ctxt->emul_flags)
5532 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5533 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5534 if (r == EMULATE_DONE)
6addfc42 5535 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5536 if (!ctxt->have_exception ||
5537 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5538 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5539
5540 /*
5541 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5542 * do nothing, and it will be requested again as soon as
5543 * the shadow expires. But we still need to check here,
5544 * because POPF has no interrupt shadow.
5545 */
5546 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5547 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5548 } else
5549 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5550
5551 return r;
de7d789a 5552}
51d8b661 5553EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5554
cf8f70bf 5555int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5556{
cf8f70bf 5557 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5558 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5559 size, port, &val, 1);
cf8f70bf 5560 /* do not return to emulator after return from userspace */
7972995b 5561 vcpu->arch.pio.count = 0;
de7d789a
CO		 5562 return ret;
5563}
cf8f70bf 5564EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5565
8cfdc000
ZA		 5566static void tsc_bad(void *info)
5567{
0a3aee0d 5568 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5569}
5570
5571static void tsc_khz_changed(void *data)
c8076604 5572{
8cfdc000
ZA		 5573 struct cpufreq_freqs *freq = data;
5574 unsigned long khz = 0;
5575
5576 if (data)
5577 khz = freq->new;
5578 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5579 khz = cpufreq_quick_get(raw_smp_processor_id());
5580 if (!khz)
5581 khz = tsc_khz;
0a3aee0d 5582 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5583}
5584
c8076604
GH		 5585static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5586 void *data)
5587{
5588 struct cpufreq_freqs *freq = data;
5589 struct kvm *kvm;
5590 struct kvm_vcpu *vcpu;
5591 int i, send_ipi = 0;
5592
8cfdc000
ZA		 5593 /*
5594 * We allow guests to temporarily run on slowing clocks,
5595 * provided we notify them after, or to run on accelerating
5596 * clocks, provided we notify them before. Thus time never
5597 * goes backwards.
5598 *
5599 * However, we have a problem. We can't atomically update
5600 * the frequency of a given CPU from this function; it is
5601 * merely a notifier, which can be called from any CPU.
5602 * Changing the TSC frequency at arbitrary points in time
5603 * requires a recomputation of local variables related to
5604 * the TSC for each VCPU. We must flag these local variables
5605 * to be updated and be sure the update takes place with the
5606 * new frequency before any guests proceed.
5607 *
5608 * Unfortunately, the combination of hotplug CPU and frequency
5609 * change creates an intractable locking scenario; the order
5610 * of when these callouts happen is undefined with respect to
5611 * CPU hotplug, and they can race with each other. As such,
5612 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5613 * undefined; you can actually have a CPU frequency change take
5614 * place in between the computation of X and the setting of the
5615 * variable. To protect against this problem, all updates of
5616 * the per_cpu tsc_khz variable are done in an interrupt
5617 * protected IPI, and all callers wishing to update the value
5618 * must wait for a synchronous IPI to complete (which is trivial
5619 * if the caller is on the CPU already). This establishes the
5620 * necessary total order on variable updates.
5621 *
5622 * Note that because a guest time update may take place
5623 * anytime after the setting of the VCPU's request bit, the
5624 * correct TSC value must be set before the request. However,
5625 * to ensure the update actually makes it to any guest which
5626 * starts running in hardware virtualization between the set
5627 * and the acquisition of the spinlock, we must also ping the
5628 * CPU after setting the request bit.
5629 *
5630 */
5631
c8076604
GH		 5632 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5633 return 0;
5634 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5635 return 0;
8cfdc000
ZA		 5636
5637 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5638
2f303b74 5639 spin_lock(&kvm_lock);
c8076604 5640 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5641 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5642 if (vcpu->cpu != freq->cpu)
5643 continue;
c285545f 5644 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5645 if (vcpu->cpu != smp_processor_id())
8cfdc000 5646 send_ipi = 1;
c8076604
GH		 5647 }
5648 }
2f303b74 5649 spin_unlock(&kvm_lock);
c8076604
GH		 5650
5651 if (freq->old < freq->new && send_ipi) {
5652 /*
5653 * We upscale the frequency. Must make the guest
5654 * doesn't see old kvmclock values while running with
5655 * the new frequency, otherwise we risk the guest sees
5656 * time go backwards.
5657 *
5658 * In case we update the frequency for another cpu
5659 * (which might be in guest context) send an interrupt
5660 * to kick the cpu out of guest context. Next time
5661 * guest context is entered kvmclock will be updated,
5662 * so the guest will not see stale values.
5663 */
8cfdc000 5664 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5665 }
5666 return 0;
5667}
5668
5669static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5670 .notifier_call = kvmclock_cpufreq_notifier
5671};
5672
5673static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5674 unsigned long action, void *hcpu)
5675{
5676 unsigned int cpu = (unsigned long)hcpu;
5677
5678 switch (action) {
5679 case CPU_ONLINE:
5680 case CPU_DOWN_FAILED:
5681 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5682 break;
5683 case CPU_DOWN_PREPARE:
5684 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5685 break;
5686 }
5687 return NOTIFY_OK;
5688}
5689
5690static struct notifier_block kvmclock_cpu_notifier_block = {
5691 .notifier_call = kvmclock_cpu_notifier,
5692 .priority = -INT_MAX
c8076604
GH		 5693};
5694
b820cc0c
ZA		 5695static void kvm_timer_init(void)
5696{
5697 int cpu;
5698
c285545f 5699 max_tsc_khz = tsc_khz;
460dd42e
SB		 5700
5701 cpu_notifier_register_begin();
b820cc0c 5702 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5703#ifdef CONFIG_CPU_FREQ
5704 struct cpufreq_policy policy;
5705 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5706 cpu = get_cpu();
5707 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5708 if (policy.cpuinfo.max_freq)
5709 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5710 put_cpu();
c285545f 5711#endif
b820cc0c
ZA		 5712 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5713 CPUFREQ_TRANSITION_NOTIFIER);
5714 }
c285545f 5715 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5716 for_each_online_cpu(cpu)
5717 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5718
5719 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5720 cpu_notifier_register_done();
5721
b820cc0c
ZA		 5722}
5723
ff9d07a0
ZY		 5724static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5725
f5132b01 5726int kvm_is_in_guest(void)
ff9d07a0 5727{
086c9855 5728 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5729}
5730
5731static int kvm_is_user_mode(void)
5732{
5733 int user_mode = 3;
dcf46b94 5734
086c9855
AS		 5735 if (__this_cpu_read(current_vcpu))
5736 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5737
ff9d07a0
ZY		 5738 return user_mode != 0;
5739}
5740
5741static unsigned long kvm_get_guest_ip(void)
5742{
5743 unsigned long ip = 0;
dcf46b94 5744
086c9855
AS		 5745 if (__this_cpu_read(current_vcpu))
5746 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5747
ff9d07a0
ZY		 5748 return ip;
5749}
5750
5751static struct perf_guest_info_callbacks kvm_guest_cbs = {
5752 .is_in_guest = kvm_is_in_guest,
5753 .is_user_mode = kvm_is_user_mode,
5754 .get_guest_ip = kvm_get_guest_ip,
5755};
5756
5757void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5758{
086c9855 5759 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5760}
5761EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5762
5763void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5764{
086c9855 5765 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5766}
5767EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5768
ce88decf
XG		 5769static void kvm_set_mmio_spte_mask(void)
5770{
5771 u64 mask;
5772 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5773
5774 /*
5775 * Set the reserved bits and the present bit of an paging-structure
5776 * entry to generate page fault with PFER.RSV = 1.
5777 */
885032b9 5778 /* Mask the reserved physical address bits. */
d1431483 5779 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5780
5781 /* Bit 62 is always reserved for 32bit host. */
5782 mask |= 0x3ull << 62;
5783
5784 /* Set the present bit. */
ce88decf
XG		 5785 mask |= 1ull;
5786
5787#ifdef CONFIG_X86_64
5788 /*
5789 * If reserved bit is not supported, clear the present bit to disable
5790 * mmio page fault.
5791 */
5792 if (maxphyaddr == 52)
5793 mask &= ~1ull;
5794#endif
5795
5796 kvm_mmu_set_mmio_spte_mask(mask);
5797}
5798
16e8d74d
MT		 5799#ifdef CONFIG_X86_64
5800static void pvclock_gtod_update_fn(struct work_struct *work)
5801{
d828199e
MT		 5802 struct kvm *kvm;
5803
5804 struct kvm_vcpu *vcpu;
5805 int i;
5806
2f303b74 5807 spin_lock(&kvm_lock);
d828199e
MT		 5808 list_for_each_entry(kvm, &vm_list, vm_list)
5809 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5810 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5811 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5812 spin_unlock(&kvm_lock);
16e8d74d
MT		 5813}
5814
5815static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5816
5817/*
5818 * Notification about pvclock gtod data update.
5819 */
5820static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5821 void *priv)
5822{
5823 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5824 struct timekeeper *tk = priv;
5825
5826 update_pvclock_gtod(tk);
5827
5828 /* disable master clock if host does not trust, or does not
5829 * use, TSC clocksource
5830 */
5831 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5832 atomic_read(&kvm_guest_has_master_clock) != 0)
5833 queue_work(system_long_wq, &pvclock_gtod_work);
5834
5835 return 0;
5836}
5837
5838static struct notifier_block pvclock_gtod_notifier = {
5839 .notifier_call = pvclock_gtod_notify,
5840};
5841#endif
5842
f8c16bba 5843int kvm_arch_init(void *opaque)
043405e1 5844{
b820cc0c 5845 int r;
6b61edf7 5846 struct kvm_x86_ops *ops = opaque;
f8c16bba 5847
f8c16bba
ZX		 5848 if (kvm_x86_ops) {
5849 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5850 r = -EEXIST;
5851 goto out;
f8c16bba
ZX		 5852 }
5853
5854 if (!ops->cpu_has_kvm_support()) {
5855 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5856 r = -EOPNOTSUPP;
5857 goto out;
f8c16bba
ZX		 5858 }
5859 if (ops->disabled_by_bios()) {
5860 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5861 r = -EOPNOTSUPP;
5862 goto out;
f8c16bba
ZX		 5863 }
5864
013f6a5d
MT		 5865 r = -ENOMEM;
5866 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5867 if (!shared_msrs) {
5868 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5869 goto out;
5870 }
5871
97db56ce
AK		 5872 r = kvm_mmu_module_init();
5873 if (r)
013f6a5d 5874 goto out_free_percpu;
97db56ce 5875
ce88decf 5876 kvm_set_mmio_spte_mask();
97db56ce 5877
f8c16bba 5878 kvm_x86_ops = ops;
920c8377 5879
7b52345e 5880 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5881 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5882
b820cc0c 5883 kvm_timer_init();
c8076604 5884
ff9d07a0
ZY		 5885 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5886
d366bf7e 5887 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 5888 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5889
c5cc421b 5890 kvm_lapic_init();
16e8d74d
MT		 5891#ifdef CONFIG_X86_64
5892 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5893#endif
5894
f8c16bba 5895 return 0;
56c6d28a 5896
013f6a5d
MT		 5897out_free_percpu:
5898 free_percpu(shared_msrs);
56c6d28a 5899out:
56c6d28a 5900 return r;
043405e1 5901}
8776e519 5902
f8c16bba
ZX		 5903void kvm_arch_exit(void)
5904{
ff9d07a0
ZY		 5905 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5906
888d256e
JK		 5907 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5908 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5909 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5910 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5911#ifdef CONFIG_X86_64
5912 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5913#endif
f8c16bba 5914 kvm_x86_ops = NULL;
56c6d28a 5915 kvm_mmu_module_exit();
013f6a5d 5916 free_percpu(shared_msrs);
56c6d28a 5917}
f8c16bba 5918
5cb56059 5919int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5920{
5921 ++vcpu->stat.halt_exits;
35754c98 5922 if (lapic_in_kernel(vcpu)) {
a4535290 5923 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5924 return 1;
5925 } else {
5926 vcpu->run->exit_reason = KVM_EXIT_HLT;
5927 return 0;
5928 }
5929}
5cb56059
JS		 5930EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5931
5932int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5933{
5934 kvm_x86_ops->skip_emulated_instruction(vcpu);
5935 return kvm_vcpu_halt(vcpu);
5936}
8776e519
HB		 5937EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5938
6aef266c
SV		 5939/*
5940 * kvm_pv_kick_cpu_op: Kick a vcpu.
5941 *
5942 * @apicid - apicid of vcpu to be kicked.
5943 */
5944static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5945{
24d2166b 5946 struct kvm_lapic_irq lapic_irq;
6aef266c 5947
24d2166b
R		 5948 lapic_irq.shorthand = 0;
5949 lapic_irq.dest_mode = 0;
5950 lapic_irq.dest_id = apicid;
93bbf0b8 5951 lapic_irq.msi_redir_hint = false;
6aef266c 5952
24d2166b 5953 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5954 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5955}
5956
d62caabb
AS		 5957void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5958{
5959 vcpu->arch.apicv_active = false;
5960 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5961}
5962
8776e519
HB		 5963int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5964{
5965 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5966 int op_64_bit, r = 1;
8776e519 5967
5cb56059
JS		 5968 kvm_x86_ops->skip_emulated_instruction(vcpu);
5969
55cd8e5a
GN		 5970 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5971 return kvm_hv_hypercall(vcpu);
5972
5fdbf976
MT		 5973 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5974 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5975 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5976 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5977 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5978
229456fc 5979 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5980
a449c7aa
NA		 5981 op_64_bit = is_64_bit_mode(vcpu);
5982 if (!op_64_bit) {
8776e519
HB		 5983 nr &= 0xFFFFFFFF;
5984 a0 &= 0xFFFFFFFF;
5985 a1 &= 0xFFFFFFFF;
5986 a2 &= 0xFFFFFFFF;
5987 a3 &= 0xFFFFFFFF;
5988 }
5989
07708c4a
JK		 5990 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5991 ret = -KVM_EPERM;
5992 goto out;
5993 }
5994
8776e519 5995 switch (nr) {
b93463aa
AK		 5996 case KVM_HC_VAPIC_POLL_IRQ:
5997 ret = 0;
5998 break;
6aef266c
SV		 5999 case KVM_HC_KICK_CPU:
6000 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6001 ret = 0;
6002 break;
8776e519
HB		 6003 default:
6004 ret = -KVM_ENOSYS;
6005 break;
6006 }
07708c4a 6007out:
a449c7aa
NA		 6008 if (!op_64_bit)
6009 ret = (u32)ret;
5fdbf976 6010 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6011 ++vcpu->stat.hypercalls;
2f333bcb 6012 return r;
8776e519
HB		 6013}
6014EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6015
b6785def 6016static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6017{
d6aa1000 6018 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6019 char instruction[3];
5fdbf976 6020 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6021
8776e519 6022 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6023
9d74191a 6024 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6025}
6026
851ba692 6027static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6028{
782d422b
MG		 6029 return vcpu->run->request_interrupt_window &&
6030 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6031}
6032
851ba692 6033static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6034{
851ba692
AK		 6035 struct kvm_run *kvm_run = vcpu->run;
6036
91586a3b 6037 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6038 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6039 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6040 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6041 kvm_run->ready_for_interrupt_injection =
6042 pic_in_kernel(vcpu->kvm) ||
782d422b 6043 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6044}
6045
95ba8273
GN		 6046static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6047{
6048 int max_irr, tpr;
6049
6050 if (!kvm_x86_ops->update_cr8_intercept)
6051 return;
6052
bce87cce 6053 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6054 return;
6055
d62caabb
AS		 6056 if (vcpu->arch.apicv_active)
6057 return;
6058
8db3baa2
GN		 6059 if (!vcpu->arch.apic->vapic_addr)
6060 max_irr = kvm_lapic_find_highest_irr(vcpu);
6061 else
6062 max_irr = -1;
95ba8273
GN		 6063
6064 if (max_irr != -1)
6065 max_irr >>= 4;
6066
6067 tpr = kvm_lapic_get_cr8(vcpu);
6068
6069 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6070}
6071
b6b8a145 6072static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6073{
b6b8a145
JK		 6074 int r;
6075
95ba8273 6076 /* try to reinject previous events if any */
b59bb7bd 6077 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6078 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6079 vcpu->arch.exception.has_error_code,
6080 vcpu->arch.exception.error_code);
d6e8c854
NA		 6081
6082 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6083 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6084 X86_EFLAGS_RF);
6085
6bdf0662
NA		 6086 if (vcpu->arch.exception.nr == DB_VECTOR &&
6087 (vcpu->arch.dr7 & DR7_GD)) {
6088 vcpu->arch.dr7 &= ~DR7_GD;
6089 kvm_update_dr7(vcpu);
6090 }
6091
b59bb7bd
GN		 6092 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6093 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6094 vcpu->arch.exception.error_code,
6095 vcpu->arch.exception.reinject);
b6b8a145 6096 return 0;
b59bb7bd
GN		 6097 }
6098
95ba8273
GN		 6099 if (vcpu->arch.nmi_injected) {
6100 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6101 return 0;
95ba8273
GN		 6102 }
6103
6104 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6105 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6106 return 0;
6107 }
6108
6109 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6110 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6111 if (r != 0)
6112 return r;
95ba8273
GN		 6113 }
6114
6115 /* try to inject new event if pending */
c43203ca
PB		 6116 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6117 vcpu->arch.smi_pending = false;
ee2cd4b7 6118 enter_smm(vcpu);
c43203ca 6119 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6120 --vcpu->arch.nmi_pending;
6121 vcpu->arch.nmi_injected = true;
6122 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6123 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6124 /*
6125 * Because interrupts can be injected asynchronously, we are
6126 * calling check_nested_events again here to avoid a race condition.
6127 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6128 * proposal and current concerns. Perhaps we should be setting
6129 * KVM_REQ_EVENT only on certain events and not unconditionally?
6130 */
6131 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6132 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6133 if (r != 0)
6134 return r;
6135 }
95ba8273 6136 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6137 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6138 false);
6139 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6140 }
6141 }
ee2cd4b7 6142
b6b8a145 6143 return 0;
95ba8273
GN		 6144}
6145
7460fb4a
AK		 6146static void process_nmi(struct kvm_vcpu *vcpu)
6147{
6148 unsigned limit = 2;
6149
6150 /*
6151 * x86 is limited to one NMI running, and one NMI pending after it.
6152 * If an NMI is already in progress, limit further NMIs to just one.
6153 * Otherwise, allow two (and we'll inject the first one immediately).
6154 */
6155 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6156 limit = 1;
6157
6158 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6159 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6160 kvm_make_request(KVM_REQ_EVENT, vcpu);
6161}
6162
660a5d51
PB		 6163#define put_smstate(type, buf, offset, val) \
6164 *(type *)((buf) + (offset) - 0x7e00) = val
6165
ee2cd4b7 6166static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6167{
6168 u32 flags = 0;
6169 flags |= seg->g << 23;
6170 flags |= seg->db << 22;
6171 flags |= seg->l << 21;
6172 flags |= seg->avl << 20;
6173 flags |= seg->present << 15;
6174 flags |= seg->dpl << 13;
6175 flags |= seg->s << 12;
6176 flags |= seg->type << 8;
6177 return flags;
6178}
6179
ee2cd4b7 6180static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6181{
6182 struct kvm_segment seg;
6183 int offset;
6184
6185 kvm_get_segment(vcpu, &seg, n);
6186 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6187
6188 if (n < 3)
6189 offset = 0x7f84 + n * 12;
6190 else
6191 offset = 0x7f2c + (n - 3) * 12;
6192
6193 put_smstate(u32, buf, offset + 8, seg.base);
6194 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6195 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6196}
6197
efbb288a 6198#ifdef CONFIG_X86_64
ee2cd4b7 6199static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6200{
6201 struct kvm_segment seg;
6202 int offset;
6203 u16 flags;
6204
6205 kvm_get_segment(vcpu, &seg, n);
6206 offset = 0x7e00 + n * 16;
6207
ee2cd4b7 6208 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6209 put_smstate(u16, buf, offset, seg.selector);
6210 put_smstate(u16, buf, offset + 2, flags);
6211 put_smstate(u32, buf, offset + 4, seg.limit);
6212 put_smstate(u64, buf, offset + 8, seg.base);
6213}
efbb288a 6214#endif
660a5d51 6215
ee2cd4b7 6216static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6217{
6218 struct desc_ptr dt;
6219 struct kvm_segment seg;
6220 unsigned long val;
6221 int i;
6222
6223 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6224 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6225 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6226 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6227
6228 for (i = 0; i < 8; i++)
6229 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6230
6231 kvm_get_dr(vcpu, 6, &val);
6232 put_smstate(u32, buf, 0x7fcc, (u32)val);
6233 kvm_get_dr(vcpu, 7, &val);
6234 put_smstate(u32, buf, 0x7fc8, (u32)val);
6235
6236 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6237 put_smstate(u32, buf, 0x7fc4, seg.selector);
6238 put_smstate(u32, buf, 0x7f64, seg.base);
6239 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6240 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6241
6242 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6243 put_smstate(u32, buf, 0x7fc0, seg.selector);
6244 put_smstate(u32, buf, 0x7f80, seg.base);
6245 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6246 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6247
6248 kvm_x86_ops->get_gdt(vcpu, &dt);
6249 put_smstate(u32, buf, 0x7f74, dt.address);
6250 put_smstate(u32, buf, 0x7f70, dt.size);
6251
6252 kvm_x86_ops->get_idt(vcpu, &dt);
6253 put_smstate(u32, buf, 0x7f58, dt.address);
6254 put_smstate(u32, buf, 0x7f54, dt.size);
6255
6256 for (i = 0; i < 6; i++)
ee2cd4b7 6257 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6258
6259 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6260
6261 /* revision id */
6262 put_smstate(u32, buf, 0x7efc, 0x00020000);
6263 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6264}
6265
ee2cd4b7 6266static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6267{
6268#ifdef CONFIG_X86_64
6269 struct desc_ptr dt;
6270 struct kvm_segment seg;
6271 unsigned long val;
6272 int i;
6273
6274 for (i = 0; i < 16; i++)
6275 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6276
6277 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6278 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6279
6280 kvm_get_dr(vcpu, 6, &val);
6281 put_smstate(u64, buf, 0x7f68, val);
6282 kvm_get_dr(vcpu, 7, &val);
6283 put_smstate(u64, buf, 0x7f60, val);
6284
6285 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6286 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6287 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6288
6289 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6290
6291 /* revision id */
6292 put_smstate(u32, buf, 0x7efc, 0x00020064);
6293
6294 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6295
6296 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6297 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6298 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6299 put_smstate(u32, buf, 0x7e94, seg.limit);
6300 put_smstate(u64, buf, 0x7e98, seg.base);
6301
6302 kvm_x86_ops->get_idt(vcpu, &dt);
6303 put_smstate(u32, buf, 0x7e84, dt.size);
6304 put_smstate(u64, buf, 0x7e88, dt.address);
6305
6306 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6307 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6308 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6309 put_smstate(u32, buf, 0x7e74, seg.limit);
6310 put_smstate(u64, buf, 0x7e78, seg.base);
6311
6312 kvm_x86_ops->get_gdt(vcpu, &dt);
6313 put_smstate(u32, buf, 0x7e64, dt.size);
6314 put_smstate(u64, buf, 0x7e68, dt.address);
6315
6316 for (i = 0; i < 6; i++)
ee2cd4b7 6317 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6318#else
6319 WARN_ON_ONCE(1);
6320#endif
6321}
6322
ee2cd4b7 6323static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6324{
660a5d51 6325 struct kvm_segment cs, ds;
18c3626e 6326 struct desc_ptr dt;
660a5d51
PB		 6327 char buf[512];
6328 u32 cr0;
6329
660a5d51
PB		 6330 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6331 vcpu->arch.hflags |= HF_SMM_MASK;
6332 memset(buf, 0, 512);
6333 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6334 enter_smm_save_state_64(vcpu, buf);
660a5d51 6335 else
ee2cd4b7 6336 enter_smm_save_state_32(vcpu, buf);
660a5d51 6337
54bf36aa 6338 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6339
6340 if (kvm_x86_ops->get_nmi_mask(vcpu))
6341 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6342 else
6343 kvm_x86_ops->set_nmi_mask(vcpu, true);
6344
6345 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6346 kvm_rip_write(vcpu, 0x8000);
6347
6348 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6349 kvm_x86_ops->set_cr0(vcpu, cr0);
6350 vcpu->arch.cr0 = cr0;
6351
6352 kvm_x86_ops->set_cr4(vcpu, 0);
6353
18c3626e
PB		 6354 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6355 dt.address = dt.size = 0;
6356 kvm_x86_ops->set_idt(vcpu, &dt);
6357
660a5d51
PB		 6358 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6359
6360 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6361 cs.base = vcpu->arch.smbase;
6362
6363 ds.selector = 0;
6364 ds.base = 0;
6365
6366 cs.limit = ds.limit = 0xffffffff;
6367 cs.type = ds.type = 0x3;
6368 cs.dpl = ds.dpl = 0;
6369 cs.db = ds.db = 0;
6370 cs.s = ds.s = 1;
6371 cs.l = ds.l = 0;
6372 cs.g = ds.g = 1;
6373 cs.avl = ds.avl = 0;
6374 cs.present = ds.present = 1;
6375 cs.unusable = ds.unusable = 0;
6376 cs.padding = ds.padding = 0;
6377
6378 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6379 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6380 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6381 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6382 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6383 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6384
6385 if (guest_cpuid_has_longmode(vcpu))
6386 kvm_x86_ops->set_efer(vcpu, 0);
6387
6388 kvm_update_cpuid(vcpu);
6389 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6390}
6391
ee2cd4b7 6392static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6393{
6394 vcpu->arch.smi_pending = true;
6395 kvm_make_request(KVM_REQ_EVENT, vcpu);
6396}
6397
2860c4b1
PB		 6398void kvm_make_scan_ioapic_request(struct kvm *kvm)
6399{
6400 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6401}
6402
3d81bc7e 6403static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6404{
5c919412
AS		 6405 u64 eoi_exit_bitmap[4];
6406
3d81bc7e
YZ		 6407 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6408 return;
c7c9c56c 6409
6308630b 6410 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6411
b053b2ae 6412 if (irqchip_split(vcpu->kvm))
6308630b 6413 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6414 else {
d62caabb
AS		 6415 if (vcpu->arch.apicv_active)
6416 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6417 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6418 }
5c919412
AS		 6419 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6420 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6421 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6422}
6423
a70656b6
RK		 6424static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6425{
6426 ++vcpu->stat.tlb_flush;
6427 kvm_x86_ops->tlb_flush(vcpu);
6428}
6429
4256f43f
TC		 6430void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6431{
c24ae0dc
TC		 6432 struct page *page = NULL;
6433
35754c98 6434 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6435 return;
6436
4256f43f
TC		 6437 if (!kvm_x86_ops->set_apic_access_page_addr)
6438 return;
6439
c24ae0dc 6440 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6441 if (is_error_page(page))
6442 return;
c24ae0dc
TC		 6443 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6444
6445 /*
6446 * Do not pin apic access page in memory, the MMU notifier
6447 * will call us again if it is migrated or swapped out.
6448 */
6449 put_page(page);
4256f43f
TC		 6450}
6451EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6452
fe71557a
TC		 6453void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6454 unsigned long address)
6455{
c24ae0dc
TC		 6456 /*
6457 * The physical address of apic access page is stored in the VMCS.
6458 * Update it when it becomes invalid.
6459 */
6460 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6461 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6462}
6463
9357d939 6464/*
362c698f 6465 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6466 * exiting to the userspace. Otherwise, the value will be returned to the
6467 * userspace.
6468 */
851ba692 6469static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6470{
6471 int r;
62a193ed
MG		 6472 bool req_int_win =
6473 dm_request_for_irq_injection(vcpu) &&
6474 kvm_cpu_accept_dm_intr(vcpu);
6475
730dca42 6476 bool req_immediate_exit = false;
b6c7a5dc 6477
3e007509 6478 if (vcpu->requests) {
a8eeb04a 6479 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6480 kvm_mmu_unload(vcpu);
a8eeb04a 6481 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6482 __kvm_migrate_timers(vcpu);
d828199e
MT		 6483 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6484 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6485 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6486 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6487 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6488 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6489 if (unlikely(r))
6490 goto out;
6491 }
a8eeb04a 6492 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6493 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6494 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6495 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6496 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6497 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6498 r = 0;
6499 goto out;
6500 }
a8eeb04a 6501 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6502 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6503 r = 0;
6504 goto out;
6505 }
a8eeb04a 6506 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6507 vcpu->fpu_active = 0;
6508 kvm_x86_ops->fpu_deactivate(vcpu);
6509 }
af585b92
GN		 6510 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6511 /* Page is swapped out. Do synthetic halt */
6512 vcpu->arch.apf.halted = true;
6513 r = 1;
6514 goto out;
6515 }
c9aaa895
GC		 6516 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6517 record_steal_time(vcpu);
64d60670 6518 if (kvm_check_request(KVM_REQ_SMI, vcpu))
ee2cd4b7 6519 process_smi(vcpu);
7460fb4a
AK		 6520 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6521 process_nmi(vcpu);
f5132b01 6522 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6523 kvm_pmu_handle_event(vcpu);
f5132b01 6524 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6525 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6526 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6527 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6528 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6529 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6530 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6531 vcpu->run->eoi.vector =
6532 vcpu->arch.pending_ioapic_eoi;
6533 r = 0;
6534 goto out;
6535 }
6536 }
3d81bc7e
YZ		 6537 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6538 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6539 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6540 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6541 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6542 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6543 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6544 r = 0;
6545 goto out;
6546 }
e516cebb
AS		 6547 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6548 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6549 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6550 r = 0;
6551 goto out;
6552 }
db397571
AS		 6553 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6554 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6555 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6556 r = 0;
6557 goto out;
6558 }
f3b138c5
AS		 6559
6560 /*
6561 * KVM_REQ_HV_STIMER has to be processed after
6562 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6563 * depend on the guest clock being up-to-date
6564 */
1f4b34f8
AS		 6565 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6566 kvm_hv_process_stimers(vcpu);
2f52d58c 6567 }
b93463aa 6568
bf9f6ac8
FW		 6569 /*
6570 * KVM_REQ_EVENT is not set when posted interrupts are set by
6571 * VT-d hardware, so we have to update RVI unconditionally.
6572 */
6573 if (kvm_lapic_enabled(vcpu)) {
6574 /*
6575 * Update architecture specific hints for APIC
6576 * virtual interrupt delivery.
6577 */
d62caabb 6578 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6579 kvm_x86_ops->hwapic_irr_update(vcpu,
6580 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6581 }
b93463aa 6582
b463a6f7 6583 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6584 kvm_apic_accept_events(vcpu);
6585 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6586 r = 1;
6587 goto out;
6588 }
6589
b6b8a145
JK		 6590 if (inject_pending_event(vcpu, req_int_win) != 0)
6591 req_immediate_exit = true;
321c5658 6592 else {
c43203ca
PB		 6593 /* Enable NMI/IRQ window open exits if needed.
6594 *
6595 * SMIs have two cases: 1) they can be nested, and
6596 * then there is nothing to do here because RSM will
6597 * cause a vmexit anyway; 2) or the SMI can be pending
6598 * because inject_pending_event has completed the
6599 * injection of an IRQ or NMI from the previous vmexit,
6600 * and then we request an immediate exit to inject the SMI.
6601 */
6602 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6603 req_immediate_exit = true;
321c5658
YS		 6604 if (vcpu->arch.nmi_pending)
6605 kvm_x86_ops->enable_nmi_window(vcpu);
6606 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6607 kvm_x86_ops->enable_irq_window(vcpu);
6608 }
b463a6f7
AK		 6609
6610 if (kvm_lapic_enabled(vcpu)) {
6611 update_cr8_intercept(vcpu);
6612 kvm_lapic_sync_to_vapic(vcpu);
6613 }
6614 }
6615
d8368af8
AK		 6616 r = kvm_mmu_reload(vcpu);
6617 if (unlikely(r)) {
d905c069 6618 goto cancel_injection;
d8368af8
AK		 6619 }
6620
b6c7a5dc
HB		 6621 preempt_disable();
6622
6623 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6624 if (vcpu->fpu_active)
6625 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6626 vcpu->mode = IN_GUEST_MODE;
6627
01b71917
MT		 6628 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6629
0f127d12
LT		 6630 /*
6631 * We should set ->mode before check ->requests,
6632 * Please see the comment in kvm_make_all_cpus_request.
6633 * This also orders the write to mode from any reads
6634 * to the page tables done while the VCPU is running.
6635 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6636 */
01b71917 6637 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6638
d94e1dc9 6639 local_irq_disable();
32f88400 6640
6b7e2d09 6641 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6642 || need_resched() || signal_pending(current)) {
6b7e2d09 6643 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6644 smp_wmb();
6c142801
AK		 6645 local_irq_enable();
6646 preempt_enable();
01b71917 6647 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6648 r = 1;
d905c069 6649 goto cancel_injection;
6c142801
AK		 6650 }
6651
fc5b7f3b
DM		 6652 kvm_load_guest_xcr0(vcpu);
6653
c43203ca
PB		 6654 if (req_immediate_exit) {
6655 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6656 smp_send_reschedule(vcpu->cpu);
c43203ca 6657 }
d6185f20 6658
8b89fe1f
PB		 6659 trace_kvm_entry(vcpu->vcpu_id);
6660 wait_lapic_expire(vcpu);
ccf73aaf 6661 __kvm_guest_enter();
b6c7a5dc 6662
42dbaa5a 6663 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6664 set_debugreg(0, 7);
6665 set_debugreg(vcpu->arch.eff_db[0], 0);
6666 set_debugreg(vcpu->arch.eff_db[1], 1);
6667 set_debugreg(vcpu->arch.eff_db[2], 2);
6668 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6669 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6670 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6671 }
b6c7a5dc 6672
851ba692 6673 kvm_x86_ops->run(vcpu);
b6c7a5dc 6674
c77fb5fe
PB		 6675 /*
6676 * Do this here before restoring debug registers on the host. And
6677 * since we do this before handling the vmexit, a DR access vmexit
6678 * can (a) read the correct value of the debug registers, (b) set
6679 * KVM_DEBUGREG_WONT_EXIT again.
6680 */
6681 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6682 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6683 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6684 kvm_update_dr0123(vcpu);
6685 kvm_update_dr6(vcpu);
6686 kvm_update_dr7(vcpu);
6687 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6688 }
6689
24f1e32c
FW		 6690 /*
6691 * If the guest has used debug registers, at least dr7
6692 * will be disabled while returning to the host.
6693 * If we don't have active breakpoints in the host, we don't
6694 * care about the messed up debug address registers. But if
6695 * we have some of them active, restore the old state.
6696 */
59d8eb53 6697 if (hw_breakpoint_active())
24f1e32c 6698 hw_breakpoint_restore();
42dbaa5a 6699
4ba76538 6700 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6701
6b7e2d09 6702 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6703 smp_wmb();
a547c6db 6704
fc5b7f3b
DM		 6705 kvm_put_guest_xcr0(vcpu);
6706
a547c6db
YZ		 6707 /* Interrupt is enabled by handle_external_intr() */
6708 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6709
6710 ++vcpu->stat.exits;
6711
6712 /*
6713 * We must have an instruction between local_irq_enable() and
6714 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6715 * the interrupt shadow. The stat.exits increment will do nicely.
6716 * But we need to prevent reordering, hence this barrier():
6717 */
6718 barrier();
6719
6720 kvm_guest_exit();
6721
6722 preempt_enable();
6723
f656ce01 6724 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6725
b6c7a5dc
HB		 6726 /*
6727 * Profile KVM exit RIPs:
6728 */
6729 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6730 unsigned long rip = kvm_rip_read(vcpu);
6731 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6732 }
6733
cc578287
ZA		 6734 if (unlikely(vcpu->arch.tsc_always_catchup))
6735 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6736
5cfb1d5a
MT		 6737 if (vcpu->arch.apic_attention)
6738 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6739
851ba692 6740 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6741 return r;
6742
6743cancel_injection:
6744 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6745 if (unlikely(vcpu->arch.apic_attention))
6746 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6747out:
6748 return r;
6749}
b6c7a5dc 6750
362c698f
PB		 6751static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6752{
bf9f6ac8
FW		 6753 if (!kvm_arch_vcpu_runnable(vcpu) &&
6754 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6755 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6756 kvm_vcpu_block(vcpu);
6757 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6758
6759 if (kvm_x86_ops->post_block)
6760 kvm_x86_ops->post_block(vcpu);
6761
9c8fd1ba
PB		 6762 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6763 return 1;
6764 }
362c698f
PB		 6765
6766 kvm_apic_accept_events(vcpu);
6767 switch(vcpu->arch.mp_state) {
6768 case KVM_MP_STATE_HALTED:
6769 vcpu->arch.pv.pv_unhalted = false;
6770 vcpu->arch.mp_state =
6771 KVM_MP_STATE_RUNNABLE;
6772 case KVM_MP_STATE_RUNNABLE:
6773 vcpu->arch.apf.halted = false;
6774 break;
6775 case KVM_MP_STATE_INIT_RECEIVED:
6776 break;
6777 default:
6778 return -EINTR;
6779 break;
6780 }
6781 return 1;
6782}
09cec754 6783
5d9bc648
PB		 6784static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6785{
6786 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6787 !vcpu->arch.apf.halted);
6788}
6789
362c698f 6790static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6791{
6792 int r;
f656ce01 6793 struct kvm *kvm = vcpu->kvm;
d7690175 6794
f656ce01 6795 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6796
362c698f 6797 for (;;) {
58f800d5 6798 if (kvm_vcpu_running(vcpu)) {
851ba692 6799 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6800 } else {
362c698f 6801 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6802 }
6803
09cec754
GN		 6804 if (r <= 0)
6805 break;
6806
6807 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6808 if (kvm_cpu_has_pending_timer(vcpu))
6809 kvm_inject_pending_timer_irqs(vcpu);
6810
782d422b
MG		 6811 if (dm_request_for_irq_injection(vcpu) &&
6812 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6813 r = 0;
6814 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6815 ++vcpu->stat.request_irq_exits;
362c698f 6816 break;
09cec754 6817 }
af585b92
GN		 6818
6819 kvm_check_async_pf_completion(vcpu);
6820
09cec754
GN		 6821 if (signal_pending(current)) {
6822 r = -EINTR;
851ba692 6823 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6824 ++vcpu->stat.signal_exits;
362c698f 6825 break;
09cec754
GN		 6826 }
6827 if (need_resched()) {
f656ce01 6828 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6829 cond_resched();
f656ce01 6830 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6831 }
b6c7a5dc
HB		 6832 }
6833
f656ce01 6834 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6835
6836 return r;
6837}
6838
716d51ab
GN		 6839static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6840{
6841 int r;
6842 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6843 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6844 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6845 if (r != EMULATE_DONE)
6846 return 0;
6847 return 1;
6848}
6849
6850static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6851{
6852 BUG_ON(!vcpu->arch.pio.count);
6853
6854 return complete_emulated_io(vcpu);
6855}
6856
f78146b0
AK		 6857/*
6858 * Implements the following, as a state machine:
6859 *
6860 * read:
6861 * for each fragment
87da7e66
XG		 6862 * for each mmio piece in the fragment
6863 * write gpa, len
6864 * exit
6865 * copy data
f78146b0
AK		 6866 * execute insn
6867 *
6868 * write:
6869 * for each fragment
87da7e66
XG		 6870 * for each mmio piece in the fragment
6871 * write gpa, len
6872 * copy data
6873 * exit
f78146b0 6874 */
716d51ab 6875static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6876{
6877 struct kvm_run *run = vcpu->run;
f78146b0 6878 struct kvm_mmio_fragment *frag;
87da7e66 6879 unsigned len;
5287f194 6880
716d51ab 6881 BUG_ON(!vcpu->mmio_needed);
5287f194 6882
716d51ab 6883 /* Complete previous fragment */
87da7e66
XG		 6884 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6885 len = min(8u, frag->len);
716d51ab 6886 if (!vcpu->mmio_is_write)
87da7e66
XG		 6887 memcpy(frag->data, run->mmio.data, len);
6888
6889 if (frag->len <= 8) {
6890 /* Switch to the next fragment. */
6891 frag++;
6892 vcpu->mmio_cur_fragment++;
6893 } else {
6894 /* Go forward to the next mmio piece. */
6895 frag->data += len;
6896 frag->gpa += len;
6897 frag->len -= len;
6898 }
6899
a08d3b3b 6900 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6901 vcpu->mmio_needed = 0;
0912c977
PB		 6902
6903 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6904 if (vcpu->mmio_is_write)
716d51ab
GN		 6905 return 1;
6906 vcpu->mmio_read_completed = 1;
6907 return complete_emulated_io(vcpu);
6908 }
87da7e66 6909
716d51ab
GN		 6910 run->exit_reason = KVM_EXIT_MMIO;
6911 run->mmio.phys_addr = frag->gpa;
6912 if (vcpu->mmio_is_write)
87da7e66
XG		 6913 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6914 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6915 run->mmio.is_write = vcpu->mmio_is_write;
6916 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6917 return 0;
5287f194
AK		 6918}
6919
716d51ab 6920
b6c7a5dc
HB		 6921int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6922{
c5bedc68 6923 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6924 int r;
6925 sigset_t sigsaved;
6926
c4d72e2d 6927 fpu__activate_curr(fpu);
e5c30142 6928
ac9f6dc0
AK		 6929 if (vcpu->sigset_active)
6930 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6931
a4535290 6932 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6933 kvm_vcpu_block(vcpu);
66450a21 6934 kvm_apic_accept_events(vcpu);
d7690175 6935 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6936 r = -EAGAIN;
6937 goto out;
b6c7a5dc
HB		 6938 }
6939
b6c7a5dc 6940 /* re-sync apic's tpr */
35754c98 6941 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6942 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6943 r = -EINVAL;
6944 goto out;
6945 }
6946 }
b6c7a5dc 6947
716d51ab
GN		 6948 if (unlikely(vcpu->arch.complete_userspace_io)) {
6949 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6950 vcpu->arch.complete_userspace_io = NULL;
6951 r = cui(vcpu);
6952 if (r <= 0)
6953 goto out;
6954 } else
6955 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6956
362c698f 6957 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6958
6959out:
f1d86e46 6960 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6961 if (vcpu->sigset_active)
6962 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6963
b6c7a5dc
HB		 6964 return r;
6965}
6966
6967int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6968{
7ae441ea
GN		 6969 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6970 /*
6971 * We are here if userspace calls get_regs() in the middle of
6972 * instruction emulation. Registers state needs to be copied
4a969980 6973 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6974 * that usually, but some bad designed PV devices (vmware
6975 * backdoor interface) need this to work
6976 */
dd856efa 6977 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6978 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6979 }
5fdbf976
MT		 6980 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6981 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6982 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6983 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6984 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6985 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6986 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6987 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6988#ifdef CONFIG_X86_64
5fdbf976
MT		 6989 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6990 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6991 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6992 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6993 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6994 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6995 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6996 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6997#endif
6998
5fdbf976 6999 regs->rip = kvm_rip_read(vcpu);
91586a3b 7000 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7001
b6c7a5dc
HB		 7002 return 0;
7003}
7004
7005int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7006{
7ae441ea
GN		 7007 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7008 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7009
5fdbf976
MT		 7010 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7011 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7012 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7013 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7014 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7015 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7016 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7017 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7018#ifdef CONFIG_X86_64
5fdbf976
MT		 7019 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7020 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7021 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7022 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7023 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7024 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7025 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7026 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7027#endif
7028
5fdbf976 7029 kvm_rip_write(vcpu, regs->rip);
91586a3b 7030 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7031
b4f14abd
JK		 7032 vcpu->arch.exception.pending = false;
7033
3842d135
AK		 7034 kvm_make_request(KVM_REQ_EVENT, vcpu);
7035
b6c7a5dc
HB		 7036 return 0;
7037}
7038
b6c7a5dc
HB		 7039void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7040{
7041 struct kvm_segment cs;
7042
3e6e0aab 7043 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7044 *db = cs.db;
7045 *l = cs.l;
7046}
7047EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7048
7049int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7050 struct kvm_sregs *sregs)
7051{
89a27f4d 7052 struct desc_ptr dt;
b6c7a5dc 7053
3e6e0aab
GT		 7054 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7055 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7056 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7057 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7058 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7059 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7060
3e6e0aab
GT		 7061 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7062 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7063
7064 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7065 sregs->idt.limit = dt.size;
7066 sregs->idt.base = dt.address;
b6c7a5dc 7067 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7068 sregs->gdt.limit = dt.size;
7069 sregs->gdt.base = dt.address;
b6c7a5dc 7070
4d4ec087 7071 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7072 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7073 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7074 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7075 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7076 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7077 sregs->apic_base = kvm_get_apic_base(vcpu);
7078
923c61bb 7079 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7080
36752c9b 7081 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7082 set_bit(vcpu->arch.interrupt.nr,
7083 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7084
b6c7a5dc
HB		 7085 return 0;
7086}
7087
62d9f0db
MT		 7088int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7089 struct kvm_mp_state *mp_state)
7090{
66450a21 7091 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7092 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7093 vcpu->arch.pv.pv_unhalted)
7094 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7095 else
7096 mp_state->mp_state = vcpu->arch.mp_state;
7097
62d9f0db
MT		 7098 return 0;
7099}
7100
7101int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7102 struct kvm_mp_state *mp_state)
7103{
bce87cce 7104 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7105 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7106 return -EINVAL;
7107
7108 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7109 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7110 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7111 } else
7112 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7113 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7114 return 0;
7115}
7116
7f3d35fd
KW		 7117int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7118 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7119{
9d74191a 7120 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7121 int ret;
e01c2426 7122
8ec4722d 7123 init_emulate_ctxt(vcpu);
c697518a 7124
7f3d35fd 7125 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7126 has_error_code, error_code);
c697518a 7127
c697518a 7128 if (ret)
19d04437 7129 return EMULATE_FAIL;
37817f29 7130
9d74191a
TY		 7131 kvm_rip_write(vcpu, ctxt->eip);
7132 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7133 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7134 return EMULATE_DONE;
37817f29
IE		 7135}
7136EXPORT_SYMBOL_GPL(kvm_task_switch);
7137
b6c7a5dc
HB		 7138int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7139 struct kvm_sregs *sregs)
7140{
58cb628d 7141 struct msr_data apic_base_msr;
b6c7a5dc 7142 int mmu_reset_needed = 0;
63f42e02 7143 int pending_vec, max_bits, idx;
89a27f4d 7144 struct desc_ptr dt;
b6c7a5dc 7145
6d1068b3
PM		 7146 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7147 return -EINVAL;
7148
89a27f4d
GN		 7149 dt.size = sregs->idt.limit;
7150 dt.address = sregs->idt.base;
b6c7a5dc 7151 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7152 dt.size = sregs->gdt.limit;
7153 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7154 kvm_x86_ops->set_gdt(vcpu, &dt);
7155
ad312c7c 7156 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7157 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7158 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7159 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7160
2d3ad1f4 7161 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7162
f6801dff 7163 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7164 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7165 apic_base_msr.data = sregs->apic_base;
7166 apic_base_msr.host_initiated = true;
7167 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7168
4d4ec087 7169 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7170 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7171 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7172
fc78f519 7173 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7174 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7175 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7176 kvm_update_cpuid(vcpu);
63f42e02
XG		 7177
7178 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7179 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7180 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7181 mmu_reset_needed = 1;
7182 }
63f42e02 7183 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7184
7185 if (mmu_reset_needed)
7186 kvm_mmu_reset_context(vcpu);
7187
a50abc3b 7188 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7189 pending_vec = find_first_bit(
7190 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7191 if (pending_vec < max_bits) {
66fd3f7f 7192 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7193 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7194 }
7195
3e6e0aab
GT		 7196 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7197 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7198 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7199 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7200 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7201 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7202
3e6e0aab
GT		 7203 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7204 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7205
5f0269f5
ME		 7206 update_cr8_intercept(vcpu);
7207
9c3e4aab 7208 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7209 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7210 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7211 !is_protmode(vcpu))
9c3e4aab
MT		 7212 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7213
3842d135
AK		 7214 kvm_make_request(KVM_REQ_EVENT, vcpu);
7215
b6c7a5dc
HB		 7216 return 0;
7217}
7218
d0bfb940
JK		 7219int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7220 struct kvm_guest_debug *dbg)
b6c7a5dc 7221{
355be0b9 7222 unsigned long rflags;
ae675ef0 7223 int i, r;
b6c7a5dc 7224
4f926bf2
JK		 7225 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7226 r = -EBUSY;
7227 if (vcpu->arch.exception.pending)
2122ff5e 7228 goto out;
4f926bf2
JK		 7229 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7230 kvm_queue_exception(vcpu, DB_VECTOR);
7231 else
7232 kvm_queue_exception(vcpu, BP_VECTOR);
7233 }
7234
91586a3b
JK		 7235 /*
7236 * Read rflags as long as potentially injected trace flags are still
7237 * filtered out.
7238 */
7239 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7240
7241 vcpu->guest_debug = dbg->control;
7242 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7243 vcpu->guest_debug = 0;
7244
7245 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7246 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7247 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7248 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7249 } else {
7250 for (i = 0; i < KVM_NR_DB_REGS; i++)
7251 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7252 }
c8639010 7253 kvm_update_dr7(vcpu);
ae675ef0 7254
f92653ee
JK		 7255 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7256 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7257 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7258
91586a3b
JK		 7259 /*
7260 * Trigger an rflags update that will inject or remove the trace
7261 * flags.
7262 */
7263 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7264
a96036b8 7265 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7266
4f926bf2 7267 r = 0;
d0bfb940 7268
2122ff5e 7269out:
b6c7a5dc
HB		 7270
7271 return r;
7272}
7273
8b006791
ZX		 7274/*
7275 * Translate a guest virtual address to a guest physical address.
7276 */
7277int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7278 struct kvm_translation *tr)
7279{
7280 unsigned long vaddr = tr->linear_address;
7281 gpa_t gpa;
f656ce01 7282 int idx;
8b006791 7283
f656ce01 7284 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7285 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7286 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7287 tr->physical_address = gpa;
7288 tr->valid = gpa != UNMAPPED_GVA;
7289 tr->writeable = 1;
7290 tr->usermode = 0;
8b006791
ZX		 7291
7292 return 0;
7293}
7294
d0752060
HB		 7295int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7296{
c47ada30 7297 struct fxregs_state *fxsave =
7366ed77 7298 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7299
d0752060
HB		 7300 memcpy(fpu->fpr, fxsave->st_space, 128);
7301 fpu->fcw = fxsave->cwd;
7302 fpu->fsw = fxsave->swd;
7303 fpu->ftwx = fxsave->twd;
7304 fpu->last_opcode = fxsave->fop;
7305 fpu->last_ip = fxsave->rip;
7306 fpu->last_dp = fxsave->rdp;
7307 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7308
d0752060
HB		 7309 return 0;
7310}
7311
7312int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7313{
c47ada30 7314 struct fxregs_state *fxsave =
7366ed77 7315 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7316
d0752060
HB		 7317 memcpy(fxsave->st_space, fpu->fpr, 128);
7318 fxsave->cwd = fpu->fcw;
7319 fxsave->swd = fpu->fsw;
7320 fxsave->twd = fpu->ftwx;
7321 fxsave->fop = fpu->last_opcode;
7322 fxsave->rip = fpu->last_ip;
7323 fxsave->rdp = fpu->last_dp;
7324 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7325
d0752060
HB		 7326 return 0;
7327}
7328
0ee6a517 7329static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7330{
bf935b0b 7331 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7332 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7333 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7334 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7335
2acf923e
DC		 7336 /*
7337 * Ensure guest xcr0 is valid for loading
7338 */
d91cab78 7339 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7340
ad312c7c 7341 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7342}
d0752060
HB		 7343
7344void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7345{
2608d7a1 7346 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7347 return;
7348
2acf923e
DC		 7349 /*
7350 * Restore all possible states in the guest,
7351 * and assume host would use all available bits.
7352 * Guest xcr0 would be loaded later.
7353 */
d0752060 7354 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7355 __kernel_fpu_begin();
003e2e8b 7356 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7357 trace_kvm_fpu(1);
d0752060 7358}
d0752060
HB		 7359
7360void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7361{
653f52c3
RR		 7362 if (!vcpu->guest_fpu_loaded) {
7363 vcpu->fpu_counter = 0;
d0752060 7364 return;
653f52c3 7365 }
d0752060
HB		 7366
7367 vcpu->guest_fpu_loaded = 0;
4f836347 7368 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7369 __kernel_fpu_end();
f096ed85 7370 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7371 /*
7372 * If using eager FPU mode, or if the guest is a frequent user
7373 * of the FPU, just leave the FPU active for next time.
7374 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7375 * the FPU in bursts will revert to loading it on demand.
7376 */
5a5fbdc0 7377 if (!use_eager_fpu()) {
653f52c3
RR		 7378 if (++vcpu->fpu_counter < 5)
7379 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7380 }
0c04851c 7381 trace_kvm_fpu(0);
d0752060 7382}
e9b11c17
ZX		 7383
7384void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7385{
12f9a48f 7386 kvmclock_reset(vcpu);
7f1ea208 7387
f5f48ee1 7388 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7389 kvm_x86_ops->vcpu_free(vcpu);
7390}
7391
7392struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7393 unsigned int id)
7394{
c447e76b
LL		 7395 struct kvm_vcpu *vcpu;
7396
6755bae8
ZA		 7397 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7398 printk_once(KERN_WARNING
7399 "kvm: SMP vm created on host with unstable TSC; "
7400 "guest TSC will not be reliable\n");
c447e76b
LL		 7401
7402 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7403
c447e76b 7404 return vcpu;
26e5215f 7405}
e9b11c17 7406
26e5215f
AK		 7407int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7408{
7409 int r;
e9b11c17 7410
19efffa2 7411 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7412 r = vcpu_load(vcpu);
7413 if (r)
7414 return r;
d28bc9dd 7415 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7416 kvm_mmu_setup(vcpu);
e9b11c17 7417 vcpu_put(vcpu);
26e5215f 7418 return r;
e9b11c17
ZX		 7419}
7420
31928aa5 7421void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7422{
8fe8ab46 7423 struct msr_data msr;
332967a3 7424 struct kvm *kvm = vcpu->kvm;
42897d86 7425
31928aa5
DD		 7426 if (vcpu_load(vcpu))
7427 return;
8fe8ab46
WA		 7428 msr.data = 0x0;
7429 msr.index = MSR_IA32_TSC;
7430 msr.host_initiated = true;
7431 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7432 vcpu_put(vcpu);
7433
630994b3
MT		 7434 if (!kvmclock_periodic_sync)
7435 return;
7436
332967a3
AJ		 7437 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7438 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7439}
7440
d40ccc62 7441void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7442{
9fc77441 7443 int r;
344d9588
GN		 7444 vcpu->arch.apf.msr_val = 0;
7445
9fc77441
MT		 7446 r = vcpu_load(vcpu);
7447 BUG_ON(r);
e9b11c17
ZX		 7448 kvm_mmu_unload(vcpu);
7449 vcpu_put(vcpu);
7450
7451 kvm_x86_ops->vcpu_free(vcpu);
7452}
7453
d28bc9dd 7454void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7455{
e69fab5d
PB		 7456 vcpu->arch.hflags = 0;
7457
c43203ca 7458 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7459 atomic_set(&vcpu->arch.nmi_queued, 0);
7460 vcpu->arch.nmi_pending = 0;
448fa4a9 7461 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7462 kvm_clear_interrupt_queue(vcpu);
7463 kvm_clear_exception_queue(vcpu);
448fa4a9 7464
42dbaa5a 7465 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7466 kvm_update_dr0123(vcpu);
6f43ed01 7467 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7468 kvm_update_dr6(vcpu);
42dbaa5a 7469 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7470 kvm_update_dr7(vcpu);
42dbaa5a 7471
1119022c
NA		 7472 vcpu->arch.cr2 = 0;
7473
3842d135 7474 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7475 vcpu->arch.apf.msr_val = 0;
c9aaa895 7476 vcpu->arch.st.msr_val = 0;
3842d135 7477
12f9a48f
GC		 7478 kvmclock_reset(vcpu);
7479
af585b92
GN		 7480 kvm_clear_async_pf_completion_queue(vcpu);
7481 kvm_async_pf_hash_reset(vcpu);
7482 vcpu->arch.apf.halted = false;
3842d135 7483
64d60670 7484 if (!init_event) {
d28bc9dd 7485 kvm_pmu_reset(vcpu);
64d60670
PB		 7486 vcpu->arch.smbase = 0x30000;
7487 }
f5132b01 7488
66f7b72e
JS		 7489 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7490 vcpu->arch.regs_avail = ~0;
7491 vcpu->arch.regs_dirty = ~0;
7492
d28bc9dd 7493 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7494}
7495
2b4a273b 7496void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7497{
7498 struct kvm_segment cs;
7499
7500 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7501 cs.selector = vector << 8;
7502 cs.base = vector << 12;
7503 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7504 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7505}
7506
13a34e06 7507int kvm_arch_hardware_enable(void)
e9b11c17 7508{
ca84d1a2
ZA		 7509 struct kvm *kvm;
7510 struct kvm_vcpu *vcpu;
7511 int i;
0dd6a6ed
ZA		 7512 int ret;
7513 u64 local_tsc;
7514 u64 max_tsc = 0;
7515 bool stable, backwards_tsc = false;
18863bdd
AK		 7516
7517 kvm_shared_msr_cpu_online();
13a34e06 7518 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7519 if (ret != 0)
7520 return ret;
7521
4ea1636b 7522 local_tsc = rdtsc();
0dd6a6ed
ZA		 7523 stable = !check_tsc_unstable();
7524 list_for_each_entry(kvm, &vm_list, vm_list) {
7525 kvm_for_each_vcpu(i, vcpu, kvm) {
7526 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7527 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7528 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7529 backwards_tsc = true;
7530 if (vcpu->arch.last_host_tsc > max_tsc)
7531 max_tsc = vcpu->arch.last_host_tsc;
7532 }
7533 }
7534 }
7535
7536 /*
7537 * Sometimes, even reliable TSCs go backwards. This happens on
7538 * platforms that reset TSC during suspend or hibernate actions, but
7539 * maintain synchronization. We must compensate. Fortunately, we can
7540 * detect that condition here, which happens early in CPU bringup,
7541 * before any KVM threads can be running. Unfortunately, we can't
7542 * bring the TSCs fully up to date with real time, as we aren't yet far
7543 * enough into CPU bringup that we know how much real time has actually
7544 * elapsed; our helper function, get_kernel_ns() will be using boot
7545 * variables that haven't been updated yet.
7546 *
7547 * So we simply find the maximum observed TSC above, then record the
7548 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7549 * the adjustment will be applied. Note that we accumulate
7550 * adjustments, in case multiple suspend cycles happen before some VCPU
7551 * gets a chance to run again. In the event that no KVM threads get a
7552 * chance to run, we will miss the entire elapsed period, as we'll have
7553 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7554 * loose cycle time. This isn't too big a deal, since the loss will be
7555 * uniform across all VCPUs (not to mention the scenario is extremely
7556 * unlikely). It is possible that a second hibernate recovery happens
7557 * much faster than a first, causing the observed TSC here to be
7558 * smaller; this would require additional padding adjustment, which is
7559 * why we set last_host_tsc to the local tsc observed here.
7560 *
7561 * N.B. - this code below runs only on platforms with reliable TSC,
7562 * as that is the only way backwards_tsc is set above. Also note
7563 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7564 * have the same delta_cyc adjustment applied if backwards_tsc
7565 * is detected. Note further, this adjustment is only done once,
7566 * as we reset last_host_tsc on all VCPUs to stop this from being
7567 * called multiple times (one for each physical CPU bringup).
7568 *
4a969980 7569 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7570 * will be compensated by the logic in vcpu_load, which sets the TSC to
7571 * catchup mode. This will catchup all VCPUs to real time, but cannot
7572 * guarantee that they stay in perfect synchronization.
7573 */
7574 if (backwards_tsc) {
7575 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7576 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7577 list_for_each_entry(kvm, &vm_list, vm_list) {
7578 kvm_for_each_vcpu(i, vcpu, kvm) {
7579 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7580 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7581 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7582 }
7583
7584 /*
7585 * We have to disable TSC offset matching.. if you were
7586 * booting a VM while issuing an S4 host suspend....
7587 * you may have some problem. Solving this issue is
7588 * left as an exercise to the reader.
7589 */
7590 kvm->arch.last_tsc_nsec = 0;
7591 kvm->arch.last_tsc_write = 0;
7592 }
7593
7594 }
7595 return 0;
e9b11c17
ZX		 7596}
7597
13a34e06 7598void kvm_arch_hardware_disable(void)
e9b11c17 7599{
13a34e06
RK		 7600 kvm_x86_ops->hardware_disable();
7601 drop_user_return_notifiers();
e9b11c17
ZX		 7602}
7603
7604int kvm_arch_hardware_setup(void)
7605{
9e9c3fe4
NA		 7606 int r;
7607
7608 r = kvm_x86_ops->hardware_setup();
7609 if (r != 0)
7610 return r;
7611
35181e86
HZ		 7612 if (kvm_has_tsc_control) {
7613 /*
7614 * Make sure the user can only configure tsc_khz values that
7615 * fit into a signed integer.
7616 * A min value is not calculated needed because it will always
7617 * be 1 on all machines.
7618 */
7619 u64 max = min(0x7fffffffULL,
7620 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7621 kvm_max_guest_tsc_khz = max;
7622
ad721883 7623 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7624 }
ad721883 7625
9e9c3fe4
NA		 7626 kvm_init_msr_list();
7627 return 0;
e9b11c17
ZX		 7628}
7629
7630void kvm_arch_hardware_unsetup(void)
7631{
7632 kvm_x86_ops->hardware_unsetup();
7633}
7634
7635void kvm_arch_check_processor_compat(void *rtn)
7636{
7637 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7638}
7639
7640bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7641{
7642 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7643}
7644EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7645
7646bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7647{
7648 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7649}
7650
54e9818f 7651struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7652EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7653
e9b11c17
ZX		 7654int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7655{
7656 struct page *page;
7657 struct kvm *kvm;
7658 int r;
7659
7660 BUG_ON(vcpu->kvm == NULL);
7661 kvm = vcpu->kvm;
7662
d62caabb 7663 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7664 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7665 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7666 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7667 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7668 else
a4535290 7669 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7670
7671 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7672 if (!page) {
7673 r = -ENOMEM;
7674 goto fail;
7675 }
ad312c7c 7676 vcpu->arch.pio_data = page_address(page);
e9b11c17 7677
cc578287 7678 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7679
e9b11c17
ZX		 7680 r = kvm_mmu_create(vcpu);
7681 if (r < 0)
7682 goto fail_free_pio_data;
7683
7684 if (irqchip_in_kernel(kvm)) {
7685 r = kvm_create_lapic(vcpu);
7686 if (r < 0)
7687 goto fail_mmu_destroy;
54e9818f
GN		 7688 } else
7689 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7690
890ca9ae
HY		 7691 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7692 GFP_KERNEL);
7693 if (!vcpu->arch.mce_banks) {
7694 r = -ENOMEM;
443c39bc 7695 goto fail_free_lapic;
890ca9ae
HY		 7696 }
7697 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7698
f1797359
WY		 7699 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7700 r = -ENOMEM;
f5f48ee1 7701 goto fail_free_mce_banks;
f1797359 7702 }
f5f48ee1 7703
0ee6a517 7704 fx_init(vcpu);
66f7b72e 7705
ba904635 7706 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7707 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7708
7709 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7710 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7711
5a4f55cd
EK		 7712 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7713
74545705
RK		 7714 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7715
af585b92 7716 kvm_async_pf_hash_reset(vcpu);
f5132b01 7717 kvm_pmu_init(vcpu);
af585b92 7718
1c1a9ce9
SR		 7719 vcpu->arch.pending_external_vector = -1;
7720
5c919412
AS		 7721 kvm_hv_vcpu_init(vcpu);
7722
e9b11c17 7723 return 0;
0ee6a517 7724
f5f48ee1
SY		 7725fail_free_mce_banks:
7726 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7727fail_free_lapic:
7728 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7729fail_mmu_destroy:
7730 kvm_mmu_destroy(vcpu);
7731fail_free_pio_data:
ad312c7c 7732 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7733fail:
7734 return r;
7735}
7736
7737void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7738{
f656ce01
MT		 7739 int idx;
7740
1f4b34f8 7741 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7742 kvm_pmu_destroy(vcpu);
36cb93fd 7743 kfree(vcpu->arch.mce_banks);
e9b11c17 7744 kvm_free_lapic(vcpu);
f656ce01 7745 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7746 kvm_mmu_destroy(vcpu);
f656ce01 7747 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7748 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7749 if (!lapic_in_kernel(vcpu))
54e9818f 7750 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7751}
d19a9cd2 7752
e790d9ef
RK		 7753void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7754{
ae97a3b8 7755 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7756}
7757
e08b9637 7758int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7759{
e08b9637
CO		 7760 if (type)
7761 return -EINVAL;
7762
6ef768fa 7763 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7764 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7765 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7766 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7767 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7768
5550af4d
SY		 7769 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7770 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7771 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7772 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7773 &kvm->arch.irq_sources_bitmap);
5550af4d 7774
038f8c11 7775 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7776 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7777 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7778
7779 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7780
7e44e449 7781 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7782 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7783
0eb05bf2 7784 kvm_page_track_init(kvm);
13d268ca 7785 kvm_mmu_init_vm(kvm);
0eb05bf2 7786
03543133
SS		 7787 if (kvm_x86_ops->vm_init)
7788 return kvm_x86_ops->vm_init(kvm);
7789
d89f5eff 7790 return 0;
d19a9cd2
ZX		 7791}
7792
7793static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7794{
9fc77441
MT		 7795 int r;
7796 r = vcpu_load(vcpu);
7797 BUG_ON(r);
d19a9cd2
ZX		 7798 kvm_mmu_unload(vcpu);
7799 vcpu_put(vcpu);
7800}
7801
7802static void kvm_free_vcpus(struct kvm *kvm)
7803{
7804 unsigned int i;
988a2cae 7805 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7806
7807 /*
7808 * Unpin any mmu pages first.
7809 */
af585b92
GN		 7810 kvm_for_each_vcpu(i, vcpu, kvm) {
7811 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7812 kvm_unload_vcpu_mmu(vcpu);
af585b92 7813 }
988a2cae
GN		 7814 kvm_for_each_vcpu(i, vcpu, kvm)
7815 kvm_arch_vcpu_free(vcpu);
7816
7817 mutex_lock(&kvm->lock);
7818 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7819 kvm->vcpus[i] = NULL;
d19a9cd2 7820
988a2cae
GN		 7821 atomic_set(&kvm->online_vcpus, 0);
7822 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7823}
7824
ad8ba2cd
SY		 7825void kvm_arch_sync_events(struct kvm *kvm)
7826{
332967a3 7827 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7828 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7829 kvm_free_all_assigned_devices(kvm);
aea924f6 7830 kvm_free_pit(kvm);
ad8ba2cd
SY		 7831}
7832
1d8007bd 7833int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7834{
7835 int i, r;
25188b99 7836 unsigned long hva;
f0d648bd
PB		 7837 struct kvm_memslots *slots = kvm_memslots(kvm);
7838 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7839
7840 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7841 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7842 return -EINVAL;
9da0e4d5 7843
f0d648bd
PB		 7844 slot = id_to_memslot(slots, id);
7845 if (size) {
b21629da 7846 if (slot->npages)
f0d648bd
PB		 7847 return -EEXIST;
7848
7849 /*
7850 * MAP_SHARED to prevent internal slot pages from being moved
7851 * by fork()/COW.
7852 */
7853 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7854 MAP_SHARED | MAP_ANONYMOUS, 0);
7855 if (IS_ERR((void *)hva))
7856 return PTR_ERR((void *)hva);
7857 } else {
7858 if (!slot->npages)
7859 return 0;
7860
7861 hva = 0;
7862 }
7863
7864 old = *slot;
9da0e4d5 7865 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7866 struct kvm_userspace_memory_region m;
9da0e4d5 7867
1d8007bd
PB		 7868 m.slot = id | (i << 16);
7869 m.flags = 0;
7870 m.guest_phys_addr = gpa;
f0d648bd 7871 m.userspace_addr = hva;
1d8007bd 7872 m.memory_size = size;
9da0e4d5
PB		 7873 r = __kvm_set_memory_region(kvm, &m);
7874 if (r < 0)
7875 return r;
7876 }
7877
f0d648bd
PB		 7878 if (!size) {
7879 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7880 WARN_ON(r < 0);
7881 }
7882
9da0e4d5
PB		 7883 return 0;
7884}
7885EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7886
1d8007bd 7887int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7888{
7889 int r;
7890
7891 mutex_lock(&kvm->slots_lock);
1d8007bd 7892 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7893 mutex_unlock(&kvm->slots_lock);
7894
7895 return r;
7896}
7897EXPORT_SYMBOL_GPL(x86_set_memory_region);
7898
d19a9cd2
ZX		 7899void kvm_arch_destroy_vm(struct kvm *kvm)
7900{
27469d29
AH		 7901 if (current->mm == kvm->mm) {
7902 /*
7903 * Free memory regions allocated on behalf of userspace,
7904 * unless the the memory map has changed due to process exit
7905 * or fd copying.
7906 */
1d8007bd
PB		 7907 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7908 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7909 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7910 }
03543133
SS		 7911 if (kvm_x86_ops->vm_destroy)
7912 kvm_x86_ops->vm_destroy(kvm);
6eb55818 7913 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7914 kfree(kvm->arch.vpic);
7915 kfree(kvm->arch.vioapic);
d19a9cd2 7916 kvm_free_vcpus(kvm);
1e08ec4a 7917 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7918 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7919}
0de10343 7920
5587027c 7921void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7922 struct kvm_memory_slot *dont)
7923{
7924 int i;
7925
d89cc617
TY		 7926 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7927 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7928 kvfree(free->arch.rmap[i]);
d89cc617 7929 free->arch.rmap[i] = NULL;
77d11309 7930 }
d89cc617
TY		 7931 if (i == 0)
7932 continue;
7933
7934 if (!dont || free->arch.lpage_info[i - 1] !=
7935 dont->arch.lpage_info[i - 1]) {
548ef284 7936 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7937 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7938 }
7939 }
21ebbeda
XG		 7940
7941 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 7942}
7943
5587027c
AK		 7944int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7945 unsigned long npages)
db3fe4eb
TY		 7946{
7947 int i;
7948
d89cc617 7949 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 7950 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 7951 unsigned long ugfn;
7952 int lpages;
d89cc617 7953 int level = i + 1;
db3fe4eb
TY		 7954
7955 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7956 slot->base_gfn, level) + 1;
7957
d89cc617
TY		 7958 slot->arch.rmap[i] =
7959 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7960 if (!slot->arch.rmap[i])
77d11309 7961 goto out_free;
d89cc617
TY		 7962 if (i == 0)
7963 continue;
77d11309 7964
92f94f1e
XG		 7965 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
7966 if (!linfo)
db3fe4eb
TY		 7967 goto out_free;
7968
92f94f1e
XG		 7969 slot->arch.lpage_info[i - 1] = linfo;
7970
db3fe4eb 7971 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7972 linfo[0].disallow_lpage = 1;
db3fe4eb 7973 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 7974 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 7975 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7976 /*
7977 * If the gfn and userspace address are not aligned wrt each
7978 * other, or if explicitly asked to, disable large page
7979 * support for this slot
7980 */
7981 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7982 !kvm_largepages_enabled()) {
7983 unsigned long j;
7984
7985 for (j = 0; j < lpages; ++j)
92f94f1e 7986 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 7987 }
7988 }
7989
21ebbeda
XG		 7990 if (kvm_page_track_create_memslot(slot, npages))
7991 goto out_free;
7992
db3fe4eb
TY		 7993 return 0;
7994
7995out_free:
d89cc617 7996 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7997 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7998 slot->arch.rmap[i] = NULL;
7999 if (i == 0)
8000 continue;
8001
548ef284 8002 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8003 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8004 }
8005 return -ENOMEM;
8006}
8007
15f46015 8008void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8009{
e6dff7d1
TY		 8010 /*
8011 * memslots->generation has been incremented.
8012 * mmio generation may have reached its maximum value.
8013 */
54bf36aa 8014 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8015}
8016
f7784b8e
MT		 8017int kvm_arch_prepare_memory_region(struct kvm *kvm,
8018 struct kvm_memory_slot *memslot,
09170a49 8019 const struct kvm_userspace_memory_region *mem,
7b6195a9 8020 enum kvm_mr_change change)
0de10343 8021{
f7784b8e
MT		 8022 return 0;
8023}
8024
88178fd4
KH		 8025static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8026 struct kvm_memory_slot *new)
8027{
8028 /* Still write protect RO slot */
8029 if (new->flags & KVM_MEM_READONLY) {
8030 kvm_mmu_slot_remove_write_access(kvm, new);
8031 return;
8032 }
8033
8034 /*
8035 * Call kvm_x86_ops dirty logging hooks when they are valid.
8036 *
8037 * kvm_x86_ops->slot_disable_log_dirty is called when:
8038 *
8039 * - KVM_MR_CREATE with dirty logging is disabled
8040 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8041 *
8042 * The reason is, in case of PML, we need to set D-bit for any slots
8043 * with dirty logging disabled in order to eliminate unnecessary GPA
8044 * logging in PML buffer (and potential PML buffer full VMEXT). This
8045 * guarantees leaving PML enabled during guest's lifetime won't have
8046 * any additonal overhead from PML when guest is running with dirty
8047 * logging disabled for memory slots.
8048 *
8049 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8050 * to dirty logging mode.
8051 *
8052 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8053 *
8054 * In case of write protect:
8055 *
8056 * Write protect all pages for dirty logging.
8057 *
8058 * All the sptes including the large sptes which point to this
8059 * slot are set to readonly. We can not create any new large
8060 * spte on this slot until the end of the logging.
8061 *
8062 * See the comments in fast_page_fault().
8063 */
8064 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8065 if (kvm_x86_ops->slot_enable_log_dirty)
8066 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8067 else
8068 kvm_mmu_slot_remove_write_access(kvm, new);
8069 } else {
8070 if (kvm_x86_ops->slot_disable_log_dirty)
8071 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8072 }
8073}
8074
f7784b8e 8075void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8076 const struct kvm_userspace_memory_region *mem,
8482644a 8077 const struct kvm_memory_slot *old,
f36f3f28 8078 const struct kvm_memory_slot *new,
8482644a 8079 enum kvm_mr_change change)
f7784b8e 8080{
8482644a 8081 int nr_mmu_pages = 0;
f7784b8e 8082
48c0e4e9
XG		 8083 if (!kvm->arch.n_requested_mmu_pages)
8084 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8085
48c0e4e9 8086 if (nr_mmu_pages)
0de10343 8087 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8088
3ea3b7fa
WL		 8089 /*
8090 * Dirty logging tracks sptes in 4k granularity, meaning that large
8091 * sptes have to be split. If live migration is successful, the guest
8092 * in the source machine will be destroyed and large sptes will be
8093 * created in the destination. However, if the guest continues to run
8094 * in the source machine (for example if live migration fails), small
8095 * sptes will remain around and cause bad performance.
8096 *
8097 * Scan sptes if dirty logging has been stopped, dropping those
8098 * which can be collapsed into a single large-page spte. Later
8099 * page faults will create the large-page sptes.
8100 */
8101 if ((change != KVM_MR_DELETE) &&
8102 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8103 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8104 kvm_mmu_zap_collapsible_sptes(kvm, new);
8105
c972f3b1 8106 /*
88178fd4 8107 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8108 *
88178fd4
KH		 8109 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8110 * been zapped so no dirty logging staff is needed for old slot. For
8111 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8112 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8113 *
8114 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8115 */
88178fd4 8116 if (change != KVM_MR_DELETE)
f36f3f28 8117 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8118}
1d737c8a 8119
2df72e9b 8120void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8121{
6ca18b69 8122 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8123}
8124
2df72e9b
MT		 8125void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8126 struct kvm_memory_slot *slot)
8127{
6ca18b69 8128 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8129}
8130
5d9bc648
PB		 8131static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8132{
8133 if (!list_empty_careful(&vcpu->async_pf.done))
8134 return true;
8135
8136 if (kvm_apic_has_events(vcpu))
8137 return true;
8138
8139 if (vcpu->arch.pv.pv_unhalted)
8140 return true;
8141
8142 if (atomic_read(&vcpu->arch.nmi_queued))
8143 return true;
8144
73917739
PB		 8145 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8146 return true;
8147
5d9bc648
PB		 8148 if (kvm_arch_interrupt_allowed(vcpu) &&
8149 kvm_cpu_has_interrupt(vcpu))
8150 return true;
8151
1f4b34f8
AS		 8152 if (kvm_hv_has_stimer_pending(vcpu))
8153 return true;
8154
5d9bc648
PB		 8155 return false;
8156}
8157
1d737c8a
ZX		 8158int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8159{
b6b8a145
JK		 8160 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8161 kvm_x86_ops->check_nested_events(vcpu, false);
8162
5d9bc648 8163 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8164}
5736199a 8165
b6d33834 8166int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8167{
b6d33834 8168 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8169}
78646121
GN		 8170
8171int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8172{
8173 return kvm_x86_ops->interrupt_allowed(vcpu);
8174}
229456fc 8175
82b32774 8176unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8177{
82b32774
NA		 8178 if (is_64_bit_mode(vcpu))
8179 return kvm_rip_read(vcpu);
8180 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8181 kvm_rip_read(vcpu));
8182}
8183EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8184
82b32774
NA		 8185bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8186{
8187 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8188}
8189EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8190
94fe45da
JK		 8191unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8192{
8193 unsigned long rflags;
8194
8195 rflags = kvm_x86_ops->get_rflags(vcpu);
8196 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8197 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8198 return rflags;
8199}
8200EXPORT_SYMBOL_GPL(kvm_get_rflags);
8201
6addfc42 8202static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8203{
8204 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8205 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8206 rflags |= X86_EFLAGS_TF;
94fe45da 8207 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8208}
8209
8210void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8211{
8212 __kvm_set_rflags(vcpu, rflags);
3842d135 8213 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8214}
8215EXPORT_SYMBOL_GPL(kvm_set_rflags);
8216
56028d08
GN		 8217void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8218{
8219 int r;
8220
fb67e14f 8221 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8222 work->wakeup_all)
56028d08
GN		 8223 return;
8224
8225 r = kvm_mmu_reload(vcpu);
8226 if (unlikely(r))
8227 return;
8228
fb67e14f
XG		 8229 if (!vcpu->arch.mmu.direct_map &&
8230 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8231 return;
8232
56028d08
GN		 8233 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8234}
8235
af585b92
GN		 8236static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8237{
8238 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8239}
8240
8241static inline u32 kvm_async_pf_next_probe(u32 key)
8242{
8243 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8244}
8245
8246static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8247{
8248 u32 key = kvm_async_pf_hash_fn(gfn);
8249
8250 while (vcpu->arch.apf.gfns[key] != ~0)
8251 key = kvm_async_pf_next_probe(key);
8252
8253 vcpu->arch.apf.gfns[key] = gfn;
8254}
8255
8256static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8257{
8258 int i;
8259 u32 key = kvm_async_pf_hash_fn(gfn);
8260
8261 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8262 (vcpu->arch.apf.gfns[key] != gfn &&
8263 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8264 key = kvm_async_pf_next_probe(key);
8265
8266 return key;
8267}
8268
8269bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8270{
8271 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8272}
8273
8274static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8275{
8276 u32 i, j, k;
8277
8278 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8279 while (true) {
8280 vcpu->arch.apf.gfns[i] = ~0;
8281 do {
8282 j = kvm_async_pf_next_probe(j);
8283 if (vcpu->arch.apf.gfns[j] == ~0)
8284 return;
8285 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8286 /*
8287 * k lies cyclically in ]i,j]
8288 * | i.k.j |
8289 * |....j i.k.| or |.k..j i...|
8290 */
8291 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8292 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8293 i = j;
8294 }
8295}
8296
7c90705b
GN		 8297static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8298{
8299
8300 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8301 sizeof(val));
8302}
8303
af585b92
GN		 8304void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8305 struct kvm_async_pf *work)
8306{
6389ee94
AK		 8307 struct x86_exception fault;
8308
7c90705b 8309 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8310 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8311
8312 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8313 (vcpu->arch.apf.send_user_only &&
8314 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8315 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8316 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8317 fault.vector = PF_VECTOR;
8318 fault.error_code_valid = true;
8319 fault.error_code = 0;
8320 fault.nested_page_fault = false;
8321 fault.address = work->arch.token;
8322 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8323 }
af585b92
GN		 8324}
8325
8326void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8327 struct kvm_async_pf *work)
8328{
6389ee94
AK		 8329 struct x86_exception fault;
8330
7c90705b 8331 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8332 if (work->wakeup_all)
7c90705b
GN		 8333 work->arch.token = ~0; /* broadcast wakeup */
8334 else
8335 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8336
8337 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8338 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8339 fault.vector = PF_VECTOR;
8340 fault.error_code_valid = true;
8341 fault.error_code = 0;
8342 fault.nested_page_fault = false;
8343 fault.address = work->arch.token;
8344 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8345 }
e6d53e3b 8346 vcpu->arch.apf.halted = false;
a4fa1635 8347 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8348}
8349
8350bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8351{
8352 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8353 return true;
8354 else
8355 return !kvm_event_needs_reinjection(vcpu) &&
8356 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8357}
8358
5544eb9b
PB		 8359void kvm_arch_start_assignment(struct kvm *kvm)
8360{
8361 atomic_inc(&kvm->arch.assigned_device_count);
8362}
8363EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8364
8365void kvm_arch_end_assignment(struct kvm *kvm)
8366{
8367 atomic_dec(&kvm->arch.assigned_device_count);
8368}
8369EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8370
8371bool kvm_arch_has_assigned_device(struct kvm *kvm)
8372{
8373 return atomic_read(&kvm->arch.assigned_device_count);
8374}
8375EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8376
e0f0bbc5
AW		 8377void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8378{
8379 atomic_inc(&kvm->arch.noncoherent_dma_count);
8380}
8381EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8382
8383void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8384{
8385 atomic_dec(&kvm->arch.noncoherent_dma_count);
8386}
8387EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8388
8389bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8390{
8391 return atomic_read(&kvm->arch.noncoherent_dma_count);
8392}
8393EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8394
14717e20
AW		 8395bool kvm_arch_has_irq_bypass(void)
8396{
8397 return kvm_x86_ops->update_pi_irte != NULL;
8398}
8399
87276880
FW		 8400int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8401 struct irq_bypass_producer *prod)
8402{
8403 struct kvm_kernel_irqfd *irqfd =
8404 container_of(cons, struct kvm_kernel_irqfd, consumer);
8405
14717e20 8406 irqfd->producer = prod;
87276880 8407
14717e20
AW		 8408 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8409 prod->irq, irqfd->gsi, 1);
87276880
FW		 8410}
8411
8412void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8413 struct irq_bypass_producer *prod)
8414{
8415 int ret;
8416 struct kvm_kernel_irqfd *irqfd =
8417 container_of(cons, struct kvm_kernel_irqfd, consumer);
8418
87276880
FW		 8419 WARN_ON(irqfd->producer != prod);
8420 irqfd->producer = NULL;
8421
8422 /*
8423 * When producer of consumer is unregistered, we change back to
8424 * remapped mode, so we can re-use the current implementation
bb3541f1 8425 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8426 * int this case doesn't want to receive the interrupts.
8427 */
8428 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8429 if (ret)
8430 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8431 " fails: %d\n", irqfd->consumer.token, ret);
8432}
8433
8434int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8435 uint32_t guest_irq, bool set)
8436{
8437 if (!kvm_x86_ops->update_pi_irte)
8438 return -EINVAL;
8439
8440 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8441}
8442
52004014
FW		 8443bool kvm_vector_hashing_enabled(void)
8444{
8445 return vector_hashing;
8446}
8447EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8448
229456fc 8449EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8450EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8451EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8452EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8453EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8454EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8455EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8456EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8457EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8458EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8459EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8460EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8461EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8462EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8463EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8464EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8465EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8466EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8467EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)