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KVM: X86: introduce invalidate_gpa argument to tlb flush
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
d1898b73
DH		 71#define CREATE_TRACE_POINTS
72#include "trace.h"
73
313a3dc7 74#define MAX_IO_MSRS 256
890ca9ae 75#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 76u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 78
0f65dd70
AK		 79#define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
50a37eb4
JR		 82/* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86#ifdef CONFIG_X86_64
1260edbe
LJ		 87static
88u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 89#else
1260edbe 90static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 91#endif
313a3dc7 92
ba1389b7
AK		 93#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 95
c519265f
RK		 96#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 98
cb142eb7 99static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 100static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 101static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 102static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 103
893590c7 104struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 105EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 106
893590c7 107static bool __read_mostly ignore_msrs = 0;
476bc001 108module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 109
fab0aa3b
EM		 110static bool __read_mostly report_ignored_msrs = true;
111module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
112
9ed96e87
MT		 113unsigned int min_timer_period_us = 500;
114module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
115
630994b3
MT		 116static bool __read_mostly kvmclock_periodic_sync = true;
117module_param(kvmclock_periodic_sync, bool, S_IRUGO);
118
893590c7 119bool __read_mostly kvm_has_tsc_control;
92a1f12d 120EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 121u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 122EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 123u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
124EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
125u64 __read_mostly kvm_max_tsc_scaling_ratio;
126EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 127u64 __read_mostly kvm_default_tsc_scaling_ratio;
128EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 129
cc578287 130/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 131static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 132module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
133
d0659d94 134/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 135unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 136module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
137
52004014
FW		 138static bool __read_mostly vector_hashing = true;
139module_param(vector_hashing, bool, S_IRUGO);
140
18863bdd
AK		 141#define KVM_NR_SHARED_MSRS 16
142
143struct kvm_shared_msrs_global {
144 int nr;
2bf78fa7 145 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 146};
147
148struct kvm_shared_msrs {
149 struct user_return_notifier urn;
150 bool registered;
2bf78fa7
SY		 151 struct kvm_shared_msr_values {
152 u64 host;
153 u64 curr;
154 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 155};
156
157static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 158static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 159
417bc304 160struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 161 { "pf_fixed", VCPU_STAT(pf_fixed) },
162 { "pf_guest", VCPU_STAT(pf_guest) },
163 { "tlb_flush", VCPU_STAT(tlb_flush) },
164 { "invlpg", VCPU_STAT(invlpg) },
165 { "exits", VCPU_STAT(exits) },
166 { "io_exits", VCPU_STAT(io_exits) },
167 { "mmio_exits", VCPU_STAT(mmio_exits) },
168 { "signal_exits", VCPU_STAT(signal_exits) },
169 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 170 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 171 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 175 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 176 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 177 { "request_irq", VCPU_STAT(request_irq_exits) },
178 { "irq_exits", VCPU_STAT(irq_exits) },
179 { "host_state_reload", VCPU_STAT(host_state_reload) },
180 { "efer_reload", VCPU_STAT(efer_reload) },
181 { "fpu_reload", VCPU_STAT(fpu_reload) },
182 { "insn_emulation", VCPU_STAT(insn_emulation) },
183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 184 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 185 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 186 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 187 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
188 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
189 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
190 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
191 { "mmu_flooded", VM_STAT(mmu_flooded) },
192 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 193 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 194 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 195 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 196 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 197 { "max_mmu_page_hash_collisions",
198 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 199 { NULL }
200};
201
2acf923e
DC		 202u64 __read_mostly host_xcr0;
203
b6785def 204static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 205
af585b92
GN		 206static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
207{
208 int i;
209 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
210 vcpu->arch.apf.gfns[i] = ~0;
211}
212
18863bdd
AK		 213static void kvm_on_user_return(struct user_return_notifier *urn)
214{
215 unsigned slot;
18863bdd
AK		 216 struct kvm_shared_msrs *locals
217 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 218 struct kvm_shared_msr_values *values;
1650b4eb
IA		 219 unsigned long flags;
220
221 /*
222 * Disabling irqs at this point since the following code could be
223 * interrupted and executed through kvm_arch_hardware_disable()
224 */
225 local_irq_save(flags);
226 if (locals->registered) {
227 locals->registered = false;
228 user_return_notifier_unregister(urn);
229 }
230 local_irq_restore(flags);
18863bdd 231 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 232 values = &locals->values[slot];
233 if (values->host != values->curr) {
234 wrmsrl(shared_msrs_global.msrs[slot], values->host);
235 values->curr = values->host;
18863bdd
AK		 236 }
237 }
18863bdd
AK		 238}
239
2bf78fa7 240static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 241{
18863bdd 242 u64 value;
013f6a5d
MT		 243 unsigned int cpu = smp_processor_id();
244 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 245
2bf78fa7
SY		 246 /* only read, and nobody should modify it at this time,
247 * so don't need lock */
248 if (slot >= shared_msrs_global.nr) {
249 printk(KERN_ERR "kvm: invalid MSR slot!");
250 return;
251 }
252 rdmsrl_safe(msr, &value);
253 smsr->values[slot].host = value;
254 smsr->values[slot].curr = value;
255}
256
257void kvm_define_shared_msr(unsigned slot, u32 msr)
258{
0123be42 259 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 260 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 261 if (slot >= shared_msrs_global.nr)
262 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 263}
264EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
265
266static void kvm_shared_msr_cpu_online(void)
267{
268 unsigned i;
18863bdd
AK		 269
270 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 271 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 272}
273
8b3c3104 274int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 275{
013f6a5d
MT		 276 unsigned int cpu = smp_processor_id();
277 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 278 int err;
18863bdd 279
2bf78fa7 280 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 281 return 0;
2bf78fa7 282 smsr->values[slot].curr = value;
8b3c3104
AH		 283 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
284 if (err)
285 return 1;
286
18863bdd
AK		 287 if (!smsr->registered) {
288 smsr->urn.on_user_return = kvm_on_user_return;
289 user_return_notifier_register(&smsr->urn);
290 smsr->registered = true;
291 }
8b3c3104 292 return 0;
18863bdd
AK		 293}
294EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
295
13a34e06 296static void drop_user_return_notifiers(void)
3548bab5 297{
013f6a5d
MT		 298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 300
301 if (smsr->registered)
302 kvm_on_user_return(&smsr->urn);
303}
304
6866b83e
CO		 305u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
306{
8a5a87d9 307 return vcpu->arch.apic_base;
6866b83e
CO		 308}
309EXPORT_SYMBOL_GPL(kvm_get_apic_base);
310
58cb628d
JK		 311int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
312{
313 u64 old_state = vcpu->arch.apic_base &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 new_state = msr_info->data &
316 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 317 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
318 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 319
d3802286
JM		 320 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
321 return 1;
58cb628d 322 if (!msr_info->host_initiated &&
d3802286 323 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 324 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
325 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
326 old_state == 0)))
327 return 1;
328
329 kvm_lapic_set_base(vcpu, msr_info->data);
330 return 0;
6866b83e
CO		 331}
332EXPORT_SYMBOL_GPL(kvm_set_apic_base);
333
2605fc21 334asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 335{
336 /* Fault while not rebooting. We want the trace. */
337 BUG();
338}
339EXPORT_SYMBOL_GPL(kvm_spurious_fault);
340
3fd28fce
ED		 341#define EXCPT_BENIGN 0
342#define EXCPT_CONTRIBUTORY 1
343#define EXCPT_PF 2
344
345static int exception_class(int vector)
346{
347 switch (vector) {
348 case PF_VECTOR:
349 return EXCPT_PF;
350 case DE_VECTOR:
351 case TS_VECTOR:
352 case NP_VECTOR:
353 case SS_VECTOR:
354 case GP_VECTOR:
355 return EXCPT_CONTRIBUTORY;
356 default:
357 break;
358 }
359 return EXCPT_BENIGN;
360}
361
d6e8c854
NA		 362#define EXCPT_FAULT 0
363#define EXCPT_TRAP 1
364#define EXCPT_ABORT 2
365#define EXCPT_INTERRUPT 3
366
367static int exception_type(int vector)
368{
369 unsigned int mask;
370
371 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
372 return EXCPT_INTERRUPT;
373
374 mask = 1 << vector;
375
376 /* #DB is trap, as instruction watchpoints are handled elsewhere */
377 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
378 return EXCPT_TRAP;
379
380 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
381 return EXCPT_ABORT;
382
383 /* Reserved exceptions will result in fault */
384 return EXCPT_FAULT;
385}
386
3fd28fce 387static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 388 unsigned nr, bool has_error, u32 error_code,
389 bool reinject)
3fd28fce
ED		 390{
391 u32 prev_nr;
392 int class1, class2;
393
3842d135
AK		 394 kvm_make_request(KVM_REQ_EVENT, vcpu);
395
664f8e26 396 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 397 queue:
3ffb2468
NA		 398 if (has_error && !is_protmode(vcpu))
399 has_error = false;
664f8e26
WL		 400 if (reinject) {
401 /*
402 * On vmentry, vcpu->arch.exception.pending is only
403 * true if an event injection was blocked by
404 * nested_run_pending. In that case, however,
405 * vcpu_enter_guest requests an immediate exit,
406 * and the guest shouldn't proceed far enough to
407 * need reinjection.
408 */
409 WARN_ON_ONCE(vcpu->arch.exception.pending);
410 vcpu->arch.exception.injected = true;
411 } else {
412 vcpu->arch.exception.pending = true;
413 vcpu->arch.exception.injected = false;
414 }
3fd28fce
ED		 415 vcpu->arch.exception.has_error_code = has_error;
416 vcpu->arch.exception.nr = nr;
417 vcpu->arch.exception.error_code = error_code;
418 return;
419 }
420
421 /* to check exception */
422 prev_nr = vcpu->arch.exception.nr;
423 if (prev_nr == DF_VECTOR) {
424 /* triple fault -> shutdown */
a8eeb04a 425 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 426 return;
427 }
428 class1 = exception_class(prev_nr);
429 class2 = exception_class(nr);
430 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
431 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 432 /*
433 * Generate double fault per SDM Table 5-5. Set
434 * exception.pending = true so that the double fault
435 * can trigger a nested vmexit.
436 */
3fd28fce 437 vcpu->arch.exception.pending = true;
664f8e26 438 vcpu->arch.exception.injected = false;
3fd28fce
ED		 439 vcpu->arch.exception.has_error_code = true;
440 vcpu->arch.exception.nr = DF_VECTOR;
441 vcpu->arch.exception.error_code = 0;
442 } else
443 /* replace previous exception with a new one in a hope
444 that instruction re-execution will regenerate lost
445 exception */
446 goto queue;
447}
448
298101da
AK		 449void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
450{
ce7ddec4 451 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 452}
453EXPORT_SYMBOL_GPL(kvm_queue_exception);
454
ce7ddec4
JR		 455void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
456{
457 kvm_multiple_exception(vcpu, nr, false, 0, true);
458}
459EXPORT_SYMBOL_GPL(kvm_requeue_exception);
460
6affcbed 461int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 462{
db8fcefa
AP		 463 if (err)
464 kvm_inject_gp(vcpu, 0);
465 else
6affcbed
KH		 466 return kvm_skip_emulated_instruction(vcpu);
467
468 return 1;
db8fcefa
AP		 469}
470EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 471
6389ee94 472void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 473{
474 ++vcpu->stat.pf_guest;
adfe20fb
WL		 475 vcpu->arch.exception.nested_apf =
476 is_guest_mode(vcpu) && fault->async_page_fault;
477 if (vcpu->arch.exception.nested_apf)
478 vcpu->arch.apf.nested_apf_token = fault->address;
479 else
480 vcpu->arch.cr2 = fault->address;
6389ee94 481 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 482}
27d6c865 483EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 484
ef54bcfe 485static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 486{
6389ee94
AK		 487 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
488 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 489 else
6389ee94 490 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 491
492 return fault->nested_page_fault;
d4f8cf66
JR		 493}
494
3419ffc8
SY		 495void kvm_inject_nmi(struct kvm_vcpu *vcpu)
496{
7460fb4a
AK		 497 atomic_inc(&vcpu->arch.nmi_queued);
498 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 499}
500EXPORT_SYMBOL_GPL(kvm_inject_nmi);
501
298101da
AK		 502void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
503{
ce7ddec4 504 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 505}
506EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
507
ce7ddec4
JR		 508void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
509{
510 kvm_multiple_exception(vcpu, nr, true, error_code, true);
511}
512EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
513
0a79b009
AK		 514/*
515 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
516 * a #GP and return false.
517 */
518bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 519{
0a79b009
AK		 520 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
521 return true;
522 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
523 return false;
298101da 524}
0a79b009 525EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 526
16f8a6f9
NA		 527bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
528{
529 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
530 return true;
531
532 kvm_queue_exception(vcpu, UD_VECTOR);
533 return false;
534}
535EXPORT_SYMBOL_GPL(kvm_require_dr);
536
ec92fe44
JR		 537/*
538 * This function will be used to read from the physical memory of the currently
54bf36aa 539 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 540 * can read from guest physical or from the guest's guest physical memory.
541 */
542int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
543 gfn_t ngfn, void *data, int offset, int len,
544 u32 access)
545{
54987b7a 546 struct x86_exception exception;
ec92fe44
JR		 547 gfn_t real_gfn;
548 gpa_t ngpa;
549
550 ngpa = gfn_to_gpa(ngfn);
54987b7a 551 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 552 if (real_gfn == UNMAPPED_GVA)
553 return -EFAULT;
554
555 real_gfn = gpa_to_gfn(real_gfn);
556
54bf36aa 557 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 558}
559EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
560
69b0049a 561static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 562 void *data, int offset, int len, u32 access)
563{
564 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
565 data, offset, len, access);
566}
567
a03490ed
CO		 568/*
569 * Load the pae pdptrs. Return true is they are all valid.
570 */
ff03a073 571int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 572{
573 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
574 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
575 int i;
576 int ret;
ff03a073 577 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 578
ff03a073
JR		 579 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
580 offset * sizeof(u64), sizeof(pdpte),
581 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 582 if (ret < 0) {
583 ret = 0;
584 goto out;
585 }
586 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 587 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 588 (pdpte[i] &
589 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 590 ret = 0;
591 goto out;
592 }
593 }
594 ret = 1;
595
ff03a073 596 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 597 __set_bit(VCPU_EXREG_PDPTR,
598 (unsigned long *)&vcpu->arch.regs_avail);
599 __set_bit(VCPU_EXREG_PDPTR,
600 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 601out:
a03490ed
CO		 602
603 return ret;
604}
cc4b6871 605EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 606
9ed38ffa 607bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 608{
ff03a073 609 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 610 bool changed = true;
3d06b8bf
JR		 611 int offset;
612 gfn_t gfn;
d835dfec
AK		 613 int r;
614
615 if (is_long_mode(vcpu) || !is_pae(vcpu))
616 return false;
617
6de4f3ad
AK		 618 if (!test_bit(VCPU_EXREG_PDPTR,
619 (unsigned long *)&vcpu->arch.regs_avail))
620 return true;
621
a512177e
PB		 622 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
623 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 624 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
625 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 626 if (r < 0)
627 goto out;
ff03a073 628 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 629out:
d835dfec
AK		 630
631 return changed;
632}
9ed38ffa 633EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 634
49a9b07e 635int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 636{
aad82703 637 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 638 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 639
f9a48e6a
AK		 640 cr0 |= X86_CR0_ET;
641
ab344828 642#ifdef CONFIG_X86_64
0f12244f
GN		 643 if (cr0 & 0xffffffff00000000UL)
644 return 1;
ab344828
GN		 645#endif
646
647 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 648
0f12244f
GN		 649 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
650 return 1;
a03490ed 651
0f12244f
GN		 652 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
653 return 1;
a03490ed
CO		 654
655 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
656#ifdef CONFIG_X86_64
f6801dff 657 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 658 int cs_db, cs_l;
659
0f12244f
GN		 660 if (!is_pae(vcpu))
661 return 1;
a03490ed 662 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 663 if (cs_l)
664 return 1;
a03490ed
CO		 665 } else
666#endif
ff03a073 667 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 668 kvm_read_cr3(vcpu)))
0f12244f 669 return 1;
a03490ed
CO		 670 }
671
ad756a16
MJ		 672 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
673 return 1;
674
a03490ed 675 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 676
d170c419 677 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 678 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 679 kvm_async_pf_hash_reset(vcpu);
680 }
e5f3f027 681
aad82703
SY		 682 if ((cr0 ^ old_cr0) & update_bits)
683 kvm_mmu_reset_context(vcpu);
b18d5431 684
879ae188
LE		 685 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
686 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
687 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 688 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
689
0f12244f
GN		 690 return 0;
691}
2d3ad1f4 692EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 693
2d3ad1f4 694void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 695{
49a9b07e 696 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 697}
2d3ad1f4 698EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 699
42bdf991
MT		 700static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
701{
702 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
703 !vcpu->guest_xcr0_loaded) {
704 /* kvm_set_xcr() also depends on this */
705 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
706 vcpu->guest_xcr0_loaded = 1;
707 }
708}
709
710static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
711{
712 if (vcpu->guest_xcr0_loaded) {
713 if (vcpu->arch.xcr0 != host_xcr0)
714 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
715 vcpu->guest_xcr0_loaded = 0;
716 }
717}
718
69b0049a 719static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 720{
56c103ec
LJ		 721 u64 xcr0 = xcr;
722 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 723 u64 valid_bits;
2acf923e
DC		 724
725 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
726 if (index != XCR_XFEATURE_ENABLED_MASK)
727 return 1;
d91cab78 728 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 729 return 1;
d91cab78 730 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 731 return 1;
46c34cb0
PB		 732
733 /*
734 * Do not allow the guest to set bits that we do not support
735 * saving. However, xcr0 bit 0 is always set, even if the
736 * emulated CPU does not support XSAVE (see fx_init).
737 */
d91cab78 738 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 739 if (xcr0 & ~valid_bits)
2acf923e 740 return 1;
46c34cb0 741
d91cab78
DH		 742 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
743 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 744 return 1;
745
d91cab78
DH		 746 if (xcr0 & XFEATURE_MASK_AVX512) {
747 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 748 return 1;
d91cab78 749 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 750 return 1;
751 }
2acf923e 752 vcpu->arch.xcr0 = xcr0;
56c103ec 753
d91cab78 754 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 755 kvm_update_cpuid(vcpu);
2acf923e
DC		 756 return 0;
757}
758
759int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
760{
764bcbc5
Z		 761 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
762 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 763 kvm_inject_gp(vcpu, 0);
764 return 1;
765 }
766 return 0;
767}
768EXPORT_SYMBOL_GPL(kvm_set_xcr);
769
a83b29c6 770int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 771{
fc78f519 772 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 773 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 774 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 775
0f12244f
GN		 776 if (cr4 & CR4_RESERVED_BITS)
777 return 1;
a03490ed 778
d6321d49 779 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 780 return 1;
781
d6321d49 782 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 783 return 1;
784
d6321d49 785 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 786 return 1;
787
d6321d49 788 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 789 return 1;
790
d6321d49 791 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 792 return 1;
793
fd8cb433 794 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 795 return 1;
796
ae3e61e1
PB		 797 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
798 return 1;
799
a03490ed 800 if (is_long_mode(vcpu)) {
0f12244f
GN		 801 if (!(cr4 & X86_CR4_PAE))
802 return 1;
a2edf57f
AK		 803 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
804 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 805 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
806 kvm_read_cr3(vcpu)))
0f12244f
GN		 807 return 1;
808
ad756a16 809 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 810 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 811 return 1;
812
813 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
814 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
815 return 1;
816 }
817
5e1746d6 818 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 819 return 1;
a03490ed 820
ad756a16
MJ		 821 if (((cr4 ^ old_cr4) & pdptr_bits) ||
822 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 823 kvm_mmu_reset_context(vcpu);
0f12244f 824
b9baba86 825 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 826 kvm_update_cpuid(vcpu);
2acf923e 827
0f12244f
GN		 828 return 0;
829}
2d3ad1f4 830EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 831
2390218b 832int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 833{
ac146235 834#ifdef CONFIG_X86_64
9d88fca7 835 cr3 &= ~CR3_PCID_INVD;
ac146235 836#endif
9d88fca7 837
9f8fe504 838 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 839 kvm_mmu_sync_roots(vcpu);
77c3913b 840 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 841 return 0;
d835dfec
AK		 842 }
843
d1cd3ce9
YZ		 844 if (is_long_mode(vcpu) &&
845 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
846 return 1;
847 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 848 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 849 return 1;
a03490ed 850
0f12244f 851 vcpu->arch.cr3 = cr3;
aff48baa 852 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 853 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 854 return 0;
855}
2d3ad1f4 856EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 857
eea1cff9 858int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 859{
0f12244f
GN		 860 if (cr8 & CR8_RESERVED_BITS)
861 return 1;
35754c98 862 if (lapic_in_kernel(vcpu))
a03490ed
CO		 863 kvm_lapic_set_tpr(vcpu, cr8);
864 else
ad312c7c 865 vcpu->arch.cr8 = cr8;
0f12244f
GN		 866 return 0;
867}
2d3ad1f4 868EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 869
2d3ad1f4 870unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 871{
35754c98 872 if (lapic_in_kernel(vcpu))
a03490ed
CO		 873 return kvm_lapic_get_cr8(vcpu);
874 else
ad312c7c 875 return vcpu->arch.cr8;
a03490ed 876}
2d3ad1f4 877EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 878
ae561ede
NA		 879static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
880{
881 int i;
882
883 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
884 for (i = 0; i < KVM_NR_DB_REGS; i++)
885 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
886 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
887 }
888}
889
73aaf249
JK		 890static void kvm_update_dr6(struct kvm_vcpu *vcpu)
891{
892 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
893 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
894}
895
c8639010
JK		 896static void kvm_update_dr7(struct kvm_vcpu *vcpu)
897{
898 unsigned long dr7;
899
900 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
901 dr7 = vcpu->arch.guest_debug_dr7;
902 else
903 dr7 = vcpu->arch.dr7;
904 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 905 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
906 if (dr7 & DR7_BP_EN_MASK)
907 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 908}
909
6f43ed01
NA		 910static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
911{
912 u64 fixed = DR6_FIXED_1;
913
d6321d49 914 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 915 fixed |= DR6_RTM;
916 return fixed;
917}
918
338dbc97 919static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 920{
921 switch (dr) {
922 case 0 ... 3:
923 vcpu->arch.db[dr] = val;
924 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
925 vcpu->arch.eff_db[dr] = val;
926 break;
927 case 4:
020df079
GN		 928 /* fall through */
929 case 6:
338dbc97
GN		 930 if (val & 0xffffffff00000000ULL)
931 return -1; /* #GP */
6f43ed01 932 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 933 kvm_update_dr6(vcpu);
020df079
GN		 934 break;
935 case 5:
020df079
GN		 936 /* fall through */
937 default: /* 7 */
338dbc97
GN		 938 if (val & 0xffffffff00000000ULL)
939 return -1; /* #GP */
020df079 940 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 941 kvm_update_dr7(vcpu);
020df079
GN		 942 break;
943 }
944
945 return 0;
946}
338dbc97
GN		 947
948int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
949{
16f8a6f9 950 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 951 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 952 return 1;
953 }
954 return 0;
338dbc97 955}
020df079
GN		 956EXPORT_SYMBOL_GPL(kvm_set_dr);
957
16f8a6f9 958int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 959{
960 switch (dr) {
961 case 0 ... 3:
962 *val = vcpu->arch.db[dr];
963 break;
964 case 4:
020df079
GN		 965 /* fall through */
966 case 6:
73aaf249
JK		 967 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
968 *val = vcpu->arch.dr6;
969 else
970 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 971 break;
972 case 5:
020df079
GN		 973 /* fall through */
974 default: /* 7 */
975 *val = vcpu->arch.dr7;
976 break;
977 }
338dbc97
GN		 978 return 0;
979}
020df079
GN		 980EXPORT_SYMBOL_GPL(kvm_get_dr);
981
022cd0e8
AK		 982bool kvm_rdpmc(struct kvm_vcpu *vcpu)
983{
984 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
985 u64 data;
986 int err;
987
c6702c9d 988 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 989 if (err)
990 return err;
991 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
992 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
993 return err;
994}
995EXPORT_SYMBOL_GPL(kvm_rdpmc);
996
043405e1
CO		 997/*
998 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
999 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1000 *
1001 * This list is modified at module load time to reflect the
e3267cbb 1002 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1003 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1004 * may depend on host virtualization features rather than host cpu features.
043405e1 1005 */
e3267cbb 1006
043405e1
CO		 1007static u32 msrs_to_save[] = {
1008 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1009 MSR_STAR,
043405e1
CO		 1010#ifdef CONFIG_X86_64
1011 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1012#endif
b3897a49 1013 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1014 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 1015};
1016
1017static unsigned num_msrs_to_save;
1018
62ef68bb
PB		 1019static u32 emulated_msrs[] = {
1020 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1021 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1022 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1023 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1024 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1025 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1026 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1027 HV_X64_MSR_RESET,
11c4b1ca 1028 HV_X64_MSR_VP_INDEX,
9eec50b8 1029 HV_X64_MSR_VP_RUNTIME,
5c919412 1030 HV_X64_MSR_SCONTROL,
1f4b34f8 1031 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1032 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1033 MSR_KVM_PV_EOI_EN,
1034
ba904635 1035 MSR_IA32_TSC_ADJUST,
a3e06bbe 1036 MSR_IA32_TSCDEADLINE,
043405e1 1037 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1038 MSR_IA32_MCG_STATUS,
1039 MSR_IA32_MCG_CTL,
c45dcc71 1040 MSR_IA32_MCG_EXT_CTL,
64d60670 1041 MSR_IA32_SMBASE,
52797bf9 1042 MSR_SMI_COUNT,
db2336a8
KH		 1043 MSR_PLATFORM_INFO,
1044 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1045};
1046
62ef68bb
PB		 1047static unsigned num_emulated_msrs;
1048
384bb783 1049bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1050{
b69e8cae 1051 if (efer & efer_reserved_bits)
384bb783 1052 return false;
15c4a640 1053
1b4d56b8 1054 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1055 return false;
1b2fd70c 1056
1b4d56b8 1057 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1058 return false;
d8017474 1059
384bb783
JK		 1060 return true;
1061}
1062EXPORT_SYMBOL_GPL(kvm_valid_efer);
1063
1064static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1065{
1066 u64 old_efer = vcpu->arch.efer;
1067
1068 if (!kvm_valid_efer(vcpu, efer))
1069 return 1;
1070
1071 if (is_paging(vcpu)
1072 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1073 return 1;
1074
15c4a640 1075 efer &= ~EFER_LMA;
f6801dff 1076 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1077
a3d204e2
SY		 1078 kvm_x86_ops->set_efer(vcpu, efer);
1079
aad82703
SY		 1080 /* Update reserved bits */
1081 if ((efer ^ old_efer) & EFER_NX)
1082 kvm_mmu_reset_context(vcpu);
1083
b69e8cae 1084 return 0;
15c4a640
CO		 1085}
1086
f2b4b7dd
JR		 1087void kvm_enable_efer_bits(u64 mask)
1088{
1089 efer_reserved_bits &= ~mask;
1090}
1091EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1092
15c4a640
CO		 1093/*
1094 * Writes msr value into into the appropriate "register".
1095 * Returns 0 on success, non-0 otherwise.
1096 * Assumes vcpu_load() was already called.
1097 */
8fe8ab46 1098int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1099{
854e8bb1
NA		 1100 switch (msr->index) {
1101 case MSR_FS_BASE:
1102 case MSR_GS_BASE:
1103 case MSR_KERNEL_GS_BASE:
1104 case MSR_CSTAR:
1105 case MSR_LSTAR:
fd8cb433 1106 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1107 return 1;
1108 break;
1109 case MSR_IA32_SYSENTER_EIP:
1110 case MSR_IA32_SYSENTER_ESP:
1111 /*
1112 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1113 * non-canonical address is written on Intel but not on
1114 * AMD (which ignores the top 32-bits, because it does
1115 * not implement 64-bit SYSENTER).
1116 *
1117 * 64-bit code should hence be able to write a non-canonical
1118 * value on AMD. Making the address canonical ensures that
1119 * vmentry does not fail on Intel after writing a non-canonical
1120 * value, and that something deterministic happens if the guest
1121 * invokes 64-bit SYSENTER.
1122 */
fd8cb433 1123 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1124 }
8fe8ab46 1125 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1126}
854e8bb1 1127EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1128
313a3dc7
CO		 1129/*
1130 * Adapt set_msr() to msr_io()'s calling convention
1131 */
609e36d3
PB		 1132static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1133{
1134 struct msr_data msr;
1135 int r;
1136
1137 msr.index = index;
1138 msr.host_initiated = true;
1139 r = kvm_get_msr(vcpu, &msr);
1140 if (r)
1141 return r;
1142
1143 *data = msr.data;
1144 return 0;
1145}
1146
313a3dc7
CO		 1147static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1148{
8fe8ab46
WA		 1149 struct msr_data msr;
1150
1151 msr.data = *data;
1152 msr.index = index;
1153 msr.host_initiated = true;
1154 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1155}
1156
16e8d74d
MT		 1157#ifdef CONFIG_X86_64
1158struct pvclock_gtod_data {
1159 seqcount_t seq;
1160
1161 struct { /* extract of a clocksource struct */
1162 int vclock_mode;
a5a1d1c2
TG		 1163 u64 cycle_last;
1164 u64 mask;
16e8d74d
MT		 1165 u32 mult;
1166 u32 shift;
1167 } clock;
1168
cbcf2dd3
TG		 1169 u64 boot_ns;
1170 u64 nsec_base;
55dd00a7 1171 u64 wall_time_sec;
16e8d74d
MT		 1172};
1173
1174static struct pvclock_gtod_data pvclock_gtod_data;
1175
1176static void update_pvclock_gtod(struct timekeeper *tk)
1177{
1178 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1179 u64 boot_ns;
1180
876e7881 1181 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1182
1183 write_seqcount_begin(&vdata->seq);
1184
1185 /* copy pvclock gtod data */
876e7881
PZ		 1186 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1187 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1188 vdata->clock.mask = tk->tkr_mono.mask;
1189 vdata->clock.mult = tk->tkr_mono.mult;
1190 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1191
cbcf2dd3 1192 vdata->boot_ns = boot_ns;
876e7881 1193 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1194
55dd00a7
MT		 1195 vdata->wall_time_sec = tk->xtime_sec;
1196
16e8d74d
MT		 1197 write_seqcount_end(&vdata->seq);
1198}
1199#endif
1200
bab5bb39
NK		 1201void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1202{
1203 /*
1204 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1205 * vcpu_enter_guest. This function is only called from
1206 * the physical CPU that is running vcpu.
1207 */
1208 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1209}
16e8d74d 1210
18068523
GOC		 1211static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1212{
9ed3c444
AK		 1213 int version;
1214 int r;
50d0a0f9 1215 struct pvclock_wall_clock wc;
87aeb54f 1216 struct timespec64 boot;
18068523
GOC		 1217
1218 if (!wall_clock)
1219 return;
1220
9ed3c444
AK		 1221 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1222 if (r)
1223 return;
1224
1225 if (version & 1)
1226 ++version; /* first time write, random junk */
1227
1228 ++version;
18068523 1229
1dab1345
NK		 1230 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1231 return;
18068523 1232
50d0a0f9
GH		 1233 /*
1234 * The guest calculates current wall clock time by adding
34c238a1 1235 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1236 * wall clock specified here. guest system time equals host
1237 * system time for us, thus we must fill in host boot time here.
1238 */
87aeb54f 1239 getboottime64(&boot);
50d0a0f9 1240
4b648665 1241 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1242 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1243 boot = timespec64_sub(boot, ts);
4b648665 1244 }
87aeb54f 1245 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1246 wc.nsec = boot.tv_nsec;
1247 wc.version = version;
18068523
GOC		 1248
1249 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1250
1251 version++;
1252 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1253}
1254
50d0a0f9
GH		 1255static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1256{
b51012de
PB		 1257 do_shl32_div32(dividend, divisor);
1258 return dividend;
50d0a0f9
GH		 1259}
1260
3ae13faa 1261static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1262 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1263{
5f4e3f88 1264 uint64_t scaled64;
50d0a0f9
GH		 1265 int32_t shift = 0;
1266 uint64_t tps64;
1267 uint32_t tps32;
1268
3ae13faa
PB		 1269 tps64 = base_hz;
1270 scaled64 = scaled_hz;
50933623 1271 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1272 tps64 >>= 1;
1273 shift--;
1274 }
1275
1276 tps32 = (uint32_t)tps64;
50933623
JK		 1277 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1278 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1279 scaled64 >>= 1;
1280 else
1281 tps32 <<= 1;
50d0a0f9
GH		 1282 shift++;
1283 }
1284
5f4e3f88
ZA		 1285 *pshift = shift;
1286 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1287
3ae13faa
PB		 1288 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1289 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1290}
1291
d828199e 1292#ifdef CONFIG_X86_64
16e8d74d 1293static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1294#endif
16e8d74d 1295
c8076604 1296static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1297static unsigned long max_tsc_khz;
c8076604 1298
cc578287 1299static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1300{
cc578287
ZA		 1301 u64 v = (u64)khz * (1000000 + ppm);
1302 do_div(v, 1000000);
1303 return v;
1e993611
JR		 1304}
1305
381d585c
HZ		 1306static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1307{
1308 u64 ratio;
1309
1310 /* Guest TSC same frequency as host TSC? */
1311 if (!scale) {
1312 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1313 return 0;
1314 }
1315
1316 /* TSC scaling supported? */
1317 if (!kvm_has_tsc_control) {
1318 if (user_tsc_khz > tsc_khz) {
1319 vcpu->arch.tsc_catchup = 1;
1320 vcpu->arch.tsc_always_catchup = 1;
1321 return 0;
1322 } else {
1323 WARN(1, "user requested TSC rate below hardware speed\n");
1324 return -1;
1325 }
1326 }
1327
1328 /* TSC scaling required - calculate ratio */
1329 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1330 user_tsc_khz, tsc_khz);
1331
1332 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1333 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1334 user_tsc_khz);
1335 return -1;
1336 }
1337
1338 vcpu->arch.tsc_scaling_ratio = ratio;
1339 return 0;
1340}
1341
4941b8cb 1342static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1343{
cc578287
ZA		 1344 u32 thresh_lo, thresh_hi;
1345 int use_scaling = 0;
217fc9cf 1346
03ba32ca 1347 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1348 if (user_tsc_khz == 0) {
ad721883
HZ		 1349 /* set tsc_scaling_ratio to a safe value */
1350 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1351 return -1;
ad721883 1352 }
03ba32ca 1353
c285545f 1354 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1355 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1356 &vcpu->arch.virtual_tsc_shift,
1357 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1358 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1359
1360 /*
1361 * Compute the variation in TSC rate which is acceptable
1362 * within the range of tolerance and decide if the
1363 * rate being applied is within that bounds of the hardware
1364 * rate. If so, no scaling or compensation need be done.
1365 */
1366 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1367 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1368 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1369 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1370 use_scaling = 1;
1371 }
4941b8cb 1372 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1373}
1374
1375static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1376{
e26101b1 1377 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1378 vcpu->arch.virtual_tsc_mult,
1379 vcpu->arch.virtual_tsc_shift);
e26101b1 1380 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1381 return tsc;
1382}
1383
69b0049a 1384static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1385{
1386#ifdef CONFIG_X86_64
1387 bool vcpus_matched;
b48aa97e
MT		 1388 struct kvm_arch *ka = &vcpu->kvm->arch;
1389 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1390
1391 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1392 atomic_read(&vcpu->kvm->online_vcpus));
1393
7f187922
MT		 1394 /*
1395 * Once the masterclock is enabled, always perform request in
1396 * order to update it.
1397 *
1398 * In order to enable masterclock, the host clocksource must be TSC
1399 * and the vcpus need to have matched TSCs. When that happens,
1400 * perform request to enable masterclock.
1401 */
1402 if (ka->use_master_clock ||
1403 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1404 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1405
1406 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1407 atomic_read(&vcpu->kvm->online_vcpus),
1408 ka->use_master_clock, gtod->clock.vclock_mode);
1409#endif
1410}
1411
ba904635
WA		 1412static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1413{
3e3f5026 1414 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1415 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1416}
1417
35181e86
HZ		 1418/*
1419 * Multiply tsc by a fixed point number represented by ratio.
1420 *
1421 * The most significant 64-N bits (mult) of ratio represent the
1422 * integral part of the fixed point number; the remaining N bits
1423 * (frac) represent the fractional part, ie. ratio represents a fixed
1424 * point number (mult + frac * 2^(-N)).
1425 *
1426 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1427 */
1428static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1429{
1430 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1431}
1432
1433u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1434{
1435 u64 _tsc = tsc;
1436 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1437
1438 if (ratio != kvm_default_tsc_scaling_ratio)
1439 _tsc = __scale_tsc(ratio, tsc);
1440
1441 return _tsc;
1442}
1443EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1444
07c1419a
HZ		 1445static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1446{
1447 u64 tsc;
1448
1449 tsc = kvm_scale_tsc(vcpu, rdtsc());
1450
1451 return target_tsc - tsc;
1452}
1453
4ba76538
HZ		 1454u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1455{
ea26e4ec 1456 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1457}
1458EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1459
a545ab6a
LC		 1460static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1461{
1462 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1463 vcpu->arch.tsc_offset = offset;
1464}
1465
8fe8ab46 1466void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1467{
1468 struct kvm *kvm = vcpu->kvm;
f38e098f 1469 u64 offset, ns, elapsed;
99e3e30a 1470 unsigned long flags;
b48aa97e 1471 bool matched;
0d3da0d2 1472 bool already_matched;
8fe8ab46 1473 u64 data = msr->data;
c5e8ec8e 1474 bool synchronizing = false;
99e3e30a 1475
038f8c11 1476 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1477 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1478 ns = ktime_get_boot_ns();
f38e098f 1479 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1480
03ba32ca 1481 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1482 if (data == 0 && msr->host_initiated) {
1483 /*
1484 * detection of vcpu initialization -- need to sync
1485 * with other vCPUs. This particularly helps to keep
1486 * kvm_clock stable after CPU hotplug
1487 */
1488 synchronizing = true;
1489 } else {
1490 u64 tsc_exp = kvm->arch.last_tsc_write +
1491 nsec_to_cycles(vcpu, elapsed);
1492 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1493 /*
1494 * Special case: TSC write with a small delta (1 second)
1495 * of virtual cycle time against real time is
1496 * interpreted as an attempt to synchronize the CPU.
1497 */
1498 synchronizing = data < tsc_exp + tsc_hz &&
1499 data + tsc_hz > tsc_exp;
1500 }
c5e8ec8e 1501 }
f38e098f
ZA		 1502
1503 /*
5d3cb0f6
ZA		 1504 * For a reliable TSC, we can match TSC offsets, and for an unstable
1505 * TSC, we add elapsed time in this computation. We could let the
1506 * compensation code attempt to catch up if we fall behind, but
1507 * it's better to try to match offsets from the beginning.
1508 */
c5e8ec8e 1509 if (synchronizing &&
5d3cb0f6 1510 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1511 if (!check_tsc_unstable()) {
e26101b1 1512 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1513 pr_debug("kvm: matched tsc offset for %llu\n", data);
1514 } else {
857e4099 1515 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1516 data += delta;
07c1419a 1517 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1518 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1519 }
b48aa97e 1520 matched = true;
0d3da0d2 1521 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1522 } else {
1523 /*
1524 * We split periods of matched TSC writes into generations.
1525 * For each generation, we track the original measured
1526 * nanosecond time, offset, and write, so if TSCs are in
1527 * sync, we can match exact offset, and if not, we can match
4a969980 1528 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1529 *
1530 * These values are tracked in kvm->arch.cur_xxx variables.
1531 */
1532 kvm->arch.cur_tsc_generation++;
1533 kvm->arch.cur_tsc_nsec = ns;
1534 kvm->arch.cur_tsc_write = data;
1535 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1536 matched = false;
0d3da0d2 1537 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1538 kvm->arch.cur_tsc_generation, data);
f38e098f 1539 }
e26101b1
ZA		 1540
1541 /*
1542 * We also track th most recent recorded KHZ, write and time to
1543 * allow the matching interval to be extended at each write.
1544 */
f38e098f
ZA		 1545 kvm->arch.last_tsc_nsec = ns;
1546 kvm->arch.last_tsc_write = data;
5d3cb0f6 1547 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1548
b183aa58 1549 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1550
1551 /* Keep track of which generation this VCPU has synchronized to */
1552 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1553 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1554 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1555
d6321d49 1556 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1557 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1558
a545ab6a 1559 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1560 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1561
1562 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1563 if (!matched) {
b48aa97e 1564 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1565 } else if (!already_matched) {
1566 kvm->arch.nr_vcpus_matched_tsc++;
1567 }
b48aa97e
MT		 1568
1569 kvm_track_tsc_matching(vcpu);
1570 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1571}
e26101b1 1572
99e3e30a
ZA		 1573EXPORT_SYMBOL_GPL(kvm_write_tsc);
1574
58ea6767
HZ		 1575static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1576 s64 adjustment)
1577{
ea26e4ec 1578 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1579}
1580
1581static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1582{
1583 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1584 WARN_ON(adjustment < 0);
1585 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1586 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1587}
1588
d828199e
MT		 1589#ifdef CONFIG_X86_64
1590
a5a1d1c2 1591static u64 read_tsc(void)
d828199e 1592{
a5a1d1c2 1593 u64 ret = (u64)rdtsc_ordered();
03b9730b 1594 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1595
1596 if (likely(ret >= last))
1597 return ret;
1598
1599 /*
1600 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1601 * predictable (it's just a function of time and the likely is
d828199e
MT		 1602 * very likely) and there's a data dependence, so force GCC
1603 * to generate a branch instead. I don't barrier() because
1604 * we don't actually need a barrier, and if this function
1605 * ever gets inlined it will generate worse code.
1606 */
1607 asm volatile ("");
1608 return last;
1609}
1610
a5a1d1c2 1611static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1612{
1613 long v;
1614 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1615
1616 *cycle_now = read_tsc();
1617
1618 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1619 return v * gtod->clock.mult;
1620}
1621
a5a1d1c2 1622static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1623{
cbcf2dd3 1624 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1625 unsigned long seq;
d828199e 1626 int mode;
cbcf2dd3 1627 u64 ns;
d828199e 1628
d828199e
MT		 1629 do {
1630 seq = read_seqcount_begin(&gtod->seq);
1631 mode = gtod->clock.vclock_mode;
cbcf2dd3 1632 ns = gtod->nsec_base;
d828199e
MT		 1633 ns += vgettsc(cycle_now);
1634 ns >>= gtod->clock.shift;
cbcf2dd3 1635 ns += gtod->boot_ns;
d828199e 1636 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1637 *t = ns;
d828199e
MT		 1638
1639 return mode;
1640}
1641
55dd00a7
MT		 1642static int do_realtime(struct timespec *ts, u64 *cycle_now)
1643{
1644 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1645 unsigned long seq;
1646 int mode;
1647 u64 ns;
1648
1649 do {
1650 seq = read_seqcount_begin(&gtod->seq);
1651 mode = gtod->clock.vclock_mode;
1652 ts->tv_sec = gtod->wall_time_sec;
1653 ns = gtod->nsec_base;
1654 ns += vgettsc(cycle_now);
1655 ns >>= gtod->clock.shift;
1656 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1657
1658 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1659 ts->tv_nsec = ns;
1660
1661 return mode;
1662}
1663
d828199e 1664/* returns true if host is using tsc clocksource */
a5a1d1c2 1665static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1666{
d828199e
MT		 1667 /* checked again under seqlock below */
1668 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1669 return false;
1670
cbcf2dd3 1671 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1672}
55dd00a7
MT		 1673
1674/* returns true if host is using tsc clocksource */
1675static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1676 u64 *cycle_now)
1677{
1678 /* checked again under seqlock below */
1679 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1680 return false;
1681
1682 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1683}
d828199e
MT		 1684#endif
1685
1686/*
1687 *
b48aa97e
MT		 1688 * Assuming a stable TSC across physical CPUS, and a stable TSC
1689 * across virtual CPUs, the following condition is possible.
1690 * Each numbered line represents an event visible to both
d828199e
MT		 1691 * CPUs at the next numbered event.
1692 *
1693 * "timespecX" represents host monotonic time. "tscX" represents
1694 * RDTSC value.
1695 *
1696 * VCPU0 on CPU0 | VCPU1 on CPU1
1697 *
1698 * 1. read timespec0,tsc0
1699 * 2. | timespec1 = timespec0 + N
1700 * | tsc1 = tsc0 + M
1701 * 3. transition to guest | transition to guest
1702 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1703 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1704 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1705 *
1706 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1707 *
1708 * - ret0 < ret1
1709 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1710 * ...
1711 * - 0 < N - M => M < N
1712 *
1713 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1714 * always the case (the difference between two distinct xtime instances
1715 * might be smaller then the difference between corresponding TSC reads,
1716 * when updating guest vcpus pvclock areas).
1717 *
1718 * To avoid that problem, do not allow visibility of distinct
1719 * system_timestamp/tsc_timestamp values simultaneously: use a master
1720 * copy of host monotonic time values. Update that master copy
1721 * in lockstep.
1722 *
b48aa97e 1723 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1724 *
1725 */
1726
1727static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1728{
1729#ifdef CONFIG_X86_64
1730 struct kvm_arch *ka = &kvm->arch;
1731 int vclock_mode;
b48aa97e
MT		 1732 bool host_tsc_clocksource, vcpus_matched;
1733
1734 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1735 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1736
1737 /*
1738 * If the host uses TSC clock, then passthrough TSC as stable
1739 * to the guest.
1740 */
b48aa97e 1741 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1742 &ka->master_kernel_ns,
1743 &ka->master_cycle_now);
1744
16a96021 1745 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1746 && !ka->backwards_tsc_observed
54750f2c 1747 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1748
d828199e
MT		 1749 if (ka->use_master_clock)
1750 atomic_set(&kvm_guest_has_master_clock, 1);
1751
1752 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1753 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1754 vcpus_matched);
d828199e
MT		 1755#endif
1756}
1757
2860c4b1
PB		 1758void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1759{
1760 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1761}
1762
2e762ff7
MT		 1763static void kvm_gen_update_masterclock(struct kvm *kvm)
1764{
1765#ifdef CONFIG_X86_64
1766 int i;
1767 struct kvm_vcpu *vcpu;
1768 struct kvm_arch *ka = &kvm->arch;
1769
1770 spin_lock(&ka->pvclock_gtod_sync_lock);
1771 kvm_make_mclock_inprogress_request(kvm);
1772 /* no guest entries from this point */
1773 pvclock_update_vm_gtod_copy(kvm);
1774
1775 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1776 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1777
1778 /* guest entries allowed */
1779 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1780 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1781
1782 spin_unlock(&ka->pvclock_gtod_sync_lock);
1783#endif
1784}
1785
e891a32e 1786u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1787{
108b249c 1788 struct kvm_arch *ka = &kvm->arch;
8b953440 1789 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1790 u64 ret;
108b249c 1791
8b953440
PB		 1792 spin_lock(&ka->pvclock_gtod_sync_lock);
1793 if (!ka->use_master_clock) {
1794 spin_unlock(&ka->pvclock_gtod_sync_lock);
1795 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1796 }
1797
8b953440
PB		 1798 hv_clock.tsc_timestamp = ka->master_cycle_now;
1799 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1800 spin_unlock(&ka->pvclock_gtod_sync_lock);
1801
e2c2206a
WL		 1802 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1803 get_cpu();
1804
e70b57a6
WL		 1805 if (__this_cpu_read(cpu_tsc_khz)) {
1806 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1807 &hv_clock.tsc_shift,
1808 &hv_clock.tsc_to_system_mul);
1809 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1810 } else
1811 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1812
1813 put_cpu();
1814
1815 return ret;
108b249c
PB		 1816}
1817
0d6dd2ff
PB		 1818static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1819{
1820 struct kvm_vcpu_arch *vcpu = &v->arch;
1821 struct pvclock_vcpu_time_info guest_hv_clock;
1822
4e335d9e 1823 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1824 &guest_hv_clock, sizeof(guest_hv_clock))))
1825 return;
1826
1827 /* This VCPU is paused, but it's legal for a guest to read another
1828 * VCPU's kvmclock, so we really have to follow the specification where
1829 * it says that version is odd if data is being modified, and even after
1830 * it is consistent.
1831 *
1832 * Version field updates must be kept separate. This is because
1833 * kvm_write_guest_cached might use a "rep movs" instruction, and
1834 * writes within a string instruction are weakly ordered. So there
1835 * are three writes overall.
1836 *
1837 * As a small optimization, only write the version field in the first
1838 * and third write. The vcpu->pv_time cache is still valid, because the
1839 * version field is the first in the struct.
1840 */
1841 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1842
51c4b8bb
LA		 1843 if (guest_hv_clock.version & 1)
1844 ++guest_hv_clock.version; /* first time write, random junk */
1845
0d6dd2ff 1846 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1847 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1848 &vcpu->hv_clock,
1849 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1850
1851 smp_wmb();
1852
1853 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1854 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1855
1856 if (vcpu->pvclock_set_guest_stopped_request) {
1857 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1858 vcpu->pvclock_set_guest_stopped_request = false;
1859 }
1860
1861 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1862
4e335d9e
PB		 1863 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1864 &vcpu->hv_clock,
1865 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1866
1867 smp_wmb();
1868
1869 vcpu->hv_clock.version++;
4e335d9e
PB		 1870 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1871 &vcpu->hv_clock,
1872 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1873}
1874
34c238a1 1875static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1876{
78db6a50 1877 unsigned long flags, tgt_tsc_khz;
18068523 1878 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1879 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1880 s64 kernel_ns;
d828199e 1881 u64 tsc_timestamp, host_tsc;
51d59c6b 1882 u8 pvclock_flags;
d828199e
MT		 1883 bool use_master_clock;
1884
1885 kernel_ns = 0;
1886 host_tsc = 0;
18068523 1887
d828199e
MT		 1888 /*
1889 * If the host uses TSC clock, then passthrough TSC as stable
1890 * to the guest.
1891 */
1892 spin_lock(&ka->pvclock_gtod_sync_lock);
1893 use_master_clock = ka->use_master_clock;
1894 if (use_master_clock) {
1895 host_tsc = ka->master_cycle_now;
1896 kernel_ns = ka->master_kernel_ns;
1897 }
1898 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1899
1900 /* Keep irq disabled to prevent changes to the clock */
1901 local_irq_save(flags);
78db6a50
PB		 1902 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1903 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1904 local_irq_restore(flags);
1905 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1906 return 1;
1907 }
d828199e 1908 if (!use_master_clock) {
4ea1636b 1909 host_tsc = rdtsc();
108b249c 1910 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1911 }
1912
4ba76538 1913 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1914
c285545f
ZA		 1915 /*
1916 * We may have to catch up the TSC to match elapsed wall clock
1917 * time for two reasons, even if kvmclock is used.
1918 * 1) CPU could have been running below the maximum TSC rate
1919 * 2) Broken TSC compensation resets the base at each VCPU
1920 * entry to avoid unknown leaps of TSC even when running
1921 * again on the same CPU. This may cause apparent elapsed
1922 * time to disappear, and the guest to stand still or run
1923 * very slowly.
1924 */
1925 if (vcpu->tsc_catchup) {
1926 u64 tsc = compute_guest_tsc(v, kernel_ns);
1927 if (tsc > tsc_timestamp) {
f1e2b260 1928 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1929 tsc_timestamp = tsc;
1930 }
50d0a0f9
GH		 1931 }
1932
18068523
GOC		 1933 local_irq_restore(flags);
1934
0d6dd2ff 1935 /* With all the info we got, fill in the values */
18068523 1936
78db6a50
PB		 1937 if (kvm_has_tsc_control)
1938 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1939
1940 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1941 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1942 &vcpu->hv_clock.tsc_shift,
1943 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1944 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1945 }
1946
1d5f066e 1947 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1948 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1949 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1950
d828199e 1951 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1952 pvclock_flags = 0;
d828199e
MT		 1953 if (use_master_clock)
1954 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1955
78c0337a
MT		 1956 vcpu->hv_clock.flags = pvclock_flags;
1957
095cf55d
PB		 1958 if (vcpu->pv_time_enabled)
1959 kvm_setup_pvclock_page(v);
1960 if (v == kvm_get_vcpu(v->kvm, 0))
1961 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1962 return 0;
c8076604
GH		 1963}
1964
0061d53d
MT		 1965/*
1966 * kvmclock updates which are isolated to a given vcpu, such as
1967 * vcpu->cpu migration, should not allow system_timestamp from
1968 * the rest of the vcpus to remain static. Otherwise ntp frequency
1969 * correction applies to one vcpu's system_timestamp but not
1970 * the others.
1971 *
1972 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1973 * We need to rate-limit these requests though, as they can
1974 * considerably slow guests that have a large number of vcpus.
1975 * The time for a remote vcpu to update its kvmclock is bound
1976 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1977 */
1978
7e44e449
AJ		 1979#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1980
1981static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1982{
1983 int i;
7e44e449
AJ		 1984 struct delayed_work *dwork = to_delayed_work(work);
1985 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1986 kvmclock_update_work);
1987 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1988 struct kvm_vcpu *vcpu;
1989
1990 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1991 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1992 kvm_vcpu_kick(vcpu);
1993 }
1994}
1995
7e44e449
AJ		 1996static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1997{
1998 struct kvm *kvm = v->kvm;
1999
105b21bb 2000 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2001 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2002 KVMCLOCK_UPDATE_DELAY);
2003}
2004
332967a3
AJ		 2005#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2006
2007static void kvmclock_sync_fn(struct work_struct *work)
2008{
2009 struct delayed_work *dwork = to_delayed_work(work);
2010 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2011 kvmclock_sync_work);
2012 struct kvm *kvm = container_of(ka, struct kvm, arch);
2013
630994b3
MT		 2014 if (!kvmclock_periodic_sync)
2015 return;
2016
332967a3
AJ		 2017 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2018 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2019 KVMCLOCK_SYNC_PERIOD);
2020}
2021
9ffd986c 2022static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2023{
890ca9ae
HY		 2024 u64 mcg_cap = vcpu->arch.mcg_cap;
2025 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2026 u32 msr = msr_info->index;
2027 u64 data = msr_info->data;
890ca9ae 2028
15c4a640 2029 switch (msr) {
15c4a640 2030 case MSR_IA32_MCG_STATUS:
890ca9ae 2031 vcpu->arch.mcg_status = data;
15c4a640 2032 break;
c7ac679c 2033 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2034 if (!(mcg_cap & MCG_CTL_P))
2035 return 1;
2036 if (data != 0 && data != ~(u64)0)
2037 return -1;
2038 vcpu->arch.mcg_ctl = data;
2039 break;
2040 default:
2041 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2042 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2043 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2044 /* only 0 or all 1s can be written to IA32_MCi_CTL
2045 * some Linux kernels though clear bit 10 in bank 4 to
2046 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2047 * this to avoid an uncatched #GP in the guest
2048 */
890ca9ae 2049 if ((offset & 0x3) == 0 &&
114be429 2050 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2051 return -1;
9ffd986c
WL		 2052 if (!msr_info->host_initiated &&
2053 (offset & 0x3) == 1 && data != 0)
2054 return -1;
890ca9ae
HY		 2055 vcpu->arch.mce_banks[offset] = data;
2056 break;
2057 }
2058 return 1;
2059 }
2060 return 0;
2061}
2062
ffde22ac
ES		 2063static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2064{
2065 struct kvm *kvm = vcpu->kvm;
2066 int lm = is_long_mode(vcpu);
2067 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2068 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2069 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2070 : kvm->arch.xen_hvm_config.blob_size_32;
2071 u32 page_num = data & ~PAGE_MASK;
2072 u64 page_addr = data & PAGE_MASK;
2073 u8 *page;
2074 int r;
2075
2076 r = -E2BIG;
2077 if (page_num >= blob_size)
2078 goto out;
2079 r = -ENOMEM;
ff5c2c03
SL		 2080 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2081 if (IS_ERR(page)) {
2082 r = PTR_ERR(page);
ffde22ac 2083 goto out;
ff5c2c03 2084 }
54bf36aa 2085 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2086 goto out_free;
2087 r = 0;
2088out_free:
2089 kfree(page);
2090out:
2091 return r;
2092}
2093
344d9588
GN		 2094static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2095{
2096 gpa_t gpa = data & ~0x3f;
2097
52a5c155
WL		 2098 /* Bits 3:5 are reserved, Should be zero */
2099 if (data & 0x38)
344d9588
GN		 2100 return 1;
2101
2102 vcpu->arch.apf.msr_val = data;
2103
2104 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2105 kvm_clear_async_pf_completion_queue(vcpu);
2106 kvm_async_pf_hash_reset(vcpu);
2107 return 0;
2108 }
2109
4e335d9e 2110 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2111 sizeof(u32)))
344d9588
GN		 2112 return 1;
2113
6adba527 2114 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2115 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2116 kvm_async_pf_wakeup_all(vcpu);
2117 return 0;
2118}
2119
12f9a48f
GC		 2120static void kvmclock_reset(struct kvm_vcpu *vcpu)
2121{
0b79459b 2122 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2123}
2124
c9aaa895
GC		 2125static void record_steal_time(struct kvm_vcpu *vcpu)
2126{
2127 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2128 return;
2129
4e335d9e 2130 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2131 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2132 return;
2133
0b9f6c46
PX		 2134 vcpu->arch.st.steal.preempted = 0;
2135
35f3fae1
WL		 2136 if (vcpu->arch.st.steal.version & 1)
2137 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2138
2139 vcpu->arch.st.steal.version += 1;
2140
4e335d9e 2141 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2142 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2143
2144 smp_wmb();
2145
c54cdf14
LC		 2146 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2147 vcpu->arch.st.last_steal;
2148 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2149
4e335d9e 2150 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2151 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2152
2153 smp_wmb();
2154
2155 vcpu->arch.st.steal.version += 1;
c9aaa895 2156
4e335d9e 2157 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2158 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2159}
2160
8fe8ab46 2161int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2162{
5753785f 2163 bool pr = false;
8fe8ab46
WA		 2164 u32 msr = msr_info->index;
2165 u64 data = msr_info->data;
5753785f 2166
15c4a640 2167 switch (msr) {
2e32b719
BP		 2168 case MSR_AMD64_NB_CFG:
2169 case MSR_IA32_UCODE_REV:
2170 case MSR_IA32_UCODE_WRITE:
2171 case MSR_VM_HSAVE_PA:
2172 case MSR_AMD64_PATCH_LOADER:
2173 case MSR_AMD64_BU_CFG2:
405a353a 2174 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2175 break;
2176
15c4a640 2177 case MSR_EFER:
b69e8cae 2178 return set_efer(vcpu, data);
8f1589d9
AP		 2179 case MSR_K7_HWCR:
2180 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2181 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2182 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2183 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2184 if (data != 0) {
a737f256
CD		 2185 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2186 data);
8f1589d9
AP		 2187 return 1;
2188 }
15c4a640 2189 break;
f7c6d140
AP		 2190 case MSR_FAM10H_MMIO_CONF_BASE:
2191 if (data != 0) {
a737f256
CD		 2192 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2193 "0x%llx\n", data);
f7c6d140
AP		 2194 return 1;
2195 }
15c4a640 2196 break;
b5e2fec0
AG		 2197 case MSR_IA32_DEBUGCTLMSR:
2198 if (!data) {
2199 /* We support the non-activated case already */
2200 break;
2201 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2202 /* Values other than LBR and BTF are vendor-specific,
2203 thus reserved and should throw a #GP */
2204 return 1;
2205 }
a737f256
CD		 2206 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2207 __func__, data);
b5e2fec0 2208 break;
9ba075a6 2209 case 0x200 ... 0x2ff:
ff53604b 2210 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2211 case MSR_IA32_APICBASE:
58cb628d 2212 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2213 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2214 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2215 case MSR_IA32_TSCDEADLINE:
2216 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2217 break;
ba904635 2218 case MSR_IA32_TSC_ADJUST:
d6321d49 2219 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2220 if (!msr_info->host_initiated) {
d913b904 2221 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2222 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2223 }
2224 vcpu->arch.ia32_tsc_adjust_msr = data;
2225 }
2226 break;
15c4a640 2227 case MSR_IA32_MISC_ENABLE:
ad312c7c 2228 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2229 break;
64d60670
PB		 2230 case MSR_IA32_SMBASE:
2231 if (!msr_info->host_initiated)
2232 return 1;
2233 vcpu->arch.smbase = data;
2234 break;
52797bf9
LA		 2235 case MSR_SMI_COUNT:
2236 if (!msr_info->host_initiated)
2237 return 1;
2238 vcpu->arch.smi_count = data;
2239 break;
11c6bffa 2240 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2241 case MSR_KVM_WALL_CLOCK:
2242 vcpu->kvm->arch.wall_clock = data;
2243 kvm_write_wall_clock(vcpu->kvm, data);
2244 break;
11c6bffa 2245 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2246 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2247 struct kvm_arch *ka = &vcpu->kvm->arch;
2248
12f9a48f 2249 kvmclock_reset(vcpu);
18068523 2250
54750f2c
MT		 2251 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2252 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2253
2254 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2255 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2256
2257 ka->boot_vcpu_runs_old_kvmclock = tmp;
2258 }
2259
18068523 2260 vcpu->arch.time = data;
0061d53d 2261 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2262
2263 /* we verify if the enable bit is set... */
2264 if (!(data & 1))
2265 break;
2266
4e335d9e 2267 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2268 &vcpu->arch.pv_time, data & ~1ULL,
2269 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2270 vcpu->arch.pv_time_enabled = false;
2271 else
2272 vcpu->arch.pv_time_enabled = true;
32cad84f 2273
18068523
GOC		 2274 break;
2275 }
344d9588
GN		 2276 case MSR_KVM_ASYNC_PF_EN:
2277 if (kvm_pv_enable_async_pf(vcpu, data))
2278 return 1;
2279 break;
c9aaa895
GC		 2280 case MSR_KVM_STEAL_TIME:
2281
2282 if (unlikely(!sched_info_on()))
2283 return 1;
2284
2285 if (data & KVM_STEAL_RESERVED_MASK)
2286 return 1;
2287
4e335d9e 2288 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2289 data & KVM_STEAL_VALID_BITS,
2290 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2291 return 1;
2292
2293 vcpu->arch.st.msr_val = data;
2294
2295 if (!(data & KVM_MSR_ENABLED))
2296 break;
2297
c9aaa895
GC		 2298 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2299
2300 break;
ae7a2a3f
MT		 2301 case MSR_KVM_PV_EOI_EN:
2302 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2303 return 1;
2304 break;
c9aaa895 2305
890ca9ae
HY		 2306 case MSR_IA32_MCG_CTL:
2307 case MSR_IA32_MCG_STATUS:
81760dcc 2308 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2309 return set_msr_mce(vcpu, msr_info);
71db6023 2310
6912ac32
WH		 2311 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2312 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2313 pr = true; /* fall through */
2314 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2315 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2316 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2317 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2318
2319 if (pr || data != 0)
a737f256
CD		 2320 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2321 "0x%x data 0x%llx\n", msr, data);
5753785f 2322 break;
84e0cefa
JS		 2323 case MSR_K7_CLK_CTL:
2324 /*
2325 * Ignore all writes to this no longer documented MSR.
2326 * Writes are only relevant for old K7 processors,
2327 * all pre-dating SVM, but a recommended workaround from
4a969980 2328 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2329 * affected processor models on the command line, hence
2330 * the need to ignore the workaround.
2331 */
2332 break;
55cd8e5a 2333 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2334 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2335 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2336 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2337 return kvm_hv_set_msr_common(vcpu, msr, data,
2338 msr_info->host_initiated);
91c9c3ed 2339 case MSR_IA32_BBL_CR_CTL3:
2340 /* Drop writes to this legacy MSR -- see rdmsr
2341 * counterpart for further detail.
2342 */
fab0aa3b
EM		 2343 if (report_ignored_msrs)
2344 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2345 msr, data);
91c9c3ed 2346 break;
2b036c6b 2347 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2348 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2349 return 1;
2350 vcpu->arch.osvw.length = data;
2351 break;
2352 case MSR_AMD64_OSVW_STATUS:
d6321d49 2353 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2354 return 1;
2355 vcpu->arch.osvw.status = data;
2356 break;
db2336a8
KH		 2357 case MSR_PLATFORM_INFO:
2358 if (!msr_info->host_initiated ||
2359 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2360 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2361 cpuid_fault_enabled(vcpu)))
2362 return 1;
2363 vcpu->arch.msr_platform_info = data;
2364 break;
2365 case MSR_MISC_FEATURES_ENABLES:
2366 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2367 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2368 !supports_cpuid_fault(vcpu)))
2369 return 1;
2370 vcpu->arch.msr_misc_features_enables = data;
2371 break;
15c4a640 2372 default:
ffde22ac
ES		 2373 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2374 return xen_hvm_config(vcpu, data);
c6702c9d 2375 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2376 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2377 if (!ignore_msrs) {
ae0f5499 2378 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2379 msr, data);
ed85c068
AP		 2380 return 1;
2381 } else {
fab0aa3b
EM		 2382 if (report_ignored_msrs)
2383 vcpu_unimpl(vcpu,
2384 "ignored wrmsr: 0x%x data 0x%llx\n",
2385 msr, data);
ed85c068
AP		 2386 break;
2387 }
15c4a640
CO		 2388 }
2389 return 0;
2390}
2391EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2392
2393
2394/*
2395 * Reads an msr value (of 'msr_index') into 'pdata'.
2396 * Returns 0 on success, non-0 otherwise.
2397 * Assumes vcpu_load() was already called.
2398 */
609e36d3 2399int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2400{
609e36d3 2401 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2402}
ff651cb6 2403EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2404
890ca9ae 2405static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2406{
2407 u64 data;
890ca9ae
HY		 2408 u64 mcg_cap = vcpu->arch.mcg_cap;
2409 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2410
2411 switch (msr) {
15c4a640
CO		 2412 case MSR_IA32_P5_MC_ADDR:
2413 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2414 data = 0;
2415 break;
15c4a640 2416 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2417 data = vcpu->arch.mcg_cap;
2418 break;
c7ac679c 2419 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2420 if (!(mcg_cap & MCG_CTL_P))
2421 return 1;
2422 data = vcpu->arch.mcg_ctl;
2423 break;
2424 case MSR_IA32_MCG_STATUS:
2425 data = vcpu->arch.mcg_status;
2426 break;
2427 default:
2428 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2429 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2430 u32 offset = msr - MSR_IA32_MC0_CTL;
2431 data = vcpu->arch.mce_banks[offset];
2432 break;
2433 }
2434 return 1;
2435 }
2436 *pdata = data;
2437 return 0;
2438}
2439
609e36d3 2440int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2441{
609e36d3 2442 switch (msr_info->index) {
890ca9ae 2443 case MSR_IA32_PLATFORM_ID:
15c4a640 2444 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2445 case MSR_IA32_DEBUGCTLMSR:
2446 case MSR_IA32_LASTBRANCHFROMIP:
2447 case MSR_IA32_LASTBRANCHTOIP:
2448 case MSR_IA32_LASTINTFROMIP:
2449 case MSR_IA32_LASTINTTOIP:
60af2ecd 2450 case MSR_K8_SYSCFG:
3afb1121
PB		 2451 case MSR_K8_TSEG_ADDR:
2452 case MSR_K8_TSEG_MASK:
60af2ecd 2453 case MSR_K7_HWCR:
61a6bd67 2454 case MSR_VM_HSAVE_PA:
1fdbd48c 2455 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2456 case MSR_AMD64_NB_CFG:
f7c6d140 2457 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2458 case MSR_AMD64_BU_CFG2:
0c2df2a1 2459 case MSR_IA32_PERF_CTL:
405a353a 2460 case MSR_AMD64_DC_CFG:
609e36d3 2461 msr_info->data = 0;
15c4a640 2462 break;
6912ac32
WH		 2463 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2464 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2465 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2466 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2467 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2468 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2469 msr_info->data = 0;
5753785f 2470 break;
742bc670 2471 case MSR_IA32_UCODE_REV:
609e36d3 2472 msr_info->data = 0x100000000ULL;
742bc670 2473 break;
9ba075a6 2474 case MSR_MTRRcap:
9ba075a6 2475 case 0x200 ... 0x2ff:
ff53604b 2476 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2477 case 0xcd: /* fsb frequency */
609e36d3 2478 msr_info->data = 3;
15c4a640 2479 break;
7b914098
JS		 2480 /*
2481 * MSR_EBC_FREQUENCY_ID
2482 * Conservative value valid for even the basic CPU models.
2483 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2484 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2485 * and 266MHz for model 3, or 4. Set Core Clock
2486 * Frequency to System Bus Frequency Ratio to 1 (bits
2487 * 31:24) even though these are only valid for CPU
2488 * models > 2, however guests may end up dividing or
2489 * multiplying by zero otherwise.
2490 */
2491 case MSR_EBC_FREQUENCY_ID:
609e36d3 2492 msr_info->data = 1 << 24;
7b914098 2493 break;
15c4a640 2494 case MSR_IA32_APICBASE:
609e36d3 2495 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2496 break;
0105d1a5 2497 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2498 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2499 break;
a3e06bbe 2500 case MSR_IA32_TSCDEADLINE:
609e36d3 2501 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2502 break;
ba904635 2503 case MSR_IA32_TSC_ADJUST:
609e36d3 2504 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2505 break;
15c4a640 2506 case MSR_IA32_MISC_ENABLE:
609e36d3 2507 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2508 break;
64d60670
PB		 2509 case MSR_IA32_SMBASE:
2510 if (!msr_info->host_initiated)
2511 return 1;
2512 msr_info->data = vcpu->arch.smbase;
15c4a640 2513 break;
52797bf9
LA		 2514 case MSR_SMI_COUNT:
2515 msr_info->data = vcpu->arch.smi_count;
2516 break;
847f0ad8
AG		 2517 case MSR_IA32_PERF_STATUS:
2518 /* TSC increment by tick */
609e36d3 2519 msr_info->data = 1000ULL;
847f0ad8 2520 /* CPU multiplier */
b0996ae4 2521 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2522 break;
15c4a640 2523 case MSR_EFER:
609e36d3 2524 msr_info->data = vcpu->arch.efer;
15c4a640 2525 break;
18068523 2526 case MSR_KVM_WALL_CLOCK:
11c6bffa 2527 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2528 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2529 break;
2530 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2531 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2532 msr_info->data = vcpu->arch.time;
18068523 2533 break;
344d9588 2534 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2535 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2536 break;
c9aaa895 2537 case MSR_KVM_STEAL_TIME:
609e36d3 2538 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2539 break;
1d92128f 2540 case MSR_KVM_PV_EOI_EN:
609e36d3 2541 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2542 break;
890ca9ae
HY		 2543 case MSR_IA32_P5_MC_ADDR:
2544 case MSR_IA32_P5_MC_TYPE:
2545 case MSR_IA32_MCG_CAP:
2546 case MSR_IA32_MCG_CTL:
2547 case MSR_IA32_MCG_STATUS:
81760dcc 2548 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2549 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2550 case MSR_K7_CLK_CTL:
2551 /*
2552 * Provide expected ramp-up count for K7. All other
2553 * are set to zero, indicating minimum divisors for
2554 * every field.
2555 *
2556 * This prevents guest kernels on AMD host with CPU
2557 * type 6, model 8 and higher from exploding due to
2558 * the rdmsr failing.
2559 */
609e36d3 2560 msr_info->data = 0x20000000;
84e0cefa 2561 break;
55cd8e5a 2562 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2563 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2564 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2565 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2566 return kvm_hv_get_msr_common(vcpu,
2567 msr_info->index, &msr_info->data);
55cd8e5a 2568 break;
91c9c3ed 2569 case MSR_IA32_BBL_CR_CTL3:
2570 /* This legacy MSR exists but isn't fully documented in current
2571 * silicon. It is however accessed by winxp in very narrow
2572 * scenarios where it sets bit #19, itself documented as
2573 * a "reserved" bit. Best effort attempt to source coherent
2574 * read data here should the balance of the register be
2575 * interpreted by the guest:
2576 *
2577 * L2 cache control register 3: 64GB range, 256KB size,
2578 * enabled, latency 0x1, configured
2579 */
609e36d3 2580 msr_info->data = 0xbe702111;
91c9c3ed 2581 break;
2b036c6b 2582 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2583 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2584 return 1;
609e36d3 2585 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2586 break;
2587 case MSR_AMD64_OSVW_STATUS:
d6321d49 2588 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2589 return 1;
609e36d3 2590 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2591 break;
db2336a8
KH		 2592 case MSR_PLATFORM_INFO:
2593 msr_info->data = vcpu->arch.msr_platform_info;
2594 break;
2595 case MSR_MISC_FEATURES_ENABLES:
2596 msr_info->data = vcpu->arch.msr_misc_features_enables;
2597 break;
15c4a640 2598 default:
c6702c9d 2599 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2600 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2601 if (!ignore_msrs) {
ae0f5499
BD		 2602 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2603 msr_info->index);
ed85c068
AP		 2604 return 1;
2605 } else {
fab0aa3b
EM		 2606 if (report_ignored_msrs)
2607 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2608 msr_info->index);
609e36d3 2609 msr_info->data = 0;
ed85c068
AP		 2610 }
2611 break;
15c4a640 2612 }
15c4a640
CO		 2613 return 0;
2614}
2615EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2616
313a3dc7
CO		 2617/*
2618 * Read or write a bunch of msrs. All parameters are kernel addresses.
2619 *
2620 * @return number of msrs set successfully.
2621 */
2622static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2623 struct kvm_msr_entry *entries,
2624 int (*do_msr)(struct kvm_vcpu *vcpu,
2625 unsigned index, u64 *data))
2626{
f656ce01 2627 int i, idx;
313a3dc7 2628
f656ce01 2629 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2630 for (i = 0; i < msrs->nmsrs; ++i)
2631 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2632 break;
f656ce01 2633 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2634
313a3dc7
CO		 2635 return i;
2636}
2637
2638/*
2639 * Read or write a bunch of msrs. Parameters are user addresses.
2640 *
2641 * @return number of msrs set successfully.
2642 */
2643static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2644 int (*do_msr)(struct kvm_vcpu *vcpu,
2645 unsigned index, u64 *data),
2646 int writeback)
2647{
2648 struct kvm_msrs msrs;
2649 struct kvm_msr_entry *entries;
2650 int r, n;
2651 unsigned size;
2652
2653 r = -EFAULT;
2654 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2655 goto out;
2656
2657 r = -E2BIG;
2658 if (msrs.nmsrs >= MAX_IO_MSRS)
2659 goto out;
2660
313a3dc7 2661 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2662 entries = memdup_user(user_msrs->entries, size);
2663 if (IS_ERR(entries)) {
2664 r = PTR_ERR(entries);
313a3dc7 2665 goto out;
ff5c2c03 2666 }
313a3dc7
CO		 2667
2668 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2669 if (r < 0)
2670 goto out_free;
2671
2672 r = -EFAULT;
2673 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2674 goto out_free;
2675
2676 r = n;
2677
2678out_free:
7a73c028 2679 kfree(entries);
313a3dc7
CO		 2680out:
2681 return r;
2682}
2683
784aa3d7 2684int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2685{
2686 int r;
2687
2688 switch (ext) {
2689 case KVM_CAP_IRQCHIP:
2690 case KVM_CAP_HLT:
2691 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2692 case KVM_CAP_SET_TSS_ADDR:
07716717 2693 case KVM_CAP_EXT_CPUID:
9c15bb1d 2694 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2695 case KVM_CAP_CLOCKSOURCE:
7837699f 2696 case KVM_CAP_PIT:
a28e4f5a 2697 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2698 case KVM_CAP_MP_STATE:
ed848624 2699 case KVM_CAP_SYNC_MMU:
a355c85c 2700 case KVM_CAP_USER_NMI:
52d939a0 2701 case KVM_CAP_REINJECT_CONTROL:
4925663a 2702 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2703 case KVM_CAP_IOEVENTFD:
f848a5a8 2704 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2705 case KVM_CAP_PIT2:
e9f42757 2706 case KVM_CAP_PIT_STATE2:
b927a3ce 2707 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2708 case KVM_CAP_XEN_HVM:
3cfc3092 2709 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2710 case KVM_CAP_HYPERV:
10388a07 2711 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2712 case KVM_CAP_HYPERV_SPIN:
5c919412 2713 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2714 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2715 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2716 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2717 case KVM_CAP_DEBUGREGS:
d2be1651 2718 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2719 case KVM_CAP_XSAVE:
344d9588 2720 case KVM_CAP_ASYNC_PF:
92a1f12d 2721 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2722 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2723 case KVM_CAP_READONLY_MEM:
5f66b620 2724 case KVM_CAP_HYPERV_TIME:
100943c5 2725 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2726 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2727 case KVM_CAP_ENABLE_CAP_VM:
2728 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2729 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2730 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2731 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2732 r = 1;
2733 break;
e3fd9a93
PB		 2734 case KVM_CAP_ADJUST_CLOCK:
2735 r = KVM_CLOCK_TSC_STABLE;
2736 break;
668fffa3
MT		 2737 case KVM_CAP_X86_GUEST_MWAIT:
2738 r = kvm_mwait_in_guest();
2739 break;
6d396b55
PB		 2740 case KVM_CAP_X86_SMM:
2741 /* SMBASE is usually relocated above 1M on modern chipsets,
2742 * and SMM handlers might indeed rely on 4G segment limits,
2743 * so do not report SMM to be available if real mode is
2744 * emulated via vm86 mode. Still, do not go to great lengths
2745 * to avoid userspace's usage of the feature, because it is a
2746 * fringe case that is not enabled except via specific settings
2747 * of the module parameters.
2748 */
2749 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2750 break;
774ead3a
AK		 2751 case KVM_CAP_VAPIC:
2752 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2753 break;
f725230a 2754 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2755 r = KVM_SOFT_MAX_VCPUS;
2756 break;
2757 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2758 r = KVM_MAX_VCPUS;
2759 break;
a988b910 2760 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2761 r = KVM_USER_MEM_SLOTS;
a988b910 2762 break;
a68a6a72
MT		 2763 case KVM_CAP_PV_MMU: /* obsolete */
2764 r = 0;
2f333bcb 2765 break;
890ca9ae
HY		 2766 case KVM_CAP_MCE:
2767 r = KVM_MAX_MCE_BANKS;
2768 break;
2d5b5a66 2769 case KVM_CAP_XCRS:
d366bf7e 2770 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2771 break;
92a1f12d
JR		 2772 case KVM_CAP_TSC_CONTROL:
2773 r = kvm_has_tsc_control;
2774 break;
37131313
RK		 2775 case KVM_CAP_X2APIC_API:
2776 r = KVM_X2APIC_API_VALID_FLAGS;
2777 break;
018d00d2
ZX		 2778 default:
2779 r = 0;
2780 break;
2781 }
2782 return r;
2783
2784}
2785
043405e1
CO		 2786long kvm_arch_dev_ioctl(struct file *filp,
2787 unsigned int ioctl, unsigned long arg)
2788{
2789 void __user *argp = (void __user *)arg;
2790 long r;
2791
2792 switch (ioctl) {
2793 case KVM_GET_MSR_INDEX_LIST: {
2794 struct kvm_msr_list __user *user_msr_list = argp;
2795 struct kvm_msr_list msr_list;
2796 unsigned n;
2797
2798 r = -EFAULT;
2799 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2800 goto out;
2801 n = msr_list.nmsrs;
62ef68bb 2802 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2803 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2804 goto out;
2805 r = -E2BIG;
e125e7b6 2806 if (n < msr_list.nmsrs)
043405e1
CO		 2807 goto out;
2808 r = -EFAULT;
2809 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2810 num_msrs_to_save * sizeof(u32)))
2811 goto out;
e125e7b6 2812 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2813 &emulated_msrs,
62ef68bb 2814 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2815 goto out;
2816 r = 0;
2817 break;
2818 }
9c15bb1d
BP		 2819 case KVM_GET_SUPPORTED_CPUID:
2820 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2821 struct kvm_cpuid2 __user *cpuid_arg = argp;
2822 struct kvm_cpuid2 cpuid;
2823
2824 r = -EFAULT;
2825 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2826 goto out;
9c15bb1d
BP		 2827
2828 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2829 ioctl);
674eea0f
AK		 2830 if (r)
2831 goto out;
2832
2833 r = -EFAULT;
2834 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2835 goto out;
2836 r = 0;
2837 break;
2838 }
890ca9ae 2839 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2840 r = -EFAULT;
c45dcc71
AR		 2841 if (copy_to_user(argp, &kvm_mce_cap_supported,
2842 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2843 goto out;
2844 r = 0;
2845 break;
2846 }
043405e1
CO		 2847 default:
2848 r = -EINVAL;
2849 }
2850out:
2851 return r;
2852}
2853
f5f48ee1
SY		 2854static void wbinvd_ipi(void *garbage)
2855{
2856 wbinvd();
2857}
2858
2859static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2860{
e0f0bbc5 2861 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2862}
2863
313a3dc7
CO		 2864void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2865{
f5f48ee1
SY		 2866 /* Address WBINVD may be executed by guest */
2867 if (need_emulate_wbinvd(vcpu)) {
2868 if (kvm_x86_ops->has_wbinvd_exit())
2869 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2870 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2871 smp_call_function_single(vcpu->cpu,
2872 wbinvd_ipi, NULL, 1);
2873 }
2874
313a3dc7 2875 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2876
0dd6a6ed
ZA		 2877 /* Apply any externally detected TSC adjustments (due to suspend) */
2878 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2879 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2880 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2881 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2882 }
8f6055cb 2883
48434c20 2884 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2885 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2886 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2887 if (tsc_delta < 0)
2888 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2889
c285545f 2890 if (check_tsc_unstable()) {
07c1419a 2891 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2892 vcpu->arch.last_guest_tsc);
a545ab6a 2893 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2894 vcpu->arch.tsc_catchup = 1;
c285545f 2895 }
a749e247
PB		 2896
2897 if (kvm_lapic_hv_timer_in_use(vcpu))
2898 kvm_lapic_restart_hv_timer(vcpu);
2899
d98d07ca
MT		 2900 /*
2901 * On a host with synchronized TSC, there is no need to update
2902 * kvmclock on vcpu->cpu migration
2903 */
2904 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2905 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2906 if (vcpu->cpu != cpu)
1bd2009e 2907 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2908 vcpu->cpu = cpu;
6b7d7e76 2909 }
c9aaa895 2910
c9aaa895 2911 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2912}
2913
0b9f6c46
PX		 2914static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2915{
2916 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2917 return;
2918
fa55eedd 2919 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 2920
4e335d9e 2921 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2922 &vcpu->arch.st.steal.preempted,
2923 offsetof(struct kvm_steal_time, preempted),
2924 sizeof(vcpu->arch.st.steal.preempted));
2925}
2926
313a3dc7
CO		 2927void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2928{
cc0d907c 2929 int idx;
de63ad4c
LM		 2930
2931 if (vcpu->preempted)
2932 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2933
931f261b
AA		 2934 /*
2935 * Disable page faults because we're in atomic context here.
2936 * kvm_write_guest_offset_cached() would call might_fault()
2937 * that relies on pagefault_disable() to tell if there's a
2938 * bug. NOTE: the write to guest memory may not go through if
2939 * during postcopy live migration or if there's heavy guest
2940 * paging.
2941 */
2942 pagefault_disable();
cc0d907c
AA		 2943 /*
2944 * kvm_memslots() will be called by
2945 * kvm_write_guest_offset_cached() so take the srcu lock.
2946 */
2947 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2948 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2949 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2950 pagefault_enable();
02daab21 2951 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 2952 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2953}
2954
313a3dc7
CO		 2955static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2956 struct kvm_lapic_state *s)
2957{
76dfafd5 2958 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2959 kvm_x86_ops->sync_pir_to_irr(vcpu);
2960
a92e2543 2961 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2962}
2963
2964static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2965 struct kvm_lapic_state *s)
2966{
a92e2543
RK		 2967 int r;
2968
2969 r = kvm_apic_set_state(vcpu, s);
2970 if (r)
2971 return r;
cb142eb7 2972 update_cr8_intercept(vcpu);
313a3dc7
CO		 2973
2974 return 0;
2975}
2976
127a457a
MG		 2977static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2978{
2979 return (!lapic_in_kernel(vcpu) ||
2980 kvm_apic_accept_pic_intr(vcpu));
2981}
2982
782d422b
MG		 2983/*
2984 * if userspace requested an interrupt window, check that the
2985 * interrupt window is open.
2986 *
2987 * No need to exit to userspace if we already have an interrupt queued.
2988 */
2989static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2990{
2991 return kvm_arch_interrupt_allowed(vcpu) &&
2992 !kvm_cpu_has_interrupt(vcpu) &&
2993 !kvm_event_needs_reinjection(vcpu) &&
2994 kvm_cpu_accept_dm_intr(vcpu);
2995}
2996
f77bc6a4
ZX		 2997static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2998 struct kvm_interrupt *irq)
2999{
02cdb50f 3000 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3001 return -EINVAL;
1c1a9ce9
SR		 3002
3003 if (!irqchip_in_kernel(vcpu->kvm)) {
3004 kvm_queue_interrupt(vcpu, irq->irq, false);
3005 kvm_make_request(KVM_REQ_EVENT, vcpu);
3006 return 0;
3007 }
3008
3009 /*
3010 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3011 * fail for in-kernel 8259.
3012 */
3013 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3014 return -ENXIO;
f77bc6a4 3015
1c1a9ce9
SR		 3016 if (vcpu->arch.pending_external_vector != -1)
3017 return -EEXIST;
f77bc6a4 3018
1c1a9ce9 3019 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3020 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3021 return 0;
3022}
3023
c4abb7c9
JK		 3024static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3025{
c4abb7c9 3026 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3027
3028 return 0;
3029}
3030
f077825a
PB		 3031static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3032{
64d60670
PB		 3033 kvm_make_request(KVM_REQ_SMI, vcpu);
3034
f077825a
PB		 3035 return 0;
3036}
3037
b209749f
AK		 3038static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3039 struct kvm_tpr_access_ctl *tac)
3040{
3041 if (tac->flags)
3042 return -EINVAL;
3043 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3044 return 0;
3045}
3046
890ca9ae
HY		 3047static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3048 u64 mcg_cap)
3049{
3050 int r;
3051 unsigned bank_num = mcg_cap & 0xff, bank;
3052
3053 r = -EINVAL;
a9e38c3e 3054 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3055 goto out;
c45dcc71 3056 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3057 goto out;
3058 r = 0;
3059 vcpu->arch.mcg_cap = mcg_cap;
3060 /* Init IA32_MCG_CTL to all 1s */
3061 if (mcg_cap & MCG_CTL_P)
3062 vcpu->arch.mcg_ctl = ~(u64)0;
3063 /* Init IA32_MCi_CTL to all 1s */
3064 for (bank = 0; bank < bank_num; bank++)
3065 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3066
3067 if (kvm_x86_ops->setup_mce)
3068 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3069out:
3070 return r;
3071}
3072
3073static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3074 struct kvm_x86_mce *mce)
3075{
3076 u64 mcg_cap = vcpu->arch.mcg_cap;
3077 unsigned bank_num = mcg_cap & 0xff;
3078 u64 *banks = vcpu->arch.mce_banks;
3079
3080 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3081 return -EINVAL;
3082 /*
3083 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3084 * reporting is disabled
3085 */
3086 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3087 vcpu->arch.mcg_ctl != ~(u64)0)
3088 return 0;
3089 banks += 4 * mce->bank;
3090 /*
3091 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3092 * reporting is disabled for the bank
3093 */
3094 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3095 return 0;
3096 if (mce->status & MCI_STATUS_UC) {
3097 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3098 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3099 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3100 return 0;
3101 }
3102 if (banks[1] & MCI_STATUS_VAL)
3103 mce->status |= MCI_STATUS_OVER;
3104 banks[2] = mce->addr;
3105 banks[3] = mce->misc;
3106 vcpu->arch.mcg_status = mce->mcg_status;
3107 banks[1] = mce->status;
3108 kvm_queue_exception(vcpu, MC_VECTOR);
3109 } else if (!(banks[1] & MCI_STATUS_VAL)
3110 || !(banks[1] & MCI_STATUS_UC)) {
3111 if (banks[1] & MCI_STATUS_VAL)
3112 mce->status |= MCI_STATUS_OVER;
3113 banks[2] = mce->addr;
3114 banks[3] = mce->misc;
3115 banks[1] = mce->status;
3116 } else
3117 banks[1] |= MCI_STATUS_OVER;
3118 return 0;
3119}
3120
3cfc3092
JK		 3121static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3122 struct kvm_vcpu_events *events)
3123{
7460fb4a 3124 process_nmi(vcpu);
664f8e26
WL		 3125 /*
3126 * FIXME: pass injected and pending separately. This is only
3127 * needed for nested virtualization, whose state cannot be
3128 * migrated yet. For now we can combine them.
3129 */
03b82a30 3130 events->exception.injected =
664f8e26
WL		 3131 (vcpu->arch.exception.pending ||
3132 vcpu->arch.exception.injected) &&
03b82a30 3133 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3134 events->exception.nr = vcpu->arch.exception.nr;
3135 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3136 events->exception.pad = 0;
3cfc3092
JK		 3137 events->exception.error_code = vcpu->arch.exception.error_code;
3138
03b82a30
JK		 3139 events->interrupt.injected =
3140 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3141 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3142 events->interrupt.soft = 0;
37ccdcbe 3143 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3144
3145 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3146 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3147 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3148 events->nmi.pad = 0;
3cfc3092 3149
66450a21 3150 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3151
f077825a
PB		 3152 events->smi.smm = is_smm(vcpu);
3153 events->smi.pending = vcpu->arch.smi_pending;
3154 events->smi.smm_inside_nmi =
3155 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3156 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3157
dab4b911 3158 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3159 | KVM_VCPUEVENT_VALID_SHADOW
3160 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3161 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3162}
3163
6ef4e07e
XG		 3164static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3165
3cfc3092
JK		 3166static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3167 struct kvm_vcpu_events *events)
3168{
dab4b911 3169 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3170 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3171 | KVM_VCPUEVENT_VALID_SHADOW
3172 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3173 return -EINVAL;
3174
78e546c8 3175 if (events->exception.injected &&
28d06353
JM		 3176 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3177 is_guest_mode(vcpu)))
78e546c8
PB		 3178 return -EINVAL;
3179
28bf2888
DH		 3180 /* INITs are latched while in SMM */
3181 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3182 (events->smi.smm || events->smi.pending) &&
3183 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3184 return -EINVAL;
3185
7460fb4a 3186 process_nmi(vcpu);
664f8e26 3187 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3188 vcpu->arch.exception.pending = events->exception.injected;
3189 vcpu->arch.exception.nr = events->exception.nr;
3190 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3191 vcpu->arch.exception.error_code = events->exception.error_code;
3192
3193 vcpu->arch.interrupt.pending = events->interrupt.injected;
3194 vcpu->arch.interrupt.nr = events->interrupt.nr;
3195 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3196 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3197 kvm_x86_ops->set_interrupt_shadow(vcpu,
3198 events->interrupt.shadow);
3cfc3092
JK		 3199
3200 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3201 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3202 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3203 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3204
66450a21 3205 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3206 lapic_in_kernel(vcpu))
66450a21 3207 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3208
f077825a 3209 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3210 u32 hflags = vcpu->arch.hflags;
f077825a 3211 if (events->smi.smm)
6ef4e07e 3212 hflags |= HF_SMM_MASK;
f077825a 3213 else
6ef4e07e
XG		 3214 hflags &= ~HF_SMM_MASK;
3215 kvm_set_hflags(vcpu, hflags);
3216
f077825a 3217 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3218
3219 if (events->smi.smm) {
3220 if (events->smi.smm_inside_nmi)
3221 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3222 else
f4ef1910
WL		 3223 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3224 if (lapic_in_kernel(vcpu)) {
3225 if (events->smi.latched_init)
3226 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3227 else
3228 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3229 }
f077825a
PB		 3230 }
3231 }
3232
3842d135
AK		 3233 kvm_make_request(KVM_REQ_EVENT, vcpu);
3234
3cfc3092
JK		 3235 return 0;
3236}
3237
a1efbe77
JK		 3238static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3239 struct kvm_debugregs *dbgregs)
3240{
73aaf249
JK		 3241 unsigned long val;
3242
a1efbe77 3243 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3244 kvm_get_dr(vcpu, 6, &val);
73aaf249 3245 dbgregs->dr6 = val;
a1efbe77
JK		 3246 dbgregs->dr7 = vcpu->arch.dr7;
3247 dbgregs->flags = 0;
97e69aa6 3248 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3249}
3250
3251static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3252 struct kvm_debugregs *dbgregs)
3253{
3254 if (dbgregs->flags)
3255 return -EINVAL;
3256
d14bdb55
PB		 3257 if (dbgregs->dr6 & ~0xffffffffull)
3258 return -EINVAL;
3259 if (dbgregs->dr7 & ~0xffffffffull)
3260 return -EINVAL;
3261
a1efbe77 3262 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3263 kvm_update_dr0123(vcpu);
a1efbe77 3264 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3265 kvm_update_dr6(vcpu);
a1efbe77 3266 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3267 kvm_update_dr7(vcpu);
a1efbe77 3268
a1efbe77
JK		 3269 return 0;
3270}
3271
df1daba7
PB		 3272#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3273
3274static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3275{
c47ada30 3276 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3277 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3278 u64 valid;
3279
3280 /*
3281 * Copy legacy XSAVE area, to avoid complications with CPUID
3282 * leaves 0 and 1 in the loop below.
3283 */
3284 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3285
3286 /* Set XSTATE_BV */
00c87e9a 3287 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3288 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3289
3290 /*
3291 * Copy each region from the possibly compacted offset to the
3292 * non-compacted offset.
3293 */
d91cab78 3294 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3295 while (valid) {
3296 u64 feature = valid & -valid;
3297 int index = fls64(feature) - 1;
3298 void *src = get_xsave_addr(xsave, feature);
3299
3300 if (src) {
3301 u32 size, offset, ecx, edx;
3302 cpuid_count(XSTATE_CPUID, index,
3303 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3304 if (feature == XFEATURE_MASK_PKRU)
3305 memcpy(dest + offset, &vcpu->arch.pkru,
3306 sizeof(vcpu->arch.pkru));
3307 else
3308 memcpy(dest + offset, src, size);
3309
df1daba7
PB		 3310 }
3311
3312 valid -= feature;
3313 }
3314}
3315
3316static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3317{
c47ada30 3318 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3319 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3320 u64 valid;
3321
3322 /*
3323 * Copy legacy XSAVE area, to avoid complications with CPUID
3324 * leaves 0 and 1 in the loop below.
3325 */
3326 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3327
3328 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3329 xsave->header.xfeatures = xstate_bv;
782511b0 3330 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3331 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3332
3333 /*
3334 * Copy each region from the non-compacted offset to the
3335 * possibly compacted offset.
3336 */
d91cab78 3337 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3338 while (valid) {
3339 u64 feature = valid & -valid;
3340 int index = fls64(feature) - 1;
3341 void *dest = get_xsave_addr(xsave, feature);
3342
3343 if (dest) {
3344 u32 size, offset, ecx, edx;
3345 cpuid_count(XSTATE_CPUID, index,
3346 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3347 if (feature == XFEATURE_MASK_PKRU)
3348 memcpy(&vcpu->arch.pkru, src + offset,
3349 sizeof(vcpu->arch.pkru));
3350 else
3351 memcpy(dest, src + offset, size);
ee4100da 3352 }
df1daba7
PB		 3353
3354 valid -= feature;
3355 }
3356}
3357
2d5b5a66
SY		 3358static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3359 struct kvm_xsave *guest_xsave)
3360{
d366bf7e 3361 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3362 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3363 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3364 } else {
2d5b5a66 3365 memcpy(guest_xsave->region,
7366ed77 3366 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3367 sizeof(struct fxregs_state));
2d5b5a66 3368 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3369 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3370 }
3371}
3372
a575813b
WL		 3373#define XSAVE_MXCSR_OFFSET 24
3374
2d5b5a66
SY		 3375static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3376 struct kvm_xsave *guest_xsave)
3377{
3378 u64 xstate_bv =
3379 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3380 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3381
d366bf7e 3382 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3383 /*
3384 * Here we allow setting states that are not present in
3385 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3386 * with old userspace.
3387 */
a575813b
WL		 3388 if (xstate_bv & ~kvm_supported_xcr0() ||
3389 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3390 return -EINVAL;
df1daba7 3391 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3392 } else {
a575813b
WL		 3393 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3394 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3395 return -EINVAL;
7366ed77 3396 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3397 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3398 }
3399 return 0;
3400}
3401
3402static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3403 struct kvm_xcrs *guest_xcrs)
3404{
d366bf7e 3405 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3406 guest_xcrs->nr_xcrs = 0;
3407 return;
3408 }
3409
3410 guest_xcrs->nr_xcrs = 1;
3411 guest_xcrs->flags = 0;
3412 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3413 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3414}
3415
3416static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3417 struct kvm_xcrs *guest_xcrs)
3418{
3419 int i, r = 0;
3420
d366bf7e 3421 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3422 return -EINVAL;
3423
3424 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3425 return -EINVAL;
3426
3427 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3428 /* Only support XCR0 currently */
c67a04cb 3429 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3430 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3431 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3432 break;
3433 }
3434 if (r)
3435 r = -EINVAL;
3436 return r;
3437}
3438
1c0b28c2
EM		 3439/*
3440 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3441 * stopped by the hypervisor. This function will be called from the host only.
3442 * EINVAL is returned when the host attempts to set the flag for a guest that
3443 * does not support pv clocks.
3444 */
3445static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3446{
0b79459b 3447 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3448 return -EINVAL;
51d59c6b 3449 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3450 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3451 return 0;
3452}
3453
5c919412
AS		 3454static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3455 struct kvm_enable_cap *cap)
3456{
3457 if (cap->flags)
3458 return -EINVAL;
3459
3460 switch (cap->cap) {
efc479e6
RK		 3461 case KVM_CAP_HYPERV_SYNIC2:
3462 if (cap->args[0])
3463 return -EINVAL;
5c919412 3464 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3465 if (!irqchip_in_kernel(vcpu->kvm))
3466 return -EINVAL;
efc479e6
RK		 3467 return kvm_hv_activate_synic(vcpu, cap->cap ==
3468 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3469 default:
3470 return -EINVAL;
3471 }
3472}
3473
313a3dc7
CO		 3474long kvm_arch_vcpu_ioctl(struct file *filp,
3475 unsigned int ioctl, unsigned long arg)
3476{
3477 struct kvm_vcpu *vcpu = filp->private_data;
3478 void __user *argp = (void __user *)arg;
3479 int r;
d1ac91d8
AK		 3480 union {
3481 struct kvm_lapic_state *lapic;
3482 struct kvm_xsave *xsave;
3483 struct kvm_xcrs *xcrs;
3484 void *buffer;
3485 } u;
3486
9b062471
CD		 3487 vcpu_load(vcpu);
3488
d1ac91d8 3489 u.buffer = NULL;
313a3dc7
CO		 3490 switch (ioctl) {
3491 case KVM_GET_LAPIC: {
2204ae3c 3492 r = -EINVAL;
bce87cce 3493 if (!lapic_in_kernel(vcpu))
2204ae3c 3494 goto out;
d1ac91d8 3495 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3496
b772ff36 3497 r = -ENOMEM;
d1ac91d8 3498 if (!u.lapic)
b772ff36 3499 goto out;
d1ac91d8 3500 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3501 if (r)
3502 goto out;
3503 r = -EFAULT;
d1ac91d8 3504 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3505 goto out;
3506 r = 0;
3507 break;
3508 }
3509 case KVM_SET_LAPIC: {
2204ae3c 3510 r = -EINVAL;
bce87cce 3511 if (!lapic_in_kernel(vcpu))
2204ae3c 3512 goto out;
ff5c2c03 3513 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3514 if (IS_ERR(u.lapic)) {
3515 r = PTR_ERR(u.lapic);
3516 goto out_nofree;
3517 }
ff5c2c03 3518
d1ac91d8 3519 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3520 break;
3521 }
f77bc6a4
ZX		 3522 case KVM_INTERRUPT: {
3523 struct kvm_interrupt irq;
3524
3525 r = -EFAULT;
3526 if (copy_from_user(&irq, argp, sizeof irq))
3527 goto out;
3528 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3529 break;
3530 }
c4abb7c9
JK		 3531 case KVM_NMI: {
3532 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3533 break;
3534 }
f077825a
PB		 3535 case KVM_SMI: {
3536 r = kvm_vcpu_ioctl_smi(vcpu);
3537 break;
3538 }
313a3dc7
CO		 3539 case KVM_SET_CPUID: {
3540 struct kvm_cpuid __user *cpuid_arg = argp;
3541 struct kvm_cpuid cpuid;
3542
3543 r = -EFAULT;
3544 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3545 goto out;
3546 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3547 break;
3548 }
07716717
DK		 3549 case KVM_SET_CPUID2: {
3550 struct kvm_cpuid2 __user *cpuid_arg = argp;
3551 struct kvm_cpuid2 cpuid;
3552
3553 r = -EFAULT;
3554 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3555 goto out;
3556 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3557 cpuid_arg->entries);
07716717
DK		 3558 break;
3559 }
3560 case KVM_GET_CPUID2: {
3561 struct kvm_cpuid2 __user *cpuid_arg = argp;
3562 struct kvm_cpuid2 cpuid;
3563
3564 r = -EFAULT;
3565 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3566 goto out;
3567 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3568 cpuid_arg->entries);
07716717
DK		 3569 if (r)
3570 goto out;
3571 r = -EFAULT;
3572 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3573 goto out;
3574 r = 0;
3575 break;
3576 }
313a3dc7 3577 case KVM_GET_MSRS:
609e36d3 3578 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3579 break;
3580 case KVM_SET_MSRS:
3581 r = msr_io(vcpu, argp, do_set_msr, 0);
3582 break;
b209749f
AK		 3583 case KVM_TPR_ACCESS_REPORTING: {
3584 struct kvm_tpr_access_ctl tac;
3585
3586 r = -EFAULT;
3587 if (copy_from_user(&tac, argp, sizeof tac))
3588 goto out;
3589 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3590 if (r)
3591 goto out;
3592 r = -EFAULT;
3593 if (copy_to_user(argp, &tac, sizeof tac))
3594 goto out;
3595 r = 0;
3596 break;
3597 };
b93463aa
AK		 3598 case KVM_SET_VAPIC_ADDR: {
3599 struct kvm_vapic_addr va;
7301d6ab 3600 int idx;
b93463aa
AK		 3601
3602 r = -EINVAL;
35754c98 3603 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3604 goto out;
3605 r = -EFAULT;
3606 if (copy_from_user(&va, argp, sizeof va))
3607 goto out;
7301d6ab 3608 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3609 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3610 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3611 break;
3612 }
890ca9ae
HY		 3613 case KVM_X86_SETUP_MCE: {
3614 u64 mcg_cap;
3615
3616 r = -EFAULT;
3617 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3618 goto out;
3619 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3620 break;
3621 }
3622 case KVM_X86_SET_MCE: {
3623 struct kvm_x86_mce mce;
3624
3625 r = -EFAULT;
3626 if (copy_from_user(&mce, argp, sizeof mce))
3627 goto out;
3628 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3629 break;
3630 }
3cfc3092
JK		 3631 case KVM_GET_VCPU_EVENTS: {
3632 struct kvm_vcpu_events events;
3633
3634 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3635
3636 r = -EFAULT;
3637 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3638 break;
3639 r = 0;
3640 break;
3641 }
3642 case KVM_SET_VCPU_EVENTS: {
3643 struct kvm_vcpu_events events;
3644
3645 r = -EFAULT;
3646 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3647 break;
3648
3649 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3650 break;
3651 }
a1efbe77
JK		 3652 case KVM_GET_DEBUGREGS: {
3653 struct kvm_debugregs dbgregs;
3654
3655 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3656
3657 r = -EFAULT;
3658 if (copy_to_user(argp, &dbgregs,
3659 sizeof(struct kvm_debugregs)))
3660 break;
3661 r = 0;
3662 break;
3663 }
3664 case KVM_SET_DEBUGREGS: {
3665 struct kvm_debugregs dbgregs;
3666
3667 r = -EFAULT;
3668 if (copy_from_user(&dbgregs, argp,
3669 sizeof(struct kvm_debugregs)))
3670 break;
3671
3672 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3673 break;
3674 }
2d5b5a66 3675 case KVM_GET_XSAVE: {
d1ac91d8 3676 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3677 r = -ENOMEM;
d1ac91d8 3678 if (!u.xsave)
2d5b5a66
SY		 3679 break;
3680
d1ac91d8 3681 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3682
3683 r = -EFAULT;
d1ac91d8 3684 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3685 break;
3686 r = 0;
3687 break;
3688 }
3689 case KVM_SET_XSAVE: {
ff5c2c03 3690 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3691 if (IS_ERR(u.xsave)) {
3692 r = PTR_ERR(u.xsave);
3693 goto out_nofree;
3694 }
2d5b5a66 3695
d1ac91d8 3696 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3697 break;
3698 }
3699 case KVM_GET_XCRS: {
d1ac91d8 3700 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3701 r = -ENOMEM;
d1ac91d8 3702 if (!u.xcrs)
2d5b5a66
SY		 3703 break;
3704
d1ac91d8 3705 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3706
3707 r = -EFAULT;
d1ac91d8 3708 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3709 sizeof(struct kvm_xcrs)))
3710 break;
3711 r = 0;
3712 break;
3713 }
3714 case KVM_SET_XCRS: {
ff5c2c03 3715 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3716 if (IS_ERR(u.xcrs)) {
3717 r = PTR_ERR(u.xcrs);
3718 goto out_nofree;
3719 }
2d5b5a66 3720
d1ac91d8 3721 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3722 break;
3723 }
92a1f12d
JR		 3724 case KVM_SET_TSC_KHZ: {
3725 u32 user_tsc_khz;
3726
3727 r = -EINVAL;
92a1f12d
JR		 3728 user_tsc_khz = (u32)arg;
3729
3730 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3731 goto out;
3732
cc578287
ZA		 3733 if (user_tsc_khz == 0)
3734 user_tsc_khz = tsc_khz;
3735
381d585c
HZ		 3736 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3737 r = 0;
92a1f12d 3738
92a1f12d
JR		 3739 goto out;
3740 }
3741 case KVM_GET_TSC_KHZ: {
cc578287 3742 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3743 goto out;
3744 }
1c0b28c2
EM		 3745 case KVM_KVMCLOCK_CTRL: {
3746 r = kvm_set_guest_paused(vcpu);
3747 goto out;
3748 }
5c919412
AS		 3749 case KVM_ENABLE_CAP: {
3750 struct kvm_enable_cap cap;
3751
3752 r = -EFAULT;
3753 if (copy_from_user(&cap, argp, sizeof(cap)))
3754 goto out;
3755 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3756 break;
3757 }
313a3dc7
CO		 3758 default:
3759 r = -EINVAL;
3760 }
3761out:
d1ac91d8 3762 kfree(u.buffer);
9b062471
CD		 3763out_nofree:
3764 vcpu_put(vcpu);
313a3dc7
CO		 3765 return r;
3766}
3767
5b1c1493
CO		 3768int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3769{
3770 return VM_FAULT_SIGBUS;
3771}
3772
1fe779f8
CO		 3773static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3774{
3775 int ret;
3776
3777 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3778 return -EINVAL;
1fe779f8
CO		 3779 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3780 return ret;
3781}
3782
b927a3ce
SY		 3783static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3784 u64 ident_addr)
3785{
3786 kvm->arch.ept_identity_map_addr = ident_addr;
3787 return 0;
3788}
3789
1fe779f8
CO		 3790static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3791 u32 kvm_nr_mmu_pages)
3792{
3793 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3794 return -EINVAL;
3795
79fac95e 3796 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3797
3798 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3799 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3800
79fac95e 3801 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3802 return 0;
3803}
3804
3805static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3806{
39de71ec 3807 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3808}
3809
1fe779f8
CO		 3810static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3811{
90bca052 3812 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3813 int r;
3814
3815 r = 0;
3816 switch (chip->chip_id) {
3817 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3818 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3819 sizeof(struct kvm_pic_state));
3820 break;
3821 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3822 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3823 sizeof(struct kvm_pic_state));
3824 break;
3825 case KVM_IRQCHIP_IOAPIC:
33392b49 3826 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3827 break;
3828 default:
3829 r = -EINVAL;
3830 break;
3831 }
3832 return r;
3833}
3834
3835static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3836{
90bca052 3837 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3838 int r;
3839
3840 r = 0;
3841 switch (chip->chip_id) {
3842 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3843 spin_lock(&pic->lock);
3844 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3845 sizeof(struct kvm_pic_state));
90bca052 3846 spin_unlock(&pic->lock);
1fe779f8
CO		 3847 break;
3848 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3849 spin_lock(&pic->lock);
3850 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3851 sizeof(struct kvm_pic_state));
90bca052 3852 spin_unlock(&pic->lock);
1fe779f8
CO		 3853 break;
3854 case KVM_IRQCHIP_IOAPIC:
33392b49 3855 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3856 break;
3857 default:
3858 r = -EINVAL;
3859 break;
3860 }
90bca052 3861 kvm_pic_update_irq(pic);
1fe779f8
CO		 3862 return r;
3863}
3864
e0f63cb9
SY		 3865static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3866{
34f3941c
RK		 3867 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3868
3869 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3870
3871 mutex_lock(&kps->lock);
3872 memcpy(ps, &kps->channels, sizeof(*ps));
3873 mutex_unlock(&kps->lock);
2da29bcc 3874 return 0;
e0f63cb9
SY		 3875}
3876
3877static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3878{
0185604c 3879 int i;
09edea72
RK		 3880 struct kvm_pit *pit = kvm->arch.vpit;
3881
3882 mutex_lock(&pit->pit_state.lock);
34f3941c 3883 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3884 for (i = 0; i < 3; i++)
09edea72
RK		 3885 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3886 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3887 return 0;
e9f42757
BK		 3888}
3889
3890static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3891{
e9f42757
BK		 3892 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3893 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3894 sizeof(ps->channels));
3895 ps->flags = kvm->arch.vpit->pit_state.flags;
3896 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3897 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3898 return 0;
e9f42757
BK		 3899}
3900
3901static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3902{
2da29bcc 3903 int start = 0;
0185604c 3904 int i;
e9f42757 3905 u32 prev_legacy, cur_legacy;
09edea72
RK		 3906 struct kvm_pit *pit = kvm->arch.vpit;
3907
3908 mutex_lock(&pit->pit_state.lock);
3909 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3910 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3911 if (!prev_legacy && cur_legacy)
3912 start = 1;
09edea72
RK		 3913 memcpy(&pit->pit_state.channels, &ps->channels,
3914 sizeof(pit->pit_state.channels));
3915 pit->pit_state.flags = ps->flags;
0185604c 3916 for (i = 0; i < 3; i++)
09edea72 3917 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3918 start && i == 0);
09edea72 3919 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3920 return 0;
e0f63cb9
SY		 3921}
3922
52d939a0
MT		 3923static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3924 struct kvm_reinject_control *control)
3925{
71474e2f
RK		 3926 struct kvm_pit *pit = kvm->arch.vpit;
3927
3928 if (!pit)
52d939a0 3929 return -ENXIO;
b39c90b6 3930
71474e2f
RK		 3931 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3932 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3933 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3934 */
3935 mutex_lock(&pit->pit_state.lock);
3936 kvm_pit_set_reinject(pit, control->pit_reinject);
3937 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3938
52d939a0
MT		 3939 return 0;
3940}
3941
95d4c16c 3942/**
60c34612
TY		 3943 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3944 * @kvm: kvm instance
3945 * @log: slot id and address to which we copy the log
95d4c16c 3946 *
e108ff2f
PB		 3947 * Steps 1-4 below provide general overview of dirty page logging. See
3948 * kvm_get_dirty_log_protect() function description for additional details.
3949 *
3950 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3951 * always flush the TLB (step 4) even if previous step failed and the dirty
3952 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3953 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3954 * writes will be marked dirty for next log read.
95d4c16c 3955 *
60c34612
TY		 3956 * 1. Take a snapshot of the bit and clear it if needed.
3957 * 2. Write protect the corresponding page.
e108ff2f
PB		 3958 * 3. Copy the snapshot to the userspace.
3959 * 4. Flush TLB's if needed.
5bb064dc 3960 */
60c34612 3961int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3962{
60c34612 3963 bool is_dirty = false;
e108ff2f 3964 int r;
5bb064dc 3965
79fac95e 3966 mutex_lock(&kvm->slots_lock);
5bb064dc 3967
88178fd4
KH		 3968 /*
3969 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3970 */
3971 if (kvm_x86_ops->flush_log_dirty)
3972 kvm_x86_ops->flush_log_dirty(kvm);
3973
e108ff2f 3974 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3975
3976 /*
3977 * All the TLBs can be flushed out of mmu lock, see the comments in
3978 * kvm_mmu_slot_remove_write_access().
3979 */
e108ff2f 3980 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3981 if (is_dirty)
3982 kvm_flush_remote_tlbs(kvm);
3983
79fac95e 3984 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3985 return r;
3986}
3987
aa2fbe6d
YZ		 3988int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3989 bool line_status)
23d43cf9
CD		 3990{
3991 if (!irqchip_in_kernel(kvm))
3992 return -ENXIO;
3993
3994 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3995 irq_event->irq, irq_event->level,
3996 line_status);
23d43cf9
CD		 3997 return 0;
3998}
3999
90de4a18
NA		 4000static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4001 struct kvm_enable_cap *cap)
4002{
4003 int r;
4004
4005 if (cap->flags)
4006 return -EINVAL;
4007
4008 switch (cap->cap) {
4009 case KVM_CAP_DISABLE_QUIRKS:
4010 kvm->arch.disabled_quirks = cap->args[0];
4011 r = 0;
4012 break;
49df6397
SR		 4013 case KVM_CAP_SPLIT_IRQCHIP: {
4014 mutex_lock(&kvm->lock);
b053b2ae
SR		 4015 r = -EINVAL;
4016 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4017 goto split_irqchip_unlock;
49df6397
SR		 4018 r = -EEXIST;
4019 if (irqchip_in_kernel(kvm))
4020 goto split_irqchip_unlock;
557abc40 4021 if (kvm->created_vcpus)
49df6397
SR		 4022 goto split_irqchip_unlock;
4023 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4024 if (r)
49df6397
SR		 4025 goto split_irqchip_unlock;
4026 /* Pairs with irqchip_in_kernel. */
4027 smp_wmb();
49776faf 4028 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4029 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4030 r = 0;
4031split_irqchip_unlock:
4032 mutex_unlock(&kvm->lock);
4033 break;
4034 }
37131313
RK		 4035 case KVM_CAP_X2APIC_API:
4036 r = -EINVAL;
4037 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4038 break;
4039
4040 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4041 kvm->arch.x2apic_format = true;
c519265f
RK		 4042 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4043 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4044
4045 r = 0;
4046 break;
90de4a18
NA		 4047 default:
4048 r = -EINVAL;
4049 break;
4050 }
4051 return r;
4052}
4053
1fe779f8
CO		 4054long kvm_arch_vm_ioctl(struct file *filp,
4055 unsigned int ioctl, unsigned long arg)
4056{
4057 struct kvm *kvm = filp->private_data;
4058 void __user *argp = (void __user *)arg;
367e1319 4059 int r = -ENOTTY;
f0d66275
DH		 4060 /*
4061 * This union makes it completely explicit to gcc-3.x
4062 * that these two variables' stack usage should be
4063 * combined, not added together.
4064 */
4065 union {
4066 struct kvm_pit_state ps;
e9f42757 4067 struct kvm_pit_state2 ps2;
c5ff41ce 4068 struct kvm_pit_config pit_config;
f0d66275 4069 } u;
1fe779f8
CO		 4070
4071 switch (ioctl) {
4072 case KVM_SET_TSS_ADDR:
4073 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4074 break;
b927a3ce
SY		 4075 case KVM_SET_IDENTITY_MAP_ADDR: {
4076 u64 ident_addr;
4077
1af1ac91
DH		 4078 mutex_lock(&kvm->lock);
4079 r = -EINVAL;
4080 if (kvm->created_vcpus)
4081 goto set_identity_unlock;
b927a3ce
SY		 4082 r = -EFAULT;
4083 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4084 goto set_identity_unlock;
b927a3ce 4085 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4086set_identity_unlock:
4087 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4088 break;
4089 }
1fe779f8
CO		 4090 case KVM_SET_NR_MMU_PAGES:
4091 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4092 break;
4093 case KVM_GET_NR_MMU_PAGES:
4094 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4095 break;
3ddea128 4096 case KVM_CREATE_IRQCHIP: {
3ddea128 4097 mutex_lock(&kvm->lock);
09941366 4098
3ddea128 4099 r = -EEXIST;
35e6eaa3 4100 if (irqchip_in_kernel(kvm))
3ddea128 4101 goto create_irqchip_unlock;
09941366 4102
3e515705 4103 r = -EINVAL;
557abc40 4104 if (kvm->created_vcpus)
3e515705 4105 goto create_irqchip_unlock;
09941366
RK		 4106
4107 r = kvm_pic_init(kvm);
4108 if (r)
3ddea128 4109 goto create_irqchip_unlock;
09941366
RK		 4110
4111 r = kvm_ioapic_init(kvm);
4112 if (r) {
09941366 4113 kvm_pic_destroy(kvm);
3ddea128 4114 goto create_irqchip_unlock;
09941366
RK		 4115 }
4116
399ec807
AK		 4117 r = kvm_setup_default_irq_routing(kvm);
4118 if (r) {
72bb2fcd 4119 kvm_ioapic_destroy(kvm);
09941366 4120 kvm_pic_destroy(kvm);
71ba994c 4121 goto create_irqchip_unlock;
399ec807 4122 }
49776faf 4123 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4124 smp_wmb();
49776faf 4125 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4126 create_irqchip_unlock:
4127 mutex_unlock(&kvm->lock);
1fe779f8 4128 break;
3ddea128 4129 }
7837699f 4130 case KVM_CREATE_PIT:
c5ff41ce
JK		 4131 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4132 goto create_pit;
4133 case KVM_CREATE_PIT2:
4134 r = -EFAULT;
4135 if (copy_from_user(&u.pit_config, argp,
4136 sizeof(struct kvm_pit_config)))
4137 goto out;
4138 create_pit:
250715a6 4139 mutex_lock(&kvm->lock);
269e05e4
AK		 4140 r = -EEXIST;
4141 if (kvm->arch.vpit)
4142 goto create_pit_unlock;
7837699f 4143 r = -ENOMEM;
c5ff41ce 4144 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4145 if (kvm->arch.vpit)
4146 r = 0;
269e05e4 4147 create_pit_unlock:
250715a6 4148 mutex_unlock(&kvm->lock);
7837699f 4149 break;
1fe779f8
CO		 4150 case KVM_GET_IRQCHIP: {
4151 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4152 struct kvm_irqchip *chip;
1fe779f8 4153
ff5c2c03
SL		 4154 chip = memdup_user(argp, sizeof(*chip));
4155 if (IS_ERR(chip)) {
4156 r = PTR_ERR(chip);
1fe779f8 4157 goto out;
ff5c2c03
SL		 4158 }
4159
1fe779f8 4160 r = -ENXIO;
826da321 4161 if (!irqchip_kernel(kvm))
f0d66275
DH		 4162 goto get_irqchip_out;
4163 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4164 if (r)
f0d66275 4165 goto get_irqchip_out;
1fe779f8 4166 r = -EFAULT;
f0d66275
DH		 4167 if (copy_to_user(argp, chip, sizeof *chip))
4168 goto get_irqchip_out;
1fe779f8 4169 r = 0;
f0d66275
DH		 4170 get_irqchip_out:
4171 kfree(chip);
1fe779f8
CO		 4172 break;
4173 }
4174 case KVM_SET_IRQCHIP: {
4175 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4176 struct kvm_irqchip *chip;
1fe779f8 4177
ff5c2c03
SL		 4178 chip = memdup_user(argp, sizeof(*chip));
4179 if (IS_ERR(chip)) {
4180 r = PTR_ERR(chip);
1fe779f8 4181 goto out;
ff5c2c03
SL		 4182 }
4183
1fe779f8 4184 r = -ENXIO;
826da321 4185 if (!irqchip_kernel(kvm))
f0d66275
DH		 4186 goto set_irqchip_out;
4187 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4188 if (r)
f0d66275 4189 goto set_irqchip_out;
1fe779f8 4190 r = 0;
f0d66275
DH		 4191 set_irqchip_out:
4192 kfree(chip);
1fe779f8
CO		 4193 break;
4194 }
e0f63cb9 4195 case KVM_GET_PIT: {
e0f63cb9 4196 r = -EFAULT;
f0d66275 4197 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4198 goto out;
4199 r = -ENXIO;
4200 if (!kvm->arch.vpit)
4201 goto out;
f0d66275 4202 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4203 if (r)
4204 goto out;
4205 r = -EFAULT;
f0d66275 4206 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4207 goto out;
4208 r = 0;
4209 break;
4210 }
4211 case KVM_SET_PIT: {
e0f63cb9 4212 r = -EFAULT;
f0d66275 4213 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4214 goto out;
4215 r = -ENXIO;
4216 if (!kvm->arch.vpit)
4217 goto out;
f0d66275 4218 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4219 break;
4220 }
e9f42757
BK		 4221 case KVM_GET_PIT2: {
4222 r = -ENXIO;
4223 if (!kvm->arch.vpit)
4224 goto out;
4225 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4226 if (r)
4227 goto out;
4228 r = -EFAULT;
4229 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4230 goto out;
4231 r = 0;
4232 break;
4233 }
4234 case KVM_SET_PIT2: {
4235 r = -EFAULT;
4236 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4237 goto out;
4238 r = -ENXIO;
4239 if (!kvm->arch.vpit)
4240 goto out;
4241 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4242 break;
4243 }
52d939a0
MT		 4244 case KVM_REINJECT_CONTROL: {
4245 struct kvm_reinject_control control;
4246 r = -EFAULT;
4247 if (copy_from_user(&control, argp, sizeof(control)))
4248 goto out;
4249 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4250 break;
4251 }
d71ba788
PB		 4252 case KVM_SET_BOOT_CPU_ID:
4253 r = 0;
4254 mutex_lock(&kvm->lock);
557abc40 4255 if (kvm->created_vcpus)
d71ba788
PB		 4256 r = -EBUSY;
4257 else
4258 kvm->arch.bsp_vcpu_id = arg;
4259 mutex_unlock(&kvm->lock);
4260 break;
ffde22ac
ES		 4261 case KVM_XEN_HVM_CONFIG: {
4262 r = -EFAULT;
4263 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4264 sizeof(struct kvm_xen_hvm_config)))
4265 goto out;
4266 r = -EINVAL;
4267 if (kvm->arch.xen_hvm_config.flags)
4268 goto out;
4269 r = 0;
4270 break;
4271 }
afbcf7ab 4272 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4273 struct kvm_clock_data user_ns;
4274 u64 now_ns;
afbcf7ab
GC		 4275
4276 r = -EFAULT;
4277 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4278 goto out;
4279
4280 r = -EINVAL;
4281 if (user_ns.flags)
4282 goto out;
4283
4284 r = 0;
0bc48bea
RK		 4285 /*
4286 * TODO: userspace has to take care of races with VCPU_RUN, so
4287 * kvm_gen_update_masterclock() can be cut down to locked
4288 * pvclock_update_vm_gtod_copy().
4289 */
4290 kvm_gen_update_masterclock(kvm);
e891a32e 4291 now_ns = get_kvmclock_ns(kvm);
108b249c 4292 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4293 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4294 break;
4295 }
4296 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4297 struct kvm_clock_data user_ns;
4298 u64 now_ns;
4299
e891a32e 4300 now_ns = get_kvmclock_ns(kvm);
108b249c 4301 user_ns.clock = now_ns;
e3fd9a93 4302 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4303 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4304
4305 r = -EFAULT;
4306 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4307 goto out;
4308 r = 0;
4309 break;
4310 }
90de4a18
NA		 4311 case KVM_ENABLE_CAP: {
4312 struct kvm_enable_cap cap;
afbcf7ab 4313
90de4a18
NA		 4314 r = -EFAULT;
4315 if (copy_from_user(&cap, argp, sizeof(cap)))
4316 goto out;
4317 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4318 break;
4319 }
1fe779f8 4320 default:
ad6260da 4321 r = -ENOTTY;
1fe779f8
CO		 4322 }
4323out:
4324 return r;
4325}
4326
a16b043c 4327static void kvm_init_msr_list(void)
043405e1
CO		 4328{
4329 u32 dummy[2];
4330 unsigned i, j;
4331
62ef68bb 4332 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4333 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4334 continue;
93c4adc7
PB		 4335
4336 /*
4337 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4338 * to the guests in some cases.
93c4adc7
PB		 4339 */
4340 switch (msrs_to_save[i]) {
4341 case MSR_IA32_BNDCFGS:
4342 if (!kvm_x86_ops->mpx_supported())
4343 continue;
4344 break;
9dbe6cf9
PB		 4345 case MSR_TSC_AUX:
4346 if (!kvm_x86_ops->rdtscp_supported())
4347 continue;
4348 break;
93c4adc7
PB		 4349 default:
4350 break;
4351 }
4352
043405e1
CO		 4353 if (j < i)
4354 msrs_to_save[j] = msrs_to_save[i];
4355 j++;
4356 }
4357 num_msrs_to_save = j;
62ef68bb
PB		 4358
4359 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4360 switch (emulated_msrs[i]) {
6d396b55
PB		 4361 case MSR_IA32_SMBASE:
4362 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4363 continue;
4364 break;
62ef68bb
PB		 4365 default:
4366 break;
4367 }
4368
4369 if (j < i)
4370 emulated_msrs[j] = emulated_msrs[i];
4371 j++;
4372 }
4373 num_emulated_msrs = j;
043405e1
CO		 4374}
4375
bda9020e
MT		 4376static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4377 const void *v)
bbd9b64e 4378{
70252a10
AK		 4379 int handled = 0;
4380 int n;
4381
4382 do {
4383 n = min(len, 8);
bce87cce 4384 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4385 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4386 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4387 break;
4388 handled += n;
4389 addr += n;
4390 len -= n;
4391 v += n;
4392 } while (len);
bbd9b64e 4393
70252a10 4394 return handled;
bbd9b64e
CO		 4395}
4396
bda9020e 4397static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4398{
70252a10
AK		 4399 int handled = 0;
4400 int n;
4401
4402 do {
4403 n = min(len, 8);
bce87cce 4404 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4405 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4406 addr, n, v))
4407 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4408 break;
4409 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4410 handled += n;
4411 addr += n;
4412 len -= n;
4413 v += n;
4414 } while (len);
bbd9b64e 4415
70252a10 4416 return handled;
bbd9b64e
CO		 4417}
4418
2dafc6c2
GN		 4419static void kvm_set_segment(struct kvm_vcpu *vcpu,
4420 struct kvm_segment *var, int seg)
4421{
4422 kvm_x86_ops->set_segment(vcpu, var, seg);
4423}
4424
4425void kvm_get_segment(struct kvm_vcpu *vcpu,
4426 struct kvm_segment *var, int seg)
4427{
4428 kvm_x86_ops->get_segment(vcpu, var, seg);
4429}
4430
54987b7a
PB		 4431gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4432 struct x86_exception *exception)
02f59dc9
JR		 4433{
4434 gpa_t t_gpa;
02f59dc9
JR		 4435
4436 BUG_ON(!mmu_is_nested(vcpu));
4437
4438 /* NPT walks are always user-walks */
4439 access |= PFERR_USER_MASK;
54987b7a 4440 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4441
4442 return t_gpa;
4443}
4444
ab9ae313
AK		 4445gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4446 struct x86_exception *exception)
1871c602
GN		 4447{
4448 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4449 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4450}
4451
ab9ae313
AK		 4452 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4453 struct x86_exception *exception)
1871c602
GN		 4454{
4455 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4456 access |= PFERR_FETCH_MASK;
ab9ae313 4457 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4458}
4459
ab9ae313
AK		 4460gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4461 struct x86_exception *exception)
1871c602
GN		 4462{
4463 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4464 access |= PFERR_WRITE_MASK;
ab9ae313 4465 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4466}
4467
4468/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4469gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4470 struct x86_exception *exception)
1871c602 4471{
ab9ae313 4472 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4473}
4474
4475static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4476 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4477 struct x86_exception *exception)
bbd9b64e
CO		 4478{
4479 void *data = val;
10589a46 4480 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4481
4482 while (bytes) {
14dfe855 4483 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4484 exception);
bbd9b64e 4485 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4486 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4487 int ret;
4488
bcc55cba 4489 if (gpa == UNMAPPED_GVA)
ab9ae313 4490 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4491 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4492 offset, toread);
10589a46 4493 if (ret < 0) {
c3cd7ffa 4494 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4495 goto out;
4496 }
bbd9b64e 4497
77c2002e
IE		 4498 bytes -= toread;
4499 data += toread;
4500 addr += toread;
bbd9b64e 4501 }
10589a46 4502out:
10589a46 4503 return r;
bbd9b64e 4504}
77c2002e 4505
1871c602 4506/* used for instruction fetching */
0f65dd70
AK		 4507static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4508 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4509 struct x86_exception *exception)
1871c602 4510{
0f65dd70 4511 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4512 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4513 unsigned offset;
4514 int ret;
0f65dd70 4515
44583cba
PB		 4516 /* Inline kvm_read_guest_virt_helper for speed. */
4517 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4518 exception);
4519 if (unlikely(gpa == UNMAPPED_GVA))
4520 return X86EMUL_PROPAGATE_FAULT;
4521
4522 offset = addr & (PAGE_SIZE-1);
4523 if (WARN_ON(offset + bytes > PAGE_SIZE))
4524 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4525 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4526 offset, bytes);
44583cba
PB		 4527 if (unlikely(ret < 0))
4528 return X86EMUL_IO_NEEDED;
4529
4530 return X86EMUL_CONTINUE;
1871c602
GN		 4531}
4532
064aea77 4533int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4534 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4535 struct x86_exception *exception)
1871c602 4536{
0f65dd70 4537 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4538 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4539
1871c602 4540 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4541 exception);
1871c602 4542}
064aea77 4543EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4544
0f65dd70
AK		 4545static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4546 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4547 struct x86_exception *exception)
1871c602 4548{
0f65dd70 4549 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4550 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4551}
4552
7a036a6f
RK		 4553static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4554 unsigned long addr, void *val, unsigned int bytes)
4555{
4556 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4557 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4558
4559 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4560}
4561
6a4d7550 4562int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4563 gva_t addr, void *val,
2dafc6c2 4564 unsigned int bytes,
bcc55cba 4565 struct x86_exception *exception)
77c2002e 4566{
0f65dd70 4567 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4568 void *data = val;
4569 int r = X86EMUL_CONTINUE;
4570
4571 while (bytes) {
14dfe855
JR		 4572 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4573 PFERR_WRITE_MASK,
ab9ae313 4574 exception);
77c2002e
IE		 4575 unsigned offset = addr & (PAGE_SIZE-1);
4576 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4577 int ret;
4578
bcc55cba 4579 if (gpa == UNMAPPED_GVA)
ab9ae313 4580 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4581 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4582 if (ret < 0) {
c3cd7ffa 4583 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4584 goto out;
4585 }
4586
4587 bytes -= towrite;
4588 data += towrite;
4589 addr += towrite;
4590 }
4591out:
4592 return r;
4593}
6a4d7550 4594EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4595
0f89b207
TL		 4596static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4597 gpa_t gpa, bool write)
4598{
4599 /* For APIC access vmexit */
4600 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4601 return 1;
4602
4603 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4604 trace_vcpu_match_mmio(gva, gpa, write, true);
4605 return 1;
4606 }
4607
4608 return 0;
4609}
4610
af7cc7d1
XG		 4611static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4612 gpa_t *gpa, struct x86_exception *exception,
4613 bool write)
4614{
97d64b78
AK		 4615 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4616 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4617
be94f6b7
HH		 4618 /*
4619 * currently PKRU is only applied to ept enabled guest so
4620 * there is no pkey in EPT page table for L1 guest or EPT
4621 * shadow page table for L2 guest.
4622 */
97d64b78 4623 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4624 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4625 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4626 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4627 (gva & (PAGE_SIZE - 1));
4f022648 4628 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4629 return 1;
4630 }
4631
af7cc7d1
XG		 4632 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4633
4634 if (*gpa == UNMAPPED_GVA)
4635 return -1;
4636
0f89b207 4637 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4638}
4639
3200f405 4640int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4641 const void *val, int bytes)
bbd9b64e
CO		 4642{
4643 int ret;
4644
54bf36aa 4645 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4646 if (ret < 0)
bbd9b64e 4647 return 0;
0eb05bf2 4648 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4649 return 1;
4650}
4651
77d197b2
XG		 4652struct read_write_emulator_ops {
4653 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4654 int bytes);
4655 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4656 void *val, int bytes);
4657 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4658 int bytes, void *val);
4659 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4660 void *val, int bytes);
4661 bool write;
4662};
4663
4664static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4665{
4666 if (vcpu->mmio_read_completed) {
77d197b2 4667 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4668 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4669 vcpu->mmio_read_completed = 0;
4670 return 1;
4671 }
4672
4673 return 0;
4674}
4675
4676static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4677 void *val, int bytes)
4678{
54bf36aa 4679 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4680}
4681
4682static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4683 void *val, int bytes)
4684{
4685 return emulator_write_phys(vcpu, gpa, val, bytes);
4686}
4687
4688static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4689{
4690 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4691 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4692}
4693
4694static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4695 void *val, int bytes)
4696{
4697 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4698 return X86EMUL_IO_NEEDED;
4699}
4700
4701static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4702 void *val, int bytes)
4703{
f78146b0
AK		 4704 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4705
87da7e66 4706 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4707 return X86EMUL_CONTINUE;
4708}
4709
0fbe9b0b 4710static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4711 .read_write_prepare = read_prepare,
4712 .read_write_emulate = read_emulate,
4713 .read_write_mmio = vcpu_mmio_read,
4714 .read_write_exit_mmio = read_exit_mmio,
4715};
4716
0fbe9b0b 4717static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4718 .read_write_emulate = write_emulate,
4719 .read_write_mmio = write_mmio,
4720 .read_write_exit_mmio = write_exit_mmio,
4721 .write = true,
4722};
4723
22388a3c
XG		 4724static int emulator_read_write_onepage(unsigned long addr, void *val,
4725 unsigned int bytes,
4726 struct x86_exception *exception,
4727 struct kvm_vcpu *vcpu,
0fbe9b0b 4728 const struct read_write_emulator_ops *ops)
bbd9b64e 4729{
af7cc7d1
XG		 4730 gpa_t gpa;
4731 int handled, ret;
22388a3c 4732 bool write = ops->write;
f78146b0 4733 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4734 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4735
4736 /*
4737 * If the exit was due to a NPF we may already have a GPA.
4738 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4739 * Note, this cannot be used on string operations since string
4740 * operation using rep will only have the initial GPA from the NPF
4741 * occurred.
4742 */
4743 if (vcpu->arch.gpa_available &&
4744 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4745 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4746 gpa = vcpu->arch.gpa_val;
4747 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4748 } else {
4749 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4750 if (ret < 0)
4751 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4752 }
10589a46 4753
618232e2 4754 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4755 return X86EMUL_CONTINUE;
4756
bbd9b64e
CO		 4757 /*
4758 * Is this MMIO handled locally?
4759 */
22388a3c 4760 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4761 if (handled == bytes)
bbd9b64e 4762 return X86EMUL_CONTINUE;
bbd9b64e 4763
70252a10
AK		 4764 gpa += handled;
4765 bytes -= handled;
4766 val += handled;
4767
87da7e66
XG		 4768 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4769 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4770 frag->gpa = gpa;
4771 frag->data = val;
4772 frag->len = bytes;
f78146b0 4773 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4774}
4775
52eb5a6d
XL		 4776static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4777 unsigned long addr,
22388a3c
XG		 4778 void *val, unsigned int bytes,
4779 struct x86_exception *exception,
0fbe9b0b 4780 const struct read_write_emulator_ops *ops)
bbd9b64e 4781{
0f65dd70 4782 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4783 gpa_t gpa;
4784 int rc;
4785
4786 if (ops->read_write_prepare &&
4787 ops->read_write_prepare(vcpu, val, bytes))
4788 return X86EMUL_CONTINUE;
4789
4790 vcpu->mmio_nr_fragments = 0;
0f65dd70 4791
bbd9b64e
CO		 4792 /* Crossing a page boundary? */
4793 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4794 int now;
bbd9b64e
CO		 4795
4796 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4797 rc = emulator_read_write_onepage(addr, val, now, exception,
4798 vcpu, ops);
4799
bbd9b64e
CO		 4800 if (rc != X86EMUL_CONTINUE)
4801 return rc;
4802 addr += now;
bac15531
NA		 4803 if (ctxt->mode != X86EMUL_MODE_PROT64)
4804 addr = (u32)addr;
bbd9b64e
CO		 4805 val += now;
4806 bytes -= now;
4807 }
22388a3c 4808
f78146b0
AK		 4809 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4810 vcpu, ops);
4811 if (rc != X86EMUL_CONTINUE)
4812 return rc;
4813
4814 if (!vcpu->mmio_nr_fragments)
4815 return rc;
4816
4817 gpa = vcpu->mmio_fragments[0].gpa;
4818
4819 vcpu->mmio_needed = 1;
4820 vcpu->mmio_cur_fragment = 0;
4821
87da7e66 4822 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4823 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4824 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4825 vcpu->run->mmio.phys_addr = gpa;
4826
4827 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4828}
4829
4830static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4831 unsigned long addr,
4832 void *val,
4833 unsigned int bytes,
4834 struct x86_exception *exception)
4835{
4836 return emulator_read_write(ctxt, addr, val, bytes,
4837 exception, &read_emultor);
4838}
4839
52eb5a6d 4840static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4841 unsigned long addr,
4842 const void *val,
4843 unsigned int bytes,
4844 struct x86_exception *exception)
4845{
4846 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4847 exception, &write_emultor);
bbd9b64e 4848}
bbd9b64e 4849
daea3e73
AK		 4850#define CMPXCHG_TYPE(t, ptr, old, new) \
4851 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4852
4853#ifdef CONFIG_X86_64
4854# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4855#else
4856# define CMPXCHG64(ptr, old, new) \
9749a6c0 4857 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4858#endif
4859
0f65dd70
AK		 4860static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4861 unsigned long addr,
bbd9b64e
CO		 4862 const void *old,
4863 const void *new,
4864 unsigned int bytes,
0f65dd70 4865 struct x86_exception *exception)
bbd9b64e 4866{
0f65dd70 4867 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4868 gpa_t gpa;
4869 struct page *page;
4870 char *kaddr;
4871 bool exchanged;
2bacc55c 4872
daea3e73
AK		 4873 /* guests cmpxchg8b have to be emulated atomically */
4874 if (bytes > 8 || (bytes & (bytes - 1)))
4875 goto emul_write;
10589a46 4876
daea3e73 4877 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4878
daea3e73
AK		 4879 if (gpa == UNMAPPED_GVA ||
4880 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4881 goto emul_write;
2bacc55c 4882
daea3e73
AK		 4883 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4884 goto emul_write;
72dc67a6 4885
54bf36aa 4886 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4887 if (is_error_page(page))
c19b8bd6 4888 goto emul_write;
72dc67a6 4889
8fd75e12 4890 kaddr = kmap_atomic(page);
daea3e73
AK		 4891 kaddr += offset_in_page(gpa);
4892 switch (bytes) {
4893 case 1:
4894 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4895 break;
4896 case 2:
4897 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4898 break;
4899 case 4:
4900 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4901 break;
4902 case 8:
4903 exchanged = CMPXCHG64(kaddr, old, new);
4904 break;
4905 default:
4906 BUG();
2bacc55c 4907 }
8fd75e12 4908 kunmap_atomic(kaddr);
daea3e73
AK		 4909 kvm_release_page_dirty(page);
4910
4911 if (!exchanged)
4912 return X86EMUL_CMPXCHG_FAILED;
4913
54bf36aa 4914 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4915 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4916
4917 return X86EMUL_CONTINUE;
4a5f48f6 4918
3200f405 4919emul_write:
daea3e73 4920 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4921
0f65dd70 4922 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4923}
4924
cf8f70bf
GN		 4925static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4926{
cbfc6c91 4927 int r = 0, i;
cf8f70bf 4928
cbfc6c91
WL		 4929 for (i = 0; i < vcpu->arch.pio.count; i++) {
4930 if (vcpu->arch.pio.in)
4931 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4932 vcpu->arch.pio.size, pd);
4933 else
4934 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4935 vcpu->arch.pio.port, vcpu->arch.pio.size,
4936 pd);
4937 if (r)
4938 break;
4939 pd += vcpu->arch.pio.size;
4940 }
cf8f70bf
GN		 4941 return r;
4942}
4943
6f6fbe98
XG		 4944static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4945 unsigned short port, void *val,
4946 unsigned int count, bool in)
cf8f70bf 4947{
cf8f70bf 4948 vcpu->arch.pio.port = port;
6f6fbe98 4949 vcpu->arch.pio.in = in;
7972995b 4950 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4951 vcpu->arch.pio.size = size;
4952
4953 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4954 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4955 return 1;
4956 }
4957
4958 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4959 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4960 vcpu->run->io.size = size;
4961 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4962 vcpu->run->io.count = count;
4963 vcpu->run->io.port = port;
4964
4965 return 0;
4966}
4967
6f6fbe98
XG		 4968static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4969 int size, unsigned short port, void *val,
4970 unsigned int count)
cf8f70bf 4971{
ca1d4a9e 4972 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4973 int ret;
ca1d4a9e 4974
6f6fbe98
XG		 4975 if (vcpu->arch.pio.count)
4976 goto data_avail;
cf8f70bf 4977
cbfc6c91
WL		 4978 memset(vcpu->arch.pio_data, 0, size * count);
4979
6f6fbe98
XG		 4980 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4981 if (ret) {
4982data_avail:
4983 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4984 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4985 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4986 return 1;
4987 }
4988
cf8f70bf
GN		 4989 return 0;
4990}
4991
6f6fbe98
XG		 4992static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4993 int size, unsigned short port,
4994 const void *val, unsigned int count)
4995{
4996 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4997
4998 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4999 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5000 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5001}
5002
bbd9b64e
CO		 5003static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5004{
5005 return kvm_x86_ops->get_segment_base(vcpu, seg);
5006}
5007
3cb16fe7 5008static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5009{
3cb16fe7 5010 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5011}
5012
ae6a2375 5013static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5014{
5015 if (!need_emulate_wbinvd(vcpu))
5016 return X86EMUL_CONTINUE;
5017
5018 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5019 int cpu = get_cpu();
5020
5021 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5022 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5023 wbinvd_ipi, NULL, 1);
2eec7343 5024 put_cpu();
f5f48ee1 5025 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5026 } else
5027 wbinvd();
f5f48ee1
SY		 5028 return X86EMUL_CONTINUE;
5029}
5cb56059
JS		 5030
5031int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5032{
6affcbed
KH		 5033 kvm_emulate_wbinvd_noskip(vcpu);
5034 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5035}
f5f48ee1
SY		 5036EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5037
5cb56059
JS		 5038
5039
bcaf5cc5
AK		 5040static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5041{
5cb56059 5042 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5043}
5044
52eb5a6d
XL		 5045static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5046 unsigned long *dest)
bbd9b64e 5047{
16f8a6f9 5048 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5049}
5050
52eb5a6d
XL		 5051static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5052 unsigned long value)
bbd9b64e 5053{
338dbc97 5054
717746e3 5055 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5056}
5057
52a46617 5058static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5059{
52a46617 5060 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5061}
5062
717746e3 5063static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5064{
717746e3 5065 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5066 unsigned long value;
5067
5068 switch (cr) {
5069 case 0:
5070 value = kvm_read_cr0(vcpu);
5071 break;
5072 case 2:
5073 value = vcpu->arch.cr2;
5074 break;
5075 case 3:
9f8fe504 5076 value = kvm_read_cr3(vcpu);
52a46617
GN		 5077 break;
5078 case 4:
5079 value = kvm_read_cr4(vcpu);
5080 break;
5081 case 8:
5082 value = kvm_get_cr8(vcpu);
5083 break;
5084 default:
a737f256 5085 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5086 return 0;
5087 }
5088
5089 return value;
5090}
5091
717746e3 5092static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5093{
717746e3 5094 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5095 int res = 0;
5096
52a46617
GN		 5097 switch (cr) {
5098 case 0:
49a9b07e 5099 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5100 break;
5101 case 2:
5102 vcpu->arch.cr2 = val;
5103 break;
5104 case 3:
2390218b 5105 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5106 break;
5107 case 4:
a83b29c6 5108 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5109 break;
5110 case 8:
eea1cff9 5111 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5112 break;
5113 default:
a737f256 5114 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5115 res = -1;
52a46617 5116 }
0f12244f
GN		 5117
5118 return res;
52a46617
GN		 5119}
5120
717746e3 5121static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5122{
717746e3 5123 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5124}
5125
4bff1e86 5126static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5127{
4bff1e86 5128 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5129}
5130
4bff1e86 5131static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5132{
4bff1e86 5133 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5134}
5135
1ac9d0cf
AK		 5136static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5137{
5138 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5139}
5140
5141static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5142{
5143 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5144}
5145
4bff1e86
AK		 5146static unsigned long emulator_get_cached_segment_base(
5147 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5148{
4bff1e86 5149 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5150}
5151
1aa36616
AK		 5152static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5153 struct desc_struct *desc, u32 *base3,
5154 int seg)
2dafc6c2
GN		 5155{
5156 struct kvm_segment var;
5157
4bff1e86 5158 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5159 *selector = var.selector;
2dafc6c2 5160
378a8b09
GN		 5161 if (var.unusable) {
5162 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5163 if (base3)
5164 *base3 = 0;
2dafc6c2 5165 return false;
378a8b09 5166 }
2dafc6c2
GN		 5167
5168 if (var.g)
5169 var.limit >>= 12;
5170 set_desc_limit(desc, var.limit);
5171 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5172#ifdef CONFIG_X86_64
5173 if (base3)
5174 *base3 = var.base >> 32;
5175#endif
2dafc6c2
GN		 5176 desc->type = var.type;
5177 desc->s = var.s;
5178 desc->dpl = var.dpl;
5179 desc->p = var.present;
5180 desc->avl = var.avl;
5181 desc->l = var.l;
5182 desc->d = var.db;
5183 desc->g = var.g;
5184
5185 return true;
5186}
5187
1aa36616
AK		 5188static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5189 struct desc_struct *desc, u32 base3,
5190 int seg)
2dafc6c2 5191{
4bff1e86 5192 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5193 struct kvm_segment var;
5194
1aa36616 5195 var.selector = selector;
2dafc6c2 5196 var.base = get_desc_base(desc);
5601d05b
GN		 5197#ifdef CONFIG_X86_64
5198 var.base |= ((u64)base3) << 32;
5199#endif
2dafc6c2
GN		 5200 var.limit = get_desc_limit(desc);
5201 if (desc->g)
5202 var.limit = (var.limit << 12) | 0xfff;
5203 var.type = desc->type;
2dafc6c2
GN		 5204 var.dpl = desc->dpl;
5205 var.db = desc->d;
5206 var.s = desc->s;
5207 var.l = desc->l;
5208 var.g = desc->g;
5209 var.avl = desc->avl;
5210 var.present = desc->p;
5211 var.unusable = !var.present;
5212 var.padding = 0;
5213
5214 kvm_set_segment(vcpu, &var, seg);
5215 return;
5216}
5217
717746e3
AK		 5218static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5219 u32 msr_index, u64 *pdata)
5220{
609e36d3
PB		 5221 struct msr_data msr;
5222 int r;
5223
5224 msr.index = msr_index;
5225 msr.host_initiated = false;
5226 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5227 if (r)
5228 return r;
5229
5230 *pdata = msr.data;
5231 return 0;
717746e3
AK		 5232}
5233
5234static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5235 u32 msr_index, u64 data)
5236{
8fe8ab46
WA		 5237 struct msr_data msr;
5238
5239 msr.data = data;
5240 msr.index = msr_index;
5241 msr.host_initiated = false;
5242 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5243}
5244
64d60670
PB		 5245static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5246{
5247 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5248
5249 return vcpu->arch.smbase;
5250}
5251
5252static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5253{
5254 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5255
5256 vcpu->arch.smbase = smbase;
5257}
5258
67f4d428
NA		 5259static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5260 u32 pmc)
5261{
c6702c9d 5262 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5263}
5264
222d21aa
AK		 5265static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5266 u32 pmc, u64 *pdata)
5267{
c6702c9d 5268 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5269}
5270
6c3287f7
AK		 5271static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5272{
5273 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5274}
5275
2953538e 5276static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5277 struct x86_instruction_info *info,
c4f035c6
AK		 5278 enum x86_intercept_stage stage)
5279{
2953538e 5280 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5281}
5282
e911eb3b
YZ		 5283static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5284 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5285{
e911eb3b 5286 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5287}
5288
dd856efa
AK		 5289static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5290{
5291 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5292}
5293
5294static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5295{
5296 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5297}
5298
801806d9
NA		 5299static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5300{
5301 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5302}
5303
6ed071f0
LP		 5304static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5305{
5306 return emul_to_vcpu(ctxt)->arch.hflags;
5307}
5308
5309static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5310{
5311 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5312}
5313
0234bf88
LP		 5314static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5315{
5316 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5317}
5318
0225fb50 5319static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5320 .read_gpr = emulator_read_gpr,
5321 .write_gpr = emulator_write_gpr,
1871c602 5322 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5323 .write_std = kvm_write_guest_virt_system,
7a036a6f 5324 .read_phys = kvm_read_guest_phys_system,
1871c602 5325 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5326 .read_emulated = emulator_read_emulated,
5327 .write_emulated = emulator_write_emulated,
5328 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5329 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5330 .pio_in_emulated = emulator_pio_in_emulated,
5331 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5332 .get_segment = emulator_get_segment,
5333 .set_segment = emulator_set_segment,
5951c442 5334 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5335 .get_gdt = emulator_get_gdt,
160ce1f1 5336 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5337 .set_gdt = emulator_set_gdt,
5338 .set_idt = emulator_set_idt,
52a46617
GN		 5339 .get_cr = emulator_get_cr,
5340 .set_cr = emulator_set_cr,
9c537244 5341 .cpl = emulator_get_cpl,
35aa5375
GN		 5342 .get_dr = emulator_get_dr,
5343 .set_dr = emulator_set_dr,
64d60670
PB		 5344 .get_smbase = emulator_get_smbase,
5345 .set_smbase = emulator_set_smbase,
717746e3
AK		 5346 .set_msr = emulator_set_msr,
5347 .get_msr = emulator_get_msr,
67f4d428 5348 .check_pmc = emulator_check_pmc,
222d21aa 5349 .read_pmc = emulator_read_pmc,
6c3287f7 5350 .halt = emulator_halt,
bcaf5cc5 5351 .wbinvd = emulator_wbinvd,
d6aa1000 5352 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5353 .intercept = emulator_intercept,
bdb42f5a 5354 .get_cpuid = emulator_get_cpuid,
801806d9 5355 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5356 .get_hflags = emulator_get_hflags,
5357 .set_hflags = emulator_set_hflags,
0234bf88 5358 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5359};
5360
95cb2295
GN		 5361static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5362{
37ccdcbe 5363 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5364 /*
5365 * an sti; sti; sequence only disable interrupts for the first
5366 * instruction. So, if the last instruction, be it emulated or
5367 * not, left the system with the INT_STI flag enabled, it
5368 * means that the last instruction is an sti. We should not
5369 * leave the flag on in this case. The same goes for mov ss
5370 */
37ccdcbe
PB		 5371 if (int_shadow & mask)
5372 mask = 0;
6addfc42 5373 if (unlikely(int_shadow || mask)) {
95cb2295 5374 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5375 if (!mask)
5376 kvm_make_request(KVM_REQ_EVENT, vcpu);
5377 }
95cb2295
GN		 5378}
5379
ef54bcfe 5380static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5381{
5382 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5383 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5384 return kvm_propagate_fault(vcpu, &ctxt->exception);
5385
5386 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5387 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5388 ctxt->exception.error_code);
54b8486f 5389 else
da9cb575 5390 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5391 return false;
54b8486f
GN		 5392}
5393
8ec4722d
MG		 5394static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5395{
adf52235 5396 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5397 int cs_db, cs_l;
5398
8ec4722d
MG		 5399 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5400
adf52235 5401 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5402 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5403
adf52235
TY		 5404 ctxt->eip = kvm_rip_read(vcpu);
5405 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5406 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5407 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5408 cs_db ? X86EMUL_MODE_PROT32 :
5409 X86EMUL_MODE_PROT16;
a584539b 5410 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5411 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5412 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5413
dd856efa 5414 init_decode_cache(ctxt);
7ae441ea 5415 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5416}
5417
71f9833b 5418int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5419{
9d74191a 5420 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5421 int ret;
5422
5423 init_emulate_ctxt(vcpu);
5424
9dac77fa
AK		 5425 ctxt->op_bytes = 2;
5426 ctxt->ad_bytes = 2;
5427 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5428 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5429
5430 if (ret != X86EMUL_CONTINUE)
5431 return EMULATE_FAIL;
5432
9dac77fa 5433 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5434 kvm_rip_write(vcpu, ctxt->eip);
5435 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5436
5437 if (irq == NMI_VECTOR)
7460fb4a 5438 vcpu->arch.nmi_pending = 0;
63995653
MG		 5439 else
5440 vcpu->arch.interrupt.pending = false;
5441
5442 return EMULATE_DONE;
5443}
5444EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5445
6d77dbfc
GN		 5446static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5447{
fc3a9157
JR		 5448 int r = EMULATE_DONE;
5449
6d77dbfc
GN		 5450 ++vcpu->stat.insn_emulation_fail;
5451 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5452 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5453 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5454 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5455 vcpu->run->internal.ndata = 0;
1f4dcb3b 5456 r = EMULATE_USER_EXIT;
fc3a9157 5457 }
6d77dbfc 5458 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5459
5460 return r;
6d77dbfc
GN		 5461}
5462
93c05d3e 5463static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5464 bool write_fault_to_shadow_pgtable,
5465 int emulation_type)
a6f177ef 5466{
95b3cf69 5467 gpa_t gpa = cr2;
ba049e93 5468 kvm_pfn_t pfn;
a6f177ef 5469
991eebf9
GN		 5470 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5471 return false;
5472
95b3cf69
XG		 5473 if (!vcpu->arch.mmu.direct_map) {
5474 /*
5475 * Write permission should be allowed since only
5476 * write access need to be emulated.
5477 */
5478 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5479
95b3cf69
XG		 5480 /*
5481 * If the mapping is invalid in guest, let cpu retry
5482 * it to generate fault.
5483 */
5484 if (gpa == UNMAPPED_GVA)
5485 return true;
5486 }
a6f177ef 5487
8e3d9d06
XG		 5488 /*
5489 * Do not retry the unhandleable instruction if it faults on the
5490 * readonly host memory, otherwise it will goto a infinite loop:
5491 * retry instruction -> write #PF -> emulation fail -> retry
5492 * instruction -> ...
5493 */
5494 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5495
5496 /*
5497 * If the instruction failed on the error pfn, it can not be fixed,
5498 * report the error to userspace.
5499 */
5500 if (is_error_noslot_pfn(pfn))
5501 return false;
5502
5503 kvm_release_pfn_clean(pfn);
5504
5505 /* The instructions are well-emulated on direct mmu. */
5506 if (vcpu->arch.mmu.direct_map) {
5507 unsigned int indirect_shadow_pages;
5508
5509 spin_lock(&vcpu->kvm->mmu_lock);
5510 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5511 spin_unlock(&vcpu->kvm->mmu_lock);
5512
5513 if (indirect_shadow_pages)
5514 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5515
a6f177ef 5516 return true;
8e3d9d06 5517 }
a6f177ef 5518
95b3cf69
XG		 5519 /*
5520 * if emulation was due to access to shadowed page table
5521 * and it failed try to unshadow page and re-enter the
5522 * guest to let CPU execute the instruction.
5523 */
5524 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5525
5526 /*
5527 * If the access faults on its page table, it can not
5528 * be fixed by unprotecting shadow page and it should
5529 * be reported to userspace.
5530 */
5531 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5532}
5533
1cb3f3ae
XG		 5534static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5535 unsigned long cr2, int emulation_type)
5536{
5537 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5538 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5539
5540 last_retry_eip = vcpu->arch.last_retry_eip;
5541 last_retry_addr = vcpu->arch.last_retry_addr;
5542
5543 /*
5544 * If the emulation is caused by #PF and it is non-page_table
5545 * writing instruction, it means the VM-EXIT is caused by shadow
5546 * page protected, we can zap the shadow page and retry this
5547 * instruction directly.
5548 *
5549 * Note: if the guest uses a non-page-table modifying instruction
5550 * on the PDE that points to the instruction, then we will unmap
5551 * the instruction and go to an infinite loop. So, we cache the
5552 * last retried eip and the last fault address, if we meet the eip
5553 * and the address again, we can break out of the potential infinite
5554 * loop.
5555 */
5556 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5557
5558 if (!(emulation_type & EMULTYPE_RETRY))
5559 return false;
5560
5561 if (x86_page_table_writing_insn(ctxt))
5562 return false;
5563
5564 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5565 return false;
5566
5567 vcpu->arch.last_retry_eip = ctxt->eip;
5568 vcpu->arch.last_retry_addr = cr2;
5569
5570 if (!vcpu->arch.mmu.direct_map)
5571 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5572
22368028 5573 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5574
5575 return true;
5576}
5577
716d51ab
GN		 5578static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5579static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5580
64d60670 5581static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5582{
64d60670 5583 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5584 /* This is a good place to trace that we are exiting SMM. */
5585 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5586
c43203ca
PB		 5587 /* Process a latched INIT or SMI, if any. */
5588 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5589 }
699023e2
PB		 5590
5591 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5592}
5593
5594static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5595{
5596 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5597
a584539b 5598 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5599
5600 if (changed & HF_SMM_MASK)
5601 kvm_smm_changed(vcpu);
a584539b
PB		 5602}
5603
4a1e10d5
PB		 5604static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5605 unsigned long *db)
5606{
5607 u32 dr6 = 0;
5608 int i;
5609 u32 enable, rwlen;
5610
5611 enable = dr7;
5612 rwlen = dr7 >> 16;
5613 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5614 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5615 dr6 |= (1 << i);
5616 return dr6;
5617}
5618
c8401dda 5619static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5620{
5621 struct kvm_run *kvm_run = vcpu->run;
5622
c8401dda
PB		 5623 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5624 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5625 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5626 kvm_run->debug.arch.exception = DB_VECTOR;
5627 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5628 *r = EMULATE_USER_EXIT;
5629 } else {
5630 /*
5631 * "Certain debug exceptions may clear bit 0-3. The
5632 * remaining contents of the DR6 register are never
5633 * cleared by the processor".
5634 */
5635 vcpu->arch.dr6 &= ~15;
5636 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5637 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5638 }
5639}
5640
6affcbed
KH		 5641int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5642{
5643 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5644 int r = EMULATE_DONE;
5645
5646 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5647
5648 /*
5649 * rflags is the old, "raw" value of the flags. The new value has
5650 * not been saved yet.
5651 *
5652 * This is correct even for TF set by the guest, because "the
5653 * processor will not generate this exception after the instruction
5654 * that sets the TF flag".
5655 */
5656 if (unlikely(rflags & X86_EFLAGS_TF))
5657 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5658 return r == EMULATE_DONE;
5659}
5660EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5661
4a1e10d5
PB		 5662static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5663{
4a1e10d5
PB		 5664 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5665 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5666 struct kvm_run *kvm_run = vcpu->run;
5667 unsigned long eip = kvm_get_linear_rip(vcpu);
5668 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5669 vcpu->arch.guest_debug_dr7,
5670 vcpu->arch.eff_db);
5671
5672 if (dr6 != 0) {
6f43ed01 5673 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5674 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5675 kvm_run->debug.arch.exception = DB_VECTOR;
5676 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5677 *r = EMULATE_USER_EXIT;
5678 return true;
5679 }
5680 }
5681
4161a569
NA		 5682 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5683 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5684 unsigned long eip = kvm_get_linear_rip(vcpu);
5685 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5686 vcpu->arch.dr7,
5687 vcpu->arch.db);
5688
5689 if (dr6 != 0) {
5690 vcpu->arch.dr6 &= ~15;
6f43ed01 5691 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5692 kvm_queue_exception(vcpu, DB_VECTOR);
5693 *r = EMULATE_DONE;
5694 return true;
5695 }
5696 }
5697
5698 return false;
5699}
5700
51d8b661
AP		 5701int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5702 unsigned long cr2,
dc25e89e
AP		 5703 int emulation_type,
5704 void *insn,
5705 int insn_len)
bbd9b64e 5706{
95cb2295 5707 int r;
9d74191a 5708 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5709 bool writeback = true;
93c05d3e 5710 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5711
93c05d3e
XG		 5712 /*
5713 * Clear write_fault_to_shadow_pgtable here to ensure it is
5714 * never reused.
5715 */
5716 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5717 kvm_clear_exception_queue(vcpu);
8d7d8102 5718
571008da 5719 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5720 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5721
5722 /*
5723 * We will reenter on the same instruction since
5724 * we do not set complete_userspace_io. This does not
5725 * handle watchpoints yet, those would be handled in
5726 * the emulate_ops.
5727 */
5728 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5729 return r;
5730
9d74191a
TY		 5731 ctxt->interruptibility = 0;
5732 ctxt->have_exception = false;
e0ad0b47 5733 ctxt->exception.vector = -1;
9d74191a 5734 ctxt->perm_ok = false;
bbd9b64e 5735
b51e974f 5736 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5737
9d74191a 5738 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5739
e46479f8 5740 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5741 ++vcpu->stat.insn_emulation;
1d2887e2 5742 if (r != EMULATION_OK) {
4005996e
AK		 5743 if (emulation_type & EMULTYPE_TRAP_UD)
5744 return EMULATE_FAIL;
991eebf9
GN		 5745 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5746 emulation_type))
bbd9b64e 5747 return EMULATE_DONE;
6ea6e843
PB		 5748 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5749 return EMULATE_DONE;
6d77dbfc
GN		 5750 if (emulation_type & EMULTYPE_SKIP)
5751 return EMULATE_FAIL;
5752 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5753 }
5754 }
5755
ba8afb6b 5756 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5757 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5758 if (ctxt->eflags & X86_EFLAGS_RF)
5759 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5760 return EMULATE_DONE;
5761 }
5762
1cb3f3ae
XG		 5763 if (retry_instruction(ctxt, cr2, emulation_type))
5764 return EMULATE_DONE;
5765
7ae441ea 5766 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5767 changes registers values during IO operation */
7ae441ea
GN		 5768 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5769 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5770 emulator_invalidate_register_cache(ctxt);
7ae441ea 5771 }
4d2179e1 5772
5cd21917 5773restart:
0f89b207
TL		 5774 /* Save the faulting GPA (cr2) in the address field */
5775 ctxt->exception.address = cr2;
5776
9d74191a 5777 r = x86_emulate_insn(ctxt);
bbd9b64e 5778
775fde86
JR		 5779 if (r == EMULATION_INTERCEPTED)
5780 return EMULATE_DONE;
5781
d2ddd1c4 5782 if (r == EMULATION_FAILED) {
991eebf9
GN		 5783 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5784 emulation_type))
c3cd7ffa
GN		 5785 return EMULATE_DONE;
5786
6d77dbfc 5787 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5788 }
5789
9d74191a 5790 if (ctxt->have_exception) {
d2ddd1c4 5791 r = EMULATE_DONE;
ef54bcfe
PB		 5792 if (inject_emulated_exception(vcpu))
5793 return r;
d2ddd1c4 5794 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5795 if (!vcpu->arch.pio.in) {
5796 /* FIXME: return into emulator if single-stepping. */
3457e419 5797 vcpu->arch.pio.count = 0;
0912c977 5798 } else {
7ae441ea 5799 writeback = false;
716d51ab
GN		 5800 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5801 }
ac0a48c3 5802 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5803 } else if (vcpu->mmio_needed) {
5804 if (!vcpu->mmio_is_write)
5805 writeback = false;
ac0a48c3 5806 r = EMULATE_USER_EXIT;
716d51ab 5807 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5808 } else if (r == EMULATION_RESTART)
5cd21917 5809 goto restart;
d2ddd1c4
GN		 5810 else
5811 r = EMULATE_DONE;
f850e2e6 5812
7ae441ea 5813 if (writeback) {
6addfc42 5814 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5815 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5816 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5817 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5818 if (r == EMULATE_DONE &&
5819 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5820 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5821 if (!ctxt->have_exception ||
5822 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5823 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5824
5825 /*
5826 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5827 * do nothing, and it will be requested again as soon as
5828 * the shadow expires. But we still need to check here,
5829 * because POPF has no interrupt shadow.
5830 */
5831 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5832 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5833 } else
5834 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5835
5836 return r;
de7d789a 5837}
51d8b661 5838EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5839
cf8f70bf 5840int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5841{
cf8f70bf 5842 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5843 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5844 size, port, &val, 1);
cf8f70bf 5845 /* do not return to emulator after return from userspace */
7972995b 5846 vcpu->arch.pio.count = 0;
de7d789a
CO		 5847 return ret;
5848}
cf8f70bf 5849EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5850
8370c3d0
TL		 5851static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5852{
5853 unsigned long val;
5854
5855 /* We should only ever be called with arch.pio.count equal to 1 */
5856 BUG_ON(vcpu->arch.pio.count != 1);
5857
5858 /* For size less than 4 we merge, else we zero extend */
5859 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5860 : 0;
5861
5862 /*
5863 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5864 * the copy and tracing
5865 */
5866 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5867 vcpu->arch.pio.port, &val, 1);
5868 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5869
5870 return 1;
5871}
5872
5873int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5874{
5875 unsigned long val;
5876 int ret;
5877
5878 /* For size less than 4 we merge, else we zero extend */
5879 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5880
5881 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5882 &val, 1);
5883 if (ret) {
5884 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5885 return ret;
5886 }
5887
5888 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5889
5890 return 0;
5891}
5892EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5893
251a5fd6 5894static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5895{
0a3aee0d 5896 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5897 return 0;
8cfdc000
ZA		 5898}
5899
5900static void tsc_khz_changed(void *data)
c8076604 5901{
8cfdc000
ZA		 5902 struct cpufreq_freqs *freq = data;
5903 unsigned long khz = 0;
5904
5905 if (data)
5906 khz = freq->new;
5907 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5908 khz = cpufreq_quick_get(raw_smp_processor_id());
5909 if (!khz)
5910 khz = tsc_khz;
0a3aee0d 5911 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5912}
5913
c8076604
GH		 5914static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5915 void *data)
5916{
5917 struct cpufreq_freqs *freq = data;
5918 struct kvm *kvm;
5919 struct kvm_vcpu *vcpu;
5920 int i, send_ipi = 0;
5921
8cfdc000
ZA		 5922 /*
5923 * We allow guests to temporarily run on slowing clocks,
5924 * provided we notify them after, or to run on accelerating
5925 * clocks, provided we notify them before. Thus time never
5926 * goes backwards.
5927 *
5928 * However, we have a problem. We can't atomically update
5929 * the frequency of a given CPU from this function; it is
5930 * merely a notifier, which can be called from any CPU.
5931 * Changing the TSC frequency at arbitrary points in time
5932 * requires a recomputation of local variables related to
5933 * the TSC for each VCPU. We must flag these local variables
5934 * to be updated and be sure the update takes place with the
5935 * new frequency before any guests proceed.
5936 *
5937 * Unfortunately, the combination of hotplug CPU and frequency
5938 * change creates an intractable locking scenario; the order
5939 * of when these callouts happen is undefined with respect to
5940 * CPU hotplug, and they can race with each other. As such,
5941 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5942 * undefined; you can actually have a CPU frequency change take
5943 * place in between the computation of X and the setting of the
5944 * variable. To protect against this problem, all updates of
5945 * the per_cpu tsc_khz variable are done in an interrupt
5946 * protected IPI, and all callers wishing to update the value
5947 * must wait for a synchronous IPI to complete (which is trivial
5948 * if the caller is on the CPU already). This establishes the
5949 * necessary total order on variable updates.
5950 *
5951 * Note that because a guest time update may take place
5952 * anytime after the setting of the VCPU's request bit, the
5953 * correct TSC value must be set before the request. However,
5954 * to ensure the update actually makes it to any guest which
5955 * starts running in hardware virtualization between the set
5956 * and the acquisition of the spinlock, we must also ping the
5957 * CPU after setting the request bit.
5958 *
5959 */
5960
c8076604
GH		 5961 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5962 return 0;
5963 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5964 return 0;
8cfdc000
ZA		 5965
5966 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5967
2f303b74 5968 spin_lock(&kvm_lock);
c8076604 5969 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5970 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5971 if (vcpu->cpu != freq->cpu)
5972 continue;
c285545f 5973 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5974 if (vcpu->cpu != smp_processor_id())
8cfdc000 5975 send_ipi = 1;
c8076604
GH		 5976 }
5977 }
2f303b74 5978 spin_unlock(&kvm_lock);
c8076604
GH		 5979
5980 if (freq->old < freq->new && send_ipi) {
5981 /*
5982 * We upscale the frequency. Must make the guest
5983 * doesn't see old kvmclock values while running with
5984 * the new frequency, otherwise we risk the guest sees
5985 * time go backwards.
5986 *
5987 * In case we update the frequency for another cpu
5988 * (which might be in guest context) send an interrupt
5989 * to kick the cpu out of guest context. Next time
5990 * guest context is entered kvmclock will be updated,
5991 * so the guest will not see stale values.
5992 */
8cfdc000 5993 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5994 }
5995 return 0;
5996}
5997
5998static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5999 .notifier_call = kvmclock_cpufreq_notifier
6000};
6001
251a5fd6 6002static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6003{
251a5fd6
SAS		 6004 tsc_khz_changed(NULL);
6005 return 0;
8cfdc000
ZA		 6006}
6007
b820cc0c
ZA		 6008static void kvm_timer_init(void)
6009{
c285545f 6010 max_tsc_khz = tsc_khz;
460dd42e 6011
b820cc0c 6012 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6013#ifdef CONFIG_CPU_FREQ
6014 struct cpufreq_policy policy;
758f588d
BP		 6015 int cpu;
6016
c285545f 6017 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6018 cpu = get_cpu();
6019 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6020 if (policy.cpuinfo.max_freq)
6021 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6022 put_cpu();
c285545f 6023#endif
b820cc0c
ZA		 6024 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6025 CPUFREQ_TRANSITION_NOTIFIER);
6026 }
c285545f 6027 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6028
73c1b41e 6029 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6030 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6031}
6032
ff9d07a0
ZY		 6033static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6034
f5132b01 6035int kvm_is_in_guest(void)
ff9d07a0 6036{
086c9855 6037 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6038}
6039
6040static int kvm_is_user_mode(void)
6041{
6042 int user_mode = 3;
dcf46b94 6043
086c9855
AS		 6044 if (__this_cpu_read(current_vcpu))
6045 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6046
ff9d07a0
ZY		 6047 return user_mode != 0;
6048}
6049
6050static unsigned long kvm_get_guest_ip(void)
6051{
6052 unsigned long ip = 0;
dcf46b94 6053
086c9855
AS		 6054 if (__this_cpu_read(current_vcpu))
6055 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6056
ff9d07a0
ZY		 6057 return ip;
6058}
6059
6060static struct perf_guest_info_callbacks kvm_guest_cbs = {
6061 .is_in_guest = kvm_is_in_guest,
6062 .is_user_mode = kvm_is_user_mode,
6063 .get_guest_ip = kvm_get_guest_ip,
6064};
6065
6066void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6067{
086c9855 6068 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6069}
6070EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6071
6072void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6073{
086c9855 6074 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6075}
6076EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6077
ce88decf
XG		 6078static void kvm_set_mmio_spte_mask(void)
6079{
6080 u64 mask;
6081 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6082
6083 /*
6084 * Set the reserved bits and the present bit of an paging-structure
6085 * entry to generate page fault with PFER.RSV = 1.
6086 */
885032b9 6087 /* Mask the reserved physical address bits. */
d1431483 6088 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6089
885032b9 6090 /* Set the present bit. */
ce88decf
XG		 6091 mask |= 1ull;
6092
6093#ifdef CONFIG_X86_64
6094 /*
6095 * If reserved bit is not supported, clear the present bit to disable
6096 * mmio page fault.
6097 */
6098 if (maxphyaddr == 52)
6099 mask &= ~1ull;
6100#endif
6101
dcdca5fe 6102 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6103}
6104
16e8d74d
MT		 6105#ifdef CONFIG_X86_64
6106static void pvclock_gtod_update_fn(struct work_struct *work)
6107{
d828199e
MT		 6108 struct kvm *kvm;
6109
6110 struct kvm_vcpu *vcpu;
6111 int i;
6112
2f303b74 6113 spin_lock(&kvm_lock);
d828199e
MT		 6114 list_for_each_entry(kvm, &vm_list, vm_list)
6115 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6116 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6117 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6118 spin_unlock(&kvm_lock);
16e8d74d
MT		 6119}
6120
6121static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6122
6123/*
6124 * Notification about pvclock gtod data update.
6125 */
6126static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6127 void *priv)
6128{
6129 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6130 struct timekeeper *tk = priv;
6131
6132 update_pvclock_gtod(tk);
6133
6134 /* disable master clock if host does not trust, or does not
6135 * use, TSC clocksource
6136 */
6137 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6138 atomic_read(&kvm_guest_has_master_clock) != 0)
6139 queue_work(system_long_wq, &pvclock_gtod_work);
6140
6141 return 0;
6142}
6143
6144static struct notifier_block pvclock_gtod_notifier = {
6145 .notifier_call = pvclock_gtod_notify,
6146};
6147#endif
6148
f8c16bba 6149int kvm_arch_init(void *opaque)
043405e1 6150{
b820cc0c 6151 int r;
6b61edf7 6152 struct kvm_x86_ops *ops = opaque;
f8c16bba 6153
f8c16bba
ZX		 6154 if (kvm_x86_ops) {
6155 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6156 r = -EEXIST;
6157 goto out;
f8c16bba
ZX		 6158 }
6159
6160 if (!ops->cpu_has_kvm_support()) {
6161 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6162 r = -EOPNOTSUPP;
6163 goto out;
f8c16bba
ZX		 6164 }
6165 if (ops->disabled_by_bios()) {
6166 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6167 r = -EOPNOTSUPP;
6168 goto out;
f8c16bba
ZX		 6169 }
6170
013f6a5d
MT		 6171 r = -ENOMEM;
6172 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6173 if (!shared_msrs) {
6174 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6175 goto out;
6176 }
6177
97db56ce
AK		 6178 r = kvm_mmu_module_init();
6179 if (r)
013f6a5d 6180 goto out_free_percpu;
97db56ce 6181
ce88decf 6182 kvm_set_mmio_spte_mask();
97db56ce 6183
f8c16bba 6184 kvm_x86_ops = ops;
920c8377 6185
7b52345e 6186 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6187 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6188 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6189 kvm_timer_init();
c8076604 6190
ff9d07a0
ZY		 6191 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6192
d366bf7e 6193 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6194 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6195
c5cc421b 6196 kvm_lapic_init();
16e8d74d
MT		 6197#ifdef CONFIG_X86_64
6198 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6199#endif
6200
f8c16bba 6201 return 0;
56c6d28a 6202
013f6a5d
MT		 6203out_free_percpu:
6204 free_percpu(shared_msrs);
56c6d28a 6205out:
56c6d28a 6206 return r;
043405e1 6207}
8776e519 6208
f8c16bba
ZX		 6209void kvm_arch_exit(void)
6210{
cef84c30 6211 kvm_lapic_exit();
ff9d07a0
ZY		 6212 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6213
888d256e
JK		 6214 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6215 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6216 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6217 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6218#ifdef CONFIG_X86_64
6219 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6220#endif
f8c16bba 6221 kvm_x86_ops = NULL;
56c6d28a 6222 kvm_mmu_module_exit();
013f6a5d 6223 free_percpu(shared_msrs);
56c6d28a 6224}
f8c16bba 6225
5cb56059 6226int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6227{
6228 ++vcpu->stat.halt_exits;
35754c98 6229 if (lapic_in_kernel(vcpu)) {
a4535290 6230 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6231 return 1;
6232 } else {
6233 vcpu->run->exit_reason = KVM_EXIT_HLT;
6234 return 0;
6235 }
6236}
5cb56059
JS		 6237EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6238
6239int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6240{
6affcbed
KH		 6241 int ret = kvm_skip_emulated_instruction(vcpu);
6242 /*
6243 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6244 * KVM_EXIT_DEBUG here.
6245 */
6246 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6247}
8776e519
HB		 6248EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6249
8ef81a9a 6250#ifdef CONFIG_X86_64
55dd00a7
MT		 6251static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6252 unsigned long clock_type)
6253{
6254 struct kvm_clock_pairing clock_pairing;
6255 struct timespec ts;
80fbd89c 6256 u64 cycle;
55dd00a7
MT		 6257 int ret;
6258
6259 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6260 return -KVM_EOPNOTSUPP;
6261
6262 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6263 return -KVM_EOPNOTSUPP;
6264
6265 clock_pairing.sec = ts.tv_sec;
6266 clock_pairing.nsec = ts.tv_nsec;
6267 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6268 clock_pairing.flags = 0;
6269
6270 ret = 0;
6271 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6272 sizeof(struct kvm_clock_pairing)))
6273 ret = -KVM_EFAULT;
6274
6275 return ret;
6276}
8ef81a9a 6277#endif
55dd00a7 6278
6aef266c
SV		 6279/*
6280 * kvm_pv_kick_cpu_op: Kick a vcpu.
6281 *
6282 * @apicid - apicid of vcpu to be kicked.
6283 */
6284static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6285{
24d2166b 6286 struct kvm_lapic_irq lapic_irq;
6aef266c 6287
24d2166b
R		 6288 lapic_irq.shorthand = 0;
6289 lapic_irq.dest_mode = 0;
ebd28fcb 6290 lapic_irq.level = 0;
24d2166b 6291 lapic_irq.dest_id = apicid;
93bbf0b8 6292 lapic_irq.msi_redir_hint = false;
6aef266c 6293
24d2166b 6294 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6295 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6296}
6297
d62caabb
AS		 6298void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6299{
6300 vcpu->arch.apicv_active = false;
6301 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6302}
6303
8776e519
HB		 6304int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6305{
6306 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6307 int op_64_bit, r;
8776e519 6308
6affcbed 6309 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6310
55cd8e5a
GN		 6311 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6312 return kvm_hv_hypercall(vcpu);
6313
5fdbf976
MT		 6314 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6315 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6316 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6317 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6318 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6319
229456fc 6320 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6321
a449c7aa
NA		 6322 op_64_bit = is_64_bit_mode(vcpu);
6323 if (!op_64_bit) {
8776e519
HB		 6324 nr &= 0xFFFFFFFF;
6325 a0 &= 0xFFFFFFFF;
6326 a1 &= 0xFFFFFFFF;
6327 a2 &= 0xFFFFFFFF;
6328 a3 &= 0xFFFFFFFF;
6329 }
6330
07708c4a
JK		 6331 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6332 ret = -KVM_EPERM;
6333 goto out;
6334 }
6335
8776e519 6336 switch (nr) {
b93463aa
AK		 6337 case KVM_HC_VAPIC_POLL_IRQ:
6338 ret = 0;
6339 break;
6aef266c
SV		 6340 case KVM_HC_KICK_CPU:
6341 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6342 ret = 0;
6343 break;
8ef81a9a 6344#ifdef CONFIG_X86_64
55dd00a7
MT		 6345 case KVM_HC_CLOCK_PAIRING:
6346 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6347 break;
8ef81a9a 6348#endif
8776e519
HB		 6349 default:
6350 ret = -KVM_ENOSYS;
6351 break;
6352 }
07708c4a 6353out:
a449c7aa
NA		 6354 if (!op_64_bit)
6355 ret = (u32)ret;
5fdbf976 6356 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6357 ++vcpu->stat.hypercalls;
2f333bcb 6358 return r;
8776e519
HB		 6359}
6360EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6361
b6785def 6362static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6363{
d6aa1000 6364 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6365 char instruction[3];
5fdbf976 6366 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6367
8776e519 6368 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6369
ce2e852e
DV		 6370 return emulator_write_emulated(ctxt, rip, instruction, 3,
6371 &ctxt->exception);
8776e519
HB		 6372}
6373
851ba692 6374static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6375{
782d422b
MG		 6376 return vcpu->run->request_interrupt_window &&
6377 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6378}
6379
851ba692 6380static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6381{
851ba692
AK		 6382 struct kvm_run *kvm_run = vcpu->run;
6383
91586a3b 6384 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6385 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6386 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6387 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6388 kvm_run->ready_for_interrupt_injection =
6389 pic_in_kernel(vcpu->kvm) ||
782d422b 6390 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6391}
6392
95ba8273
GN		 6393static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6394{
6395 int max_irr, tpr;
6396
6397 if (!kvm_x86_ops->update_cr8_intercept)
6398 return;
6399
bce87cce 6400 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6401 return;
6402
d62caabb
AS		 6403 if (vcpu->arch.apicv_active)
6404 return;
6405
8db3baa2
GN		 6406 if (!vcpu->arch.apic->vapic_addr)
6407 max_irr = kvm_lapic_find_highest_irr(vcpu);
6408 else
6409 max_irr = -1;
95ba8273
GN		 6410
6411 if (max_irr != -1)
6412 max_irr >>= 4;
6413
6414 tpr = kvm_lapic_get_cr8(vcpu);
6415
6416 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6417}
6418
b6b8a145 6419static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6420{
b6b8a145
JK		 6421 int r;
6422
95ba8273 6423 /* try to reinject previous events if any */
664f8e26
WL		 6424 if (vcpu->arch.exception.injected) {
6425 kvm_x86_ops->queue_exception(vcpu);
6426 return 0;
6427 }
6428
6429 /*
6430 * Exceptions must be injected immediately, or the exception
6431 * frame will have the address of the NMI or interrupt handler.
6432 */
6433 if (!vcpu->arch.exception.pending) {
6434 if (vcpu->arch.nmi_injected) {
6435 kvm_x86_ops->set_nmi(vcpu);
6436 return 0;
6437 }
6438
6439 if (vcpu->arch.interrupt.pending) {
6440 kvm_x86_ops->set_irq(vcpu);
6441 return 0;
6442 }
6443 }
6444
6445 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6446 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6447 if (r != 0)
6448 return r;
6449 }
6450
6451 /* try to inject new event if pending */
b59bb7bd 6452 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6453 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6454 vcpu->arch.exception.has_error_code,
6455 vcpu->arch.exception.error_code);
d6e8c854 6456
664f8e26
WL		 6457 vcpu->arch.exception.pending = false;
6458 vcpu->arch.exception.injected = true;
6459
d6e8c854
NA		 6460 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6461 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6462 X86_EFLAGS_RF);
6463
6bdf0662
NA		 6464 if (vcpu->arch.exception.nr == DB_VECTOR &&
6465 (vcpu->arch.dr7 & DR7_GD)) {
6466 vcpu->arch.dr7 &= ~DR7_GD;
6467 kvm_update_dr7(vcpu);
6468 }
6469
cfcd20e5 6470 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6471 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6472 vcpu->arch.smi_pending = false;
52797bf9 6473 ++vcpu->arch.smi_count;
ee2cd4b7 6474 enter_smm(vcpu);
c43203ca 6475 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6476 --vcpu->arch.nmi_pending;
6477 vcpu->arch.nmi_injected = true;
6478 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6479 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6480 /*
6481 * Because interrupts can be injected asynchronously, we are
6482 * calling check_nested_events again here to avoid a race condition.
6483 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6484 * proposal and current concerns. Perhaps we should be setting
6485 * KVM_REQ_EVENT only on certain events and not unconditionally?
6486 */
6487 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6488 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6489 if (r != 0)
6490 return r;
6491 }
95ba8273 6492 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6493 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6494 false);
6495 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6496 }
6497 }
ee2cd4b7 6498
b6b8a145 6499 return 0;
95ba8273
GN		 6500}
6501
7460fb4a
AK		 6502static void process_nmi(struct kvm_vcpu *vcpu)
6503{
6504 unsigned limit = 2;
6505
6506 /*
6507 * x86 is limited to one NMI running, and one NMI pending after it.
6508 * If an NMI is already in progress, limit further NMIs to just one.
6509 * Otherwise, allow two (and we'll inject the first one immediately).
6510 */
6511 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6512 limit = 1;
6513
6514 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6515 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6516 kvm_make_request(KVM_REQ_EVENT, vcpu);
6517}
6518
ee2cd4b7 6519static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6520{
6521 u32 flags = 0;
6522 flags |= seg->g << 23;
6523 flags |= seg->db << 22;
6524 flags |= seg->l << 21;
6525 flags |= seg->avl << 20;
6526 flags |= seg->present << 15;
6527 flags |= seg->dpl << 13;
6528 flags |= seg->s << 12;
6529 flags |= seg->type << 8;
6530 return flags;
6531}
6532
ee2cd4b7 6533static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6534{
6535 struct kvm_segment seg;
6536 int offset;
6537
6538 kvm_get_segment(vcpu, &seg, n);
6539 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6540
6541 if (n < 3)
6542 offset = 0x7f84 + n * 12;
6543 else
6544 offset = 0x7f2c + (n - 3) * 12;
6545
6546 put_smstate(u32, buf, offset + 8, seg.base);
6547 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6548 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6549}
6550
efbb288a 6551#ifdef CONFIG_X86_64
ee2cd4b7 6552static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6553{
6554 struct kvm_segment seg;
6555 int offset;
6556 u16 flags;
6557
6558 kvm_get_segment(vcpu, &seg, n);
6559 offset = 0x7e00 + n * 16;
6560
ee2cd4b7 6561 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6562 put_smstate(u16, buf, offset, seg.selector);
6563 put_smstate(u16, buf, offset + 2, flags);
6564 put_smstate(u32, buf, offset + 4, seg.limit);
6565 put_smstate(u64, buf, offset + 8, seg.base);
6566}
efbb288a 6567#endif
660a5d51 6568
ee2cd4b7 6569static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6570{
6571 struct desc_ptr dt;
6572 struct kvm_segment seg;
6573 unsigned long val;
6574 int i;
6575
6576 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6577 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6578 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6579 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6580
6581 for (i = 0; i < 8; i++)
6582 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6583
6584 kvm_get_dr(vcpu, 6, &val);
6585 put_smstate(u32, buf, 0x7fcc, (u32)val);
6586 kvm_get_dr(vcpu, 7, &val);
6587 put_smstate(u32, buf, 0x7fc8, (u32)val);
6588
6589 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6590 put_smstate(u32, buf, 0x7fc4, seg.selector);
6591 put_smstate(u32, buf, 0x7f64, seg.base);
6592 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6593 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6594
6595 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6596 put_smstate(u32, buf, 0x7fc0, seg.selector);
6597 put_smstate(u32, buf, 0x7f80, seg.base);
6598 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6599 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6600
6601 kvm_x86_ops->get_gdt(vcpu, &dt);
6602 put_smstate(u32, buf, 0x7f74, dt.address);
6603 put_smstate(u32, buf, 0x7f70, dt.size);
6604
6605 kvm_x86_ops->get_idt(vcpu, &dt);
6606 put_smstate(u32, buf, 0x7f58, dt.address);
6607 put_smstate(u32, buf, 0x7f54, dt.size);
6608
6609 for (i = 0; i < 6; i++)
ee2cd4b7 6610 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6611
6612 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6613
6614 /* revision id */
6615 put_smstate(u32, buf, 0x7efc, 0x00020000);
6616 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6617}
6618
ee2cd4b7 6619static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6620{
6621#ifdef CONFIG_X86_64
6622 struct desc_ptr dt;
6623 struct kvm_segment seg;
6624 unsigned long val;
6625 int i;
6626
6627 for (i = 0; i < 16; i++)
6628 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6629
6630 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6631 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6632
6633 kvm_get_dr(vcpu, 6, &val);
6634 put_smstate(u64, buf, 0x7f68, val);
6635 kvm_get_dr(vcpu, 7, &val);
6636 put_smstate(u64, buf, 0x7f60, val);
6637
6638 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6639 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6640 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6641
6642 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6643
6644 /* revision id */
6645 put_smstate(u32, buf, 0x7efc, 0x00020064);
6646
6647 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6648
6649 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6650 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6651 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6652 put_smstate(u32, buf, 0x7e94, seg.limit);
6653 put_smstate(u64, buf, 0x7e98, seg.base);
6654
6655 kvm_x86_ops->get_idt(vcpu, &dt);
6656 put_smstate(u32, buf, 0x7e84, dt.size);
6657 put_smstate(u64, buf, 0x7e88, dt.address);
6658
6659 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6660 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6661 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6662 put_smstate(u32, buf, 0x7e74, seg.limit);
6663 put_smstate(u64, buf, 0x7e78, seg.base);
6664
6665 kvm_x86_ops->get_gdt(vcpu, &dt);
6666 put_smstate(u32, buf, 0x7e64, dt.size);
6667 put_smstate(u64, buf, 0x7e68, dt.address);
6668
6669 for (i = 0; i < 6; i++)
ee2cd4b7 6670 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6671#else
6672 WARN_ON_ONCE(1);
6673#endif
6674}
6675
ee2cd4b7 6676static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6677{
660a5d51 6678 struct kvm_segment cs, ds;
18c3626e 6679 struct desc_ptr dt;
660a5d51
PB		 6680 char buf[512];
6681 u32 cr0;
6682
660a5d51 6683 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6684 memset(buf, 0, 512);
d6321d49 6685 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6686 enter_smm_save_state_64(vcpu, buf);
660a5d51 6687 else
ee2cd4b7 6688 enter_smm_save_state_32(vcpu, buf);
660a5d51 6689
0234bf88
LP		 6690 /*
6691 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6692 * vCPU state (e.g. leave guest mode) after we've saved the state into
6693 * the SMM state-save area.
6694 */
6695 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6696
6697 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6698 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6699
6700 if (kvm_x86_ops->get_nmi_mask(vcpu))
6701 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6702 else
6703 kvm_x86_ops->set_nmi_mask(vcpu, true);
6704
6705 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6706 kvm_rip_write(vcpu, 0x8000);
6707
6708 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6709 kvm_x86_ops->set_cr0(vcpu, cr0);
6710 vcpu->arch.cr0 = cr0;
6711
6712 kvm_x86_ops->set_cr4(vcpu, 0);
6713
18c3626e
PB		 6714 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6715 dt.address = dt.size = 0;
6716 kvm_x86_ops->set_idt(vcpu, &dt);
6717
660a5d51
PB		 6718 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6719
6720 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6721 cs.base = vcpu->arch.smbase;
6722
6723 ds.selector = 0;
6724 ds.base = 0;
6725
6726 cs.limit = ds.limit = 0xffffffff;
6727 cs.type = ds.type = 0x3;
6728 cs.dpl = ds.dpl = 0;
6729 cs.db = ds.db = 0;
6730 cs.s = ds.s = 1;
6731 cs.l = ds.l = 0;
6732 cs.g = ds.g = 1;
6733 cs.avl = ds.avl = 0;
6734 cs.present = ds.present = 1;
6735 cs.unusable = ds.unusable = 0;
6736 cs.padding = ds.padding = 0;
6737
6738 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6739 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6740 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6741 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6742 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6743 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6744
d6321d49 6745 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6746 kvm_x86_ops->set_efer(vcpu, 0);
6747
6748 kvm_update_cpuid(vcpu);
6749 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6750}
6751
ee2cd4b7 6752static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6753{
6754 vcpu->arch.smi_pending = true;
6755 kvm_make_request(KVM_REQ_EVENT, vcpu);
6756}
6757
2860c4b1
PB		 6758void kvm_make_scan_ioapic_request(struct kvm *kvm)
6759{
6760 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6761}
6762
3d81bc7e 6763static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6764{
5c919412
AS		 6765 u64 eoi_exit_bitmap[4];
6766
3d81bc7e
YZ		 6767 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6768 return;
c7c9c56c 6769
6308630b 6770 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6771
b053b2ae 6772 if (irqchip_split(vcpu->kvm))
6308630b 6773 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6774 else {
76dfafd5 6775 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6776 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6777 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6778 }
5c919412
AS		 6779 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6780 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6781 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6782}
6783
c2ba05cc 6784static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
a70656b6
RK		 6785{
6786 ++vcpu->stat.tlb_flush;
c2ba05cc 6787 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
a70656b6
RK		 6788}
6789
b1394e74
RK		 6790void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6791 unsigned long start, unsigned long end)
6792{
6793 unsigned long apic_address;
6794
6795 /*
6796 * The physical address of apic access page is stored in the VMCS.
6797 * Update it when it becomes invalid.
6798 */
6799 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6800 if (start <= apic_address && apic_address < end)
6801 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6802}
6803
4256f43f
TC		 6804void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6805{
c24ae0dc
TC		 6806 struct page *page = NULL;
6807
35754c98 6808 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6809 return;
6810
4256f43f
TC		 6811 if (!kvm_x86_ops->set_apic_access_page_addr)
6812 return;
6813
c24ae0dc 6814 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6815 if (is_error_page(page))
6816 return;
c24ae0dc
TC		 6817 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6818
6819 /*
6820 * Do not pin apic access page in memory, the MMU notifier
6821 * will call us again if it is migrated or swapped out.
6822 */
6823 put_page(page);
4256f43f
TC		 6824}
6825EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6826
9357d939 6827/*
362c698f 6828 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6829 * exiting to the userspace. Otherwise, the value will be returned to the
6830 * userspace.
6831 */
851ba692 6832static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6833{
6834 int r;
62a193ed
MG		 6835 bool req_int_win =
6836 dm_request_for_irq_injection(vcpu) &&
6837 kvm_cpu_accept_dm_intr(vcpu);
6838
730dca42 6839 bool req_immediate_exit = false;
b6c7a5dc 6840
2fa6e1e1 6841 if (kvm_request_pending(vcpu)) {
a8eeb04a 6842 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6843 kvm_mmu_unload(vcpu);
a8eeb04a 6844 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6845 __kvm_migrate_timers(vcpu);
d828199e
MT		 6846 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6847 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6848 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6849 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6850 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6851 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6852 if (unlikely(r))
6853 goto out;
6854 }
a8eeb04a 6855 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6856 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6857 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 6858 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 6859 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6860 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6861 r = 0;
6862 goto out;
6863 }
a8eeb04a 6864 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6865 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6866 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6867 r = 0;
6868 goto out;
6869 }
af585b92
GN		 6870 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6871 /* Page is swapped out. Do synthetic halt */
6872 vcpu->arch.apf.halted = true;
6873 r = 1;
6874 goto out;
6875 }
c9aaa895
GC		 6876 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6877 record_steal_time(vcpu);
64d60670
PB		 6878 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6879 process_smi(vcpu);
7460fb4a
AK		 6880 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6881 process_nmi(vcpu);
f5132b01 6882 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6883 kvm_pmu_handle_event(vcpu);
f5132b01 6884 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6885 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6886 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6887 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6888 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6889 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6890 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6891 vcpu->run->eoi.vector =
6892 vcpu->arch.pending_ioapic_eoi;
6893 r = 0;
6894 goto out;
6895 }
6896 }
3d81bc7e
YZ		 6897 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6898 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6899 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6900 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6901 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6902 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6903 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6904 r = 0;
6905 goto out;
6906 }
e516cebb
AS		 6907 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6908 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6909 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6910 r = 0;
6911 goto out;
6912 }
db397571
AS		 6913 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6914 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6915 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6916 r = 0;
6917 goto out;
6918 }
f3b138c5
AS		 6919
6920 /*
6921 * KVM_REQ_HV_STIMER has to be processed after
6922 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6923 * depend on the guest clock being up-to-date
6924 */
1f4b34f8
AS		 6925 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6926 kvm_hv_process_stimers(vcpu);
2f52d58c 6927 }
b93463aa 6928
b463a6f7 6929 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6930 ++vcpu->stat.req_event;
66450a21
JK		 6931 kvm_apic_accept_events(vcpu);
6932 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6933 r = 1;
6934 goto out;
6935 }
6936
b6b8a145
JK		 6937 if (inject_pending_event(vcpu, req_int_win) != 0)
6938 req_immediate_exit = true;
321c5658 6939 else {
cc3d967f 6940 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 6941 *
cc3d967f
LP		 6942 * SMIs have three cases:
6943 * 1) They can be nested, and then there is nothing to
6944 * do here because RSM will cause a vmexit anyway.
6945 * 2) There is an ISA-specific reason why SMI cannot be
6946 * injected, and the moment when this changes can be
6947 * intercepted.
6948 * 3) Or the SMI can be pending because
6949 * inject_pending_event has completed the injection
6950 * of an IRQ or NMI from the previous vmexit, and
6951 * then we request an immediate exit to inject the
6952 * SMI.
c43203ca
PB		 6953 */
6954 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 6955 if (!kvm_x86_ops->enable_smi_window(vcpu))
6956 req_immediate_exit = true;
321c5658
YS		 6957 if (vcpu->arch.nmi_pending)
6958 kvm_x86_ops->enable_nmi_window(vcpu);
6959 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6960 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 6961 WARN_ON(vcpu->arch.exception.pending);
321c5658 6962 }
b463a6f7
AK		 6963
6964 if (kvm_lapic_enabled(vcpu)) {
6965 update_cr8_intercept(vcpu);
6966 kvm_lapic_sync_to_vapic(vcpu);
6967 }
6968 }
6969
d8368af8
AK		 6970 r = kvm_mmu_reload(vcpu);
6971 if (unlikely(r)) {
d905c069 6972 goto cancel_injection;
d8368af8
AK		 6973 }
6974
b6c7a5dc
HB		 6975 preempt_disable();
6976
6977 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 6978
6979 /*
6980 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6981 * IPI are then delayed after guest entry, which ensures that they
6982 * result in virtual interrupt delivery.
6983 */
6984 local_irq_disable();
6b7e2d09
XG		 6985 vcpu->mode = IN_GUEST_MODE;
6986
01b71917
MT		 6987 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6988
0f127d12 6989 /*
b95234c8 6990 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 6991 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 6992 *
6993 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6994 * pairs with the memory barrier implicit in pi_test_and_set_on
6995 * (see vmx_deliver_posted_interrupt).
6996 *
6997 * 3) This also orders the write to mode from any reads to the page
6998 * tables done while the VCPU is running. Please see the comment
6999 * in kvm_flush_remote_tlbs.
6b7e2d09 7000 */
01b71917 7001 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7002
b95234c8
PB		 7003 /*
7004 * This handles the case where a posted interrupt was
7005 * notified with kvm_vcpu_kick.
7006 */
7007 if (kvm_lapic_enabled(vcpu)) {
7008 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
7009 kvm_x86_ops->sync_pir_to_irr(vcpu);
7010 }
32f88400 7011
2fa6e1e1 7012 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7013 || need_resched() || signal_pending(current)) {
6b7e2d09 7014 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7015 smp_wmb();
6c142801
AK		 7016 local_irq_enable();
7017 preempt_enable();
01b71917 7018 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7019 r = 1;
d905c069 7020 goto cancel_injection;
6c142801
AK		 7021 }
7022
fc5b7f3b
DM		 7023 kvm_load_guest_xcr0(vcpu);
7024
c43203ca
PB		 7025 if (req_immediate_exit) {
7026 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7027 smp_send_reschedule(vcpu->cpu);
c43203ca 7028 }
d6185f20 7029
8b89fe1f 7030 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7031 if (lapic_timer_advance_ns)
7032 wait_lapic_expire(vcpu);
6edaa530 7033 guest_enter_irqoff();
b6c7a5dc 7034
42dbaa5a 7035 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7036 set_debugreg(0, 7);
7037 set_debugreg(vcpu->arch.eff_db[0], 0);
7038 set_debugreg(vcpu->arch.eff_db[1], 1);
7039 set_debugreg(vcpu->arch.eff_db[2], 2);
7040 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7041 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7042 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7043 }
b6c7a5dc 7044
851ba692 7045 kvm_x86_ops->run(vcpu);
b6c7a5dc 7046
c77fb5fe
PB		 7047 /*
7048 * Do this here before restoring debug registers on the host. And
7049 * since we do this before handling the vmexit, a DR access vmexit
7050 * can (a) read the correct value of the debug registers, (b) set
7051 * KVM_DEBUGREG_WONT_EXIT again.
7052 */
7053 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7054 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7055 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7056 kvm_update_dr0123(vcpu);
7057 kvm_update_dr6(vcpu);
7058 kvm_update_dr7(vcpu);
7059 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7060 }
7061
24f1e32c
FW		 7062 /*
7063 * If the guest has used debug registers, at least dr7
7064 * will be disabled while returning to the host.
7065 * If we don't have active breakpoints in the host, we don't
7066 * care about the messed up debug address registers. But if
7067 * we have some of them active, restore the old state.
7068 */
59d8eb53 7069 if (hw_breakpoint_active())
24f1e32c 7070 hw_breakpoint_restore();
42dbaa5a 7071
4ba76538 7072 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7073
6b7e2d09 7074 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7075 smp_wmb();
a547c6db 7076
fc5b7f3b
DM		 7077 kvm_put_guest_xcr0(vcpu);
7078
a547c6db 7079 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7080
7081 ++vcpu->stat.exits;
7082
f2485b3e 7083 guest_exit_irqoff();
b6c7a5dc 7084
f2485b3e 7085 local_irq_enable();
b6c7a5dc
HB		 7086 preempt_enable();
7087
f656ce01 7088 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7089
b6c7a5dc
HB		 7090 /*
7091 * Profile KVM exit RIPs:
7092 */
7093 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7094 unsigned long rip = kvm_rip_read(vcpu);
7095 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7096 }
7097
cc578287
ZA		 7098 if (unlikely(vcpu->arch.tsc_always_catchup))
7099 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7100
5cfb1d5a
MT		 7101 if (vcpu->arch.apic_attention)
7102 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7103
618232e2 7104 vcpu->arch.gpa_available = false;
851ba692 7105 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7106 return r;
7107
7108cancel_injection:
7109 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7110 if (unlikely(vcpu->arch.apic_attention))
7111 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7112out:
7113 return r;
7114}
b6c7a5dc 7115
362c698f
PB		 7116static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7117{
bf9f6ac8
FW		 7118 if (!kvm_arch_vcpu_runnable(vcpu) &&
7119 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7120 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7121 kvm_vcpu_block(vcpu);
7122 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7123
7124 if (kvm_x86_ops->post_block)
7125 kvm_x86_ops->post_block(vcpu);
7126
9c8fd1ba
PB		 7127 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7128 return 1;
7129 }
362c698f
PB		 7130
7131 kvm_apic_accept_events(vcpu);
7132 switch(vcpu->arch.mp_state) {
7133 case KVM_MP_STATE_HALTED:
7134 vcpu->arch.pv.pv_unhalted = false;
7135 vcpu->arch.mp_state =
7136 KVM_MP_STATE_RUNNABLE;
7137 case KVM_MP_STATE_RUNNABLE:
7138 vcpu->arch.apf.halted = false;
7139 break;
7140 case KVM_MP_STATE_INIT_RECEIVED:
7141 break;
7142 default:
7143 return -EINTR;
7144 break;
7145 }
7146 return 1;
7147}
09cec754 7148
5d9bc648
PB		 7149static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7150{
0ad3bed6
PB		 7151 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7152 kvm_x86_ops->check_nested_events(vcpu, false);
7153
5d9bc648
PB		 7154 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7155 !vcpu->arch.apf.halted);
7156}
7157
362c698f 7158static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7159{
7160 int r;
f656ce01 7161 struct kvm *kvm = vcpu->kvm;
d7690175 7162
f656ce01 7163 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7164
362c698f 7165 for (;;) {
58f800d5 7166 if (kvm_vcpu_running(vcpu)) {
851ba692 7167 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7168 } else {
362c698f 7169 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7170 }
7171
09cec754
GN		 7172 if (r <= 0)
7173 break;
7174
72875d8a 7175 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7176 if (kvm_cpu_has_pending_timer(vcpu))
7177 kvm_inject_pending_timer_irqs(vcpu);
7178
782d422b
MG		 7179 if (dm_request_for_irq_injection(vcpu) &&
7180 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7181 r = 0;
7182 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7183 ++vcpu->stat.request_irq_exits;
362c698f 7184 break;
09cec754 7185 }
af585b92
GN		 7186
7187 kvm_check_async_pf_completion(vcpu);
7188
09cec754
GN		 7189 if (signal_pending(current)) {
7190 r = -EINTR;
851ba692 7191 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7192 ++vcpu->stat.signal_exits;
362c698f 7193 break;
09cec754
GN		 7194 }
7195 if (need_resched()) {
f656ce01 7196 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7197 cond_resched();
f656ce01 7198 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7199 }
b6c7a5dc
HB		 7200 }
7201
f656ce01 7202 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7203
7204 return r;
7205}
7206
716d51ab
GN		 7207static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7208{
7209 int r;
7210 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7211 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7212 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7213 if (r != EMULATE_DONE)
7214 return 0;
7215 return 1;
7216}
7217
7218static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7219{
7220 BUG_ON(!vcpu->arch.pio.count);
7221
7222 return complete_emulated_io(vcpu);
7223}
7224
f78146b0
AK		 7225/*
7226 * Implements the following, as a state machine:
7227 *
7228 * read:
7229 * for each fragment
87da7e66
XG		 7230 * for each mmio piece in the fragment
7231 * write gpa, len
7232 * exit
7233 * copy data
f78146b0
AK		 7234 * execute insn
7235 *
7236 * write:
7237 * for each fragment
87da7e66
XG		 7238 * for each mmio piece in the fragment
7239 * write gpa, len
7240 * copy data
7241 * exit
f78146b0 7242 */
716d51ab 7243static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7244{
7245 struct kvm_run *run = vcpu->run;
f78146b0 7246 struct kvm_mmio_fragment *frag;
87da7e66 7247 unsigned len;
5287f194 7248
716d51ab 7249 BUG_ON(!vcpu->mmio_needed);
5287f194 7250
716d51ab 7251 /* Complete previous fragment */
87da7e66
XG		 7252 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7253 len = min(8u, frag->len);
716d51ab 7254 if (!vcpu->mmio_is_write)
87da7e66
XG		 7255 memcpy(frag->data, run->mmio.data, len);
7256
7257 if (frag->len <= 8) {
7258 /* Switch to the next fragment. */
7259 frag++;
7260 vcpu->mmio_cur_fragment++;
7261 } else {
7262 /* Go forward to the next mmio piece. */
7263 frag->data += len;
7264 frag->gpa += len;
7265 frag->len -= len;
7266 }
7267
a08d3b3b 7268 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7269 vcpu->mmio_needed = 0;
0912c977
PB		 7270
7271 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7272 if (vcpu->mmio_is_write)
716d51ab
GN		 7273 return 1;
7274 vcpu->mmio_read_completed = 1;
7275 return complete_emulated_io(vcpu);
7276 }
87da7e66 7277
716d51ab
GN		 7278 run->exit_reason = KVM_EXIT_MMIO;
7279 run->mmio.phys_addr = frag->gpa;
7280 if (vcpu->mmio_is_write)
87da7e66
XG		 7281 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7282 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7283 run->mmio.is_write = vcpu->mmio_is_write;
7284 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7285 return 0;
5287f194
AK		 7286}
7287
716d51ab 7288
b6c7a5dc
HB		 7289int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7290{
7291 int r;
b6c7a5dc 7292
accb757d 7293 vcpu_load(vcpu);
20b7035c 7294 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7295 kvm_load_guest_fpu(vcpu);
7296
a4535290 7297 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7298 if (kvm_run->immediate_exit) {
7299 r = -EINTR;
7300 goto out;
7301 }
b6c7a5dc 7302 kvm_vcpu_block(vcpu);
66450a21 7303 kvm_apic_accept_events(vcpu);
72875d8a 7304 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7305 r = -EAGAIN;
a0595000
JS		 7306 if (signal_pending(current)) {
7307 r = -EINTR;
7308 vcpu->run->exit_reason = KVM_EXIT_INTR;
7309 ++vcpu->stat.signal_exits;
7310 }
ac9f6dc0 7311 goto out;
b6c7a5dc
HB		 7312 }
7313
b6c7a5dc 7314 /* re-sync apic's tpr */
35754c98 7315 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7316 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7317 r = -EINVAL;
7318 goto out;
7319 }
7320 }
b6c7a5dc 7321
716d51ab
GN		 7322 if (unlikely(vcpu->arch.complete_userspace_io)) {
7323 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7324 vcpu->arch.complete_userspace_io = NULL;
7325 r = cui(vcpu);
7326 if (r <= 0)
5663d8f9 7327 goto out;
716d51ab
GN		 7328 } else
7329 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7330
460df4c1
PB		 7331 if (kvm_run->immediate_exit)
7332 r = -EINTR;
7333 else
7334 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7335
7336out:
5663d8f9 7337 kvm_put_guest_fpu(vcpu);
f1d86e46 7338 post_kvm_run_save(vcpu);
20b7035c 7339 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7340
accb757d 7341 vcpu_put(vcpu);
b6c7a5dc
HB		 7342 return r;
7343}
7344
7345int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7346{
1fc9b76b
CD		 7347 vcpu_load(vcpu);
7348
7ae441ea
GN		 7349 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7350 /*
7351 * We are here if userspace calls get_regs() in the middle of
7352 * instruction emulation. Registers state needs to be copied
4a969980 7353 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7354 * that usually, but some bad designed PV devices (vmware
7355 * backdoor interface) need this to work
7356 */
dd856efa 7357 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7358 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7359 }
5fdbf976
MT		 7360 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7361 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7362 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7363 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7364 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7365 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7366 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7367 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7368#ifdef CONFIG_X86_64
5fdbf976
MT		 7369 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7370 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7371 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7372 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7373 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7374 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7375 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7376 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7377#endif
7378
5fdbf976 7379 regs->rip = kvm_rip_read(vcpu);
91586a3b 7380 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7381
1fc9b76b 7382 vcpu_put(vcpu);
b6c7a5dc
HB		 7383 return 0;
7384}
7385
7386int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7387{
875656fe
CD		 7388 vcpu_load(vcpu);
7389
7ae441ea
GN		 7390 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7391 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7392
5fdbf976
MT		 7393 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7394 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7395 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7396 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7397 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7398 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7399 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7400 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7401#ifdef CONFIG_X86_64
5fdbf976
MT		 7402 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7403 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7404 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7405 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7406 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7407 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7408 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7409 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7410#endif
7411
5fdbf976 7412 kvm_rip_write(vcpu, regs->rip);
d73235d1 7413 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7414
b4f14abd
JK		 7415 vcpu->arch.exception.pending = false;
7416
3842d135
AK		 7417 kvm_make_request(KVM_REQ_EVENT, vcpu);
7418
875656fe 7419 vcpu_put(vcpu);
b6c7a5dc
HB		 7420 return 0;
7421}
7422
b6c7a5dc
HB		 7423void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7424{
7425 struct kvm_segment cs;
7426
3e6e0aab 7427 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7428 *db = cs.db;
7429 *l = cs.l;
7430}
7431EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7432
7433int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7434 struct kvm_sregs *sregs)
7435{
89a27f4d 7436 struct desc_ptr dt;
b6c7a5dc 7437
bcdec41c
CD		 7438 vcpu_load(vcpu);
7439
3e6e0aab
GT		 7440 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7441 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7442 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7443 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7444 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7445 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7446
3e6e0aab
GT		 7447 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7448 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7449
7450 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7451 sregs->idt.limit = dt.size;
7452 sregs->idt.base = dt.address;
b6c7a5dc 7453 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7454 sregs->gdt.limit = dt.size;
7455 sregs->gdt.base = dt.address;
b6c7a5dc 7456
4d4ec087 7457 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7458 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7459 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7460 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7461 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7462 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7463 sregs->apic_base = kvm_get_apic_base(vcpu);
7464
923c61bb 7465 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7466
36752c9b 7467 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7468 set_bit(vcpu->arch.interrupt.nr,
7469 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7470
bcdec41c 7471 vcpu_put(vcpu);
b6c7a5dc
HB		 7472 return 0;
7473}
7474
62d9f0db
MT		 7475int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7476 struct kvm_mp_state *mp_state)
7477{
fd232561
CD		 7478 vcpu_load(vcpu);
7479
66450a21 7480 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7481 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7482 vcpu->arch.pv.pv_unhalted)
7483 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7484 else
7485 mp_state->mp_state = vcpu->arch.mp_state;
7486
fd232561 7487 vcpu_put(vcpu);
62d9f0db
MT		 7488 return 0;
7489}
7490
7491int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7492 struct kvm_mp_state *mp_state)
7493{
e83dff5e
CD		 7494 int ret = -EINVAL;
7495
7496 vcpu_load(vcpu);
7497
bce87cce 7498 if (!lapic_in_kernel(vcpu) &&
66450a21 7499 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7500 goto out;
66450a21 7501
28bf2888
DH		 7502 /* INITs are latched while in SMM */
7503 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7504 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7505 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7506 goto out;
28bf2888 7507
66450a21
JK		 7508 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7509 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7510 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7511 } else
7512 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7513 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7514
7515 ret = 0;
7516out:
7517 vcpu_put(vcpu);
7518 return ret;
62d9f0db
MT		 7519}
7520
7f3d35fd
KW		 7521int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7522 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7523{
9d74191a 7524 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7525 int ret;
e01c2426 7526
8ec4722d 7527 init_emulate_ctxt(vcpu);
c697518a 7528
7f3d35fd 7529 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7530 has_error_code, error_code);
c697518a 7531
c697518a 7532 if (ret)
19d04437 7533 return EMULATE_FAIL;
37817f29 7534
9d74191a
TY		 7535 kvm_rip_write(vcpu, ctxt->eip);
7536 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7537 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7538 return EMULATE_DONE;
37817f29
IE		 7539}
7540EXPORT_SYMBOL_GPL(kvm_task_switch);
7541
b6c7a5dc
HB		 7542int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7543 struct kvm_sregs *sregs)
7544{
58cb628d 7545 struct msr_data apic_base_msr;
b6c7a5dc 7546 int mmu_reset_needed = 0;
63f42e02 7547 int pending_vec, max_bits, idx;
89a27f4d 7548 struct desc_ptr dt;
b4ef9d4e
CD		 7549 int ret = -EINVAL;
7550
7551 vcpu_load(vcpu);
b6c7a5dc 7552
d6321d49
RK		 7553 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7554 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7555 goto out;
6d1068b3 7556
d3802286
JM		 7557 apic_base_msr.data = sregs->apic_base;
7558 apic_base_msr.host_initiated = true;
7559 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 7560 goto out;
6d1068b3 7561
89a27f4d
GN		 7562 dt.size = sregs->idt.limit;
7563 dt.address = sregs->idt.base;
b6c7a5dc 7564 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7565 dt.size = sregs->gdt.limit;
7566 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7567 kvm_x86_ops->set_gdt(vcpu, &dt);
7568
ad312c7c 7569 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7570 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7571 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7572 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7573
2d3ad1f4 7574 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7575
f6801dff 7576 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7577 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7578
4d4ec087 7579 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7580 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7581 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7582
fc78f519 7583 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7584 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7585 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7586 kvm_update_cpuid(vcpu);
63f42e02
XG		 7587
7588 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7589 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7590 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7591 mmu_reset_needed = 1;
7592 }
63f42e02 7593 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7594
7595 if (mmu_reset_needed)
7596 kvm_mmu_reset_context(vcpu);
7597
a50abc3b 7598 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7599 pending_vec = find_first_bit(
7600 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7601 if (pending_vec < max_bits) {
66fd3f7f 7602 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7603 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7604 }
7605
3e6e0aab
GT		 7606 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7607 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7608 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7609 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7610 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7611 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7612
3e6e0aab
GT		 7613 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7614 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7615
5f0269f5
ME		 7616 update_cr8_intercept(vcpu);
7617
9c3e4aab 7618 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7619 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7620 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7621 !is_protmode(vcpu))
9c3e4aab
MT		 7622 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7623
3842d135
AK		 7624 kvm_make_request(KVM_REQ_EVENT, vcpu);
7625
b4ef9d4e
CD		 7626 ret = 0;
7627out:
7628 vcpu_put(vcpu);
7629 return ret;
b6c7a5dc
HB		 7630}
7631
d0bfb940
JK		 7632int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7633 struct kvm_guest_debug *dbg)
b6c7a5dc 7634{
355be0b9 7635 unsigned long rflags;
ae675ef0 7636 int i, r;
b6c7a5dc 7637
66b56562
CD		 7638 vcpu_load(vcpu);
7639
4f926bf2
JK		 7640 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7641 r = -EBUSY;
7642 if (vcpu->arch.exception.pending)
2122ff5e 7643 goto out;
4f926bf2
JK		 7644 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7645 kvm_queue_exception(vcpu, DB_VECTOR);
7646 else
7647 kvm_queue_exception(vcpu, BP_VECTOR);
7648 }
7649
91586a3b
JK		 7650 /*
7651 * Read rflags as long as potentially injected trace flags are still
7652 * filtered out.
7653 */
7654 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7655
7656 vcpu->guest_debug = dbg->control;
7657 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7658 vcpu->guest_debug = 0;
7659
7660 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7661 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7662 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7663 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7664 } else {
7665 for (i = 0; i < KVM_NR_DB_REGS; i++)
7666 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7667 }
c8639010 7668 kvm_update_dr7(vcpu);
ae675ef0 7669
f92653ee
JK		 7670 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7671 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7672 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7673
91586a3b
JK		 7674 /*
7675 * Trigger an rflags update that will inject or remove the trace
7676 * flags.
7677 */
7678 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7679
a96036b8 7680 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7681
4f926bf2 7682 r = 0;
d0bfb940 7683
2122ff5e 7684out:
66b56562 7685 vcpu_put(vcpu);
b6c7a5dc
HB		 7686 return r;
7687}
7688
8b006791
ZX		 7689/*
7690 * Translate a guest virtual address to a guest physical address.
7691 */
7692int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7693 struct kvm_translation *tr)
7694{
7695 unsigned long vaddr = tr->linear_address;
7696 gpa_t gpa;
f656ce01 7697 int idx;
8b006791 7698
1da5b61d
CD		 7699 vcpu_load(vcpu);
7700
f656ce01 7701 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7702 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7703 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7704 tr->physical_address = gpa;
7705 tr->valid = gpa != UNMAPPED_GVA;
7706 tr->writeable = 1;
7707 tr->usermode = 0;
8b006791 7708
1da5b61d 7709 vcpu_put(vcpu);
8b006791
ZX		 7710 return 0;
7711}
7712
d0752060
HB		 7713int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7714{
1393123e 7715 struct fxregs_state *fxsave;
d0752060 7716
1393123e
CD		 7717 vcpu_load(vcpu);
7718
7719 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 7720 memcpy(fpu->fpr, fxsave->st_space, 128);
7721 fpu->fcw = fxsave->cwd;
7722 fpu->fsw = fxsave->swd;
7723 fpu->ftwx = fxsave->twd;
7724 fpu->last_opcode = fxsave->fop;
7725 fpu->last_ip = fxsave->rip;
7726 fpu->last_dp = fxsave->rdp;
7727 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7728
1393123e 7729 vcpu_put(vcpu);
d0752060
HB		 7730 return 0;
7731}
7732
7733int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7734{
6a96bc7f
CD		 7735 struct fxregs_state *fxsave;
7736
7737 vcpu_load(vcpu);
7738
7739 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7740
d0752060
HB		 7741 memcpy(fxsave->st_space, fpu->fpr, 128);
7742 fxsave->cwd = fpu->fcw;
7743 fxsave->swd = fpu->fsw;
7744 fxsave->twd = fpu->ftwx;
7745 fxsave->fop = fpu->last_opcode;
7746 fxsave->rip = fpu->last_ip;
7747 fxsave->rdp = fpu->last_dp;
7748 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7749
6a96bc7f 7750 vcpu_put(vcpu);
d0752060
HB		 7751 return 0;
7752}
7753
0ee6a517 7754static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7755{
bf935b0b 7756 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7757 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7758 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7759 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7760
2acf923e
DC		 7761 /*
7762 * Ensure guest xcr0 is valid for loading
7763 */
d91cab78 7764 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7765
ad312c7c 7766 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7767}
d0752060 7768
f775b13e 7769/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 7770void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7771{
f775b13e
RR		 7772 preempt_disable();
7773 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 7774 /* PKRU is separately restored in kvm_x86_ops->run. */
7775 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7776 ~XFEATURE_MASK_PKRU);
f775b13e 7777 preempt_enable();
0c04851c 7778 trace_kvm_fpu(1);
d0752060 7779}
d0752060 7780
f775b13e 7781/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 7782void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7783{
f775b13e 7784 preempt_disable();
4f836347 7785 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 7786 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7787 preempt_enable();
f096ed85 7788 ++vcpu->stat.fpu_reload;
0c04851c 7789 trace_kvm_fpu(0);
d0752060 7790}
e9b11c17
ZX		 7791
7792void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7793{
bd768e14
IY		 7794 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7795
12f9a48f 7796 kvmclock_reset(vcpu);
7f1ea208 7797
e9b11c17 7798 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7799 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7800}
7801
7802struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7803 unsigned int id)
7804{
c447e76b
LL		 7805 struct kvm_vcpu *vcpu;
7806
6755bae8
ZA		 7807 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7808 printk_once(KERN_WARNING
7809 "kvm: SMP vm created on host with unstable TSC; "
7810 "guest TSC will not be reliable\n");
c447e76b
LL		 7811
7812 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7813
c447e76b 7814 return vcpu;
26e5215f 7815}
e9b11c17 7816
26e5215f
AK		 7817int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7818{
19efffa2 7819 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 7820 vcpu_load(vcpu);
d28bc9dd 7821 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7822 kvm_mmu_setup(vcpu);
e9b11c17 7823 vcpu_put(vcpu);
ec7660cc 7824 return 0;
e9b11c17
ZX		 7825}
7826
31928aa5 7827void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7828{
8fe8ab46 7829 struct msr_data msr;
332967a3 7830 struct kvm *kvm = vcpu->kvm;
42897d86 7831
d3457c87
RK		 7832 kvm_hv_vcpu_postcreate(vcpu);
7833
ec7660cc 7834 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 7835 return;
ec7660cc 7836 vcpu_load(vcpu);
8fe8ab46
WA		 7837 msr.data = 0x0;
7838 msr.index = MSR_IA32_TSC;
7839 msr.host_initiated = true;
7840 kvm_write_tsc(vcpu, &msr);
42897d86 7841 vcpu_put(vcpu);
ec7660cc 7842 mutex_unlock(&vcpu->mutex);
42897d86 7843
630994b3
MT		 7844 if (!kvmclock_periodic_sync)
7845 return;
7846
332967a3
AJ		 7847 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7848 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7849}
7850
d40ccc62 7851void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7852{
344d9588
GN		 7853 vcpu->arch.apf.msr_val = 0;
7854
ec7660cc 7855 vcpu_load(vcpu);
e9b11c17
ZX		 7856 kvm_mmu_unload(vcpu);
7857 vcpu_put(vcpu);
7858
7859 kvm_x86_ops->vcpu_free(vcpu);
7860}
7861
d28bc9dd 7862void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7863{
e69fab5d
PB		 7864 vcpu->arch.hflags = 0;
7865
c43203ca 7866 vcpu->arch.smi_pending = 0;
52797bf9 7867 vcpu->arch.smi_count = 0;
7460fb4a
AK		 7868 atomic_set(&vcpu->arch.nmi_queued, 0);
7869 vcpu->arch.nmi_pending = 0;
448fa4a9 7870 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7871 kvm_clear_interrupt_queue(vcpu);
7872 kvm_clear_exception_queue(vcpu);
664f8e26 7873 vcpu->arch.exception.pending = false;
448fa4a9 7874
42dbaa5a 7875 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7876 kvm_update_dr0123(vcpu);
6f43ed01 7877 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7878 kvm_update_dr6(vcpu);
42dbaa5a 7879 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7880 kvm_update_dr7(vcpu);
42dbaa5a 7881
1119022c
NA		 7882 vcpu->arch.cr2 = 0;
7883
3842d135 7884 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7885 vcpu->arch.apf.msr_val = 0;
c9aaa895 7886 vcpu->arch.st.msr_val = 0;
3842d135 7887
12f9a48f
GC		 7888 kvmclock_reset(vcpu);
7889
af585b92
GN		 7890 kvm_clear_async_pf_completion_queue(vcpu);
7891 kvm_async_pf_hash_reset(vcpu);
7892 vcpu->arch.apf.halted = false;
3842d135 7893
a554d207
WL		 7894 if (kvm_mpx_supported()) {
7895 void *mpx_state_buffer;
7896
7897 /*
7898 * To avoid have the INIT path from kvm_apic_has_events() that be
7899 * called with loaded FPU and does not let userspace fix the state.
7900 */
f775b13e
RR		 7901 if (init_event)
7902 kvm_put_guest_fpu(vcpu);
a554d207
WL		 7903 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7904 XFEATURE_MASK_BNDREGS);
7905 if (mpx_state_buffer)
7906 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
7907 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7908 XFEATURE_MASK_BNDCSR);
7909 if (mpx_state_buffer)
7910 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 7911 if (init_event)
7912 kvm_load_guest_fpu(vcpu);
a554d207
WL		 7913 }
7914
64d60670 7915 if (!init_event) {
d28bc9dd 7916 kvm_pmu_reset(vcpu);
64d60670 7917 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7918
7919 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7920 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 7921
7922 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 7923 }
f5132b01 7924
66f7b72e
JS		 7925 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7926 vcpu->arch.regs_avail = ~0;
7927 vcpu->arch.regs_dirty = ~0;
7928
a554d207
WL		 7929 vcpu->arch.ia32_xss = 0;
7930
d28bc9dd 7931 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7932}
7933
2b4a273b 7934void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7935{
7936 struct kvm_segment cs;
7937
7938 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7939 cs.selector = vector << 8;
7940 cs.base = vector << 12;
7941 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7942 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7943}
7944
13a34e06 7945int kvm_arch_hardware_enable(void)
e9b11c17 7946{
ca84d1a2
ZA		 7947 struct kvm *kvm;
7948 struct kvm_vcpu *vcpu;
7949 int i;
0dd6a6ed
ZA		 7950 int ret;
7951 u64 local_tsc;
7952 u64 max_tsc = 0;
7953 bool stable, backwards_tsc = false;
18863bdd
AK		 7954
7955 kvm_shared_msr_cpu_online();
13a34e06 7956 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7957 if (ret != 0)
7958 return ret;
7959
4ea1636b 7960 local_tsc = rdtsc();
0dd6a6ed
ZA		 7961 stable = !check_tsc_unstable();
7962 list_for_each_entry(kvm, &vm_list, vm_list) {
7963 kvm_for_each_vcpu(i, vcpu, kvm) {
7964 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7965 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7966 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7967 backwards_tsc = true;
7968 if (vcpu->arch.last_host_tsc > max_tsc)
7969 max_tsc = vcpu->arch.last_host_tsc;
7970 }
7971 }
7972 }
7973
7974 /*
7975 * Sometimes, even reliable TSCs go backwards. This happens on
7976 * platforms that reset TSC during suspend or hibernate actions, but
7977 * maintain synchronization. We must compensate. Fortunately, we can
7978 * detect that condition here, which happens early in CPU bringup,
7979 * before any KVM threads can be running. Unfortunately, we can't
7980 * bring the TSCs fully up to date with real time, as we aren't yet far
7981 * enough into CPU bringup that we know how much real time has actually
108b249c 7982 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7983 * variables that haven't been updated yet.
7984 *
7985 * So we simply find the maximum observed TSC above, then record the
7986 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7987 * the adjustment will be applied. Note that we accumulate
7988 * adjustments, in case multiple suspend cycles happen before some VCPU
7989 * gets a chance to run again. In the event that no KVM threads get a
7990 * chance to run, we will miss the entire elapsed period, as we'll have
7991 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7992 * loose cycle time. This isn't too big a deal, since the loss will be
7993 * uniform across all VCPUs (not to mention the scenario is extremely
7994 * unlikely). It is possible that a second hibernate recovery happens
7995 * much faster than a first, causing the observed TSC here to be
7996 * smaller; this would require additional padding adjustment, which is
7997 * why we set last_host_tsc to the local tsc observed here.
7998 *
7999 * N.B. - this code below runs only on platforms with reliable TSC,
8000 * as that is the only way backwards_tsc is set above. Also note
8001 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8002 * have the same delta_cyc adjustment applied if backwards_tsc
8003 * is detected. Note further, this adjustment is only done once,
8004 * as we reset last_host_tsc on all VCPUs to stop this from being
8005 * called multiple times (one for each physical CPU bringup).
8006 *
4a969980 8007 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8008 * will be compensated by the logic in vcpu_load, which sets the TSC to
8009 * catchup mode. This will catchup all VCPUs to real time, but cannot
8010 * guarantee that they stay in perfect synchronization.
8011 */
8012 if (backwards_tsc) {
8013 u64 delta_cyc = max_tsc - local_tsc;
8014 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8015 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8016 kvm_for_each_vcpu(i, vcpu, kvm) {
8017 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8018 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8019 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8020 }
8021
8022 /*
8023 * We have to disable TSC offset matching.. if you were
8024 * booting a VM while issuing an S4 host suspend....
8025 * you may have some problem. Solving this issue is
8026 * left as an exercise to the reader.
8027 */
8028 kvm->arch.last_tsc_nsec = 0;
8029 kvm->arch.last_tsc_write = 0;
8030 }
8031
8032 }
8033 return 0;
e9b11c17
ZX		 8034}
8035
13a34e06 8036void kvm_arch_hardware_disable(void)
e9b11c17 8037{
13a34e06
RK		 8038 kvm_x86_ops->hardware_disable();
8039 drop_user_return_notifiers();
e9b11c17
ZX		 8040}
8041
8042int kvm_arch_hardware_setup(void)
8043{
9e9c3fe4
NA		 8044 int r;
8045
8046 r = kvm_x86_ops->hardware_setup();
8047 if (r != 0)
8048 return r;
8049
35181e86
HZ		 8050 if (kvm_has_tsc_control) {
8051 /*
8052 * Make sure the user can only configure tsc_khz values that
8053 * fit into a signed integer.
8054 * A min value is not calculated needed because it will always
8055 * be 1 on all machines.
8056 */
8057 u64 max = min(0x7fffffffULL,
8058 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8059 kvm_max_guest_tsc_khz = max;
8060
ad721883 8061 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8062 }
ad721883 8063
9e9c3fe4
NA		 8064 kvm_init_msr_list();
8065 return 0;
e9b11c17
ZX		 8066}
8067
8068void kvm_arch_hardware_unsetup(void)
8069{
8070 kvm_x86_ops->hardware_unsetup();
8071}
8072
8073void kvm_arch_check_processor_compat(void *rtn)
8074{
8075 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8076}
8077
8078bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8079{
8080 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8081}
8082EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8083
8084bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8085{
8086 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8087}
8088
54e9818f 8089struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8090EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8091
e9b11c17
ZX		 8092int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8093{
8094 struct page *page;
e9b11c17
ZX		 8095 int r;
8096
b2a05fef 8097 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8098 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8099 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8100 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8101 else
a4535290 8102 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8103
8104 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8105 if (!page) {
8106 r = -ENOMEM;
8107 goto fail;
8108 }
ad312c7c 8109 vcpu->arch.pio_data = page_address(page);
e9b11c17 8110
cc578287 8111 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8112
e9b11c17
ZX		 8113 r = kvm_mmu_create(vcpu);
8114 if (r < 0)
8115 goto fail_free_pio_data;
8116
26de7988 8117 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8118 r = kvm_create_lapic(vcpu);
8119 if (r < 0)
8120 goto fail_mmu_destroy;
54e9818f
GN		 8121 } else
8122 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8123
890ca9ae
HY		 8124 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8125 GFP_KERNEL);
8126 if (!vcpu->arch.mce_banks) {
8127 r = -ENOMEM;
443c39bc 8128 goto fail_free_lapic;
890ca9ae
HY		 8129 }
8130 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8131
f1797359
WY		 8132 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8133 r = -ENOMEM;
f5f48ee1 8134 goto fail_free_mce_banks;
f1797359 8135 }
f5f48ee1 8136
0ee6a517 8137 fx_init(vcpu);
66f7b72e 8138
4344ee98 8139 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8140
5a4f55cd
EK		 8141 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8142
74545705
RK		 8143 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8144
af585b92 8145 kvm_async_pf_hash_reset(vcpu);
f5132b01 8146 kvm_pmu_init(vcpu);
af585b92 8147
1c1a9ce9 8148 vcpu->arch.pending_external_vector = -1;
de63ad4c 8149 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8150
5c919412
AS		 8151 kvm_hv_vcpu_init(vcpu);
8152
e9b11c17 8153 return 0;
0ee6a517 8154
f5f48ee1
SY		 8155fail_free_mce_banks:
8156 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8157fail_free_lapic:
8158 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8159fail_mmu_destroy:
8160 kvm_mmu_destroy(vcpu);
8161fail_free_pio_data:
ad312c7c 8162 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8163fail:
8164 return r;
8165}
8166
8167void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8168{
f656ce01
MT		 8169 int idx;
8170
1f4b34f8 8171 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8172 kvm_pmu_destroy(vcpu);
36cb93fd 8173 kfree(vcpu->arch.mce_banks);
e9b11c17 8174 kvm_free_lapic(vcpu);
f656ce01 8175 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8176 kvm_mmu_destroy(vcpu);
f656ce01 8177 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8178 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8179 if (!lapic_in_kernel(vcpu))
54e9818f 8180 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8181}
d19a9cd2 8182
e790d9ef
RK		 8183void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8184{
ae97a3b8 8185 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8186}
8187
e08b9637 8188int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8189{
e08b9637
CO		 8190 if (type)
8191 return -EINVAL;
8192
6ef768fa 8193 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8194 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8195 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8196 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8197 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8198
5550af4d
SY		 8199 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8200 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8201 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8202 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8203 &kvm->arch.irq_sources_bitmap);
5550af4d 8204
038f8c11 8205 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8206 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8207 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8208 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8209
108b249c 8210 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8211 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8212
7e44e449 8213 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8214 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8215
0eb05bf2 8216 kvm_page_track_init(kvm);
13d268ca 8217 kvm_mmu_init_vm(kvm);
0eb05bf2 8218
03543133
SS		 8219 if (kvm_x86_ops->vm_init)
8220 return kvm_x86_ops->vm_init(kvm);
8221
d89f5eff 8222 return 0;
d19a9cd2
ZX		 8223}
8224
8225static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8226{
ec7660cc 8227 vcpu_load(vcpu);
d19a9cd2
ZX		 8228 kvm_mmu_unload(vcpu);
8229 vcpu_put(vcpu);
8230}
8231
8232static void kvm_free_vcpus(struct kvm *kvm)
8233{
8234 unsigned int i;
988a2cae 8235 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8236
8237 /*
8238 * Unpin any mmu pages first.
8239 */
af585b92
GN		 8240 kvm_for_each_vcpu(i, vcpu, kvm) {
8241 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8242 kvm_unload_vcpu_mmu(vcpu);
af585b92 8243 }
988a2cae
GN		 8244 kvm_for_each_vcpu(i, vcpu, kvm)
8245 kvm_arch_vcpu_free(vcpu);
8246
8247 mutex_lock(&kvm->lock);
8248 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8249 kvm->vcpus[i] = NULL;
d19a9cd2 8250
988a2cae
GN		 8251 atomic_set(&kvm->online_vcpus, 0);
8252 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8253}
8254
ad8ba2cd
SY		 8255void kvm_arch_sync_events(struct kvm *kvm)
8256{
332967a3 8257 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8258 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8259 kvm_free_pit(kvm);
ad8ba2cd
SY		 8260}
8261
1d8007bd 8262int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8263{
8264 int i, r;
25188b99 8265 unsigned long hva;
f0d648bd
PB		 8266 struct kvm_memslots *slots = kvm_memslots(kvm);
8267 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8268
8269 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8270 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8271 return -EINVAL;
9da0e4d5 8272
f0d648bd
PB		 8273 slot = id_to_memslot(slots, id);
8274 if (size) {
b21629da 8275 if (slot->npages)
f0d648bd
PB		 8276 return -EEXIST;
8277
8278 /*
8279 * MAP_SHARED to prevent internal slot pages from being moved
8280 * by fork()/COW.
8281 */
8282 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8283 MAP_SHARED | MAP_ANONYMOUS, 0);
8284 if (IS_ERR((void *)hva))
8285 return PTR_ERR((void *)hva);
8286 } else {
8287 if (!slot->npages)
8288 return 0;
8289
8290 hva = 0;
8291 }
8292
8293 old = *slot;
9da0e4d5 8294 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8295 struct kvm_userspace_memory_region m;
9da0e4d5 8296
1d8007bd
PB		 8297 m.slot = id | (i << 16);
8298 m.flags = 0;
8299 m.guest_phys_addr = gpa;
f0d648bd 8300 m.userspace_addr = hva;
1d8007bd 8301 m.memory_size = size;
9da0e4d5
PB		 8302 r = __kvm_set_memory_region(kvm, &m);
8303 if (r < 0)
8304 return r;
8305 }
8306
f0d648bd
PB		 8307 if (!size) {
8308 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8309 WARN_ON(r < 0);
8310 }
8311
9da0e4d5
PB		 8312 return 0;
8313}
8314EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8315
1d8007bd 8316int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8317{
8318 int r;
8319
8320 mutex_lock(&kvm->slots_lock);
1d8007bd 8321 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8322 mutex_unlock(&kvm->slots_lock);
8323
8324 return r;
8325}
8326EXPORT_SYMBOL_GPL(x86_set_memory_region);
8327
d19a9cd2
ZX		 8328void kvm_arch_destroy_vm(struct kvm *kvm)
8329{
27469d29
AH		 8330 if (current->mm == kvm->mm) {
8331 /*
8332 * Free memory regions allocated on behalf of userspace,
8333 * unless the the memory map has changed due to process exit
8334 * or fd copying.
8335 */
1d8007bd
PB		 8336 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8337 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8338 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8339 }
03543133
SS		 8340 if (kvm_x86_ops->vm_destroy)
8341 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8342 kvm_pic_destroy(kvm);
8343 kvm_ioapic_destroy(kvm);
d19a9cd2 8344 kvm_free_vcpus(kvm);
af1bae54 8345 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8346 kvm_mmu_uninit_vm(kvm);
2beb6dad 8347 kvm_page_track_cleanup(kvm);
d19a9cd2 8348}
0de10343 8349
5587027c 8350void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8351 struct kvm_memory_slot *dont)
8352{
8353 int i;
8354
d89cc617
TY		 8355 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8356 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8357 kvfree(free->arch.rmap[i]);
d89cc617 8358 free->arch.rmap[i] = NULL;
77d11309 8359 }
d89cc617
TY		 8360 if (i == 0)
8361 continue;
8362
8363 if (!dont || free->arch.lpage_info[i - 1] !=
8364 dont->arch.lpage_info[i - 1]) {
548ef284 8365 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8366 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8367 }
8368 }
21ebbeda
XG		 8369
8370 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8371}
8372
5587027c
AK		 8373int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8374 unsigned long npages)
db3fe4eb
TY		 8375{
8376 int i;
8377
d89cc617 8378 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8379 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8380 unsigned long ugfn;
8381 int lpages;
d89cc617 8382 int level = i + 1;
db3fe4eb
TY		 8383
8384 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8385 slot->base_gfn, level) + 1;
8386
d89cc617 8387 slot->arch.rmap[i] =
a7c3e901 8388 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8389 if (!slot->arch.rmap[i])
77d11309 8390 goto out_free;
d89cc617
TY		 8391 if (i == 0)
8392 continue;
77d11309 8393
a7c3e901 8394 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8395 if (!linfo)
db3fe4eb
TY		 8396 goto out_free;
8397
92f94f1e
XG		 8398 slot->arch.lpage_info[i - 1] = linfo;
8399
db3fe4eb 8400 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8401 linfo[0].disallow_lpage = 1;
db3fe4eb 8402 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8403 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8404 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8405 /*
8406 * If the gfn and userspace address are not aligned wrt each
8407 * other, or if explicitly asked to, disable large page
8408 * support for this slot
8409 */
8410 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8411 !kvm_largepages_enabled()) {
8412 unsigned long j;
8413
8414 for (j = 0; j < lpages; ++j)
92f94f1e 8415 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8416 }
8417 }
8418
21ebbeda
XG		 8419 if (kvm_page_track_create_memslot(slot, npages))
8420 goto out_free;
8421
db3fe4eb
TY		 8422 return 0;
8423
8424out_free:
d89cc617 8425 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8426 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8427 slot->arch.rmap[i] = NULL;
8428 if (i == 0)
8429 continue;
8430
548ef284 8431 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8432 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8433 }
8434 return -ENOMEM;
8435}
8436
15f46015 8437void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8438{
e6dff7d1
TY		 8439 /*
8440 * memslots->generation has been incremented.
8441 * mmio generation may have reached its maximum value.
8442 */
54bf36aa 8443 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8444}
8445
f7784b8e
MT		 8446int kvm_arch_prepare_memory_region(struct kvm *kvm,
8447 struct kvm_memory_slot *memslot,
09170a49 8448 const struct kvm_userspace_memory_region *mem,
7b6195a9 8449 enum kvm_mr_change change)
0de10343 8450{
f7784b8e
MT		 8451 return 0;
8452}
8453
88178fd4
KH		 8454static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8455 struct kvm_memory_slot *new)
8456{
8457 /* Still write protect RO slot */
8458 if (new->flags & KVM_MEM_READONLY) {
8459 kvm_mmu_slot_remove_write_access(kvm, new);
8460 return;
8461 }
8462
8463 /*
8464 * Call kvm_x86_ops dirty logging hooks when they are valid.
8465 *
8466 * kvm_x86_ops->slot_disable_log_dirty is called when:
8467 *
8468 * - KVM_MR_CREATE with dirty logging is disabled
8469 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8470 *
8471 * The reason is, in case of PML, we need to set D-bit for any slots
8472 * with dirty logging disabled in order to eliminate unnecessary GPA
8473 * logging in PML buffer (and potential PML buffer full VMEXT). This
8474 * guarantees leaving PML enabled during guest's lifetime won't have
8475 * any additonal overhead from PML when guest is running with dirty
8476 * logging disabled for memory slots.
8477 *
8478 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8479 * to dirty logging mode.
8480 *
8481 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8482 *
8483 * In case of write protect:
8484 *
8485 * Write protect all pages for dirty logging.
8486 *
8487 * All the sptes including the large sptes which point to this
8488 * slot are set to readonly. We can not create any new large
8489 * spte on this slot until the end of the logging.
8490 *
8491 * See the comments in fast_page_fault().
8492 */
8493 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8494 if (kvm_x86_ops->slot_enable_log_dirty)
8495 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8496 else
8497 kvm_mmu_slot_remove_write_access(kvm, new);
8498 } else {
8499 if (kvm_x86_ops->slot_disable_log_dirty)
8500 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8501 }
8502}
8503
f7784b8e 8504void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8505 const struct kvm_userspace_memory_region *mem,
8482644a 8506 const struct kvm_memory_slot *old,
f36f3f28 8507 const struct kvm_memory_slot *new,
8482644a 8508 enum kvm_mr_change change)
f7784b8e 8509{
8482644a 8510 int nr_mmu_pages = 0;
f7784b8e 8511
48c0e4e9
XG		 8512 if (!kvm->arch.n_requested_mmu_pages)
8513 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8514
48c0e4e9 8515 if (nr_mmu_pages)
0de10343 8516 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8517
3ea3b7fa
WL		 8518 /*
8519 * Dirty logging tracks sptes in 4k granularity, meaning that large
8520 * sptes have to be split. If live migration is successful, the guest
8521 * in the source machine will be destroyed and large sptes will be
8522 * created in the destination. However, if the guest continues to run
8523 * in the source machine (for example if live migration fails), small
8524 * sptes will remain around and cause bad performance.
8525 *
8526 * Scan sptes if dirty logging has been stopped, dropping those
8527 * which can be collapsed into a single large-page spte. Later
8528 * page faults will create the large-page sptes.
8529 */
8530 if ((change != KVM_MR_DELETE) &&
8531 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8532 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8533 kvm_mmu_zap_collapsible_sptes(kvm, new);
8534
c972f3b1 8535 /*
88178fd4 8536 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8537 *
88178fd4
KH		 8538 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8539 * been zapped so no dirty logging staff is needed for old slot. For
8540 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8541 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8542 *
8543 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8544 */
88178fd4 8545 if (change != KVM_MR_DELETE)
f36f3f28 8546 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8547}
1d737c8a 8548
2df72e9b 8549void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8550{
6ca18b69 8551 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8552}
8553
2df72e9b
MT		 8554void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8555 struct kvm_memory_slot *slot)
8556{
ae7cd873 8557 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8558}
8559
5d9bc648
PB		 8560static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8561{
8562 if (!list_empty_careful(&vcpu->async_pf.done))
8563 return true;
8564
8565 if (kvm_apic_has_events(vcpu))
8566 return true;
8567
8568 if (vcpu->arch.pv.pv_unhalted)
8569 return true;
8570
a5f01f8e
WL		 8571 if (vcpu->arch.exception.pending)
8572 return true;
8573
47a66eed
Z		 8574 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8575 (vcpu->arch.nmi_pending &&
8576 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8577 return true;
8578
47a66eed
Z		 8579 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8580 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8581 return true;
8582
5d9bc648
PB		 8583 if (kvm_arch_interrupt_allowed(vcpu) &&
8584 kvm_cpu_has_interrupt(vcpu))
8585 return true;
8586
1f4b34f8
AS		 8587 if (kvm_hv_has_stimer_pending(vcpu))
8588 return true;
8589
5d9bc648
PB		 8590 return false;
8591}
8592
1d737c8a
ZX		 8593int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8594{
5d9bc648 8595 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8596}
5736199a 8597
199b5763
LM		 8598bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8599{
de63ad4c 8600 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8601}
8602
b6d33834 8603int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8604{
b6d33834 8605 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8606}
78646121
GN		 8607
8608int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8609{
8610 return kvm_x86_ops->interrupt_allowed(vcpu);
8611}
229456fc 8612
82b32774 8613unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8614{
82b32774
NA		 8615 if (is_64_bit_mode(vcpu))
8616 return kvm_rip_read(vcpu);
8617 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8618 kvm_rip_read(vcpu));
8619}
8620EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8621
82b32774
NA		 8622bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8623{
8624 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8625}
8626EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8627
94fe45da
JK		 8628unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8629{
8630 unsigned long rflags;
8631
8632 rflags = kvm_x86_ops->get_rflags(vcpu);
8633 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8634 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8635 return rflags;
8636}
8637EXPORT_SYMBOL_GPL(kvm_get_rflags);
8638
6addfc42 8639static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8640{
8641 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8642 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8643 rflags |= X86_EFLAGS_TF;
94fe45da 8644 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8645}
8646
8647void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8648{
8649 __kvm_set_rflags(vcpu, rflags);
3842d135 8650 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8651}
8652EXPORT_SYMBOL_GPL(kvm_set_rflags);
8653
56028d08
GN		 8654void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8655{
8656 int r;
8657
fb67e14f 8658 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8659 work->wakeup_all)
56028d08
GN		 8660 return;
8661
8662 r = kvm_mmu_reload(vcpu);
8663 if (unlikely(r))
8664 return;
8665
fb67e14f
XG		 8666 if (!vcpu->arch.mmu.direct_map &&
8667 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8668 return;
8669
56028d08
GN		 8670 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8671}
8672
af585b92
GN		 8673static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8674{
8675 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8676}
8677
8678static inline u32 kvm_async_pf_next_probe(u32 key)
8679{
8680 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8681}
8682
8683static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8684{
8685 u32 key = kvm_async_pf_hash_fn(gfn);
8686
8687 while (vcpu->arch.apf.gfns[key] != ~0)
8688 key = kvm_async_pf_next_probe(key);
8689
8690 vcpu->arch.apf.gfns[key] = gfn;
8691}
8692
8693static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8694{
8695 int i;
8696 u32 key = kvm_async_pf_hash_fn(gfn);
8697
8698 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8699 (vcpu->arch.apf.gfns[key] != gfn &&
8700 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8701 key = kvm_async_pf_next_probe(key);
8702
8703 return key;
8704}
8705
8706bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8707{
8708 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8709}
8710
8711static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8712{
8713 u32 i, j, k;
8714
8715 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8716 while (true) {
8717 vcpu->arch.apf.gfns[i] = ~0;
8718 do {
8719 j = kvm_async_pf_next_probe(j);
8720 if (vcpu->arch.apf.gfns[j] == ~0)
8721 return;
8722 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8723 /*
8724 * k lies cyclically in ]i,j]
8725 * | i.k.j |
8726 * |....j i.k.| or |.k..j i...|
8727 */
8728 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8729 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8730 i = j;
8731 }
8732}
8733
7c90705b
GN		 8734static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8735{
4e335d9e
PB		 8736
8737 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8738 sizeof(val));
7c90705b
GN		 8739}
8740
9a6e7c39
WL		 8741static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8742{
8743
8744 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8745 sizeof(u32));
8746}
8747
af585b92
GN		 8748void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8749 struct kvm_async_pf *work)
8750{
6389ee94
AK		 8751 struct x86_exception fault;
8752
7c90705b 8753 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8754 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8755
8756 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8757 (vcpu->arch.apf.send_user_only &&
8758 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8759 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8760 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8761 fault.vector = PF_VECTOR;
8762 fault.error_code_valid = true;
8763 fault.error_code = 0;
8764 fault.nested_page_fault = false;
8765 fault.address = work->arch.token;
adfe20fb 8766 fault.async_page_fault = true;
6389ee94 8767 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8768 }
af585b92
GN		 8769}
8770
8771void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8772 struct kvm_async_pf *work)
8773{
6389ee94 8774 struct x86_exception fault;
9a6e7c39 8775 u32 val;
6389ee94 8776
f2e10669 8777 if (work->wakeup_all)
7c90705b
GN		 8778 work->arch.token = ~0; /* broadcast wakeup */
8779 else
8780 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8781 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8782
9a6e7c39
WL		 8783 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8784 !apf_get_user(vcpu, &val)) {
8785 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8786 vcpu->arch.exception.pending &&
8787 vcpu->arch.exception.nr == PF_VECTOR &&
8788 !apf_put_user(vcpu, 0)) {
8789 vcpu->arch.exception.injected = false;
8790 vcpu->arch.exception.pending = false;
8791 vcpu->arch.exception.nr = 0;
8792 vcpu->arch.exception.has_error_code = false;
8793 vcpu->arch.exception.error_code = 0;
8794 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8795 fault.vector = PF_VECTOR;
8796 fault.error_code_valid = true;
8797 fault.error_code = 0;
8798 fault.nested_page_fault = false;
8799 fault.address = work->arch.token;
8800 fault.async_page_fault = true;
8801 kvm_inject_page_fault(vcpu, &fault);
8802 }
7c90705b 8803 }
e6d53e3b 8804 vcpu->arch.apf.halted = false;
a4fa1635 8805 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8806}
8807
8808bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8809{
8810 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8811 return true;
8812 else
9bc1f09f 8813 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8814}
8815
5544eb9b
PB		 8816void kvm_arch_start_assignment(struct kvm *kvm)
8817{
8818 atomic_inc(&kvm->arch.assigned_device_count);
8819}
8820EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8821
8822void kvm_arch_end_assignment(struct kvm *kvm)
8823{
8824 atomic_dec(&kvm->arch.assigned_device_count);
8825}
8826EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8827
8828bool kvm_arch_has_assigned_device(struct kvm *kvm)
8829{
8830 return atomic_read(&kvm->arch.assigned_device_count);
8831}
8832EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8833
e0f0bbc5
AW		 8834void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8835{
8836 atomic_inc(&kvm->arch.noncoherent_dma_count);
8837}
8838EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8839
8840void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8841{
8842 atomic_dec(&kvm->arch.noncoherent_dma_count);
8843}
8844EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8845
8846bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8847{
8848 return atomic_read(&kvm->arch.noncoherent_dma_count);
8849}
8850EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8851
14717e20
AW		 8852bool kvm_arch_has_irq_bypass(void)
8853{
8854 return kvm_x86_ops->update_pi_irte != NULL;
8855}
8856
87276880
FW		 8857int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8858 struct irq_bypass_producer *prod)
8859{
8860 struct kvm_kernel_irqfd *irqfd =
8861 container_of(cons, struct kvm_kernel_irqfd, consumer);
8862
14717e20 8863 irqfd->producer = prod;
87276880 8864
14717e20
AW		 8865 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8866 prod->irq, irqfd->gsi, 1);
87276880
FW		 8867}
8868
8869void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8870 struct irq_bypass_producer *prod)
8871{
8872 int ret;
8873 struct kvm_kernel_irqfd *irqfd =
8874 container_of(cons, struct kvm_kernel_irqfd, consumer);
8875
87276880
FW		 8876 WARN_ON(irqfd->producer != prod);
8877 irqfd->producer = NULL;
8878
8879 /*
8880 * When producer of consumer is unregistered, we change back to
8881 * remapped mode, so we can re-use the current implementation
bb3541f1 8882 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8883 * int this case doesn't want to receive the interrupts.
8884 */
8885 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8886 if (ret)
8887 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8888 " fails: %d\n", irqfd->consumer.token, ret);
8889}
8890
8891int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8892 uint32_t guest_irq, bool set)
8893{
8894 if (!kvm_x86_ops->update_pi_irte)
8895 return -EINVAL;
8896
8897 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8898}
8899
52004014
FW		 8900bool kvm_vector_hashing_enabled(void)
8901{
8902 return vector_hashing;
8903}
8904EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8905
229456fc 8906EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8907EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8908EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8909EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8910EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8911EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8912EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8913EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8914EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8915EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8916EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8917EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8918EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8919EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8920EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8921EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8922EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8923EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8924EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)