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20c8ccb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
043405e1 CO |
2 | /* |
3 | * Kernel-based Virtual Machine driver for Linux | |
4 | * | |
5 | * derived from drivers/kvm/kvm_main.c | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
4d5c5d0f BAY |
8 | * Copyright (C) 2008 Qumranet, Inc. |
9 | * Copyright IBM Corporation, 2008 | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
043405e1 CO |
11 | * |
12 | * Authors: | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
4d5c5d0f BAY |
15 | * Amit Shah <amit.shah@qumranet.com> |
16 | * Ben-Ami Yassour <benami@il.ibm.com> | |
043405e1 CO |
17 | */ |
18 | ||
edf88417 | 19 | #include <linux/kvm_host.h> |
313a3dc7 | 20 | #include "irq.h" |
88197e6a | 21 | #include "ioapic.h" |
1d737c8a | 22 | #include "mmu.h" |
7837699f | 23 | #include "i8254.h" |
37817f29 | 24 | #include "tss.h" |
5fdbf976 | 25 | #include "kvm_cache_regs.h" |
2f728d66 | 26 | #include "kvm_emulate.h" |
26eef70c | 27 | #include "x86.h" |
00b27a3e | 28 | #include "cpuid.h" |
474a5bb9 | 29 | #include "pmu.h" |
e83d5887 | 30 | #include "hyperv.h" |
8df14af4 | 31 | #include "lapic.h" |
23200b7a | 32 | #include "xen.h" |
313a3dc7 | 33 | |
18068523 | 34 | #include <linux/clocksource.h> |
4d5c5d0f | 35 | #include <linux/interrupt.h> |
313a3dc7 CO |
36 | #include <linux/kvm.h> |
37 | #include <linux/fs.h> | |
38 | #include <linux/vmalloc.h> | |
1767e931 PG |
39 | #include <linux/export.h> |
40 | #include <linux/moduleparam.h> | |
0de10343 | 41 | #include <linux/mman.h> |
2bacc55c | 42 | #include <linux/highmem.h> |
19de40a8 | 43 | #include <linux/iommu.h> |
c8076604 | 44 | #include <linux/cpufreq.h> |
18863bdd | 45 | #include <linux/user-return-notifier.h> |
a983fb23 | 46 | #include <linux/srcu.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
ff9d07a0 | 48 | #include <linux/perf_event.h> |
7bee342a | 49 | #include <linux/uaccess.h> |
af585b92 | 50 | #include <linux/hash.h> |
a1b60c1c | 51 | #include <linux/pci.h> |
16e8d74d MT |
52 | #include <linux/timekeeper_internal.h> |
53 | #include <linux/pvclock_gtod.h> | |
87276880 FW |
54 | #include <linux/kvm_irqfd.h> |
55 | #include <linux/irqbypass.h> | |
3905f9ad | 56 | #include <linux/sched/stat.h> |
0c5f81da | 57 | #include <linux/sched/isolation.h> |
d0ec49d4 | 58 | #include <linux/mem_encrypt.h> |
72c3c0fe | 59 | #include <linux/entry-kvm.h> |
7d62874f | 60 | #include <linux/suspend.h> |
3905f9ad | 61 | |
aec51dc4 | 62 | #include <trace/events/kvm.h> |
2ed152af | 63 | |
24f1e32c | 64 | #include <asm/debugreg.h> |
d825ed0a | 65 | #include <asm/msr.h> |
a5f61300 | 66 | #include <asm/desc.h> |
890ca9ae | 67 | #include <asm/mce.h> |
784a4661 | 68 | #include <asm/pkru.h> |
f89e32e0 | 69 | #include <linux/kernel_stat.h> |
a0ff0611 TG |
70 | #include <asm/fpu/api.h> |
71 | #include <asm/fpu/xcr.h> | |
72 | #include <asm/fpu/xstate.h> | |
1d5f066e | 73 | #include <asm/pvclock.h> |
217fc9cf | 74 | #include <asm/div64.h> |
efc64404 | 75 | #include <asm/irq_remapping.h> |
b0c39dc6 | 76 | #include <asm/mshyperv.h> |
0092e434 | 77 | #include <asm/hypervisor.h> |
9715092f | 78 | #include <asm/tlbflush.h> |
bf8c55d8 | 79 | #include <asm/intel_pt.h> |
b3dc0695 | 80 | #include <asm/emulate_prefix.h> |
fe7e9488 | 81 | #include <asm/sgx.h> |
dd2cb348 | 82 | #include <clocksource/hyperv_timer.h> |
043405e1 | 83 | |
d1898b73 DH |
84 | #define CREATE_TRACE_POINTS |
85 | #include "trace.h" | |
86 | ||
313a3dc7 | 87 | #define MAX_IO_MSRS 256 |
890ca9ae | 88 | #define KVM_MAX_MCE_BANKS 32 |
938c8745 SC |
89 | |
90 | struct kvm_caps kvm_caps __read_mostly = { | |
91 | .supported_mce_cap = MCG_CTL_P | MCG_SER_P, | |
92 | }; | |
93 | EXPORT_SYMBOL_GPL(kvm_caps); | |
890ca9ae | 94 | |
6e37ec88 SC |
95 | #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e)) |
96 | ||
0f65dd70 | 97 | #define emul_to_vcpu(ctxt) \ |
c9b8b07c | 98 | ((struct kvm_vcpu *)(ctxt)->vcpu) |
0f65dd70 | 99 | |
50a37eb4 JR |
100 | /* EFER defaults: |
101 | * - enable syscall per default because its emulated by KVM | |
102 | * - enable LME and LMA per default on 64 bit KVM | |
103 | */ | |
104 | #ifdef CONFIG_X86_64 | |
1260edbe LJ |
105 | static |
106 | u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA)); | |
50a37eb4 | 107 | #else |
1260edbe | 108 | static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE); |
50a37eb4 | 109 | #endif |
313a3dc7 | 110 | |
b11306b5 SC |
111 | static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS; |
112 | ||
0dbb1123 AK |
113 | #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE) |
114 | ||
ba7bb663 DD |
115 | #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE |
116 | ||
c519265f RK |
117 | #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \ |
118 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) | |
37131313 | 119 | |
cb142eb7 | 120 | static void update_cr8_intercept(struct kvm_vcpu *vcpu); |
7460fb4a | 121 | static void process_nmi(struct kvm_vcpu *vcpu); |
1f7becf1 | 122 | static void process_smi(struct kvm_vcpu *vcpu); |
ee2cd4b7 | 123 | static void enter_smm(struct kvm_vcpu *vcpu); |
6addfc42 | 124 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); |
01643c51 KH |
125 | static void store_regs(struct kvm_vcpu *vcpu); |
126 | static int sync_regs(struct kvm_vcpu *vcpu); | |
d2f7d498 | 127 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu); |
674eea0f | 128 | |
6dba9403 ML |
129 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); |
130 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2); | |
131 | ||
afaf0b2f | 132 | struct kvm_x86_ops kvm_x86_ops __read_mostly; |
97896d04 | 133 | |
9af5471b JB |
134 | #define KVM_X86_OP(func) \ |
135 | DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \ | |
136 | *(((struct kvm_x86_ops *)0)->func)); | |
e4fc23ba | 137 | #define KVM_X86_OP_OPTIONAL KVM_X86_OP |
5be2226f | 138 | #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP |
9af5471b JB |
139 | #include <asm/kvm-x86-ops.h> |
140 | EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits); | |
141 | EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg); | |
9af5471b | 142 | |
893590c7 | 143 | static bool __read_mostly ignore_msrs = 0; |
476bc001 | 144 | module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR); |
ed85c068 | 145 | |
d855066f | 146 | bool __read_mostly report_ignored_msrs = true; |
fab0aa3b | 147 | module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR); |
d855066f | 148 | EXPORT_SYMBOL_GPL(report_ignored_msrs); |
fab0aa3b | 149 | |
4c27625b | 150 | unsigned int min_timer_period_us = 200; |
9ed96e87 MT |
151 | module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR); |
152 | ||
630994b3 MT |
153 | static bool __read_mostly kvmclock_periodic_sync = true; |
154 | module_param(kvmclock_periodic_sync, bool, S_IRUGO); | |
155 | ||
cc578287 | 156 | /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */ |
893590c7 | 157 | static u32 __read_mostly tsc_tolerance_ppm = 250; |
cc578287 ZA |
158 | module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR); |
159 | ||
c3941d9e SC |
160 | /* |
161 | * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables | |
d9f6e12f | 162 | * adaptive tuning starting from default advancement of 1000ns. '0' disables |
c3941d9e | 163 | * advancement entirely. Any other value is used as-is and disables adaptive |
d9f6e12f | 164 | * tuning, i.e. allows privileged userspace to set an exact advancement time. |
c3941d9e SC |
165 | */ |
166 | static int __read_mostly lapic_timer_advance_ns = -1; | |
0e6edceb | 167 | module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR); |
d0659d94 | 168 | |
52004014 FW |
169 | static bool __read_mostly vector_hashing = true; |
170 | module_param(vector_hashing, bool, S_IRUGO); | |
171 | ||
c4ae60e4 LA |
172 | bool __read_mostly enable_vmware_backdoor = false; |
173 | module_param(enable_vmware_backdoor, bool, S_IRUGO); | |
174 | EXPORT_SYMBOL_GPL(enable_vmware_backdoor); | |
175 | ||
d500e1ed SC |
176 | /* |
177 | * Flags to manipulate forced emulation behavior (any non-zero value will | |
178 | * enable forced emulation). | |
179 | */ | |
180 | #define KVM_FEP_CLEAR_RFLAGS_RF BIT(1) | |
181 | static int __read_mostly force_emulation_prefix; | |
182 | module_param(force_emulation_prefix, int, 0444); | |
6c86eedc | 183 | |
0c5f81da WL |
184 | int __read_mostly pi_inject_timer = -1; |
185 | module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR); | |
186 | ||
4732f244 LX |
187 | /* Enable/disable PMU virtualization */ |
188 | bool __read_mostly enable_pmu = true; | |
189 | EXPORT_SYMBOL_GPL(enable_pmu); | |
190 | module_param(enable_pmu, bool, 0444); | |
191 | ||
cb00a70b | 192 | bool __read_mostly eager_page_split = true; |
a3fe5dbd DM |
193 | module_param(eager_page_split, bool, 0644); |
194 | ||
7e34fbd0 SC |
195 | /* |
196 | * Restoring the host value for MSRs that are only consumed when running in | |
197 | * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU | |
198 | * returns to userspace, i.e. the kernel can run with the guest's value. | |
199 | */ | |
200 | #define KVM_MAX_NR_USER_RETURN_MSRS 16 | |
18863bdd | 201 | |
7e34fbd0 | 202 | struct kvm_user_return_msrs { |
18863bdd AK |
203 | struct user_return_notifier urn; |
204 | bool registered; | |
7e34fbd0 | 205 | struct kvm_user_return_msr_values { |
2bf78fa7 SY |
206 | u64 host; |
207 | u64 curr; | |
7e34fbd0 | 208 | } values[KVM_MAX_NR_USER_RETURN_MSRS]; |
18863bdd AK |
209 | }; |
210 | ||
9cc39a5a SC |
211 | u32 __read_mostly kvm_nr_uret_msrs; |
212 | EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs); | |
213 | static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS]; | |
7e34fbd0 | 214 | static struct kvm_user_return_msrs __percpu *user_return_msrs; |
18863bdd | 215 | |
cfc48181 SC |
216 | #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ |
217 | | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ | |
218 | | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ | |
86aff7a4 | 219 | | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE) |
cfc48181 | 220 | |
91661989 SC |
221 | u64 __read_mostly host_efer; |
222 | EXPORT_SYMBOL_GPL(host_efer); | |
223 | ||
b96e6506 | 224 | bool __read_mostly allow_smaller_maxphyaddr = 0; |
3edd6839 MG |
225 | EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); |
226 | ||
fdf513e3 VK |
227 | bool __read_mostly enable_apicv = true; |
228 | EXPORT_SYMBOL_GPL(enable_apicv); | |
229 | ||
86137773 TL |
230 | u64 __read_mostly host_xss; |
231 | EXPORT_SYMBOL_GPL(host_xss); | |
139a12cf | 232 | |
fcfe1bae JZ |
233 | const struct _kvm_stats_desc kvm_vm_stats_desc[] = { |
234 | KVM_GENERIC_VM_STATS(), | |
235 | STATS_DESC_COUNTER(VM, mmu_shadow_zapped), | |
236 | STATS_DESC_COUNTER(VM, mmu_pte_write), | |
237 | STATS_DESC_COUNTER(VM, mmu_pde_zapped), | |
238 | STATS_DESC_COUNTER(VM, mmu_flooded), | |
239 | STATS_DESC_COUNTER(VM, mmu_recycled), | |
240 | STATS_DESC_COUNTER(VM, mmu_cache_miss), | |
241 | STATS_DESC_ICOUNTER(VM, mmu_unsync), | |
71f51d2c MZ |
242 | STATS_DESC_ICOUNTER(VM, pages_4k), |
243 | STATS_DESC_ICOUNTER(VM, pages_2m), | |
244 | STATS_DESC_ICOUNTER(VM, pages_1g), | |
fcfe1bae | 245 | STATS_DESC_ICOUNTER(VM, nx_lpage_splits), |
ec1cf69c | 246 | STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size), |
bc9e9e67 | 247 | STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions) |
fcfe1bae | 248 | }; |
fcfe1bae JZ |
249 | |
250 | const struct kvm_stats_header kvm_vm_stats_header = { | |
251 | .name_size = KVM_STATS_NAME_SIZE, | |
252 | .num_desc = ARRAY_SIZE(kvm_vm_stats_desc), | |
253 | .id_offset = sizeof(struct kvm_stats_header), | |
254 | .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, | |
255 | .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + | |
256 | sizeof(kvm_vm_stats_desc), | |
257 | }; | |
258 | ||
ce55c049 JZ |
259 | const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { |
260 | KVM_GENERIC_VCPU_STATS(), | |
1075d41e | 261 | STATS_DESC_COUNTER(VCPU, pf_taken), |
ce55c049 | 262 | STATS_DESC_COUNTER(VCPU, pf_fixed), |
1075d41e SC |
263 | STATS_DESC_COUNTER(VCPU, pf_emulate), |
264 | STATS_DESC_COUNTER(VCPU, pf_spurious), | |
265 | STATS_DESC_COUNTER(VCPU, pf_fast), | |
266 | STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created), | |
ce55c049 JZ |
267 | STATS_DESC_COUNTER(VCPU, pf_guest), |
268 | STATS_DESC_COUNTER(VCPU, tlb_flush), | |
269 | STATS_DESC_COUNTER(VCPU, invlpg), | |
270 | STATS_DESC_COUNTER(VCPU, exits), | |
271 | STATS_DESC_COUNTER(VCPU, io_exits), | |
272 | STATS_DESC_COUNTER(VCPU, mmio_exits), | |
273 | STATS_DESC_COUNTER(VCPU, signal_exits), | |
274 | STATS_DESC_COUNTER(VCPU, irq_window_exits), | |
275 | STATS_DESC_COUNTER(VCPU, nmi_window_exits), | |
276 | STATS_DESC_COUNTER(VCPU, l1d_flush), | |
277 | STATS_DESC_COUNTER(VCPU, halt_exits), | |
278 | STATS_DESC_COUNTER(VCPU, request_irq_exits), | |
279 | STATS_DESC_COUNTER(VCPU, irq_exits), | |
280 | STATS_DESC_COUNTER(VCPU, host_state_reload), | |
281 | STATS_DESC_COUNTER(VCPU, fpu_reload), | |
282 | STATS_DESC_COUNTER(VCPU, insn_emulation), | |
283 | STATS_DESC_COUNTER(VCPU, insn_emulation_fail), | |
284 | STATS_DESC_COUNTER(VCPU, hypercalls), | |
285 | STATS_DESC_COUNTER(VCPU, irq_injections), | |
286 | STATS_DESC_COUNTER(VCPU, nmi_injections), | |
287 | STATS_DESC_COUNTER(VCPU, req_event), | |
288 | STATS_DESC_COUNTER(VCPU, nested_run), | |
289 | STATS_DESC_COUNTER(VCPU, directed_yield_attempted), | |
290 | STATS_DESC_COUNTER(VCPU, directed_yield_successful), | |
6cd88243 PB |
291 | STATS_DESC_COUNTER(VCPU, preemption_reported), |
292 | STATS_DESC_COUNTER(VCPU, preemption_other), | |
63f4b210 | 293 | STATS_DESC_IBOOLEAN(VCPU, guest_mode), |
2f4073e0 | 294 | STATS_DESC_COUNTER(VCPU, notify_window_exits), |
ce55c049 | 295 | }; |
ce55c049 JZ |
296 | |
297 | const struct kvm_stats_header kvm_vcpu_stats_header = { | |
298 | .name_size = KVM_STATS_NAME_SIZE, | |
299 | .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), | |
300 | .id_offset = sizeof(struct kvm_stats_header), | |
301 | .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, | |
302 | .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + | |
303 | sizeof(kvm_vcpu_stats_desc), | |
304 | }; | |
305 | ||
2acf923e DC |
306 | u64 __read_mostly host_xcr0; |
307 | ||
c9b8b07c SC |
308 | static struct kmem_cache *x86_emulator_cache; |
309 | ||
6abe9c13 PX |
310 | /* |
311 | * When called, it means the previous get/set msr reached an invalid msr. | |
cc4cb017 | 312 | * Return true if we want to ignore/silent this failed msr access. |
6abe9c13 | 313 | */ |
d632826f | 314 | static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write) |
6abe9c13 PX |
315 | { |
316 | const char *op = write ? "wrmsr" : "rdmsr"; | |
317 | ||
318 | if (ignore_msrs) { | |
319 | if (report_ignored_msrs) | |
d383b314 TI |
320 | kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n", |
321 | op, msr, data); | |
6abe9c13 | 322 | /* Mask the error */ |
cc4cb017 | 323 | return true; |
6abe9c13 | 324 | } else { |
d383b314 TI |
325 | kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n", |
326 | op, msr, data); | |
cc4cb017 | 327 | return false; |
6abe9c13 PX |
328 | } |
329 | } | |
330 | ||
c9b8b07c SC |
331 | static struct kmem_cache *kvm_alloc_emulator_cache(void) |
332 | { | |
06add254 SC |
333 | unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src); |
334 | unsigned int size = sizeof(struct x86_emulate_ctxt); | |
335 | ||
336 | return kmem_cache_create_usercopy("x86_emulator", size, | |
c9b8b07c | 337 | __alignof__(struct x86_emulate_ctxt), |
06add254 SC |
338 | SLAB_ACCOUNT, useroffset, |
339 | size - useroffset, NULL); | |
c9b8b07c SC |
340 | } |
341 | ||
b6785def | 342 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); |
d6aa1000 | 343 | |
af585b92 GN |
344 | static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) |
345 | { | |
346 | int i; | |
dd03bcaa | 347 | for (i = 0; i < ASYNC_PF_PER_VCPU; i++) |
af585b92 GN |
348 | vcpu->arch.apf.gfns[i] = ~0; |
349 | } | |
350 | ||
18863bdd AK |
351 | static void kvm_on_user_return(struct user_return_notifier *urn) |
352 | { | |
353 | unsigned slot; | |
7e34fbd0 SC |
354 | struct kvm_user_return_msrs *msrs |
355 | = container_of(urn, struct kvm_user_return_msrs, urn); | |
356 | struct kvm_user_return_msr_values *values; | |
1650b4eb IA |
357 | unsigned long flags; |
358 | ||
359 | /* | |
360 | * Disabling irqs at this point since the following code could be | |
361 | * interrupted and executed through kvm_arch_hardware_disable() | |
362 | */ | |
363 | local_irq_save(flags); | |
7e34fbd0 SC |
364 | if (msrs->registered) { |
365 | msrs->registered = false; | |
1650b4eb IA |
366 | user_return_notifier_unregister(urn); |
367 | } | |
368 | local_irq_restore(flags); | |
9cc39a5a | 369 | for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) { |
7e34fbd0 | 370 | values = &msrs->values[slot]; |
2bf78fa7 | 371 | if (values->host != values->curr) { |
9cc39a5a | 372 | wrmsrl(kvm_uret_msrs_list[slot], values->host); |
2bf78fa7 | 373 | values->curr = values->host; |
18863bdd AK |
374 | } |
375 | } | |
18863bdd AK |
376 | } |
377 | ||
e5fda4bb | 378 | static int kvm_probe_user_return_msr(u32 msr) |
5104d7ff SC |
379 | { |
380 | u64 val; | |
381 | int ret; | |
382 | ||
383 | preempt_disable(); | |
384 | ret = rdmsrl_safe(msr, &val); | |
385 | if (ret) | |
386 | goto out; | |
387 | ret = wrmsrl_safe(msr, val); | |
388 | out: | |
389 | preempt_enable(); | |
390 | return ret; | |
391 | } | |
5104d7ff | 392 | |
e5fda4bb | 393 | int kvm_add_user_return_msr(u32 msr) |
2bf78fa7 | 394 | { |
e5fda4bb SC |
395 | BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS); |
396 | ||
397 | if (kvm_probe_user_return_msr(msr)) | |
398 | return -1; | |
399 | ||
400 | kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr; | |
401 | return kvm_nr_uret_msrs++; | |
18863bdd | 402 | } |
e5fda4bb | 403 | EXPORT_SYMBOL_GPL(kvm_add_user_return_msr); |
18863bdd | 404 | |
8ea8b8d6 SC |
405 | int kvm_find_user_return_msr(u32 msr) |
406 | { | |
407 | int i; | |
408 | ||
9cc39a5a SC |
409 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
410 | if (kvm_uret_msrs_list[i] == msr) | |
8ea8b8d6 SC |
411 | return i; |
412 | } | |
413 | return -1; | |
414 | } | |
415 | EXPORT_SYMBOL_GPL(kvm_find_user_return_msr); | |
416 | ||
7e34fbd0 | 417 | static void kvm_user_return_msr_cpu_online(void) |
18863bdd | 418 | { |
05c19c2f | 419 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 420 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
05c19c2f SC |
421 | u64 value; |
422 | int i; | |
18863bdd | 423 | |
9cc39a5a SC |
424 | for (i = 0; i < kvm_nr_uret_msrs; ++i) { |
425 | rdmsrl_safe(kvm_uret_msrs_list[i], &value); | |
7e34fbd0 SC |
426 | msrs->values[i].host = value; |
427 | msrs->values[i].curr = value; | |
05c19c2f | 428 | } |
18863bdd AK |
429 | } |
430 | ||
7e34fbd0 | 431 | int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask) |
18863bdd | 432 | { |
013f6a5d | 433 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 434 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
8b3c3104 | 435 | int err; |
18863bdd | 436 | |
7e34fbd0 SC |
437 | value = (value & mask) | (msrs->values[slot].host & ~mask); |
438 | if (value == msrs->values[slot].curr) | |
8b3c3104 | 439 | return 0; |
9cc39a5a | 440 | err = wrmsrl_safe(kvm_uret_msrs_list[slot], value); |
8b3c3104 AH |
441 | if (err) |
442 | return 1; | |
443 | ||
7e34fbd0 SC |
444 | msrs->values[slot].curr = value; |
445 | if (!msrs->registered) { | |
446 | msrs->urn.on_user_return = kvm_on_user_return; | |
447 | user_return_notifier_register(&msrs->urn); | |
448 | msrs->registered = true; | |
18863bdd | 449 | } |
8b3c3104 | 450 | return 0; |
18863bdd | 451 | } |
7e34fbd0 | 452 | EXPORT_SYMBOL_GPL(kvm_set_user_return_msr); |
18863bdd | 453 | |
13a34e06 | 454 | static void drop_user_return_notifiers(void) |
3548bab5 | 455 | { |
013f6a5d | 456 | unsigned int cpu = smp_processor_id(); |
7e34fbd0 | 457 | struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu); |
3548bab5 | 458 | |
7e34fbd0 SC |
459 | if (msrs->registered) |
460 | kvm_on_user_return(&msrs->urn); | |
3548bab5 AK |
461 | } |
462 | ||
6866b83e CO |
463 | u64 kvm_get_apic_base(struct kvm_vcpu *vcpu) |
464 | { | |
8a5a87d9 | 465 | return vcpu->arch.apic_base; |
6866b83e CO |
466 | } |
467 | EXPORT_SYMBOL_GPL(kvm_get_apic_base); | |
468 | ||
58871649 JM |
469 | enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu) |
470 | { | |
471 | return kvm_apic_mode(kvm_get_apic_base(vcpu)); | |
472 | } | |
473 | EXPORT_SYMBOL_GPL(kvm_get_apic_mode); | |
474 | ||
58cb628d JK |
475 | int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
476 | { | |
58871649 JM |
477 | enum lapic_mode old_mode = kvm_get_apic_mode(vcpu); |
478 | enum lapic_mode new_mode = kvm_apic_mode(msr_info->data); | |
a8ac864a | 479 | u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff | |
d6321d49 | 480 | (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE); |
58cb628d | 481 | |
58871649 | 482 | if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID) |
58cb628d | 483 | return 1; |
58871649 JM |
484 | if (!msr_info->host_initiated) { |
485 | if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC) | |
486 | return 1; | |
487 | if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC) | |
488 | return 1; | |
489 | } | |
58cb628d JK |
490 | |
491 | kvm_lapic_set_base(vcpu, msr_info->data); | |
4abaffce | 492 | kvm_recalculate_apic_map(vcpu->kvm); |
58cb628d | 493 | return 0; |
6866b83e CO |
494 | } |
495 | EXPORT_SYMBOL_GPL(kvm_set_apic_base); | |
496 | ||
ad0577c3 SC |
497 | /* |
498 | * Handle a fault on a hardware virtualization (VMX or SVM) instruction. | |
499 | * | |
500 | * Hardware virtualization extension instructions may fault if a reboot turns | |
501 | * off virtualization while processes are running. Usually after catching the | |
502 | * fault we just panic; during reboot instead the instruction is ignored. | |
503 | */ | |
504 | noinstr void kvm_spurious_fault(void) | |
e3ba45b8 GL |
505 | { |
506 | /* Fault while not rebooting. We want the trace. */ | |
b4fdcf60 | 507 | BUG_ON(!kvm_rebooting); |
e3ba45b8 GL |
508 | } |
509 | EXPORT_SYMBOL_GPL(kvm_spurious_fault); | |
510 | ||
3fd28fce ED |
511 | #define EXCPT_BENIGN 0 |
512 | #define EXCPT_CONTRIBUTORY 1 | |
513 | #define EXCPT_PF 2 | |
514 | ||
515 | static int exception_class(int vector) | |
516 | { | |
517 | switch (vector) { | |
518 | case PF_VECTOR: | |
519 | return EXCPT_PF; | |
520 | case DE_VECTOR: | |
521 | case TS_VECTOR: | |
522 | case NP_VECTOR: | |
523 | case SS_VECTOR: | |
524 | case GP_VECTOR: | |
525 | return EXCPT_CONTRIBUTORY; | |
526 | default: | |
527 | break; | |
528 | } | |
529 | return EXCPT_BENIGN; | |
530 | } | |
531 | ||
d6e8c854 NA |
532 | #define EXCPT_FAULT 0 |
533 | #define EXCPT_TRAP 1 | |
534 | #define EXCPT_ABORT 2 | |
535 | #define EXCPT_INTERRUPT 3 | |
5623f751 | 536 | #define EXCPT_DB 4 |
d6e8c854 NA |
537 | |
538 | static int exception_type(int vector) | |
539 | { | |
540 | unsigned int mask; | |
541 | ||
542 | if (WARN_ON(vector > 31 || vector == NMI_VECTOR)) | |
543 | return EXCPT_INTERRUPT; | |
544 | ||
545 | mask = 1 << vector; | |
546 | ||
5623f751 SC |
547 | /* |
548 | * #DBs can be trap-like or fault-like, the caller must check other CPU | |
549 | * state, e.g. DR6, to determine whether a #DB is a trap or fault. | |
550 | */ | |
551 | if (mask & (1 << DB_VECTOR)) | |
552 | return EXCPT_DB; | |
553 | ||
554 | if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR))) | |
d6e8c854 NA |
555 | return EXCPT_TRAP; |
556 | ||
557 | if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR))) | |
558 | return EXCPT_ABORT; | |
559 | ||
560 | /* Reserved exceptions will result in fault */ | |
561 | return EXCPT_FAULT; | |
562 | } | |
563 | ||
da998b46 JM |
564 | void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu) |
565 | { | |
566 | unsigned nr = vcpu->arch.exception.nr; | |
567 | bool has_payload = vcpu->arch.exception.has_payload; | |
568 | unsigned long payload = vcpu->arch.exception.payload; | |
569 | ||
570 | if (!has_payload) | |
571 | return; | |
572 | ||
573 | switch (nr) { | |
f10c729f JM |
574 | case DB_VECTOR: |
575 | /* | |
576 | * "Certain debug exceptions may clear bit 0-3. The | |
577 | * remaining contents of the DR6 register are never | |
578 | * cleared by the processor". | |
579 | */ | |
580 | vcpu->arch.dr6 &= ~DR_TRAP_BITS; | |
581 | /* | |
9a3ecd5e CQ |
582 | * In order to reflect the #DB exception payload in guest |
583 | * dr6, three components need to be considered: active low | |
584 | * bit, FIXED_1 bits and active high bits (e.g. DR6_BD, | |
585 | * DR6_BS and DR6_BT) | |
586 | * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits. | |
587 | * In the target guest dr6: | |
588 | * FIXED_1 bits should always be set. | |
589 | * Active low bits should be cleared if 1-setting in payload. | |
590 | * Active high bits should be set if 1-setting in payload. | |
591 | * | |
592 | * Note, the payload is compatible with the pending debug | |
593 | * exceptions/exit qualification under VMX, that active_low bits | |
594 | * are active high in payload. | |
595 | * So they need to be flipped for DR6. | |
f10c729f | 596 | */ |
9a3ecd5e | 597 | vcpu->arch.dr6 |= DR6_ACTIVE_LOW; |
f10c729f | 598 | vcpu->arch.dr6 |= payload; |
9a3ecd5e | 599 | vcpu->arch.dr6 ^= payload & DR6_ACTIVE_LOW; |
307f1cfa OU |
600 | |
601 | /* | |
602 | * The #DB payload is defined as compatible with the 'pending | |
603 | * debug exceptions' field under VMX, not DR6. While bit 12 is | |
604 | * defined in the 'pending debug exceptions' field (enabled | |
605 | * breakpoint), it is reserved and must be zero in DR6. | |
606 | */ | |
607 | vcpu->arch.dr6 &= ~BIT(12); | |
f10c729f | 608 | break; |
da998b46 JM |
609 | case PF_VECTOR: |
610 | vcpu->arch.cr2 = payload; | |
611 | break; | |
612 | } | |
613 | ||
614 | vcpu->arch.exception.has_payload = false; | |
615 | vcpu->arch.exception.payload = 0; | |
616 | } | |
617 | EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload); | |
618 | ||
3fd28fce | 619 | static void kvm_multiple_exception(struct kvm_vcpu *vcpu, |
ce7ddec4 | 620 | unsigned nr, bool has_error, u32 error_code, |
91e86d22 | 621 | bool has_payload, unsigned long payload, bool reinject) |
3fd28fce ED |
622 | { |
623 | u32 prev_nr; | |
624 | int class1, class2; | |
625 | ||
3842d135 AK |
626 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
627 | ||
664f8e26 | 628 | if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) { |
3fd28fce | 629 | queue: |
664f8e26 WL |
630 | if (reinject) { |
631 | /* | |
632 | * On vmentry, vcpu->arch.exception.pending is only | |
633 | * true if an event injection was blocked by | |
634 | * nested_run_pending. In that case, however, | |
635 | * vcpu_enter_guest requests an immediate exit, | |
636 | * and the guest shouldn't proceed far enough to | |
637 | * need reinjection. | |
638 | */ | |
639 | WARN_ON_ONCE(vcpu->arch.exception.pending); | |
640 | vcpu->arch.exception.injected = true; | |
91e86d22 JM |
641 | if (WARN_ON_ONCE(has_payload)) { |
642 | /* | |
643 | * A reinjected event has already | |
644 | * delivered its payload. | |
645 | */ | |
646 | has_payload = false; | |
647 | payload = 0; | |
648 | } | |
664f8e26 WL |
649 | } else { |
650 | vcpu->arch.exception.pending = true; | |
651 | vcpu->arch.exception.injected = false; | |
652 | } | |
3fd28fce ED |
653 | vcpu->arch.exception.has_error_code = has_error; |
654 | vcpu->arch.exception.nr = nr; | |
655 | vcpu->arch.exception.error_code = error_code; | |
91e86d22 JM |
656 | vcpu->arch.exception.has_payload = has_payload; |
657 | vcpu->arch.exception.payload = payload; | |
a06230b6 | 658 | if (!is_guest_mode(vcpu)) |
da998b46 | 659 | kvm_deliver_exception_payload(vcpu); |
3fd28fce ED |
660 | return; |
661 | } | |
662 | ||
663 | /* to check exception */ | |
664 | prev_nr = vcpu->arch.exception.nr; | |
665 | if (prev_nr == DF_VECTOR) { | |
666 | /* triple fault -> shutdown */ | |
a8eeb04a | 667 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
3fd28fce ED |
668 | return; |
669 | } | |
670 | class1 = exception_class(prev_nr); | |
671 | class2 = exception_class(nr); | |
672 | if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) | |
673 | || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) { | |
664f8e26 WL |
674 | /* |
675 | * Generate double fault per SDM Table 5-5. Set | |
676 | * exception.pending = true so that the double fault | |
677 | * can trigger a nested vmexit. | |
678 | */ | |
3fd28fce | 679 | vcpu->arch.exception.pending = true; |
664f8e26 | 680 | vcpu->arch.exception.injected = false; |
3fd28fce ED |
681 | vcpu->arch.exception.has_error_code = true; |
682 | vcpu->arch.exception.nr = DF_VECTOR; | |
683 | vcpu->arch.exception.error_code = 0; | |
c851436a JM |
684 | vcpu->arch.exception.has_payload = false; |
685 | vcpu->arch.exception.payload = 0; | |
3fd28fce ED |
686 | } else |
687 | /* replace previous exception with a new one in a hope | |
688 | that instruction re-execution will regenerate lost | |
689 | exception */ | |
690 | goto queue; | |
691 | } | |
692 | ||
298101da AK |
693 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
694 | { | |
91e86d22 | 695 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false); |
298101da AK |
696 | } |
697 | EXPORT_SYMBOL_GPL(kvm_queue_exception); | |
698 | ||
ce7ddec4 JR |
699 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr) |
700 | { | |
91e86d22 | 701 | kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true); |
ce7ddec4 JR |
702 | } |
703 | EXPORT_SYMBOL_GPL(kvm_requeue_exception); | |
704 | ||
4d5523cf PB |
705 | void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, |
706 | unsigned long payload) | |
f10c729f JM |
707 | { |
708 | kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false); | |
709 | } | |
4d5523cf | 710 | EXPORT_SYMBOL_GPL(kvm_queue_exception_p); |
f10c729f | 711 | |
da998b46 JM |
712 | static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr, |
713 | u32 error_code, unsigned long payload) | |
714 | { | |
715 | kvm_multiple_exception(vcpu, nr, true, error_code, | |
716 | true, payload, false); | |
717 | } | |
718 | ||
6affcbed | 719 | int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err) |
c3c91fee | 720 | { |
db8fcefa AP |
721 | if (err) |
722 | kvm_inject_gp(vcpu, 0); | |
723 | else | |
6affcbed KH |
724 | return kvm_skip_emulated_instruction(vcpu); |
725 | ||
726 | return 1; | |
db8fcefa AP |
727 | } |
728 | EXPORT_SYMBOL_GPL(kvm_complete_insn_gp); | |
8df25a32 | 729 | |
d2f7d498 HW |
730 | static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err) |
731 | { | |
732 | if (err) { | |
733 | kvm_inject_gp(vcpu, 0); | |
734 | return 1; | |
735 | } | |
736 | ||
737 | return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP | | |
738 | EMULTYPE_COMPLETE_USER_EXIT); | |
739 | } | |
740 | ||
6389ee94 | 741 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault) |
c3c91fee AK |
742 | { |
743 | ++vcpu->stat.pf_guest; | |
adfe20fb WL |
744 | vcpu->arch.exception.nested_apf = |
745 | is_guest_mode(vcpu) && fault->async_page_fault; | |
da998b46 | 746 | if (vcpu->arch.exception.nested_apf) { |
adfe20fb | 747 | vcpu->arch.apf.nested_apf_token = fault->address; |
da998b46 JM |
748 | kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code); |
749 | } else { | |
750 | kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code, | |
751 | fault->address); | |
752 | } | |
c3c91fee | 753 | } |
27d6c865 | 754 | EXPORT_SYMBOL_GPL(kvm_inject_page_fault); |
c3c91fee | 755 | |
6819af75 | 756 | /* Returns true if the page fault was immediately morphed into a VM-Exit. */ |
53b3d8e9 SC |
757 | bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu, |
758 | struct x86_exception *fault) | |
d4f8cf66 | 759 | { |
0cd665bd | 760 | struct kvm_mmu *fault_mmu; |
53b3d8e9 SC |
761 | WARN_ON_ONCE(fault->vector != PF_VECTOR); |
762 | ||
0cd665bd PB |
763 | fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu : |
764 | vcpu->arch.walk_mmu; | |
ef54bcfe | 765 | |
ee1fa209 JS |
766 | /* |
767 | * Invalidate the TLB entry for the faulting address, if it exists, | |
768 | * else the access will fault indefinitely (and to emulate hardware). | |
769 | */ | |
770 | if ((fault->error_code & PFERR_PRESENT_MASK) && | |
771 | !(fault->error_code & PFERR_RSVD_MASK)) | |
772 | kvm_mmu_invalidate_gva(vcpu, fault_mmu, fault->address, | |
b9e5603c | 773 | fault_mmu->root.hpa); |
ee1fa209 | 774 | |
6819af75 SC |
775 | /* |
776 | * A workaround for KVM's bad exception handling. If KVM injected an | |
777 | * exception into L2, and L2 encountered a #PF while vectoring the | |
778 | * injected exception, manually check to see if L1 wants to intercept | |
779 | * #PF, otherwise queuing the #PF will lead to #DF or a lost exception. | |
780 | * In all other cases, defer the check to nested_ops->check_events(), | |
781 | * which will correctly handle priority (this does not). Note, other | |
782 | * exceptions, e.g. #GP, are theoretically affected, #PF is simply the | |
783 | * most problematic, e.g. when L0 and L1 are both intercepting #PF for | |
784 | * shadow paging. | |
785 | * | |
786 | * TODO: Rewrite exception handling to track injected and pending | |
787 | * (VM-Exit) exceptions separately. | |
788 | */ | |
789 | if (unlikely(vcpu->arch.exception.injected && is_guest_mode(vcpu)) && | |
790 | kvm_x86_ops.nested_ops->handle_page_fault_workaround(vcpu, fault)) | |
791 | return true; | |
792 | ||
ee1fa209 | 793 | fault_mmu->inject_page_fault(vcpu, fault); |
6819af75 | 794 | return false; |
d4f8cf66 | 795 | } |
53b3d8e9 | 796 | EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault); |
d4f8cf66 | 797 | |
3419ffc8 SY |
798 | void kvm_inject_nmi(struct kvm_vcpu *vcpu) |
799 | { | |
7460fb4a AK |
800 | atomic_inc(&vcpu->arch.nmi_queued); |
801 | kvm_make_request(KVM_REQ_NMI, vcpu); | |
3419ffc8 SY |
802 | } |
803 | EXPORT_SYMBOL_GPL(kvm_inject_nmi); | |
804 | ||
298101da AK |
805 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
806 | { | |
91e86d22 | 807 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false); |
298101da AK |
808 | } |
809 | EXPORT_SYMBOL_GPL(kvm_queue_exception_e); | |
810 | ||
ce7ddec4 JR |
811 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code) |
812 | { | |
91e86d22 | 813 | kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true); |
ce7ddec4 JR |
814 | } |
815 | EXPORT_SYMBOL_GPL(kvm_requeue_exception_e); | |
816 | ||
0a79b009 AK |
817 | /* |
818 | * Checks if cpl <= required_cpl; if true, return true. Otherwise queue | |
819 | * a #GP and return false. | |
820 | */ | |
821 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl) | |
298101da | 822 | { |
b3646477 | 823 | if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl) |
0a79b009 AK |
824 | return true; |
825 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
826 | return false; | |
298101da | 827 | } |
0a79b009 | 828 | EXPORT_SYMBOL_GPL(kvm_require_cpl); |
298101da | 829 | |
16f8a6f9 NA |
830 | bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr) |
831 | { | |
832 | if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE)) | |
833 | return true; | |
834 | ||
835 | kvm_queue_exception(vcpu, UD_VECTOR); | |
836 | return false; | |
837 | } | |
838 | EXPORT_SYMBOL_GPL(kvm_require_dr); | |
839 | ||
16cfacc8 SC |
840 | static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu) |
841 | { | |
5b7f575c | 842 | return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2); |
16cfacc8 SC |
843 | } |
844 | ||
a03490ed | 845 | /* |
16cfacc8 | 846 | * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise. |
a03490ed | 847 | */ |
2df4a5eb | 848 | int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 849 | { |
2df4a5eb | 850 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
a03490ed | 851 | gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT; |
15cabbc2 | 852 | gpa_t real_gpa; |
a03490ed CO |
853 | int i; |
854 | int ret; | |
ff03a073 | 855 | u64 pdpte[ARRAY_SIZE(mmu->pdptrs)]; |
a03490ed | 856 | |
15cabbc2 SC |
857 | /* |
858 | * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated | |
859 | * to an L1 GPA. | |
860 | */ | |
c59a0f57 LJ |
861 | real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn), |
862 | PFERR_USER_MASK | PFERR_WRITE_MASK, NULL); | |
6e1d2a3f | 863 | if (real_gpa == INVALID_GPA) |
15cabbc2 SC |
864 | return 0; |
865 | ||
94c641ba | 866 | /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */ |
15cabbc2 | 867 | ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte, |
94c641ba | 868 | cr3 & GENMASK(11, 5), sizeof(pdpte)); |
15cabbc2 SC |
869 | if (ret < 0) |
870 | return 0; | |
871 | ||
a03490ed | 872 | for (i = 0; i < ARRAY_SIZE(pdpte); ++i) { |
812f30b2 | 873 | if ((pdpte[i] & PT_PRESENT_MASK) && |
16cfacc8 | 874 | (pdpte[i] & pdptr_rsvd_bits(vcpu))) { |
15cabbc2 | 875 | return 0; |
a03490ed CO |
876 | } |
877 | } | |
a03490ed | 878 | |
6b123c3a LJ |
879 | /* |
880 | * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled. | |
881 | * Shadow page roots need to be reconstructed instead. | |
882 | */ | |
883 | if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs))) | |
0c1c92f1 | 884 | kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT); |
6b123c3a | 885 | |
46cbc040 PB |
886 | memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)); |
887 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); | |
888 | kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu); | |
158a48ec ML |
889 | vcpu->arch.pdptrs_from_userspace = false; |
890 | ||
15cabbc2 | 891 | return 1; |
a03490ed | 892 | } |
cc4b6871 | 893 | EXPORT_SYMBOL_GPL(load_pdptrs); |
a03490ed | 894 | |
f27ad38a TL |
895 | void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0) |
896 | { | |
f27ad38a TL |
897 | if ((cr0 ^ old_cr0) & X86_CR0_PG) { |
898 | kvm_clear_async_pf_completion_queue(vcpu); | |
899 | kvm_async_pf_hash_reset(vcpu); | |
b5f61c03 PB |
900 | |
901 | /* | |
902 | * Clearing CR0.PG is defined to flush the TLB from the guest's | |
903 | * perspective. | |
904 | */ | |
905 | if (!(cr0 & X86_CR0_PG)) | |
906 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
f27ad38a TL |
907 | } |
908 | ||
20f632bd | 909 | if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS) |
f27ad38a TL |
910 | kvm_mmu_reset_context(vcpu); |
911 | ||
912 | if (((cr0 ^ old_cr0) & X86_CR0_CD) && | |
913 | kvm_arch_has_noncoherent_dma(vcpu->kvm) && | |
914 | !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) | |
915 | kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL); | |
916 | } | |
917 | EXPORT_SYMBOL_GPL(kvm_post_set_cr0); | |
918 | ||
49a9b07e | 919 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
a03490ed | 920 | { |
aad82703 | 921 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
aad82703 | 922 | |
f9a48e6a AK |
923 | cr0 |= X86_CR0_ET; |
924 | ||
ab344828 | 925 | #ifdef CONFIG_X86_64 |
0f12244f GN |
926 | if (cr0 & 0xffffffff00000000UL) |
927 | return 1; | |
ab344828 GN |
928 | #endif |
929 | ||
930 | cr0 &= ~CR0_RESERVED_BITS; | |
a03490ed | 931 | |
0f12244f GN |
932 | if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) |
933 | return 1; | |
a03490ed | 934 | |
0f12244f GN |
935 | if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) |
936 | return 1; | |
a03490ed | 937 | |
a03490ed | 938 | #ifdef CONFIG_X86_64 |
05487215 SC |
939 | if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) && |
940 | (cr0 & X86_CR0_PG)) { | |
941 | int cs_db, cs_l; | |
942 | ||
943 | if (!is_pae(vcpu)) | |
944 | return 1; | |
b3646477 | 945 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
05487215 | 946 | if (cs_l) |
0f12244f | 947 | return 1; |
a03490ed | 948 | } |
05487215 SC |
949 | #endif |
950 | if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) && | |
e63f315d | 951 | is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) && |
2df4a5eb | 952 | !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) |
05487215 | 953 | return 1; |
a03490ed | 954 | |
777ab82d LJ |
955 | if (!(cr0 & X86_CR0_PG) && |
956 | (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))) | |
ad756a16 MJ |
957 | return 1; |
958 | ||
b3646477 | 959 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
a03490ed | 960 | |
f27ad38a | 961 | kvm_post_set_cr0(vcpu, old_cr0, cr0); |
b18d5431 | 962 | |
0f12244f GN |
963 | return 0; |
964 | } | |
2d3ad1f4 | 965 | EXPORT_SYMBOL_GPL(kvm_set_cr0); |
a03490ed | 966 | |
2d3ad1f4 | 967 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw) |
a03490ed | 968 | { |
49a9b07e | 969 | (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f)); |
a03490ed | 970 | } |
2d3ad1f4 | 971 | EXPORT_SYMBOL_GPL(kvm_lmsw); |
a03490ed | 972 | |
139a12cf | 973 | void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 974 | { |
16809ecd TL |
975 | if (vcpu->arch.guest_state_protected) |
976 | return; | |
977 | ||
139a12cf AL |
978 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
979 | ||
980 | if (vcpu->arch.xcr0 != host_xcr0) | |
981 | xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0); | |
982 | ||
983 | if (vcpu->arch.xsaves_enabled && | |
984 | vcpu->arch.ia32_xss != host_xss) | |
985 | wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss); | |
986 | } | |
37486135 | 987 | |
945024d7 | 988 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS |
37486135 | 989 | if (static_cpu_has(X86_FEATURE_PKU) && |
945024d7 JK |
990 | vcpu->arch.pkru != vcpu->arch.host_pkru && |
991 | ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || | |
992 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE))) | |
72a6c08c | 993 | write_pkru(vcpu->arch.pkru); |
945024d7 | 994 | #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ |
42bdf991 | 995 | } |
139a12cf | 996 | EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state); |
42bdf991 | 997 | |
139a12cf | 998 | void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu) |
42bdf991 | 999 | { |
16809ecd TL |
1000 | if (vcpu->arch.guest_state_protected) |
1001 | return; | |
1002 | ||
945024d7 | 1003 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS |
37486135 | 1004 | if (static_cpu_has(X86_FEATURE_PKU) && |
945024d7 JK |
1005 | ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) || |
1006 | kvm_read_cr4_bits(vcpu, X86_CR4_PKE))) { | |
37486135 BM |
1007 | vcpu->arch.pkru = rdpkru(); |
1008 | if (vcpu->arch.pkru != vcpu->arch.host_pkru) | |
72a6c08c | 1009 | write_pkru(vcpu->arch.host_pkru); |
37486135 | 1010 | } |
945024d7 | 1011 | #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ |
37486135 | 1012 | |
139a12cf AL |
1013 | if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) { |
1014 | ||
1015 | if (vcpu->arch.xcr0 != host_xcr0) | |
1016 | xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0); | |
1017 | ||
1018 | if (vcpu->arch.xsaves_enabled && | |
1019 | vcpu->arch.ia32_xss != host_xss) | |
1020 | wrmsrl(MSR_IA32_XSS, host_xss); | |
1021 | } | |
1022 | ||
42bdf991 | 1023 | } |
139a12cf | 1024 | EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state); |
42bdf991 | 1025 | |
988896bb LB |
1026 | static inline u64 kvm_guest_supported_xcr0(struct kvm_vcpu *vcpu) |
1027 | { | |
1028 | return vcpu->arch.guest_fpu.fpstate->user_xfeatures; | |
1029 | } | |
1030 | ||
ba1f77c5 | 1031 | #ifdef CONFIG_X86_64 |
988896bb LB |
1032 | static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu) |
1033 | { | |
1034 | return kvm_guest_supported_xcr0(vcpu) & XFEATURE_MASK_USER_DYNAMIC; | |
1035 | } | |
ba1f77c5 | 1036 | #endif |
988896bb | 1037 | |
69b0049a | 1038 | static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) |
2acf923e | 1039 | { |
56c103ec LJ |
1040 | u64 xcr0 = xcr; |
1041 | u64 old_xcr0 = vcpu->arch.xcr0; | |
46c34cb0 | 1042 | u64 valid_bits; |
2acf923e DC |
1043 | |
1044 | /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */ | |
1045 | if (index != XCR_XFEATURE_ENABLED_MASK) | |
1046 | return 1; | |
d91cab78 | 1047 | if (!(xcr0 & XFEATURE_MASK_FP)) |
2acf923e | 1048 | return 1; |
d91cab78 | 1049 | if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE)) |
2acf923e | 1050 | return 1; |
46c34cb0 PB |
1051 | |
1052 | /* | |
1053 | * Do not allow the guest to set bits that we do not support | |
1054 | * saving. However, xcr0 bit 0 is always set, even if the | |
e8f65b9b | 1055 | * emulated CPU does not support XSAVE (see kvm_vcpu_reset()). |
46c34cb0 | 1056 | */ |
988896bb | 1057 | valid_bits = kvm_guest_supported_xcr0(vcpu) | XFEATURE_MASK_FP; |
46c34cb0 | 1058 | if (xcr0 & ~valid_bits) |
2acf923e | 1059 | return 1; |
46c34cb0 | 1060 | |
d91cab78 DH |
1061 | if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) != |
1062 | (!(xcr0 & XFEATURE_MASK_BNDCSR))) | |
390bd528 LJ |
1063 | return 1; |
1064 | ||
d91cab78 DH |
1065 | if (xcr0 & XFEATURE_MASK_AVX512) { |
1066 | if (!(xcr0 & XFEATURE_MASK_YMM)) | |
612263b3 | 1067 | return 1; |
d91cab78 | 1068 | if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512) |
612263b3 CP |
1069 | return 1; |
1070 | } | |
86aff7a4 JL |
1071 | |
1072 | if ((xcr0 & XFEATURE_MASK_XTILE) && | |
1073 | ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE)) | |
1074 | return 1; | |
1075 | ||
2acf923e | 1076 | vcpu->arch.xcr0 = xcr0; |
56c103ec | 1077 | |
d91cab78 | 1078 | if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND) |
aedbaf4f | 1079 | kvm_update_cpuid_runtime(vcpu); |
2acf923e DC |
1080 | return 0; |
1081 | } | |
1082 | ||
92f9895c | 1083 | int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu) |
2acf923e | 1084 | { |
92f9895c SC |
1085 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0 || |
1086 | __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) { | |
1087 | kvm_inject_gp(vcpu, 0); | |
1088 | return 1; | |
1089 | } | |
bbefd4fc | 1090 | |
92f9895c | 1091 | return kvm_skip_emulated_instruction(vcpu); |
2acf923e | 1092 | } |
92f9895c | 1093 | EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv); |
2acf923e | 1094 | |
c33f6f22 | 1095 | bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) |
a03490ed | 1096 | { |
b11306b5 | 1097 | if (cr4 & cr4_reserved_bits) |
ee69c92b | 1098 | return false; |
b9baba86 | 1099 | |
b899c132 | 1100 | if (cr4 & vcpu->arch.cr4_guest_rsvd_bits) |
ee69c92b | 1101 | return false; |
3ca94192 | 1102 | |
c33f6f22 SC |
1103 | return true; |
1104 | } | |
1105 | EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4); | |
1106 | ||
1107 | static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1108 | { | |
1109 | return __kvm_is_valid_cr4(vcpu, cr4) && | |
1110 | static_call(kvm_x86_is_valid_cr4)(vcpu, cr4); | |
3ca94192 WL |
1111 | } |
1112 | ||
5b51cb13 TL |
1113 | void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4) |
1114 | { | |
b5f61c03 PB |
1115 | if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) |
1116 | kvm_mmu_reset_context(vcpu); | |
1117 | ||
509bfe3d | 1118 | /* |
509bfe3d LJ |
1119 | * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB |
1120 | * according to the SDM; however, stale prev_roots could be reused | |
1121 | * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we | |
b5f61c03 PB |
1122 | * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST |
1123 | * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed, | |
1124 | * so fall through. | |
509bfe3d | 1125 | */ |
b5f61c03 PB |
1126 | if (!tdp_enabled && |
1127 | (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) | |
f6d0a252 | 1128 | kvm_mmu_unload(vcpu); |
b5f61c03 PB |
1129 | |
1130 | /* | |
1131 | * The TLB has to be flushed for all PCIDs if any of the following | |
1132 | * (architecturally required) changes happen: | |
1133 | * - CR4.PCIDE is changed from 1 to 0 | |
1134 | * - CR4.PGE is toggled | |
509bfe3d | 1135 | * |
b5f61c03 | 1136 | * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT. |
509bfe3d | 1137 | */ |
b5f61c03 PB |
1138 | if (((cr4 ^ old_cr4) & X86_CR4_PGE) || |
1139 | (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))) | |
55261738 | 1140 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); |
b5f61c03 PB |
1141 | |
1142 | /* | |
1143 | * The TLB has to be flushed for the current PCID if any of the | |
1144 | * following (architecturally required) changes happen: | |
1145 | * - CR4.SMEP is changed from 0 to 1 | |
1146 | * - CR4.PAE is toggled | |
1147 | */ | |
1148 | else if (((cr4 ^ old_cr4) & X86_CR4_PAE) || | |
1149 | ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP))) | |
1150 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
1151 | ||
3ca94192 | 1152 | } |
5b51cb13 | 1153 | EXPORT_SYMBOL_GPL(kvm_post_set_cr4); |
3ca94192 WL |
1154 | |
1155 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1156 | { | |
1157 | unsigned long old_cr4 = kvm_read_cr4(vcpu); | |
3ca94192 | 1158 | |
ee69c92b | 1159 | if (!kvm_is_valid_cr4(vcpu, cr4)) |
ae3e61e1 PB |
1160 | return 1; |
1161 | ||
a03490ed | 1162 | if (is_long_mode(vcpu)) { |
0f12244f GN |
1163 | if (!(cr4 & X86_CR4_PAE)) |
1164 | return 1; | |
d74fcfc1 SC |
1165 | if ((cr4 ^ old_cr4) & X86_CR4_LA57) |
1166 | return 1; | |
a2edf57f | 1167 | } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE) |
a37ebdce | 1168 | && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS) |
2df4a5eb | 1169 | && !load_pdptrs(vcpu, kvm_read_cr3(vcpu))) |
0f12244f GN |
1170 | return 1; |
1171 | ||
ad756a16 | 1172 | if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) { |
d6321d49 | 1173 | if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID)) |
ad756a16 MJ |
1174 | return 1; |
1175 | ||
1176 | /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */ | |
1177 | if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu)) | |
1178 | return 1; | |
1179 | } | |
1180 | ||
b3646477 | 1181 | static_call(kvm_x86_set_cr4)(vcpu, cr4); |
a03490ed | 1182 | |
5b51cb13 | 1183 | kvm_post_set_cr4(vcpu, old_cr4, cr4); |
2acf923e | 1184 | |
0f12244f GN |
1185 | return 0; |
1186 | } | |
2d3ad1f4 | 1187 | EXPORT_SYMBOL_GPL(kvm_set_cr4); |
a03490ed | 1188 | |
21823fbd SC |
1189 | static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid) |
1190 | { | |
1191 | struct kvm_mmu *mmu = vcpu->arch.mmu; | |
1192 | unsigned long roots_to_free = 0; | |
1193 | int i; | |
1194 | ||
e45e9e39 LJ |
1195 | /* |
1196 | * MOV CR3 and INVPCID are usually not intercepted when using TDP, but | |
1197 | * this is reachable when running EPT=1 and unrestricted_guest=0, and | |
1198 | * also via the emulator. KVM's TDP page tables are not in the scope of | |
1199 | * the invalidation, but the guest's TLB entries need to be flushed as | |
1200 | * the CPU may have cached entries in its TLB for the target PCID. | |
1201 | */ | |
1202 | if (unlikely(tdp_enabled)) { | |
1203 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
1204 | return; | |
1205 | } | |
1206 | ||
21823fbd SC |
1207 | /* |
1208 | * If neither the current CR3 nor any of the prev_roots use the given | |
1209 | * PCID, then nothing needs to be done here because a resync will | |
1210 | * happen anyway before switching to any other CR3. | |
1211 | */ | |
1212 | if (kvm_get_active_pcid(vcpu) == pcid) { | |
e62f1aa8 | 1213 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
21823fbd SC |
1214 | kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); |
1215 | } | |
1216 | ||
509bfe3d LJ |
1217 | /* |
1218 | * If PCID is disabled, there is no need to free prev_roots even if the | |
1219 | * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB | |
1220 | * with PCIDE=0. | |
1221 | */ | |
1222 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) | |
1223 | return; | |
1224 | ||
21823fbd SC |
1225 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
1226 | if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid) | |
1227 | roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); | |
1228 | ||
0c1c92f1 | 1229 | kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free); |
21823fbd SC |
1230 | } |
1231 | ||
2390218b | 1232 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
a03490ed | 1233 | { |
ade61e28 | 1234 | bool skip_tlb_flush = false; |
21823fbd | 1235 | unsigned long pcid = 0; |
ac146235 | 1236 | #ifdef CONFIG_X86_64 |
c19986fe JS |
1237 | bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); |
1238 | ||
ade61e28 | 1239 | if (pcid_enabled) { |
208320ba JS |
1240 | skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH; |
1241 | cr3 &= ~X86_CR3_PCID_NOFLUSH; | |
21823fbd | 1242 | pcid = cr3 & X86_CR3_PCID_MASK; |
ade61e28 | 1243 | } |
ac146235 | 1244 | #endif |
9d88fca7 | 1245 | |
c7313155 | 1246 | /* PDPTRs are always reloaded for PAE paging. */ |
21823fbd SC |
1247 | if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu)) |
1248 | goto handle_tlb_flush; | |
d835dfec | 1249 | |
886bbcc7 SC |
1250 | /* |
1251 | * Do not condition the GPA check on long mode, this helper is used to | |
1252 | * stuff CR3, e.g. for RSM emulation, and there is no guarantee that | |
1253 | * the current vCPU mode is accurate. | |
1254 | */ | |
1255 | if (kvm_vcpu_is_illegal_gpa(vcpu, cr3)) | |
d1cd3ce9 | 1256 | return 1; |
886bbcc7 | 1257 | |
2df4a5eb | 1258 | if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3)) |
346874c9 | 1259 | return 1; |
a03490ed | 1260 | |
21823fbd | 1261 | if (cr3 != kvm_read_cr3(vcpu)) |
b5129100 | 1262 | kvm_mmu_new_pgd(vcpu, cr3); |
21823fbd | 1263 | |
0f12244f | 1264 | vcpu->arch.cr3 = cr3; |
3883bc9d | 1265 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); |
405329fc | 1266 | /* Do not call post_set_cr3, we do not get here for confidential guests. */ |
7c390d35 | 1267 | |
21823fbd SC |
1268 | handle_tlb_flush: |
1269 | /* | |
1270 | * A load of CR3 that flushes the TLB flushes only the current PCID, | |
1271 | * even if PCID is disabled, in which case PCID=0 is flushed. It's a | |
1272 | * moot point in the end because _disabling_ PCID will flush all PCIDs, | |
1273 | * and it's impossible to use a non-zero PCID when PCID is disabled, | |
1274 | * i.e. only PCID=0 can be relevant. | |
1275 | */ | |
1276 | if (!skip_tlb_flush) | |
1277 | kvm_invalidate_pcid(vcpu, pcid); | |
1278 | ||
0f12244f GN |
1279 | return 0; |
1280 | } | |
2d3ad1f4 | 1281 | EXPORT_SYMBOL_GPL(kvm_set_cr3); |
a03490ed | 1282 | |
eea1cff9 | 1283 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8) |
a03490ed | 1284 | { |
0f12244f GN |
1285 | if (cr8 & CR8_RESERVED_BITS) |
1286 | return 1; | |
35754c98 | 1287 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1288 | kvm_lapic_set_tpr(vcpu, cr8); |
1289 | else | |
ad312c7c | 1290 | vcpu->arch.cr8 = cr8; |
0f12244f GN |
1291 | return 0; |
1292 | } | |
2d3ad1f4 | 1293 | EXPORT_SYMBOL_GPL(kvm_set_cr8); |
a03490ed | 1294 | |
2d3ad1f4 | 1295 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu) |
a03490ed | 1296 | { |
35754c98 | 1297 | if (lapic_in_kernel(vcpu)) |
a03490ed CO |
1298 | return kvm_lapic_get_cr8(vcpu); |
1299 | else | |
ad312c7c | 1300 | return vcpu->arch.cr8; |
a03490ed | 1301 | } |
2d3ad1f4 | 1302 | EXPORT_SYMBOL_GPL(kvm_get_cr8); |
a03490ed | 1303 | |
ae561ede NA |
1304 | static void kvm_update_dr0123(struct kvm_vcpu *vcpu) |
1305 | { | |
1306 | int i; | |
1307 | ||
1308 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) { | |
1309 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
1310 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae561ede NA |
1311 | } |
1312 | } | |
1313 | ||
7c86663b | 1314 | void kvm_update_dr7(struct kvm_vcpu *vcpu) |
c8639010 JK |
1315 | { |
1316 | unsigned long dr7; | |
1317 | ||
1318 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) | |
1319 | dr7 = vcpu->arch.guest_debug_dr7; | |
1320 | else | |
1321 | dr7 = vcpu->arch.dr7; | |
b3646477 | 1322 | static_call(kvm_x86_set_dr7)(vcpu, dr7); |
360b948d PB |
1323 | vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED; |
1324 | if (dr7 & DR7_BP_EN_MASK) | |
1325 | vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED; | |
c8639010 | 1326 | } |
7c86663b | 1327 | EXPORT_SYMBOL_GPL(kvm_update_dr7); |
c8639010 | 1328 | |
6f43ed01 NA |
1329 | static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu) |
1330 | { | |
1331 | u64 fixed = DR6_FIXED_1; | |
1332 | ||
d6321d49 | 1333 | if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM)) |
6f43ed01 | 1334 | fixed |= DR6_RTM; |
e8ea85fb CQ |
1335 | |
1336 | if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT)) | |
1337 | fixed |= DR6_BUS_LOCK; | |
6f43ed01 NA |
1338 | return fixed; |
1339 | } | |
1340 | ||
996ff542 | 1341 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val) |
020df079 | 1342 | { |
ea740059 MP |
1343 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1344 | ||
020df079 GN |
1345 | switch (dr) { |
1346 | case 0 ... 3: | |
ea740059 | 1347 | vcpu->arch.db[array_index_nospec(dr, size)] = val; |
020df079 GN |
1348 | if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) |
1349 | vcpu->arch.eff_db[dr] = val; | |
1350 | break; | |
1351 | case 4: | |
020df079 | 1352 | case 6: |
f5f6145e | 1353 | if (!kvm_dr6_valid(val)) |
996ff542 | 1354 | return 1; /* #GP */ |
6f43ed01 | 1355 | vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu); |
020df079 GN |
1356 | break; |
1357 | case 5: | |
020df079 | 1358 | default: /* 7 */ |
b91991bf | 1359 | if (!kvm_dr7_valid(val)) |
996ff542 | 1360 | return 1; /* #GP */ |
020df079 | 1361 | vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1; |
c8639010 | 1362 | kvm_update_dr7(vcpu); |
020df079 GN |
1363 | break; |
1364 | } | |
1365 | ||
1366 | return 0; | |
1367 | } | |
1368 | EXPORT_SYMBOL_GPL(kvm_set_dr); | |
1369 | ||
29d6ca41 | 1370 | void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val) |
020df079 | 1371 | { |
ea740059 MP |
1372 | size_t size = ARRAY_SIZE(vcpu->arch.db); |
1373 | ||
020df079 GN |
1374 | switch (dr) { |
1375 | case 0 ... 3: | |
ea740059 | 1376 | *val = vcpu->arch.db[array_index_nospec(dr, size)]; |
020df079 GN |
1377 | break; |
1378 | case 4: | |
020df079 | 1379 | case 6: |
5679b803 | 1380 | *val = vcpu->arch.dr6; |
020df079 GN |
1381 | break; |
1382 | case 5: | |
020df079 GN |
1383 | default: /* 7 */ |
1384 | *val = vcpu->arch.dr7; | |
1385 | break; | |
1386 | } | |
338dbc97 | 1387 | } |
020df079 GN |
1388 | EXPORT_SYMBOL_GPL(kvm_get_dr); |
1389 | ||
c483c454 | 1390 | int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu) |
022cd0e8 | 1391 | { |
de3cd117 | 1392 | u32 ecx = kvm_rcx_read(vcpu); |
022cd0e8 | 1393 | u64 data; |
022cd0e8 | 1394 | |
c483c454 SC |
1395 | if (kvm_pmu_rdpmc(vcpu, ecx, &data)) { |
1396 | kvm_inject_gp(vcpu, 0); | |
1397 | return 1; | |
1398 | } | |
1399 | ||
de3cd117 SC |
1400 | kvm_rax_write(vcpu, (u32)data); |
1401 | kvm_rdx_write(vcpu, data >> 32); | |
c483c454 | 1402 | return kvm_skip_emulated_instruction(vcpu); |
022cd0e8 | 1403 | } |
c483c454 | 1404 | EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc); |
022cd0e8 | 1405 | |
043405e1 CO |
1406 | /* |
1407 | * List of msr numbers which we expose to userspace through KVM_GET_MSRS | |
1408 | * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. | |
1409 | * | |
7a5ee6ed CQ |
1410 | * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) |
1411 | * extract the supported MSRs from the related const lists. | |
1412 | * msrs_to_save is selected from the msrs_to_save_all to reflect the | |
e3267cbb | 1413 | * capabilities of the host cpu. This capabilities test skips MSRs that are |
7a5ee6ed | 1414 | * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs |
62ef68bb | 1415 | * may depend on host virtualization features rather than host cpu features. |
043405e1 | 1416 | */ |
e3267cbb | 1417 | |
7a5ee6ed | 1418 | static const u32 msrs_to_save_all[] = { |
043405e1 | 1419 | MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, |
8c06585d | 1420 | MSR_STAR, |
043405e1 CO |
1421 | #ifdef CONFIG_X86_64 |
1422 | MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR, | |
1423 | #endif | |
b3897a49 | 1424 | MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA, |
32ad73db | 1425 | MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX, |
2bdb76c0 | 1426 | MSR_IA32_SPEC_CTRL, |
bf8c55d8 CP |
1427 | MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH, |
1428 | MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK, | |
1429 | MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B, | |
1430 | MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B, | |
1431 | MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B, | |
1432 | MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B, | |
6e3ba4ab TX |
1433 | MSR_IA32_UMWAIT_CONTROL, |
1434 | ||
e2ada66e | 1435 | MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, |
9fb12fe5 | 1436 | MSR_ARCH_PERFMON_FIXED_CTR0 + 2, |
e2ada66e JM |
1437 | MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, |
1438 | MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
1439 | MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1, | |
1440 | MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3, | |
1441 | MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5, | |
1442 | MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7, | |
1443 | MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9, | |
1444 | MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11, | |
1445 | MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13, | |
1446 | MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15, | |
1447 | MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17, | |
e2ada66e JM |
1448 | MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1, |
1449 | MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3, | |
1450 | MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5, | |
1451 | MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7, | |
1452 | MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9, | |
1453 | MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11, | |
1454 | MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13, | |
1455 | MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15, | |
1456 | MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17, | |
902caeb6 | 1457 | MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, |
e1fc1553 FM |
1458 | |
1459 | MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3, | |
1460 | MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3, | |
1461 | MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2, | |
1462 | MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, | |
1463 | MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, | |
1464 | MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, | |
548e8365 | 1465 | MSR_IA32_XFD, MSR_IA32_XFD_ERR, |
043405e1 CO |
1466 | }; |
1467 | ||
7a5ee6ed | 1468 | static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)]; |
043405e1 CO |
1469 | static unsigned num_msrs_to_save; |
1470 | ||
7a5ee6ed | 1471 | static const u32 emulated_msrs_all[] = { |
62ef68bb PB |
1472 | MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK, |
1473 | MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW, | |
1474 | HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL, | |
1475 | HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC, | |
72c139ba | 1476 | HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY, |
e7d9513b AS |
1477 | HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2, |
1478 | HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL, | |
e516cebb | 1479 | HV_X64_MSR_RESET, |
11c4b1ca | 1480 | HV_X64_MSR_VP_INDEX, |
9eec50b8 | 1481 | HV_X64_MSR_VP_RUNTIME, |
5c919412 | 1482 | HV_X64_MSR_SCONTROL, |
1f4b34f8 | 1483 | HV_X64_MSR_STIMER0_CONFIG, |
d4abc577 | 1484 | HV_X64_MSR_VP_ASSIST_PAGE, |
a2e164e7 VK |
1485 | HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL, |
1486 | HV_X64_MSR_TSC_EMULATION_STATUS, | |
f97f5a56 JD |
1487 | HV_X64_MSR_SYNDBG_OPTIONS, |
1488 | HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS, | |
1489 | HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER, | |
1490 | HV_X64_MSR_SYNDBG_PENDING_BUFFER, | |
a2e164e7 VK |
1491 | |
1492 | MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME, | |
557a961a | 1493 | MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK, |
62ef68bb | 1494 | |
ba904635 | 1495 | MSR_IA32_TSC_ADJUST, |
09141ec0 | 1496 | MSR_IA32_TSC_DEADLINE, |
2bdb76c0 | 1497 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1498 | MSR_IA32_PERF_CAPABILITIES, |
043405e1 | 1499 | MSR_IA32_MISC_ENABLE, |
908e75f3 AK |
1500 | MSR_IA32_MCG_STATUS, |
1501 | MSR_IA32_MCG_CTL, | |
c45dcc71 | 1502 | MSR_IA32_MCG_EXT_CTL, |
64d60670 | 1503 | MSR_IA32_SMBASE, |
52797bf9 | 1504 | MSR_SMI_COUNT, |
db2336a8 KH |
1505 | MSR_PLATFORM_INFO, |
1506 | MSR_MISC_FEATURES_ENABLES, | |
bc226f07 | 1507 | MSR_AMD64_VIRT_SPEC_CTRL, |
5228eb96 | 1508 | MSR_AMD64_TSC_RATIO, |
6c6a2ab9 | 1509 | MSR_IA32_POWER_CTL, |
99634e3e | 1510 | MSR_IA32_UCODE_REV, |
191c8137 | 1511 | |
95c5c7c7 PB |
1512 | /* |
1513 | * The following list leaves out MSRs whose values are determined | |
1514 | * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs. | |
1515 | * We always support the "true" VMX control MSRs, even if the host | |
1516 | * processor does not, so I am putting these registers here rather | |
7a5ee6ed | 1517 | * than in msrs_to_save_all. |
95c5c7c7 PB |
1518 | */ |
1519 | MSR_IA32_VMX_BASIC, | |
1520 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1521 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1522 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1523 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1524 | MSR_IA32_VMX_MISC, | |
1525 | MSR_IA32_VMX_CR0_FIXED0, | |
1526 | MSR_IA32_VMX_CR4_FIXED0, | |
1527 | MSR_IA32_VMX_VMCS_ENUM, | |
1528 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1529 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1530 | MSR_IA32_VMX_VMFUNC, | |
1531 | ||
191c8137 | 1532 | MSR_K7_HWCR, |
2d5ba19b | 1533 | MSR_KVM_POLL_CONTROL, |
043405e1 CO |
1534 | }; |
1535 | ||
7a5ee6ed | 1536 | static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)]; |
62ef68bb PB |
1537 | static unsigned num_emulated_msrs; |
1538 | ||
801e459a TL |
1539 | /* |
1540 | * List of msr numbers which are used to expose MSR-based features that | |
1541 | * can be used by a hypervisor to validate requested CPU features. | |
1542 | */ | |
7a5ee6ed | 1543 | static const u32 msr_based_features_all[] = { |
1389309c PB |
1544 | MSR_IA32_VMX_BASIC, |
1545 | MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
1546 | MSR_IA32_VMX_PINBASED_CTLS, | |
1547 | MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
1548 | MSR_IA32_VMX_PROCBASED_CTLS, | |
1549 | MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
1550 | MSR_IA32_VMX_EXIT_CTLS, | |
1551 | MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
1552 | MSR_IA32_VMX_ENTRY_CTLS, | |
1553 | MSR_IA32_VMX_MISC, | |
1554 | MSR_IA32_VMX_CR0_FIXED0, | |
1555 | MSR_IA32_VMX_CR0_FIXED1, | |
1556 | MSR_IA32_VMX_CR4_FIXED0, | |
1557 | MSR_IA32_VMX_CR4_FIXED1, | |
1558 | MSR_IA32_VMX_VMCS_ENUM, | |
1559 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
1560 | MSR_IA32_VMX_EPT_VPID_CAP, | |
1561 | MSR_IA32_VMX_VMFUNC, | |
1562 | ||
d1d93fa9 | 1563 | MSR_F10H_DECFG, |
518e7b94 | 1564 | MSR_IA32_UCODE_REV, |
cd283252 | 1565 | MSR_IA32_ARCH_CAPABILITIES, |
27461da3 | 1566 | MSR_IA32_PERF_CAPABILITIES, |
801e459a TL |
1567 | }; |
1568 | ||
7a5ee6ed | 1569 | static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)]; |
801e459a TL |
1570 | static unsigned int num_msr_based_features; |
1571 | ||
4d22c17c | 1572 | static u64 kvm_get_arch_capabilities(void) |
5b76a3cf | 1573 | { |
4d22c17c | 1574 | u64 data = 0; |
5b76a3cf | 1575 | |
4d22c17c XL |
1576 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1577 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data); | |
5b76a3cf | 1578 | |
b8e8c830 PB |
1579 | /* |
1580 | * If nx_huge_pages is enabled, KVM's shadow paging will ensure that | |
1581 | * the nested hypervisor runs with NX huge pages. If it is not, | |
d9f6e12f | 1582 | * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other |
b8e8c830 PB |
1583 | * L1 guests, so it need not worry about its own (L2) guests. |
1584 | */ | |
1585 | data |= ARCH_CAP_PSCHANGE_MC_NO; | |
1586 | ||
5b76a3cf PB |
1587 | /* |
1588 | * If we're doing cache flushes (either "always" or "cond") | |
1589 | * we will do one whenever the guest does a vmlaunch/vmresume. | |
1590 | * If an outer hypervisor is doing the cache flush for us | |
1591 | * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that | |
1592 | * capability to the guest too, and if EPT is disabled we're not | |
1593 | * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will | |
1594 | * require a nested hypervisor to do a flush of its own. | |
1595 | */ | |
1596 | if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER) | |
1597 | data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH; | |
1598 | ||
0c54914d PB |
1599 | if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN)) |
1600 | data |= ARCH_CAP_RDCL_NO; | |
1601 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1602 | data |= ARCH_CAP_SSB_NO; | |
1603 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
1604 | data |= ARCH_CAP_MDS_NO; | |
1605 | ||
7131636e PB |
1606 | if (!boot_cpu_has(X86_FEATURE_RTM)) { |
1607 | /* | |
1608 | * If RTM=0 because the kernel has disabled TSX, the host might | |
1609 | * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0 | |
1610 | * and therefore knows that there cannot be TAA) but keep | |
1611 | * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts, | |
1612 | * and we want to allow migrating those guests to tsx=off hosts. | |
1613 | */ | |
1614 | data &= ~ARCH_CAP_TAA_NO; | |
1615 | } else if (!boot_cpu_has_bug(X86_BUG_TAA)) { | |
cbbaa272 | 1616 | data |= ARCH_CAP_TAA_NO; |
7131636e PB |
1617 | } else { |
1618 | /* | |
1619 | * Nothing to do here; we emulate TSX_CTRL if present on the | |
1620 | * host so the guest can choose between disabling TSX or | |
1621 | * using VERW to clear CPU buffers. | |
1622 | */ | |
1623 | } | |
e1d38b63 | 1624 | |
027bbb88 PG |
1625 | /* Guests don't need to know "Fill buffer clear control" exists */ |
1626 | data &= ~ARCH_CAP_FB_CLEAR_CTRL; | |
1627 | ||
5b76a3cf PB |
1628 | return data; |
1629 | } | |
5b76a3cf | 1630 | |
66421c1e WL |
1631 | static int kvm_get_msr_feature(struct kvm_msr_entry *msr) |
1632 | { | |
1633 | switch (msr->index) { | |
cd283252 | 1634 | case MSR_IA32_ARCH_CAPABILITIES: |
5b76a3cf PB |
1635 | msr->data = kvm_get_arch_capabilities(); |
1636 | break; | |
1637 | case MSR_IA32_UCODE_REV: | |
cd283252 | 1638 | rdmsrl_safe(msr->index, &msr->data); |
518e7b94 | 1639 | break; |
66421c1e | 1640 | default: |
b3646477 | 1641 | return static_call(kvm_x86_get_msr_feature)(msr); |
66421c1e WL |
1642 | } |
1643 | return 0; | |
1644 | } | |
1645 | ||
801e459a TL |
1646 | static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) |
1647 | { | |
1648 | struct kvm_msr_entry msr; | |
66421c1e | 1649 | int r; |
801e459a TL |
1650 | |
1651 | msr.index = index; | |
66421c1e | 1652 | r = kvm_get_msr_feature(&msr); |
12bc2132 PX |
1653 | |
1654 | if (r == KVM_MSR_RET_INVALID) { | |
1655 | /* Unconditionally clear the output for simplicity */ | |
1656 | *data = 0; | |
d632826f | 1657 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1658 | r = 0; |
12bc2132 PX |
1659 | } |
1660 | ||
66421c1e WL |
1661 | if (r) |
1662 | return r; | |
801e459a TL |
1663 | |
1664 | *data = msr.data; | |
1665 | ||
1666 | return 0; | |
1667 | } | |
1668 | ||
11988499 | 1669 | static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) |
15c4a640 | 1670 | { |
1b4d56b8 | 1671 | if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) |
11988499 | 1672 | return false; |
1b2fd70c | 1673 | |
1b4d56b8 | 1674 | if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM)) |
11988499 | 1675 | return false; |
d8017474 | 1676 | |
0a629563 SC |
1677 | if (efer & (EFER_LME | EFER_LMA) && |
1678 | !guest_cpuid_has(vcpu, X86_FEATURE_LM)) | |
1679 | return false; | |
1680 | ||
1681 | if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX)) | |
1682 | return false; | |
d8017474 | 1683 | |
384bb783 | 1684 | return true; |
11988499 SC |
1685 | |
1686 | } | |
1687 | bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) | |
1688 | { | |
1689 | if (efer & efer_reserved_bits) | |
1690 | return false; | |
1691 | ||
1692 | return __kvm_valid_efer(vcpu, efer); | |
384bb783 JK |
1693 | } |
1694 | EXPORT_SYMBOL_GPL(kvm_valid_efer); | |
1695 | ||
11988499 | 1696 | static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
384bb783 JK |
1697 | { |
1698 | u64 old_efer = vcpu->arch.efer; | |
11988499 | 1699 | u64 efer = msr_info->data; |
72f211ec | 1700 | int r; |
384bb783 | 1701 | |
11988499 | 1702 | if (efer & efer_reserved_bits) |
66f61c92 | 1703 | return 1; |
384bb783 | 1704 | |
11988499 SC |
1705 | if (!msr_info->host_initiated) { |
1706 | if (!__kvm_valid_efer(vcpu, efer)) | |
1707 | return 1; | |
1708 | ||
1709 | if (is_paging(vcpu) && | |
1710 | (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) | |
1711 | return 1; | |
1712 | } | |
384bb783 | 1713 | |
15c4a640 | 1714 | efer &= ~EFER_LMA; |
f6801dff | 1715 | efer |= vcpu->arch.efer & EFER_LMA; |
15c4a640 | 1716 | |
b3646477 | 1717 | r = static_call(kvm_x86_set_efer)(vcpu, efer); |
72f211ec ML |
1718 | if (r) { |
1719 | WARN_ON(r > 0); | |
1720 | return r; | |
1721 | } | |
a3d204e2 | 1722 | |
d6174299 | 1723 | if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS) |
aad82703 SY |
1724 | kvm_mmu_reset_context(vcpu); |
1725 | ||
b69e8cae | 1726 | return 0; |
15c4a640 CO |
1727 | } |
1728 | ||
f2b4b7dd JR |
1729 | void kvm_enable_efer_bits(u64 mask) |
1730 | { | |
1731 | efer_reserved_bits &= ~mask; | |
1732 | } | |
1733 | EXPORT_SYMBOL_GPL(kvm_enable_efer_bits); | |
1734 | ||
51de8151 AG |
1735 | bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type) |
1736 | { | |
b318e8de SC |
1737 | struct kvm_x86_msr_filter *msr_filter; |
1738 | struct msr_bitmap_range *ranges; | |
1a155254 | 1739 | struct kvm *kvm = vcpu->kvm; |
b318e8de | 1740 | bool allowed; |
1a155254 | 1741 | int idx; |
b318e8de | 1742 | u32 i; |
1a155254 | 1743 | |
b318e8de SC |
1744 | /* x2APIC MSRs do not support filtering. */ |
1745 | if (index >= 0x800 && index <= 0x8ff) | |
1a155254 AG |
1746 | return true; |
1747 | ||
1a155254 AG |
1748 | idx = srcu_read_lock(&kvm->srcu); |
1749 | ||
b318e8de SC |
1750 | msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu); |
1751 | if (!msr_filter) { | |
1752 | allowed = true; | |
1753 | goto out; | |
1754 | } | |
1755 | ||
1756 | allowed = msr_filter->default_allow; | |
1757 | ranges = msr_filter->ranges; | |
1758 | ||
1759 | for (i = 0; i < msr_filter->count; i++) { | |
1a155254 AG |
1760 | u32 start = ranges[i].base; |
1761 | u32 end = start + ranges[i].nmsrs; | |
1762 | u32 flags = ranges[i].flags; | |
1763 | unsigned long *bitmap = ranges[i].bitmap; | |
1764 | ||
1765 | if ((index >= start) && (index < end) && (flags & type)) { | |
b318e8de | 1766 | allowed = !!test_bit(index - start, bitmap); |
1a155254 AG |
1767 | break; |
1768 | } | |
1769 | } | |
1770 | ||
b318e8de | 1771 | out: |
1a155254 AG |
1772 | srcu_read_unlock(&kvm->srcu, idx); |
1773 | ||
b318e8de | 1774 | return allowed; |
51de8151 AG |
1775 | } |
1776 | EXPORT_SYMBOL_GPL(kvm_msr_allowed); | |
1777 | ||
15c4a640 | 1778 | /* |
f20935d8 SC |
1779 | * Write @data into the MSR specified by @index. Select MSR specific fault |
1780 | * checks are bypassed if @host_initiated is %true. | |
15c4a640 CO |
1781 | * Returns 0 on success, non-0 otherwise. |
1782 | * Assumes vcpu_load() was already called. | |
1783 | */ | |
f20935d8 SC |
1784 | static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data, |
1785 | bool host_initiated) | |
15c4a640 | 1786 | { |
f20935d8 SC |
1787 | struct msr_data msr; |
1788 | ||
1789 | switch (index) { | |
854e8bb1 NA |
1790 | case MSR_FS_BASE: |
1791 | case MSR_GS_BASE: | |
1792 | case MSR_KERNEL_GS_BASE: | |
1793 | case MSR_CSTAR: | |
1794 | case MSR_LSTAR: | |
f20935d8 | 1795 | if (is_noncanonical_address(data, vcpu)) |
854e8bb1 NA |
1796 | return 1; |
1797 | break; | |
1798 | case MSR_IA32_SYSENTER_EIP: | |
1799 | case MSR_IA32_SYSENTER_ESP: | |
1800 | /* | |
1801 | * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if | |
1802 | * non-canonical address is written on Intel but not on | |
1803 | * AMD (which ignores the top 32-bits, because it does | |
1804 | * not implement 64-bit SYSENTER). | |
1805 | * | |
1806 | * 64-bit code should hence be able to write a non-canonical | |
1807 | * value on AMD. Making the address canonical ensures that | |
1808 | * vmentry does not fail on Intel after writing a non-canonical | |
1809 | * value, and that something deterministic happens if the guest | |
1810 | * invokes 64-bit SYSENTER. | |
1811 | */ | |
1fb85d06 | 1812 | data = __canonical_address(data, vcpu_virt_addr_bits(vcpu)); |
61a05d44 SC |
1813 | break; |
1814 | case MSR_TSC_AUX: | |
1815 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1816 | return 1; | |
1817 | ||
1818 | if (!host_initiated && | |
1819 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1820 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1821 | return 1; | |
1822 | ||
1823 | /* | |
1824 | * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has | |
1825 | * incomplete and conflicting architectural behavior. Current | |
1826 | * AMD CPUs completely ignore bits 63:32, i.e. they aren't | |
1827 | * reserved and always read as zeros. Enforce Intel's reserved | |
1828 | * bits check if and only if the guest CPU is Intel, and clear | |
1829 | * the bits in all other cases. This ensures cross-vendor | |
1830 | * migration will provide consistent behavior for the guest. | |
1831 | */ | |
1832 | if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0) | |
1833 | return 1; | |
1834 | ||
1835 | data = (u32)data; | |
1836 | break; | |
854e8bb1 | 1837 | } |
f20935d8 SC |
1838 | |
1839 | msr.data = data; | |
1840 | msr.index = index; | |
1841 | msr.host_initiated = host_initiated; | |
1842 | ||
b3646477 | 1843 | return static_call(kvm_x86_set_msr)(vcpu, &msr); |
15c4a640 CO |
1844 | } |
1845 | ||
6abe9c13 PX |
1846 | static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu, |
1847 | u32 index, u64 data, bool host_initiated) | |
1848 | { | |
1849 | int ret = __kvm_set_msr(vcpu, index, data, host_initiated); | |
1850 | ||
1851 | if (ret == KVM_MSR_RET_INVALID) | |
d632826f | 1852 | if (kvm_msr_ignored_check(index, data, true)) |
cc4cb017 | 1853 | ret = 0; |
6abe9c13 PX |
1854 | |
1855 | return ret; | |
1856 | } | |
1857 | ||
313a3dc7 | 1858 | /* |
f20935d8 SC |
1859 | * Read the MSR specified by @index into @data. Select MSR specific fault |
1860 | * checks are bypassed if @host_initiated is %true. | |
1861 | * Returns 0 on success, non-0 otherwise. | |
1862 | * Assumes vcpu_load() was already called. | |
313a3dc7 | 1863 | */ |
edef5c36 PB |
1864 | int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, |
1865 | bool host_initiated) | |
609e36d3 PB |
1866 | { |
1867 | struct msr_data msr; | |
f20935d8 | 1868 | int ret; |
609e36d3 | 1869 | |
61a05d44 SC |
1870 | switch (index) { |
1871 | case MSR_TSC_AUX: | |
1872 | if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX)) | |
1873 | return 1; | |
1874 | ||
1875 | if (!host_initiated && | |
1876 | !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) && | |
1877 | !guest_cpuid_has(vcpu, X86_FEATURE_RDPID)) | |
1878 | return 1; | |
1879 | break; | |
1880 | } | |
1881 | ||
609e36d3 | 1882 | msr.index = index; |
f20935d8 | 1883 | msr.host_initiated = host_initiated; |
609e36d3 | 1884 | |
b3646477 | 1885 | ret = static_call(kvm_x86_get_msr)(vcpu, &msr); |
f20935d8 SC |
1886 | if (!ret) |
1887 | *data = msr.data; | |
1888 | return ret; | |
609e36d3 PB |
1889 | } |
1890 | ||
6abe9c13 PX |
1891 | static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu, |
1892 | u32 index, u64 *data, bool host_initiated) | |
1893 | { | |
1894 | int ret = __kvm_get_msr(vcpu, index, data, host_initiated); | |
1895 | ||
1896 | if (ret == KVM_MSR_RET_INVALID) { | |
1897 | /* Unconditionally clear *data for simplicity */ | |
1898 | *data = 0; | |
d632826f | 1899 | if (kvm_msr_ignored_check(index, 0, false)) |
cc4cb017 | 1900 | ret = 0; |
6abe9c13 PX |
1901 | } |
1902 | ||
1903 | return ret; | |
1904 | } | |
1905 | ||
ac8d6cad HW |
1906 | static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
1907 | { | |
1908 | if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ)) | |
1909 | return KVM_MSR_RET_FILTERED; | |
1910 | return kvm_get_msr_ignored_check(vcpu, index, data, false); | |
1911 | } | |
1912 | ||
1913 | static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data) | |
1914 | { | |
1915 | if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE)) | |
1916 | return KVM_MSR_RET_FILTERED; | |
1917 | return kvm_set_msr_ignored_check(vcpu, index, data, false); | |
1918 | } | |
1919 | ||
f20935d8 | 1920 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data) |
313a3dc7 | 1921 | { |
6abe9c13 | 1922 | return kvm_get_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1923 | } |
1924 | EXPORT_SYMBOL_GPL(kvm_get_msr); | |
8fe8ab46 | 1925 | |
f20935d8 SC |
1926 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data) |
1927 | { | |
6abe9c13 | 1928 | return kvm_set_msr_ignored_check(vcpu, index, data, false); |
f20935d8 SC |
1929 | } |
1930 | EXPORT_SYMBOL_GPL(kvm_set_msr); | |
1931 | ||
d2f7d498 | 1932 | static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu) |
1ae09954 | 1933 | { |
d2f7d498 | 1934 | if (!vcpu->run->msr.error) { |
1ae09954 AG |
1935 | kvm_rax_write(vcpu, (u32)vcpu->run->msr.data); |
1936 | kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32); | |
1937 | } | |
d2f7d498 | 1938 | } |
1ae09954 | 1939 | |
d2f7d498 HW |
1940 | static int complete_emulated_msr_access(struct kvm_vcpu *vcpu) |
1941 | { | |
1942 | return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error); | |
1ae09954 AG |
1943 | } |
1944 | ||
d2f7d498 HW |
1945 | static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu) |
1946 | { | |
1947 | complete_userspace_rdmsr(vcpu); | |
1948 | return complete_emulated_msr_access(vcpu); | |
1949 | } | |
1950 | ||
1951 | static int complete_fast_msr_access(struct kvm_vcpu *vcpu) | |
1ae09954 | 1952 | { |
b3646477 | 1953 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error); |
1ae09954 AG |
1954 | } |
1955 | ||
d2f7d498 HW |
1956 | static int complete_fast_rdmsr(struct kvm_vcpu *vcpu) |
1957 | { | |
1958 | complete_userspace_rdmsr(vcpu); | |
1959 | return complete_fast_msr_access(vcpu); | |
1960 | } | |
1961 | ||
1ae09954 AG |
1962 | static u64 kvm_msr_reason(int r) |
1963 | { | |
1964 | switch (r) { | |
cc4cb017 | 1965 | case KVM_MSR_RET_INVALID: |
1ae09954 | 1966 | return KVM_MSR_EXIT_REASON_UNKNOWN; |
cc4cb017 | 1967 | case KVM_MSR_RET_FILTERED: |
1a155254 | 1968 | return KVM_MSR_EXIT_REASON_FILTER; |
1ae09954 AG |
1969 | default: |
1970 | return KVM_MSR_EXIT_REASON_INVAL; | |
1971 | } | |
1972 | } | |
1973 | ||
1974 | static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index, | |
1975 | u32 exit_reason, u64 data, | |
1976 | int (*completion)(struct kvm_vcpu *vcpu), | |
1977 | int r) | |
1978 | { | |
1979 | u64 msr_reason = kvm_msr_reason(r); | |
1980 | ||
1981 | /* Check if the user wanted to know about this MSR fault */ | |
1982 | if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason)) | |
1983 | return 0; | |
1984 | ||
1985 | vcpu->run->exit_reason = exit_reason; | |
1986 | vcpu->run->msr.error = 0; | |
1987 | memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad)); | |
1988 | vcpu->run->msr.reason = msr_reason; | |
1989 | vcpu->run->msr.index = index; | |
1990 | vcpu->run->msr.data = data; | |
1991 | vcpu->arch.complete_userspace_io = completion; | |
1992 | ||
1993 | return 1; | |
1994 | } | |
1995 | ||
1edce0a9 SC |
1996 | int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu) |
1997 | { | |
1998 | u32 ecx = kvm_rcx_read(vcpu); | |
1999 | u64 data; | |
1ae09954 AG |
2000 | int r; |
2001 | ||
ac8d6cad | 2002 | r = kvm_get_msr_with_filter(vcpu, ecx, &data); |
1edce0a9 | 2003 | |
8b474427 PB |
2004 | if (!r) { |
2005 | trace_kvm_msr_read(ecx, data); | |
2006 | ||
2007 | kvm_rax_write(vcpu, data & -1u); | |
2008 | kvm_rdx_write(vcpu, (data >> 32) & -1u); | |
2009 | } else { | |
d2f7d498 HW |
2010 | /* MSR read failed? See if we should ask user space */ |
2011 | if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0, | |
2012 | complete_fast_rdmsr, r)) | |
2013 | return 0; | |
1edce0a9 | 2014 | trace_kvm_msr_read_ex(ecx); |
1edce0a9 SC |
2015 | } |
2016 | ||
b3646477 | 2017 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
2018 | } |
2019 | EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr); | |
2020 | ||
2021 | int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu) | |
2022 | { | |
2023 | u32 ecx = kvm_rcx_read(vcpu); | |
2024 | u64 data = kvm_read_edx_eax(vcpu); | |
1ae09954 | 2025 | int r; |
1edce0a9 | 2026 | |
ac8d6cad | 2027 | r = kvm_set_msr_with_filter(vcpu, ecx, data); |
1ae09954 | 2028 | |
d2f7d498 | 2029 | if (!r) { |
8b474427 | 2030 | trace_kvm_msr_write(ecx, data); |
d2f7d498 HW |
2031 | } else { |
2032 | /* MSR write failed? See if we should ask user space */ | |
2033 | if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data, | |
2034 | complete_fast_msr_access, r)) | |
2035 | return 0; | |
2036 | /* Signal all other negative errors to userspace */ | |
2037 | if (r < 0) | |
2038 | return r; | |
1edce0a9 | 2039 | trace_kvm_msr_write_ex(ecx, data); |
d2f7d498 | 2040 | } |
1edce0a9 | 2041 | |
b3646477 | 2042 | return static_call(kvm_x86_complete_emulated_msr)(vcpu, r); |
1edce0a9 SC |
2043 | } |
2044 | EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr); | |
2045 | ||
5ff3a351 SC |
2046 | int kvm_emulate_as_nop(struct kvm_vcpu *vcpu) |
2047 | { | |
2048 | return kvm_skip_emulated_instruction(vcpu); | |
2049 | } | |
2050 | EXPORT_SYMBOL_GPL(kvm_emulate_as_nop); | |
2051 | ||
2052 | int kvm_emulate_invd(struct kvm_vcpu *vcpu) | |
2053 | { | |
2054 | /* Treat an INVD instruction as a NOP and just skip it. */ | |
2055 | return kvm_emulate_as_nop(vcpu); | |
2056 | } | |
2057 | EXPORT_SYMBOL_GPL(kvm_emulate_invd); | |
2058 | ||
5ff3a351 SC |
2059 | int kvm_handle_invalid_op(struct kvm_vcpu *vcpu) |
2060 | { | |
2061 | kvm_queue_exception(vcpu, UD_VECTOR); | |
2062 | return 1; | |
2063 | } | |
2064 | EXPORT_SYMBOL_GPL(kvm_handle_invalid_op); | |
2065 | ||
bfbcc81b SC |
2066 | |
2067 | static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn) | |
5ff3a351 | 2068 | { |
43bb9e00 | 2069 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) && |
bfbcc81b SC |
2070 | !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT)) |
2071 | return kvm_handle_invalid_op(vcpu); | |
2072 | ||
2073 | pr_warn_once("kvm: %s instruction emulated as NOP!\n", insn); | |
5ff3a351 SC |
2074 | return kvm_emulate_as_nop(vcpu); |
2075 | } | |
bfbcc81b SC |
2076 | int kvm_emulate_mwait(struct kvm_vcpu *vcpu) |
2077 | { | |
2078 | return kvm_emulate_monitor_mwait(vcpu, "MWAIT"); | |
2079 | } | |
2080 | EXPORT_SYMBOL_GPL(kvm_emulate_mwait); | |
2081 | ||
2082 | int kvm_emulate_monitor(struct kvm_vcpu *vcpu) | |
2083 | { | |
2084 | return kvm_emulate_monitor_mwait(vcpu, "MONITOR"); | |
2085 | } | |
5ff3a351 SC |
2086 | EXPORT_SYMBOL_GPL(kvm_emulate_monitor); |
2087 | ||
d89d04ab | 2088 | static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu) |
5a9f5443 | 2089 | { |
4ae7dc97 | 2090 | xfer_to_guest_mode_prepare(); |
5a9f5443 | 2091 | return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) || |
72c3c0fe | 2092 | xfer_to_guest_mode_work_pending(); |
5a9f5443 | 2093 | } |
5a9f5443 | 2094 | |
1e9e2622 WL |
2095 | /* |
2096 | * The fast path for frequent and performance sensitive wrmsr emulation, | |
2097 | * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces | |
2098 | * the latency of virtual IPI by avoiding the expensive bits of transitioning | |
2099 | * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the | |
2100 | * other cases which must be called after interrupts are enabled on the host. | |
2101 | */ | |
2102 | static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data) | |
2103 | { | |
e1be9ac8 WL |
2104 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic)) |
2105 | return 1; | |
2106 | ||
2107 | if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) && | |
bd17f417 SC |
2108 | ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) && |
2109 | ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && | |
b9964ee3 SC |
2110 | ((u32)(data >> 32) != X2APIC_BROADCAST)) |
2111 | return kvm_x2apic_icr_write(vcpu->arch.apic, data); | |
1e9e2622 WL |
2112 | |
2113 | return 1; | |
2114 | } | |
2115 | ||
ae95f566 WL |
2116 | static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data) |
2117 | { | |
2118 | if (!kvm_can_use_hv_timer(vcpu)) | |
2119 | return 1; | |
2120 | ||
2121 | kvm_set_lapic_tscdeadline_msr(vcpu, data); | |
2122 | return 0; | |
2123 | } | |
2124 | ||
404d5d7b | 2125 | fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu) |
1e9e2622 WL |
2126 | { |
2127 | u32 msr = kvm_rcx_read(vcpu); | |
8a1038de | 2128 | u64 data; |
404d5d7b | 2129 | fastpath_t ret = EXIT_FASTPATH_NONE; |
1e9e2622 WL |
2130 | |
2131 | switch (msr) { | |
2132 | case APIC_BASE_MSR + (APIC_ICR >> 4): | |
8a1038de | 2133 | data = kvm_read_edx_eax(vcpu); |
404d5d7b WL |
2134 | if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) { |
2135 | kvm_skip_emulated_instruction(vcpu); | |
2136 | ret = EXIT_FASTPATH_EXIT_HANDLED; | |
80bc97f2 | 2137 | } |
1e9e2622 | 2138 | break; |
09141ec0 | 2139 | case MSR_IA32_TSC_DEADLINE: |
ae95f566 WL |
2140 | data = kvm_read_edx_eax(vcpu); |
2141 | if (!handle_fastpath_set_tscdeadline(vcpu, data)) { | |
2142 | kvm_skip_emulated_instruction(vcpu); | |
2143 | ret = EXIT_FASTPATH_REENTER_GUEST; | |
2144 | } | |
2145 | break; | |
1e9e2622 | 2146 | default: |
404d5d7b | 2147 | break; |
1e9e2622 WL |
2148 | } |
2149 | ||
404d5d7b | 2150 | if (ret != EXIT_FASTPATH_NONE) |
1e9e2622 | 2151 | trace_kvm_msr_write(msr, data); |
1e9e2622 | 2152 | |
404d5d7b | 2153 | return ret; |
1e9e2622 WL |
2154 | } |
2155 | EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff); | |
2156 | ||
f20935d8 SC |
2157 | /* |
2158 | * Adapt set_msr() to msr_io()'s calling convention | |
2159 | */ | |
2160 | static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
2161 | { | |
6abe9c13 | 2162 | return kvm_get_msr_ignored_check(vcpu, index, data, true); |
f20935d8 SC |
2163 | } |
2164 | ||
2165 | static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data) | |
2166 | { | |
6abe9c13 | 2167 | return kvm_set_msr_ignored_check(vcpu, index, *data, true); |
313a3dc7 CO |
2168 | } |
2169 | ||
16e8d74d | 2170 | #ifdef CONFIG_X86_64 |
53fafdbb MT |
2171 | struct pvclock_clock { |
2172 | int vclock_mode; | |
2173 | u64 cycle_last; | |
2174 | u64 mask; | |
2175 | u32 mult; | |
2176 | u32 shift; | |
917f9475 PB |
2177 | u64 base_cycles; |
2178 | u64 offset; | |
53fafdbb MT |
2179 | }; |
2180 | ||
16e8d74d MT |
2181 | struct pvclock_gtod_data { |
2182 | seqcount_t seq; | |
2183 | ||
53fafdbb MT |
2184 | struct pvclock_clock clock; /* extract of a clocksource struct */ |
2185 | struct pvclock_clock raw_clock; /* extract of a clocksource struct */ | |
16e8d74d | 2186 | |
917f9475 | 2187 | ktime_t offs_boot; |
55dd00a7 | 2188 | u64 wall_time_sec; |
16e8d74d MT |
2189 | }; |
2190 | ||
2191 | static struct pvclock_gtod_data pvclock_gtod_data; | |
2192 | ||
2193 | static void update_pvclock_gtod(struct timekeeper *tk) | |
2194 | { | |
2195 | struct pvclock_gtod_data *vdata = &pvclock_gtod_data; | |
2196 | ||
2197 | write_seqcount_begin(&vdata->seq); | |
2198 | ||
2199 | /* copy pvclock gtod data */ | |
b95a8a27 | 2200 | vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode; |
876e7881 PZ |
2201 | vdata->clock.cycle_last = tk->tkr_mono.cycle_last; |
2202 | vdata->clock.mask = tk->tkr_mono.mask; | |
2203 | vdata->clock.mult = tk->tkr_mono.mult; | |
2204 | vdata->clock.shift = tk->tkr_mono.shift; | |
917f9475 PB |
2205 | vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec; |
2206 | vdata->clock.offset = tk->tkr_mono.base; | |
16e8d74d | 2207 | |
b95a8a27 | 2208 | vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode; |
53fafdbb MT |
2209 | vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last; |
2210 | vdata->raw_clock.mask = tk->tkr_raw.mask; | |
2211 | vdata->raw_clock.mult = tk->tkr_raw.mult; | |
2212 | vdata->raw_clock.shift = tk->tkr_raw.shift; | |
917f9475 PB |
2213 | vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec; |
2214 | vdata->raw_clock.offset = tk->tkr_raw.base; | |
16e8d74d | 2215 | |
55dd00a7 MT |
2216 | vdata->wall_time_sec = tk->xtime_sec; |
2217 | ||
917f9475 | 2218 | vdata->offs_boot = tk->offs_boot; |
53fafdbb | 2219 | |
16e8d74d MT |
2220 | write_seqcount_end(&vdata->seq); |
2221 | } | |
8171cd68 PB |
2222 | |
2223 | static s64 get_kvmclock_base_ns(void) | |
2224 | { | |
2225 | /* Count up from boot time, but with the frequency of the raw clock. */ | |
2226 | return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot)); | |
2227 | } | |
2228 | #else | |
2229 | static s64 get_kvmclock_base_ns(void) | |
2230 | { | |
2231 | /* Master clock not used, so we can just use CLOCK_BOOTTIME. */ | |
2232 | return ktime_get_boottime_ns(); | |
2233 | } | |
16e8d74d MT |
2234 | #endif |
2235 | ||
55749769 | 2236 | static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs) |
18068523 | 2237 | { |
9ed3c444 AK |
2238 | int version; |
2239 | int r; | |
50d0a0f9 | 2240 | struct pvclock_wall_clock wc; |
629b5348 | 2241 | u32 wc_sec_hi; |
8171cd68 | 2242 | u64 wall_nsec; |
18068523 GOC |
2243 | |
2244 | if (!wall_clock) | |
2245 | return; | |
2246 | ||
9ed3c444 AK |
2247 | r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version)); |
2248 | if (r) | |
2249 | return; | |
2250 | ||
2251 | if (version & 1) | |
2252 | ++version; /* first time write, random junk */ | |
2253 | ||
2254 | ++version; | |
18068523 | 2255 | |
1dab1345 NK |
2256 | if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version))) |
2257 | return; | |
18068523 | 2258 | |
50d0a0f9 GH |
2259 | /* |
2260 | * The guest calculates current wall clock time by adding | |
34c238a1 | 2261 | * system time (updated by kvm_guest_time_update below) to the |
8171cd68 | 2262 | * wall clock specified here. We do the reverse here. |
50d0a0f9 | 2263 | */ |
8171cd68 | 2264 | wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm); |
50d0a0f9 | 2265 | |
8171cd68 PB |
2266 | wc.nsec = do_div(wall_nsec, 1000000000); |
2267 | wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */ | |
50d0a0f9 | 2268 | wc.version = version; |
18068523 GOC |
2269 | |
2270 | kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc)); | |
2271 | ||
629b5348 JM |
2272 | if (sec_hi_ofs) { |
2273 | wc_sec_hi = wall_nsec >> 32; | |
2274 | kvm_write_guest(kvm, wall_clock + sec_hi_ofs, | |
2275 | &wc_sec_hi, sizeof(wc_sec_hi)); | |
2276 | } | |
2277 | ||
18068523 GOC |
2278 | version++; |
2279 | kvm_write_guest(kvm, wall_clock, &version, sizeof(version)); | |
18068523 GOC |
2280 | } |
2281 | ||
5b9bb0eb OU |
2282 | static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time, |
2283 | bool old_msr, bool host_initiated) | |
2284 | { | |
2285 | struct kvm_arch *ka = &vcpu->kvm->arch; | |
2286 | ||
2287 | if (vcpu->vcpu_id == 0 && !host_initiated) { | |
1e293d1a | 2288 | if (ka->boot_vcpu_runs_old_kvmclock != old_msr) |
5b9bb0eb OU |
2289 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2290 | ||
2291 | ka->boot_vcpu_runs_old_kvmclock = old_msr; | |
2292 | } | |
2293 | ||
2294 | vcpu->arch.time = system_time; | |
2295 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); | |
2296 | ||
2297 | /* we verify if the enable bit is set... */ | |
916d3608 DW |
2298 | if (system_time & 1) { |
2299 | kvm_gfn_to_pfn_cache_init(vcpu->kvm, &vcpu->arch.pv_time, vcpu, | |
2300 | KVM_HOST_USES_PFN, system_time & ~1ULL, | |
2301 | sizeof(struct pvclock_vcpu_time_info)); | |
2302 | } else { | |
2303 | kvm_gfn_to_pfn_cache_destroy(vcpu->kvm, &vcpu->arch.pv_time); | |
2304 | } | |
5b9bb0eb OU |
2305 | |
2306 | return; | |
2307 | } | |
2308 | ||
50d0a0f9 GH |
2309 | static uint32_t div_frac(uint32_t dividend, uint32_t divisor) |
2310 | { | |
b51012de PB |
2311 | do_shl32_div32(dividend, divisor); |
2312 | return dividend; | |
50d0a0f9 GH |
2313 | } |
2314 | ||
3ae13faa | 2315 | static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz, |
5f4e3f88 | 2316 | s8 *pshift, u32 *pmultiplier) |
50d0a0f9 | 2317 | { |
5f4e3f88 | 2318 | uint64_t scaled64; |
50d0a0f9 GH |
2319 | int32_t shift = 0; |
2320 | uint64_t tps64; | |
2321 | uint32_t tps32; | |
2322 | ||
3ae13faa PB |
2323 | tps64 = base_hz; |
2324 | scaled64 = scaled_hz; | |
50933623 | 2325 | while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) { |
50d0a0f9 GH |
2326 | tps64 >>= 1; |
2327 | shift--; | |
2328 | } | |
2329 | ||
2330 | tps32 = (uint32_t)tps64; | |
50933623 JK |
2331 | while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) { |
2332 | if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000) | |
5f4e3f88 ZA |
2333 | scaled64 >>= 1; |
2334 | else | |
2335 | tps32 <<= 1; | |
50d0a0f9 GH |
2336 | shift++; |
2337 | } | |
2338 | ||
5f4e3f88 ZA |
2339 | *pshift = shift; |
2340 | *pmultiplier = div_frac(scaled64, tps32); | |
50d0a0f9 GH |
2341 | } |
2342 | ||
d828199e | 2343 | #ifdef CONFIG_X86_64 |
16e8d74d | 2344 | static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0); |
d828199e | 2345 | #endif |
16e8d74d | 2346 | |
c8076604 | 2347 | static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz); |
69b0049a | 2348 | static unsigned long max_tsc_khz; |
c8076604 | 2349 | |
cc578287 | 2350 | static u32 adjust_tsc_khz(u32 khz, s32 ppm) |
1e993611 | 2351 | { |
cc578287 ZA |
2352 | u64 v = (u64)khz * (1000000 + ppm); |
2353 | do_div(v, 1000000); | |
2354 | return v; | |
1e993611 JR |
2355 | } |
2356 | ||
1ab9287a IS |
2357 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier); |
2358 | ||
381d585c HZ |
2359 | static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale) |
2360 | { | |
2361 | u64 ratio; | |
2362 | ||
2363 | /* Guest TSC same frequency as host TSC? */ | |
2364 | if (!scale) { | |
938c8745 | 2365 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio); |
381d585c HZ |
2366 | return 0; |
2367 | } | |
2368 | ||
2369 | /* TSC scaling supported? */ | |
938c8745 | 2370 | if (!kvm_caps.has_tsc_control) { |
381d585c HZ |
2371 | if (user_tsc_khz > tsc_khz) { |
2372 | vcpu->arch.tsc_catchup = 1; | |
2373 | vcpu->arch.tsc_always_catchup = 1; | |
2374 | return 0; | |
2375 | } else { | |
3f16a5c3 | 2376 | pr_warn_ratelimited("user requested TSC rate below hardware speed\n"); |
381d585c HZ |
2377 | return -1; |
2378 | } | |
2379 | } | |
2380 | ||
2381 | /* TSC scaling required - calculate ratio */ | |
938c8745 | 2382 | ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits, |
381d585c HZ |
2383 | user_tsc_khz, tsc_khz); |
2384 | ||
938c8745 | 2385 | if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) { |
3f16a5c3 PB |
2386 | pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n", |
2387 | user_tsc_khz); | |
381d585c HZ |
2388 | return -1; |
2389 | } | |
2390 | ||
1ab9287a | 2391 | kvm_vcpu_write_tsc_multiplier(vcpu, ratio); |
381d585c HZ |
2392 | return 0; |
2393 | } | |
2394 | ||
4941b8cb | 2395 | static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz) |
759379dd | 2396 | { |
cc578287 ZA |
2397 | u32 thresh_lo, thresh_hi; |
2398 | int use_scaling = 0; | |
217fc9cf | 2399 | |
03ba32ca | 2400 | /* tsc_khz can be zero if TSC calibration fails */ |
4941b8cb | 2401 | if (user_tsc_khz == 0) { |
ad721883 | 2402 | /* set tsc_scaling_ratio to a safe value */ |
938c8745 | 2403 | kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio); |
381d585c | 2404 | return -1; |
ad721883 | 2405 | } |
03ba32ca | 2406 | |
c285545f | 2407 | /* Compute a scale to convert nanoseconds in TSC cycles */ |
3ae13faa | 2408 | kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC, |
cc578287 ZA |
2409 | &vcpu->arch.virtual_tsc_shift, |
2410 | &vcpu->arch.virtual_tsc_mult); | |
4941b8cb | 2411 | vcpu->arch.virtual_tsc_khz = user_tsc_khz; |
cc578287 ZA |
2412 | |
2413 | /* | |
2414 | * Compute the variation in TSC rate which is acceptable | |
2415 | * within the range of tolerance and decide if the | |
2416 | * rate being applied is within that bounds of the hardware | |
2417 | * rate. If so, no scaling or compensation need be done. | |
2418 | */ | |
2419 | thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm); | |
2420 | thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm); | |
4941b8cb PB |
2421 | if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) { |
2422 | pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi); | |
cc578287 ZA |
2423 | use_scaling = 1; |
2424 | } | |
4941b8cb | 2425 | return set_tsc_khz(vcpu, user_tsc_khz, use_scaling); |
c285545f ZA |
2426 | } |
2427 | ||
2428 | static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns) | |
2429 | { | |
e26101b1 | 2430 | u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec, |
cc578287 ZA |
2431 | vcpu->arch.virtual_tsc_mult, |
2432 | vcpu->arch.virtual_tsc_shift); | |
e26101b1 | 2433 | tsc += vcpu->arch.this_tsc_write; |
c285545f ZA |
2434 | return tsc; |
2435 | } | |
2436 | ||
ba1f77c5 | 2437 | #ifdef CONFIG_X86_64 |
b0c39dc6 VK |
2438 | static inline int gtod_is_based_on_tsc(int mode) |
2439 | { | |
b95a8a27 | 2440 | return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK; |
b0c39dc6 | 2441 | } |
ba1f77c5 | 2442 | #endif |
b0c39dc6 | 2443 | |
69b0049a | 2444 | static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu) |
b48aa97e MT |
2445 | { |
2446 | #ifdef CONFIG_X86_64 | |
2447 | bool vcpus_matched; | |
b48aa97e MT |
2448 | struct kvm_arch *ka = &vcpu->kvm->arch; |
2449 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2450 | ||
2451 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == | |
2452 | atomic_read(&vcpu->kvm->online_vcpus)); | |
2453 | ||
7f187922 MT |
2454 | /* |
2455 | * Once the masterclock is enabled, always perform request in | |
2456 | * order to update it. | |
2457 | * | |
2458 | * In order to enable masterclock, the host clocksource must be TSC | |
2459 | * and the vcpus need to have matched TSCs. When that happens, | |
2460 | * perform request to enable masterclock. | |
2461 | */ | |
2462 | if (ka->use_master_clock || | |
b0c39dc6 | 2463 | (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched)) |
b48aa97e MT |
2464 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
2465 | ||
2466 | trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc, | |
2467 | atomic_read(&vcpu->kvm->online_vcpus), | |
2468 | ka->use_master_clock, gtod->clock.vclock_mode); | |
2469 | #endif | |
2470 | } | |
2471 | ||
35181e86 HZ |
2472 | /* |
2473 | * Multiply tsc by a fixed point number represented by ratio. | |
2474 | * | |
2475 | * The most significant 64-N bits (mult) of ratio represent the | |
2476 | * integral part of the fixed point number; the remaining N bits | |
2477 | * (frac) represent the fractional part, ie. ratio represents a fixed | |
2478 | * point number (mult + frac * 2^(-N)). | |
2479 | * | |
938c8745 | 2480 | * N equals to kvm_caps.tsc_scaling_ratio_frac_bits. |
35181e86 HZ |
2481 | */ |
2482 | static inline u64 __scale_tsc(u64 ratio, u64 tsc) | |
2483 | { | |
938c8745 | 2484 | return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits); |
35181e86 HZ |
2485 | } |
2486 | ||
62711e5a | 2487 | u64 kvm_scale_tsc(u64 tsc, u64 ratio) |
35181e86 HZ |
2488 | { |
2489 | u64 _tsc = tsc; | |
35181e86 | 2490 | |
938c8745 | 2491 | if (ratio != kvm_caps.default_tsc_scaling_ratio) |
35181e86 HZ |
2492 | _tsc = __scale_tsc(ratio, tsc); |
2493 | ||
2494 | return _tsc; | |
2495 | } | |
2496 | EXPORT_SYMBOL_GPL(kvm_scale_tsc); | |
2497 | ||
9b399dfd | 2498 | static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc) |
07c1419a HZ |
2499 | { |
2500 | u64 tsc; | |
2501 | ||
62711e5a | 2502 | tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio); |
07c1419a HZ |
2503 | |
2504 | return target_tsc - tsc; | |
2505 | } | |
2506 | ||
4ba76538 HZ |
2507 | u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc) |
2508 | { | |
fe3eb504 | 2509 | return vcpu->arch.l1_tsc_offset + |
62711e5a | 2510 | kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio); |
4ba76538 HZ |
2511 | } |
2512 | EXPORT_SYMBOL_GPL(kvm_read_l1_tsc); | |
2513 | ||
83150f29 IS |
2514 | u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier) |
2515 | { | |
2516 | u64 nested_offset; | |
2517 | ||
938c8745 | 2518 | if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio) |
83150f29 IS |
2519 | nested_offset = l1_offset; |
2520 | else | |
2521 | nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier, | |
938c8745 | 2522 | kvm_caps.tsc_scaling_ratio_frac_bits); |
83150f29 IS |
2523 | |
2524 | nested_offset += l2_offset; | |
2525 | return nested_offset; | |
2526 | } | |
2527 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset); | |
2528 | ||
2529 | u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier) | |
2530 | { | |
938c8745 | 2531 | if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio) |
83150f29 | 2532 | return mul_u64_u64_shr(l1_multiplier, l2_multiplier, |
938c8745 | 2533 | kvm_caps.tsc_scaling_ratio_frac_bits); |
83150f29 IS |
2534 | |
2535 | return l1_multiplier; | |
2536 | } | |
2537 | EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier); | |
2538 | ||
edcfe540 | 2539 | static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset) |
a545ab6a | 2540 | { |
edcfe540 IS |
2541 | trace_kvm_write_tsc_offset(vcpu->vcpu_id, |
2542 | vcpu->arch.l1_tsc_offset, | |
2543 | l1_offset); | |
2544 | ||
2545 | vcpu->arch.l1_tsc_offset = l1_offset; | |
2546 | ||
2547 | /* | |
2548 | * If we are here because L1 chose not to trap WRMSR to TSC then | |
2549 | * according to the spec this should set L1's TSC (as opposed to | |
2550 | * setting L1's offset for L2). | |
2551 | */ | |
2552 | if (is_guest_mode(vcpu)) | |
2553 | vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset( | |
2554 | l1_offset, | |
2555 | static_call(kvm_x86_get_l2_tsc_offset)(vcpu), | |
2556 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2557 | else | |
2558 | vcpu->arch.tsc_offset = l1_offset; | |
2559 | ||
2560 | static_call(kvm_x86_write_tsc_offset)(vcpu, vcpu->arch.tsc_offset); | |
a545ab6a LC |
2561 | } |
2562 | ||
1ab9287a IS |
2563 | static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier) |
2564 | { | |
2565 | vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier; | |
2566 | ||
2567 | /* Userspace is changing the multiplier while L2 is active */ | |
2568 | if (is_guest_mode(vcpu)) | |
2569 | vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier( | |
2570 | l1_multiplier, | |
2571 | static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu)); | |
2572 | else | |
2573 | vcpu->arch.tsc_scaling_ratio = l1_multiplier; | |
2574 | ||
938c8745 | 2575 | if (kvm_caps.has_tsc_control) |
1ab9287a IS |
2576 | static_call(kvm_x86_write_tsc_multiplier)( |
2577 | vcpu, vcpu->arch.tsc_scaling_ratio); | |
2578 | } | |
2579 | ||
b0c39dc6 VK |
2580 | static inline bool kvm_check_tsc_unstable(void) |
2581 | { | |
2582 | #ifdef CONFIG_X86_64 | |
2583 | /* | |
2584 | * TSC is marked unstable when we're running on Hyper-V, | |
2585 | * 'TSC page' clocksource is good. | |
2586 | */ | |
b95a8a27 | 2587 | if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK) |
b0c39dc6 VK |
2588 | return false; |
2589 | #endif | |
2590 | return check_tsc_unstable(); | |
2591 | } | |
2592 | ||
58d4277b OU |
2593 | /* |
2594 | * Infers attempts to synchronize the guest's tsc from host writes. Sets the | |
2595 | * offset for the vcpu and tracks the TSC matching generation that the vcpu | |
2596 | * participates in. | |
2597 | */ | |
2598 | static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc, | |
2599 | u64 ns, bool matched) | |
2600 | { | |
2601 | struct kvm *kvm = vcpu->kvm; | |
2602 | ||
2603 | lockdep_assert_held(&kvm->arch.tsc_write_lock); | |
2604 | ||
2605 | /* | |
2606 | * We also track th most recent recorded KHZ, write and time to | |
2607 | * allow the matching interval to be extended at each write. | |
2608 | */ | |
2609 | kvm->arch.last_tsc_nsec = ns; | |
2610 | kvm->arch.last_tsc_write = tsc; | |
2611 | kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz; | |
828ca896 | 2612 | kvm->arch.last_tsc_offset = offset; |
58d4277b OU |
2613 | |
2614 | vcpu->arch.last_guest_tsc = tsc; | |
2615 | ||
2616 | kvm_vcpu_write_tsc_offset(vcpu, offset); | |
2617 | ||
2618 | if (!matched) { | |
2619 | /* | |
2620 | * We split periods of matched TSC writes into generations. | |
2621 | * For each generation, we track the original measured | |
2622 | * nanosecond time, offset, and write, so if TSCs are in | |
2623 | * sync, we can match exact offset, and if not, we can match | |
2624 | * exact software computation in compute_guest_tsc() | |
2625 | * | |
2626 | * These values are tracked in kvm->arch.cur_xxx variables. | |
2627 | */ | |
2628 | kvm->arch.cur_tsc_generation++; | |
2629 | kvm->arch.cur_tsc_nsec = ns; | |
2630 | kvm->arch.cur_tsc_write = tsc; | |
2631 | kvm->arch.cur_tsc_offset = offset; | |
2632 | kvm->arch.nr_vcpus_matched_tsc = 0; | |
2633 | } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) { | |
2634 | kvm->arch.nr_vcpus_matched_tsc++; | |
2635 | } | |
2636 | ||
2637 | /* Keep track of which generation this VCPU has synchronized to */ | |
2638 | vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation; | |
2639 | vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec; | |
2640 | vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write; | |
2641 | ||
2642 | kvm_track_tsc_matching(vcpu); | |
2643 | } | |
2644 | ||
0c899c25 | 2645 | static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data) |
99e3e30a ZA |
2646 | { |
2647 | struct kvm *kvm = vcpu->kvm; | |
f38e098f | 2648 | u64 offset, ns, elapsed; |
99e3e30a | 2649 | unsigned long flags; |
58d4277b | 2650 | bool matched = false; |
c5e8ec8e | 2651 | bool synchronizing = false; |
99e3e30a | 2652 | |
038f8c11 | 2653 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); |
9b399dfd | 2654 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
8171cd68 | 2655 | ns = get_kvmclock_base_ns(); |
f38e098f | 2656 | elapsed = ns - kvm->arch.last_tsc_nsec; |
5d3cb0f6 | 2657 | |
03ba32ca | 2658 | if (vcpu->arch.virtual_tsc_khz) { |
0c899c25 | 2659 | if (data == 0) { |
bd8fab39 DP |
2660 | /* |
2661 | * detection of vcpu initialization -- need to sync | |
2662 | * with other vCPUs. This particularly helps to keep | |
2663 | * kvm_clock stable after CPU hotplug | |
2664 | */ | |
2665 | synchronizing = true; | |
2666 | } else { | |
2667 | u64 tsc_exp = kvm->arch.last_tsc_write + | |
2668 | nsec_to_cycles(vcpu, elapsed); | |
2669 | u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL; | |
2670 | /* | |
2671 | * Special case: TSC write with a small delta (1 second) | |
2672 | * of virtual cycle time against real time is | |
2673 | * interpreted as an attempt to synchronize the CPU. | |
2674 | */ | |
2675 | synchronizing = data < tsc_exp + tsc_hz && | |
2676 | data + tsc_hz > tsc_exp; | |
2677 | } | |
c5e8ec8e | 2678 | } |
f38e098f ZA |
2679 | |
2680 | /* | |
5d3cb0f6 ZA |
2681 | * For a reliable TSC, we can match TSC offsets, and for an unstable |
2682 | * TSC, we add elapsed time in this computation. We could let the | |
2683 | * compensation code attempt to catch up if we fall behind, but | |
2684 | * it's better to try to match offsets from the beginning. | |
2685 | */ | |
c5e8ec8e | 2686 | if (synchronizing && |
5d3cb0f6 | 2687 | vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) { |
b0c39dc6 | 2688 | if (!kvm_check_tsc_unstable()) { |
e26101b1 | 2689 | offset = kvm->arch.cur_tsc_offset; |
f38e098f | 2690 | } else { |
857e4099 | 2691 | u64 delta = nsec_to_cycles(vcpu, elapsed); |
5d3cb0f6 | 2692 | data += delta; |
9b399dfd | 2693 | offset = kvm_compute_l1_tsc_offset(vcpu, data); |
f38e098f | 2694 | } |
b48aa97e | 2695 | matched = true; |
f38e098f | 2696 | } |
e26101b1 | 2697 | |
58d4277b | 2698 | __kvm_synchronize_tsc(vcpu, offset, data, ns, matched); |
e26101b1 | 2699 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
99e3e30a | 2700 | } |
e26101b1 | 2701 | |
58ea6767 HZ |
2702 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
2703 | s64 adjustment) | |
2704 | { | |
56ba77a4 | 2705 | u64 tsc_offset = vcpu->arch.l1_tsc_offset; |
326e7425 | 2706 | kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment); |
58ea6767 HZ |
2707 | } |
2708 | ||
2709 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
2710 | { | |
938c8745 | 2711 | if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio) |
58ea6767 | 2712 | WARN_ON(adjustment < 0); |
62711e5a | 2713 | adjustment = kvm_scale_tsc((u64) adjustment, |
fe3eb504 | 2714 | vcpu->arch.l1_tsc_scaling_ratio); |
ea26e4ec | 2715 | adjust_tsc_offset_guest(vcpu, adjustment); |
58ea6767 HZ |
2716 | } |
2717 | ||
d828199e MT |
2718 | #ifdef CONFIG_X86_64 |
2719 | ||
a5a1d1c2 | 2720 | static u64 read_tsc(void) |
d828199e | 2721 | { |
a5a1d1c2 | 2722 | u64 ret = (u64)rdtsc_ordered(); |
03b9730b | 2723 | u64 last = pvclock_gtod_data.clock.cycle_last; |
d828199e MT |
2724 | |
2725 | if (likely(ret >= last)) | |
2726 | return ret; | |
2727 | ||
2728 | /* | |
2729 | * GCC likes to generate cmov here, but this branch is extremely | |
6a6256f9 | 2730 | * predictable (it's just a function of time and the likely is |
d828199e MT |
2731 | * very likely) and there's a data dependence, so force GCC |
2732 | * to generate a branch instead. I don't barrier() because | |
2733 | * we don't actually need a barrier, and if this function | |
2734 | * ever gets inlined it will generate worse code. | |
2735 | */ | |
2736 | asm volatile (""); | |
2737 | return last; | |
2738 | } | |
2739 | ||
53fafdbb MT |
2740 | static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp, |
2741 | int *mode) | |
d828199e MT |
2742 | { |
2743 | long v; | |
b0c39dc6 VK |
2744 | u64 tsc_pg_val; |
2745 | ||
53fafdbb | 2746 | switch (clock->vclock_mode) { |
b95a8a27 | 2747 | case VDSO_CLOCKMODE_HVCLOCK: |
b0c39dc6 VK |
2748 | tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(), |
2749 | tsc_timestamp); | |
2750 | if (tsc_pg_val != U64_MAX) { | |
2751 | /* TSC page valid */ | |
b95a8a27 | 2752 | *mode = VDSO_CLOCKMODE_HVCLOCK; |
53fafdbb MT |
2753 | v = (tsc_pg_val - clock->cycle_last) & |
2754 | clock->mask; | |
b0c39dc6 VK |
2755 | } else { |
2756 | /* TSC page invalid */ | |
b95a8a27 | 2757 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 VK |
2758 | } |
2759 | break; | |
b95a8a27 TG |
2760 | case VDSO_CLOCKMODE_TSC: |
2761 | *mode = VDSO_CLOCKMODE_TSC; | |
b0c39dc6 | 2762 | *tsc_timestamp = read_tsc(); |
53fafdbb MT |
2763 | v = (*tsc_timestamp - clock->cycle_last) & |
2764 | clock->mask; | |
b0c39dc6 VK |
2765 | break; |
2766 | default: | |
b95a8a27 | 2767 | *mode = VDSO_CLOCKMODE_NONE; |
b0c39dc6 | 2768 | } |
d828199e | 2769 | |
b95a8a27 | 2770 | if (*mode == VDSO_CLOCKMODE_NONE) |
b0c39dc6 | 2771 | *tsc_timestamp = v = 0; |
d828199e | 2772 | |
53fafdbb | 2773 | return v * clock->mult; |
d828199e MT |
2774 | } |
2775 | ||
53fafdbb | 2776 | static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp) |
d828199e | 2777 | { |
cbcf2dd3 | 2778 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; |
d828199e | 2779 | unsigned long seq; |
d828199e | 2780 | int mode; |
cbcf2dd3 | 2781 | u64 ns; |
d828199e | 2782 | |
d828199e MT |
2783 | do { |
2784 | seq = read_seqcount_begin(>od->seq); | |
917f9475 | 2785 | ns = gtod->raw_clock.base_cycles; |
53fafdbb | 2786 | ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode); |
917f9475 PB |
2787 | ns >>= gtod->raw_clock.shift; |
2788 | ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot)); | |
d828199e | 2789 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); |
cbcf2dd3 | 2790 | *t = ns; |
d828199e MT |
2791 | |
2792 | return mode; | |
2793 | } | |
2794 | ||
899a31f5 | 2795 | static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp) |
55dd00a7 MT |
2796 | { |
2797 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
2798 | unsigned long seq; | |
2799 | int mode; | |
2800 | u64 ns; | |
2801 | ||
2802 | do { | |
2803 | seq = read_seqcount_begin(>od->seq); | |
55dd00a7 | 2804 | ts->tv_sec = gtod->wall_time_sec; |
917f9475 | 2805 | ns = gtod->clock.base_cycles; |
53fafdbb | 2806 | ns += vgettsc(>od->clock, tsc_timestamp, &mode); |
55dd00a7 MT |
2807 | ns >>= gtod->clock.shift; |
2808 | } while (unlikely(read_seqcount_retry(>od->seq, seq))); | |
2809 | ||
2810 | ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); | |
2811 | ts->tv_nsec = ns; | |
2812 | ||
2813 | return mode; | |
2814 | } | |
2815 | ||
b0c39dc6 VK |
2816 | /* returns true if host is using TSC based clocksource */ |
2817 | static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp) | |
d828199e | 2818 | { |
d828199e | 2819 | /* checked again under seqlock below */ |
b0c39dc6 | 2820 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
d828199e MT |
2821 | return false; |
2822 | ||
53fafdbb | 2823 | return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns, |
b0c39dc6 | 2824 | tsc_timestamp)); |
d828199e | 2825 | } |
55dd00a7 | 2826 | |
b0c39dc6 | 2827 | /* returns true if host is using TSC based clocksource */ |
899a31f5 | 2828 | static bool kvm_get_walltime_and_clockread(struct timespec64 *ts, |
b0c39dc6 | 2829 | u64 *tsc_timestamp) |
55dd00a7 MT |
2830 | { |
2831 | /* checked again under seqlock below */ | |
b0c39dc6 | 2832 | if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode)) |
55dd00a7 MT |
2833 | return false; |
2834 | ||
b0c39dc6 | 2835 | return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp)); |
55dd00a7 | 2836 | } |
d828199e MT |
2837 | #endif |
2838 | ||
2839 | /* | |
2840 | * | |
b48aa97e MT |
2841 | * Assuming a stable TSC across physical CPUS, and a stable TSC |
2842 | * across virtual CPUs, the following condition is possible. | |
2843 | * Each numbered line represents an event visible to both | |
d828199e MT |
2844 | * CPUs at the next numbered event. |
2845 | * | |
2846 | * "timespecX" represents host monotonic time. "tscX" represents | |
2847 | * RDTSC value. | |
2848 | * | |
2849 | * VCPU0 on CPU0 | VCPU1 on CPU1 | |
2850 | * | |
2851 | * 1. read timespec0,tsc0 | |
2852 | * 2. | timespec1 = timespec0 + N | |
2853 | * | tsc1 = tsc0 + M | |
2854 | * 3. transition to guest | transition to guest | |
2855 | * 4. ret0 = timespec0 + (rdtsc - tsc0) | | |
2856 | * 5. | ret1 = timespec1 + (rdtsc - tsc1) | |
2857 | * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M)) | |
2858 | * | |
2859 | * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity: | |
2860 | * | |
2861 | * - ret0 < ret1 | |
2862 | * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M)) | |
2863 | * ... | |
2864 | * - 0 < N - M => M < N | |
2865 | * | |
2866 | * That is, when timespec0 != timespec1, M < N. Unfortunately that is not | |
2867 | * always the case (the difference between two distinct xtime instances | |
2868 | * might be smaller then the difference between corresponding TSC reads, | |
2869 | * when updating guest vcpus pvclock areas). | |
2870 | * | |
2871 | * To avoid that problem, do not allow visibility of distinct | |
2872 | * system_timestamp/tsc_timestamp values simultaneously: use a master | |
2873 | * copy of host monotonic time values. Update that master copy | |
2874 | * in lockstep. | |
2875 | * | |
b48aa97e | 2876 | * Rely on synchronization of host TSCs and guest TSCs for monotonicity. |
d828199e MT |
2877 | * |
2878 | */ | |
2879 | ||
2880 | static void pvclock_update_vm_gtod_copy(struct kvm *kvm) | |
2881 | { | |
2882 | #ifdef CONFIG_X86_64 | |
2883 | struct kvm_arch *ka = &kvm->arch; | |
2884 | int vclock_mode; | |
b48aa97e MT |
2885 | bool host_tsc_clocksource, vcpus_matched; |
2886 | ||
869b4421 | 2887 | lockdep_assert_held(&kvm->arch.tsc_write_lock); |
b48aa97e MT |
2888 | vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 == |
2889 | atomic_read(&kvm->online_vcpus)); | |
d828199e MT |
2890 | |
2891 | /* | |
2892 | * If the host uses TSC clock, then passthrough TSC as stable | |
2893 | * to the guest. | |
2894 | */ | |
b48aa97e | 2895 | host_tsc_clocksource = kvm_get_time_and_clockread( |
d828199e MT |
2896 | &ka->master_kernel_ns, |
2897 | &ka->master_cycle_now); | |
2898 | ||
16a96021 | 2899 | ka->use_master_clock = host_tsc_clocksource && vcpus_matched |
a826faf1 | 2900 | && !ka->backwards_tsc_observed |
54750f2c | 2901 | && !ka->boot_vcpu_runs_old_kvmclock; |
b48aa97e | 2902 | |
d828199e MT |
2903 | if (ka->use_master_clock) |
2904 | atomic_set(&kvm_guest_has_master_clock, 1); | |
2905 | ||
2906 | vclock_mode = pvclock_gtod_data.clock.vclock_mode; | |
b48aa97e MT |
2907 | trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode, |
2908 | vcpus_matched); | |
d828199e MT |
2909 | #endif |
2910 | } | |
2911 | ||
6b6fcd28 | 2912 | static void kvm_make_mclock_inprogress_request(struct kvm *kvm) |
2860c4b1 PB |
2913 | { |
2914 | kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS); | |
2915 | } | |
2916 | ||
869b4421 | 2917 | static void __kvm_start_pvclock_update(struct kvm *kvm) |
2e762ff7 | 2918 | { |
869b4421 PB |
2919 | raw_spin_lock_irq(&kvm->arch.tsc_write_lock); |
2920 | write_seqcount_begin(&kvm->arch.pvclock_sc); | |
2921 | } | |
e880c6ea | 2922 | |
869b4421 PB |
2923 | static void kvm_start_pvclock_update(struct kvm *kvm) |
2924 | { | |
2e762ff7 | 2925 | kvm_make_mclock_inprogress_request(kvm); |
c2c647f9 | 2926 | |
2e762ff7 | 2927 | /* no guest entries from this point */ |
869b4421 | 2928 | __kvm_start_pvclock_update(kvm); |
6b6fcd28 | 2929 | } |
2e762ff7 | 2930 | |
6b6fcd28 PB |
2931 | static void kvm_end_pvclock_update(struct kvm *kvm) |
2932 | { | |
2933 | struct kvm_arch *ka = &kvm->arch; | |
2934 | struct kvm_vcpu *vcpu; | |
46808a4c | 2935 | unsigned long i; |
2e762ff7 | 2936 | |
869b4421 PB |
2937 | write_seqcount_end(&ka->pvclock_sc); |
2938 | raw_spin_unlock_irq(&ka->tsc_write_lock); | |
2e762ff7 | 2939 | kvm_for_each_vcpu(i, vcpu, kvm) |
105b21bb | 2940 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
2e762ff7 MT |
2941 | |
2942 | /* guest entries allowed */ | |
2943 | kvm_for_each_vcpu(i, vcpu, kvm) | |
72875d8a | 2944 | kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu); |
2e762ff7 MT |
2945 | } |
2946 | ||
6b6fcd28 PB |
2947 | static void kvm_update_masterclock(struct kvm *kvm) |
2948 | { | |
42dcbe7d | 2949 | kvm_hv_request_tsc_page_update(kvm); |
6b6fcd28 PB |
2950 | kvm_start_pvclock_update(kvm); |
2951 | pvclock_update_vm_gtod_copy(kvm); | |
2952 | kvm_end_pvclock_update(kvm); | |
2e762ff7 MT |
2953 | } |
2954 | ||
869b4421 PB |
2955 | /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */ |
2956 | static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) | |
108b249c | 2957 | { |
108b249c | 2958 | struct kvm_arch *ka = &kvm->arch; |
8b953440 | 2959 | struct pvclock_vcpu_time_info hv_clock; |
8b953440 | 2960 | |
e2c2206a WL |
2961 | /* both __this_cpu_read() and rdtsc() should be on the same cpu */ |
2962 | get_cpu(); | |
2963 | ||
869b4421 PB |
2964 | data->flags = 0; |
2965 | if (ka->use_master_clock && __this_cpu_read(cpu_tsc_khz)) { | |
c68dc1b5 OU |
2966 | #ifdef CONFIG_X86_64 |
2967 | struct timespec64 ts; | |
2968 | ||
2969 | if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) { | |
2970 | data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec; | |
2971 | data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC; | |
2972 | } else | |
2973 | #endif | |
2974 | data->host_tsc = rdtsc(); | |
2975 | ||
869b4421 PB |
2976 | data->flags |= KVM_CLOCK_TSC_STABLE; |
2977 | hv_clock.tsc_timestamp = ka->master_cycle_now; | |
2978 | hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset; | |
e70b57a6 WL |
2979 | kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL, |
2980 | &hv_clock.tsc_shift, | |
2981 | &hv_clock.tsc_to_system_mul); | |
c68dc1b5 | 2982 | data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc); |
55c0cefb OU |
2983 | } else { |
2984 | data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset; | |
2985 | } | |
e2c2206a WL |
2986 | |
2987 | put_cpu(); | |
55c0cefb | 2988 | } |
e2c2206a | 2989 | |
869b4421 PB |
2990 | static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data) |
2991 | { | |
2992 | struct kvm_arch *ka = &kvm->arch; | |
2993 | unsigned seq; | |
2994 | ||
2995 | do { | |
2996 | seq = read_seqcount_begin(&ka->pvclock_sc); | |
2997 | __get_kvmclock(kvm, data); | |
2998 | } while (read_seqcount_retry(&ka->pvclock_sc, seq)); | |
2999 | } | |
3000 | ||
55c0cefb OU |
3001 | u64 get_kvmclock_ns(struct kvm *kvm) |
3002 | { | |
3003 | struct kvm_clock_data data; | |
3004 | ||
55c0cefb OU |
3005 | get_kvmclock(kvm, &data); |
3006 | return data.clock; | |
108b249c PB |
3007 | } |
3008 | ||
916d3608 DW |
3009 | static void kvm_setup_guest_pvclock(struct kvm_vcpu *v, |
3010 | struct gfn_to_pfn_cache *gpc, | |
3011 | unsigned int offset) | |
0d6dd2ff PB |
3012 | { |
3013 | struct kvm_vcpu_arch *vcpu = &v->arch; | |
916d3608 DW |
3014 | struct pvclock_vcpu_time_info *guest_hv_clock; |
3015 | unsigned long flags; | |
0d6dd2ff | 3016 | |
916d3608 DW |
3017 | read_lock_irqsave(&gpc->lock, flags); |
3018 | while (!kvm_gfn_to_pfn_cache_check(v->kvm, gpc, gpc->gpa, | |
3019 | offset + sizeof(*guest_hv_clock))) { | |
3020 | read_unlock_irqrestore(&gpc->lock, flags); | |
3021 | ||
3022 | if (kvm_gfn_to_pfn_cache_refresh(v->kvm, gpc, gpc->gpa, | |
3023 | offset + sizeof(*guest_hv_clock))) | |
3024 | return; | |
0d6dd2ff | 3025 | |
916d3608 DW |
3026 | read_lock_irqsave(&gpc->lock, flags); |
3027 | } | |
3028 | ||
3029 | guest_hv_clock = (void *)(gpc->khva + offset); | |
3030 | ||
3031 | /* | |
3032 | * This VCPU is paused, but it's legal for a guest to read another | |
0d6dd2ff PB |
3033 | * VCPU's kvmclock, so we really have to follow the specification where |
3034 | * it says that version is odd if data is being modified, and even after | |
3035 | * it is consistent. | |
0d6dd2ff | 3036 | */ |
0d6dd2ff | 3037 | |
916d3608 | 3038 | guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1; |
0d6dd2ff PB |
3039 | smp_wmb(); |
3040 | ||
3041 | /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */ | |
916d3608 | 3042 | vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED); |
0d6dd2ff PB |
3043 | |
3044 | if (vcpu->pvclock_set_guest_stopped_request) { | |
3045 | vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED; | |
3046 | vcpu->pvclock_set_guest_stopped_request = false; | |
3047 | } | |
3048 | ||
916d3608 DW |
3049 | memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock)); |
3050 | smp_wmb(); | |
0d6dd2ff | 3051 | |
916d3608 | 3052 | guest_hv_clock->version = ++vcpu->hv_clock.version; |
0d6dd2ff | 3053 | |
916d3608 DW |
3054 | mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT); |
3055 | read_unlock_irqrestore(&gpc->lock, flags); | |
0d6dd2ff | 3056 | |
916d3608 | 3057 | trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock); |
0d6dd2ff PB |
3058 | } |
3059 | ||
34c238a1 | 3060 | static int kvm_guest_time_update(struct kvm_vcpu *v) |
18068523 | 3061 | { |
78db6a50 | 3062 | unsigned long flags, tgt_tsc_khz; |
869b4421 | 3063 | unsigned seq; |
18068523 | 3064 | struct kvm_vcpu_arch *vcpu = &v->arch; |
d828199e | 3065 | struct kvm_arch *ka = &v->kvm->arch; |
f25e656d | 3066 | s64 kernel_ns; |
d828199e | 3067 | u64 tsc_timestamp, host_tsc; |
51d59c6b | 3068 | u8 pvclock_flags; |
d828199e MT |
3069 | bool use_master_clock; |
3070 | ||
3071 | kernel_ns = 0; | |
3072 | host_tsc = 0; | |
18068523 | 3073 | |
d828199e MT |
3074 | /* |
3075 | * If the host uses TSC clock, then passthrough TSC as stable | |
3076 | * to the guest. | |
3077 | */ | |
869b4421 PB |
3078 | do { |
3079 | seq = read_seqcount_begin(&ka->pvclock_sc); | |
3080 | use_master_clock = ka->use_master_clock; | |
3081 | if (use_master_clock) { | |
3082 | host_tsc = ka->master_cycle_now; | |
3083 | kernel_ns = ka->master_kernel_ns; | |
3084 | } | |
3085 | } while (read_seqcount_retry(&ka->pvclock_sc, seq)); | |
c09664bb MT |
3086 | |
3087 | /* Keep irq disabled to prevent changes to the clock */ | |
3088 | local_irq_save(flags); | |
78db6a50 PB |
3089 | tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz); |
3090 | if (unlikely(tgt_tsc_khz == 0)) { | |
c09664bb MT |
3091 | local_irq_restore(flags); |
3092 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); | |
3093 | return 1; | |
3094 | } | |
d828199e | 3095 | if (!use_master_clock) { |
4ea1636b | 3096 | host_tsc = rdtsc(); |
8171cd68 | 3097 | kernel_ns = get_kvmclock_base_ns(); |
d828199e MT |
3098 | } |
3099 | ||
4ba76538 | 3100 | tsc_timestamp = kvm_read_l1_tsc(v, host_tsc); |
d828199e | 3101 | |
c285545f ZA |
3102 | /* |
3103 | * We may have to catch up the TSC to match elapsed wall clock | |
3104 | * time for two reasons, even if kvmclock is used. | |
3105 | * 1) CPU could have been running below the maximum TSC rate | |
3106 | * 2) Broken TSC compensation resets the base at each VCPU | |
3107 | * entry to avoid unknown leaps of TSC even when running | |
3108 | * again on the same CPU. This may cause apparent elapsed | |
3109 | * time to disappear, and the guest to stand still or run | |
3110 | * very slowly. | |
3111 | */ | |
3112 | if (vcpu->tsc_catchup) { | |
3113 | u64 tsc = compute_guest_tsc(v, kernel_ns); | |
3114 | if (tsc > tsc_timestamp) { | |
f1e2b260 | 3115 | adjust_tsc_offset_guest(v, tsc - tsc_timestamp); |
c285545f ZA |
3116 | tsc_timestamp = tsc; |
3117 | } | |
50d0a0f9 GH |
3118 | } |
3119 | ||
18068523 GOC |
3120 | local_irq_restore(flags); |
3121 | ||
0d6dd2ff | 3122 | /* With all the info we got, fill in the values */ |
18068523 | 3123 | |
938c8745 | 3124 | if (kvm_caps.has_tsc_control) |
62711e5a | 3125 | tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz, |
fe3eb504 | 3126 | v->arch.l1_tsc_scaling_ratio); |
78db6a50 PB |
3127 | |
3128 | if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) { | |
3ae13faa | 3129 | kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL, |
5f4e3f88 ZA |
3130 | &vcpu->hv_clock.tsc_shift, |
3131 | &vcpu->hv_clock.tsc_to_system_mul); | |
78db6a50 | 3132 | vcpu->hw_tsc_khz = tgt_tsc_khz; |
8cfdc000 ZA |
3133 | } |
3134 | ||
1d5f066e | 3135 | vcpu->hv_clock.tsc_timestamp = tsc_timestamp; |
759379dd | 3136 | vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset; |
28e4639a | 3137 | vcpu->last_guest_tsc = tsc_timestamp; |
51d59c6b | 3138 | |
d828199e | 3139 | /* If the host uses TSC clocksource, then it is stable */ |
0d6dd2ff | 3140 | pvclock_flags = 0; |
d828199e MT |
3141 | if (use_master_clock) |
3142 | pvclock_flags |= PVCLOCK_TSC_STABLE_BIT; | |
3143 | ||
78c0337a MT |
3144 | vcpu->hv_clock.flags = pvclock_flags; |
3145 | ||
916d3608 DW |
3146 | if (vcpu->pv_time.active) |
3147 | kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0); | |
7caf9571 DW |
3148 | if (vcpu->xen.vcpu_info_cache.active) |
3149 | kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache, | |
3150 | offsetof(struct compat_vcpu_info, time)); | |
69d413cf DW |
3151 | if (vcpu->xen.vcpu_time_info_cache.active) |
3152 | kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0); | |
42dcbe7d | 3153 | kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock); |
8cfdc000 | 3154 | return 0; |
c8076604 GH |
3155 | } |
3156 | ||
0061d53d MT |
3157 | /* |
3158 | * kvmclock updates which are isolated to a given vcpu, such as | |
3159 | * vcpu->cpu migration, should not allow system_timestamp from | |
3160 | * the rest of the vcpus to remain static. Otherwise ntp frequency | |
3161 | * correction applies to one vcpu's system_timestamp but not | |
3162 | * the others. | |
3163 | * | |
3164 | * So in those cases, request a kvmclock update for all vcpus. | |
7e44e449 AJ |
3165 | * We need to rate-limit these requests though, as they can |
3166 | * considerably slow guests that have a large number of vcpus. | |
3167 | * The time for a remote vcpu to update its kvmclock is bound | |
3168 | * by the delay we use to rate-limit the updates. | |
0061d53d MT |
3169 | */ |
3170 | ||
7e44e449 AJ |
3171 | #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100) |
3172 | ||
3173 | static void kvmclock_update_fn(struct work_struct *work) | |
0061d53d | 3174 | { |
46808a4c | 3175 | unsigned long i; |
7e44e449 AJ |
3176 | struct delayed_work *dwork = to_delayed_work(work); |
3177 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
3178 | kvmclock_update_work); | |
3179 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
0061d53d MT |
3180 | struct kvm_vcpu *vcpu; |
3181 | ||
3182 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
105b21bb | 3183 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0061d53d MT |
3184 | kvm_vcpu_kick(vcpu); |
3185 | } | |
3186 | } | |
3187 | ||
7e44e449 AJ |
3188 | static void kvm_gen_kvmclock_update(struct kvm_vcpu *v) |
3189 | { | |
3190 | struct kvm *kvm = v->kvm; | |
3191 | ||
105b21bb | 3192 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, v); |
7e44e449 AJ |
3193 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, |
3194 | KVMCLOCK_UPDATE_DELAY); | |
3195 | } | |
3196 | ||
332967a3 AJ |
3197 | #define KVMCLOCK_SYNC_PERIOD (300 * HZ) |
3198 | ||
3199 | static void kvmclock_sync_fn(struct work_struct *work) | |
3200 | { | |
3201 | struct delayed_work *dwork = to_delayed_work(work); | |
3202 | struct kvm_arch *ka = container_of(dwork, struct kvm_arch, | |
3203 | kvmclock_sync_work); | |
3204 | struct kvm *kvm = container_of(ka, struct kvm, arch); | |
3205 | ||
630994b3 MT |
3206 | if (!kvmclock_periodic_sync) |
3207 | return; | |
3208 | ||
332967a3 AJ |
3209 | schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0); |
3210 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
3211 | KVMCLOCK_SYNC_PERIOD); | |
3212 | } | |
3213 | ||
281b5278 JW |
3214 | /* These helpers are safe iff @msr is known to be an MCx bank MSR. */ |
3215 | static bool is_mci_control_msr(u32 msr) | |
3216 | { | |
3217 | return (msr & 3) == 0; | |
3218 | } | |
3219 | static bool is_mci_status_msr(u32 msr) | |
3220 | { | |
3221 | return (msr & 3) == 1; | |
3222 | } | |
3223 | ||
191c8137 BP |
3224 | /* |
3225 | * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP. | |
3226 | */ | |
3227 | static bool can_set_mci_status(struct kvm_vcpu *vcpu) | |
3228 | { | |
3229 | /* McStatusWrEn enabled? */ | |
23493d0a | 3230 | if (guest_cpuid_is_amd_or_hygon(vcpu)) |
191c8137 BP |
3231 | return !!(vcpu->arch.msr_hwcr & BIT_ULL(18)); |
3232 | ||
3233 | return false; | |
3234 | } | |
3235 | ||
9ffd986c | 3236 | static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3237 | { |
890ca9ae HY |
3238 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3239 | unsigned bank_num = mcg_cap & 0xff; | |
9ffd986c WL |
3240 | u32 msr = msr_info->index; |
3241 | u64 data = msr_info->data; | |
281b5278 | 3242 | u32 offset, last_msr; |
890ca9ae | 3243 | |
15c4a640 | 3244 | switch (msr) { |
15c4a640 | 3245 | case MSR_IA32_MCG_STATUS: |
890ca9ae | 3246 | vcpu->arch.mcg_status = data; |
15c4a640 | 3247 | break; |
c7ac679c | 3248 | case MSR_IA32_MCG_CTL: |
44883f01 PB |
3249 | if (!(mcg_cap & MCG_CTL_P) && |
3250 | (data || !msr_info->host_initiated)) | |
890ca9ae HY |
3251 | return 1; |
3252 | if (data != 0 && data != ~(u64)0) | |
44883f01 | 3253 | return 1; |
890ca9ae HY |
3254 | vcpu->arch.mcg_ctl = data; |
3255 | break; | |
281b5278 JW |
3256 | case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: |
3257 | last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1; | |
3258 | if (msr > last_msr) | |
3259 | return 1; | |
191c8137 | 3260 | |
281b5278 JW |
3261 | if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated)) |
3262 | return 1; | |
3263 | /* An attempt to write a 1 to a reserved bit raises #GP */ | |
3264 | if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK)) | |
3265 | return 1; | |
3266 | offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2, | |
3267 | last_msr + 1 - MSR_IA32_MC0_CTL2); | |
3268 | vcpu->arch.mci_ctl2_banks[offset] = data; | |
3269 | break; | |
3270 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: | |
3271 | last_msr = MSR_IA32_MCx_CTL(bank_num) - 1; | |
3272 | if (msr > last_msr) | |
3273 | return 1; | |
3274 | ||
3275 | /* | |
3276 | * Only 0 or all 1s can be written to IA32_MCi_CTL, all other | |
3277 | * values are architecturally undefined. But, some Linux | |
3278 | * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB | |
3279 | * issue on AMD K8s, allow bit 10 to be clear when setting all | |
3280 | * other bits in order to avoid an uncaught #GP in the guest. | |
f5223a33 SC |
3281 | * |
3282 | * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable, | |
3283 | * single-bit ECC data errors. | |
281b5278 JW |
3284 | */ |
3285 | if (is_mci_control_msr(msr) && | |
3286 | data != 0 && (data | (1 << 10) | 1) != ~(u64)0) | |
3287 | return 1; | |
191c8137 | 3288 | |
281b5278 JW |
3289 | /* |
3290 | * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR. | |
3291 | * AMD-based CPUs allow non-zero values, but if and only if | |
3292 | * HWCR[McStatusWrEn] is set. | |
3293 | */ | |
3294 | if (!msr_info->host_initiated && is_mci_status_msr(msr) && | |
3295 | data != 0 && !can_set_mci_status(vcpu)) | |
3296 | return 1; | |
3297 | ||
3298 | offset = array_index_nospec(msr - MSR_IA32_MC0_CTL, | |
3299 | last_msr + 1 - MSR_IA32_MC0_CTL); | |
3300 | vcpu->arch.mce_banks[offset] = data; | |
3301 | break; | |
3302 | default: | |
890ca9ae HY |
3303 | return 1; |
3304 | } | |
3305 | return 0; | |
3306 | } | |
3307 | ||
2635b5c4 VK |
3308 | static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu) |
3309 | { | |
3310 | u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT; | |
3311 | ||
3312 | return (vcpu->arch.apf.msr_en_val & mask) == mask; | |
3313 | } | |
3314 | ||
344d9588 GN |
3315 | static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data) |
3316 | { | |
3317 | gpa_t gpa = data & ~0x3f; | |
3318 | ||
2635b5c4 VK |
3319 | /* Bits 4:5 are reserved, Should be zero */ |
3320 | if (data & 0x30) | |
344d9588 GN |
3321 | return 1; |
3322 | ||
66570e96 OU |
3323 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) && |
3324 | (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT)) | |
3325 | return 1; | |
3326 | ||
3327 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) && | |
3328 | (data & KVM_ASYNC_PF_DELIVERY_AS_INT)) | |
3329 | return 1; | |
3330 | ||
9d3c447c | 3331 | if (!lapic_in_kernel(vcpu)) |
d831de17 | 3332 | return data ? 1 : 0; |
9d3c447c | 3333 | |
2635b5c4 | 3334 | vcpu->arch.apf.msr_en_val = data; |
344d9588 | 3335 | |
2635b5c4 | 3336 | if (!kvm_pv_async_pf_enabled(vcpu)) { |
344d9588 GN |
3337 | kvm_clear_async_pf_completion_queue(vcpu); |
3338 | kvm_async_pf_hash_reset(vcpu); | |
3339 | return 0; | |
3340 | } | |
3341 | ||
4e335d9e | 3342 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa, |
68fd66f1 | 3343 | sizeof(u64))) |
344d9588 GN |
3344 | return 1; |
3345 | ||
6adba527 | 3346 | vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS); |
52a5c155 | 3347 | vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT; |
2635b5c4 | 3348 | |
344d9588 | 3349 | kvm_async_pf_wakeup_all(vcpu); |
2635b5c4 VK |
3350 | |
3351 | return 0; | |
3352 | } | |
3353 | ||
3354 | static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data) | |
3355 | { | |
3356 | /* Bits 8-63 are reserved */ | |
3357 | if (data >> 8) | |
3358 | return 1; | |
3359 | ||
3360 | if (!lapic_in_kernel(vcpu)) | |
3361 | return 1; | |
3362 | ||
3363 | vcpu->arch.apf.msr_int_val = data; | |
3364 | ||
3365 | vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK; | |
3366 | ||
344d9588 GN |
3367 | return 0; |
3368 | } | |
3369 | ||
12f9a48f GC |
3370 | static void kvmclock_reset(struct kvm_vcpu *vcpu) |
3371 | { | |
916d3608 | 3372 | kvm_gfn_to_pfn_cache_destroy(vcpu->kvm, &vcpu->arch.pv_time); |
49dedf0d | 3373 | vcpu->arch.time = 0; |
12f9a48f GC |
3374 | } |
3375 | ||
7780938c | 3376 | static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu) |
f38a7b75 WL |
3377 | { |
3378 | ++vcpu->stat.tlb_flush; | |
e27bc044 | 3379 | static_call(kvm_x86_flush_tlb_all)(vcpu); |
f38a7b75 WL |
3380 | } |
3381 | ||
0baedd79 VK |
3382 | static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu) |
3383 | { | |
3384 | ++vcpu->stat.tlb_flush; | |
b53e84ee LJ |
3385 | |
3386 | if (!tdp_enabled) { | |
61b05a9f | 3387 | /* |
b53e84ee LJ |
3388 | * A TLB flush on behalf of the guest is equivalent to |
3389 | * INVPCID(all), toggling CR4.PGE, etc., which requires | |
61b05a9f LJ |
3390 | * a forced sync of the shadow page tables. Ensure all the |
3391 | * roots are synced and the guest TLB in hardware is clean. | |
b53e84ee | 3392 | */ |
61b05a9f LJ |
3393 | kvm_mmu_sync_roots(vcpu); |
3394 | kvm_mmu_sync_prev_roots(vcpu); | |
b53e84ee LJ |
3395 | } |
3396 | ||
e27bc044 | 3397 | static_call(kvm_x86_flush_tlb_guest)(vcpu); |
0baedd79 VK |
3398 | } |
3399 | ||
40e5f908 SC |
3400 | |
3401 | static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu) | |
3402 | { | |
3403 | ++vcpu->stat.tlb_flush; | |
e27bc044 | 3404 | static_call(kvm_x86_flush_tlb_current)(vcpu); |
40e5f908 SC |
3405 | } |
3406 | ||
3407 | /* | |
3408 | * Service "local" TLB flush requests, which are specific to the current MMU | |
3409 | * context. In addition to the generic event handling in vcpu_enter_guest(), | |
3410 | * TLB flushes that are targeted at an MMU context also need to be serviced | |
3411 | * prior before nested VM-Enter/VM-Exit. | |
3412 | */ | |
3413 | void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu) | |
3414 | { | |
3415 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu)) | |
3416 | kvm_vcpu_flush_tlb_current(vcpu); | |
3417 | ||
3418 | if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu)) | |
3419 | kvm_vcpu_flush_tlb_guest(vcpu); | |
3420 | } | |
3421 | EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests); | |
3422 | ||
c9aaa895 GC |
3423 | static void record_steal_time(struct kvm_vcpu *vcpu) |
3424 | { | |
7e2175eb DW |
3425 | struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; |
3426 | struct kvm_steal_time __user *st; | |
3427 | struct kvm_memslots *slots; | |
901d3765 | 3428 | gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; |
7e2175eb DW |
3429 | u64 steal; |
3430 | u32 version; | |
b0431382 | 3431 | |
30b5c851 DW |
3432 | if (kvm_xen_msr_enabled(vcpu->kvm)) { |
3433 | kvm_xen_runstate_set_running(vcpu); | |
3434 | return; | |
3435 | } | |
3436 | ||
c9aaa895 GC |
3437 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
3438 | return; | |
3439 | ||
7e2175eb | 3440 | if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm)) |
c9aaa895 GC |
3441 | return; |
3442 | ||
7e2175eb DW |
3443 | slots = kvm_memslots(vcpu->kvm); |
3444 | ||
3445 | if (unlikely(slots->generation != ghc->generation || | |
901d3765 | 3446 | gpa != ghc->gpa || |
7e2175eb | 3447 | kvm_is_error_hva(ghc->hva) || !ghc->memslot)) { |
7e2175eb DW |
3448 | /* We rely on the fact that it fits in a single page. */ |
3449 | BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS); | |
3450 | ||
901d3765 | 3451 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) || |
7e2175eb DW |
3452 | kvm_is_error_hva(ghc->hva) || !ghc->memslot) |
3453 | return; | |
3454 | } | |
3455 | ||
3456 | st = (struct kvm_steal_time __user *)ghc->hva; | |
f38a7b75 WL |
3457 | /* |
3458 | * Doing a TLB flush here, on the guest's behalf, can avoid | |
3459 | * expensive IPIs. | |
3460 | */ | |
66570e96 | 3461 | if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) { |
7e2175eb DW |
3462 | u8 st_preempted = 0; |
3463 | int err = -EFAULT; | |
3464 | ||
3e067fd8 PB |
3465 | if (!user_access_begin(st, sizeof(*st))) |
3466 | return; | |
3467 | ||
7e2175eb DW |
3468 | asm volatile("1: xchgb %0, %2\n" |
3469 | "xor %1, %1\n" | |
3470 | "2:\n" | |
3471 | _ASM_EXTABLE_UA(1b, 2b) | |
964b7aa0 DW |
3472 | : "+q" (st_preempted), |
3473 | "+&r" (err), | |
3474 | "+m" (st->preempted)); | |
7e2175eb DW |
3475 | if (err) |
3476 | goto out; | |
3477 | ||
3478 | user_access_end(); | |
3479 | ||
3480 | vcpu->arch.st.preempted = 0; | |
af3511ff | 3481 | |
66570e96 | 3482 | trace_kvm_pv_tlb_flush(vcpu->vcpu_id, |
af3511ff LJ |
3483 | st_preempted & KVM_VCPU_FLUSH_TLB); |
3484 | if (st_preempted & KVM_VCPU_FLUSH_TLB) | |
66570e96 | 3485 | kvm_vcpu_flush_tlb_guest(vcpu); |
7e2175eb DW |
3486 | |
3487 | if (!user_access_begin(st, sizeof(*st))) | |
3488 | goto dirty; | |
1eff0ada | 3489 | } else { |
3e067fd8 PB |
3490 | if (!user_access_begin(st, sizeof(*st))) |
3491 | return; | |
3492 | ||
7e2175eb DW |
3493 | unsafe_put_user(0, &st->preempted, out); |
3494 | vcpu->arch.st.preempted = 0; | |
66570e96 | 3495 | } |
0b9f6c46 | 3496 | |
7e2175eb DW |
3497 | unsafe_get_user(version, &st->version, out); |
3498 | if (version & 1) | |
3499 | version += 1; /* first time write, random junk */ | |
35f3fae1 | 3500 | |
7e2175eb DW |
3501 | version += 1; |
3502 | unsafe_put_user(version, &st->version, out); | |
35f3fae1 WL |
3503 | |
3504 | smp_wmb(); | |
3505 | ||
7e2175eb DW |
3506 | unsafe_get_user(steal, &st->steal, out); |
3507 | steal += current->sched_info.run_delay - | |
c54cdf14 LC |
3508 | vcpu->arch.st.last_steal; |
3509 | vcpu->arch.st.last_steal = current->sched_info.run_delay; | |
7e2175eb | 3510 | unsafe_put_user(steal, &st->steal, out); |
35f3fae1 | 3511 | |
7e2175eb DW |
3512 | version += 1; |
3513 | unsafe_put_user(version, &st->version, out); | |
35f3fae1 | 3514 | |
7e2175eb DW |
3515 | out: |
3516 | user_access_end(); | |
3517 | dirty: | |
3518 | mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); | |
c9aaa895 GC |
3519 | } |
3520 | ||
8fe8ab46 | 3521 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
15c4a640 | 3522 | { |
5753785f | 3523 | bool pr = false; |
8fe8ab46 WA |
3524 | u32 msr = msr_info->index; |
3525 | u64 data = msr_info->data; | |
5753785f | 3526 | |
1232f8e6 | 3527 | if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr) |
23200b7a | 3528 | return kvm_xen_write_hypercall_page(vcpu, data); |
1232f8e6 | 3529 | |
15c4a640 | 3530 | switch (msr) { |
2e32b719 | 3531 | case MSR_AMD64_NB_CFG: |
2e32b719 BP |
3532 | case MSR_IA32_UCODE_WRITE: |
3533 | case MSR_VM_HSAVE_PA: | |
3534 | case MSR_AMD64_PATCH_LOADER: | |
3535 | case MSR_AMD64_BU_CFG2: | |
405a353a | 3536 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3537 | case MSR_F15H_EX_CFG: |
2e32b719 BP |
3538 | break; |
3539 | ||
518e7b94 WL |
3540 | case MSR_IA32_UCODE_REV: |
3541 | if (msr_info->host_initiated) | |
3542 | vcpu->arch.microcode_version = data; | |
3543 | break; | |
0cf9135b SC |
3544 | case MSR_IA32_ARCH_CAPABILITIES: |
3545 | if (!msr_info->host_initiated) | |
3546 | return 1; | |
3547 | vcpu->arch.arch_capabilities = data; | |
3548 | break; | |
d574c539 VK |
3549 | case MSR_IA32_PERF_CAPABILITIES: { |
3550 | struct kvm_msr_entry msr_ent = {.index = msr, .data = 0}; | |
3551 | ||
3552 | if (!msr_info->host_initiated) | |
3553 | return 1; | |
1aa2abb3 | 3554 | if (kvm_get_msr_feature(&msr_ent)) |
d574c539 VK |
3555 | return 1; |
3556 | if (data & ~msr_ent.data) | |
3557 | return 1; | |
3558 | ||
3559 | vcpu->arch.perf_capabilities = data; | |
17a024a8 | 3560 | kvm_pmu_refresh(vcpu); |
d574c539 | 3561 | return 0; |
17a024a8 | 3562 | } |
15c4a640 | 3563 | case MSR_EFER: |
11988499 | 3564 | return set_efer(vcpu, msr_info); |
8f1589d9 AP |
3565 | case MSR_K7_HWCR: |
3566 | data &= ~(u64)0x40; /* ignore flush filter disable */ | |
82494028 | 3567 | data &= ~(u64)0x100; /* ignore ignne emulation enable */ |
a223c313 | 3568 | data &= ~(u64)0x8; /* ignore TLB cache disable */ |
191c8137 BP |
3569 | |
3570 | /* Handle McStatusWrEn */ | |
3571 | if (data == BIT_ULL(18)) { | |
3572 | vcpu->arch.msr_hwcr = data; | |
3573 | } else if (data != 0) { | |
a737f256 CD |
3574 | vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n", |
3575 | data); | |
8f1589d9 AP |
3576 | return 1; |
3577 | } | |
15c4a640 | 3578 | break; |
f7c6d140 AP |
3579 | case MSR_FAM10H_MMIO_CONF_BASE: |
3580 | if (data != 0) { | |
a737f256 CD |
3581 | vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: " |
3582 | "0x%llx\n", data); | |
f7c6d140 AP |
3583 | return 1; |
3584 | } | |
15c4a640 | 3585 | break; |
281b5278 JW |
3586 | case 0x200 ... MSR_IA32_MC0_CTL2 - 1: |
3587 | case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff: | |
ff53604b | 3588 | return kvm_mtrr_set_msr(vcpu, msr, data); |
15c4a640 | 3589 | case MSR_IA32_APICBASE: |
58cb628d | 3590 | return kvm_set_apic_base(vcpu, msr_info); |
bf10bd0b | 3591 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
0105d1a5 | 3592 | return kvm_x2apic_msr_write(vcpu, msr, data); |
09141ec0 | 3593 | case MSR_IA32_TSC_DEADLINE: |
a3e06bbe LJ |
3594 | kvm_set_lapic_tscdeadline_msr(vcpu, data); |
3595 | break; | |
ba904635 | 3596 | case MSR_IA32_TSC_ADJUST: |
d6321d49 | 3597 | if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) { |
ba904635 | 3598 | if (!msr_info->host_initiated) { |
d913b904 | 3599 | s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr; |
d7add054 | 3600 | adjust_tsc_offset_guest(vcpu, adj); |
d9130a2d ZD |
3601 | /* Before back to guest, tsc_timestamp must be adjusted |
3602 | * as well, otherwise guest's percpu pvclock time could jump. | |
3603 | */ | |
3604 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
ba904635 WA |
3605 | } |
3606 | vcpu->arch.ia32_tsc_adjust_msr = data; | |
3607 | } | |
3608 | break; | |
bef6ecca LX |
3609 | case MSR_IA32_MISC_ENABLE: { |
3610 | u64 old_val = vcpu->arch.ia32_misc_enable_msr; | |
d1055173 | 3611 | |
9fc22296 SC |
3612 | if (!msr_info->host_initiated) { |
3613 | /* RO bits */ | |
3614 | if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK) | |
3615 | return 1; | |
3616 | ||
3617 | /* R bits, i.e. writes are ignored, but don't fault. */ | |
3618 | data = data & ~MSR_IA32_MISC_ENABLE_EMON; | |
3619 | data |= old_val & MSR_IA32_MISC_ENABLE_EMON; | |
3620 | } | |
bef6ecca | 3621 | |
511a8556 | 3622 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) && |
bef6ecca | 3623 | ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) { |
511a8556 WL |
3624 | if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3)) |
3625 | return 1; | |
3626 | vcpu->arch.ia32_misc_enable_msr = data; | |
aedbaf4f | 3627 | kvm_update_cpuid_runtime(vcpu); |
511a8556 WL |
3628 | } else { |
3629 | vcpu->arch.ia32_misc_enable_msr = data; | |
3630 | } | |
15c4a640 | 3631 | break; |
bef6ecca | 3632 | } |
64d60670 PB |
3633 | case MSR_IA32_SMBASE: |
3634 | if (!msr_info->host_initiated) | |
3635 | return 1; | |
3636 | vcpu->arch.smbase = data; | |
3637 | break; | |
73f624f4 PB |
3638 | case MSR_IA32_POWER_CTL: |
3639 | vcpu->arch.msr_ia32_power_ctl = data; | |
3640 | break; | |
dd259935 | 3641 | case MSR_IA32_TSC: |
0c899c25 PB |
3642 | if (msr_info->host_initiated) { |
3643 | kvm_synchronize_tsc(vcpu, data); | |
3644 | } else { | |
9b399dfd | 3645 | u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset; |
0c899c25 PB |
3646 | adjust_tsc_offset_guest(vcpu, adj); |
3647 | vcpu->arch.ia32_tsc_adjust_msr += adj; | |
3648 | } | |
dd259935 | 3649 | break; |
864e2ab2 AL |
3650 | case MSR_IA32_XSS: |
3651 | if (!msr_info->host_initiated && | |
3652 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
3653 | return 1; | |
3654 | /* | |
a1bead2a SC |
3655 | * KVM supports exposing PT to the guest, but does not support |
3656 | * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than | |
3657 | * XSAVES/XRSTORS to save/restore PT MSRs. | |
864e2ab2 | 3658 | */ |
938c8745 | 3659 | if (data & ~kvm_caps.supported_xss) |
864e2ab2 AL |
3660 | return 1; |
3661 | vcpu->arch.ia32_xss = data; | |
4c282e51 | 3662 | kvm_update_cpuid_runtime(vcpu); |
864e2ab2 | 3663 | break; |
52797bf9 LA |
3664 | case MSR_SMI_COUNT: |
3665 | if (!msr_info->host_initiated) | |
3666 | return 1; | |
3667 | vcpu->arch.smi_count = data; | |
3668 | break; | |
11c6bffa | 3669 | case MSR_KVM_WALL_CLOCK_NEW: |
66570e96 OU |
3670 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3671 | return 1; | |
3672 | ||
629b5348 JM |
3673 | vcpu->kvm->arch.wall_clock = data; |
3674 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
66570e96 | 3675 | break; |
18068523 | 3676 | case MSR_KVM_WALL_CLOCK: |
66570e96 OU |
3677 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3678 | return 1; | |
3679 | ||
629b5348 JM |
3680 | vcpu->kvm->arch.wall_clock = data; |
3681 | kvm_write_wall_clock(vcpu->kvm, data, 0); | |
18068523 | 3682 | break; |
11c6bffa | 3683 | case MSR_KVM_SYSTEM_TIME_NEW: |
66570e96 OU |
3684 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
3685 | return 1; | |
3686 | ||
5b9bb0eb OU |
3687 | kvm_write_system_time(vcpu, data, false, msr_info->host_initiated); |
3688 | break; | |
3689 | case MSR_KVM_SYSTEM_TIME: | |
66570e96 OU |
3690 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
3691 | return 1; | |
3692 | ||
3693 | kvm_write_system_time(vcpu, data, true, msr_info->host_initiated); | |
18068523 | 3694 | break; |
344d9588 | 3695 | case MSR_KVM_ASYNC_PF_EN: |
66570e96 OU |
3696 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
3697 | return 1; | |
3698 | ||
344d9588 GN |
3699 | if (kvm_pv_enable_async_pf(vcpu, data)) |
3700 | return 1; | |
3701 | break; | |
2635b5c4 | 3702 | case MSR_KVM_ASYNC_PF_INT: |
66570e96 OU |
3703 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
3704 | return 1; | |
3705 | ||
2635b5c4 VK |
3706 | if (kvm_pv_enable_async_pf_int(vcpu, data)) |
3707 | return 1; | |
3708 | break; | |
557a961a | 3709 | case MSR_KVM_ASYNC_PF_ACK: |
0a31df68 | 3710 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
66570e96 | 3711 | return 1; |
557a961a VK |
3712 | if (data & 0x1) { |
3713 | vcpu->arch.apf.pageready_pending = false; | |
3714 | kvm_check_async_pf_completion(vcpu); | |
3715 | } | |
3716 | break; | |
c9aaa895 | 3717 | case MSR_KVM_STEAL_TIME: |
66570e96 OU |
3718 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
3719 | return 1; | |
c9aaa895 GC |
3720 | |
3721 | if (unlikely(!sched_info_on())) | |
3722 | return 1; | |
3723 | ||
3724 | if (data & KVM_STEAL_RESERVED_MASK) | |
3725 | return 1; | |
3726 | ||
c9aaa895 GC |
3727 | vcpu->arch.st.msr_val = data; |
3728 | ||
3729 | if (!(data & KVM_MSR_ENABLED)) | |
3730 | break; | |
3731 | ||
c9aaa895 GC |
3732 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
3733 | ||
3734 | break; | |
ae7a2a3f | 3735 | case MSR_KVM_PV_EOI_EN: |
66570e96 OU |
3736 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
3737 | return 1; | |
3738 | ||
77c3323f | 3739 | if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8))) |
ae7a2a3f MT |
3740 | return 1; |
3741 | break; | |
c9aaa895 | 3742 | |
2d5ba19b | 3743 | case MSR_KVM_POLL_CONTROL: |
66570e96 OU |
3744 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
3745 | return 1; | |
3746 | ||
2d5ba19b MT |
3747 | /* only enable bit supported */ |
3748 | if (data & (-1ULL << 1)) | |
3749 | return 1; | |
3750 | ||
3751 | vcpu->arch.msr_kvm_poll_control = data; | |
3752 | break; | |
3753 | ||
890ca9ae HY |
3754 | case MSR_IA32_MCG_CTL: |
3755 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 3756 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
281b5278 | 3757 | case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: |
9ffd986c | 3758 | return set_msr_mce(vcpu, msr_info); |
71db6023 | 3759 | |
6912ac32 WH |
3760 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: |
3761 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
df561f66 GS |
3762 | pr = true; |
3763 | fallthrough; | |
6912ac32 WH |
3764 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3765 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3766 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3767 | return kvm_pmu_set_msr(vcpu, msr_info); |
5753785f GN |
3768 | |
3769 | if (pr || data != 0) | |
a737f256 CD |
3770 | vcpu_unimpl(vcpu, "disabled perfctr wrmsr: " |
3771 | "0x%x data 0x%llx\n", msr, data); | |
5753785f | 3772 | break; |
84e0cefa JS |
3773 | case MSR_K7_CLK_CTL: |
3774 | /* | |
3775 | * Ignore all writes to this no longer documented MSR. | |
3776 | * Writes are only relevant for old K7 processors, | |
3777 | * all pre-dating SVM, but a recommended workaround from | |
4a969980 | 3778 | * AMD for these chips. It is possible to specify the |
84e0cefa JS |
3779 | * affected processor models on the command line, hence |
3780 | * the need to ignore the workaround. | |
3781 | */ | |
3782 | break; | |
55cd8e5a | 3783 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
3784 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
3785 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
3786 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3787 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 3788 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
3789 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3790 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3791 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e7d9513b AS |
3792 | return kvm_hv_set_msr_common(vcpu, msr, data, |
3793 | msr_info->host_initiated); | |
91c9c3ed | 3794 | case MSR_IA32_BBL_CR_CTL3: |
3795 | /* Drop writes to this legacy MSR -- see rdmsr | |
3796 | * counterpart for further detail. | |
3797 | */ | |
fab0aa3b EM |
3798 | if (report_ignored_msrs) |
3799 | vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", | |
3800 | msr, data); | |
91c9c3ed | 3801 | break; |
2b036c6b | 3802 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 3803 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3804 | return 1; |
3805 | vcpu->arch.osvw.length = data; | |
3806 | break; | |
3807 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 3808 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b BO |
3809 | return 1; |
3810 | vcpu->arch.osvw.status = data; | |
3811 | break; | |
db2336a8 KH |
3812 | case MSR_PLATFORM_INFO: |
3813 | if (!msr_info->host_initiated || | |
db2336a8 KH |
3814 | (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && |
3815 | cpuid_fault_enabled(vcpu))) | |
3816 | return 1; | |
3817 | vcpu->arch.msr_platform_info = data; | |
3818 | break; | |
3819 | case MSR_MISC_FEATURES_ENABLES: | |
3820 | if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT || | |
3821 | (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && | |
3822 | !supports_cpuid_fault(vcpu))) | |
3823 | return 1; | |
3824 | vcpu->arch.msr_misc_features_enables = data; | |
3825 | break; | |
820a6ee9 JL |
3826 | #ifdef CONFIG_X86_64 |
3827 | case MSR_IA32_XFD: | |
3828 | if (!msr_info->host_initiated && | |
3829 | !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) | |
3830 | return 1; | |
3831 | ||
988896bb | 3832 | if (data & ~kvm_guest_supported_xfd(vcpu)) |
820a6ee9 JL |
3833 | return 1; |
3834 | ||
3835 | fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data); | |
3836 | break; | |
548e8365 JL |
3837 | case MSR_IA32_XFD_ERR: |
3838 | if (!msr_info->host_initiated && | |
3839 | !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) | |
3840 | return 1; | |
3841 | ||
988896bb | 3842 | if (data & ~kvm_guest_supported_xfd(vcpu)) |
548e8365 JL |
3843 | return 1; |
3844 | ||
3845 | vcpu->arch.guest_fpu.xfd_err = data; | |
3846 | break; | |
820a6ee9 | 3847 | #endif |
157fc497 SC |
3848 | case MSR_IA32_PEBS_ENABLE: |
3849 | case MSR_IA32_DS_AREA: | |
3850 | case MSR_PEBS_DATA_CFG: | |
ff81a90f | 3851 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
157fc497 SC |
3852 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
3853 | return kvm_pmu_set_msr(vcpu, msr_info); | |
3854 | /* | |
3855 | * Userspace is allowed to write '0' to MSRs that KVM reports | |
3856 | * as to-be-saved, even if an MSRs isn't fully supported. | |
3857 | */ | |
3858 | return !msr_info->host_initiated || data; | |
15c4a640 | 3859 | default: |
c6702c9d | 3860 | if (kvm_pmu_is_valid_msr(vcpu, msr)) |
afd80d85 | 3861 | return kvm_pmu_set_msr(vcpu, msr_info); |
6abe9c13 | 3862 | return KVM_MSR_RET_INVALID; |
15c4a640 CO |
3863 | } |
3864 | return 0; | |
3865 | } | |
3866 | EXPORT_SYMBOL_GPL(kvm_set_msr_common); | |
3867 | ||
44883f01 | 3868 | static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host) |
15c4a640 CO |
3869 | { |
3870 | u64 data; | |
890ca9ae HY |
3871 | u64 mcg_cap = vcpu->arch.mcg_cap; |
3872 | unsigned bank_num = mcg_cap & 0xff; | |
281b5278 | 3873 | u32 offset, last_msr; |
15c4a640 CO |
3874 | |
3875 | switch (msr) { | |
15c4a640 CO |
3876 | case MSR_IA32_P5_MC_ADDR: |
3877 | case MSR_IA32_P5_MC_TYPE: | |
890ca9ae HY |
3878 | data = 0; |
3879 | break; | |
15c4a640 | 3880 | case MSR_IA32_MCG_CAP: |
890ca9ae HY |
3881 | data = vcpu->arch.mcg_cap; |
3882 | break; | |
c7ac679c | 3883 | case MSR_IA32_MCG_CTL: |
44883f01 | 3884 | if (!(mcg_cap & MCG_CTL_P) && !host) |
890ca9ae HY |
3885 | return 1; |
3886 | data = vcpu->arch.mcg_ctl; | |
3887 | break; | |
3888 | case MSR_IA32_MCG_STATUS: | |
3889 | data = vcpu->arch.mcg_status; | |
3890 | break; | |
281b5278 JW |
3891 | case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: |
3892 | last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1; | |
3893 | if (msr > last_msr) | |
3894 | return 1; | |
6ec4c5ee | 3895 | |
281b5278 JW |
3896 | if (!(mcg_cap & MCG_CMCI_P) && !host) |
3897 | return 1; | |
3898 | offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2, | |
3899 | last_msr + 1 - MSR_IA32_MC0_CTL2); | |
3900 | data = vcpu->arch.mci_ctl2_banks[offset]; | |
3901 | break; | |
3902 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: | |
3903 | last_msr = MSR_IA32_MCx_CTL(bank_num) - 1; | |
3904 | if (msr > last_msr) | |
3905 | return 1; | |
3906 | ||
3907 | offset = array_index_nospec(msr - MSR_IA32_MC0_CTL, | |
3908 | last_msr + 1 - MSR_IA32_MC0_CTL); | |
3909 | data = vcpu->arch.mce_banks[offset]; | |
3910 | break; | |
3911 | default: | |
890ca9ae HY |
3912 | return 1; |
3913 | } | |
3914 | *pdata = data; | |
3915 | return 0; | |
3916 | } | |
3917 | ||
609e36d3 | 3918 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) |
890ca9ae | 3919 | { |
609e36d3 | 3920 | switch (msr_info->index) { |
890ca9ae | 3921 | case MSR_IA32_PLATFORM_ID: |
15c4a640 | 3922 | case MSR_IA32_EBL_CR_POWERON: |
b5e2fec0 AG |
3923 | case MSR_IA32_LASTBRANCHFROMIP: |
3924 | case MSR_IA32_LASTBRANCHTOIP: | |
3925 | case MSR_IA32_LASTINTFROMIP: | |
3926 | case MSR_IA32_LASTINTTOIP: | |
059e5c32 | 3927 | case MSR_AMD64_SYSCFG: |
3afb1121 PB |
3928 | case MSR_K8_TSEG_ADDR: |
3929 | case MSR_K8_TSEG_MASK: | |
61a6bd67 | 3930 | case MSR_VM_HSAVE_PA: |
1fdbd48c | 3931 | case MSR_K8_INT_PENDING_MSG: |
c323c0e5 | 3932 | case MSR_AMD64_NB_CFG: |
f7c6d140 | 3933 | case MSR_FAM10H_MMIO_CONF_BASE: |
2e32b719 | 3934 | case MSR_AMD64_BU_CFG2: |
0c2df2a1 | 3935 | case MSR_IA32_PERF_CTL: |
405a353a | 3936 | case MSR_AMD64_DC_CFG: |
0e1b869f | 3937 | case MSR_F15H_EX_CFG: |
2ca1a06a VS |
3938 | /* |
3939 | * Intel Sandy Bridge CPUs must support the RAPL (running average power | |
3940 | * limit) MSRs. Just return 0, as we do not want to expose the host | |
3941 | * data here. Do not conditionalize this on CPUID, as KVM does not do | |
3942 | * so for existing CPU-specific MSRs. | |
3943 | */ | |
3944 | case MSR_RAPL_POWER_UNIT: | |
3945 | case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */ | |
3946 | case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */ | |
3947 | case MSR_PKG_ENERGY_STATUS: /* Total package */ | |
3948 | case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ | |
609e36d3 | 3949 | msr_info->data = 0; |
15c4a640 | 3950 | break; |
157fc497 SC |
3951 | case MSR_IA32_PEBS_ENABLE: |
3952 | case MSR_IA32_DS_AREA: | |
3953 | case MSR_PEBS_DATA_CFG: | |
c51eb52b | 3954 | case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: |
c28fa560 VK |
3955 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
3956 | return kvm_pmu_get_msr(vcpu, msr_info); | |
157fc497 | 3957 | /* |
bfbcc81b SC |
3958 | * Userspace is allowed to read MSRs that KVM reports as |
3959 | * to-be-saved, even if an MSR isn't fully supported. | |
157fc497 | 3960 | */ |
c28fa560 VK |
3961 | if (!msr_info->host_initiated) |
3962 | return 1; | |
3963 | msr_info->data = 0; | |
3964 | break; | |
6912ac32 WH |
3965 | case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: |
3966 | case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: | |
3967 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: | |
3968 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: | |
c6702c9d | 3969 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 3970 | return kvm_pmu_get_msr(vcpu, msr_info); |
609e36d3 | 3971 | msr_info->data = 0; |
5753785f | 3972 | break; |
742bc670 | 3973 | case MSR_IA32_UCODE_REV: |
518e7b94 | 3974 | msr_info->data = vcpu->arch.microcode_version; |
742bc670 | 3975 | break; |
0cf9135b SC |
3976 | case MSR_IA32_ARCH_CAPABILITIES: |
3977 | if (!msr_info->host_initiated && | |
3978 | !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES)) | |
3979 | return 1; | |
3980 | msr_info->data = vcpu->arch.arch_capabilities; | |
3981 | break; | |
d574c539 VK |
3982 | case MSR_IA32_PERF_CAPABILITIES: |
3983 | if (!msr_info->host_initiated && | |
3984 | !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) | |
3985 | return 1; | |
3986 | msr_info->data = vcpu->arch.perf_capabilities; | |
3987 | break; | |
73f624f4 PB |
3988 | case MSR_IA32_POWER_CTL: |
3989 | msr_info->data = vcpu->arch.msr_ia32_power_ctl; | |
3990 | break; | |
cc5b54dd ML |
3991 | case MSR_IA32_TSC: { |
3992 | /* | |
3993 | * Intel SDM states that MSR_IA32_TSC read adds the TSC offset | |
3994 | * even when not intercepted. AMD manual doesn't explicitly | |
3995 | * state this but appears to behave the same. | |
3996 | * | |
ee6fa053 | 3997 | * On userspace reads and writes, however, we unconditionally |
c0623f5e | 3998 | * return L1's TSC value to ensure backwards-compatible |
ee6fa053 | 3999 | * behavior for migration. |
cc5b54dd | 4000 | */ |
fe3eb504 | 4001 | u64 offset, ratio; |
cc5b54dd | 4002 | |
fe3eb504 IS |
4003 | if (msr_info->host_initiated) { |
4004 | offset = vcpu->arch.l1_tsc_offset; | |
4005 | ratio = vcpu->arch.l1_tsc_scaling_ratio; | |
4006 | } else { | |
4007 | offset = vcpu->arch.tsc_offset; | |
4008 | ratio = vcpu->arch.tsc_scaling_ratio; | |
4009 | } | |
4010 | ||
62711e5a | 4011 | msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset; |
dd259935 | 4012 | break; |
cc5b54dd | 4013 | } |
9ba075a6 | 4014 | case MSR_MTRRcap: |
281b5278 JW |
4015 | case 0x200 ... MSR_IA32_MC0_CTL2 - 1: |
4016 | case MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) ... 0x2ff: | |
ff53604b | 4017 | return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |
15c4a640 | 4018 | case 0xcd: /* fsb frequency */ |
609e36d3 | 4019 | msr_info->data = 3; |
15c4a640 | 4020 | break; |
7b914098 JS |
4021 | /* |
4022 | * MSR_EBC_FREQUENCY_ID | |
4023 | * Conservative value valid for even the basic CPU models. | |
4024 | * Models 0,1: 000 in bits 23:21 indicating a bus speed of | |
4025 | * 100MHz, model 2 000 in bits 18:16 indicating 100MHz, | |
4026 | * and 266MHz for model 3, or 4. Set Core Clock | |
4027 | * Frequency to System Bus Frequency Ratio to 1 (bits | |
4028 | * 31:24) even though these are only valid for CPU | |
4029 | * models > 2, however guests may end up dividing or | |
4030 | * multiplying by zero otherwise. | |
4031 | */ | |
4032 | case MSR_EBC_FREQUENCY_ID: | |
609e36d3 | 4033 | msr_info->data = 1 << 24; |
7b914098 | 4034 | break; |
15c4a640 | 4035 | case MSR_IA32_APICBASE: |
609e36d3 | 4036 | msr_info->data = kvm_get_apic_base(vcpu); |
15c4a640 | 4037 | break; |
bf10bd0b | 4038 | case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff: |
609e36d3 | 4039 | return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data); |
09141ec0 | 4040 | case MSR_IA32_TSC_DEADLINE: |
609e36d3 | 4041 | msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu); |
a3e06bbe | 4042 | break; |
ba904635 | 4043 | case MSR_IA32_TSC_ADJUST: |
609e36d3 | 4044 | msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr; |
ba904635 | 4045 | break; |
15c4a640 | 4046 | case MSR_IA32_MISC_ENABLE: |
609e36d3 | 4047 | msr_info->data = vcpu->arch.ia32_misc_enable_msr; |
15c4a640 | 4048 | break; |
64d60670 PB |
4049 | case MSR_IA32_SMBASE: |
4050 | if (!msr_info->host_initiated) | |
4051 | return 1; | |
4052 | msr_info->data = vcpu->arch.smbase; | |
15c4a640 | 4053 | break; |
52797bf9 LA |
4054 | case MSR_SMI_COUNT: |
4055 | msr_info->data = vcpu->arch.smi_count; | |
4056 | break; | |
847f0ad8 AG |
4057 | case MSR_IA32_PERF_STATUS: |
4058 | /* TSC increment by tick */ | |
609e36d3 | 4059 | msr_info->data = 1000ULL; |
847f0ad8 | 4060 | /* CPU multiplier */ |
b0996ae4 | 4061 | msr_info->data |= (((uint64_t)4ULL) << 40); |
847f0ad8 | 4062 | break; |
15c4a640 | 4063 | case MSR_EFER: |
609e36d3 | 4064 | msr_info->data = vcpu->arch.efer; |
15c4a640 | 4065 | break; |
18068523 | 4066 | case MSR_KVM_WALL_CLOCK: |
1930e5dd OU |
4067 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
4068 | return 1; | |
4069 | ||
4070 | msr_info->data = vcpu->kvm->arch.wall_clock; | |
4071 | break; | |
11c6bffa | 4072 | case MSR_KVM_WALL_CLOCK_NEW: |
1930e5dd OU |
4073 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
4074 | return 1; | |
4075 | ||
609e36d3 | 4076 | msr_info->data = vcpu->kvm->arch.wall_clock; |
18068523 GOC |
4077 | break; |
4078 | case MSR_KVM_SYSTEM_TIME: | |
1930e5dd OU |
4079 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE)) |
4080 | return 1; | |
4081 | ||
4082 | msr_info->data = vcpu->arch.time; | |
4083 | break; | |
11c6bffa | 4084 | case MSR_KVM_SYSTEM_TIME_NEW: |
1930e5dd OU |
4085 | if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2)) |
4086 | return 1; | |
4087 | ||
609e36d3 | 4088 | msr_info->data = vcpu->arch.time; |
18068523 | 4089 | break; |
344d9588 | 4090 | case MSR_KVM_ASYNC_PF_EN: |
1930e5dd OU |
4091 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF)) |
4092 | return 1; | |
4093 | ||
2635b5c4 VK |
4094 | msr_info->data = vcpu->arch.apf.msr_en_val; |
4095 | break; | |
4096 | case MSR_KVM_ASYNC_PF_INT: | |
1930e5dd OU |
4097 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
4098 | return 1; | |
4099 | ||
2635b5c4 | 4100 | msr_info->data = vcpu->arch.apf.msr_int_val; |
344d9588 | 4101 | break; |
557a961a | 4102 | case MSR_KVM_ASYNC_PF_ACK: |
0a31df68 | 4103 | if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT)) |
1930e5dd OU |
4104 | return 1; |
4105 | ||
557a961a VK |
4106 | msr_info->data = 0; |
4107 | break; | |
c9aaa895 | 4108 | case MSR_KVM_STEAL_TIME: |
1930e5dd OU |
4109 | if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME)) |
4110 | return 1; | |
4111 | ||
609e36d3 | 4112 | msr_info->data = vcpu->arch.st.msr_val; |
c9aaa895 | 4113 | break; |
1d92128f | 4114 | case MSR_KVM_PV_EOI_EN: |
1930e5dd OU |
4115 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI)) |
4116 | return 1; | |
4117 | ||
609e36d3 | 4118 | msr_info->data = vcpu->arch.pv_eoi.msr_val; |
1d92128f | 4119 | break; |
2d5ba19b | 4120 | case MSR_KVM_POLL_CONTROL: |
1930e5dd OU |
4121 | if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL)) |
4122 | return 1; | |
4123 | ||
2d5ba19b MT |
4124 | msr_info->data = vcpu->arch.msr_kvm_poll_control; |
4125 | break; | |
890ca9ae HY |
4126 | case MSR_IA32_P5_MC_ADDR: |
4127 | case MSR_IA32_P5_MC_TYPE: | |
4128 | case MSR_IA32_MCG_CAP: | |
4129 | case MSR_IA32_MCG_CTL: | |
4130 | case MSR_IA32_MCG_STATUS: | |
81760dcc | 4131 | case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1: |
281b5278 | 4132 | case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1: |
44883f01 PB |
4133 | return get_msr_mce(vcpu, msr_info->index, &msr_info->data, |
4134 | msr_info->host_initiated); | |
864e2ab2 AL |
4135 | case MSR_IA32_XSS: |
4136 | if (!msr_info->host_initiated && | |
4137 | !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES)) | |
4138 | return 1; | |
4139 | msr_info->data = vcpu->arch.ia32_xss; | |
4140 | break; | |
84e0cefa JS |
4141 | case MSR_K7_CLK_CTL: |
4142 | /* | |
4143 | * Provide expected ramp-up count for K7. All other | |
4144 | * are set to zero, indicating minimum divisors for | |
4145 | * every field. | |
4146 | * | |
4147 | * This prevents guest kernels on AMD host with CPU | |
4148 | * type 6, model 8 and higher from exploding due to | |
4149 | * the rdmsr failing. | |
4150 | */ | |
609e36d3 | 4151 | msr_info->data = 0x20000000; |
84e0cefa | 4152 | break; |
55cd8e5a | 4153 | case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15: |
f97f5a56 JD |
4154 | case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER: |
4155 | case HV_X64_MSR_SYNDBG_OPTIONS: | |
e7d9513b AS |
4156 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
4157 | case HV_X64_MSR_CRASH_CTL: | |
1f4b34f8 | 4158 | case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT: |
a2e164e7 VK |
4159 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
4160 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
4161 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
e83d5887 | 4162 | return kvm_hv_get_msr_common(vcpu, |
44883f01 PB |
4163 | msr_info->index, &msr_info->data, |
4164 | msr_info->host_initiated); | |
91c9c3ed | 4165 | case MSR_IA32_BBL_CR_CTL3: |
4166 | /* This legacy MSR exists but isn't fully documented in current | |
4167 | * silicon. It is however accessed by winxp in very narrow | |
4168 | * scenarios where it sets bit #19, itself documented as | |
4169 | * a "reserved" bit. Best effort attempt to source coherent | |
4170 | * read data here should the balance of the register be | |
4171 | * interpreted by the guest: | |
4172 | * | |
4173 | * L2 cache control register 3: 64GB range, 256KB size, | |
4174 | * enabled, latency 0x1, configured | |
4175 | */ | |
609e36d3 | 4176 | msr_info->data = 0xbe702111; |
91c9c3ed | 4177 | break; |
2b036c6b | 4178 | case MSR_AMD64_OSVW_ID_LENGTH: |
d6321d49 | 4179 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 4180 | return 1; |
609e36d3 | 4181 | msr_info->data = vcpu->arch.osvw.length; |
2b036c6b BO |
4182 | break; |
4183 | case MSR_AMD64_OSVW_STATUS: | |
d6321d49 | 4184 | if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW)) |
2b036c6b | 4185 | return 1; |
609e36d3 | 4186 | msr_info->data = vcpu->arch.osvw.status; |
2b036c6b | 4187 | break; |
db2336a8 | 4188 | case MSR_PLATFORM_INFO: |
6fbbde9a DS |
4189 | if (!msr_info->host_initiated && |
4190 | !vcpu->kvm->arch.guest_can_read_msr_platform_info) | |
4191 | return 1; | |
db2336a8 KH |
4192 | msr_info->data = vcpu->arch.msr_platform_info; |
4193 | break; | |
4194 | case MSR_MISC_FEATURES_ENABLES: | |
4195 | msr_info->data = vcpu->arch.msr_misc_features_enables; | |
4196 | break; | |
191c8137 BP |
4197 | case MSR_K7_HWCR: |
4198 | msr_info->data = vcpu->arch.msr_hwcr; | |
4199 | break; | |
820a6ee9 JL |
4200 | #ifdef CONFIG_X86_64 |
4201 | case MSR_IA32_XFD: | |
4202 | if (!msr_info->host_initiated && | |
4203 | !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) | |
4204 | return 1; | |
4205 | ||
4206 | msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd; | |
4207 | break; | |
548e8365 JL |
4208 | case MSR_IA32_XFD_ERR: |
4209 | if (!msr_info->host_initiated && | |
4210 | !guest_cpuid_has(vcpu, X86_FEATURE_XFD)) | |
4211 | return 1; | |
4212 | ||
4213 | msr_info->data = vcpu->arch.guest_fpu.xfd_err; | |
4214 | break; | |
820a6ee9 | 4215 | #endif |
15c4a640 | 4216 | default: |
c6702c9d | 4217 | if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) |
cbd71758 | 4218 | return kvm_pmu_get_msr(vcpu, msr_info); |
6abe9c13 | 4219 | return KVM_MSR_RET_INVALID; |
15c4a640 | 4220 | } |
15c4a640 CO |
4221 | return 0; |
4222 | } | |
4223 | EXPORT_SYMBOL_GPL(kvm_get_msr_common); | |
4224 | ||
313a3dc7 CO |
4225 | /* |
4226 | * Read or write a bunch of msrs. All parameters are kernel addresses. | |
4227 | * | |
4228 | * @return number of msrs set successfully. | |
4229 | */ | |
4230 | static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs, | |
4231 | struct kvm_msr_entry *entries, | |
4232 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
4233 | unsigned index, u64 *data)) | |
4234 | { | |
801e459a | 4235 | int i; |
313a3dc7 | 4236 | |
313a3dc7 CO |
4237 | for (i = 0; i < msrs->nmsrs; ++i) |
4238 | if (do_msr(vcpu, entries[i].index, &entries[i].data)) | |
4239 | break; | |
4240 | ||
313a3dc7 CO |
4241 | return i; |
4242 | } | |
4243 | ||
4244 | /* | |
4245 | * Read or write a bunch of msrs. Parameters are user addresses. | |
4246 | * | |
4247 | * @return number of msrs set successfully. | |
4248 | */ | |
4249 | static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs, | |
4250 | int (*do_msr)(struct kvm_vcpu *vcpu, | |
4251 | unsigned index, u64 *data), | |
4252 | int writeback) | |
4253 | { | |
4254 | struct kvm_msrs msrs; | |
4255 | struct kvm_msr_entry *entries; | |
4256 | int r, n; | |
4257 | unsigned size; | |
4258 | ||
4259 | r = -EFAULT; | |
0e96f31e | 4260 | if (copy_from_user(&msrs, user_msrs, sizeof(msrs))) |
313a3dc7 CO |
4261 | goto out; |
4262 | ||
4263 | r = -E2BIG; | |
4264 | if (msrs.nmsrs >= MAX_IO_MSRS) | |
4265 | goto out; | |
4266 | ||
313a3dc7 | 4267 | size = sizeof(struct kvm_msr_entry) * msrs.nmsrs; |
ff5c2c03 SL |
4268 | entries = memdup_user(user_msrs->entries, size); |
4269 | if (IS_ERR(entries)) { | |
4270 | r = PTR_ERR(entries); | |
313a3dc7 | 4271 | goto out; |
ff5c2c03 | 4272 | } |
313a3dc7 CO |
4273 | |
4274 | r = n = __msr_io(vcpu, &msrs, entries, do_msr); | |
4275 | if (r < 0) | |
4276 | goto out_free; | |
4277 | ||
4278 | r = -EFAULT; | |
4279 | if (writeback && copy_to_user(user_msrs->entries, entries, size)) | |
4280 | goto out_free; | |
4281 | ||
4282 | r = n; | |
4283 | ||
4284 | out_free: | |
7a73c028 | 4285 | kfree(entries); |
313a3dc7 CO |
4286 | out: |
4287 | return r; | |
4288 | } | |
4289 | ||
4d5422ce WL |
4290 | static inline bool kvm_can_mwait_in_guest(void) |
4291 | { | |
4292 | return boot_cpu_has(X86_FEATURE_MWAIT) && | |
8e9b29b6 KA |
4293 | !boot_cpu_has_bug(X86_BUG_MONITOR) && |
4294 | boot_cpu_has(X86_FEATURE_ARAT); | |
4d5422ce WL |
4295 | } |
4296 | ||
c21d54f0 VK |
4297 | static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu, |
4298 | struct kvm_cpuid2 __user *cpuid_arg) | |
4299 | { | |
4300 | struct kvm_cpuid2 cpuid; | |
4301 | int r; | |
4302 | ||
4303 | r = -EFAULT; | |
4304 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) | |
4305 | return r; | |
4306 | ||
4307 | r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
4308 | if (r) | |
4309 | return r; | |
4310 | ||
4311 | r = -EFAULT; | |
4312 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) | |
4313 | return r; | |
4314 | ||
4315 | return 0; | |
4316 | } | |
4317 | ||
784aa3d7 | 4318 | int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) |
018d00d2 | 4319 | { |
4d5422ce | 4320 | int r = 0; |
018d00d2 ZX |
4321 | |
4322 | switch (ext) { | |
4323 | case KVM_CAP_IRQCHIP: | |
4324 | case KVM_CAP_HLT: | |
4325 | case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: | |
018d00d2 | 4326 | case KVM_CAP_SET_TSS_ADDR: |
07716717 | 4327 | case KVM_CAP_EXT_CPUID: |
9c15bb1d | 4328 | case KVM_CAP_EXT_EMUL_CPUID: |
c8076604 | 4329 | case KVM_CAP_CLOCKSOURCE: |
7837699f | 4330 | case KVM_CAP_PIT: |
a28e4f5a | 4331 | case KVM_CAP_NOP_IO_DELAY: |
62d9f0db | 4332 | case KVM_CAP_MP_STATE: |
ed848624 | 4333 | case KVM_CAP_SYNC_MMU: |
a355c85c | 4334 | case KVM_CAP_USER_NMI: |
52d939a0 | 4335 | case KVM_CAP_REINJECT_CONTROL: |
4925663a | 4336 | case KVM_CAP_IRQ_INJECT_STATUS: |
d34e6b17 | 4337 | case KVM_CAP_IOEVENTFD: |
f848a5a8 | 4338 | case KVM_CAP_IOEVENTFD_NO_LENGTH: |
c5ff41ce | 4339 | case KVM_CAP_PIT2: |
e9f42757 | 4340 | case KVM_CAP_PIT_STATE2: |
b927a3ce | 4341 | case KVM_CAP_SET_IDENTITY_MAP_ADDR: |
3cfc3092 | 4342 | case KVM_CAP_VCPU_EVENTS: |
55cd8e5a | 4343 | case KVM_CAP_HYPERV: |
10388a07 | 4344 | case KVM_CAP_HYPERV_VAPIC: |
c25bc163 | 4345 | case KVM_CAP_HYPERV_SPIN: |
5c919412 | 4346 | case KVM_CAP_HYPERV_SYNIC: |
efc479e6 | 4347 | case KVM_CAP_HYPERV_SYNIC2: |
d3457c87 | 4348 | case KVM_CAP_HYPERV_VP_INDEX: |
faeb7833 | 4349 | case KVM_CAP_HYPERV_EVENTFD: |
c1aea919 | 4350 | case KVM_CAP_HYPERV_TLBFLUSH: |
214ff83d | 4351 | case KVM_CAP_HYPERV_SEND_IPI: |
2bc39970 | 4352 | case KVM_CAP_HYPERV_CPUID: |
644f7067 | 4353 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
c21d54f0 | 4354 | case KVM_CAP_SYS_HYPERV_CPUID: |
ab9f4ecb | 4355 | case KVM_CAP_PCI_SEGMENT: |
a1efbe77 | 4356 | case KVM_CAP_DEBUGREGS: |
d2be1651 | 4357 | case KVM_CAP_X86_ROBUST_SINGLESTEP: |
2d5b5a66 | 4358 | case KVM_CAP_XSAVE: |
344d9588 | 4359 | case KVM_CAP_ASYNC_PF: |
72de5fa4 | 4360 | case KVM_CAP_ASYNC_PF_INT: |
92a1f12d | 4361 | case KVM_CAP_GET_TSC_KHZ: |
1c0b28c2 | 4362 | case KVM_CAP_KVMCLOCK_CTRL: |
4d8b81ab | 4363 | case KVM_CAP_READONLY_MEM: |
5f66b620 | 4364 | case KVM_CAP_HYPERV_TIME: |
100943c5 | 4365 | case KVM_CAP_IOAPIC_POLARITY_IGNORED: |
defcf51f | 4366 | case KVM_CAP_TSC_DEADLINE_TIMER: |
90de4a18 | 4367 | case KVM_CAP_DISABLE_QUIRKS: |
d71ba788 | 4368 | case KVM_CAP_SET_BOOT_CPU_ID: |
49df6397 | 4369 | case KVM_CAP_SPLIT_IRQCHIP: |
460df4c1 | 4370 | case KVM_CAP_IMMEDIATE_EXIT: |
66bb8a06 | 4371 | case KVM_CAP_PMU_EVENT_FILTER: |
801e459a | 4372 | case KVM_CAP_GET_MSR_FEATURES: |
6fbbde9a | 4373 | case KVM_CAP_MSR_PLATFORM_INFO: |
c4f55198 | 4374 | case KVM_CAP_EXCEPTION_PAYLOAD: |
ed235117 | 4375 | case KVM_CAP_X86_TRIPLE_FAULT_EVENT: |
b9b2782c | 4376 | case KVM_CAP_SET_GUEST_DEBUG: |
1aa561b1 | 4377 | case KVM_CAP_LAST_CPU: |
1ae09954 | 4378 | case KVM_CAP_X86_USER_SPACE_MSR: |
1a155254 | 4379 | case KVM_CAP_X86_MSR_FILTER: |
66570e96 | 4380 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
fe7e9488 SC |
4381 | #ifdef CONFIG_X86_SGX_KVM |
4382 | case KVM_CAP_SGX_ATTRIBUTE: | |
4383 | #endif | |
54526d1f | 4384 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
30d7c5d6 | 4385 | case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: |
6dba9403 | 4386 | case KVM_CAP_SREGS2: |
19238e75 | 4387 | case KVM_CAP_EXIT_ON_EMULATION_FAILURE: |
828ca896 | 4388 | case KVM_CAP_VCPU_ATTRIBUTES: |
dd6e6312 | 4389 | case KVM_CAP_SYS_ATTRIBUTES: |
8a289785 | 4390 | case KVM_CAP_VAPIC: |
127770ac | 4391 | case KVM_CAP_ENABLE_CAP: |
084cc29f | 4392 | case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES: |
018d00d2 ZX |
4393 | r = 1; |
4394 | break; | |
0dbb1123 AK |
4395 | case KVM_CAP_EXIT_HYPERCALL: |
4396 | r = KVM_EXIT_HYPERCALL_VALID_MASK; | |
4397 | break; | |
7e582ccb ML |
4398 | case KVM_CAP_SET_GUEST_DEBUG2: |
4399 | return KVM_GUESTDBG_VALID_MASK; | |
b59b153d | 4400 | #ifdef CONFIG_KVM_XEN |
23200b7a JM |
4401 | case KVM_CAP_XEN_HVM: |
4402 | r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR | | |
8d4e7e80 | 4403 | KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL | |
14243b38 | 4404 | KVM_XEN_HVM_CONFIG_SHARED_INFO | |
661a20fa DW |
4405 | KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL | |
4406 | KVM_XEN_HVM_CONFIG_EVTCHN_SEND; | |
30b5c851 DW |
4407 | if (sched_info_on()) |
4408 | r |= KVM_XEN_HVM_CONFIG_RUNSTATE; | |
23200b7a | 4409 | break; |
b59b153d | 4410 | #endif |
01643c51 KH |
4411 | case KVM_CAP_SYNC_REGS: |
4412 | r = KVM_SYNC_X86_VALID_FIELDS; | |
4413 | break; | |
e3fd9a93 | 4414 | case KVM_CAP_ADJUST_CLOCK: |
c68dc1b5 | 4415 | r = KVM_CLOCK_VALID_FLAGS; |
e3fd9a93 | 4416 | break; |
4d5422ce | 4417 | case KVM_CAP_X86_DISABLE_EXITS: |
b5170063 WL |
4418 | r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE | |
4419 | KVM_X86_DISABLE_EXITS_CSTATE; | |
4d5422ce WL |
4420 | if(kvm_can_mwait_in_guest()) |
4421 | r |= KVM_X86_DISABLE_EXITS_MWAIT; | |
668fffa3 | 4422 | break; |
6d396b55 PB |
4423 | case KVM_CAP_X86_SMM: |
4424 | /* SMBASE is usually relocated above 1M on modern chipsets, | |
4425 | * and SMM handlers might indeed rely on 4G segment limits, | |
4426 | * so do not report SMM to be available if real mode is | |
4427 | * emulated via vm86 mode. Still, do not go to great lengths | |
4428 | * to avoid userspace's usage of the feature, because it is a | |
4429 | * fringe case that is not enabled except via specific settings | |
4430 | * of the module parameters. | |
4431 | */ | |
b3646477 | 4432 | r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE); |
6d396b55 | 4433 | break; |
f725230a | 4434 | case KVM_CAP_NR_VCPUS: |
2845e735 | 4435 | r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS); |
8c3ba334 SL |
4436 | break; |
4437 | case KVM_CAP_MAX_VCPUS: | |
f725230a AK |
4438 | r = KVM_MAX_VCPUS; |
4439 | break; | |
a86cb413 | 4440 | case KVM_CAP_MAX_VCPU_ID: |
a1c42dde | 4441 | r = KVM_MAX_VCPU_IDS; |
a86cb413 | 4442 | break; |
a68a6a72 MT |
4443 | case KVM_CAP_PV_MMU: /* obsolete */ |
4444 | r = 0; | |
2f333bcb | 4445 | break; |
890ca9ae HY |
4446 | case KVM_CAP_MCE: |
4447 | r = KVM_MAX_MCE_BANKS; | |
4448 | break; | |
2d5b5a66 | 4449 | case KVM_CAP_XCRS: |
d366bf7e | 4450 | r = boot_cpu_has(X86_FEATURE_XSAVE); |
2d5b5a66 | 4451 | break; |
92a1f12d | 4452 | case KVM_CAP_TSC_CONTROL: |
ffbb61d0 | 4453 | case KVM_CAP_VM_TSC_CONTROL: |
938c8745 | 4454 | r = kvm_caps.has_tsc_control; |
92a1f12d | 4455 | break; |
37131313 RK |
4456 | case KVM_CAP_X2APIC_API: |
4457 | r = KVM_X2APIC_API_VALID_FLAGS; | |
4458 | break; | |
8fcc4b59 | 4459 | case KVM_CAP_NESTED_STATE: |
33b22172 PB |
4460 | r = kvm_x86_ops.nested_ops->get_state ? |
4461 | kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0; | |
8fcc4b59 | 4462 | break; |
344c6c80 | 4463 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 4464 | r = kvm_x86_ops.enable_direct_tlbflush != NULL; |
5a0165f6 VK |
4465 | break; |
4466 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: | |
33b22172 | 4467 | r = kvm_x86_ops.nested_ops->enable_evmcs != NULL; |
344c6c80 | 4468 | break; |
3edd6839 MG |
4469 | case KVM_CAP_SMALLER_MAXPHYADDR: |
4470 | r = (int) allow_smaller_maxphyaddr; | |
4471 | break; | |
004a0124 AJ |
4472 | case KVM_CAP_STEAL_TIME: |
4473 | r = sched_info_on(); | |
4474 | break; | |
fe6b6bc8 | 4475 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
938c8745 | 4476 | if (kvm_caps.has_bus_lock_exit) |
fe6b6bc8 CQ |
4477 | r = KVM_BUS_LOCK_DETECTION_OFF | |
4478 | KVM_BUS_LOCK_DETECTION_EXIT; | |
4479 | else | |
4480 | r = 0; | |
4481 | break; | |
be50b206 GZ |
4482 | case KVM_CAP_XSAVE2: { |
4483 | u64 guest_perm = xstate_get_guest_group_perm(); | |
4484 | ||
938c8745 | 4485 | r = xstate_required_size(kvm_caps.supported_xcr0 & guest_perm, false); |
be50b206 GZ |
4486 | if (r < sizeof(struct kvm_xsave)) |
4487 | r = sizeof(struct kvm_xsave); | |
4488 | break; | |
1c4dc573 | 4489 | } |
ba7bb663 DD |
4490 | case KVM_CAP_PMU_CAPABILITY: |
4491 | r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0; | |
4492 | break; | |
6d849191 OU |
4493 | case KVM_CAP_DISABLE_QUIRKS2: |
4494 | r = KVM_X86_VALID_QUIRKS; | |
4495 | break; | |
2f4073e0 TX |
4496 | case KVM_CAP_X86_NOTIFY_VMEXIT: |
4497 | r = kvm_caps.has_notify_vmexit; | |
4498 | break; | |
018d00d2 | 4499 | default: |
018d00d2 ZX |
4500 | break; |
4501 | } | |
4502 | return r; | |
56f289a8 SC |
4503 | } |
4504 | ||
4505 | static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr) | |
4506 | { | |
4507 | void __user *uaddr = (void __user*)(unsigned long)attr->addr; | |
018d00d2 | 4508 | |
56f289a8 | 4509 | if ((u64)(unsigned long)uaddr != attr->addr) |
6e37ec88 | 4510 | return ERR_PTR_USR(-EFAULT); |
56f289a8 | 4511 | return uaddr; |
018d00d2 ZX |
4512 | } |
4513 | ||
dd6e6312 PB |
4514 | static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr) |
4515 | { | |
4516 | u64 __user *uaddr = kvm_get_attr_addr(attr); | |
4517 | ||
4518 | if (attr->group) | |
4519 | return -ENXIO; | |
4520 | ||
4521 | if (IS_ERR(uaddr)) | |
4522 | return PTR_ERR(uaddr); | |
4523 | ||
4524 | switch (attr->attr) { | |
4525 | case KVM_X86_XCOMP_GUEST_SUPP: | |
938c8745 | 4526 | if (put_user(kvm_caps.supported_xcr0, uaddr)) |
dd6e6312 PB |
4527 | return -EFAULT; |
4528 | return 0; | |
4529 | default: | |
4530 | return -ENXIO; | |
4531 | break; | |
4532 | } | |
4533 | } | |
4534 | ||
4535 | static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr) | |
4536 | { | |
4537 | if (attr->group) | |
4538 | return -ENXIO; | |
4539 | ||
4540 | switch (attr->attr) { | |
4541 | case KVM_X86_XCOMP_GUEST_SUPP: | |
4542 | return 0; | |
4543 | default: | |
4544 | return -ENXIO; | |
4545 | } | |
4546 | } | |
4547 | ||
043405e1 CO |
4548 | long kvm_arch_dev_ioctl(struct file *filp, |
4549 | unsigned int ioctl, unsigned long arg) | |
4550 | { | |
4551 | void __user *argp = (void __user *)arg; | |
4552 | long r; | |
4553 | ||
4554 | switch (ioctl) { | |
4555 | case KVM_GET_MSR_INDEX_LIST: { | |
4556 | struct kvm_msr_list __user *user_msr_list = argp; | |
4557 | struct kvm_msr_list msr_list; | |
4558 | unsigned n; | |
4559 | ||
4560 | r = -EFAULT; | |
0e96f31e | 4561 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) |
043405e1 CO |
4562 | goto out; |
4563 | n = msr_list.nmsrs; | |
62ef68bb | 4564 | msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs; |
0e96f31e | 4565 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) |
043405e1 CO |
4566 | goto out; |
4567 | r = -E2BIG; | |
e125e7b6 | 4568 | if (n < msr_list.nmsrs) |
043405e1 CO |
4569 | goto out; |
4570 | r = -EFAULT; | |
4571 | if (copy_to_user(user_msr_list->indices, &msrs_to_save, | |
4572 | num_msrs_to_save * sizeof(u32))) | |
4573 | goto out; | |
e125e7b6 | 4574 | if (copy_to_user(user_msr_list->indices + num_msrs_to_save, |
043405e1 | 4575 | &emulated_msrs, |
62ef68bb | 4576 | num_emulated_msrs * sizeof(u32))) |
043405e1 CO |
4577 | goto out; |
4578 | r = 0; | |
4579 | break; | |
4580 | } | |
9c15bb1d BP |
4581 | case KVM_GET_SUPPORTED_CPUID: |
4582 | case KVM_GET_EMULATED_CPUID: { | |
674eea0f AK |
4583 | struct kvm_cpuid2 __user *cpuid_arg = argp; |
4584 | struct kvm_cpuid2 cpuid; | |
4585 | ||
4586 | r = -EFAULT; | |
0e96f31e | 4587 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
674eea0f | 4588 | goto out; |
9c15bb1d BP |
4589 | |
4590 | r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries, | |
4591 | ioctl); | |
674eea0f AK |
4592 | if (r) |
4593 | goto out; | |
4594 | ||
4595 | r = -EFAULT; | |
0e96f31e | 4596 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
674eea0f AK |
4597 | goto out; |
4598 | r = 0; | |
4599 | break; | |
4600 | } | |
cf6c26ec | 4601 | case KVM_X86_GET_MCE_CAP_SUPPORTED: |
890ca9ae | 4602 | r = -EFAULT; |
938c8745 SC |
4603 | if (copy_to_user(argp, &kvm_caps.supported_mce_cap, |
4604 | sizeof(kvm_caps.supported_mce_cap))) | |
890ca9ae HY |
4605 | goto out; |
4606 | r = 0; | |
4607 | break; | |
801e459a TL |
4608 | case KVM_GET_MSR_FEATURE_INDEX_LIST: { |
4609 | struct kvm_msr_list __user *user_msr_list = argp; | |
4610 | struct kvm_msr_list msr_list; | |
4611 | unsigned int n; | |
4612 | ||
4613 | r = -EFAULT; | |
4614 | if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list))) | |
4615 | goto out; | |
4616 | n = msr_list.nmsrs; | |
4617 | msr_list.nmsrs = num_msr_based_features; | |
4618 | if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list))) | |
4619 | goto out; | |
4620 | r = -E2BIG; | |
4621 | if (n < msr_list.nmsrs) | |
4622 | goto out; | |
4623 | r = -EFAULT; | |
4624 | if (copy_to_user(user_msr_list->indices, &msr_based_features, | |
4625 | num_msr_based_features * sizeof(u32))) | |
4626 | goto out; | |
4627 | r = 0; | |
4628 | break; | |
4629 | } | |
4630 | case KVM_GET_MSRS: | |
4631 | r = msr_io(NULL, argp, do_get_msr_feature, 1); | |
4632 | break; | |
c21d54f0 VK |
4633 | case KVM_GET_SUPPORTED_HV_CPUID: |
4634 | r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp); | |
4635 | break; | |
dd6e6312 PB |
4636 | case KVM_GET_DEVICE_ATTR: { |
4637 | struct kvm_device_attr attr; | |
4638 | r = -EFAULT; | |
4639 | if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) | |
4640 | break; | |
4641 | r = kvm_x86_dev_get_attr(&attr); | |
4642 | break; | |
4643 | } | |
4644 | case KVM_HAS_DEVICE_ATTR: { | |
4645 | struct kvm_device_attr attr; | |
4646 | r = -EFAULT; | |
4647 | if (copy_from_user(&attr, (void __user *)arg, sizeof(attr))) | |
4648 | break; | |
4649 | r = kvm_x86_dev_has_attr(&attr); | |
4650 | break; | |
4651 | } | |
043405e1 CO |
4652 | default: |
4653 | r = -EINVAL; | |
cf6c26ec | 4654 | break; |
043405e1 CO |
4655 | } |
4656 | out: | |
4657 | return r; | |
4658 | } | |
4659 | ||
f5f48ee1 SY |
4660 | static void wbinvd_ipi(void *garbage) |
4661 | { | |
4662 | wbinvd(); | |
4663 | } | |
4664 | ||
4665 | static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
4666 | { | |
e0f0bbc5 | 4667 | return kvm_arch_has_noncoherent_dma(vcpu->kvm); |
f5f48ee1 SY |
4668 | } |
4669 | ||
313a3dc7 CO |
4670 | void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
4671 | { | |
f5f48ee1 SY |
4672 | /* Address WBINVD may be executed by guest */ |
4673 | if (need_emulate_wbinvd(vcpu)) { | |
b3646477 | 4674 | if (static_call(kvm_x86_has_wbinvd_exit)()) |
f5f48ee1 SY |
4675 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); |
4676 | else if (vcpu->cpu != -1 && vcpu->cpu != cpu) | |
4677 | smp_call_function_single(vcpu->cpu, | |
4678 | wbinvd_ipi, NULL, 1); | |
4679 | } | |
4680 | ||
b3646477 | 4681 | static_call(kvm_x86_vcpu_load)(vcpu, cpu); |
8f6055cb | 4682 | |
37486135 BM |
4683 | /* Save host pkru register if supported */ |
4684 | vcpu->arch.host_pkru = read_pkru(); | |
4685 | ||
0dd6a6ed ZA |
4686 | /* Apply any externally detected TSC adjustments (due to suspend) */ |
4687 | if (unlikely(vcpu->arch.tsc_offset_adjustment)) { | |
4688 | adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment); | |
4689 | vcpu->arch.tsc_offset_adjustment = 0; | |
105b21bb | 4690 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed | 4691 | } |
8f6055cb | 4692 | |
b0c39dc6 | 4693 | if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) { |
6f526ec5 | 4694 | s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 : |
4ea1636b | 4695 | rdtsc() - vcpu->arch.last_host_tsc; |
e48672fa ZA |
4696 | if (tsc_delta < 0) |
4697 | mark_tsc_unstable("KVM discovered backwards TSC"); | |
ce7a058a | 4698 | |
b0c39dc6 | 4699 | if (kvm_check_tsc_unstable()) { |
9b399dfd | 4700 | u64 offset = kvm_compute_l1_tsc_offset(vcpu, |
b183aa58 | 4701 | vcpu->arch.last_guest_tsc); |
a545ab6a | 4702 | kvm_vcpu_write_tsc_offset(vcpu, offset); |
c285545f | 4703 | vcpu->arch.tsc_catchup = 1; |
c285545f | 4704 | } |
a749e247 PB |
4705 | |
4706 | if (kvm_lapic_hv_timer_in_use(vcpu)) | |
4707 | kvm_lapic_restart_hv_timer(vcpu); | |
4708 | ||
d98d07ca MT |
4709 | /* |
4710 | * On a host with synchronized TSC, there is no need to update | |
4711 | * kvmclock on vcpu->cpu migration | |
4712 | */ | |
4713 | if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1) | |
0061d53d | 4714 | kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu); |
c285545f | 4715 | if (vcpu->cpu != cpu) |
1bd2009e | 4716 | kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu); |
e48672fa | 4717 | vcpu->cpu = cpu; |
6b7d7e76 | 4718 | } |
c9aaa895 | 4719 | |
c9aaa895 | 4720 | kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); |
313a3dc7 CO |
4721 | } |
4722 | ||
0b9f6c46 PX |
4723 | static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu) |
4724 | { | |
7e2175eb DW |
4725 | struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache; |
4726 | struct kvm_steal_time __user *st; | |
4727 | struct kvm_memslots *slots; | |
4728 | static const u8 preempted = KVM_VCPU_PREEMPTED; | |
c3c28d24 | 4729 | gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS; |
b0431382 | 4730 | |
6cd88243 PB |
4731 | /* |
4732 | * The vCPU can be marked preempted if and only if the VM-Exit was on | |
4733 | * an instruction boundary and will not trigger guest emulation of any | |
4734 | * kind (see vcpu_run). Vendor specific code controls (conservatively) | |
4735 | * when this is true, for example allowing the vCPU to be marked | |
4736 | * preempted if and only if the VM-Exit was due to a host interrupt. | |
4737 | */ | |
4738 | if (!vcpu->arch.at_instruction_boundary) { | |
4739 | vcpu->stat.preemption_other++; | |
4740 | return; | |
4741 | } | |
4742 | ||
4743 | vcpu->stat.preemption_reported++; | |
0b9f6c46 PX |
4744 | if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED)) |
4745 | return; | |
4746 | ||
a6bd811f | 4747 | if (vcpu->arch.st.preempted) |
8c6de56a BO |
4748 | return; |
4749 | ||
7e2175eb DW |
4750 | /* This happens on process exit */ |
4751 | if (unlikely(current->mm != vcpu->kvm->mm)) | |
9c1a0744 | 4752 | return; |
b0431382 | 4753 | |
7e2175eb DW |
4754 | slots = kvm_memslots(vcpu->kvm); |
4755 | ||
4756 | if (unlikely(slots->generation != ghc->generation || | |
c3c28d24 | 4757 | gpa != ghc->gpa || |
7e2175eb | 4758 | kvm_is_error_hva(ghc->hva) || !ghc->memslot)) |
9c1a0744 | 4759 | return; |
b0431382 | 4760 | |
7e2175eb DW |
4761 | st = (struct kvm_steal_time __user *)ghc->hva; |
4762 | BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted)); | |
0b9f6c46 | 4763 | |
7e2175eb DW |
4764 | if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted))) |
4765 | vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; | |
0b9f6c46 | 4766 | |
7e2175eb | 4767 | mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); |
0b9f6c46 PX |
4768 | } |
4769 | ||
313a3dc7 CO |
4770 | void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) |
4771 | { | |
9c1a0744 WL |
4772 | int idx; |
4773 | ||
54aa83c9 PB |
4774 | if (vcpu->preempted) { |
4775 | if (!vcpu->arch.guest_state_protected) | |
4776 | vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu); | |
de63ad4c | 4777 | |
54aa83c9 PB |
4778 | /* |
4779 | * Take the srcu lock as memslots will be accessed to check the gfn | |
4780 | * cache generation against the memslots generation. | |
4781 | */ | |
4782 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
4783 | if (kvm_xen_msr_enabled(vcpu->kvm)) | |
4784 | kvm_xen_runstate_set_preempted(vcpu); | |
4785 | else | |
4786 | kvm_steal_time_set_preempted(vcpu); | |
4787 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
4788 | } | |
30b5c851 | 4789 | |
b3646477 | 4790 | static_call(kvm_x86_vcpu_put)(vcpu); |
4ea1636b | 4791 | vcpu->arch.last_host_tsc = rdtsc(); |
313a3dc7 CO |
4792 | } |
4793 | ||
313a3dc7 CO |
4794 | static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, |
4795 | struct kvm_lapic_state *s) | |
4796 | { | |
37c4dbf3 | 4797 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); |
d62caabb | 4798 | |
a92e2543 | 4799 | return kvm_apic_get_state(vcpu, s); |
313a3dc7 CO |
4800 | } |
4801 | ||
4802 | static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, | |
4803 | struct kvm_lapic_state *s) | |
4804 | { | |
a92e2543 RK |
4805 | int r; |
4806 | ||
4807 | r = kvm_apic_set_state(vcpu, s); | |
4808 | if (r) | |
4809 | return r; | |
cb142eb7 | 4810 | update_cr8_intercept(vcpu); |
313a3dc7 CO |
4811 | |
4812 | return 0; | |
4813 | } | |
4814 | ||
127a457a MG |
4815 | static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu) |
4816 | { | |
71cc849b PB |
4817 | /* |
4818 | * We can accept userspace's request for interrupt injection | |
4819 | * as long as we have a place to store the interrupt number. | |
4820 | * The actual injection will happen when the CPU is able to | |
4821 | * deliver the interrupt. | |
4822 | */ | |
4823 | if (kvm_cpu_has_extint(vcpu)) | |
4824 | return false; | |
4825 | ||
4826 | /* Acknowledging ExtINT does not happen if LINT0 is masked. */ | |
127a457a MG |
4827 | return (!lapic_in_kernel(vcpu) || |
4828 | kvm_apic_accept_pic_intr(vcpu)); | |
4829 | } | |
4830 | ||
782d422b MG |
4831 | static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu) |
4832 | { | |
fa7a549d PB |
4833 | /* |
4834 | * Do not cause an interrupt window exit if an exception | |
4835 | * is pending or an event needs reinjection; userspace | |
4836 | * might want to inject the interrupt manually using KVM_SET_REGS | |
4837 | * or KVM_SET_SREGS. For that to work, we must be at an | |
4838 | * instruction boundary and with no events half-injected. | |
4839 | */ | |
4840 | return (kvm_arch_interrupt_allowed(vcpu) && | |
4841 | kvm_cpu_accept_dm_intr(vcpu) && | |
4842 | !kvm_event_needs_reinjection(vcpu) && | |
4843 | !vcpu->arch.exception.pending); | |
782d422b MG |
4844 | } |
4845 | ||
f77bc6a4 ZX |
4846 | static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, |
4847 | struct kvm_interrupt *irq) | |
4848 | { | |
02cdb50f | 4849 | if (irq->irq >= KVM_NR_INTERRUPTS) |
f77bc6a4 | 4850 | return -EINVAL; |
1c1a9ce9 SR |
4851 | |
4852 | if (!irqchip_in_kernel(vcpu->kvm)) { | |
4853 | kvm_queue_interrupt(vcpu, irq->irq, false); | |
4854 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
4855 | return 0; | |
4856 | } | |
4857 | ||
4858 | /* | |
4859 | * With in-kernel LAPIC, we only use this to inject EXTINT, so | |
4860 | * fail for in-kernel 8259. | |
4861 | */ | |
4862 | if (pic_in_kernel(vcpu->kvm)) | |
f77bc6a4 | 4863 | return -ENXIO; |
f77bc6a4 | 4864 | |
1c1a9ce9 SR |
4865 | if (vcpu->arch.pending_external_vector != -1) |
4866 | return -EEXIST; | |
f77bc6a4 | 4867 | |
1c1a9ce9 | 4868 | vcpu->arch.pending_external_vector = irq->irq; |
934bf653 | 4869 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f77bc6a4 ZX |
4870 | return 0; |
4871 | } | |
4872 | ||
c4abb7c9 JK |
4873 | static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu) |
4874 | { | |
c4abb7c9 | 4875 | kvm_inject_nmi(vcpu); |
c4abb7c9 JK |
4876 | |
4877 | return 0; | |
4878 | } | |
4879 | ||
f077825a PB |
4880 | static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu) |
4881 | { | |
64d60670 PB |
4882 | kvm_make_request(KVM_REQ_SMI, vcpu); |
4883 | ||
f077825a PB |
4884 | return 0; |
4885 | } | |
4886 | ||
b209749f AK |
4887 | static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu, |
4888 | struct kvm_tpr_access_ctl *tac) | |
4889 | { | |
4890 | if (tac->flags) | |
4891 | return -EINVAL; | |
4892 | vcpu->arch.tpr_access_reporting = !!tac->enabled; | |
4893 | return 0; | |
4894 | } | |
4895 | ||
890ca9ae HY |
4896 | static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu, |
4897 | u64 mcg_cap) | |
4898 | { | |
4899 | int r; | |
4900 | unsigned bank_num = mcg_cap & 0xff, bank; | |
4901 | ||
4902 | r = -EINVAL; | |
c4e0e4ab | 4903 | if (!bank_num || bank_num > KVM_MAX_MCE_BANKS) |
890ca9ae | 4904 | goto out; |
938c8745 | 4905 | if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000)) |
890ca9ae HY |
4906 | goto out; |
4907 | r = 0; | |
4908 | vcpu->arch.mcg_cap = mcg_cap; | |
4909 | /* Init IA32_MCG_CTL to all 1s */ | |
4910 | if (mcg_cap & MCG_CTL_P) | |
4911 | vcpu->arch.mcg_ctl = ~(u64)0; | |
281b5278 JW |
4912 | /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */ |
4913 | for (bank = 0; bank < bank_num; bank++) { | |
890ca9ae | 4914 | vcpu->arch.mce_banks[bank*4] = ~(u64)0; |
281b5278 JW |
4915 | if (mcg_cap & MCG_CMCI_P) |
4916 | vcpu->arch.mci_ctl2_banks[bank] = 0; | |
4917 | } | |
f83894b2 SC |
4918 | |
4919 | kvm_apic_after_set_mcg_cap(vcpu); | |
c45dcc71 | 4920 | |
b3646477 | 4921 | static_call(kvm_x86_setup_mce)(vcpu); |
890ca9ae HY |
4922 | out: |
4923 | return r; | |
4924 | } | |
4925 | ||
aebc3ca1 JW |
4926 | /* |
4927 | * Validate this is an UCNA (uncorrectable no action) error by checking the | |
4928 | * MCG_STATUS and MCi_STATUS registers: | |
4929 | * - none of the bits for Machine Check Exceptions are set | |
4930 | * - both the VAL (valid) and UC (uncorrectable) bits are set | |
4931 | * MCI_STATUS_PCC - Processor Context Corrupted | |
4932 | * MCI_STATUS_S - Signaled as a Machine Check Exception | |
4933 | * MCI_STATUS_AR - Software recoverable Action Required | |
4934 | */ | |
4935 | static bool is_ucna(struct kvm_x86_mce *mce) | |
4936 | { | |
4937 | return !mce->mcg_status && | |
4938 | !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) && | |
4939 | (mce->status & MCI_STATUS_VAL) && | |
4940 | (mce->status & MCI_STATUS_UC); | |
4941 | } | |
4942 | ||
4943 | static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks) | |
4944 | { | |
4945 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
4946 | ||
4947 | banks[1] = mce->status; | |
4948 | banks[2] = mce->addr; | |
4949 | banks[3] = mce->misc; | |
4950 | vcpu->arch.mcg_status = mce->mcg_status; | |
4951 | ||
4952 | if (!(mcg_cap & MCG_CMCI_P) || | |
4953 | !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN)) | |
4954 | return 0; | |
4955 | ||
4956 | if (lapic_in_kernel(vcpu)) | |
4957 | kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI); | |
4958 | ||
4959 | return 0; | |
4960 | } | |
4961 | ||
890ca9ae HY |
4962 | static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu, |
4963 | struct kvm_x86_mce *mce) | |
4964 | { | |
4965 | u64 mcg_cap = vcpu->arch.mcg_cap; | |
4966 | unsigned bank_num = mcg_cap & 0xff; | |
4967 | u64 *banks = vcpu->arch.mce_banks; | |
4968 | ||
4969 | if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL)) | |
4970 | return -EINVAL; | |
aebc3ca1 JW |
4971 | |
4972 | banks += array_index_nospec(4 * mce->bank, 4 * bank_num); | |
4973 | ||
4974 | if (is_ucna(mce)) | |
4975 | return kvm_vcpu_x86_set_ucna(vcpu, mce, banks); | |
4976 | ||
890ca9ae HY |
4977 | /* |
4978 | * if IA32_MCG_CTL is not all 1s, the uncorrected error | |
4979 | * reporting is disabled | |
4980 | */ | |
4981 | if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) && | |
4982 | vcpu->arch.mcg_ctl != ~(u64)0) | |
4983 | return 0; | |
890ca9ae HY |
4984 | /* |
4985 | * if IA32_MCi_CTL is not all 1s, the uncorrected error | |
4986 | * reporting is disabled for the bank | |
4987 | */ | |
4988 | if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0) | |
4989 | return 0; | |
4990 | if (mce->status & MCI_STATUS_UC) { | |
4991 | if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) || | |
fc78f519 | 4992 | !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) { |
a8eeb04a | 4993 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
890ca9ae HY |
4994 | return 0; |
4995 | } | |
4996 | if (banks[1] & MCI_STATUS_VAL) | |
4997 | mce->status |= MCI_STATUS_OVER; | |
4998 | banks[2] = mce->addr; | |
4999 | banks[3] = mce->misc; | |
5000 | vcpu->arch.mcg_status = mce->mcg_status; | |
5001 | banks[1] = mce->status; | |
5002 | kvm_queue_exception(vcpu, MC_VECTOR); | |
5003 | } else if (!(banks[1] & MCI_STATUS_VAL) | |
5004 | || !(banks[1] & MCI_STATUS_UC)) { | |
5005 | if (banks[1] & MCI_STATUS_VAL) | |
5006 | mce->status |= MCI_STATUS_OVER; | |
5007 | banks[2] = mce->addr; | |
5008 | banks[3] = mce->misc; | |
5009 | banks[1] = mce->status; | |
5010 | } else | |
5011 | banks[1] |= MCI_STATUS_OVER; | |
5012 | return 0; | |
5013 | } | |
5014 | ||
3cfc3092 JK |
5015 | static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu, |
5016 | struct kvm_vcpu_events *events) | |
5017 | { | |
7460fb4a | 5018 | process_nmi(vcpu); |
59073aaf | 5019 | |
1f7becf1 JZ |
5020 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
5021 | process_smi(vcpu); | |
5022 | ||
a06230b6 OU |
5023 | /* |
5024 | * In guest mode, payload delivery should be deferred, | |
5025 | * so that the L1 hypervisor can intercept #PF before | |
5026 | * CR2 is modified (or intercept #DB before DR6 is | |
5027 | * modified under nVMX). Unless the per-VM capability, | |
5028 | * KVM_CAP_EXCEPTION_PAYLOAD, is set, we may not defer the delivery of | |
5029 | * an exception payload and handle after a KVM_GET_VCPU_EVENTS. Since we | |
5030 | * opportunistically defer the exception payload, deliver it if the | |
5031 | * capability hasn't been requested before processing a | |
5032 | * KVM_GET_VCPU_EVENTS. | |
5033 | */ | |
5034 | if (!vcpu->kvm->arch.exception_payload_enabled && | |
5035 | vcpu->arch.exception.pending && vcpu->arch.exception.has_payload) | |
5036 | kvm_deliver_exception_payload(vcpu); | |
5037 | ||
664f8e26 | 5038 | /* |
59073aaf JM |
5039 | * The API doesn't provide the instruction length for software |
5040 | * exceptions, so don't report them. As long as the guest RIP | |
5041 | * isn't advanced, we should expect to encounter the exception | |
5042 | * again. | |
664f8e26 | 5043 | */ |
59073aaf JM |
5044 | if (kvm_exception_is_soft(vcpu->arch.exception.nr)) { |
5045 | events->exception.injected = 0; | |
5046 | events->exception.pending = 0; | |
5047 | } else { | |
5048 | events->exception.injected = vcpu->arch.exception.injected; | |
5049 | events->exception.pending = vcpu->arch.exception.pending; | |
5050 | /* | |
5051 | * For ABI compatibility, deliberately conflate | |
5052 | * pending and injected exceptions when | |
5053 | * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled. | |
5054 | */ | |
5055 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
5056 | events->exception.injected |= | |
5057 | vcpu->arch.exception.pending; | |
5058 | } | |
3cfc3092 JK |
5059 | events->exception.nr = vcpu->arch.exception.nr; |
5060 | events->exception.has_error_code = vcpu->arch.exception.has_error_code; | |
5061 | events->exception.error_code = vcpu->arch.exception.error_code; | |
59073aaf JM |
5062 | events->exception_has_payload = vcpu->arch.exception.has_payload; |
5063 | events->exception_payload = vcpu->arch.exception.payload; | |
3cfc3092 | 5064 | |
03b82a30 | 5065 | events->interrupt.injected = |
04140b41 | 5066 | vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft; |
3cfc3092 | 5067 | events->interrupt.nr = vcpu->arch.interrupt.nr; |
03b82a30 | 5068 | events->interrupt.soft = 0; |
b3646477 | 5069 | events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
3cfc3092 JK |
5070 | |
5071 | events->nmi.injected = vcpu->arch.nmi_injected; | |
7460fb4a | 5072 | events->nmi.pending = vcpu->arch.nmi_pending != 0; |
b3646477 | 5073 | events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu); |
97e69aa6 | 5074 | events->nmi.pad = 0; |
3cfc3092 | 5075 | |
66450a21 | 5076 | events->sipi_vector = 0; /* never valid when reporting to user space */ |
3cfc3092 | 5077 | |
f077825a PB |
5078 | events->smi.smm = is_smm(vcpu); |
5079 | events->smi.pending = vcpu->arch.smi_pending; | |
5080 | events->smi.smm_inside_nmi = | |
5081 | !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK); | |
5082 | events->smi.latched_init = kvm_lapic_latched_init(vcpu); | |
5083 | ||
dab4b911 | 5084 | events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING |
f077825a PB |
5085 | | KVM_VCPUEVENT_VALID_SHADOW |
5086 | | KVM_VCPUEVENT_VALID_SMM); | |
59073aaf JM |
5087 | if (vcpu->kvm->arch.exception_payload_enabled) |
5088 | events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
ed235117 CQ |
5089 | if (vcpu->kvm->arch.triple_fault_event) { |
5090 | events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
5091 | events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT; | |
5092 | } | |
59073aaf | 5093 | |
97e69aa6 | 5094 | memset(&events->reserved, 0, sizeof(events->reserved)); |
3cfc3092 JK |
5095 | } |
5096 | ||
dc87275f | 5097 | static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm); |
6ef4e07e | 5098 | |
3cfc3092 JK |
5099 | static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu, |
5100 | struct kvm_vcpu_events *events) | |
5101 | { | |
dab4b911 | 5102 | if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING |
48005f64 | 5103 | | KVM_VCPUEVENT_VALID_SIPI_VECTOR |
f077825a | 5104 | | KVM_VCPUEVENT_VALID_SHADOW |
59073aaf | 5105 | | KVM_VCPUEVENT_VALID_SMM |
ed235117 CQ |
5106 | | KVM_VCPUEVENT_VALID_PAYLOAD |
5107 | | KVM_VCPUEVENT_VALID_TRIPLE_FAULT)) | |
3cfc3092 JK |
5108 | return -EINVAL; |
5109 | ||
59073aaf JM |
5110 | if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) { |
5111 | if (!vcpu->kvm->arch.exception_payload_enabled) | |
5112 | return -EINVAL; | |
5113 | if (events->exception.pending) | |
5114 | events->exception.injected = 0; | |
5115 | else | |
5116 | events->exception_has_payload = 0; | |
5117 | } else { | |
5118 | events->exception.pending = 0; | |
5119 | events->exception_has_payload = 0; | |
5120 | } | |
5121 | ||
5122 | if ((events->exception.injected || events->exception.pending) && | |
5123 | (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR)) | |
78e546c8 PB |
5124 | return -EINVAL; |
5125 | ||
28bf2888 DH |
5126 | /* INITs are latched while in SMM */ |
5127 | if (events->flags & KVM_VCPUEVENT_VALID_SMM && | |
5128 | (events->smi.smm || events->smi.pending) && | |
5129 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) | |
5130 | return -EINVAL; | |
5131 | ||
7460fb4a | 5132 | process_nmi(vcpu); |
59073aaf JM |
5133 | vcpu->arch.exception.injected = events->exception.injected; |
5134 | vcpu->arch.exception.pending = events->exception.pending; | |
3cfc3092 JK |
5135 | vcpu->arch.exception.nr = events->exception.nr; |
5136 | vcpu->arch.exception.has_error_code = events->exception.has_error_code; | |
5137 | vcpu->arch.exception.error_code = events->exception.error_code; | |
59073aaf JM |
5138 | vcpu->arch.exception.has_payload = events->exception_has_payload; |
5139 | vcpu->arch.exception.payload = events->exception_payload; | |
3cfc3092 | 5140 | |
04140b41 | 5141 | vcpu->arch.interrupt.injected = events->interrupt.injected; |
3cfc3092 JK |
5142 | vcpu->arch.interrupt.nr = events->interrupt.nr; |
5143 | vcpu->arch.interrupt.soft = events->interrupt.soft; | |
48005f64 | 5144 | if (events->flags & KVM_VCPUEVENT_VALID_SHADOW) |
b3646477 JB |
5145 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, |
5146 | events->interrupt.shadow); | |
3cfc3092 JK |
5147 | |
5148 | vcpu->arch.nmi_injected = events->nmi.injected; | |
dab4b911 JK |
5149 | if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) |
5150 | vcpu->arch.nmi_pending = events->nmi.pending; | |
b3646477 | 5151 | static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked); |
3cfc3092 | 5152 | |
66450a21 | 5153 | if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR && |
bce87cce | 5154 | lapic_in_kernel(vcpu)) |
66450a21 | 5155 | vcpu->arch.apic->sipi_vector = events->sipi_vector; |
3cfc3092 | 5156 | |
f077825a | 5157 | if (events->flags & KVM_VCPUEVENT_VALID_SMM) { |
f7e57078 SC |
5158 | if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) { |
5159 | kvm_x86_ops.nested_ops->leave_nested(vcpu); | |
dc87275f | 5160 | kvm_smm_changed(vcpu, events->smi.smm); |
f7e57078 | 5161 | } |
6ef4e07e | 5162 | |
f077825a | 5163 | vcpu->arch.smi_pending = events->smi.pending; |
f4ef1910 WL |
5164 | |
5165 | if (events->smi.smm) { | |
5166 | if (events->smi.smm_inside_nmi) | |
5167 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; | |
f077825a | 5168 | else |
f4ef1910 | 5169 | vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK; |
ff90afa7 LA |
5170 | } |
5171 | ||
5172 | if (lapic_in_kernel(vcpu)) { | |
5173 | if (events->smi.latched_init) | |
5174 | set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
5175 | else | |
5176 | clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); | |
f077825a PB |
5177 | } |
5178 | } | |
5179 | ||
ed235117 CQ |
5180 | if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) { |
5181 | if (!vcpu->kvm->arch.triple_fault_event) | |
5182 | return -EINVAL; | |
5183 | if (events->triple_fault.pending) | |
5184 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
5185 | else | |
5186 | kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
5187 | } | |
5188 | ||
3842d135 AK |
5189 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5190 | ||
3cfc3092 JK |
5191 | return 0; |
5192 | } | |
5193 | ||
a1efbe77 JK |
5194 | static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu, |
5195 | struct kvm_debugregs *dbgregs) | |
5196 | { | |
73aaf249 JK |
5197 | unsigned long val; |
5198 | ||
a1efbe77 | 5199 | memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db)); |
16f8a6f9 | 5200 | kvm_get_dr(vcpu, 6, &val); |
73aaf249 | 5201 | dbgregs->dr6 = val; |
a1efbe77 JK |
5202 | dbgregs->dr7 = vcpu->arch.dr7; |
5203 | dbgregs->flags = 0; | |
97e69aa6 | 5204 | memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved)); |
a1efbe77 JK |
5205 | } |
5206 | ||
5207 | static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu, | |
5208 | struct kvm_debugregs *dbgregs) | |
5209 | { | |
5210 | if (dbgregs->flags) | |
5211 | return -EINVAL; | |
5212 | ||
fd238002 | 5213 | if (!kvm_dr6_valid(dbgregs->dr6)) |
d14bdb55 | 5214 | return -EINVAL; |
fd238002 | 5215 | if (!kvm_dr7_valid(dbgregs->dr7)) |
d14bdb55 PB |
5216 | return -EINVAL; |
5217 | ||
a1efbe77 | 5218 | memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db)); |
ae561ede | 5219 | kvm_update_dr0123(vcpu); |
a1efbe77 JK |
5220 | vcpu->arch.dr6 = dbgregs->dr6; |
5221 | vcpu->arch.dr7 = dbgregs->dr7; | |
9926c9fd | 5222 | kvm_update_dr7(vcpu); |
a1efbe77 | 5223 | |
a1efbe77 JK |
5224 | return 0; |
5225 | } | |
5226 | ||
2d5b5a66 SY |
5227 | static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu, |
5228 | struct kvm_xsave *guest_xsave) | |
5229 | { | |
d69c1382 | 5230 | if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) |
ed02b213 TL |
5231 | return; |
5232 | ||
d69c1382 TG |
5233 | fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, |
5234 | guest_xsave->region, | |
5235 | sizeof(guest_xsave->region), | |
5236 | vcpu->arch.pkru); | |
2d5b5a66 SY |
5237 | } |
5238 | ||
be50b206 GZ |
5239 | static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu, |
5240 | u8 *state, unsigned int size) | |
5241 | { | |
5242 | if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) | |
5243 | return; | |
5244 | ||
5245 | fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, | |
5246 | state, size, vcpu->arch.pkru); | |
5247 | } | |
5248 | ||
2d5b5a66 SY |
5249 | static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu, |
5250 | struct kvm_xsave *guest_xsave) | |
5251 | { | |
d69c1382 | 5252 | if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) |
ed02b213 TL |
5253 | return 0; |
5254 | ||
d69c1382 TG |
5255 | return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu, |
5256 | guest_xsave->region, | |
938c8745 SC |
5257 | kvm_caps.supported_xcr0, |
5258 | &vcpu->arch.pkru); | |
2d5b5a66 SY |
5259 | } |
5260 | ||
5261 | static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu, | |
5262 | struct kvm_xcrs *guest_xcrs) | |
5263 | { | |
d366bf7e | 5264 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) { |
2d5b5a66 SY |
5265 | guest_xcrs->nr_xcrs = 0; |
5266 | return; | |
5267 | } | |
5268 | ||
5269 | guest_xcrs->nr_xcrs = 1; | |
5270 | guest_xcrs->flags = 0; | |
5271 | guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK; | |
5272 | guest_xcrs->xcrs[0].value = vcpu->arch.xcr0; | |
5273 | } | |
5274 | ||
5275 | static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu, | |
5276 | struct kvm_xcrs *guest_xcrs) | |
5277 | { | |
5278 | int i, r = 0; | |
5279 | ||
d366bf7e | 5280 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) |
2d5b5a66 SY |
5281 | return -EINVAL; |
5282 | ||
5283 | if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags) | |
5284 | return -EINVAL; | |
5285 | ||
5286 | for (i = 0; i < guest_xcrs->nr_xcrs; i++) | |
5287 | /* Only support XCR0 currently */ | |
c67a04cb | 5288 | if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) { |
2d5b5a66 | 5289 | r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK, |
c67a04cb | 5290 | guest_xcrs->xcrs[i].value); |
2d5b5a66 SY |
5291 | break; |
5292 | } | |
5293 | if (r) | |
5294 | r = -EINVAL; | |
5295 | return r; | |
5296 | } | |
5297 | ||
1c0b28c2 EM |
5298 | /* |
5299 | * kvm_set_guest_paused() indicates to the guest kernel that it has been | |
5300 | * stopped by the hypervisor. This function will be called from the host only. | |
5301 | * EINVAL is returned when the host attempts to set the flag for a guest that | |
5302 | * does not support pv clocks. | |
5303 | */ | |
5304 | static int kvm_set_guest_paused(struct kvm_vcpu *vcpu) | |
5305 | { | |
916d3608 | 5306 | if (!vcpu->arch.pv_time.active) |
1c0b28c2 | 5307 | return -EINVAL; |
51d59c6b | 5308 | vcpu->arch.pvclock_set_guest_stopped_request = true; |
1c0b28c2 EM |
5309 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
5310 | return 0; | |
5311 | } | |
5312 | ||
828ca896 OU |
5313 | static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu, |
5314 | struct kvm_device_attr *attr) | |
5315 | { | |
5316 | int r; | |
5317 | ||
5318 | switch (attr->attr) { | |
5319 | case KVM_VCPU_TSC_OFFSET: | |
5320 | r = 0; | |
5321 | break; | |
5322 | default: | |
5323 | r = -ENXIO; | |
5324 | } | |
5325 | ||
5326 | return r; | |
5327 | } | |
5328 | ||
5329 | static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu, | |
5330 | struct kvm_device_attr *attr) | |
5331 | { | |
56f289a8 | 5332 | u64 __user *uaddr = kvm_get_attr_addr(attr); |
828ca896 OU |
5333 | int r; |
5334 | ||
56f289a8 SC |
5335 | if (IS_ERR(uaddr)) |
5336 | return PTR_ERR(uaddr); | |
828ca896 OU |
5337 | |
5338 | switch (attr->attr) { | |
5339 | case KVM_VCPU_TSC_OFFSET: | |
5340 | r = -EFAULT; | |
5341 | if (put_user(vcpu->arch.l1_tsc_offset, uaddr)) | |
5342 | break; | |
5343 | r = 0; | |
5344 | break; | |
5345 | default: | |
5346 | r = -ENXIO; | |
5347 | } | |
5348 | ||
5349 | return r; | |
5350 | } | |
5351 | ||
5352 | static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu, | |
5353 | struct kvm_device_attr *attr) | |
5354 | { | |
56f289a8 | 5355 | u64 __user *uaddr = kvm_get_attr_addr(attr); |
828ca896 OU |
5356 | struct kvm *kvm = vcpu->kvm; |
5357 | int r; | |
5358 | ||
56f289a8 SC |
5359 | if (IS_ERR(uaddr)) |
5360 | return PTR_ERR(uaddr); | |
828ca896 OU |
5361 | |
5362 | switch (attr->attr) { | |
5363 | case KVM_VCPU_TSC_OFFSET: { | |
5364 | u64 offset, tsc, ns; | |
5365 | unsigned long flags; | |
5366 | bool matched; | |
5367 | ||
5368 | r = -EFAULT; | |
5369 | if (get_user(offset, uaddr)) | |
5370 | break; | |
5371 | ||
5372 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); | |
5373 | ||
5374 | matched = (vcpu->arch.virtual_tsc_khz && | |
5375 | kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz && | |
5376 | kvm->arch.last_tsc_offset == offset); | |
5377 | ||
62711e5a | 5378 | tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset; |
828ca896 OU |
5379 | ns = get_kvmclock_base_ns(); |
5380 | ||
5381 | __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched); | |
5382 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); | |
5383 | ||
5384 | r = 0; | |
5385 | break; | |
5386 | } | |
5387 | default: | |
5388 | r = -ENXIO; | |
5389 | } | |
5390 | ||
5391 | return r; | |
5392 | } | |
5393 | ||
5394 | static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu, | |
5395 | unsigned int ioctl, | |
5396 | void __user *argp) | |
5397 | { | |
5398 | struct kvm_device_attr attr; | |
5399 | int r; | |
5400 | ||
5401 | if (copy_from_user(&attr, argp, sizeof(attr))) | |
5402 | return -EFAULT; | |
5403 | ||
5404 | if (attr.group != KVM_VCPU_TSC_CTRL) | |
5405 | return -ENXIO; | |
5406 | ||
5407 | switch (ioctl) { | |
5408 | case KVM_HAS_DEVICE_ATTR: | |
5409 | r = kvm_arch_tsc_has_attr(vcpu, &attr); | |
5410 | break; | |
5411 | case KVM_GET_DEVICE_ATTR: | |
5412 | r = kvm_arch_tsc_get_attr(vcpu, &attr); | |
5413 | break; | |
5414 | case KVM_SET_DEVICE_ATTR: | |
5415 | r = kvm_arch_tsc_set_attr(vcpu, &attr); | |
5416 | break; | |
5417 | } | |
5418 | ||
5419 | return r; | |
5420 | } | |
5421 | ||
5c919412 AS |
5422 | static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, |
5423 | struct kvm_enable_cap *cap) | |
5424 | { | |
57b119da VK |
5425 | int r; |
5426 | uint16_t vmcs_version; | |
5427 | void __user *user_ptr; | |
5428 | ||
5c919412 AS |
5429 | if (cap->flags) |
5430 | return -EINVAL; | |
5431 | ||
5432 | switch (cap->cap) { | |
efc479e6 RK |
5433 | case KVM_CAP_HYPERV_SYNIC2: |
5434 | if (cap->args[0]) | |
5435 | return -EINVAL; | |
df561f66 | 5436 | fallthrough; |
b2869f28 | 5437 | |
5c919412 | 5438 | case KVM_CAP_HYPERV_SYNIC: |
546d87e5 WL |
5439 | if (!irqchip_in_kernel(vcpu->kvm)) |
5440 | return -EINVAL; | |
efc479e6 RK |
5441 | return kvm_hv_activate_synic(vcpu, cap->cap == |
5442 | KVM_CAP_HYPERV_SYNIC2); | |
57b119da | 5443 | case KVM_CAP_HYPERV_ENLIGHTENED_VMCS: |
33b22172 | 5444 | if (!kvm_x86_ops.nested_ops->enable_evmcs) |
5158917c | 5445 | return -ENOTTY; |
33b22172 | 5446 | r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version); |
57b119da VK |
5447 | if (!r) { |
5448 | user_ptr = (void __user *)(uintptr_t)cap->args[0]; | |
5449 | if (copy_to_user(user_ptr, &vmcs_version, | |
5450 | sizeof(vmcs_version))) | |
5451 | r = -EFAULT; | |
5452 | } | |
5453 | return r; | |
344c6c80 | 5454 | case KVM_CAP_HYPERV_DIRECT_TLBFLUSH: |
afaf0b2f | 5455 | if (!kvm_x86_ops.enable_direct_tlbflush) |
344c6c80 TL |
5456 | return -ENOTTY; |
5457 | ||
b3646477 | 5458 | return static_call(kvm_x86_enable_direct_tlbflush)(vcpu); |
57b119da | 5459 | |
644f7067 VK |
5460 | case KVM_CAP_HYPERV_ENFORCE_CPUID: |
5461 | return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]); | |
5462 | ||
66570e96 OU |
5463 | case KVM_CAP_ENFORCE_PV_FEATURE_CPUID: |
5464 | vcpu->arch.pv_cpuid.enforce = cap->args[0]; | |
01b4f510 OU |
5465 | if (vcpu->arch.pv_cpuid.enforce) |
5466 | kvm_update_pv_runtime(vcpu); | |
66570e96 OU |
5467 | |
5468 | return 0; | |
5c919412 AS |
5469 | default: |
5470 | return -EINVAL; | |
5471 | } | |
5472 | } | |
5473 | ||
313a3dc7 CO |
5474 | long kvm_arch_vcpu_ioctl(struct file *filp, |
5475 | unsigned int ioctl, unsigned long arg) | |
5476 | { | |
5477 | struct kvm_vcpu *vcpu = filp->private_data; | |
5478 | void __user *argp = (void __user *)arg; | |
5479 | int r; | |
d1ac91d8 | 5480 | union { |
6dba9403 | 5481 | struct kvm_sregs2 *sregs2; |
d1ac91d8 AK |
5482 | struct kvm_lapic_state *lapic; |
5483 | struct kvm_xsave *xsave; | |
5484 | struct kvm_xcrs *xcrs; | |
5485 | void *buffer; | |
5486 | } u; | |
5487 | ||
9b062471 CD |
5488 | vcpu_load(vcpu); |
5489 | ||
d1ac91d8 | 5490 | u.buffer = NULL; |
313a3dc7 CO |
5491 | switch (ioctl) { |
5492 | case KVM_GET_LAPIC: { | |
2204ae3c | 5493 | r = -EINVAL; |
bce87cce | 5494 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 5495 | goto out; |
254272ce BG |
5496 | u.lapic = kzalloc(sizeof(struct kvm_lapic_state), |
5497 | GFP_KERNEL_ACCOUNT); | |
313a3dc7 | 5498 | |
b772ff36 | 5499 | r = -ENOMEM; |
d1ac91d8 | 5500 | if (!u.lapic) |
b772ff36 | 5501 | goto out; |
d1ac91d8 | 5502 | r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); |
313a3dc7 CO |
5503 | if (r) |
5504 | goto out; | |
5505 | r = -EFAULT; | |
d1ac91d8 | 5506 | if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) |
313a3dc7 CO |
5507 | goto out; |
5508 | r = 0; | |
5509 | break; | |
5510 | } | |
5511 | case KVM_SET_LAPIC: { | |
2204ae3c | 5512 | r = -EINVAL; |
bce87cce | 5513 | if (!lapic_in_kernel(vcpu)) |
2204ae3c | 5514 | goto out; |
ff5c2c03 | 5515 | u.lapic = memdup_user(argp, sizeof(*u.lapic)); |
9b062471 CD |
5516 | if (IS_ERR(u.lapic)) { |
5517 | r = PTR_ERR(u.lapic); | |
5518 | goto out_nofree; | |
5519 | } | |
ff5c2c03 | 5520 | |
d1ac91d8 | 5521 | r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); |
313a3dc7 CO |
5522 | break; |
5523 | } | |
f77bc6a4 ZX |
5524 | case KVM_INTERRUPT: { |
5525 | struct kvm_interrupt irq; | |
5526 | ||
5527 | r = -EFAULT; | |
0e96f31e | 5528 | if (copy_from_user(&irq, argp, sizeof(irq))) |
f77bc6a4 ZX |
5529 | goto out; |
5530 | r = kvm_vcpu_ioctl_interrupt(vcpu, &irq); | |
f77bc6a4 ZX |
5531 | break; |
5532 | } | |
c4abb7c9 JK |
5533 | case KVM_NMI: { |
5534 | r = kvm_vcpu_ioctl_nmi(vcpu); | |
c4abb7c9 JK |
5535 | break; |
5536 | } | |
f077825a PB |
5537 | case KVM_SMI: { |
5538 | r = kvm_vcpu_ioctl_smi(vcpu); | |
5539 | break; | |
5540 | } | |
313a3dc7 CO |
5541 | case KVM_SET_CPUID: { |
5542 | struct kvm_cpuid __user *cpuid_arg = argp; | |
5543 | struct kvm_cpuid cpuid; | |
5544 | ||
5545 | r = -EFAULT; | |
0e96f31e | 5546 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
313a3dc7 CO |
5547 | goto out; |
5548 | r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries); | |
313a3dc7 CO |
5549 | break; |
5550 | } | |
07716717 DK |
5551 | case KVM_SET_CPUID2: { |
5552 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
5553 | struct kvm_cpuid2 cpuid; | |
5554 | ||
5555 | r = -EFAULT; | |
0e96f31e | 5556 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
5557 | goto out; |
5558 | r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid, | |
19355475 | 5559 | cpuid_arg->entries); |
07716717 DK |
5560 | break; |
5561 | } | |
5562 | case KVM_GET_CPUID2: { | |
5563 | struct kvm_cpuid2 __user *cpuid_arg = argp; | |
5564 | struct kvm_cpuid2 cpuid; | |
5565 | ||
5566 | r = -EFAULT; | |
0e96f31e | 5567 | if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid))) |
07716717 DK |
5568 | goto out; |
5569 | r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid, | |
19355475 | 5570 | cpuid_arg->entries); |
07716717 DK |
5571 | if (r) |
5572 | goto out; | |
5573 | r = -EFAULT; | |
0e96f31e | 5574 | if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid))) |
07716717 DK |
5575 | goto out; |
5576 | r = 0; | |
5577 | break; | |
5578 | } | |
801e459a TL |
5579 | case KVM_GET_MSRS: { |
5580 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
609e36d3 | 5581 | r = msr_io(vcpu, argp, do_get_msr, 1); |
801e459a | 5582 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 5583 | break; |
801e459a TL |
5584 | } |
5585 | case KVM_SET_MSRS: { | |
5586 | int idx = srcu_read_lock(&vcpu->kvm->srcu); | |
313a3dc7 | 5587 | r = msr_io(vcpu, argp, do_set_msr, 0); |
801e459a | 5588 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
313a3dc7 | 5589 | break; |
801e459a | 5590 | } |
b209749f AK |
5591 | case KVM_TPR_ACCESS_REPORTING: { |
5592 | struct kvm_tpr_access_ctl tac; | |
5593 | ||
5594 | r = -EFAULT; | |
0e96f31e | 5595 | if (copy_from_user(&tac, argp, sizeof(tac))) |
b209749f AK |
5596 | goto out; |
5597 | r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac); | |
5598 | if (r) | |
5599 | goto out; | |
5600 | r = -EFAULT; | |
0e96f31e | 5601 | if (copy_to_user(argp, &tac, sizeof(tac))) |
b209749f AK |
5602 | goto out; |
5603 | r = 0; | |
5604 | break; | |
5605 | }; | |
b93463aa AK |
5606 | case KVM_SET_VAPIC_ADDR: { |
5607 | struct kvm_vapic_addr va; | |
7301d6ab | 5608 | int idx; |
b93463aa AK |
5609 | |
5610 | r = -EINVAL; | |
35754c98 | 5611 | if (!lapic_in_kernel(vcpu)) |
b93463aa AK |
5612 | goto out; |
5613 | r = -EFAULT; | |
0e96f31e | 5614 | if (copy_from_user(&va, argp, sizeof(va))) |
b93463aa | 5615 | goto out; |
7301d6ab | 5616 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
fda4e2e8 | 5617 | r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr); |
7301d6ab | 5618 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
b93463aa AK |
5619 | break; |
5620 | } | |
890ca9ae HY |
5621 | case KVM_X86_SETUP_MCE: { |
5622 | u64 mcg_cap; | |
5623 | ||
5624 | r = -EFAULT; | |
0e96f31e | 5625 | if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap))) |
890ca9ae HY |
5626 | goto out; |
5627 | r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap); | |
5628 | break; | |
5629 | } | |
5630 | case KVM_X86_SET_MCE: { | |
5631 | struct kvm_x86_mce mce; | |
5632 | ||
5633 | r = -EFAULT; | |
0e96f31e | 5634 | if (copy_from_user(&mce, argp, sizeof(mce))) |
890ca9ae HY |
5635 | goto out; |
5636 | r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce); | |
5637 | break; | |
5638 | } | |
3cfc3092 JK |
5639 | case KVM_GET_VCPU_EVENTS: { |
5640 | struct kvm_vcpu_events events; | |
5641 | ||
5642 | kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events); | |
5643 | ||
5644 | r = -EFAULT; | |
5645 | if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events))) | |
5646 | break; | |
5647 | r = 0; | |
5648 | break; | |
5649 | } | |
5650 | case KVM_SET_VCPU_EVENTS: { | |
5651 | struct kvm_vcpu_events events; | |
5652 | ||
5653 | r = -EFAULT; | |
5654 | if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events))) | |
5655 | break; | |
5656 | ||
5657 | r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events); | |
5658 | break; | |
5659 | } | |
a1efbe77 JK |
5660 | case KVM_GET_DEBUGREGS: { |
5661 | struct kvm_debugregs dbgregs; | |
5662 | ||
5663 | kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs); | |
5664 | ||
5665 | r = -EFAULT; | |
5666 | if (copy_to_user(argp, &dbgregs, | |
5667 | sizeof(struct kvm_debugregs))) | |
5668 | break; | |
5669 | r = 0; | |
5670 | break; | |
5671 | } | |
5672 | case KVM_SET_DEBUGREGS: { | |
5673 | struct kvm_debugregs dbgregs; | |
5674 | ||
5675 | r = -EFAULT; | |
5676 | if (copy_from_user(&dbgregs, argp, | |
5677 | sizeof(struct kvm_debugregs))) | |
5678 | break; | |
5679 | ||
5680 | r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs); | |
5681 | break; | |
5682 | } | |
2d5b5a66 | 5683 | case KVM_GET_XSAVE: { |
be50b206 GZ |
5684 | r = -EINVAL; |
5685 | if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave)) | |
5686 | break; | |
5687 | ||
254272ce | 5688 | u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5689 | r = -ENOMEM; |
d1ac91d8 | 5690 | if (!u.xsave) |
2d5b5a66 SY |
5691 | break; |
5692 | ||
d1ac91d8 | 5693 | kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5694 | |
5695 | r = -EFAULT; | |
d1ac91d8 | 5696 | if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave))) |
2d5b5a66 SY |
5697 | break; |
5698 | r = 0; | |
5699 | break; | |
5700 | } | |
5701 | case KVM_SET_XSAVE: { | |
be50b206 GZ |
5702 | int size = vcpu->arch.guest_fpu.uabi_size; |
5703 | ||
5704 | u.xsave = memdup_user(argp, size); | |
9b062471 CD |
5705 | if (IS_ERR(u.xsave)) { |
5706 | r = PTR_ERR(u.xsave); | |
5707 | goto out_nofree; | |
5708 | } | |
2d5b5a66 | 5709 | |
d1ac91d8 | 5710 | r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave); |
2d5b5a66 SY |
5711 | break; |
5712 | } | |
be50b206 GZ |
5713 | |
5714 | case KVM_GET_XSAVE2: { | |
5715 | int size = vcpu->arch.guest_fpu.uabi_size; | |
5716 | ||
5717 | u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT); | |
5718 | r = -ENOMEM; | |
5719 | if (!u.xsave) | |
5720 | break; | |
5721 | ||
5722 | kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size); | |
5723 | ||
5724 | r = -EFAULT; | |
5725 | if (copy_to_user(argp, u.xsave, size)) | |
5726 | break; | |
5727 | ||
5728 | r = 0; | |
5729 | break; | |
5730 | } | |
5731 | ||
2d5b5a66 | 5732 | case KVM_GET_XCRS: { |
254272ce | 5733 | u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT); |
2d5b5a66 | 5734 | r = -ENOMEM; |
d1ac91d8 | 5735 | if (!u.xcrs) |
2d5b5a66 SY |
5736 | break; |
5737 | ||
d1ac91d8 | 5738 | kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5739 | |
5740 | r = -EFAULT; | |
d1ac91d8 | 5741 | if (copy_to_user(argp, u.xcrs, |
2d5b5a66 SY |
5742 | sizeof(struct kvm_xcrs))) |
5743 | break; | |
5744 | r = 0; | |
5745 | break; | |
5746 | } | |
5747 | case KVM_SET_XCRS: { | |
ff5c2c03 | 5748 | u.xcrs = memdup_user(argp, sizeof(*u.xcrs)); |
9b062471 CD |
5749 | if (IS_ERR(u.xcrs)) { |
5750 | r = PTR_ERR(u.xcrs); | |
5751 | goto out_nofree; | |
5752 | } | |
2d5b5a66 | 5753 | |
d1ac91d8 | 5754 | r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs); |
2d5b5a66 SY |
5755 | break; |
5756 | } | |
92a1f12d JR |
5757 | case KVM_SET_TSC_KHZ: { |
5758 | u32 user_tsc_khz; | |
5759 | ||
5760 | r = -EINVAL; | |
92a1f12d JR |
5761 | user_tsc_khz = (u32)arg; |
5762 | ||
938c8745 SC |
5763 | if (kvm_caps.has_tsc_control && |
5764 | user_tsc_khz >= kvm_caps.max_guest_tsc_khz) | |
92a1f12d JR |
5765 | goto out; |
5766 | ||
cc578287 ZA |
5767 | if (user_tsc_khz == 0) |
5768 | user_tsc_khz = tsc_khz; | |
5769 | ||
381d585c HZ |
5770 | if (!kvm_set_tsc_khz(vcpu, user_tsc_khz)) |
5771 | r = 0; | |
92a1f12d | 5772 | |
92a1f12d JR |
5773 | goto out; |
5774 | } | |
5775 | case KVM_GET_TSC_KHZ: { | |
cc578287 | 5776 | r = vcpu->arch.virtual_tsc_khz; |
92a1f12d JR |
5777 | goto out; |
5778 | } | |
1c0b28c2 EM |
5779 | case KVM_KVMCLOCK_CTRL: { |
5780 | r = kvm_set_guest_paused(vcpu); | |
5781 | goto out; | |
5782 | } | |
5c919412 AS |
5783 | case KVM_ENABLE_CAP: { |
5784 | struct kvm_enable_cap cap; | |
5785 | ||
5786 | r = -EFAULT; | |
5787 | if (copy_from_user(&cap, argp, sizeof(cap))) | |
5788 | goto out; | |
5789 | r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); | |
5790 | break; | |
5791 | } | |
8fcc4b59 JM |
5792 | case KVM_GET_NESTED_STATE: { |
5793 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5794 | u32 user_data_size; | |
5795 | ||
5796 | r = -EINVAL; | |
33b22172 | 5797 | if (!kvm_x86_ops.nested_ops->get_state) |
8fcc4b59 JM |
5798 | break; |
5799 | ||
5800 | BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size)); | |
26b471c7 | 5801 | r = -EFAULT; |
8fcc4b59 | 5802 | if (get_user(user_data_size, &user_kvm_nested_state->size)) |
26b471c7 | 5803 | break; |
8fcc4b59 | 5804 | |
33b22172 PB |
5805 | r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state, |
5806 | user_data_size); | |
8fcc4b59 | 5807 | if (r < 0) |
26b471c7 | 5808 | break; |
8fcc4b59 JM |
5809 | |
5810 | if (r > user_data_size) { | |
5811 | if (put_user(r, &user_kvm_nested_state->size)) | |
26b471c7 LA |
5812 | r = -EFAULT; |
5813 | else | |
5814 | r = -E2BIG; | |
5815 | break; | |
8fcc4b59 | 5816 | } |
26b471c7 | 5817 | |
8fcc4b59 JM |
5818 | r = 0; |
5819 | break; | |
5820 | } | |
5821 | case KVM_SET_NESTED_STATE: { | |
5822 | struct kvm_nested_state __user *user_kvm_nested_state = argp; | |
5823 | struct kvm_nested_state kvm_state; | |
ad5996d9 | 5824 | int idx; |
8fcc4b59 JM |
5825 | |
5826 | r = -EINVAL; | |
33b22172 | 5827 | if (!kvm_x86_ops.nested_ops->set_state) |
8fcc4b59 JM |
5828 | break; |
5829 | ||
26b471c7 | 5830 | r = -EFAULT; |
8fcc4b59 | 5831 | if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state))) |
26b471c7 | 5832 | break; |
8fcc4b59 | 5833 | |
26b471c7 | 5834 | r = -EINVAL; |
8fcc4b59 | 5835 | if (kvm_state.size < sizeof(kvm_state)) |
26b471c7 | 5836 | break; |
8fcc4b59 JM |
5837 | |
5838 | if (kvm_state.flags & | |
8cab6507 | 5839 | ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE |
cc440cda PB |
5840 | | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING |
5841 | | KVM_STATE_NESTED_GIF_SET)) | |
26b471c7 | 5842 | break; |
8fcc4b59 JM |
5843 | |
5844 | /* nested_run_pending implies guest_mode. */ | |
8cab6507 VK |
5845 | if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING) |
5846 | && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE)) | |
26b471c7 | 5847 | break; |
8fcc4b59 | 5848 | |
ad5996d9 | 5849 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
33b22172 | 5850 | r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state); |
ad5996d9 | 5851 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8fcc4b59 JM |
5852 | break; |
5853 | } | |
c21d54f0 VK |
5854 | case KVM_GET_SUPPORTED_HV_CPUID: |
5855 | r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp); | |
2bc39970 | 5856 | break; |
b59b153d | 5857 | #ifdef CONFIG_KVM_XEN |
3e324615 DW |
5858 | case KVM_XEN_VCPU_GET_ATTR: { |
5859 | struct kvm_xen_vcpu_attr xva; | |
5860 | ||
5861 | r = -EFAULT; | |
5862 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
5863 | goto out; | |
5864 | r = kvm_xen_vcpu_get_attr(vcpu, &xva); | |
5865 | if (!r && copy_to_user(argp, &xva, sizeof(xva))) | |
5866 | r = -EFAULT; | |
5867 | break; | |
5868 | } | |
5869 | case KVM_XEN_VCPU_SET_ATTR: { | |
5870 | struct kvm_xen_vcpu_attr xva; | |
5871 | ||
5872 | r = -EFAULT; | |
5873 | if (copy_from_user(&xva, argp, sizeof(xva))) | |
5874 | goto out; | |
5875 | r = kvm_xen_vcpu_set_attr(vcpu, &xva); | |
5876 | break; | |
5877 | } | |
b59b153d | 5878 | #endif |
6dba9403 ML |
5879 | case KVM_GET_SREGS2: { |
5880 | u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL); | |
5881 | r = -ENOMEM; | |
5882 | if (!u.sregs2) | |
5883 | goto out; | |
5884 | __get_sregs2(vcpu, u.sregs2); | |
5885 | r = -EFAULT; | |
5886 | if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2))) | |
5887 | goto out; | |
5888 | r = 0; | |
5889 | break; | |
5890 | } | |
5891 | case KVM_SET_SREGS2: { | |
5892 | u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2)); | |
5893 | if (IS_ERR(u.sregs2)) { | |
5894 | r = PTR_ERR(u.sregs2); | |
5895 | u.sregs2 = NULL; | |
5896 | goto out; | |
5897 | } | |
5898 | r = __set_sregs2(vcpu, u.sregs2); | |
5899 | break; | |
5900 | } | |
828ca896 OU |
5901 | case KVM_HAS_DEVICE_ATTR: |
5902 | case KVM_GET_DEVICE_ATTR: | |
5903 | case KVM_SET_DEVICE_ATTR: | |
5904 | r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp); | |
5905 | break; | |
313a3dc7 CO |
5906 | default: |
5907 | r = -EINVAL; | |
5908 | } | |
5909 | out: | |
d1ac91d8 | 5910 | kfree(u.buffer); |
9b062471 CD |
5911 | out_nofree: |
5912 | vcpu_put(vcpu); | |
313a3dc7 CO |
5913 | return r; |
5914 | } | |
5915 | ||
1499fa80 | 5916 | vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) |
5b1c1493 CO |
5917 | { |
5918 | return VM_FAULT_SIGBUS; | |
5919 | } | |
5920 | ||
1fe779f8 CO |
5921 | static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr) |
5922 | { | |
5923 | int ret; | |
5924 | ||
5925 | if (addr > (unsigned int)(-3 * PAGE_SIZE)) | |
951179ce | 5926 | return -EINVAL; |
b3646477 | 5927 | ret = static_call(kvm_x86_set_tss_addr)(kvm, addr); |
1fe779f8 CO |
5928 | return ret; |
5929 | } | |
5930 | ||
b927a3ce SY |
5931 | static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm, |
5932 | u64 ident_addr) | |
5933 | { | |
b3646477 | 5934 | return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr); |
b927a3ce SY |
5935 | } |
5936 | ||
1fe779f8 | 5937 | static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm, |
bc8a3d89 | 5938 | unsigned long kvm_nr_mmu_pages) |
1fe779f8 CO |
5939 | { |
5940 | if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES) | |
5941 | return -EINVAL; | |
5942 | ||
79fac95e | 5943 | mutex_lock(&kvm->slots_lock); |
1fe779f8 CO |
5944 | |
5945 | kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages); | |
f05e70ac | 5946 | kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages; |
1fe779f8 | 5947 | |
79fac95e | 5948 | mutex_unlock(&kvm->slots_lock); |
1fe779f8 CO |
5949 | return 0; |
5950 | } | |
5951 | ||
bc8a3d89 | 5952 | static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm) |
1fe779f8 | 5953 | { |
39de71ec | 5954 | return kvm->arch.n_max_mmu_pages; |
1fe779f8 CO |
5955 | } |
5956 | ||
1fe779f8 CO |
5957 | static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) |
5958 | { | |
90bca052 | 5959 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5960 | int r; |
5961 | ||
5962 | r = 0; | |
5963 | switch (chip->chip_id) { | |
5964 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 | 5965 | memcpy(&chip->chip.pic, &pic->pics[0], |
1fe779f8 CO |
5966 | sizeof(struct kvm_pic_state)); |
5967 | break; | |
5968 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 | 5969 | memcpy(&chip->chip.pic, &pic->pics[1], |
1fe779f8 CO |
5970 | sizeof(struct kvm_pic_state)); |
5971 | break; | |
5972 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 5973 | kvm_get_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
5974 | break; |
5975 | default: | |
5976 | r = -EINVAL; | |
5977 | break; | |
5978 | } | |
5979 | return r; | |
5980 | } | |
5981 | ||
5982 | static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip) | |
5983 | { | |
90bca052 | 5984 | struct kvm_pic *pic = kvm->arch.vpic; |
1fe779f8 CO |
5985 | int r; |
5986 | ||
5987 | r = 0; | |
5988 | switch (chip->chip_id) { | |
5989 | case KVM_IRQCHIP_PIC_MASTER: | |
90bca052 DH |
5990 | spin_lock(&pic->lock); |
5991 | memcpy(&pic->pics[0], &chip->chip.pic, | |
1fe779f8 | 5992 | sizeof(struct kvm_pic_state)); |
90bca052 | 5993 | spin_unlock(&pic->lock); |
1fe779f8 CO |
5994 | break; |
5995 | case KVM_IRQCHIP_PIC_SLAVE: | |
90bca052 DH |
5996 | spin_lock(&pic->lock); |
5997 | memcpy(&pic->pics[1], &chip->chip.pic, | |
1fe779f8 | 5998 | sizeof(struct kvm_pic_state)); |
90bca052 | 5999 | spin_unlock(&pic->lock); |
1fe779f8 CO |
6000 | break; |
6001 | case KVM_IRQCHIP_IOAPIC: | |
33392b49 | 6002 | kvm_set_ioapic(kvm, &chip->chip.ioapic); |
1fe779f8 CO |
6003 | break; |
6004 | default: | |
6005 | r = -EINVAL; | |
6006 | break; | |
6007 | } | |
90bca052 | 6008 | kvm_pic_update_irq(pic); |
1fe779f8 CO |
6009 | return r; |
6010 | } | |
6011 | ||
e0f63cb9 SY |
6012 | static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps) |
6013 | { | |
34f3941c RK |
6014 | struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state; |
6015 | ||
6016 | BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels)); | |
6017 | ||
6018 | mutex_lock(&kps->lock); | |
6019 | memcpy(ps, &kps->channels, sizeof(*ps)); | |
6020 | mutex_unlock(&kps->lock); | |
2da29bcc | 6021 | return 0; |
e0f63cb9 SY |
6022 | } |
6023 | ||
6024 | static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps) | |
6025 | { | |
0185604c | 6026 | int i; |
09edea72 RK |
6027 | struct kvm_pit *pit = kvm->arch.vpit; |
6028 | ||
6029 | mutex_lock(&pit->pit_state.lock); | |
34f3941c | 6030 | memcpy(&pit->pit_state.channels, ps, sizeof(*ps)); |
0185604c | 6031 | for (i = 0; i < 3; i++) |
09edea72 RK |
6032 | kvm_pit_load_count(pit, i, ps->channels[i].count, 0); |
6033 | mutex_unlock(&pit->pit_state.lock); | |
2da29bcc | 6034 | return 0; |
e9f42757 BK |
6035 | } |
6036 | ||
6037 | static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
6038 | { | |
e9f42757 BK |
6039 | mutex_lock(&kvm->arch.vpit->pit_state.lock); |
6040 | memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels, | |
6041 | sizeof(ps->channels)); | |
6042 | ps->flags = kvm->arch.vpit->pit_state.flags; | |
6043 | mutex_unlock(&kvm->arch.vpit->pit_state.lock); | |
97e69aa6 | 6044 | memset(&ps->reserved, 0, sizeof(ps->reserved)); |
2da29bcc | 6045 | return 0; |
e9f42757 BK |
6046 | } |
6047 | ||
6048 | static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps) | |
6049 | { | |
2da29bcc | 6050 | int start = 0; |
0185604c | 6051 | int i; |
e9f42757 | 6052 | u32 prev_legacy, cur_legacy; |
09edea72 RK |
6053 | struct kvm_pit *pit = kvm->arch.vpit; |
6054 | ||
6055 | mutex_lock(&pit->pit_state.lock); | |
6056 | prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY; | |
e9f42757 BK |
6057 | cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY; |
6058 | if (!prev_legacy && cur_legacy) | |
6059 | start = 1; | |
09edea72 RK |
6060 | memcpy(&pit->pit_state.channels, &ps->channels, |
6061 | sizeof(pit->pit_state.channels)); | |
6062 | pit->pit_state.flags = ps->flags; | |
0185604c | 6063 | for (i = 0; i < 3; i++) |
09edea72 | 6064 | kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count, |
e5e57e7a | 6065 | start && i == 0); |
09edea72 | 6066 | mutex_unlock(&pit->pit_state.lock); |
2da29bcc | 6067 | return 0; |
e0f63cb9 SY |
6068 | } |
6069 | ||
52d939a0 MT |
6070 | static int kvm_vm_ioctl_reinject(struct kvm *kvm, |
6071 | struct kvm_reinject_control *control) | |
6072 | { | |
71474e2f RK |
6073 | struct kvm_pit *pit = kvm->arch.vpit; |
6074 | ||
71474e2f RK |
6075 | /* pit->pit_state.lock was overloaded to prevent userspace from getting |
6076 | * an inconsistent state after running multiple KVM_REINJECT_CONTROL | |
6077 | * ioctls in parallel. Use a separate lock if that ioctl isn't rare. | |
6078 | */ | |
6079 | mutex_lock(&pit->pit_state.lock); | |
6080 | kvm_pit_set_reinject(pit, control->pit_reinject); | |
6081 | mutex_unlock(&pit->pit_state.lock); | |
b39c90b6 | 6082 | |
52d939a0 MT |
6083 | return 0; |
6084 | } | |
6085 | ||
0dff0846 | 6086 | void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot) |
5bb064dc | 6087 | { |
a018eba5 | 6088 | |
88178fd4 | 6089 | /* |
a018eba5 SC |
6090 | * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called |
6091 | * before reporting dirty_bitmap to userspace. KVM flushes the buffers | |
6092 | * on all VM-Exits, thus we only need to kick running vCPUs to force a | |
6093 | * VM-Exit. | |
88178fd4 | 6094 | */ |
a018eba5 | 6095 | struct kvm_vcpu *vcpu; |
46808a4c | 6096 | unsigned long i; |
a018eba5 SC |
6097 | |
6098 | kvm_for_each_vcpu(i, vcpu, kvm) | |
6099 | kvm_vcpu_kick(vcpu); | |
5bb064dc ZX |
6100 | } |
6101 | ||
aa2fbe6d YZ |
6102 | int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event, |
6103 | bool line_status) | |
23d43cf9 CD |
6104 | { |
6105 | if (!irqchip_in_kernel(kvm)) | |
6106 | return -ENXIO; | |
6107 | ||
6108 | irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID, | |
aa2fbe6d YZ |
6109 | irq_event->irq, irq_event->level, |
6110 | line_status); | |
23d43cf9 CD |
6111 | return 0; |
6112 | } | |
6113 | ||
e5d83c74 PB |
6114 | int kvm_vm_ioctl_enable_cap(struct kvm *kvm, |
6115 | struct kvm_enable_cap *cap) | |
90de4a18 NA |
6116 | { |
6117 | int r; | |
6118 | ||
6119 | if (cap->flags) | |
6120 | return -EINVAL; | |
6121 | ||
6122 | switch (cap->cap) { | |
6d849191 OU |
6123 | case KVM_CAP_DISABLE_QUIRKS2: |
6124 | r = -EINVAL; | |
6125 | if (cap->args[0] & ~KVM_X86_VALID_QUIRKS) | |
6126 | break; | |
6127 | fallthrough; | |
90de4a18 NA |
6128 | case KVM_CAP_DISABLE_QUIRKS: |
6129 | kvm->arch.disabled_quirks = cap->args[0]; | |
6130 | r = 0; | |
6131 | break; | |
49df6397 SR |
6132 | case KVM_CAP_SPLIT_IRQCHIP: { |
6133 | mutex_lock(&kvm->lock); | |
b053b2ae SR |
6134 | r = -EINVAL; |
6135 | if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS) | |
6136 | goto split_irqchip_unlock; | |
49df6397 SR |
6137 | r = -EEXIST; |
6138 | if (irqchip_in_kernel(kvm)) | |
6139 | goto split_irqchip_unlock; | |
557abc40 | 6140 | if (kvm->created_vcpus) |
49df6397 SR |
6141 | goto split_irqchip_unlock; |
6142 | r = kvm_setup_empty_irq_routing(kvm); | |
5c0aea0e | 6143 | if (r) |
49df6397 SR |
6144 | goto split_irqchip_unlock; |
6145 | /* Pairs with irqchip_in_kernel. */ | |
6146 | smp_wmb(); | |
49776faf | 6147 | kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT; |
b053b2ae | 6148 | kvm->arch.nr_reserved_ioapic_pins = cap->args[0]; |
320af55a | 6149 | kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); |
49df6397 SR |
6150 | r = 0; |
6151 | split_irqchip_unlock: | |
6152 | mutex_unlock(&kvm->lock); | |
6153 | break; | |
6154 | } | |
37131313 RK |
6155 | case KVM_CAP_X2APIC_API: |
6156 | r = -EINVAL; | |
6157 | if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS) | |
6158 | break; | |
6159 | ||
6160 | if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS) | |
6161 | kvm->arch.x2apic_format = true; | |
c519265f RK |
6162 | if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK) |
6163 | kvm->arch.x2apic_broadcast_quirk_disabled = true; | |
37131313 RK |
6164 | |
6165 | r = 0; | |
6166 | break; | |
4d5422ce WL |
6167 | case KVM_CAP_X86_DISABLE_EXITS: |
6168 | r = -EINVAL; | |
6169 | if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS) | |
6170 | break; | |
6171 | ||
6172 | if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) && | |
6173 | kvm_can_mwait_in_guest()) | |
6174 | kvm->arch.mwait_in_guest = true; | |
766d3571 | 6175 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT) |
caa057a2 | 6176 | kvm->arch.hlt_in_guest = true; |
b31c114b WL |
6177 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE) |
6178 | kvm->arch.pause_in_guest = true; | |
b5170063 WL |
6179 | if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE) |
6180 | kvm->arch.cstate_in_guest = true; | |
4d5422ce WL |
6181 | r = 0; |
6182 | break; | |
6fbbde9a DS |
6183 | case KVM_CAP_MSR_PLATFORM_INFO: |
6184 | kvm->arch.guest_can_read_msr_platform_info = cap->args[0]; | |
6185 | r = 0; | |
c4f55198 JM |
6186 | break; |
6187 | case KVM_CAP_EXCEPTION_PAYLOAD: | |
6188 | kvm->arch.exception_payload_enabled = cap->args[0]; | |
6189 | r = 0; | |
6fbbde9a | 6190 | break; |
ed235117 CQ |
6191 | case KVM_CAP_X86_TRIPLE_FAULT_EVENT: |
6192 | kvm->arch.triple_fault_event = cap->args[0]; | |
6193 | r = 0; | |
6194 | break; | |
1ae09954 | 6195 | case KVM_CAP_X86_USER_SPACE_MSR: |
cf5029d5 AL |
6196 | r = -EINVAL; |
6197 | if (cap->args[0] & ~(KVM_MSR_EXIT_REASON_INVAL | | |
6198 | KVM_MSR_EXIT_REASON_UNKNOWN | | |
6199 | KVM_MSR_EXIT_REASON_FILTER)) | |
6200 | break; | |
1ae09954 AG |
6201 | kvm->arch.user_space_msr_mask = cap->args[0]; |
6202 | r = 0; | |
6203 | break; | |
fe6b6bc8 CQ |
6204 | case KVM_CAP_X86_BUS_LOCK_EXIT: |
6205 | r = -EINVAL; | |
6206 | if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE) | |
6207 | break; | |
6208 | ||
6209 | if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) && | |
6210 | (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)) | |
6211 | break; | |
6212 | ||
938c8745 | 6213 | if (kvm_caps.has_bus_lock_exit && |
fe6b6bc8 CQ |
6214 | cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT) |
6215 | kvm->arch.bus_lock_detection_enabled = true; | |
6216 | r = 0; | |
6217 | break; | |
fe7e9488 SC |
6218 | #ifdef CONFIG_X86_SGX_KVM |
6219 | case KVM_CAP_SGX_ATTRIBUTE: { | |
6220 | unsigned long allowed_attributes = 0; | |
6221 | ||
6222 | r = sgx_set_attribute(&allowed_attributes, cap->args[0]); | |
6223 | if (r) | |
6224 | break; | |
6225 | ||
6226 | /* KVM only supports the PROVISIONKEY privileged attribute. */ | |
6227 | if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) && | |
6228 | !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY)) | |
6229 | kvm->arch.sgx_provisioning_allowed = true; | |
6230 | else | |
6231 | r = -EINVAL; | |
6232 | break; | |
6233 | } | |
6234 | #endif | |
54526d1f NT |
6235 | case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM: |
6236 | r = -EINVAL; | |
7ad02ef0 SC |
6237 | if (!kvm_x86_ops.vm_copy_enc_context_from) |
6238 | break; | |
6239 | ||
6240 | r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]); | |
6241 | break; | |
b5663931 PG |
6242 | case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM: |
6243 | r = -EINVAL; | |
7ad02ef0 SC |
6244 | if (!kvm_x86_ops.vm_move_enc_context_from) |
6245 | break; | |
6246 | ||
6247 | r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]); | |
6248 | break; | |
0dbb1123 AK |
6249 | case KVM_CAP_EXIT_HYPERCALL: |
6250 | if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) { | |
6251 | r = -EINVAL; | |
6252 | break; | |
6253 | } | |
6254 | kvm->arch.hypercall_exit_enabled = cap->args[0]; | |
6255 | r = 0; | |
6256 | break; | |
19238e75 AL |
6257 | case KVM_CAP_EXIT_ON_EMULATION_FAILURE: |
6258 | r = -EINVAL; | |
6259 | if (cap->args[0] & ~1) | |
6260 | break; | |
6261 | kvm->arch.exit_on_emulation_error = cap->args[0]; | |
6262 | r = 0; | |
6263 | break; | |
ba7bb663 DD |
6264 | case KVM_CAP_PMU_CAPABILITY: |
6265 | r = -EINVAL; | |
6266 | if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK)) | |
6267 | break; | |
6268 | ||
6269 | mutex_lock(&kvm->lock); | |
6270 | if (!kvm->created_vcpus) { | |
6271 | kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE); | |
6272 | r = 0; | |
6273 | } | |
6274 | mutex_unlock(&kvm->lock); | |
6275 | break; | |
35875316 ZG |
6276 | case KVM_CAP_MAX_VCPU_ID: |
6277 | r = -EINVAL; | |
6278 | if (cap->args[0] > KVM_MAX_VCPU_IDS) | |
6279 | break; | |
6280 | ||
6281 | mutex_lock(&kvm->lock); | |
6282 | if (kvm->arch.max_vcpu_ids == cap->args[0]) { | |
6283 | r = 0; | |
6284 | } else if (!kvm->arch.max_vcpu_ids) { | |
6285 | kvm->arch.max_vcpu_ids = cap->args[0]; | |
6286 | r = 0; | |
6287 | } | |
6288 | mutex_unlock(&kvm->lock); | |
6289 | break; | |
2f4073e0 TX |
6290 | case KVM_CAP_X86_NOTIFY_VMEXIT: |
6291 | r = -EINVAL; | |
6292 | if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS) | |
6293 | break; | |
6294 | if (!kvm_caps.has_notify_vmexit) | |
6295 | break; | |
6296 | if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED)) | |
6297 | break; | |
6298 | mutex_lock(&kvm->lock); | |
6299 | if (!kvm->created_vcpus) { | |
6300 | kvm->arch.notify_window = cap->args[0] >> 32; | |
6301 | kvm->arch.notify_vmexit_flags = (u32)cap->args[0]; | |
6302 | r = 0; | |
6303 | } | |
6304 | mutex_unlock(&kvm->lock); | |
6305 | break; | |
084cc29f BG |
6306 | case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES: |
6307 | r = -EINVAL; | |
6308 | ||
6309 | /* | |
6310 | * Since the risk of disabling NX hugepages is a guest crashing | |
6311 | * the system, ensure the userspace process has permission to | |
6312 | * reboot the system. | |
6313 | * | |
6314 | * Note that unlike the reboot() syscall, the process must have | |
6315 | * this capability in the root namespace because exposing | |
6316 | * /dev/kvm into a container does not limit the scope of the | |
6317 | * iTLB multihit bug to that container. In other words, | |
6318 | * this must use capable(), not ns_capable(). | |
6319 | */ | |
6320 | if (!capable(CAP_SYS_BOOT)) { | |
6321 | r = -EPERM; | |
6322 | break; | |
6323 | } | |
6324 | ||
6325 | if (cap->args[0]) | |
6326 | break; | |
6327 | ||
6328 | mutex_lock(&kvm->lock); | |
6329 | if (!kvm->created_vcpus) { | |
6330 | kvm->arch.disable_nx_huge_pages = true; | |
6331 | r = 0; | |
6332 | } | |
6333 | mutex_unlock(&kvm->lock); | |
6334 | break; | |
90de4a18 NA |
6335 | default: |
6336 | r = -EINVAL; | |
6337 | break; | |
6338 | } | |
6339 | return r; | |
6340 | } | |
6341 | ||
b318e8de SC |
6342 | static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow) |
6343 | { | |
6344 | struct kvm_x86_msr_filter *msr_filter; | |
6345 | ||
6346 | msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT); | |
6347 | if (!msr_filter) | |
6348 | return NULL; | |
6349 | ||
6350 | msr_filter->default_allow = default_allow; | |
6351 | return msr_filter; | |
6352 | } | |
6353 | ||
6354 | static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter) | |
1a155254 AG |
6355 | { |
6356 | u32 i; | |
1a155254 | 6357 | |
b318e8de SC |
6358 | if (!msr_filter) |
6359 | return; | |
6360 | ||
6361 | for (i = 0; i < msr_filter->count; i++) | |
6362 | kfree(msr_filter->ranges[i].bitmap); | |
1a155254 | 6363 | |
b318e8de | 6364 | kfree(msr_filter); |
1a155254 AG |
6365 | } |
6366 | ||
b318e8de SC |
6367 | static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, |
6368 | struct kvm_msr_filter_range *user_range) | |
1a155254 | 6369 | { |
1a155254 AG |
6370 | unsigned long *bitmap = NULL; |
6371 | size_t bitmap_size; | |
1a155254 AG |
6372 | |
6373 | if (!user_range->nmsrs) | |
6374 | return 0; | |
6375 | ||
aca35288 SC |
6376 | if (user_range->flags & ~(KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE)) |
6377 | return -EINVAL; | |
6378 | ||
6379 | if (!user_range->flags) | |
6380 | return -EINVAL; | |
6381 | ||
1a155254 AG |
6382 | bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long); |
6383 | if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE) | |
6384 | return -EINVAL; | |
6385 | ||
6386 | bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size); | |
6387 | if (IS_ERR(bitmap)) | |
6388 | return PTR_ERR(bitmap); | |
6389 | ||
aca35288 | 6390 | msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) { |
1a155254 AG |
6391 | .flags = user_range->flags, |
6392 | .base = user_range->base, | |
6393 | .nmsrs = user_range->nmsrs, | |
6394 | .bitmap = bitmap, | |
6395 | }; | |
6396 | ||
b318e8de | 6397 | msr_filter->count++; |
1a155254 | 6398 | return 0; |
1a155254 AG |
6399 | } |
6400 | ||
6401 | static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) | |
6402 | { | |
6403 | struct kvm_msr_filter __user *user_msr_filter = argp; | |
b318e8de | 6404 | struct kvm_x86_msr_filter *new_filter, *old_filter; |
1a155254 AG |
6405 | struct kvm_msr_filter filter; |
6406 | bool default_allow; | |
043248b3 | 6407 | bool empty = true; |
b318e8de | 6408 | int r = 0; |
1a155254 AG |
6409 | u32 i; |
6410 | ||
6411 | if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) | |
6412 | return -EFAULT; | |
6413 | ||
cf5029d5 AL |
6414 | if (filter.flags & ~KVM_MSR_FILTER_DEFAULT_DENY) |
6415 | return -EINVAL; | |
6416 | ||
043248b3 PB |
6417 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) |
6418 | empty &= !filter.ranges[i].nmsrs; | |
1a155254 AG |
6419 | |
6420 | default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); | |
043248b3 PB |
6421 | if (empty && !default_allow) |
6422 | return -EINVAL; | |
6423 | ||
b318e8de SC |
6424 | new_filter = kvm_alloc_msr_filter(default_allow); |
6425 | if (!new_filter) | |
6426 | return -ENOMEM; | |
1a155254 | 6427 | |
1a155254 | 6428 | for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { |
b318e8de SC |
6429 | r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); |
6430 | if (r) { | |
6431 | kvm_free_msr_filter(new_filter); | |
6432 | return r; | |
6433 | } | |
1a155254 AG |
6434 | } |
6435 | ||
b318e8de SC |
6436 | mutex_lock(&kvm->lock); |
6437 | ||
6438 | /* The per-VM filter is protected by kvm->lock... */ | |
6439 | old_filter = srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1); | |
6440 | ||
6441 | rcu_assign_pointer(kvm->arch.msr_filter, new_filter); | |
6442 | synchronize_srcu(&kvm->srcu); | |
6443 | ||
6444 | kvm_free_msr_filter(old_filter); | |
6445 | ||
1a155254 AG |
6446 | kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED); |
6447 | mutex_unlock(&kvm->lock); | |
6448 | ||
b318e8de | 6449 | return 0; |
1a155254 AG |
6450 | } |
6451 | ||
7d62874f SS |
6452 | #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER |
6453 | static int kvm_arch_suspend_notifier(struct kvm *kvm) | |
6454 | { | |
6455 | struct kvm_vcpu *vcpu; | |
46808a4c MZ |
6456 | unsigned long i; |
6457 | int ret = 0; | |
7d62874f SS |
6458 | |
6459 | mutex_lock(&kvm->lock); | |
6460 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
916d3608 | 6461 | if (!vcpu->arch.pv_time.active) |
7d62874f SS |
6462 | continue; |
6463 | ||
6464 | ret = kvm_set_guest_paused(vcpu); | |
6465 | if (ret) { | |
6466 | kvm_err("Failed to pause guest VCPU%d: %d\n", | |
6467 | vcpu->vcpu_id, ret); | |
6468 | break; | |
6469 | } | |
6470 | } | |
6471 | mutex_unlock(&kvm->lock); | |
6472 | ||
6473 | return ret ? NOTIFY_BAD : NOTIFY_DONE; | |
6474 | } | |
6475 | ||
6476 | int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state) | |
6477 | { | |
6478 | switch (state) { | |
6479 | case PM_HIBERNATION_PREPARE: | |
6480 | case PM_SUSPEND_PREPARE: | |
6481 | return kvm_arch_suspend_notifier(kvm); | |
6482 | } | |
6483 | ||
6484 | return NOTIFY_DONE; | |
6485 | } | |
6486 | #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */ | |
6487 | ||
45e6c2fa PB |
6488 | static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp) |
6489 | { | |
869b4421 | 6490 | struct kvm_clock_data data = { 0 }; |
45e6c2fa | 6491 | |
55c0cefb | 6492 | get_kvmclock(kvm, &data); |
45e6c2fa PB |
6493 | if (copy_to_user(argp, &data, sizeof(data))) |
6494 | return -EFAULT; | |
6495 | ||
6496 | return 0; | |
6497 | } | |
6498 | ||
6499 | static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp) | |
6500 | { | |
6501 | struct kvm_arch *ka = &kvm->arch; | |
6502 | struct kvm_clock_data data; | |
c68dc1b5 | 6503 | u64 now_raw_ns; |
45e6c2fa PB |
6504 | |
6505 | if (copy_from_user(&data, argp, sizeof(data))) | |
6506 | return -EFAULT; | |
6507 | ||
c68dc1b5 OU |
6508 | /* |
6509 | * Only KVM_CLOCK_REALTIME is used, but allow passing the | |
6510 | * result of KVM_GET_CLOCK back to KVM_SET_CLOCK. | |
6511 | */ | |
6512 | if (data.flags & ~KVM_CLOCK_VALID_FLAGS) | |
45e6c2fa PB |
6513 | return -EINVAL; |
6514 | ||
42dcbe7d | 6515 | kvm_hv_request_tsc_page_update(kvm); |
45e6c2fa PB |
6516 | kvm_start_pvclock_update(kvm); |
6517 | pvclock_update_vm_gtod_copy(kvm); | |
6518 | ||
6519 | /* | |
6520 | * This pairs with kvm_guest_time_update(): when masterclock is | |
6521 | * in use, we use master_kernel_ns + kvmclock_offset to set | |
6522 | * unsigned 'system_time' so if we use get_kvmclock_ns() (which | |
6523 | * is slightly ahead) here we risk going negative on unsigned | |
6524 | * 'system_time' when 'data.clock' is very small. | |
6525 | */ | |
c68dc1b5 OU |
6526 | if (data.flags & KVM_CLOCK_REALTIME) { |
6527 | u64 now_real_ns = ktime_get_real_ns(); | |
6528 | ||
6529 | /* | |
6530 | * Avoid stepping the kvmclock backwards. | |
6531 | */ | |
6532 | if (now_real_ns > data.realtime) | |
6533 | data.clock += now_real_ns - data.realtime; | |
6534 | } | |
6535 | ||
6536 | if (ka->use_master_clock) | |
6537 | now_raw_ns = ka->master_kernel_ns; | |
45e6c2fa | 6538 | else |
c68dc1b5 OU |
6539 | now_raw_ns = get_kvmclock_base_ns(); |
6540 | ka->kvmclock_offset = data.clock - now_raw_ns; | |
45e6c2fa PB |
6541 | kvm_end_pvclock_update(kvm); |
6542 | return 0; | |
6543 | } | |
6544 | ||
1fe779f8 CO |
6545 | long kvm_arch_vm_ioctl(struct file *filp, |
6546 | unsigned int ioctl, unsigned long arg) | |
6547 | { | |
6548 | struct kvm *kvm = filp->private_data; | |
6549 | void __user *argp = (void __user *)arg; | |
367e1319 | 6550 | int r = -ENOTTY; |
f0d66275 DH |
6551 | /* |
6552 | * This union makes it completely explicit to gcc-3.x | |
6553 | * that these two variables' stack usage should be | |
6554 | * combined, not added together. | |
6555 | */ | |
6556 | union { | |
6557 | struct kvm_pit_state ps; | |
e9f42757 | 6558 | struct kvm_pit_state2 ps2; |
c5ff41ce | 6559 | struct kvm_pit_config pit_config; |
f0d66275 | 6560 | } u; |
1fe779f8 CO |
6561 | |
6562 | switch (ioctl) { | |
6563 | case KVM_SET_TSS_ADDR: | |
6564 | r = kvm_vm_ioctl_set_tss_addr(kvm, arg); | |
1fe779f8 | 6565 | break; |
b927a3ce SY |
6566 | case KVM_SET_IDENTITY_MAP_ADDR: { |
6567 | u64 ident_addr; | |
6568 | ||
1af1ac91 DH |
6569 | mutex_lock(&kvm->lock); |
6570 | r = -EINVAL; | |
6571 | if (kvm->created_vcpus) | |
6572 | goto set_identity_unlock; | |
b927a3ce | 6573 | r = -EFAULT; |
0e96f31e | 6574 | if (copy_from_user(&ident_addr, argp, sizeof(ident_addr))) |
1af1ac91 | 6575 | goto set_identity_unlock; |
b927a3ce | 6576 | r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr); |
1af1ac91 DH |
6577 | set_identity_unlock: |
6578 | mutex_unlock(&kvm->lock); | |
b927a3ce SY |
6579 | break; |
6580 | } | |
1fe779f8 CO |
6581 | case KVM_SET_NR_MMU_PAGES: |
6582 | r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg); | |
1fe779f8 CO |
6583 | break; |
6584 | case KVM_GET_NR_MMU_PAGES: | |
6585 | r = kvm_vm_ioctl_get_nr_mmu_pages(kvm); | |
6586 | break; | |
3ddea128 | 6587 | case KVM_CREATE_IRQCHIP: { |
3ddea128 | 6588 | mutex_lock(&kvm->lock); |
09941366 | 6589 | |
3ddea128 | 6590 | r = -EEXIST; |
35e6eaa3 | 6591 | if (irqchip_in_kernel(kvm)) |
3ddea128 | 6592 | goto create_irqchip_unlock; |
09941366 | 6593 | |
3e515705 | 6594 | r = -EINVAL; |
557abc40 | 6595 | if (kvm->created_vcpus) |
3e515705 | 6596 | goto create_irqchip_unlock; |
09941366 RK |
6597 | |
6598 | r = kvm_pic_init(kvm); | |
6599 | if (r) | |
3ddea128 | 6600 | goto create_irqchip_unlock; |
09941366 RK |
6601 | |
6602 | r = kvm_ioapic_init(kvm); | |
6603 | if (r) { | |
09941366 | 6604 | kvm_pic_destroy(kvm); |
3ddea128 | 6605 | goto create_irqchip_unlock; |
09941366 RK |
6606 | } |
6607 | ||
399ec807 AK |
6608 | r = kvm_setup_default_irq_routing(kvm); |
6609 | if (r) { | |
72bb2fcd | 6610 | kvm_ioapic_destroy(kvm); |
09941366 | 6611 | kvm_pic_destroy(kvm); |
71ba994c | 6612 | goto create_irqchip_unlock; |
399ec807 | 6613 | } |
49776faf | 6614 | /* Write kvm->irq_routing before enabling irqchip_in_kernel. */ |
71ba994c | 6615 | smp_wmb(); |
49776faf | 6616 | kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL; |
320af55a | 6617 | kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT); |
3ddea128 MT |
6618 | create_irqchip_unlock: |
6619 | mutex_unlock(&kvm->lock); | |
1fe779f8 | 6620 | break; |
3ddea128 | 6621 | } |
7837699f | 6622 | case KVM_CREATE_PIT: |
c5ff41ce JK |
6623 | u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY; |
6624 | goto create_pit; | |
6625 | case KVM_CREATE_PIT2: | |
6626 | r = -EFAULT; | |
6627 | if (copy_from_user(&u.pit_config, argp, | |
6628 | sizeof(struct kvm_pit_config))) | |
6629 | goto out; | |
6630 | create_pit: | |
250715a6 | 6631 | mutex_lock(&kvm->lock); |
269e05e4 AK |
6632 | r = -EEXIST; |
6633 | if (kvm->arch.vpit) | |
6634 | goto create_pit_unlock; | |
7837699f | 6635 | r = -ENOMEM; |
c5ff41ce | 6636 | kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags); |
7837699f SY |
6637 | if (kvm->arch.vpit) |
6638 | r = 0; | |
269e05e4 | 6639 | create_pit_unlock: |
250715a6 | 6640 | mutex_unlock(&kvm->lock); |
7837699f | 6641 | break; |
1fe779f8 CO |
6642 | case KVM_GET_IRQCHIP: { |
6643 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 6644 | struct kvm_irqchip *chip; |
1fe779f8 | 6645 | |
ff5c2c03 SL |
6646 | chip = memdup_user(argp, sizeof(*chip)); |
6647 | if (IS_ERR(chip)) { | |
6648 | r = PTR_ERR(chip); | |
1fe779f8 | 6649 | goto out; |
ff5c2c03 SL |
6650 | } |
6651 | ||
1fe779f8 | 6652 | r = -ENXIO; |
826da321 | 6653 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
6654 | goto get_irqchip_out; |
6655 | r = kvm_vm_ioctl_get_irqchip(kvm, chip); | |
1fe779f8 | 6656 | if (r) |
f0d66275 | 6657 | goto get_irqchip_out; |
1fe779f8 | 6658 | r = -EFAULT; |
0e96f31e | 6659 | if (copy_to_user(argp, chip, sizeof(*chip))) |
f0d66275 | 6660 | goto get_irqchip_out; |
1fe779f8 | 6661 | r = 0; |
f0d66275 DH |
6662 | get_irqchip_out: |
6663 | kfree(chip); | |
1fe779f8 CO |
6664 | break; |
6665 | } | |
6666 | case KVM_SET_IRQCHIP: { | |
6667 | /* 0: PIC master, 1: PIC slave, 2: IOAPIC */ | |
ff5c2c03 | 6668 | struct kvm_irqchip *chip; |
1fe779f8 | 6669 | |
ff5c2c03 SL |
6670 | chip = memdup_user(argp, sizeof(*chip)); |
6671 | if (IS_ERR(chip)) { | |
6672 | r = PTR_ERR(chip); | |
1fe779f8 | 6673 | goto out; |
ff5c2c03 SL |
6674 | } |
6675 | ||
1fe779f8 | 6676 | r = -ENXIO; |
826da321 | 6677 | if (!irqchip_kernel(kvm)) |
f0d66275 DH |
6678 | goto set_irqchip_out; |
6679 | r = kvm_vm_ioctl_set_irqchip(kvm, chip); | |
f0d66275 DH |
6680 | set_irqchip_out: |
6681 | kfree(chip); | |
1fe779f8 CO |
6682 | break; |
6683 | } | |
e0f63cb9 | 6684 | case KVM_GET_PIT: { |
e0f63cb9 | 6685 | r = -EFAULT; |
f0d66275 | 6686 | if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
6687 | goto out; |
6688 | r = -ENXIO; | |
6689 | if (!kvm->arch.vpit) | |
6690 | goto out; | |
f0d66275 | 6691 | r = kvm_vm_ioctl_get_pit(kvm, &u.ps); |
e0f63cb9 SY |
6692 | if (r) |
6693 | goto out; | |
6694 | r = -EFAULT; | |
f0d66275 | 6695 | if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state))) |
e0f63cb9 SY |
6696 | goto out; |
6697 | r = 0; | |
6698 | break; | |
6699 | } | |
6700 | case KVM_SET_PIT: { | |
e0f63cb9 | 6701 | r = -EFAULT; |
0e96f31e | 6702 | if (copy_from_user(&u.ps, argp, sizeof(u.ps))) |
e0f63cb9 | 6703 | goto out; |
7289fdb5 | 6704 | mutex_lock(&kvm->lock); |
e0f63cb9 SY |
6705 | r = -ENXIO; |
6706 | if (!kvm->arch.vpit) | |
7289fdb5 | 6707 | goto set_pit_out; |
f0d66275 | 6708 | r = kvm_vm_ioctl_set_pit(kvm, &u.ps); |
7289fdb5 SR |
6709 | set_pit_out: |
6710 | mutex_unlock(&kvm->lock); | |
e0f63cb9 SY |
6711 | break; |
6712 | } | |
e9f42757 BK |
6713 | case KVM_GET_PIT2: { |
6714 | r = -ENXIO; | |
6715 | if (!kvm->arch.vpit) | |
6716 | goto out; | |
6717 | r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2); | |
6718 | if (r) | |
6719 | goto out; | |
6720 | r = -EFAULT; | |
6721 | if (copy_to_user(argp, &u.ps2, sizeof(u.ps2))) | |
6722 | goto out; | |
6723 | r = 0; | |
6724 | break; | |
6725 | } | |
6726 | case KVM_SET_PIT2: { | |
6727 | r = -EFAULT; | |
6728 | if (copy_from_user(&u.ps2, argp, sizeof(u.ps2))) | |
6729 | goto out; | |
7289fdb5 | 6730 | mutex_lock(&kvm->lock); |
e9f42757 BK |
6731 | r = -ENXIO; |
6732 | if (!kvm->arch.vpit) | |
7289fdb5 | 6733 | goto set_pit2_out; |
e9f42757 | 6734 | r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2); |
7289fdb5 SR |
6735 | set_pit2_out: |
6736 | mutex_unlock(&kvm->lock); | |
e9f42757 BK |
6737 | break; |
6738 | } | |
52d939a0 MT |
6739 | case KVM_REINJECT_CONTROL: { |
6740 | struct kvm_reinject_control control; | |
6741 | r = -EFAULT; | |
6742 | if (copy_from_user(&control, argp, sizeof(control))) | |
6743 | goto out; | |
cad23e72 ML |
6744 | r = -ENXIO; |
6745 | if (!kvm->arch.vpit) | |
6746 | goto out; | |
52d939a0 | 6747 | r = kvm_vm_ioctl_reinject(kvm, &control); |
52d939a0 MT |
6748 | break; |
6749 | } | |
d71ba788 PB |
6750 | case KVM_SET_BOOT_CPU_ID: |
6751 | r = 0; | |
6752 | mutex_lock(&kvm->lock); | |
557abc40 | 6753 | if (kvm->created_vcpus) |
d71ba788 PB |
6754 | r = -EBUSY; |
6755 | else | |
6756 | kvm->arch.bsp_vcpu_id = arg; | |
6757 | mutex_unlock(&kvm->lock); | |
6758 | break; | |
b59b153d | 6759 | #ifdef CONFIG_KVM_XEN |
ffde22ac | 6760 | case KVM_XEN_HVM_CONFIG: { |
51776043 | 6761 | struct kvm_xen_hvm_config xhc; |
ffde22ac | 6762 | r = -EFAULT; |
51776043 | 6763 | if (copy_from_user(&xhc, argp, sizeof(xhc))) |
ffde22ac | 6764 | goto out; |
78e9878c | 6765 | r = kvm_xen_hvm_config(kvm, &xhc); |
ffde22ac ES |
6766 | break; |
6767 | } | |
a76b9641 JM |
6768 | case KVM_XEN_HVM_GET_ATTR: { |
6769 | struct kvm_xen_hvm_attr xha; | |
6770 | ||
6771 | r = -EFAULT; | |
6772 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
ffde22ac | 6773 | goto out; |
a76b9641 JM |
6774 | r = kvm_xen_hvm_get_attr(kvm, &xha); |
6775 | if (!r && copy_to_user(argp, &xha, sizeof(xha))) | |
6776 | r = -EFAULT; | |
6777 | break; | |
6778 | } | |
6779 | case KVM_XEN_HVM_SET_ATTR: { | |
6780 | struct kvm_xen_hvm_attr xha; | |
6781 | ||
6782 | r = -EFAULT; | |
6783 | if (copy_from_user(&xha, argp, sizeof(xha))) | |
6784 | goto out; | |
6785 | r = kvm_xen_hvm_set_attr(kvm, &xha); | |
ffde22ac ES |
6786 | break; |
6787 | } | |
35025735 DW |
6788 | case KVM_XEN_HVM_EVTCHN_SEND: { |
6789 | struct kvm_irq_routing_xen_evtchn uxe; | |
6790 | ||
6791 | r = -EFAULT; | |
6792 | if (copy_from_user(&uxe, argp, sizeof(uxe))) | |
6793 | goto out; | |
6794 | r = kvm_xen_hvm_evtchn_send(kvm, &uxe); | |
6795 | break; | |
6796 | } | |
b59b153d | 6797 | #endif |
45e6c2fa PB |
6798 | case KVM_SET_CLOCK: |
6799 | r = kvm_vm_ioctl_set_clock(kvm, argp); | |
afbcf7ab | 6800 | break; |
45e6c2fa PB |
6801 | case KVM_GET_CLOCK: |
6802 | r = kvm_vm_ioctl_get_clock(kvm, argp); | |
afbcf7ab | 6803 | break; |
ffbb61d0 DW |
6804 | case KVM_SET_TSC_KHZ: { |
6805 | u32 user_tsc_khz; | |
6806 | ||
6807 | r = -EINVAL; | |
6808 | user_tsc_khz = (u32)arg; | |
6809 | ||
938c8745 SC |
6810 | if (kvm_caps.has_tsc_control && |
6811 | user_tsc_khz >= kvm_caps.max_guest_tsc_khz) | |
ffbb61d0 DW |
6812 | goto out; |
6813 | ||
6814 | if (user_tsc_khz == 0) | |
6815 | user_tsc_khz = tsc_khz; | |
6816 | ||
6817 | WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz); | |
6818 | r = 0; | |
6819 | ||
6820 | goto out; | |
6821 | } | |
6822 | case KVM_GET_TSC_KHZ: { | |
6823 | r = READ_ONCE(kvm->arch.default_tsc_khz); | |
6824 | goto out; | |
6825 | } | |
5acc5c06 BS |
6826 | case KVM_MEMORY_ENCRYPT_OP: { |
6827 | r = -ENOTTY; | |
03d004cd SC |
6828 | if (!kvm_x86_ops.mem_enc_ioctl) |
6829 | goto out; | |
6830 | ||
6831 | r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp); | |
5acc5c06 BS |
6832 | break; |
6833 | } | |
69eaedee BS |
6834 | case KVM_MEMORY_ENCRYPT_REG_REGION: { |
6835 | struct kvm_enc_region region; | |
6836 | ||
6837 | r = -EFAULT; | |
6838 | if (copy_from_user(®ion, argp, sizeof(region))) | |
6839 | goto out; | |
6840 | ||
6841 | r = -ENOTTY; | |
03d004cd SC |
6842 | if (!kvm_x86_ops.mem_enc_register_region) |
6843 | goto out; | |
6844 | ||
6845 | r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion); | |
69eaedee BS |
6846 | break; |
6847 | } | |
6848 | case KVM_MEMORY_ENCRYPT_UNREG_REGION: { | |
6849 | struct kvm_enc_region region; | |
6850 | ||
6851 | r = -EFAULT; | |
6852 | if (copy_from_user(®ion, argp, sizeof(region))) | |
6853 | goto out; | |
6854 | ||
6855 | r = -ENOTTY; | |
03d004cd SC |
6856 | if (!kvm_x86_ops.mem_enc_unregister_region) |
6857 | goto out; | |
6858 | ||
6859 | r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion); | |
69eaedee BS |
6860 | break; |
6861 | } | |
faeb7833 RK |
6862 | case KVM_HYPERV_EVENTFD: { |
6863 | struct kvm_hyperv_eventfd hvevfd; | |
6864 | ||
6865 | r = -EFAULT; | |
6866 | if (copy_from_user(&hvevfd, argp, sizeof(hvevfd))) | |
6867 | goto out; | |
6868 | r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd); | |
6869 | break; | |
6870 | } | |
66bb8a06 EH |
6871 | case KVM_SET_PMU_EVENT_FILTER: |
6872 | r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); | |
6873 | break; | |
1a155254 AG |
6874 | case KVM_X86_SET_MSR_FILTER: |
6875 | r = kvm_vm_ioctl_set_msr_filter(kvm, argp); | |
6876 | break; | |
1fe779f8 | 6877 | default: |
ad6260da | 6878 | r = -ENOTTY; |
1fe779f8 CO |
6879 | } |
6880 | out: | |
6881 | return r; | |
6882 | } | |
6883 | ||
a16b043c | 6884 | static void kvm_init_msr_list(void) |
043405e1 CO |
6885 | { |
6886 | u32 dummy[2]; | |
7a5ee6ed | 6887 | unsigned i; |
043405e1 | 6888 | |
0144ba0c | 6889 | BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3, |
7a5ee6ed | 6890 | "Please update the fixed PMCs in msrs_to_saved_all[]"); |
24c29b7a | 6891 | |
6cbee2b9 XL |
6892 | num_msrs_to_save = 0; |
6893 | num_emulated_msrs = 0; | |
6894 | num_msr_based_features = 0; | |
6895 | ||
7a5ee6ed CQ |
6896 | for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) { |
6897 | if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0) | |
043405e1 | 6898 | continue; |
93c4adc7 PB |
6899 | |
6900 | /* | |
6901 | * Even MSRs that are valid in the host may not be exposed | |
9dbe6cf9 | 6902 | * to the guests in some cases. |
93c4adc7 | 6903 | */ |
7a5ee6ed | 6904 | switch (msrs_to_save_all[i]) { |
93c4adc7 | 6905 | case MSR_IA32_BNDCFGS: |
503234b3 | 6906 | if (!kvm_mpx_supported()) |
93c4adc7 PB |
6907 | continue; |
6908 | break; | |
9dbe6cf9 | 6909 | case MSR_TSC_AUX: |
36fa06f9 SC |
6910 | if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) && |
6911 | !kvm_cpu_cap_has(X86_FEATURE_RDPID)) | |
9dbe6cf9 PB |
6912 | continue; |
6913 | break; | |
f4cfcd2d ML |
6914 | case MSR_IA32_UMWAIT_CONTROL: |
6915 | if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) | |
6916 | continue; | |
6917 | break; | |
bf8c55d8 CP |
6918 | case MSR_IA32_RTIT_CTL: |
6919 | case MSR_IA32_RTIT_STATUS: | |
7b874c26 | 6920 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) |
bf8c55d8 CP |
6921 | continue; |
6922 | break; | |
6923 | case MSR_IA32_RTIT_CR3_MATCH: | |
7b874c26 | 6924 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
6925 | !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering)) |
6926 | continue; | |
6927 | break; | |
6928 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
6929 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
7b874c26 | 6930 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
bf8c55d8 CP |
6931 | (!intel_pt_validate_hw_cap(PT_CAP_topa_output) && |
6932 | !intel_pt_validate_hw_cap(PT_CAP_single_range_output))) | |
6933 | continue; | |
6934 | break; | |
7cb85fc4 | 6935 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: |
7b874c26 | 6936 | if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) || |
7a5ee6ed | 6937 | msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >= |
bf8c55d8 CP |
6938 | intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2) |
6939 | continue; | |
6940 | break; | |
cf05a67b | 6941 | case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17: |
7a5ee6ed | 6942 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >= |
968635ab | 6943 | min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp)) |
24c29b7a PB |
6944 | continue; |
6945 | break; | |
cf05a67b | 6946 | case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17: |
7a5ee6ed | 6947 | if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= |
968635ab | 6948 | min(INTEL_PMC_MAX_GENERIC, kvm_pmu_cap.num_counters_gp)) |
24c29b7a | 6949 | continue; |
7cb85fc4 | 6950 | break; |
820a6ee9 | 6951 | case MSR_IA32_XFD: |
548e8365 | 6952 | case MSR_IA32_XFD_ERR: |
820a6ee9 JL |
6953 | if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) |
6954 | continue; | |
6955 | break; | |
93c4adc7 PB |
6956 | default: |
6957 | break; | |
6958 | } | |
6959 | ||
7a5ee6ed | 6960 | msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i]; |
043405e1 | 6961 | } |
62ef68bb | 6962 | |
7a5ee6ed | 6963 | for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) { |
b3646477 | 6964 | if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i])) |
bc226f07 | 6965 | continue; |
62ef68bb | 6966 | |
7a5ee6ed | 6967 | emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i]; |
62ef68bb | 6968 | } |
801e459a | 6969 | |
7a5ee6ed | 6970 | for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) { |
801e459a TL |
6971 | struct kvm_msr_entry msr; |
6972 | ||
7a5ee6ed | 6973 | msr.index = msr_based_features_all[i]; |
66421c1e | 6974 | if (kvm_get_msr_feature(&msr)) |
801e459a TL |
6975 | continue; |
6976 | ||
7a5ee6ed | 6977 | msr_based_features[num_msr_based_features++] = msr_based_features_all[i]; |
801e459a | 6978 | } |
043405e1 CO |
6979 | } |
6980 | ||
bda9020e MT |
6981 | static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, |
6982 | const void *v) | |
bbd9b64e | 6983 | { |
70252a10 AK |
6984 | int handled = 0; |
6985 | int n; | |
6986 | ||
6987 | do { | |
6988 | n = min(len, 8); | |
bce87cce | 6989 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
6990 | !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v)) |
6991 | && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 AK |
6992 | break; |
6993 | handled += n; | |
6994 | addr += n; | |
6995 | len -= n; | |
6996 | v += n; | |
6997 | } while (len); | |
bbd9b64e | 6998 | |
70252a10 | 6999 | return handled; |
bbd9b64e CO |
7000 | } |
7001 | ||
bda9020e | 7002 | static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v) |
bbd9b64e | 7003 | { |
70252a10 AK |
7004 | int handled = 0; |
7005 | int n; | |
7006 | ||
7007 | do { | |
7008 | n = min(len, 8); | |
bce87cce | 7009 | if (!(lapic_in_kernel(vcpu) && |
e32edf4f NN |
7010 | !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev, |
7011 | addr, n, v)) | |
7012 | && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v)) | |
70252a10 | 7013 | break; |
e39d200f | 7014 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v); |
70252a10 AK |
7015 | handled += n; |
7016 | addr += n; | |
7017 | len -= n; | |
7018 | v += n; | |
7019 | } while (len); | |
bbd9b64e | 7020 | |
70252a10 | 7021 | return handled; |
bbd9b64e CO |
7022 | } |
7023 | ||
2dafc6c2 GN |
7024 | static void kvm_set_segment(struct kvm_vcpu *vcpu, |
7025 | struct kvm_segment *var, int seg) | |
7026 | { | |
b3646477 | 7027 | static_call(kvm_x86_set_segment)(vcpu, var, seg); |
2dafc6c2 GN |
7028 | } |
7029 | ||
7030 | void kvm_get_segment(struct kvm_vcpu *vcpu, | |
7031 | struct kvm_segment *var, int seg) | |
7032 | { | |
b3646477 | 7033 | static_call(kvm_x86_get_segment)(vcpu, var, seg); |
2dafc6c2 GN |
7034 | } |
7035 | ||
5b22bbe7 | 7036 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access, |
54987b7a | 7037 | struct x86_exception *exception) |
02f59dc9 | 7038 | { |
1f5a21ee | 7039 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
02f59dc9 | 7040 | gpa_t t_gpa; |
02f59dc9 JR |
7041 | |
7042 | BUG_ON(!mmu_is_nested(vcpu)); | |
7043 | ||
7044 | /* NPT walks are always user-walks */ | |
7045 | access |= PFERR_USER_MASK; | |
1f5a21ee | 7046 | t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception); |
02f59dc9 JR |
7047 | |
7048 | return t_gpa; | |
7049 | } | |
7050 | ||
ab9ae313 AK |
7051 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
7052 | struct x86_exception *exception) | |
1871c602 | 7053 | { |
1f5a21ee LJ |
7054 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
7055 | ||
5b22bbe7 | 7056 | u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1f5a21ee | 7057 | return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); |
1871c602 | 7058 | } |
54f958cd | 7059 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read); |
1871c602 | 7060 | |
ab9ae313 AK |
7061 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, |
7062 | struct x86_exception *exception) | |
1871c602 | 7063 | { |
1f5a21ee LJ |
7064 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
7065 | ||
5b22bbe7 | 7066 | u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 7067 | access |= PFERR_FETCH_MASK; |
1f5a21ee | 7068 | return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); |
1871c602 GN |
7069 | } |
7070 | ||
ab9ae313 AK |
7071 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, |
7072 | struct x86_exception *exception) | |
1871c602 | 7073 | { |
1f5a21ee LJ |
7074 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
7075 | ||
5b22bbe7 | 7076 | u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
1871c602 | 7077 | access |= PFERR_WRITE_MASK; |
1f5a21ee | 7078 | return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); |
1871c602 | 7079 | } |
54f958cd | 7080 | EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write); |
1871c602 GN |
7081 | |
7082 | /* uses this to access any guest's mapped memory without checking CPL */ | |
ab9ae313 AK |
7083 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, |
7084 | struct x86_exception *exception) | |
1871c602 | 7085 | { |
1f5a21ee LJ |
7086 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
7087 | ||
7088 | return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception); | |
1871c602 GN |
7089 | } |
7090 | ||
7091 | static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, | |
5b22bbe7 | 7092 | struct kvm_vcpu *vcpu, u64 access, |
bcc55cba | 7093 | struct x86_exception *exception) |
bbd9b64e | 7094 | { |
1f5a21ee | 7095 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
bbd9b64e | 7096 | void *data = val; |
10589a46 | 7097 | int r = X86EMUL_CONTINUE; |
bbd9b64e CO |
7098 | |
7099 | while (bytes) { | |
1f5a21ee | 7100 | gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); |
bbd9b64e | 7101 | unsigned offset = addr & (PAGE_SIZE-1); |
77c2002e | 7102 | unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset); |
bbd9b64e CO |
7103 | int ret; |
7104 | ||
6e1d2a3f | 7105 | if (gpa == INVALID_GPA) |
ab9ae313 | 7106 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa PB |
7107 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data, |
7108 | offset, toread); | |
10589a46 | 7109 | if (ret < 0) { |
c3cd7ffa | 7110 | r = X86EMUL_IO_NEEDED; |
10589a46 MT |
7111 | goto out; |
7112 | } | |
bbd9b64e | 7113 | |
77c2002e IE |
7114 | bytes -= toread; |
7115 | data += toread; | |
7116 | addr += toread; | |
bbd9b64e | 7117 | } |
10589a46 | 7118 | out: |
10589a46 | 7119 | return r; |
bbd9b64e | 7120 | } |
77c2002e | 7121 | |
1871c602 | 7122 | /* used for instruction fetching */ |
0f65dd70 AK |
7123 | static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt, |
7124 | gva_t addr, void *val, unsigned int bytes, | |
bcc55cba | 7125 | struct x86_exception *exception) |
1871c602 | 7126 | { |
0f65dd70 | 7127 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
1f5a21ee | 7128 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
5b22bbe7 | 7129 | u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
44583cba PB |
7130 | unsigned offset; |
7131 | int ret; | |
0f65dd70 | 7132 | |
44583cba | 7133 | /* Inline kvm_read_guest_virt_helper for speed. */ |
1f5a21ee LJ |
7134 | gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK, |
7135 | exception); | |
6e1d2a3f | 7136 | if (unlikely(gpa == INVALID_GPA)) |
44583cba PB |
7137 | return X86EMUL_PROPAGATE_FAULT; |
7138 | ||
7139 | offset = addr & (PAGE_SIZE-1); | |
7140 | if (WARN_ON(offset + bytes > PAGE_SIZE)) | |
7141 | bytes = (unsigned)PAGE_SIZE - offset; | |
54bf36aa PB |
7142 | ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val, |
7143 | offset, bytes); | |
44583cba PB |
7144 | if (unlikely(ret < 0)) |
7145 | return X86EMUL_IO_NEEDED; | |
7146 | ||
7147 | return X86EMUL_CONTINUE; | |
1871c602 GN |
7148 | } |
7149 | ||
ce14e868 | 7150 | int kvm_read_guest_virt(struct kvm_vcpu *vcpu, |
0f65dd70 | 7151 | gva_t addr, void *val, unsigned int bytes, |
bcc55cba | 7152 | struct x86_exception *exception) |
1871c602 | 7153 | { |
5b22bbe7 | 7154 | u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0; |
0f65dd70 | 7155 | |
353c0956 PB |
7156 | /* |
7157 | * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED | |
7158 | * is returned, but our callers are not ready for that and they blindly | |
7159 | * call kvm_inject_page_fault. Ensure that they at least do not leak | |
7160 | * uninitialized kernel stack memory into cr2 and error code. | |
7161 | */ | |
7162 | memset(exception, 0, sizeof(*exception)); | |
1871c602 | 7163 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, |
bcc55cba | 7164 | exception); |
1871c602 | 7165 | } |
064aea77 | 7166 | EXPORT_SYMBOL_GPL(kvm_read_guest_virt); |
1871c602 | 7167 | |
ce14e868 PB |
7168 | static int emulator_read_std(struct x86_emulate_ctxt *ctxt, |
7169 | gva_t addr, void *val, unsigned int bytes, | |
3c9fa24c | 7170 | struct x86_exception *exception, bool system) |
1871c602 | 7171 | { |
0f65dd70 | 7172 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
5b22bbe7 | 7173 | u64 access = 0; |
3c9fa24c | 7174 | |
4f4aa80e LJ |
7175 | if (system) |
7176 | access |= PFERR_IMPLICIT_ACCESS; | |
7177 | else if (static_call(kvm_x86_get_cpl)(vcpu) == 3) | |
3c9fa24c PB |
7178 | access |= PFERR_USER_MASK; |
7179 | ||
7180 | return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception); | |
1871c602 GN |
7181 | } |
7182 | ||
7a036a6f RK |
7183 | static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt, |
7184 | unsigned long addr, void *val, unsigned int bytes) | |
7185 | { | |
7186 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
7187 | int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes); | |
7188 | ||
7189 | return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE; | |
7190 | } | |
7191 | ||
ce14e868 | 7192 | static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes, |
5b22bbe7 | 7193 | struct kvm_vcpu *vcpu, u64 access, |
ce14e868 | 7194 | struct x86_exception *exception) |
77c2002e | 7195 | { |
1f5a21ee | 7196 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
77c2002e IE |
7197 | void *data = val; |
7198 | int r = X86EMUL_CONTINUE; | |
7199 | ||
7200 | while (bytes) { | |
1f5a21ee | 7201 | gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception); |
77c2002e IE |
7202 | unsigned offset = addr & (PAGE_SIZE-1); |
7203 | unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset); | |
7204 | int ret; | |
7205 | ||
6e1d2a3f | 7206 | if (gpa == INVALID_GPA) |
ab9ae313 | 7207 | return X86EMUL_PROPAGATE_FAULT; |
54bf36aa | 7208 | ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite); |
77c2002e | 7209 | if (ret < 0) { |
c3cd7ffa | 7210 | r = X86EMUL_IO_NEEDED; |
77c2002e IE |
7211 | goto out; |
7212 | } | |
7213 | ||
7214 | bytes -= towrite; | |
7215 | data += towrite; | |
7216 | addr += towrite; | |
7217 | } | |
7218 | out: | |
7219 | return r; | |
7220 | } | |
ce14e868 PB |
7221 | |
7222 | static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val, | |
3c9fa24c PB |
7223 | unsigned int bytes, struct x86_exception *exception, |
7224 | bool system) | |
ce14e868 PB |
7225 | { |
7226 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
5b22bbe7 | 7227 | u64 access = PFERR_WRITE_MASK; |
3c9fa24c | 7228 | |
4f4aa80e LJ |
7229 | if (system) |
7230 | access |= PFERR_IMPLICIT_ACCESS; | |
7231 | else if (static_call(kvm_x86_get_cpl)(vcpu) == 3) | |
3c9fa24c | 7232 | access |= PFERR_USER_MASK; |
ce14e868 PB |
7233 | |
7234 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, | |
3c9fa24c | 7235 | access, exception); |
ce14e868 PB |
7236 | } |
7237 | ||
7238 | int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val, | |
7239 | unsigned int bytes, struct x86_exception *exception) | |
7240 | { | |
c595ceee PB |
7241 | /* kvm_write_guest_virt_system can pull in tons of pages. */ |
7242 | vcpu->arch.l1tf_flush_l1d = true; | |
7243 | ||
ce14e868 PB |
7244 | return kvm_write_guest_virt_helper(addr, val, bytes, vcpu, |
7245 | PFERR_WRITE_MASK, exception); | |
7246 | } | |
6a4d7550 | 7247 | EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system); |
77c2002e | 7248 | |
4d31d9ef SC |
7249 | static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type, |
7250 | void *insn, int insn_len) | |
7251 | { | |
7252 | return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type, | |
7253 | insn, insn_len); | |
7254 | } | |
7255 | ||
082d06ed WL |
7256 | int handle_ud(struct kvm_vcpu *vcpu) |
7257 | { | |
b3dc0695 | 7258 | static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX }; |
6c86eedc | 7259 | int emul_type = EMULTYPE_TRAP_UD; |
6c86eedc WL |
7260 | char sig[5]; /* ud2; .ascii "kvm" */ |
7261 | struct x86_exception e; | |
7262 | ||
4d31d9ef | 7263 | if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0))) |
09e3e2a1 SC |
7264 | return 1; |
7265 | ||
6c86eedc | 7266 | if (force_emulation_prefix && |
3c9fa24c PB |
7267 | kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu), |
7268 | sig, sizeof(sig), &e) == 0 && | |
b3dc0695 | 7269 | memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) { |
d500e1ed SC |
7270 | if (force_emulation_prefix & KVM_FEP_CLEAR_RFLAGS_RF) |
7271 | kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) & ~X86_EFLAGS_RF); | |
6c86eedc | 7272 | kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig)); |
b4000606 | 7273 | emul_type = EMULTYPE_TRAP_UD_FORCED; |
6c86eedc | 7274 | } |
082d06ed | 7275 | |
60fc3d02 | 7276 | return kvm_emulate_instruction(vcpu, emul_type); |
082d06ed WL |
7277 | } |
7278 | EXPORT_SYMBOL_GPL(handle_ud); | |
7279 | ||
0f89b207 TL |
7280 | static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
7281 | gpa_t gpa, bool write) | |
7282 | { | |
7283 | /* For APIC access vmexit */ | |
7284 | if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) | |
7285 | return 1; | |
7286 | ||
7287 | if (vcpu_match_mmio_gpa(vcpu, gpa)) { | |
7288 | trace_vcpu_match_mmio(gva, gpa, write, true); | |
7289 | return 1; | |
7290 | } | |
7291 | ||
7292 | return 0; | |
7293 | } | |
7294 | ||
af7cc7d1 XG |
7295 | static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva, |
7296 | gpa_t *gpa, struct x86_exception *exception, | |
7297 | bool write) | |
7298 | { | |
1f5a21ee | 7299 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
5b22bbe7 | 7300 | u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0) |
97d64b78 | 7301 | | (write ? PFERR_WRITE_MASK : 0); |
af7cc7d1 | 7302 | |
be94f6b7 HH |
7303 | /* |
7304 | * currently PKRU is only applied to ept enabled guest so | |
7305 | * there is no pkey in EPT page table for L1 guest or EPT | |
7306 | * shadow page table for L2 guest. | |
7307 | */ | |
908b7d43 SC |
7308 | if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) || |
7309 | !permission_fault(vcpu, vcpu->arch.walk_mmu, | |
7310 | vcpu->arch.mmio_access, 0, access))) { | |
bebb106a XG |
7311 | *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT | |
7312 | (gva & (PAGE_SIZE - 1)); | |
4f022648 | 7313 | trace_vcpu_match_mmio(gva, *gpa, write, false); |
bebb106a XG |
7314 | return 1; |
7315 | } | |
7316 | ||
1f5a21ee | 7317 | *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception); |
af7cc7d1 | 7318 | |
6e1d2a3f | 7319 | if (*gpa == INVALID_GPA) |
af7cc7d1 XG |
7320 | return -1; |
7321 | ||
0f89b207 | 7322 | return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write); |
af7cc7d1 XG |
7323 | } |
7324 | ||
3200f405 | 7325 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
bcc55cba | 7326 | const void *val, int bytes) |
bbd9b64e CO |
7327 | { |
7328 | int ret; | |
7329 | ||
54bf36aa | 7330 | ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes); |
9f811285 | 7331 | if (ret < 0) |
bbd9b64e | 7332 | return 0; |
0eb05bf2 | 7333 | kvm_page_track_write(vcpu, gpa, val, bytes); |
bbd9b64e CO |
7334 | return 1; |
7335 | } | |
7336 | ||
77d197b2 XG |
7337 | struct read_write_emulator_ops { |
7338 | int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val, | |
7339 | int bytes); | |
7340 | int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7341 | void *val, int bytes); | |
7342 | int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7343 | int bytes, void *val); | |
7344 | int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7345 | void *val, int bytes); | |
7346 | bool write; | |
7347 | }; | |
7348 | ||
7349 | static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes) | |
7350 | { | |
7351 | if (vcpu->mmio_read_completed) { | |
77d197b2 | 7352 | trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, |
e39d200f | 7353 | vcpu->mmio_fragments[0].gpa, val); |
77d197b2 XG |
7354 | vcpu->mmio_read_completed = 0; |
7355 | return 1; | |
7356 | } | |
7357 | ||
7358 | return 0; | |
7359 | } | |
7360 | ||
7361 | static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7362 | void *val, int bytes) | |
7363 | { | |
54bf36aa | 7364 | return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes); |
77d197b2 XG |
7365 | } |
7366 | ||
7367 | static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7368 | void *val, int bytes) | |
7369 | { | |
7370 | return emulator_write_phys(vcpu, gpa, val, bytes); | |
7371 | } | |
7372 | ||
7373 | static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val) | |
7374 | { | |
e39d200f | 7375 | trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val); |
77d197b2 XG |
7376 | return vcpu_mmio_write(vcpu, gpa, bytes, val); |
7377 | } | |
7378 | ||
7379 | static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7380 | void *val, int bytes) | |
7381 | { | |
e39d200f | 7382 | trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL); |
77d197b2 XG |
7383 | return X86EMUL_IO_NEEDED; |
7384 | } | |
7385 | ||
7386 | static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, | |
7387 | void *val, int bytes) | |
7388 | { | |
f78146b0 AK |
7389 | struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0]; |
7390 | ||
87da7e66 | 7391 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); |
77d197b2 XG |
7392 | return X86EMUL_CONTINUE; |
7393 | } | |
7394 | ||
0fbe9b0b | 7395 | static const struct read_write_emulator_ops read_emultor = { |
77d197b2 XG |
7396 | .read_write_prepare = read_prepare, |
7397 | .read_write_emulate = read_emulate, | |
7398 | .read_write_mmio = vcpu_mmio_read, | |
7399 | .read_write_exit_mmio = read_exit_mmio, | |
7400 | }; | |
7401 | ||
0fbe9b0b | 7402 | static const struct read_write_emulator_ops write_emultor = { |
77d197b2 XG |
7403 | .read_write_emulate = write_emulate, |
7404 | .read_write_mmio = write_mmio, | |
7405 | .read_write_exit_mmio = write_exit_mmio, | |
7406 | .write = true, | |
7407 | }; | |
7408 | ||
22388a3c XG |
7409 | static int emulator_read_write_onepage(unsigned long addr, void *val, |
7410 | unsigned int bytes, | |
7411 | struct x86_exception *exception, | |
7412 | struct kvm_vcpu *vcpu, | |
0fbe9b0b | 7413 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 7414 | { |
af7cc7d1 XG |
7415 | gpa_t gpa; |
7416 | int handled, ret; | |
22388a3c | 7417 | bool write = ops->write; |
f78146b0 | 7418 | struct kvm_mmio_fragment *frag; |
c9b8b07c | 7419 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
0f89b207 TL |
7420 | |
7421 | /* | |
7422 | * If the exit was due to a NPF we may already have a GPA. | |
7423 | * If the GPA is present, use it to avoid the GVA to GPA table walk. | |
7424 | * Note, this cannot be used on string operations since string | |
7425 | * operation using rep will only have the initial GPA from the NPF | |
7426 | * occurred. | |
7427 | */ | |
744e699c SC |
7428 | if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) && |
7429 | (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) { | |
7430 | gpa = ctxt->gpa_val; | |
618232e2 BS |
7431 | ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write); |
7432 | } else { | |
7433 | ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write); | |
7434 | if (ret < 0) | |
7435 | return X86EMUL_PROPAGATE_FAULT; | |
0f89b207 | 7436 | } |
10589a46 | 7437 | |
618232e2 | 7438 | if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes)) |
bbd9b64e CO |
7439 | return X86EMUL_CONTINUE; |
7440 | ||
bbd9b64e CO |
7441 | /* |
7442 | * Is this MMIO handled locally? | |
7443 | */ | |
22388a3c | 7444 | handled = ops->read_write_mmio(vcpu, gpa, bytes, val); |
70252a10 | 7445 | if (handled == bytes) |
bbd9b64e | 7446 | return X86EMUL_CONTINUE; |
bbd9b64e | 7447 | |
70252a10 AK |
7448 | gpa += handled; |
7449 | bytes -= handled; | |
7450 | val += handled; | |
7451 | ||
87da7e66 XG |
7452 | WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS); |
7453 | frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++]; | |
7454 | frag->gpa = gpa; | |
7455 | frag->data = val; | |
7456 | frag->len = bytes; | |
f78146b0 | 7457 | return X86EMUL_CONTINUE; |
bbd9b64e CO |
7458 | } |
7459 | ||
52eb5a6d XL |
7460 | static int emulator_read_write(struct x86_emulate_ctxt *ctxt, |
7461 | unsigned long addr, | |
22388a3c XG |
7462 | void *val, unsigned int bytes, |
7463 | struct x86_exception *exception, | |
0fbe9b0b | 7464 | const struct read_write_emulator_ops *ops) |
bbd9b64e | 7465 | { |
0f65dd70 | 7466 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
f78146b0 AK |
7467 | gpa_t gpa; |
7468 | int rc; | |
7469 | ||
7470 | if (ops->read_write_prepare && | |
7471 | ops->read_write_prepare(vcpu, val, bytes)) | |
7472 | return X86EMUL_CONTINUE; | |
7473 | ||
7474 | vcpu->mmio_nr_fragments = 0; | |
0f65dd70 | 7475 | |
bbd9b64e CO |
7476 | /* Crossing a page boundary? */ |
7477 | if (((addr + bytes - 1) ^ addr) & PAGE_MASK) { | |
f78146b0 | 7478 | int now; |
bbd9b64e CO |
7479 | |
7480 | now = -addr & ~PAGE_MASK; | |
22388a3c XG |
7481 | rc = emulator_read_write_onepage(addr, val, now, exception, |
7482 | vcpu, ops); | |
7483 | ||
bbd9b64e CO |
7484 | if (rc != X86EMUL_CONTINUE) |
7485 | return rc; | |
7486 | addr += now; | |
bac15531 NA |
7487 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
7488 | addr = (u32)addr; | |
bbd9b64e CO |
7489 | val += now; |
7490 | bytes -= now; | |
7491 | } | |
22388a3c | 7492 | |
f78146b0 AK |
7493 | rc = emulator_read_write_onepage(addr, val, bytes, exception, |
7494 | vcpu, ops); | |
7495 | if (rc != X86EMUL_CONTINUE) | |
7496 | return rc; | |
7497 | ||
7498 | if (!vcpu->mmio_nr_fragments) | |
7499 | return rc; | |
7500 | ||
7501 | gpa = vcpu->mmio_fragments[0].gpa; | |
7502 | ||
7503 | vcpu->mmio_needed = 1; | |
7504 | vcpu->mmio_cur_fragment = 0; | |
7505 | ||
87da7e66 | 7506 | vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len); |
f78146b0 AK |
7507 | vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write; |
7508 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
7509 | vcpu->run->mmio.phys_addr = gpa; | |
7510 | ||
7511 | return ops->read_write_exit_mmio(vcpu, gpa, val, bytes); | |
22388a3c XG |
7512 | } |
7513 | ||
7514 | static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt, | |
7515 | unsigned long addr, | |
7516 | void *val, | |
7517 | unsigned int bytes, | |
7518 | struct x86_exception *exception) | |
7519 | { | |
7520 | return emulator_read_write(ctxt, addr, val, bytes, | |
7521 | exception, &read_emultor); | |
7522 | } | |
7523 | ||
52eb5a6d | 7524 | static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt, |
22388a3c XG |
7525 | unsigned long addr, |
7526 | const void *val, | |
7527 | unsigned int bytes, | |
7528 | struct x86_exception *exception) | |
7529 | { | |
7530 | return emulator_read_write(ctxt, addr, (void *)val, bytes, | |
7531 | exception, &write_emultor); | |
bbd9b64e | 7532 | } |
bbd9b64e | 7533 | |
1c2361f6 SC |
7534 | #define emulator_try_cmpxchg_user(t, ptr, old, new) \ |
7535 | (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t)) | |
daea3e73 | 7536 | |
0f65dd70 AK |
7537 | static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, |
7538 | unsigned long addr, | |
bbd9b64e CO |
7539 | const void *old, |
7540 | const void *new, | |
7541 | unsigned int bytes, | |
0f65dd70 | 7542 | struct x86_exception *exception) |
bbd9b64e | 7543 | { |
0f65dd70 | 7544 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
9de6fe3c | 7545 | u64 page_line_mask; |
1c2361f6 | 7546 | unsigned long hva; |
daea3e73 | 7547 | gpa_t gpa; |
1c2361f6 | 7548 | int r; |
2bacc55c | 7549 | |
daea3e73 AK |
7550 | /* guests cmpxchg8b have to be emulated atomically */ |
7551 | if (bytes > 8 || (bytes & (bytes - 1))) | |
7552 | goto emul_write; | |
10589a46 | 7553 | |
daea3e73 | 7554 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL); |
2bacc55c | 7555 | |
6e1d2a3f | 7556 | if (gpa == INVALID_GPA || |
daea3e73 AK |
7557 | (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE) |
7558 | goto emul_write; | |
2bacc55c | 7559 | |
9de6fe3c XL |
7560 | /* |
7561 | * Emulate the atomic as a straight write to avoid #AC if SLD is | |
7562 | * enabled in the host and the access splits a cache line. | |
7563 | */ | |
7564 | if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) | |
7565 | page_line_mask = ~(cache_line_size() - 1); | |
7566 | else | |
7567 | page_line_mask = PAGE_MASK; | |
7568 | ||
7569 | if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask)) | |
daea3e73 | 7570 | goto emul_write; |
72dc67a6 | 7571 | |
1c2361f6 | 7572 | hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa)); |
33fbe6be | 7573 | if (kvm_is_error_hva(hva)) |
c19b8bd6 | 7574 | goto emul_write; |
72dc67a6 | 7575 | |
1c2361f6 | 7576 | hva += offset_in_page(gpa); |
42e35f80 | 7577 | |
daea3e73 AK |
7578 | switch (bytes) { |
7579 | case 1: | |
1c2361f6 | 7580 | r = emulator_try_cmpxchg_user(u8, hva, old, new); |
daea3e73 AK |
7581 | break; |
7582 | case 2: | |
1c2361f6 | 7583 | r = emulator_try_cmpxchg_user(u16, hva, old, new); |
daea3e73 AK |
7584 | break; |
7585 | case 4: | |
1c2361f6 | 7586 | r = emulator_try_cmpxchg_user(u32, hva, old, new); |
daea3e73 AK |
7587 | break; |
7588 | case 8: | |
1c2361f6 | 7589 | r = emulator_try_cmpxchg_user(u64, hva, old, new); |
daea3e73 AK |
7590 | break; |
7591 | default: | |
7592 | BUG(); | |
2bacc55c | 7593 | } |
42e35f80 | 7594 | |
1c2361f6 | 7595 | if (r < 0) |
5d6c7de6 | 7596 | return X86EMUL_UNHANDLEABLE; |
1c2361f6 | 7597 | if (r) |
daea3e73 AK |
7598 | return X86EMUL_CMPXCHG_FAILED; |
7599 | ||
0eb05bf2 | 7600 | kvm_page_track_write(vcpu, gpa, new, bytes); |
8f6abd06 GN |
7601 | |
7602 | return X86EMUL_CONTINUE; | |
4a5f48f6 | 7603 | |
3200f405 | 7604 | emul_write: |
daea3e73 | 7605 | printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); |
2bacc55c | 7606 | |
0f65dd70 | 7607 | return emulator_write_emulated(ctxt, addr, new, bytes, exception); |
bbd9b64e CO |
7608 | } |
7609 | ||
6f6fbe98 | 7610 | static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size, |
30d583fd | 7611 | unsigned short port, void *data, |
6f6fbe98 | 7612 | unsigned int count, bool in) |
cf8f70bf | 7613 | { |
0f87ac23 PB |
7614 | unsigned i; |
7615 | int r; | |
cf8f70bf | 7616 | |
30d583fd | 7617 | WARN_ON_ONCE(vcpu->arch.pio.count); |
0f87ac23 PB |
7618 | for (i = 0; i < count; i++) { |
7619 | if (in) | |
7620 | r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data); | |
cbfc6c91 | 7621 | else |
0f87ac23 | 7622 | r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data); |
35ab3b77 PB |
7623 | |
7624 | if (r) { | |
7625 | if (i == 0) | |
7626 | goto userspace_io; | |
7627 | ||
7628 | /* | |
7629 | * Userspace must have unregistered the device while PIO | |
0c05e10b | 7630 | * was running. Drop writes / read as 0. |
35ab3b77 | 7631 | */ |
0c05e10b PB |
7632 | if (in) |
7633 | memset(data, 0, size * (count - i)); | |
cbfc6c91 | 7634 | break; |
35ab3b77 PB |
7635 | } |
7636 | ||
0f87ac23 | 7637 | data += size; |
cbfc6c91 | 7638 | } |
0f87ac23 | 7639 | return 1; |
cf8f70bf | 7640 | |
0f87ac23 | 7641 | userspace_io: |
cf8f70bf | 7642 | vcpu->arch.pio.port = port; |
6f6fbe98 | 7643 | vcpu->arch.pio.in = in; |
0c05e10b | 7644 | vcpu->arch.pio.count = count; |
cf8f70bf GN |
7645 | vcpu->arch.pio.size = size; |
7646 | ||
0c05e10b PB |
7647 | if (in) |
7648 | memset(vcpu->arch.pio_data, 0, size * count); | |
7649 | else | |
7650 | memcpy(vcpu->arch.pio_data, data, size * count); | |
cf8f70bf GN |
7651 | |
7652 | vcpu->run->exit_reason = KVM_EXIT_IO; | |
6f6fbe98 | 7653 | vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT; |
cf8f70bf GN |
7654 | vcpu->run->io.size = size; |
7655 | vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE; | |
7656 | vcpu->run->io.count = count; | |
7657 | vcpu->run->io.port = port; | |
cf8f70bf GN |
7658 | return 0; |
7659 | } | |
7660 | ||
f35cee4a PB |
7661 | static int emulator_pio_in(struct kvm_vcpu *vcpu, int size, |
7662 | unsigned short port, void *val, unsigned int count) | |
cf8f70bf | 7663 | { |
0c05e10b PB |
7664 | int r = emulator_pio_in_out(vcpu, size, port, val, count, true); |
7665 | if (r) | |
7666 | trace_kvm_pio(KVM_PIO_IN, port, size, count, val); | |
7667 | ||
7668 | return r; | |
3b27de27 | 7669 | } |
ca1d4a9e | 7670 | |
6b5efc93 | 7671 | static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val) |
3b27de27 | 7672 | { |
6b5efc93 | 7673 | int size = vcpu->arch.pio.size; |
0c05e10b | 7674 | unsigned int count = vcpu->arch.pio.count; |
6b5efc93 PB |
7675 | memcpy(val, vcpu->arch.pio_data, size * count); |
7676 | trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data); | |
3b27de27 PB |
7677 | vcpu->arch.pio.count = 0; |
7678 | } | |
cf8f70bf | 7679 | |
f35cee4a PB |
7680 | static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt, |
7681 | int size, unsigned short port, void *val, | |
7682 | unsigned int count) | |
3b27de27 | 7683 | { |
f35cee4a | 7684 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
3b27de27 | 7685 | if (vcpu->arch.pio.count) { |
d07898ea SC |
7686 | /* |
7687 | * Complete a previous iteration that required userspace I/O. | |
7688 | * Note, @count isn't guaranteed to match pio.count as userspace | |
7689 | * can modify ECX before rerunning the vCPU. Ignore any such | |
7690 | * shenanigans as KVM doesn't support modifying the rep count, | |
7691 | * and the emulator ensures @count doesn't overflow the buffer. | |
7692 | */ | |
0c05e10b PB |
7693 | complete_emulator_pio_in(vcpu, val); |
7694 | return 1; | |
cf8f70bf GN |
7695 | } |
7696 | ||
f35cee4a | 7697 | return emulator_pio_in(vcpu, size, port, val, count); |
2e3bb4d8 | 7698 | } |
6f6fbe98 | 7699 | |
2e3bb4d8 SC |
7700 | static int emulator_pio_out(struct kvm_vcpu *vcpu, int size, |
7701 | unsigned short port, const void *val, | |
7702 | unsigned int count) | |
7703 | { | |
30d583fd | 7704 | trace_kvm_pio(KVM_PIO_OUT, port, size, count, val); |
0c05e10b | 7705 | return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false); |
6f6fbe98 XG |
7706 | } |
7707 | ||
2e3bb4d8 SC |
7708 | static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt, |
7709 | int size, unsigned short port, | |
7710 | const void *val, unsigned int count) | |
7711 | { | |
7712 | return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count); | |
7713 | } | |
7714 | ||
bbd9b64e CO |
7715 | static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg) |
7716 | { | |
b3646477 | 7717 | return static_call(kvm_x86_get_segment_base)(vcpu, seg); |
bbd9b64e CO |
7718 | } |
7719 | ||
3cb16fe7 | 7720 | static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address) |
bbd9b64e | 7721 | { |
3cb16fe7 | 7722 | kvm_mmu_invlpg(emul_to_vcpu(ctxt), address); |
bbd9b64e CO |
7723 | } |
7724 | ||
ae6a2375 | 7725 | static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu) |
f5f48ee1 SY |
7726 | { |
7727 | if (!need_emulate_wbinvd(vcpu)) | |
7728 | return X86EMUL_CONTINUE; | |
7729 | ||
b3646477 | 7730 | if (static_call(kvm_x86_has_wbinvd_exit)()) { |
2eec7343 JK |
7731 | int cpu = get_cpu(); |
7732 | ||
7733 | cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask); | |
c2162e13 | 7734 | on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask, |
f5f48ee1 | 7735 | wbinvd_ipi, NULL, 1); |
2eec7343 | 7736 | put_cpu(); |
f5f48ee1 | 7737 | cpumask_clear(vcpu->arch.wbinvd_dirty_mask); |
2eec7343 JK |
7738 | } else |
7739 | wbinvd(); | |
f5f48ee1 SY |
7740 | return X86EMUL_CONTINUE; |
7741 | } | |
5cb56059 JS |
7742 | |
7743 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu) | |
7744 | { | |
6affcbed KH |
7745 | kvm_emulate_wbinvd_noskip(vcpu); |
7746 | return kvm_skip_emulated_instruction(vcpu); | |
5cb56059 | 7747 | } |
f5f48ee1 SY |
7748 | EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd); |
7749 | ||
5cb56059 JS |
7750 | |
7751 | ||
bcaf5cc5 AK |
7752 | static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt) |
7753 | { | |
5cb56059 | 7754 | kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt)); |
bcaf5cc5 AK |
7755 | } |
7756 | ||
29d6ca41 PB |
7757 | static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, |
7758 | unsigned long *dest) | |
bbd9b64e | 7759 | { |
29d6ca41 | 7760 | kvm_get_dr(emul_to_vcpu(ctxt), dr, dest); |
bbd9b64e CO |
7761 | } |
7762 | ||
52eb5a6d XL |
7763 | static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, |
7764 | unsigned long value) | |
bbd9b64e | 7765 | { |
338dbc97 | 7766 | |
996ff542 | 7767 | return kvm_set_dr(emul_to_vcpu(ctxt), dr, value); |
bbd9b64e CO |
7768 | } |
7769 | ||
52a46617 | 7770 | static u64 mk_cr_64(u64 curr_cr, u32 new_val) |
5fdbf976 | 7771 | { |
52a46617 | 7772 | return (curr_cr & ~((1ULL << 32) - 1)) | new_val; |
5fdbf976 MT |
7773 | } |
7774 | ||
717746e3 | 7775 | static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr) |
bbd9b64e | 7776 | { |
717746e3 | 7777 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
52a46617 GN |
7778 | unsigned long value; |
7779 | ||
7780 | switch (cr) { | |
7781 | case 0: | |
7782 | value = kvm_read_cr0(vcpu); | |
7783 | break; | |
7784 | case 2: | |
7785 | value = vcpu->arch.cr2; | |
7786 | break; | |
7787 | case 3: | |
9f8fe504 | 7788 | value = kvm_read_cr3(vcpu); |
52a46617 GN |
7789 | break; |
7790 | case 4: | |
7791 | value = kvm_read_cr4(vcpu); | |
7792 | break; | |
7793 | case 8: | |
7794 | value = kvm_get_cr8(vcpu); | |
7795 | break; | |
7796 | default: | |
a737f256 | 7797 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
52a46617 GN |
7798 | return 0; |
7799 | } | |
7800 | ||
7801 | return value; | |
7802 | } | |
7803 | ||
717746e3 | 7804 | static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val) |
52a46617 | 7805 | { |
717746e3 | 7806 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
0f12244f GN |
7807 | int res = 0; |
7808 | ||
52a46617 GN |
7809 | switch (cr) { |
7810 | case 0: | |
49a9b07e | 7811 | res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val)); |
52a46617 GN |
7812 | break; |
7813 | case 2: | |
7814 | vcpu->arch.cr2 = val; | |
7815 | break; | |
7816 | case 3: | |
2390218b | 7817 | res = kvm_set_cr3(vcpu, val); |
52a46617 GN |
7818 | break; |
7819 | case 4: | |
a83b29c6 | 7820 | res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val)); |
52a46617 GN |
7821 | break; |
7822 | case 8: | |
eea1cff9 | 7823 | res = kvm_set_cr8(vcpu, val); |
52a46617 GN |
7824 | break; |
7825 | default: | |
a737f256 | 7826 | kvm_err("%s: unexpected cr %u\n", __func__, cr); |
0f12244f | 7827 | res = -1; |
52a46617 | 7828 | } |
0f12244f GN |
7829 | |
7830 | return res; | |
52a46617 GN |
7831 | } |
7832 | ||
717746e3 | 7833 | static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt) |
9c537244 | 7834 | { |
b3646477 | 7835 | return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt)); |
9c537244 GN |
7836 | } |
7837 | ||
4bff1e86 | 7838 | static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
2dafc6c2 | 7839 | { |
b3646477 | 7840 | static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt); |
2dafc6c2 GN |
7841 | } |
7842 | ||
4bff1e86 | 7843 | static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
160ce1f1 | 7844 | { |
b3646477 | 7845 | static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt); |
160ce1f1 MG |
7846 | } |
7847 | ||
1ac9d0cf AK |
7848 | static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) |
7849 | { | |
b3646477 | 7850 | static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
7851 | } |
7852 | ||
7853 | static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt) | |
7854 | { | |
b3646477 | 7855 | static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt); |
1ac9d0cf AK |
7856 | } |
7857 | ||
4bff1e86 AK |
7858 | static unsigned long emulator_get_cached_segment_base( |
7859 | struct x86_emulate_ctxt *ctxt, int seg) | |
5951c442 | 7860 | { |
4bff1e86 | 7861 | return get_segment_base(emul_to_vcpu(ctxt), seg); |
5951c442 GN |
7862 | } |
7863 | ||
1aa36616 AK |
7864 | static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector, |
7865 | struct desc_struct *desc, u32 *base3, | |
7866 | int seg) | |
2dafc6c2 GN |
7867 | { |
7868 | struct kvm_segment var; | |
7869 | ||
4bff1e86 | 7870 | kvm_get_segment(emul_to_vcpu(ctxt), &var, seg); |
1aa36616 | 7871 | *selector = var.selector; |
2dafc6c2 | 7872 | |
378a8b09 GN |
7873 | if (var.unusable) { |
7874 | memset(desc, 0, sizeof(*desc)); | |
f0367ee1 RK |
7875 | if (base3) |
7876 | *base3 = 0; | |
2dafc6c2 | 7877 | return false; |
378a8b09 | 7878 | } |
2dafc6c2 GN |
7879 | |
7880 | if (var.g) | |
7881 | var.limit >>= 12; | |
7882 | set_desc_limit(desc, var.limit); | |
7883 | set_desc_base(desc, (unsigned long)var.base); | |
5601d05b GN |
7884 | #ifdef CONFIG_X86_64 |
7885 | if (base3) | |
7886 | *base3 = var.base >> 32; | |
7887 | #endif | |
2dafc6c2 GN |
7888 | desc->type = var.type; |
7889 | desc->s = var.s; | |
7890 | desc->dpl = var.dpl; | |
7891 | desc->p = var.present; | |
7892 | desc->avl = var.avl; | |
7893 | desc->l = var.l; | |
7894 | desc->d = var.db; | |
7895 | desc->g = var.g; | |
7896 | ||
7897 | return true; | |
7898 | } | |
7899 | ||
1aa36616 AK |
7900 | static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector, |
7901 | struct desc_struct *desc, u32 base3, | |
7902 | int seg) | |
2dafc6c2 | 7903 | { |
4bff1e86 | 7904 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
2dafc6c2 GN |
7905 | struct kvm_segment var; |
7906 | ||
1aa36616 | 7907 | var.selector = selector; |
2dafc6c2 | 7908 | var.base = get_desc_base(desc); |
5601d05b GN |
7909 | #ifdef CONFIG_X86_64 |
7910 | var.base |= ((u64)base3) << 32; | |
7911 | #endif | |
2dafc6c2 GN |
7912 | var.limit = get_desc_limit(desc); |
7913 | if (desc->g) | |
7914 | var.limit = (var.limit << 12) | 0xfff; | |
7915 | var.type = desc->type; | |
2dafc6c2 GN |
7916 | var.dpl = desc->dpl; |
7917 | var.db = desc->d; | |
7918 | var.s = desc->s; | |
7919 | var.l = desc->l; | |
7920 | var.g = desc->g; | |
7921 | var.avl = desc->avl; | |
7922 | var.present = desc->p; | |
7923 | var.unusable = !var.present; | |
7924 | var.padding = 0; | |
7925 | ||
7926 | kvm_set_segment(vcpu, &var, seg); | |
7927 | return; | |
7928 | } | |
7929 | ||
ac8d6cad HW |
7930 | static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt, |
7931 | u32 msr_index, u64 *pdata) | |
717746e3 | 7932 | { |
1ae09954 AG |
7933 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7934 | int r; | |
7935 | ||
ac8d6cad | 7936 | r = kvm_get_msr_with_filter(vcpu, msr_index, pdata); |
36d546d5 HW |
7937 | if (r < 0) |
7938 | return X86EMUL_UNHANDLEABLE; | |
1ae09954 | 7939 | |
36d546d5 HW |
7940 | if (r) { |
7941 | if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0, | |
7942 | complete_emulated_rdmsr, r)) | |
7943 | return X86EMUL_IO_NEEDED; | |
794663e1 HW |
7944 | |
7945 | trace_kvm_msr_read_ex(msr_index); | |
36d546d5 | 7946 | return X86EMUL_PROPAGATE_FAULT; |
1ae09954 AG |
7947 | } |
7948 | ||
794663e1 | 7949 | trace_kvm_msr_read(msr_index, *pdata); |
36d546d5 | 7950 | return X86EMUL_CONTINUE; |
717746e3 AK |
7951 | } |
7952 | ||
ac8d6cad HW |
7953 | static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt, |
7954 | u32 msr_index, u64 data) | |
717746e3 | 7955 | { |
1ae09954 AG |
7956 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
7957 | int r; | |
7958 | ||
ac8d6cad | 7959 | r = kvm_set_msr_with_filter(vcpu, msr_index, data); |
36d546d5 HW |
7960 | if (r < 0) |
7961 | return X86EMUL_UNHANDLEABLE; | |
1ae09954 | 7962 | |
36d546d5 HW |
7963 | if (r) { |
7964 | if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data, | |
7965 | complete_emulated_msr_access, r)) | |
7966 | return X86EMUL_IO_NEEDED; | |
794663e1 HW |
7967 | |
7968 | trace_kvm_msr_write_ex(msr_index, data); | |
36d546d5 | 7969 | return X86EMUL_PROPAGATE_FAULT; |
1ae09954 AG |
7970 | } |
7971 | ||
794663e1 | 7972 | trace_kvm_msr_write(msr_index, data); |
36d546d5 | 7973 | return X86EMUL_CONTINUE; |
717746e3 AK |
7974 | } |
7975 | ||
ac8d6cad HW |
7976 | static int emulator_get_msr(struct x86_emulate_ctxt *ctxt, |
7977 | u32 msr_index, u64 *pdata) | |
7978 | { | |
7979 | return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata); | |
7980 | } | |
7981 | ||
7982 | static int emulator_set_msr(struct x86_emulate_ctxt *ctxt, | |
7983 | u32 msr_index, u64 data) | |
7984 | { | |
7985 | return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data); | |
7986 | } | |
7987 | ||
64d60670 PB |
7988 | static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt) |
7989 | { | |
7990 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
7991 | ||
7992 | return vcpu->arch.smbase; | |
7993 | } | |
7994 | ||
7995 | static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase) | |
7996 | { | |
7997 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
7998 | ||
7999 | vcpu->arch.smbase = smbase; | |
8000 | } | |
8001 | ||
67f4d428 NA |
8002 | static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt, |
8003 | u32 pmc) | |
8004 | { | |
e6cd31f1 JM |
8005 | if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc)) |
8006 | return 0; | |
8007 | return -EINVAL; | |
67f4d428 NA |
8008 | } |
8009 | ||
222d21aa AK |
8010 | static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt, |
8011 | u32 pmc, u64 *pdata) | |
8012 | { | |
c6702c9d | 8013 | return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata); |
222d21aa AK |
8014 | } |
8015 | ||
6c3287f7 AK |
8016 | static void emulator_halt(struct x86_emulate_ctxt *ctxt) |
8017 | { | |
8018 | emul_to_vcpu(ctxt)->arch.halt_request = 1; | |
8019 | } | |
8020 | ||
2953538e | 8021 | static int emulator_intercept(struct x86_emulate_ctxt *ctxt, |
8a76d7f2 | 8022 | struct x86_instruction_info *info, |
c4f035c6 AK |
8023 | enum x86_intercept_stage stage) |
8024 | { | |
b3646477 | 8025 | return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage, |
21f1b8f2 | 8026 | &ctxt->exception); |
c4f035c6 AK |
8027 | } |
8028 | ||
e911eb3b | 8029 | static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt, |
f91af517 SC |
8030 | u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, |
8031 | bool exact_only) | |
bdb42f5a | 8032 | { |
f91af517 | 8033 | return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only); |
bdb42f5a SB |
8034 | } |
8035 | ||
5ae78e95 SC |
8036 | static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt) |
8037 | { | |
8038 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM); | |
8039 | } | |
8040 | ||
8041 | static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt) | |
8042 | { | |
8043 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE); | |
8044 | } | |
8045 | ||
8046 | static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt) | |
8047 | { | |
8048 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR); | |
8049 | } | |
8050 | ||
a836839c HW |
8051 | static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt) |
8052 | { | |
8053 | return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID); | |
8054 | } | |
8055 | ||
dd856efa AK |
8056 | static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) |
8057 | { | |
27b4a9c4 | 8058 | return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); |
dd856efa AK |
8059 | } |
8060 | ||
8061 | static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) | |
8062 | { | |
27b4a9c4 | 8063 | kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); |
dd856efa AK |
8064 | } |
8065 | ||
801806d9 NA |
8066 | static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked) |
8067 | { | |
b3646477 | 8068 | static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked); |
801806d9 NA |
8069 | } |
8070 | ||
6ed071f0 LP |
8071 | static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt) |
8072 | { | |
8073 | return emul_to_vcpu(ctxt)->arch.hflags; | |
8074 | } | |
8075 | ||
edce4654 | 8076 | static void emulator_exiting_smm(struct x86_emulate_ctxt *ctxt) |
6ed071f0 | 8077 | { |
78fcb2c9 SC |
8078 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8079 | ||
dc87275f | 8080 | kvm_smm_changed(vcpu, false); |
6ed071f0 LP |
8081 | } |
8082 | ||
ecc513e5 | 8083 | static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt, |
ed19321f | 8084 | const char *smstate) |
0234bf88 | 8085 | { |
ecc513e5 | 8086 | return static_call(kvm_x86_leave_smm)(emul_to_vcpu(ctxt), smstate); |
0234bf88 LP |
8087 | } |
8088 | ||
25b17226 SC |
8089 | static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) |
8090 | { | |
8091 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); | |
8092 | } | |
8093 | ||
02d4160f VK |
8094 | static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) |
8095 | { | |
8096 | return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); | |
8097 | } | |
8098 | ||
1cca2f8c SC |
8099 | static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt) |
8100 | { | |
8101 | struct kvm *kvm = emul_to_vcpu(ctxt)->kvm; | |
8102 | ||
8103 | if (!kvm->vm_bugged) | |
8104 | kvm_vm_bugged(kvm); | |
8105 | } | |
8106 | ||
0225fb50 | 8107 | static const struct x86_emulate_ops emulate_ops = { |
1cca2f8c | 8108 | .vm_bugged = emulator_vm_bugged, |
dd856efa AK |
8109 | .read_gpr = emulator_read_gpr, |
8110 | .write_gpr = emulator_write_gpr, | |
ce14e868 PB |
8111 | .read_std = emulator_read_std, |
8112 | .write_std = emulator_write_std, | |
7a036a6f | 8113 | .read_phys = kvm_read_guest_phys_system, |
1871c602 | 8114 | .fetch = kvm_fetch_guest_virt, |
bbd9b64e CO |
8115 | .read_emulated = emulator_read_emulated, |
8116 | .write_emulated = emulator_write_emulated, | |
8117 | .cmpxchg_emulated = emulator_cmpxchg_emulated, | |
3cb16fe7 | 8118 | .invlpg = emulator_invlpg, |
cf8f70bf GN |
8119 | .pio_in_emulated = emulator_pio_in_emulated, |
8120 | .pio_out_emulated = emulator_pio_out_emulated, | |
1aa36616 AK |
8121 | .get_segment = emulator_get_segment, |
8122 | .set_segment = emulator_set_segment, | |
5951c442 | 8123 | .get_cached_segment_base = emulator_get_cached_segment_base, |
2dafc6c2 | 8124 | .get_gdt = emulator_get_gdt, |
160ce1f1 | 8125 | .get_idt = emulator_get_idt, |
1ac9d0cf AK |
8126 | .set_gdt = emulator_set_gdt, |
8127 | .set_idt = emulator_set_idt, | |
52a46617 GN |
8128 | .get_cr = emulator_get_cr, |
8129 | .set_cr = emulator_set_cr, | |
9c537244 | 8130 | .cpl = emulator_get_cpl, |
35aa5375 GN |
8131 | .get_dr = emulator_get_dr, |
8132 | .set_dr = emulator_set_dr, | |
64d60670 PB |
8133 | .get_smbase = emulator_get_smbase, |
8134 | .set_smbase = emulator_set_smbase, | |
ac8d6cad HW |
8135 | .set_msr_with_filter = emulator_set_msr_with_filter, |
8136 | .get_msr_with_filter = emulator_get_msr_with_filter, | |
717746e3 AK |
8137 | .set_msr = emulator_set_msr, |
8138 | .get_msr = emulator_get_msr, | |
67f4d428 | 8139 | .check_pmc = emulator_check_pmc, |
222d21aa | 8140 | .read_pmc = emulator_read_pmc, |
6c3287f7 | 8141 | .halt = emulator_halt, |
bcaf5cc5 | 8142 | .wbinvd = emulator_wbinvd, |
d6aa1000 | 8143 | .fix_hypercall = emulator_fix_hypercall, |
c4f035c6 | 8144 | .intercept = emulator_intercept, |
bdb42f5a | 8145 | .get_cpuid = emulator_get_cpuid, |
5ae78e95 SC |
8146 | .guest_has_long_mode = emulator_guest_has_long_mode, |
8147 | .guest_has_movbe = emulator_guest_has_movbe, | |
8148 | .guest_has_fxsr = emulator_guest_has_fxsr, | |
a836839c | 8149 | .guest_has_rdpid = emulator_guest_has_rdpid, |
801806d9 | 8150 | .set_nmi_mask = emulator_set_nmi_mask, |
6ed071f0 | 8151 | .get_hflags = emulator_get_hflags, |
edce4654 | 8152 | .exiting_smm = emulator_exiting_smm, |
ecc513e5 | 8153 | .leave_smm = emulator_leave_smm, |
25b17226 | 8154 | .triple_fault = emulator_triple_fault, |
02d4160f | 8155 | .set_xcr = emulator_set_xcr, |
bbd9b64e CO |
8156 | }; |
8157 | ||
95cb2295 GN |
8158 | static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask) |
8159 | { | |
b3646477 | 8160 | u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); |
95cb2295 GN |
8161 | /* |
8162 | * an sti; sti; sequence only disable interrupts for the first | |
8163 | * instruction. So, if the last instruction, be it emulated or | |
8164 | * not, left the system with the INT_STI flag enabled, it | |
8165 | * means that the last instruction is an sti. We should not | |
8166 | * leave the flag on in this case. The same goes for mov ss | |
8167 | */ | |
37ccdcbe PB |
8168 | if (int_shadow & mask) |
8169 | mask = 0; | |
6addfc42 | 8170 | if (unlikely(int_shadow || mask)) { |
b3646477 | 8171 | static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask); |
6addfc42 PB |
8172 | if (!mask) |
8173 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
8174 | } | |
95cb2295 GN |
8175 | } |
8176 | ||
ef54bcfe | 8177 | static bool inject_emulated_exception(struct kvm_vcpu *vcpu) |
54b8486f | 8178 | { |
c9b8b07c | 8179 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
da9cb575 | 8180 | if (ctxt->exception.vector == PF_VECTOR) |
53b3d8e9 | 8181 | return kvm_inject_emulated_page_fault(vcpu, &ctxt->exception); |
ef54bcfe PB |
8182 | |
8183 | if (ctxt->exception.error_code_valid) | |
da9cb575 AK |
8184 | kvm_queue_exception_e(vcpu, ctxt->exception.vector, |
8185 | ctxt->exception.error_code); | |
54b8486f | 8186 | else |
da9cb575 | 8187 | kvm_queue_exception(vcpu, ctxt->exception.vector); |
ef54bcfe | 8188 | return false; |
54b8486f GN |
8189 | } |
8190 | ||
c9b8b07c SC |
8191 | static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu) |
8192 | { | |
8193 | struct x86_emulate_ctxt *ctxt; | |
8194 | ||
8195 | ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT); | |
8196 | if (!ctxt) { | |
8197 | pr_err("kvm: failed to allocate vcpu's emulator\n"); | |
8198 | return NULL; | |
8199 | } | |
8200 | ||
8201 | ctxt->vcpu = vcpu; | |
8202 | ctxt->ops = &emulate_ops; | |
8203 | vcpu->arch.emulate_ctxt = ctxt; | |
8204 | ||
8205 | return ctxt; | |
8206 | } | |
8207 | ||
8ec4722d MG |
8208 | static void init_emulate_ctxt(struct kvm_vcpu *vcpu) |
8209 | { | |
c9b8b07c | 8210 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d MG |
8211 | int cs_db, cs_l; |
8212 | ||
b3646477 | 8213 | static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l); |
8ec4722d | 8214 | |
744e699c | 8215 | ctxt->gpa_available = false; |
adf52235 | 8216 | ctxt->eflags = kvm_get_rflags(vcpu); |
c8401dda PB |
8217 | ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; |
8218 | ||
adf52235 TY |
8219 | ctxt->eip = kvm_rip_read(vcpu); |
8220 | ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL : | |
8221 | (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 : | |
42bf549f | 8222 | (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 : |
adf52235 TY |
8223 | cs_db ? X86EMUL_MODE_PROT32 : |
8224 | X86EMUL_MODE_PROT16; | |
a584539b | 8225 | BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK); |
64d60670 PB |
8226 | BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK); |
8227 | BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK); | |
adf52235 | 8228 | |
da6393cd WL |
8229 | ctxt->interruptibility = 0; |
8230 | ctxt->have_exception = false; | |
8231 | ctxt->exception.vector = -1; | |
8232 | ctxt->perm_ok = false; | |
8233 | ||
dd856efa | 8234 | init_decode_cache(ctxt); |
7ae441ea | 8235 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; |
8ec4722d MG |
8236 | } |
8237 | ||
9497e1f2 | 8238 | void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip) |
63995653 | 8239 | { |
c9b8b07c | 8240 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
63995653 MG |
8241 | int ret; |
8242 | ||
8243 | init_emulate_ctxt(vcpu); | |
8244 | ||
9dac77fa AK |
8245 | ctxt->op_bytes = 2; |
8246 | ctxt->ad_bytes = 2; | |
8247 | ctxt->_eip = ctxt->eip + inc_eip; | |
9d74191a | 8248 | ret = emulate_int_real(ctxt, irq); |
63995653 | 8249 | |
9497e1f2 SC |
8250 | if (ret != X86EMUL_CONTINUE) { |
8251 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); | |
8252 | } else { | |
8253 | ctxt->eip = ctxt->_eip; | |
8254 | kvm_rip_write(vcpu, ctxt->eip); | |
8255 | kvm_set_rflags(vcpu, ctxt->eflags); | |
8256 | } | |
63995653 MG |
8257 | } |
8258 | EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt); | |
8259 | ||
e615e355 DE |
8260 | static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, |
8261 | u8 ndata, u8 *insn_bytes, u8 insn_size) | |
19238e75 | 8262 | { |
19238e75 | 8263 | struct kvm_run *run = vcpu->run; |
e615e355 DE |
8264 | u64 info[5]; |
8265 | u8 info_start; | |
8266 | ||
8267 | /* | |
8268 | * Zero the whole array used to retrieve the exit info, as casting to | |
8269 | * u32 for select entries will leave some chunks uninitialized. | |
8270 | */ | |
8271 | memset(&info, 0, sizeof(info)); | |
8272 | ||
8273 | static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1], | |
8274 | &info[2], (u32 *)&info[3], | |
8275 | (u32 *)&info[4]); | |
19238e75 AL |
8276 | |
8277 | run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
8278 | run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
e615e355 DE |
8279 | |
8280 | /* | |
8281 | * There's currently space for 13 entries, but 5 are used for the exit | |
8282 | * reason and info. Restrict to 4 to reduce the maintenance burden | |
8283 | * when expanding kvm_run.emulation_failure in the future. | |
8284 | */ | |
8285 | if (WARN_ON_ONCE(ndata > 4)) | |
8286 | ndata = 4; | |
8287 | ||
8288 | /* Always include the flags as a 'data' entry. */ | |
8289 | info_start = 1; | |
19238e75 AL |
8290 | run->emulation_failure.flags = 0; |
8291 | ||
8292 | if (insn_size) { | |
e615e355 DE |
8293 | BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) + |
8294 | sizeof(run->emulation_failure.insn_bytes) != 16)); | |
8295 | info_start += 2; | |
19238e75 AL |
8296 | run->emulation_failure.flags |= |
8297 | KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES; | |
8298 | run->emulation_failure.insn_size = insn_size; | |
8299 | memset(run->emulation_failure.insn_bytes, 0x90, | |
8300 | sizeof(run->emulation_failure.insn_bytes)); | |
e615e355 | 8301 | memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size); |
19238e75 | 8302 | } |
e615e355 DE |
8303 | |
8304 | memcpy(&run->internal.data[info_start], info, sizeof(info)); | |
8305 | memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data, | |
8306 | ndata * sizeof(data[0])); | |
8307 | ||
8308 | run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata; | |
19238e75 AL |
8309 | } |
8310 | ||
e615e355 DE |
8311 | static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu) |
8312 | { | |
8313 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; | |
8314 | ||
8315 | prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data, | |
8316 | ctxt->fetch.end - ctxt->fetch.data); | |
8317 | } | |
8318 | ||
8319 | void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data, | |
8320 | u8 ndata) | |
8321 | { | |
8322 | prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0); | |
19238e75 | 8323 | } |
e615e355 DE |
8324 | EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit); |
8325 | ||
8326 | void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu) | |
8327 | { | |
8328 | __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0); | |
8329 | } | |
8330 | EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit); | |
19238e75 | 8331 | |
e2366171 | 8332 | static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type) |
6d77dbfc | 8333 | { |
19238e75 AL |
8334 | struct kvm *kvm = vcpu->kvm; |
8335 | ||
6d77dbfc GN |
8336 | ++vcpu->stat.insn_emulation_fail; |
8337 | trace_kvm_emulate_insn_failed(vcpu); | |
e2366171 | 8338 | |
42cbf068 SC |
8339 | if (emulation_type & EMULTYPE_VMWARE_GP) { |
8340 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 8341 | return 1; |
42cbf068 | 8342 | } |
e2366171 | 8343 | |
19238e75 AL |
8344 | if (kvm->arch.exit_on_emulation_error || |
8345 | (emulation_type & EMULTYPE_SKIP)) { | |
e615e355 | 8346 | prepare_emulation_ctxt_failure_exit(vcpu); |
60fc3d02 | 8347 | return 0; |
738fece4 SC |
8348 | } |
8349 | ||
22da61c9 SC |
8350 | kvm_queue_exception(vcpu, UD_VECTOR); |
8351 | ||
b3646477 | 8352 | if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) { |
e615e355 | 8353 | prepare_emulation_ctxt_failure_exit(vcpu); |
60fc3d02 | 8354 | return 0; |
fc3a9157 | 8355 | } |
e2366171 | 8356 | |
60fc3d02 | 8357 | return 1; |
6d77dbfc GN |
8358 | } |
8359 | ||
736c291c | 8360 | static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
991eebf9 GN |
8361 | bool write_fault_to_shadow_pgtable, |
8362 | int emulation_type) | |
a6f177ef | 8363 | { |
736c291c | 8364 | gpa_t gpa = cr2_or_gpa; |
ba049e93 | 8365 | kvm_pfn_t pfn; |
a6f177ef | 8366 | |
92daa48b | 8367 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
991eebf9 GN |
8368 | return false; |
8369 | ||
92daa48b SC |
8370 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
8371 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
8372 | return false; |
8373 | ||
347a0d0d | 8374 | if (!vcpu->arch.mmu->root_role.direct) { |
95b3cf69 XG |
8375 | /* |
8376 | * Write permission should be allowed since only | |
8377 | * write access need to be emulated. | |
8378 | */ | |
736c291c | 8379 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
a6f177ef | 8380 | |
95b3cf69 XG |
8381 | /* |
8382 | * If the mapping is invalid in guest, let cpu retry | |
8383 | * it to generate fault. | |
8384 | */ | |
6e1d2a3f | 8385 | if (gpa == INVALID_GPA) |
95b3cf69 XG |
8386 | return true; |
8387 | } | |
a6f177ef | 8388 | |
8e3d9d06 XG |
8389 | /* |
8390 | * Do not retry the unhandleable instruction if it faults on the | |
8391 | * readonly host memory, otherwise it will goto a infinite loop: | |
8392 | * retry instruction -> write #PF -> emulation fail -> retry | |
8393 | * instruction -> ... | |
8394 | */ | |
8395 | pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); | |
95b3cf69 XG |
8396 | |
8397 | /* | |
8398 | * If the instruction failed on the error pfn, it can not be fixed, | |
8399 | * report the error to userspace. | |
8400 | */ | |
8401 | if (is_error_noslot_pfn(pfn)) | |
8402 | return false; | |
8403 | ||
8404 | kvm_release_pfn_clean(pfn); | |
8405 | ||
8406 | /* The instructions are well-emulated on direct mmu. */ | |
347a0d0d | 8407 | if (vcpu->arch.mmu->root_role.direct) { |
95b3cf69 XG |
8408 | unsigned int indirect_shadow_pages; |
8409 | ||
531810ca | 8410 | write_lock(&vcpu->kvm->mmu_lock); |
95b3cf69 | 8411 | indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages; |
531810ca | 8412 | write_unlock(&vcpu->kvm->mmu_lock); |
95b3cf69 XG |
8413 | |
8414 | if (indirect_shadow_pages) | |
8415 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
8416 | ||
a6f177ef | 8417 | return true; |
8e3d9d06 | 8418 | } |
a6f177ef | 8419 | |
95b3cf69 XG |
8420 | /* |
8421 | * if emulation was due to access to shadowed page table | |
8422 | * and it failed try to unshadow page and re-enter the | |
8423 | * guest to let CPU execute the instruction. | |
8424 | */ | |
8425 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); | |
93c05d3e XG |
8426 | |
8427 | /* | |
8428 | * If the access faults on its page table, it can not | |
8429 | * be fixed by unprotecting shadow page and it should | |
8430 | * be reported to userspace. | |
8431 | */ | |
8432 | return !write_fault_to_shadow_pgtable; | |
a6f177ef GN |
8433 | } |
8434 | ||
1cb3f3ae | 8435 | static bool retry_instruction(struct x86_emulate_ctxt *ctxt, |
736c291c | 8436 | gpa_t cr2_or_gpa, int emulation_type) |
1cb3f3ae XG |
8437 | { |
8438 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); | |
736c291c | 8439 | unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa; |
1cb3f3ae XG |
8440 | |
8441 | last_retry_eip = vcpu->arch.last_retry_eip; | |
8442 | last_retry_addr = vcpu->arch.last_retry_addr; | |
8443 | ||
8444 | /* | |
8445 | * If the emulation is caused by #PF and it is non-page_table | |
8446 | * writing instruction, it means the VM-EXIT is caused by shadow | |
8447 | * page protected, we can zap the shadow page and retry this | |
8448 | * instruction directly. | |
8449 | * | |
8450 | * Note: if the guest uses a non-page-table modifying instruction | |
8451 | * on the PDE that points to the instruction, then we will unmap | |
8452 | * the instruction and go to an infinite loop. So, we cache the | |
8453 | * last retried eip and the last fault address, if we meet the eip | |
8454 | * and the address again, we can break out of the potential infinite | |
8455 | * loop. | |
8456 | */ | |
8457 | vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0; | |
8458 | ||
92daa48b | 8459 | if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF)) |
1cb3f3ae XG |
8460 | return false; |
8461 | ||
92daa48b SC |
8462 | if (WARN_ON_ONCE(is_guest_mode(vcpu)) || |
8463 | WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF))) | |
6c3dfeb6 SC |
8464 | return false; |
8465 | ||
1cb3f3ae XG |
8466 | if (x86_page_table_writing_insn(ctxt)) |
8467 | return false; | |
8468 | ||
736c291c | 8469 | if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa) |
1cb3f3ae XG |
8470 | return false; |
8471 | ||
8472 | vcpu->arch.last_retry_eip = ctxt->eip; | |
736c291c | 8473 | vcpu->arch.last_retry_addr = cr2_or_gpa; |
1cb3f3ae | 8474 | |
347a0d0d | 8475 | if (!vcpu->arch.mmu->root_role.direct) |
736c291c | 8476 | gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL); |
1cb3f3ae | 8477 | |
22368028 | 8478 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa)); |
1cb3f3ae XG |
8479 | |
8480 | return true; | |
8481 | } | |
8482 | ||
716d51ab GN |
8483 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu); |
8484 | static int complete_emulated_pio(struct kvm_vcpu *vcpu); | |
8485 | ||
dc87275f | 8486 | static void kvm_smm_changed(struct kvm_vcpu *vcpu, bool entering_smm) |
a584539b | 8487 | { |
1270e647 | 8488 | trace_kvm_smm_transition(vcpu->vcpu_id, vcpu->arch.smbase, entering_smm); |
0d7ee6f4 | 8489 | |
dc87275f SC |
8490 | if (entering_smm) { |
8491 | vcpu->arch.hflags |= HF_SMM_MASK; | |
8492 | } else { | |
8493 | vcpu->arch.hflags &= ~(HF_SMM_MASK | HF_SMM_INSIDE_NMI_MASK); | |
8494 | ||
c43203ca PB |
8495 | /* Process a latched INIT or SMI, if any. */ |
8496 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
37687c40 ML |
8497 | |
8498 | /* | |
8499 | * Even if KVM_SET_SREGS2 loaded PDPTRs out of band, | |
8500 | * on SMM exit we still need to reload them from | |
8501 | * guest memory | |
8502 | */ | |
8503 | vcpu->arch.pdptrs_from_userspace = false; | |
64d60670 | 8504 | } |
699023e2 PB |
8505 | |
8506 | kvm_mmu_reset_context(vcpu); | |
64d60670 PB |
8507 | } |
8508 | ||
4a1e10d5 PB |
8509 | static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7, |
8510 | unsigned long *db) | |
8511 | { | |
8512 | u32 dr6 = 0; | |
8513 | int i; | |
8514 | u32 enable, rwlen; | |
8515 | ||
8516 | enable = dr7; | |
8517 | rwlen = dr7 >> 16; | |
8518 | for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4) | |
8519 | if ((enable & 3) && (rwlen & 15) == type && db[i] == addr) | |
8520 | dr6 |= (1 << i); | |
8521 | return dr6; | |
8522 | } | |
8523 | ||
120c2c4f | 8524 | static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu) |
663f4c61 PB |
8525 | { |
8526 | struct kvm_run *kvm_run = vcpu->run; | |
8527 | ||
c8401dda | 8528 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) { |
9a3ecd5e | 8529 | kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW; |
d5d260c5 | 8530 | kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu); |
c8401dda PB |
8531 | kvm_run->debug.arch.exception = DB_VECTOR; |
8532 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 8533 | return 0; |
663f4c61 | 8534 | } |
120c2c4f | 8535 | kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS); |
60fc3d02 | 8536 | return 1; |
663f4c61 PB |
8537 | } |
8538 | ||
6affcbed KH |
8539 | int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu) |
8540 | { | |
b3646477 | 8541 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
f8ea7c60 | 8542 | int r; |
6affcbed | 8543 | |
b3646477 | 8544 | r = static_call(kvm_x86_skip_emulated_instruction)(vcpu); |
60fc3d02 | 8545 | if (unlikely(!r)) |
f8ea7c60 | 8546 | return 0; |
c8401dda | 8547 | |
9cd803d4 EH |
8548 | kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); |
8549 | ||
c8401dda PB |
8550 | /* |
8551 | * rflags is the old, "raw" value of the flags. The new value has | |
8552 | * not been saved yet. | |
8553 | * | |
8554 | * This is correct even for TF set by the guest, because "the | |
8555 | * processor will not generate this exception after the instruction | |
8556 | * that sets the TF flag". | |
8557 | */ | |
8558 | if (unlikely(rflags & X86_EFLAGS_TF)) | |
120c2c4f | 8559 | r = kvm_vcpu_do_singlestep(vcpu); |
60fc3d02 | 8560 | return r; |
6affcbed KH |
8561 | } |
8562 | EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction); | |
8563 | ||
baf67ca8 SC |
8564 | static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu) |
8565 | { | |
8566 | u32 shadow; | |
8567 | ||
8568 | if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF) | |
8569 | return true; | |
8570 | ||
8571 | /* | |
8572 | * Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active, | |
8573 | * but AMD CPUs do not. MOV/POP SS blocking is rare, check that first | |
8574 | * to avoid the relatively expensive CPUID lookup. | |
8575 | */ | |
8576 | shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu); | |
8577 | return (shadow & KVM_X86_SHADOW_INT_MOV_SS) && | |
8578 | guest_cpuid_is_intel(vcpu); | |
8579 | } | |
8580 | ||
750f8fcb SC |
8581 | static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu, |
8582 | int emulation_type, int *r) | |
4a1e10d5 | 8583 | { |
750f8fcb SC |
8584 | WARN_ON_ONCE(emulation_type & EMULTYPE_NO_DECODE); |
8585 | ||
8586 | /* | |
8587 | * Do not check for code breakpoints if hardware has already done the | |
8588 | * checks, as inferred from the emulation type. On NO_DECODE and SKIP, | |
8589 | * the instruction has passed all exception checks, and all intercepted | |
8590 | * exceptions that trigger emulation have lower priority than code | |
8591 | * breakpoints, i.e. the fact that the intercepted exception occurred | |
8592 | * means any code breakpoints have already been serviced. | |
8593 | * | |
8594 | * Note, KVM needs to check for code #DBs on EMULTYPE_TRAP_UD_FORCED as | |
8595 | * hardware has checked the RIP of the magic prefix, but not the RIP of | |
8596 | * the instruction being emulated. The intent of forced emulation is | |
8597 | * to behave as if KVM intercepted the instruction without an exception | |
8598 | * and without a prefix. | |
8599 | */ | |
8600 | if (emulation_type & (EMULTYPE_NO_DECODE | EMULTYPE_SKIP | | |
8601 | EMULTYPE_TRAP_UD | EMULTYPE_VMWARE_GP | EMULTYPE_PF)) | |
8602 | return false; | |
8603 | ||
4a1e10d5 PB |
8604 | if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) && |
8605 | (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) { | |
82b32774 NA |
8606 | struct kvm_run *kvm_run = vcpu->run; |
8607 | unsigned long eip = kvm_get_linear_rip(vcpu); | |
8608 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
8609 | vcpu->arch.guest_debug_dr7, |
8610 | vcpu->arch.eff_db); | |
8611 | ||
8612 | if (dr6 != 0) { | |
9a3ecd5e | 8613 | kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW; |
82b32774 | 8614 | kvm_run->debug.arch.pc = eip; |
4a1e10d5 PB |
8615 | kvm_run->debug.arch.exception = DB_VECTOR; |
8616 | kvm_run->exit_reason = KVM_EXIT_DEBUG; | |
60fc3d02 | 8617 | *r = 0; |
4a1e10d5 PB |
8618 | return true; |
8619 | } | |
8620 | } | |
8621 | ||
4161a569 | 8622 | if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) && |
baf67ca8 | 8623 | !kvm_is_code_breakpoint_inhibited(vcpu)) { |
82b32774 NA |
8624 | unsigned long eip = kvm_get_linear_rip(vcpu); |
8625 | u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0, | |
4a1e10d5 PB |
8626 | vcpu->arch.dr7, |
8627 | vcpu->arch.db); | |
8628 | ||
8629 | if (dr6 != 0) { | |
4d5523cf | 8630 | kvm_queue_exception_p(vcpu, DB_VECTOR, dr6); |
60fc3d02 | 8631 | *r = 1; |
4a1e10d5 PB |
8632 | return true; |
8633 | } | |
8634 | } | |
8635 | ||
8636 | return false; | |
8637 | } | |
8638 | ||
04789b66 LA |
8639 | static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt) |
8640 | { | |
2d7921c4 AM |
8641 | switch (ctxt->opcode_len) { |
8642 | case 1: | |
8643 | switch (ctxt->b) { | |
8644 | case 0xe4: /* IN */ | |
8645 | case 0xe5: | |
8646 | case 0xec: | |
8647 | case 0xed: | |
8648 | case 0xe6: /* OUT */ | |
8649 | case 0xe7: | |
8650 | case 0xee: | |
8651 | case 0xef: | |
8652 | case 0x6c: /* INS */ | |
8653 | case 0x6d: | |
8654 | case 0x6e: /* OUTS */ | |
8655 | case 0x6f: | |
8656 | return true; | |
8657 | } | |
8658 | break; | |
8659 | case 2: | |
8660 | switch (ctxt->b) { | |
8661 | case 0x33: /* RDPMC */ | |
8662 | return true; | |
8663 | } | |
8664 | break; | |
04789b66 LA |
8665 | } |
8666 | ||
8667 | return false; | |
8668 | } | |
8669 | ||
4aa2691d | 8670 | /* |
fee060cd SC |
8671 | * Decode an instruction for emulation. The caller is responsible for handling |
8672 | * code breakpoints. Note, manually detecting code breakpoints is unnecessary | |
8673 | * (and wrong) when emulating on an intercepted fault-like exception[*], as | |
8674 | * code breakpoints have higher priority and thus have already been done by | |
8675 | * hardware. | |
8676 | * | |
8677 | * [*] Except #MC, which is higher priority, but KVM should never emulate in | |
8678 | * response to a machine check. | |
4aa2691d WH |
8679 | */ |
8680 | int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type, | |
8681 | void *insn, int insn_len) | |
8682 | { | |
4aa2691d | 8683 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
fee060cd | 8684 | int r; |
4aa2691d WH |
8685 | |
8686 | init_emulate_ctxt(vcpu); | |
8687 | ||
b35491e6 | 8688 | r = x86_decode_insn(ctxt, insn, insn_len, emulation_type); |
4aa2691d WH |
8689 | |
8690 | trace_kvm_emulate_insn_start(vcpu); | |
8691 | ++vcpu->stat.insn_emulation; | |
8692 | ||
8693 | return r; | |
8694 | } | |
8695 | EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction); | |
8696 | ||
736c291c SC |
8697 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, |
8698 | int emulation_type, void *insn, int insn_len) | |
bbd9b64e | 8699 | { |
95cb2295 | 8700 | int r; |
c9b8b07c | 8701 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
7ae441ea | 8702 | bool writeback = true; |
09e3e2a1 SC |
8703 | bool write_fault_to_spt; |
8704 | ||
4d31d9ef | 8705 | if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len))) |
09e3e2a1 | 8706 | return 1; |
bbd9b64e | 8707 | |
c595ceee PB |
8708 | vcpu->arch.l1tf_flush_l1d = true; |
8709 | ||
93c05d3e XG |
8710 | /* |
8711 | * Clear write_fault_to_shadow_pgtable here to ensure it is | |
8712 | * never reused. | |
8713 | */ | |
09e3e2a1 | 8714 | write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable; |
93c05d3e | 8715 | vcpu->arch.write_fault_to_shadow_pgtable = false; |
8d7d8102 | 8716 | |
571008da | 8717 | if (!(emulation_type & EMULTYPE_NO_DECODE)) { |
4aa2691d | 8718 | kvm_clear_exception_queue(vcpu); |
4a1e10d5 | 8719 | |
fee060cd SC |
8720 | /* |
8721 | * Return immediately if RIP hits a code breakpoint, such #DBs | |
8722 | * are fault-like and are higher priority than any faults on | |
8723 | * the code fetch itself. | |
8724 | */ | |
750f8fcb | 8725 | if (kvm_vcpu_check_code_breakpoint(vcpu, emulation_type, &r)) |
fee060cd SC |
8726 | return r; |
8727 | ||
4aa2691d WH |
8728 | r = x86_decode_emulated_instruction(vcpu, emulation_type, |
8729 | insn, insn_len); | |
1d2887e2 | 8730 | if (r != EMULATION_OK) { |
b4000606 | 8731 | if ((emulation_type & EMULTYPE_TRAP_UD) || |
c83fad65 SC |
8732 | (emulation_type & EMULTYPE_TRAP_UD_FORCED)) { |
8733 | kvm_queue_exception(vcpu, UD_VECTOR); | |
60fc3d02 | 8734 | return 1; |
c83fad65 | 8735 | } |
736c291c SC |
8736 | if (reexecute_instruction(vcpu, cr2_or_gpa, |
8737 | write_fault_to_spt, | |
8738 | emulation_type)) | |
60fc3d02 | 8739 | return 1; |
8530a79c | 8740 | if (ctxt->have_exception) { |
c8848cee JD |
8741 | /* |
8742 | * #UD should result in just EMULATION_FAILED, and trap-like | |
8743 | * exception should not be encountered during decode. | |
8744 | */ | |
8745 | WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR || | |
8746 | exception_type(ctxt->exception.vector) == EXCPT_TRAP); | |
8530a79c | 8747 | inject_emulated_exception(vcpu); |
60fc3d02 | 8748 | return 1; |
8530a79c | 8749 | } |
e2366171 | 8750 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
8751 | } |
8752 | } | |
8753 | ||
42cbf068 SC |
8754 | if ((emulation_type & EMULTYPE_VMWARE_GP) && |
8755 | !is_vmware_backdoor_opcode(ctxt)) { | |
8756 | kvm_queue_exception_e(vcpu, GP_VECTOR, 0); | |
60fc3d02 | 8757 | return 1; |
42cbf068 | 8758 | } |
04789b66 | 8759 | |
1957aa63 | 8760 | /* |
906fa904 HW |
8761 | * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for |
8762 | * use *only* by vendor callbacks for kvm_skip_emulated_instruction(). | |
8763 | * The caller is responsible for updating interruptibility state and | |
8764 | * injecting single-step #DBs. | |
1957aa63 | 8765 | */ |
ba8afb6b | 8766 | if (emulation_type & EMULTYPE_SKIP) { |
5e854864 SC |
8767 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
8768 | ctxt->eip = (u32)ctxt->_eip; | |
8769 | else | |
8770 | ctxt->eip = ctxt->_eip; | |
8771 | ||
906fa904 HW |
8772 | if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) { |
8773 | r = 1; | |
8774 | goto writeback; | |
8775 | } | |
8776 | ||
5e854864 | 8777 | kvm_rip_write(vcpu, ctxt->eip); |
bb663c7a NA |
8778 | if (ctxt->eflags & X86_EFLAGS_RF) |
8779 | kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF); | |
60fc3d02 | 8780 | return 1; |
ba8afb6b GN |
8781 | } |
8782 | ||
736c291c | 8783 | if (retry_instruction(ctxt, cr2_or_gpa, emulation_type)) |
60fc3d02 | 8784 | return 1; |
1cb3f3ae | 8785 | |
7ae441ea | 8786 | /* this is needed for vmware backdoor interface to work since it |
4d2179e1 | 8787 | changes registers values during IO operation */ |
7ae441ea GN |
8788 | if (vcpu->arch.emulate_regs_need_sync_from_vcpu) { |
8789 | vcpu->arch.emulate_regs_need_sync_from_vcpu = false; | |
dd856efa | 8790 | emulator_invalidate_register_cache(ctxt); |
7ae441ea | 8791 | } |
4d2179e1 | 8792 | |
5cd21917 | 8793 | restart: |
92daa48b SC |
8794 | if (emulation_type & EMULTYPE_PF) { |
8795 | /* Save the faulting GPA (cr2) in the address field */ | |
8796 | ctxt->exception.address = cr2_or_gpa; | |
8797 | ||
8798 | /* With shadow page tables, cr2 contains a GVA or nGPA. */ | |
347a0d0d | 8799 | if (vcpu->arch.mmu->root_role.direct) { |
744e699c SC |
8800 | ctxt->gpa_available = true; |
8801 | ctxt->gpa_val = cr2_or_gpa; | |
92daa48b SC |
8802 | } |
8803 | } else { | |
8804 | /* Sanitize the address out of an abundance of paranoia. */ | |
8805 | ctxt->exception.address = 0; | |
8806 | } | |
0f89b207 | 8807 | |
9d74191a | 8808 | r = x86_emulate_insn(ctxt); |
bbd9b64e | 8809 | |
775fde86 | 8810 | if (r == EMULATION_INTERCEPTED) |
60fc3d02 | 8811 | return 1; |
775fde86 | 8812 | |
d2ddd1c4 | 8813 | if (r == EMULATION_FAILED) { |
736c291c | 8814 | if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt, |
991eebf9 | 8815 | emulation_type)) |
60fc3d02 | 8816 | return 1; |
c3cd7ffa | 8817 | |
e2366171 | 8818 | return handle_emulation_failure(vcpu, emulation_type); |
bbd9b64e CO |
8819 | } |
8820 | ||
9d74191a | 8821 | if (ctxt->have_exception) { |
60fc3d02 | 8822 | r = 1; |
ef54bcfe PB |
8823 | if (inject_emulated_exception(vcpu)) |
8824 | return r; | |
d2ddd1c4 | 8825 | } else if (vcpu->arch.pio.count) { |
0912c977 PB |
8826 | if (!vcpu->arch.pio.in) { |
8827 | /* FIXME: return into emulator if single-stepping. */ | |
3457e419 | 8828 | vcpu->arch.pio.count = 0; |
0912c977 | 8829 | } else { |
7ae441ea | 8830 | writeback = false; |
716d51ab GN |
8831 | vcpu->arch.complete_userspace_io = complete_emulated_pio; |
8832 | } | |
60fc3d02 | 8833 | r = 0; |
7ae441ea | 8834 | } else if (vcpu->mmio_needed) { |
bc8a0aaf SC |
8835 | ++vcpu->stat.mmio_exits; |
8836 | ||
7ae441ea GN |
8837 | if (!vcpu->mmio_is_write) |
8838 | writeback = false; | |
60fc3d02 | 8839 | r = 0; |
716d51ab | 8840 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; |
adbfb12d HW |
8841 | } else if (vcpu->arch.complete_userspace_io) { |
8842 | writeback = false; | |
8843 | r = 0; | |
7ae441ea | 8844 | } else if (r == EMULATION_RESTART) |
5cd21917 | 8845 | goto restart; |
d2ddd1c4 | 8846 | else |
60fc3d02 | 8847 | r = 1; |
f850e2e6 | 8848 | |
906fa904 | 8849 | writeback: |
7ae441ea | 8850 | if (writeback) { |
b3646477 | 8851 | unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu); |
9d74191a | 8852 | toggle_interruptibility(vcpu, ctxt->interruptibility); |
7ae441ea | 8853 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
5623f751 SC |
8854 | |
8855 | /* | |
8856 | * Note, EXCPT_DB is assumed to be fault-like as the emulator | |
8857 | * only supports code breakpoints and general detect #DB, both | |
8858 | * of which are fault-like. | |
8859 | */ | |
38827dbd | 8860 | if (!ctxt->have_exception || |
75ee23b3 | 8861 | exception_type(ctxt->exception.vector) == EXCPT_TRAP) { |
9cd803d4 | 8862 | kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS); |
018d70ff EH |
8863 | if (ctxt->is_branch) |
8864 | kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS); | |
75ee23b3 | 8865 | kvm_rip_write(vcpu, ctxt->eip); |
384dea1c | 8866 | if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP))) |
120c2c4f | 8867 | r = kvm_vcpu_do_singlestep(vcpu); |
2a890614 | 8868 | static_call_cond(kvm_x86_update_emulated_instruction)(vcpu); |
38827dbd | 8869 | __kvm_set_rflags(vcpu, ctxt->eflags); |
75ee23b3 | 8870 | } |
6addfc42 PB |
8871 | |
8872 | /* | |
8873 | * For STI, interrupts are shadowed; so KVM_REQ_EVENT will | |
8874 | * do nothing, and it will be requested again as soon as | |
8875 | * the shadow expires. But we still need to check here, | |
8876 | * because POPF has no interrupt shadow. | |
8877 | */ | |
8878 | if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF)) | |
8879 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
7ae441ea GN |
8880 | } else |
8881 | vcpu->arch.emulate_regs_need_sync_to_vcpu = true; | |
e85d28f8 GN |
8882 | |
8883 | return r; | |
de7d789a | 8884 | } |
c60658d1 SC |
8885 | |
8886 | int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type) | |
8887 | { | |
8888 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); | |
8889 | } | |
8890 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction); | |
8891 | ||
8892 | int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu, | |
8893 | void *insn, int insn_len) | |
8894 | { | |
8895 | return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len); | |
8896 | } | |
8897 | EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer); | |
de7d789a | 8898 | |
8764ed55 SC |
8899 | static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu) |
8900 | { | |
8901 | vcpu->arch.pio.count = 0; | |
8902 | return 1; | |
8903 | } | |
8904 | ||
45def77e SC |
8905 | static int complete_fast_pio_out(struct kvm_vcpu *vcpu) |
8906 | { | |
8907 | vcpu->arch.pio.count = 0; | |
8908 | ||
8909 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) | |
8910 | return 1; | |
8911 | ||
8912 | return kvm_skip_emulated_instruction(vcpu); | |
8913 | } | |
8914 | ||
dca7f128 SC |
8915 | static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, |
8916 | unsigned short port) | |
de7d789a | 8917 | { |
de3cd117 | 8918 | unsigned long val = kvm_rax_read(vcpu); |
2e3bb4d8 SC |
8919 | int ret = emulator_pio_out(vcpu, size, port, &val, 1); |
8920 | ||
8764ed55 SC |
8921 | if (ret) |
8922 | return ret; | |
45def77e | 8923 | |
8764ed55 SC |
8924 | /* |
8925 | * Workaround userspace that relies on old KVM behavior of %rip being | |
8926 | * incremented prior to exiting to userspace to handle "OUT 0x7e". | |
8927 | */ | |
8928 | if (port == 0x7e && | |
8929 | kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) { | |
8930 | vcpu->arch.complete_userspace_io = | |
8931 | complete_fast_pio_out_port_0x7e; | |
8932 | kvm_skip_emulated_instruction(vcpu); | |
8933 | } else { | |
45def77e SC |
8934 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8935 | vcpu->arch.complete_userspace_io = complete_fast_pio_out; | |
8936 | } | |
8764ed55 | 8937 | return 0; |
de7d789a | 8938 | } |
de7d789a | 8939 | |
8370c3d0 TL |
8940 | static int complete_fast_pio_in(struct kvm_vcpu *vcpu) |
8941 | { | |
8942 | unsigned long val; | |
8943 | ||
8944 | /* We should only ever be called with arch.pio.count equal to 1 */ | |
8945 | BUG_ON(vcpu->arch.pio.count != 1); | |
8946 | ||
45def77e SC |
8947 | if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) { |
8948 | vcpu->arch.pio.count = 0; | |
8949 | return 1; | |
8950 | } | |
8951 | ||
8370c3d0 | 8952 | /* For size less than 4 we merge, else we zero extend */ |
de3cd117 | 8953 | val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 8954 | |
7a6177d6 | 8955 | complete_emulator_pio_in(vcpu, &val); |
de3cd117 | 8956 | kvm_rax_write(vcpu, val); |
8370c3d0 | 8957 | |
45def77e | 8958 | return kvm_skip_emulated_instruction(vcpu); |
8370c3d0 TL |
8959 | } |
8960 | ||
dca7f128 SC |
8961 | static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, |
8962 | unsigned short port) | |
8370c3d0 TL |
8963 | { |
8964 | unsigned long val; | |
8965 | int ret; | |
8966 | ||
8967 | /* For size less than 4 we merge, else we zero extend */ | |
de3cd117 | 8968 | val = (size < 4) ? kvm_rax_read(vcpu) : 0; |
8370c3d0 | 8969 | |
2e3bb4d8 | 8970 | ret = emulator_pio_in(vcpu, size, port, &val, 1); |
8370c3d0 | 8971 | if (ret) { |
de3cd117 | 8972 | kvm_rax_write(vcpu, val); |
8370c3d0 TL |
8973 | return ret; |
8974 | } | |
8975 | ||
45def77e | 8976 | vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu); |
8370c3d0 TL |
8977 | vcpu->arch.complete_userspace_io = complete_fast_pio_in; |
8978 | ||
8979 | return 0; | |
8980 | } | |
dca7f128 SC |
8981 | |
8982 | int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in) | |
8983 | { | |
45def77e | 8984 | int ret; |
dca7f128 | 8985 | |
dca7f128 | 8986 | if (in) |
45def77e | 8987 | ret = kvm_fast_pio_in(vcpu, size, port); |
dca7f128 | 8988 | else |
45def77e SC |
8989 | ret = kvm_fast_pio_out(vcpu, size, port); |
8990 | return ret && kvm_skip_emulated_instruction(vcpu); | |
dca7f128 SC |
8991 | } |
8992 | EXPORT_SYMBOL_GPL(kvm_fast_pio); | |
8370c3d0 | 8993 | |
251a5fd6 | 8994 | static int kvmclock_cpu_down_prep(unsigned int cpu) |
8cfdc000 | 8995 | { |
0a3aee0d | 8996 | __this_cpu_write(cpu_tsc_khz, 0); |
251a5fd6 | 8997 | return 0; |
8cfdc000 ZA |
8998 | } |
8999 | ||
9000 | static void tsc_khz_changed(void *data) | |
c8076604 | 9001 | { |
8cfdc000 ZA |
9002 | struct cpufreq_freqs *freq = data; |
9003 | unsigned long khz = 0; | |
9004 | ||
9005 | if (data) | |
9006 | khz = freq->new; | |
9007 | else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
9008 | khz = cpufreq_quick_get(raw_smp_processor_id()); | |
9009 | if (!khz) | |
9010 | khz = tsc_khz; | |
0a3aee0d | 9011 | __this_cpu_write(cpu_tsc_khz, khz); |
c8076604 GH |
9012 | } |
9013 | ||
5fa4ec9c | 9014 | #ifdef CONFIG_X86_64 |
0092e434 VK |
9015 | static void kvm_hyperv_tsc_notifier(void) |
9016 | { | |
0092e434 | 9017 | struct kvm *kvm; |
0092e434 VK |
9018 | int cpu; |
9019 | ||
0d9ce162 | 9020 | mutex_lock(&kvm_lock); |
0092e434 VK |
9021 | list_for_each_entry(kvm, &vm_list, vm_list) |
9022 | kvm_make_mclock_inprogress_request(kvm); | |
9023 | ||
6b6fcd28 | 9024 | /* no guest entries from this point */ |
0092e434 VK |
9025 | hyperv_stop_tsc_emulation(); |
9026 | ||
9027 | /* TSC frequency always matches when on Hyper-V */ | |
9028 | for_each_present_cpu(cpu) | |
9029 | per_cpu(cpu_tsc_khz, cpu) = tsc_khz; | |
938c8745 | 9030 | kvm_caps.max_guest_tsc_khz = tsc_khz; |
0092e434 VK |
9031 | |
9032 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
869b4421 | 9033 | __kvm_start_pvclock_update(kvm); |
0092e434 | 9034 | pvclock_update_vm_gtod_copy(kvm); |
6b6fcd28 | 9035 | kvm_end_pvclock_update(kvm); |
0092e434 | 9036 | } |
6b6fcd28 | 9037 | |
0d9ce162 | 9038 | mutex_unlock(&kvm_lock); |
0092e434 | 9039 | } |
5fa4ec9c | 9040 | #endif |
0092e434 | 9041 | |
df24014a | 9042 | static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu) |
c8076604 | 9043 | { |
c8076604 GH |
9044 | struct kvm *kvm; |
9045 | struct kvm_vcpu *vcpu; | |
46808a4c MZ |
9046 | int send_ipi = 0; |
9047 | unsigned long i; | |
c8076604 | 9048 | |
8cfdc000 ZA |
9049 | /* |
9050 | * We allow guests to temporarily run on slowing clocks, | |
9051 | * provided we notify them after, or to run on accelerating | |
9052 | * clocks, provided we notify them before. Thus time never | |
9053 | * goes backwards. | |
9054 | * | |
9055 | * However, we have a problem. We can't atomically update | |
9056 | * the frequency of a given CPU from this function; it is | |
9057 | * merely a notifier, which can be called from any CPU. | |
9058 | * Changing the TSC frequency at arbitrary points in time | |
9059 | * requires a recomputation of local variables related to | |
9060 | * the TSC for each VCPU. We must flag these local variables | |
9061 | * to be updated and be sure the update takes place with the | |
9062 | * new frequency before any guests proceed. | |
9063 | * | |
9064 | * Unfortunately, the combination of hotplug CPU and frequency | |
9065 | * change creates an intractable locking scenario; the order | |
9066 | * of when these callouts happen is undefined with respect to | |
9067 | * CPU hotplug, and they can race with each other. As such, | |
9068 | * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is | |
9069 | * undefined; you can actually have a CPU frequency change take | |
9070 | * place in between the computation of X and the setting of the | |
9071 | * variable. To protect against this problem, all updates of | |
9072 | * the per_cpu tsc_khz variable are done in an interrupt | |
9073 | * protected IPI, and all callers wishing to update the value | |
9074 | * must wait for a synchronous IPI to complete (which is trivial | |
9075 | * if the caller is on the CPU already). This establishes the | |
9076 | * necessary total order on variable updates. | |
9077 | * | |
9078 | * Note that because a guest time update may take place | |
9079 | * anytime after the setting of the VCPU's request bit, the | |
9080 | * correct TSC value must be set before the request. However, | |
9081 | * to ensure the update actually makes it to any guest which | |
9082 | * starts running in hardware virtualization between the set | |
9083 | * and the acquisition of the spinlock, we must also ping the | |
9084 | * CPU after setting the request bit. | |
9085 | * | |
9086 | */ | |
9087 | ||
df24014a | 9088 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 9089 | |
0d9ce162 | 9090 | mutex_lock(&kvm_lock); |
c8076604 | 9091 | list_for_each_entry(kvm, &vm_list, vm_list) { |
988a2cae | 9092 | kvm_for_each_vcpu(i, vcpu, kvm) { |
df24014a | 9093 | if (vcpu->cpu != cpu) |
c8076604 | 9094 | continue; |
c285545f | 9095 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0d9ce162 | 9096 | if (vcpu->cpu != raw_smp_processor_id()) |
8cfdc000 | 9097 | send_ipi = 1; |
c8076604 GH |
9098 | } |
9099 | } | |
0d9ce162 | 9100 | mutex_unlock(&kvm_lock); |
c8076604 GH |
9101 | |
9102 | if (freq->old < freq->new && send_ipi) { | |
9103 | /* | |
9104 | * We upscale the frequency. Must make the guest | |
9105 | * doesn't see old kvmclock values while running with | |
9106 | * the new frequency, otherwise we risk the guest sees | |
9107 | * time go backwards. | |
9108 | * | |
9109 | * In case we update the frequency for another cpu | |
9110 | * (which might be in guest context) send an interrupt | |
9111 | * to kick the cpu out of guest context. Next time | |
9112 | * guest context is entered kvmclock will be updated, | |
9113 | * so the guest will not see stale values. | |
9114 | */ | |
df24014a | 9115 | smp_call_function_single(cpu, tsc_khz_changed, freq, 1); |
c8076604 | 9116 | } |
df24014a VK |
9117 | } |
9118 | ||
9119 | static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val, | |
9120 | void *data) | |
9121 | { | |
9122 | struct cpufreq_freqs *freq = data; | |
9123 | int cpu; | |
9124 | ||
9125 | if (val == CPUFREQ_PRECHANGE && freq->old > freq->new) | |
9126 | return 0; | |
9127 | if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new) | |
9128 | return 0; | |
9129 | ||
9130 | for_each_cpu(cpu, freq->policy->cpus) | |
9131 | __kvmclock_cpufreq_notifier(freq, cpu); | |
9132 | ||
c8076604 GH |
9133 | return 0; |
9134 | } | |
9135 | ||
9136 | static struct notifier_block kvmclock_cpufreq_notifier_block = { | |
8cfdc000 ZA |
9137 | .notifier_call = kvmclock_cpufreq_notifier |
9138 | }; | |
9139 | ||
251a5fd6 | 9140 | static int kvmclock_cpu_online(unsigned int cpu) |
8cfdc000 | 9141 | { |
251a5fd6 SAS |
9142 | tsc_khz_changed(NULL); |
9143 | return 0; | |
8cfdc000 ZA |
9144 | } |
9145 | ||
b820cc0c ZA |
9146 | static void kvm_timer_init(void) |
9147 | { | |
b820cc0c | 9148 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
741e511b SC |
9149 | max_tsc_khz = tsc_khz; |
9150 | ||
9151 | if (IS_ENABLED(CONFIG_CPU_FREQ)) { | |
9152 | struct cpufreq_policy *policy; | |
9153 | int cpu; | |
9154 | ||
9155 | cpu = get_cpu(); | |
9156 | policy = cpufreq_cpu_get(cpu); | |
9157 | if (policy) { | |
9158 | if (policy->cpuinfo.max_freq) | |
9159 | max_tsc_khz = policy->cpuinfo.max_freq; | |
9160 | cpufreq_cpu_put(policy); | |
9161 | } | |
9162 | put_cpu(); | |
9a11997e | 9163 | } |
b820cc0c ZA |
9164 | cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block, |
9165 | CPUFREQ_TRANSITION_NOTIFIER); | |
9166 | } | |
460dd42e | 9167 | |
73c1b41e | 9168 | cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online", |
251a5fd6 | 9169 | kvmclock_cpu_online, kvmclock_cpu_down_prep); |
b820cc0c ZA |
9170 | } |
9171 | ||
16e8d74d MT |
9172 | #ifdef CONFIG_X86_64 |
9173 | static void pvclock_gtod_update_fn(struct work_struct *work) | |
9174 | { | |
d828199e | 9175 | struct kvm *kvm; |
d828199e | 9176 | struct kvm_vcpu *vcpu; |
46808a4c | 9177 | unsigned long i; |
d828199e | 9178 | |
0d9ce162 | 9179 | mutex_lock(&kvm_lock); |
d828199e MT |
9180 | list_for_each_entry(kvm, &vm_list, vm_list) |
9181 | kvm_for_each_vcpu(i, vcpu, kvm) | |
105b21bb | 9182 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
d828199e | 9183 | atomic_set(&kvm_guest_has_master_clock, 0); |
0d9ce162 | 9184 | mutex_unlock(&kvm_lock); |
16e8d74d MT |
9185 | } |
9186 | ||
9187 | static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn); | |
9188 | ||
3f804f6d TG |
9189 | /* |
9190 | * Indirection to move queue_work() out of the tk_core.seq write held | |
9191 | * region to prevent possible deadlocks against time accessors which | |
9192 | * are invoked with work related locks held. | |
9193 | */ | |
9194 | static void pvclock_irq_work_fn(struct irq_work *w) | |
9195 | { | |
9196 | queue_work(system_long_wq, &pvclock_gtod_work); | |
9197 | } | |
9198 | ||
9199 | static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn); | |
9200 | ||
16e8d74d MT |
9201 | /* |
9202 | * Notification about pvclock gtod data update. | |
9203 | */ | |
9204 | static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, | |
9205 | void *priv) | |
9206 | { | |
9207 | struct pvclock_gtod_data *gtod = &pvclock_gtod_data; | |
9208 | struct timekeeper *tk = priv; | |
9209 | ||
9210 | update_pvclock_gtod(tk); | |
9211 | ||
3f804f6d TG |
9212 | /* |
9213 | * Disable master clock if host does not trust, or does not use, | |
9214 | * TSC based clocksource. Delegate queue_work() to irq_work as | |
9215 | * this is invoked with tk_core.seq write held. | |
16e8d74d | 9216 | */ |
b0c39dc6 | 9217 | if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) && |
16e8d74d | 9218 | atomic_read(&kvm_guest_has_master_clock) != 0) |
3f804f6d | 9219 | irq_work_queue(&pvclock_irq_work); |
16e8d74d MT |
9220 | return 0; |
9221 | } | |
9222 | ||
9223 | static struct notifier_block pvclock_gtod_notifier = { | |
9224 | .notifier_call = pvclock_gtod_notify, | |
9225 | }; | |
9226 | #endif | |
9227 | ||
f8c16bba | 9228 | int kvm_arch_init(void *opaque) |
043405e1 | 9229 | { |
d008dfdb | 9230 | struct kvm_x86_init_ops *ops = opaque; |
94bda2f4 | 9231 | u64 host_pat; |
b820cc0c | 9232 | int r; |
f8c16bba | 9233 | |
afaf0b2f | 9234 | if (kvm_x86_ops.hardware_enable) { |
9dadfc4a | 9235 | pr_err("kvm: already loaded vendor module '%s'\n", kvm_x86_ops.name); |
82ffad2d | 9236 | return -EEXIST; |
f8c16bba ZX |
9237 | } |
9238 | ||
9239 | if (!ops->cpu_has_kvm_support()) { | |
9dadfc4a SC |
9240 | pr_err_ratelimited("kvm: no hardware support for '%s'\n", |
9241 | ops->runtime_ops->name); | |
82ffad2d | 9242 | return -EOPNOTSUPP; |
f8c16bba ZX |
9243 | } |
9244 | if (ops->disabled_by_bios()) { | |
9dadfc4a SC |
9245 | pr_err_ratelimited("kvm: support for '%s' disabled by bios\n", |
9246 | ops->runtime_ops->name); | |
82ffad2d | 9247 | return -EOPNOTSUPP; |
f8c16bba ZX |
9248 | } |
9249 | ||
b666a4b6 MO |
9250 | /* |
9251 | * KVM explicitly assumes that the guest has an FPU and | |
9252 | * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the | |
9253 | * vCPU's FPU state as a fxregs_state struct. | |
9254 | */ | |
9255 | if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) { | |
9256 | printk(KERN_ERR "kvm: inadequate fpu\n"); | |
82ffad2d | 9257 | return -EOPNOTSUPP; |
b666a4b6 MO |
9258 | } |
9259 | ||
5e17b2ee TG |
9260 | if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) { |
9261 | pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n"); | |
82ffad2d | 9262 | return -EOPNOTSUPP; |
b666a4b6 MO |
9263 | } |
9264 | ||
94bda2f4 SC |
9265 | /* |
9266 | * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes | |
9267 | * the PAT bits in SPTEs. Bail if PAT[0] is programmed to something | |
9268 | * other than WB. Note, EPT doesn't utilize the PAT, but don't bother | |
9269 | * with an exception. PAT[0] is set to WB on RESET and also by the | |
9270 | * kernel, i.e. failure indicates a kernel bug or broken firmware. | |
9271 | */ | |
9272 | if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) || | |
9273 | (host_pat & GENMASK(2, 0)) != 6) { | |
9274 | pr_err("kvm: host PAT[0] is not WB\n"); | |
82ffad2d | 9275 | return -EIO; |
94bda2f4 | 9276 | } |
b666a4b6 | 9277 | |
c9b8b07c SC |
9278 | x86_emulator_cache = kvm_alloc_emulator_cache(); |
9279 | if (!x86_emulator_cache) { | |
9280 | pr_err("kvm: failed to allocate cache for x86 emulator\n"); | |
82ffad2d | 9281 | return -ENOMEM; |
c9b8b07c SC |
9282 | } |
9283 | ||
7e34fbd0 SC |
9284 | user_return_msrs = alloc_percpu(struct kvm_user_return_msrs); |
9285 | if (!user_return_msrs) { | |
9286 | printk(KERN_ERR "kvm: failed to allocate percpu kvm_user_return_msrs\n"); | |
82ffad2d | 9287 | r = -ENOMEM; |
c9b8b07c | 9288 | goto out_free_x86_emulator_cache; |
013f6a5d | 9289 | } |
e5fda4bb | 9290 | kvm_nr_uret_msrs = 0; |
013f6a5d | 9291 | |
1d0e8480 | 9292 | r = kvm_mmu_vendor_module_init(); |
97db56ce | 9293 | if (r) |
013f6a5d | 9294 | goto out_free_percpu; |
97db56ce | 9295 | |
b820cc0c | 9296 | kvm_timer_init(); |
c8076604 | 9297 | |
cfc48181 | 9298 | if (boot_cpu_has(X86_FEATURE_XSAVE)) { |
2acf923e | 9299 | host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK); |
938c8745 | 9300 | kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0; |
cfc48181 | 9301 | } |
2acf923e | 9302 | |
0c5f81da | 9303 | if (pi_inject_timer == -1) |
04d4e665 | 9304 | pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER); |
16e8d74d MT |
9305 | #ifdef CONFIG_X86_64 |
9306 | pvclock_gtod_register_notifier(&pvclock_gtod_notifier); | |
0092e434 | 9307 | |
5fa4ec9c | 9308 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 | 9309 | set_hv_tscchange_cb(kvm_hyperv_tsc_notifier); |
16e8d74d MT |
9310 | #endif |
9311 | ||
f8c16bba | 9312 | return 0; |
56c6d28a | 9313 | |
013f6a5d | 9314 | out_free_percpu: |
7e34fbd0 | 9315 | free_percpu(user_return_msrs); |
c9b8b07c SC |
9316 | out_free_x86_emulator_cache: |
9317 | kmem_cache_destroy(x86_emulator_cache); | |
56c6d28a | 9318 | return r; |
043405e1 | 9319 | } |
8776e519 | 9320 | |
f8c16bba ZX |
9321 | void kvm_arch_exit(void) |
9322 | { | |
0092e434 | 9323 | #ifdef CONFIG_X86_64 |
5fa4ec9c | 9324 | if (hypervisor_is_type(X86_HYPER_MS_HYPERV)) |
0092e434 VK |
9325 | clear_hv_tscchange_cb(); |
9326 | #endif | |
cef84c30 | 9327 | kvm_lapic_exit(); |
ff9d07a0 | 9328 | |
888d256e JK |
9329 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) |
9330 | cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block, | |
9331 | CPUFREQ_TRANSITION_NOTIFIER); | |
251a5fd6 | 9332 | cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE); |
16e8d74d MT |
9333 | #ifdef CONFIG_X86_64 |
9334 | pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier); | |
3f804f6d | 9335 | irq_work_sync(&pvclock_irq_work); |
594b27e6 | 9336 | cancel_work_sync(&pvclock_gtod_work); |
16e8d74d | 9337 | #endif |
afaf0b2f | 9338 | kvm_x86_ops.hardware_enable = NULL; |
1d0e8480 | 9339 | kvm_mmu_vendor_module_exit(); |
7e34fbd0 | 9340 | free_percpu(user_return_msrs); |
dfdc0a71 | 9341 | kmem_cache_destroy(x86_emulator_cache); |
b59b153d | 9342 | #ifdef CONFIG_KVM_XEN |
c462f859 | 9343 | static_key_deferred_flush(&kvm_xen_enabled); |
7d6bbebb | 9344 | WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key)); |
b59b153d | 9345 | #endif |
56c6d28a | 9346 | } |
f8c16bba | 9347 | |
1460179d | 9348 | static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason) |
8776e519 | 9349 | { |
91b99ea7 SC |
9350 | /* |
9351 | * The vCPU has halted, e.g. executed HLT. Update the run state if the | |
9352 | * local APIC is in-kernel, the run loop will detect the non-runnable | |
9353 | * state and halt the vCPU. Exit to userspace if the local APIC is | |
9354 | * managed by userspace, in which case userspace is responsible for | |
9355 | * handling wake events. | |
9356 | */ | |
8776e519 | 9357 | ++vcpu->stat.halt_exits; |
35754c98 | 9358 | if (lapic_in_kernel(vcpu)) { |
647daca2 | 9359 | vcpu->arch.mp_state = state; |
8776e519 HB |
9360 | return 1; |
9361 | } else { | |
647daca2 | 9362 | vcpu->run->exit_reason = reason; |
8776e519 HB |
9363 | return 0; |
9364 | } | |
9365 | } | |
647daca2 | 9366 | |
1460179d | 9367 | int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu) |
647daca2 | 9368 | { |
1460179d | 9369 | return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT); |
647daca2 | 9370 | } |
1460179d | 9371 | EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip); |
5cb56059 JS |
9372 | |
9373 | int kvm_emulate_halt(struct kvm_vcpu *vcpu) | |
9374 | { | |
6affcbed KH |
9375 | int ret = kvm_skip_emulated_instruction(vcpu); |
9376 | /* | |
9377 | * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered | |
9378 | * KVM_EXIT_DEBUG here. | |
9379 | */ | |
1460179d | 9380 | return kvm_emulate_halt_noskip(vcpu) && ret; |
5cb56059 | 9381 | } |
8776e519 HB |
9382 | EXPORT_SYMBOL_GPL(kvm_emulate_halt); |
9383 | ||
647daca2 TL |
9384 | int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu) |
9385 | { | |
9386 | int ret = kvm_skip_emulated_instruction(vcpu); | |
9387 | ||
1460179d SC |
9388 | return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD, |
9389 | KVM_EXIT_AP_RESET_HOLD) && ret; | |
647daca2 TL |
9390 | } |
9391 | EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold); | |
9392 | ||
8ef81a9a | 9393 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
9394 | static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr, |
9395 | unsigned long clock_type) | |
9396 | { | |
9397 | struct kvm_clock_pairing clock_pairing; | |
899a31f5 | 9398 | struct timespec64 ts; |
80fbd89c | 9399 | u64 cycle; |
55dd00a7 MT |
9400 | int ret; |
9401 | ||
9402 | if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK) | |
9403 | return -KVM_EOPNOTSUPP; | |
9404 | ||
3a55f729 AR |
9405 | /* |
9406 | * When tsc is in permanent catchup mode guests won't be able to use | |
9407 | * pvclock_read_retry loop to get consistent view of pvclock | |
9408 | */ | |
9409 | if (vcpu->arch.tsc_always_catchup) | |
9410 | return -KVM_EOPNOTSUPP; | |
9411 | ||
7ca7f3b9 | 9412 | if (!kvm_get_walltime_and_clockread(&ts, &cycle)) |
55dd00a7 MT |
9413 | return -KVM_EOPNOTSUPP; |
9414 | ||
9415 | clock_pairing.sec = ts.tv_sec; | |
9416 | clock_pairing.nsec = ts.tv_nsec; | |
9417 | clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle); | |
9418 | clock_pairing.flags = 0; | |
bcbfbd8e | 9419 | memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad)); |
55dd00a7 MT |
9420 | |
9421 | ret = 0; | |
9422 | if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing, | |
9423 | sizeof(struct kvm_clock_pairing))) | |
9424 | ret = -KVM_EFAULT; | |
9425 | ||
9426 | return ret; | |
9427 | } | |
8ef81a9a | 9428 | #endif |
55dd00a7 | 9429 | |
6aef266c SV |
9430 | /* |
9431 | * kvm_pv_kick_cpu_op: Kick a vcpu. | |
9432 | * | |
9433 | * @apicid - apicid of vcpu to be kicked. | |
9434 | */ | |
9d68c6f6 | 9435 | static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid) |
6aef266c | 9436 | { |
8a414f94 VK |
9437 | /* |
9438 | * All other fields are unused for APIC_DM_REMRD, but may be consumed by | |
9439 | * common code, e.g. for tracing. Defer initialization to the compiler. | |
9440 | */ | |
9441 | struct kvm_lapic_irq lapic_irq = { | |
9442 | .delivery_mode = APIC_DM_REMRD, | |
9443 | .dest_mode = APIC_DEST_PHYSICAL, | |
9444 | .shorthand = APIC_DEST_NOSHORT, | |
9445 | .dest_id = apicid, | |
9446 | }; | |
6aef266c | 9447 | |
795a149e | 9448 | kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL); |
6aef266c SV |
9449 | } |
9450 | ||
4e19c36f SS |
9451 | bool kvm_apicv_activated(struct kvm *kvm) |
9452 | { | |
9453 | return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0); | |
9454 | } | |
9455 | EXPORT_SYMBOL_GPL(kvm_apicv_activated); | |
9456 | ||
d5fa597e ML |
9457 | bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu) |
9458 | { | |
9459 | ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons); | |
9460 | ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu); | |
9461 | ||
9462 | return (vm_reasons | vcpu_reasons) == 0; | |
9463 | } | |
9464 | EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated); | |
4f4c4a3e SC |
9465 | |
9466 | static void set_or_clear_apicv_inhibit(unsigned long *inhibits, | |
9467 | enum kvm_apicv_inhibit reason, bool set) | |
9468 | { | |
9469 | if (set) | |
9470 | __set_bit(reason, inhibits); | |
9471 | else | |
9472 | __clear_bit(reason, inhibits); | |
9473 | ||
9474 | trace_kvm_apicv_inhibit_changed(reason, set, *inhibits); | |
9475 | } | |
9476 | ||
4651fc56 | 9477 | static void kvm_apicv_init(struct kvm *kvm) |
4e19c36f | 9478 | { |
4f4c4a3e SC |
9479 | unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons; |
9480 | ||
187c8833 | 9481 | init_rwsem(&kvm->arch.apicv_update_lock); |
b0a1637f | 9482 | |
4f4c4a3e SC |
9483 | set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true); |
9484 | ||
ef8b4b72 | 9485 | if (!enable_apicv) |
4f4c4a3e | 9486 | set_or_clear_apicv_inhibit(inhibits, |
80f0497c | 9487 | APICV_INHIBIT_REASON_DISABLE, true); |
4e19c36f | 9488 | } |
4e19c36f | 9489 | |
4a7132ef | 9490 | static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id) |
71506297 WL |
9491 | { |
9492 | struct kvm_vcpu *target = NULL; | |
9493 | struct kvm_apic_map *map; | |
9494 | ||
4a7132ef WL |
9495 | vcpu->stat.directed_yield_attempted++; |
9496 | ||
72b268a8 WL |
9497 | if (single_task_running()) |
9498 | goto no_yield; | |
9499 | ||
71506297 | 9500 | rcu_read_lock(); |
4a7132ef | 9501 | map = rcu_dereference(vcpu->kvm->arch.apic_map); |
71506297 WL |
9502 | |
9503 | if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id]) | |
9504 | target = map->phys_map[dest_id]->vcpu; | |
9505 | ||
9506 | rcu_read_unlock(); | |
9507 | ||
4a7132ef WL |
9508 | if (!target || !READ_ONCE(target->ready)) |
9509 | goto no_yield; | |
9510 | ||
a1fa4cbd WL |
9511 | /* Ignore requests to yield to self */ |
9512 | if (vcpu == target) | |
9513 | goto no_yield; | |
9514 | ||
4a7132ef WL |
9515 | if (kvm_vcpu_yield_to(target) <= 0) |
9516 | goto no_yield; | |
9517 | ||
9518 | vcpu->stat.directed_yield_successful++; | |
9519 | ||
9520 | no_yield: | |
9521 | return; | |
71506297 WL |
9522 | } |
9523 | ||
0dbb1123 AK |
9524 | static int complete_hypercall_exit(struct kvm_vcpu *vcpu) |
9525 | { | |
9526 | u64 ret = vcpu->run->hypercall.ret; | |
9527 | ||
9528 | if (!is_64_bit_mode(vcpu)) | |
9529 | ret = (u32)ret; | |
9530 | kvm_rax_write(vcpu, ret); | |
9531 | ++vcpu->stat.hypercalls; | |
9532 | return kvm_skip_emulated_instruction(vcpu); | |
9533 | } | |
9534 | ||
8776e519 HB |
9535 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu) |
9536 | { | |
9537 | unsigned long nr, a0, a1, a2, a3, ret; | |
6356ee0c | 9538 | int op_64_bit; |
8776e519 | 9539 | |
23200b7a JM |
9540 | if (kvm_xen_hypercall_enabled(vcpu->kvm)) |
9541 | return kvm_xen_hypercall(vcpu); | |
9542 | ||
8f014550 | 9543 | if (kvm_hv_hypercall_enabled(vcpu)) |
696ca779 | 9544 | return kvm_hv_hypercall(vcpu); |
55cd8e5a | 9545 | |
de3cd117 SC |
9546 | nr = kvm_rax_read(vcpu); |
9547 | a0 = kvm_rbx_read(vcpu); | |
9548 | a1 = kvm_rcx_read(vcpu); | |
9549 | a2 = kvm_rdx_read(vcpu); | |
9550 | a3 = kvm_rsi_read(vcpu); | |
8776e519 | 9551 | |
229456fc | 9552 | trace_kvm_hypercall(nr, a0, a1, a2, a3); |
2714d1d3 | 9553 | |
b5aead00 | 9554 | op_64_bit = is_64_bit_hypercall(vcpu); |
a449c7aa | 9555 | if (!op_64_bit) { |
8776e519 HB |
9556 | nr &= 0xFFFFFFFF; |
9557 | a0 &= 0xFFFFFFFF; | |
9558 | a1 &= 0xFFFFFFFF; | |
9559 | a2 &= 0xFFFFFFFF; | |
9560 | a3 &= 0xFFFFFFFF; | |
9561 | } | |
9562 | ||
b3646477 | 9563 | if (static_call(kvm_x86_get_cpl)(vcpu) != 0) { |
07708c4a | 9564 | ret = -KVM_EPERM; |
696ca779 | 9565 | goto out; |
07708c4a JK |
9566 | } |
9567 | ||
66570e96 OU |
9568 | ret = -KVM_ENOSYS; |
9569 | ||
8776e519 | 9570 | switch (nr) { |
b93463aa AK |
9571 | case KVM_HC_VAPIC_POLL_IRQ: |
9572 | ret = 0; | |
9573 | break; | |
6aef266c | 9574 | case KVM_HC_KICK_CPU: |
66570e96 OU |
9575 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT)) |
9576 | break; | |
9577 | ||
9d68c6f6 | 9578 | kvm_pv_kick_cpu_op(vcpu->kvm, a1); |
4a7132ef | 9579 | kvm_sched_yield(vcpu, a1); |
6aef266c SV |
9580 | ret = 0; |
9581 | break; | |
8ef81a9a | 9582 | #ifdef CONFIG_X86_64 |
55dd00a7 MT |
9583 | case KVM_HC_CLOCK_PAIRING: |
9584 | ret = kvm_pv_clock_pairing(vcpu, a0, a1); | |
9585 | break; | |
1ed199a4 | 9586 | #endif |
4180bf1b | 9587 | case KVM_HC_SEND_IPI: |
66570e96 OU |
9588 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI)) |
9589 | break; | |
9590 | ||
4180bf1b WL |
9591 | ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit); |
9592 | break; | |
71506297 | 9593 | case KVM_HC_SCHED_YIELD: |
66570e96 OU |
9594 | if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD)) |
9595 | break; | |
9596 | ||
4a7132ef | 9597 | kvm_sched_yield(vcpu, a0); |
71506297 WL |
9598 | ret = 0; |
9599 | break; | |
0dbb1123 AK |
9600 | case KVM_HC_MAP_GPA_RANGE: { |
9601 | u64 gpa = a0, npages = a1, attrs = a2; | |
9602 | ||
9603 | ret = -KVM_ENOSYS; | |
9604 | if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE))) | |
9605 | break; | |
9606 | ||
9607 | if (!PAGE_ALIGNED(gpa) || !npages || | |
9608 | gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) { | |
9609 | ret = -KVM_EINVAL; | |
9610 | break; | |
9611 | } | |
9612 | ||
9613 | vcpu->run->exit_reason = KVM_EXIT_HYPERCALL; | |
9614 | vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE; | |
9615 | vcpu->run->hypercall.args[0] = gpa; | |
9616 | vcpu->run->hypercall.args[1] = npages; | |
9617 | vcpu->run->hypercall.args[2] = attrs; | |
9618 | vcpu->run->hypercall.longmode = op_64_bit; | |
9619 | vcpu->arch.complete_userspace_io = complete_hypercall_exit; | |
9620 | return 0; | |
9621 | } | |
8776e519 HB |
9622 | default: |
9623 | ret = -KVM_ENOSYS; | |
9624 | break; | |
9625 | } | |
696ca779 | 9626 | out: |
a449c7aa NA |
9627 | if (!op_64_bit) |
9628 | ret = (u32)ret; | |
de3cd117 | 9629 | kvm_rax_write(vcpu, ret); |
6356ee0c | 9630 | |
f11c3a8d | 9631 | ++vcpu->stat.hypercalls; |
6356ee0c | 9632 | return kvm_skip_emulated_instruction(vcpu); |
8776e519 HB |
9633 | } |
9634 | EXPORT_SYMBOL_GPL(kvm_emulate_hypercall); | |
9635 | ||
b6785def | 9636 | static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt) |
8776e519 | 9637 | { |
d6aa1000 | 9638 | struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt); |
8776e519 | 9639 | char instruction[3]; |
5fdbf976 | 9640 | unsigned long rip = kvm_rip_read(vcpu); |
8776e519 | 9641 | |
f1a9761f OU |
9642 | /* |
9643 | * If the quirk is disabled, synthesize a #UD and let the guest pick up | |
9644 | * the pieces. | |
9645 | */ | |
9646 | if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) { | |
9647 | ctxt->exception.error_code_valid = false; | |
9648 | ctxt->exception.vector = UD_VECTOR; | |
9649 | ctxt->have_exception = true; | |
9650 | return X86EMUL_PROPAGATE_FAULT; | |
9651 | } | |
9652 | ||
b3646477 | 9653 | static_call(kvm_x86_patch_hypercall)(vcpu, instruction); |
8776e519 | 9654 | |
ce2e852e DV |
9655 | return emulator_write_emulated(ctxt, rip, instruction, 3, |
9656 | &ctxt->exception); | |
8776e519 HB |
9657 | } |
9658 | ||
851ba692 | 9659 | static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu) |
b6c7a5dc | 9660 | { |
782d422b MG |
9661 | return vcpu->run->request_interrupt_window && |
9662 | likely(!pic_in_kernel(vcpu->kvm)); | |
b6c7a5dc HB |
9663 | } |
9664 | ||
8d25b7be | 9665 | /* Called within kvm->srcu read side. */ |
851ba692 | 9666 | static void post_kvm_run_save(struct kvm_vcpu *vcpu) |
b6c7a5dc | 9667 | { |
851ba692 AK |
9668 | struct kvm_run *kvm_run = vcpu->run; |
9669 | ||
c5063551 | 9670 | kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu); |
2d3ad1f4 | 9671 | kvm_run->cr8 = kvm_get_cr8(vcpu); |
b6c7a5dc | 9672 | kvm_run->apic_base = kvm_get_apic_base(vcpu); |
f3d1436d | 9673 | |
127a457a MG |
9674 | kvm_run->ready_for_interrupt_injection = |
9675 | pic_in_kernel(vcpu->kvm) || | |
782d422b | 9676 | kvm_vcpu_ready_for_interrupt_injection(vcpu); |
15aad3be CQ |
9677 | |
9678 | if (is_smm(vcpu)) | |
9679 | kvm_run->flags |= KVM_RUN_X86_SMM; | |
b6c7a5dc HB |
9680 | } |
9681 | ||
95ba8273 GN |
9682 | static void update_cr8_intercept(struct kvm_vcpu *vcpu) |
9683 | { | |
9684 | int max_irr, tpr; | |
9685 | ||
afaf0b2f | 9686 | if (!kvm_x86_ops.update_cr8_intercept) |
95ba8273 GN |
9687 | return; |
9688 | ||
bce87cce | 9689 | if (!lapic_in_kernel(vcpu)) |
88c808fd AK |
9690 | return; |
9691 | ||
ce0a58f4 | 9692 | if (vcpu->arch.apic->apicv_active) |
d62caabb AS |
9693 | return; |
9694 | ||
8db3baa2 GN |
9695 | if (!vcpu->arch.apic->vapic_addr) |
9696 | max_irr = kvm_lapic_find_highest_irr(vcpu); | |
9697 | else | |
9698 | max_irr = -1; | |
95ba8273 GN |
9699 | |
9700 | if (max_irr != -1) | |
9701 | max_irr >>= 4; | |
9702 | ||
9703 | tpr = kvm_lapic_get_cr8(vcpu); | |
9704 | ||
b3646477 | 9705 | static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr); |
95ba8273 GN |
9706 | } |
9707 | ||
b97f0745 | 9708 | |
cb6a32c2 SC |
9709 | int kvm_check_nested_events(struct kvm_vcpu *vcpu) |
9710 | { | |
cb6a32c2 SC |
9711 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
9712 | kvm_x86_ops.nested_ops->triple_fault(vcpu); | |
9713 | return 1; | |
9714 | } | |
9715 | ||
9716 | return kvm_x86_ops.nested_ops->check_events(vcpu); | |
9717 | } | |
9718 | ||
b97f0745 ML |
9719 | static void kvm_inject_exception(struct kvm_vcpu *vcpu) |
9720 | { | |
a61d7c54 SC |
9721 | trace_kvm_inj_exception(vcpu->arch.exception.nr, |
9722 | vcpu->arch.exception.has_error_code, | |
9723 | vcpu->arch.exception.error_code, | |
9724 | vcpu->arch.exception.injected); | |
9725 | ||
b97f0745 ML |
9726 | if (vcpu->arch.exception.error_code && !is_protmode(vcpu)) |
9727 | vcpu->arch.exception.error_code = false; | |
9728 | static_call(kvm_x86_queue_exception)(vcpu); | |
9729 | } | |
9730 | ||
a5f6909a | 9731 | static int inject_pending_event(struct kvm_vcpu *vcpu, bool *req_immediate_exit) |
95ba8273 | 9732 | { |
b6b8a145 | 9733 | int r; |
c6b22f59 | 9734 | bool can_inject = true; |
b6b8a145 | 9735 | |
95ba8273 | 9736 | /* try to reinject previous events if any */ |
664f8e26 | 9737 | |
c6b22f59 | 9738 | if (vcpu->arch.exception.injected) { |
b97f0745 | 9739 | kvm_inject_exception(vcpu); |
c6b22f59 PB |
9740 | can_inject = false; |
9741 | } | |
664f8e26 | 9742 | /* |
a042c26f LA |
9743 | * Do not inject an NMI or interrupt if there is a pending |
9744 | * exception. Exceptions and interrupts are recognized at | |
9745 | * instruction boundaries, i.e. the start of an instruction. | |
9746 | * Trap-like exceptions, e.g. #DB, have higher priority than | |
9747 | * NMIs and interrupts, i.e. traps are recognized before an | |
9748 | * NMI/interrupt that's pending on the same instruction. | |
9749 | * Fault-like exceptions, e.g. #GP and #PF, are the lowest | |
9750 | * priority, but are only generated (pended) during instruction | |
9751 | * execution, i.e. a pending fault-like exception means the | |
9752 | * fault occurred on the *previous* instruction and must be | |
9753 | * serviced prior to recognizing any new events in order to | |
9754 | * fully complete the previous instruction. | |
664f8e26 | 9755 | */ |
1a680e35 | 9756 | else if (!vcpu->arch.exception.pending) { |
c6b22f59 | 9757 | if (vcpu->arch.nmi_injected) { |
e27bc044 | 9758 | static_call(kvm_x86_inject_nmi)(vcpu); |
c6b22f59 PB |
9759 | can_inject = false; |
9760 | } else if (vcpu->arch.interrupt.injected) { | |
2d613912 | 9761 | static_call(kvm_x86_inject_irq)(vcpu, true); |
c6b22f59 PB |
9762 | can_inject = false; |
9763 | } | |
664f8e26 WL |
9764 | } |
9765 | ||
3b82b8d7 SC |
9766 | WARN_ON_ONCE(vcpu->arch.exception.injected && |
9767 | vcpu->arch.exception.pending); | |
9768 | ||
1a680e35 LA |
9769 | /* |
9770 | * Call check_nested_events() even if we reinjected a previous event | |
9771 | * in order for caller to determine if it should require immediate-exit | |
9772 | * from L2 to L1 due to pending L1 events which require exit | |
9773 | * from L2 to L1. | |
9774 | */ | |
56083bdf | 9775 | if (is_guest_mode(vcpu)) { |
cb6a32c2 | 9776 | r = kvm_check_nested_events(vcpu); |
c9d40913 | 9777 | if (r < 0) |
a5f6909a | 9778 | goto out; |
664f8e26 WL |
9779 | } |
9780 | ||
9781 | /* try to inject new event if pending */ | |
b59bb7bd | 9782 | if (vcpu->arch.exception.pending) { |
5623f751 SC |
9783 | /* |
9784 | * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS | |
9785 | * value pushed on the stack. Trap-like exception and all #DBs | |
9786 | * leave RF as-is (KVM follows Intel's behavior in this regard; | |
9787 | * AMD states that code breakpoint #DBs excplitly clear RF=0). | |
9788 | * | |
9789 | * Note, most versions of Intel's SDM and AMD's APM incorrectly | |
9790 | * describe the behavior of General Detect #DBs, which are | |
9791 | * fault-like. They do _not_ set RF, a la code breakpoints. | |
9792 | */ | |
d6e8c854 NA |
9793 | if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT) |
9794 | __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) | | |
9795 | X86_EFLAGS_RF); | |
9796 | ||
f10c729f | 9797 | if (vcpu->arch.exception.nr == DB_VECTOR) { |
f10c729f JM |
9798 | kvm_deliver_exception_payload(vcpu); |
9799 | if (vcpu->arch.dr7 & DR7_GD) { | |
9800 | vcpu->arch.dr7 &= ~DR7_GD; | |
9801 | kvm_update_dr7(vcpu); | |
9802 | } | |
6bdf0662 NA |
9803 | } |
9804 | ||
b97f0745 | 9805 | kvm_inject_exception(vcpu); |
a61d7c54 SC |
9806 | |
9807 | vcpu->arch.exception.pending = false; | |
9808 | vcpu->arch.exception.injected = true; | |
9809 | ||
c6b22f59 | 9810 | can_inject = false; |
1a680e35 LA |
9811 | } |
9812 | ||
61e5f69e ML |
9813 | /* Don't inject interrupts if the user asked to avoid doing so */ |
9814 | if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) | |
9815 | return 0; | |
9816 | ||
c9d40913 PB |
9817 | /* |
9818 | * Finally, inject interrupt events. If an event cannot be injected | |
9819 | * due to architectural conditions (e.g. IF=0) a window-open exit | |
9820 | * will re-request KVM_REQ_EVENT. Sometimes however an event is pending | |
9821 | * and can architecturally be injected, but we cannot do it right now: | |
9822 | * an interrupt could have arrived just now and we have to inject it | |
9823 | * as a vmexit, or there could already an event in the queue, which is | |
9824 | * indicated by can_inject. In that case we request an immediate exit | |
9825 | * in order to make progress and get back here for another iteration. | |
9826 | * The kvm_x86_ops hooks communicate this by returning -EBUSY. | |
9827 | */ | |
9828 | if (vcpu->arch.smi_pending) { | |
b3646477 | 9829 | r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 9830 | if (r < 0) |
a5f6909a | 9831 | goto out; |
c9d40913 PB |
9832 | if (r) { |
9833 | vcpu->arch.smi_pending = false; | |
9834 | ++vcpu->arch.smi_count; | |
9835 | enter_smm(vcpu); | |
9836 | can_inject = false; | |
9837 | } else | |
b3646477 | 9838 | static_call(kvm_x86_enable_smi_window)(vcpu); |
c9d40913 PB |
9839 | } |
9840 | ||
9841 | if (vcpu->arch.nmi_pending) { | |
b3646477 | 9842 | r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 9843 | if (r < 0) |
a5f6909a | 9844 | goto out; |
c9d40913 PB |
9845 | if (r) { |
9846 | --vcpu->arch.nmi_pending; | |
9847 | vcpu->arch.nmi_injected = true; | |
e27bc044 | 9848 | static_call(kvm_x86_inject_nmi)(vcpu); |
c9d40913 | 9849 | can_inject = false; |
b3646477 | 9850 | WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0); |
c9d40913 PB |
9851 | } |
9852 | if (vcpu->arch.nmi_pending) | |
b3646477 | 9853 | static_call(kvm_x86_enable_nmi_window)(vcpu); |
c9d40913 | 9854 | } |
1a680e35 | 9855 | |
c9d40913 | 9856 | if (kvm_cpu_has_injectable_intr(vcpu)) { |
b3646477 | 9857 | r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY; |
c9d40913 | 9858 | if (r < 0) |
a5f6909a | 9859 | goto out; |
c9d40913 PB |
9860 | if (r) { |
9861 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu), false); | |
2d613912 | 9862 | static_call(kvm_x86_inject_irq)(vcpu, false); |
b3646477 | 9863 | WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0); |
c9d40913 PB |
9864 | } |
9865 | if (kvm_cpu_has_injectable_intr(vcpu)) | |
b3646477 | 9866 | static_call(kvm_x86_enable_irq_window)(vcpu); |
95ba8273 | 9867 | } |
ee2cd4b7 | 9868 | |
c9d40913 PB |
9869 | if (is_guest_mode(vcpu) && |
9870 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
9871 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
9872 | *req_immediate_exit = true; | |
9873 | ||
9874 | WARN_ON(vcpu->arch.exception.pending); | |
a5f6909a | 9875 | return 0; |
c9d40913 | 9876 | |
a5f6909a JM |
9877 | out: |
9878 | if (r == -EBUSY) { | |
9879 | *req_immediate_exit = true; | |
9880 | r = 0; | |
9881 | } | |
9882 | return r; | |
95ba8273 GN |
9883 | } |
9884 | ||
7460fb4a AK |
9885 | static void process_nmi(struct kvm_vcpu *vcpu) |
9886 | { | |
9887 | unsigned limit = 2; | |
9888 | ||
9889 | /* | |
9890 | * x86 is limited to one NMI running, and one NMI pending after it. | |
9891 | * If an NMI is already in progress, limit further NMIs to just one. | |
9892 | * Otherwise, allow two (and we'll inject the first one immediately). | |
9893 | */ | |
b3646477 | 9894 | if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected) |
7460fb4a AK |
9895 | limit = 1; |
9896 | ||
9897 | vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0); | |
9898 | vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit); | |
9899 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
9900 | } | |
9901 | ||
ee2cd4b7 | 9902 | static u32 enter_smm_get_segment_flags(struct kvm_segment *seg) |
660a5d51 PB |
9903 | { |
9904 | u32 flags = 0; | |
9905 | flags |= seg->g << 23; | |
9906 | flags |= seg->db << 22; | |
9907 | flags |= seg->l << 21; | |
9908 | flags |= seg->avl << 20; | |
9909 | flags |= seg->present << 15; | |
9910 | flags |= seg->dpl << 13; | |
9911 | flags |= seg->s << 12; | |
9912 | flags |= seg->type << 8; | |
9913 | return flags; | |
9914 | } | |
9915 | ||
ee2cd4b7 | 9916 | static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
9917 | { |
9918 | struct kvm_segment seg; | |
9919 | int offset; | |
9920 | ||
9921 | kvm_get_segment(vcpu, &seg, n); | |
9922 | put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector); | |
9923 | ||
9924 | if (n < 3) | |
9925 | offset = 0x7f84 + n * 12; | |
9926 | else | |
9927 | offset = 0x7f2c + (n - 3) * 12; | |
9928 | ||
9929 | put_smstate(u32, buf, offset + 8, seg.base); | |
9930 | put_smstate(u32, buf, offset + 4, seg.limit); | |
ee2cd4b7 | 9931 | put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
9932 | } |
9933 | ||
efbb288a | 9934 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 9935 | static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n) |
660a5d51 PB |
9936 | { |
9937 | struct kvm_segment seg; | |
9938 | int offset; | |
9939 | u16 flags; | |
9940 | ||
9941 | kvm_get_segment(vcpu, &seg, n); | |
9942 | offset = 0x7e00 + n * 16; | |
9943 | ||
ee2cd4b7 | 9944 | flags = enter_smm_get_segment_flags(&seg) >> 8; |
660a5d51 PB |
9945 | put_smstate(u16, buf, offset, seg.selector); |
9946 | put_smstate(u16, buf, offset + 2, flags); | |
9947 | put_smstate(u32, buf, offset + 4, seg.limit); | |
9948 | put_smstate(u64, buf, offset + 8, seg.base); | |
9949 | } | |
efbb288a | 9950 | #endif |
660a5d51 | 9951 | |
ee2cd4b7 | 9952 | static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 PB |
9953 | { |
9954 | struct desc_ptr dt; | |
9955 | struct kvm_segment seg; | |
9956 | unsigned long val; | |
9957 | int i; | |
9958 | ||
9959 | put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu)); | |
9960 | put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu)); | |
9961 | put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu)); | |
9962 | put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu)); | |
9963 | ||
9964 | for (i = 0; i < 8; i++) | |
27b4a9c4 | 9965 | put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read_raw(vcpu, i)); |
660a5d51 PB |
9966 | |
9967 | kvm_get_dr(vcpu, 6, &val); | |
9968 | put_smstate(u32, buf, 0x7fcc, (u32)val); | |
9969 | kvm_get_dr(vcpu, 7, &val); | |
9970 | put_smstate(u32, buf, 0x7fc8, (u32)val); | |
9971 | ||
9972 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
9973 | put_smstate(u32, buf, 0x7fc4, seg.selector); | |
9974 | put_smstate(u32, buf, 0x7f64, seg.base); | |
9975 | put_smstate(u32, buf, 0x7f60, seg.limit); | |
ee2cd4b7 | 9976 | put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg)); |
660a5d51 PB |
9977 | |
9978 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
9979 | put_smstate(u32, buf, 0x7fc0, seg.selector); | |
9980 | put_smstate(u32, buf, 0x7f80, seg.base); | |
9981 | put_smstate(u32, buf, 0x7f7c, seg.limit); | |
ee2cd4b7 | 9982 | put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg)); |
660a5d51 | 9983 | |
b3646477 | 9984 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
660a5d51 PB |
9985 | put_smstate(u32, buf, 0x7f74, dt.address); |
9986 | put_smstate(u32, buf, 0x7f70, dt.size); | |
9987 | ||
b3646477 | 9988 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
660a5d51 PB |
9989 | put_smstate(u32, buf, 0x7f58, dt.address); |
9990 | put_smstate(u32, buf, 0x7f54, dt.size); | |
9991 | ||
9992 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 9993 | enter_smm_save_seg_32(vcpu, buf, i); |
660a5d51 PB |
9994 | |
9995 | put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu)); | |
9996 | ||
9997 | /* revision id */ | |
9998 | put_smstate(u32, buf, 0x7efc, 0x00020000); | |
9999 | put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase); | |
10000 | } | |
10001 | ||
b68f3cc7 | 10002 | #ifdef CONFIG_X86_64 |
ee2cd4b7 | 10003 | static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf) |
660a5d51 | 10004 | { |
660a5d51 PB |
10005 | struct desc_ptr dt; |
10006 | struct kvm_segment seg; | |
10007 | unsigned long val; | |
10008 | int i; | |
10009 | ||
10010 | for (i = 0; i < 16; i++) | |
27b4a9c4 | 10011 | put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read_raw(vcpu, i)); |
660a5d51 PB |
10012 | |
10013 | put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu)); | |
10014 | put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu)); | |
10015 | ||
10016 | kvm_get_dr(vcpu, 6, &val); | |
10017 | put_smstate(u64, buf, 0x7f68, val); | |
10018 | kvm_get_dr(vcpu, 7, &val); | |
10019 | put_smstate(u64, buf, 0x7f60, val); | |
10020 | ||
10021 | put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu)); | |
10022 | put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu)); | |
10023 | put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu)); | |
10024 | ||
10025 | put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase); | |
10026 | ||
10027 | /* revision id */ | |
10028 | put_smstate(u32, buf, 0x7efc, 0x00020064); | |
10029 | ||
10030 | put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer); | |
10031 | ||
10032 | kvm_get_segment(vcpu, &seg, VCPU_SREG_TR); | |
10033 | put_smstate(u16, buf, 0x7e90, seg.selector); | |
ee2cd4b7 | 10034 | put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
10035 | put_smstate(u32, buf, 0x7e94, seg.limit); |
10036 | put_smstate(u64, buf, 0x7e98, seg.base); | |
10037 | ||
b3646477 | 10038 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
660a5d51 PB |
10039 | put_smstate(u32, buf, 0x7e84, dt.size); |
10040 | put_smstate(u64, buf, 0x7e88, dt.address); | |
10041 | ||
10042 | kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR); | |
10043 | put_smstate(u16, buf, 0x7e70, seg.selector); | |
ee2cd4b7 | 10044 | put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8); |
660a5d51 PB |
10045 | put_smstate(u32, buf, 0x7e74, seg.limit); |
10046 | put_smstate(u64, buf, 0x7e78, seg.base); | |
10047 | ||
b3646477 | 10048 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
660a5d51 PB |
10049 | put_smstate(u32, buf, 0x7e64, dt.size); |
10050 | put_smstate(u64, buf, 0x7e68, dt.address); | |
10051 | ||
10052 | for (i = 0; i < 6; i++) | |
ee2cd4b7 | 10053 | enter_smm_save_seg_64(vcpu, buf, i); |
660a5d51 | 10054 | } |
b68f3cc7 | 10055 | #endif |
660a5d51 | 10056 | |
ee2cd4b7 | 10057 | static void enter_smm(struct kvm_vcpu *vcpu) |
64d60670 | 10058 | { |
660a5d51 | 10059 | struct kvm_segment cs, ds; |
18c3626e | 10060 | struct desc_ptr dt; |
dbc4739b | 10061 | unsigned long cr0; |
660a5d51 | 10062 | char buf[512]; |
660a5d51 | 10063 | |
660a5d51 | 10064 | memset(buf, 0, 512); |
b68f3cc7 | 10065 | #ifdef CONFIG_X86_64 |
d6321d49 | 10066 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
ee2cd4b7 | 10067 | enter_smm_save_state_64(vcpu, buf); |
660a5d51 | 10068 | else |
b68f3cc7 | 10069 | #endif |
ee2cd4b7 | 10070 | enter_smm_save_state_32(vcpu, buf); |
660a5d51 | 10071 | |
0234bf88 | 10072 | /* |
ecc513e5 SC |
10073 | * Give enter_smm() a chance to make ISA-specific changes to the vCPU |
10074 | * state (e.g. leave guest mode) after we've saved the state into the | |
10075 | * SMM state-save area. | |
0234bf88 | 10076 | */ |
ecc513e5 | 10077 | static_call(kvm_x86_enter_smm)(vcpu, buf); |
0234bf88 | 10078 | |
dc87275f | 10079 | kvm_smm_changed(vcpu, true); |
54bf36aa | 10080 | kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf)); |
660a5d51 | 10081 | |
b3646477 | 10082 | if (static_call(kvm_x86_get_nmi_mask)(vcpu)) |
660a5d51 PB |
10083 | vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK; |
10084 | else | |
b3646477 | 10085 | static_call(kvm_x86_set_nmi_mask)(vcpu, true); |
660a5d51 PB |
10086 | |
10087 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); | |
10088 | kvm_rip_write(vcpu, 0x8000); | |
10089 | ||
10090 | cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG); | |
b3646477 | 10091 | static_call(kvm_x86_set_cr0)(vcpu, cr0); |
660a5d51 PB |
10092 | vcpu->arch.cr0 = cr0; |
10093 | ||
b3646477 | 10094 | static_call(kvm_x86_set_cr4)(vcpu, 0); |
660a5d51 | 10095 | |
18c3626e PB |
10096 | /* Undocumented: IDT limit is set to zero on entry to SMM. */ |
10097 | dt.address = dt.size = 0; | |
b3646477 | 10098 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
18c3626e | 10099 | |
996ff542 | 10100 | kvm_set_dr(vcpu, 7, DR7_FIXED_1); |
660a5d51 PB |
10101 | |
10102 | cs.selector = (vcpu->arch.smbase >> 4) & 0xffff; | |
10103 | cs.base = vcpu->arch.smbase; | |
10104 | ||
10105 | ds.selector = 0; | |
10106 | ds.base = 0; | |
10107 | ||
10108 | cs.limit = ds.limit = 0xffffffff; | |
10109 | cs.type = ds.type = 0x3; | |
10110 | cs.dpl = ds.dpl = 0; | |
10111 | cs.db = ds.db = 0; | |
10112 | cs.s = ds.s = 1; | |
10113 | cs.l = ds.l = 0; | |
10114 | cs.g = ds.g = 1; | |
10115 | cs.avl = ds.avl = 0; | |
10116 | cs.present = ds.present = 1; | |
10117 | cs.unusable = ds.unusable = 0; | |
10118 | cs.padding = ds.padding = 0; | |
10119 | ||
10120 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
10121 | kvm_set_segment(vcpu, &ds, VCPU_SREG_DS); | |
10122 | kvm_set_segment(vcpu, &ds, VCPU_SREG_ES); | |
10123 | kvm_set_segment(vcpu, &ds, VCPU_SREG_FS); | |
10124 | kvm_set_segment(vcpu, &ds, VCPU_SREG_GS); | |
10125 | kvm_set_segment(vcpu, &ds, VCPU_SREG_SS); | |
10126 | ||
b68f3cc7 | 10127 | #ifdef CONFIG_X86_64 |
d6321d49 | 10128 | if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) |
b3646477 | 10129 | static_call(kvm_x86_set_efer)(vcpu, 0); |
b68f3cc7 | 10130 | #endif |
660a5d51 | 10131 | |
aedbaf4f | 10132 | kvm_update_cpuid_runtime(vcpu); |
660a5d51 | 10133 | kvm_mmu_reset_context(vcpu); |
64d60670 PB |
10134 | } |
10135 | ||
ee2cd4b7 | 10136 | static void process_smi(struct kvm_vcpu *vcpu) |
c43203ca PB |
10137 | { |
10138 | vcpu->arch.smi_pending = true; | |
10139 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
10140 | } | |
10141 | ||
7ee30bc1 NNL |
10142 | void kvm_make_scan_ioapic_request_mask(struct kvm *kvm, |
10143 | unsigned long *vcpu_bitmap) | |
10144 | { | |
620b2438 | 10145 | kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap); |
7ee30bc1 NNL |
10146 | } |
10147 | ||
2860c4b1 PB |
10148 | void kvm_make_scan_ioapic_request(struct kvm *kvm) |
10149 | { | |
10150 | kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC); | |
10151 | } | |
10152 | ||
8df14af4 SS |
10153 | void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu) |
10154 | { | |
ce0a58f4 | 10155 | struct kvm_lapic *apic = vcpu->arch.apic; |
06ef8134 ML |
10156 | bool activate; |
10157 | ||
8df14af4 SS |
10158 | if (!lapic_in_kernel(vcpu)) |
10159 | return; | |
10160 | ||
187c8833 | 10161 | down_read(&vcpu->kvm->arch.apicv_update_lock); |
66c768d3 | 10162 | preempt_disable(); |
b0a1637f | 10163 | |
8fc9c7a3 SS |
10164 | /* Do not activate APICV when APIC is disabled */ |
10165 | activate = kvm_vcpu_apicv_activated(vcpu) && | |
10166 | (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED); | |
d5fa597e | 10167 | |
ce0a58f4 | 10168 | if (apic->apicv_active == activate) |
06ef8134 ML |
10169 | goto out; |
10170 | ||
ce0a58f4 | 10171 | apic->apicv_active = activate; |
8df14af4 | 10172 | kvm_apic_update_apicv(vcpu); |
b3646477 | 10173 | static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu); |
bca66dbc VK |
10174 | |
10175 | /* | |
10176 | * When APICv gets disabled, we may still have injected interrupts | |
10177 | * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was | |
10178 | * still active when the interrupt got accepted. Make sure | |
10179 | * inject_pending_event() is called to check for that. | |
10180 | */ | |
ce0a58f4 | 10181 | if (!apic->apicv_active) |
bca66dbc | 10182 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
b0a1637f | 10183 | |
06ef8134 | 10184 | out: |
66c768d3 | 10185 | preempt_enable(); |
187c8833 | 10186 | up_read(&vcpu->kvm->arch.apicv_update_lock); |
8df14af4 SS |
10187 | } |
10188 | EXPORT_SYMBOL_GPL(kvm_vcpu_update_apicv); | |
10189 | ||
320af55a SC |
10190 | void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, |
10191 | enum kvm_apicv_inhibit reason, bool set) | |
8df14af4 | 10192 | { |
b0a1637f | 10193 | unsigned long old, new; |
8e205a6b | 10194 | |
187c8833 SC |
10195 | lockdep_assert_held_write(&kvm->arch.apicv_update_lock); |
10196 | ||
7491b7b2 | 10197 | if (!static_call(kvm_x86_check_apicv_inhibit_reasons)(reason)) |
ef8efd7a SS |
10198 | return; |
10199 | ||
b0a1637f ML |
10200 | old = new = kvm->arch.apicv_inhibit_reasons; |
10201 | ||
4f4c4a3e | 10202 | set_or_clear_apicv_inhibit(&new, reason, set); |
8e205a6b | 10203 | |
36222b11 | 10204 | if (!!old != !!new) { |
ee49a893 SC |
10205 | /* |
10206 | * Kick all vCPUs before setting apicv_inhibit_reasons to avoid | |
10207 | * false positives in the sanity check WARN in svm_vcpu_run(). | |
10208 | * This task will wait for all vCPUs to ack the kick IRQ before | |
10209 | * updating apicv_inhibit_reasons, and all other vCPUs will | |
10210 | * block on acquiring apicv_update_lock so that vCPUs can't | |
10211 | * redo svm_vcpu_run() without seeing the new inhibit state. | |
10212 | * | |
10213 | * Note, holding apicv_update_lock and taking it in the read | |
10214 | * side (handling the request) also prevents other vCPUs from | |
10215 | * servicing the request with a stale apicv_inhibit_reasons. | |
10216 | */ | |
36222b11 | 10217 | kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE); |
b0a1637f | 10218 | kvm->arch.apicv_inhibit_reasons = new; |
36222b11 ML |
10219 | if (new) { |
10220 | unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE); | |
36222b11 ML |
10221 | kvm_zap_gfn_range(kvm, gfn, gfn+1); |
10222 | } | |
7491b7b2 | 10223 | } else { |
b0a1637f | 10224 | kvm->arch.apicv_inhibit_reasons = new; |
7491b7b2 | 10225 | } |
b0a1637f | 10226 | } |
7d611233 | 10227 | |
320af55a SC |
10228 | void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm, |
10229 | enum kvm_apicv_inhibit reason, bool set) | |
b0a1637f | 10230 | { |
f1575642 SC |
10231 | if (!enable_apicv) |
10232 | return; | |
10233 | ||
187c8833 | 10234 | down_write(&kvm->arch.apicv_update_lock); |
320af55a | 10235 | __kvm_set_or_clear_apicv_inhibit(kvm, reason, set); |
187c8833 | 10236 | up_write(&kvm->arch.apicv_update_lock); |
8df14af4 | 10237 | } |
320af55a | 10238 | EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit); |
8df14af4 | 10239 | |
3d81bc7e | 10240 | static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu) |
c7c9c56c | 10241 | { |
dcbd3e49 | 10242 | if (!kvm_apic_present(vcpu)) |
3d81bc7e | 10243 | return; |
c7c9c56c | 10244 | |
6308630b | 10245 | bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256); |
c7c9c56c | 10246 | |
b053b2ae | 10247 | if (irqchip_split(vcpu->kvm)) |
6308630b | 10248 | kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors); |
db2bdcbb | 10249 | else { |
37c4dbf3 | 10250 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); |
e97f852f WL |
10251 | if (ioapic_in_kernel(vcpu->kvm)) |
10252 | kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors); | |
db2bdcbb | 10253 | } |
e40ff1d6 LA |
10254 | |
10255 | if (is_guest_mode(vcpu)) | |
10256 | vcpu->arch.load_eoi_exitmap_pending = true; | |
10257 | else | |
10258 | kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu); | |
10259 | } | |
10260 | ||
10261 | static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu) | |
10262 | { | |
10263 | u64 eoi_exit_bitmap[4]; | |
10264 | ||
10265 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) | |
10266 | return; | |
10267 | ||
c5adbb3a | 10268 | if (to_hv_vcpu(vcpu)) { |
f2bc14b6 VK |
10269 | bitmap_or((ulong *)eoi_exit_bitmap, |
10270 | vcpu->arch.ioapic_handled_vectors, | |
10271 | to_hv_synic(vcpu)->vec_bitmap, 256); | |
abb6d479 | 10272 | static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap); |
c5adbb3a | 10273 | return; |
10274 | } | |
f2bc14b6 | 10275 | |
abb6d479 | 10276 | static_call_cond(kvm_x86_load_eoi_exitmap)( |
c5adbb3a | 10277 | vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors); |
c7c9c56c YZ |
10278 | } |
10279 | ||
e649b3f0 ET |
10280 | void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm, |
10281 | unsigned long start, unsigned long end) | |
b1394e74 RK |
10282 | { |
10283 | unsigned long apic_address; | |
10284 | ||
10285 | /* | |
10286 | * The physical address of apic access page is stored in the VMCS. | |
10287 | * Update it when it becomes invalid. | |
10288 | */ | |
10289 | apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); | |
10290 | if (start <= apic_address && apic_address < end) | |
10291 | kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD); | |
10292 | } | |
10293 | ||
683412cc MZ |
10294 | void kvm_arch_guest_memory_reclaimed(struct kvm *kvm) |
10295 | { | |
10296 | static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm); | |
10297 | } | |
10298 | ||
d081a343 | 10299 | static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu) |
4256f43f | 10300 | { |
35754c98 | 10301 | if (!lapic_in_kernel(vcpu)) |
f439ed27 PB |
10302 | return; |
10303 | ||
2a890614 | 10304 | static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu); |
4256f43f | 10305 | } |
4256f43f | 10306 | |
d264ee0c SC |
10307 | void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu) |
10308 | { | |
10309 | smp_send_reschedule(vcpu->cpu); | |
10310 | } | |
10311 | EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit); | |
10312 | ||
9357d939 | 10313 | /* |
8d25b7be | 10314 | * Called within kvm->srcu read side. |
362c698f | 10315 | * Returns 1 to let vcpu_run() continue the guest execution loop without |
9357d939 TY |
10316 | * exiting to the userspace. Otherwise, the value will be returned to the |
10317 | * userspace. | |
10318 | */ | |
851ba692 | 10319 | static int vcpu_enter_guest(struct kvm_vcpu *vcpu) |
b6c7a5dc HB |
10320 | { |
10321 | int r; | |
62a193ed MG |
10322 | bool req_int_win = |
10323 | dm_request_for_irq_injection(vcpu) && | |
10324 | kvm_cpu_accept_dm_intr(vcpu); | |
404d5d7b | 10325 | fastpath_t exit_fastpath; |
62a193ed | 10326 | |
730dca42 | 10327 | bool req_immediate_exit = false; |
b6c7a5dc | 10328 | |
fb04a1ed PX |
10329 | /* Forbid vmenter if vcpu dirty ring is soft-full */ |
10330 | if (unlikely(vcpu->kvm->dirty_ring_size && | |
10331 | kvm_dirty_ring_soft_full(&vcpu->dirty_ring))) { | |
10332 | vcpu->run->exit_reason = KVM_EXIT_DIRTY_RING_FULL; | |
10333 | trace_kvm_dirty_ring_exit(vcpu); | |
10334 | r = 0; | |
10335 | goto out; | |
10336 | } | |
10337 | ||
2fa6e1e1 | 10338 | if (kvm_request_pending(vcpu)) { |
f4d31653 | 10339 | if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) { |
67369273 SC |
10340 | r = -EIO; |
10341 | goto out; | |
10342 | } | |
729c15c2 | 10343 | if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) { |
9a78e158 | 10344 | if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) { |
671ddc70 JM |
10345 | r = 0; |
10346 | goto out; | |
10347 | } | |
10348 | } | |
527d5cd7 SC |
10349 | if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu)) |
10350 | kvm_mmu_free_obsolete_roots(vcpu); | |
a8eeb04a | 10351 | if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu)) |
2f599714 | 10352 | __kvm_migrate_timers(vcpu); |
d828199e | 10353 | if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu)) |
6b6fcd28 | 10354 | kvm_update_masterclock(vcpu->kvm); |
0061d53d MT |
10355 | if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu)) |
10356 | kvm_gen_kvmclock_update(vcpu); | |
34c238a1 ZA |
10357 | if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) { |
10358 | r = kvm_guest_time_update(vcpu); | |
8cfdc000 ZA |
10359 | if (unlikely(r)) |
10360 | goto out; | |
10361 | } | |
a8eeb04a | 10362 | if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu)) |
4731d4c7 | 10363 | kvm_mmu_sync_roots(vcpu); |
727a7e27 PB |
10364 | if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu)) |
10365 | kvm_mmu_load_pgd(vcpu); | |
eeeb4f67 | 10366 | if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) { |
7780938c | 10367 | kvm_vcpu_flush_tlb_all(vcpu); |
eeeb4f67 SC |
10368 | |
10369 | /* Flushing all ASIDs flushes the current ASID... */ | |
10370 | kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); | |
10371 | } | |
40e5f908 | 10372 | kvm_service_local_tlb_flush_requests(vcpu); |
eeeb4f67 | 10373 | |
a8eeb04a | 10374 | if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) { |
851ba692 | 10375 | vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS; |
b93463aa AK |
10376 | r = 0; |
10377 | goto out; | |
10378 | } | |
a8eeb04a | 10379 | if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) { |
cb6a32c2 SC |
10380 | if (is_guest_mode(vcpu)) { |
10381 | kvm_x86_ops.nested_ops->triple_fault(vcpu); | |
10382 | } else { | |
10383 | vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; | |
10384 | vcpu->mmio_needed = 0; | |
10385 | r = 0; | |
10386 | goto out; | |
10387 | } | |
71c4dfaf | 10388 | } |
af585b92 GN |
10389 | if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) { |
10390 | /* Page is swapped out. Do synthetic halt */ | |
10391 | vcpu->arch.apf.halted = true; | |
10392 | r = 1; | |
10393 | goto out; | |
10394 | } | |
c9aaa895 GC |
10395 | if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) |
10396 | record_steal_time(vcpu); | |
64d60670 PB |
10397 | if (kvm_check_request(KVM_REQ_SMI, vcpu)) |
10398 | process_smi(vcpu); | |
7460fb4a AK |
10399 | if (kvm_check_request(KVM_REQ_NMI, vcpu)) |
10400 | process_nmi(vcpu); | |
f5132b01 | 10401 | if (kvm_check_request(KVM_REQ_PMU, vcpu)) |
c6702c9d | 10402 | kvm_pmu_handle_event(vcpu); |
f5132b01 | 10403 | if (kvm_check_request(KVM_REQ_PMI, vcpu)) |
c6702c9d | 10404 | kvm_pmu_deliver_pmi(vcpu); |
7543a635 SR |
10405 | if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) { |
10406 | BUG_ON(vcpu->arch.pending_ioapic_eoi > 255); | |
10407 | if (test_bit(vcpu->arch.pending_ioapic_eoi, | |
6308630b | 10408 | vcpu->arch.ioapic_handled_vectors)) { |
7543a635 SR |
10409 | vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI; |
10410 | vcpu->run->eoi.vector = | |
10411 | vcpu->arch.pending_ioapic_eoi; | |
10412 | r = 0; | |
10413 | goto out; | |
10414 | } | |
10415 | } | |
3d81bc7e YZ |
10416 | if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu)) |
10417 | vcpu_scan_ioapic(vcpu); | |
e40ff1d6 LA |
10418 | if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu)) |
10419 | vcpu_load_eoi_exitmap(vcpu); | |
4256f43f TC |
10420 | if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu)) |
10421 | kvm_vcpu_reload_apic_access_page(vcpu); | |
2ce79189 AS |
10422 | if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) { |
10423 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
10424 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH; | |
d495f942 | 10425 | vcpu->run->system_event.ndata = 0; |
2ce79189 AS |
10426 | r = 0; |
10427 | goto out; | |
10428 | } | |
e516cebb AS |
10429 | if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) { |
10430 | vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT; | |
10431 | vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET; | |
d495f942 | 10432 | vcpu->run->system_event.ndata = 0; |
e516cebb AS |
10433 | r = 0; |
10434 | goto out; | |
10435 | } | |
db397571 | 10436 | if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) { |
9ff5e030 VK |
10437 | struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu); |
10438 | ||
db397571 | 10439 | vcpu->run->exit_reason = KVM_EXIT_HYPERV; |
9ff5e030 | 10440 | vcpu->run->hyperv = hv_vcpu->exit; |
db397571 AS |
10441 | r = 0; |
10442 | goto out; | |
10443 | } | |
f3b138c5 AS |
10444 | |
10445 | /* | |
10446 | * KVM_REQ_HV_STIMER has to be processed after | |
10447 | * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers | |
10448 | * depend on the guest clock being up-to-date | |
10449 | */ | |
1f4b34f8 AS |
10450 | if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu)) |
10451 | kvm_hv_process_stimers(vcpu); | |
8df14af4 SS |
10452 | if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu)) |
10453 | kvm_vcpu_update_apicv(vcpu); | |
557a961a VK |
10454 | if (kvm_check_request(KVM_REQ_APF_READY, vcpu)) |
10455 | kvm_check_async_pf_completion(vcpu); | |
1a155254 | 10456 | if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu)) |
b3646477 | 10457 | static_call(kvm_x86_msr_filter_changed)(vcpu); |
a85863c2 MS |
10458 | |
10459 | if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu)) | |
10460 | static_call(kvm_x86_update_cpu_dirty_logging)(vcpu); | |
2f52d58c | 10461 | } |
b93463aa | 10462 | |
40da8ccd DW |
10463 | if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win || |
10464 | kvm_xen_has_interrupt(vcpu)) { | |
0f1e261e | 10465 | ++vcpu->stat.req_event; |
4fe09bcf JM |
10466 | r = kvm_apic_accept_events(vcpu); |
10467 | if (r < 0) { | |
10468 | r = 0; | |
10469 | goto out; | |
10470 | } | |
66450a21 JK |
10471 | if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
10472 | r = 1; | |
10473 | goto out; | |
10474 | } | |
10475 | ||
a5f6909a JM |
10476 | r = inject_pending_event(vcpu, &req_immediate_exit); |
10477 | if (r < 0) { | |
10478 | r = 0; | |
10479 | goto out; | |
10480 | } | |
c9d40913 | 10481 | if (req_int_win) |
b3646477 | 10482 | static_call(kvm_x86_enable_irq_window)(vcpu); |
b463a6f7 AK |
10483 | |
10484 | if (kvm_lapic_enabled(vcpu)) { | |
10485 | update_cr8_intercept(vcpu); | |
10486 | kvm_lapic_sync_to_vapic(vcpu); | |
10487 | } | |
10488 | } | |
10489 | ||
d8368af8 AK |
10490 | r = kvm_mmu_reload(vcpu); |
10491 | if (unlikely(r)) { | |
d905c069 | 10492 | goto cancel_injection; |
d8368af8 AK |
10493 | } |
10494 | ||
b6c7a5dc HB |
10495 | preempt_disable(); |
10496 | ||
e27bc044 | 10497 | static_call(kvm_x86_prepare_switch_to_guest)(vcpu); |
b95234c8 PB |
10498 | |
10499 | /* | |
10500 | * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt | |
10501 | * IPI are then delayed after guest entry, which ensures that they | |
10502 | * result in virtual interrupt delivery. | |
10503 | */ | |
10504 | local_irq_disable(); | |
66fa226c ML |
10505 | |
10506 | /* Store vcpu->apicv_active before vcpu->mode. */ | |
10507 | smp_store_release(&vcpu->mode, IN_GUEST_MODE); | |
6b7e2d09 | 10508 | |
2031f287 | 10509 | kvm_vcpu_srcu_read_unlock(vcpu); |
01b71917 | 10510 | |
0f127d12 | 10511 | /* |
b95234c8 | 10512 | * 1) We should set ->mode before checking ->requests. Please see |
cde9af6e | 10513 | * the comment in kvm_vcpu_exiting_guest_mode(). |
b95234c8 | 10514 | * |
81b01667 | 10515 | * 2) For APICv, we should set ->mode before checking PID.ON. This |
b95234c8 PB |
10516 | * pairs with the memory barrier implicit in pi_test_and_set_on |
10517 | * (see vmx_deliver_posted_interrupt). | |
10518 | * | |
10519 | * 3) This also orders the write to mode from any reads to the page | |
10520 | * tables done while the VCPU is running. Please see the comment | |
10521 | * in kvm_flush_remote_tlbs. | |
6b7e2d09 | 10522 | */ |
01b71917 | 10523 | smp_mb__after_srcu_read_unlock(); |
b6c7a5dc | 10524 | |
b95234c8 | 10525 | /* |
0f65a9d3 SC |
10526 | * Process pending posted interrupts to handle the case where the |
10527 | * notification IRQ arrived in the host, or was never sent (because the | |
10528 | * target vCPU wasn't running). Do this regardless of the vCPU's APICv | |
10529 | * status, KVM doesn't update assigned devices when APICv is inhibited, | |
10530 | * i.e. they can post interrupts even if APICv is temporarily disabled. | |
b95234c8 | 10531 | */ |
37c4dbf3 PB |
10532 | if (kvm_lapic_enabled(vcpu)) |
10533 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); | |
32f88400 | 10534 | |
5a9f5443 | 10535 | if (kvm_vcpu_exit_request(vcpu)) { |
6b7e2d09 | 10536 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 10537 | smp_wmb(); |
6c142801 AK |
10538 | local_irq_enable(); |
10539 | preempt_enable(); | |
2031f287 | 10540 | kvm_vcpu_srcu_read_lock(vcpu); |
6c142801 | 10541 | r = 1; |
d905c069 | 10542 | goto cancel_injection; |
6c142801 AK |
10543 | } |
10544 | ||
c43203ca PB |
10545 | if (req_immediate_exit) { |
10546 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 10547 | static_call(kvm_x86_request_immediate_exit)(vcpu); |
c43203ca | 10548 | } |
d6185f20 | 10549 | |
2620fe26 SC |
10550 | fpregs_assert_state_consistent(); |
10551 | if (test_thread_flag(TIF_NEED_FPU_LOAD)) | |
10552 | switch_fpu_return(); | |
5f409e20 | 10553 | |
ec5be88a JL |
10554 | if (vcpu->arch.guest_fpu.xfd_err) |
10555 | wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err); | |
10556 | ||
42dbaa5a | 10557 | if (unlikely(vcpu->arch.switch_db_regs)) { |
42dbaa5a JK |
10558 | set_debugreg(0, 7); |
10559 | set_debugreg(vcpu->arch.eff_db[0], 0); | |
10560 | set_debugreg(vcpu->arch.eff_db[1], 1); | |
10561 | set_debugreg(vcpu->arch.eff_db[2], 2); | |
10562 | set_debugreg(vcpu->arch.eff_db[3], 3); | |
f85d4016 LJ |
10563 | } else if (unlikely(hw_breakpoint_active())) { |
10564 | set_debugreg(0, 7); | |
42dbaa5a | 10565 | } |
b6c7a5dc | 10566 | |
b2d2af7e MR |
10567 | guest_timing_enter_irqoff(); |
10568 | ||
d89d04ab | 10569 | for (;;) { |
ee49a893 SC |
10570 | /* |
10571 | * Assert that vCPU vs. VM APICv state is consistent. An APICv | |
10572 | * update must kick and wait for all vCPUs before toggling the | |
10573 | * per-VM state, and responsing vCPUs must wait for the update | |
10574 | * to complete before servicing KVM_REQ_APICV_UPDATE. | |
10575 | */ | |
f8d8ac21 SS |
10576 | WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) && |
10577 | (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED)); | |
ee49a893 | 10578 | |
e27bc044 | 10579 | exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu); |
d89d04ab PB |
10580 | if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST)) |
10581 | break; | |
10582 | ||
37c4dbf3 PB |
10583 | if (kvm_lapic_enabled(vcpu)) |
10584 | static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); | |
de7cd3f6 PB |
10585 | |
10586 | if (unlikely(kvm_vcpu_exit_request(vcpu))) { | |
d89d04ab PB |
10587 | exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED; |
10588 | break; | |
10589 | } | |
de7cd3f6 | 10590 | } |
b6c7a5dc | 10591 | |
c77fb5fe PB |
10592 | /* |
10593 | * Do this here before restoring debug registers on the host. And | |
10594 | * since we do this before handling the vmexit, a DR access vmexit | |
10595 | * can (a) read the correct value of the debug registers, (b) set | |
10596 | * KVM_DEBUGREG_WONT_EXIT again. | |
10597 | */ | |
10598 | if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) { | |
c77fb5fe | 10599 | WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP); |
b3646477 | 10600 | static_call(kvm_x86_sync_dirty_debug_regs)(vcpu); |
70e4da7a | 10601 | kvm_update_dr0123(vcpu); |
70e4da7a | 10602 | kvm_update_dr7(vcpu); |
c77fb5fe PB |
10603 | } |
10604 | ||
24f1e32c FW |
10605 | /* |
10606 | * If the guest has used debug registers, at least dr7 | |
10607 | * will be disabled while returning to the host. | |
10608 | * If we don't have active breakpoints in the host, we don't | |
10609 | * care about the messed up debug address registers. But if | |
10610 | * we have some of them active, restore the old state. | |
10611 | */ | |
59d8eb53 | 10612 | if (hw_breakpoint_active()) |
24f1e32c | 10613 | hw_breakpoint_restore(); |
42dbaa5a | 10614 | |
c967118d | 10615 | vcpu->arch.last_vmentry_cpu = vcpu->cpu; |
4ba76538 | 10616 | vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
1d5f066e | 10617 | |
6b7e2d09 | 10618 | vcpu->mode = OUTSIDE_GUEST_MODE; |
d94e1dc9 | 10619 | smp_wmb(); |
a547c6db | 10620 | |
b5274b1b KT |
10621 | /* |
10622 | * Sync xfd before calling handle_exit_irqoff() which may | |
10623 | * rely on the fact that guest_fpu::xfd is up-to-date (e.g. | |
10624 | * in #NM irqoff handler). | |
10625 | */ | |
10626 | if (vcpu->arch.xfd_no_write_intercept) | |
10627 | fpu_sync_guest_vmexit_xfd_state(); | |
10628 | ||
b3646477 | 10629 | static_call(kvm_x86_handle_exit_irqoff)(vcpu); |
b6c7a5dc | 10630 | |
ec5be88a JL |
10631 | if (vcpu->arch.guest_fpu.xfd_err) |
10632 | wrmsrl(MSR_IA32_XFD_ERR, 0); | |
10633 | ||
d7a08882 SC |
10634 | /* |
10635 | * Consume any pending interrupts, including the possible source of | |
10636 | * VM-Exit on SVM and any ticks that occur between VM-Exit and now. | |
10637 | * An instruction is required after local_irq_enable() to fully unblock | |
10638 | * interrupts on processors that implement an interrupt shadow, the | |
10639 | * stat.exits increment will do nicely. | |
10640 | */ | |
db215756 | 10641 | kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ); |
d7a08882 | 10642 | local_irq_enable(); |
b6c7a5dc | 10643 | ++vcpu->stat.exits; |
d7a08882 SC |
10644 | local_irq_disable(); |
10645 | kvm_after_interrupt(vcpu); | |
b6c7a5dc | 10646 | |
16045714 WL |
10647 | /* |
10648 | * Wait until after servicing IRQs to account guest time so that any | |
10649 | * ticks that occurred while running the guest are properly accounted | |
10650 | * to the guest. Waiting until IRQs are enabled degrades the accuracy | |
10651 | * of accounting via context tracking, but the loss of accuracy is | |
10652 | * acceptable for all known use cases. | |
10653 | */ | |
b2d2af7e | 10654 | guest_timing_exit_irqoff(); |
16045714 | 10655 | |
f2485b3e | 10656 | local_irq_enable(); |
b6c7a5dc HB |
10657 | preempt_enable(); |
10658 | ||
2031f287 | 10659 | kvm_vcpu_srcu_read_lock(vcpu); |
3200f405 | 10660 | |
b6c7a5dc HB |
10661 | /* |
10662 | * Profile KVM exit RIPs: | |
10663 | */ | |
10664 | if (unlikely(prof_on == KVM_PROFILING)) { | |
5fdbf976 MT |
10665 | unsigned long rip = kvm_rip_read(vcpu); |
10666 | profile_hit(KVM_PROFILING, (void *)rip); | |
b6c7a5dc HB |
10667 | } |
10668 | ||
cc578287 ZA |
10669 | if (unlikely(vcpu->arch.tsc_always_catchup)) |
10670 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); | |
298101da | 10671 | |
5cfb1d5a MT |
10672 | if (vcpu->arch.apic_attention) |
10673 | kvm_lapic_sync_from_vapic(vcpu); | |
b93463aa | 10674 | |
b3646477 | 10675 | r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath); |
d905c069 MT |
10676 | return r; |
10677 | ||
10678 | cancel_injection: | |
8081ad06 SC |
10679 | if (req_immediate_exit) |
10680 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
b3646477 | 10681 | static_call(kvm_x86_cancel_injection)(vcpu); |
ae7a2a3f MT |
10682 | if (unlikely(vcpu->arch.apic_attention)) |
10683 | kvm_lapic_sync_from_vapic(vcpu); | |
d7690175 MT |
10684 | out: |
10685 | return r; | |
10686 | } | |
b6c7a5dc | 10687 | |
8d25b7be | 10688 | /* Called within kvm->srcu read side. */ |
2031f287 | 10689 | static inline int vcpu_block(struct kvm_vcpu *vcpu) |
362c698f | 10690 | { |
98c25ead SC |
10691 | bool hv_timer; |
10692 | ||
c3e8abf0 | 10693 | if (!kvm_arch_vcpu_runnable(vcpu)) { |
98c25ead SC |
10694 | /* |
10695 | * Switch to the software timer before halt-polling/blocking as | |
10696 | * the guest's timer may be a break event for the vCPU, and the | |
10697 | * hypervisor timer runs only when the CPU is in guest mode. | |
10698 | * Switch before halt-polling so that KVM recognizes an expired | |
10699 | * timer before blocking. | |
10700 | */ | |
10701 | hv_timer = kvm_lapic_hv_timer_in_use(vcpu); | |
10702 | if (hv_timer) | |
10703 | kvm_lapic_switch_to_sw_timer(vcpu); | |
10704 | ||
2031f287 | 10705 | kvm_vcpu_srcu_read_unlock(vcpu); |
cdafece4 SC |
10706 | if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED) |
10707 | kvm_vcpu_halt(vcpu); | |
10708 | else | |
10709 | kvm_vcpu_block(vcpu); | |
2031f287 | 10710 | kvm_vcpu_srcu_read_lock(vcpu); |
bf9f6ac8 | 10711 | |
98c25ead SC |
10712 | if (hv_timer) |
10713 | kvm_lapic_switch_to_hv_timer(vcpu); | |
10714 | ||
9c8fd1ba PB |
10715 | if (!kvm_check_request(KVM_REQ_UNHALT, vcpu)) |
10716 | return 1; | |
10717 | } | |
362c698f | 10718 | |
4fe09bcf JM |
10719 | if (kvm_apic_accept_events(vcpu) < 0) |
10720 | return 0; | |
362c698f PB |
10721 | switch(vcpu->arch.mp_state) { |
10722 | case KVM_MP_STATE_HALTED: | |
647daca2 | 10723 | case KVM_MP_STATE_AP_RESET_HOLD: |
362c698f PB |
10724 | vcpu->arch.pv.pv_unhalted = false; |
10725 | vcpu->arch.mp_state = | |
10726 | KVM_MP_STATE_RUNNABLE; | |
df561f66 | 10727 | fallthrough; |
362c698f PB |
10728 | case KVM_MP_STATE_RUNNABLE: |
10729 | vcpu->arch.apf.halted = false; | |
10730 | break; | |
10731 | case KVM_MP_STATE_INIT_RECEIVED: | |
10732 | break; | |
10733 | default: | |
10734 | return -EINTR; | |
362c698f PB |
10735 | } |
10736 | return 1; | |
10737 | } | |
09cec754 | 10738 | |
5d9bc648 PB |
10739 | static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu) |
10740 | { | |
56083bdf | 10741 | if (is_guest_mode(vcpu)) |
cb6a32c2 | 10742 | kvm_check_nested_events(vcpu); |
0ad3bed6 | 10743 | |
5d9bc648 PB |
10744 | return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE && |
10745 | !vcpu->arch.apf.halted); | |
10746 | } | |
10747 | ||
8d25b7be | 10748 | /* Called within kvm->srcu read side. */ |
362c698f | 10749 | static int vcpu_run(struct kvm_vcpu *vcpu) |
d7690175 MT |
10750 | { |
10751 | int r; | |
10752 | ||
c595ceee | 10753 | vcpu->arch.l1tf_flush_l1d = true; |
d7690175 | 10754 | |
362c698f | 10755 | for (;;) { |
6cd88243 PB |
10756 | /* |
10757 | * If another guest vCPU requests a PV TLB flush in the middle | |
10758 | * of instruction emulation, the rest of the emulation could | |
10759 | * use a stale page translation. Assume that any code after | |
10760 | * this point can start executing an instruction. | |
10761 | */ | |
10762 | vcpu->arch.at_instruction_boundary = false; | |
58f800d5 | 10763 | if (kvm_vcpu_running(vcpu)) { |
851ba692 | 10764 | r = vcpu_enter_guest(vcpu); |
bf9f6ac8 | 10765 | } else { |
2031f287 | 10766 | r = vcpu_block(vcpu); |
bf9f6ac8 FW |
10767 | } |
10768 | ||
09cec754 GN |
10769 | if (r <= 0) |
10770 | break; | |
10771 | ||
084071d5 | 10772 | kvm_clear_request(KVM_REQ_UNBLOCK, vcpu); |
7caf9571 DW |
10773 | if (kvm_xen_has_pending_events(vcpu)) |
10774 | kvm_xen_inject_pending_events(vcpu); | |
10775 | ||
09cec754 GN |
10776 | if (kvm_cpu_has_pending_timer(vcpu)) |
10777 | kvm_inject_pending_timer_irqs(vcpu); | |
10778 | ||
782d422b MG |
10779 | if (dm_request_for_irq_injection(vcpu) && |
10780 | kvm_vcpu_ready_for_interrupt_injection(vcpu)) { | |
4ca7dd8c PB |
10781 | r = 0; |
10782 | vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; | |
09cec754 | 10783 | ++vcpu->stat.request_irq_exits; |
362c698f | 10784 | break; |
09cec754 | 10785 | } |
af585b92 | 10786 | |
f3020b88 | 10787 | if (__xfer_to_guest_mode_work_pending()) { |
2031f287 | 10788 | kvm_vcpu_srcu_read_unlock(vcpu); |
72c3c0fe | 10789 | r = xfer_to_guest_mode_handle_work(vcpu); |
2031f287 | 10790 | kvm_vcpu_srcu_read_lock(vcpu); |
72c3c0fe TG |
10791 | if (r) |
10792 | return r; | |
d7690175 | 10793 | } |
b6c7a5dc HB |
10794 | } |
10795 | ||
b6c7a5dc HB |
10796 | return r; |
10797 | } | |
10798 | ||
716d51ab GN |
10799 | static inline int complete_emulated_io(struct kvm_vcpu *vcpu) |
10800 | { | |
2d089356 | 10801 | return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE); |
716d51ab GN |
10802 | } |
10803 | ||
10804 | static int complete_emulated_pio(struct kvm_vcpu *vcpu) | |
10805 | { | |
10806 | BUG_ON(!vcpu->arch.pio.count); | |
10807 | ||
10808 | return complete_emulated_io(vcpu); | |
10809 | } | |
10810 | ||
f78146b0 AK |
10811 | /* |
10812 | * Implements the following, as a state machine: | |
10813 | * | |
10814 | * read: | |
10815 | * for each fragment | |
87da7e66 XG |
10816 | * for each mmio piece in the fragment |
10817 | * write gpa, len | |
10818 | * exit | |
10819 | * copy data | |
f78146b0 AK |
10820 | * execute insn |
10821 | * | |
10822 | * write: | |
10823 | * for each fragment | |
87da7e66 XG |
10824 | * for each mmio piece in the fragment |
10825 | * write gpa, len | |
10826 | * copy data | |
10827 | * exit | |
f78146b0 | 10828 | */ |
716d51ab | 10829 | static int complete_emulated_mmio(struct kvm_vcpu *vcpu) |
5287f194 AK |
10830 | { |
10831 | struct kvm_run *run = vcpu->run; | |
f78146b0 | 10832 | struct kvm_mmio_fragment *frag; |
87da7e66 | 10833 | unsigned len; |
5287f194 | 10834 | |
716d51ab | 10835 | BUG_ON(!vcpu->mmio_needed); |
5287f194 | 10836 | |
716d51ab | 10837 | /* Complete previous fragment */ |
87da7e66 XG |
10838 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; |
10839 | len = min(8u, frag->len); | |
716d51ab | 10840 | if (!vcpu->mmio_is_write) |
87da7e66 XG |
10841 | memcpy(frag->data, run->mmio.data, len); |
10842 | ||
10843 | if (frag->len <= 8) { | |
10844 | /* Switch to the next fragment. */ | |
10845 | frag++; | |
10846 | vcpu->mmio_cur_fragment++; | |
10847 | } else { | |
10848 | /* Go forward to the next mmio piece. */ | |
10849 | frag->data += len; | |
10850 | frag->gpa += len; | |
10851 | frag->len -= len; | |
10852 | } | |
10853 | ||
a08d3b3b | 10854 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { |
716d51ab | 10855 | vcpu->mmio_needed = 0; |
0912c977 PB |
10856 | |
10857 | /* FIXME: return into emulator if single-stepping. */ | |
cef4dea0 | 10858 | if (vcpu->mmio_is_write) |
716d51ab GN |
10859 | return 1; |
10860 | vcpu->mmio_read_completed = 1; | |
10861 | return complete_emulated_io(vcpu); | |
10862 | } | |
87da7e66 | 10863 | |
716d51ab GN |
10864 | run->exit_reason = KVM_EXIT_MMIO; |
10865 | run->mmio.phys_addr = frag->gpa; | |
10866 | if (vcpu->mmio_is_write) | |
87da7e66 XG |
10867 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); |
10868 | run->mmio.len = min(8u, frag->len); | |
716d51ab GN |
10869 | run->mmio.is_write = vcpu->mmio_is_write; |
10870 | vcpu->arch.complete_userspace_io = complete_emulated_mmio; | |
10871 | return 0; | |
5287f194 AK |
10872 | } |
10873 | ||
822f312d SAS |
10874 | /* Swap (qemu) user FPU context for the guest FPU context. */ |
10875 | static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu) | |
10876 | { | |
e27bc044 | 10877 | /* Exclude PKRU, it's restored separately immediately after VM-Exit. */ |
d69c1382 | 10878 | fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true); |
822f312d SAS |
10879 | trace_kvm_fpu(1); |
10880 | } | |
10881 | ||
10882 | /* When vcpu_run ends, restore user space FPU context. */ | |
10883 | static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu) | |
10884 | { | |
d69c1382 | 10885 | fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false); |
822f312d SAS |
10886 | ++vcpu->stat.fpu_reload; |
10887 | trace_kvm_fpu(0); | |
10888 | } | |
10889 | ||
1b94f6f8 | 10890 | int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) |
b6c7a5dc | 10891 | { |
1b94f6f8 | 10892 | struct kvm_run *kvm_run = vcpu->run; |
b6c7a5dc | 10893 | int r; |
b6c7a5dc | 10894 | |
accb757d | 10895 | vcpu_load(vcpu); |
20b7035c | 10896 | kvm_sigset_activate(vcpu); |
15aad3be | 10897 | kvm_run->flags = 0; |
5663d8f9 PX |
10898 | kvm_load_guest_fpu(vcpu); |
10899 | ||
2031f287 | 10900 | kvm_vcpu_srcu_read_lock(vcpu); |
a4535290 | 10901 | if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) { |
2f173d26 JS |
10902 | if (kvm_run->immediate_exit) { |
10903 | r = -EINTR; | |
10904 | goto out; | |
10905 | } | |
98c25ead SC |
10906 | /* |
10907 | * It should be impossible for the hypervisor timer to be in | |
10908 | * use before KVM has ever run the vCPU. | |
10909 | */ | |
10910 | WARN_ON_ONCE(kvm_lapic_hv_timer_in_use(vcpu)); | |
8d25b7be | 10911 | |
2031f287 | 10912 | kvm_vcpu_srcu_read_unlock(vcpu); |
c91d4497 | 10913 | kvm_vcpu_block(vcpu); |
2031f287 | 10914 | kvm_vcpu_srcu_read_lock(vcpu); |
8d25b7be | 10915 | |
4fe09bcf JM |
10916 | if (kvm_apic_accept_events(vcpu) < 0) { |
10917 | r = 0; | |
10918 | goto out; | |
10919 | } | |
72875d8a | 10920 | kvm_clear_request(KVM_REQ_UNHALT, vcpu); |
ac9f6dc0 | 10921 | r = -EAGAIN; |
a0595000 JS |
10922 | if (signal_pending(current)) { |
10923 | r = -EINTR; | |
1b94f6f8 | 10924 | kvm_run->exit_reason = KVM_EXIT_INTR; |
a0595000 JS |
10925 | ++vcpu->stat.signal_exits; |
10926 | } | |
ac9f6dc0 | 10927 | goto out; |
b6c7a5dc HB |
10928 | } |
10929 | ||
e489a4a6 SC |
10930 | if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) || |
10931 | (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) { | |
01643c51 KH |
10932 | r = -EINVAL; |
10933 | goto out; | |
10934 | } | |
10935 | ||
1b94f6f8 | 10936 | if (kvm_run->kvm_dirty_regs) { |
01643c51 KH |
10937 | r = sync_regs(vcpu); |
10938 | if (r != 0) | |
10939 | goto out; | |
10940 | } | |
10941 | ||
b6c7a5dc | 10942 | /* re-sync apic's tpr */ |
35754c98 | 10943 | if (!lapic_in_kernel(vcpu)) { |
eea1cff9 AP |
10944 | if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) { |
10945 | r = -EINVAL; | |
10946 | goto out; | |
10947 | } | |
10948 | } | |
b6c7a5dc | 10949 | |
716d51ab GN |
10950 | if (unlikely(vcpu->arch.complete_userspace_io)) { |
10951 | int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io; | |
10952 | vcpu->arch.complete_userspace_io = NULL; | |
10953 | r = cui(vcpu); | |
10954 | if (r <= 0) | |
5663d8f9 | 10955 | goto out; |
0bc27326 SC |
10956 | } else { |
10957 | WARN_ON_ONCE(vcpu->arch.pio.count); | |
10958 | WARN_ON_ONCE(vcpu->mmio_needed); | |
10959 | } | |
5287f194 | 10960 | |
fc4fad79 | 10961 | if (kvm_run->immediate_exit) { |
460df4c1 | 10962 | r = -EINTR; |
fc4fad79 SC |
10963 | goto out; |
10964 | } | |
10965 | ||
10966 | r = static_call(kvm_x86_vcpu_pre_run)(vcpu); | |
10967 | if (r <= 0) | |
10968 | goto out; | |
10969 | ||
10970 | r = vcpu_run(vcpu); | |
b6c7a5dc HB |
10971 | |
10972 | out: | |
5663d8f9 | 10973 | kvm_put_guest_fpu(vcpu); |
1b94f6f8 | 10974 | if (kvm_run->kvm_valid_regs) |
01643c51 | 10975 | store_regs(vcpu); |
f1d86e46 | 10976 | post_kvm_run_save(vcpu); |
2031f287 | 10977 | kvm_vcpu_srcu_read_unlock(vcpu); |
b6c7a5dc | 10978 | |
8d25b7be | 10979 | kvm_sigset_deactivate(vcpu); |
accb757d | 10980 | vcpu_put(vcpu); |
b6c7a5dc HB |
10981 | return r; |
10982 | } | |
10983 | ||
01643c51 | 10984 | static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 10985 | { |
7ae441ea GN |
10986 | if (vcpu->arch.emulate_regs_need_sync_to_vcpu) { |
10987 | /* | |
10988 | * We are here if userspace calls get_regs() in the middle of | |
10989 | * instruction emulation. Registers state needs to be copied | |
4a969980 | 10990 | * back from emulation context to vcpu. Userspace shouldn't do |
7ae441ea GN |
10991 | * that usually, but some bad designed PV devices (vmware |
10992 | * backdoor interface) need this to work | |
10993 | */ | |
c9b8b07c | 10994 | emulator_writeback_register_cache(vcpu->arch.emulate_ctxt); |
7ae441ea GN |
10995 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; |
10996 | } | |
de3cd117 SC |
10997 | regs->rax = kvm_rax_read(vcpu); |
10998 | regs->rbx = kvm_rbx_read(vcpu); | |
10999 | regs->rcx = kvm_rcx_read(vcpu); | |
11000 | regs->rdx = kvm_rdx_read(vcpu); | |
11001 | regs->rsi = kvm_rsi_read(vcpu); | |
11002 | regs->rdi = kvm_rdi_read(vcpu); | |
e9c16c78 | 11003 | regs->rsp = kvm_rsp_read(vcpu); |
de3cd117 | 11004 | regs->rbp = kvm_rbp_read(vcpu); |
b6c7a5dc | 11005 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
11006 | regs->r8 = kvm_r8_read(vcpu); |
11007 | regs->r9 = kvm_r9_read(vcpu); | |
11008 | regs->r10 = kvm_r10_read(vcpu); | |
11009 | regs->r11 = kvm_r11_read(vcpu); | |
11010 | regs->r12 = kvm_r12_read(vcpu); | |
11011 | regs->r13 = kvm_r13_read(vcpu); | |
11012 | regs->r14 = kvm_r14_read(vcpu); | |
11013 | regs->r15 = kvm_r15_read(vcpu); | |
b6c7a5dc HB |
11014 | #endif |
11015 | ||
5fdbf976 | 11016 | regs->rip = kvm_rip_read(vcpu); |
91586a3b | 11017 | regs->rflags = kvm_get_rflags(vcpu); |
01643c51 | 11018 | } |
b6c7a5dc | 11019 | |
01643c51 KH |
11020 | int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
11021 | { | |
11022 | vcpu_load(vcpu); | |
11023 | __get_regs(vcpu, regs); | |
1fc9b76b | 11024 | vcpu_put(vcpu); |
b6c7a5dc HB |
11025 | return 0; |
11026 | } | |
11027 | ||
01643c51 | 11028 | static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
b6c7a5dc | 11029 | { |
7ae441ea GN |
11030 | vcpu->arch.emulate_regs_need_sync_from_vcpu = true; |
11031 | vcpu->arch.emulate_regs_need_sync_to_vcpu = false; | |
11032 | ||
de3cd117 SC |
11033 | kvm_rax_write(vcpu, regs->rax); |
11034 | kvm_rbx_write(vcpu, regs->rbx); | |
11035 | kvm_rcx_write(vcpu, regs->rcx); | |
11036 | kvm_rdx_write(vcpu, regs->rdx); | |
11037 | kvm_rsi_write(vcpu, regs->rsi); | |
11038 | kvm_rdi_write(vcpu, regs->rdi); | |
e9c16c78 | 11039 | kvm_rsp_write(vcpu, regs->rsp); |
de3cd117 | 11040 | kvm_rbp_write(vcpu, regs->rbp); |
b6c7a5dc | 11041 | #ifdef CONFIG_X86_64 |
de3cd117 SC |
11042 | kvm_r8_write(vcpu, regs->r8); |
11043 | kvm_r9_write(vcpu, regs->r9); | |
11044 | kvm_r10_write(vcpu, regs->r10); | |
11045 | kvm_r11_write(vcpu, regs->r11); | |
11046 | kvm_r12_write(vcpu, regs->r12); | |
11047 | kvm_r13_write(vcpu, regs->r13); | |
11048 | kvm_r14_write(vcpu, regs->r14); | |
11049 | kvm_r15_write(vcpu, regs->r15); | |
b6c7a5dc HB |
11050 | #endif |
11051 | ||
5fdbf976 | 11052 | kvm_rip_write(vcpu, regs->rip); |
d73235d1 | 11053 | kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED); |
b6c7a5dc | 11054 | |
b4f14abd JK |
11055 | vcpu->arch.exception.pending = false; |
11056 | ||
3842d135 | 11057 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
01643c51 | 11058 | } |
3842d135 | 11059 | |
01643c51 KH |
11060 | int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) |
11061 | { | |
11062 | vcpu_load(vcpu); | |
11063 | __set_regs(vcpu, regs); | |
875656fe | 11064 | vcpu_put(vcpu); |
b6c7a5dc HB |
11065 | return 0; |
11066 | } | |
11067 | ||
6dba9403 | 11068 | static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
b6c7a5dc | 11069 | { |
89a27f4d | 11070 | struct desc_ptr dt; |
b6c7a5dc | 11071 | |
5265713a TL |
11072 | if (vcpu->arch.guest_state_protected) |
11073 | goto skip_protected_regs; | |
11074 | ||
3e6e0aab GT |
11075 | kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
11076 | kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
11077 | kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
11078 | kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
11079 | kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
11080 | kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 11081 | |
3e6e0aab GT |
11082 | kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
11083 | kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 11084 | |
b3646477 | 11085 | static_call(kvm_x86_get_idt)(vcpu, &dt); |
89a27f4d GN |
11086 | sregs->idt.limit = dt.size; |
11087 | sregs->idt.base = dt.address; | |
b3646477 | 11088 | static_call(kvm_x86_get_gdt)(vcpu, &dt); |
89a27f4d GN |
11089 | sregs->gdt.limit = dt.size; |
11090 | sregs->gdt.base = dt.address; | |
b6c7a5dc | 11091 | |
ad312c7c | 11092 | sregs->cr2 = vcpu->arch.cr2; |
9f8fe504 | 11093 | sregs->cr3 = kvm_read_cr3(vcpu); |
5265713a TL |
11094 | |
11095 | skip_protected_regs: | |
11096 | sregs->cr0 = kvm_read_cr0(vcpu); | |
fc78f519 | 11097 | sregs->cr4 = kvm_read_cr4(vcpu); |
2d3ad1f4 | 11098 | sregs->cr8 = kvm_get_cr8(vcpu); |
f6801dff | 11099 | sregs->efer = vcpu->arch.efer; |
b6c7a5dc | 11100 | sregs->apic_base = kvm_get_apic_base(vcpu); |
6dba9403 | 11101 | } |
b6c7a5dc | 11102 | |
6dba9403 ML |
11103 | static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
11104 | { | |
11105 | __get_sregs_common(vcpu, sregs); | |
11106 | ||
11107 | if (vcpu->arch.guest_state_protected) | |
11108 | return; | |
b6c7a5dc | 11109 | |
04140b41 | 11110 | if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft) |
14d0bc1f GN |
11111 | set_bit(vcpu->arch.interrupt.nr, |
11112 | (unsigned long *)sregs->interrupt_bitmap); | |
01643c51 | 11113 | } |
16d7a191 | 11114 | |
6dba9403 ML |
11115 | static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
11116 | { | |
11117 | int i; | |
11118 | ||
11119 | __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2); | |
11120 | ||
11121 | if (vcpu->arch.guest_state_protected) | |
11122 | return; | |
11123 | ||
11124 | if (is_pae_paging(vcpu)) { | |
11125 | for (i = 0 ; i < 4 ; i++) | |
11126 | sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i); | |
11127 | sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
11128 | } | |
11129 | } | |
11130 | ||
01643c51 KH |
11131 | int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, |
11132 | struct kvm_sregs *sregs) | |
11133 | { | |
11134 | vcpu_load(vcpu); | |
11135 | __get_sregs(vcpu, sregs); | |
bcdec41c | 11136 | vcpu_put(vcpu); |
b6c7a5dc HB |
11137 | return 0; |
11138 | } | |
11139 | ||
62d9f0db MT |
11140 | int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, |
11141 | struct kvm_mp_state *mp_state) | |
11142 | { | |
4fe09bcf JM |
11143 | int r; |
11144 | ||
fd232561 | 11145 | vcpu_load(vcpu); |
f958bd23 SC |
11146 | if (kvm_mpx_supported()) |
11147 | kvm_load_guest_fpu(vcpu); | |
fd232561 | 11148 | |
4fe09bcf JM |
11149 | r = kvm_apic_accept_events(vcpu); |
11150 | if (r < 0) | |
11151 | goto out; | |
11152 | r = 0; | |
11153 | ||
647daca2 TL |
11154 | if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED || |
11155 | vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) && | |
11156 | vcpu->arch.pv.pv_unhalted) | |
6aef266c SV |
11157 | mp_state->mp_state = KVM_MP_STATE_RUNNABLE; |
11158 | else | |
11159 | mp_state->mp_state = vcpu->arch.mp_state; | |
11160 | ||
4fe09bcf | 11161 | out: |
f958bd23 SC |
11162 | if (kvm_mpx_supported()) |
11163 | kvm_put_guest_fpu(vcpu); | |
fd232561 | 11164 | vcpu_put(vcpu); |
4fe09bcf | 11165 | return r; |
62d9f0db MT |
11166 | } |
11167 | ||
11168 | int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, | |
11169 | struct kvm_mp_state *mp_state) | |
11170 | { | |
e83dff5e CD |
11171 | int ret = -EINVAL; |
11172 | ||
11173 | vcpu_load(vcpu); | |
11174 | ||
bce87cce | 11175 | if (!lapic_in_kernel(vcpu) && |
66450a21 | 11176 | mp_state->mp_state != KVM_MP_STATE_RUNNABLE) |
e83dff5e | 11177 | goto out; |
66450a21 | 11178 | |
27cbe7d6 LA |
11179 | /* |
11180 | * KVM_MP_STATE_INIT_RECEIVED means the processor is in | |
11181 | * INIT state; latched init should be reported using | |
11182 | * KVM_SET_VCPU_EVENTS, so reject it here. | |
11183 | */ | |
11184 | if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) && | |
28bf2888 DH |
11185 | (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED || |
11186 | mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED)) | |
e83dff5e | 11187 | goto out; |
28bf2888 | 11188 | |
66450a21 JK |
11189 | if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { |
11190 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
11191 | set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events); | |
11192 | } else | |
11193 | vcpu->arch.mp_state = mp_state->mp_state; | |
3842d135 | 11194 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
e83dff5e CD |
11195 | |
11196 | ret = 0; | |
11197 | out: | |
11198 | vcpu_put(vcpu); | |
11199 | return ret; | |
62d9f0db MT |
11200 | } |
11201 | ||
7f3d35fd KW |
11202 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
11203 | int reason, bool has_error_code, u32 error_code) | |
b6c7a5dc | 11204 | { |
c9b8b07c | 11205 | struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt; |
8ec4722d | 11206 | int ret; |
e01c2426 | 11207 | |
8ec4722d | 11208 | init_emulate_ctxt(vcpu); |
c697518a | 11209 | |
7f3d35fd | 11210 | ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason, |
9d74191a | 11211 | has_error_code, error_code); |
1051778f SC |
11212 | if (ret) { |
11213 | vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; | |
11214 | vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION; | |
11215 | vcpu->run->internal.ndata = 0; | |
60fc3d02 | 11216 | return 0; |
1051778f | 11217 | } |
37817f29 | 11218 | |
9d74191a TY |
11219 | kvm_rip_write(vcpu, ctxt->eip); |
11220 | kvm_set_rflags(vcpu, ctxt->eflags); | |
60fc3d02 | 11221 | return 1; |
37817f29 IE |
11222 | } |
11223 | EXPORT_SYMBOL_GPL(kvm_task_switch); | |
11224 | ||
ee69c92b | 11225 | static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) |
f2981033 | 11226 | { |
37b95951 | 11227 | if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) { |
f2981033 LT |
11228 | /* |
11229 | * When EFER.LME and CR0.PG are set, the processor is in | |
11230 | * 64-bit mode (though maybe in a 32-bit code segment). | |
11231 | * CR4.PAE and EFER.LMA must be set. | |
11232 | */ | |
ee69c92b SC |
11233 | if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA)) |
11234 | return false; | |
ca29e145 | 11235 | if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3)) |
c1c35cf7 | 11236 | return false; |
f2981033 LT |
11237 | } else { |
11238 | /* | |
11239 | * Not in 64-bit mode: EFER.LMA is clear and the code | |
11240 | * segment cannot be 64-bit. | |
11241 | */ | |
11242 | if (sregs->efer & EFER_LMA || sregs->cs.l) | |
ee69c92b | 11243 | return false; |
f2981033 LT |
11244 | } |
11245 | ||
ee69c92b | 11246 | return kvm_is_valid_cr4(vcpu, sregs->cr4); |
f2981033 LT |
11247 | } |
11248 | ||
6dba9403 ML |
11249 | static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs, |
11250 | int *mmu_reset_needed, bool update_pdptrs) | |
b6c7a5dc | 11251 | { |
58cb628d | 11252 | struct msr_data apic_base_msr; |
6dba9403 | 11253 | int idx; |
89a27f4d | 11254 | struct desc_ptr dt; |
b4ef9d4e | 11255 | |
ee69c92b | 11256 | if (!kvm_is_valid_sregs(vcpu, sregs)) |
6dba9403 | 11257 | return -EINVAL; |
f2981033 | 11258 | |
d3802286 JM |
11259 | apic_base_msr.data = sregs->apic_base; |
11260 | apic_base_msr.host_initiated = true; | |
11261 | if (kvm_set_apic_base(vcpu, &apic_base_msr)) | |
6dba9403 | 11262 | return -EINVAL; |
6d1068b3 | 11263 | |
5265713a | 11264 | if (vcpu->arch.guest_state_protected) |
6dba9403 | 11265 | return 0; |
5265713a | 11266 | |
89a27f4d GN |
11267 | dt.size = sregs->idt.limit; |
11268 | dt.address = sregs->idt.base; | |
b3646477 | 11269 | static_call(kvm_x86_set_idt)(vcpu, &dt); |
89a27f4d GN |
11270 | dt.size = sregs->gdt.limit; |
11271 | dt.address = sregs->gdt.base; | |
b3646477 | 11272 | static_call(kvm_x86_set_gdt)(vcpu, &dt); |
b6c7a5dc | 11273 | |
ad312c7c | 11274 | vcpu->arch.cr2 = sregs->cr2; |
6dba9403 | 11275 | *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3; |
dc7e795e | 11276 | vcpu->arch.cr3 = sregs->cr3; |
3883bc9d | 11277 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); |
405329fc | 11278 | static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3); |
b6c7a5dc | 11279 | |
2d3ad1f4 | 11280 | kvm_set_cr8(vcpu, sregs->cr8); |
b6c7a5dc | 11281 | |
6dba9403 | 11282 | *mmu_reset_needed |= vcpu->arch.efer != sregs->efer; |
b3646477 | 11283 | static_call(kvm_x86_set_efer)(vcpu, sregs->efer); |
b6c7a5dc | 11284 | |
6dba9403 | 11285 | *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0; |
b3646477 | 11286 | static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0); |
d7306163 | 11287 | vcpu->arch.cr0 = sregs->cr0; |
b6c7a5dc | 11288 | |
6dba9403 | 11289 | *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4; |
b3646477 | 11290 | static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4); |
63f42e02 | 11291 | |
6dba9403 ML |
11292 | if (update_pdptrs) { |
11293 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
11294 | if (is_pae_paging(vcpu)) { | |
2df4a5eb | 11295 | load_pdptrs(vcpu, kvm_read_cr3(vcpu)); |
6dba9403 ML |
11296 | *mmu_reset_needed = 1; |
11297 | } | |
11298 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
7c93be44 | 11299 | } |
b6c7a5dc | 11300 | |
3e6e0aab GT |
11301 | kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS); |
11302 | kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS); | |
11303 | kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES); | |
11304 | kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS); | |
11305 | kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS); | |
11306 | kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS); | |
b6c7a5dc | 11307 | |
3e6e0aab GT |
11308 | kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR); |
11309 | kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR); | |
b6c7a5dc | 11310 | |
5f0269f5 ME |
11311 | update_cr8_intercept(vcpu); |
11312 | ||
9c3e4aab | 11313 | /* Older userspace won't unhalt the vcpu on reset. */ |
c5af89b6 | 11314 | if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 && |
9c3e4aab | 11315 | sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 && |
3eeb3288 | 11316 | !is_protmode(vcpu)) |
9c3e4aab MT |
11317 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
11318 | ||
6dba9403 ML |
11319 | return 0; |
11320 | } | |
11321 | ||
11322 | static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) | |
11323 | { | |
11324 | int pending_vec, max_bits; | |
11325 | int mmu_reset_needed = 0; | |
11326 | int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true); | |
11327 | ||
11328 | if (ret) | |
11329 | return ret; | |
11330 | ||
11331 | if (mmu_reset_needed) | |
11332 | kvm_mmu_reset_context(vcpu); | |
11333 | ||
5265713a TL |
11334 | max_bits = KVM_NR_INTERRUPTS; |
11335 | pending_vec = find_first_bit( | |
11336 | (const unsigned long *)sregs->interrupt_bitmap, max_bits); | |
6dba9403 | 11337 | |
5265713a TL |
11338 | if (pending_vec < max_bits) { |
11339 | kvm_queue_interrupt(vcpu, pending_vec, false); | |
11340 | pr_debug("Set back pending irq %d\n", pending_vec); | |
6dba9403 | 11341 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
5265713a | 11342 | } |
6dba9403 ML |
11343 | return 0; |
11344 | } | |
5265713a | 11345 | |
6dba9403 ML |
11346 | static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2) |
11347 | { | |
11348 | int mmu_reset_needed = 0; | |
11349 | bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
11350 | bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) && | |
11351 | !(sregs2->efer & EFER_LMA); | |
11352 | int i, ret; | |
3842d135 | 11353 | |
6dba9403 ML |
11354 | if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID) |
11355 | return -EINVAL; | |
11356 | ||
11357 | if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected)) | |
11358 | return -EINVAL; | |
11359 | ||
11360 | ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2, | |
11361 | &mmu_reset_needed, !valid_pdptrs); | |
11362 | if (ret) | |
11363 | return ret; | |
11364 | ||
11365 | if (valid_pdptrs) { | |
11366 | for (i = 0; i < 4 ; i++) | |
11367 | kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]); | |
11368 | ||
11369 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); | |
11370 | mmu_reset_needed = 1; | |
158a48ec | 11371 | vcpu->arch.pdptrs_from_userspace = true; |
6dba9403 ML |
11372 | } |
11373 | if (mmu_reset_needed) | |
11374 | kvm_mmu_reset_context(vcpu); | |
11375 | return 0; | |
01643c51 KH |
11376 | } |
11377 | ||
11378 | int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, | |
11379 | struct kvm_sregs *sregs) | |
11380 | { | |
11381 | int ret; | |
11382 | ||
11383 | vcpu_load(vcpu); | |
11384 | ret = __set_sregs(vcpu, sregs); | |
b4ef9d4e CD |
11385 | vcpu_put(vcpu); |
11386 | return ret; | |
b6c7a5dc HB |
11387 | } |
11388 | ||
cae72dcc ML |
11389 | static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm) |
11390 | { | |
320af55a | 11391 | bool set = false; |
cae72dcc | 11392 | struct kvm_vcpu *vcpu; |
46808a4c | 11393 | unsigned long i; |
cae72dcc | 11394 | |
0047fb33 SC |
11395 | if (!enable_apicv) |
11396 | return; | |
11397 | ||
cae72dcc ML |
11398 | down_write(&kvm->arch.apicv_update_lock); |
11399 | ||
11400 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
11401 | if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) { | |
320af55a | 11402 | set = true; |
cae72dcc ML |
11403 | break; |
11404 | } | |
11405 | } | |
320af55a | 11406 | __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set); |
cae72dcc ML |
11407 | up_write(&kvm->arch.apicv_update_lock); |
11408 | } | |
11409 | ||
d0bfb940 JK |
11410 | int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, |
11411 | struct kvm_guest_debug *dbg) | |
b6c7a5dc | 11412 | { |
355be0b9 | 11413 | unsigned long rflags; |
ae675ef0 | 11414 | int i, r; |
b6c7a5dc | 11415 | |
8d4846b9 TL |
11416 | if (vcpu->arch.guest_state_protected) |
11417 | return -EINVAL; | |
11418 | ||
66b56562 CD |
11419 | vcpu_load(vcpu); |
11420 | ||
4f926bf2 JK |
11421 | if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) { |
11422 | r = -EBUSY; | |
11423 | if (vcpu->arch.exception.pending) | |
2122ff5e | 11424 | goto out; |
4f926bf2 JK |
11425 | if (dbg->control & KVM_GUESTDBG_INJECT_DB) |
11426 | kvm_queue_exception(vcpu, DB_VECTOR); | |
11427 | else | |
11428 | kvm_queue_exception(vcpu, BP_VECTOR); | |
11429 | } | |
11430 | ||
91586a3b JK |
11431 | /* |
11432 | * Read rflags as long as potentially injected trace flags are still | |
11433 | * filtered out. | |
11434 | */ | |
11435 | rflags = kvm_get_rflags(vcpu); | |
355be0b9 JK |
11436 | |
11437 | vcpu->guest_debug = dbg->control; | |
11438 | if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE)) | |
11439 | vcpu->guest_debug = 0; | |
11440 | ||
11441 | if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { | |
ae675ef0 JK |
11442 | for (i = 0; i < KVM_NR_DB_REGS; ++i) |
11443 | vcpu->arch.eff_db[i] = dbg->arch.debugreg[i]; | |
c8639010 | 11444 | vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7]; |
ae675ef0 JK |
11445 | } else { |
11446 | for (i = 0; i < KVM_NR_DB_REGS; i++) | |
11447 | vcpu->arch.eff_db[i] = vcpu->arch.db[i]; | |
ae675ef0 | 11448 | } |
c8639010 | 11449 | kvm_update_dr7(vcpu); |
ae675ef0 | 11450 | |
f92653ee | 11451 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
e87e46d5 | 11452 | vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu); |
94fe45da | 11453 | |
91586a3b JK |
11454 | /* |
11455 | * Trigger an rflags update that will inject or remove the trace | |
11456 | * flags. | |
11457 | */ | |
11458 | kvm_set_rflags(vcpu, rflags); | |
b6c7a5dc | 11459 | |
b3646477 | 11460 | static_call(kvm_x86_update_exception_bitmap)(vcpu); |
b6c7a5dc | 11461 | |
cae72dcc ML |
11462 | kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm); |
11463 | ||
4f926bf2 | 11464 | r = 0; |
d0bfb940 | 11465 | |
2122ff5e | 11466 | out: |
66b56562 | 11467 | vcpu_put(vcpu); |
b6c7a5dc HB |
11468 | return r; |
11469 | } | |
11470 | ||
8b006791 ZX |
11471 | /* |
11472 | * Translate a guest virtual address to a guest physical address. | |
11473 | */ | |
11474 | int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, | |
11475 | struct kvm_translation *tr) | |
11476 | { | |
11477 | unsigned long vaddr = tr->linear_address; | |
11478 | gpa_t gpa; | |
f656ce01 | 11479 | int idx; |
8b006791 | 11480 | |
1da5b61d CD |
11481 | vcpu_load(vcpu); |
11482 | ||
f656ce01 | 11483 | idx = srcu_read_lock(&vcpu->kvm->srcu); |
1871c602 | 11484 | gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL); |
f656ce01 | 11485 | srcu_read_unlock(&vcpu->kvm->srcu, idx); |
8b006791 | 11486 | tr->physical_address = gpa; |
6e1d2a3f | 11487 | tr->valid = gpa != INVALID_GPA; |
8b006791 ZX |
11488 | tr->writeable = 1; |
11489 | tr->usermode = 0; | |
8b006791 | 11490 | |
1da5b61d | 11491 | vcpu_put(vcpu); |
8b006791 ZX |
11492 | return 0; |
11493 | } | |
11494 | ||
d0752060 HB |
11495 | int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) |
11496 | { | |
1393123e | 11497 | struct fxregs_state *fxsave; |
d0752060 | 11498 | |
d69c1382 | 11499 | if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) |
ed02b213 TL |
11500 | return 0; |
11501 | ||
1393123e | 11502 | vcpu_load(vcpu); |
d0752060 | 11503 | |
d69c1382 | 11504 | fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; |
d0752060 HB |
11505 | memcpy(fpu->fpr, fxsave->st_space, 128); |
11506 | fpu->fcw = fxsave->cwd; | |
11507 | fpu->fsw = fxsave->swd; | |
11508 | fpu->ftwx = fxsave->twd; | |
11509 | fpu->last_opcode = fxsave->fop; | |
11510 | fpu->last_ip = fxsave->rip; | |
11511 | fpu->last_dp = fxsave->rdp; | |
0e96f31e | 11512 | memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space)); |
d0752060 | 11513 | |
1393123e | 11514 | vcpu_put(vcpu); |
d0752060 HB |
11515 | return 0; |
11516 | } | |
11517 | ||
11518 | int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) | |
11519 | { | |
6a96bc7f CD |
11520 | struct fxregs_state *fxsave; |
11521 | ||
d69c1382 | 11522 | if (fpstate_is_confidential(&vcpu->arch.guest_fpu)) |
ed02b213 TL |
11523 | return 0; |
11524 | ||
6a96bc7f CD |
11525 | vcpu_load(vcpu); |
11526 | ||
d69c1382 | 11527 | fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave; |
d0752060 | 11528 | |
d0752060 HB |
11529 | memcpy(fxsave->st_space, fpu->fpr, 128); |
11530 | fxsave->cwd = fpu->fcw; | |
11531 | fxsave->swd = fpu->fsw; | |
11532 | fxsave->twd = fpu->ftwx; | |
11533 | fxsave->fop = fpu->last_opcode; | |
11534 | fxsave->rip = fpu->last_ip; | |
11535 | fxsave->rdp = fpu->last_dp; | |
0e96f31e | 11536 | memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space)); |
d0752060 | 11537 | |
6a96bc7f | 11538 | vcpu_put(vcpu); |
d0752060 HB |
11539 | return 0; |
11540 | } | |
11541 | ||
01643c51 KH |
11542 | static void store_regs(struct kvm_vcpu *vcpu) |
11543 | { | |
11544 | BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES); | |
11545 | ||
11546 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS) | |
11547 | __get_regs(vcpu, &vcpu->run->s.regs.regs); | |
11548 | ||
11549 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS) | |
11550 | __get_sregs(vcpu, &vcpu->run->s.regs.sregs); | |
11551 | ||
11552 | if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS) | |
11553 | kvm_vcpu_ioctl_x86_get_vcpu_events( | |
11554 | vcpu, &vcpu->run->s.regs.events); | |
11555 | } | |
11556 | ||
11557 | static int sync_regs(struct kvm_vcpu *vcpu) | |
11558 | { | |
01643c51 KH |
11559 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) { |
11560 | __set_regs(vcpu, &vcpu->run->s.regs.regs); | |
11561 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS; | |
11562 | } | |
11563 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) { | |
11564 | if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs)) | |
11565 | return -EINVAL; | |
11566 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS; | |
11567 | } | |
11568 | if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) { | |
11569 | if (kvm_vcpu_ioctl_x86_set_vcpu_events( | |
11570 | vcpu, &vcpu->run->s.regs.events)) | |
11571 | return -EINVAL; | |
11572 | vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS; | |
11573 | } | |
11574 | ||
11575 | return 0; | |
11576 | } | |
11577 | ||
897cc38e | 11578 | int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) |
e9b11c17 | 11579 | { |
1d5e740d | 11580 | if (kvm_check_tsc_unstable() && kvm->created_vcpus) |
897cc38e SC |
11581 | pr_warn_once("kvm: SMP vm created on host with unstable TSC; " |
11582 | "guest TSC will not be reliable\n"); | |
7f1ea208 | 11583 | |
35875316 ZG |
11584 | if (!kvm->arch.max_vcpu_ids) |
11585 | kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS; | |
11586 | ||
11587 | if (id >= kvm->arch.max_vcpu_ids) | |
11588 | return -EINVAL; | |
11589 | ||
d588bb9b | 11590 | return static_call(kvm_x86_vcpu_precreate)(kvm); |
e9b11c17 ZX |
11591 | } |
11592 | ||
e529ef66 | 11593 | int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) |
e9b11c17 | 11594 | { |
95a0d01e SC |
11595 | struct page *page; |
11596 | int r; | |
c447e76b | 11597 | |
63f5a190 | 11598 | vcpu->arch.last_vmentry_cpu = -1; |
7117003f SC |
11599 | vcpu->arch.regs_avail = ~0; |
11600 | vcpu->arch.regs_dirty = ~0; | |
63f5a190 | 11601 | |
95a0d01e SC |
11602 | if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu)) |
11603 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
11604 | else | |
11605 | vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED; | |
c447e76b | 11606 | |
95a0d01e SC |
11607 | r = kvm_mmu_create(vcpu); |
11608 | if (r < 0) | |
11609 | return r; | |
11610 | ||
11611 | if (irqchip_in_kernel(vcpu->kvm)) { | |
95a0d01e SC |
11612 | r = kvm_create_lapic(vcpu, lapic_timer_advance_ns); |
11613 | if (r < 0) | |
11614 | goto fail_mmu_destroy; | |
423ecfea SC |
11615 | |
11616 | /* | |
11617 | * Defer evaluating inhibits until the vCPU is first run, as | |
11618 | * this vCPU will not get notified of any changes until this | |
11619 | * vCPU is visible to other vCPUs (marked online and added to | |
11620 | * the set of vCPUs). Opportunistically mark APICv active as | |
11621 | * VMX in particularly is highly unlikely to have inhibits. | |
11622 | * Ignore the current per-VM APICv state so that vCPU creation | |
11623 | * is guaranteed to run with a deterministic value, the request | |
11624 | * will ensure the vCPU gets the correct state before VM-Entry. | |
11625 | */ | |
11626 | if (enable_apicv) { | |
ce0a58f4 | 11627 | vcpu->arch.apic->apicv_active = true; |
423ecfea SC |
11628 | kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu); |
11629 | } | |
95a0d01e | 11630 | } else |
6e4e3b4d | 11631 | static_branch_inc(&kvm_has_noapic_vcpu); |
95a0d01e SC |
11632 | |
11633 | r = -ENOMEM; | |
11634 | ||
93bb59ca | 11635 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); |
95a0d01e SC |
11636 | if (!page) |
11637 | goto fail_free_lapic; | |
11638 | vcpu->arch.pio_data = page_address(page); | |
11639 | ||
087acc4e | 11640 | vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64), |
95a0d01e | 11641 | GFP_KERNEL_ACCOUNT); |
281b5278 JW |
11642 | vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64), |
11643 | GFP_KERNEL_ACCOUNT); | |
11644 | if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks) | |
95a0d01e SC |
11645 | goto fail_free_pio_data; |
11646 | vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS; | |
11647 | ||
11648 | if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, | |
11649 | GFP_KERNEL_ACCOUNT)) | |
11650 | goto fail_free_mce_banks; | |
11651 | ||
c9b8b07c SC |
11652 | if (!alloc_emulate_ctxt(vcpu)) |
11653 | goto free_wbinvd_dirty_mask; | |
11654 | ||
d69c1382 | 11655 | if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) { |
95a0d01e | 11656 | pr_err("kvm: failed to allocate vcpu's fpu\n"); |
c9b8b07c | 11657 | goto free_emulate_ctxt; |
95a0d01e SC |
11658 | } |
11659 | ||
95a0d01e | 11660 | vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); |
a8ac864a | 11661 | vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); |
95a0d01e SC |
11662 | |
11663 | vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT; | |
11664 | ||
11665 | kvm_async_pf_hash_reset(vcpu); | |
11666 | kvm_pmu_init(vcpu); | |
11667 | ||
11668 | vcpu->arch.pending_external_vector = -1; | |
11669 | vcpu->arch.preempted_in_kernel = false; | |
11670 | ||
3c86c0d3 VP |
11671 | #if IS_ENABLED(CONFIG_HYPERV) |
11672 | vcpu->arch.hv_root_tdp = INVALID_PAGE; | |
11673 | #endif | |
11674 | ||
b3646477 | 11675 | r = static_call(kvm_x86_vcpu_create)(vcpu); |
95a0d01e SC |
11676 | if (r) |
11677 | goto free_guest_fpu; | |
e9b11c17 | 11678 | |
0cf9135b | 11679 | vcpu->arch.arch_capabilities = kvm_get_arch_capabilities(); |
e53d88af | 11680 | vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT; |
942c2490 | 11681 | kvm_xen_init_vcpu(vcpu); |
19efffa2 | 11682 | kvm_vcpu_mtrr_init(vcpu); |
ec7660cc | 11683 | vcpu_load(vcpu); |
ffbb61d0 | 11684 | kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz); |
d28bc9dd | 11685 | kvm_vcpu_reset(vcpu, false); |
c9060662 | 11686 | kvm_init_mmu(vcpu); |
e9b11c17 | 11687 | vcpu_put(vcpu); |
ec7660cc | 11688 | return 0; |
95a0d01e SC |
11689 | |
11690 | free_guest_fpu: | |
d69c1382 | 11691 | fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); |
c9b8b07c SC |
11692 | free_emulate_ctxt: |
11693 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); | |
95a0d01e SC |
11694 | free_wbinvd_dirty_mask: |
11695 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); | |
11696 | fail_free_mce_banks: | |
11697 | kfree(vcpu->arch.mce_banks); | |
281b5278 | 11698 | kfree(vcpu->arch.mci_ctl2_banks); |
95a0d01e SC |
11699 | fail_free_pio_data: |
11700 | free_page((unsigned long)vcpu->arch.pio_data); | |
11701 | fail_free_lapic: | |
11702 | kvm_free_lapic(vcpu); | |
11703 | fail_mmu_destroy: | |
11704 | kvm_mmu_destroy(vcpu); | |
11705 | return r; | |
e9b11c17 ZX |
11706 | } |
11707 | ||
31928aa5 | 11708 | void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) |
42897d86 | 11709 | { |
332967a3 | 11710 | struct kvm *kvm = vcpu->kvm; |
42897d86 | 11711 | |
ec7660cc | 11712 | if (mutex_lock_killable(&vcpu->mutex)) |
31928aa5 | 11713 | return; |
ec7660cc | 11714 | vcpu_load(vcpu); |
0c899c25 | 11715 | kvm_synchronize_tsc(vcpu, 0); |
42897d86 | 11716 | vcpu_put(vcpu); |
2d5ba19b MT |
11717 | |
11718 | /* poll control enabled by default */ | |
11719 | vcpu->arch.msr_kvm_poll_control = 1; | |
11720 | ||
ec7660cc | 11721 | mutex_unlock(&vcpu->mutex); |
42897d86 | 11722 | |
b34de572 WL |
11723 | if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0) |
11724 | schedule_delayed_work(&kvm->arch.kvmclock_sync_work, | |
11725 | KVMCLOCK_SYNC_PERIOD); | |
42897d86 MT |
11726 | } |
11727 | ||
d40ccc62 | 11728 | void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) |
e9b11c17 | 11729 | { |
95a0d01e | 11730 | int idx; |
344d9588 | 11731 | |
50b143e1 | 11732 | kvmclock_reset(vcpu); |
e9b11c17 | 11733 | |
b3646477 | 11734 | static_call(kvm_x86_vcpu_free)(vcpu); |
50b143e1 | 11735 | |
c9b8b07c | 11736 | kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt); |
50b143e1 | 11737 | free_cpumask_var(vcpu->arch.wbinvd_dirty_mask); |
d69c1382 | 11738 | fpu_free_guest_fpstate(&vcpu->arch.guest_fpu); |
95a0d01e | 11739 | |
a795cd43 | 11740 | kvm_xen_destroy_vcpu(vcpu); |
95a0d01e SC |
11741 | kvm_hv_vcpu_uninit(vcpu); |
11742 | kvm_pmu_destroy(vcpu); | |
11743 | kfree(vcpu->arch.mce_banks); | |
281b5278 | 11744 | kfree(vcpu->arch.mci_ctl2_banks); |
95a0d01e SC |
11745 | kvm_free_lapic(vcpu); |
11746 | idx = srcu_read_lock(&vcpu->kvm->srcu); | |
11747 | kvm_mmu_destroy(vcpu); | |
11748 | srcu_read_unlock(&vcpu->kvm->srcu, idx); | |
11749 | free_page((unsigned long)vcpu->arch.pio_data); | |
255cbecf | 11750 | kvfree(vcpu->arch.cpuid_entries); |
95a0d01e | 11751 | if (!lapic_in_kernel(vcpu)) |
6e4e3b4d | 11752 | static_branch_dec(&kvm_has_noapic_vcpu); |
e9b11c17 ZX |
11753 | } |
11754 | ||
d28bc9dd | 11755 | void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) |
e9b11c17 | 11756 | { |
25b97845 | 11757 | struct kvm_cpuid_entry2 *cpuid_0x1; |
0aa18375 | 11758 | unsigned long old_cr0 = kvm_read_cr0(vcpu); |
4c72ab5a | 11759 | unsigned long new_cr0; |
0aa18375 | 11760 | |
62dd57dd SC |
11761 | /* |
11762 | * Several of the "set" flows, e.g. ->set_cr0(), read other registers | |
11763 | * to handle side effects. RESET emulation hits those flows and relies | |
11764 | * on emulated/virtualized registers, including those that are loaded | |
11765 | * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel | |
11766 | * to detect improper or missing initialization. | |
11767 | */ | |
11768 | WARN_ON_ONCE(!init_event && | |
11769 | (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu))); | |
0aa18375 | 11770 | |
b7e31be3 RK |
11771 | kvm_lapic_reset(vcpu, init_event); |
11772 | ||
e69fab5d PB |
11773 | vcpu->arch.hflags = 0; |
11774 | ||
c43203ca | 11775 | vcpu->arch.smi_pending = 0; |
52797bf9 | 11776 | vcpu->arch.smi_count = 0; |
7460fb4a AK |
11777 | atomic_set(&vcpu->arch.nmi_queued, 0); |
11778 | vcpu->arch.nmi_pending = 0; | |
448fa4a9 | 11779 | vcpu->arch.nmi_injected = false; |
5f7552d4 NA |
11780 | kvm_clear_interrupt_queue(vcpu); |
11781 | kvm_clear_exception_queue(vcpu); | |
448fa4a9 | 11782 | |
42dbaa5a | 11783 | memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db)); |
ae561ede | 11784 | kvm_update_dr0123(vcpu); |
9a3ecd5e | 11785 | vcpu->arch.dr6 = DR6_ACTIVE_LOW; |
42dbaa5a | 11786 | vcpu->arch.dr7 = DR7_FIXED_1; |
c8639010 | 11787 | kvm_update_dr7(vcpu); |
42dbaa5a | 11788 | |
1119022c NA |
11789 | vcpu->arch.cr2 = 0; |
11790 | ||
3842d135 | 11791 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
2635b5c4 VK |
11792 | vcpu->arch.apf.msr_en_val = 0; |
11793 | vcpu->arch.apf.msr_int_val = 0; | |
c9aaa895 | 11794 | vcpu->arch.st.msr_val = 0; |
3842d135 | 11795 | |
12f9a48f GC |
11796 | kvmclock_reset(vcpu); |
11797 | ||
af585b92 GN |
11798 | kvm_clear_async_pf_completion_queue(vcpu); |
11799 | kvm_async_pf_hash_reset(vcpu); | |
11800 | vcpu->arch.apf.halted = false; | |
3842d135 | 11801 | |
d69c1382 TG |
11802 | if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) { |
11803 | struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate; | |
a554d207 WL |
11804 | |
11805 | /* | |
11806 | * To avoid have the INIT path from kvm_apic_has_events() that be | |
11807 | * called with loaded FPU and does not let userspace fix the state. | |
11808 | */ | |
f775b13e RR |
11809 | if (init_event) |
11810 | kvm_put_guest_fpu(vcpu); | |
087df48c TG |
11811 | |
11812 | fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS); | |
11813 | fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR); | |
11814 | ||
f775b13e RR |
11815 | if (init_event) |
11816 | kvm_load_guest_fpu(vcpu); | |
a554d207 WL |
11817 | } |
11818 | ||
64d60670 | 11819 | if (!init_event) { |
d28bc9dd | 11820 | kvm_pmu_reset(vcpu); |
64d60670 | 11821 | vcpu->arch.smbase = 0x30000; |
db2336a8 | 11822 | |
db2336a8 | 11823 | vcpu->arch.msr_misc_features_enables = 0; |
9fc22296 SC |
11824 | vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL | |
11825 | MSR_IA32_MISC_ENABLE_BTS_UNAVAIL; | |
a554d207 | 11826 | |
05a9e065 LX |
11827 | __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP); |
11828 | __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true); | |
64d60670 | 11829 | } |
f5132b01 | 11830 | |
ff8828c8 | 11831 | /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */ |
66f7b72e | 11832 | memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs)); |
ff8828c8 | 11833 | kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP); |
66f7b72e | 11834 | |
49d8665c SC |
11835 | /* |
11836 | * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon) | |
11837 | * if no CPUID match is found. Note, it's impossible to get a match at | |
11838 | * RESET since KVM emulates RESET before exposing the vCPU to userspace, | |
25b97845 SC |
11839 | * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry |
11840 | * on RESET. But, go through the motions in case that's ever remedied. | |
49d8665c | 11841 | */ |
277ad7d5 | 11842 | cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1); |
25b97845 | 11843 | kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600); |
49d8665c | 11844 | |
b3646477 | 11845 | static_call(kvm_x86_vcpu_reset)(vcpu, init_event); |
0aa18375 | 11846 | |
f39e805e SC |
11847 | kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); |
11848 | kvm_rip_write(vcpu, 0xfff0); | |
11849 | ||
03a6e840 SC |
11850 | vcpu->arch.cr3 = 0; |
11851 | kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3); | |
11852 | ||
4c72ab5a SC |
11853 | /* |
11854 | * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions | |
11855 | * of Intel's SDM list CD/NW as being set on INIT, but they contradict | |
11856 | * (or qualify) that with a footnote stating that CD/NW are preserved. | |
11857 | */ | |
11858 | new_cr0 = X86_CR0_ET; | |
11859 | if (init_event) | |
11860 | new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD)); | |
11861 | else | |
11862 | new_cr0 |= X86_CR0_NW | X86_CR0_CD; | |
11863 | ||
11864 | static_call(kvm_x86_set_cr0)(vcpu, new_cr0); | |
f39e805e SC |
11865 | static_call(kvm_x86_set_cr4)(vcpu, 0); |
11866 | static_call(kvm_x86_set_efer)(vcpu, 0); | |
11867 | static_call(kvm_x86_update_exception_bitmap)(vcpu); | |
11868 | ||
0aa18375 | 11869 | /* |
b5f61c03 PB |
11870 | * On the standard CR0/CR4/EFER modification paths, there are several |
11871 | * complex conditions determining whether the MMU has to be reset and/or | |
11872 | * which PCIDs have to be flushed. However, CR0.WP and the paging-related | |
11873 | * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush | |
11874 | * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as | |
11875 | * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here. | |
0aa18375 | 11876 | */ |
b5f61c03 PB |
11877 | if (old_cr0 & X86_CR0_PG) { |
11878 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
0aa18375 | 11879 | kvm_mmu_reset_context(vcpu); |
b5f61c03 | 11880 | } |
df37ed38 SC |
11881 | |
11882 | /* | |
11883 | * Intel's SDM states that all TLB entries are flushed on INIT. AMD's | |
11884 | * APM states the TLBs are untouched by INIT, but it also states that | |
11885 | * the TLBs are flushed on "External initialization of the processor." | |
11886 | * Flush the guest TLB regardless of vendor, there is no meaningful | |
11887 | * benefit in relying on the guest to flush the TLB immediately after | |
11888 | * INIT. A spurious TLB flush is benign and likely negligible from a | |
11889 | * performance perspective. | |
11890 | */ | |
11891 | if (init_event) | |
11892 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); | |
e9b11c17 | 11893 | } |
265e4353 | 11894 | EXPORT_SYMBOL_GPL(kvm_vcpu_reset); |
e9b11c17 | 11895 | |
2b4a273b | 11896 | void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) |
66450a21 JK |
11897 | { |
11898 | struct kvm_segment cs; | |
11899 | ||
11900 | kvm_get_segment(vcpu, &cs, VCPU_SREG_CS); | |
11901 | cs.selector = vector << 8; | |
11902 | cs.base = vector << 12; | |
11903 | kvm_set_segment(vcpu, &cs, VCPU_SREG_CS); | |
11904 | kvm_rip_write(vcpu, 0); | |
e9b11c17 | 11905 | } |
647daca2 | 11906 | EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector); |
e9b11c17 | 11907 | |
13a34e06 | 11908 | int kvm_arch_hardware_enable(void) |
e9b11c17 | 11909 | { |
ca84d1a2 ZA |
11910 | struct kvm *kvm; |
11911 | struct kvm_vcpu *vcpu; | |
46808a4c | 11912 | unsigned long i; |
0dd6a6ed ZA |
11913 | int ret; |
11914 | u64 local_tsc; | |
11915 | u64 max_tsc = 0; | |
11916 | bool stable, backwards_tsc = false; | |
18863bdd | 11917 | |
7e34fbd0 | 11918 | kvm_user_return_msr_cpu_online(); |
b3646477 | 11919 | ret = static_call(kvm_x86_hardware_enable)(); |
0dd6a6ed ZA |
11920 | if (ret != 0) |
11921 | return ret; | |
11922 | ||
4ea1636b | 11923 | local_tsc = rdtsc(); |
b0c39dc6 | 11924 | stable = !kvm_check_tsc_unstable(); |
0dd6a6ed ZA |
11925 | list_for_each_entry(kvm, &vm_list, vm_list) { |
11926 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
11927 | if (!stable && vcpu->cpu == smp_processor_id()) | |
105b21bb | 11928 | kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
11929 | if (stable && vcpu->arch.last_host_tsc > local_tsc) { |
11930 | backwards_tsc = true; | |
11931 | if (vcpu->arch.last_host_tsc > max_tsc) | |
11932 | max_tsc = vcpu->arch.last_host_tsc; | |
11933 | } | |
11934 | } | |
11935 | } | |
11936 | ||
11937 | /* | |
11938 | * Sometimes, even reliable TSCs go backwards. This happens on | |
11939 | * platforms that reset TSC during suspend or hibernate actions, but | |
11940 | * maintain synchronization. We must compensate. Fortunately, we can | |
11941 | * detect that condition here, which happens early in CPU bringup, | |
11942 | * before any KVM threads can be running. Unfortunately, we can't | |
11943 | * bring the TSCs fully up to date with real time, as we aren't yet far | |
11944 | * enough into CPU bringup that we know how much real time has actually | |
9285ec4c | 11945 | * elapsed; our helper function, ktime_get_boottime_ns() will be using boot |
0dd6a6ed ZA |
11946 | * variables that haven't been updated yet. |
11947 | * | |
11948 | * So we simply find the maximum observed TSC above, then record the | |
11949 | * adjustment to TSC in each VCPU. When the VCPU later gets loaded, | |
11950 | * the adjustment will be applied. Note that we accumulate | |
11951 | * adjustments, in case multiple suspend cycles happen before some VCPU | |
11952 | * gets a chance to run again. In the event that no KVM threads get a | |
11953 | * chance to run, we will miss the entire elapsed period, as we'll have | |
11954 | * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may | |
11955 | * loose cycle time. This isn't too big a deal, since the loss will be | |
11956 | * uniform across all VCPUs (not to mention the scenario is extremely | |
11957 | * unlikely). It is possible that a second hibernate recovery happens | |
11958 | * much faster than a first, causing the observed TSC here to be | |
11959 | * smaller; this would require additional padding adjustment, which is | |
11960 | * why we set last_host_tsc to the local tsc observed here. | |
11961 | * | |
11962 | * N.B. - this code below runs only on platforms with reliable TSC, | |
11963 | * as that is the only way backwards_tsc is set above. Also note | |
11964 | * that this runs for ALL vcpus, which is not a bug; all VCPUs should | |
11965 | * have the same delta_cyc adjustment applied if backwards_tsc | |
11966 | * is detected. Note further, this adjustment is only done once, | |
11967 | * as we reset last_host_tsc on all VCPUs to stop this from being | |
11968 | * called multiple times (one for each physical CPU bringup). | |
11969 | * | |
4a969980 | 11970 | * Platforms with unreliable TSCs don't have to deal with this, they |
0dd6a6ed ZA |
11971 | * will be compensated by the logic in vcpu_load, which sets the TSC to |
11972 | * catchup mode. This will catchup all VCPUs to real time, but cannot | |
11973 | * guarantee that they stay in perfect synchronization. | |
11974 | */ | |
11975 | if (backwards_tsc) { | |
11976 | u64 delta_cyc = max_tsc - local_tsc; | |
11977 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
a826faf1 | 11978 | kvm->arch.backwards_tsc_observed = true; |
0dd6a6ed ZA |
11979 | kvm_for_each_vcpu(i, vcpu, kvm) { |
11980 | vcpu->arch.tsc_offset_adjustment += delta_cyc; | |
11981 | vcpu->arch.last_host_tsc = local_tsc; | |
105b21bb | 11982 | kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu); |
0dd6a6ed ZA |
11983 | } |
11984 | ||
11985 | /* | |
11986 | * We have to disable TSC offset matching.. if you were | |
11987 | * booting a VM while issuing an S4 host suspend.... | |
11988 | * you may have some problem. Solving this issue is | |
11989 | * left as an exercise to the reader. | |
11990 | */ | |
11991 | kvm->arch.last_tsc_nsec = 0; | |
11992 | kvm->arch.last_tsc_write = 0; | |
11993 | } | |
11994 | ||
11995 | } | |
11996 | return 0; | |
e9b11c17 ZX |
11997 | } |
11998 | ||
13a34e06 | 11999 | void kvm_arch_hardware_disable(void) |
e9b11c17 | 12000 | { |
b3646477 | 12001 | static_call(kvm_x86_hardware_disable)(); |
13a34e06 | 12002 | drop_user_return_notifiers(); |
e9b11c17 ZX |
12003 | } |
12004 | ||
fdc298da LX |
12005 | static inline void kvm_ops_update(struct kvm_x86_init_ops *ops) |
12006 | { | |
12007 | memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops)); | |
12008 | ||
12009 | #define __KVM_X86_OP(func) \ | |
12010 | static_call_update(kvm_x86_##func, kvm_x86_ops.func); | |
12011 | #define KVM_X86_OP(func) \ | |
12012 | WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func) | |
12013 | #define KVM_X86_OP_OPTIONAL __KVM_X86_OP | |
12014 | #define KVM_X86_OP_OPTIONAL_RET0(func) \ | |
12015 | static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \ | |
12016 | (void *)__static_call_return0); | |
12017 | #include <asm/kvm-x86-ops.h> | |
12018 | #undef __KVM_X86_OP | |
8f969c0c | 12019 | |
34886e79 | 12020 | kvm_pmu_ops_update(ops->pmu_ops); |
fdc298da LX |
12021 | } |
12022 | ||
b9904085 | 12023 | int kvm_arch_hardware_setup(void *opaque) |
e9b11c17 | 12024 | { |
d008dfdb | 12025 | struct kvm_x86_init_ops *ops = opaque; |
9e9c3fe4 NA |
12026 | int r; |
12027 | ||
91661989 SC |
12028 | rdmsrl_safe(MSR_EFER, &host_efer); |
12029 | ||
408e9a31 PB |
12030 | if (boot_cpu_has(X86_FEATURE_XSAVES)) |
12031 | rdmsrl(MSR_IA32_XSS, host_xss); | |
12032 | ||
968635ab LX |
12033 | kvm_init_pmu_capability(); |
12034 | ||
d008dfdb | 12035 | r = ops->hardware_setup(); |
9e9c3fe4 NA |
12036 | if (r != 0) |
12037 | return r; | |
12038 | ||
fdc298da | 12039 | kvm_ops_update(ops); |
69c6f69a | 12040 | |
33271a9e | 12041 | kvm_register_perf_callbacks(ops->handle_intel_pt_intr); |
5c7df80e | 12042 | |
408e9a31 | 12043 | if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES)) |
938c8745 | 12044 | kvm_caps.supported_xss = 0; |
408e9a31 | 12045 | |
139f7425 PB |
12046 | #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) |
12047 | cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_); | |
12048 | #undef __kvm_cpu_cap_has | |
b11306b5 | 12049 | |
938c8745 | 12050 | if (kvm_caps.has_tsc_control) { |
35181e86 HZ |
12051 | /* |
12052 | * Make sure the user can only configure tsc_khz values that | |
12053 | * fit into a signed integer. | |
273ba457 | 12054 | * A min value is not calculated because it will always |
35181e86 HZ |
12055 | * be 1 on all machines. |
12056 | */ | |
12057 | u64 max = min(0x7fffffffULL, | |
938c8745 SC |
12058 | __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz)); |
12059 | kvm_caps.max_guest_tsc_khz = max; | |
35181e86 | 12060 | } |
938c8745 | 12061 | kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits; |
9e9c3fe4 NA |
12062 | kvm_init_msr_list(); |
12063 | return 0; | |
e9b11c17 ZX |
12064 | } |
12065 | ||
12066 | void kvm_arch_hardware_unsetup(void) | |
12067 | { | |
e1bfc245 | 12068 | kvm_unregister_perf_callbacks(); |
5c7df80e | 12069 | |
b3646477 | 12070 | static_call(kvm_x86_hardware_unsetup)(); |
e9b11c17 ZX |
12071 | } |
12072 | ||
b9904085 | 12073 | int kvm_arch_check_processor_compat(void *opaque) |
e9b11c17 | 12074 | { |
f1cdecf5 | 12075 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); |
d008dfdb | 12076 | struct kvm_x86_init_ops *ops = opaque; |
f1cdecf5 SC |
12077 | |
12078 | WARN_ON(!irqs_disabled()); | |
12079 | ||
139f7425 PB |
12080 | if (__cr4_reserved_bits(cpu_has, c) != |
12081 | __cr4_reserved_bits(cpu_has, &boot_cpu_data)) | |
f1cdecf5 SC |
12082 | return -EIO; |
12083 | ||
d008dfdb | 12084 | return ops->check_processor_compatibility(); |
d71ba788 PB |
12085 | } |
12086 | ||
12087 | bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu) | |
12088 | { | |
12089 | return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id; | |
12090 | } | |
12091 | EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp); | |
12092 | ||
12093 | bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu) | |
12094 | { | |
12095 | return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0; | |
e9b11c17 ZX |
12096 | } |
12097 | ||
6e4e3b4d CL |
12098 | __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu); |
12099 | EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu); | |
54e9818f | 12100 | |
e790d9ef RK |
12101 | void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) |
12102 | { | |
b35e5548 LX |
12103 | struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); |
12104 | ||
c595ceee | 12105 | vcpu->arch.l1tf_flush_l1d = true; |
b35e5548 LX |
12106 | if (pmu->version && unlikely(pmu->event_count)) { |
12107 | pmu->need_cleanup = true; | |
12108 | kvm_make_request(KVM_REQ_PMU, vcpu); | |
12109 | } | |
b3646477 | 12110 | static_call(kvm_x86_sched_in)(vcpu, cpu); |
e790d9ef RK |
12111 | } |
12112 | ||
562b6b08 SC |
12113 | void kvm_arch_free_vm(struct kvm *kvm) |
12114 | { | |
05f04ae4 | 12115 | kfree(to_kvm_hv(kvm)->hv_pa_pg); |
78b497f2 | 12116 | __kvm_arch_free_vm(kvm); |
e790d9ef RK |
12117 | } |
12118 | ||
562b6b08 | 12119 | |
e08b9637 | 12120 | int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) |
d19a9cd2 | 12121 | { |
eb7511bf | 12122 | int ret; |
869b4421 | 12123 | unsigned long flags; |
eb7511bf | 12124 | |
e08b9637 CO |
12125 | if (type) |
12126 | return -EINVAL; | |
12127 | ||
eb7511bf HZ |
12128 | ret = kvm_page_track_init(kvm); |
12129 | if (ret) | |
a1a39128 PB |
12130 | goto out; |
12131 | ||
12132 | ret = kvm_mmu_init_vm(kvm); | |
12133 | if (ret) | |
12134 | goto out_page_track; | |
eb7511bf | 12135 | |
b24ede22 JS |
12136 | ret = static_call(kvm_x86_vm_init)(kvm); |
12137 | if (ret) | |
12138 | goto out_uninit_mmu; | |
12139 | ||
6ef768fa | 12140 | INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list); |
4d5c5d0f | 12141 | INIT_LIST_HEAD(&kvm->arch.assigned_dev_head); |
e0f0bbc5 | 12142 | atomic_set(&kvm->arch.noncoherent_dma_count, 0); |
d19a9cd2 | 12143 | |
5550af4d SY |
12144 | /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */ |
12145 | set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap); | |
7a84428a AW |
12146 | /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */ |
12147 | set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID, | |
12148 | &kvm->arch.irq_sources_bitmap); | |
5550af4d | 12149 | |
038f8c11 | 12150 | raw_spin_lock_init(&kvm->arch.tsc_write_lock); |
1e08ec4a | 12151 | mutex_init(&kvm->arch.apic_map_lock); |
869b4421 | 12152 | seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock); |
8171cd68 | 12153 | kvm->arch.kvmclock_offset = -get_kvmclock_base_ns(); |
869b4421 PB |
12154 | |
12155 | raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags); | |
d828199e | 12156 | pvclock_update_vm_gtod_copy(kvm); |
869b4421 | 12157 | raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags); |
53f658b3 | 12158 | |
741e511b | 12159 | kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz; |
6fbbde9a | 12160 | kvm->arch.guest_can_read_msr_platform_info = true; |
ba7bb663 | 12161 | kvm->arch.enable_pmu = enable_pmu; |
6fbbde9a | 12162 | |
3c86c0d3 VP |
12163 | #if IS_ENABLED(CONFIG_HYPERV) |
12164 | spin_lock_init(&kvm->arch.hv_root_tdp_lock); | |
12165 | kvm->arch.hv_root_tdp = INVALID_PAGE; | |
12166 | #endif | |
12167 | ||
7e44e449 | 12168 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn); |
332967a3 | 12169 | INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn); |
7e44e449 | 12170 | |
4651fc56 | 12171 | kvm_apicv_init(kvm); |
cbc0236a | 12172 | kvm_hv_init_vm(kvm); |
319afe68 | 12173 | kvm_xen_init_vm(kvm); |
0eb05bf2 | 12174 | |
b24ede22 | 12175 | return 0; |
a1a39128 | 12176 | |
b24ede22 JS |
12177 | out_uninit_mmu: |
12178 | kvm_mmu_uninit_vm(kvm); | |
a1a39128 PB |
12179 | out_page_track: |
12180 | kvm_page_track_cleanup(kvm); | |
12181 | out: | |
12182 | return ret; | |
d19a9cd2 ZX |
12183 | } |
12184 | ||
1aa9b957 JS |
12185 | int kvm_arch_post_init_vm(struct kvm *kvm) |
12186 | { | |
12187 | return kvm_mmu_post_init_vm(kvm); | |
12188 | } | |
12189 | ||
d19a9cd2 ZX |
12190 | static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu) |
12191 | { | |
ec7660cc | 12192 | vcpu_load(vcpu); |
d19a9cd2 ZX |
12193 | kvm_mmu_unload(vcpu); |
12194 | vcpu_put(vcpu); | |
12195 | } | |
12196 | ||
6fcee03d | 12197 | static void kvm_unload_vcpu_mmus(struct kvm *kvm) |
d19a9cd2 | 12198 | { |
46808a4c | 12199 | unsigned long i; |
988a2cae | 12200 | struct kvm_vcpu *vcpu; |
d19a9cd2 | 12201 | |
af585b92 GN |
12202 | kvm_for_each_vcpu(i, vcpu, kvm) { |
12203 | kvm_clear_async_pf_completion_queue(vcpu); | |
988a2cae | 12204 | kvm_unload_vcpu_mmu(vcpu); |
af585b92 | 12205 | } |
d19a9cd2 ZX |
12206 | } |
12207 | ||
ad8ba2cd SY |
12208 | void kvm_arch_sync_events(struct kvm *kvm) |
12209 | { | |
332967a3 | 12210 | cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work); |
7e44e449 | 12211 | cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work); |
aea924f6 | 12212 | kvm_free_pit(kvm); |
ad8ba2cd SY |
12213 | } |
12214 | ||
ff5a983c PX |
12215 | /** |
12216 | * __x86_set_memory_region: Setup KVM internal memory slot | |
12217 | * | |
12218 | * @kvm: the kvm pointer to the VM. | |
12219 | * @id: the slot ID to setup. | |
12220 | * @gpa: the GPA to install the slot (unused when @size == 0). | |
12221 | * @size: the size of the slot. Set to zero to uninstall a slot. | |
12222 | * | |
12223 | * This function helps to setup a KVM internal memory slot. Specify | |
12224 | * @size > 0 to install a new slot, while @size == 0 to uninstall a | |
12225 | * slot. The return code can be one of the following: | |
12226 | * | |
12227 | * HVA: on success (uninstall will return a bogus HVA) | |
12228 | * -errno: on error | |
12229 | * | |
12230 | * The caller should always use IS_ERR() to check the return value | |
12231 | * before use. Note, the KVM internal memory slots are guaranteed to | |
12232 | * remain valid and unchanged until the VM is destroyed, i.e., the | |
12233 | * GPA->HVA translation will not change. However, the HVA is a user | |
12234 | * address, i.e. its accessibility is not guaranteed, and must be | |
12235 | * accessed via __copy_{to,from}_user(). | |
12236 | */ | |
12237 | void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, | |
12238 | u32 size) | |
9da0e4d5 PB |
12239 | { |
12240 | int i, r; | |
3f649ab7 | 12241 | unsigned long hva, old_npages; |
f0d648bd | 12242 | struct kvm_memslots *slots = kvm_memslots(kvm); |
0577d1ab | 12243 | struct kvm_memory_slot *slot; |
9da0e4d5 PB |
12244 | |
12245 | /* Called with kvm->slots_lock held. */ | |
1d8007bd | 12246 | if (WARN_ON(id >= KVM_MEM_SLOTS_NUM)) |
ff5a983c | 12247 | return ERR_PTR_USR(-EINVAL); |
9da0e4d5 | 12248 | |
f0d648bd PB |
12249 | slot = id_to_memslot(slots, id); |
12250 | if (size) { | |
0577d1ab | 12251 | if (slot && slot->npages) |
ff5a983c | 12252 | return ERR_PTR_USR(-EEXIST); |
f0d648bd PB |
12253 | |
12254 | /* | |
12255 | * MAP_SHARED to prevent internal slot pages from being moved | |
12256 | * by fork()/COW. | |
12257 | */ | |
12258 | hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE, | |
12259 | MAP_SHARED | MAP_ANONYMOUS, 0); | |
12260 | if (IS_ERR((void *)hva)) | |
ff5a983c | 12261 | return (void __user *)hva; |
f0d648bd | 12262 | } else { |
0577d1ab | 12263 | if (!slot || !slot->npages) |
46914534 | 12264 | return NULL; |
f0d648bd | 12265 | |
0577d1ab | 12266 | old_npages = slot->npages; |
b66f9bab | 12267 | hva = slot->userspace_addr; |
f0d648bd PB |
12268 | } |
12269 | ||
9da0e4d5 | 12270 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1d8007bd | 12271 | struct kvm_userspace_memory_region m; |
9da0e4d5 | 12272 | |
1d8007bd PB |
12273 | m.slot = id | (i << 16); |
12274 | m.flags = 0; | |
12275 | m.guest_phys_addr = gpa; | |
f0d648bd | 12276 | m.userspace_addr = hva; |
1d8007bd | 12277 | m.memory_size = size; |
9da0e4d5 PB |
12278 | r = __kvm_set_memory_region(kvm, &m); |
12279 | if (r < 0) | |
ff5a983c | 12280 | return ERR_PTR_USR(r); |
9da0e4d5 PB |
12281 | } |
12282 | ||
103c763c | 12283 | if (!size) |
0577d1ab | 12284 | vm_munmap(hva, old_npages * PAGE_SIZE); |
f0d648bd | 12285 | |
ff5a983c | 12286 | return (void __user *)hva; |
9da0e4d5 PB |
12287 | } |
12288 | EXPORT_SYMBOL_GPL(__x86_set_memory_region); | |
12289 | ||
1aa9b957 JS |
12290 | void kvm_arch_pre_destroy_vm(struct kvm *kvm) |
12291 | { | |
12292 | kvm_mmu_pre_destroy_vm(kvm); | |
12293 | } | |
12294 | ||
d19a9cd2 ZX |
12295 | void kvm_arch_destroy_vm(struct kvm *kvm) |
12296 | { | |
27469d29 AH |
12297 | if (current->mm == kvm->mm) { |
12298 | /* | |
12299 | * Free memory regions allocated on behalf of userspace, | |
f7081834 | 12300 | * unless the memory map has changed due to process exit |
27469d29 AH |
12301 | * or fd copying. |
12302 | */ | |
6a3c623b PX |
12303 | mutex_lock(&kvm->slots_lock); |
12304 | __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, | |
12305 | 0, 0); | |
12306 | __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, | |
12307 | 0, 0); | |
12308 | __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0); | |
12309 | mutex_unlock(&kvm->slots_lock); | |
27469d29 | 12310 | } |
6fcee03d | 12311 | kvm_unload_vcpu_mmus(kvm); |
b3646477 | 12312 | static_call_cond(kvm_x86_vm_destroy)(kvm); |
b318e8de | 12313 | kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1)); |
c761159c PX |
12314 | kvm_pic_destroy(kvm); |
12315 | kvm_ioapic_destroy(kvm); | |
6fcee03d | 12316 | kvm_destroy_vcpus(kvm); |
af1bae54 | 12317 | kvfree(rcu_dereference_check(kvm->arch.apic_map, 1)); |
66bb8a06 | 12318 | kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1)); |
13d268ca | 12319 | kvm_mmu_uninit_vm(kvm); |
2beb6dad | 12320 | kvm_page_track_cleanup(kvm); |
7d6bbebb | 12321 | kvm_xen_destroy_vm(kvm); |
cbc0236a | 12322 | kvm_hv_destroy_vm(kvm); |
d19a9cd2 | 12323 | } |
0de10343 | 12324 | |
c9b929b3 | 12325 | static void memslot_rmap_free(struct kvm_memory_slot *slot) |
db3fe4eb TY |
12326 | { |
12327 | int i; | |
12328 | ||
d89cc617 | 12329 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
12330 | kvfree(slot->arch.rmap[i]); |
12331 | slot->arch.rmap[i] = NULL; | |
c9b929b3 BG |
12332 | } |
12333 | } | |
e96c81ee | 12334 | |
c9b929b3 BG |
12335 | void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot) |
12336 | { | |
12337 | int i; | |
12338 | ||
12339 | memslot_rmap_free(slot); | |
d89cc617 | 12340 | |
c9b929b3 | 12341 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
e96c81ee SC |
12342 | kvfree(slot->arch.lpage_info[i - 1]); |
12343 | slot->arch.lpage_info[i - 1] = NULL; | |
db3fe4eb | 12344 | } |
21ebbeda | 12345 | |
e96c81ee | 12346 | kvm_page_track_free_memslot(slot); |
db3fe4eb TY |
12347 | } |
12348 | ||
1e76a3ce | 12349 | int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages) |
56dd1019 BG |
12350 | { |
12351 | const int sz = sizeof(*slot->arch.rmap[0]); | |
12352 | int i; | |
12353 | ||
12354 | for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) { | |
12355 | int level = i + 1; | |
4139b197 | 12356 | int lpages = __kvm_mmu_slot_lpages(slot, npages, level); |
56dd1019 | 12357 | |
fa13843d PB |
12358 | if (slot->arch.rmap[i]) |
12359 | continue; | |
d501f747 | 12360 | |
37b2a651 | 12361 | slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT); |
56dd1019 BG |
12362 | if (!slot->arch.rmap[i]) { |
12363 | memslot_rmap_free(slot); | |
12364 | return -ENOMEM; | |
12365 | } | |
12366 | } | |
12367 | ||
12368 | return 0; | |
12369 | } | |
12370 | ||
a2557408 | 12371 | static int kvm_alloc_memslot_metadata(struct kvm *kvm, |
9d7d18ee | 12372 | struct kvm_memory_slot *slot) |
db3fe4eb | 12373 | { |
9d7d18ee | 12374 | unsigned long npages = slot->npages; |
56dd1019 | 12375 | int i, r; |
db3fe4eb | 12376 | |
edd4fa37 SC |
12377 | /* |
12378 | * Clear out the previous array pointers for the KVM_MR_MOVE case. The | |
12379 | * old arrays will be freed by __kvm_set_memory_region() if installing | |
12380 | * the new memslot is successful. | |
12381 | */ | |
12382 | memset(&slot->arch, 0, sizeof(slot->arch)); | |
12383 | ||
e2209710 | 12384 | if (kvm_memslots_have_rmaps(kvm)) { |
a2557408 BG |
12385 | r = memslot_rmap_alloc(slot, npages); |
12386 | if (r) | |
12387 | return r; | |
12388 | } | |
56dd1019 BG |
12389 | |
12390 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { | |
92f94f1e | 12391 | struct kvm_lpage_info *linfo; |
db3fe4eb TY |
12392 | unsigned long ugfn; |
12393 | int lpages; | |
d89cc617 | 12394 | int level = i + 1; |
db3fe4eb | 12395 | |
4139b197 | 12396 | lpages = __kvm_mmu_slot_lpages(slot, npages, level); |
db3fe4eb | 12397 | |
37b2a651 | 12398 | linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT); |
92f94f1e | 12399 | if (!linfo) |
db3fe4eb TY |
12400 | goto out_free; |
12401 | ||
92f94f1e XG |
12402 | slot->arch.lpage_info[i - 1] = linfo; |
12403 | ||
db3fe4eb | 12404 | if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 12405 | linfo[0].disallow_lpage = 1; |
db3fe4eb | 12406 | if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1)) |
92f94f1e | 12407 | linfo[lpages - 1].disallow_lpage = 1; |
db3fe4eb TY |
12408 | ugfn = slot->userspace_addr >> PAGE_SHIFT; |
12409 | /* | |
12410 | * If the gfn and userspace address are not aligned wrt each | |
600087b6 | 12411 | * other, disable large page support for this slot. |
db3fe4eb | 12412 | */ |
600087b6 | 12413 | if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) { |
db3fe4eb TY |
12414 | unsigned long j; |
12415 | ||
12416 | for (j = 0; j < lpages; ++j) | |
92f94f1e | 12417 | linfo[j].disallow_lpage = 1; |
db3fe4eb TY |
12418 | } |
12419 | } | |
12420 | ||
deae4a10 | 12421 | if (kvm_page_track_create_memslot(kvm, slot, npages)) |
21ebbeda XG |
12422 | goto out_free; |
12423 | ||
db3fe4eb TY |
12424 | return 0; |
12425 | ||
12426 | out_free: | |
c9b929b3 | 12427 | memslot_rmap_free(slot); |
d89cc617 | 12428 | |
c9b929b3 | 12429 | for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) { |
548ef284 | 12430 | kvfree(slot->arch.lpage_info[i - 1]); |
d89cc617 | 12431 | slot->arch.lpage_info[i - 1] = NULL; |
db3fe4eb TY |
12432 | } |
12433 | return -ENOMEM; | |
12434 | } | |
12435 | ||
15248258 | 12436 | void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen) |
e59dbe09 | 12437 | { |
91724814 | 12438 | struct kvm_vcpu *vcpu; |
46808a4c | 12439 | unsigned long i; |
91724814 | 12440 | |
e6dff7d1 TY |
12441 | /* |
12442 | * memslots->generation has been incremented. | |
12443 | * mmio generation may have reached its maximum value. | |
12444 | */ | |
15248258 | 12445 | kvm_mmu_invalidate_mmio_sptes(kvm, gen); |
91724814 BO |
12446 | |
12447 | /* Force re-initialization of steal_time cache */ | |
12448 | kvm_for_each_vcpu(i, vcpu, kvm) | |
12449 | kvm_vcpu_kick(vcpu); | |
e59dbe09 TY |
12450 | } |
12451 | ||
f7784b8e | 12452 | int kvm_arch_prepare_memory_region(struct kvm *kvm, |
537a17b3 SC |
12453 | const struct kvm_memory_slot *old, |
12454 | struct kvm_memory_slot *new, | |
12455 | enum kvm_mr_change change) | |
0de10343 | 12456 | { |
86931ff7 SC |
12457 | if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) { |
12458 | if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn()) | |
12459 | return -EINVAL; | |
12460 | ||
9d7d18ee | 12461 | return kvm_alloc_memslot_metadata(kvm, new); |
86931ff7 | 12462 | } |
537a17b3 SC |
12463 | |
12464 | if (change == KVM_MR_FLAGS_ONLY) | |
12465 | memcpy(&new->arch, &old->arch, sizeof(old->arch)); | |
12466 | else if (WARN_ON_ONCE(change != KVM_MR_DELETE)) | |
12467 | return -EIO; | |
12468 | ||
f7784b8e MT |
12469 | return 0; |
12470 | } | |
12471 | ||
a85863c2 MS |
12472 | |
12473 | static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable) | |
12474 | { | |
12475 | struct kvm_arch *ka = &kvm->arch; | |
12476 | ||
12477 | if (!kvm_x86_ops.cpu_dirty_log_size) | |
12478 | return; | |
12479 | ||
12480 | if ((enable && ++ka->cpu_dirty_logging_count == 1) || | |
12481 | (!enable && --ka->cpu_dirty_logging_count == 0)) | |
12482 | kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING); | |
12483 | ||
12484 | WARN_ON_ONCE(ka->cpu_dirty_logging_count < 0); | |
12485 | } | |
12486 | ||
88178fd4 | 12487 | static void kvm_mmu_slot_apply_flags(struct kvm *kvm, |
3741679b | 12488 | struct kvm_memory_slot *old, |
269e9552 | 12489 | const struct kvm_memory_slot *new, |
3741679b | 12490 | enum kvm_mr_change change) |
88178fd4 | 12491 | { |
77aedf26 SC |
12492 | u32 old_flags = old ? old->flags : 0; |
12493 | u32 new_flags = new ? new->flags : 0; | |
12494 | bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES; | |
a85863c2 | 12495 | |
3741679b | 12496 | /* |
a85863c2 MS |
12497 | * Update CPU dirty logging if dirty logging is being toggled. This |
12498 | * applies to all operations. | |
3741679b | 12499 | */ |
77aedf26 | 12500 | if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES) |
a85863c2 | 12501 | kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages); |
88178fd4 KH |
12502 | |
12503 | /* | |
a85863c2 | 12504 | * Nothing more to do for RO slots (which can't be dirtied and can't be |
b6e16ae5 | 12505 | * made writable) or CREATE/MOVE/DELETE of a slot. |
88178fd4 | 12506 | * |
b6e16ae5 | 12507 | * For a memslot with dirty logging disabled: |
3741679b AY |
12508 | * CREATE: No dirty mappings will already exist. |
12509 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
12510 | * kvm_arch_flush_shadow_memslot() | |
b6e16ae5 SC |
12511 | * |
12512 | * For a memslot with dirty logging enabled: | |
12513 | * CREATE: No shadow pages exist, thus nothing to write-protect | |
12514 | * and no dirty bits to clear. | |
12515 | * MOVE/DELETE: The old mappings will already have been cleaned up by | |
12516 | * kvm_arch_flush_shadow_memslot(). | |
3741679b | 12517 | */ |
77aedf26 | 12518 | if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY)) |
88178fd4 | 12519 | return; |
3741679b AY |
12520 | |
12521 | /* | |
52f46079 SC |
12522 | * READONLY and non-flags changes were filtered out above, and the only |
12523 | * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty | |
12524 | * logging isn't being toggled on or off. | |
88178fd4 | 12525 | */ |
77aedf26 | 12526 | if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES))) |
52f46079 SC |
12527 | return; |
12528 | ||
b6e16ae5 SC |
12529 | if (!log_dirty_pages) { |
12530 | /* | |
12531 | * Dirty logging tracks sptes in 4k granularity, meaning that | |
12532 | * large sptes have to be split. If live migration succeeds, | |
12533 | * the guest in the source machine will be destroyed and large | |
12534 | * sptes will be created in the destination. However, if the | |
12535 | * guest continues to run in the source machine (for example if | |
12536 | * live migration fails), small sptes will remain around and | |
12537 | * cause bad performance. | |
12538 | * | |
12539 | * Scan sptes if dirty logging has been stopped, dropping those | |
12540 | * which can be collapsed into a single large-page spte. Later | |
12541 | * page faults will create the large-page sptes. | |
12542 | */ | |
3741679b | 12543 | kvm_mmu_zap_collapsible_sptes(kvm, new); |
b6e16ae5 | 12544 | } else { |
89212919 KZ |
12545 | /* |
12546 | * Initially-all-set does not require write protecting any page, | |
12547 | * because they're all assumed to be dirty. | |
12548 | */ | |
12549 | if (kvm_dirty_log_manual_protect_and_init_set(kvm)) | |
12550 | return; | |
a1419f8b | 12551 | |
a3fe5dbd DM |
12552 | if (READ_ONCE(eager_page_split)) |
12553 | kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K); | |
12554 | ||
a018eba5 | 12555 | if (kvm_x86_ops.cpu_dirty_log_size) { |
89212919 KZ |
12556 | kvm_mmu_slot_leaf_clear_dirty(kvm, new); |
12557 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M); | |
12558 | } else { | |
12559 | kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K); | |
3c9bd400 | 12560 | } |
b64d740e JS |
12561 | |
12562 | /* | |
12563 | * Unconditionally flush the TLBs after enabling dirty logging. | |
12564 | * A flush is almost always going to be necessary (see below), | |
12565 | * and unconditionally flushing allows the helpers to omit | |
12566 | * the subtly complex checks when removing write access. | |
12567 | * | |
12568 | * Do the flush outside of mmu_lock to reduce the amount of | |
12569 | * time mmu_lock is held. Flushing after dropping mmu_lock is | |
12570 | * safe as KVM only needs to guarantee the slot is fully | |
12571 | * write-protected before returning to userspace, i.e. before | |
12572 | * userspace can consume the dirty status. | |
12573 | * | |
12574 | * Flushing outside of mmu_lock requires KVM to be careful when | |
12575 | * making decisions based on writable status of an SPTE, e.g. a | |
12576 | * !writable SPTE doesn't guarantee a CPU can't perform writes. | |
12577 | * | |
12578 | * Specifically, KVM also write-protects guest page tables to | |
12579 | * monitor changes when using shadow paging, and must guarantee | |
12580 | * no CPUs can write to those page before mmu_lock is dropped. | |
12581 | * Because CPUs may have stale TLB entries at this point, a | |
12582 | * !writable SPTE doesn't guarantee CPUs can't perform writes. | |
12583 | * | |
12584 | * KVM also allows making SPTES writable outside of mmu_lock, | |
12585 | * e.g. to allow dirty logging without taking mmu_lock. | |
12586 | * | |
12587 | * To handle these scenarios, KVM uses a separate software-only | |
12588 | * bit (MMU-writable) to track if a SPTE is !writable due to | |
12589 | * a guest page table being write-protected (KVM clears the | |
12590 | * MMU-writable flag when write-protecting for shadow paging). | |
12591 | * | |
12592 | * The use of MMU-writable is also the primary motivation for | |
12593 | * the unconditional flush. Because KVM must guarantee that a | |
12594 | * CPU doesn't contain stale, writable TLB entries for a | |
12595 | * !MMU-writable SPTE, KVM must flush if it encounters any | |
12596 | * MMU-writable SPTE regardless of whether the actual hardware | |
12597 | * writable bit was set. I.e. KVM is almost guaranteed to need | |
12598 | * to flush, while unconditionally flushing allows the "remove | |
12599 | * write access" helpers to ignore MMU-writable entirely. | |
12600 | * | |
12601 | * See is_writable_pte() for more details (the case involving | |
12602 | * access-tracked SPTEs is particularly relevant). | |
12603 | */ | |
12604 | kvm_arch_flush_remote_tlbs_memslot(kvm, new); | |
88178fd4 KH |
12605 | } |
12606 | } | |
12607 | ||
f7784b8e | 12608 | void kvm_arch_commit_memory_region(struct kvm *kvm, |
9d4c197c | 12609 | struct kvm_memory_slot *old, |
f36f3f28 | 12610 | const struct kvm_memory_slot *new, |
8482644a | 12611 | enum kvm_mr_change change) |
f7784b8e | 12612 | { |
e0c2b633 | 12613 | if (!kvm->arch.n_requested_mmu_pages && |
f5756029 MS |
12614 | (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) { |
12615 | unsigned long nr_mmu_pages; | |
12616 | ||
12617 | nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO; | |
12618 | nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES); | |
12619 | kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages); | |
12620 | } | |
1c91cad4 | 12621 | |
269e9552 | 12622 | kvm_mmu_slot_apply_flags(kvm, old, new, change); |
21198846 SC |
12623 | |
12624 | /* Free the arrays associated with the old memslot. */ | |
12625 | if (change == KVM_MR_MOVE) | |
e96c81ee | 12626 | kvm_arch_free_memslot(kvm, old); |
0de10343 | 12627 | } |
1d737c8a | 12628 | |
2df72e9b | 12629 | void kvm_arch_flush_shadow_all(struct kvm *kvm) |
34d4cb8f | 12630 | { |
7390de1e | 12631 | kvm_mmu_zap_all(kvm); |
34d4cb8f MT |
12632 | } |
12633 | ||
2df72e9b MT |
12634 | void kvm_arch_flush_shadow_memslot(struct kvm *kvm, |
12635 | struct kvm_memory_slot *slot) | |
12636 | { | |
ae7cd873 | 12637 | kvm_page_track_flush_slot(kvm, slot); |
2df72e9b MT |
12638 | } |
12639 | ||
e6c67d8c LA |
12640 | static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) |
12641 | { | |
12642 | return (is_guest_mode(vcpu) && | |
5be2226f | 12643 | static_call(kvm_x86_guest_apic_has_interrupt)(vcpu)); |
e6c67d8c LA |
12644 | } |
12645 | ||
5d9bc648 PB |
12646 | static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu) |
12647 | { | |
12648 | if (!list_empty_careful(&vcpu->async_pf.done)) | |
12649 | return true; | |
12650 | ||
12651 | if (kvm_apic_has_events(vcpu)) | |
12652 | return true; | |
12653 | ||
12654 | if (vcpu->arch.pv.pv_unhalted) | |
12655 | return true; | |
12656 | ||
a5f01f8e WL |
12657 | if (vcpu->arch.exception.pending) |
12658 | return true; | |
12659 | ||
47a66eed Z |
12660 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || |
12661 | (vcpu->arch.nmi_pending && | |
b3646477 | 12662 | static_call(kvm_x86_nmi_allowed)(vcpu, false))) |
5d9bc648 PB |
12663 | return true; |
12664 | ||
47a66eed | 12665 | if (kvm_test_request(KVM_REQ_SMI, vcpu) || |
a9fa7cb6 | 12666 | (vcpu->arch.smi_pending && |
b3646477 | 12667 | static_call(kvm_x86_smi_allowed)(vcpu, false))) |
73917739 PB |
12668 | return true; |
12669 | ||
5d9bc648 | 12670 | if (kvm_arch_interrupt_allowed(vcpu) && |
e6c67d8c LA |
12671 | (kvm_cpu_has_interrupt(vcpu) || |
12672 | kvm_guest_apic_has_interrupt(vcpu))) | |
5d9bc648 PB |
12673 | return true; |
12674 | ||
1f4b34f8 AS |
12675 | if (kvm_hv_has_stimer_pending(vcpu)) |
12676 | return true; | |
12677 | ||
d2060bd4 SC |
12678 | if (is_guest_mode(vcpu) && |
12679 | kvm_x86_ops.nested_ops->hv_timer_pending && | |
12680 | kvm_x86_ops.nested_ops->hv_timer_pending(vcpu)) | |
12681 | return true; | |
12682 | ||
7caf9571 DW |
12683 | if (kvm_xen_has_pending_events(vcpu)) |
12684 | return true; | |
12685 | ||
c9f3d9fb PB |
12686 | if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) |
12687 | return true; | |
12688 | ||
5d9bc648 PB |
12689 | return false; |
12690 | } | |
12691 | ||
1d737c8a ZX |
12692 | int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) |
12693 | { | |
5d9bc648 | 12694 | return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu); |
1d737c8a | 12695 | } |
5736199a | 12696 | |
10dbdf98 | 12697 | bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu) |
17e433b5 | 12698 | { |
ae801e13 SC |
12699 | if (kvm_vcpu_apicv_active(vcpu) && |
12700 | static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu)) | |
52acd22f WL |
12701 | return true; |
12702 | ||
12703 | return false; | |
12704 | } | |
12705 | ||
17e433b5 WL |
12706 | bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu) |
12707 | { | |
12708 | if (READ_ONCE(vcpu->arch.pv.pv_unhalted)) | |
12709 | return true; | |
12710 | ||
12711 | if (kvm_test_request(KVM_REQ_NMI, vcpu) || | |
12712 | kvm_test_request(KVM_REQ_SMI, vcpu) || | |
12713 | kvm_test_request(KVM_REQ_EVENT, vcpu)) | |
12714 | return true; | |
12715 | ||
10dbdf98 | 12716 | return kvm_arch_dy_has_pending_interrupt(vcpu); |
17e433b5 WL |
12717 | } |
12718 | ||
199b5763 LM |
12719 | bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) |
12720 | { | |
b86bb11e WL |
12721 | if (vcpu->arch.guest_state_protected) |
12722 | return true; | |
12723 | ||
de63ad4c | 12724 | return vcpu->arch.preempted_in_kernel; |
199b5763 LM |
12725 | } |
12726 | ||
e1bfc245 SC |
12727 | unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu) |
12728 | { | |
12729 | return kvm_rip_read(vcpu); | |
12730 | } | |
12731 | ||
b6d33834 | 12732 | int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) |
5736199a | 12733 | { |
b6d33834 | 12734 | return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; |
5736199a | 12735 | } |
78646121 GN |
12736 | |
12737 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu) | |
12738 | { | |
b3646477 | 12739 | return static_call(kvm_x86_interrupt_allowed)(vcpu, false); |
78646121 | 12740 | } |
229456fc | 12741 | |
82b32774 | 12742 | unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu) |
f92653ee | 12743 | { |
7ed9abfe TL |
12744 | /* Can't read the RIP when guest state is protected, just return 0 */ |
12745 | if (vcpu->arch.guest_state_protected) | |
12746 | return 0; | |
12747 | ||
82b32774 NA |
12748 | if (is_64_bit_mode(vcpu)) |
12749 | return kvm_rip_read(vcpu); | |
12750 | return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) + | |
12751 | kvm_rip_read(vcpu)); | |
12752 | } | |
12753 | EXPORT_SYMBOL_GPL(kvm_get_linear_rip); | |
f92653ee | 12754 | |
82b32774 NA |
12755 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip) |
12756 | { | |
12757 | return kvm_get_linear_rip(vcpu) == linear_rip; | |
f92653ee JK |
12758 | } |
12759 | EXPORT_SYMBOL_GPL(kvm_is_linear_rip); | |
12760 | ||
94fe45da JK |
12761 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu) |
12762 | { | |
12763 | unsigned long rflags; | |
12764 | ||
b3646477 | 12765 | rflags = static_call(kvm_x86_get_rflags)(vcpu); |
94fe45da | 12766 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) |
c310bac5 | 12767 | rflags &= ~X86_EFLAGS_TF; |
94fe45da JK |
12768 | return rflags; |
12769 | } | |
12770 | EXPORT_SYMBOL_GPL(kvm_get_rflags); | |
12771 | ||
6addfc42 | 12772 | static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) |
94fe45da JK |
12773 | { |
12774 | if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP && | |
f92653ee | 12775 | kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip)) |
c310bac5 | 12776 | rflags |= X86_EFLAGS_TF; |
b3646477 | 12777 | static_call(kvm_x86_set_rflags)(vcpu, rflags); |
6addfc42 PB |
12778 | } |
12779 | ||
12780 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
12781 | { | |
12782 | __kvm_set_rflags(vcpu, rflags); | |
3842d135 | 12783 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
94fe45da JK |
12784 | } |
12785 | EXPORT_SYMBOL_GPL(kvm_set_rflags); | |
12786 | ||
af585b92 GN |
12787 | static inline u32 kvm_async_pf_hash_fn(gfn_t gfn) |
12788 | { | |
dd03bcaa PX |
12789 | BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU)); |
12790 | ||
af585b92 GN |
12791 | return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU)); |
12792 | } | |
12793 | ||
12794 | static inline u32 kvm_async_pf_next_probe(u32 key) | |
12795 | { | |
dd03bcaa | 12796 | return (key + 1) & (ASYNC_PF_PER_VCPU - 1); |
af585b92 GN |
12797 | } |
12798 | ||
12799 | static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
12800 | { | |
12801 | u32 key = kvm_async_pf_hash_fn(gfn); | |
12802 | ||
12803 | while (vcpu->arch.apf.gfns[key] != ~0) | |
12804 | key = kvm_async_pf_next_probe(key); | |
12805 | ||
12806 | vcpu->arch.apf.gfns[key] = gfn; | |
12807 | } | |
12808 | ||
12809 | static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn) | |
12810 | { | |
12811 | int i; | |
12812 | u32 key = kvm_async_pf_hash_fn(gfn); | |
12813 | ||
dd03bcaa | 12814 | for (i = 0; i < ASYNC_PF_PER_VCPU && |
c7d28c24 XG |
12815 | (vcpu->arch.apf.gfns[key] != gfn && |
12816 | vcpu->arch.apf.gfns[key] != ~0); i++) | |
af585b92 GN |
12817 | key = kvm_async_pf_next_probe(key); |
12818 | ||
12819 | return key; | |
12820 | } | |
12821 | ||
12822 | bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
12823 | { | |
12824 | return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn; | |
12825 | } | |
12826 | ||
12827 | static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn) | |
12828 | { | |
12829 | u32 i, j, k; | |
12830 | ||
12831 | i = j = kvm_async_pf_gfn_slot(vcpu, gfn); | |
0fd46044 PX |
12832 | |
12833 | if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn)) | |
12834 | return; | |
12835 | ||
af585b92 GN |
12836 | while (true) { |
12837 | vcpu->arch.apf.gfns[i] = ~0; | |
12838 | do { | |
12839 | j = kvm_async_pf_next_probe(j); | |
12840 | if (vcpu->arch.apf.gfns[j] == ~0) | |
12841 | return; | |
12842 | k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]); | |
12843 | /* | |
12844 | * k lies cyclically in ]i,j] | |
12845 | * | i.k.j | | |
12846 | * |....j i.k.| or |.k..j i...| | |
12847 | */ | |
12848 | } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j)); | |
12849 | vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j]; | |
12850 | i = j; | |
12851 | } | |
12852 | } | |
12853 | ||
68fd66f1 | 12854 | static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu) |
7c90705b | 12855 | { |
68fd66f1 VK |
12856 | u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT; |
12857 | ||
12858 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason, | |
12859 | sizeof(reason)); | |
12860 | } | |
12861 | ||
12862 | static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token) | |
12863 | { | |
2635b5c4 | 12864 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); |
4e335d9e | 12865 | |
2635b5c4 VK |
12866 | return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, |
12867 | &token, offset, sizeof(token)); | |
12868 | } | |
12869 | ||
12870 | static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu) | |
12871 | { | |
12872 | unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token); | |
12873 | u32 val; | |
12874 | ||
12875 | if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data, | |
12876 | &val, offset, sizeof(val))) | |
12877 | return false; | |
12878 | ||
12879 | return !val; | |
7c90705b GN |
12880 | } |
12881 | ||
1dfdb45e PB |
12882 | static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu) |
12883 | { | |
57cb3bb0 PB |
12884 | |
12885 | if (!kvm_pv_async_pf_enabled(vcpu)) | |
1dfdb45e PB |
12886 | return false; |
12887 | ||
57cb3bb0 PB |
12888 | if (vcpu->arch.apf.send_user_only && |
12889 | static_call(kvm_x86_get_cpl)(vcpu) == 0) | |
1dfdb45e PB |
12890 | return false; |
12891 | ||
57cb3bb0 PB |
12892 | if (is_guest_mode(vcpu)) { |
12893 | /* | |
12894 | * L1 needs to opt into the special #PF vmexits that are | |
12895 | * used to deliver async page faults. | |
12896 | */ | |
12897 | return vcpu->arch.apf.delivery_as_pf_vmexit; | |
12898 | } else { | |
12899 | /* | |
12900 | * Play it safe in case the guest temporarily disables paging. | |
12901 | * The real mode IDT in particular is unlikely to have a #PF | |
12902 | * exception setup. | |
12903 | */ | |
12904 | return is_paging(vcpu); | |
12905 | } | |
1dfdb45e PB |
12906 | } |
12907 | ||
12908 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) | |
12909 | { | |
12910 | if (unlikely(!lapic_in_kernel(vcpu) || | |
12911 | kvm_event_needs_reinjection(vcpu) || | |
12912 | vcpu->arch.exception.pending)) | |
12913 | return false; | |
12914 | ||
12915 | if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu)) | |
12916 | return false; | |
12917 | ||
12918 | /* | |
12919 | * If interrupts are off we cannot even use an artificial | |
12920 | * halt state. | |
12921 | */ | |
c300ab9f | 12922 | return kvm_arch_interrupt_allowed(vcpu); |
1dfdb45e PB |
12923 | } |
12924 | ||
2a18b7e7 | 12925 | bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
af585b92 GN |
12926 | struct kvm_async_pf *work) |
12927 | { | |
6389ee94 AK |
12928 | struct x86_exception fault; |
12929 | ||
736c291c | 12930 | trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa); |
af585b92 | 12931 | kvm_add_async_pf_gfn(vcpu, work->arch.gfn); |
7c90705b | 12932 | |
1dfdb45e | 12933 | if (kvm_can_deliver_async_pf(vcpu) && |
68fd66f1 | 12934 | !apf_put_user_notpresent(vcpu)) { |
6389ee94 AK |
12935 | fault.vector = PF_VECTOR; |
12936 | fault.error_code_valid = true; | |
12937 | fault.error_code = 0; | |
12938 | fault.nested_page_fault = false; | |
12939 | fault.address = work->arch.token; | |
adfe20fb | 12940 | fault.async_page_fault = true; |
6389ee94 | 12941 | kvm_inject_page_fault(vcpu, &fault); |
2a18b7e7 | 12942 | return true; |
1dfdb45e PB |
12943 | } else { |
12944 | /* | |
12945 | * It is not possible to deliver a paravirtualized asynchronous | |
12946 | * page fault, but putting the guest in an artificial halt state | |
12947 | * can be beneficial nevertheless: if an interrupt arrives, we | |
12948 | * can deliver it timely and perhaps the guest will schedule | |
12949 | * another process. When the instruction that triggered a page | |
12950 | * fault is retried, hopefully the page will be ready in the host. | |
12951 | */ | |
12952 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
2a18b7e7 | 12953 | return false; |
7c90705b | 12954 | } |
af585b92 GN |
12955 | } |
12956 | ||
12957 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
12958 | struct kvm_async_pf *work) | |
12959 | { | |
2635b5c4 VK |
12960 | struct kvm_lapic_irq irq = { |
12961 | .delivery_mode = APIC_DM_FIXED, | |
12962 | .vector = vcpu->arch.apf.vec | |
12963 | }; | |
6389ee94 | 12964 | |
f2e10669 | 12965 | if (work->wakeup_all) |
7c90705b GN |
12966 | work->arch.token = ~0; /* broadcast wakeup */ |
12967 | else | |
12968 | kvm_del_async_pf_gfn(vcpu, work->arch.gfn); | |
736c291c | 12969 | trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa); |
7c90705b | 12970 | |
2a18b7e7 VK |
12971 | if ((work->wakeup_all || work->notpresent_injected) && |
12972 | kvm_pv_async_pf_enabled(vcpu) && | |
557a961a VK |
12973 | !apf_put_user_ready(vcpu, work->arch.token)) { |
12974 | vcpu->arch.apf.pageready_pending = true; | |
2635b5c4 | 12975 | kvm_apic_set_irq(vcpu, &irq, NULL); |
557a961a | 12976 | } |
2635b5c4 | 12977 | |
e6d53e3b | 12978 | vcpu->arch.apf.halted = false; |
a4fa1635 | 12979 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; |
7c90705b GN |
12980 | } |
12981 | ||
557a961a VK |
12982 | void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu) |
12983 | { | |
12984 | kvm_make_request(KVM_REQ_APF_READY, vcpu); | |
12985 | if (!vcpu->arch.apf.pageready_pending) | |
12986 | kvm_vcpu_kick(vcpu); | |
12987 | } | |
12988 | ||
7c0ade6c | 12989 | bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu) |
7c90705b | 12990 | { |
2635b5c4 | 12991 | if (!kvm_pv_async_pf_enabled(vcpu)) |
7c90705b GN |
12992 | return true; |
12993 | else | |
2f15d027 | 12994 | return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu); |
af585b92 GN |
12995 | } |
12996 | ||
5544eb9b PB |
12997 | void kvm_arch_start_assignment(struct kvm *kvm) |
12998 | { | |
57ab8794 | 12999 | if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1) |
e27bc044 | 13000 | static_call_cond(kvm_x86_pi_start_assignment)(kvm); |
5544eb9b PB |
13001 | } |
13002 | EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); | |
13003 | ||
13004 | void kvm_arch_end_assignment(struct kvm *kvm) | |
13005 | { | |
13006 | atomic_dec(&kvm->arch.assigned_device_count); | |
13007 | } | |
13008 | EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); | |
13009 | ||
742ab6df | 13010 | bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm) |
5544eb9b | 13011 | { |
742ab6df | 13012 | return arch_atomic_read(&kvm->arch.assigned_device_count); |
5544eb9b PB |
13013 | } |
13014 | EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); | |
13015 | ||
e0f0bbc5 AW |
13016 | void kvm_arch_register_noncoherent_dma(struct kvm *kvm) |
13017 | { | |
13018 | atomic_inc(&kvm->arch.noncoherent_dma_count); | |
13019 | } | |
13020 | EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma); | |
13021 | ||
13022 | void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm) | |
13023 | { | |
13024 | atomic_dec(&kvm->arch.noncoherent_dma_count); | |
13025 | } | |
13026 | EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma); | |
13027 | ||
13028 | bool kvm_arch_has_noncoherent_dma(struct kvm *kvm) | |
13029 | { | |
13030 | return atomic_read(&kvm->arch.noncoherent_dma_count); | |
13031 | } | |
13032 | EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma); | |
13033 | ||
14717e20 AW |
13034 | bool kvm_arch_has_irq_bypass(void) |
13035 | { | |
92735b1b | 13036 | return true; |
14717e20 AW |
13037 | } |
13038 | ||
87276880 FW |
13039 | int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, |
13040 | struct irq_bypass_producer *prod) | |
13041 | { | |
13042 | struct kvm_kernel_irqfd *irqfd = | |
13043 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
2edd9cb7 | 13044 | int ret; |
87276880 | 13045 | |
14717e20 | 13046 | irqfd->producer = prod; |
2edd9cb7 | 13047 | kvm_arch_start_assignment(irqfd->kvm); |
e27bc044 | 13048 | ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, |
2edd9cb7 ZL |
13049 | prod->irq, irqfd->gsi, 1); |
13050 | ||
13051 | if (ret) | |
13052 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 | 13053 | |
2edd9cb7 | 13054 | return ret; |
87276880 FW |
13055 | } |
13056 | ||
13057 | void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, | |
13058 | struct irq_bypass_producer *prod) | |
13059 | { | |
13060 | int ret; | |
13061 | struct kvm_kernel_irqfd *irqfd = | |
13062 | container_of(cons, struct kvm_kernel_irqfd, consumer); | |
13063 | ||
87276880 FW |
13064 | WARN_ON(irqfd->producer != prod); |
13065 | irqfd->producer = NULL; | |
13066 | ||
13067 | /* | |
13068 | * When producer of consumer is unregistered, we change back to | |
13069 | * remapped mode, so we can re-use the current implementation | |
bb3541f1 | 13070 | * when the irq is masked/disabled or the consumer side (KVM |
87276880 FW |
13071 | * int this case doesn't want to receive the interrupts. |
13072 | */ | |
e27bc044 | 13073 | ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); |
87276880 FW |
13074 | if (ret) |
13075 | printk(KERN_INFO "irq bypass consumer (token %p) unregistration" | |
13076 | " fails: %d\n", irqfd->consumer.token, ret); | |
2edd9cb7 ZL |
13077 | |
13078 | kvm_arch_end_assignment(irqfd->kvm); | |
87276880 FW |
13079 | } |
13080 | ||
13081 | int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, | |
13082 | uint32_t guest_irq, bool set) | |
13083 | { | |
e27bc044 | 13084 | return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set); |
87276880 FW |
13085 | } |
13086 | ||
515a0c79 LM |
13087 | bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, |
13088 | struct kvm_kernel_irq_routing_entry *new) | |
13089 | { | |
13090 | if (new->type != KVM_IRQ_ROUTING_MSI) | |
13091 | return true; | |
13092 | ||
13093 | return !!memcmp(&old->msi, &new->msi, sizeof(new->msi)); | |
13094 | } | |
13095 | ||
52004014 FW |
13096 | bool kvm_vector_hashing_enabled(void) |
13097 | { | |
13098 | return vector_hashing; | |
13099 | } | |
52004014 | 13100 | |
2d5ba19b MT |
13101 | bool kvm_arch_no_poll(struct kvm_vcpu *vcpu) |
13102 | { | |
13103 | return (vcpu->arch.msr_kvm_poll_control & 1) == 0; | |
13104 | } | |
13105 | EXPORT_SYMBOL_GPL(kvm_arch_no_poll); | |
13106 | ||
841c2be0 ML |
13107 | |
13108 | int kvm_spec_ctrl_test_value(u64 value) | |
6441fa61 | 13109 | { |
841c2be0 ML |
13110 | /* |
13111 | * test that setting IA32_SPEC_CTRL to given value | |
13112 | * is allowed by the host processor | |
13113 | */ | |
6441fa61 | 13114 | |
841c2be0 ML |
13115 | u64 saved_value; |
13116 | unsigned long flags; | |
13117 | int ret = 0; | |
6441fa61 | 13118 | |
841c2be0 | 13119 | local_irq_save(flags); |
6441fa61 | 13120 | |
841c2be0 ML |
13121 | if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value)) |
13122 | ret = 1; | |
13123 | else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value)) | |
13124 | ret = 1; | |
13125 | else | |
13126 | wrmsrl(MSR_IA32_SPEC_CTRL, saved_value); | |
6441fa61 | 13127 | |
841c2be0 | 13128 | local_irq_restore(flags); |
6441fa61 | 13129 | |
841c2be0 | 13130 | return ret; |
6441fa61 | 13131 | } |
841c2be0 | 13132 | EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value); |
2d5ba19b | 13133 | |
89786147 MG |
13134 | void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code) |
13135 | { | |
1f5a21ee | 13136 | struct kvm_mmu *mmu = vcpu->arch.walk_mmu; |
89786147 | 13137 | struct x86_exception fault; |
5b22bbe7 | 13138 | u64 access = error_code & |
19cf4b7e | 13139 | (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK); |
89786147 MG |
13140 | |
13141 | if (!(error_code & PFERR_PRESENT_MASK) || | |
6e1d2a3f | 13142 | mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) { |
89786147 MG |
13143 | /* |
13144 | * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page | |
13145 | * tables probably do not match the TLB. Just proceed | |
13146 | * with the error code that the processor gave. | |
13147 | */ | |
13148 | fault.vector = PF_VECTOR; | |
13149 | fault.error_code_valid = true; | |
13150 | fault.error_code = error_code; | |
13151 | fault.nested_page_fault = false; | |
13152 | fault.address = gva; | |
2bc685e6 | 13153 | fault.async_page_fault = false; |
89786147 MG |
13154 | } |
13155 | vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault); | |
6441fa61 | 13156 | } |
89786147 | 13157 | EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error); |
2d5ba19b | 13158 | |
3f3393b3 BM |
13159 | /* |
13160 | * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns | |
13161 | * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value | |
13162 | * indicates whether exit to userspace is needed. | |
13163 | */ | |
13164 | int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r, | |
13165 | struct x86_exception *e) | |
13166 | { | |
13167 | if (r == X86EMUL_PROPAGATE_FAULT) { | |
13168 | kvm_inject_emulated_page_fault(vcpu, e); | |
13169 | return 1; | |
13170 | } | |
13171 | ||
13172 | /* | |
13173 | * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED | |
13174 | * while handling a VMX instruction KVM could've handled the request | |
13175 | * correctly by exiting to userspace and performing I/O but there | |
13176 | * doesn't seem to be a real use-case behind such requests, just return | |
13177 | * KVM_EXIT_INTERNAL_ERROR for now. | |
13178 | */ | |
e615e355 | 13179 | kvm_prepare_emulation_failure_exit(vcpu); |
3f3393b3 BM |
13180 | |
13181 | return 0; | |
13182 | } | |
13183 | EXPORT_SYMBOL_GPL(kvm_handle_memory_failure); | |
13184 | ||
9715092f BM |
13185 | int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva) |
13186 | { | |
13187 | bool pcid_enabled; | |
13188 | struct x86_exception e; | |
9715092f BM |
13189 | struct { |
13190 | u64 pcid; | |
13191 | u64 gla; | |
13192 | } operand; | |
13193 | int r; | |
13194 | ||
13195 | r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); | |
13196 | if (r != X86EMUL_CONTINUE) | |
13197 | return kvm_handle_memory_failure(vcpu, r, &e); | |
13198 | ||
13199 | if (operand.pcid >> 12 != 0) { | |
13200 | kvm_inject_gp(vcpu, 0); | |
13201 | return 1; | |
13202 | } | |
13203 | ||
13204 | pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); | |
13205 | ||
13206 | switch (type) { | |
13207 | case INVPCID_TYPE_INDIV_ADDR: | |
13208 | if ((!pcid_enabled && (operand.pcid != 0)) || | |
13209 | is_noncanonical_address(operand.gla, vcpu)) { | |
13210 | kvm_inject_gp(vcpu, 0); | |
13211 | return 1; | |
13212 | } | |
13213 | kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); | |
13214 | return kvm_skip_emulated_instruction(vcpu); | |
13215 | ||
13216 | case INVPCID_TYPE_SINGLE_CTXT: | |
13217 | if (!pcid_enabled && (operand.pcid != 0)) { | |
13218 | kvm_inject_gp(vcpu, 0); | |
13219 | return 1; | |
13220 | } | |
13221 | ||
21823fbd | 13222 | kvm_invalidate_pcid(vcpu, operand.pcid); |
9715092f BM |
13223 | return kvm_skip_emulated_instruction(vcpu); |
13224 | ||
13225 | case INVPCID_TYPE_ALL_NON_GLOBAL: | |
13226 | /* | |
13227 | * Currently, KVM doesn't mark global entries in the shadow | |
13228 | * page tables, so a non-global flush just degenerates to a | |
13229 | * global flush. If needed, we could optimize this later by | |
13230 | * keeping track of global entries in shadow page tables. | |
13231 | */ | |
13232 | ||
13233 | fallthrough; | |
13234 | case INVPCID_TYPE_ALL_INCL_GLOBAL: | |
28f28d45 | 13235 | kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu); |
9715092f BM |
13236 | return kvm_skip_emulated_instruction(vcpu); |
13237 | ||
13238 | default: | |
796c83c5 VS |
13239 | kvm_inject_gp(vcpu, 0); |
13240 | return 1; | |
9715092f BM |
13241 | } |
13242 | } | |
13243 | EXPORT_SYMBOL_GPL(kvm_handle_invpcid); | |
13244 | ||
8f423a80 TL |
13245 | static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu) |
13246 | { | |
13247 | struct kvm_run *run = vcpu->run; | |
13248 | struct kvm_mmio_fragment *frag; | |
13249 | unsigned int len; | |
13250 | ||
13251 | BUG_ON(!vcpu->mmio_needed); | |
13252 | ||
13253 | /* Complete previous fragment */ | |
13254 | frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment]; | |
13255 | len = min(8u, frag->len); | |
13256 | if (!vcpu->mmio_is_write) | |
13257 | memcpy(frag->data, run->mmio.data, len); | |
13258 | ||
13259 | if (frag->len <= 8) { | |
13260 | /* Switch to the next fragment. */ | |
13261 | frag++; | |
13262 | vcpu->mmio_cur_fragment++; | |
13263 | } else { | |
13264 | /* Go forward to the next mmio piece. */ | |
13265 | frag->data += len; | |
13266 | frag->gpa += len; | |
13267 | frag->len -= len; | |
13268 | } | |
13269 | ||
13270 | if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) { | |
13271 | vcpu->mmio_needed = 0; | |
13272 | ||
13273 | // VMG change, at this point, we're always done | |
13274 | // RIP has already been advanced | |
13275 | return 1; | |
13276 | } | |
13277 | ||
13278 | // More MMIO is needed | |
13279 | run->mmio.phys_addr = frag->gpa; | |
13280 | run->mmio.len = min(8u, frag->len); | |
13281 | run->mmio.is_write = vcpu->mmio_is_write; | |
13282 | if (run->mmio.is_write) | |
13283 | memcpy(run->mmio.data, frag->data, min(8u, frag->len)); | |
13284 | run->exit_reason = KVM_EXIT_MMIO; | |
13285 | ||
13286 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
13287 | ||
13288 | return 0; | |
13289 | } | |
13290 | ||
13291 | int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
13292 | void *data) | |
13293 | { | |
13294 | int handled; | |
13295 | struct kvm_mmio_fragment *frag; | |
13296 | ||
13297 | if (!data) | |
13298 | return -EINVAL; | |
13299 | ||
13300 | handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
13301 | if (handled == bytes) | |
13302 | return 1; | |
13303 | ||
13304 | bytes -= handled; | |
13305 | gpa += handled; | |
13306 | data += handled; | |
13307 | ||
13308 | /*TODO: Check if need to increment number of frags */ | |
13309 | frag = vcpu->mmio_fragments; | |
13310 | vcpu->mmio_nr_fragments = 1; | |
13311 | frag->len = bytes; | |
13312 | frag->gpa = gpa; | |
13313 | frag->data = data; | |
13314 | ||
13315 | vcpu->mmio_needed = 1; | |
13316 | vcpu->mmio_cur_fragment = 0; | |
13317 | ||
13318 | vcpu->run->mmio.phys_addr = gpa; | |
13319 | vcpu->run->mmio.len = min(8u, frag->len); | |
13320 | vcpu->run->mmio.is_write = 1; | |
13321 | memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len)); | |
13322 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
13323 | ||
13324 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
13325 | ||
13326 | return 0; | |
13327 | } | |
13328 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write); | |
13329 | ||
13330 | int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes, | |
13331 | void *data) | |
13332 | { | |
13333 | int handled; | |
13334 | struct kvm_mmio_fragment *frag; | |
13335 | ||
13336 | if (!data) | |
13337 | return -EINVAL; | |
13338 | ||
13339 | handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data); | |
13340 | if (handled == bytes) | |
13341 | return 1; | |
13342 | ||
13343 | bytes -= handled; | |
13344 | gpa += handled; | |
13345 | data += handled; | |
13346 | ||
13347 | /*TODO: Check if need to increment number of frags */ | |
13348 | frag = vcpu->mmio_fragments; | |
13349 | vcpu->mmio_nr_fragments = 1; | |
13350 | frag->len = bytes; | |
13351 | frag->gpa = gpa; | |
13352 | frag->data = data; | |
13353 | ||
13354 | vcpu->mmio_needed = 1; | |
13355 | vcpu->mmio_cur_fragment = 0; | |
13356 | ||
13357 | vcpu->run->mmio.phys_addr = gpa; | |
13358 | vcpu->run->mmio.len = min(8u, frag->len); | |
13359 | vcpu->run->mmio.is_write = 0; | |
13360 | vcpu->run->exit_reason = KVM_EXIT_MMIO; | |
13361 | ||
13362 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio; | |
13363 | ||
13364 | return 0; | |
13365 | } | |
13366 | EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read); | |
13367 | ||
db209369 PB |
13368 | static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size) |
13369 | { | |
13370 | vcpu->arch.sev_pio_count -= count; | |
13371 | vcpu->arch.sev_pio_data += count * size; | |
13372 | } | |
13373 | ||
7ed9abfe | 13374 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, |
95e16b47 PB |
13375 | unsigned int port); |
13376 | ||
13377 | static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu) | |
7ed9abfe | 13378 | { |
95e16b47 PB |
13379 | int size = vcpu->arch.pio.size; |
13380 | int port = vcpu->arch.pio.port; | |
13381 | ||
13382 | vcpu->arch.pio.count = 0; | |
13383 | if (vcpu->arch.sev_pio_count) | |
13384 | return kvm_sev_es_outs(vcpu, size, port); | |
13385 | return 1; | |
13386 | } | |
13387 | ||
13388 | static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size, | |
13389 | unsigned int port) | |
13390 | { | |
13391 | for (;;) { | |
13392 | unsigned int count = | |
13393 | min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); | |
13394 | int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count); | |
13395 | ||
13396 | /* memcpy done already by emulator_pio_out. */ | |
db209369 | 13397 | advance_sev_es_emulated_pio(vcpu, count, size); |
95e16b47 PB |
13398 | if (!ret) |
13399 | break; | |
7ed9abfe | 13400 | |
ea724ea4 | 13401 | /* Emulation done by the kernel. */ |
95e16b47 PB |
13402 | if (!vcpu->arch.sev_pio_count) |
13403 | return 1; | |
ea724ea4 | 13404 | } |
7ed9abfe | 13405 | |
95e16b47 | 13406 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs; |
7ed9abfe TL |
13407 | return 0; |
13408 | } | |
13409 | ||
95e16b47 PB |
13410 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, |
13411 | unsigned int port); | |
13412 | ||
4fa4b38d PB |
13413 | static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu) |
13414 | { | |
0c05e10b | 13415 | unsigned count = vcpu->arch.pio.count; |
95e16b47 PB |
13416 | int size = vcpu->arch.pio.size; |
13417 | int port = vcpu->arch.pio.port; | |
4fa4b38d | 13418 | |
0c05e10b | 13419 | complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data); |
db209369 | 13420 | advance_sev_es_emulated_pio(vcpu, count, size); |
95e16b47 PB |
13421 | if (vcpu->arch.sev_pio_count) |
13422 | return kvm_sev_es_ins(vcpu, size, port); | |
4fa4b38d PB |
13423 | return 1; |
13424 | } | |
13425 | ||
7ed9abfe | 13426 | static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size, |
95e16b47 | 13427 | unsigned int port) |
7ed9abfe | 13428 | { |
95e16b47 PB |
13429 | for (;;) { |
13430 | unsigned int count = | |
13431 | min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count); | |
f35cee4a | 13432 | if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count)) |
95e16b47 | 13433 | break; |
7ed9abfe | 13434 | |
ea724ea4 | 13435 | /* Emulation done by the kernel. */ |
db209369 | 13436 | advance_sev_es_emulated_pio(vcpu, count, size); |
95e16b47 PB |
13437 | if (!vcpu->arch.sev_pio_count) |
13438 | return 1; | |
7ed9abfe TL |
13439 | } |
13440 | ||
ea724ea4 | 13441 | vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins; |
7ed9abfe TL |
13442 | return 0; |
13443 | } | |
13444 | ||
13445 | int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size, | |
13446 | unsigned int port, void *data, unsigned int count, | |
13447 | int in) | |
13448 | { | |
ea724ea4 | 13449 | vcpu->arch.sev_pio_data = data; |
95e16b47 PB |
13450 | vcpu->arch.sev_pio_count = count; |
13451 | return in ? kvm_sev_es_ins(vcpu, size, port) | |
13452 | : kvm_sev_es_outs(vcpu, size, port); | |
7ed9abfe TL |
13453 | } |
13454 | EXPORT_SYMBOL_GPL(kvm_sev_es_string_io); | |
13455 | ||
d95df951 | 13456 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry); |
229456fc | 13457 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); |
931c33b1 | 13458 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); |
229456fc MT |
13459 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); |
13460 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault); | |
13461 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr); | |
13462 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr); | |
89e54ec5 | 13463 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter); |
d8cabddf | 13464 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit); |
17897f36 | 13465 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject); |
236649de | 13466 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit); |
5497b955 | 13467 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed); |
ec1ff790 | 13468 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga); |
532a46b9 | 13469 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit); |
2e554e8d | 13470 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); |
489223ed | 13471 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); |
4f75bcc3 | 13472 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); |
843e4330 | 13473 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); |
efc64404 | 13474 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); |
18f40c53 SS |
13475 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); |
13476 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi); | |
ab56f8e6 | 13477 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log); |
9f084f7c | 13478 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath); |
39b6b8c3 | 13479 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell); |
8e819d75 | 13480 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq); |
d523ab6b TL |
13481 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter); |
13482 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit); | |
59e38b58 TL |
13483 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter); |
13484 | EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit); | |
1d0e8480 SC |
13485 | |
13486 | static int __init kvm_x86_init(void) | |
13487 | { | |
13488 | kvm_mmu_x86_module_init(); | |
13489 | return 0; | |
13490 | } | |
13491 | module_init(kvm_x86_init); | |
13492 | ||
13493 | static void __exit kvm_x86_exit(void) | |
13494 | { | |
13495 | /* | |
13496 | * If module_init() is implemented, module_exit() must also be | |
13497 | * implemented to allow module unload. | |
13498 | */ | |
13499 | } | |
13500 | module_exit(kvm_x86_exit); |