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KVM: selftests: exit with 0 status code when tests cannot be run
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
9ed96e87
MT		 117unsigned int min_timer_period_us = 500;
118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
141
52004014
FW		 142static bool __read_mostly vector_hashing = true;
143module_param(vector_hashing, bool, S_IRUGO);
144
c4ae60e4
LA		 145bool __read_mostly enable_vmware_backdoor = false;
146module_param(enable_vmware_backdoor, bool, S_IRUGO);
147EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
148
6c86eedc
WL		 149static bool __read_mostly force_emulation_prefix = false;
150module_param(force_emulation_prefix, bool, S_IRUGO);
151
18863bdd
AK		 152#define KVM_NR_SHARED_MSRS 16
153
154struct kvm_shared_msrs_global {
155 int nr;
2bf78fa7 156 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 157};
158
159struct kvm_shared_msrs {
160 struct user_return_notifier urn;
161 bool registered;
2bf78fa7
SY		 162 struct kvm_shared_msr_values {
163 u64 host;
164 u64 curr;
165 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 166};
167
168static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 169static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 170
417bc304 171struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 172 { "pf_fixed", VCPU_STAT(pf_fixed) },
173 { "pf_guest", VCPU_STAT(pf_guest) },
174 { "tlb_flush", VCPU_STAT(tlb_flush) },
175 { "invlpg", VCPU_STAT(invlpg) },
176 { "exits", VCPU_STAT(exits) },
177 { "io_exits", VCPU_STAT(io_exits) },
178 { "mmio_exits", VCPU_STAT(mmio_exits) },
179 { "signal_exits", VCPU_STAT(signal_exits) },
180 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 181 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 182 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 183 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 184 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 185 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 186 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 187 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 188 { "request_irq", VCPU_STAT(request_irq_exits) },
189 { "irq_exits", VCPU_STAT(irq_exits) },
190 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 191 { "fpu_reload", VCPU_STAT(fpu_reload) },
192 { "insn_emulation", VCPU_STAT(insn_emulation) },
193 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 194 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 195 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 196 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 197 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
198 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
199 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
200 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
201 { "mmu_flooded", VM_STAT(mmu_flooded) },
202 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 203 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 204 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 205 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 206 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 207 { "max_mmu_page_hash_collisions",
208 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 209 { NULL }
210};
211
2acf923e
DC		 212u64 __read_mostly host_xcr0;
213
b6785def 214static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 215
af585b92
GN		 216static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
217{
218 int i;
219 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
220 vcpu->arch.apf.gfns[i] = ~0;
221}
222
18863bdd
AK		 223static void kvm_on_user_return(struct user_return_notifier *urn)
224{
225 unsigned slot;
18863bdd
AK		 226 struct kvm_shared_msrs *locals
227 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 228 struct kvm_shared_msr_values *values;
1650b4eb
IA		 229 unsigned long flags;
230
231 /*
232 * Disabling irqs at this point since the following code could be
233 * interrupted and executed through kvm_arch_hardware_disable()
234 */
235 local_irq_save(flags);
236 if (locals->registered) {
237 locals->registered = false;
238 user_return_notifier_unregister(urn);
239 }
240 local_irq_restore(flags);
18863bdd 241 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 242 values = &locals->values[slot];
243 if (values->host != values->curr) {
244 wrmsrl(shared_msrs_global.msrs[slot], values->host);
245 values->curr = values->host;
18863bdd
AK		 246 }
247 }
18863bdd
AK		 248}
249
2bf78fa7 250static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 251{
18863bdd 252 u64 value;
013f6a5d
MT		 253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 255
2bf78fa7
SY		 256 /* only read, and nobody should modify it at this time,
257 * so don't need lock */
258 if (slot >= shared_msrs_global.nr) {
259 printk(KERN_ERR "kvm: invalid MSR slot!");
260 return;
261 }
262 rdmsrl_safe(msr, &value);
263 smsr->values[slot].host = value;
264 smsr->values[slot].curr = value;
265}
266
267void kvm_define_shared_msr(unsigned slot, u32 msr)
268{
0123be42 269 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 270 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 271 if (slot >= shared_msrs_global.nr)
272 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 273}
274EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
275
276static void kvm_shared_msr_cpu_online(void)
277{
278 unsigned i;
18863bdd
AK		 279
280 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 281 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 282}
283
8b3c3104 284int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 285{
013f6a5d
MT		 286 unsigned int cpu = smp_processor_id();
287 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 288 int err;
18863bdd 289
2bf78fa7 290 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 291 return 0;
2bf78fa7 292 smsr->values[slot].curr = value;
8b3c3104
AH		 293 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
294 if (err)
295 return 1;
296
18863bdd
AK		 297 if (!smsr->registered) {
298 smsr->urn.on_user_return = kvm_on_user_return;
299 user_return_notifier_register(&smsr->urn);
300 smsr->registered = true;
301 }
8b3c3104 302 return 0;
18863bdd
AK		 303}
304EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
305
13a34e06 306static void drop_user_return_notifiers(void)
3548bab5 307{
013f6a5d
MT		 308 unsigned int cpu = smp_processor_id();
309 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 310
311 if (smsr->registered)
312 kvm_on_user_return(&smsr->urn);
313}
314
6866b83e
CO		 315u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
316{
8a5a87d9 317 return vcpu->arch.apic_base;
6866b83e
CO		 318}
319EXPORT_SYMBOL_GPL(kvm_get_apic_base);
320
58cb628d
JK		 321int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
322{
323 u64 old_state = vcpu->arch.apic_base &
324 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
325 u64 new_state = msr_info->data &
326 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 327 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
328 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 329
d3802286
JM		 330 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
331 return 1;
58cb628d 332 if (!msr_info->host_initiated &&
d3802286 333 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 334 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
335 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
336 old_state == 0)))
337 return 1;
338
339 kvm_lapic_set_base(vcpu, msr_info->data);
340 return 0;
6866b83e
CO		 341}
342EXPORT_SYMBOL_GPL(kvm_set_apic_base);
343
2605fc21 344asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 345{
346 /* Fault while not rebooting. We want the trace. */
347 BUG();
348}
349EXPORT_SYMBOL_GPL(kvm_spurious_fault);
350
3fd28fce
ED		 351#define EXCPT_BENIGN 0
352#define EXCPT_CONTRIBUTORY 1
353#define EXCPT_PF 2
354
355static int exception_class(int vector)
356{
357 switch (vector) {
358 case PF_VECTOR:
359 return EXCPT_PF;
360 case DE_VECTOR:
361 case TS_VECTOR:
362 case NP_VECTOR:
363 case SS_VECTOR:
364 case GP_VECTOR:
365 return EXCPT_CONTRIBUTORY;
366 default:
367 break;
368 }
369 return EXCPT_BENIGN;
370}
371
d6e8c854
NA		 372#define EXCPT_FAULT 0
373#define EXCPT_TRAP 1
374#define EXCPT_ABORT 2
375#define EXCPT_INTERRUPT 3
376
377static int exception_type(int vector)
378{
379 unsigned int mask;
380
381 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
382 return EXCPT_INTERRUPT;
383
384 mask = 1 << vector;
385
386 /* #DB is trap, as instruction watchpoints are handled elsewhere */
387 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
388 return EXCPT_TRAP;
389
390 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
391 return EXCPT_ABORT;
392
393 /* Reserved exceptions will result in fault */
394 return EXCPT_FAULT;
395}
396
3fd28fce 397static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 398 unsigned nr, bool has_error, u32 error_code,
399 bool reinject)
3fd28fce
ED		 400{
401 u32 prev_nr;
402 int class1, class2;
403
3842d135
AK		 404 kvm_make_request(KVM_REQ_EVENT, vcpu);
405
664f8e26 406 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 407 queue:
3ffb2468
NA		 408 if (has_error && !is_protmode(vcpu))
409 has_error = false;
664f8e26
WL		 410 if (reinject) {
411 /*
412 * On vmentry, vcpu->arch.exception.pending is only
413 * true if an event injection was blocked by
414 * nested_run_pending. In that case, however,
415 * vcpu_enter_guest requests an immediate exit,
416 * and the guest shouldn't proceed far enough to
417 * need reinjection.
418 */
419 WARN_ON_ONCE(vcpu->arch.exception.pending);
420 vcpu->arch.exception.injected = true;
421 } else {
422 vcpu->arch.exception.pending = true;
423 vcpu->arch.exception.injected = false;
424 }
3fd28fce
ED		 425 vcpu->arch.exception.has_error_code = has_error;
426 vcpu->arch.exception.nr = nr;
427 vcpu->arch.exception.error_code = error_code;
428 return;
429 }
430
431 /* to check exception */
432 prev_nr = vcpu->arch.exception.nr;
433 if (prev_nr == DF_VECTOR) {
434 /* triple fault -> shutdown */
a8eeb04a 435 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 436 return;
437 }
438 class1 = exception_class(prev_nr);
439 class2 = exception_class(nr);
440 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
441 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 442 /*
443 * Generate double fault per SDM Table 5-5. Set
444 * exception.pending = true so that the double fault
445 * can trigger a nested vmexit.
446 */
3fd28fce 447 vcpu->arch.exception.pending = true;
664f8e26 448 vcpu->arch.exception.injected = false;
3fd28fce
ED		 449 vcpu->arch.exception.has_error_code = true;
450 vcpu->arch.exception.nr = DF_VECTOR;
451 vcpu->arch.exception.error_code = 0;
452 } else
453 /* replace previous exception with a new one in a hope
454 that instruction re-execution will regenerate lost
455 exception */
456 goto queue;
457}
458
298101da
AK		 459void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
460{
ce7ddec4 461 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 462}
463EXPORT_SYMBOL_GPL(kvm_queue_exception);
464
ce7ddec4
JR		 465void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
466{
467 kvm_multiple_exception(vcpu, nr, false, 0, true);
468}
469EXPORT_SYMBOL_GPL(kvm_requeue_exception);
470
6affcbed 471int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 472{
db8fcefa
AP		 473 if (err)
474 kvm_inject_gp(vcpu, 0);
475 else
6affcbed
KH		 476 return kvm_skip_emulated_instruction(vcpu);
477
478 return 1;
db8fcefa
AP		 479}
480EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 481
6389ee94 482void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 483{
484 ++vcpu->stat.pf_guest;
adfe20fb
WL		 485 vcpu->arch.exception.nested_apf =
486 is_guest_mode(vcpu) && fault->async_page_fault;
487 if (vcpu->arch.exception.nested_apf)
488 vcpu->arch.apf.nested_apf_token = fault->address;
489 else
490 vcpu->arch.cr2 = fault->address;
6389ee94 491 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 492}
27d6c865 493EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 494
ef54bcfe 495static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 496{
6389ee94
AK		 497 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
498 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 499 else
6389ee94 500 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 501
502 return fault->nested_page_fault;
d4f8cf66
JR		 503}
504
3419ffc8
SY		 505void kvm_inject_nmi(struct kvm_vcpu *vcpu)
506{
7460fb4a
AK		 507 atomic_inc(&vcpu->arch.nmi_queued);
508 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 509}
510EXPORT_SYMBOL_GPL(kvm_inject_nmi);
511
298101da
AK		 512void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
513{
ce7ddec4 514 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 515}
516EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
517
ce7ddec4
JR		 518void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
519{
520 kvm_multiple_exception(vcpu, nr, true, error_code, true);
521}
522EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
523
0a79b009
AK		 524/*
525 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
526 * a #GP and return false.
527 */
528bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 529{
0a79b009
AK		 530 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
531 return true;
532 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
533 return false;
298101da 534}
0a79b009 535EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 536
16f8a6f9
NA		 537bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
538{
539 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
540 return true;
541
542 kvm_queue_exception(vcpu, UD_VECTOR);
543 return false;
544}
545EXPORT_SYMBOL_GPL(kvm_require_dr);
546
ec92fe44
JR		 547/*
548 * This function will be used to read from the physical memory of the currently
54bf36aa 549 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 550 * can read from guest physical or from the guest's guest physical memory.
551 */
552int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
553 gfn_t ngfn, void *data, int offset, int len,
554 u32 access)
555{
54987b7a 556 struct x86_exception exception;
ec92fe44
JR		 557 gfn_t real_gfn;
558 gpa_t ngpa;
559
560 ngpa = gfn_to_gpa(ngfn);
54987b7a 561 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 562 if (real_gfn == UNMAPPED_GVA)
563 return -EFAULT;
564
565 real_gfn = gpa_to_gfn(real_gfn);
566
54bf36aa 567 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 568}
569EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
570
69b0049a 571static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 572 void *data, int offset, int len, u32 access)
573{
574 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
575 data, offset, len, access);
576}
577
a03490ed
CO		 578/*
579 * Load the pae pdptrs. Return true is they are all valid.
580 */
ff03a073 581int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 582{
583 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
584 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
585 int i;
586 int ret;
ff03a073 587 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 588
ff03a073
JR		 589 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
590 offset * sizeof(u64), sizeof(pdpte),
591 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 592 if (ret < 0) {
593 ret = 0;
594 goto out;
595 }
596 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 597 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 598 (pdpte[i] &
599 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 600 ret = 0;
601 goto out;
602 }
603 }
604 ret = 1;
605
ff03a073 606 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 607 __set_bit(VCPU_EXREG_PDPTR,
608 (unsigned long *)&vcpu->arch.regs_avail);
609 __set_bit(VCPU_EXREG_PDPTR,
610 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 611out:
a03490ed
CO		 612
613 return ret;
614}
cc4b6871 615EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 616
9ed38ffa 617bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 618{
ff03a073 619 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 620 bool changed = true;
3d06b8bf
JR		 621 int offset;
622 gfn_t gfn;
d835dfec
AK		 623 int r;
624
625 if (is_long_mode(vcpu) || !is_pae(vcpu))
626 return false;
627
6de4f3ad
AK		 628 if (!test_bit(VCPU_EXREG_PDPTR,
629 (unsigned long *)&vcpu->arch.regs_avail))
630 return true;
631
a512177e
PB		 632 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
633 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 634 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
635 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 636 if (r < 0)
637 goto out;
ff03a073 638 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 639out:
d835dfec
AK		 640
641 return changed;
642}
9ed38ffa 643EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 644
49a9b07e 645int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 646{
aad82703 647 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 648 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 649
f9a48e6a
AK		 650 cr0 |= X86_CR0_ET;
651
ab344828 652#ifdef CONFIG_X86_64
0f12244f
GN		 653 if (cr0 & 0xffffffff00000000UL)
654 return 1;
ab344828
GN		 655#endif
656
657 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 658
0f12244f
GN		 659 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
660 return 1;
a03490ed 661
0f12244f
GN		 662 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
663 return 1;
a03490ed
CO		 664
665 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
666#ifdef CONFIG_X86_64
f6801dff 667 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 668 int cs_db, cs_l;
669
0f12244f
GN		 670 if (!is_pae(vcpu))
671 return 1;
a03490ed 672 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 673 if (cs_l)
674 return 1;
a03490ed
CO		 675 } else
676#endif
ff03a073 677 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 678 kvm_read_cr3(vcpu)))
0f12244f 679 return 1;
a03490ed
CO		 680 }
681
ad756a16
MJ		 682 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
683 return 1;
684
a03490ed 685 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 686
d170c419 687 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 688 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 689 kvm_async_pf_hash_reset(vcpu);
690 }
e5f3f027 691
aad82703
SY		 692 if ((cr0 ^ old_cr0) & update_bits)
693 kvm_mmu_reset_context(vcpu);
b18d5431 694
879ae188
LE		 695 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
696 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
697 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 698 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
699
0f12244f
GN		 700 return 0;
701}
2d3ad1f4 702EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 703
2d3ad1f4 704void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 705{
49a9b07e 706 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 707}
2d3ad1f4 708EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 709
42bdf991
MT		 710static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
711{
712 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
713 !vcpu->guest_xcr0_loaded) {
714 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 715 if (vcpu->arch.xcr0 != host_xcr0)
716 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 717 vcpu->guest_xcr0_loaded = 1;
718 }
719}
720
721static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
722{
723 if (vcpu->guest_xcr0_loaded) {
724 if (vcpu->arch.xcr0 != host_xcr0)
725 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
726 vcpu->guest_xcr0_loaded = 0;
727 }
728}
729
69b0049a 730static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 731{
56c103ec
LJ		 732 u64 xcr0 = xcr;
733 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 734 u64 valid_bits;
2acf923e
DC		 735
736 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
737 if (index != XCR_XFEATURE_ENABLED_MASK)
738 return 1;
d91cab78 739 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 740 return 1;
d91cab78 741 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 742 return 1;
46c34cb0
PB		 743
744 /*
745 * Do not allow the guest to set bits that we do not support
746 * saving. However, xcr0 bit 0 is always set, even if the
747 * emulated CPU does not support XSAVE (see fx_init).
748 */
d91cab78 749 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 750 if (xcr0 & ~valid_bits)
2acf923e 751 return 1;
46c34cb0 752
d91cab78
DH		 753 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
754 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 755 return 1;
756
d91cab78
DH		 757 if (xcr0 & XFEATURE_MASK_AVX512) {
758 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 759 return 1;
d91cab78 760 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 761 return 1;
762 }
2acf923e 763 vcpu->arch.xcr0 = xcr0;
56c103ec 764
d91cab78 765 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 766 kvm_update_cpuid(vcpu);
2acf923e
DC		 767 return 0;
768}
769
770int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
771{
764bcbc5
Z		 772 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
773 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 774 kvm_inject_gp(vcpu, 0);
775 return 1;
776 }
777 return 0;
778}
779EXPORT_SYMBOL_GPL(kvm_set_xcr);
780
a83b29c6 781int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 782{
fc78f519 783 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 784 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 785 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 786
0f12244f
GN		 787 if (cr4 & CR4_RESERVED_BITS)
788 return 1;
a03490ed 789
d6321d49 790 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 791 return 1;
792
d6321d49 793 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 794 return 1;
795
d6321d49 796 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 797 return 1;
798
d6321d49 799 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 800 return 1;
801
d6321d49 802 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 803 return 1;
804
fd8cb433 805 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 806 return 1;
807
ae3e61e1
PB		 808 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
809 return 1;
810
a03490ed 811 if (is_long_mode(vcpu)) {
0f12244f
GN		 812 if (!(cr4 & X86_CR4_PAE))
813 return 1;
a2edf57f
AK		 814 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
815 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 816 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
817 kvm_read_cr3(vcpu)))
0f12244f
GN		 818 return 1;
819
ad756a16 820 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 821 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 822 return 1;
823
824 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
825 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
826 return 1;
827 }
828
5e1746d6 829 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 830 return 1;
a03490ed 831
ad756a16
MJ		 832 if (((cr4 ^ old_cr4) & pdptr_bits) ||
833 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 834 kvm_mmu_reset_context(vcpu);
0f12244f 835
b9baba86 836 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 837 kvm_update_cpuid(vcpu);
2acf923e 838
0f12244f
GN		 839 return 0;
840}
2d3ad1f4 841EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 842
2390218b 843int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 844{
ac146235 845#ifdef CONFIG_X86_64
9d88fca7 846 cr3 &= ~CR3_PCID_INVD;
ac146235 847#endif
9d88fca7 848
9f8fe504 849 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 850 kvm_mmu_sync_roots(vcpu);
77c3913b 851 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 852 return 0;
d835dfec
AK		 853 }
854
d1cd3ce9
YZ		 855 if (is_long_mode(vcpu) &&
856 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
857 return 1;
858 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 859 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 860 return 1;
a03490ed 861
0f12244f 862 vcpu->arch.cr3 = cr3;
aff48baa 863 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 864 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 865 return 0;
866}
2d3ad1f4 867EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 868
eea1cff9 869int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 870{
0f12244f
GN		 871 if (cr8 & CR8_RESERVED_BITS)
872 return 1;
35754c98 873 if (lapic_in_kernel(vcpu))
a03490ed
CO		 874 kvm_lapic_set_tpr(vcpu, cr8);
875 else
ad312c7c 876 vcpu->arch.cr8 = cr8;
0f12244f
GN		 877 return 0;
878}
2d3ad1f4 879EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 880
2d3ad1f4 881unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 882{
35754c98 883 if (lapic_in_kernel(vcpu))
a03490ed
CO		 884 return kvm_lapic_get_cr8(vcpu);
885 else
ad312c7c 886 return vcpu->arch.cr8;
a03490ed 887}
2d3ad1f4 888EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 889
ae561ede
NA		 890static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
891{
892 int i;
893
894 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
895 for (i = 0; i < KVM_NR_DB_REGS; i++)
896 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
897 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
898 }
899}
900
73aaf249
JK		 901static void kvm_update_dr6(struct kvm_vcpu *vcpu)
902{
903 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
904 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
905}
906
c8639010
JK		 907static void kvm_update_dr7(struct kvm_vcpu *vcpu)
908{
909 unsigned long dr7;
910
911 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
912 dr7 = vcpu->arch.guest_debug_dr7;
913 else
914 dr7 = vcpu->arch.dr7;
915 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 916 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
917 if (dr7 & DR7_BP_EN_MASK)
918 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 919}
920
6f43ed01
NA		 921static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
922{
923 u64 fixed = DR6_FIXED_1;
924
d6321d49 925 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 926 fixed |= DR6_RTM;
927 return fixed;
928}
929
338dbc97 930static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 931{
932 switch (dr) {
933 case 0 ... 3:
934 vcpu->arch.db[dr] = val;
935 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
936 vcpu->arch.eff_db[dr] = val;
937 break;
938 case 4:
020df079
GN		 939 /* fall through */
940 case 6:
338dbc97
GN		 941 if (val & 0xffffffff00000000ULL)
942 return -1; /* #GP */
6f43ed01 943 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 944 kvm_update_dr6(vcpu);
020df079
GN		 945 break;
946 case 5:
020df079
GN		 947 /* fall through */
948 default: /* 7 */
338dbc97
GN		 949 if (val & 0xffffffff00000000ULL)
950 return -1; /* #GP */
020df079 951 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 952 kvm_update_dr7(vcpu);
020df079
GN		 953 break;
954 }
955
956 return 0;
957}
338dbc97
GN		 958
959int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
960{
16f8a6f9 961 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 962 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 963 return 1;
964 }
965 return 0;
338dbc97 966}
020df079
GN		 967EXPORT_SYMBOL_GPL(kvm_set_dr);
968
16f8a6f9 969int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 970{
971 switch (dr) {
972 case 0 ... 3:
973 *val = vcpu->arch.db[dr];
974 break;
975 case 4:
020df079
GN		 976 /* fall through */
977 case 6:
73aaf249
JK		 978 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
979 *val = vcpu->arch.dr6;
980 else
981 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 982 break;
983 case 5:
020df079
GN		 984 /* fall through */
985 default: /* 7 */
986 *val = vcpu->arch.dr7;
987 break;
988 }
338dbc97
GN		 989 return 0;
990}
020df079
GN		 991EXPORT_SYMBOL_GPL(kvm_get_dr);
992
022cd0e8
AK		 993bool kvm_rdpmc(struct kvm_vcpu *vcpu)
994{
995 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
996 u64 data;
997 int err;
998
c6702c9d 999 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1000 if (err)
1001 return err;
1002 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1003 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1004 return err;
1005}
1006EXPORT_SYMBOL_GPL(kvm_rdpmc);
1007
043405e1
CO		 1008/*
1009 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1010 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1011 *
1012 * This list is modified at module load time to reflect the
e3267cbb 1013 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1014 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1015 * may depend on host virtualization features rather than host cpu features.
043405e1 1016 */
e3267cbb 1017
043405e1
CO		 1018static u32 msrs_to_save[] = {
1019 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1020 MSR_STAR,
043405e1
CO		 1021#ifdef CONFIG_X86_64
1022 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1023#endif
b3897a49 1024 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1025 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1026 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1027};
1028
1029static unsigned num_msrs_to_save;
1030
62ef68bb
PB		 1031static u32 emulated_msrs[] = {
1032 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1033 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1034 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1035 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1036 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1037 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1038 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1039 HV_X64_MSR_RESET,
11c4b1ca 1040 HV_X64_MSR_VP_INDEX,
9eec50b8 1041 HV_X64_MSR_VP_RUNTIME,
5c919412 1042 HV_X64_MSR_SCONTROL,
1f4b34f8 1043 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1044 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1045 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1046 HV_X64_MSR_TSC_EMULATION_STATUS,
1047
1048 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1049 MSR_KVM_PV_EOI_EN,
1050
ba904635 1051 MSR_IA32_TSC_ADJUST,
a3e06bbe 1052 MSR_IA32_TSCDEADLINE,
043405e1 1053 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1054 MSR_IA32_MCG_STATUS,
1055 MSR_IA32_MCG_CTL,
c45dcc71 1056 MSR_IA32_MCG_EXT_CTL,
64d60670 1057 MSR_IA32_SMBASE,
52797bf9 1058 MSR_SMI_COUNT,
db2336a8
KH		 1059 MSR_PLATFORM_INFO,
1060 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1061};
1062
62ef68bb
PB		 1063static unsigned num_emulated_msrs;
1064
801e459a
TL		 1065/*
1066 * List of msr numbers which are used to expose MSR-based features that
1067 * can be used by a hypervisor to validate requested CPU features.
1068 */
1069static u32 msr_based_features[] = {
1389309c
PB		 1070 MSR_IA32_VMX_BASIC,
1071 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1072 MSR_IA32_VMX_PINBASED_CTLS,
1073 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1074 MSR_IA32_VMX_PROCBASED_CTLS,
1075 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1076 MSR_IA32_VMX_EXIT_CTLS,
1077 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1078 MSR_IA32_VMX_ENTRY_CTLS,
1079 MSR_IA32_VMX_MISC,
1080 MSR_IA32_VMX_CR0_FIXED0,
1081 MSR_IA32_VMX_CR0_FIXED1,
1082 MSR_IA32_VMX_CR4_FIXED0,
1083 MSR_IA32_VMX_CR4_FIXED1,
1084 MSR_IA32_VMX_VMCS_ENUM,
1085 MSR_IA32_VMX_PROCBASED_CTLS2,
1086 MSR_IA32_VMX_EPT_VPID_CAP,
1087 MSR_IA32_VMX_VMFUNC,
1088
d1d93fa9 1089 MSR_F10H_DECFG,
518e7b94 1090 MSR_IA32_UCODE_REV,
801e459a
TL		 1091};
1092
1093static unsigned int num_msr_based_features;
1094
66421c1e
WL		 1095static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1096{
1097 switch (msr->index) {
518e7b94
WL		 1098 case MSR_IA32_UCODE_REV:
1099 rdmsrl(msr->index, msr->data);
1100 break;
66421c1e
WL		 1101 default:
1102 if (kvm_x86_ops->get_msr_feature(msr))
1103 return 1;
1104 }
1105 return 0;
1106}
1107
801e459a
TL		 1108static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1109{
1110 struct kvm_msr_entry msr;
66421c1e 1111 int r;
801e459a
TL		 1112
1113 msr.index = index;
66421c1e
WL		 1114 r = kvm_get_msr_feature(&msr);
1115 if (r)
1116 return r;
801e459a
TL		 1117
1118 *data = msr.data;
1119
1120 return 0;
1121}
1122
384bb783 1123bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1124{
b69e8cae 1125 if (efer & efer_reserved_bits)
384bb783 1126 return false;
15c4a640 1127
1b4d56b8 1128 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1129 return false;
1b2fd70c 1130
1b4d56b8 1131 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1132 return false;
d8017474 1133
384bb783
JK		 1134 return true;
1135}
1136EXPORT_SYMBOL_GPL(kvm_valid_efer);
1137
1138static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1139{
1140 u64 old_efer = vcpu->arch.efer;
1141
1142 if (!kvm_valid_efer(vcpu, efer))
1143 return 1;
1144
1145 if (is_paging(vcpu)
1146 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1147 return 1;
1148
15c4a640 1149 efer &= ~EFER_LMA;
f6801dff 1150 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1151
a3d204e2
SY		 1152 kvm_x86_ops->set_efer(vcpu, efer);
1153
aad82703
SY		 1154 /* Update reserved bits */
1155 if ((efer ^ old_efer) & EFER_NX)
1156 kvm_mmu_reset_context(vcpu);
1157
b69e8cae 1158 return 0;
15c4a640
CO		 1159}
1160
f2b4b7dd
JR		 1161void kvm_enable_efer_bits(u64 mask)
1162{
1163 efer_reserved_bits &= ~mask;
1164}
1165EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1166
15c4a640
CO		 1167/*
1168 * Writes msr value into into the appropriate "register".
1169 * Returns 0 on success, non-0 otherwise.
1170 * Assumes vcpu_load() was already called.
1171 */
8fe8ab46 1172int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1173{
854e8bb1
NA		 1174 switch (msr->index) {
1175 case MSR_FS_BASE:
1176 case MSR_GS_BASE:
1177 case MSR_KERNEL_GS_BASE:
1178 case MSR_CSTAR:
1179 case MSR_LSTAR:
fd8cb433 1180 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1181 return 1;
1182 break;
1183 case MSR_IA32_SYSENTER_EIP:
1184 case MSR_IA32_SYSENTER_ESP:
1185 /*
1186 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1187 * non-canonical address is written on Intel but not on
1188 * AMD (which ignores the top 32-bits, because it does
1189 * not implement 64-bit SYSENTER).
1190 *
1191 * 64-bit code should hence be able to write a non-canonical
1192 * value on AMD. Making the address canonical ensures that
1193 * vmentry does not fail on Intel after writing a non-canonical
1194 * value, and that something deterministic happens if the guest
1195 * invokes 64-bit SYSENTER.
1196 */
fd8cb433 1197 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1198 }
8fe8ab46 1199 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1200}
854e8bb1 1201EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1202
313a3dc7
CO		 1203/*
1204 * Adapt set_msr() to msr_io()'s calling convention
1205 */
609e36d3
PB		 1206static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1207{
1208 struct msr_data msr;
1209 int r;
1210
1211 msr.index = index;
1212 msr.host_initiated = true;
1213 r = kvm_get_msr(vcpu, &msr);
1214 if (r)
1215 return r;
1216
1217 *data = msr.data;
1218 return 0;
1219}
1220
313a3dc7
CO		 1221static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1222{
8fe8ab46
WA		 1223 struct msr_data msr;
1224
1225 msr.data = *data;
1226 msr.index = index;
1227 msr.host_initiated = true;
1228 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1229}
1230
16e8d74d
MT		 1231#ifdef CONFIG_X86_64
1232struct pvclock_gtod_data {
1233 seqcount_t seq;
1234
1235 struct { /* extract of a clocksource struct */
1236 int vclock_mode;
a5a1d1c2
TG		 1237 u64 cycle_last;
1238 u64 mask;
16e8d74d
MT		 1239 u32 mult;
1240 u32 shift;
1241 } clock;
1242
cbcf2dd3
TG		 1243 u64 boot_ns;
1244 u64 nsec_base;
55dd00a7 1245 u64 wall_time_sec;
16e8d74d
MT		 1246};
1247
1248static struct pvclock_gtod_data pvclock_gtod_data;
1249
1250static void update_pvclock_gtod(struct timekeeper *tk)
1251{
1252 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1253 u64 boot_ns;
1254
876e7881 1255 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1256
1257 write_seqcount_begin(&vdata->seq);
1258
1259 /* copy pvclock gtod data */
876e7881
PZ		 1260 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1261 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1262 vdata->clock.mask = tk->tkr_mono.mask;
1263 vdata->clock.mult = tk->tkr_mono.mult;
1264 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1265
cbcf2dd3 1266 vdata->boot_ns = boot_ns;
876e7881 1267 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1268
55dd00a7
MT		 1269 vdata->wall_time_sec = tk->xtime_sec;
1270
16e8d74d
MT		 1271 write_seqcount_end(&vdata->seq);
1272}
1273#endif
1274
bab5bb39
NK		 1275void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1276{
1277 /*
1278 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1279 * vcpu_enter_guest. This function is only called from
1280 * the physical CPU that is running vcpu.
1281 */
1282 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1283}
16e8d74d 1284
18068523
GOC		 1285static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1286{
9ed3c444
AK		 1287 int version;
1288 int r;
50d0a0f9 1289 struct pvclock_wall_clock wc;
87aeb54f 1290 struct timespec64 boot;
18068523
GOC		 1291
1292 if (!wall_clock)
1293 return;
1294
9ed3c444
AK		 1295 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1296 if (r)
1297 return;
1298
1299 if (version & 1)
1300 ++version; /* first time write, random junk */
1301
1302 ++version;
18068523 1303
1dab1345
NK		 1304 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1305 return;
18068523 1306
50d0a0f9
GH		 1307 /*
1308 * The guest calculates current wall clock time by adding
34c238a1 1309 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1310 * wall clock specified here. guest system time equals host
1311 * system time for us, thus we must fill in host boot time here.
1312 */
87aeb54f 1313 getboottime64(&boot);
50d0a0f9 1314
4b648665 1315 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1316 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1317 boot = timespec64_sub(boot, ts);
4b648665 1318 }
87aeb54f 1319 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1320 wc.nsec = boot.tv_nsec;
1321 wc.version = version;
18068523
GOC		 1322
1323 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1324
1325 version++;
1326 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1327}
1328
50d0a0f9
GH		 1329static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1330{
b51012de
PB		 1331 do_shl32_div32(dividend, divisor);
1332 return dividend;
50d0a0f9
GH		 1333}
1334
3ae13faa 1335static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1336 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1337{
5f4e3f88 1338 uint64_t scaled64;
50d0a0f9
GH		 1339 int32_t shift = 0;
1340 uint64_t tps64;
1341 uint32_t tps32;
1342
3ae13faa
PB		 1343 tps64 = base_hz;
1344 scaled64 = scaled_hz;
50933623 1345 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1346 tps64 >>= 1;
1347 shift--;
1348 }
1349
1350 tps32 = (uint32_t)tps64;
50933623
JK		 1351 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1352 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1353 scaled64 >>= 1;
1354 else
1355 tps32 <<= 1;
50d0a0f9
GH		 1356 shift++;
1357 }
1358
5f4e3f88
ZA		 1359 *pshift = shift;
1360 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1361
3ae13faa
PB		 1362 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1363 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1364}
1365
d828199e 1366#ifdef CONFIG_X86_64
16e8d74d 1367static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1368#endif
16e8d74d 1369
c8076604 1370static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1371static unsigned long max_tsc_khz;
c8076604 1372
cc578287 1373static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1374{
cc578287
ZA		 1375 u64 v = (u64)khz * (1000000 + ppm);
1376 do_div(v, 1000000);
1377 return v;
1e993611
JR		 1378}
1379
381d585c
HZ		 1380static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1381{
1382 u64 ratio;
1383
1384 /* Guest TSC same frequency as host TSC? */
1385 if (!scale) {
1386 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1387 return 0;
1388 }
1389
1390 /* TSC scaling supported? */
1391 if (!kvm_has_tsc_control) {
1392 if (user_tsc_khz > tsc_khz) {
1393 vcpu->arch.tsc_catchup = 1;
1394 vcpu->arch.tsc_always_catchup = 1;
1395 return 0;
1396 } else {
1397 WARN(1, "user requested TSC rate below hardware speed\n");
1398 return -1;
1399 }
1400 }
1401
1402 /* TSC scaling required - calculate ratio */
1403 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1404 user_tsc_khz, tsc_khz);
1405
1406 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1407 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1408 user_tsc_khz);
1409 return -1;
1410 }
1411
1412 vcpu->arch.tsc_scaling_ratio = ratio;
1413 return 0;
1414}
1415
4941b8cb 1416static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1417{
cc578287
ZA		 1418 u32 thresh_lo, thresh_hi;
1419 int use_scaling = 0;
217fc9cf 1420
03ba32ca 1421 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1422 if (user_tsc_khz == 0) {
ad721883
HZ		 1423 /* set tsc_scaling_ratio to a safe value */
1424 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1425 return -1;
ad721883 1426 }
03ba32ca 1427
c285545f 1428 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1429 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1430 &vcpu->arch.virtual_tsc_shift,
1431 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1432 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1433
1434 /*
1435 * Compute the variation in TSC rate which is acceptable
1436 * within the range of tolerance and decide if the
1437 * rate being applied is within that bounds of the hardware
1438 * rate. If so, no scaling or compensation need be done.
1439 */
1440 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1441 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1442 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1443 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1444 use_scaling = 1;
1445 }
4941b8cb 1446 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1447}
1448
1449static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1450{
e26101b1 1451 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1452 vcpu->arch.virtual_tsc_mult,
1453 vcpu->arch.virtual_tsc_shift);
e26101b1 1454 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1455 return tsc;
1456}
1457
b0c39dc6
VK		 1458static inline int gtod_is_based_on_tsc(int mode)
1459{
1460 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1461}
1462
69b0049a 1463static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1464{
1465#ifdef CONFIG_X86_64
1466 bool vcpus_matched;
b48aa97e
MT		 1467 struct kvm_arch *ka = &vcpu->kvm->arch;
1468 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1469
1470 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1471 atomic_read(&vcpu->kvm->online_vcpus));
1472
7f187922
MT		 1473 /*
1474 * Once the masterclock is enabled, always perform request in
1475 * order to update it.
1476 *
1477 * In order to enable masterclock, the host clocksource must be TSC
1478 * and the vcpus need to have matched TSCs. When that happens,
1479 * perform request to enable masterclock.
1480 */
1481 if (ka->use_master_clock ||
b0c39dc6 1482 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1483 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1484
1485 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1486 atomic_read(&vcpu->kvm->online_vcpus),
1487 ka->use_master_clock, gtod->clock.vclock_mode);
1488#endif
1489}
1490
ba904635
WA		 1491static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1492{
e79f245d 1493 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1494 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1495}
1496
35181e86
HZ		 1497/*
1498 * Multiply tsc by a fixed point number represented by ratio.
1499 *
1500 * The most significant 64-N bits (mult) of ratio represent the
1501 * integral part of the fixed point number; the remaining N bits
1502 * (frac) represent the fractional part, ie. ratio represents a fixed
1503 * point number (mult + frac * 2^(-N)).
1504 *
1505 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1506 */
1507static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1508{
1509 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1510}
1511
1512u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1513{
1514 u64 _tsc = tsc;
1515 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1516
1517 if (ratio != kvm_default_tsc_scaling_ratio)
1518 _tsc = __scale_tsc(ratio, tsc);
1519
1520 return _tsc;
1521}
1522EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1523
07c1419a
HZ		 1524static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1525{
1526 u64 tsc;
1527
1528 tsc = kvm_scale_tsc(vcpu, rdtsc());
1529
1530 return target_tsc - tsc;
1531}
1532
4ba76538
HZ		 1533u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1534{
e79f245d
KA		 1535 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1536
1537 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1538}
1539EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1540
a545ab6a
LC		 1541static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1542{
1543 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1544 vcpu->arch.tsc_offset = offset;
1545}
1546
b0c39dc6
VK		 1547static inline bool kvm_check_tsc_unstable(void)
1548{
1549#ifdef CONFIG_X86_64
1550 /*
1551 * TSC is marked unstable when we're running on Hyper-V,
1552 * 'TSC page' clocksource is good.
1553 */
1554 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1555 return false;
1556#endif
1557 return check_tsc_unstable();
1558}
1559
8fe8ab46 1560void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1561{
1562 struct kvm *kvm = vcpu->kvm;
f38e098f 1563 u64 offset, ns, elapsed;
99e3e30a 1564 unsigned long flags;
b48aa97e 1565 bool matched;
0d3da0d2 1566 bool already_matched;
8fe8ab46 1567 u64 data = msr->data;
c5e8ec8e 1568 bool synchronizing = false;
99e3e30a 1569
038f8c11 1570 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1571 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1572 ns = ktime_get_boot_ns();
f38e098f 1573 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1574
03ba32ca 1575 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1576 if (data == 0 && msr->host_initiated) {
1577 /*
1578 * detection of vcpu initialization -- need to sync
1579 * with other vCPUs. This particularly helps to keep
1580 * kvm_clock stable after CPU hotplug
1581 */
1582 synchronizing = true;
1583 } else {
1584 u64 tsc_exp = kvm->arch.last_tsc_write +
1585 nsec_to_cycles(vcpu, elapsed);
1586 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1587 /*
1588 * Special case: TSC write with a small delta (1 second)
1589 * of virtual cycle time against real time is
1590 * interpreted as an attempt to synchronize the CPU.
1591 */
1592 synchronizing = data < tsc_exp + tsc_hz &&
1593 data + tsc_hz > tsc_exp;
1594 }
c5e8ec8e 1595 }
f38e098f
ZA		 1596
1597 /*
5d3cb0f6
ZA		 1598 * For a reliable TSC, we can match TSC offsets, and for an unstable
1599 * TSC, we add elapsed time in this computation. We could let the
1600 * compensation code attempt to catch up if we fall behind, but
1601 * it's better to try to match offsets from the beginning.
1602 */
c5e8ec8e 1603 if (synchronizing &&
5d3cb0f6 1604 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1605 if (!kvm_check_tsc_unstable()) {
e26101b1 1606 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1607 pr_debug("kvm: matched tsc offset for %llu\n", data);
1608 } else {
857e4099 1609 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1610 data += delta;
07c1419a 1611 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1612 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1613 }
b48aa97e 1614 matched = true;
0d3da0d2 1615 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1616 } else {
1617 /*
1618 * We split periods of matched TSC writes into generations.
1619 * For each generation, we track the original measured
1620 * nanosecond time, offset, and write, so if TSCs are in
1621 * sync, we can match exact offset, and if not, we can match
4a969980 1622 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1623 *
1624 * These values are tracked in kvm->arch.cur_xxx variables.
1625 */
1626 kvm->arch.cur_tsc_generation++;
1627 kvm->arch.cur_tsc_nsec = ns;
1628 kvm->arch.cur_tsc_write = data;
1629 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1630 matched = false;
0d3da0d2 1631 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1632 kvm->arch.cur_tsc_generation, data);
f38e098f 1633 }
e26101b1
ZA		 1634
1635 /*
1636 * We also track th most recent recorded KHZ, write and time to
1637 * allow the matching interval to be extended at each write.
1638 */
f38e098f
ZA		 1639 kvm->arch.last_tsc_nsec = ns;
1640 kvm->arch.last_tsc_write = data;
5d3cb0f6 1641 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1642
b183aa58 1643 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1644
1645 /* Keep track of which generation this VCPU has synchronized to */
1646 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1647 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1648 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1649
d6321d49 1650 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1651 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1652
a545ab6a 1653 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1654 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1655
1656 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1657 if (!matched) {
b48aa97e 1658 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1659 } else if (!already_matched) {
1660 kvm->arch.nr_vcpus_matched_tsc++;
1661 }
b48aa97e
MT		 1662
1663 kvm_track_tsc_matching(vcpu);
1664 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1665}
e26101b1 1666
99e3e30a
ZA		 1667EXPORT_SYMBOL_GPL(kvm_write_tsc);
1668
58ea6767
HZ		 1669static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1670 s64 adjustment)
1671{
ea26e4ec 1672 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1673}
1674
1675static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1676{
1677 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1678 WARN_ON(adjustment < 0);
1679 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1680 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1681}
1682
d828199e
MT		 1683#ifdef CONFIG_X86_64
1684
a5a1d1c2 1685static u64 read_tsc(void)
d828199e 1686{
a5a1d1c2 1687 u64 ret = (u64)rdtsc_ordered();
03b9730b 1688 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1689
1690 if (likely(ret >= last))
1691 return ret;
1692
1693 /*
1694 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1695 * predictable (it's just a function of time and the likely is
d828199e
MT		 1696 * very likely) and there's a data dependence, so force GCC
1697 * to generate a branch instead. I don't barrier() because
1698 * we don't actually need a barrier, and if this function
1699 * ever gets inlined it will generate worse code.
1700 */
1701 asm volatile ("");
1702 return last;
1703}
1704
b0c39dc6 1705static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1706{
1707 long v;
1708 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1709 u64 tsc_pg_val;
1710
1711 switch (gtod->clock.vclock_mode) {
1712 case VCLOCK_HVCLOCK:
1713 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1714 tsc_timestamp);
1715 if (tsc_pg_val != U64_MAX) {
1716 /* TSC page valid */
1717 *mode = VCLOCK_HVCLOCK;
1718 v = (tsc_pg_val - gtod->clock.cycle_last) &
1719 gtod->clock.mask;
1720 } else {
1721 /* TSC page invalid */
1722 *mode = VCLOCK_NONE;
1723 }
1724 break;
1725 case VCLOCK_TSC:
1726 *mode = VCLOCK_TSC;
1727 *tsc_timestamp = read_tsc();
1728 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1729 gtod->clock.mask;
1730 break;
1731 default:
1732 *mode = VCLOCK_NONE;
1733 }
d828199e 1734
b0c39dc6
VK		 1735 if (*mode == VCLOCK_NONE)
1736 *tsc_timestamp = v = 0;
d828199e 1737
d828199e
MT		 1738 return v * gtod->clock.mult;
1739}
1740
b0c39dc6 1741static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1742{
cbcf2dd3 1743 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1744 unsigned long seq;
d828199e 1745 int mode;
cbcf2dd3 1746 u64 ns;
d828199e 1747
d828199e
MT		 1748 do {
1749 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1750 ns = gtod->nsec_base;
b0c39dc6 1751 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1752 ns >>= gtod->clock.shift;
cbcf2dd3 1753 ns += gtod->boot_ns;
d828199e 1754 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1755 *t = ns;
d828199e
MT		 1756
1757 return mode;
1758}
1759
b0c39dc6 1760static int do_realtime(struct timespec *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1761{
1762 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1763 unsigned long seq;
1764 int mode;
1765 u64 ns;
1766
1767 do {
1768 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1769 ts->tv_sec = gtod->wall_time_sec;
1770 ns = gtod->nsec_base;
b0c39dc6 1771 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1772 ns >>= gtod->clock.shift;
1773 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1774
1775 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1776 ts->tv_nsec = ns;
1777
1778 return mode;
1779}
1780
b0c39dc6
VK		 1781/* returns true if host is using TSC based clocksource */
1782static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1783{
d828199e 1784 /* checked again under seqlock below */
b0c39dc6 1785 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1786 return false;
1787
b0c39dc6
VK		 1788 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1789 tsc_timestamp));
d828199e 1790}
55dd00a7 1791
b0c39dc6 1792/* returns true if host is using TSC based clocksource */
55dd00a7 1793static bool kvm_get_walltime_and_clockread(struct timespec *ts,
b0c39dc6 1794 u64 *tsc_timestamp)
55dd00a7
MT		 1795{
1796 /* checked again under seqlock below */
b0c39dc6 1797 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1798 return false;
1799
b0c39dc6 1800 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1801}
d828199e
MT		 1802#endif
1803
1804/*
1805 *
b48aa97e
MT		 1806 * Assuming a stable TSC across physical CPUS, and a stable TSC
1807 * across virtual CPUs, the following condition is possible.
1808 * Each numbered line represents an event visible to both
d828199e
MT		 1809 * CPUs at the next numbered event.
1810 *
1811 * "timespecX" represents host monotonic time. "tscX" represents
1812 * RDTSC value.
1813 *
1814 * VCPU0 on CPU0 | VCPU1 on CPU1
1815 *
1816 * 1. read timespec0,tsc0
1817 * 2. | timespec1 = timespec0 + N
1818 * | tsc1 = tsc0 + M
1819 * 3. transition to guest | transition to guest
1820 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1821 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1822 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1823 *
1824 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1825 *
1826 * - ret0 < ret1
1827 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1828 * ...
1829 * - 0 < N - M => M < N
1830 *
1831 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1832 * always the case (the difference between two distinct xtime instances
1833 * might be smaller then the difference between corresponding TSC reads,
1834 * when updating guest vcpus pvclock areas).
1835 *
1836 * To avoid that problem, do not allow visibility of distinct
1837 * system_timestamp/tsc_timestamp values simultaneously: use a master
1838 * copy of host monotonic time values. Update that master copy
1839 * in lockstep.
1840 *
b48aa97e 1841 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1842 *
1843 */
1844
1845static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1846{
1847#ifdef CONFIG_X86_64
1848 struct kvm_arch *ka = &kvm->arch;
1849 int vclock_mode;
b48aa97e
MT		 1850 bool host_tsc_clocksource, vcpus_matched;
1851
1852 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1853 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1854
1855 /*
1856 * If the host uses TSC clock, then passthrough TSC as stable
1857 * to the guest.
1858 */
b48aa97e 1859 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1860 &ka->master_kernel_ns,
1861 &ka->master_cycle_now);
1862
16a96021 1863 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1864 && !ka->backwards_tsc_observed
54750f2c 1865 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1866
d828199e
MT		 1867 if (ka->use_master_clock)
1868 atomic_set(&kvm_guest_has_master_clock, 1);
1869
1870 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1871 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1872 vcpus_matched);
d828199e
MT		 1873#endif
1874}
1875
2860c4b1
PB		 1876void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1877{
1878 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1879}
1880
2e762ff7
MT		 1881static void kvm_gen_update_masterclock(struct kvm *kvm)
1882{
1883#ifdef CONFIG_X86_64
1884 int i;
1885 struct kvm_vcpu *vcpu;
1886 struct kvm_arch *ka = &kvm->arch;
1887
1888 spin_lock(&ka->pvclock_gtod_sync_lock);
1889 kvm_make_mclock_inprogress_request(kvm);
1890 /* no guest entries from this point */
1891 pvclock_update_vm_gtod_copy(kvm);
1892
1893 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1894 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1895
1896 /* guest entries allowed */
1897 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1898 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1899
1900 spin_unlock(&ka->pvclock_gtod_sync_lock);
1901#endif
1902}
1903
e891a32e 1904u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1905{
108b249c 1906 struct kvm_arch *ka = &kvm->arch;
8b953440 1907 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1908 u64 ret;
108b249c 1909
8b953440
PB		 1910 spin_lock(&ka->pvclock_gtod_sync_lock);
1911 if (!ka->use_master_clock) {
1912 spin_unlock(&ka->pvclock_gtod_sync_lock);
1913 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1914 }
1915
8b953440
PB		 1916 hv_clock.tsc_timestamp = ka->master_cycle_now;
1917 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1918 spin_unlock(&ka->pvclock_gtod_sync_lock);
1919
e2c2206a
WL		 1920 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1921 get_cpu();
1922
e70b57a6
WL		 1923 if (__this_cpu_read(cpu_tsc_khz)) {
1924 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1925 &hv_clock.tsc_shift,
1926 &hv_clock.tsc_to_system_mul);
1927 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1928 } else
1929 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1930
1931 put_cpu();
1932
1933 return ret;
108b249c
PB		 1934}
1935
0d6dd2ff
PB		 1936static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1937{
1938 struct kvm_vcpu_arch *vcpu = &v->arch;
1939 struct pvclock_vcpu_time_info guest_hv_clock;
1940
4e335d9e 1941 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1942 &guest_hv_clock, sizeof(guest_hv_clock))))
1943 return;
1944
1945 /* This VCPU is paused, but it's legal for a guest to read another
1946 * VCPU's kvmclock, so we really have to follow the specification where
1947 * it says that version is odd if data is being modified, and even after
1948 * it is consistent.
1949 *
1950 * Version field updates must be kept separate. This is because
1951 * kvm_write_guest_cached might use a "rep movs" instruction, and
1952 * writes within a string instruction are weakly ordered. So there
1953 * are three writes overall.
1954 *
1955 * As a small optimization, only write the version field in the first
1956 * and third write. The vcpu->pv_time cache is still valid, because the
1957 * version field is the first in the struct.
1958 */
1959 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1960
51c4b8bb
LA		 1961 if (guest_hv_clock.version & 1)
1962 ++guest_hv_clock.version; /* first time write, random junk */
1963
0d6dd2ff 1964 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1965 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1966 &vcpu->hv_clock,
1967 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1968
1969 smp_wmb();
1970
1971 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1972 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1973
1974 if (vcpu->pvclock_set_guest_stopped_request) {
1975 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1976 vcpu->pvclock_set_guest_stopped_request = false;
1977 }
1978
1979 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1980
4e335d9e
PB		 1981 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1982 &vcpu->hv_clock,
1983 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1984
1985 smp_wmb();
1986
1987 vcpu->hv_clock.version++;
4e335d9e
PB		 1988 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1989 &vcpu->hv_clock,
1990 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1991}
1992
34c238a1 1993static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1994{
78db6a50 1995 unsigned long flags, tgt_tsc_khz;
18068523 1996 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1997 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1998 s64 kernel_ns;
d828199e 1999 u64 tsc_timestamp, host_tsc;
51d59c6b 2000 u8 pvclock_flags;
d828199e
MT		 2001 bool use_master_clock;
2002
2003 kernel_ns = 0;
2004 host_tsc = 0;
18068523 2005
d828199e
MT		 2006 /*
2007 * If the host uses TSC clock, then passthrough TSC as stable
2008 * to the guest.
2009 */
2010 spin_lock(&ka->pvclock_gtod_sync_lock);
2011 use_master_clock = ka->use_master_clock;
2012 if (use_master_clock) {
2013 host_tsc = ka->master_cycle_now;
2014 kernel_ns = ka->master_kernel_ns;
2015 }
2016 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2017
2018 /* Keep irq disabled to prevent changes to the clock */
2019 local_irq_save(flags);
78db6a50
PB		 2020 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2021 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2022 local_irq_restore(flags);
2023 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2024 return 1;
2025 }
d828199e 2026 if (!use_master_clock) {
4ea1636b 2027 host_tsc = rdtsc();
108b249c 2028 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2029 }
2030
4ba76538 2031 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2032
c285545f
ZA		 2033 /*
2034 * We may have to catch up the TSC to match elapsed wall clock
2035 * time for two reasons, even if kvmclock is used.
2036 * 1) CPU could have been running below the maximum TSC rate
2037 * 2) Broken TSC compensation resets the base at each VCPU
2038 * entry to avoid unknown leaps of TSC even when running
2039 * again on the same CPU. This may cause apparent elapsed
2040 * time to disappear, and the guest to stand still or run
2041 * very slowly.
2042 */
2043 if (vcpu->tsc_catchup) {
2044 u64 tsc = compute_guest_tsc(v, kernel_ns);
2045 if (tsc > tsc_timestamp) {
f1e2b260 2046 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2047 tsc_timestamp = tsc;
2048 }
50d0a0f9
GH		 2049 }
2050
18068523
GOC		 2051 local_irq_restore(flags);
2052
0d6dd2ff 2053 /* With all the info we got, fill in the values */
18068523 2054
78db6a50
PB		 2055 if (kvm_has_tsc_control)
2056 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2057
2058 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2059 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2060 &vcpu->hv_clock.tsc_shift,
2061 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2062 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2063 }
2064
1d5f066e 2065 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2066 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2067 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2068
d828199e 2069 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2070 pvclock_flags = 0;
d828199e
MT		 2071 if (use_master_clock)
2072 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2073
78c0337a
MT		 2074 vcpu->hv_clock.flags = pvclock_flags;
2075
095cf55d
PB		 2076 if (vcpu->pv_time_enabled)
2077 kvm_setup_pvclock_page(v);
2078 if (v == kvm_get_vcpu(v->kvm, 0))
2079 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2080 return 0;
c8076604
GH		 2081}
2082
0061d53d
MT		 2083/*
2084 * kvmclock updates which are isolated to a given vcpu, such as
2085 * vcpu->cpu migration, should not allow system_timestamp from
2086 * the rest of the vcpus to remain static. Otherwise ntp frequency
2087 * correction applies to one vcpu's system_timestamp but not
2088 * the others.
2089 *
2090 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2091 * We need to rate-limit these requests though, as they can
2092 * considerably slow guests that have a large number of vcpus.
2093 * The time for a remote vcpu to update its kvmclock is bound
2094 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2095 */
2096
7e44e449
AJ		 2097#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2098
2099static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2100{
2101 int i;
7e44e449
AJ		 2102 struct delayed_work *dwork = to_delayed_work(work);
2103 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2104 kvmclock_update_work);
2105 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2106 struct kvm_vcpu *vcpu;
2107
2108 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2109 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2110 kvm_vcpu_kick(vcpu);
2111 }
2112}
2113
7e44e449
AJ		 2114static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2115{
2116 struct kvm *kvm = v->kvm;
2117
105b21bb 2118 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2119 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2120 KVMCLOCK_UPDATE_DELAY);
2121}
2122
332967a3
AJ		 2123#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2124
2125static void kvmclock_sync_fn(struct work_struct *work)
2126{
2127 struct delayed_work *dwork = to_delayed_work(work);
2128 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2129 kvmclock_sync_work);
2130 struct kvm *kvm = container_of(ka, struct kvm, arch);
2131
630994b3
MT		 2132 if (!kvmclock_periodic_sync)
2133 return;
2134
332967a3
AJ		 2135 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2136 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2137 KVMCLOCK_SYNC_PERIOD);
2138}
2139
9ffd986c 2140static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2141{
890ca9ae
HY		 2142 u64 mcg_cap = vcpu->arch.mcg_cap;
2143 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2144 u32 msr = msr_info->index;
2145 u64 data = msr_info->data;
890ca9ae 2146
15c4a640 2147 switch (msr) {
15c4a640 2148 case MSR_IA32_MCG_STATUS:
890ca9ae 2149 vcpu->arch.mcg_status = data;
15c4a640 2150 break;
c7ac679c 2151 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2152 if (!(mcg_cap & MCG_CTL_P))
2153 return 1;
2154 if (data != 0 && data != ~(u64)0)
2155 return -1;
2156 vcpu->arch.mcg_ctl = data;
2157 break;
2158 default:
2159 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2160 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2161 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2162 /* only 0 or all 1s can be written to IA32_MCi_CTL
2163 * some Linux kernels though clear bit 10 in bank 4 to
2164 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2165 * this to avoid an uncatched #GP in the guest
2166 */
890ca9ae 2167 if ((offset & 0x3) == 0 &&
114be429 2168 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2169 return -1;
9ffd986c
WL		 2170 if (!msr_info->host_initiated &&
2171 (offset & 0x3) == 1 && data != 0)
2172 return -1;
890ca9ae
HY		 2173 vcpu->arch.mce_banks[offset] = data;
2174 break;
2175 }
2176 return 1;
2177 }
2178 return 0;
2179}
2180
ffde22ac
ES		 2181static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2182{
2183 struct kvm *kvm = vcpu->kvm;
2184 int lm = is_long_mode(vcpu);
2185 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2186 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2187 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2188 : kvm->arch.xen_hvm_config.blob_size_32;
2189 u32 page_num = data & ~PAGE_MASK;
2190 u64 page_addr = data & PAGE_MASK;
2191 u8 *page;
2192 int r;
2193
2194 r = -E2BIG;
2195 if (page_num >= blob_size)
2196 goto out;
2197 r = -ENOMEM;
ff5c2c03
SL		 2198 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2199 if (IS_ERR(page)) {
2200 r = PTR_ERR(page);
ffde22ac 2201 goto out;
ff5c2c03 2202 }
54bf36aa 2203 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2204 goto out_free;
2205 r = 0;
2206out_free:
2207 kfree(page);
2208out:
2209 return r;
2210}
2211
344d9588
GN		 2212static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2213{
2214 gpa_t gpa = data & ~0x3f;
2215
52a5c155
WL		 2216 /* Bits 3:5 are reserved, Should be zero */
2217 if (data & 0x38)
344d9588
GN		 2218 return 1;
2219
2220 vcpu->arch.apf.msr_val = data;
2221
2222 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2223 kvm_clear_async_pf_completion_queue(vcpu);
2224 kvm_async_pf_hash_reset(vcpu);
2225 return 0;
2226 }
2227
4e335d9e 2228 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2229 sizeof(u32)))
344d9588
GN		 2230 return 1;
2231
6adba527 2232 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2233 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2234 kvm_async_pf_wakeup_all(vcpu);
2235 return 0;
2236}
2237
12f9a48f
GC		 2238static void kvmclock_reset(struct kvm_vcpu *vcpu)
2239{
0b79459b 2240 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2241}
2242
f38a7b75
WL		 2243static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2244{
2245 ++vcpu->stat.tlb_flush;
2246 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2247}
2248
c9aaa895
GC		 2249static void record_steal_time(struct kvm_vcpu *vcpu)
2250{
2251 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2252 return;
2253
4e335d9e 2254 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2255 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2256 return;
2257
f38a7b75
WL		 2258 /*
2259 * Doing a TLB flush here, on the guest's behalf, can avoid
2260 * expensive IPIs.
2261 */
2262 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2263 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2264
35f3fae1
WL		 2265 if (vcpu->arch.st.steal.version & 1)
2266 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2267
2268 vcpu->arch.st.steal.version += 1;
2269
4e335d9e 2270 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2271 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2272
2273 smp_wmb();
2274
c54cdf14
LC		 2275 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2276 vcpu->arch.st.last_steal;
2277 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2278
4e335d9e 2279 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2280 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2281
2282 smp_wmb();
2283
2284 vcpu->arch.st.steal.version += 1;
c9aaa895 2285
4e335d9e 2286 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2287 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2288}
2289
8fe8ab46 2290int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2291{
5753785f 2292 bool pr = false;
8fe8ab46
WA		 2293 u32 msr = msr_info->index;
2294 u64 data = msr_info->data;
5753785f 2295
15c4a640 2296 switch (msr) {
2e32b719 2297 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2298 case MSR_IA32_UCODE_WRITE:
2299 case MSR_VM_HSAVE_PA:
2300 case MSR_AMD64_PATCH_LOADER:
2301 case MSR_AMD64_BU_CFG2:
405a353a 2302 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2303 break;
2304
518e7b94
WL		 2305 case MSR_IA32_UCODE_REV:
2306 if (msr_info->host_initiated)
2307 vcpu->arch.microcode_version = data;
2308 break;
15c4a640 2309 case MSR_EFER:
b69e8cae 2310 return set_efer(vcpu, data);
8f1589d9
AP		 2311 case MSR_K7_HWCR:
2312 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2313 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2314 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2315 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2316 if (data != 0) {
a737f256
CD		 2317 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2318 data);
8f1589d9
AP		 2319 return 1;
2320 }
15c4a640 2321 break;
f7c6d140
AP		 2322 case MSR_FAM10H_MMIO_CONF_BASE:
2323 if (data != 0) {
a737f256
CD		 2324 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2325 "0x%llx\n", data);
f7c6d140
AP		 2326 return 1;
2327 }
15c4a640 2328 break;
b5e2fec0
AG		 2329 case MSR_IA32_DEBUGCTLMSR:
2330 if (!data) {
2331 /* We support the non-activated case already */
2332 break;
2333 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2334 /* Values other than LBR and BTF are vendor-specific,
2335 thus reserved and should throw a #GP */
2336 return 1;
2337 }
a737f256
CD		 2338 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2339 __func__, data);
b5e2fec0 2340 break;
9ba075a6 2341 case 0x200 ... 0x2ff:
ff53604b 2342 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2343 case MSR_IA32_APICBASE:
58cb628d 2344 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2345 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2346 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2347 case MSR_IA32_TSCDEADLINE:
2348 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2349 break;
ba904635 2350 case MSR_IA32_TSC_ADJUST:
d6321d49 2351 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2352 if (!msr_info->host_initiated) {
d913b904 2353 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2354 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2355 }
2356 vcpu->arch.ia32_tsc_adjust_msr = data;
2357 }
2358 break;
15c4a640 2359 case MSR_IA32_MISC_ENABLE:
ad312c7c 2360 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2361 break;
64d60670
PB		 2362 case MSR_IA32_SMBASE:
2363 if (!msr_info->host_initiated)
2364 return 1;
2365 vcpu->arch.smbase = data;
2366 break;
dd259935
PB		 2367 case MSR_IA32_TSC:
2368 kvm_write_tsc(vcpu, msr_info);
2369 break;
52797bf9
LA		 2370 case MSR_SMI_COUNT:
2371 if (!msr_info->host_initiated)
2372 return 1;
2373 vcpu->arch.smi_count = data;
2374 break;
11c6bffa 2375 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2376 case MSR_KVM_WALL_CLOCK:
2377 vcpu->kvm->arch.wall_clock = data;
2378 kvm_write_wall_clock(vcpu->kvm, data);
2379 break;
11c6bffa 2380 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2381 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2382 struct kvm_arch *ka = &vcpu->kvm->arch;
2383
12f9a48f 2384 kvmclock_reset(vcpu);
18068523 2385
54750f2c
MT		 2386 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2387 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2388
2389 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2390 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2391
2392 ka->boot_vcpu_runs_old_kvmclock = tmp;
2393 }
2394
18068523 2395 vcpu->arch.time = data;
0061d53d 2396 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2397
2398 /* we verify if the enable bit is set... */
2399 if (!(data & 1))
2400 break;
2401
4e335d9e 2402 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2403 &vcpu->arch.pv_time, data & ~1ULL,
2404 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2405 vcpu->arch.pv_time_enabled = false;
2406 else
2407 vcpu->arch.pv_time_enabled = true;
32cad84f 2408
18068523
GOC		 2409 break;
2410 }
344d9588
GN		 2411 case MSR_KVM_ASYNC_PF_EN:
2412 if (kvm_pv_enable_async_pf(vcpu, data))
2413 return 1;
2414 break;
c9aaa895
GC		 2415 case MSR_KVM_STEAL_TIME:
2416
2417 if (unlikely(!sched_info_on()))
2418 return 1;
2419
2420 if (data & KVM_STEAL_RESERVED_MASK)
2421 return 1;
2422
4e335d9e 2423 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2424 data & KVM_STEAL_VALID_BITS,
2425 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2426 return 1;
2427
2428 vcpu->arch.st.msr_val = data;
2429
2430 if (!(data & KVM_MSR_ENABLED))
2431 break;
2432
c9aaa895
GC		 2433 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2434
2435 break;
ae7a2a3f
MT		 2436 case MSR_KVM_PV_EOI_EN:
2437 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2438 return 1;
2439 break;
c9aaa895 2440
890ca9ae
HY		 2441 case MSR_IA32_MCG_CTL:
2442 case MSR_IA32_MCG_STATUS:
81760dcc 2443 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2444 return set_msr_mce(vcpu, msr_info);
71db6023 2445
6912ac32
WH		 2446 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2447 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2448 pr = true; /* fall through */
2449 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2450 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2451 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2452 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2453
2454 if (pr || data != 0)
a737f256
CD		 2455 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2456 "0x%x data 0x%llx\n", msr, data);
5753785f 2457 break;
84e0cefa
JS		 2458 case MSR_K7_CLK_CTL:
2459 /*
2460 * Ignore all writes to this no longer documented MSR.
2461 * Writes are only relevant for old K7 processors,
2462 * all pre-dating SVM, but a recommended workaround from
4a969980 2463 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2464 * affected processor models on the command line, hence
2465 * the need to ignore the workaround.
2466 */
2467 break;
55cd8e5a 2468 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2469 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2470 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2471 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2472 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2473 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2474 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2475 return kvm_hv_set_msr_common(vcpu, msr, data,
2476 msr_info->host_initiated);
91c9c3ed 2477 case MSR_IA32_BBL_CR_CTL3:
2478 /* Drop writes to this legacy MSR -- see rdmsr
2479 * counterpart for further detail.
2480 */
fab0aa3b
EM		 2481 if (report_ignored_msrs)
2482 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2483 msr, data);
91c9c3ed 2484 break;
2b036c6b 2485 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2486 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2487 return 1;
2488 vcpu->arch.osvw.length = data;
2489 break;
2490 case MSR_AMD64_OSVW_STATUS:
d6321d49 2491 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2492 return 1;
2493 vcpu->arch.osvw.status = data;
2494 break;
db2336a8
KH		 2495 case MSR_PLATFORM_INFO:
2496 if (!msr_info->host_initiated ||
2497 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2498 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2499 cpuid_fault_enabled(vcpu)))
2500 return 1;
2501 vcpu->arch.msr_platform_info = data;
2502 break;
2503 case MSR_MISC_FEATURES_ENABLES:
2504 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2505 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2506 !supports_cpuid_fault(vcpu)))
2507 return 1;
2508 vcpu->arch.msr_misc_features_enables = data;
2509 break;
15c4a640 2510 default:
ffde22ac
ES		 2511 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2512 return xen_hvm_config(vcpu, data);
c6702c9d 2513 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2514 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2515 if (!ignore_msrs) {
ae0f5499 2516 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2517 msr, data);
ed85c068
AP		 2518 return 1;
2519 } else {
fab0aa3b
EM		 2520 if (report_ignored_msrs)
2521 vcpu_unimpl(vcpu,
2522 "ignored wrmsr: 0x%x data 0x%llx\n",
2523 msr, data);
ed85c068
AP		 2524 break;
2525 }
15c4a640
CO		 2526 }
2527 return 0;
2528}
2529EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2530
2531
2532/*
2533 * Reads an msr value (of 'msr_index') into 'pdata'.
2534 * Returns 0 on success, non-0 otherwise.
2535 * Assumes vcpu_load() was already called.
2536 */
609e36d3 2537int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2538{
609e36d3 2539 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2540}
ff651cb6 2541EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2542
890ca9ae 2543static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2544{
2545 u64 data;
890ca9ae
HY		 2546 u64 mcg_cap = vcpu->arch.mcg_cap;
2547 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2548
2549 switch (msr) {
15c4a640
CO		 2550 case MSR_IA32_P5_MC_ADDR:
2551 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2552 data = 0;
2553 break;
15c4a640 2554 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2555 data = vcpu->arch.mcg_cap;
2556 break;
c7ac679c 2557 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2558 if (!(mcg_cap & MCG_CTL_P))
2559 return 1;
2560 data = vcpu->arch.mcg_ctl;
2561 break;
2562 case MSR_IA32_MCG_STATUS:
2563 data = vcpu->arch.mcg_status;
2564 break;
2565 default:
2566 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2567 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2568 u32 offset = msr - MSR_IA32_MC0_CTL;
2569 data = vcpu->arch.mce_banks[offset];
2570 break;
2571 }
2572 return 1;
2573 }
2574 *pdata = data;
2575 return 0;
2576}
2577
609e36d3 2578int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2579{
609e36d3 2580 switch (msr_info->index) {
890ca9ae 2581 case MSR_IA32_PLATFORM_ID:
15c4a640 2582 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2583 case MSR_IA32_DEBUGCTLMSR:
2584 case MSR_IA32_LASTBRANCHFROMIP:
2585 case MSR_IA32_LASTBRANCHTOIP:
2586 case MSR_IA32_LASTINTFROMIP:
2587 case MSR_IA32_LASTINTTOIP:
60af2ecd 2588 case MSR_K8_SYSCFG:
3afb1121
PB		 2589 case MSR_K8_TSEG_ADDR:
2590 case MSR_K8_TSEG_MASK:
60af2ecd 2591 case MSR_K7_HWCR:
61a6bd67 2592 case MSR_VM_HSAVE_PA:
1fdbd48c 2593 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2594 case MSR_AMD64_NB_CFG:
f7c6d140 2595 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2596 case MSR_AMD64_BU_CFG2:
0c2df2a1 2597 case MSR_IA32_PERF_CTL:
405a353a 2598 case MSR_AMD64_DC_CFG:
609e36d3 2599 msr_info->data = 0;
15c4a640 2600 break;
c51eb52b 2601 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2602 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2603 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2604 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2605 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2606 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2607 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2608 msr_info->data = 0;
5753785f 2609 break;
742bc670 2610 case MSR_IA32_UCODE_REV:
518e7b94 2611 msr_info->data = vcpu->arch.microcode_version;
742bc670 2612 break;
dd259935
PB		 2613 case MSR_IA32_TSC:
2614 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2615 break;
9ba075a6 2616 case MSR_MTRRcap:
9ba075a6 2617 case 0x200 ... 0x2ff:
ff53604b 2618 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2619 case 0xcd: /* fsb frequency */
609e36d3 2620 msr_info->data = 3;
15c4a640 2621 break;
7b914098
JS		 2622 /*
2623 * MSR_EBC_FREQUENCY_ID
2624 * Conservative value valid for even the basic CPU models.
2625 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2626 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2627 * and 266MHz for model 3, or 4. Set Core Clock
2628 * Frequency to System Bus Frequency Ratio to 1 (bits
2629 * 31:24) even though these are only valid for CPU
2630 * models > 2, however guests may end up dividing or
2631 * multiplying by zero otherwise.
2632 */
2633 case MSR_EBC_FREQUENCY_ID:
609e36d3 2634 msr_info->data = 1 << 24;
7b914098 2635 break;
15c4a640 2636 case MSR_IA32_APICBASE:
609e36d3 2637 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2638 break;
0105d1a5 2639 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2640 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2641 break;
a3e06bbe 2642 case MSR_IA32_TSCDEADLINE:
609e36d3 2643 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2644 break;
ba904635 2645 case MSR_IA32_TSC_ADJUST:
609e36d3 2646 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2647 break;
15c4a640 2648 case MSR_IA32_MISC_ENABLE:
609e36d3 2649 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2650 break;
64d60670
PB		 2651 case MSR_IA32_SMBASE:
2652 if (!msr_info->host_initiated)
2653 return 1;
2654 msr_info->data = vcpu->arch.smbase;
15c4a640 2655 break;
52797bf9
LA		 2656 case MSR_SMI_COUNT:
2657 msr_info->data = vcpu->arch.smi_count;
2658 break;
847f0ad8
AG		 2659 case MSR_IA32_PERF_STATUS:
2660 /* TSC increment by tick */
609e36d3 2661 msr_info->data = 1000ULL;
847f0ad8 2662 /* CPU multiplier */
b0996ae4 2663 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2664 break;
15c4a640 2665 case MSR_EFER:
609e36d3 2666 msr_info->data = vcpu->arch.efer;
15c4a640 2667 break;
18068523 2668 case MSR_KVM_WALL_CLOCK:
11c6bffa 2669 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2670 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2671 break;
2672 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2673 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2674 msr_info->data = vcpu->arch.time;
18068523 2675 break;
344d9588 2676 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2677 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2678 break;
c9aaa895 2679 case MSR_KVM_STEAL_TIME:
609e36d3 2680 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2681 break;
1d92128f 2682 case MSR_KVM_PV_EOI_EN:
609e36d3 2683 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2684 break;
890ca9ae
HY		 2685 case MSR_IA32_P5_MC_ADDR:
2686 case MSR_IA32_P5_MC_TYPE:
2687 case MSR_IA32_MCG_CAP:
2688 case MSR_IA32_MCG_CTL:
2689 case MSR_IA32_MCG_STATUS:
81760dcc 2690 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2691 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2692 case MSR_K7_CLK_CTL:
2693 /*
2694 * Provide expected ramp-up count for K7. All other
2695 * are set to zero, indicating minimum divisors for
2696 * every field.
2697 *
2698 * This prevents guest kernels on AMD host with CPU
2699 * type 6, model 8 and higher from exploding due to
2700 * the rdmsr failing.
2701 */
609e36d3 2702 msr_info->data = 0x20000000;
84e0cefa 2703 break;
55cd8e5a 2704 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2705 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2706 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2707 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2708 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2709 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2710 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887
AS		 2711 return kvm_hv_get_msr_common(vcpu,
2712 msr_info->index, &msr_info->data);
55cd8e5a 2713 break;
91c9c3ed 2714 case MSR_IA32_BBL_CR_CTL3:
2715 /* This legacy MSR exists but isn't fully documented in current
2716 * silicon. It is however accessed by winxp in very narrow
2717 * scenarios where it sets bit #19, itself documented as
2718 * a "reserved" bit. Best effort attempt to source coherent
2719 * read data here should the balance of the register be
2720 * interpreted by the guest:
2721 *
2722 * L2 cache control register 3: 64GB range, 256KB size,
2723 * enabled, latency 0x1, configured
2724 */
609e36d3 2725 msr_info->data = 0xbe702111;
91c9c3ed 2726 break;
2b036c6b 2727 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2728 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2729 return 1;
609e36d3 2730 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2731 break;
2732 case MSR_AMD64_OSVW_STATUS:
d6321d49 2733 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2734 return 1;
609e36d3 2735 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2736 break;
db2336a8
KH		 2737 case MSR_PLATFORM_INFO:
2738 msr_info->data = vcpu->arch.msr_platform_info;
2739 break;
2740 case MSR_MISC_FEATURES_ENABLES:
2741 msr_info->data = vcpu->arch.msr_misc_features_enables;
2742 break;
15c4a640 2743 default:
c6702c9d 2744 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2745 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2746 if (!ignore_msrs) {
ae0f5499
BD		 2747 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2748 msr_info->index);
ed85c068
AP		 2749 return 1;
2750 } else {
fab0aa3b
EM		 2751 if (report_ignored_msrs)
2752 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2753 msr_info->index);
609e36d3 2754 msr_info->data = 0;
ed85c068
AP		 2755 }
2756 break;
15c4a640 2757 }
15c4a640
CO		 2758 return 0;
2759}
2760EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2761
313a3dc7
CO		 2762/*
2763 * Read or write a bunch of msrs. All parameters are kernel addresses.
2764 *
2765 * @return number of msrs set successfully.
2766 */
2767static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2768 struct kvm_msr_entry *entries,
2769 int (*do_msr)(struct kvm_vcpu *vcpu,
2770 unsigned index, u64 *data))
2771{
801e459a 2772 int i;
313a3dc7 2773
313a3dc7
CO		 2774 for (i = 0; i < msrs->nmsrs; ++i)
2775 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2776 break;
2777
313a3dc7
CO		 2778 return i;
2779}
2780
2781/*
2782 * Read or write a bunch of msrs. Parameters are user addresses.
2783 *
2784 * @return number of msrs set successfully.
2785 */
2786static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2787 int (*do_msr)(struct kvm_vcpu *vcpu,
2788 unsigned index, u64 *data),
2789 int writeback)
2790{
2791 struct kvm_msrs msrs;
2792 struct kvm_msr_entry *entries;
2793 int r, n;
2794 unsigned size;
2795
2796 r = -EFAULT;
2797 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2798 goto out;
2799
2800 r = -E2BIG;
2801 if (msrs.nmsrs >= MAX_IO_MSRS)
2802 goto out;
2803
313a3dc7 2804 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2805 entries = memdup_user(user_msrs->entries, size);
2806 if (IS_ERR(entries)) {
2807 r = PTR_ERR(entries);
313a3dc7 2808 goto out;
ff5c2c03 2809 }
313a3dc7
CO		 2810
2811 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2812 if (r < 0)
2813 goto out_free;
2814
2815 r = -EFAULT;
2816 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2817 goto out_free;
2818
2819 r = n;
2820
2821out_free:
7a73c028 2822 kfree(entries);
313a3dc7
CO		 2823out:
2824 return r;
2825}
2826
4d5422ce
WL		 2827static inline bool kvm_can_mwait_in_guest(void)
2828{
2829 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2830 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2831 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2832}
2833
784aa3d7 2834int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2835{
4d5422ce 2836 int r = 0;
018d00d2
ZX		 2837
2838 switch (ext) {
2839 case KVM_CAP_IRQCHIP:
2840 case KVM_CAP_HLT:
2841 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2842 case KVM_CAP_SET_TSS_ADDR:
07716717 2843 case KVM_CAP_EXT_CPUID:
9c15bb1d 2844 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2845 case KVM_CAP_CLOCKSOURCE:
7837699f 2846 case KVM_CAP_PIT:
a28e4f5a 2847 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2848 case KVM_CAP_MP_STATE:
ed848624 2849 case KVM_CAP_SYNC_MMU:
a355c85c 2850 case KVM_CAP_USER_NMI:
52d939a0 2851 case KVM_CAP_REINJECT_CONTROL:
4925663a 2852 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2853 case KVM_CAP_IOEVENTFD:
f848a5a8 2854 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2855 case KVM_CAP_PIT2:
e9f42757 2856 case KVM_CAP_PIT_STATE2:
b927a3ce 2857 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2858 case KVM_CAP_XEN_HVM:
3cfc3092 2859 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2860 case KVM_CAP_HYPERV:
10388a07 2861 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2862 case KVM_CAP_HYPERV_SPIN:
5c919412 2863 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2864 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2865 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2866 case KVM_CAP_HYPERV_EVENTFD:
ab9f4ecb 2867 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2868 case KVM_CAP_DEBUGREGS:
d2be1651 2869 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2870 case KVM_CAP_XSAVE:
344d9588 2871 case KVM_CAP_ASYNC_PF:
92a1f12d 2872 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2873 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2874 case KVM_CAP_READONLY_MEM:
5f66b620 2875 case KVM_CAP_HYPERV_TIME:
100943c5 2876 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2877 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2878 case KVM_CAP_ENABLE_CAP_VM:
2879 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2880 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2881 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2882 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2883 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2884 r = 1;
2885 break;
01643c51
KH		 2886 case KVM_CAP_SYNC_REGS:
2887 r = KVM_SYNC_X86_VALID_FIELDS;
2888 break;
e3fd9a93
PB		 2889 case KVM_CAP_ADJUST_CLOCK:
2890 r = KVM_CLOCK_TSC_STABLE;
2891 break;
4d5422ce 2892 case KVM_CAP_X86_DISABLE_EXITS:
b31c114b 2893 r |= KVM_X86_DISABLE_EXITS_HTL | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 2894 if(kvm_can_mwait_in_guest())
2895 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 2896 break;
6d396b55
PB		 2897 case KVM_CAP_X86_SMM:
2898 /* SMBASE is usually relocated above 1M on modern chipsets,
2899 * and SMM handlers might indeed rely on 4G segment limits,
2900 * so do not report SMM to be available if real mode is
2901 * emulated via vm86 mode. Still, do not go to great lengths
2902 * to avoid userspace's usage of the feature, because it is a
2903 * fringe case that is not enabled except via specific settings
2904 * of the module parameters.
2905 */
2906 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2907 break;
774ead3a
AK		 2908 case KVM_CAP_VAPIC:
2909 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2910 break;
f725230a 2911 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2912 r = KVM_SOFT_MAX_VCPUS;
2913 break;
2914 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2915 r = KVM_MAX_VCPUS;
2916 break;
a988b910 2917 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2918 r = KVM_USER_MEM_SLOTS;
a988b910 2919 break;
a68a6a72
MT		 2920 case KVM_CAP_PV_MMU: /* obsolete */
2921 r = 0;
2f333bcb 2922 break;
890ca9ae
HY		 2923 case KVM_CAP_MCE:
2924 r = KVM_MAX_MCE_BANKS;
2925 break;
2d5b5a66 2926 case KVM_CAP_XCRS:
d366bf7e 2927 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2928 break;
92a1f12d
JR		 2929 case KVM_CAP_TSC_CONTROL:
2930 r = kvm_has_tsc_control;
2931 break;
37131313
RK		 2932 case KVM_CAP_X2APIC_API:
2933 r = KVM_X2APIC_API_VALID_FLAGS;
2934 break;
018d00d2 2935 default:
018d00d2
ZX		 2936 break;
2937 }
2938 return r;
2939
2940}
2941
043405e1
CO		 2942long kvm_arch_dev_ioctl(struct file *filp,
2943 unsigned int ioctl, unsigned long arg)
2944{
2945 void __user *argp = (void __user *)arg;
2946 long r;
2947
2948 switch (ioctl) {
2949 case KVM_GET_MSR_INDEX_LIST: {
2950 struct kvm_msr_list __user *user_msr_list = argp;
2951 struct kvm_msr_list msr_list;
2952 unsigned n;
2953
2954 r = -EFAULT;
2955 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2956 goto out;
2957 n = msr_list.nmsrs;
62ef68bb 2958 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2959 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2960 goto out;
2961 r = -E2BIG;
e125e7b6 2962 if (n < msr_list.nmsrs)
043405e1
CO		 2963 goto out;
2964 r = -EFAULT;
2965 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2966 num_msrs_to_save * sizeof(u32)))
2967 goto out;
e125e7b6 2968 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2969 &emulated_msrs,
62ef68bb 2970 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2971 goto out;
2972 r = 0;
2973 break;
2974 }
9c15bb1d
BP		 2975 case KVM_GET_SUPPORTED_CPUID:
2976 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2977 struct kvm_cpuid2 __user *cpuid_arg = argp;
2978 struct kvm_cpuid2 cpuid;
2979
2980 r = -EFAULT;
2981 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2982 goto out;
9c15bb1d
BP		 2983
2984 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2985 ioctl);
674eea0f
AK		 2986 if (r)
2987 goto out;
2988
2989 r = -EFAULT;
2990 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2991 goto out;
2992 r = 0;
2993 break;
2994 }
890ca9ae 2995 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2996 r = -EFAULT;
c45dcc71
AR		 2997 if (copy_to_user(argp, &kvm_mce_cap_supported,
2998 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2999 goto out;
3000 r = 0;
3001 break;
801e459a
TL		 3002 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3003 struct kvm_msr_list __user *user_msr_list = argp;
3004 struct kvm_msr_list msr_list;
3005 unsigned int n;
3006
3007 r = -EFAULT;
3008 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3009 goto out;
3010 n = msr_list.nmsrs;
3011 msr_list.nmsrs = num_msr_based_features;
3012 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3013 goto out;
3014 r = -E2BIG;
3015 if (n < msr_list.nmsrs)
3016 goto out;
3017 r = -EFAULT;
3018 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3019 num_msr_based_features * sizeof(u32)))
3020 goto out;
3021 r = 0;
3022 break;
3023 }
3024 case KVM_GET_MSRS:
3025 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3026 break;
890ca9ae 3027 }
043405e1
CO		 3028 default:
3029 r = -EINVAL;
3030 }
3031out:
3032 return r;
3033}
3034
f5f48ee1
SY		 3035static void wbinvd_ipi(void *garbage)
3036{
3037 wbinvd();
3038}
3039
3040static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3041{
e0f0bbc5 3042 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3043}
3044
313a3dc7
CO		 3045void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3046{
f5f48ee1
SY		 3047 /* Address WBINVD may be executed by guest */
3048 if (need_emulate_wbinvd(vcpu)) {
3049 if (kvm_x86_ops->has_wbinvd_exit())
3050 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3051 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3052 smp_call_function_single(vcpu->cpu,
3053 wbinvd_ipi, NULL, 1);
3054 }
3055
313a3dc7 3056 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3057
0dd6a6ed
ZA		 3058 /* Apply any externally detected TSC adjustments (due to suspend) */
3059 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3060 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3061 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3062 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3063 }
8f6055cb 3064
b0c39dc6 3065 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3066 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3067 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3068 if (tsc_delta < 0)
3069 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3070
b0c39dc6 3071 if (kvm_check_tsc_unstable()) {
07c1419a 3072 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3073 vcpu->arch.last_guest_tsc);
a545ab6a 3074 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3075 vcpu->arch.tsc_catchup = 1;
c285545f 3076 }
a749e247
PB		 3077
3078 if (kvm_lapic_hv_timer_in_use(vcpu))
3079 kvm_lapic_restart_hv_timer(vcpu);
3080
d98d07ca
MT		 3081 /*
3082 * On a host with synchronized TSC, there is no need to update
3083 * kvmclock on vcpu->cpu migration
3084 */
3085 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3086 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3087 if (vcpu->cpu != cpu)
1bd2009e 3088 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3089 vcpu->cpu = cpu;
6b7d7e76 3090 }
c9aaa895 3091
c9aaa895 3092 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3093}
3094
0b9f6c46
PX		 3095static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3096{
3097 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3098 return;
3099
fa55eedd 3100 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3101
4e335d9e 3102 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3103 &vcpu->arch.st.steal.preempted,
3104 offsetof(struct kvm_steal_time, preempted),
3105 sizeof(vcpu->arch.st.steal.preempted));
3106}
3107
313a3dc7
CO		 3108void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3109{
cc0d907c 3110 int idx;
de63ad4c
LM		 3111
3112 if (vcpu->preempted)
3113 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3114
931f261b
AA		 3115 /*
3116 * Disable page faults because we're in atomic context here.
3117 * kvm_write_guest_offset_cached() would call might_fault()
3118 * that relies on pagefault_disable() to tell if there's a
3119 * bug. NOTE: the write to guest memory may not go through if
3120 * during postcopy live migration or if there's heavy guest
3121 * paging.
3122 */
3123 pagefault_disable();
cc0d907c
AA		 3124 /*
3125 * kvm_memslots() will be called by
3126 * kvm_write_guest_offset_cached() so take the srcu lock.
3127 */
3128 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3129 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3130 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3131 pagefault_enable();
02daab21 3132 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3133 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3134 /*
3135 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3136 * on every vmexit, but if not, we might have a stale dr6 from the
3137 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3138 */
3139 set_debugreg(0, 6);
313a3dc7
CO		 3140}
3141
313a3dc7
CO		 3142static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3143 struct kvm_lapic_state *s)
3144{
fa59cc00 3145 if (vcpu->arch.apicv_active)
d62caabb
AS		 3146 kvm_x86_ops->sync_pir_to_irr(vcpu);
3147
a92e2543 3148 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3149}
3150
3151static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3152 struct kvm_lapic_state *s)
3153{
a92e2543
RK		 3154 int r;
3155
3156 r = kvm_apic_set_state(vcpu, s);
3157 if (r)
3158 return r;
cb142eb7 3159 update_cr8_intercept(vcpu);
313a3dc7
CO		 3160
3161 return 0;
3162}
3163
127a457a
MG		 3164static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3165{
3166 return (!lapic_in_kernel(vcpu) ||
3167 kvm_apic_accept_pic_intr(vcpu));
3168}
3169
782d422b
MG		 3170/*
3171 * if userspace requested an interrupt window, check that the
3172 * interrupt window is open.
3173 *
3174 * No need to exit to userspace if we already have an interrupt queued.
3175 */
3176static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3177{
3178 return kvm_arch_interrupt_allowed(vcpu) &&
3179 !kvm_cpu_has_interrupt(vcpu) &&
3180 !kvm_event_needs_reinjection(vcpu) &&
3181 kvm_cpu_accept_dm_intr(vcpu);
3182}
3183
f77bc6a4
ZX		 3184static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3185 struct kvm_interrupt *irq)
3186{
02cdb50f 3187 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3188 return -EINVAL;
1c1a9ce9
SR		 3189
3190 if (!irqchip_in_kernel(vcpu->kvm)) {
3191 kvm_queue_interrupt(vcpu, irq->irq, false);
3192 kvm_make_request(KVM_REQ_EVENT, vcpu);
3193 return 0;
3194 }
3195
3196 /*
3197 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3198 * fail for in-kernel 8259.
3199 */
3200 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3201 return -ENXIO;
f77bc6a4 3202
1c1a9ce9
SR		 3203 if (vcpu->arch.pending_external_vector != -1)
3204 return -EEXIST;
f77bc6a4 3205
1c1a9ce9 3206 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3207 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3208 return 0;
3209}
3210
c4abb7c9
JK		 3211static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3212{
c4abb7c9 3213 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3214
3215 return 0;
3216}
3217
f077825a
PB		 3218static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3219{
64d60670
PB		 3220 kvm_make_request(KVM_REQ_SMI, vcpu);
3221
f077825a
PB		 3222 return 0;
3223}
3224
b209749f
AK		 3225static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3226 struct kvm_tpr_access_ctl *tac)
3227{
3228 if (tac->flags)
3229 return -EINVAL;
3230 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3231 return 0;
3232}
3233
890ca9ae
HY		 3234static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3235 u64 mcg_cap)
3236{
3237 int r;
3238 unsigned bank_num = mcg_cap & 0xff, bank;
3239
3240 r = -EINVAL;
a9e38c3e 3241 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3242 goto out;
c45dcc71 3243 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3244 goto out;
3245 r = 0;
3246 vcpu->arch.mcg_cap = mcg_cap;
3247 /* Init IA32_MCG_CTL to all 1s */
3248 if (mcg_cap & MCG_CTL_P)
3249 vcpu->arch.mcg_ctl = ~(u64)0;
3250 /* Init IA32_MCi_CTL to all 1s */
3251 for (bank = 0; bank < bank_num; bank++)
3252 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3253
3254 if (kvm_x86_ops->setup_mce)
3255 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3256out:
3257 return r;
3258}
3259
3260static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3261 struct kvm_x86_mce *mce)
3262{
3263 u64 mcg_cap = vcpu->arch.mcg_cap;
3264 unsigned bank_num = mcg_cap & 0xff;
3265 u64 *banks = vcpu->arch.mce_banks;
3266
3267 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3268 return -EINVAL;
3269 /*
3270 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3271 * reporting is disabled
3272 */
3273 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3274 vcpu->arch.mcg_ctl != ~(u64)0)
3275 return 0;
3276 banks += 4 * mce->bank;
3277 /*
3278 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3279 * reporting is disabled for the bank
3280 */
3281 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3282 return 0;
3283 if (mce->status & MCI_STATUS_UC) {
3284 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3285 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3286 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3287 return 0;
3288 }
3289 if (banks[1] & MCI_STATUS_VAL)
3290 mce->status |= MCI_STATUS_OVER;
3291 banks[2] = mce->addr;
3292 banks[3] = mce->misc;
3293 vcpu->arch.mcg_status = mce->mcg_status;
3294 banks[1] = mce->status;
3295 kvm_queue_exception(vcpu, MC_VECTOR);
3296 } else if (!(banks[1] & MCI_STATUS_VAL)
3297 || !(banks[1] & MCI_STATUS_UC)) {
3298 if (banks[1] & MCI_STATUS_VAL)
3299 mce->status |= MCI_STATUS_OVER;
3300 banks[2] = mce->addr;
3301 banks[3] = mce->misc;
3302 banks[1] = mce->status;
3303 } else
3304 banks[1] |= MCI_STATUS_OVER;
3305 return 0;
3306}
3307
3cfc3092
JK		 3308static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3309 struct kvm_vcpu_events *events)
3310{
7460fb4a 3311 process_nmi(vcpu);
664f8e26
WL		 3312 /*
3313 * FIXME: pass injected and pending separately. This is only
3314 * needed for nested virtualization, whose state cannot be
3315 * migrated yet. For now we can combine them.
3316 */
03b82a30 3317 events->exception.injected =
664f8e26
WL		 3318 (vcpu->arch.exception.pending ||
3319 vcpu->arch.exception.injected) &&
03b82a30 3320 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3321 events->exception.nr = vcpu->arch.exception.nr;
3322 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3323 events->exception.pad = 0;
3cfc3092
JK		 3324 events->exception.error_code = vcpu->arch.exception.error_code;
3325
03b82a30 3326 events->interrupt.injected =
04140b41 3327 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3328 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3329 events->interrupt.soft = 0;
37ccdcbe 3330 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3331
3332 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3333 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3334 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3335 events->nmi.pad = 0;
3cfc3092 3336
66450a21 3337 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3338
f077825a
PB		 3339 events->smi.smm = is_smm(vcpu);
3340 events->smi.pending = vcpu->arch.smi_pending;
3341 events->smi.smm_inside_nmi =
3342 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3343 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3344
dab4b911 3345 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3346 | KVM_VCPUEVENT_VALID_SHADOW
3347 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3348 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3349}
3350
6ef4e07e
XG		 3351static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3352
3cfc3092
JK		 3353static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3354 struct kvm_vcpu_events *events)
3355{
dab4b911 3356 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3357 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3358 | KVM_VCPUEVENT_VALID_SHADOW
3359 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3360 return -EINVAL;
3361
78e546c8 3362 if (events->exception.injected &&
28d06353
JM		 3363 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3364 is_guest_mode(vcpu)))
78e546c8
PB		 3365 return -EINVAL;
3366
28bf2888
DH		 3367 /* INITs are latched while in SMM */
3368 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3369 (events->smi.smm || events->smi.pending) &&
3370 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3371 return -EINVAL;
3372
7460fb4a 3373 process_nmi(vcpu);
664f8e26 3374 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3375 vcpu->arch.exception.pending = events->exception.injected;
3376 vcpu->arch.exception.nr = events->exception.nr;
3377 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3378 vcpu->arch.exception.error_code = events->exception.error_code;
3379
04140b41 3380 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3381 vcpu->arch.interrupt.nr = events->interrupt.nr;
3382 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3383 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3384 kvm_x86_ops->set_interrupt_shadow(vcpu,
3385 events->interrupt.shadow);
3cfc3092
JK		 3386
3387 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3388 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3389 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3390 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3391
66450a21 3392 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3393 lapic_in_kernel(vcpu))
66450a21 3394 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3395
f077825a 3396 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3397 u32 hflags = vcpu->arch.hflags;
f077825a 3398 if (events->smi.smm)
6ef4e07e 3399 hflags |= HF_SMM_MASK;
f077825a 3400 else
6ef4e07e
XG		 3401 hflags &= ~HF_SMM_MASK;
3402 kvm_set_hflags(vcpu, hflags);
3403
f077825a 3404 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3405
3406 if (events->smi.smm) {
3407 if (events->smi.smm_inside_nmi)
3408 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3409 else
f4ef1910
WL		 3410 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3411 if (lapic_in_kernel(vcpu)) {
3412 if (events->smi.latched_init)
3413 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3414 else
3415 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3416 }
f077825a
PB		 3417 }
3418 }
3419
3842d135
AK		 3420 kvm_make_request(KVM_REQ_EVENT, vcpu);
3421
3cfc3092
JK		 3422 return 0;
3423}
3424
a1efbe77
JK		 3425static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3426 struct kvm_debugregs *dbgregs)
3427{
73aaf249
JK		 3428 unsigned long val;
3429
a1efbe77 3430 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3431 kvm_get_dr(vcpu, 6, &val);
73aaf249 3432 dbgregs->dr6 = val;
a1efbe77
JK		 3433 dbgregs->dr7 = vcpu->arch.dr7;
3434 dbgregs->flags = 0;
97e69aa6 3435 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3436}
3437
3438static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3439 struct kvm_debugregs *dbgregs)
3440{
3441 if (dbgregs->flags)
3442 return -EINVAL;
3443
d14bdb55
PB		 3444 if (dbgregs->dr6 & ~0xffffffffull)
3445 return -EINVAL;
3446 if (dbgregs->dr7 & ~0xffffffffull)
3447 return -EINVAL;
3448
a1efbe77 3449 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3450 kvm_update_dr0123(vcpu);
a1efbe77 3451 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3452 kvm_update_dr6(vcpu);
a1efbe77 3453 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3454 kvm_update_dr7(vcpu);
a1efbe77 3455
a1efbe77
JK		 3456 return 0;
3457}
3458
df1daba7
PB		 3459#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3460
3461static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3462{
c47ada30 3463 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3464 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3465 u64 valid;
3466
3467 /*
3468 * Copy legacy XSAVE area, to avoid complications with CPUID
3469 * leaves 0 and 1 in the loop below.
3470 */
3471 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3472
3473 /* Set XSTATE_BV */
00c87e9a 3474 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3475 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3476
3477 /*
3478 * Copy each region from the possibly compacted offset to the
3479 * non-compacted offset.
3480 */
d91cab78 3481 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3482 while (valid) {
3483 u64 feature = valid & -valid;
3484 int index = fls64(feature) - 1;
3485 void *src = get_xsave_addr(xsave, feature);
3486
3487 if (src) {
3488 u32 size, offset, ecx, edx;
3489 cpuid_count(XSTATE_CPUID, index,
3490 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3491 if (feature == XFEATURE_MASK_PKRU)
3492 memcpy(dest + offset, &vcpu->arch.pkru,
3493 sizeof(vcpu->arch.pkru));
3494 else
3495 memcpy(dest + offset, src, size);
3496
df1daba7
PB		 3497 }
3498
3499 valid -= feature;
3500 }
3501}
3502
3503static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3504{
c47ada30 3505 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3506 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3507 u64 valid;
3508
3509 /*
3510 * Copy legacy XSAVE area, to avoid complications with CPUID
3511 * leaves 0 and 1 in the loop below.
3512 */
3513 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3514
3515 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3516 xsave->header.xfeatures = xstate_bv;
782511b0 3517 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3518 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3519
3520 /*
3521 * Copy each region from the non-compacted offset to the
3522 * possibly compacted offset.
3523 */
d91cab78 3524 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3525 while (valid) {
3526 u64 feature = valid & -valid;
3527 int index = fls64(feature) - 1;
3528 void *dest = get_xsave_addr(xsave, feature);
3529
3530 if (dest) {
3531 u32 size, offset, ecx, edx;
3532 cpuid_count(XSTATE_CPUID, index,
3533 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3534 if (feature == XFEATURE_MASK_PKRU)
3535 memcpy(&vcpu->arch.pkru, src + offset,
3536 sizeof(vcpu->arch.pkru));
3537 else
3538 memcpy(dest, src + offset, size);
ee4100da 3539 }
df1daba7
PB		 3540
3541 valid -= feature;
3542 }
3543}
3544
2d5b5a66
SY		 3545static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3546 struct kvm_xsave *guest_xsave)
3547{
d366bf7e 3548 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3549 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3550 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3551 } else {
2d5b5a66 3552 memcpy(guest_xsave->region,
7366ed77 3553 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3554 sizeof(struct fxregs_state));
2d5b5a66 3555 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3556 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3557 }
3558}
3559
a575813b
WL		 3560#define XSAVE_MXCSR_OFFSET 24
3561
2d5b5a66
SY		 3562static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3563 struct kvm_xsave *guest_xsave)
3564{
3565 u64 xstate_bv =
3566 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3567 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3568
d366bf7e 3569 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3570 /*
3571 * Here we allow setting states that are not present in
3572 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3573 * with old userspace.
3574 */
a575813b
WL		 3575 if (xstate_bv & ~kvm_supported_xcr0() ||
3576 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3577 return -EINVAL;
df1daba7 3578 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3579 } else {
a575813b
WL		 3580 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3581 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3582 return -EINVAL;
7366ed77 3583 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3584 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3585 }
3586 return 0;
3587}
3588
3589static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3590 struct kvm_xcrs *guest_xcrs)
3591{
d366bf7e 3592 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3593 guest_xcrs->nr_xcrs = 0;
3594 return;
3595 }
3596
3597 guest_xcrs->nr_xcrs = 1;
3598 guest_xcrs->flags = 0;
3599 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3600 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3601}
3602
3603static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3604 struct kvm_xcrs *guest_xcrs)
3605{
3606 int i, r = 0;
3607
d366bf7e 3608 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3609 return -EINVAL;
3610
3611 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3612 return -EINVAL;
3613
3614 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3615 /* Only support XCR0 currently */
c67a04cb 3616 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3617 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3618 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3619 break;
3620 }
3621 if (r)
3622 r = -EINVAL;
3623 return r;
3624}
3625
1c0b28c2
EM		 3626/*
3627 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3628 * stopped by the hypervisor. This function will be called from the host only.
3629 * EINVAL is returned when the host attempts to set the flag for a guest that
3630 * does not support pv clocks.
3631 */
3632static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3633{
0b79459b 3634 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3635 return -EINVAL;
51d59c6b 3636 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3637 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3638 return 0;
3639}
3640
5c919412
AS		 3641static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3642 struct kvm_enable_cap *cap)
3643{
3644 if (cap->flags)
3645 return -EINVAL;
3646
3647 switch (cap->cap) {
efc479e6
RK		 3648 case KVM_CAP_HYPERV_SYNIC2:
3649 if (cap->args[0])
3650 return -EINVAL;
5c919412 3651 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3652 if (!irqchip_in_kernel(vcpu->kvm))
3653 return -EINVAL;
efc479e6
RK		 3654 return kvm_hv_activate_synic(vcpu, cap->cap ==
3655 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3656 default:
3657 return -EINVAL;
3658 }
3659}
3660
313a3dc7
CO		 3661long kvm_arch_vcpu_ioctl(struct file *filp,
3662 unsigned int ioctl, unsigned long arg)
3663{
3664 struct kvm_vcpu *vcpu = filp->private_data;
3665 void __user *argp = (void __user *)arg;
3666 int r;
d1ac91d8
AK		 3667 union {
3668 struct kvm_lapic_state *lapic;
3669 struct kvm_xsave *xsave;
3670 struct kvm_xcrs *xcrs;
3671 void *buffer;
3672 } u;
3673
9b062471
CD		 3674 vcpu_load(vcpu);
3675
d1ac91d8 3676 u.buffer = NULL;
313a3dc7
CO		 3677 switch (ioctl) {
3678 case KVM_GET_LAPIC: {
2204ae3c 3679 r = -EINVAL;
bce87cce 3680 if (!lapic_in_kernel(vcpu))
2204ae3c 3681 goto out;
d1ac91d8 3682 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3683
b772ff36 3684 r = -ENOMEM;
d1ac91d8 3685 if (!u.lapic)
b772ff36 3686 goto out;
d1ac91d8 3687 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3688 if (r)
3689 goto out;
3690 r = -EFAULT;
d1ac91d8 3691 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3692 goto out;
3693 r = 0;
3694 break;
3695 }
3696 case KVM_SET_LAPIC: {
2204ae3c 3697 r = -EINVAL;
bce87cce 3698 if (!lapic_in_kernel(vcpu))
2204ae3c 3699 goto out;
ff5c2c03 3700 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3701 if (IS_ERR(u.lapic)) {
3702 r = PTR_ERR(u.lapic);
3703 goto out_nofree;
3704 }
ff5c2c03 3705
d1ac91d8 3706 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3707 break;
3708 }
f77bc6a4
ZX		 3709 case KVM_INTERRUPT: {
3710 struct kvm_interrupt irq;
3711
3712 r = -EFAULT;
3713 if (copy_from_user(&irq, argp, sizeof irq))
3714 goto out;
3715 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3716 break;
3717 }
c4abb7c9
JK		 3718 case KVM_NMI: {
3719 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3720 break;
3721 }
f077825a
PB		 3722 case KVM_SMI: {
3723 r = kvm_vcpu_ioctl_smi(vcpu);
3724 break;
3725 }
313a3dc7
CO		 3726 case KVM_SET_CPUID: {
3727 struct kvm_cpuid __user *cpuid_arg = argp;
3728 struct kvm_cpuid cpuid;
3729
3730 r = -EFAULT;
3731 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3732 goto out;
3733 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3734 break;
3735 }
07716717
DK		 3736 case KVM_SET_CPUID2: {
3737 struct kvm_cpuid2 __user *cpuid_arg = argp;
3738 struct kvm_cpuid2 cpuid;
3739
3740 r = -EFAULT;
3741 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3742 goto out;
3743 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3744 cpuid_arg->entries);
07716717
DK		 3745 break;
3746 }
3747 case KVM_GET_CPUID2: {
3748 struct kvm_cpuid2 __user *cpuid_arg = argp;
3749 struct kvm_cpuid2 cpuid;
3750
3751 r = -EFAULT;
3752 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3753 goto out;
3754 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3755 cpuid_arg->entries);
07716717
DK		 3756 if (r)
3757 goto out;
3758 r = -EFAULT;
3759 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3760 goto out;
3761 r = 0;
3762 break;
3763 }
801e459a
TL		 3764 case KVM_GET_MSRS: {
3765 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3766 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3767 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3768 break;
801e459a
TL		 3769 }
3770 case KVM_SET_MSRS: {
3771 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3772 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3773 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3774 break;
801e459a 3775 }
b209749f
AK		 3776 case KVM_TPR_ACCESS_REPORTING: {
3777 struct kvm_tpr_access_ctl tac;
3778
3779 r = -EFAULT;
3780 if (copy_from_user(&tac, argp, sizeof tac))
3781 goto out;
3782 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3783 if (r)
3784 goto out;
3785 r = -EFAULT;
3786 if (copy_to_user(argp, &tac, sizeof tac))
3787 goto out;
3788 r = 0;
3789 break;
3790 };
b93463aa
AK		 3791 case KVM_SET_VAPIC_ADDR: {
3792 struct kvm_vapic_addr va;
7301d6ab 3793 int idx;
b93463aa
AK		 3794
3795 r = -EINVAL;
35754c98 3796 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3797 goto out;
3798 r = -EFAULT;
3799 if (copy_from_user(&va, argp, sizeof va))
3800 goto out;
7301d6ab 3801 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3802 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3803 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3804 break;
3805 }
890ca9ae
HY		 3806 case KVM_X86_SETUP_MCE: {
3807 u64 mcg_cap;
3808
3809 r = -EFAULT;
3810 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3811 goto out;
3812 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3813 break;
3814 }
3815 case KVM_X86_SET_MCE: {
3816 struct kvm_x86_mce mce;
3817
3818 r = -EFAULT;
3819 if (copy_from_user(&mce, argp, sizeof mce))
3820 goto out;
3821 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3822 break;
3823 }
3cfc3092
JK		 3824 case KVM_GET_VCPU_EVENTS: {
3825 struct kvm_vcpu_events events;
3826
3827 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3828
3829 r = -EFAULT;
3830 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3831 break;
3832 r = 0;
3833 break;
3834 }
3835 case KVM_SET_VCPU_EVENTS: {
3836 struct kvm_vcpu_events events;
3837
3838 r = -EFAULT;
3839 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3840 break;
3841
3842 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3843 break;
3844 }
a1efbe77
JK		 3845 case KVM_GET_DEBUGREGS: {
3846 struct kvm_debugregs dbgregs;
3847
3848 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3849
3850 r = -EFAULT;
3851 if (copy_to_user(argp, &dbgregs,
3852 sizeof(struct kvm_debugregs)))
3853 break;
3854 r = 0;
3855 break;
3856 }
3857 case KVM_SET_DEBUGREGS: {
3858 struct kvm_debugregs dbgregs;
3859
3860 r = -EFAULT;
3861 if (copy_from_user(&dbgregs, argp,
3862 sizeof(struct kvm_debugregs)))
3863 break;
3864
3865 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3866 break;
3867 }
2d5b5a66 3868 case KVM_GET_XSAVE: {
d1ac91d8 3869 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3870 r = -ENOMEM;
d1ac91d8 3871 if (!u.xsave)
2d5b5a66
SY		 3872 break;
3873
d1ac91d8 3874 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3875
3876 r = -EFAULT;
d1ac91d8 3877 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3878 break;
3879 r = 0;
3880 break;
3881 }
3882 case KVM_SET_XSAVE: {
ff5c2c03 3883 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3884 if (IS_ERR(u.xsave)) {
3885 r = PTR_ERR(u.xsave);
3886 goto out_nofree;
3887 }
2d5b5a66 3888
d1ac91d8 3889 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3890 break;
3891 }
3892 case KVM_GET_XCRS: {
d1ac91d8 3893 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3894 r = -ENOMEM;
d1ac91d8 3895 if (!u.xcrs)
2d5b5a66
SY		 3896 break;
3897
d1ac91d8 3898 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3899
3900 r = -EFAULT;
d1ac91d8 3901 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3902 sizeof(struct kvm_xcrs)))
3903 break;
3904 r = 0;
3905 break;
3906 }
3907 case KVM_SET_XCRS: {
ff5c2c03 3908 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3909 if (IS_ERR(u.xcrs)) {
3910 r = PTR_ERR(u.xcrs);
3911 goto out_nofree;
3912 }
2d5b5a66 3913
d1ac91d8 3914 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3915 break;
3916 }
92a1f12d
JR		 3917 case KVM_SET_TSC_KHZ: {
3918 u32 user_tsc_khz;
3919
3920 r = -EINVAL;
92a1f12d
JR		 3921 user_tsc_khz = (u32)arg;
3922
3923 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3924 goto out;
3925
cc578287
ZA		 3926 if (user_tsc_khz == 0)
3927 user_tsc_khz = tsc_khz;
3928
381d585c
HZ		 3929 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3930 r = 0;
92a1f12d 3931
92a1f12d
JR		 3932 goto out;
3933 }
3934 case KVM_GET_TSC_KHZ: {
cc578287 3935 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3936 goto out;
3937 }
1c0b28c2
EM		 3938 case KVM_KVMCLOCK_CTRL: {
3939 r = kvm_set_guest_paused(vcpu);
3940 goto out;
3941 }
5c919412
AS		 3942 case KVM_ENABLE_CAP: {
3943 struct kvm_enable_cap cap;
3944
3945 r = -EFAULT;
3946 if (copy_from_user(&cap, argp, sizeof(cap)))
3947 goto out;
3948 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3949 break;
3950 }
313a3dc7
CO		 3951 default:
3952 r = -EINVAL;
3953 }
3954out:
d1ac91d8 3955 kfree(u.buffer);
9b062471
CD		 3956out_nofree:
3957 vcpu_put(vcpu);
313a3dc7
CO		 3958 return r;
3959}
3960
5b1c1493
CO		 3961int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3962{
3963 return VM_FAULT_SIGBUS;
3964}
3965
1fe779f8
CO		 3966static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3967{
3968 int ret;
3969
3970 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3971 return -EINVAL;
1fe779f8
CO		 3972 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3973 return ret;
3974}
3975
b927a3ce
SY		 3976static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3977 u64 ident_addr)
3978{
2ac52ab8 3979 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3980}
3981
1fe779f8
CO		 3982static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3983 u32 kvm_nr_mmu_pages)
3984{
3985 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3986 return -EINVAL;
3987
79fac95e 3988 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3989
3990 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3991 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3992
79fac95e 3993 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3994 return 0;
3995}
3996
3997static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3998{
39de71ec 3999 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4000}
4001
1fe779f8
CO		 4002static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4003{
90bca052 4004 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4005 int r;
4006
4007 r = 0;
4008 switch (chip->chip_id) {
4009 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4010 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4011 sizeof(struct kvm_pic_state));
4012 break;
4013 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4014 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4015 sizeof(struct kvm_pic_state));
4016 break;
4017 case KVM_IRQCHIP_IOAPIC:
33392b49 4018 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4019 break;
4020 default:
4021 r = -EINVAL;
4022 break;
4023 }
4024 return r;
4025}
4026
4027static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4028{
90bca052 4029 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4030 int r;
4031
4032 r = 0;
4033 switch (chip->chip_id) {
4034 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4035 spin_lock(&pic->lock);
4036 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4037 sizeof(struct kvm_pic_state));
90bca052 4038 spin_unlock(&pic->lock);
1fe779f8
CO		 4039 break;
4040 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4041 spin_lock(&pic->lock);
4042 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4043 sizeof(struct kvm_pic_state));
90bca052 4044 spin_unlock(&pic->lock);
1fe779f8
CO		 4045 break;
4046 case KVM_IRQCHIP_IOAPIC:
33392b49 4047 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4048 break;
4049 default:
4050 r = -EINVAL;
4051 break;
4052 }
90bca052 4053 kvm_pic_update_irq(pic);
1fe779f8
CO		 4054 return r;
4055}
4056
e0f63cb9
SY		 4057static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4058{
34f3941c
RK		 4059 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4060
4061 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4062
4063 mutex_lock(&kps->lock);
4064 memcpy(ps, &kps->channels, sizeof(*ps));
4065 mutex_unlock(&kps->lock);
2da29bcc 4066 return 0;
e0f63cb9
SY		 4067}
4068
4069static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4070{
0185604c 4071 int i;
09edea72
RK		 4072 struct kvm_pit *pit = kvm->arch.vpit;
4073
4074 mutex_lock(&pit->pit_state.lock);
34f3941c 4075 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4076 for (i = 0; i < 3; i++)
09edea72
RK		 4077 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4078 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4079 return 0;
e9f42757
BK		 4080}
4081
4082static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4083{
e9f42757
BK		 4084 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4085 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4086 sizeof(ps->channels));
4087 ps->flags = kvm->arch.vpit->pit_state.flags;
4088 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4089 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4090 return 0;
e9f42757
BK		 4091}
4092
4093static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4094{
2da29bcc 4095 int start = 0;
0185604c 4096 int i;
e9f42757 4097 u32 prev_legacy, cur_legacy;
09edea72
RK		 4098 struct kvm_pit *pit = kvm->arch.vpit;
4099
4100 mutex_lock(&pit->pit_state.lock);
4101 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4102 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4103 if (!prev_legacy && cur_legacy)
4104 start = 1;
09edea72
RK		 4105 memcpy(&pit->pit_state.channels, &ps->channels,
4106 sizeof(pit->pit_state.channels));
4107 pit->pit_state.flags = ps->flags;
0185604c 4108 for (i = 0; i < 3; i++)
09edea72 4109 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4110 start && i == 0);
09edea72 4111 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4112 return 0;
e0f63cb9
SY		 4113}
4114
52d939a0
MT		 4115static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4116 struct kvm_reinject_control *control)
4117{
71474e2f
RK		 4118 struct kvm_pit *pit = kvm->arch.vpit;
4119
4120 if (!pit)
52d939a0 4121 return -ENXIO;
b39c90b6 4122
71474e2f
RK		 4123 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4124 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4125 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4126 */
4127 mutex_lock(&pit->pit_state.lock);
4128 kvm_pit_set_reinject(pit, control->pit_reinject);
4129 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4130
52d939a0
MT		 4131 return 0;
4132}
4133
95d4c16c 4134/**
60c34612
TY		 4135 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4136 * @kvm: kvm instance
4137 * @log: slot id and address to which we copy the log
95d4c16c 4138 *
e108ff2f
PB		 4139 * Steps 1-4 below provide general overview of dirty page logging. See
4140 * kvm_get_dirty_log_protect() function description for additional details.
4141 *
4142 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4143 * always flush the TLB (step 4) even if previous step failed and the dirty
4144 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4145 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4146 * writes will be marked dirty for next log read.
95d4c16c 4147 *
60c34612
TY		 4148 * 1. Take a snapshot of the bit and clear it if needed.
4149 * 2. Write protect the corresponding page.
e108ff2f
PB		 4150 * 3. Copy the snapshot to the userspace.
4151 * 4. Flush TLB's if needed.
5bb064dc 4152 */
60c34612 4153int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4154{
60c34612 4155 bool is_dirty = false;
e108ff2f 4156 int r;
5bb064dc 4157
79fac95e 4158 mutex_lock(&kvm->slots_lock);
5bb064dc 4159
88178fd4
KH		 4160 /*
4161 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4162 */
4163 if (kvm_x86_ops->flush_log_dirty)
4164 kvm_x86_ops->flush_log_dirty(kvm);
4165
e108ff2f 4166 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4167
4168 /*
4169 * All the TLBs can be flushed out of mmu lock, see the comments in
4170 * kvm_mmu_slot_remove_write_access().
4171 */
e108ff2f 4172 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4173 if (is_dirty)
4174 kvm_flush_remote_tlbs(kvm);
4175
79fac95e 4176 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4177 return r;
4178}
4179
aa2fbe6d
YZ		 4180int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4181 bool line_status)
23d43cf9
CD		 4182{
4183 if (!irqchip_in_kernel(kvm))
4184 return -ENXIO;
4185
4186 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4187 irq_event->irq, irq_event->level,
4188 line_status);
23d43cf9
CD		 4189 return 0;
4190}
4191
90de4a18
NA		 4192static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4193 struct kvm_enable_cap *cap)
4194{
4195 int r;
4196
4197 if (cap->flags)
4198 return -EINVAL;
4199
4200 switch (cap->cap) {
4201 case KVM_CAP_DISABLE_QUIRKS:
4202 kvm->arch.disabled_quirks = cap->args[0];
4203 r = 0;
4204 break;
49df6397
SR		 4205 case KVM_CAP_SPLIT_IRQCHIP: {
4206 mutex_lock(&kvm->lock);
b053b2ae
SR		 4207 r = -EINVAL;
4208 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4209 goto split_irqchip_unlock;
49df6397
SR		 4210 r = -EEXIST;
4211 if (irqchip_in_kernel(kvm))
4212 goto split_irqchip_unlock;
557abc40 4213 if (kvm->created_vcpus)
49df6397
SR		 4214 goto split_irqchip_unlock;
4215 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4216 if (r)
49df6397
SR		 4217 goto split_irqchip_unlock;
4218 /* Pairs with irqchip_in_kernel. */
4219 smp_wmb();
49776faf 4220 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4221 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4222 r = 0;
4223split_irqchip_unlock:
4224 mutex_unlock(&kvm->lock);
4225 break;
4226 }
37131313
RK		 4227 case KVM_CAP_X2APIC_API:
4228 r = -EINVAL;
4229 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4230 break;
4231
4232 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4233 kvm->arch.x2apic_format = true;
c519265f
RK		 4234 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4235 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4236
4237 r = 0;
4238 break;
4d5422ce
WL		 4239 case KVM_CAP_X86_DISABLE_EXITS:
4240 r = -EINVAL;
4241 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4242 break;
4243
4244 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4245 kvm_can_mwait_in_guest())
4246 kvm->arch.mwait_in_guest = true;
caa057a2
WL		 4247 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HTL)
4248 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4249 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4250 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4251 r = 0;
4252 break;
90de4a18
NA		 4253 default:
4254 r = -EINVAL;
4255 break;
4256 }
4257 return r;
4258}
4259
1fe779f8
CO		 4260long kvm_arch_vm_ioctl(struct file *filp,
4261 unsigned int ioctl, unsigned long arg)
4262{
4263 struct kvm *kvm = filp->private_data;
4264 void __user *argp = (void __user *)arg;
367e1319 4265 int r = -ENOTTY;
f0d66275
DH		 4266 /*
4267 * This union makes it completely explicit to gcc-3.x
4268 * that these two variables' stack usage should be
4269 * combined, not added together.
4270 */
4271 union {
4272 struct kvm_pit_state ps;
e9f42757 4273 struct kvm_pit_state2 ps2;
c5ff41ce 4274 struct kvm_pit_config pit_config;
f0d66275 4275 } u;
1fe779f8
CO		 4276
4277 switch (ioctl) {
4278 case KVM_SET_TSS_ADDR:
4279 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4280 break;
b927a3ce
SY		 4281 case KVM_SET_IDENTITY_MAP_ADDR: {
4282 u64 ident_addr;
4283
1af1ac91
DH		 4284 mutex_lock(&kvm->lock);
4285 r = -EINVAL;
4286 if (kvm->created_vcpus)
4287 goto set_identity_unlock;
b927a3ce
SY		 4288 r = -EFAULT;
4289 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4290 goto set_identity_unlock;
b927a3ce 4291 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4292set_identity_unlock:
4293 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4294 break;
4295 }
1fe779f8
CO		 4296 case KVM_SET_NR_MMU_PAGES:
4297 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4298 break;
4299 case KVM_GET_NR_MMU_PAGES:
4300 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4301 break;
3ddea128 4302 case KVM_CREATE_IRQCHIP: {
3ddea128 4303 mutex_lock(&kvm->lock);
09941366 4304
3ddea128 4305 r = -EEXIST;
35e6eaa3 4306 if (irqchip_in_kernel(kvm))
3ddea128 4307 goto create_irqchip_unlock;
09941366 4308
3e515705 4309 r = -EINVAL;
557abc40 4310 if (kvm->created_vcpus)
3e515705 4311 goto create_irqchip_unlock;
09941366
RK		 4312
4313 r = kvm_pic_init(kvm);
4314 if (r)
3ddea128 4315 goto create_irqchip_unlock;
09941366
RK		 4316
4317 r = kvm_ioapic_init(kvm);
4318 if (r) {
09941366 4319 kvm_pic_destroy(kvm);
3ddea128 4320 goto create_irqchip_unlock;
09941366
RK		 4321 }
4322
399ec807
AK		 4323 r = kvm_setup_default_irq_routing(kvm);
4324 if (r) {
72bb2fcd 4325 kvm_ioapic_destroy(kvm);
09941366 4326 kvm_pic_destroy(kvm);
71ba994c 4327 goto create_irqchip_unlock;
399ec807 4328 }
49776faf 4329 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4330 smp_wmb();
49776faf 4331 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4332 create_irqchip_unlock:
4333 mutex_unlock(&kvm->lock);
1fe779f8 4334 break;
3ddea128 4335 }
7837699f 4336 case KVM_CREATE_PIT:
c5ff41ce
JK		 4337 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4338 goto create_pit;
4339 case KVM_CREATE_PIT2:
4340 r = -EFAULT;
4341 if (copy_from_user(&u.pit_config, argp,
4342 sizeof(struct kvm_pit_config)))
4343 goto out;
4344 create_pit:
250715a6 4345 mutex_lock(&kvm->lock);
269e05e4
AK		 4346 r = -EEXIST;
4347 if (kvm->arch.vpit)
4348 goto create_pit_unlock;
7837699f 4349 r = -ENOMEM;
c5ff41ce 4350 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4351 if (kvm->arch.vpit)
4352 r = 0;
269e05e4 4353 create_pit_unlock:
250715a6 4354 mutex_unlock(&kvm->lock);
7837699f 4355 break;
1fe779f8
CO		 4356 case KVM_GET_IRQCHIP: {
4357 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4358 struct kvm_irqchip *chip;
1fe779f8 4359
ff5c2c03
SL		 4360 chip = memdup_user(argp, sizeof(*chip));
4361 if (IS_ERR(chip)) {
4362 r = PTR_ERR(chip);
1fe779f8 4363 goto out;
ff5c2c03
SL		 4364 }
4365
1fe779f8 4366 r = -ENXIO;
826da321 4367 if (!irqchip_kernel(kvm))
f0d66275
DH		 4368 goto get_irqchip_out;
4369 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4370 if (r)
f0d66275 4371 goto get_irqchip_out;
1fe779f8 4372 r = -EFAULT;
f0d66275
DH		 4373 if (copy_to_user(argp, chip, sizeof *chip))
4374 goto get_irqchip_out;
1fe779f8 4375 r = 0;
f0d66275
DH		 4376 get_irqchip_out:
4377 kfree(chip);
1fe779f8
CO		 4378 break;
4379 }
4380 case KVM_SET_IRQCHIP: {
4381 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4382 struct kvm_irqchip *chip;
1fe779f8 4383
ff5c2c03
SL		 4384 chip = memdup_user(argp, sizeof(*chip));
4385 if (IS_ERR(chip)) {
4386 r = PTR_ERR(chip);
1fe779f8 4387 goto out;
ff5c2c03
SL		 4388 }
4389
1fe779f8 4390 r = -ENXIO;
826da321 4391 if (!irqchip_kernel(kvm))
f0d66275
DH		 4392 goto set_irqchip_out;
4393 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4394 if (r)
f0d66275 4395 goto set_irqchip_out;
1fe779f8 4396 r = 0;
f0d66275
DH		 4397 set_irqchip_out:
4398 kfree(chip);
1fe779f8
CO		 4399 break;
4400 }
e0f63cb9 4401 case KVM_GET_PIT: {
e0f63cb9 4402 r = -EFAULT;
f0d66275 4403 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4404 goto out;
4405 r = -ENXIO;
4406 if (!kvm->arch.vpit)
4407 goto out;
f0d66275 4408 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4409 if (r)
4410 goto out;
4411 r = -EFAULT;
f0d66275 4412 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4413 goto out;
4414 r = 0;
4415 break;
4416 }
4417 case KVM_SET_PIT: {
e0f63cb9 4418 r = -EFAULT;
f0d66275 4419 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4420 goto out;
4421 r = -ENXIO;
4422 if (!kvm->arch.vpit)
4423 goto out;
f0d66275 4424 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4425 break;
4426 }
e9f42757
BK		 4427 case KVM_GET_PIT2: {
4428 r = -ENXIO;
4429 if (!kvm->arch.vpit)
4430 goto out;
4431 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4432 if (r)
4433 goto out;
4434 r = -EFAULT;
4435 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4436 goto out;
4437 r = 0;
4438 break;
4439 }
4440 case KVM_SET_PIT2: {
4441 r = -EFAULT;
4442 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4443 goto out;
4444 r = -ENXIO;
4445 if (!kvm->arch.vpit)
4446 goto out;
4447 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4448 break;
4449 }
52d939a0
MT		 4450 case KVM_REINJECT_CONTROL: {
4451 struct kvm_reinject_control control;
4452 r = -EFAULT;
4453 if (copy_from_user(&control, argp, sizeof(control)))
4454 goto out;
4455 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4456 break;
4457 }
d71ba788
PB		 4458 case KVM_SET_BOOT_CPU_ID:
4459 r = 0;
4460 mutex_lock(&kvm->lock);
557abc40 4461 if (kvm->created_vcpus)
d71ba788
PB		 4462 r = -EBUSY;
4463 else
4464 kvm->arch.bsp_vcpu_id = arg;
4465 mutex_unlock(&kvm->lock);
4466 break;
ffde22ac 4467 case KVM_XEN_HVM_CONFIG: {
51776043 4468 struct kvm_xen_hvm_config xhc;
ffde22ac 4469 r = -EFAULT;
51776043 4470 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4471 goto out;
4472 r = -EINVAL;
51776043 4473 if (xhc.flags)
ffde22ac 4474 goto out;
51776043 4475 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4476 r = 0;
4477 break;
4478 }
afbcf7ab 4479 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4480 struct kvm_clock_data user_ns;
4481 u64 now_ns;
afbcf7ab
GC		 4482
4483 r = -EFAULT;
4484 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4485 goto out;
4486
4487 r = -EINVAL;
4488 if (user_ns.flags)
4489 goto out;
4490
4491 r = 0;
0bc48bea
RK		 4492 /*
4493 * TODO: userspace has to take care of races with VCPU_RUN, so
4494 * kvm_gen_update_masterclock() can be cut down to locked
4495 * pvclock_update_vm_gtod_copy().
4496 */
4497 kvm_gen_update_masterclock(kvm);
e891a32e 4498 now_ns = get_kvmclock_ns(kvm);
108b249c 4499 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4500 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4501 break;
4502 }
4503 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4504 struct kvm_clock_data user_ns;
4505 u64 now_ns;
4506
e891a32e 4507 now_ns = get_kvmclock_ns(kvm);
108b249c 4508 user_ns.clock = now_ns;
e3fd9a93 4509 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4510 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4511
4512 r = -EFAULT;
4513 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4514 goto out;
4515 r = 0;
4516 break;
4517 }
90de4a18
NA		 4518 case KVM_ENABLE_CAP: {
4519 struct kvm_enable_cap cap;
afbcf7ab 4520
90de4a18
NA		 4521 r = -EFAULT;
4522 if (copy_from_user(&cap, argp, sizeof(cap)))
4523 goto out;
4524 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4525 break;
4526 }
5acc5c06
BS		 4527 case KVM_MEMORY_ENCRYPT_OP: {
4528 r = -ENOTTY;
4529 if (kvm_x86_ops->mem_enc_op)
4530 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4531 break;
4532 }
69eaedee
BS		 4533 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4534 struct kvm_enc_region region;
4535
4536 r = -EFAULT;
4537 if (copy_from_user(&region, argp, sizeof(region)))
4538 goto out;
4539
4540 r = -ENOTTY;
4541 if (kvm_x86_ops->mem_enc_reg_region)
4542 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4543 break;
4544 }
4545 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4546 struct kvm_enc_region region;
4547
4548 r = -EFAULT;
4549 if (copy_from_user(&region, argp, sizeof(region)))
4550 goto out;
4551
4552 r = -ENOTTY;
4553 if (kvm_x86_ops->mem_enc_unreg_region)
4554 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4555 break;
4556 }
faeb7833
RK		 4557 case KVM_HYPERV_EVENTFD: {
4558 struct kvm_hyperv_eventfd hvevfd;
4559
4560 r = -EFAULT;
4561 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4562 goto out;
4563 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4564 break;
4565 }
1fe779f8 4566 default:
ad6260da 4567 r = -ENOTTY;
1fe779f8
CO		 4568 }
4569out:
4570 return r;
4571}
4572
a16b043c 4573static void kvm_init_msr_list(void)
043405e1
CO		 4574{
4575 u32 dummy[2];
4576 unsigned i, j;
4577
62ef68bb 4578 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4579 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4580 continue;
93c4adc7
PB		 4581
4582 /*
4583 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4584 * to the guests in some cases.
93c4adc7
PB		 4585 */
4586 switch (msrs_to_save[i]) {
4587 case MSR_IA32_BNDCFGS:
4588 if (!kvm_x86_ops->mpx_supported())
4589 continue;
4590 break;
9dbe6cf9
PB		 4591 case MSR_TSC_AUX:
4592 if (!kvm_x86_ops->rdtscp_supported())
4593 continue;
4594 break;
93c4adc7
PB		 4595 default:
4596 break;
4597 }
4598
043405e1
CO		 4599 if (j < i)
4600 msrs_to_save[j] = msrs_to_save[i];
4601 j++;
4602 }
4603 num_msrs_to_save = j;
62ef68bb
PB		 4604
4605 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4606 switch (emulated_msrs[i]) {
6d396b55
PB		 4607 case MSR_IA32_SMBASE:
4608 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4609 continue;
4610 break;
62ef68bb
PB		 4611 default:
4612 break;
4613 }
4614
4615 if (j < i)
4616 emulated_msrs[j] = emulated_msrs[i];
4617 j++;
4618 }
4619 num_emulated_msrs = j;
801e459a
TL		 4620
4621 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4622 struct kvm_msr_entry msr;
4623
4624 msr.index = msr_based_features[i];
66421c1e 4625 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4626 continue;
4627
4628 if (j < i)
4629 msr_based_features[j] = msr_based_features[i];
4630 j++;
4631 }
4632 num_msr_based_features = j;
043405e1
CO		 4633}
4634
bda9020e
MT		 4635static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4636 const void *v)
bbd9b64e 4637{
70252a10
AK		 4638 int handled = 0;
4639 int n;
4640
4641 do {
4642 n = min(len, 8);
bce87cce 4643 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4644 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4645 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4646 break;
4647 handled += n;
4648 addr += n;
4649 len -= n;
4650 v += n;
4651 } while (len);
bbd9b64e 4652
70252a10 4653 return handled;
bbd9b64e
CO		 4654}
4655
bda9020e 4656static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4657{
70252a10
AK		 4658 int handled = 0;
4659 int n;
4660
4661 do {
4662 n = min(len, 8);
bce87cce 4663 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4664 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4665 addr, n, v))
4666 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4667 break;
e39d200f 4668 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4669 handled += n;
4670 addr += n;
4671 len -= n;
4672 v += n;
4673 } while (len);
bbd9b64e 4674
70252a10 4675 return handled;
bbd9b64e
CO		 4676}
4677
2dafc6c2
GN		 4678static void kvm_set_segment(struct kvm_vcpu *vcpu,
4679 struct kvm_segment *var, int seg)
4680{
4681 kvm_x86_ops->set_segment(vcpu, var, seg);
4682}
4683
4684void kvm_get_segment(struct kvm_vcpu *vcpu,
4685 struct kvm_segment *var, int seg)
4686{
4687 kvm_x86_ops->get_segment(vcpu, var, seg);
4688}
4689
54987b7a
PB		 4690gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4691 struct x86_exception *exception)
02f59dc9
JR		 4692{
4693 gpa_t t_gpa;
02f59dc9
JR		 4694
4695 BUG_ON(!mmu_is_nested(vcpu));
4696
4697 /* NPT walks are always user-walks */
4698 access |= PFERR_USER_MASK;
54987b7a 4699 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4700
4701 return t_gpa;
4702}
4703
ab9ae313
AK		 4704gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4705 struct x86_exception *exception)
1871c602
GN		 4706{
4707 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4708 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4709}
4710
ab9ae313
AK		 4711 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4712 struct x86_exception *exception)
1871c602
GN		 4713{
4714 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4715 access |= PFERR_FETCH_MASK;
ab9ae313 4716 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4717}
4718
ab9ae313
AK		 4719gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4720 struct x86_exception *exception)
1871c602
GN		 4721{
4722 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4723 access |= PFERR_WRITE_MASK;
ab9ae313 4724 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4725}
4726
4727/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4728gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4729 struct x86_exception *exception)
1871c602 4730{
ab9ae313 4731 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4732}
4733
4734static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4735 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4736 struct x86_exception *exception)
bbd9b64e
CO		 4737{
4738 void *data = val;
10589a46 4739 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4740
4741 while (bytes) {
14dfe855 4742 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4743 exception);
bbd9b64e 4744 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4745 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4746 int ret;
4747
bcc55cba 4748 if (gpa == UNMAPPED_GVA)
ab9ae313 4749 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4750 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4751 offset, toread);
10589a46 4752 if (ret < 0) {
c3cd7ffa 4753 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4754 goto out;
4755 }
bbd9b64e 4756
77c2002e
IE		 4757 bytes -= toread;
4758 data += toread;
4759 addr += toread;
bbd9b64e 4760 }
10589a46 4761out:
10589a46 4762 return r;
bbd9b64e 4763}
77c2002e 4764
1871c602 4765/* used for instruction fetching */
0f65dd70
AK		 4766static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4767 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4768 struct x86_exception *exception)
1871c602 4769{
0f65dd70 4770 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4771 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4772 unsigned offset;
4773 int ret;
0f65dd70 4774
44583cba
PB		 4775 /* Inline kvm_read_guest_virt_helper for speed. */
4776 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4777 exception);
4778 if (unlikely(gpa == UNMAPPED_GVA))
4779 return X86EMUL_PROPAGATE_FAULT;
4780
4781 offset = addr & (PAGE_SIZE-1);
4782 if (WARN_ON(offset + bytes > PAGE_SIZE))
4783 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4784 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4785 offset, bytes);
44583cba
PB		 4786 if (unlikely(ret < 0))
4787 return X86EMUL_IO_NEEDED;
4788
4789 return X86EMUL_CONTINUE;
1871c602
GN		 4790}
4791
064aea77 4792int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4793 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4794 struct x86_exception *exception)
1871c602 4795{
0f65dd70 4796 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4797 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4798
1871c602 4799 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4800 exception);
1871c602 4801}
064aea77 4802EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4803
0f65dd70
AK		 4804static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4805 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4806 struct x86_exception *exception)
1871c602 4807{
0f65dd70 4808 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4809 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4810}
4811
7a036a6f
RK		 4812static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4813 unsigned long addr, void *val, unsigned int bytes)
4814{
4815 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4816 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4817
4818 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4819}
4820
6a4d7550 4821int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4822 gva_t addr, void *val,
2dafc6c2 4823 unsigned int bytes,
bcc55cba 4824 struct x86_exception *exception)
77c2002e 4825{
0f65dd70 4826 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4827 void *data = val;
4828 int r = X86EMUL_CONTINUE;
4829
4830 while (bytes) {
14dfe855
JR		 4831 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4832 PFERR_WRITE_MASK,
ab9ae313 4833 exception);
77c2002e
IE		 4834 unsigned offset = addr & (PAGE_SIZE-1);
4835 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4836 int ret;
4837
bcc55cba 4838 if (gpa == UNMAPPED_GVA)
ab9ae313 4839 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4840 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4841 if (ret < 0) {
c3cd7ffa 4842 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4843 goto out;
4844 }
4845
4846 bytes -= towrite;
4847 data += towrite;
4848 addr += towrite;
4849 }
4850out:
4851 return r;
4852}
6a4d7550 4853EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4854
082d06ed
WL		 4855int handle_ud(struct kvm_vcpu *vcpu)
4856{
6c86eedc 4857 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 4858 enum emulation_result er;
6c86eedc
WL		 4859 char sig[5]; /* ud2; .ascii "kvm" */
4860 struct x86_exception e;
4861
4862 if (force_emulation_prefix &&
4863 kvm_read_guest_virt(&vcpu->arch.emulate_ctxt,
4864 kvm_get_linear_rip(vcpu), sig, sizeof(sig), &e) == 0 &&
4865 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
4866 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
4867 emul_type = 0;
4868 }
082d06ed 4869
6c86eedc 4870 er = emulate_instruction(vcpu, emul_type);
082d06ed
WL		 4871 if (er == EMULATE_USER_EXIT)
4872 return 0;
4873 if (er != EMULATE_DONE)
4874 kvm_queue_exception(vcpu, UD_VECTOR);
4875 return 1;
4876}
4877EXPORT_SYMBOL_GPL(handle_ud);
4878
0f89b207
TL		 4879static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4880 gpa_t gpa, bool write)
4881{
4882 /* For APIC access vmexit */
4883 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4884 return 1;
4885
4886 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4887 trace_vcpu_match_mmio(gva, gpa, write, true);
4888 return 1;
4889 }
4890
4891 return 0;
4892}
4893
af7cc7d1
XG		 4894static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4895 gpa_t *gpa, struct x86_exception *exception,
4896 bool write)
4897{
97d64b78
AK		 4898 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4899 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4900
be94f6b7
HH		 4901 /*
4902 * currently PKRU is only applied to ept enabled guest so
4903 * there is no pkey in EPT page table for L1 guest or EPT
4904 * shadow page table for L2 guest.
4905 */
97d64b78 4906 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4907 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4908 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4909 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4910 (gva & (PAGE_SIZE - 1));
4f022648 4911 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4912 return 1;
4913 }
4914
af7cc7d1
XG		 4915 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4916
4917 if (*gpa == UNMAPPED_GVA)
4918 return -1;
4919
0f89b207 4920 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4921}
4922
3200f405 4923int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4924 const void *val, int bytes)
bbd9b64e
CO		 4925{
4926 int ret;
4927
54bf36aa 4928 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4929 if (ret < 0)
bbd9b64e 4930 return 0;
0eb05bf2 4931 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4932 return 1;
4933}
4934
77d197b2
XG		 4935struct read_write_emulator_ops {
4936 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4937 int bytes);
4938 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4939 void *val, int bytes);
4940 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4941 int bytes, void *val);
4942 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4943 void *val, int bytes);
4944 bool write;
4945};
4946
4947static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4948{
4949 if (vcpu->mmio_read_completed) {
77d197b2 4950 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4951 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4952 vcpu->mmio_read_completed = 0;
4953 return 1;
4954 }
4955
4956 return 0;
4957}
4958
4959static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4960 void *val, int bytes)
4961{
54bf36aa 4962 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4963}
4964
4965static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4966 void *val, int bytes)
4967{
4968 return emulator_write_phys(vcpu, gpa, val, bytes);
4969}
4970
4971static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4972{
e39d200f 4973 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4974 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4975}
4976
4977static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4978 void *val, int bytes)
4979{
e39d200f 4980 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4981 return X86EMUL_IO_NEEDED;
4982}
4983
4984static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4985 void *val, int bytes)
4986{
f78146b0
AK		 4987 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4988
87da7e66 4989 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4990 return X86EMUL_CONTINUE;
4991}
4992
0fbe9b0b 4993static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4994 .read_write_prepare = read_prepare,
4995 .read_write_emulate = read_emulate,
4996 .read_write_mmio = vcpu_mmio_read,
4997 .read_write_exit_mmio = read_exit_mmio,
4998};
4999
0fbe9b0b 5000static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5001 .read_write_emulate = write_emulate,
5002 .read_write_mmio = write_mmio,
5003 .read_write_exit_mmio = write_exit_mmio,
5004 .write = true,
5005};
5006
22388a3c
XG		 5007static int emulator_read_write_onepage(unsigned long addr, void *val,
5008 unsigned int bytes,
5009 struct x86_exception *exception,
5010 struct kvm_vcpu *vcpu,
0fbe9b0b 5011 const struct read_write_emulator_ops *ops)
bbd9b64e 5012{
af7cc7d1
XG		 5013 gpa_t gpa;
5014 int handled, ret;
22388a3c 5015 bool write = ops->write;
f78146b0 5016 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5017 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5018
5019 /*
5020 * If the exit was due to a NPF we may already have a GPA.
5021 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5022 * Note, this cannot be used on string operations since string
5023 * operation using rep will only have the initial GPA from the NPF
5024 * occurred.
5025 */
5026 if (vcpu->arch.gpa_available &&
5027 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5028 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5029 gpa = vcpu->arch.gpa_val;
5030 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5031 } else {
5032 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5033 if (ret < 0)
5034 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5035 }
10589a46 5036
618232e2 5037 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5038 return X86EMUL_CONTINUE;
5039
bbd9b64e
CO		 5040 /*
5041 * Is this MMIO handled locally?
5042 */
22388a3c 5043 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5044 if (handled == bytes)
bbd9b64e 5045 return X86EMUL_CONTINUE;
bbd9b64e 5046
70252a10
AK		 5047 gpa += handled;
5048 bytes -= handled;
5049 val += handled;
5050
87da7e66
XG		 5051 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5052 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5053 frag->gpa = gpa;
5054 frag->data = val;
5055 frag->len = bytes;
f78146b0 5056 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5057}
5058
52eb5a6d
XL		 5059static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5060 unsigned long addr,
22388a3c
XG		 5061 void *val, unsigned int bytes,
5062 struct x86_exception *exception,
0fbe9b0b 5063 const struct read_write_emulator_ops *ops)
bbd9b64e 5064{
0f65dd70 5065 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5066 gpa_t gpa;
5067 int rc;
5068
5069 if (ops->read_write_prepare &&
5070 ops->read_write_prepare(vcpu, val, bytes))
5071 return X86EMUL_CONTINUE;
5072
5073 vcpu->mmio_nr_fragments = 0;
0f65dd70 5074
bbd9b64e
CO		 5075 /* Crossing a page boundary? */
5076 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5077 int now;
bbd9b64e
CO		 5078
5079 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5080 rc = emulator_read_write_onepage(addr, val, now, exception,
5081 vcpu, ops);
5082
bbd9b64e
CO		 5083 if (rc != X86EMUL_CONTINUE)
5084 return rc;
5085 addr += now;
bac15531
NA		 5086 if (ctxt->mode != X86EMUL_MODE_PROT64)
5087 addr = (u32)addr;
bbd9b64e
CO		 5088 val += now;
5089 bytes -= now;
5090 }
22388a3c 5091
f78146b0
AK		 5092 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5093 vcpu, ops);
5094 if (rc != X86EMUL_CONTINUE)
5095 return rc;
5096
5097 if (!vcpu->mmio_nr_fragments)
5098 return rc;
5099
5100 gpa = vcpu->mmio_fragments[0].gpa;
5101
5102 vcpu->mmio_needed = 1;
5103 vcpu->mmio_cur_fragment = 0;
5104
87da7e66 5105 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5106 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5107 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5108 vcpu->run->mmio.phys_addr = gpa;
5109
5110 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5111}
5112
5113static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5114 unsigned long addr,
5115 void *val,
5116 unsigned int bytes,
5117 struct x86_exception *exception)
5118{
5119 return emulator_read_write(ctxt, addr, val, bytes,
5120 exception, &read_emultor);
5121}
5122
52eb5a6d 5123static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5124 unsigned long addr,
5125 const void *val,
5126 unsigned int bytes,
5127 struct x86_exception *exception)
5128{
5129 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5130 exception, &write_emultor);
bbd9b64e 5131}
bbd9b64e 5132
daea3e73
AK		 5133#define CMPXCHG_TYPE(t, ptr, old, new) \
5134 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5135
5136#ifdef CONFIG_X86_64
5137# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5138#else
5139# define CMPXCHG64(ptr, old, new) \
9749a6c0 5140 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5141#endif
5142
0f65dd70
AK		 5143static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5144 unsigned long addr,
bbd9b64e
CO		 5145 const void *old,
5146 const void *new,
5147 unsigned int bytes,
0f65dd70 5148 struct x86_exception *exception)
bbd9b64e 5149{
0f65dd70 5150 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5151 gpa_t gpa;
5152 struct page *page;
5153 char *kaddr;
5154 bool exchanged;
2bacc55c 5155
daea3e73
AK		 5156 /* guests cmpxchg8b have to be emulated atomically */
5157 if (bytes > 8 || (bytes & (bytes - 1)))
5158 goto emul_write;
10589a46 5159
daea3e73 5160 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5161
daea3e73
AK		 5162 if (gpa == UNMAPPED_GVA ||
5163 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5164 goto emul_write;
2bacc55c 5165
daea3e73
AK		 5166 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5167 goto emul_write;
72dc67a6 5168
54bf36aa 5169 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5170 if (is_error_page(page))
c19b8bd6 5171 goto emul_write;
72dc67a6 5172
8fd75e12 5173 kaddr = kmap_atomic(page);
daea3e73
AK		 5174 kaddr += offset_in_page(gpa);
5175 switch (bytes) {
5176 case 1:
5177 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5178 break;
5179 case 2:
5180 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5181 break;
5182 case 4:
5183 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5184 break;
5185 case 8:
5186 exchanged = CMPXCHG64(kaddr, old, new);
5187 break;
5188 default:
5189 BUG();
2bacc55c 5190 }
8fd75e12 5191 kunmap_atomic(kaddr);
daea3e73
AK		 5192 kvm_release_page_dirty(page);
5193
5194 if (!exchanged)
5195 return X86EMUL_CMPXCHG_FAILED;
5196
54bf36aa 5197 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5198 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5199
5200 return X86EMUL_CONTINUE;
4a5f48f6 5201
3200f405 5202emul_write:
daea3e73 5203 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5204
0f65dd70 5205 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5206}
5207
cf8f70bf
GN		 5208static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5209{
cbfc6c91 5210 int r = 0, i;
cf8f70bf 5211
cbfc6c91
WL		 5212 for (i = 0; i < vcpu->arch.pio.count; i++) {
5213 if (vcpu->arch.pio.in)
5214 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5215 vcpu->arch.pio.size, pd);
5216 else
5217 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5218 vcpu->arch.pio.port, vcpu->arch.pio.size,
5219 pd);
5220 if (r)
5221 break;
5222 pd += vcpu->arch.pio.size;
5223 }
cf8f70bf
GN		 5224 return r;
5225}
5226
6f6fbe98
XG		 5227static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5228 unsigned short port, void *val,
5229 unsigned int count, bool in)
cf8f70bf 5230{
cf8f70bf 5231 vcpu->arch.pio.port = port;
6f6fbe98 5232 vcpu->arch.pio.in = in;
7972995b 5233 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5234 vcpu->arch.pio.size = size;
5235
5236 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5237 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5238 return 1;
5239 }
5240
5241 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5242 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5243 vcpu->run->io.size = size;
5244 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5245 vcpu->run->io.count = count;
5246 vcpu->run->io.port = port;
5247
5248 return 0;
5249}
5250
6f6fbe98
XG		 5251static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5252 int size, unsigned short port, void *val,
5253 unsigned int count)
cf8f70bf 5254{
ca1d4a9e 5255 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5256 int ret;
ca1d4a9e 5257
6f6fbe98
XG		 5258 if (vcpu->arch.pio.count)
5259 goto data_avail;
cf8f70bf 5260
cbfc6c91
WL		 5261 memset(vcpu->arch.pio_data, 0, size * count);
5262
6f6fbe98
XG		 5263 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5264 if (ret) {
5265data_avail:
5266 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5267 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5268 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5269 return 1;
5270 }
5271
cf8f70bf
GN		 5272 return 0;
5273}
5274
6f6fbe98
XG		 5275static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5276 int size, unsigned short port,
5277 const void *val, unsigned int count)
5278{
5279 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5280
5281 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5282 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5283 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5284}
5285
bbd9b64e
CO		 5286static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5287{
5288 return kvm_x86_ops->get_segment_base(vcpu, seg);
5289}
5290
3cb16fe7 5291static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5292{
3cb16fe7 5293 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5294}
5295
ae6a2375 5296static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5297{
5298 if (!need_emulate_wbinvd(vcpu))
5299 return X86EMUL_CONTINUE;
5300
5301 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5302 int cpu = get_cpu();
5303
5304 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5305 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5306 wbinvd_ipi, NULL, 1);
2eec7343 5307 put_cpu();
f5f48ee1 5308 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5309 } else
5310 wbinvd();
f5f48ee1
SY		 5311 return X86EMUL_CONTINUE;
5312}
5cb56059
JS		 5313
5314int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5315{
6affcbed
KH		 5316 kvm_emulate_wbinvd_noskip(vcpu);
5317 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5318}
f5f48ee1
SY		 5319EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5320
5cb56059
JS		 5321
5322
bcaf5cc5
AK		 5323static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5324{
5cb56059 5325 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5326}
5327
52eb5a6d
XL		 5328static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5329 unsigned long *dest)
bbd9b64e 5330{
16f8a6f9 5331 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5332}
5333
52eb5a6d
XL		 5334static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5335 unsigned long value)
bbd9b64e 5336{
338dbc97 5337
717746e3 5338 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5339}
5340
52a46617 5341static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5342{
52a46617 5343 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5344}
5345
717746e3 5346static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5347{
717746e3 5348 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5349 unsigned long value;
5350
5351 switch (cr) {
5352 case 0:
5353 value = kvm_read_cr0(vcpu);
5354 break;
5355 case 2:
5356 value = vcpu->arch.cr2;
5357 break;
5358 case 3:
9f8fe504 5359 value = kvm_read_cr3(vcpu);
52a46617
GN		 5360 break;
5361 case 4:
5362 value = kvm_read_cr4(vcpu);
5363 break;
5364 case 8:
5365 value = kvm_get_cr8(vcpu);
5366 break;
5367 default:
a737f256 5368 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5369 return 0;
5370 }
5371
5372 return value;
5373}
5374
717746e3 5375static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5376{
717746e3 5377 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5378 int res = 0;
5379
52a46617
GN		 5380 switch (cr) {
5381 case 0:
49a9b07e 5382 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5383 break;
5384 case 2:
5385 vcpu->arch.cr2 = val;
5386 break;
5387 case 3:
2390218b 5388 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5389 break;
5390 case 4:
a83b29c6 5391 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5392 break;
5393 case 8:
eea1cff9 5394 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5395 break;
5396 default:
a737f256 5397 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5398 res = -1;
52a46617 5399 }
0f12244f
GN		 5400
5401 return res;
52a46617
GN		 5402}
5403
717746e3 5404static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5405{
717746e3 5406 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5407}
5408
4bff1e86 5409static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5410{
4bff1e86 5411 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5412}
5413
4bff1e86 5414static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5415{
4bff1e86 5416 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5417}
5418
1ac9d0cf
AK		 5419static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5420{
5421 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5422}
5423
5424static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5425{
5426 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5427}
5428
4bff1e86
AK		 5429static unsigned long emulator_get_cached_segment_base(
5430 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5431{
4bff1e86 5432 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5433}
5434
1aa36616
AK		 5435static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5436 struct desc_struct *desc, u32 *base3,
5437 int seg)
2dafc6c2
GN		 5438{
5439 struct kvm_segment var;
5440
4bff1e86 5441 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5442 *selector = var.selector;
2dafc6c2 5443
378a8b09
GN		 5444 if (var.unusable) {
5445 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5446 if (base3)
5447 *base3 = 0;
2dafc6c2 5448 return false;
378a8b09 5449 }
2dafc6c2
GN		 5450
5451 if (var.g)
5452 var.limit >>= 12;
5453 set_desc_limit(desc, var.limit);
5454 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5455#ifdef CONFIG_X86_64
5456 if (base3)
5457 *base3 = var.base >> 32;
5458#endif
2dafc6c2
GN		 5459 desc->type = var.type;
5460 desc->s = var.s;
5461 desc->dpl = var.dpl;
5462 desc->p = var.present;
5463 desc->avl = var.avl;
5464 desc->l = var.l;
5465 desc->d = var.db;
5466 desc->g = var.g;
5467
5468 return true;
5469}
5470
1aa36616
AK		 5471static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5472 struct desc_struct *desc, u32 base3,
5473 int seg)
2dafc6c2 5474{
4bff1e86 5475 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5476 struct kvm_segment var;
5477
1aa36616 5478 var.selector = selector;
2dafc6c2 5479 var.base = get_desc_base(desc);
5601d05b
GN		 5480#ifdef CONFIG_X86_64
5481 var.base |= ((u64)base3) << 32;
5482#endif
2dafc6c2
GN		 5483 var.limit = get_desc_limit(desc);
5484 if (desc->g)
5485 var.limit = (var.limit << 12) | 0xfff;
5486 var.type = desc->type;
2dafc6c2
GN		 5487 var.dpl = desc->dpl;
5488 var.db = desc->d;
5489 var.s = desc->s;
5490 var.l = desc->l;
5491 var.g = desc->g;
5492 var.avl = desc->avl;
5493 var.present = desc->p;
5494 var.unusable = !var.present;
5495 var.padding = 0;
5496
5497 kvm_set_segment(vcpu, &var, seg);
5498 return;
5499}
5500
717746e3
AK		 5501static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5502 u32 msr_index, u64 *pdata)
5503{
609e36d3
PB		 5504 struct msr_data msr;
5505 int r;
5506
5507 msr.index = msr_index;
5508 msr.host_initiated = false;
5509 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5510 if (r)
5511 return r;
5512
5513 *pdata = msr.data;
5514 return 0;
717746e3
AK		 5515}
5516
5517static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5518 u32 msr_index, u64 data)
5519{
8fe8ab46
WA		 5520 struct msr_data msr;
5521
5522 msr.data = data;
5523 msr.index = msr_index;
5524 msr.host_initiated = false;
5525 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5526}
5527
64d60670
PB		 5528static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5529{
5530 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5531
5532 return vcpu->arch.smbase;
5533}
5534
5535static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5536{
5537 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5538
5539 vcpu->arch.smbase = smbase;
5540}
5541
67f4d428
NA		 5542static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5543 u32 pmc)
5544{
c6702c9d 5545 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5546}
5547
222d21aa
AK		 5548static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5549 u32 pmc, u64 *pdata)
5550{
c6702c9d 5551 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5552}
5553
6c3287f7
AK		 5554static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5555{
5556 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5557}
5558
2953538e 5559static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5560 struct x86_instruction_info *info,
c4f035c6
AK		 5561 enum x86_intercept_stage stage)
5562{
2953538e 5563 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5564}
5565
e911eb3b
YZ		 5566static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5567 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5568{
e911eb3b 5569 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5570}
5571
dd856efa
AK		 5572static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5573{
5574 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5575}
5576
5577static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5578{
5579 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5580}
5581
801806d9
NA		 5582static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5583{
5584 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5585}
5586
6ed071f0
LP		 5587static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5588{
5589 return emul_to_vcpu(ctxt)->arch.hflags;
5590}
5591
5592static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5593{
5594 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5595}
5596
0234bf88
LP		 5597static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5598{
5599 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5600}
5601
0225fb50 5602static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5603 .read_gpr = emulator_read_gpr,
5604 .write_gpr = emulator_write_gpr,
1871c602 5605 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5606 .write_std = kvm_write_guest_virt_system,
7a036a6f 5607 .read_phys = kvm_read_guest_phys_system,
1871c602 5608 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5609 .read_emulated = emulator_read_emulated,
5610 .write_emulated = emulator_write_emulated,
5611 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5612 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5613 .pio_in_emulated = emulator_pio_in_emulated,
5614 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5615 .get_segment = emulator_get_segment,
5616 .set_segment = emulator_set_segment,
5951c442 5617 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5618 .get_gdt = emulator_get_gdt,
160ce1f1 5619 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5620 .set_gdt = emulator_set_gdt,
5621 .set_idt = emulator_set_idt,
52a46617
GN		 5622 .get_cr = emulator_get_cr,
5623 .set_cr = emulator_set_cr,
9c537244 5624 .cpl = emulator_get_cpl,
35aa5375
GN		 5625 .get_dr = emulator_get_dr,
5626 .set_dr = emulator_set_dr,
64d60670
PB		 5627 .get_smbase = emulator_get_smbase,
5628 .set_smbase = emulator_set_smbase,
717746e3
AK		 5629 .set_msr = emulator_set_msr,
5630 .get_msr = emulator_get_msr,
67f4d428 5631 .check_pmc = emulator_check_pmc,
222d21aa 5632 .read_pmc = emulator_read_pmc,
6c3287f7 5633 .halt = emulator_halt,
bcaf5cc5 5634 .wbinvd = emulator_wbinvd,
d6aa1000 5635 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5636 .intercept = emulator_intercept,
bdb42f5a 5637 .get_cpuid = emulator_get_cpuid,
801806d9 5638 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5639 .get_hflags = emulator_get_hflags,
5640 .set_hflags = emulator_set_hflags,
0234bf88 5641 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5642};
5643
95cb2295
GN		 5644static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5645{
37ccdcbe 5646 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5647 /*
5648 * an sti; sti; sequence only disable interrupts for the first
5649 * instruction. So, if the last instruction, be it emulated or
5650 * not, left the system with the INT_STI flag enabled, it
5651 * means that the last instruction is an sti. We should not
5652 * leave the flag on in this case. The same goes for mov ss
5653 */
37ccdcbe
PB		 5654 if (int_shadow & mask)
5655 mask = 0;
6addfc42 5656 if (unlikely(int_shadow || mask)) {
95cb2295 5657 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5658 if (!mask)
5659 kvm_make_request(KVM_REQ_EVENT, vcpu);
5660 }
95cb2295
GN		 5661}
5662
ef54bcfe 5663static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5664{
5665 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5666 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5667 return kvm_propagate_fault(vcpu, &ctxt->exception);
5668
5669 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5670 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5671 ctxt->exception.error_code);
54b8486f 5672 else
da9cb575 5673 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5674 return false;
54b8486f
GN		 5675}
5676
8ec4722d
MG		 5677static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5678{
adf52235 5679 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5680 int cs_db, cs_l;
5681
8ec4722d
MG		 5682 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5683
adf52235 5684 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5685 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5686
adf52235
TY		 5687 ctxt->eip = kvm_rip_read(vcpu);
5688 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5689 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5690 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5691 cs_db ? X86EMUL_MODE_PROT32 :
5692 X86EMUL_MODE_PROT16;
a584539b 5693 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5694 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5695 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5696
dd856efa 5697 init_decode_cache(ctxt);
7ae441ea 5698 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5699}
5700
71f9833b 5701int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5702{
9d74191a 5703 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5704 int ret;
5705
5706 init_emulate_ctxt(vcpu);
5707
9dac77fa
AK		 5708 ctxt->op_bytes = 2;
5709 ctxt->ad_bytes = 2;
5710 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5711 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5712
5713 if (ret != X86EMUL_CONTINUE)
5714 return EMULATE_FAIL;
5715
9dac77fa 5716 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5717 kvm_rip_write(vcpu, ctxt->eip);
5718 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5719
63995653
MG		 5720 return EMULATE_DONE;
5721}
5722EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5723
e2366171 5724static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5725{
fc3a9157
JR		 5726 int r = EMULATE_DONE;
5727
6d77dbfc
GN		 5728 ++vcpu->stat.insn_emulation_fail;
5729 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5730
5731 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5732 return EMULATE_FAIL;
5733
a2b9e6c1 5734 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5735 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5736 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5737 vcpu->run->internal.ndata = 0;
1f4dcb3b 5738 r = EMULATE_USER_EXIT;
fc3a9157 5739 }
e2366171 5740
6d77dbfc 5741 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5742
5743 return r;
6d77dbfc
GN		 5744}
5745
93c05d3e 5746static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5747 bool write_fault_to_shadow_pgtable,
5748 int emulation_type)
a6f177ef 5749{
95b3cf69 5750 gpa_t gpa = cr2;
ba049e93 5751 kvm_pfn_t pfn;
a6f177ef 5752
991eebf9
GN		 5753 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5754 return false;
5755
95b3cf69
XG		 5756 if (!vcpu->arch.mmu.direct_map) {
5757 /*
5758 * Write permission should be allowed since only
5759 * write access need to be emulated.
5760 */
5761 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5762
95b3cf69
XG		 5763 /*
5764 * If the mapping is invalid in guest, let cpu retry
5765 * it to generate fault.
5766 */
5767 if (gpa == UNMAPPED_GVA)
5768 return true;
5769 }
a6f177ef 5770
8e3d9d06
XG		 5771 /*
5772 * Do not retry the unhandleable instruction if it faults on the
5773 * readonly host memory, otherwise it will goto a infinite loop:
5774 * retry instruction -> write #PF -> emulation fail -> retry
5775 * instruction -> ...
5776 */
5777 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5778
5779 /*
5780 * If the instruction failed on the error pfn, it can not be fixed,
5781 * report the error to userspace.
5782 */
5783 if (is_error_noslot_pfn(pfn))
5784 return false;
5785
5786 kvm_release_pfn_clean(pfn);
5787
5788 /* The instructions are well-emulated on direct mmu. */
5789 if (vcpu->arch.mmu.direct_map) {
5790 unsigned int indirect_shadow_pages;
5791
5792 spin_lock(&vcpu->kvm->mmu_lock);
5793 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5794 spin_unlock(&vcpu->kvm->mmu_lock);
5795
5796 if (indirect_shadow_pages)
5797 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5798
a6f177ef 5799 return true;
8e3d9d06 5800 }
a6f177ef 5801
95b3cf69
XG		 5802 /*
5803 * if emulation was due to access to shadowed page table
5804 * and it failed try to unshadow page and re-enter the
5805 * guest to let CPU execute the instruction.
5806 */
5807 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5808
5809 /*
5810 * If the access faults on its page table, it can not
5811 * be fixed by unprotecting shadow page and it should
5812 * be reported to userspace.
5813 */
5814 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5815}
5816
1cb3f3ae
XG		 5817static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5818 unsigned long cr2, int emulation_type)
5819{
5820 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5821 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5822
5823 last_retry_eip = vcpu->arch.last_retry_eip;
5824 last_retry_addr = vcpu->arch.last_retry_addr;
5825
5826 /*
5827 * If the emulation is caused by #PF and it is non-page_table
5828 * writing instruction, it means the VM-EXIT is caused by shadow
5829 * page protected, we can zap the shadow page and retry this
5830 * instruction directly.
5831 *
5832 * Note: if the guest uses a non-page-table modifying instruction
5833 * on the PDE that points to the instruction, then we will unmap
5834 * the instruction and go to an infinite loop. So, we cache the
5835 * last retried eip and the last fault address, if we meet the eip
5836 * and the address again, we can break out of the potential infinite
5837 * loop.
5838 */
5839 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5840
5841 if (!(emulation_type & EMULTYPE_RETRY))
5842 return false;
5843
5844 if (x86_page_table_writing_insn(ctxt))
5845 return false;
5846
5847 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5848 return false;
5849
5850 vcpu->arch.last_retry_eip = ctxt->eip;
5851 vcpu->arch.last_retry_addr = cr2;
5852
5853 if (!vcpu->arch.mmu.direct_map)
5854 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5855
22368028 5856 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5857
5858 return true;
5859}
5860
716d51ab
GN		 5861static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5862static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5863
64d60670 5864static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5865{
64d60670 5866 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5867 /* This is a good place to trace that we are exiting SMM. */
5868 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5869
c43203ca
PB		 5870 /* Process a latched INIT or SMI, if any. */
5871 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5872 }
699023e2
PB		 5873
5874 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5875}
5876
5877static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5878{
5879 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5880
a584539b 5881 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5882
5883 if (changed & HF_SMM_MASK)
5884 kvm_smm_changed(vcpu);
a584539b
PB		 5885}
5886
4a1e10d5
PB		 5887static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5888 unsigned long *db)
5889{
5890 u32 dr6 = 0;
5891 int i;
5892 u32 enable, rwlen;
5893
5894 enable = dr7;
5895 rwlen = dr7 >> 16;
5896 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5897 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5898 dr6 |= (1 << i);
5899 return dr6;
5900}
5901
c8401dda 5902static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5903{
5904 struct kvm_run *kvm_run = vcpu->run;
5905
c8401dda
PB		 5906 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5907 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5908 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5909 kvm_run->debug.arch.exception = DB_VECTOR;
5910 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5911 *r = EMULATE_USER_EXIT;
5912 } else {
5913 /*
5914 * "Certain debug exceptions may clear bit 0-3. The
5915 * remaining contents of the DR6 register are never
5916 * cleared by the processor".
5917 */
5918 vcpu->arch.dr6 &= ~15;
5919 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5920 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5921 }
5922}
5923
6affcbed
KH		 5924int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5925{
5926 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5927 int r = EMULATE_DONE;
5928
5929 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5930
5931 /*
5932 * rflags is the old, "raw" value of the flags. The new value has
5933 * not been saved yet.
5934 *
5935 * This is correct even for TF set by the guest, because "the
5936 * processor will not generate this exception after the instruction
5937 * that sets the TF flag".
5938 */
5939 if (unlikely(rflags & X86_EFLAGS_TF))
5940 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5941 return r == EMULATE_DONE;
5942}
5943EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5944
4a1e10d5
PB		 5945static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5946{
4a1e10d5
PB		 5947 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5948 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5949 struct kvm_run *kvm_run = vcpu->run;
5950 unsigned long eip = kvm_get_linear_rip(vcpu);
5951 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5952 vcpu->arch.guest_debug_dr7,
5953 vcpu->arch.eff_db);
5954
5955 if (dr6 != 0) {
6f43ed01 5956 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5957 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5958 kvm_run->debug.arch.exception = DB_VECTOR;
5959 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5960 *r = EMULATE_USER_EXIT;
5961 return true;
5962 }
5963 }
5964
4161a569
NA		 5965 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5966 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5967 unsigned long eip = kvm_get_linear_rip(vcpu);
5968 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5969 vcpu->arch.dr7,
5970 vcpu->arch.db);
5971
5972 if (dr6 != 0) {
5973 vcpu->arch.dr6 &= ~15;
6f43ed01 5974 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5975 kvm_queue_exception(vcpu, DB_VECTOR);
5976 *r = EMULATE_DONE;
5977 return true;
5978 }
5979 }
5980
5981 return false;
5982}
5983
04789b66
LA		 5984static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
5985{
2d7921c4
AM		 5986 switch (ctxt->opcode_len) {
5987 case 1:
5988 switch (ctxt->b) {
5989 case 0xe4: /* IN */
5990 case 0xe5:
5991 case 0xec:
5992 case 0xed:
5993 case 0xe6: /* OUT */
5994 case 0xe7:
5995 case 0xee:
5996 case 0xef:
5997 case 0x6c: /* INS */
5998 case 0x6d:
5999 case 0x6e: /* OUTS */
6000 case 0x6f:
6001 return true;
6002 }
6003 break;
6004 case 2:
6005 switch (ctxt->b) {
6006 case 0x33: /* RDPMC */
6007 return true;
6008 }
6009 break;
04789b66
LA		 6010 }
6011
6012 return false;
6013}
6014
51d8b661
AP		 6015int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6016 unsigned long cr2,
dc25e89e
AP		 6017 int emulation_type,
6018 void *insn,
6019 int insn_len)
bbd9b64e 6020{
95cb2295 6021 int r;
9d74191a 6022 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6023 bool writeback = true;
93c05d3e 6024 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6025
93c05d3e
XG		 6026 /*
6027 * Clear write_fault_to_shadow_pgtable here to ensure it is
6028 * never reused.
6029 */
6030 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6031 kvm_clear_exception_queue(vcpu);
8d7d8102 6032
571008da 6033 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6034 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6035
6036 /*
6037 * We will reenter on the same instruction since
6038 * we do not set complete_userspace_io. This does not
6039 * handle watchpoints yet, those would be handled in
6040 * the emulate_ops.
6041 */
d391f120
VK		 6042 if (!(emulation_type & EMULTYPE_SKIP) &&
6043 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6044 return r;
6045
9d74191a
TY		 6046 ctxt->interruptibility = 0;
6047 ctxt->have_exception = false;
e0ad0b47 6048 ctxt->exception.vector = -1;
9d74191a 6049 ctxt->perm_ok = false;
bbd9b64e 6050
b51e974f 6051 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6052
9d74191a 6053 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6054
e46479f8 6055 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6056 ++vcpu->stat.insn_emulation;
1d2887e2 6057 if (r != EMULATION_OK) {
4005996e
AK		 6058 if (emulation_type & EMULTYPE_TRAP_UD)
6059 return EMULATE_FAIL;
991eebf9
GN		 6060 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6061 emulation_type))
bbd9b64e 6062 return EMULATE_DONE;
6ea6e843
PB		 6063 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6064 return EMULATE_DONE;
6d77dbfc
GN		 6065 if (emulation_type & EMULTYPE_SKIP)
6066 return EMULATE_FAIL;
e2366171 6067 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6068 }
6069 }
6070
04789b66
LA		 6071 if ((emulation_type & EMULTYPE_VMWARE) &&
6072 !is_vmware_backdoor_opcode(ctxt))
6073 return EMULATE_FAIL;
6074
ba8afb6b 6075 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6076 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6077 if (ctxt->eflags & X86_EFLAGS_RF)
6078 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6079 return EMULATE_DONE;
6080 }
6081
1cb3f3ae
XG		 6082 if (retry_instruction(ctxt, cr2, emulation_type))
6083 return EMULATE_DONE;
6084
7ae441ea 6085 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6086 changes registers values during IO operation */
7ae441ea
GN		 6087 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6088 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6089 emulator_invalidate_register_cache(ctxt);
7ae441ea 6090 }
4d2179e1 6091
5cd21917 6092restart:
0f89b207
TL		 6093 /* Save the faulting GPA (cr2) in the address field */
6094 ctxt->exception.address = cr2;
6095
9d74191a 6096 r = x86_emulate_insn(ctxt);
bbd9b64e 6097
775fde86
JR		 6098 if (r == EMULATION_INTERCEPTED)
6099 return EMULATE_DONE;
6100
d2ddd1c4 6101 if (r == EMULATION_FAILED) {
991eebf9
GN		 6102 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6103 emulation_type))
c3cd7ffa
GN		 6104 return EMULATE_DONE;
6105
e2366171 6106 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6107 }
6108
9d74191a 6109 if (ctxt->have_exception) {
d2ddd1c4 6110 r = EMULATE_DONE;
ef54bcfe
PB		 6111 if (inject_emulated_exception(vcpu))
6112 return r;
d2ddd1c4 6113 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6114 if (!vcpu->arch.pio.in) {
6115 /* FIXME: return into emulator if single-stepping. */
3457e419 6116 vcpu->arch.pio.count = 0;
0912c977 6117 } else {
7ae441ea 6118 writeback = false;
716d51ab
GN		 6119 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6120 }
ac0a48c3 6121 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6122 } else if (vcpu->mmio_needed) {
6123 if (!vcpu->mmio_is_write)
6124 writeback = false;
ac0a48c3 6125 r = EMULATE_USER_EXIT;
716d51ab 6126 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6127 } else if (r == EMULATION_RESTART)
5cd21917 6128 goto restart;
d2ddd1c4
GN		 6129 else
6130 r = EMULATE_DONE;
f850e2e6 6131
7ae441ea 6132 if (writeback) {
6addfc42 6133 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6134 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6135 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6136 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6137 if (r == EMULATE_DONE &&
6138 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6139 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6140 if (!ctxt->have_exception ||
6141 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6142 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6143
6144 /*
6145 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6146 * do nothing, and it will be requested again as soon as
6147 * the shadow expires. But we still need to check here,
6148 * because POPF has no interrupt shadow.
6149 */
6150 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6151 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6152 } else
6153 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6154
6155 return r;
de7d789a 6156}
51d8b661 6157EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6158
dca7f128
SC		 6159static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6160 unsigned short port)
de7d789a 6161{
cf8f70bf 6162 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6163 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6164 size, port, &val, 1);
cf8f70bf 6165 /* do not return to emulator after return from userspace */
7972995b 6166 vcpu->arch.pio.count = 0;
de7d789a
CO		 6167 return ret;
6168}
de7d789a 6169
8370c3d0
TL		 6170static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6171{
6172 unsigned long val;
6173
6174 /* We should only ever be called with arch.pio.count equal to 1 */
6175 BUG_ON(vcpu->arch.pio.count != 1);
6176
6177 /* For size less than 4 we merge, else we zero extend */
6178 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6179 : 0;
6180
6181 /*
6182 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6183 * the copy and tracing
6184 */
6185 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6186 vcpu->arch.pio.port, &val, 1);
6187 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6188
6189 return 1;
6190}
6191
dca7f128
SC		 6192static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6193 unsigned short port)
8370c3d0
TL		 6194{
6195 unsigned long val;
6196 int ret;
6197
6198 /* For size less than 4 we merge, else we zero extend */
6199 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6200
6201 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6202 &val, 1);
6203 if (ret) {
6204 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6205 return ret;
6206 }
6207
6208 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6209
6210 return 0;
6211}
dca7f128
SC		 6212
6213int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6214{
6215 int ret = kvm_skip_emulated_instruction(vcpu);
6216
6217 /*
6218 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6219 * KVM_EXIT_DEBUG here.
6220 */
6221 if (in)
6222 return kvm_fast_pio_in(vcpu, size, port) && ret;
6223 else
6224 return kvm_fast_pio_out(vcpu, size, port) && ret;
6225}
6226EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6227
251a5fd6 6228static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6229{
0a3aee0d 6230 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6231 return 0;
8cfdc000
ZA		 6232}
6233
6234static void tsc_khz_changed(void *data)
c8076604 6235{
8cfdc000
ZA		 6236 struct cpufreq_freqs *freq = data;
6237 unsigned long khz = 0;
6238
6239 if (data)
6240 khz = freq->new;
6241 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6242 khz = cpufreq_quick_get(raw_smp_processor_id());
6243 if (!khz)
6244 khz = tsc_khz;
0a3aee0d 6245 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6246}
6247
5fa4ec9c 6248#ifdef CONFIG_X86_64
0092e434
VK		 6249static void kvm_hyperv_tsc_notifier(void)
6250{
0092e434
VK		 6251 struct kvm *kvm;
6252 struct kvm_vcpu *vcpu;
6253 int cpu;
6254
6255 spin_lock(&kvm_lock);
6256 list_for_each_entry(kvm, &vm_list, vm_list)
6257 kvm_make_mclock_inprogress_request(kvm);
6258
6259 hyperv_stop_tsc_emulation();
6260
6261 /* TSC frequency always matches when on Hyper-V */
6262 for_each_present_cpu(cpu)
6263 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6264 kvm_max_guest_tsc_khz = tsc_khz;
6265
6266 list_for_each_entry(kvm, &vm_list, vm_list) {
6267 struct kvm_arch *ka = &kvm->arch;
6268
6269 spin_lock(&ka->pvclock_gtod_sync_lock);
6270
6271 pvclock_update_vm_gtod_copy(kvm);
6272
6273 kvm_for_each_vcpu(cpu, vcpu, kvm)
6274 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6275
6276 kvm_for_each_vcpu(cpu, vcpu, kvm)
6277 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6278
6279 spin_unlock(&ka->pvclock_gtod_sync_lock);
6280 }
6281 spin_unlock(&kvm_lock);
0092e434 6282}
5fa4ec9c 6283#endif
0092e434 6284
c8076604
GH		 6285static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6286 void *data)
6287{
6288 struct cpufreq_freqs *freq = data;
6289 struct kvm *kvm;
6290 struct kvm_vcpu *vcpu;
6291 int i, send_ipi = 0;
6292
8cfdc000
ZA		 6293 /*
6294 * We allow guests to temporarily run on slowing clocks,
6295 * provided we notify them after, or to run on accelerating
6296 * clocks, provided we notify them before. Thus time never
6297 * goes backwards.
6298 *
6299 * However, we have a problem. We can't atomically update
6300 * the frequency of a given CPU from this function; it is
6301 * merely a notifier, which can be called from any CPU.
6302 * Changing the TSC frequency at arbitrary points in time
6303 * requires a recomputation of local variables related to
6304 * the TSC for each VCPU. We must flag these local variables
6305 * to be updated and be sure the update takes place with the
6306 * new frequency before any guests proceed.
6307 *
6308 * Unfortunately, the combination of hotplug CPU and frequency
6309 * change creates an intractable locking scenario; the order
6310 * of when these callouts happen is undefined with respect to
6311 * CPU hotplug, and they can race with each other. As such,
6312 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6313 * undefined; you can actually have a CPU frequency change take
6314 * place in between the computation of X and the setting of the
6315 * variable. To protect against this problem, all updates of
6316 * the per_cpu tsc_khz variable are done in an interrupt
6317 * protected IPI, and all callers wishing to update the value
6318 * must wait for a synchronous IPI to complete (which is trivial
6319 * if the caller is on the CPU already). This establishes the
6320 * necessary total order on variable updates.
6321 *
6322 * Note that because a guest time update may take place
6323 * anytime after the setting of the VCPU's request bit, the
6324 * correct TSC value must be set before the request. However,
6325 * to ensure the update actually makes it to any guest which
6326 * starts running in hardware virtualization between the set
6327 * and the acquisition of the spinlock, we must also ping the
6328 * CPU after setting the request bit.
6329 *
6330 */
6331
c8076604
GH		 6332 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6333 return 0;
6334 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6335 return 0;
8cfdc000
ZA		 6336
6337 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6338
2f303b74 6339 spin_lock(&kvm_lock);
c8076604 6340 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6341 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6342 if (vcpu->cpu != freq->cpu)
6343 continue;
c285545f 6344 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6345 if (vcpu->cpu != smp_processor_id())
8cfdc000 6346 send_ipi = 1;
c8076604
GH		 6347 }
6348 }
2f303b74 6349 spin_unlock(&kvm_lock);
c8076604
GH		 6350
6351 if (freq->old < freq->new && send_ipi) {
6352 /*
6353 * We upscale the frequency. Must make the guest
6354 * doesn't see old kvmclock values while running with
6355 * the new frequency, otherwise we risk the guest sees
6356 * time go backwards.
6357 *
6358 * In case we update the frequency for another cpu
6359 * (which might be in guest context) send an interrupt
6360 * to kick the cpu out of guest context. Next time
6361 * guest context is entered kvmclock will be updated,
6362 * so the guest will not see stale values.
6363 */
8cfdc000 6364 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6365 }
6366 return 0;
6367}
6368
6369static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6370 .notifier_call = kvmclock_cpufreq_notifier
6371};
6372
251a5fd6 6373static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6374{
251a5fd6
SAS		 6375 tsc_khz_changed(NULL);
6376 return 0;
8cfdc000
ZA		 6377}
6378
b820cc0c
ZA		 6379static void kvm_timer_init(void)
6380{
c285545f 6381 max_tsc_khz = tsc_khz;
460dd42e 6382
b820cc0c 6383 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6384#ifdef CONFIG_CPU_FREQ
6385 struct cpufreq_policy policy;
758f588d
BP		 6386 int cpu;
6387
c285545f 6388 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6389 cpu = get_cpu();
6390 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6391 if (policy.cpuinfo.max_freq)
6392 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6393 put_cpu();
c285545f 6394#endif
b820cc0c
ZA		 6395 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6396 CPUFREQ_TRANSITION_NOTIFIER);
6397 }
c285545f 6398 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6399
73c1b41e 6400 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6401 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6402}
6403
dd60d217
AK		 6404DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6405EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6406
f5132b01 6407int kvm_is_in_guest(void)
ff9d07a0 6408{
086c9855 6409 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6410}
6411
6412static int kvm_is_user_mode(void)
6413{
6414 int user_mode = 3;
dcf46b94 6415
086c9855
AS		 6416 if (__this_cpu_read(current_vcpu))
6417 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6418
ff9d07a0
ZY		 6419 return user_mode != 0;
6420}
6421
6422static unsigned long kvm_get_guest_ip(void)
6423{
6424 unsigned long ip = 0;
dcf46b94 6425
086c9855
AS		 6426 if (__this_cpu_read(current_vcpu))
6427 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6428
ff9d07a0
ZY		 6429 return ip;
6430}
6431
6432static struct perf_guest_info_callbacks kvm_guest_cbs = {
6433 .is_in_guest = kvm_is_in_guest,
6434 .is_user_mode = kvm_is_user_mode,
6435 .get_guest_ip = kvm_get_guest_ip,
6436};
6437
ce88decf
XG		 6438static void kvm_set_mmio_spte_mask(void)
6439{
6440 u64 mask;
6441 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6442
6443 /*
6444 * Set the reserved bits and the present bit of an paging-structure
6445 * entry to generate page fault with PFER.RSV = 1.
6446 */
885032b9 6447 /* Mask the reserved physical address bits. */
d1431483 6448 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6449
885032b9 6450 /* Set the present bit. */
ce88decf
XG		 6451 mask |= 1ull;
6452
6453#ifdef CONFIG_X86_64
6454 /*
6455 * If reserved bit is not supported, clear the present bit to disable
6456 * mmio page fault.
6457 */
6458 if (maxphyaddr == 52)
6459 mask &= ~1ull;
6460#endif
6461
dcdca5fe 6462 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6463}
6464
16e8d74d
MT		 6465#ifdef CONFIG_X86_64
6466static void pvclock_gtod_update_fn(struct work_struct *work)
6467{
d828199e
MT		 6468 struct kvm *kvm;
6469
6470 struct kvm_vcpu *vcpu;
6471 int i;
6472
2f303b74 6473 spin_lock(&kvm_lock);
d828199e
MT		 6474 list_for_each_entry(kvm, &vm_list, vm_list)
6475 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6476 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6477 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6478 spin_unlock(&kvm_lock);
16e8d74d
MT		 6479}
6480
6481static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6482
6483/*
6484 * Notification about pvclock gtod data update.
6485 */
6486static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6487 void *priv)
6488{
6489 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6490 struct timekeeper *tk = priv;
6491
6492 update_pvclock_gtod(tk);
6493
6494 /* disable master clock if host does not trust, or does not
b0c39dc6 6495 * use, TSC based clocksource.
16e8d74d 6496 */
b0c39dc6 6497 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6498 atomic_read(&kvm_guest_has_master_clock) != 0)
6499 queue_work(system_long_wq, &pvclock_gtod_work);
6500
6501 return 0;
6502}
6503
6504static struct notifier_block pvclock_gtod_notifier = {
6505 .notifier_call = pvclock_gtod_notify,
6506};
6507#endif
6508
f8c16bba 6509int kvm_arch_init(void *opaque)
043405e1 6510{
b820cc0c 6511 int r;
6b61edf7 6512 struct kvm_x86_ops *ops = opaque;
f8c16bba 6513
f8c16bba
ZX		 6514 if (kvm_x86_ops) {
6515 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6516 r = -EEXIST;
6517 goto out;
f8c16bba
ZX		 6518 }
6519
6520 if (!ops->cpu_has_kvm_support()) {
6521 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6522 r = -EOPNOTSUPP;
6523 goto out;
f8c16bba
ZX		 6524 }
6525 if (ops->disabled_by_bios()) {
6526 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6527 r = -EOPNOTSUPP;
6528 goto out;
f8c16bba
ZX		 6529 }
6530
013f6a5d
MT		 6531 r = -ENOMEM;
6532 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6533 if (!shared_msrs) {
6534 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6535 goto out;
6536 }
6537
97db56ce
AK		 6538 r = kvm_mmu_module_init();
6539 if (r)
013f6a5d 6540 goto out_free_percpu;
97db56ce 6541
ce88decf 6542 kvm_set_mmio_spte_mask();
97db56ce 6543
f8c16bba 6544 kvm_x86_ops = ops;
920c8377 6545
7b52345e 6546 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6547 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6548 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6549 kvm_timer_init();
c8076604 6550
ff9d07a0
ZY		 6551 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6552
d366bf7e 6553 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6554 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6555
c5cc421b 6556 kvm_lapic_init();
16e8d74d
MT		 6557#ifdef CONFIG_X86_64
6558 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6559
5fa4ec9c 6560 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6561 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6562#endif
6563
f8c16bba 6564 return 0;
56c6d28a 6565
013f6a5d
MT		 6566out_free_percpu:
6567 free_percpu(shared_msrs);
56c6d28a 6568out:
56c6d28a 6569 return r;
043405e1 6570}
8776e519 6571
f8c16bba
ZX		 6572void kvm_arch_exit(void)
6573{
0092e434 6574#ifdef CONFIG_X86_64
5fa4ec9c 6575 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6576 clear_hv_tscchange_cb();
6577#endif
cef84c30 6578 kvm_lapic_exit();
ff9d07a0
ZY		 6579 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6580
888d256e
JK		 6581 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6582 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6583 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6584 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6585#ifdef CONFIG_X86_64
6586 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6587#endif
f8c16bba 6588 kvm_x86_ops = NULL;
56c6d28a 6589 kvm_mmu_module_exit();
013f6a5d 6590 free_percpu(shared_msrs);
56c6d28a 6591}
f8c16bba 6592
5cb56059 6593int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6594{
6595 ++vcpu->stat.halt_exits;
35754c98 6596 if (lapic_in_kernel(vcpu)) {
a4535290 6597 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6598 return 1;
6599 } else {
6600 vcpu->run->exit_reason = KVM_EXIT_HLT;
6601 return 0;
6602 }
6603}
5cb56059
JS		 6604EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6605
6606int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6607{
6affcbed
KH		 6608 int ret = kvm_skip_emulated_instruction(vcpu);
6609 /*
6610 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6611 * KVM_EXIT_DEBUG here.
6612 */
6613 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6614}
8776e519
HB		 6615EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6616
8ef81a9a 6617#ifdef CONFIG_X86_64
55dd00a7
MT		 6618static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6619 unsigned long clock_type)
6620{
6621 struct kvm_clock_pairing clock_pairing;
6622 struct timespec ts;
80fbd89c 6623 u64 cycle;
55dd00a7
MT		 6624 int ret;
6625
6626 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6627 return -KVM_EOPNOTSUPP;
6628
6629 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6630 return -KVM_EOPNOTSUPP;
6631
6632 clock_pairing.sec = ts.tv_sec;
6633 clock_pairing.nsec = ts.tv_nsec;
6634 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6635 clock_pairing.flags = 0;
6636
6637 ret = 0;
6638 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6639 sizeof(struct kvm_clock_pairing)))
6640 ret = -KVM_EFAULT;
6641
6642 return ret;
6643}
8ef81a9a 6644#endif
55dd00a7 6645
6aef266c
SV		 6646/*
6647 * kvm_pv_kick_cpu_op: Kick a vcpu.
6648 *
6649 * @apicid - apicid of vcpu to be kicked.
6650 */
6651static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6652{
24d2166b 6653 struct kvm_lapic_irq lapic_irq;
6aef266c 6654
24d2166b
R		 6655 lapic_irq.shorthand = 0;
6656 lapic_irq.dest_mode = 0;
ebd28fcb 6657 lapic_irq.level = 0;
24d2166b 6658 lapic_irq.dest_id = apicid;
93bbf0b8 6659 lapic_irq.msi_redir_hint = false;
6aef266c 6660
24d2166b 6661 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6662 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6663}
6664
d62caabb
AS		 6665void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6666{
6667 vcpu->arch.apicv_active = false;
6668 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6669}
6670
8776e519
HB		 6671int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6672{
6673 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6674 int op_64_bit;
8776e519 6675
6356ee0c
MR		 6676 if (kvm_hv_hypercall_enabled(vcpu->kvm)) {
6677 if (!kvm_hv_hypercall(vcpu))
6678 return 0;
6679 goto out;
6680 }
55cd8e5a 6681
5fdbf976
MT		 6682 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6683 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6684 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6685 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6686 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6687
229456fc 6688 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6689
a449c7aa
NA		 6690 op_64_bit = is_64_bit_mode(vcpu);
6691 if (!op_64_bit) {
8776e519
HB		 6692 nr &= 0xFFFFFFFF;
6693 a0 &= 0xFFFFFFFF;
6694 a1 &= 0xFFFFFFFF;
6695 a2 &= 0xFFFFFFFF;
6696 a3 &= 0xFFFFFFFF;
6697 }
6698
07708c4a
JK		 6699 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6700 ret = -KVM_EPERM;
6356ee0c 6701 goto out_error;
07708c4a
JK		 6702 }
6703
8776e519 6704 switch (nr) {
b93463aa
AK		 6705 case KVM_HC_VAPIC_POLL_IRQ:
6706 ret = 0;
6707 break;
6aef266c
SV		 6708 case KVM_HC_KICK_CPU:
6709 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6710 ret = 0;
6711 break;
8ef81a9a 6712#ifdef CONFIG_X86_64
55dd00a7
MT		 6713 case KVM_HC_CLOCK_PAIRING:
6714 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6715 break;
8ef81a9a 6716#endif
8776e519
HB		 6717 default:
6718 ret = -KVM_ENOSYS;
6719 break;
6720 }
6356ee0c 6721out_error:
a449c7aa
NA		 6722 if (!op_64_bit)
6723 ret = (u32)ret;
5fdbf976 6724 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c
MR		 6725
6726out:
f11c3a8d 6727 ++vcpu->stat.hypercalls;
6356ee0c 6728 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 6729}
6730EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6731
b6785def 6732static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6733{
d6aa1000 6734 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6735 char instruction[3];
5fdbf976 6736 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6737
8776e519 6738 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6739
ce2e852e
DV		 6740 return emulator_write_emulated(ctxt, rip, instruction, 3,
6741 &ctxt->exception);
8776e519
HB		 6742}
6743
851ba692 6744static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6745{
782d422b
MG		 6746 return vcpu->run->request_interrupt_window &&
6747 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6748}
6749
851ba692 6750static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6751{
851ba692
AK		 6752 struct kvm_run *kvm_run = vcpu->run;
6753
91586a3b 6754 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6755 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6756 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6757 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6758 kvm_run->ready_for_interrupt_injection =
6759 pic_in_kernel(vcpu->kvm) ||
782d422b 6760 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6761}
6762
95ba8273
GN		 6763static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6764{
6765 int max_irr, tpr;
6766
6767 if (!kvm_x86_ops->update_cr8_intercept)
6768 return;
6769
bce87cce 6770 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6771 return;
6772
d62caabb
AS		 6773 if (vcpu->arch.apicv_active)
6774 return;
6775
8db3baa2
GN		 6776 if (!vcpu->arch.apic->vapic_addr)
6777 max_irr = kvm_lapic_find_highest_irr(vcpu);
6778 else
6779 max_irr = -1;
95ba8273
GN		 6780
6781 if (max_irr != -1)
6782 max_irr >>= 4;
6783
6784 tpr = kvm_lapic_get_cr8(vcpu);
6785
6786 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6787}
6788
b6b8a145 6789static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6790{
b6b8a145
JK		 6791 int r;
6792
95ba8273 6793 /* try to reinject previous events if any */
664f8e26 6794
1a680e35
LA		 6795 if (vcpu->arch.exception.injected)
6796 kvm_x86_ops->queue_exception(vcpu);
664f8e26 6797 /*
a042c26f
LA		 6798 * Do not inject an NMI or interrupt if there is a pending
6799 * exception. Exceptions and interrupts are recognized at
6800 * instruction boundaries, i.e. the start of an instruction.
6801 * Trap-like exceptions, e.g. #DB, have higher priority than
6802 * NMIs and interrupts, i.e. traps are recognized before an
6803 * NMI/interrupt that's pending on the same instruction.
6804 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
6805 * priority, but are only generated (pended) during instruction
6806 * execution, i.e. a pending fault-like exception means the
6807 * fault occurred on the *previous* instruction and must be
6808 * serviced prior to recognizing any new events in order to
6809 * fully complete the previous instruction.
664f8e26 6810 */
1a680e35
LA		 6811 else if (!vcpu->arch.exception.pending) {
6812 if (vcpu->arch.nmi_injected)
664f8e26 6813 kvm_x86_ops->set_nmi(vcpu);
1a680e35 6814 else if (vcpu->arch.interrupt.injected)
664f8e26 6815 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 6816 }
6817
1a680e35
LA		 6818 /*
6819 * Call check_nested_events() even if we reinjected a previous event
6820 * in order for caller to determine if it should require immediate-exit
6821 * from L2 to L1 due to pending L1 events which require exit
6822 * from L2 to L1.
6823 */
664f8e26
WL		 6824 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6825 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6826 if (r != 0)
6827 return r;
6828 }
6829
6830 /* try to inject new event if pending */
b59bb7bd 6831 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6832 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6833 vcpu->arch.exception.has_error_code,
6834 vcpu->arch.exception.error_code);
d6e8c854 6835
1a680e35 6836 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 6837 vcpu->arch.exception.pending = false;
6838 vcpu->arch.exception.injected = true;
6839
d6e8c854
NA		 6840 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6841 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6842 X86_EFLAGS_RF);
6843
6bdf0662
NA		 6844 if (vcpu->arch.exception.nr == DB_VECTOR &&
6845 (vcpu->arch.dr7 & DR7_GD)) {
6846 vcpu->arch.dr7 &= ~DR7_GD;
6847 kvm_update_dr7(vcpu);
6848 }
6849
cfcd20e5 6850 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 6851 }
6852
6853 /* Don't consider new event if we re-injected an event */
6854 if (kvm_event_needs_reinjection(vcpu))
6855 return 0;
6856
6857 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
6858 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6859 vcpu->arch.smi_pending = false;
52797bf9 6860 ++vcpu->arch.smi_count;
ee2cd4b7 6861 enter_smm(vcpu);
c43203ca 6862 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6863 --vcpu->arch.nmi_pending;
6864 vcpu->arch.nmi_injected = true;
6865 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6866 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6867 /*
6868 * Because interrupts can be injected asynchronously, we are
6869 * calling check_nested_events again here to avoid a race condition.
6870 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6871 * proposal and current concerns. Perhaps we should be setting
6872 * KVM_REQ_EVENT only on certain events and not unconditionally?
6873 */
6874 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6875 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6876 if (r != 0)
6877 return r;
6878 }
95ba8273 6879 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6880 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6881 false);
6882 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6883 }
6884 }
ee2cd4b7 6885
b6b8a145 6886 return 0;
95ba8273
GN		 6887}
6888
7460fb4a
AK		 6889static void process_nmi(struct kvm_vcpu *vcpu)
6890{
6891 unsigned limit = 2;
6892
6893 /*
6894 * x86 is limited to one NMI running, and one NMI pending after it.
6895 * If an NMI is already in progress, limit further NMIs to just one.
6896 * Otherwise, allow two (and we'll inject the first one immediately).
6897 */
6898 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6899 limit = 1;
6900
6901 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6902 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6903 kvm_make_request(KVM_REQ_EVENT, vcpu);
6904}
6905
ee2cd4b7 6906static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6907{
6908 u32 flags = 0;
6909 flags |= seg->g << 23;
6910 flags |= seg->db << 22;
6911 flags |= seg->l << 21;
6912 flags |= seg->avl << 20;
6913 flags |= seg->present << 15;
6914 flags |= seg->dpl << 13;
6915 flags |= seg->s << 12;
6916 flags |= seg->type << 8;
6917 return flags;
6918}
6919
ee2cd4b7 6920static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6921{
6922 struct kvm_segment seg;
6923 int offset;
6924
6925 kvm_get_segment(vcpu, &seg, n);
6926 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6927
6928 if (n < 3)
6929 offset = 0x7f84 + n * 12;
6930 else
6931 offset = 0x7f2c + (n - 3) * 12;
6932
6933 put_smstate(u32, buf, offset + 8, seg.base);
6934 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6935 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6936}
6937
efbb288a 6938#ifdef CONFIG_X86_64
ee2cd4b7 6939static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6940{
6941 struct kvm_segment seg;
6942 int offset;
6943 u16 flags;
6944
6945 kvm_get_segment(vcpu, &seg, n);
6946 offset = 0x7e00 + n * 16;
6947
ee2cd4b7 6948 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6949 put_smstate(u16, buf, offset, seg.selector);
6950 put_smstate(u16, buf, offset + 2, flags);
6951 put_smstate(u32, buf, offset + 4, seg.limit);
6952 put_smstate(u64, buf, offset + 8, seg.base);
6953}
efbb288a 6954#endif
660a5d51 6955
ee2cd4b7 6956static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6957{
6958 struct desc_ptr dt;
6959 struct kvm_segment seg;
6960 unsigned long val;
6961 int i;
6962
6963 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6964 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6965 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6966 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6967
6968 for (i = 0; i < 8; i++)
6969 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6970
6971 kvm_get_dr(vcpu, 6, &val);
6972 put_smstate(u32, buf, 0x7fcc, (u32)val);
6973 kvm_get_dr(vcpu, 7, &val);
6974 put_smstate(u32, buf, 0x7fc8, (u32)val);
6975
6976 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6977 put_smstate(u32, buf, 0x7fc4, seg.selector);
6978 put_smstate(u32, buf, 0x7f64, seg.base);
6979 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6980 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6981
6982 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6983 put_smstate(u32, buf, 0x7fc0, seg.selector);
6984 put_smstate(u32, buf, 0x7f80, seg.base);
6985 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6986 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6987
6988 kvm_x86_ops->get_gdt(vcpu, &dt);
6989 put_smstate(u32, buf, 0x7f74, dt.address);
6990 put_smstate(u32, buf, 0x7f70, dt.size);
6991
6992 kvm_x86_ops->get_idt(vcpu, &dt);
6993 put_smstate(u32, buf, 0x7f58, dt.address);
6994 put_smstate(u32, buf, 0x7f54, dt.size);
6995
6996 for (i = 0; i < 6; i++)
ee2cd4b7 6997 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6998
6999 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7000
7001 /* revision id */
7002 put_smstate(u32, buf, 0x7efc, 0x00020000);
7003 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7004}
7005
ee2cd4b7 7006static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7007{
7008#ifdef CONFIG_X86_64
7009 struct desc_ptr dt;
7010 struct kvm_segment seg;
7011 unsigned long val;
7012 int i;
7013
7014 for (i = 0; i < 16; i++)
7015 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7016
7017 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7018 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7019
7020 kvm_get_dr(vcpu, 6, &val);
7021 put_smstate(u64, buf, 0x7f68, val);
7022 kvm_get_dr(vcpu, 7, &val);
7023 put_smstate(u64, buf, 0x7f60, val);
7024
7025 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7026 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7027 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7028
7029 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7030
7031 /* revision id */
7032 put_smstate(u32, buf, 0x7efc, 0x00020064);
7033
7034 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7035
7036 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7037 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7038 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7039 put_smstate(u32, buf, 0x7e94, seg.limit);
7040 put_smstate(u64, buf, 0x7e98, seg.base);
7041
7042 kvm_x86_ops->get_idt(vcpu, &dt);
7043 put_smstate(u32, buf, 0x7e84, dt.size);
7044 put_smstate(u64, buf, 0x7e88, dt.address);
7045
7046 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7047 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7048 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7049 put_smstate(u32, buf, 0x7e74, seg.limit);
7050 put_smstate(u64, buf, 0x7e78, seg.base);
7051
7052 kvm_x86_ops->get_gdt(vcpu, &dt);
7053 put_smstate(u32, buf, 0x7e64, dt.size);
7054 put_smstate(u64, buf, 0x7e68, dt.address);
7055
7056 for (i = 0; i < 6; i++)
ee2cd4b7 7057 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7058#else
7059 WARN_ON_ONCE(1);
7060#endif
7061}
7062
ee2cd4b7 7063static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7064{
660a5d51 7065 struct kvm_segment cs, ds;
18c3626e 7066 struct desc_ptr dt;
660a5d51
PB		 7067 char buf[512];
7068 u32 cr0;
7069
660a5d51 7070 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7071 memset(buf, 0, 512);
d6321d49 7072 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7073 enter_smm_save_state_64(vcpu, buf);
660a5d51 7074 else
ee2cd4b7 7075 enter_smm_save_state_32(vcpu, buf);
660a5d51 7076
0234bf88
LP		 7077 /*
7078 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7079 * vCPU state (e.g. leave guest mode) after we've saved the state into
7080 * the SMM state-save area.
7081 */
7082 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7083
7084 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7085 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7086
7087 if (kvm_x86_ops->get_nmi_mask(vcpu))
7088 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7089 else
7090 kvm_x86_ops->set_nmi_mask(vcpu, true);
7091
7092 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7093 kvm_rip_write(vcpu, 0x8000);
7094
7095 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7096 kvm_x86_ops->set_cr0(vcpu, cr0);
7097 vcpu->arch.cr0 = cr0;
7098
7099 kvm_x86_ops->set_cr4(vcpu, 0);
7100
18c3626e
PB		 7101 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7102 dt.address = dt.size = 0;
7103 kvm_x86_ops->set_idt(vcpu, &dt);
7104
660a5d51
PB		 7105 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7106
7107 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7108 cs.base = vcpu->arch.smbase;
7109
7110 ds.selector = 0;
7111 ds.base = 0;
7112
7113 cs.limit = ds.limit = 0xffffffff;
7114 cs.type = ds.type = 0x3;
7115 cs.dpl = ds.dpl = 0;
7116 cs.db = ds.db = 0;
7117 cs.s = ds.s = 1;
7118 cs.l = ds.l = 0;
7119 cs.g = ds.g = 1;
7120 cs.avl = ds.avl = 0;
7121 cs.present = ds.present = 1;
7122 cs.unusable = ds.unusable = 0;
7123 cs.padding = ds.padding = 0;
7124
7125 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7126 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7127 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7128 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7129 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7130 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7131
d6321d49 7132 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7133 kvm_x86_ops->set_efer(vcpu, 0);
7134
7135 kvm_update_cpuid(vcpu);
7136 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7137}
7138
ee2cd4b7 7139static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7140{
7141 vcpu->arch.smi_pending = true;
7142 kvm_make_request(KVM_REQ_EVENT, vcpu);
7143}
7144
2860c4b1
PB		 7145void kvm_make_scan_ioapic_request(struct kvm *kvm)
7146{
7147 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7148}
7149
3d81bc7e 7150static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7151{
3d81bc7e
YZ		 7152 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7153 return;
c7c9c56c 7154
6308630b 7155 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7156
b053b2ae 7157 if (irqchip_split(vcpu->kvm))
6308630b 7158 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7159 else {
fa59cc00 7160 if (vcpu->arch.apicv_active)
d62caabb 7161 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7162 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7163 }
e40ff1d6
LA		 7164
7165 if (is_guest_mode(vcpu))
7166 vcpu->arch.load_eoi_exitmap_pending = true;
7167 else
7168 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7169}
7170
7171static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7172{
7173 u64 eoi_exit_bitmap[4];
7174
7175 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7176 return;
7177
5c919412
AS		 7178 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7179 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7180 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7181}
7182
b1394e74
RK		 7183void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7184 unsigned long start, unsigned long end)
7185{
7186 unsigned long apic_address;
7187
7188 /*
7189 * The physical address of apic access page is stored in the VMCS.
7190 * Update it when it becomes invalid.
7191 */
7192 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7193 if (start <= apic_address && apic_address < end)
7194 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7195}
7196
4256f43f
TC		 7197void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7198{
c24ae0dc
TC		 7199 struct page *page = NULL;
7200
35754c98 7201 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7202 return;
7203
4256f43f
TC		 7204 if (!kvm_x86_ops->set_apic_access_page_addr)
7205 return;
7206
c24ae0dc 7207 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7208 if (is_error_page(page))
7209 return;
c24ae0dc
TC		 7210 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7211
7212 /*
7213 * Do not pin apic access page in memory, the MMU notifier
7214 * will call us again if it is migrated or swapped out.
7215 */
7216 put_page(page);
4256f43f
TC		 7217}
7218EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7219
9357d939 7220/*
362c698f 7221 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7222 * exiting to the userspace. Otherwise, the value will be returned to the
7223 * userspace.
7224 */
851ba692 7225static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7226{
7227 int r;
62a193ed
MG		 7228 bool req_int_win =
7229 dm_request_for_irq_injection(vcpu) &&
7230 kvm_cpu_accept_dm_intr(vcpu);
7231
730dca42 7232 bool req_immediate_exit = false;
b6c7a5dc 7233
2fa6e1e1 7234 if (kvm_request_pending(vcpu)) {
a8eeb04a 7235 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7236 kvm_mmu_unload(vcpu);
a8eeb04a 7237 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7238 __kvm_migrate_timers(vcpu);
d828199e
MT		 7239 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7240 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7241 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7242 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7243 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7244 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7245 if (unlikely(r))
7246 goto out;
7247 }
a8eeb04a 7248 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7249 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7250 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7251 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7252 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7253 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7254 r = 0;
7255 goto out;
7256 }
a8eeb04a 7257 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7258 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7259 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7260 r = 0;
7261 goto out;
7262 }
af585b92
GN		 7263 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7264 /* Page is swapped out. Do synthetic halt */
7265 vcpu->arch.apf.halted = true;
7266 r = 1;
7267 goto out;
7268 }
c9aaa895
GC		 7269 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7270 record_steal_time(vcpu);
64d60670
PB		 7271 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7272 process_smi(vcpu);
7460fb4a
AK		 7273 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7274 process_nmi(vcpu);
f5132b01 7275 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7276 kvm_pmu_handle_event(vcpu);
f5132b01 7277 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7278 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7279 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7280 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7281 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7282 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7283 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7284 vcpu->run->eoi.vector =
7285 vcpu->arch.pending_ioapic_eoi;
7286 r = 0;
7287 goto out;
7288 }
7289 }
3d81bc7e
YZ		 7290 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7291 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7292 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7293 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7294 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7295 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7296 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7297 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7298 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7299 r = 0;
7300 goto out;
7301 }
e516cebb
AS		 7302 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7303 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7304 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7305 r = 0;
7306 goto out;
7307 }
db397571
AS		 7308 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7309 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7310 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7311 r = 0;
7312 goto out;
7313 }
f3b138c5
AS		 7314
7315 /*
7316 * KVM_REQ_HV_STIMER has to be processed after
7317 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7318 * depend on the guest clock being up-to-date
7319 */
1f4b34f8
AS		 7320 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7321 kvm_hv_process_stimers(vcpu);
2f52d58c 7322 }
b93463aa 7323
b463a6f7 7324 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7325 ++vcpu->stat.req_event;
66450a21
JK		 7326 kvm_apic_accept_events(vcpu);
7327 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7328 r = 1;
7329 goto out;
7330 }
7331
b6b8a145
JK		 7332 if (inject_pending_event(vcpu, req_int_win) != 0)
7333 req_immediate_exit = true;
321c5658 7334 else {
cc3d967f 7335 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7336 *
cc3d967f
LP		 7337 * SMIs have three cases:
7338 * 1) They can be nested, and then there is nothing to
7339 * do here because RSM will cause a vmexit anyway.
7340 * 2) There is an ISA-specific reason why SMI cannot be
7341 * injected, and the moment when this changes can be
7342 * intercepted.
7343 * 3) Or the SMI can be pending because
7344 * inject_pending_event has completed the injection
7345 * of an IRQ or NMI from the previous vmexit, and
7346 * then we request an immediate exit to inject the
7347 * SMI.
c43203ca
PB		 7348 */
7349 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7350 if (!kvm_x86_ops->enable_smi_window(vcpu))
7351 req_immediate_exit = true;
321c5658
YS		 7352 if (vcpu->arch.nmi_pending)
7353 kvm_x86_ops->enable_nmi_window(vcpu);
7354 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7355 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7356 WARN_ON(vcpu->arch.exception.pending);
321c5658 7357 }
b463a6f7
AK		 7358
7359 if (kvm_lapic_enabled(vcpu)) {
7360 update_cr8_intercept(vcpu);
7361 kvm_lapic_sync_to_vapic(vcpu);
7362 }
7363 }
7364
d8368af8
AK		 7365 r = kvm_mmu_reload(vcpu);
7366 if (unlikely(r)) {
d905c069 7367 goto cancel_injection;
d8368af8
AK		 7368 }
7369
b6c7a5dc
HB		 7370 preempt_disable();
7371
7372 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7373
7374 /*
7375 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7376 * IPI are then delayed after guest entry, which ensures that they
7377 * result in virtual interrupt delivery.
7378 */
7379 local_irq_disable();
6b7e2d09
XG		 7380 vcpu->mode = IN_GUEST_MODE;
7381
01b71917
MT		 7382 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7383
0f127d12 7384 /*
b95234c8 7385 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7386 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7387 *
7388 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7389 * pairs with the memory barrier implicit in pi_test_and_set_on
7390 * (see vmx_deliver_posted_interrupt).
7391 *
7392 * 3) This also orders the write to mode from any reads to the page
7393 * tables done while the VCPU is running. Please see the comment
7394 * in kvm_flush_remote_tlbs.
6b7e2d09 7395 */
01b71917 7396 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7397
b95234c8
PB		 7398 /*
7399 * This handles the case where a posted interrupt was
7400 * notified with kvm_vcpu_kick.
7401 */
fa59cc00
LA		 7402 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7403 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7404
2fa6e1e1 7405 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7406 || need_resched() || signal_pending(current)) {
6b7e2d09 7407 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7408 smp_wmb();
6c142801
AK		 7409 local_irq_enable();
7410 preempt_enable();
01b71917 7411 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7412 r = 1;
d905c069 7413 goto cancel_injection;
6c142801
AK		 7414 }
7415
fc5b7f3b
DM		 7416 kvm_load_guest_xcr0(vcpu);
7417
c43203ca
PB		 7418 if (req_immediate_exit) {
7419 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7420 smp_send_reschedule(vcpu->cpu);
c43203ca 7421 }
d6185f20 7422
8b89fe1f 7423 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7424 if (lapic_timer_advance_ns)
7425 wait_lapic_expire(vcpu);
6edaa530 7426 guest_enter_irqoff();
b6c7a5dc 7427
42dbaa5a 7428 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7429 set_debugreg(0, 7);
7430 set_debugreg(vcpu->arch.eff_db[0], 0);
7431 set_debugreg(vcpu->arch.eff_db[1], 1);
7432 set_debugreg(vcpu->arch.eff_db[2], 2);
7433 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7434 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7435 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7436 }
b6c7a5dc 7437
851ba692 7438 kvm_x86_ops->run(vcpu);
b6c7a5dc 7439
c77fb5fe
PB		 7440 /*
7441 * Do this here before restoring debug registers on the host. And
7442 * since we do this before handling the vmexit, a DR access vmexit
7443 * can (a) read the correct value of the debug registers, (b) set
7444 * KVM_DEBUGREG_WONT_EXIT again.
7445 */
7446 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7447 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7448 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7449 kvm_update_dr0123(vcpu);
7450 kvm_update_dr6(vcpu);
7451 kvm_update_dr7(vcpu);
7452 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7453 }
7454
24f1e32c
FW		 7455 /*
7456 * If the guest has used debug registers, at least dr7
7457 * will be disabled while returning to the host.
7458 * If we don't have active breakpoints in the host, we don't
7459 * care about the messed up debug address registers. But if
7460 * we have some of them active, restore the old state.
7461 */
59d8eb53 7462 if (hw_breakpoint_active())
24f1e32c 7463 hw_breakpoint_restore();
42dbaa5a 7464
4ba76538 7465 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7466
6b7e2d09 7467 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7468 smp_wmb();
a547c6db 7469
fc5b7f3b
DM		 7470 kvm_put_guest_xcr0(vcpu);
7471
dd60d217 7472 kvm_before_interrupt(vcpu);
a547c6db 7473 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7474 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7475
7476 ++vcpu->stat.exits;
7477
f2485b3e 7478 guest_exit_irqoff();
b6c7a5dc 7479
f2485b3e 7480 local_irq_enable();
b6c7a5dc
HB		 7481 preempt_enable();
7482
f656ce01 7483 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7484
b6c7a5dc
HB		 7485 /*
7486 * Profile KVM exit RIPs:
7487 */
7488 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7489 unsigned long rip = kvm_rip_read(vcpu);
7490 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7491 }
7492
cc578287
ZA		 7493 if (unlikely(vcpu->arch.tsc_always_catchup))
7494 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7495
5cfb1d5a
MT		 7496 if (vcpu->arch.apic_attention)
7497 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7498
618232e2 7499 vcpu->arch.gpa_available = false;
851ba692 7500 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7501 return r;
7502
7503cancel_injection:
7504 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7505 if (unlikely(vcpu->arch.apic_attention))
7506 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7507out:
7508 return r;
7509}
b6c7a5dc 7510
362c698f
PB		 7511static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7512{
bf9f6ac8
FW		 7513 if (!kvm_arch_vcpu_runnable(vcpu) &&
7514 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7515 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7516 kvm_vcpu_block(vcpu);
7517 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7518
7519 if (kvm_x86_ops->post_block)
7520 kvm_x86_ops->post_block(vcpu);
7521
9c8fd1ba
PB		 7522 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7523 return 1;
7524 }
362c698f
PB		 7525
7526 kvm_apic_accept_events(vcpu);
7527 switch(vcpu->arch.mp_state) {
7528 case KVM_MP_STATE_HALTED:
7529 vcpu->arch.pv.pv_unhalted = false;
7530 vcpu->arch.mp_state =
7531 KVM_MP_STATE_RUNNABLE;
7532 case KVM_MP_STATE_RUNNABLE:
7533 vcpu->arch.apf.halted = false;
7534 break;
7535 case KVM_MP_STATE_INIT_RECEIVED:
7536 break;
7537 default:
7538 return -EINTR;
7539 break;
7540 }
7541 return 1;
7542}
09cec754 7543
5d9bc648
PB		 7544static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7545{
0ad3bed6
PB		 7546 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7547 kvm_x86_ops->check_nested_events(vcpu, false);
7548
5d9bc648
PB		 7549 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7550 !vcpu->arch.apf.halted);
7551}
7552
362c698f 7553static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7554{
7555 int r;
f656ce01 7556 struct kvm *kvm = vcpu->kvm;
d7690175 7557
f656ce01 7558 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7559
362c698f 7560 for (;;) {
58f800d5 7561 if (kvm_vcpu_running(vcpu)) {
851ba692 7562 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7563 } else {
362c698f 7564 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7565 }
7566
09cec754
GN		 7567 if (r <= 0)
7568 break;
7569
72875d8a 7570 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7571 if (kvm_cpu_has_pending_timer(vcpu))
7572 kvm_inject_pending_timer_irqs(vcpu);
7573
782d422b
MG		 7574 if (dm_request_for_irq_injection(vcpu) &&
7575 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7576 r = 0;
7577 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7578 ++vcpu->stat.request_irq_exits;
362c698f 7579 break;
09cec754 7580 }
af585b92
GN		 7581
7582 kvm_check_async_pf_completion(vcpu);
7583
09cec754
GN		 7584 if (signal_pending(current)) {
7585 r = -EINTR;
851ba692 7586 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7587 ++vcpu->stat.signal_exits;
362c698f 7588 break;
09cec754
GN		 7589 }
7590 if (need_resched()) {
f656ce01 7591 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7592 cond_resched();
f656ce01 7593 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7594 }
b6c7a5dc
HB		 7595 }
7596
f656ce01 7597 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7598
7599 return r;
7600}
7601
716d51ab
GN		 7602static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7603{
7604 int r;
7605 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7606 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7607 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7608 if (r != EMULATE_DONE)
7609 return 0;
7610 return 1;
7611}
7612
7613static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7614{
7615 BUG_ON(!vcpu->arch.pio.count);
7616
7617 return complete_emulated_io(vcpu);
7618}
7619
f78146b0
AK		 7620/*
7621 * Implements the following, as a state machine:
7622 *
7623 * read:
7624 * for each fragment
87da7e66
XG		 7625 * for each mmio piece in the fragment
7626 * write gpa, len
7627 * exit
7628 * copy data
f78146b0
AK		 7629 * execute insn
7630 *
7631 * write:
7632 * for each fragment
87da7e66
XG		 7633 * for each mmio piece in the fragment
7634 * write gpa, len
7635 * copy data
7636 * exit
f78146b0 7637 */
716d51ab 7638static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7639{
7640 struct kvm_run *run = vcpu->run;
f78146b0 7641 struct kvm_mmio_fragment *frag;
87da7e66 7642 unsigned len;
5287f194 7643
716d51ab 7644 BUG_ON(!vcpu->mmio_needed);
5287f194 7645
716d51ab 7646 /* Complete previous fragment */
87da7e66
XG		 7647 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7648 len = min(8u, frag->len);
716d51ab 7649 if (!vcpu->mmio_is_write)
87da7e66
XG		 7650 memcpy(frag->data, run->mmio.data, len);
7651
7652 if (frag->len <= 8) {
7653 /* Switch to the next fragment. */
7654 frag++;
7655 vcpu->mmio_cur_fragment++;
7656 } else {
7657 /* Go forward to the next mmio piece. */
7658 frag->data += len;
7659 frag->gpa += len;
7660 frag->len -= len;
7661 }
7662
a08d3b3b 7663 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7664 vcpu->mmio_needed = 0;
0912c977
PB		 7665
7666 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7667 if (vcpu->mmio_is_write)
716d51ab
GN		 7668 return 1;
7669 vcpu->mmio_read_completed = 1;
7670 return complete_emulated_io(vcpu);
7671 }
87da7e66 7672
716d51ab
GN		 7673 run->exit_reason = KVM_EXIT_MMIO;
7674 run->mmio.phys_addr = frag->gpa;
7675 if (vcpu->mmio_is_write)
87da7e66
XG		 7676 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7677 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7678 run->mmio.is_write = vcpu->mmio_is_write;
7679 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7680 return 0;
5287f194
AK		 7681}
7682
b6c7a5dc
HB		 7683int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7684{
7685 int r;
b6c7a5dc 7686
accb757d 7687 vcpu_load(vcpu);
20b7035c 7688 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7689 kvm_load_guest_fpu(vcpu);
7690
a4535290 7691 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7692 if (kvm_run->immediate_exit) {
7693 r = -EINTR;
7694 goto out;
7695 }
b6c7a5dc 7696 kvm_vcpu_block(vcpu);
66450a21 7697 kvm_apic_accept_events(vcpu);
72875d8a 7698 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7699 r = -EAGAIN;
a0595000
JS		 7700 if (signal_pending(current)) {
7701 r = -EINTR;
7702 vcpu->run->exit_reason = KVM_EXIT_INTR;
7703 ++vcpu->stat.signal_exits;
7704 }
ac9f6dc0 7705 goto out;
b6c7a5dc
HB		 7706 }
7707
01643c51
KH		 7708 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7709 r = -EINVAL;
7710 goto out;
7711 }
7712
7713 if (vcpu->run->kvm_dirty_regs) {
7714 r = sync_regs(vcpu);
7715 if (r != 0)
7716 goto out;
7717 }
7718
b6c7a5dc 7719 /* re-sync apic's tpr */
35754c98 7720 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7721 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7722 r = -EINVAL;
7723 goto out;
7724 }
7725 }
b6c7a5dc 7726
716d51ab
GN		 7727 if (unlikely(vcpu->arch.complete_userspace_io)) {
7728 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7729 vcpu->arch.complete_userspace_io = NULL;
7730 r = cui(vcpu);
7731 if (r <= 0)
5663d8f9 7732 goto out;
716d51ab
GN		 7733 } else
7734 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7735
460df4c1
PB		 7736 if (kvm_run->immediate_exit)
7737 r = -EINTR;
7738 else
7739 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7740
7741out:
5663d8f9 7742 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7743 if (vcpu->run->kvm_valid_regs)
7744 store_regs(vcpu);
f1d86e46 7745 post_kvm_run_save(vcpu);
20b7035c 7746 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7747
accb757d 7748 vcpu_put(vcpu);
b6c7a5dc
HB		 7749 return r;
7750}
7751
01643c51 7752static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7753{
7ae441ea
GN		 7754 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7755 /*
7756 * We are here if userspace calls get_regs() in the middle of
7757 * instruction emulation. Registers state needs to be copied
4a969980 7758 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7759 * that usually, but some bad designed PV devices (vmware
7760 * backdoor interface) need this to work
7761 */
dd856efa 7762 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7763 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7764 }
5fdbf976
MT		 7765 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7766 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7767 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7768 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7769 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7770 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7771 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7772 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7773#ifdef CONFIG_X86_64
5fdbf976
MT		 7774 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7775 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7776 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7777 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7778 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7779 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7780 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7781 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7782#endif
7783
5fdbf976 7784 regs->rip = kvm_rip_read(vcpu);
91586a3b 7785 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7786}
b6c7a5dc 7787
01643c51
KH		 7788int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7789{
7790 vcpu_load(vcpu);
7791 __get_regs(vcpu, regs);
1fc9b76b 7792 vcpu_put(vcpu);
b6c7a5dc
HB		 7793 return 0;
7794}
7795
01643c51 7796static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7797{
7ae441ea
GN		 7798 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7799 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7800
5fdbf976
MT		 7801 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7802 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7803 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7804 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7805 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7806 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7807 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7808 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7809#ifdef CONFIG_X86_64
5fdbf976
MT		 7810 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7811 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7812 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7813 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7814 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7815 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7816 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7817 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7818#endif
7819
5fdbf976 7820 kvm_rip_write(vcpu, regs->rip);
d73235d1 7821 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7822
b4f14abd
JK		 7823 vcpu->arch.exception.pending = false;
7824
3842d135 7825 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7826}
3842d135 7827
01643c51
KH		 7828int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7829{
7830 vcpu_load(vcpu);
7831 __set_regs(vcpu, regs);
875656fe 7832 vcpu_put(vcpu);
b6c7a5dc
HB		 7833 return 0;
7834}
7835
b6c7a5dc
HB		 7836void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7837{
7838 struct kvm_segment cs;
7839
3e6e0aab 7840 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7841 *db = cs.db;
7842 *l = cs.l;
7843}
7844EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7845
01643c51 7846static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7847{
89a27f4d 7848 struct desc_ptr dt;
b6c7a5dc 7849
3e6e0aab
GT		 7850 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7851 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7852 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7853 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7854 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7855 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7856
3e6e0aab
GT		 7857 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7858 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7859
7860 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7861 sregs->idt.limit = dt.size;
7862 sregs->idt.base = dt.address;
b6c7a5dc 7863 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7864 sregs->gdt.limit = dt.size;
7865 sregs->gdt.base = dt.address;
b6c7a5dc 7866
4d4ec087 7867 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7868 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7869 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7870 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7871 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7872 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7873 sregs->apic_base = kvm_get_apic_base(vcpu);
7874
923c61bb 7875 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7876
04140b41 7877 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7878 set_bit(vcpu->arch.interrupt.nr,
7879 (unsigned long *)sregs->interrupt_bitmap);
01643c51 7880}
16d7a191 7881
01643c51
KH		 7882int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7883 struct kvm_sregs *sregs)
7884{
7885 vcpu_load(vcpu);
7886 __get_sregs(vcpu, sregs);
bcdec41c 7887 vcpu_put(vcpu);
b6c7a5dc
HB		 7888 return 0;
7889}
7890
62d9f0db
MT		 7891int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7892 struct kvm_mp_state *mp_state)
7893{
fd232561
CD		 7894 vcpu_load(vcpu);
7895
66450a21 7896 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7897 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7898 vcpu->arch.pv.pv_unhalted)
7899 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7900 else
7901 mp_state->mp_state = vcpu->arch.mp_state;
7902
fd232561 7903 vcpu_put(vcpu);
62d9f0db
MT		 7904 return 0;
7905}
7906
7907int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7908 struct kvm_mp_state *mp_state)
7909{
e83dff5e
CD		 7910 int ret = -EINVAL;
7911
7912 vcpu_load(vcpu);
7913
bce87cce 7914 if (!lapic_in_kernel(vcpu) &&
66450a21 7915 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7916 goto out;
66450a21 7917
28bf2888
DH		 7918 /* INITs are latched while in SMM */
7919 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7920 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7921 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7922 goto out;
28bf2888 7923
66450a21
JK		 7924 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7925 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7926 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7927 } else
7928 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7929 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7930
7931 ret = 0;
7932out:
7933 vcpu_put(vcpu);
7934 return ret;
62d9f0db
MT		 7935}
7936
7f3d35fd
KW		 7937int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7938 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7939{
9d74191a 7940 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7941 int ret;
e01c2426 7942
8ec4722d 7943 init_emulate_ctxt(vcpu);
c697518a 7944
7f3d35fd 7945 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7946 has_error_code, error_code);
c697518a 7947
c697518a 7948 if (ret)
19d04437 7949 return EMULATE_FAIL;
37817f29 7950
9d74191a
TY		 7951 kvm_rip_write(vcpu, ctxt->eip);
7952 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7953 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7954 return EMULATE_DONE;
37817f29
IE		 7955}
7956EXPORT_SYMBOL_GPL(kvm_task_switch);
7957
3140c156 7958static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 7959{
37b95951 7960 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7961 /*
7962 * When EFER.LME and CR0.PG are set, the processor is in
7963 * 64-bit mode (though maybe in a 32-bit code segment).
7964 * CR4.PAE and EFER.LMA must be set.
7965 */
37b95951 7966 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7967 || !(sregs->efer & EFER_LMA))
7968 return -EINVAL;
7969 } else {
7970 /*
7971 * Not in 64-bit mode: EFER.LMA is clear and the code
7972 * segment cannot be 64-bit.
7973 */
7974 if (sregs->efer & EFER_LMA || sregs->cs.l)
7975 return -EINVAL;
7976 }
7977
7978 return 0;
7979}
7980
01643c51 7981static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7982{
58cb628d 7983 struct msr_data apic_base_msr;
b6c7a5dc 7984 int mmu_reset_needed = 0;
63f42e02 7985 int pending_vec, max_bits, idx;
89a27f4d 7986 struct desc_ptr dt;
b4ef9d4e
CD		 7987 int ret = -EINVAL;
7988
d6321d49
RK		 7989 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7990 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7991 goto out;
6d1068b3 7992
f2981033 7993 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 7994 goto out;
f2981033 7995
d3802286
JM		 7996 apic_base_msr.data = sregs->apic_base;
7997 apic_base_msr.host_initiated = true;
7998 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 7999 goto out;
6d1068b3 8000
89a27f4d
GN		 8001 dt.size = sregs->idt.limit;
8002 dt.address = sregs->idt.base;
b6c7a5dc 8003 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8004 dt.size = sregs->gdt.limit;
8005 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8006 kvm_x86_ops->set_gdt(vcpu, &dt);
8007
ad312c7c 8008 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8009 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8010 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8011 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8012
2d3ad1f4 8013 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8014
f6801dff 8015 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8016 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8017
4d4ec087 8018 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8019 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8020 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8021
fc78f519 8022 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 8023 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 8024 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 8025 kvm_update_cpuid(vcpu);
63f42e02
XG		 8026
8027 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 8028 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 8029 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8030 mmu_reset_needed = 1;
8031 }
63f42e02 8032 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8033
8034 if (mmu_reset_needed)
8035 kvm_mmu_reset_context(vcpu);
8036
a50abc3b 8037 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8038 pending_vec = find_first_bit(
8039 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8040 if (pending_vec < max_bits) {
66fd3f7f 8041 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8042 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8043 }
8044
3e6e0aab
GT		 8045 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8046 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8047 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8048 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8049 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8050 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8051
3e6e0aab
GT		 8052 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8053 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8054
5f0269f5
ME		 8055 update_cr8_intercept(vcpu);
8056
9c3e4aab 8057 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8058 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8059 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8060 !is_protmode(vcpu))
9c3e4aab
MT		 8061 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8062
3842d135
AK		 8063 kvm_make_request(KVM_REQ_EVENT, vcpu);
8064
b4ef9d4e
CD		 8065 ret = 0;
8066out:
01643c51
KH		 8067 return ret;
8068}
8069
8070int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8071 struct kvm_sregs *sregs)
8072{
8073 int ret;
8074
8075 vcpu_load(vcpu);
8076 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8077 vcpu_put(vcpu);
8078 return ret;
b6c7a5dc
HB		 8079}
8080
d0bfb940
JK		 8081int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8082 struct kvm_guest_debug *dbg)
b6c7a5dc 8083{
355be0b9 8084 unsigned long rflags;
ae675ef0 8085 int i, r;
b6c7a5dc 8086
66b56562
CD		 8087 vcpu_load(vcpu);
8088
4f926bf2
JK		 8089 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8090 r = -EBUSY;
8091 if (vcpu->arch.exception.pending)
2122ff5e 8092 goto out;
4f926bf2
JK		 8093 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8094 kvm_queue_exception(vcpu, DB_VECTOR);
8095 else
8096 kvm_queue_exception(vcpu, BP_VECTOR);
8097 }
8098
91586a3b
JK		 8099 /*
8100 * Read rflags as long as potentially injected trace flags are still
8101 * filtered out.
8102 */
8103 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8104
8105 vcpu->guest_debug = dbg->control;
8106 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8107 vcpu->guest_debug = 0;
8108
8109 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8110 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8111 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8112 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8113 } else {
8114 for (i = 0; i < KVM_NR_DB_REGS; i++)
8115 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8116 }
c8639010 8117 kvm_update_dr7(vcpu);
ae675ef0 8118
f92653ee
JK		 8119 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8120 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8121 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8122
91586a3b
JK		 8123 /*
8124 * Trigger an rflags update that will inject or remove the trace
8125 * flags.
8126 */
8127 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8128
a96036b8 8129 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8130
4f926bf2 8131 r = 0;
d0bfb940 8132
2122ff5e 8133out:
66b56562 8134 vcpu_put(vcpu);
b6c7a5dc
HB		 8135 return r;
8136}
8137
8b006791
ZX		 8138/*
8139 * Translate a guest virtual address to a guest physical address.
8140 */
8141int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8142 struct kvm_translation *tr)
8143{
8144 unsigned long vaddr = tr->linear_address;
8145 gpa_t gpa;
f656ce01 8146 int idx;
8b006791 8147
1da5b61d
CD		 8148 vcpu_load(vcpu);
8149
f656ce01 8150 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8151 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8152 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8153 tr->physical_address = gpa;
8154 tr->valid = gpa != UNMAPPED_GVA;
8155 tr->writeable = 1;
8156 tr->usermode = 0;
8b006791 8157
1da5b61d 8158 vcpu_put(vcpu);
8b006791
ZX		 8159 return 0;
8160}
8161
d0752060
HB		 8162int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8163{
1393123e 8164 struct fxregs_state *fxsave;
d0752060 8165
1393123e 8166 vcpu_load(vcpu);
d0752060 8167
1393123e 8168 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8169 memcpy(fpu->fpr, fxsave->st_space, 128);
8170 fpu->fcw = fxsave->cwd;
8171 fpu->fsw = fxsave->swd;
8172 fpu->ftwx = fxsave->twd;
8173 fpu->last_opcode = fxsave->fop;
8174 fpu->last_ip = fxsave->rip;
8175 fpu->last_dp = fxsave->rdp;
8176 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8177
1393123e 8178 vcpu_put(vcpu);
d0752060
HB		 8179 return 0;
8180}
8181
8182int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8183{
6a96bc7f
CD		 8184 struct fxregs_state *fxsave;
8185
8186 vcpu_load(vcpu);
8187
8188 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8189
d0752060
HB		 8190 memcpy(fxsave->st_space, fpu->fpr, 128);
8191 fxsave->cwd = fpu->fcw;
8192 fxsave->swd = fpu->fsw;
8193 fxsave->twd = fpu->ftwx;
8194 fxsave->fop = fpu->last_opcode;
8195 fxsave->rip = fpu->last_ip;
8196 fxsave->rdp = fpu->last_dp;
8197 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8198
6a96bc7f 8199 vcpu_put(vcpu);
d0752060
HB		 8200 return 0;
8201}
8202
01643c51
KH		 8203static void store_regs(struct kvm_vcpu *vcpu)
8204{
8205 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8206
8207 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8208 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8209
8210 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8211 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8212
8213 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8214 kvm_vcpu_ioctl_x86_get_vcpu_events(
8215 vcpu, &vcpu->run->s.regs.events);
8216}
8217
8218static int sync_regs(struct kvm_vcpu *vcpu)
8219{
8220 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8221 return -EINVAL;
8222
8223 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8224 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8225 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8226 }
8227 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8228 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8229 return -EINVAL;
8230 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8231 }
8232 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8233 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8234 vcpu, &vcpu->run->s.regs.events))
8235 return -EINVAL;
8236 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8237 }
8238
8239 return 0;
8240}
8241
0ee6a517 8242static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8243{
bf935b0b 8244 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8245 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8246 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8247 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8248
2acf923e
DC		 8249 /*
8250 * Ensure guest xcr0 is valid for loading
8251 */
d91cab78 8252 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8253
ad312c7c 8254 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8255}
d0752060 8256
f775b13e 8257/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8258void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8259{
f775b13e
RR		 8260 preempt_disable();
8261 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8262 /* PKRU is separately restored in kvm_x86_ops->run. */
8263 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8264 ~XFEATURE_MASK_PKRU);
f775b13e 8265 preempt_enable();
0c04851c 8266 trace_kvm_fpu(1);
d0752060 8267}
d0752060 8268
f775b13e 8269/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8270void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8271{
f775b13e 8272 preempt_disable();
4f836347 8273 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8274 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8275 preempt_enable();
f096ed85 8276 ++vcpu->stat.fpu_reload;
0c04851c 8277 trace_kvm_fpu(0);
d0752060 8278}
e9b11c17
ZX		 8279
8280void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8281{
bd768e14
IY		 8282 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8283
12f9a48f 8284 kvmclock_reset(vcpu);
7f1ea208 8285
e9b11c17 8286 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8287 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8288}
8289
8290struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8291 unsigned int id)
8292{
c447e76b
LL		 8293 struct kvm_vcpu *vcpu;
8294
b0c39dc6 8295 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8296 printk_once(KERN_WARNING
8297 "kvm: SMP vm created on host with unstable TSC; "
8298 "guest TSC will not be reliable\n");
c447e76b
LL		 8299
8300 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8301
c447e76b 8302 return vcpu;
26e5215f 8303}
e9b11c17 8304
26e5215f
AK		 8305int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8306{
19efffa2 8307 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8308 vcpu_load(vcpu);
d28bc9dd 8309 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8310 kvm_mmu_setup(vcpu);
e9b11c17 8311 vcpu_put(vcpu);
ec7660cc 8312 return 0;
e9b11c17
ZX		 8313}
8314
31928aa5 8315void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8316{
8fe8ab46 8317 struct msr_data msr;
332967a3 8318 struct kvm *kvm = vcpu->kvm;
42897d86 8319
d3457c87
RK		 8320 kvm_hv_vcpu_postcreate(vcpu);
8321
ec7660cc 8322 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8323 return;
ec7660cc 8324 vcpu_load(vcpu);
8fe8ab46
WA		 8325 msr.data = 0x0;
8326 msr.index = MSR_IA32_TSC;
8327 msr.host_initiated = true;
8328 kvm_write_tsc(vcpu, &msr);
42897d86 8329 vcpu_put(vcpu);
ec7660cc 8330 mutex_unlock(&vcpu->mutex);
42897d86 8331
630994b3
MT		 8332 if (!kvmclock_periodic_sync)
8333 return;
8334
332967a3
AJ		 8335 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8336 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8337}
8338
d40ccc62 8339void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8340{
344d9588
GN		 8341 vcpu->arch.apf.msr_val = 0;
8342
ec7660cc 8343 vcpu_load(vcpu);
e9b11c17
ZX		 8344 kvm_mmu_unload(vcpu);
8345 vcpu_put(vcpu);
8346
8347 kvm_x86_ops->vcpu_free(vcpu);
8348}
8349
d28bc9dd 8350void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8351{
b7e31be3
RK		 8352 kvm_lapic_reset(vcpu, init_event);
8353
e69fab5d
PB		 8354 vcpu->arch.hflags = 0;
8355
c43203ca 8356 vcpu->arch.smi_pending = 0;
52797bf9 8357 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8358 atomic_set(&vcpu->arch.nmi_queued, 0);
8359 vcpu->arch.nmi_pending = 0;
448fa4a9 8360 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8361 kvm_clear_interrupt_queue(vcpu);
8362 kvm_clear_exception_queue(vcpu);
664f8e26 8363 vcpu->arch.exception.pending = false;
448fa4a9 8364
42dbaa5a 8365 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8366 kvm_update_dr0123(vcpu);
6f43ed01 8367 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8368 kvm_update_dr6(vcpu);
42dbaa5a 8369 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8370 kvm_update_dr7(vcpu);
42dbaa5a 8371
1119022c
NA		 8372 vcpu->arch.cr2 = 0;
8373
3842d135 8374 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8375 vcpu->arch.apf.msr_val = 0;
c9aaa895 8376 vcpu->arch.st.msr_val = 0;
3842d135 8377
12f9a48f
GC		 8378 kvmclock_reset(vcpu);
8379
af585b92
GN		 8380 kvm_clear_async_pf_completion_queue(vcpu);
8381 kvm_async_pf_hash_reset(vcpu);
8382 vcpu->arch.apf.halted = false;
3842d135 8383
a554d207
WL		 8384 if (kvm_mpx_supported()) {
8385 void *mpx_state_buffer;
8386
8387 /*
8388 * To avoid have the INIT path from kvm_apic_has_events() that be
8389 * called with loaded FPU and does not let userspace fix the state.
8390 */
f775b13e
RR		 8391 if (init_event)
8392 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8393 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8394 XFEATURE_MASK_BNDREGS);
8395 if (mpx_state_buffer)
8396 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8397 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8398 XFEATURE_MASK_BNDCSR);
8399 if (mpx_state_buffer)
8400 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8401 if (init_event)
8402 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8403 }
8404
64d60670 8405 if (!init_event) {
d28bc9dd 8406 kvm_pmu_reset(vcpu);
64d60670 8407 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8408
8409 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8410 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8411
8412 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8413 }
f5132b01 8414
66f7b72e
JS		 8415 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8416 vcpu->arch.regs_avail = ~0;
8417 vcpu->arch.regs_dirty = ~0;
8418
a554d207
WL		 8419 vcpu->arch.ia32_xss = 0;
8420
d28bc9dd 8421 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8422}
8423
2b4a273b 8424void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8425{
8426 struct kvm_segment cs;
8427
8428 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8429 cs.selector = vector << 8;
8430 cs.base = vector << 12;
8431 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8432 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8433}
8434
13a34e06 8435int kvm_arch_hardware_enable(void)
e9b11c17 8436{
ca84d1a2
ZA		 8437 struct kvm *kvm;
8438 struct kvm_vcpu *vcpu;
8439 int i;
0dd6a6ed
ZA		 8440 int ret;
8441 u64 local_tsc;
8442 u64 max_tsc = 0;
8443 bool stable, backwards_tsc = false;
18863bdd
AK		 8444
8445 kvm_shared_msr_cpu_online();
13a34e06 8446 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8447 if (ret != 0)
8448 return ret;
8449
4ea1636b 8450 local_tsc = rdtsc();
b0c39dc6 8451 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8452 list_for_each_entry(kvm, &vm_list, vm_list) {
8453 kvm_for_each_vcpu(i, vcpu, kvm) {
8454 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8455 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8456 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8457 backwards_tsc = true;
8458 if (vcpu->arch.last_host_tsc > max_tsc)
8459 max_tsc = vcpu->arch.last_host_tsc;
8460 }
8461 }
8462 }
8463
8464 /*
8465 * Sometimes, even reliable TSCs go backwards. This happens on
8466 * platforms that reset TSC during suspend or hibernate actions, but
8467 * maintain synchronization. We must compensate. Fortunately, we can
8468 * detect that condition here, which happens early in CPU bringup,
8469 * before any KVM threads can be running. Unfortunately, we can't
8470 * bring the TSCs fully up to date with real time, as we aren't yet far
8471 * enough into CPU bringup that we know how much real time has actually
108b249c 8472 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8473 * variables that haven't been updated yet.
8474 *
8475 * So we simply find the maximum observed TSC above, then record the
8476 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8477 * the adjustment will be applied. Note that we accumulate
8478 * adjustments, in case multiple suspend cycles happen before some VCPU
8479 * gets a chance to run again. In the event that no KVM threads get a
8480 * chance to run, we will miss the entire elapsed period, as we'll have
8481 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8482 * loose cycle time. This isn't too big a deal, since the loss will be
8483 * uniform across all VCPUs (not to mention the scenario is extremely
8484 * unlikely). It is possible that a second hibernate recovery happens
8485 * much faster than a first, causing the observed TSC here to be
8486 * smaller; this would require additional padding adjustment, which is
8487 * why we set last_host_tsc to the local tsc observed here.
8488 *
8489 * N.B. - this code below runs only on platforms with reliable TSC,
8490 * as that is the only way backwards_tsc is set above. Also note
8491 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8492 * have the same delta_cyc adjustment applied if backwards_tsc
8493 * is detected. Note further, this adjustment is only done once,
8494 * as we reset last_host_tsc on all VCPUs to stop this from being
8495 * called multiple times (one for each physical CPU bringup).
8496 *
4a969980 8497 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8498 * will be compensated by the logic in vcpu_load, which sets the TSC to
8499 * catchup mode. This will catchup all VCPUs to real time, but cannot
8500 * guarantee that they stay in perfect synchronization.
8501 */
8502 if (backwards_tsc) {
8503 u64 delta_cyc = max_tsc - local_tsc;
8504 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8505 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8506 kvm_for_each_vcpu(i, vcpu, kvm) {
8507 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8508 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8509 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8510 }
8511
8512 /*
8513 * We have to disable TSC offset matching.. if you were
8514 * booting a VM while issuing an S4 host suspend....
8515 * you may have some problem. Solving this issue is
8516 * left as an exercise to the reader.
8517 */
8518 kvm->arch.last_tsc_nsec = 0;
8519 kvm->arch.last_tsc_write = 0;
8520 }
8521
8522 }
8523 return 0;
e9b11c17
ZX		 8524}
8525
13a34e06 8526void kvm_arch_hardware_disable(void)
e9b11c17 8527{
13a34e06
RK		 8528 kvm_x86_ops->hardware_disable();
8529 drop_user_return_notifiers();
e9b11c17
ZX		 8530}
8531
8532int kvm_arch_hardware_setup(void)
8533{
9e9c3fe4
NA		 8534 int r;
8535
8536 r = kvm_x86_ops->hardware_setup();
8537 if (r != 0)
8538 return r;
8539
35181e86
HZ		 8540 if (kvm_has_tsc_control) {
8541 /*
8542 * Make sure the user can only configure tsc_khz values that
8543 * fit into a signed integer.
8544 * A min value is not calculated needed because it will always
8545 * be 1 on all machines.
8546 */
8547 u64 max = min(0x7fffffffULL,
8548 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8549 kvm_max_guest_tsc_khz = max;
8550
ad721883 8551 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8552 }
ad721883 8553
9e9c3fe4
NA		 8554 kvm_init_msr_list();
8555 return 0;
e9b11c17
ZX		 8556}
8557
8558void kvm_arch_hardware_unsetup(void)
8559{
8560 kvm_x86_ops->hardware_unsetup();
8561}
8562
8563void kvm_arch_check_processor_compat(void *rtn)
8564{
8565 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8566}
8567
8568bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8569{
8570 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8571}
8572EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8573
8574bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8575{
8576 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8577}
8578
54e9818f 8579struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8580EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8581
e9b11c17
ZX		 8582int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8583{
8584 struct page *page;
e9b11c17
ZX		 8585 int r;
8586
b2a05fef 8587 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8588 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8589 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8590 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8591 else
a4535290 8592 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8593
8594 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8595 if (!page) {
8596 r = -ENOMEM;
8597 goto fail;
8598 }
ad312c7c 8599 vcpu->arch.pio_data = page_address(page);
e9b11c17 8600
cc578287 8601 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8602
e9b11c17
ZX		 8603 r = kvm_mmu_create(vcpu);
8604 if (r < 0)
8605 goto fail_free_pio_data;
8606
26de7988 8607 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8608 r = kvm_create_lapic(vcpu);
8609 if (r < 0)
8610 goto fail_mmu_destroy;
54e9818f
GN		 8611 } else
8612 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8613
890ca9ae
HY		 8614 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8615 GFP_KERNEL);
8616 if (!vcpu->arch.mce_banks) {
8617 r = -ENOMEM;
443c39bc 8618 goto fail_free_lapic;
890ca9ae
HY		 8619 }
8620 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8621
f1797359
WY		 8622 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8623 r = -ENOMEM;
f5f48ee1 8624 goto fail_free_mce_banks;
f1797359 8625 }
f5f48ee1 8626
0ee6a517 8627 fx_init(vcpu);
66f7b72e 8628
4344ee98 8629 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8630
5a4f55cd
EK		 8631 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8632
74545705
RK		 8633 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8634
af585b92 8635 kvm_async_pf_hash_reset(vcpu);
f5132b01 8636 kvm_pmu_init(vcpu);
af585b92 8637
1c1a9ce9 8638 vcpu->arch.pending_external_vector = -1;
de63ad4c 8639 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8640
5c919412
AS		 8641 kvm_hv_vcpu_init(vcpu);
8642
e9b11c17 8643 return 0;
0ee6a517 8644
f5f48ee1
SY		 8645fail_free_mce_banks:
8646 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8647fail_free_lapic:
8648 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8649fail_mmu_destroy:
8650 kvm_mmu_destroy(vcpu);
8651fail_free_pio_data:
ad312c7c 8652 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8653fail:
8654 return r;
8655}
8656
8657void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8658{
f656ce01
MT		 8659 int idx;
8660
1f4b34f8 8661 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8662 kvm_pmu_destroy(vcpu);
36cb93fd 8663 kfree(vcpu->arch.mce_banks);
e9b11c17 8664 kvm_free_lapic(vcpu);
f656ce01 8665 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8666 kvm_mmu_destroy(vcpu);
f656ce01 8667 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8668 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8669 if (!lapic_in_kernel(vcpu))
54e9818f 8670 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8671}
d19a9cd2 8672
e790d9ef
RK		 8673void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8674{
ae97a3b8 8675 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8676}
8677
e08b9637 8678int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8679{
e08b9637
CO		 8680 if (type)
8681 return -EINVAL;
8682
6ef768fa 8683 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8684 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8685 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8686 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8687 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8688
5550af4d
SY		 8689 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8690 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8691 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8692 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8693 &kvm->arch.irq_sources_bitmap);
5550af4d 8694
038f8c11 8695 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8696 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8697 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8698
108b249c 8699 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8700 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8701
7e44e449 8702 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8703 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8704
cbc0236a 8705 kvm_hv_init_vm(kvm);
0eb05bf2 8706 kvm_page_track_init(kvm);
13d268ca 8707 kvm_mmu_init_vm(kvm);
0eb05bf2 8708
03543133
SS		 8709 if (kvm_x86_ops->vm_init)
8710 return kvm_x86_ops->vm_init(kvm);
8711
d89f5eff 8712 return 0;
d19a9cd2
ZX		 8713}
8714
8715static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8716{
ec7660cc 8717 vcpu_load(vcpu);
d19a9cd2
ZX		 8718 kvm_mmu_unload(vcpu);
8719 vcpu_put(vcpu);
8720}
8721
8722static void kvm_free_vcpus(struct kvm *kvm)
8723{
8724 unsigned int i;
988a2cae 8725 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8726
8727 /*
8728 * Unpin any mmu pages first.
8729 */
af585b92
GN		 8730 kvm_for_each_vcpu(i, vcpu, kvm) {
8731 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8732 kvm_unload_vcpu_mmu(vcpu);
af585b92 8733 }
988a2cae
GN		 8734 kvm_for_each_vcpu(i, vcpu, kvm)
8735 kvm_arch_vcpu_free(vcpu);
8736
8737 mutex_lock(&kvm->lock);
8738 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8739 kvm->vcpus[i] = NULL;
d19a9cd2 8740
988a2cae
GN		 8741 atomic_set(&kvm->online_vcpus, 0);
8742 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8743}
8744
ad8ba2cd
SY		 8745void kvm_arch_sync_events(struct kvm *kvm)
8746{
332967a3 8747 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8748 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8749 kvm_free_pit(kvm);
ad8ba2cd
SY		 8750}
8751
1d8007bd 8752int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8753{
8754 int i, r;
25188b99 8755 unsigned long hva;
f0d648bd
PB		 8756 struct kvm_memslots *slots = kvm_memslots(kvm);
8757 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8758
8759 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8760 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8761 return -EINVAL;
9da0e4d5 8762
f0d648bd
PB		 8763 slot = id_to_memslot(slots, id);
8764 if (size) {
b21629da 8765 if (slot->npages)
f0d648bd
PB		 8766 return -EEXIST;
8767
8768 /*
8769 * MAP_SHARED to prevent internal slot pages from being moved
8770 * by fork()/COW.
8771 */
8772 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8773 MAP_SHARED | MAP_ANONYMOUS, 0);
8774 if (IS_ERR((void *)hva))
8775 return PTR_ERR((void *)hva);
8776 } else {
8777 if (!slot->npages)
8778 return 0;
8779
8780 hva = 0;
8781 }
8782
8783 old = *slot;
9da0e4d5 8784 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8785 struct kvm_userspace_memory_region m;
9da0e4d5 8786
1d8007bd
PB		 8787 m.slot = id | (i << 16);
8788 m.flags = 0;
8789 m.guest_phys_addr = gpa;
f0d648bd 8790 m.userspace_addr = hva;
1d8007bd 8791 m.memory_size = size;
9da0e4d5
PB		 8792 r = __kvm_set_memory_region(kvm, &m);
8793 if (r < 0)
8794 return r;
8795 }
8796
103c763c
EB		 8797 if (!size)
8798 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8799
9da0e4d5
PB		 8800 return 0;
8801}
8802EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8803
1d8007bd 8804int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8805{
8806 int r;
8807
8808 mutex_lock(&kvm->slots_lock);
1d8007bd 8809 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8810 mutex_unlock(&kvm->slots_lock);
8811
8812 return r;
8813}
8814EXPORT_SYMBOL_GPL(x86_set_memory_region);
8815
d19a9cd2
ZX		 8816void kvm_arch_destroy_vm(struct kvm *kvm)
8817{
27469d29
AH		 8818 if (current->mm == kvm->mm) {
8819 /*
8820 * Free memory regions allocated on behalf of userspace,
8821 * unless the the memory map has changed due to process exit
8822 * or fd copying.
8823 */
1d8007bd
PB		 8824 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8825 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8826 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8827 }
03543133
SS		 8828 if (kvm_x86_ops->vm_destroy)
8829 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8830 kvm_pic_destroy(kvm);
8831 kvm_ioapic_destroy(kvm);
d19a9cd2 8832 kvm_free_vcpus(kvm);
af1bae54 8833 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8834 kvm_mmu_uninit_vm(kvm);
2beb6dad 8835 kvm_page_track_cleanup(kvm);
cbc0236a 8836 kvm_hv_destroy_vm(kvm);
d19a9cd2 8837}
0de10343 8838
5587027c 8839void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8840 struct kvm_memory_slot *dont)
8841{
8842 int i;
8843
d89cc617
TY		 8844 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8845 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8846 kvfree(free->arch.rmap[i]);
d89cc617 8847 free->arch.rmap[i] = NULL;
77d11309 8848 }
d89cc617
TY		 8849 if (i == 0)
8850 continue;
8851
8852 if (!dont || free->arch.lpage_info[i - 1] !=
8853 dont->arch.lpage_info[i - 1]) {
548ef284 8854 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8855 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8856 }
8857 }
21ebbeda
XG		 8858
8859 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8860}
8861
5587027c
AK		 8862int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8863 unsigned long npages)
db3fe4eb
TY		 8864{
8865 int i;
8866
d89cc617 8867 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8868 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8869 unsigned long ugfn;
8870 int lpages;
d89cc617 8871 int level = i + 1;
db3fe4eb
TY		 8872
8873 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8874 slot->base_gfn, level) + 1;
8875
d89cc617 8876 slot->arch.rmap[i] =
a7c3e901 8877 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8878 if (!slot->arch.rmap[i])
77d11309 8879 goto out_free;
d89cc617
TY		 8880 if (i == 0)
8881 continue;
77d11309 8882
a7c3e901 8883 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8884 if (!linfo)
db3fe4eb
TY		 8885 goto out_free;
8886
92f94f1e
XG		 8887 slot->arch.lpage_info[i - 1] = linfo;
8888
db3fe4eb 8889 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8890 linfo[0].disallow_lpage = 1;
db3fe4eb 8891 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8892 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8893 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8894 /*
8895 * If the gfn and userspace address are not aligned wrt each
8896 * other, or if explicitly asked to, disable large page
8897 * support for this slot
8898 */
8899 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8900 !kvm_largepages_enabled()) {
8901 unsigned long j;
8902
8903 for (j = 0; j < lpages; ++j)
92f94f1e 8904 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8905 }
8906 }
8907
21ebbeda
XG		 8908 if (kvm_page_track_create_memslot(slot, npages))
8909 goto out_free;
8910
db3fe4eb
TY		 8911 return 0;
8912
8913out_free:
d89cc617 8914 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8915 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8916 slot->arch.rmap[i] = NULL;
8917 if (i == 0)
8918 continue;
8919
548ef284 8920 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8921 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8922 }
8923 return -ENOMEM;
8924}
8925
15f46015 8926void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8927{
e6dff7d1
TY		 8928 /*
8929 * memslots->generation has been incremented.
8930 * mmio generation may have reached its maximum value.
8931 */
54bf36aa 8932 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8933}
8934
f7784b8e
MT		 8935int kvm_arch_prepare_memory_region(struct kvm *kvm,
8936 struct kvm_memory_slot *memslot,
09170a49 8937 const struct kvm_userspace_memory_region *mem,
7b6195a9 8938 enum kvm_mr_change change)
0de10343 8939{
f7784b8e
MT		 8940 return 0;
8941}
8942
88178fd4
KH		 8943static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8944 struct kvm_memory_slot *new)
8945{
8946 /* Still write protect RO slot */
8947 if (new->flags & KVM_MEM_READONLY) {
8948 kvm_mmu_slot_remove_write_access(kvm, new);
8949 return;
8950 }
8951
8952 /*
8953 * Call kvm_x86_ops dirty logging hooks when they are valid.
8954 *
8955 * kvm_x86_ops->slot_disable_log_dirty is called when:
8956 *
8957 * - KVM_MR_CREATE with dirty logging is disabled
8958 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8959 *
8960 * The reason is, in case of PML, we need to set D-bit for any slots
8961 * with dirty logging disabled in order to eliminate unnecessary GPA
8962 * logging in PML buffer (and potential PML buffer full VMEXT). This
8963 * guarantees leaving PML enabled during guest's lifetime won't have
8964 * any additonal overhead from PML when guest is running with dirty
8965 * logging disabled for memory slots.
8966 *
8967 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8968 * to dirty logging mode.
8969 *
8970 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8971 *
8972 * In case of write protect:
8973 *
8974 * Write protect all pages for dirty logging.
8975 *
8976 * All the sptes including the large sptes which point to this
8977 * slot are set to readonly. We can not create any new large
8978 * spte on this slot until the end of the logging.
8979 *
8980 * See the comments in fast_page_fault().
8981 */
8982 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8983 if (kvm_x86_ops->slot_enable_log_dirty)
8984 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8985 else
8986 kvm_mmu_slot_remove_write_access(kvm, new);
8987 } else {
8988 if (kvm_x86_ops->slot_disable_log_dirty)
8989 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8990 }
8991}
8992
f7784b8e 8993void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8994 const struct kvm_userspace_memory_region *mem,
8482644a 8995 const struct kvm_memory_slot *old,
f36f3f28 8996 const struct kvm_memory_slot *new,
8482644a 8997 enum kvm_mr_change change)
f7784b8e 8998{
8482644a 8999 int nr_mmu_pages = 0;
f7784b8e 9000
48c0e4e9
XG		 9001 if (!kvm->arch.n_requested_mmu_pages)
9002 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9003
48c0e4e9 9004 if (nr_mmu_pages)
0de10343 9005 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9006
3ea3b7fa
WL		 9007 /*
9008 * Dirty logging tracks sptes in 4k granularity, meaning that large
9009 * sptes have to be split. If live migration is successful, the guest
9010 * in the source machine will be destroyed and large sptes will be
9011 * created in the destination. However, if the guest continues to run
9012 * in the source machine (for example if live migration fails), small
9013 * sptes will remain around and cause bad performance.
9014 *
9015 * Scan sptes if dirty logging has been stopped, dropping those
9016 * which can be collapsed into a single large-page spte. Later
9017 * page faults will create the large-page sptes.
9018 */
9019 if ((change != KVM_MR_DELETE) &&
9020 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9021 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9022 kvm_mmu_zap_collapsible_sptes(kvm, new);
9023
c972f3b1 9024 /*
88178fd4 9025 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9026 *
88178fd4
KH		 9027 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9028 * been zapped so no dirty logging staff is needed for old slot. For
9029 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9030 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9031 *
9032 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9033 */
88178fd4 9034 if (change != KVM_MR_DELETE)
f36f3f28 9035 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9036}
1d737c8a 9037
2df72e9b 9038void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9039{
6ca18b69 9040 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9041}
9042
2df72e9b
MT		 9043void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9044 struct kvm_memory_slot *slot)
9045{
ae7cd873 9046 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9047}
9048
5d9bc648
PB		 9049static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9050{
9051 if (!list_empty_careful(&vcpu->async_pf.done))
9052 return true;
9053
9054 if (kvm_apic_has_events(vcpu))
9055 return true;
9056
9057 if (vcpu->arch.pv.pv_unhalted)
9058 return true;
9059
a5f01f8e
WL		 9060 if (vcpu->arch.exception.pending)
9061 return true;
9062
47a66eed
Z		 9063 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9064 (vcpu->arch.nmi_pending &&
9065 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9066 return true;
9067
47a66eed
Z		 9068 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9069 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9070 return true;
9071
5d9bc648
PB		 9072 if (kvm_arch_interrupt_allowed(vcpu) &&
9073 kvm_cpu_has_interrupt(vcpu))
9074 return true;
9075
1f4b34f8
AS		 9076 if (kvm_hv_has_stimer_pending(vcpu))
9077 return true;
9078
5d9bc648
PB		 9079 return false;
9080}
9081
1d737c8a
ZX		 9082int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9083{
5d9bc648 9084 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9085}
5736199a 9086
199b5763
LM		 9087bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9088{
de63ad4c 9089 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9090}
9091
b6d33834 9092int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9093{
b6d33834 9094 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9095}
78646121
GN		 9096
9097int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9098{
9099 return kvm_x86_ops->interrupt_allowed(vcpu);
9100}
229456fc 9101
82b32774 9102unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9103{
82b32774
NA		 9104 if (is_64_bit_mode(vcpu))
9105 return kvm_rip_read(vcpu);
9106 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9107 kvm_rip_read(vcpu));
9108}
9109EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9110
82b32774
NA		 9111bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9112{
9113 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9114}
9115EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9116
94fe45da
JK		 9117unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9118{
9119 unsigned long rflags;
9120
9121 rflags = kvm_x86_ops->get_rflags(vcpu);
9122 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9123 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9124 return rflags;
9125}
9126EXPORT_SYMBOL_GPL(kvm_get_rflags);
9127
6addfc42 9128static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9129{
9130 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9131 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9132 rflags |= X86_EFLAGS_TF;
94fe45da 9133 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9134}
9135
9136void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9137{
9138 __kvm_set_rflags(vcpu, rflags);
3842d135 9139 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9140}
9141EXPORT_SYMBOL_GPL(kvm_set_rflags);
9142
56028d08
GN		 9143void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9144{
9145 int r;
9146
fb67e14f 9147 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 9148 work->wakeup_all)
56028d08
GN		 9149 return;
9150
9151 r = kvm_mmu_reload(vcpu);
9152 if (unlikely(r))
9153 return;
9154
fb67e14f
XG		 9155 if (!vcpu->arch.mmu.direct_map &&
9156 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9157 return;
9158
56028d08
GN		 9159 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9160}
9161
af585b92
GN		 9162static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9163{
9164 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9165}
9166
9167static inline u32 kvm_async_pf_next_probe(u32 key)
9168{
9169 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9170}
9171
9172static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9173{
9174 u32 key = kvm_async_pf_hash_fn(gfn);
9175
9176 while (vcpu->arch.apf.gfns[key] != ~0)
9177 key = kvm_async_pf_next_probe(key);
9178
9179 vcpu->arch.apf.gfns[key] = gfn;
9180}
9181
9182static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9183{
9184 int i;
9185 u32 key = kvm_async_pf_hash_fn(gfn);
9186
9187 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9188 (vcpu->arch.apf.gfns[key] != gfn &&
9189 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9190 key = kvm_async_pf_next_probe(key);
9191
9192 return key;
9193}
9194
9195bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9196{
9197 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9198}
9199
9200static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9201{
9202 u32 i, j, k;
9203
9204 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9205 while (true) {
9206 vcpu->arch.apf.gfns[i] = ~0;
9207 do {
9208 j = kvm_async_pf_next_probe(j);
9209 if (vcpu->arch.apf.gfns[j] == ~0)
9210 return;
9211 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9212 /*
9213 * k lies cyclically in ]i,j]
9214 * | i.k.j |
9215 * |....j i.k.| or |.k..j i...|
9216 */
9217 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9218 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9219 i = j;
9220 }
9221}
9222
7c90705b
GN		 9223static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9224{
4e335d9e
PB		 9225
9226 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9227 sizeof(val));
7c90705b
GN		 9228}
9229
9a6e7c39
WL		 9230static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9231{
9232
9233 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9234 sizeof(u32));
9235}
9236
af585b92
GN		 9237void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9238 struct kvm_async_pf *work)
9239{
6389ee94
AK		 9240 struct x86_exception fault;
9241
7c90705b 9242 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9243 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9244
9245 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9246 (vcpu->arch.apf.send_user_only &&
9247 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9248 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9249 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9250 fault.vector = PF_VECTOR;
9251 fault.error_code_valid = true;
9252 fault.error_code = 0;
9253 fault.nested_page_fault = false;
9254 fault.address = work->arch.token;
adfe20fb 9255 fault.async_page_fault = true;
6389ee94 9256 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9257 }
af585b92
GN		 9258}
9259
9260void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9261 struct kvm_async_pf *work)
9262{
6389ee94 9263 struct x86_exception fault;
9a6e7c39 9264 u32 val;
6389ee94 9265
f2e10669 9266 if (work->wakeup_all)
7c90705b
GN		 9267 work->arch.token = ~0; /* broadcast wakeup */
9268 else
9269 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9270 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9271
9a6e7c39
WL		 9272 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9273 !apf_get_user(vcpu, &val)) {
9274 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9275 vcpu->arch.exception.pending &&
9276 vcpu->arch.exception.nr == PF_VECTOR &&
9277 !apf_put_user(vcpu, 0)) {
9278 vcpu->arch.exception.injected = false;
9279 vcpu->arch.exception.pending = false;
9280 vcpu->arch.exception.nr = 0;
9281 vcpu->arch.exception.has_error_code = false;
9282 vcpu->arch.exception.error_code = 0;
9283 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9284 fault.vector = PF_VECTOR;
9285 fault.error_code_valid = true;
9286 fault.error_code = 0;
9287 fault.nested_page_fault = false;
9288 fault.address = work->arch.token;
9289 fault.async_page_fault = true;
9290 kvm_inject_page_fault(vcpu, &fault);
9291 }
7c90705b 9292 }
e6d53e3b 9293 vcpu->arch.apf.halted = false;
a4fa1635 9294 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9295}
9296
9297bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9298{
9299 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9300 return true;
9301 else
9bc1f09f 9302 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9303}
9304
5544eb9b
PB		 9305void kvm_arch_start_assignment(struct kvm *kvm)
9306{
9307 atomic_inc(&kvm->arch.assigned_device_count);
9308}
9309EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9310
9311void kvm_arch_end_assignment(struct kvm *kvm)
9312{
9313 atomic_dec(&kvm->arch.assigned_device_count);
9314}
9315EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9316
9317bool kvm_arch_has_assigned_device(struct kvm *kvm)
9318{
9319 return atomic_read(&kvm->arch.assigned_device_count);
9320}
9321EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9322
e0f0bbc5
AW		 9323void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9324{
9325 atomic_inc(&kvm->arch.noncoherent_dma_count);
9326}
9327EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9328
9329void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9330{
9331 atomic_dec(&kvm->arch.noncoherent_dma_count);
9332}
9333EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9334
9335bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9336{
9337 return atomic_read(&kvm->arch.noncoherent_dma_count);
9338}
9339EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9340
14717e20
AW		 9341bool kvm_arch_has_irq_bypass(void)
9342{
9343 return kvm_x86_ops->update_pi_irte != NULL;
9344}
9345
87276880
FW		 9346int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9347 struct irq_bypass_producer *prod)
9348{
9349 struct kvm_kernel_irqfd *irqfd =
9350 container_of(cons, struct kvm_kernel_irqfd, consumer);
9351
14717e20 9352 irqfd->producer = prod;
87276880 9353
14717e20
AW		 9354 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9355 prod->irq, irqfd->gsi, 1);
87276880
FW		 9356}
9357
9358void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9359 struct irq_bypass_producer *prod)
9360{
9361 int ret;
9362 struct kvm_kernel_irqfd *irqfd =
9363 container_of(cons, struct kvm_kernel_irqfd, consumer);
9364
87276880
FW		 9365 WARN_ON(irqfd->producer != prod);
9366 irqfd->producer = NULL;
9367
9368 /*
9369 * When producer of consumer is unregistered, we change back to
9370 * remapped mode, so we can re-use the current implementation
bb3541f1 9371 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9372 * int this case doesn't want to receive the interrupts.
9373 */
9374 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9375 if (ret)
9376 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9377 " fails: %d\n", irqfd->consumer.token, ret);
9378}
9379
9380int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9381 uint32_t guest_irq, bool set)
9382{
9383 if (!kvm_x86_ops->update_pi_irte)
9384 return -EINVAL;
9385
9386 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9387}
9388
52004014
FW		 9389bool kvm_vector_hashing_enabled(void)
9390{
9391 return vector_hashing;
9392}
9393EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9394
229456fc 9395EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9396EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9397EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9398EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9399EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9400EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9401EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9402EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9403EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9404EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9405EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9406EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9407EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9408EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9409EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9410EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9411EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9412EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9413EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)