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KVM: SVM: Implement VIRT_SPEC_CTRL support for SSBD
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
9ed96e87
MT		 117unsigned int min_timer_period_us = 500;
118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
141
52004014
FW		 142static bool __read_mostly vector_hashing = true;
143module_param(vector_hashing, bool, S_IRUGO);
144
c4ae60e4
LA		 145bool __read_mostly enable_vmware_backdoor = false;
146module_param(enable_vmware_backdoor, bool, S_IRUGO);
147EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
148
6c86eedc
WL		 149static bool __read_mostly force_emulation_prefix = false;
150module_param(force_emulation_prefix, bool, S_IRUGO);
151
18863bdd
AK		 152#define KVM_NR_SHARED_MSRS 16
153
154struct kvm_shared_msrs_global {
155 int nr;
2bf78fa7 156 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 157};
158
159struct kvm_shared_msrs {
160 struct user_return_notifier urn;
161 bool registered;
2bf78fa7
SY		 162 struct kvm_shared_msr_values {
163 u64 host;
164 u64 curr;
165 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 166};
167
168static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 169static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 170
417bc304 171struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 172 { "pf_fixed", VCPU_STAT(pf_fixed) },
173 { "pf_guest", VCPU_STAT(pf_guest) },
174 { "tlb_flush", VCPU_STAT(tlb_flush) },
175 { "invlpg", VCPU_STAT(invlpg) },
176 { "exits", VCPU_STAT(exits) },
177 { "io_exits", VCPU_STAT(io_exits) },
178 { "mmio_exits", VCPU_STAT(mmio_exits) },
179 { "signal_exits", VCPU_STAT(signal_exits) },
180 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 181 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 182 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 183 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 184 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 185 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 186 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 187 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 188 { "request_irq", VCPU_STAT(request_irq_exits) },
189 { "irq_exits", VCPU_STAT(irq_exits) },
190 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 191 { "fpu_reload", VCPU_STAT(fpu_reload) },
192 { "insn_emulation", VCPU_STAT(insn_emulation) },
193 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 194 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 195 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 196 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 197 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
198 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
199 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
200 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
201 { "mmu_flooded", VM_STAT(mmu_flooded) },
202 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 203 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 204 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 205 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 206 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 207 { "max_mmu_page_hash_collisions",
208 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 209 { NULL }
210};
211
2acf923e
DC		 212u64 __read_mostly host_xcr0;
213
b6785def 214static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 215
af585b92
GN		 216static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
217{
218 int i;
219 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
220 vcpu->arch.apf.gfns[i] = ~0;
221}
222
18863bdd
AK		 223static void kvm_on_user_return(struct user_return_notifier *urn)
224{
225 unsigned slot;
18863bdd
AK		 226 struct kvm_shared_msrs *locals
227 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 228 struct kvm_shared_msr_values *values;
1650b4eb
IA		 229 unsigned long flags;
230
231 /*
232 * Disabling irqs at this point since the following code could be
233 * interrupted and executed through kvm_arch_hardware_disable()
234 */
235 local_irq_save(flags);
236 if (locals->registered) {
237 locals->registered = false;
238 user_return_notifier_unregister(urn);
239 }
240 local_irq_restore(flags);
18863bdd 241 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 242 values = &locals->values[slot];
243 if (values->host != values->curr) {
244 wrmsrl(shared_msrs_global.msrs[slot], values->host);
245 values->curr = values->host;
18863bdd
AK		 246 }
247 }
18863bdd
AK		 248}
249
2bf78fa7 250static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 251{
18863bdd 252 u64 value;
013f6a5d
MT		 253 unsigned int cpu = smp_processor_id();
254 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 255
2bf78fa7
SY		 256 /* only read, and nobody should modify it at this time,
257 * so don't need lock */
258 if (slot >= shared_msrs_global.nr) {
259 printk(KERN_ERR "kvm: invalid MSR slot!");
260 return;
261 }
262 rdmsrl_safe(msr, &value);
263 smsr->values[slot].host = value;
264 smsr->values[slot].curr = value;
265}
266
267void kvm_define_shared_msr(unsigned slot, u32 msr)
268{
0123be42 269 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 270 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 271 if (slot >= shared_msrs_global.nr)
272 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 273}
274EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
275
276static void kvm_shared_msr_cpu_online(void)
277{
278 unsigned i;
18863bdd
AK		 279
280 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 281 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 282}
283
8b3c3104 284int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 285{
013f6a5d
MT		 286 unsigned int cpu = smp_processor_id();
287 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 288 int err;
18863bdd 289
2bf78fa7 290 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 291 return 0;
2bf78fa7 292 smsr->values[slot].curr = value;
8b3c3104
AH		 293 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
294 if (err)
295 return 1;
296
18863bdd
AK		 297 if (!smsr->registered) {
298 smsr->urn.on_user_return = kvm_on_user_return;
299 user_return_notifier_register(&smsr->urn);
300 smsr->registered = true;
301 }
8b3c3104 302 return 0;
18863bdd
AK		 303}
304EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
305
13a34e06 306static void drop_user_return_notifiers(void)
3548bab5 307{
013f6a5d
MT		 308 unsigned int cpu = smp_processor_id();
309 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 310
311 if (smsr->registered)
312 kvm_on_user_return(&smsr->urn);
313}
314
6866b83e
CO		 315u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
316{
8a5a87d9 317 return vcpu->arch.apic_base;
6866b83e
CO		 318}
319EXPORT_SYMBOL_GPL(kvm_get_apic_base);
320
58cb628d
JK		 321int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
322{
323 u64 old_state = vcpu->arch.apic_base &
324 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
325 u64 new_state = msr_info->data &
326 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 327 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
328 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 329
d3802286
JM		 330 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
331 return 1;
58cb628d 332 if (!msr_info->host_initiated &&
d3802286 333 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 334 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
335 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
336 old_state == 0)))
337 return 1;
338
339 kvm_lapic_set_base(vcpu, msr_info->data);
340 return 0;
6866b83e
CO		 341}
342EXPORT_SYMBOL_GPL(kvm_set_apic_base);
343
2605fc21 344asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 345{
346 /* Fault while not rebooting. We want the trace. */
347 BUG();
348}
349EXPORT_SYMBOL_GPL(kvm_spurious_fault);
350
3fd28fce
ED		 351#define EXCPT_BENIGN 0
352#define EXCPT_CONTRIBUTORY 1
353#define EXCPT_PF 2
354
355static int exception_class(int vector)
356{
357 switch (vector) {
358 case PF_VECTOR:
359 return EXCPT_PF;
360 case DE_VECTOR:
361 case TS_VECTOR:
362 case NP_VECTOR:
363 case SS_VECTOR:
364 case GP_VECTOR:
365 return EXCPT_CONTRIBUTORY;
366 default:
367 break;
368 }
369 return EXCPT_BENIGN;
370}
371
d6e8c854
NA		 372#define EXCPT_FAULT 0
373#define EXCPT_TRAP 1
374#define EXCPT_ABORT 2
375#define EXCPT_INTERRUPT 3
376
377static int exception_type(int vector)
378{
379 unsigned int mask;
380
381 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
382 return EXCPT_INTERRUPT;
383
384 mask = 1 << vector;
385
386 /* #DB is trap, as instruction watchpoints are handled elsewhere */
387 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
388 return EXCPT_TRAP;
389
390 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
391 return EXCPT_ABORT;
392
393 /* Reserved exceptions will result in fault */
394 return EXCPT_FAULT;
395}
396
3fd28fce 397static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 398 unsigned nr, bool has_error, u32 error_code,
399 bool reinject)
3fd28fce
ED		 400{
401 u32 prev_nr;
402 int class1, class2;
403
3842d135
AK		 404 kvm_make_request(KVM_REQ_EVENT, vcpu);
405
664f8e26 406 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 407 queue:
3ffb2468
NA		 408 if (has_error && !is_protmode(vcpu))
409 has_error = false;
664f8e26
WL		 410 if (reinject) {
411 /*
412 * On vmentry, vcpu->arch.exception.pending is only
413 * true if an event injection was blocked by
414 * nested_run_pending. In that case, however,
415 * vcpu_enter_guest requests an immediate exit,
416 * and the guest shouldn't proceed far enough to
417 * need reinjection.
418 */
419 WARN_ON_ONCE(vcpu->arch.exception.pending);
420 vcpu->arch.exception.injected = true;
421 } else {
422 vcpu->arch.exception.pending = true;
423 vcpu->arch.exception.injected = false;
424 }
3fd28fce
ED		 425 vcpu->arch.exception.has_error_code = has_error;
426 vcpu->arch.exception.nr = nr;
427 vcpu->arch.exception.error_code = error_code;
428 return;
429 }
430
431 /* to check exception */
432 prev_nr = vcpu->arch.exception.nr;
433 if (prev_nr == DF_VECTOR) {
434 /* triple fault -> shutdown */
a8eeb04a 435 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 436 return;
437 }
438 class1 = exception_class(prev_nr);
439 class2 = exception_class(nr);
440 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
441 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 442 /*
443 * Generate double fault per SDM Table 5-5. Set
444 * exception.pending = true so that the double fault
445 * can trigger a nested vmexit.
446 */
3fd28fce 447 vcpu->arch.exception.pending = true;
664f8e26 448 vcpu->arch.exception.injected = false;
3fd28fce
ED		 449 vcpu->arch.exception.has_error_code = true;
450 vcpu->arch.exception.nr = DF_VECTOR;
451 vcpu->arch.exception.error_code = 0;
452 } else
453 /* replace previous exception with a new one in a hope
454 that instruction re-execution will regenerate lost
455 exception */
456 goto queue;
457}
458
298101da
AK		 459void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
460{
ce7ddec4 461 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 462}
463EXPORT_SYMBOL_GPL(kvm_queue_exception);
464
ce7ddec4
JR		 465void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
466{
467 kvm_multiple_exception(vcpu, nr, false, 0, true);
468}
469EXPORT_SYMBOL_GPL(kvm_requeue_exception);
470
6affcbed 471int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 472{
db8fcefa
AP		 473 if (err)
474 kvm_inject_gp(vcpu, 0);
475 else
6affcbed
KH		 476 return kvm_skip_emulated_instruction(vcpu);
477
478 return 1;
db8fcefa
AP		 479}
480EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 481
6389ee94 482void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 483{
484 ++vcpu->stat.pf_guest;
adfe20fb
WL		 485 vcpu->arch.exception.nested_apf =
486 is_guest_mode(vcpu) && fault->async_page_fault;
487 if (vcpu->arch.exception.nested_apf)
488 vcpu->arch.apf.nested_apf_token = fault->address;
489 else
490 vcpu->arch.cr2 = fault->address;
6389ee94 491 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 492}
27d6c865 493EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 494
ef54bcfe 495static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 496{
6389ee94
AK		 497 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
498 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 499 else
6389ee94 500 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 501
502 return fault->nested_page_fault;
d4f8cf66
JR		 503}
504
3419ffc8
SY		 505void kvm_inject_nmi(struct kvm_vcpu *vcpu)
506{
7460fb4a
AK		 507 atomic_inc(&vcpu->arch.nmi_queued);
508 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 509}
510EXPORT_SYMBOL_GPL(kvm_inject_nmi);
511
298101da
AK		 512void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
513{
ce7ddec4 514 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 515}
516EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
517
ce7ddec4
JR		 518void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
519{
520 kvm_multiple_exception(vcpu, nr, true, error_code, true);
521}
522EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
523
0a79b009
AK		 524/*
525 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
526 * a #GP and return false.
527 */
528bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 529{
0a79b009
AK		 530 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
531 return true;
532 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
533 return false;
298101da 534}
0a79b009 535EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 536
16f8a6f9
NA		 537bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
538{
539 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
540 return true;
541
542 kvm_queue_exception(vcpu, UD_VECTOR);
543 return false;
544}
545EXPORT_SYMBOL_GPL(kvm_require_dr);
546
ec92fe44
JR		 547/*
548 * This function will be used to read from the physical memory of the currently
54bf36aa 549 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 550 * can read from guest physical or from the guest's guest physical memory.
551 */
552int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
553 gfn_t ngfn, void *data, int offset, int len,
554 u32 access)
555{
54987b7a 556 struct x86_exception exception;
ec92fe44
JR		 557 gfn_t real_gfn;
558 gpa_t ngpa;
559
560 ngpa = gfn_to_gpa(ngfn);
54987b7a 561 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 562 if (real_gfn == UNMAPPED_GVA)
563 return -EFAULT;
564
565 real_gfn = gpa_to_gfn(real_gfn);
566
54bf36aa 567 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 568}
569EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
570
69b0049a 571static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 572 void *data, int offset, int len, u32 access)
573{
574 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
575 data, offset, len, access);
576}
577
a03490ed
CO		 578/*
579 * Load the pae pdptrs. Return true is they are all valid.
580 */
ff03a073 581int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 582{
583 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
584 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
585 int i;
586 int ret;
ff03a073 587 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 588
ff03a073
JR		 589 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
590 offset * sizeof(u64), sizeof(pdpte),
591 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 592 if (ret < 0) {
593 ret = 0;
594 goto out;
595 }
596 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 597 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 598 (pdpte[i] &
599 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 600 ret = 0;
601 goto out;
602 }
603 }
604 ret = 1;
605
ff03a073 606 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 607 __set_bit(VCPU_EXREG_PDPTR,
608 (unsigned long *)&vcpu->arch.regs_avail);
609 __set_bit(VCPU_EXREG_PDPTR,
610 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 611out:
a03490ed
CO		 612
613 return ret;
614}
cc4b6871 615EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 616
9ed38ffa 617bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 618{
ff03a073 619 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 620 bool changed = true;
3d06b8bf
JR		 621 int offset;
622 gfn_t gfn;
d835dfec
AK		 623 int r;
624
625 if (is_long_mode(vcpu) || !is_pae(vcpu))
626 return false;
627
6de4f3ad
AK		 628 if (!test_bit(VCPU_EXREG_PDPTR,
629 (unsigned long *)&vcpu->arch.regs_avail))
630 return true;
631
a512177e
PB		 632 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
633 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 634 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
635 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 636 if (r < 0)
637 goto out;
ff03a073 638 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 639out:
d835dfec
AK		 640
641 return changed;
642}
9ed38ffa 643EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 644
49a9b07e 645int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 646{
aad82703 647 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 648 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 649
f9a48e6a
AK		 650 cr0 |= X86_CR0_ET;
651
ab344828 652#ifdef CONFIG_X86_64
0f12244f
GN		 653 if (cr0 & 0xffffffff00000000UL)
654 return 1;
ab344828
GN		 655#endif
656
657 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 658
0f12244f
GN		 659 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
660 return 1;
a03490ed 661
0f12244f
GN		 662 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
663 return 1;
a03490ed
CO		 664
665 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
666#ifdef CONFIG_X86_64
f6801dff 667 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 668 int cs_db, cs_l;
669
0f12244f
GN		 670 if (!is_pae(vcpu))
671 return 1;
a03490ed 672 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 673 if (cs_l)
674 return 1;
a03490ed
CO		 675 } else
676#endif
ff03a073 677 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 678 kvm_read_cr3(vcpu)))
0f12244f 679 return 1;
a03490ed
CO		 680 }
681
ad756a16
MJ		 682 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
683 return 1;
684
a03490ed 685 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 686
d170c419 687 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 688 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 689 kvm_async_pf_hash_reset(vcpu);
690 }
e5f3f027 691
aad82703
SY		 692 if ((cr0 ^ old_cr0) & update_bits)
693 kvm_mmu_reset_context(vcpu);
b18d5431 694
879ae188
LE		 695 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
696 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
697 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 698 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
699
0f12244f
GN		 700 return 0;
701}
2d3ad1f4 702EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 703
2d3ad1f4 704void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 705{
49a9b07e 706 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 707}
2d3ad1f4 708EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 709
42bdf991
MT		 710static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
711{
712 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
713 !vcpu->guest_xcr0_loaded) {
714 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 715 if (vcpu->arch.xcr0 != host_xcr0)
716 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 717 vcpu->guest_xcr0_loaded = 1;
718 }
719}
720
721static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
722{
723 if (vcpu->guest_xcr0_loaded) {
724 if (vcpu->arch.xcr0 != host_xcr0)
725 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
726 vcpu->guest_xcr0_loaded = 0;
727 }
728}
729
69b0049a 730static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 731{
56c103ec
LJ		 732 u64 xcr0 = xcr;
733 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 734 u64 valid_bits;
2acf923e
DC		 735
736 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
737 if (index != XCR_XFEATURE_ENABLED_MASK)
738 return 1;
d91cab78 739 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 740 return 1;
d91cab78 741 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 742 return 1;
46c34cb0
PB		 743
744 /*
745 * Do not allow the guest to set bits that we do not support
746 * saving. However, xcr0 bit 0 is always set, even if the
747 * emulated CPU does not support XSAVE (see fx_init).
748 */
d91cab78 749 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 750 if (xcr0 & ~valid_bits)
2acf923e 751 return 1;
46c34cb0 752
d91cab78
DH		 753 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
754 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 755 return 1;
756
d91cab78
DH		 757 if (xcr0 & XFEATURE_MASK_AVX512) {
758 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 759 return 1;
d91cab78 760 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 761 return 1;
762 }
2acf923e 763 vcpu->arch.xcr0 = xcr0;
56c103ec 764
d91cab78 765 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 766 kvm_update_cpuid(vcpu);
2acf923e
DC		 767 return 0;
768}
769
770int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
771{
764bcbc5
Z		 772 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
773 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 774 kvm_inject_gp(vcpu, 0);
775 return 1;
776 }
777 return 0;
778}
779EXPORT_SYMBOL_GPL(kvm_set_xcr);
780
a83b29c6 781int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 782{
fc78f519 783 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 784 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 785 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 786
0f12244f
GN		 787 if (cr4 & CR4_RESERVED_BITS)
788 return 1;
a03490ed 789
d6321d49 790 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 791 return 1;
792
d6321d49 793 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 794 return 1;
795
d6321d49 796 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 797 return 1;
798
d6321d49 799 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 800 return 1;
801
d6321d49 802 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 803 return 1;
804
fd8cb433 805 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 806 return 1;
807
ae3e61e1
PB		 808 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
809 return 1;
810
a03490ed 811 if (is_long_mode(vcpu)) {
0f12244f
GN		 812 if (!(cr4 & X86_CR4_PAE))
813 return 1;
a2edf57f
AK		 814 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
815 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 816 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
817 kvm_read_cr3(vcpu)))
0f12244f
GN		 818 return 1;
819
ad756a16 820 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 821 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 822 return 1;
823
824 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
825 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
826 return 1;
827 }
828
5e1746d6 829 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 830 return 1;
a03490ed 831
ad756a16
MJ		 832 if (((cr4 ^ old_cr4) & pdptr_bits) ||
833 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 834 kvm_mmu_reset_context(vcpu);
0f12244f 835
b9baba86 836 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 837 kvm_update_cpuid(vcpu);
2acf923e 838
0f12244f
GN		 839 return 0;
840}
2d3ad1f4 841EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 842
2390218b 843int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 844{
ac146235 845#ifdef CONFIG_X86_64
9d88fca7 846 cr3 &= ~CR3_PCID_INVD;
ac146235 847#endif
9d88fca7 848
9f8fe504 849 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 850 kvm_mmu_sync_roots(vcpu);
77c3913b 851 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 852 return 0;
d835dfec
AK		 853 }
854
d1cd3ce9
YZ		 855 if (is_long_mode(vcpu) &&
856 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
857 return 1;
858 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 859 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 860 return 1;
a03490ed 861
0f12244f 862 vcpu->arch.cr3 = cr3;
aff48baa 863 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 864 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 865 return 0;
866}
2d3ad1f4 867EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 868
eea1cff9 869int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 870{
0f12244f
GN		 871 if (cr8 & CR8_RESERVED_BITS)
872 return 1;
35754c98 873 if (lapic_in_kernel(vcpu))
a03490ed
CO		 874 kvm_lapic_set_tpr(vcpu, cr8);
875 else
ad312c7c 876 vcpu->arch.cr8 = cr8;
0f12244f
GN		 877 return 0;
878}
2d3ad1f4 879EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 880
2d3ad1f4 881unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 882{
35754c98 883 if (lapic_in_kernel(vcpu))
a03490ed
CO		 884 return kvm_lapic_get_cr8(vcpu);
885 else
ad312c7c 886 return vcpu->arch.cr8;
a03490ed 887}
2d3ad1f4 888EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 889
ae561ede
NA		 890static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
891{
892 int i;
893
894 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
895 for (i = 0; i < KVM_NR_DB_REGS; i++)
896 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
897 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
898 }
899}
900
73aaf249
JK		 901static void kvm_update_dr6(struct kvm_vcpu *vcpu)
902{
903 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
904 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
905}
906
c8639010
JK		 907static void kvm_update_dr7(struct kvm_vcpu *vcpu)
908{
909 unsigned long dr7;
910
911 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
912 dr7 = vcpu->arch.guest_debug_dr7;
913 else
914 dr7 = vcpu->arch.dr7;
915 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 916 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
917 if (dr7 & DR7_BP_EN_MASK)
918 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 919}
920
6f43ed01
NA		 921static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
922{
923 u64 fixed = DR6_FIXED_1;
924
d6321d49 925 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 926 fixed |= DR6_RTM;
927 return fixed;
928}
929
338dbc97 930static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 931{
932 switch (dr) {
933 case 0 ... 3:
934 vcpu->arch.db[dr] = val;
935 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
936 vcpu->arch.eff_db[dr] = val;
937 break;
938 case 4:
020df079
GN		 939 /* fall through */
940 case 6:
338dbc97
GN		 941 if (val & 0xffffffff00000000ULL)
942 return -1; /* #GP */
6f43ed01 943 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 944 kvm_update_dr6(vcpu);
020df079
GN		 945 break;
946 case 5:
020df079
GN		 947 /* fall through */
948 default: /* 7 */
338dbc97
GN		 949 if (val & 0xffffffff00000000ULL)
950 return -1; /* #GP */
020df079 951 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 952 kvm_update_dr7(vcpu);
020df079
GN		 953 break;
954 }
955
956 return 0;
957}
338dbc97
GN		 958
959int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
960{
16f8a6f9 961 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 962 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 963 return 1;
964 }
965 return 0;
338dbc97 966}
020df079
GN		 967EXPORT_SYMBOL_GPL(kvm_set_dr);
968
16f8a6f9 969int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 970{
971 switch (dr) {
972 case 0 ... 3:
973 *val = vcpu->arch.db[dr];
974 break;
975 case 4:
020df079
GN		 976 /* fall through */
977 case 6:
73aaf249
JK		 978 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
979 *val = vcpu->arch.dr6;
980 else
981 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 982 break;
983 case 5:
020df079
GN		 984 /* fall through */
985 default: /* 7 */
986 *val = vcpu->arch.dr7;
987 break;
988 }
338dbc97
GN		 989 return 0;
990}
020df079
GN		 991EXPORT_SYMBOL_GPL(kvm_get_dr);
992
022cd0e8
AK		 993bool kvm_rdpmc(struct kvm_vcpu *vcpu)
994{
995 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
996 u64 data;
997 int err;
998
c6702c9d 999 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1000 if (err)
1001 return err;
1002 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1003 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1004 return err;
1005}
1006EXPORT_SYMBOL_GPL(kvm_rdpmc);
1007
043405e1
CO		 1008/*
1009 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1010 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1011 *
1012 * This list is modified at module load time to reflect the
e3267cbb 1013 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1014 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1015 * may depend on host virtualization features rather than host cpu features.
043405e1 1016 */
e3267cbb 1017
043405e1
CO		 1018static u32 msrs_to_save[] = {
1019 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1020 MSR_STAR,
043405e1
CO		 1021#ifdef CONFIG_X86_64
1022 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1023#endif
b3897a49 1024 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1025 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1026 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1027};
1028
1029static unsigned num_msrs_to_save;
1030
62ef68bb
PB		 1031static u32 emulated_msrs[] = {
1032 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1033 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1034 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1035 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1036 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1037 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1038 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1039 HV_X64_MSR_RESET,
11c4b1ca 1040 HV_X64_MSR_VP_INDEX,
9eec50b8 1041 HV_X64_MSR_VP_RUNTIME,
5c919412 1042 HV_X64_MSR_SCONTROL,
1f4b34f8 1043 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1044 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1045 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1046 HV_X64_MSR_TSC_EMULATION_STATUS,
1047
1048 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1049 MSR_KVM_PV_EOI_EN,
1050
ba904635 1051 MSR_IA32_TSC_ADJUST,
a3e06bbe 1052 MSR_IA32_TSCDEADLINE,
043405e1 1053 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1054 MSR_IA32_MCG_STATUS,
1055 MSR_IA32_MCG_CTL,
c45dcc71 1056 MSR_IA32_MCG_EXT_CTL,
64d60670 1057 MSR_IA32_SMBASE,
52797bf9 1058 MSR_SMI_COUNT,
db2336a8
KH		 1059 MSR_PLATFORM_INFO,
1060 MSR_MISC_FEATURES_ENABLES,
bc226f07 1061 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1062};
1063
62ef68bb
PB		 1064static unsigned num_emulated_msrs;
1065
801e459a
TL		 1066/*
1067 * List of msr numbers which are used to expose MSR-based features that
1068 * can be used by a hypervisor to validate requested CPU features.
1069 */
1070static u32 msr_based_features[] = {
1389309c
PB		 1071 MSR_IA32_VMX_BASIC,
1072 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1073 MSR_IA32_VMX_PINBASED_CTLS,
1074 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1075 MSR_IA32_VMX_PROCBASED_CTLS,
1076 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1077 MSR_IA32_VMX_EXIT_CTLS,
1078 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1079 MSR_IA32_VMX_ENTRY_CTLS,
1080 MSR_IA32_VMX_MISC,
1081 MSR_IA32_VMX_CR0_FIXED0,
1082 MSR_IA32_VMX_CR0_FIXED1,
1083 MSR_IA32_VMX_CR4_FIXED0,
1084 MSR_IA32_VMX_CR4_FIXED1,
1085 MSR_IA32_VMX_VMCS_ENUM,
1086 MSR_IA32_VMX_PROCBASED_CTLS2,
1087 MSR_IA32_VMX_EPT_VPID_CAP,
1088 MSR_IA32_VMX_VMFUNC,
1089
d1d93fa9 1090 MSR_F10H_DECFG,
518e7b94 1091 MSR_IA32_UCODE_REV,
801e459a
TL		 1092};
1093
1094static unsigned int num_msr_based_features;
1095
66421c1e
WL		 1096static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1097{
1098 switch (msr->index) {
518e7b94
WL		 1099 case MSR_IA32_UCODE_REV:
1100 rdmsrl(msr->index, msr->data);
1101 break;
66421c1e
WL		 1102 default:
1103 if (kvm_x86_ops->get_msr_feature(msr))
1104 return 1;
1105 }
1106 return 0;
1107}
1108
801e459a
TL		 1109static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1110{
1111 struct kvm_msr_entry msr;
66421c1e 1112 int r;
801e459a
TL		 1113
1114 msr.index = index;
66421c1e
WL		 1115 r = kvm_get_msr_feature(&msr);
1116 if (r)
1117 return r;
801e459a
TL		 1118
1119 *data = msr.data;
1120
1121 return 0;
1122}
1123
384bb783 1124bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1125{
b69e8cae 1126 if (efer & efer_reserved_bits)
384bb783 1127 return false;
15c4a640 1128
1b4d56b8 1129 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1130 return false;
1b2fd70c 1131
1b4d56b8 1132 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1133 return false;
d8017474 1134
384bb783
JK		 1135 return true;
1136}
1137EXPORT_SYMBOL_GPL(kvm_valid_efer);
1138
1139static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1140{
1141 u64 old_efer = vcpu->arch.efer;
1142
1143 if (!kvm_valid_efer(vcpu, efer))
1144 return 1;
1145
1146 if (is_paging(vcpu)
1147 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1148 return 1;
1149
15c4a640 1150 efer &= ~EFER_LMA;
f6801dff 1151 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1152
a3d204e2
SY		 1153 kvm_x86_ops->set_efer(vcpu, efer);
1154
aad82703
SY		 1155 /* Update reserved bits */
1156 if ((efer ^ old_efer) & EFER_NX)
1157 kvm_mmu_reset_context(vcpu);
1158
b69e8cae 1159 return 0;
15c4a640
CO		 1160}
1161
f2b4b7dd
JR		 1162void kvm_enable_efer_bits(u64 mask)
1163{
1164 efer_reserved_bits &= ~mask;
1165}
1166EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1167
15c4a640
CO		 1168/*
1169 * Writes msr value into into the appropriate "register".
1170 * Returns 0 on success, non-0 otherwise.
1171 * Assumes vcpu_load() was already called.
1172 */
8fe8ab46 1173int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1174{
854e8bb1
NA		 1175 switch (msr->index) {
1176 case MSR_FS_BASE:
1177 case MSR_GS_BASE:
1178 case MSR_KERNEL_GS_BASE:
1179 case MSR_CSTAR:
1180 case MSR_LSTAR:
fd8cb433 1181 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1182 return 1;
1183 break;
1184 case MSR_IA32_SYSENTER_EIP:
1185 case MSR_IA32_SYSENTER_ESP:
1186 /*
1187 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1188 * non-canonical address is written on Intel but not on
1189 * AMD (which ignores the top 32-bits, because it does
1190 * not implement 64-bit SYSENTER).
1191 *
1192 * 64-bit code should hence be able to write a non-canonical
1193 * value on AMD. Making the address canonical ensures that
1194 * vmentry does not fail on Intel after writing a non-canonical
1195 * value, and that something deterministic happens if the guest
1196 * invokes 64-bit SYSENTER.
1197 */
fd8cb433 1198 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1199 }
8fe8ab46 1200 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1201}
854e8bb1 1202EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1203
313a3dc7
CO		 1204/*
1205 * Adapt set_msr() to msr_io()'s calling convention
1206 */
609e36d3
PB		 1207static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1208{
1209 struct msr_data msr;
1210 int r;
1211
1212 msr.index = index;
1213 msr.host_initiated = true;
1214 r = kvm_get_msr(vcpu, &msr);
1215 if (r)
1216 return r;
1217
1218 *data = msr.data;
1219 return 0;
1220}
1221
313a3dc7
CO		 1222static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1223{
8fe8ab46
WA		 1224 struct msr_data msr;
1225
1226 msr.data = *data;
1227 msr.index = index;
1228 msr.host_initiated = true;
1229 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1230}
1231
16e8d74d
MT		 1232#ifdef CONFIG_X86_64
1233struct pvclock_gtod_data {
1234 seqcount_t seq;
1235
1236 struct { /* extract of a clocksource struct */
1237 int vclock_mode;
a5a1d1c2
TG		 1238 u64 cycle_last;
1239 u64 mask;
16e8d74d
MT		 1240 u32 mult;
1241 u32 shift;
1242 } clock;
1243
cbcf2dd3
TG		 1244 u64 boot_ns;
1245 u64 nsec_base;
55dd00a7 1246 u64 wall_time_sec;
16e8d74d
MT		 1247};
1248
1249static struct pvclock_gtod_data pvclock_gtod_data;
1250
1251static void update_pvclock_gtod(struct timekeeper *tk)
1252{
1253 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1254 u64 boot_ns;
1255
876e7881 1256 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1257
1258 write_seqcount_begin(&vdata->seq);
1259
1260 /* copy pvclock gtod data */
876e7881
PZ		 1261 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1262 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1263 vdata->clock.mask = tk->tkr_mono.mask;
1264 vdata->clock.mult = tk->tkr_mono.mult;
1265 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1266
cbcf2dd3 1267 vdata->boot_ns = boot_ns;
876e7881 1268 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1269
55dd00a7
MT		 1270 vdata->wall_time_sec = tk->xtime_sec;
1271
16e8d74d
MT		 1272 write_seqcount_end(&vdata->seq);
1273}
1274#endif
1275
bab5bb39
NK		 1276void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1277{
1278 /*
1279 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1280 * vcpu_enter_guest. This function is only called from
1281 * the physical CPU that is running vcpu.
1282 */
1283 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1284}
16e8d74d 1285
18068523
GOC		 1286static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1287{
9ed3c444
AK		 1288 int version;
1289 int r;
50d0a0f9 1290 struct pvclock_wall_clock wc;
87aeb54f 1291 struct timespec64 boot;
18068523
GOC		 1292
1293 if (!wall_clock)
1294 return;
1295
9ed3c444
AK		 1296 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1297 if (r)
1298 return;
1299
1300 if (version & 1)
1301 ++version; /* first time write, random junk */
1302
1303 ++version;
18068523 1304
1dab1345
NK		 1305 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1306 return;
18068523 1307
50d0a0f9
GH		 1308 /*
1309 * The guest calculates current wall clock time by adding
34c238a1 1310 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1311 * wall clock specified here. guest system time equals host
1312 * system time for us, thus we must fill in host boot time here.
1313 */
87aeb54f 1314 getboottime64(&boot);
50d0a0f9 1315
4b648665 1316 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1317 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1318 boot = timespec64_sub(boot, ts);
4b648665 1319 }
87aeb54f 1320 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1321 wc.nsec = boot.tv_nsec;
1322 wc.version = version;
18068523
GOC		 1323
1324 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1325
1326 version++;
1327 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1328}
1329
50d0a0f9
GH		 1330static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1331{
b51012de
PB		 1332 do_shl32_div32(dividend, divisor);
1333 return dividend;
50d0a0f9
GH		 1334}
1335
3ae13faa 1336static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1337 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1338{
5f4e3f88 1339 uint64_t scaled64;
50d0a0f9
GH		 1340 int32_t shift = 0;
1341 uint64_t tps64;
1342 uint32_t tps32;
1343
3ae13faa
PB		 1344 tps64 = base_hz;
1345 scaled64 = scaled_hz;
50933623 1346 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1347 tps64 >>= 1;
1348 shift--;
1349 }
1350
1351 tps32 = (uint32_t)tps64;
50933623
JK		 1352 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1353 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1354 scaled64 >>= 1;
1355 else
1356 tps32 <<= 1;
50d0a0f9
GH		 1357 shift++;
1358 }
1359
5f4e3f88
ZA		 1360 *pshift = shift;
1361 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1362
3ae13faa
PB		 1363 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1364 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1365}
1366
d828199e 1367#ifdef CONFIG_X86_64
16e8d74d 1368static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1369#endif
16e8d74d 1370
c8076604 1371static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1372static unsigned long max_tsc_khz;
c8076604 1373
cc578287 1374static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1375{
cc578287
ZA		 1376 u64 v = (u64)khz * (1000000 + ppm);
1377 do_div(v, 1000000);
1378 return v;
1e993611
JR		 1379}
1380
381d585c
HZ		 1381static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1382{
1383 u64 ratio;
1384
1385 /* Guest TSC same frequency as host TSC? */
1386 if (!scale) {
1387 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1388 return 0;
1389 }
1390
1391 /* TSC scaling supported? */
1392 if (!kvm_has_tsc_control) {
1393 if (user_tsc_khz > tsc_khz) {
1394 vcpu->arch.tsc_catchup = 1;
1395 vcpu->arch.tsc_always_catchup = 1;
1396 return 0;
1397 } else {
1398 WARN(1, "user requested TSC rate below hardware speed\n");
1399 return -1;
1400 }
1401 }
1402
1403 /* TSC scaling required - calculate ratio */
1404 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1405 user_tsc_khz, tsc_khz);
1406
1407 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1408 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1409 user_tsc_khz);
1410 return -1;
1411 }
1412
1413 vcpu->arch.tsc_scaling_ratio = ratio;
1414 return 0;
1415}
1416
4941b8cb 1417static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1418{
cc578287
ZA		 1419 u32 thresh_lo, thresh_hi;
1420 int use_scaling = 0;
217fc9cf 1421
03ba32ca 1422 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1423 if (user_tsc_khz == 0) {
ad721883
HZ		 1424 /* set tsc_scaling_ratio to a safe value */
1425 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1426 return -1;
ad721883 1427 }
03ba32ca 1428
c285545f 1429 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1430 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1431 &vcpu->arch.virtual_tsc_shift,
1432 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1433 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1434
1435 /*
1436 * Compute the variation in TSC rate which is acceptable
1437 * within the range of tolerance and decide if the
1438 * rate being applied is within that bounds of the hardware
1439 * rate. If so, no scaling or compensation need be done.
1440 */
1441 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1442 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1443 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1444 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1445 use_scaling = 1;
1446 }
4941b8cb 1447 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1448}
1449
1450static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1451{
e26101b1 1452 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1453 vcpu->arch.virtual_tsc_mult,
1454 vcpu->arch.virtual_tsc_shift);
e26101b1 1455 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1456 return tsc;
1457}
1458
b0c39dc6
VK		 1459static inline int gtod_is_based_on_tsc(int mode)
1460{
1461 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1462}
1463
69b0049a 1464static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1465{
1466#ifdef CONFIG_X86_64
1467 bool vcpus_matched;
b48aa97e
MT		 1468 struct kvm_arch *ka = &vcpu->kvm->arch;
1469 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1470
1471 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1472 atomic_read(&vcpu->kvm->online_vcpus));
1473
7f187922
MT		 1474 /*
1475 * Once the masterclock is enabled, always perform request in
1476 * order to update it.
1477 *
1478 * In order to enable masterclock, the host clocksource must be TSC
1479 * and the vcpus need to have matched TSCs. When that happens,
1480 * perform request to enable masterclock.
1481 */
1482 if (ka->use_master_clock ||
b0c39dc6 1483 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1484 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1485
1486 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1487 atomic_read(&vcpu->kvm->online_vcpus),
1488 ka->use_master_clock, gtod->clock.vclock_mode);
1489#endif
1490}
1491
ba904635
WA		 1492static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1493{
e79f245d 1494 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1495 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1496}
1497
35181e86
HZ		 1498/*
1499 * Multiply tsc by a fixed point number represented by ratio.
1500 *
1501 * The most significant 64-N bits (mult) of ratio represent the
1502 * integral part of the fixed point number; the remaining N bits
1503 * (frac) represent the fractional part, ie. ratio represents a fixed
1504 * point number (mult + frac * 2^(-N)).
1505 *
1506 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1507 */
1508static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1509{
1510 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1511}
1512
1513u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1514{
1515 u64 _tsc = tsc;
1516 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1517
1518 if (ratio != kvm_default_tsc_scaling_ratio)
1519 _tsc = __scale_tsc(ratio, tsc);
1520
1521 return _tsc;
1522}
1523EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1524
07c1419a
HZ		 1525static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1526{
1527 u64 tsc;
1528
1529 tsc = kvm_scale_tsc(vcpu, rdtsc());
1530
1531 return target_tsc - tsc;
1532}
1533
4ba76538
HZ		 1534u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1535{
e79f245d
KA		 1536 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1537
1538 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1539}
1540EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1541
a545ab6a
LC		 1542static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1543{
1544 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1545 vcpu->arch.tsc_offset = offset;
1546}
1547
b0c39dc6
VK		 1548static inline bool kvm_check_tsc_unstable(void)
1549{
1550#ifdef CONFIG_X86_64
1551 /*
1552 * TSC is marked unstable when we're running on Hyper-V,
1553 * 'TSC page' clocksource is good.
1554 */
1555 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1556 return false;
1557#endif
1558 return check_tsc_unstable();
1559}
1560
8fe8ab46 1561void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1562{
1563 struct kvm *kvm = vcpu->kvm;
f38e098f 1564 u64 offset, ns, elapsed;
99e3e30a 1565 unsigned long flags;
b48aa97e 1566 bool matched;
0d3da0d2 1567 bool already_matched;
8fe8ab46 1568 u64 data = msr->data;
c5e8ec8e 1569 bool synchronizing = false;
99e3e30a 1570
038f8c11 1571 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1572 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1573 ns = ktime_get_boot_ns();
f38e098f 1574 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1575
03ba32ca 1576 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1577 if (data == 0 && msr->host_initiated) {
1578 /*
1579 * detection of vcpu initialization -- need to sync
1580 * with other vCPUs. This particularly helps to keep
1581 * kvm_clock stable after CPU hotplug
1582 */
1583 synchronizing = true;
1584 } else {
1585 u64 tsc_exp = kvm->arch.last_tsc_write +
1586 nsec_to_cycles(vcpu, elapsed);
1587 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1588 /*
1589 * Special case: TSC write with a small delta (1 second)
1590 * of virtual cycle time against real time is
1591 * interpreted as an attempt to synchronize the CPU.
1592 */
1593 synchronizing = data < tsc_exp + tsc_hz &&
1594 data + tsc_hz > tsc_exp;
1595 }
c5e8ec8e 1596 }
f38e098f
ZA		 1597
1598 /*
5d3cb0f6
ZA		 1599 * For a reliable TSC, we can match TSC offsets, and for an unstable
1600 * TSC, we add elapsed time in this computation. We could let the
1601 * compensation code attempt to catch up if we fall behind, but
1602 * it's better to try to match offsets from the beginning.
1603 */
c5e8ec8e 1604 if (synchronizing &&
5d3cb0f6 1605 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1606 if (!kvm_check_tsc_unstable()) {
e26101b1 1607 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1608 pr_debug("kvm: matched tsc offset for %llu\n", data);
1609 } else {
857e4099 1610 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1611 data += delta;
07c1419a 1612 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1613 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1614 }
b48aa97e 1615 matched = true;
0d3da0d2 1616 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1617 } else {
1618 /*
1619 * We split periods of matched TSC writes into generations.
1620 * For each generation, we track the original measured
1621 * nanosecond time, offset, and write, so if TSCs are in
1622 * sync, we can match exact offset, and if not, we can match
4a969980 1623 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1624 *
1625 * These values are tracked in kvm->arch.cur_xxx variables.
1626 */
1627 kvm->arch.cur_tsc_generation++;
1628 kvm->arch.cur_tsc_nsec = ns;
1629 kvm->arch.cur_tsc_write = data;
1630 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1631 matched = false;
0d3da0d2 1632 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1633 kvm->arch.cur_tsc_generation, data);
f38e098f 1634 }
e26101b1
ZA		 1635
1636 /*
1637 * We also track th most recent recorded KHZ, write and time to
1638 * allow the matching interval to be extended at each write.
1639 */
f38e098f
ZA		 1640 kvm->arch.last_tsc_nsec = ns;
1641 kvm->arch.last_tsc_write = data;
5d3cb0f6 1642 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1643
b183aa58 1644 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1645
1646 /* Keep track of which generation this VCPU has synchronized to */
1647 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1648 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1649 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1650
d6321d49 1651 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1652 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1653
a545ab6a 1654 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1655 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1656
1657 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1658 if (!matched) {
b48aa97e 1659 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1660 } else if (!already_matched) {
1661 kvm->arch.nr_vcpus_matched_tsc++;
1662 }
b48aa97e
MT		 1663
1664 kvm_track_tsc_matching(vcpu);
1665 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1666}
e26101b1 1667
99e3e30a
ZA		 1668EXPORT_SYMBOL_GPL(kvm_write_tsc);
1669
58ea6767
HZ		 1670static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1671 s64 adjustment)
1672{
ea26e4ec 1673 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1674}
1675
1676static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1677{
1678 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1679 WARN_ON(adjustment < 0);
1680 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1681 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1682}
1683
d828199e
MT		 1684#ifdef CONFIG_X86_64
1685
a5a1d1c2 1686static u64 read_tsc(void)
d828199e 1687{
a5a1d1c2 1688 u64 ret = (u64)rdtsc_ordered();
03b9730b 1689 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1690
1691 if (likely(ret >= last))
1692 return ret;
1693
1694 /*
1695 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1696 * predictable (it's just a function of time and the likely is
d828199e
MT		 1697 * very likely) and there's a data dependence, so force GCC
1698 * to generate a branch instead. I don't barrier() because
1699 * we don't actually need a barrier, and if this function
1700 * ever gets inlined it will generate worse code.
1701 */
1702 asm volatile ("");
1703 return last;
1704}
1705
b0c39dc6 1706static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1707{
1708 long v;
1709 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1710 u64 tsc_pg_val;
1711
1712 switch (gtod->clock.vclock_mode) {
1713 case VCLOCK_HVCLOCK:
1714 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1715 tsc_timestamp);
1716 if (tsc_pg_val != U64_MAX) {
1717 /* TSC page valid */
1718 *mode = VCLOCK_HVCLOCK;
1719 v = (tsc_pg_val - gtod->clock.cycle_last) &
1720 gtod->clock.mask;
1721 } else {
1722 /* TSC page invalid */
1723 *mode = VCLOCK_NONE;
1724 }
1725 break;
1726 case VCLOCK_TSC:
1727 *mode = VCLOCK_TSC;
1728 *tsc_timestamp = read_tsc();
1729 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1730 gtod->clock.mask;
1731 break;
1732 default:
1733 *mode = VCLOCK_NONE;
1734 }
d828199e 1735
b0c39dc6
VK		 1736 if (*mode == VCLOCK_NONE)
1737 *tsc_timestamp = v = 0;
d828199e 1738
d828199e
MT		 1739 return v * gtod->clock.mult;
1740}
1741
b0c39dc6 1742static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1743{
cbcf2dd3 1744 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1745 unsigned long seq;
d828199e 1746 int mode;
cbcf2dd3 1747 u64 ns;
d828199e 1748
d828199e
MT		 1749 do {
1750 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1751 ns = gtod->nsec_base;
b0c39dc6 1752 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1753 ns >>= gtod->clock.shift;
cbcf2dd3 1754 ns += gtod->boot_ns;
d828199e 1755 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1756 *t = ns;
d828199e
MT		 1757
1758 return mode;
1759}
1760
b0c39dc6 1761static int do_realtime(struct timespec *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1762{
1763 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1764 unsigned long seq;
1765 int mode;
1766 u64 ns;
1767
1768 do {
1769 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1770 ts->tv_sec = gtod->wall_time_sec;
1771 ns = gtod->nsec_base;
b0c39dc6 1772 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1773 ns >>= gtod->clock.shift;
1774 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1775
1776 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1777 ts->tv_nsec = ns;
1778
1779 return mode;
1780}
1781
b0c39dc6
VK		 1782/* returns true if host is using TSC based clocksource */
1783static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1784{
d828199e 1785 /* checked again under seqlock below */
b0c39dc6 1786 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1787 return false;
1788
b0c39dc6
VK		 1789 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1790 tsc_timestamp));
d828199e 1791}
55dd00a7 1792
b0c39dc6 1793/* returns true if host is using TSC based clocksource */
55dd00a7 1794static bool kvm_get_walltime_and_clockread(struct timespec *ts,
b0c39dc6 1795 u64 *tsc_timestamp)
55dd00a7
MT		 1796{
1797 /* checked again under seqlock below */
b0c39dc6 1798 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1799 return false;
1800
b0c39dc6 1801 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1802}
d828199e
MT		 1803#endif
1804
1805/*
1806 *
b48aa97e
MT		 1807 * Assuming a stable TSC across physical CPUS, and a stable TSC
1808 * across virtual CPUs, the following condition is possible.
1809 * Each numbered line represents an event visible to both
d828199e
MT		 1810 * CPUs at the next numbered event.
1811 *
1812 * "timespecX" represents host monotonic time. "tscX" represents
1813 * RDTSC value.
1814 *
1815 * VCPU0 on CPU0 | VCPU1 on CPU1
1816 *
1817 * 1. read timespec0,tsc0
1818 * 2. | timespec1 = timespec0 + N
1819 * | tsc1 = tsc0 + M
1820 * 3. transition to guest | transition to guest
1821 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1822 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1823 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1824 *
1825 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1826 *
1827 * - ret0 < ret1
1828 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1829 * ...
1830 * - 0 < N - M => M < N
1831 *
1832 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1833 * always the case (the difference between two distinct xtime instances
1834 * might be smaller then the difference between corresponding TSC reads,
1835 * when updating guest vcpus pvclock areas).
1836 *
1837 * To avoid that problem, do not allow visibility of distinct
1838 * system_timestamp/tsc_timestamp values simultaneously: use a master
1839 * copy of host monotonic time values. Update that master copy
1840 * in lockstep.
1841 *
b48aa97e 1842 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1843 *
1844 */
1845
1846static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1847{
1848#ifdef CONFIG_X86_64
1849 struct kvm_arch *ka = &kvm->arch;
1850 int vclock_mode;
b48aa97e
MT		 1851 bool host_tsc_clocksource, vcpus_matched;
1852
1853 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1854 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1855
1856 /*
1857 * If the host uses TSC clock, then passthrough TSC as stable
1858 * to the guest.
1859 */
b48aa97e 1860 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1861 &ka->master_kernel_ns,
1862 &ka->master_cycle_now);
1863
16a96021 1864 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1865 && !ka->backwards_tsc_observed
54750f2c 1866 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1867
d828199e
MT		 1868 if (ka->use_master_clock)
1869 atomic_set(&kvm_guest_has_master_clock, 1);
1870
1871 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1872 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1873 vcpus_matched);
d828199e
MT		 1874#endif
1875}
1876
2860c4b1
PB		 1877void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1878{
1879 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1880}
1881
2e762ff7
MT		 1882static void kvm_gen_update_masterclock(struct kvm *kvm)
1883{
1884#ifdef CONFIG_X86_64
1885 int i;
1886 struct kvm_vcpu *vcpu;
1887 struct kvm_arch *ka = &kvm->arch;
1888
1889 spin_lock(&ka->pvclock_gtod_sync_lock);
1890 kvm_make_mclock_inprogress_request(kvm);
1891 /* no guest entries from this point */
1892 pvclock_update_vm_gtod_copy(kvm);
1893
1894 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1895 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1896
1897 /* guest entries allowed */
1898 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1899 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1900
1901 spin_unlock(&ka->pvclock_gtod_sync_lock);
1902#endif
1903}
1904
e891a32e 1905u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1906{
108b249c 1907 struct kvm_arch *ka = &kvm->arch;
8b953440 1908 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1909 u64 ret;
108b249c 1910
8b953440
PB		 1911 spin_lock(&ka->pvclock_gtod_sync_lock);
1912 if (!ka->use_master_clock) {
1913 spin_unlock(&ka->pvclock_gtod_sync_lock);
1914 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1915 }
1916
8b953440
PB		 1917 hv_clock.tsc_timestamp = ka->master_cycle_now;
1918 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1919 spin_unlock(&ka->pvclock_gtod_sync_lock);
1920
e2c2206a
WL		 1921 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1922 get_cpu();
1923
e70b57a6
WL		 1924 if (__this_cpu_read(cpu_tsc_khz)) {
1925 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1926 &hv_clock.tsc_shift,
1927 &hv_clock.tsc_to_system_mul);
1928 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1929 } else
1930 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1931
1932 put_cpu();
1933
1934 return ret;
108b249c
PB		 1935}
1936
0d6dd2ff
PB		 1937static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1938{
1939 struct kvm_vcpu_arch *vcpu = &v->arch;
1940 struct pvclock_vcpu_time_info guest_hv_clock;
1941
4e335d9e 1942 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1943 &guest_hv_clock, sizeof(guest_hv_clock))))
1944 return;
1945
1946 /* This VCPU is paused, but it's legal for a guest to read another
1947 * VCPU's kvmclock, so we really have to follow the specification where
1948 * it says that version is odd if data is being modified, and even after
1949 * it is consistent.
1950 *
1951 * Version field updates must be kept separate. This is because
1952 * kvm_write_guest_cached might use a "rep movs" instruction, and
1953 * writes within a string instruction are weakly ordered. So there
1954 * are three writes overall.
1955 *
1956 * As a small optimization, only write the version field in the first
1957 * and third write. The vcpu->pv_time cache is still valid, because the
1958 * version field is the first in the struct.
1959 */
1960 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1961
51c4b8bb
LA		 1962 if (guest_hv_clock.version & 1)
1963 ++guest_hv_clock.version; /* first time write, random junk */
1964
0d6dd2ff 1965 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1966 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1967 &vcpu->hv_clock,
1968 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1969
1970 smp_wmb();
1971
1972 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1973 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1974
1975 if (vcpu->pvclock_set_guest_stopped_request) {
1976 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1977 vcpu->pvclock_set_guest_stopped_request = false;
1978 }
1979
1980 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1981
4e335d9e
PB		 1982 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1983 &vcpu->hv_clock,
1984 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1985
1986 smp_wmb();
1987
1988 vcpu->hv_clock.version++;
4e335d9e
PB		 1989 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1990 &vcpu->hv_clock,
1991 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1992}
1993
34c238a1 1994static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1995{
78db6a50 1996 unsigned long flags, tgt_tsc_khz;
18068523 1997 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1998 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1999 s64 kernel_ns;
d828199e 2000 u64 tsc_timestamp, host_tsc;
51d59c6b 2001 u8 pvclock_flags;
d828199e
MT		 2002 bool use_master_clock;
2003
2004 kernel_ns = 0;
2005 host_tsc = 0;
18068523 2006
d828199e
MT		 2007 /*
2008 * If the host uses TSC clock, then passthrough TSC as stable
2009 * to the guest.
2010 */
2011 spin_lock(&ka->pvclock_gtod_sync_lock);
2012 use_master_clock = ka->use_master_clock;
2013 if (use_master_clock) {
2014 host_tsc = ka->master_cycle_now;
2015 kernel_ns = ka->master_kernel_ns;
2016 }
2017 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2018
2019 /* Keep irq disabled to prevent changes to the clock */
2020 local_irq_save(flags);
78db6a50
PB		 2021 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2022 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2023 local_irq_restore(flags);
2024 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2025 return 1;
2026 }
d828199e 2027 if (!use_master_clock) {
4ea1636b 2028 host_tsc = rdtsc();
108b249c 2029 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2030 }
2031
4ba76538 2032 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2033
c285545f
ZA		 2034 /*
2035 * We may have to catch up the TSC to match elapsed wall clock
2036 * time for two reasons, even if kvmclock is used.
2037 * 1) CPU could have been running below the maximum TSC rate
2038 * 2) Broken TSC compensation resets the base at each VCPU
2039 * entry to avoid unknown leaps of TSC even when running
2040 * again on the same CPU. This may cause apparent elapsed
2041 * time to disappear, and the guest to stand still or run
2042 * very slowly.
2043 */
2044 if (vcpu->tsc_catchup) {
2045 u64 tsc = compute_guest_tsc(v, kernel_ns);
2046 if (tsc > tsc_timestamp) {
f1e2b260 2047 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2048 tsc_timestamp = tsc;
2049 }
50d0a0f9
GH		 2050 }
2051
18068523
GOC		 2052 local_irq_restore(flags);
2053
0d6dd2ff 2054 /* With all the info we got, fill in the values */
18068523 2055
78db6a50
PB		 2056 if (kvm_has_tsc_control)
2057 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2058
2059 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2060 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2061 &vcpu->hv_clock.tsc_shift,
2062 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2063 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2064 }
2065
1d5f066e 2066 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2067 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2068 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2069
d828199e 2070 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2071 pvclock_flags = 0;
d828199e
MT		 2072 if (use_master_clock)
2073 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2074
78c0337a
MT		 2075 vcpu->hv_clock.flags = pvclock_flags;
2076
095cf55d
PB		 2077 if (vcpu->pv_time_enabled)
2078 kvm_setup_pvclock_page(v);
2079 if (v == kvm_get_vcpu(v->kvm, 0))
2080 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2081 return 0;
c8076604
GH		 2082}
2083
0061d53d
MT		 2084/*
2085 * kvmclock updates which are isolated to a given vcpu, such as
2086 * vcpu->cpu migration, should not allow system_timestamp from
2087 * the rest of the vcpus to remain static. Otherwise ntp frequency
2088 * correction applies to one vcpu's system_timestamp but not
2089 * the others.
2090 *
2091 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2092 * We need to rate-limit these requests though, as they can
2093 * considerably slow guests that have a large number of vcpus.
2094 * The time for a remote vcpu to update its kvmclock is bound
2095 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2096 */
2097
7e44e449
AJ		 2098#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2099
2100static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2101{
2102 int i;
7e44e449
AJ		 2103 struct delayed_work *dwork = to_delayed_work(work);
2104 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2105 kvmclock_update_work);
2106 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2107 struct kvm_vcpu *vcpu;
2108
2109 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2110 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2111 kvm_vcpu_kick(vcpu);
2112 }
2113}
2114
7e44e449
AJ		 2115static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2116{
2117 struct kvm *kvm = v->kvm;
2118
105b21bb 2119 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2120 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2121 KVMCLOCK_UPDATE_DELAY);
2122}
2123
332967a3
AJ		 2124#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2125
2126static void kvmclock_sync_fn(struct work_struct *work)
2127{
2128 struct delayed_work *dwork = to_delayed_work(work);
2129 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2130 kvmclock_sync_work);
2131 struct kvm *kvm = container_of(ka, struct kvm, arch);
2132
630994b3
MT		 2133 if (!kvmclock_periodic_sync)
2134 return;
2135
332967a3
AJ		 2136 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2137 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2138 KVMCLOCK_SYNC_PERIOD);
2139}
2140
9ffd986c 2141static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2142{
890ca9ae
HY		 2143 u64 mcg_cap = vcpu->arch.mcg_cap;
2144 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2145 u32 msr = msr_info->index;
2146 u64 data = msr_info->data;
890ca9ae 2147
15c4a640 2148 switch (msr) {
15c4a640 2149 case MSR_IA32_MCG_STATUS:
890ca9ae 2150 vcpu->arch.mcg_status = data;
15c4a640 2151 break;
c7ac679c 2152 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2153 if (!(mcg_cap & MCG_CTL_P))
2154 return 1;
2155 if (data != 0 && data != ~(u64)0)
2156 return -1;
2157 vcpu->arch.mcg_ctl = data;
2158 break;
2159 default:
2160 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2161 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2162 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2163 /* only 0 or all 1s can be written to IA32_MCi_CTL
2164 * some Linux kernels though clear bit 10 in bank 4 to
2165 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2166 * this to avoid an uncatched #GP in the guest
2167 */
890ca9ae 2168 if ((offset & 0x3) == 0 &&
114be429 2169 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2170 return -1;
9ffd986c
WL		 2171 if (!msr_info->host_initiated &&
2172 (offset & 0x3) == 1 && data != 0)
2173 return -1;
890ca9ae
HY		 2174 vcpu->arch.mce_banks[offset] = data;
2175 break;
2176 }
2177 return 1;
2178 }
2179 return 0;
2180}
2181
ffde22ac
ES		 2182static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2183{
2184 struct kvm *kvm = vcpu->kvm;
2185 int lm = is_long_mode(vcpu);
2186 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2187 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2188 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2189 : kvm->arch.xen_hvm_config.blob_size_32;
2190 u32 page_num = data & ~PAGE_MASK;
2191 u64 page_addr = data & PAGE_MASK;
2192 u8 *page;
2193 int r;
2194
2195 r = -E2BIG;
2196 if (page_num >= blob_size)
2197 goto out;
2198 r = -ENOMEM;
ff5c2c03
SL		 2199 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2200 if (IS_ERR(page)) {
2201 r = PTR_ERR(page);
ffde22ac 2202 goto out;
ff5c2c03 2203 }
54bf36aa 2204 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2205 goto out_free;
2206 r = 0;
2207out_free:
2208 kfree(page);
2209out:
2210 return r;
2211}
2212
344d9588
GN		 2213static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2214{
2215 gpa_t gpa = data & ~0x3f;
2216
52a5c155
WL		 2217 /* Bits 3:5 are reserved, Should be zero */
2218 if (data & 0x38)
344d9588
GN		 2219 return 1;
2220
2221 vcpu->arch.apf.msr_val = data;
2222
2223 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2224 kvm_clear_async_pf_completion_queue(vcpu);
2225 kvm_async_pf_hash_reset(vcpu);
2226 return 0;
2227 }
2228
4e335d9e 2229 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2230 sizeof(u32)))
344d9588
GN		 2231 return 1;
2232
6adba527 2233 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2234 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2235 kvm_async_pf_wakeup_all(vcpu);
2236 return 0;
2237}
2238
12f9a48f
GC		 2239static void kvmclock_reset(struct kvm_vcpu *vcpu)
2240{
0b79459b 2241 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2242}
2243
f38a7b75
WL		 2244static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2245{
2246 ++vcpu->stat.tlb_flush;
2247 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2248}
2249
c9aaa895
GC		 2250static void record_steal_time(struct kvm_vcpu *vcpu)
2251{
2252 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2253 return;
2254
4e335d9e 2255 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2256 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2257 return;
2258
f38a7b75
WL		 2259 /*
2260 * Doing a TLB flush here, on the guest's behalf, can avoid
2261 * expensive IPIs.
2262 */
2263 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2264 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2265
35f3fae1
WL		 2266 if (vcpu->arch.st.steal.version & 1)
2267 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2268
2269 vcpu->arch.st.steal.version += 1;
2270
4e335d9e 2271 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2272 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2273
2274 smp_wmb();
2275
c54cdf14
LC		 2276 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2277 vcpu->arch.st.last_steal;
2278 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2279
4e335d9e 2280 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2281 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2282
2283 smp_wmb();
2284
2285 vcpu->arch.st.steal.version += 1;
c9aaa895 2286
4e335d9e 2287 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2288 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2289}
2290
8fe8ab46 2291int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2292{
5753785f 2293 bool pr = false;
8fe8ab46
WA		 2294 u32 msr = msr_info->index;
2295 u64 data = msr_info->data;
5753785f 2296
15c4a640 2297 switch (msr) {
2e32b719 2298 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2299 case MSR_IA32_UCODE_WRITE:
2300 case MSR_VM_HSAVE_PA:
2301 case MSR_AMD64_PATCH_LOADER:
2302 case MSR_AMD64_BU_CFG2:
405a353a 2303 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2304 break;
2305
518e7b94
WL		 2306 case MSR_IA32_UCODE_REV:
2307 if (msr_info->host_initiated)
2308 vcpu->arch.microcode_version = data;
2309 break;
15c4a640 2310 case MSR_EFER:
b69e8cae 2311 return set_efer(vcpu, data);
8f1589d9
AP		 2312 case MSR_K7_HWCR:
2313 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2314 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2315 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2316 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2317 if (data != 0) {
a737f256
CD		 2318 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2319 data);
8f1589d9
AP		 2320 return 1;
2321 }
15c4a640 2322 break;
f7c6d140
AP		 2323 case MSR_FAM10H_MMIO_CONF_BASE:
2324 if (data != 0) {
a737f256
CD		 2325 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2326 "0x%llx\n", data);
f7c6d140
AP		 2327 return 1;
2328 }
15c4a640 2329 break;
b5e2fec0
AG		 2330 case MSR_IA32_DEBUGCTLMSR:
2331 if (!data) {
2332 /* We support the non-activated case already */
2333 break;
2334 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2335 /* Values other than LBR and BTF are vendor-specific,
2336 thus reserved and should throw a #GP */
2337 return 1;
2338 }
a737f256
CD		 2339 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2340 __func__, data);
b5e2fec0 2341 break;
9ba075a6 2342 case 0x200 ... 0x2ff:
ff53604b 2343 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2344 case MSR_IA32_APICBASE:
58cb628d 2345 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2346 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2347 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2348 case MSR_IA32_TSCDEADLINE:
2349 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2350 break;
ba904635 2351 case MSR_IA32_TSC_ADJUST:
d6321d49 2352 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2353 if (!msr_info->host_initiated) {
d913b904 2354 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2355 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2356 }
2357 vcpu->arch.ia32_tsc_adjust_msr = data;
2358 }
2359 break;
15c4a640 2360 case MSR_IA32_MISC_ENABLE:
ad312c7c 2361 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2362 break;
64d60670
PB		 2363 case MSR_IA32_SMBASE:
2364 if (!msr_info->host_initiated)
2365 return 1;
2366 vcpu->arch.smbase = data;
2367 break;
dd259935
PB		 2368 case MSR_IA32_TSC:
2369 kvm_write_tsc(vcpu, msr_info);
2370 break;
52797bf9
LA		 2371 case MSR_SMI_COUNT:
2372 if (!msr_info->host_initiated)
2373 return 1;
2374 vcpu->arch.smi_count = data;
2375 break;
11c6bffa 2376 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2377 case MSR_KVM_WALL_CLOCK:
2378 vcpu->kvm->arch.wall_clock = data;
2379 kvm_write_wall_clock(vcpu->kvm, data);
2380 break;
11c6bffa 2381 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2382 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2383 struct kvm_arch *ka = &vcpu->kvm->arch;
2384
12f9a48f 2385 kvmclock_reset(vcpu);
18068523 2386
54750f2c
MT		 2387 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2388 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2389
2390 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2391 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2392
2393 ka->boot_vcpu_runs_old_kvmclock = tmp;
2394 }
2395
18068523 2396 vcpu->arch.time = data;
0061d53d 2397 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2398
2399 /* we verify if the enable bit is set... */
2400 if (!(data & 1))
2401 break;
2402
4e335d9e 2403 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2404 &vcpu->arch.pv_time, data & ~1ULL,
2405 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2406 vcpu->arch.pv_time_enabled = false;
2407 else
2408 vcpu->arch.pv_time_enabled = true;
32cad84f 2409
18068523
GOC		 2410 break;
2411 }
344d9588
GN		 2412 case MSR_KVM_ASYNC_PF_EN:
2413 if (kvm_pv_enable_async_pf(vcpu, data))
2414 return 1;
2415 break;
c9aaa895
GC		 2416 case MSR_KVM_STEAL_TIME:
2417
2418 if (unlikely(!sched_info_on()))
2419 return 1;
2420
2421 if (data & KVM_STEAL_RESERVED_MASK)
2422 return 1;
2423
4e335d9e 2424 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2425 data & KVM_STEAL_VALID_BITS,
2426 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2427 return 1;
2428
2429 vcpu->arch.st.msr_val = data;
2430
2431 if (!(data & KVM_MSR_ENABLED))
2432 break;
2433
c9aaa895
GC		 2434 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2435
2436 break;
ae7a2a3f
MT		 2437 case MSR_KVM_PV_EOI_EN:
2438 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2439 return 1;
2440 break;
c9aaa895 2441
890ca9ae
HY		 2442 case MSR_IA32_MCG_CTL:
2443 case MSR_IA32_MCG_STATUS:
81760dcc 2444 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2445 return set_msr_mce(vcpu, msr_info);
71db6023 2446
6912ac32
WH		 2447 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2448 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2449 pr = true; /* fall through */
2450 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2451 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2452 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2453 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2454
2455 if (pr || data != 0)
a737f256
CD		 2456 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2457 "0x%x data 0x%llx\n", msr, data);
5753785f 2458 break;
84e0cefa
JS		 2459 case MSR_K7_CLK_CTL:
2460 /*
2461 * Ignore all writes to this no longer documented MSR.
2462 * Writes are only relevant for old K7 processors,
2463 * all pre-dating SVM, but a recommended workaround from
4a969980 2464 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2465 * affected processor models on the command line, hence
2466 * the need to ignore the workaround.
2467 */
2468 break;
55cd8e5a 2469 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2470 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2471 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2472 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2473 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2474 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2475 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2476 return kvm_hv_set_msr_common(vcpu, msr, data,
2477 msr_info->host_initiated);
91c9c3ed 2478 case MSR_IA32_BBL_CR_CTL3:
2479 /* Drop writes to this legacy MSR -- see rdmsr
2480 * counterpart for further detail.
2481 */
fab0aa3b
EM		 2482 if (report_ignored_msrs)
2483 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2484 msr, data);
91c9c3ed 2485 break;
2b036c6b 2486 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2487 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2488 return 1;
2489 vcpu->arch.osvw.length = data;
2490 break;
2491 case MSR_AMD64_OSVW_STATUS:
d6321d49 2492 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2493 return 1;
2494 vcpu->arch.osvw.status = data;
2495 break;
db2336a8
KH		 2496 case MSR_PLATFORM_INFO:
2497 if (!msr_info->host_initiated ||
2498 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2499 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2500 cpuid_fault_enabled(vcpu)))
2501 return 1;
2502 vcpu->arch.msr_platform_info = data;
2503 break;
2504 case MSR_MISC_FEATURES_ENABLES:
2505 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2506 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2507 !supports_cpuid_fault(vcpu)))
2508 return 1;
2509 vcpu->arch.msr_misc_features_enables = data;
2510 break;
15c4a640 2511 default:
ffde22ac
ES		 2512 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2513 return xen_hvm_config(vcpu, data);
c6702c9d 2514 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2515 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2516 if (!ignore_msrs) {
ae0f5499 2517 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2518 msr, data);
ed85c068
AP		 2519 return 1;
2520 } else {
fab0aa3b
EM		 2521 if (report_ignored_msrs)
2522 vcpu_unimpl(vcpu,
2523 "ignored wrmsr: 0x%x data 0x%llx\n",
2524 msr, data);
ed85c068
AP		 2525 break;
2526 }
15c4a640
CO		 2527 }
2528 return 0;
2529}
2530EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2531
2532
2533/*
2534 * Reads an msr value (of 'msr_index') into 'pdata'.
2535 * Returns 0 on success, non-0 otherwise.
2536 * Assumes vcpu_load() was already called.
2537 */
609e36d3 2538int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2539{
609e36d3 2540 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2541}
ff651cb6 2542EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2543
890ca9ae 2544static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2545{
2546 u64 data;
890ca9ae
HY		 2547 u64 mcg_cap = vcpu->arch.mcg_cap;
2548 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2549
2550 switch (msr) {
15c4a640
CO		 2551 case MSR_IA32_P5_MC_ADDR:
2552 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2553 data = 0;
2554 break;
15c4a640 2555 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2556 data = vcpu->arch.mcg_cap;
2557 break;
c7ac679c 2558 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2559 if (!(mcg_cap & MCG_CTL_P))
2560 return 1;
2561 data = vcpu->arch.mcg_ctl;
2562 break;
2563 case MSR_IA32_MCG_STATUS:
2564 data = vcpu->arch.mcg_status;
2565 break;
2566 default:
2567 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2568 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2569 u32 offset = msr - MSR_IA32_MC0_CTL;
2570 data = vcpu->arch.mce_banks[offset];
2571 break;
2572 }
2573 return 1;
2574 }
2575 *pdata = data;
2576 return 0;
2577}
2578
609e36d3 2579int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2580{
609e36d3 2581 switch (msr_info->index) {
890ca9ae 2582 case MSR_IA32_PLATFORM_ID:
15c4a640 2583 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2584 case MSR_IA32_DEBUGCTLMSR:
2585 case MSR_IA32_LASTBRANCHFROMIP:
2586 case MSR_IA32_LASTBRANCHTOIP:
2587 case MSR_IA32_LASTINTFROMIP:
2588 case MSR_IA32_LASTINTTOIP:
60af2ecd 2589 case MSR_K8_SYSCFG:
3afb1121
PB		 2590 case MSR_K8_TSEG_ADDR:
2591 case MSR_K8_TSEG_MASK:
60af2ecd 2592 case MSR_K7_HWCR:
61a6bd67 2593 case MSR_VM_HSAVE_PA:
1fdbd48c 2594 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2595 case MSR_AMD64_NB_CFG:
f7c6d140 2596 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2597 case MSR_AMD64_BU_CFG2:
0c2df2a1 2598 case MSR_IA32_PERF_CTL:
405a353a 2599 case MSR_AMD64_DC_CFG:
609e36d3 2600 msr_info->data = 0;
15c4a640 2601 break;
c51eb52b 2602 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2603 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2604 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2605 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2606 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2607 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2608 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2609 msr_info->data = 0;
5753785f 2610 break;
742bc670 2611 case MSR_IA32_UCODE_REV:
518e7b94 2612 msr_info->data = vcpu->arch.microcode_version;
742bc670 2613 break;
dd259935
PB		 2614 case MSR_IA32_TSC:
2615 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2616 break;
9ba075a6 2617 case MSR_MTRRcap:
9ba075a6 2618 case 0x200 ... 0x2ff:
ff53604b 2619 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2620 case 0xcd: /* fsb frequency */
609e36d3 2621 msr_info->data = 3;
15c4a640 2622 break;
7b914098
JS		 2623 /*
2624 * MSR_EBC_FREQUENCY_ID
2625 * Conservative value valid for even the basic CPU models.
2626 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2627 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2628 * and 266MHz for model 3, or 4. Set Core Clock
2629 * Frequency to System Bus Frequency Ratio to 1 (bits
2630 * 31:24) even though these are only valid for CPU
2631 * models > 2, however guests may end up dividing or
2632 * multiplying by zero otherwise.
2633 */
2634 case MSR_EBC_FREQUENCY_ID:
609e36d3 2635 msr_info->data = 1 << 24;
7b914098 2636 break;
15c4a640 2637 case MSR_IA32_APICBASE:
609e36d3 2638 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2639 break;
0105d1a5 2640 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2641 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2642 break;
a3e06bbe 2643 case MSR_IA32_TSCDEADLINE:
609e36d3 2644 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2645 break;
ba904635 2646 case MSR_IA32_TSC_ADJUST:
609e36d3 2647 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2648 break;
15c4a640 2649 case MSR_IA32_MISC_ENABLE:
609e36d3 2650 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2651 break;
64d60670
PB		 2652 case MSR_IA32_SMBASE:
2653 if (!msr_info->host_initiated)
2654 return 1;
2655 msr_info->data = vcpu->arch.smbase;
15c4a640 2656 break;
52797bf9
LA		 2657 case MSR_SMI_COUNT:
2658 msr_info->data = vcpu->arch.smi_count;
2659 break;
847f0ad8
AG		 2660 case MSR_IA32_PERF_STATUS:
2661 /* TSC increment by tick */
609e36d3 2662 msr_info->data = 1000ULL;
847f0ad8 2663 /* CPU multiplier */
b0996ae4 2664 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2665 break;
15c4a640 2666 case MSR_EFER:
609e36d3 2667 msr_info->data = vcpu->arch.efer;
15c4a640 2668 break;
18068523 2669 case MSR_KVM_WALL_CLOCK:
11c6bffa 2670 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2671 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2672 break;
2673 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2674 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2675 msr_info->data = vcpu->arch.time;
18068523 2676 break;
344d9588 2677 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2678 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2679 break;
c9aaa895 2680 case MSR_KVM_STEAL_TIME:
609e36d3 2681 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2682 break;
1d92128f 2683 case MSR_KVM_PV_EOI_EN:
609e36d3 2684 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2685 break;
890ca9ae
HY		 2686 case MSR_IA32_P5_MC_ADDR:
2687 case MSR_IA32_P5_MC_TYPE:
2688 case MSR_IA32_MCG_CAP:
2689 case MSR_IA32_MCG_CTL:
2690 case MSR_IA32_MCG_STATUS:
81760dcc 2691 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2692 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2693 case MSR_K7_CLK_CTL:
2694 /*
2695 * Provide expected ramp-up count for K7. All other
2696 * are set to zero, indicating minimum divisors for
2697 * every field.
2698 *
2699 * This prevents guest kernels on AMD host with CPU
2700 * type 6, model 8 and higher from exploding due to
2701 * the rdmsr failing.
2702 */
609e36d3 2703 msr_info->data = 0x20000000;
84e0cefa 2704 break;
55cd8e5a 2705 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2706 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2707 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2708 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2709 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2710 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2711 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887
AS		 2712 return kvm_hv_get_msr_common(vcpu,
2713 msr_info->index, &msr_info->data);
55cd8e5a 2714 break;
91c9c3ed 2715 case MSR_IA32_BBL_CR_CTL3:
2716 /* This legacy MSR exists but isn't fully documented in current
2717 * silicon. It is however accessed by winxp in very narrow
2718 * scenarios where it sets bit #19, itself documented as
2719 * a "reserved" bit. Best effort attempt to source coherent
2720 * read data here should the balance of the register be
2721 * interpreted by the guest:
2722 *
2723 * L2 cache control register 3: 64GB range, 256KB size,
2724 * enabled, latency 0x1, configured
2725 */
609e36d3 2726 msr_info->data = 0xbe702111;
91c9c3ed 2727 break;
2b036c6b 2728 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2729 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2730 return 1;
609e36d3 2731 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2732 break;
2733 case MSR_AMD64_OSVW_STATUS:
d6321d49 2734 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2735 return 1;
609e36d3 2736 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2737 break;
db2336a8
KH		 2738 case MSR_PLATFORM_INFO:
2739 msr_info->data = vcpu->arch.msr_platform_info;
2740 break;
2741 case MSR_MISC_FEATURES_ENABLES:
2742 msr_info->data = vcpu->arch.msr_misc_features_enables;
2743 break;
15c4a640 2744 default:
c6702c9d 2745 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2746 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2747 if (!ignore_msrs) {
ae0f5499
BD		 2748 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2749 msr_info->index);
ed85c068
AP		 2750 return 1;
2751 } else {
fab0aa3b
EM		 2752 if (report_ignored_msrs)
2753 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2754 msr_info->index);
609e36d3 2755 msr_info->data = 0;
ed85c068
AP		 2756 }
2757 break;
15c4a640 2758 }
15c4a640
CO		 2759 return 0;
2760}
2761EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2762
313a3dc7
CO		 2763/*
2764 * Read or write a bunch of msrs. All parameters are kernel addresses.
2765 *
2766 * @return number of msrs set successfully.
2767 */
2768static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2769 struct kvm_msr_entry *entries,
2770 int (*do_msr)(struct kvm_vcpu *vcpu,
2771 unsigned index, u64 *data))
2772{
801e459a 2773 int i;
313a3dc7 2774
313a3dc7
CO		 2775 for (i = 0; i < msrs->nmsrs; ++i)
2776 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2777 break;
2778
313a3dc7
CO		 2779 return i;
2780}
2781
2782/*
2783 * Read or write a bunch of msrs. Parameters are user addresses.
2784 *
2785 * @return number of msrs set successfully.
2786 */
2787static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2788 int (*do_msr)(struct kvm_vcpu *vcpu,
2789 unsigned index, u64 *data),
2790 int writeback)
2791{
2792 struct kvm_msrs msrs;
2793 struct kvm_msr_entry *entries;
2794 int r, n;
2795 unsigned size;
2796
2797 r = -EFAULT;
2798 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2799 goto out;
2800
2801 r = -E2BIG;
2802 if (msrs.nmsrs >= MAX_IO_MSRS)
2803 goto out;
2804
313a3dc7 2805 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2806 entries = memdup_user(user_msrs->entries, size);
2807 if (IS_ERR(entries)) {
2808 r = PTR_ERR(entries);
313a3dc7 2809 goto out;
ff5c2c03 2810 }
313a3dc7
CO		 2811
2812 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2813 if (r < 0)
2814 goto out_free;
2815
2816 r = -EFAULT;
2817 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2818 goto out_free;
2819
2820 r = n;
2821
2822out_free:
7a73c028 2823 kfree(entries);
313a3dc7
CO		 2824out:
2825 return r;
2826}
2827
4d5422ce
WL		 2828static inline bool kvm_can_mwait_in_guest(void)
2829{
2830 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2831 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2832 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2833}
2834
784aa3d7 2835int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2836{
4d5422ce 2837 int r = 0;
018d00d2
ZX		 2838
2839 switch (ext) {
2840 case KVM_CAP_IRQCHIP:
2841 case KVM_CAP_HLT:
2842 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2843 case KVM_CAP_SET_TSS_ADDR:
07716717 2844 case KVM_CAP_EXT_CPUID:
9c15bb1d 2845 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2846 case KVM_CAP_CLOCKSOURCE:
7837699f 2847 case KVM_CAP_PIT:
a28e4f5a 2848 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2849 case KVM_CAP_MP_STATE:
ed848624 2850 case KVM_CAP_SYNC_MMU:
a355c85c 2851 case KVM_CAP_USER_NMI:
52d939a0 2852 case KVM_CAP_REINJECT_CONTROL:
4925663a 2853 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2854 case KVM_CAP_IOEVENTFD:
f848a5a8 2855 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2856 case KVM_CAP_PIT2:
e9f42757 2857 case KVM_CAP_PIT_STATE2:
b927a3ce 2858 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2859 case KVM_CAP_XEN_HVM:
3cfc3092 2860 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2861 case KVM_CAP_HYPERV:
10388a07 2862 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2863 case KVM_CAP_HYPERV_SPIN:
5c919412 2864 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2865 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2866 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2867 case KVM_CAP_HYPERV_EVENTFD:
ab9f4ecb 2868 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2869 case KVM_CAP_DEBUGREGS:
d2be1651 2870 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2871 case KVM_CAP_XSAVE:
344d9588 2872 case KVM_CAP_ASYNC_PF:
92a1f12d 2873 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2874 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2875 case KVM_CAP_READONLY_MEM:
5f66b620 2876 case KVM_CAP_HYPERV_TIME:
100943c5 2877 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2878 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2879 case KVM_CAP_ENABLE_CAP_VM:
2880 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2881 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2882 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2883 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2884 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2885 r = 1;
2886 break;
01643c51
KH		 2887 case KVM_CAP_SYNC_REGS:
2888 r = KVM_SYNC_X86_VALID_FIELDS;
2889 break;
e3fd9a93
PB		 2890 case KVM_CAP_ADJUST_CLOCK:
2891 r = KVM_CLOCK_TSC_STABLE;
2892 break;
4d5422ce 2893 case KVM_CAP_X86_DISABLE_EXITS:
b31c114b 2894 r |= KVM_X86_DISABLE_EXITS_HTL | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 2895 if(kvm_can_mwait_in_guest())
2896 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 2897 break;
6d396b55
PB		 2898 case KVM_CAP_X86_SMM:
2899 /* SMBASE is usually relocated above 1M on modern chipsets,
2900 * and SMM handlers might indeed rely on 4G segment limits,
2901 * so do not report SMM to be available if real mode is
2902 * emulated via vm86 mode. Still, do not go to great lengths
2903 * to avoid userspace's usage of the feature, because it is a
2904 * fringe case that is not enabled except via specific settings
2905 * of the module parameters.
2906 */
bc226f07 2907 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 2908 break;
774ead3a
AK		 2909 case KVM_CAP_VAPIC:
2910 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2911 break;
f725230a 2912 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2913 r = KVM_SOFT_MAX_VCPUS;
2914 break;
2915 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2916 r = KVM_MAX_VCPUS;
2917 break;
a988b910 2918 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2919 r = KVM_USER_MEM_SLOTS;
a988b910 2920 break;
a68a6a72
MT		 2921 case KVM_CAP_PV_MMU: /* obsolete */
2922 r = 0;
2f333bcb 2923 break;
890ca9ae
HY		 2924 case KVM_CAP_MCE:
2925 r = KVM_MAX_MCE_BANKS;
2926 break;
2d5b5a66 2927 case KVM_CAP_XCRS:
d366bf7e 2928 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2929 break;
92a1f12d
JR		 2930 case KVM_CAP_TSC_CONTROL:
2931 r = kvm_has_tsc_control;
2932 break;
37131313
RK		 2933 case KVM_CAP_X2APIC_API:
2934 r = KVM_X2APIC_API_VALID_FLAGS;
2935 break;
018d00d2 2936 default:
018d00d2
ZX		 2937 break;
2938 }
2939 return r;
2940
2941}
2942
043405e1
CO		 2943long kvm_arch_dev_ioctl(struct file *filp,
2944 unsigned int ioctl, unsigned long arg)
2945{
2946 void __user *argp = (void __user *)arg;
2947 long r;
2948
2949 switch (ioctl) {
2950 case KVM_GET_MSR_INDEX_LIST: {
2951 struct kvm_msr_list __user *user_msr_list = argp;
2952 struct kvm_msr_list msr_list;
2953 unsigned n;
2954
2955 r = -EFAULT;
2956 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2957 goto out;
2958 n = msr_list.nmsrs;
62ef68bb 2959 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2960 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2961 goto out;
2962 r = -E2BIG;
e125e7b6 2963 if (n < msr_list.nmsrs)
043405e1
CO		 2964 goto out;
2965 r = -EFAULT;
2966 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2967 num_msrs_to_save * sizeof(u32)))
2968 goto out;
e125e7b6 2969 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2970 &emulated_msrs,
62ef68bb 2971 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2972 goto out;
2973 r = 0;
2974 break;
2975 }
9c15bb1d
BP		 2976 case KVM_GET_SUPPORTED_CPUID:
2977 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2978 struct kvm_cpuid2 __user *cpuid_arg = argp;
2979 struct kvm_cpuid2 cpuid;
2980
2981 r = -EFAULT;
2982 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2983 goto out;
9c15bb1d
BP		 2984
2985 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2986 ioctl);
674eea0f
AK		 2987 if (r)
2988 goto out;
2989
2990 r = -EFAULT;
2991 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2992 goto out;
2993 r = 0;
2994 break;
2995 }
890ca9ae 2996 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2997 r = -EFAULT;
c45dcc71
AR		 2998 if (copy_to_user(argp, &kvm_mce_cap_supported,
2999 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3000 goto out;
3001 r = 0;
3002 break;
801e459a
TL		 3003 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3004 struct kvm_msr_list __user *user_msr_list = argp;
3005 struct kvm_msr_list msr_list;
3006 unsigned int n;
3007
3008 r = -EFAULT;
3009 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3010 goto out;
3011 n = msr_list.nmsrs;
3012 msr_list.nmsrs = num_msr_based_features;
3013 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3014 goto out;
3015 r = -E2BIG;
3016 if (n < msr_list.nmsrs)
3017 goto out;
3018 r = -EFAULT;
3019 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3020 num_msr_based_features * sizeof(u32)))
3021 goto out;
3022 r = 0;
3023 break;
3024 }
3025 case KVM_GET_MSRS:
3026 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3027 break;
890ca9ae 3028 }
043405e1
CO		 3029 default:
3030 r = -EINVAL;
3031 }
3032out:
3033 return r;
3034}
3035
f5f48ee1
SY		 3036static void wbinvd_ipi(void *garbage)
3037{
3038 wbinvd();
3039}
3040
3041static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3042{
e0f0bbc5 3043 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3044}
3045
313a3dc7
CO		 3046void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3047{
f5f48ee1
SY		 3048 /* Address WBINVD may be executed by guest */
3049 if (need_emulate_wbinvd(vcpu)) {
3050 if (kvm_x86_ops->has_wbinvd_exit())
3051 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3052 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3053 smp_call_function_single(vcpu->cpu,
3054 wbinvd_ipi, NULL, 1);
3055 }
3056
313a3dc7 3057 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3058
0dd6a6ed
ZA		 3059 /* Apply any externally detected TSC adjustments (due to suspend) */
3060 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3061 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3062 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3063 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3064 }
8f6055cb 3065
b0c39dc6 3066 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3067 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3068 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3069 if (tsc_delta < 0)
3070 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3071
b0c39dc6 3072 if (kvm_check_tsc_unstable()) {
07c1419a 3073 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3074 vcpu->arch.last_guest_tsc);
a545ab6a 3075 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3076 vcpu->arch.tsc_catchup = 1;
c285545f 3077 }
a749e247
PB		 3078
3079 if (kvm_lapic_hv_timer_in_use(vcpu))
3080 kvm_lapic_restart_hv_timer(vcpu);
3081
d98d07ca
MT		 3082 /*
3083 * On a host with synchronized TSC, there is no need to update
3084 * kvmclock on vcpu->cpu migration
3085 */
3086 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3087 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3088 if (vcpu->cpu != cpu)
1bd2009e 3089 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3090 vcpu->cpu = cpu;
6b7d7e76 3091 }
c9aaa895 3092
c9aaa895 3093 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3094}
3095
0b9f6c46
PX		 3096static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3097{
3098 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3099 return;
3100
fa55eedd 3101 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3102
4e335d9e 3103 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3104 &vcpu->arch.st.steal.preempted,
3105 offsetof(struct kvm_steal_time, preempted),
3106 sizeof(vcpu->arch.st.steal.preempted));
3107}
3108
313a3dc7
CO		 3109void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3110{
cc0d907c 3111 int idx;
de63ad4c
LM		 3112
3113 if (vcpu->preempted)
3114 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3115
931f261b
AA		 3116 /*
3117 * Disable page faults because we're in atomic context here.
3118 * kvm_write_guest_offset_cached() would call might_fault()
3119 * that relies on pagefault_disable() to tell if there's a
3120 * bug. NOTE: the write to guest memory may not go through if
3121 * during postcopy live migration or if there's heavy guest
3122 * paging.
3123 */
3124 pagefault_disable();
cc0d907c
AA		 3125 /*
3126 * kvm_memslots() will be called by
3127 * kvm_write_guest_offset_cached() so take the srcu lock.
3128 */
3129 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3130 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3131 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3132 pagefault_enable();
02daab21 3133 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3134 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3135 /*
3136 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3137 * on every vmexit, but if not, we might have a stale dr6 from the
3138 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3139 */
3140 set_debugreg(0, 6);
313a3dc7
CO		 3141}
3142
313a3dc7
CO		 3143static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3144 struct kvm_lapic_state *s)
3145{
fa59cc00 3146 if (vcpu->arch.apicv_active)
d62caabb
AS		 3147 kvm_x86_ops->sync_pir_to_irr(vcpu);
3148
a92e2543 3149 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3150}
3151
3152static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3153 struct kvm_lapic_state *s)
3154{
a92e2543
RK		 3155 int r;
3156
3157 r = kvm_apic_set_state(vcpu, s);
3158 if (r)
3159 return r;
cb142eb7 3160 update_cr8_intercept(vcpu);
313a3dc7
CO		 3161
3162 return 0;
3163}
3164
127a457a
MG		 3165static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3166{
3167 return (!lapic_in_kernel(vcpu) ||
3168 kvm_apic_accept_pic_intr(vcpu));
3169}
3170
782d422b
MG		 3171/*
3172 * if userspace requested an interrupt window, check that the
3173 * interrupt window is open.
3174 *
3175 * No need to exit to userspace if we already have an interrupt queued.
3176 */
3177static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3178{
3179 return kvm_arch_interrupt_allowed(vcpu) &&
3180 !kvm_cpu_has_interrupt(vcpu) &&
3181 !kvm_event_needs_reinjection(vcpu) &&
3182 kvm_cpu_accept_dm_intr(vcpu);
3183}
3184
f77bc6a4
ZX		 3185static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3186 struct kvm_interrupt *irq)
3187{
02cdb50f 3188 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3189 return -EINVAL;
1c1a9ce9
SR		 3190
3191 if (!irqchip_in_kernel(vcpu->kvm)) {
3192 kvm_queue_interrupt(vcpu, irq->irq, false);
3193 kvm_make_request(KVM_REQ_EVENT, vcpu);
3194 return 0;
3195 }
3196
3197 /*
3198 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3199 * fail for in-kernel 8259.
3200 */
3201 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3202 return -ENXIO;
f77bc6a4 3203
1c1a9ce9
SR		 3204 if (vcpu->arch.pending_external_vector != -1)
3205 return -EEXIST;
f77bc6a4 3206
1c1a9ce9 3207 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3208 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3209 return 0;
3210}
3211
c4abb7c9
JK		 3212static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3213{
c4abb7c9 3214 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3215
3216 return 0;
3217}
3218
f077825a
PB		 3219static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3220{
64d60670
PB		 3221 kvm_make_request(KVM_REQ_SMI, vcpu);
3222
f077825a
PB		 3223 return 0;
3224}
3225
b209749f
AK		 3226static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3227 struct kvm_tpr_access_ctl *tac)
3228{
3229 if (tac->flags)
3230 return -EINVAL;
3231 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3232 return 0;
3233}
3234
890ca9ae
HY		 3235static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3236 u64 mcg_cap)
3237{
3238 int r;
3239 unsigned bank_num = mcg_cap & 0xff, bank;
3240
3241 r = -EINVAL;
a9e38c3e 3242 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3243 goto out;
c45dcc71 3244 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3245 goto out;
3246 r = 0;
3247 vcpu->arch.mcg_cap = mcg_cap;
3248 /* Init IA32_MCG_CTL to all 1s */
3249 if (mcg_cap & MCG_CTL_P)
3250 vcpu->arch.mcg_ctl = ~(u64)0;
3251 /* Init IA32_MCi_CTL to all 1s */
3252 for (bank = 0; bank < bank_num; bank++)
3253 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3254
3255 if (kvm_x86_ops->setup_mce)
3256 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3257out:
3258 return r;
3259}
3260
3261static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3262 struct kvm_x86_mce *mce)
3263{
3264 u64 mcg_cap = vcpu->arch.mcg_cap;
3265 unsigned bank_num = mcg_cap & 0xff;
3266 u64 *banks = vcpu->arch.mce_banks;
3267
3268 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3269 return -EINVAL;
3270 /*
3271 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3272 * reporting is disabled
3273 */
3274 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3275 vcpu->arch.mcg_ctl != ~(u64)0)
3276 return 0;
3277 banks += 4 * mce->bank;
3278 /*
3279 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3280 * reporting is disabled for the bank
3281 */
3282 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3283 return 0;
3284 if (mce->status & MCI_STATUS_UC) {
3285 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3286 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3287 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3288 return 0;
3289 }
3290 if (banks[1] & MCI_STATUS_VAL)
3291 mce->status |= MCI_STATUS_OVER;
3292 banks[2] = mce->addr;
3293 banks[3] = mce->misc;
3294 vcpu->arch.mcg_status = mce->mcg_status;
3295 banks[1] = mce->status;
3296 kvm_queue_exception(vcpu, MC_VECTOR);
3297 } else if (!(banks[1] & MCI_STATUS_VAL)
3298 || !(banks[1] & MCI_STATUS_UC)) {
3299 if (banks[1] & MCI_STATUS_VAL)
3300 mce->status |= MCI_STATUS_OVER;
3301 banks[2] = mce->addr;
3302 banks[3] = mce->misc;
3303 banks[1] = mce->status;
3304 } else
3305 banks[1] |= MCI_STATUS_OVER;
3306 return 0;
3307}
3308
3cfc3092
JK		 3309static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3310 struct kvm_vcpu_events *events)
3311{
7460fb4a 3312 process_nmi(vcpu);
664f8e26
WL		 3313 /*
3314 * FIXME: pass injected and pending separately. This is only
3315 * needed for nested virtualization, whose state cannot be
3316 * migrated yet. For now we can combine them.
3317 */
03b82a30 3318 events->exception.injected =
664f8e26
WL		 3319 (vcpu->arch.exception.pending ||
3320 vcpu->arch.exception.injected) &&
03b82a30 3321 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3322 events->exception.nr = vcpu->arch.exception.nr;
3323 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3324 events->exception.pad = 0;
3cfc3092
JK		 3325 events->exception.error_code = vcpu->arch.exception.error_code;
3326
03b82a30 3327 events->interrupt.injected =
04140b41 3328 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3329 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3330 events->interrupt.soft = 0;
37ccdcbe 3331 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3332
3333 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3334 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3335 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3336 events->nmi.pad = 0;
3cfc3092 3337
66450a21 3338 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3339
f077825a
PB		 3340 events->smi.smm = is_smm(vcpu);
3341 events->smi.pending = vcpu->arch.smi_pending;
3342 events->smi.smm_inside_nmi =
3343 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3344 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3345
dab4b911 3346 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3347 | KVM_VCPUEVENT_VALID_SHADOW
3348 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3349 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3350}
3351
6ef4e07e
XG		 3352static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3353
3cfc3092
JK		 3354static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3355 struct kvm_vcpu_events *events)
3356{
dab4b911 3357 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3358 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3359 | KVM_VCPUEVENT_VALID_SHADOW
3360 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3361 return -EINVAL;
3362
78e546c8 3363 if (events->exception.injected &&
28d06353
JM		 3364 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3365 is_guest_mode(vcpu)))
78e546c8
PB		 3366 return -EINVAL;
3367
28bf2888
DH		 3368 /* INITs are latched while in SMM */
3369 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3370 (events->smi.smm || events->smi.pending) &&
3371 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3372 return -EINVAL;
3373
7460fb4a 3374 process_nmi(vcpu);
664f8e26 3375 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3376 vcpu->arch.exception.pending = events->exception.injected;
3377 vcpu->arch.exception.nr = events->exception.nr;
3378 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3379 vcpu->arch.exception.error_code = events->exception.error_code;
3380
04140b41 3381 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3382 vcpu->arch.interrupt.nr = events->interrupt.nr;
3383 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3384 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3385 kvm_x86_ops->set_interrupt_shadow(vcpu,
3386 events->interrupt.shadow);
3cfc3092
JK		 3387
3388 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3389 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3390 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3391 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3392
66450a21 3393 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3394 lapic_in_kernel(vcpu))
66450a21 3395 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3396
f077825a 3397 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3398 u32 hflags = vcpu->arch.hflags;
f077825a 3399 if (events->smi.smm)
6ef4e07e 3400 hflags |= HF_SMM_MASK;
f077825a 3401 else
6ef4e07e
XG		 3402 hflags &= ~HF_SMM_MASK;
3403 kvm_set_hflags(vcpu, hflags);
3404
f077825a 3405 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3406
3407 if (events->smi.smm) {
3408 if (events->smi.smm_inside_nmi)
3409 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3410 else
f4ef1910
WL		 3411 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3412 if (lapic_in_kernel(vcpu)) {
3413 if (events->smi.latched_init)
3414 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3415 else
3416 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3417 }
f077825a
PB		 3418 }
3419 }
3420
3842d135
AK		 3421 kvm_make_request(KVM_REQ_EVENT, vcpu);
3422
3cfc3092
JK		 3423 return 0;
3424}
3425
a1efbe77
JK		 3426static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3427 struct kvm_debugregs *dbgregs)
3428{
73aaf249
JK		 3429 unsigned long val;
3430
a1efbe77 3431 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3432 kvm_get_dr(vcpu, 6, &val);
73aaf249 3433 dbgregs->dr6 = val;
a1efbe77
JK		 3434 dbgregs->dr7 = vcpu->arch.dr7;
3435 dbgregs->flags = 0;
97e69aa6 3436 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3437}
3438
3439static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3440 struct kvm_debugregs *dbgregs)
3441{
3442 if (dbgregs->flags)
3443 return -EINVAL;
3444
d14bdb55
PB		 3445 if (dbgregs->dr6 & ~0xffffffffull)
3446 return -EINVAL;
3447 if (dbgregs->dr7 & ~0xffffffffull)
3448 return -EINVAL;
3449
a1efbe77 3450 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3451 kvm_update_dr0123(vcpu);
a1efbe77 3452 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3453 kvm_update_dr6(vcpu);
a1efbe77 3454 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3455 kvm_update_dr7(vcpu);
a1efbe77 3456
a1efbe77
JK		 3457 return 0;
3458}
3459
df1daba7
PB		 3460#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3461
3462static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3463{
c47ada30 3464 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3465 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3466 u64 valid;
3467
3468 /*
3469 * Copy legacy XSAVE area, to avoid complications with CPUID
3470 * leaves 0 and 1 in the loop below.
3471 */
3472 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3473
3474 /* Set XSTATE_BV */
00c87e9a 3475 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3476 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3477
3478 /*
3479 * Copy each region from the possibly compacted offset to the
3480 * non-compacted offset.
3481 */
d91cab78 3482 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3483 while (valid) {
3484 u64 feature = valid & -valid;
3485 int index = fls64(feature) - 1;
3486 void *src = get_xsave_addr(xsave, feature);
3487
3488 if (src) {
3489 u32 size, offset, ecx, edx;
3490 cpuid_count(XSTATE_CPUID, index,
3491 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3492 if (feature == XFEATURE_MASK_PKRU)
3493 memcpy(dest + offset, &vcpu->arch.pkru,
3494 sizeof(vcpu->arch.pkru));
3495 else
3496 memcpy(dest + offset, src, size);
3497
df1daba7
PB		 3498 }
3499
3500 valid -= feature;
3501 }
3502}
3503
3504static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3505{
c47ada30 3506 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3507 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3508 u64 valid;
3509
3510 /*
3511 * Copy legacy XSAVE area, to avoid complications with CPUID
3512 * leaves 0 and 1 in the loop below.
3513 */
3514 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3515
3516 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3517 xsave->header.xfeatures = xstate_bv;
782511b0 3518 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3519 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3520
3521 /*
3522 * Copy each region from the non-compacted offset to the
3523 * possibly compacted offset.
3524 */
d91cab78 3525 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3526 while (valid) {
3527 u64 feature = valid & -valid;
3528 int index = fls64(feature) - 1;
3529 void *dest = get_xsave_addr(xsave, feature);
3530
3531 if (dest) {
3532 u32 size, offset, ecx, edx;
3533 cpuid_count(XSTATE_CPUID, index,
3534 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3535 if (feature == XFEATURE_MASK_PKRU)
3536 memcpy(&vcpu->arch.pkru, src + offset,
3537 sizeof(vcpu->arch.pkru));
3538 else
3539 memcpy(dest, src + offset, size);
ee4100da 3540 }
df1daba7
PB		 3541
3542 valid -= feature;
3543 }
3544}
3545
2d5b5a66
SY		 3546static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3547 struct kvm_xsave *guest_xsave)
3548{
d366bf7e 3549 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3550 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3551 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3552 } else {
2d5b5a66 3553 memcpy(guest_xsave->region,
7366ed77 3554 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3555 sizeof(struct fxregs_state));
2d5b5a66 3556 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3557 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3558 }
3559}
3560
a575813b
WL		 3561#define XSAVE_MXCSR_OFFSET 24
3562
2d5b5a66
SY		 3563static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3564 struct kvm_xsave *guest_xsave)
3565{
3566 u64 xstate_bv =
3567 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3568 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3569
d366bf7e 3570 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3571 /*
3572 * Here we allow setting states that are not present in
3573 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3574 * with old userspace.
3575 */
a575813b
WL		 3576 if (xstate_bv & ~kvm_supported_xcr0() ||
3577 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3578 return -EINVAL;
df1daba7 3579 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3580 } else {
a575813b
WL		 3581 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3582 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3583 return -EINVAL;
7366ed77 3584 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3585 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3586 }
3587 return 0;
3588}
3589
3590static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3591 struct kvm_xcrs *guest_xcrs)
3592{
d366bf7e 3593 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3594 guest_xcrs->nr_xcrs = 0;
3595 return;
3596 }
3597
3598 guest_xcrs->nr_xcrs = 1;
3599 guest_xcrs->flags = 0;
3600 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3601 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3602}
3603
3604static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3605 struct kvm_xcrs *guest_xcrs)
3606{
3607 int i, r = 0;
3608
d366bf7e 3609 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3610 return -EINVAL;
3611
3612 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3613 return -EINVAL;
3614
3615 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3616 /* Only support XCR0 currently */
c67a04cb 3617 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3618 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3619 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3620 break;
3621 }
3622 if (r)
3623 r = -EINVAL;
3624 return r;
3625}
3626
1c0b28c2
EM		 3627/*
3628 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3629 * stopped by the hypervisor. This function will be called from the host only.
3630 * EINVAL is returned when the host attempts to set the flag for a guest that
3631 * does not support pv clocks.
3632 */
3633static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3634{
0b79459b 3635 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3636 return -EINVAL;
51d59c6b 3637 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3638 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3639 return 0;
3640}
3641
5c919412
AS		 3642static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3643 struct kvm_enable_cap *cap)
3644{
3645 if (cap->flags)
3646 return -EINVAL;
3647
3648 switch (cap->cap) {
efc479e6
RK		 3649 case KVM_CAP_HYPERV_SYNIC2:
3650 if (cap->args[0])
3651 return -EINVAL;
5c919412 3652 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3653 if (!irqchip_in_kernel(vcpu->kvm))
3654 return -EINVAL;
efc479e6
RK		 3655 return kvm_hv_activate_synic(vcpu, cap->cap ==
3656 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3657 default:
3658 return -EINVAL;
3659 }
3660}
3661
313a3dc7
CO		 3662long kvm_arch_vcpu_ioctl(struct file *filp,
3663 unsigned int ioctl, unsigned long arg)
3664{
3665 struct kvm_vcpu *vcpu = filp->private_data;
3666 void __user *argp = (void __user *)arg;
3667 int r;
d1ac91d8
AK		 3668 union {
3669 struct kvm_lapic_state *lapic;
3670 struct kvm_xsave *xsave;
3671 struct kvm_xcrs *xcrs;
3672 void *buffer;
3673 } u;
3674
9b062471
CD		 3675 vcpu_load(vcpu);
3676
d1ac91d8 3677 u.buffer = NULL;
313a3dc7
CO		 3678 switch (ioctl) {
3679 case KVM_GET_LAPIC: {
2204ae3c 3680 r = -EINVAL;
bce87cce 3681 if (!lapic_in_kernel(vcpu))
2204ae3c 3682 goto out;
d1ac91d8 3683 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3684
b772ff36 3685 r = -ENOMEM;
d1ac91d8 3686 if (!u.lapic)
b772ff36 3687 goto out;
d1ac91d8 3688 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3689 if (r)
3690 goto out;
3691 r = -EFAULT;
d1ac91d8 3692 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3693 goto out;
3694 r = 0;
3695 break;
3696 }
3697 case KVM_SET_LAPIC: {
2204ae3c 3698 r = -EINVAL;
bce87cce 3699 if (!lapic_in_kernel(vcpu))
2204ae3c 3700 goto out;
ff5c2c03 3701 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3702 if (IS_ERR(u.lapic)) {
3703 r = PTR_ERR(u.lapic);
3704 goto out_nofree;
3705 }
ff5c2c03 3706
d1ac91d8 3707 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3708 break;
3709 }
f77bc6a4
ZX		 3710 case KVM_INTERRUPT: {
3711 struct kvm_interrupt irq;
3712
3713 r = -EFAULT;
3714 if (copy_from_user(&irq, argp, sizeof irq))
3715 goto out;
3716 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3717 break;
3718 }
c4abb7c9
JK		 3719 case KVM_NMI: {
3720 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3721 break;
3722 }
f077825a
PB		 3723 case KVM_SMI: {
3724 r = kvm_vcpu_ioctl_smi(vcpu);
3725 break;
3726 }
313a3dc7
CO		 3727 case KVM_SET_CPUID: {
3728 struct kvm_cpuid __user *cpuid_arg = argp;
3729 struct kvm_cpuid cpuid;
3730
3731 r = -EFAULT;
3732 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3733 goto out;
3734 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3735 break;
3736 }
07716717
DK		 3737 case KVM_SET_CPUID2: {
3738 struct kvm_cpuid2 __user *cpuid_arg = argp;
3739 struct kvm_cpuid2 cpuid;
3740
3741 r = -EFAULT;
3742 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3743 goto out;
3744 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3745 cpuid_arg->entries);
07716717
DK		 3746 break;
3747 }
3748 case KVM_GET_CPUID2: {
3749 struct kvm_cpuid2 __user *cpuid_arg = argp;
3750 struct kvm_cpuid2 cpuid;
3751
3752 r = -EFAULT;
3753 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3754 goto out;
3755 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3756 cpuid_arg->entries);
07716717
DK		 3757 if (r)
3758 goto out;
3759 r = -EFAULT;
3760 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3761 goto out;
3762 r = 0;
3763 break;
3764 }
801e459a
TL		 3765 case KVM_GET_MSRS: {
3766 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3767 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3768 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3769 break;
801e459a
TL		 3770 }
3771 case KVM_SET_MSRS: {
3772 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3773 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3774 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3775 break;
801e459a 3776 }
b209749f
AK		 3777 case KVM_TPR_ACCESS_REPORTING: {
3778 struct kvm_tpr_access_ctl tac;
3779
3780 r = -EFAULT;
3781 if (copy_from_user(&tac, argp, sizeof tac))
3782 goto out;
3783 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3784 if (r)
3785 goto out;
3786 r = -EFAULT;
3787 if (copy_to_user(argp, &tac, sizeof tac))
3788 goto out;
3789 r = 0;
3790 break;
3791 };
b93463aa
AK		 3792 case KVM_SET_VAPIC_ADDR: {
3793 struct kvm_vapic_addr va;
7301d6ab 3794 int idx;
b93463aa
AK		 3795
3796 r = -EINVAL;
35754c98 3797 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3798 goto out;
3799 r = -EFAULT;
3800 if (copy_from_user(&va, argp, sizeof va))
3801 goto out;
7301d6ab 3802 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3803 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3804 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3805 break;
3806 }
890ca9ae
HY		 3807 case KVM_X86_SETUP_MCE: {
3808 u64 mcg_cap;
3809
3810 r = -EFAULT;
3811 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3812 goto out;
3813 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3814 break;
3815 }
3816 case KVM_X86_SET_MCE: {
3817 struct kvm_x86_mce mce;
3818
3819 r = -EFAULT;
3820 if (copy_from_user(&mce, argp, sizeof mce))
3821 goto out;
3822 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3823 break;
3824 }
3cfc3092
JK		 3825 case KVM_GET_VCPU_EVENTS: {
3826 struct kvm_vcpu_events events;
3827
3828 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3829
3830 r = -EFAULT;
3831 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3832 break;
3833 r = 0;
3834 break;
3835 }
3836 case KVM_SET_VCPU_EVENTS: {
3837 struct kvm_vcpu_events events;
3838
3839 r = -EFAULT;
3840 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3841 break;
3842
3843 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3844 break;
3845 }
a1efbe77
JK		 3846 case KVM_GET_DEBUGREGS: {
3847 struct kvm_debugregs dbgregs;
3848
3849 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3850
3851 r = -EFAULT;
3852 if (copy_to_user(argp, &dbgregs,
3853 sizeof(struct kvm_debugregs)))
3854 break;
3855 r = 0;
3856 break;
3857 }
3858 case KVM_SET_DEBUGREGS: {
3859 struct kvm_debugregs dbgregs;
3860
3861 r = -EFAULT;
3862 if (copy_from_user(&dbgregs, argp,
3863 sizeof(struct kvm_debugregs)))
3864 break;
3865
3866 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3867 break;
3868 }
2d5b5a66 3869 case KVM_GET_XSAVE: {
d1ac91d8 3870 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3871 r = -ENOMEM;
d1ac91d8 3872 if (!u.xsave)
2d5b5a66
SY		 3873 break;
3874
d1ac91d8 3875 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3876
3877 r = -EFAULT;
d1ac91d8 3878 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3879 break;
3880 r = 0;
3881 break;
3882 }
3883 case KVM_SET_XSAVE: {
ff5c2c03 3884 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3885 if (IS_ERR(u.xsave)) {
3886 r = PTR_ERR(u.xsave);
3887 goto out_nofree;
3888 }
2d5b5a66 3889
d1ac91d8 3890 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3891 break;
3892 }
3893 case KVM_GET_XCRS: {
d1ac91d8 3894 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3895 r = -ENOMEM;
d1ac91d8 3896 if (!u.xcrs)
2d5b5a66
SY		 3897 break;
3898
d1ac91d8 3899 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3900
3901 r = -EFAULT;
d1ac91d8 3902 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3903 sizeof(struct kvm_xcrs)))
3904 break;
3905 r = 0;
3906 break;
3907 }
3908 case KVM_SET_XCRS: {
ff5c2c03 3909 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3910 if (IS_ERR(u.xcrs)) {
3911 r = PTR_ERR(u.xcrs);
3912 goto out_nofree;
3913 }
2d5b5a66 3914
d1ac91d8 3915 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3916 break;
3917 }
92a1f12d
JR		 3918 case KVM_SET_TSC_KHZ: {
3919 u32 user_tsc_khz;
3920
3921 r = -EINVAL;
92a1f12d
JR		 3922 user_tsc_khz = (u32)arg;
3923
3924 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3925 goto out;
3926
cc578287
ZA		 3927 if (user_tsc_khz == 0)
3928 user_tsc_khz = tsc_khz;
3929
381d585c
HZ		 3930 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3931 r = 0;
92a1f12d 3932
92a1f12d
JR		 3933 goto out;
3934 }
3935 case KVM_GET_TSC_KHZ: {
cc578287 3936 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3937 goto out;
3938 }
1c0b28c2
EM		 3939 case KVM_KVMCLOCK_CTRL: {
3940 r = kvm_set_guest_paused(vcpu);
3941 goto out;
3942 }
5c919412
AS		 3943 case KVM_ENABLE_CAP: {
3944 struct kvm_enable_cap cap;
3945
3946 r = -EFAULT;
3947 if (copy_from_user(&cap, argp, sizeof(cap)))
3948 goto out;
3949 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3950 break;
3951 }
313a3dc7
CO		 3952 default:
3953 r = -EINVAL;
3954 }
3955out:
d1ac91d8 3956 kfree(u.buffer);
9b062471
CD		 3957out_nofree:
3958 vcpu_put(vcpu);
313a3dc7
CO		 3959 return r;
3960}
3961
5b1c1493
CO		 3962int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3963{
3964 return VM_FAULT_SIGBUS;
3965}
3966
1fe779f8
CO		 3967static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3968{
3969 int ret;
3970
3971 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3972 return -EINVAL;
1fe779f8
CO		 3973 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3974 return ret;
3975}
3976
b927a3ce
SY		 3977static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3978 u64 ident_addr)
3979{
2ac52ab8 3980 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3981}
3982
1fe779f8
CO		 3983static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3984 u32 kvm_nr_mmu_pages)
3985{
3986 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3987 return -EINVAL;
3988
79fac95e 3989 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3990
3991 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3992 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3993
79fac95e 3994 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3995 return 0;
3996}
3997
3998static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3999{
39de71ec 4000 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4001}
4002
1fe779f8
CO		 4003static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4004{
90bca052 4005 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4006 int r;
4007
4008 r = 0;
4009 switch (chip->chip_id) {
4010 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4011 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4012 sizeof(struct kvm_pic_state));
4013 break;
4014 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4015 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4016 sizeof(struct kvm_pic_state));
4017 break;
4018 case KVM_IRQCHIP_IOAPIC:
33392b49 4019 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4020 break;
4021 default:
4022 r = -EINVAL;
4023 break;
4024 }
4025 return r;
4026}
4027
4028static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4029{
90bca052 4030 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4031 int r;
4032
4033 r = 0;
4034 switch (chip->chip_id) {
4035 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4036 spin_lock(&pic->lock);
4037 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4038 sizeof(struct kvm_pic_state));
90bca052 4039 spin_unlock(&pic->lock);
1fe779f8
CO		 4040 break;
4041 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4042 spin_lock(&pic->lock);
4043 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4044 sizeof(struct kvm_pic_state));
90bca052 4045 spin_unlock(&pic->lock);
1fe779f8
CO		 4046 break;
4047 case KVM_IRQCHIP_IOAPIC:
33392b49 4048 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4049 break;
4050 default:
4051 r = -EINVAL;
4052 break;
4053 }
90bca052 4054 kvm_pic_update_irq(pic);
1fe779f8
CO		 4055 return r;
4056}
4057
e0f63cb9
SY		 4058static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4059{
34f3941c
RK		 4060 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4061
4062 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4063
4064 mutex_lock(&kps->lock);
4065 memcpy(ps, &kps->channels, sizeof(*ps));
4066 mutex_unlock(&kps->lock);
2da29bcc 4067 return 0;
e0f63cb9
SY		 4068}
4069
4070static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4071{
0185604c 4072 int i;
09edea72
RK		 4073 struct kvm_pit *pit = kvm->arch.vpit;
4074
4075 mutex_lock(&pit->pit_state.lock);
34f3941c 4076 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4077 for (i = 0; i < 3; i++)
09edea72
RK		 4078 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4079 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4080 return 0;
e9f42757
BK		 4081}
4082
4083static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4084{
e9f42757
BK		 4085 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4086 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4087 sizeof(ps->channels));
4088 ps->flags = kvm->arch.vpit->pit_state.flags;
4089 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4090 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4091 return 0;
e9f42757
BK		 4092}
4093
4094static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4095{
2da29bcc 4096 int start = 0;
0185604c 4097 int i;
e9f42757 4098 u32 prev_legacy, cur_legacy;
09edea72
RK		 4099 struct kvm_pit *pit = kvm->arch.vpit;
4100
4101 mutex_lock(&pit->pit_state.lock);
4102 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4103 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4104 if (!prev_legacy && cur_legacy)
4105 start = 1;
09edea72
RK		 4106 memcpy(&pit->pit_state.channels, &ps->channels,
4107 sizeof(pit->pit_state.channels));
4108 pit->pit_state.flags = ps->flags;
0185604c 4109 for (i = 0; i < 3; i++)
09edea72 4110 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4111 start && i == 0);
09edea72 4112 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4113 return 0;
e0f63cb9
SY		 4114}
4115
52d939a0
MT		 4116static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4117 struct kvm_reinject_control *control)
4118{
71474e2f
RK		 4119 struct kvm_pit *pit = kvm->arch.vpit;
4120
4121 if (!pit)
52d939a0 4122 return -ENXIO;
b39c90b6 4123
71474e2f
RK		 4124 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4125 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4126 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4127 */
4128 mutex_lock(&pit->pit_state.lock);
4129 kvm_pit_set_reinject(pit, control->pit_reinject);
4130 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4131
52d939a0
MT		 4132 return 0;
4133}
4134
95d4c16c 4135/**
60c34612
TY		 4136 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4137 * @kvm: kvm instance
4138 * @log: slot id and address to which we copy the log
95d4c16c 4139 *
e108ff2f
PB		 4140 * Steps 1-4 below provide general overview of dirty page logging. See
4141 * kvm_get_dirty_log_protect() function description for additional details.
4142 *
4143 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4144 * always flush the TLB (step 4) even if previous step failed and the dirty
4145 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4146 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4147 * writes will be marked dirty for next log read.
95d4c16c 4148 *
60c34612
TY		 4149 * 1. Take a snapshot of the bit and clear it if needed.
4150 * 2. Write protect the corresponding page.
e108ff2f
PB		 4151 * 3. Copy the snapshot to the userspace.
4152 * 4. Flush TLB's if needed.
5bb064dc 4153 */
60c34612 4154int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4155{
60c34612 4156 bool is_dirty = false;
e108ff2f 4157 int r;
5bb064dc 4158
79fac95e 4159 mutex_lock(&kvm->slots_lock);
5bb064dc 4160
88178fd4
KH		 4161 /*
4162 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4163 */
4164 if (kvm_x86_ops->flush_log_dirty)
4165 kvm_x86_ops->flush_log_dirty(kvm);
4166
e108ff2f 4167 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4168
4169 /*
4170 * All the TLBs can be flushed out of mmu lock, see the comments in
4171 * kvm_mmu_slot_remove_write_access().
4172 */
e108ff2f 4173 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4174 if (is_dirty)
4175 kvm_flush_remote_tlbs(kvm);
4176
79fac95e 4177 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4178 return r;
4179}
4180
aa2fbe6d
YZ		 4181int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4182 bool line_status)
23d43cf9
CD		 4183{
4184 if (!irqchip_in_kernel(kvm))
4185 return -ENXIO;
4186
4187 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4188 irq_event->irq, irq_event->level,
4189 line_status);
23d43cf9
CD		 4190 return 0;
4191}
4192
90de4a18
NA		 4193static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4194 struct kvm_enable_cap *cap)
4195{
4196 int r;
4197
4198 if (cap->flags)
4199 return -EINVAL;
4200
4201 switch (cap->cap) {
4202 case KVM_CAP_DISABLE_QUIRKS:
4203 kvm->arch.disabled_quirks = cap->args[0];
4204 r = 0;
4205 break;
49df6397
SR		 4206 case KVM_CAP_SPLIT_IRQCHIP: {
4207 mutex_lock(&kvm->lock);
b053b2ae
SR		 4208 r = -EINVAL;
4209 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4210 goto split_irqchip_unlock;
49df6397
SR		 4211 r = -EEXIST;
4212 if (irqchip_in_kernel(kvm))
4213 goto split_irqchip_unlock;
557abc40 4214 if (kvm->created_vcpus)
49df6397
SR		 4215 goto split_irqchip_unlock;
4216 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4217 if (r)
49df6397
SR		 4218 goto split_irqchip_unlock;
4219 /* Pairs with irqchip_in_kernel. */
4220 smp_wmb();
49776faf 4221 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4222 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4223 r = 0;
4224split_irqchip_unlock:
4225 mutex_unlock(&kvm->lock);
4226 break;
4227 }
37131313
RK		 4228 case KVM_CAP_X2APIC_API:
4229 r = -EINVAL;
4230 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4231 break;
4232
4233 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4234 kvm->arch.x2apic_format = true;
c519265f
RK		 4235 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4236 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4237
4238 r = 0;
4239 break;
4d5422ce
WL		 4240 case KVM_CAP_X86_DISABLE_EXITS:
4241 r = -EINVAL;
4242 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4243 break;
4244
4245 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4246 kvm_can_mwait_in_guest())
4247 kvm->arch.mwait_in_guest = true;
caa057a2
WL		 4248 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HTL)
4249 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4250 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4251 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4252 r = 0;
4253 break;
90de4a18
NA		 4254 default:
4255 r = -EINVAL;
4256 break;
4257 }
4258 return r;
4259}
4260
1fe779f8
CO		 4261long kvm_arch_vm_ioctl(struct file *filp,
4262 unsigned int ioctl, unsigned long arg)
4263{
4264 struct kvm *kvm = filp->private_data;
4265 void __user *argp = (void __user *)arg;
367e1319 4266 int r = -ENOTTY;
f0d66275
DH		 4267 /*
4268 * This union makes it completely explicit to gcc-3.x
4269 * that these two variables' stack usage should be
4270 * combined, not added together.
4271 */
4272 union {
4273 struct kvm_pit_state ps;
e9f42757 4274 struct kvm_pit_state2 ps2;
c5ff41ce 4275 struct kvm_pit_config pit_config;
f0d66275 4276 } u;
1fe779f8
CO		 4277
4278 switch (ioctl) {
4279 case KVM_SET_TSS_ADDR:
4280 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4281 break;
b927a3ce
SY		 4282 case KVM_SET_IDENTITY_MAP_ADDR: {
4283 u64 ident_addr;
4284
1af1ac91
DH		 4285 mutex_lock(&kvm->lock);
4286 r = -EINVAL;
4287 if (kvm->created_vcpus)
4288 goto set_identity_unlock;
b927a3ce
SY		 4289 r = -EFAULT;
4290 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4291 goto set_identity_unlock;
b927a3ce 4292 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4293set_identity_unlock:
4294 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4295 break;
4296 }
1fe779f8
CO		 4297 case KVM_SET_NR_MMU_PAGES:
4298 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4299 break;
4300 case KVM_GET_NR_MMU_PAGES:
4301 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4302 break;
3ddea128 4303 case KVM_CREATE_IRQCHIP: {
3ddea128 4304 mutex_lock(&kvm->lock);
09941366 4305
3ddea128 4306 r = -EEXIST;
35e6eaa3 4307 if (irqchip_in_kernel(kvm))
3ddea128 4308 goto create_irqchip_unlock;
09941366 4309
3e515705 4310 r = -EINVAL;
557abc40 4311 if (kvm->created_vcpus)
3e515705 4312 goto create_irqchip_unlock;
09941366
RK		 4313
4314 r = kvm_pic_init(kvm);
4315 if (r)
3ddea128 4316 goto create_irqchip_unlock;
09941366
RK		 4317
4318 r = kvm_ioapic_init(kvm);
4319 if (r) {
09941366 4320 kvm_pic_destroy(kvm);
3ddea128 4321 goto create_irqchip_unlock;
09941366
RK		 4322 }
4323
399ec807
AK		 4324 r = kvm_setup_default_irq_routing(kvm);
4325 if (r) {
72bb2fcd 4326 kvm_ioapic_destroy(kvm);
09941366 4327 kvm_pic_destroy(kvm);
71ba994c 4328 goto create_irqchip_unlock;
399ec807 4329 }
49776faf 4330 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4331 smp_wmb();
49776faf 4332 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4333 create_irqchip_unlock:
4334 mutex_unlock(&kvm->lock);
1fe779f8 4335 break;
3ddea128 4336 }
7837699f 4337 case KVM_CREATE_PIT:
c5ff41ce
JK		 4338 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4339 goto create_pit;
4340 case KVM_CREATE_PIT2:
4341 r = -EFAULT;
4342 if (copy_from_user(&u.pit_config, argp,
4343 sizeof(struct kvm_pit_config)))
4344 goto out;
4345 create_pit:
250715a6 4346 mutex_lock(&kvm->lock);
269e05e4
AK		 4347 r = -EEXIST;
4348 if (kvm->arch.vpit)
4349 goto create_pit_unlock;
7837699f 4350 r = -ENOMEM;
c5ff41ce 4351 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4352 if (kvm->arch.vpit)
4353 r = 0;
269e05e4 4354 create_pit_unlock:
250715a6 4355 mutex_unlock(&kvm->lock);
7837699f 4356 break;
1fe779f8
CO		 4357 case KVM_GET_IRQCHIP: {
4358 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4359 struct kvm_irqchip *chip;
1fe779f8 4360
ff5c2c03
SL		 4361 chip = memdup_user(argp, sizeof(*chip));
4362 if (IS_ERR(chip)) {
4363 r = PTR_ERR(chip);
1fe779f8 4364 goto out;
ff5c2c03
SL		 4365 }
4366
1fe779f8 4367 r = -ENXIO;
826da321 4368 if (!irqchip_kernel(kvm))
f0d66275
DH		 4369 goto get_irqchip_out;
4370 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4371 if (r)
f0d66275 4372 goto get_irqchip_out;
1fe779f8 4373 r = -EFAULT;
f0d66275
DH		 4374 if (copy_to_user(argp, chip, sizeof *chip))
4375 goto get_irqchip_out;
1fe779f8 4376 r = 0;
f0d66275
DH		 4377 get_irqchip_out:
4378 kfree(chip);
1fe779f8
CO		 4379 break;
4380 }
4381 case KVM_SET_IRQCHIP: {
4382 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4383 struct kvm_irqchip *chip;
1fe779f8 4384
ff5c2c03
SL		 4385 chip = memdup_user(argp, sizeof(*chip));
4386 if (IS_ERR(chip)) {
4387 r = PTR_ERR(chip);
1fe779f8 4388 goto out;
ff5c2c03
SL		 4389 }
4390
1fe779f8 4391 r = -ENXIO;
826da321 4392 if (!irqchip_kernel(kvm))
f0d66275
DH		 4393 goto set_irqchip_out;
4394 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4395 if (r)
f0d66275 4396 goto set_irqchip_out;
1fe779f8 4397 r = 0;
f0d66275
DH		 4398 set_irqchip_out:
4399 kfree(chip);
1fe779f8
CO		 4400 break;
4401 }
e0f63cb9 4402 case KVM_GET_PIT: {
e0f63cb9 4403 r = -EFAULT;
f0d66275 4404 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4405 goto out;
4406 r = -ENXIO;
4407 if (!kvm->arch.vpit)
4408 goto out;
f0d66275 4409 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4410 if (r)
4411 goto out;
4412 r = -EFAULT;
f0d66275 4413 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4414 goto out;
4415 r = 0;
4416 break;
4417 }
4418 case KVM_SET_PIT: {
e0f63cb9 4419 r = -EFAULT;
f0d66275 4420 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4421 goto out;
4422 r = -ENXIO;
4423 if (!kvm->arch.vpit)
4424 goto out;
f0d66275 4425 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4426 break;
4427 }
e9f42757
BK		 4428 case KVM_GET_PIT2: {
4429 r = -ENXIO;
4430 if (!kvm->arch.vpit)
4431 goto out;
4432 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4433 if (r)
4434 goto out;
4435 r = -EFAULT;
4436 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4437 goto out;
4438 r = 0;
4439 break;
4440 }
4441 case KVM_SET_PIT2: {
4442 r = -EFAULT;
4443 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4444 goto out;
4445 r = -ENXIO;
4446 if (!kvm->arch.vpit)
4447 goto out;
4448 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4449 break;
4450 }
52d939a0
MT		 4451 case KVM_REINJECT_CONTROL: {
4452 struct kvm_reinject_control control;
4453 r = -EFAULT;
4454 if (copy_from_user(&control, argp, sizeof(control)))
4455 goto out;
4456 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4457 break;
4458 }
d71ba788
PB		 4459 case KVM_SET_BOOT_CPU_ID:
4460 r = 0;
4461 mutex_lock(&kvm->lock);
557abc40 4462 if (kvm->created_vcpus)
d71ba788
PB		 4463 r = -EBUSY;
4464 else
4465 kvm->arch.bsp_vcpu_id = arg;
4466 mutex_unlock(&kvm->lock);
4467 break;
ffde22ac 4468 case KVM_XEN_HVM_CONFIG: {
51776043 4469 struct kvm_xen_hvm_config xhc;
ffde22ac 4470 r = -EFAULT;
51776043 4471 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4472 goto out;
4473 r = -EINVAL;
51776043 4474 if (xhc.flags)
ffde22ac 4475 goto out;
51776043 4476 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4477 r = 0;
4478 break;
4479 }
afbcf7ab 4480 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4481 struct kvm_clock_data user_ns;
4482 u64 now_ns;
afbcf7ab
GC		 4483
4484 r = -EFAULT;
4485 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4486 goto out;
4487
4488 r = -EINVAL;
4489 if (user_ns.flags)
4490 goto out;
4491
4492 r = 0;
0bc48bea
RK		 4493 /*
4494 * TODO: userspace has to take care of races with VCPU_RUN, so
4495 * kvm_gen_update_masterclock() can be cut down to locked
4496 * pvclock_update_vm_gtod_copy().
4497 */
4498 kvm_gen_update_masterclock(kvm);
e891a32e 4499 now_ns = get_kvmclock_ns(kvm);
108b249c 4500 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4501 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4502 break;
4503 }
4504 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4505 struct kvm_clock_data user_ns;
4506 u64 now_ns;
4507
e891a32e 4508 now_ns = get_kvmclock_ns(kvm);
108b249c 4509 user_ns.clock = now_ns;
e3fd9a93 4510 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4511 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4512
4513 r = -EFAULT;
4514 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4515 goto out;
4516 r = 0;
4517 break;
4518 }
90de4a18
NA		 4519 case KVM_ENABLE_CAP: {
4520 struct kvm_enable_cap cap;
afbcf7ab 4521
90de4a18
NA		 4522 r = -EFAULT;
4523 if (copy_from_user(&cap, argp, sizeof(cap)))
4524 goto out;
4525 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4526 break;
4527 }
5acc5c06
BS		 4528 case KVM_MEMORY_ENCRYPT_OP: {
4529 r = -ENOTTY;
4530 if (kvm_x86_ops->mem_enc_op)
4531 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4532 break;
4533 }
69eaedee
BS		 4534 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4535 struct kvm_enc_region region;
4536
4537 r = -EFAULT;
4538 if (copy_from_user(&region, argp, sizeof(region)))
4539 goto out;
4540
4541 r = -ENOTTY;
4542 if (kvm_x86_ops->mem_enc_reg_region)
4543 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4544 break;
4545 }
4546 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4547 struct kvm_enc_region region;
4548
4549 r = -EFAULT;
4550 if (copy_from_user(&region, argp, sizeof(region)))
4551 goto out;
4552
4553 r = -ENOTTY;
4554 if (kvm_x86_ops->mem_enc_unreg_region)
4555 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4556 break;
4557 }
faeb7833
RK		 4558 case KVM_HYPERV_EVENTFD: {
4559 struct kvm_hyperv_eventfd hvevfd;
4560
4561 r = -EFAULT;
4562 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4563 goto out;
4564 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4565 break;
4566 }
1fe779f8 4567 default:
ad6260da 4568 r = -ENOTTY;
1fe779f8
CO		 4569 }
4570out:
4571 return r;
4572}
4573
a16b043c 4574static void kvm_init_msr_list(void)
043405e1
CO		 4575{
4576 u32 dummy[2];
4577 unsigned i, j;
4578
62ef68bb 4579 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4580 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4581 continue;
93c4adc7
PB		 4582
4583 /*
4584 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4585 * to the guests in some cases.
93c4adc7
PB		 4586 */
4587 switch (msrs_to_save[i]) {
4588 case MSR_IA32_BNDCFGS:
4589 if (!kvm_x86_ops->mpx_supported())
4590 continue;
4591 break;
9dbe6cf9
PB		 4592 case MSR_TSC_AUX:
4593 if (!kvm_x86_ops->rdtscp_supported())
4594 continue;
4595 break;
93c4adc7
PB		 4596 default:
4597 break;
4598 }
4599
043405e1
CO		 4600 if (j < i)
4601 msrs_to_save[j] = msrs_to_save[i];
4602 j++;
4603 }
4604 num_msrs_to_save = j;
62ef68bb
PB		 4605
4606 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4607 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4608 continue;
62ef68bb
PB		 4609
4610 if (j < i)
4611 emulated_msrs[j] = emulated_msrs[i];
4612 j++;
4613 }
4614 num_emulated_msrs = j;
801e459a
TL		 4615
4616 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4617 struct kvm_msr_entry msr;
4618
4619 msr.index = msr_based_features[i];
66421c1e 4620 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4621 continue;
4622
4623 if (j < i)
4624 msr_based_features[j] = msr_based_features[i];
4625 j++;
4626 }
4627 num_msr_based_features = j;
043405e1
CO		 4628}
4629
bda9020e
MT		 4630static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4631 const void *v)
bbd9b64e 4632{
70252a10
AK		 4633 int handled = 0;
4634 int n;
4635
4636 do {
4637 n = min(len, 8);
bce87cce 4638 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4639 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4640 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4641 break;
4642 handled += n;
4643 addr += n;
4644 len -= n;
4645 v += n;
4646 } while (len);
bbd9b64e 4647
70252a10 4648 return handled;
bbd9b64e
CO		 4649}
4650
bda9020e 4651static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4652{
70252a10
AK		 4653 int handled = 0;
4654 int n;
4655
4656 do {
4657 n = min(len, 8);
bce87cce 4658 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4659 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4660 addr, n, v))
4661 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4662 break;
e39d200f 4663 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4664 handled += n;
4665 addr += n;
4666 len -= n;
4667 v += n;
4668 } while (len);
bbd9b64e 4669
70252a10 4670 return handled;
bbd9b64e
CO		 4671}
4672
2dafc6c2
GN		 4673static void kvm_set_segment(struct kvm_vcpu *vcpu,
4674 struct kvm_segment *var, int seg)
4675{
4676 kvm_x86_ops->set_segment(vcpu, var, seg);
4677}
4678
4679void kvm_get_segment(struct kvm_vcpu *vcpu,
4680 struct kvm_segment *var, int seg)
4681{
4682 kvm_x86_ops->get_segment(vcpu, var, seg);
4683}
4684
54987b7a
PB		 4685gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4686 struct x86_exception *exception)
02f59dc9
JR		 4687{
4688 gpa_t t_gpa;
02f59dc9
JR		 4689
4690 BUG_ON(!mmu_is_nested(vcpu));
4691
4692 /* NPT walks are always user-walks */
4693 access |= PFERR_USER_MASK;
54987b7a 4694 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4695
4696 return t_gpa;
4697}
4698
ab9ae313
AK		 4699gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4700 struct x86_exception *exception)
1871c602
GN		 4701{
4702 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4703 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4704}
4705
ab9ae313
AK		 4706 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4707 struct x86_exception *exception)
1871c602
GN		 4708{
4709 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4710 access |= PFERR_FETCH_MASK;
ab9ae313 4711 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4712}
4713
ab9ae313
AK		 4714gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4715 struct x86_exception *exception)
1871c602
GN		 4716{
4717 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4718 access |= PFERR_WRITE_MASK;
ab9ae313 4719 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4720}
4721
4722/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4723gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4724 struct x86_exception *exception)
1871c602 4725{
ab9ae313 4726 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4727}
4728
4729static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4730 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4731 struct x86_exception *exception)
bbd9b64e
CO		 4732{
4733 void *data = val;
10589a46 4734 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4735
4736 while (bytes) {
14dfe855 4737 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4738 exception);
bbd9b64e 4739 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4740 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4741 int ret;
4742
bcc55cba 4743 if (gpa == UNMAPPED_GVA)
ab9ae313 4744 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4745 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4746 offset, toread);
10589a46 4747 if (ret < 0) {
c3cd7ffa 4748 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4749 goto out;
4750 }
bbd9b64e 4751
77c2002e
IE		 4752 bytes -= toread;
4753 data += toread;
4754 addr += toread;
bbd9b64e 4755 }
10589a46 4756out:
10589a46 4757 return r;
bbd9b64e 4758}
77c2002e 4759
1871c602 4760/* used for instruction fetching */
0f65dd70
AK		 4761static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4762 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4763 struct x86_exception *exception)
1871c602 4764{
0f65dd70 4765 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4766 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4767 unsigned offset;
4768 int ret;
0f65dd70 4769
44583cba
PB		 4770 /* Inline kvm_read_guest_virt_helper for speed. */
4771 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4772 exception);
4773 if (unlikely(gpa == UNMAPPED_GVA))
4774 return X86EMUL_PROPAGATE_FAULT;
4775
4776 offset = addr & (PAGE_SIZE-1);
4777 if (WARN_ON(offset + bytes > PAGE_SIZE))
4778 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4779 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4780 offset, bytes);
44583cba
PB		 4781 if (unlikely(ret < 0))
4782 return X86EMUL_IO_NEEDED;
4783
4784 return X86EMUL_CONTINUE;
1871c602
GN		 4785}
4786
064aea77 4787int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4788 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4789 struct x86_exception *exception)
1871c602 4790{
0f65dd70 4791 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4792 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4793
1871c602 4794 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4795 exception);
1871c602 4796}
064aea77 4797EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4798
0f65dd70
AK		 4799static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4800 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4801 struct x86_exception *exception)
1871c602 4802{
0f65dd70 4803 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4804 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4805}
4806
7a036a6f
RK		 4807static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4808 unsigned long addr, void *val, unsigned int bytes)
4809{
4810 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4811 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4812
4813 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4814}
4815
6a4d7550 4816int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4817 gva_t addr, void *val,
2dafc6c2 4818 unsigned int bytes,
bcc55cba 4819 struct x86_exception *exception)
77c2002e 4820{
0f65dd70 4821 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4822 void *data = val;
4823 int r = X86EMUL_CONTINUE;
4824
4825 while (bytes) {
14dfe855
JR		 4826 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4827 PFERR_WRITE_MASK,
ab9ae313 4828 exception);
77c2002e
IE		 4829 unsigned offset = addr & (PAGE_SIZE-1);
4830 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4831 int ret;
4832
bcc55cba 4833 if (gpa == UNMAPPED_GVA)
ab9ae313 4834 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4835 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4836 if (ret < 0) {
c3cd7ffa 4837 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4838 goto out;
4839 }
4840
4841 bytes -= towrite;
4842 data += towrite;
4843 addr += towrite;
4844 }
4845out:
4846 return r;
4847}
6a4d7550 4848EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4849
082d06ed
WL		 4850int handle_ud(struct kvm_vcpu *vcpu)
4851{
6c86eedc 4852 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 4853 enum emulation_result er;
6c86eedc
WL		 4854 char sig[5]; /* ud2; .ascii "kvm" */
4855 struct x86_exception e;
4856
4857 if (force_emulation_prefix &&
4858 kvm_read_guest_virt(&vcpu->arch.emulate_ctxt,
4859 kvm_get_linear_rip(vcpu), sig, sizeof(sig), &e) == 0 &&
4860 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
4861 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
4862 emul_type = 0;
4863 }
082d06ed 4864
6c86eedc 4865 er = emulate_instruction(vcpu, emul_type);
082d06ed
WL		 4866 if (er == EMULATE_USER_EXIT)
4867 return 0;
4868 if (er != EMULATE_DONE)
4869 kvm_queue_exception(vcpu, UD_VECTOR);
4870 return 1;
4871}
4872EXPORT_SYMBOL_GPL(handle_ud);
4873
0f89b207
TL		 4874static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4875 gpa_t gpa, bool write)
4876{
4877 /* For APIC access vmexit */
4878 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4879 return 1;
4880
4881 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4882 trace_vcpu_match_mmio(gva, gpa, write, true);
4883 return 1;
4884 }
4885
4886 return 0;
4887}
4888
af7cc7d1
XG		 4889static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4890 gpa_t *gpa, struct x86_exception *exception,
4891 bool write)
4892{
97d64b78
AK		 4893 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4894 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4895
be94f6b7
HH		 4896 /*
4897 * currently PKRU is only applied to ept enabled guest so
4898 * there is no pkey in EPT page table for L1 guest or EPT
4899 * shadow page table for L2 guest.
4900 */
97d64b78 4901 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4902 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4903 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4904 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4905 (gva & (PAGE_SIZE - 1));
4f022648 4906 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4907 return 1;
4908 }
4909
af7cc7d1
XG		 4910 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4911
4912 if (*gpa == UNMAPPED_GVA)
4913 return -1;
4914
0f89b207 4915 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4916}
4917
3200f405 4918int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4919 const void *val, int bytes)
bbd9b64e
CO		 4920{
4921 int ret;
4922
54bf36aa 4923 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4924 if (ret < 0)
bbd9b64e 4925 return 0;
0eb05bf2 4926 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4927 return 1;
4928}
4929
77d197b2
XG		 4930struct read_write_emulator_ops {
4931 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4932 int bytes);
4933 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4934 void *val, int bytes);
4935 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4936 int bytes, void *val);
4937 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4938 void *val, int bytes);
4939 bool write;
4940};
4941
4942static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4943{
4944 if (vcpu->mmio_read_completed) {
77d197b2 4945 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4946 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4947 vcpu->mmio_read_completed = 0;
4948 return 1;
4949 }
4950
4951 return 0;
4952}
4953
4954static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4955 void *val, int bytes)
4956{
54bf36aa 4957 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4958}
4959
4960static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4961 void *val, int bytes)
4962{
4963 return emulator_write_phys(vcpu, gpa, val, bytes);
4964}
4965
4966static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4967{
e39d200f 4968 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4969 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4970}
4971
4972static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4973 void *val, int bytes)
4974{
e39d200f 4975 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4976 return X86EMUL_IO_NEEDED;
4977}
4978
4979static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4980 void *val, int bytes)
4981{
f78146b0
AK		 4982 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4983
87da7e66 4984 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4985 return X86EMUL_CONTINUE;
4986}
4987
0fbe9b0b 4988static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4989 .read_write_prepare = read_prepare,
4990 .read_write_emulate = read_emulate,
4991 .read_write_mmio = vcpu_mmio_read,
4992 .read_write_exit_mmio = read_exit_mmio,
4993};
4994
0fbe9b0b 4995static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4996 .read_write_emulate = write_emulate,
4997 .read_write_mmio = write_mmio,
4998 .read_write_exit_mmio = write_exit_mmio,
4999 .write = true,
5000};
5001
22388a3c
XG		 5002static int emulator_read_write_onepage(unsigned long addr, void *val,
5003 unsigned int bytes,
5004 struct x86_exception *exception,
5005 struct kvm_vcpu *vcpu,
0fbe9b0b 5006 const struct read_write_emulator_ops *ops)
bbd9b64e 5007{
af7cc7d1
XG		 5008 gpa_t gpa;
5009 int handled, ret;
22388a3c 5010 bool write = ops->write;
f78146b0 5011 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5012 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5013
5014 /*
5015 * If the exit was due to a NPF we may already have a GPA.
5016 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5017 * Note, this cannot be used on string operations since string
5018 * operation using rep will only have the initial GPA from the NPF
5019 * occurred.
5020 */
5021 if (vcpu->arch.gpa_available &&
5022 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5023 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5024 gpa = vcpu->arch.gpa_val;
5025 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5026 } else {
5027 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5028 if (ret < 0)
5029 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5030 }
10589a46 5031
618232e2 5032 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5033 return X86EMUL_CONTINUE;
5034
bbd9b64e
CO		 5035 /*
5036 * Is this MMIO handled locally?
5037 */
22388a3c 5038 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5039 if (handled == bytes)
bbd9b64e 5040 return X86EMUL_CONTINUE;
bbd9b64e 5041
70252a10
AK		 5042 gpa += handled;
5043 bytes -= handled;
5044 val += handled;
5045
87da7e66
XG		 5046 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5047 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5048 frag->gpa = gpa;
5049 frag->data = val;
5050 frag->len = bytes;
f78146b0 5051 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5052}
5053
52eb5a6d
XL		 5054static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5055 unsigned long addr,
22388a3c
XG		 5056 void *val, unsigned int bytes,
5057 struct x86_exception *exception,
0fbe9b0b 5058 const struct read_write_emulator_ops *ops)
bbd9b64e 5059{
0f65dd70 5060 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5061 gpa_t gpa;
5062 int rc;
5063
5064 if (ops->read_write_prepare &&
5065 ops->read_write_prepare(vcpu, val, bytes))
5066 return X86EMUL_CONTINUE;
5067
5068 vcpu->mmio_nr_fragments = 0;
0f65dd70 5069
bbd9b64e
CO		 5070 /* Crossing a page boundary? */
5071 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5072 int now;
bbd9b64e
CO		 5073
5074 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5075 rc = emulator_read_write_onepage(addr, val, now, exception,
5076 vcpu, ops);
5077
bbd9b64e
CO		 5078 if (rc != X86EMUL_CONTINUE)
5079 return rc;
5080 addr += now;
bac15531
NA		 5081 if (ctxt->mode != X86EMUL_MODE_PROT64)
5082 addr = (u32)addr;
bbd9b64e
CO		 5083 val += now;
5084 bytes -= now;
5085 }
22388a3c 5086
f78146b0
AK		 5087 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5088 vcpu, ops);
5089 if (rc != X86EMUL_CONTINUE)
5090 return rc;
5091
5092 if (!vcpu->mmio_nr_fragments)
5093 return rc;
5094
5095 gpa = vcpu->mmio_fragments[0].gpa;
5096
5097 vcpu->mmio_needed = 1;
5098 vcpu->mmio_cur_fragment = 0;
5099
87da7e66 5100 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5101 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5102 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5103 vcpu->run->mmio.phys_addr = gpa;
5104
5105 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5106}
5107
5108static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5109 unsigned long addr,
5110 void *val,
5111 unsigned int bytes,
5112 struct x86_exception *exception)
5113{
5114 return emulator_read_write(ctxt, addr, val, bytes,
5115 exception, &read_emultor);
5116}
5117
52eb5a6d 5118static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5119 unsigned long addr,
5120 const void *val,
5121 unsigned int bytes,
5122 struct x86_exception *exception)
5123{
5124 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5125 exception, &write_emultor);
bbd9b64e 5126}
bbd9b64e 5127
daea3e73
AK		 5128#define CMPXCHG_TYPE(t, ptr, old, new) \
5129 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5130
5131#ifdef CONFIG_X86_64
5132# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5133#else
5134# define CMPXCHG64(ptr, old, new) \
9749a6c0 5135 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5136#endif
5137
0f65dd70
AK		 5138static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5139 unsigned long addr,
bbd9b64e
CO		 5140 const void *old,
5141 const void *new,
5142 unsigned int bytes,
0f65dd70 5143 struct x86_exception *exception)
bbd9b64e 5144{
0f65dd70 5145 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5146 gpa_t gpa;
5147 struct page *page;
5148 char *kaddr;
5149 bool exchanged;
2bacc55c 5150
daea3e73
AK		 5151 /* guests cmpxchg8b have to be emulated atomically */
5152 if (bytes > 8 || (bytes & (bytes - 1)))
5153 goto emul_write;
10589a46 5154
daea3e73 5155 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5156
daea3e73
AK		 5157 if (gpa == UNMAPPED_GVA ||
5158 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5159 goto emul_write;
2bacc55c 5160
daea3e73
AK		 5161 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5162 goto emul_write;
72dc67a6 5163
54bf36aa 5164 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5165 if (is_error_page(page))
c19b8bd6 5166 goto emul_write;
72dc67a6 5167
8fd75e12 5168 kaddr = kmap_atomic(page);
daea3e73
AK		 5169 kaddr += offset_in_page(gpa);
5170 switch (bytes) {
5171 case 1:
5172 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5173 break;
5174 case 2:
5175 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5176 break;
5177 case 4:
5178 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5179 break;
5180 case 8:
5181 exchanged = CMPXCHG64(kaddr, old, new);
5182 break;
5183 default:
5184 BUG();
2bacc55c 5185 }
8fd75e12 5186 kunmap_atomic(kaddr);
daea3e73
AK		 5187 kvm_release_page_dirty(page);
5188
5189 if (!exchanged)
5190 return X86EMUL_CMPXCHG_FAILED;
5191
54bf36aa 5192 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5193 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5194
5195 return X86EMUL_CONTINUE;
4a5f48f6 5196
3200f405 5197emul_write:
daea3e73 5198 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5199
0f65dd70 5200 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5201}
5202
cf8f70bf
GN		 5203static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5204{
cbfc6c91 5205 int r = 0, i;
cf8f70bf 5206
cbfc6c91
WL		 5207 for (i = 0; i < vcpu->arch.pio.count; i++) {
5208 if (vcpu->arch.pio.in)
5209 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5210 vcpu->arch.pio.size, pd);
5211 else
5212 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5213 vcpu->arch.pio.port, vcpu->arch.pio.size,
5214 pd);
5215 if (r)
5216 break;
5217 pd += vcpu->arch.pio.size;
5218 }
cf8f70bf
GN		 5219 return r;
5220}
5221
6f6fbe98
XG		 5222static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5223 unsigned short port, void *val,
5224 unsigned int count, bool in)
cf8f70bf 5225{
cf8f70bf 5226 vcpu->arch.pio.port = port;
6f6fbe98 5227 vcpu->arch.pio.in = in;
7972995b 5228 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5229 vcpu->arch.pio.size = size;
5230
5231 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5232 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5233 return 1;
5234 }
5235
5236 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5237 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5238 vcpu->run->io.size = size;
5239 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5240 vcpu->run->io.count = count;
5241 vcpu->run->io.port = port;
5242
5243 return 0;
5244}
5245
6f6fbe98
XG		 5246static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5247 int size, unsigned short port, void *val,
5248 unsigned int count)
cf8f70bf 5249{
ca1d4a9e 5250 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5251 int ret;
ca1d4a9e 5252
6f6fbe98
XG		 5253 if (vcpu->arch.pio.count)
5254 goto data_avail;
cf8f70bf 5255
cbfc6c91
WL		 5256 memset(vcpu->arch.pio_data, 0, size * count);
5257
6f6fbe98
XG		 5258 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5259 if (ret) {
5260data_avail:
5261 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5262 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5263 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5264 return 1;
5265 }
5266
cf8f70bf
GN		 5267 return 0;
5268}
5269
6f6fbe98
XG		 5270static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5271 int size, unsigned short port,
5272 const void *val, unsigned int count)
5273{
5274 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5275
5276 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5277 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5278 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5279}
5280
bbd9b64e
CO		 5281static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5282{
5283 return kvm_x86_ops->get_segment_base(vcpu, seg);
5284}
5285
3cb16fe7 5286static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5287{
3cb16fe7 5288 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5289}
5290
ae6a2375 5291static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5292{
5293 if (!need_emulate_wbinvd(vcpu))
5294 return X86EMUL_CONTINUE;
5295
5296 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5297 int cpu = get_cpu();
5298
5299 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5300 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5301 wbinvd_ipi, NULL, 1);
2eec7343 5302 put_cpu();
f5f48ee1 5303 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5304 } else
5305 wbinvd();
f5f48ee1
SY		 5306 return X86EMUL_CONTINUE;
5307}
5cb56059
JS		 5308
5309int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5310{
6affcbed
KH		 5311 kvm_emulate_wbinvd_noskip(vcpu);
5312 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5313}
f5f48ee1
SY		 5314EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5315
5cb56059
JS		 5316
5317
bcaf5cc5
AK		 5318static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5319{
5cb56059 5320 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5321}
5322
52eb5a6d
XL		 5323static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5324 unsigned long *dest)
bbd9b64e 5325{
16f8a6f9 5326 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5327}
5328
52eb5a6d
XL		 5329static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5330 unsigned long value)
bbd9b64e 5331{
338dbc97 5332
717746e3 5333 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5334}
5335
52a46617 5336static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5337{
52a46617 5338 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5339}
5340
717746e3 5341static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5342{
717746e3 5343 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5344 unsigned long value;
5345
5346 switch (cr) {
5347 case 0:
5348 value = kvm_read_cr0(vcpu);
5349 break;
5350 case 2:
5351 value = vcpu->arch.cr2;
5352 break;
5353 case 3:
9f8fe504 5354 value = kvm_read_cr3(vcpu);
52a46617
GN		 5355 break;
5356 case 4:
5357 value = kvm_read_cr4(vcpu);
5358 break;
5359 case 8:
5360 value = kvm_get_cr8(vcpu);
5361 break;
5362 default:
a737f256 5363 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5364 return 0;
5365 }
5366
5367 return value;
5368}
5369
717746e3 5370static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5371{
717746e3 5372 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5373 int res = 0;
5374
52a46617
GN		 5375 switch (cr) {
5376 case 0:
49a9b07e 5377 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5378 break;
5379 case 2:
5380 vcpu->arch.cr2 = val;
5381 break;
5382 case 3:
2390218b 5383 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5384 break;
5385 case 4:
a83b29c6 5386 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5387 break;
5388 case 8:
eea1cff9 5389 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5390 break;
5391 default:
a737f256 5392 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5393 res = -1;
52a46617 5394 }
0f12244f
GN		 5395
5396 return res;
52a46617
GN		 5397}
5398
717746e3 5399static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5400{
717746e3 5401 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5402}
5403
4bff1e86 5404static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5405{
4bff1e86 5406 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5407}
5408
4bff1e86 5409static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5410{
4bff1e86 5411 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5412}
5413
1ac9d0cf
AK		 5414static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5415{
5416 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5417}
5418
5419static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5420{
5421 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5422}
5423
4bff1e86
AK		 5424static unsigned long emulator_get_cached_segment_base(
5425 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5426{
4bff1e86 5427 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5428}
5429
1aa36616
AK		 5430static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5431 struct desc_struct *desc, u32 *base3,
5432 int seg)
2dafc6c2
GN		 5433{
5434 struct kvm_segment var;
5435
4bff1e86 5436 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5437 *selector = var.selector;
2dafc6c2 5438
378a8b09
GN		 5439 if (var.unusable) {
5440 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5441 if (base3)
5442 *base3 = 0;
2dafc6c2 5443 return false;
378a8b09 5444 }
2dafc6c2
GN		 5445
5446 if (var.g)
5447 var.limit >>= 12;
5448 set_desc_limit(desc, var.limit);
5449 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5450#ifdef CONFIG_X86_64
5451 if (base3)
5452 *base3 = var.base >> 32;
5453#endif
2dafc6c2
GN		 5454 desc->type = var.type;
5455 desc->s = var.s;
5456 desc->dpl = var.dpl;
5457 desc->p = var.present;
5458 desc->avl = var.avl;
5459 desc->l = var.l;
5460 desc->d = var.db;
5461 desc->g = var.g;
5462
5463 return true;
5464}
5465
1aa36616
AK		 5466static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5467 struct desc_struct *desc, u32 base3,
5468 int seg)
2dafc6c2 5469{
4bff1e86 5470 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5471 struct kvm_segment var;
5472
1aa36616 5473 var.selector = selector;
2dafc6c2 5474 var.base = get_desc_base(desc);
5601d05b
GN		 5475#ifdef CONFIG_X86_64
5476 var.base |= ((u64)base3) << 32;
5477#endif
2dafc6c2
GN		 5478 var.limit = get_desc_limit(desc);
5479 if (desc->g)
5480 var.limit = (var.limit << 12) | 0xfff;
5481 var.type = desc->type;
2dafc6c2
GN		 5482 var.dpl = desc->dpl;
5483 var.db = desc->d;
5484 var.s = desc->s;
5485 var.l = desc->l;
5486 var.g = desc->g;
5487 var.avl = desc->avl;
5488 var.present = desc->p;
5489 var.unusable = !var.present;
5490 var.padding = 0;
5491
5492 kvm_set_segment(vcpu, &var, seg);
5493 return;
5494}
5495
717746e3
AK		 5496static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5497 u32 msr_index, u64 *pdata)
5498{
609e36d3
PB		 5499 struct msr_data msr;
5500 int r;
5501
5502 msr.index = msr_index;
5503 msr.host_initiated = false;
5504 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5505 if (r)
5506 return r;
5507
5508 *pdata = msr.data;
5509 return 0;
717746e3
AK		 5510}
5511
5512static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5513 u32 msr_index, u64 data)
5514{
8fe8ab46
WA		 5515 struct msr_data msr;
5516
5517 msr.data = data;
5518 msr.index = msr_index;
5519 msr.host_initiated = false;
5520 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5521}
5522
64d60670
PB		 5523static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5524{
5525 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5526
5527 return vcpu->arch.smbase;
5528}
5529
5530static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5531{
5532 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5533
5534 vcpu->arch.smbase = smbase;
5535}
5536
67f4d428
NA		 5537static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5538 u32 pmc)
5539{
c6702c9d 5540 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5541}
5542
222d21aa
AK		 5543static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5544 u32 pmc, u64 *pdata)
5545{
c6702c9d 5546 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5547}
5548
6c3287f7
AK		 5549static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5550{
5551 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5552}
5553
2953538e 5554static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5555 struct x86_instruction_info *info,
c4f035c6
AK		 5556 enum x86_intercept_stage stage)
5557{
2953538e 5558 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5559}
5560
e911eb3b
YZ		 5561static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5562 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5563{
e911eb3b 5564 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5565}
5566
dd856efa
AK		 5567static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5568{
5569 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5570}
5571
5572static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5573{
5574 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5575}
5576
801806d9
NA		 5577static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5578{
5579 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5580}
5581
6ed071f0
LP		 5582static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5583{
5584 return emul_to_vcpu(ctxt)->arch.hflags;
5585}
5586
5587static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5588{
5589 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5590}
5591
0234bf88
LP		 5592static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5593{
5594 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5595}
5596
0225fb50 5597static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5598 .read_gpr = emulator_read_gpr,
5599 .write_gpr = emulator_write_gpr,
1871c602 5600 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5601 .write_std = kvm_write_guest_virt_system,
7a036a6f 5602 .read_phys = kvm_read_guest_phys_system,
1871c602 5603 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5604 .read_emulated = emulator_read_emulated,
5605 .write_emulated = emulator_write_emulated,
5606 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5607 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5608 .pio_in_emulated = emulator_pio_in_emulated,
5609 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5610 .get_segment = emulator_get_segment,
5611 .set_segment = emulator_set_segment,
5951c442 5612 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5613 .get_gdt = emulator_get_gdt,
160ce1f1 5614 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5615 .set_gdt = emulator_set_gdt,
5616 .set_idt = emulator_set_idt,
52a46617
GN		 5617 .get_cr = emulator_get_cr,
5618 .set_cr = emulator_set_cr,
9c537244 5619 .cpl = emulator_get_cpl,
35aa5375
GN		 5620 .get_dr = emulator_get_dr,
5621 .set_dr = emulator_set_dr,
64d60670
PB		 5622 .get_smbase = emulator_get_smbase,
5623 .set_smbase = emulator_set_smbase,
717746e3
AK		 5624 .set_msr = emulator_set_msr,
5625 .get_msr = emulator_get_msr,
67f4d428 5626 .check_pmc = emulator_check_pmc,
222d21aa 5627 .read_pmc = emulator_read_pmc,
6c3287f7 5628 .halt = emulator_halt,
bcaf5cc5 5629 .wbinvd = emulator_wbinvd,
d6aa1000 5630 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5631 .intercept = emulator_intercept,
bdb42f5a 5632 .get_cpuid = emulator_get_cpuid,
801806d9 5633 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5634 .get_hflags = emulator_get_hflags,
5635 .set_hflags = emulator_set_hflags,
0234bf88 5636 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5637};
5638
95cb2295
GN		 5639static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5640{
37ccdcbe 5641 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5642 /*
5643 * an sti; sti; sequence only disable interrupts for the first
5644 * instruction. So, if the last instruction, be it emulated or
5645 * not, left the system with the INT_STI flag enabled, it
5646 * means that the last instruction is an sti. We should not
5647 * leave the flag on in this case. The same goes for mov ss
5648 */
37ccdcbe
PB		 5649 if (int_shadow & mask)
5650 mask = 0;
6addfc42 5651 if (unlikely(int_shadow || mask)) {
95cb2295 5652 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5653 if (!mask)
5654 kvm_make_request(KVM_REQ_EVENT, vcpu);
5655 }
95cb2295
GN		 5656}
5657
ef54bcfe 5658static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5659{
5660 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5661 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5662 return kvm_propagate_fault(vcpu, &ctxt->exception);
5663
5664 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5665 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5666 ctxt->exception.error_code);
54b8486f 5667 else
da9cb575 5668 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5669 return false;
54b8486f
GN		 5670}
5671
8ec4722d
MG		 5672static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5673{
adf52235 5674 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5675 int cs_db, cs_l;
5676
8ec4722d
MG		 5677 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5678
adf52235 5679 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5680 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5681
adf52235
TY		 5682 ctxt->eip = kvm_rip_read(vcpu);
5683 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5684 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5685 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5686 cs_db ? X86EMUL_MODE_PROT32 :
5687 X86EMUL_MODE_PROT16;
a584539b 5688 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5689 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5690 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5691
dd856efa 5692 init_decode_cache(ctxt);
7ae441ea 5693 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5694}
5695
71f9833b 5696int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5697{
9d74191a 5698 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5699 int ret;
5700
5701 init_emulate_ctxt(vcpu);
5702
9dac77fa
AK		 5703 ctxt->op_bytes = 2;
5704 ctxt->ad_bytes = 2;
5705 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5706 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5707
5708 if (ret != X86EMUL_CONTINUE)
5709 return EMULATE_FAIL;
5710
9dac77fa 5711 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5712 kvm_rip_write(vcpu, ctxt->eip);
5713 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5714
63995653
MG		 5715 return EMULATE_DONE;
5716}
5717EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5718
e2366171 5719static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5720{
fc3a9157
JR		 5721 int r = EMULATE_DONE;
5722
6d77dbfc
GN		 5723 ++vcpu->stat.insn_emulation_fail;
5724 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5725
5726 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5727 return EMULATE_FAIL;
5728
a2b9e6c1 5729 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5730 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5731 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5732 vcpu->run->internal.ndata = 0;
1f4dcb3b 5733 r = EMULATE_USER_EXIT;
fc3a9157 5734 }
e2366171 5735
6d77dbfc 5736 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5737
5738 return r;
6d77dbfc
GN		 5739}
5740
93c05d3e 5741static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5742 bool write_fault_to_shadow_pgtable,
5743 int emulation_type)
a6f177ef 5744{
95b3cf69 5745 gpa_t gpa = cr2;
ba049e93 5746 kvm_pfn_t pfn;
a6f177ef 5747
991eebf9
GN		 5748 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5749 return false;
5750
95b3cf69
XG		 5751 if (!vcpu->arch.mmu.direct_map) {
5752 /*
5753 * Write permission should be allowed since only
5754 * write access need to be emulated.
5755 */
5756 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5757
95b3cf69
XG		 5758 /*
5759 * If the mapping is invalid in guest, let cpu retry
5760 * it to generate fault.
5761 */
5762 if (gpa == UNMAPPED_GVA)
5763 return true;
5764 }
a6f177ef 5765
8e3d9d06
XG		 5766 /*
5767 * Do not retry the unhandleable instruction if it faults on the
5768 * readonly host memory, otherwise it will goto a infinite loop:
5769 * retry instruction -> write #PF -> emulation fail -> retry
5770 * instruction -> ...
5771 */
5772 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5773
5774 /*
5775 * If the instruction failed on the error pfn, it can not be fixed,
5776 * report the error to userspace.
5777 */
5778 if (is_error_noslot_pfn(pfn))
5779 return false;
5780
5781 kvm_release_pfn_clean(pfn);
5782
5783 /* The instructions are well-emulated on direct mmu. */
5784 if (vcpu->arch.mmu.direct_map) {
5785 unsigned int indirect_shadow_pages;
5786
5787 spin_lock(&vcpu->kvm->mmu_lock);
5788 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5789 spin_unlock(&vcpu->kvm->mmu_lock);
5790
5791 if (indirect_shadow_pages)
5792 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5793
a6f177ef 5794 return true;
8e3d9d06 5795 }
a6f177ef 5796
95b3cf69
XG		 5797 /*
5798 * if emulation was due to access to shadowed page table
5799 * and it failed try to unshadow page and re-enter the
5800 * guest to let CPU execute the instruction.
5801 */
5802 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5803
5804 /*
5805 * If the access faults on its page table, it can not
5806 * be fixed by unprotecting shadow page and it should
5807 * be reported to userspace.
5808 */
5809 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5810}
5811
1cb3f3ae
XG		 5812static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5813 unsigned long cr2, int emulation_type)
5814{
5815 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5816 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5817
5818 last_retry_eip = vcpu->arch.last_retry_eip;
5819 last_retry_addr = vcpu->arch.last_retry_addr;
5820
5821 /*
5822 * If the emulation is caused by #PF and it is non-page_table
5823 * writing instruction, it means the VM-EXIT is caused by shadow
5824 * page protected, we can zap the shadow page and retry this
5825 * instruction directly.
5826 *
5827 * Note: if the guest uses a non-page-table modifying instruction
5828 * on the PDE that points to the instruction, then we will unmap
5829 * the instruction and go to an infinite loop. So, we cache the
5830 * last retried eip and the last fault address, if we meet the eip
5831 * and the address again, we can break out of the potential infinite
5832 * loop.
5833 */
5834 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5835
5836 if (!(emulation_type & EMULTYPE_RETRY))
5837 return false;
5838
5839 if (x86_page_table_writing_insn(ctxt))
5840 return false;
5841
5842 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5843 return false;
5844
5845 vcpu->arch.last_retry_eip = ctxt->eip;
5846 vcpu->arch.last_retry_addr = cr2;
5847
5848 if (!vcpu->arch.mmu.direct_map)
5849 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5850
22368028 5851 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5852
5853 return true;
5854}
5855
716d51ab
GN		 5856static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5857static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5858
64d60670 5859static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5860{
64d60670 5861 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5862 /* This is a good place to trace that we are exiting SMM. */
5863 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5864
c43203ca
PB		 5865 /* Process a latched INIT or SMI, if any. */
5866 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5867 }
699023e2
PB		 5868
5869 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5870}
5871
5872static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5873{
5874 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5875
a584539b 5876 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5877
5878 if (changed & HF_SMM_MASK)
5879 kvm_smm_changed(vcpu);
a584539b
PB		 5880}
5881
4a1e10d5
PB		 5882static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5883 unsigned long *db)
5884{
5885 u32 dr6 = 0;
5886 int i;
5887 u32 enable, rwlen;
5888
5889 enable = dr7;
5890 rwlen = dr7 >> 16;
5891 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5892 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5893 dr6 |= (1 << i);
5894 return dr6;
5895}
5896
c8401dda 5897static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5898{
5899 struct kvm_run *kvm_run = vcpu->run;
5900
c8401dda
PB		 5901 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5902 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5903 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5904 kvm_run->debug.arch.exception = DB_VECTOR;
5905 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5906 *r = EMULATE_USER_EXIT;
5907 } else {
5908 /*
5909 * "Certain debug exceptions may clear bit 0-3. The
5910 * remaining contents of the DR6 register are never
5911 * cleared by the processor".
5912 */
5913 vcpu->arch.dr6 &= ~15;
5914 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5915 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5916 }
5917}
5918
6affcbed
KH		 5919int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5920{
5921 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5922 int r = EMULATE_DONE;
5923
5924 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5925
5926 /*
5927 * rflags is the old, "raw" value of the flags. The new value has
5928 * not been saved yet.
5929 *
5930 * This is correct even for TF set by the guest, because "the
5931 * processor will not generate this exception after the instruction
5932 * that sets the TF flag".
5933 */
5934 if (unlikely(rflags & X86_EFLAGS_TF))
5935 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5936 return r == EMULATE_DONE;
5937}
5938EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5939
4a1e10d5
PB		 5940static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5941{
4a1e10d5
PB		 5942 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5943 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5944 struct kvm_run *kvm_run = vcpu->run;
5945 unsigned long eip = kvm_get_linear_rip(vcpu);
5946 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5947 vcpu->arch.guest_debug_dr7,
5948 vcpu->arch.eff_db);
5949
5950 if (dr6 != 0) {
6f43ed01 5951 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5952 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5953 kvm_run->debug.arch.exception = DB_VECTOR;
5954 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5955 *r = EMULATE_USER_EXIT;
5956 return true;
5957 }
5958 }
5959
4161a569
NA		 5960 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5961 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5962 unsigned long eip = kvm_get_linear_rip(vcpu);
5963 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5964 vcpu->arch.dr7,
5965 vcpu->arch.db);
5966
5967 if (dr6 != 0) {
5968 vcpu->arch.dr6 &= ~15;
6f43ed01 5969 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5970 kvm_queue_exception(vcpu, DB_VECTOR);
5971 *r = EMULATE_DONE;
5972 return true;
5973 }
5974 }
5975
5976 return false;
5977}
5978
04789b66
LA		 5979static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
5980{
2d7921c4
AM		 5981 switch (ctxt->opcode_len) {
5982 case 1:
5983 switch (ctxt->b) {
5984 case 0xe4: /* IN */
5985 case 0xe5:
5986 case 0xec:
5987 case 0xed:
5988 case 0xe6: /* OUT */
5989 case 0xe7:
5990 case 0xee:
5991 case 0xef:
5992 case 0x6c: /* INS */
5993 case 0x6d:
5994 case 0x6e: /* OUTS */
5995 case 0x6f:
5996 return true;
5997 }
5998 break;
5999 case 2:
6000 switch (ctxt->b) {
6001 case 0x33: /* RDPMC */
6002 return true;
6003 }
6004 break;
04789b66
LA		 6005 }
6006
6007 return false;
6008}
6009
51d8b661
AP		 6010int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6011 unsigned long cr2,
dc25e89e
AP		 6012 int emulation_type,
6013 void *insn,
6014 int insn_len)
bbd9b64e 6015{
95cb2295 6016 int r;
9d74191a 6017 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6018 bool writeback = true;
93c05d3e 6019 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6020
93c05d3e
XG		 6021 /*
6022 * Clear write_fault_to_shadow_pgtable here to ensure it is
6023 * never reused.
6024 */
6025 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6026 kvm_clear_exception_queue(vcpu);
8d7d8102 6027
571008da 6028 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6029 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6030
6031 /*
6032 * We will reenter on the same instruction since
6033 * we do not set complete_userspace_io. This does not
6034 * handle watchpoints yet, those would be handled in
6035 * the emulate_ops.
6036 */
d391f120
VK		 6037 if (!(emulation_type & EMULTYPE_SKIP) &&
6038 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6039 return r;
6040
9d74191a
TY		 6041 ctxt->interruptibility = 0;
6042 ctxt->have_exception = false;
e0ad0b47 6043 ctxt->exception.vector = -1;
9d74191a 6044 ctxt->perm_ok = false;
bbd9b64e 6045
b51e974f 6046 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6047
9d74191a 6048 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6049
e46479f8 6050 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6051 ++vcpu->stat.insn_emulation;
1d2887e2 6052 if (r != EMULATION_OK) {
4005996e
AK		 6053 if (emulation_type & EMULTYPE_TRAP_UD)
6054 return EMULATE_FAIL;
991eebf9
GN		 6055 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6056 emulation_type))
bbd9b64e 6057 return EMULATE_DONE;
6ea6e843
PB		 6058 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6059 return EMULATE_DONE;
6d77dbfc
GN		 6060 if (emulation_type & EMULTYPE_SKIP)
6061 return EMULATE_FAIL;
e2366171 6062 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6063 }
6064 }
6065
04789b66
LA		 6066 if ((emulation_type & EMULTYPE_VMWARE) &&
6067 !is_vmware_backdoor_opcode(ctxt))
6068 return EMULATE_FAIL;
6069
ba8afb6b 6070 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6071 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6072 if (ctxt->eflags & X86_EFLAGS_RF)
6073 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6074 return EMULATE_DONE;
6075 }
6076
1cb3f3ae
XG		 6077 if (retry_instruction(ctxt, cr2, emulation_type))
6078 return EMULATE_DONE;
6079
7ae441ea 6080 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6081 changes registers values during IO operation */
7ae441ea
GN		 6082 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6083 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6084 emulator_invalidate_register_cache(ctxt);
7ae441ea 6085 }
4d2179e1 6086
5cd21917 6087restart:
0f89b207
TL		 6088 /* Save the faulting GPA (cr2) in the address field */
6089 ctxt->exception.address = cr2;
6090
9d74191a 6091 r = x86_emulate_insn(ctxt);
bbd9b64e 6092
775fde86
JR		 6093 if (r == EMULATION_INTERCEPTED)
6094 return EMULATE_DONE;
6095
d2ddd1c4 6096 if (r == EMULATION_FAILED) {
991eebf9
GN		 6097 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6098 emulation_type))
c3cd7ffa
GN		 6099 return EMULATE_DONE;
6100
e2366171 6101 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6102 }
6103
9d74191a 6104 if (ctxt->have_exception) {
d2ddd1c4 6105 r = EMULATE_DONE;
ef54bcfe
PB		 6106 if (inject_emulated_exception(vcpu))
6107 return r;
d2ddd1c4 6108 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6109 if (!vcpu->arch.pio.in) {
6110 /* FIXME: return into emulator if single-stepping. */
3457e419 6111 vcpu->arch.pio.count = 0;
0912c977 6112 } else {
7ae441ea 6113 writeback = false;
716d51ab
GN		 6114 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6115 }
ac0a48c3 6116 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6117 } else if (vcpu->mmio_needed) {
6118 if (!vcpu->mmio_is_write)
6119 writeback = false;
ac0a48c3 6120 r = EMULATE_USER_EXIT;
716d51ab 6121 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6122 } else if (r == EMULATION_RESTART)
5cd21917 6123 goto restart;
d2ddd1c4
GN		 6124 else
6125 r = EMULATE_DONE;
f850e2e6 6126
7ae441ea 6127 if (writeback) {
6addfc42 6128 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6129 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6130 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6131 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6132 if (r == EMULATE_DONE &&
6133 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6134 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6135 if (!ctxt->have_exception ||
6136 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6137 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6138
6139 /*
6140 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6141 * do nothing, and it will be requested again as soon as
6142 * the shadow expires. But we still need to check here,
6143 * because POPF has no interrupt shadow.
6144 */
6145 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6146 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6147 } else
6148 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6149
6150 return r;
de7d789a 6151}
51d8b661 6152EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6153
dca7f128
SC		 6154static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6155 unsigned short port)
de7d789a 6156{
cf8f70bf 6157 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6158 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6159 size, port, &val, 1);
cf8f70bf 6160 /* do not return to emulator after return from userspace */
7972995b 6161 vcpu->arch.pio.count = 0;
de7d789a
CO		 6162 return ret;
6163}
de7d789a 6164
8370c3d0
TL		 6165static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6166{
6167 unsigned long val;
6168
6169 /* We should only ever be called with arch.pio.count equal to 1 */
6170 BUG_ON(vcpu->arch.pio.count != 1);
6171
6172 /* For size less than 4 we merge, else we zero extend */
6173 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6174 : 0;
6175
6176 /*
6177 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6178 * the copy and tracing
6179 */
6180 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6181 vcpu->arch.pio.port, &val, 1);
6182 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6183
6184 return 1;
6185}
6186
dca7f128
SC		 6187static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6188 unsigned short port)
8370c3d0
TL		 6189{
6190 unsigned long val;
6191 int ret;
6192
6193 /* For size less than 4 we merge, else we zero extend */
6194 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6195
6196 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6197 &val, 1);
6198 if (ret) {
6199 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6200 return ret;
6201 }
6202
6203 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6204
6205 return 0;
6206}
dca7f128
SC		 6207
6208int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6209{
6210 int ret = kvm_skip_emulated_instruction(vcpu);
6211
6212 /*
6213 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6214 * KVM_EXIT_DEBUG here.
6215 */
6216 if (in)
6217 return kvm_fast_pio_in(vcpu, size, port) && ret;
6218 else
6219 return kvm_fast_pio_out(vcpu, size, port) && ret;
6220}
6221EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6222
251a5fd6 6223static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6224{
0a3aee0d 6225 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6226 return 0;
8cfdc000
ZA		 6227}
6228
6229static void tsc_khz_changed(void *data)
c8076604 6230{
8cfdc000
ZA		 6231 struct cpufreq_freqs *freq = data;
6232 unsigned long khz = 0;
6233
6234 if (data)
6235 khz = freq->new;
6236 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6237 khz = cpufreq_quick_get(raw_smp_processor_id());
6238 if (!khz)
6239 khz = tsc_khz;
0a3aee0d 6240 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6241}
6242
5fa4ec9c 6243#ifdef CONFIG_X86_64
0092e434
VK		 6244static void kvm_hyperv_tsc_notifier(void)
6245{
0092e434
VK		 6246 struct kvm *kvm;
6247 struct kvm_vcpu *vcpu;
6248 int cpu;
6249
6250 spin_lock(&kvm_lock);
6251 list_for_each_entry(kvm, &vm_list, vm_list)
6252 kvm_make_mclock_inprogress_request(kvm);
6253
6254 hyperv_stop_tsc_emulation();
6255
6256 /* TSC frequency always matches when on Hyper-V */
6257 for_each_present_cpu(cpu)
6258 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6259 kvm_max_guest_tsc_khz = tsc_khz;
6260
6261 list_for_each_entry(kvm, &vm_list, vm_list) {
6262 struct kvm_arch *ka = &kvm->arch;
6263
6264 spin_lock(&ka->pvclock_gtod_sync_lock);
6265
6266 pvclock_update_vm_gtod_copy(kvm);
6267
6268 kvm_for_each_vcpu(cpu, vcpu, kvm)
6269 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6270
6271 kvm_for_each_vcpu(cpu, vcpu, kvm)
6272 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6273
6274 spin_unlock(&ka->pvclock_gtod_sync_lock);
6275 }
6276 spin_unlock(&kvm_lock);
0092e434 6277}
5fa4ec9c 6278#endif
0092e434 6279
c8076604
GH		 6280static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6281 void *data)
6282{
6283 struct cpufreq_freqs *freq = data;
6284 struct kvm *kvm;
6285 struct kvm_vcpu *vcpu;
6286 int i, send_ipi = 0;
6287
8cfdc000
ZA		 6288 /*
6289 * We allow guests to temporarily run on slowing clocks,
6290 * provided we notify them after, or to run on accelerating
6291 * clocks, provided we notify them before. Thus time never
6292 * goes backwards.
6293 *
6294 * However, we have a problem. We can't atomically update
6295 * the frequency of a given CPU from this function; it is
6296 * merely a notifier, which can be called from any CPU.
6297 * Changing the TSC frequency at arbitrary points in time
6298 * requires a recomputation of local variables related to
6299 * the TSC for each VCPU. We must flag these local variables
6300 * to be updated and be sure the update takes place with the
6301 * new frequency before any guests proceed.
6302 *
6303 * Unfortunately, the combination of hotplug CPU and frequency
6304 * change creates an intractable locking scenario; the order
6305 * of when these callouts happen is undefined with respect to
6306 * CPU hotplug, and they can race with each other. As such,
6307 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6308 * undefined; you can actually have a CPU frequency change take
6309 * place in between the computation of X and the setting of the
6310 * variable. To protect against this problem, all updates of
6311 * the per_cpu tsc_khz variable are done in an interrupt
6312 * protected IPI, and all callers wishing to update the value
6313 * must wait for a synchronous IPI to complete (which is trivial
6314 * if the caller is on the CPU already). This establishes the
6315 * necessary total order on variable updates.
6316 *
6317 * Note that because a guest time update may take place
6318 * anytime after the setting of the VCPU's request bit, the
6319 * correct TSC value must be set before the request. However,
6320 * to ensure the update actually makes it to any guest which
6321 * starts running in hardware virtualization between the set
6322 * and the acquisition of the spinlock, we must also ping the
6323 * CPU after setting the request bit.
6324 *
6325 */
6326
c8076604
GH		 6327 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6328 return 0;
6329 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6330 return 0;
8cfdc000
ZA		 6331
6332 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6333
2f303b74 6334 spin_lock(&kvm_lock);
c8076604 6335 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6336 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6337 if (vcpu->cpu != freq->cpu)
6338 continue;
c285545f 6339 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6340 if (vcpu->cpu != smp_processor_id())
8cfdc000 6341 send_ipi = 1;
c8076604
GH		 6342 }
6343 }
2f303b74 6344 spin_unlock(&kvm_lock);
c8076604
GH		 6345
6346 if (freq->old < freq->new && send_ipi) {
6347 /*
6348 * We upscale the frequency. Must make the guest
6349 * doesn't see old kvmclock values while running with
6350 * the new frequency, otherwise we risk the guest sees
6351 * time go backwards.
6352 *
6353 * In case we update the frequency for another cpu
6354 * (which might be in guest context) send an interrupt
6355 * to kick the cpu out of guest context. Next time
6356 * guest context is entered kvmclock will be updated,
6357 * so the guest will not see stale values.
6358 */
8cfdc000 6359 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6360 }
6361 return 0;
6362}
6363
6364static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6365 .notifier_call = kvmclock_cpufreq_notifier
6366};
6367
251a5fd6 6368static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6369{
251a5fd6
SAS		 6370 tsc_khz_changed(NULL);
6371 return 0;
8cfdc000
ZA		 6372}
6373
b820cc0c
ZA		 6374static void kvm_timer_init(void)
6375{
c285545f 6376 max_tsc_khz = tsc_khz;
460dd42e 6377
b820cc0c 6378 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6379#ifdef CONFIG_CPU_FREQ
6380 struct cpufreq_policy policy;
758f588d
BP		 6381 int cpu;
6382
c285545f 6383 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6384 cpu = get_cpu();
6385 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6386 if (policy.cpuinfo.max_freq)
6387 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6388 put_cpu();
c285545f 6389#endif
b820cc0c
ZA		 6390 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6391 CPUFREQ_TRANSITION_NOTIFIER);
6392 }
c285545f 6393 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6394
73c1b41e 6395 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6396 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6397}
6398
dd60d217
AK		 6399DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6400EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6401
f5132b01 6402int kvm_is_in_guest(void)
ff9d07a0 6403{
086c9855 6404 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6405}
6406
6407static int kvm_is_user_mode(void)
6408{
6409 int user_mode = 3;
dcf46b94 6410
086c9855
AS		 6411 if (__this_cpu_read(current_vcpu))
6412 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6413
ff9d07a0
ZY		 6414 return user_mode != 0;
6415}
6416
6417static unsigned long kvm_get_guest_ip(void)
6418{
6419 unsigned long ip = 0;
dcf46b94 6420
086c9855
AS		 6421 if (__this_cpu_read(current_vcpu))
6422 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6423
ff9d07a0
ZY		 6424 return ip;
6425}
6426
6427static struct perf_guest_info_callbacks kvm_guest_cbs = {
6428 .is_in_guest = kvm_is_in_guest,
6429 .is_user_mode = kvm_is_user_mode,
6430 .get_guest_ip = kvm_get_guest_ip,
6431};
6432
ce88decf
XG		 6433static void kvm_set_mmio_spte_mask(void)
6434{
6435 u64 mask;
6436 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6437
6438 /*
6439 * Set the reserved bits and the present bit of an paging-structure
6440 * entry to generate page fault with PFER.RSV = 1.
6441 */
885032b9 6442 /* Mask the reserved physical address bits. */
d1431483 6443 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6444
885032b9 6445 /* Set the present bit. */
ce88decf
XG		 6446 mask |= 1ull;
6447
6448#ifdef CONFIG_X86_64
6449 /*
6450 * If reserved bit is not supported, clear the present bit to disable
6451 * mmio page fault.
6452 */
6453 if (maxphyaddr == 52)
6454 mask &= ~1ull;
6455#endif
6456
dcdca5fe 6457 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6458}
6459
16e8d74d
MT		 6460#ifdef CONFIG_X86_64
6461static void pvclock_gtod_update_fn(struct work_struct *work)
6462{
d828199e
MT		 6463 struct kvm *kvm;
6464
6465 struct kvm_vcpu *vcpu;
6466 int i;
6467
2f303b74 6468 spin_lock(&kvm_lock);
d828199e
MT		 6469 list_for_each_entry(kvm, &vm_list, vm_list)
6470 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6471 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6472 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6473 spin_unlock(&kvm_lock);
16e8d74d
MT		 6474}
6475
6476static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6477
6478/*
6479 * Notification about pvclock gtod data update.
6480 */
6481static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6482 void *priv)
6483{
6484 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6485 struct timekeeper *tk = priv;
6486
6487 update_pvclock_gtod(tk);
6488
6489 /* disable master clock if host does not trust, or does not
b0c39dc6 6490 * use, TSC based clocksource.
16e8d74d 6491 */
b0c39dc6 6492 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6493 atomic_read(&kvm_guest_has_master_clock) != 0)
6494 queue_work(system_long_wq, &pvclock_gtod_work);
6495
6496 return 0;
6497}
6498
6499static struct notifier_block pvclock_gtod_notifier = {
6500 .notifier_call = pvclock_gtod_notify,
6501};
6502#endif
6503
f8c16bba 6504int kvm_arch_init(void *opaque)
043405e1 6505{
b820cc0c 6506 int r;
6b61edf7 6507 struct kvm_x86_ops *ops = opaque;
f8c16bba 6508
f8c16bba
ZX		 6509 if (kvm_x86_ops) {
6510 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6511 r = -EEXIST;
6512 goto out;
f8c16bba
ZX		 6513 }
6514
6515 if (!ops->cpu_has_kvm_support()) {
6516 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6517 r = -EOPNOTSUPP;
6518 goto out;
f8c16bba
ZX		 6519 }
6520 if (ops->disabled_by_bios()) {
6521 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6522 r = -EOPNOTSUPP;
6523 goto out;
f8c16bba
ZX		 6524 }
6525
013f6a5d
MT		 6526 r = -ENOMEM;
6527 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6528 if (!shared_msrs) {
6529 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6530 goto out;
6531 }
6532
97db56ce
AK		 6533 r = kvm_mmu_module_init();
6534 if (r)
013f6a5d 6535 goto out_free_percpu;
97db56ce 6536
ce88decf 6537 kvm_set_mmio_spte_mask();
97db56ce 6538
f8c16bba 6539 kvm_x86_ops = ops;
920c8377 6540
7b52345e 6541 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6542 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6543 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6544 kvm_timer_init();
c8076604 6545
ff9d07a0
ZY		 6546 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6547
d366bf7e 6548 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6549 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6550
c5cc421b 6551 kvm_lapic_init();
16e8d74d
MT		 6552#ifdef CONFIG_X86_64
6553 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6554
5fa4ec9c 6555 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6556 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6557#endif
6558
f8c16bba 6559 return 0;
56c6d28a 6560
013f6a5d
MT		 6561out_free_percpu:
6562 free_percpu(shared_msrs);
56c6d28a 6563out:
56c6d28a 6564 return r;
043405e1 6565}
8776e519 6566
f8c16bba
ZX		 6567void kvm_arch_exit(void)
6568{
0092e434 6569#ifdef CONFIG_X86_64
5fa4ec9c 6570 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6571 clear_hv_tscchange_cb();
6572#endif
cef84c30 6573 kvm_lapic_exit();
ff9d07a0
ZY		 6574 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6575
888d256e
JK		 6576 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6577 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6578 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6579 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6580#ifdef CONFIG_X86_64
6581 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6582#endif
f8c16bba 6583 kvm_x86_ops = NULL;
56c6d28a 6584 kvm_mmu_module_exit();
013f6a5d 6585 free_percpu(shared_msrs);
56c6d28a 6586}
f8c16bba 6587
5cb56059 6588int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6589{
6590 ++vcpu->stat.halt_exits;
35754c98 6591 if (lapic_in_kernel(vcpu)) {
a4535290 6592 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6593 return 1;
6594 } else {
6595 vcpu->run->exit_reason = KVM_EXIT_HLT;
6596 return 0;
6597 }
6598}
5cb56059
JS		 6599EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6600
6601int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6602{
6affcbed
KH		 6603 int ret = kvm_skip_emulated_instruction(vcpu);
6604 /*
6605 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6606 * KVM_EXIT_DEBUG here.
6607 */
6608 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6609}
8776e519
HB		 6610EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6611
8ef81a9a 6612#ifdef CONFIG_X86_64
55dd00a7
MT		 6613static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6614 unsigned long clock_type)
6615{
6616 struct kvm_clock_pairing clock_pairing;
6617 struct timespec ts;
80fbd89c 6618 u64 cycle;
55dd00a7
MT		 6619 int ret;
6620
6621 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6622 return -KVM_EOPNOTSUPP;
6623
6624 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6625 return -KVM_EOPNOTSUPP;
6626
6627 clock_pairing.sec = ts.tv_sec;
6628 clock_pairing.nsec = ts.tv_nsec;
6629 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6630 clock_pairing.flags = 0;
6631
6632 ret = 0;
6633 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6634 sizeof(struct kvm_clock_pairing)))
6635 ret = -KVM_EFAULT;
6636
6637 return ret;
6638}
8ef81a9a 6639#endif
55dd00a7 6640
6aef266c
SV		 6641/*
6642 * kvm_pv_kick_cpu_op: Kick a vcpu.
6643 *
6644 * @apicid - apicid of vcpu to be kicked.
6645 */
6646static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6647{
24d2166b 6648 struct kvm_lapic_irq lapic_irq;
6aef266c 6649
24d2166b
R		 6650 lapic_irq.shorthand = 0;
6651 lapic_irq.dest_mode = 0;
ebd28fcb 6652 lapic_irq.level = 0;
24d2166b 6653 lapic_irq.dest_id = apicid;
93bbf0b8 6654 lapic_irq.msi_redir_hint = false;
6aef266c 6655
24d2166b 6656 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6657 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6658}
6659
d62caabb
AS		 6660void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6661{
6662 vcpu->arch.apicv_active = false;
6663 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6664}
6665
8776e519
HB		 6666int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6667{
6668 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6669 int op_64_bit, r;
8776e519 6670
6affcbed 6671 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6672
55cd8e5a
GN		 6673 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6674 return kvm_hv_hypercall(vcpu);
6675
5fdbf976
MT		 6676 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6677 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6678 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6679 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6680 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6681
229456fc 6682 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6683
a449c7aa
NA		 6684 op_64_bit = is_64_bit_mode(vcpu);
6685 if (!op_64_bit) {
8776e519
HB		 6686 nr &= 0xFFFFFFFF;
6687 a0 &= 0xFFFFFFFF;
6688 a1 &= 0xFFFFFFFF;
6689 a2 &= 0xFFFFFFFF;
6690 a3 &= 0xFFFFFFFF;
6691 }
6692
07708c4a
JK		 6693 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6694 ret = -KVM_EPERM;
6695 goto out;
6696 }
6697
8776e519 6698 switch (nr) {
b93463aa
AK		 6699 case KVM_HC_VAPIC_POLL_IRQ:
6700 ret = 0;
6701 break;
6aef266c
SV		 6702 case KVM_HC_KICK_CPU:
6703 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6704 ret = 0;
6705 break;
8ef81a9a 6706#ifdef CONFIG_X86_64
55dd00a7
MT		 6707 case KVM_HC_CLOCK_PAIRING:
6708 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6709 break;
8ef81a9a 6710#endif
8776e519
HB		 6711 default:
6712 ret = -KVM_ENOSYS;
6713 break;
6714 }
07708c4a 6715out:
a449c7aa
NA		 6716 if (!op_64_bit)
6717 ret = (u32)ret;
5fdbf976 6718 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6719 ++vcpu->stat.hypercalls;
2f333bcb 6720 return r;
8776e519
HB		 6721}
6722EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6723
b6785def 6724static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6725{
d6aa1000 6726 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6727 char instruction[3];
5fdbf976 6728 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6729
8776e519 6730 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6731
ce2e852e
DV		 6732 return emulator_write_emulated(ctxt, rip, instruction, 3,
6733 &ctxt->exception);
8776e519
HB		 6734}
6735
851ba692 6736static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6737{
782d422b
MG		 6738 return vcpu->run->request_interrupt_window &&
6739 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6740}
6741
851ba692 6742static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6743{
851ba692
AK		 6744 struct kvm_run *kvm_run = vcpu->run;
6745
91586a3b 6746 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6747 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6748 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6749 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6750 kvm_run->ready_for_interrupt_injection =
6751 pic_in_kernel(vcpu->kvm) ||
782d422b 6752 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6753}
6754
95ba8273
GN		 6755static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6756{
6757 int max_irr, tpr;
6758
6759 if (!kvm_x86_ops->update_cr8_intercept)
6760 return;
6761
bce87cce 6762 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6763 return;
6764
d62caabb
AS		 6765 if (vcpu->arch.apicv_active)
6766 return;
6767
8db3baa2
GN		 6768 if (!vcpu->arch.apic->vapic_addr)
6769 max_irr = kvm_lapic_find_highest_irr(vcpu);
6770 else
6771 max_irr = -1;
95ba8273
GN		 6772
6773 if (max_irr != -1)
6774 max_irr >>= 4;
6775
6776 tpr = kvm_lapic_get_cr8(vcpu);
6777
6778 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6779}
6780
b6b8a145 6781static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6782{
b6b8a145
JK		 6783 int r;
6784
95ba8273 6785 /* try to reinject previous events if any */
664f8e26 6786
1a680e35
LA		 6787 if (vcpu->arch.exception.injected)
6788 kvm_x86_ops->queue_exception(vcpu);
664f8e26 6789 /*
a042c26f
LA		 6790 * Do not inject an NMI or interrupt if there is a pending
6791 * exception. Exceptions and interrupts are recognized at
6792 * instruction boundaries, i.e. the start of an instruction.
6793 * Trap-like exceptions, e.g. #DB, have higher priority than
6794 * NMIs and interrupts, i.e. traps are recognized before an
6795 * NMI/interrupt that's pending on the same instruction.
6796 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
6797 * priority, but are only generated (pended) during instruction
6798 * execution, i.e. a pending fault-like exception means the
6799 * fault occurred on the *previous* instruction and must be
6800 * serviced prior to recognizing any new events in order to
6801 * fully complete the previous instruction.
664f8e26 6802 */
1a680e35
LA		 6803 else if (!vcpu->arch.exception.pending) {
6804 if (vcpu->arch.nmi_injected)
664f8e26 6805 kvm_x86_ops->set_nmi(vcpu);
1a680e35 6806 else if (vcpu->arch.interrupt.injected)
664f8e26 6807 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 6808 }
6809
1a680e35
LA		 6810 /*
6811 * Call check_nested_events() even if we reinjected a previous event
6812 * in order for caller to determine if it should require immediate-exit
6813 * from L2 to L1 due to pending L1 events which require exit
6814 * from L2 to L1.
6815 */
664f8e26
WL		 6816 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6817 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6818 if (r != 0)
6819 return r;
6820 }
6821
6822 /* try to inject new event if pending */
b59bb7bd 6823 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6824 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6825 vcpu->arch.exception.has_error_code,
6826 vcpu->arch.exception.error_code);
d6e8c854 6827
1a680e35 6828 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 6829 vcpu->arch.exception.pending = false;
6830 vcpu->arch.exception.injected = true;
6831
d6e8c854
NA		 6832 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6833 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6834 X86_EFLAGS_RF);
6835
6bdf0662
NA		 6836 if (vcpu->arch.exception.nr == DB_VECTOR &&
6837 (vcpu->arch.dr7 & DR7_GD)) {
6838 vcpu->arch.dr7 &= ~DR7_GD;
6839 kvm_update_dr7(vcpu);
6840 }
6841
cfcd20e5 6842 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 6843 }
6844
6845 /* Don't consider new event if we re-injected an event */
6846 if (kvm_event_needs_reinjection(vcpu))
6847 return 0;
6848
6849 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
6850 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6851 vcpu->arch.smi_pending = false;
52797bf9 6852 ++vcpu->arch.smi_count;
ee2cd4b7 6853 enter_smm(vcpu);
c43203ca 6854 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6855 --vcpu->arch.nmi_pending;
6856 vcpu->arch.nmi_injected = true;
6857 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6858 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6859 /*
6860 * Because interrupts can be injected asynchronously, we are
6861 * calling check_nested_events again here to avoid a race condition.
6862 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6863 * proposal and current concerns. Perhaps we should be setting
6864 * KVM_REQ_EVENT only on certain events and not unconditionally?
6865 */
6866 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6867 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6868 if (r != 0)
6869 return r;
6870 }
95ba8273 6871 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6872 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6873 false);
6874 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6875 }
6876 }
ee2cd4b7 6877
b6b8a145 6878 return 0;
95ba8273
GN		 6879}
6880
7460fb4a
AK		 6881static void process_nmi(struct kvm_vcpu *vcpu)
6882{
6883 unsigned limit = 2;
6884
6885 /*
6886 * x86 is limited to one NMI running, and one NMI pending after it.
6887 * If an NMI is already in progress, limit further NMIs to just one.
6888 * Otherwise, allow two (and we'll inject the first one immediately).
6889 */
6890 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6891 limit = 1;
6892
6893 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6894 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6895 kvm_make_request(KVM_REQ_EVENT, vcpu);
6896}
6897
ee2cd4b7 6898static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6899{
6900 u32 flags = 0;
6901 flags |= seg->g << 23;
6902 flags |= seg->db << 22;
6903 flags |= seg->l << 21;
6904 flags |= seg->avl << 20;
6905 flags |= seg->present << 15;
6906 flags |= seg->dpl << 13;
6907 flags |= seg->s << 12;
6908 flags |= seg->type << 8;
6909 return flags;
6910}
6911
ee2cd4b7 6912static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6913{
6914 struct kvm_segment seg;
6915 int offset;
6916
6917 kvm_get_segment(vcpu, &seg, n);
6918 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6919
6920 if (n < 3)
6921 offset = 0x7f84 + n * 12;
6922 else
6923 offset = 0x7f2c + (n - 3) * 12;
6924
6925 put_smstate(u32, buf, offset + 8, seg.base);
6926 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6927 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6928}
6929
efbb288a 6930#ifdef CONFIG_X86_64
ee2cd4b7 6931static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6932{
6933 struct kvm_segment seg;
6934 int offset;
6935 u16 flags;
6936
6937 kvm_get_segment(vcpu, &seg, n);
6938 offset = 0x7e00 + n * 16;
6939
ee2cd4b7 6940 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6941 put_smstate(u16, buf, offset, seg.selector);
6942 put_smstate(u16, buf, offset + 2, flags);
6943 put_smstate(u32, buf, offset + 4, seg.limit);
6944 put_smstate(u64, buf, offset + 8, seg.base);
6945}
efbb288a 6946#endif
660a5d51 6947
ee2cd4b7 6948static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6949{
6950 struct desc_ptr dt;
6951 struct kvm_segment seg;
6952 unsigned long val;
6953 int i;
6954
6955 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6956 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6957 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6958 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6959
6960 for (i = 0; i < 8; i++)
6961 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6962
6963 kvm_get_dr(vcpu, 6, &val);
6964 put_smstate(u32, buf, 0x7fcc, (u32)val);
6965 kvm_get_dr(vcpu, 7, &val);
6966 put_smstate(u32, buf, 0x7fc8, (u32)val);
6967
6968 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6969 put_smstate(u32, buf, 0x7fc4, seg.selector);
6970 put_smstate(u32, buf, 0x7f64, seg.base);
6971 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6972 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6973
6974 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6975 put_smstate(u32, buf, 0x7fc0, seg.selector);
6976 put_smstate(u32, buf, 0x7f80, seg.base);
6977 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6978 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6979
6980 kvm_x86_ops->get_gdt(vcpu, &dt);
6981 put_smstate(u32, buf, 0x7f74, dt.address);
6982 put_smstate(u32, buf, 0x7f70, dt.size);
6983
6984 kvm_x86_ops->get_idt(vcpu, &dt);
6985 put_smstate(u32, buf, 0x7f58, dt.address);
6986 put_smstate(u32, buf, 0x7f54, dt.size);
6987
6988 for (i = 0; i < 6; i++)
ee2cd4b7 6989 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6990
6991 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6992
6993 /* revision id */
6994 put_smstate(u32, buf, 0x7efc, 0x00020000);
6995 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6996}
6997
ee2cd4b7 6998static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6999{
7000#ifdef CONFIG_X86_64
7001 struct desc_ptr dt;
7002 struct kvm_segment seg;
7003 unsigned long val;
7004 int i;
7005
7006 for (i = 0; i < 16; i++)
7007 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7008
7009 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7010 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7011
7012 kvm_get_dr(vcpu, 6, &val);
7013 put_smstate(u64, buf, 0x7f68, val);
7014 kvm_get_dr(vcpu, 7, &val);
7015 put_smstate(u64, buf, 0x7f60, val);
7016
7017 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7018 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7019 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7020
7021 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7022
7023 /* revision id */
7024 put_smstate(u32, buf, 0x7efc, 0x00020064);
7025
7026 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7027
7028 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7029 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7030 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7031 put_smstate(u32, buf, 0x7e94, seg.limit);
7032 put_smstate(u64, buf, 0x7e98, seg.base);
7033
7034 kvm_x86_ops->get_idt(vcpu, &dt);
7035 put_smstate(u32, buf, 0x7e84, dt.size);
7036 put_smstate(u64, buf, 0x7e88, dt.address);
7037
7038 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7039 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7040 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7041 put_smstate(u32, buf, 0x7e74, seg.limit);
7042 put_smstate(u64, buf, 0x7e78, seg.base);
7043
7044 kvm_x86_ops->get_gdt(vcpu, &dt);
7045 put_smstate(u32, buf, 0x7e64, dt.size);
7046 put_smstate(u64, buf, 0x7e68, dt.address);
7047
7048 for (i = 0; i < 6; i++)
ee2cd4b7 7049 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7050#else
7051 WARN_ON_ONCE(1);
7052#endif
7053}
7054
ee2cd4b7 7055static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7056{
660a5d51 7057 struct kvm_segment cs, ds;
18c3626e 7058 struct desc_ptr dt;
660a5d51
PB		 7059 char buf[512];
7060 u32 cr0;
7061
660a5d51 7062 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7063 memset(buf, 0, 512);
d6321d49 7064 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7065 enter_smm_save_state_64(vcpu, buf);
660a5d51 7066 else
ee2cd4b7 7067 enter_smm_save_state_32(vcpu, buf);
660a5d51 7068
0234bf88
LP		 7069 /*
7070 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7071 * vCPU state (e.g. leave guest mode) after we've saved the state into
7072 * the SMM state-save area.
7073 */
7074 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7075
7076 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7077 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7078
7079 if (kvm_x86_ops->get_nmi_mask(vcpu))
7080 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7081 else
7082 kvm_x86_ops->set_nmi_mask(vcpu, true);
7083
7084 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7085 kvm_rip_write(vcpu, 0x8000);
7086
7087 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7088 kvm_x86_ops->set_cr0(vcpu, cr0);
7089 vcpu->arch.cr0 = cr0;
7090
7091 kvm_x86_ops->set_cr4(vcpu, 0);
7092
18c3626e
PB		 7093 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7094 dt.address = dt.size = 0;
7095 kvm_x86_ops->set_idt(vcpu, &dt);
7096
660a5d51
PB		 7097 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7098
7099 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7100 cs.base = vcpu->arch.smbase;
7101
7102 ds.selector = 0;
7103 ds.base = 0;
7104
7105 cs.limit = ds.limit = 0xffffffff;
7106 cs.type = ds.type = 0x3;
7107 cs.dpl = ds.dpl = 0;
7108 cs.db = ds.db = 0;
7109 cs.s = ds.s = 1;
7110 cs.l = ds.l = 0;
7111 cs.g = ds.g = 1;
7112 cs.avl = ds.avl = 0;
7113 cs.present = ds.present = 1;
7114 cs.unusable = ds.unusable = 0;
7115 cs.padding = ds.padding = 0;
7116
7117 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7118 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7119 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7120 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7121 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7122 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7123
d6321d49 7124 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7125 kvm_x86_ops->set_efer(vcpu, 0);
7126
7127 kvm_update_cpuid(vcpu);
7128 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7129}
7130
ee2cd4b7 7131static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7132{
7133 vcpu->arch.smi_pending = true;
7134 kvm_make_request(KVM_REQ_EVENT, vcpu);
7135}
7136
2860c4b1
PB		 7137void kvm_make_scan_ioapic_request(struct kvm *kvm)
7138{
7139 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7140}
7141
3d81bc7e 7142static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7143{
3d81bc7e
YZ		 7144 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7145 return;
c7c9c56c 7146
6308630b 7147 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7148
b053b2ae 7149 if (irqchip_split(vcpu->kvm))
6308630b 7150 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7151 else {
fa59cc00 7152 if (vcpu->arch.apicv_active)
d62caabb 7153 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7154 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7155 }
e40ff1d6
LA		 7156
7157 if (is_guest_mode(vcpu))
7158 vcpu->arch.load_eoi_exitmap_pending = true;
7159 else
7160 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7161}
7162
7163static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7164{
7165 u64 eoi_exit_bitmap[4];
7166
7167 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7168 return;
7169
5c919412
AS		 7170 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7171 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7172 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7173}
7174
b1394e74
RK		 7175void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7176 unsigned long start, unsigned long end)
7177{
7178 unsigned long apic_address;
7179
7180 /*
7181 * The physical address of apic access page is stored in the VMCS.
7182 * Update it when it becomes invalid.
7183 */
7184 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7185 if (start <= apic_address && apic_address < end)
7186 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7187}
7188
4256f43f
TC		 7189void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7190{
c24ae0dc
TC		 7191 struct page *page = NULL;
7192
35754c98 7193 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7194 return;
7195
4256f43f
TC		 7196 if (!kvm_x86_ops->set_apic_access_page_addr)
7197 return;
7198
c24ae0dc 7199 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7200 if (is_error_page(page))
7201 return;
c24ae0dc
TC		 7202 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7203
7204 /*
7205 * Do not pin apic access page in memory, the MMU notifier
7206 * will call us again if it is migrated or swapped out.
7207 */
7208 put_page(page);
4256f43f
TC		 7209}
7210EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7211
9357d939 7212/*
362c698f 7213 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7214 * exiting to the userspace. Otherwise, the value will be returned to the
7215 * userspace.
7216 */
851ba692 7217static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7218{
7219 int r;
62a193ed
MG		 7220 bool req_int_win =
7221 dm_request_for_irq_injection(vcpu) &&
7222 kvm_cpu_accept_dm_intr(vcpu);
7223
730dca42 7224 bool req_immediate_exit = false;
b6c7a5dc 7225
2fa6e1e1 7226 if (kvm_request_pending(vcpu)) {
a8eeb04a 7227 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7228 kvm_mmu_unload(vcpu);
a8eeb04a 7229 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7230 __kvm_migrate_timers(vcpu);
d828199e
MT		 7231 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7232 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7233 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7234 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7235 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7236 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7237 if (unlikely(r))
7238 goto out;
7239 }
a8eeb04a 7240 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7241 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7242 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7243 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7244 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7245 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7246 r = 0;
7247 goto out;
7248 }
a8eeb04a 7249 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7250 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7251 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7252 r = 0;
7253 goto out;
7254 }
af585b92
GN		 7255 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7256 /* Page is swapped out. Do synthetic halt */
7257 vcpu->arch.apf.halted = true;
7258 r = 1;
7259 goto out;
7260 }
c9aaa895
GC		 7261 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7262 record_steal_time(vcpu);
64d60670
PB		 7263 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7264 process_smi(vcpu);
7460fb4a
AK		 7265 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7266 process_nmi(vcpu);
f5132b01 7267 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7268 kvm_pmu_handle_event(vcpu);
f5132b01 7269 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7270 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7271 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7272 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7273 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7274 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7275 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7276 vcpu->run->eoi.vector =
7277 vcpu->arch.pending_ioapic_eoi;
7278 r = 0;
7279 goto out;
7280 }
7281 }
3d81bc7e
YZ		 7282 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7283 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7284 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7285 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7286 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7287 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7288 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7289 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7290 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7291 r = 0;
7292 goto out;
7293 }
e516cebb
AS		 7294 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7295 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7296 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7297 r = 0;
7298 goto out;
7299 }
db397571
AS		 7300 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7301 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7302 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7303 r = 0;
7304 goto out;
7305 }
f3b138c5
AS		 7306
7307 /*
7308 * KVM_REQ_HV_STIMER has to be processed after
7309 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7310 * depend on the guest clock being up-to-date
7311 */
1f4b34f8
AS		 7312 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7313 kvm_hv_process_stimers(vcpu);
2f52d58c 7314 }
b93463aa 7315
b463a6f7 7316 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7317 ++vcpu->stat.req_event;
66450a21
JK		 7318 kvm_apic_accept_events(vcpu);
7319 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7320 r = 1;
7321 goto out;
7322 }
7323
b6b8a145
JK		 7324 if (inject_pending_event(vcpu, req_int_win) != 0)
7325 req_immediate_exit = true;
321c5658 7326 else {
cc3d967f 7327 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7328 *
cc3d967f
LP		 7329 * SMIs have three cases:
7330 * 1) They can be nested, and then there is nothing to
7331 * do here because RSM will cause a vmexit anyway.
7332 * 2) There is an ISA-specific reason why SMI cannot be
7333 * injected, and the moment when this changes can be
7334 * intercepted.
7335 * 3) Or the SMI can be pending because
7336 * inject_pending_event has completed the injection
7337 * of an IRQ or NMI from the previous vmexit, and
7338 * then we request an immediate exit to inject the
7339 * SMI.
c43203ca
PB		 7340 */
7341 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7342 if (!kvm_x86_ops->enable_smi_window(vcpu))
7343 req_immediate_exit = true;
321c5658
YS		 7344 if (vcpu->arch.nmi_pending)
7345 kvm_x86_ops->enable_nmi_window(vcpu);
7346 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7347 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7348 WARN_ON(vcpu->arch.exception.pending);
321c5658 7349 }
b463a6f7
AK		 7350
7351 if (kvm_lapic_enabled(vcpu)) {
7352 update_cr8_intercept(vcpu);
7353 kvm_lapic_sync_to_vapic(vcpu);
7354 }
7355 }
7356
d8368af8
AK		 7357 r = kvm_mmu_reload(vcpu);
7358 if (unlikely(r)) {
d905c069 7359 goto cancel_injection;
d8368af8
AK		 7360 }
7361
b6c7a5dc
HB		 7362 preempt_disable();
7363
7364 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7365
7366 /*
7367 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7368 * IPI are then delayed after guest entry, which ensures that they
7369 * result in virtual interrupt delivery.
7370 */
7371 local_irq_disable();
6b7e2d09
XG		 7372 vcpu->mode = IN_GUEST_MODE;
7373
01b71917
MT		 7374 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7375
0f127d12 7376 /*
b95234c8 7377 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7378 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7379 *
7380 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7381 * pairs with the memory barrier implicit in pi_test_and_set_on
7382 * (see vmx_deliver_posted_interrupt).
7383 *
7384 * 3) This also orders the write to mode from any reads to the page
7385 * tables done while the VCPU is running. Please see the comment
7386 * in kvm_flush_remote_tlbs.
6b7e2d09 7387 */
01b71917 7388 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7389
b95234c8
PB		 7390 /*
7391 * This handles the case where a posted interrupt was
7392 * notified with kvm_vcpu_kick.
7393 */
fa59cc00
LA		 7394 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7395 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7396
2fa6e1e1 7397 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7398 || need_resched() || signal_pending(current)) {
6b7e2d09 7399 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7400 smp_wmb();
6c142801
AK		 7401 local_irq_enable();
7402 preempt_enable();
01b71917 7403 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7404 r = 1;
d905c069 7405 goto cancel_injection;
6c142801
AK		 7406 }
7407
fc5b7f3b
DM		 7408 kvm_load_guest_xcr0(vcpu);
7409
c43203ca
PB		 7410 if (req_immediate_exit) {
7411 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7412 smp_send_reschedule(vcpu->cpu);
c43203ca 7413 }
d6185f20 7414
8b89fe1f 7415 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7416 if (lapic_timer_advance_ns)
7417 wait_lapic_expire(vcpu);
6edaa530 7418 guest_enter_irqoff();
b6c7a5dc 7419
42dbaa5a 7420 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7421 set_debugreg(0, 7);
7422 set_debugreg(vcpu->arch.eff_db[0], 0);
7423 set_debugreg(vcpu->arch.eff_db[1], 1);
7424 set_debugreg(vcpu->arch.eff_db[2], 2);
7425 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7426 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7427 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7428 }
b6c7a5dc 7429
851ba692 7430 kvm_x86_ops->run(vcpu);
b6c7a5dc 7431
c77fb5fe
PB		 7432 /*
7433 * Do this here before restoring debug registers on the host. And
7434 * since we do this before handling the vmexit, a DR access vmexit
7435 * can (a) read the correct value of the debug registers, (b) set
7436 * KVM_DEBUGREG_WONT_EXIT again.
7437 */
7438 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7439 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7440 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7441 kvm_update_dr0123(vcpu);
7442 kvm_update_dr6(vcpu);
7443 kvm_update_dr7(vcpu);
7444 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7445 }
7446
24f1e32c
FW		 7447 /*
7448 * If the guest has used debug registers, at least dr7
7449 * will be disabled while returning to the host.
7450 * If we don't have active breakpoints in the host, we don't
7451 * care about the messed up debug address registers. But if
7452 * we have some of them active, restore the old state.
7453 */
59d8eb53 7454 if (hw_breakpoint_active())
24f1e32c 7455 hw_breakpoint_restore();
42dbaa5a 7456
4ba76538 7457 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7458
6b7e2d09 7459 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7460 smp_wmb();
a547c6db 7461
fc5b7f3b
DM		 7462 kvm_put_guest_xcr0(vcpu);
7463
dd60d217 7464 kvm_before_interrupt(vcpu);
a547c6db 7465 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7466 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7467
7468 ++vcpu->stat.exits;
7469
f2485b3e 7470 guest_exit_irqoff();
b6c7a5dc 7471
f2485b3e 7472 local_irq_enable();
b6c7a5dc
HB		 7473 preempt_enable();
7474
f656ce01 7475 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7476
b6c7a5dc
HB		 7477 /*
7478 * Profile KVM exit RIPs:
7479 */
7480 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7481 unsigned long rip = kvm_rip_read(vcpu);
7482 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7483 }
7484
cc578287
ZA		 7485 if (unlikely(vcpu->arch.tsc_always_catchup))
7486 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7487
5cfb1d5a
MT		 7488 if (vcpu->arch.apic_attention)
7489 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7490
618232e2 7491 vcpu->arch.gpa_available = false;
851ba692 7492 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7493 return r;
7494
7495cancel_injection:
7496 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7497 if (unlikely(vcpu->arch.apic_attention))
7498 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7499out:
7500 return r;
7501}
b6c7a5dc 7502
362c698f
PB		 7503static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7504{
bf9f6ac8
FW		 7505 if (!kvm_arch_vcpu_runnable(vcpu) &&
7506 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7507 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7508 kvm_vcpu_block(vcpu);
7509 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7510
7511 if (kvm_x86_ops->post_block)
7512 kvm_x86_ops->post_block(vcpu);
7513
9c8fd1ba
PB		 7514 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7515 return 1;
7516 }
362c698f
PB		 7517
7518 kvm_apic_accept_events(vcpu);
7519 switch(vcpu->arch.mp_state) {
7520 case KVM_MP_STATE_HALTED:
7521 vcpu->arch.pv.pv_unhalted = false;
7522 vcpu->arch.mp_state =
7523 KVM_MP_STATE_RUNNABLE;
7524 case KVM_MP_STATE_RUNNABLE:
7525 vcpu->arch.apf.halted = false;
7526 break;
7527 case KVM_MP_STATE_INIT_RECEIVED:
7528 break;
7529 default:
7530 return -EINTR;
7531 break;
7532 }
7533 return 1;
7534}
09cec754 7535
5d9bc648
PB		 7536static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7537{
0ad3bed6
PB		 7538 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7539 kvm_x86_ops->check_nested_events(vcpu, false);
7540
5d9bc648
PB		 7541 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7542 !vcpu->arch.apf.halted);
7543}
7544
362c698f 7545static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7546{
7547 int r;
f656ce01 7548 struct kvm *kvm = vcpu->kvm;
d7690175 7549
f656ce01 7550 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7551
362c698f 7552 for (;;) {
58f800d5 7553 if (kvm_vcpu_running(vcpu)) {
851ba692 7554 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7555 } else {
362c698f 7556 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7557 }
7558
09cec754
GN		 7559 if (r <= 0)
7560 break;
7561
72875d8a 7562 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7563 if (kvm_cpu_has_pending_timer(vcpu))
7564 kvm_inject_pending_timer_irqs(vcpu);
7565
782d422b
MG		 7566 if (dm_request_for_irq_injection(vcpu) &&
7567 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7568 r = 0;
7569 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7570 ++vcpu->stat.request_irq_exits;
362c698f 7571 break;
09cec754 7572 }
af585b92
GN		 7573
7574 kvm_check_async_pf_completion(vcpu);
7575
09cec754
GN		 7576 if (signal_pending(current)) {
7577 r = -EINTR;
851ba692 7578 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7579 ++vcpu->stat.signal_exits;
362c698f 7580 break;
09cec754
GN		 7581 }
7582 if (need_resched()) {
f656ce01 7583 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7584 cond_resched();
f656ce01 7585 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7586 }
b6c7a5dc
HB		 7587 }
7588
f656ce01 7589 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7590
7591 return r;
7592}
7593
716d51ab
GN		 7594static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7595{
7596 int r;
7597 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7598 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7599 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7600 if (r != EMULATE_DONE)
7601 return 0;
7602 return 1;
7603}
7604
7605static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7606{
7607 BUG_ON(!vcpu->arch.pio.count);
7608
7609 return complete_emulated_io(vcpu);
7610}
7611
f78146b0
AK		 7612/*
7613 * Implements the following, as a state machine:
7614 *
7615 * read:
7616 * for each fragment
87da7e66
XG		 7617 * for each mmio piece in the fragment
7618 * write gpa, len
7619 * exit
7620 * copy data
f78146b0
AK		 7621 * execute insn
7622 *
7623 * write:
7624 * for each fragment
87da7e66
XG		 7625 * for each mmio piece in the fragment
7626 * write gpa, len
7627 * copy data
7628 * exit
f78146b0 7629 */
716d51ab 7630static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7631{
7632 struct kvm_run *run = vcpu->run;
f78146b0 7633 struct kvm_mmio_fragment *frag;
87da7e66 7634 unsigned len;
5287f194 7635
716d51ab 7636 BUG_ON(!vcpu->mmio_needed);
5287f194 7637
716d51ab 7638 /* Complete previous fragment */
87da7e66
XG		 7639 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7640 len = min(8u, frag->len);
716d51ab 7641 if (!vcpu->mmio_is_write)
87da7e66
XG		 7642 memcpy(frag->data, run->mmio.data, len);
7643
7644 if (frag->len <= 8) {
7645 /* Switch to the next fragment. */
7646 frag++;
7647 vcpu->mmio_cur_fragment++;
7648 } else {
7649 /* Go forward to the next mmio piece. */
7650 frag->data += len;
7651 frag->gpa += len;
7652 frag->len -= len;
7653 }
7654
a08d3b3b 7655 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7656 vcpu->mmio_needed = 0;
0912c977
PB		 7657
7658 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7659 if (vcpu->mmio_is_write)
716d51ab
GN		 7660 return 1;
7661 vcpu->mmio_read_completed = 1;
7662 return complete_emulated_io(vcpu);
7663 }
87da7e66 7664
716d51ab
GN		 7665 run->exit_reason = KVM_EXIT_MMIO;
7666 run->mmio.phys_addr = frag->gpa;
7667 if (vcpu->mmio_is_write)
87da7e66
XG		 7668 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7669 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7670 run->mmio.is_write = vcpu->mmio_is_write;
7671 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7672 return 0;
5287f194
AK		 7673}
7674
b6c7a5dc
HB		 7675int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7676{
7677 int r;
b6c7a5dc 7678
accb757d 7679 vcpu_load(vcpu);
20b7035c 7680 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7681 kvm_load_guest_fpu(vcpu);
7682
a4535290 7683 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7684 if (kvm_run->immediate_exit) {
7685 r = -EINTR;
7686 goto out;
7687 }
b6c7a5dc 7688 kvm_vcpu_block(vcpu);
66450a21 7689 kvm_apic_accept_events(vcpu);
72875d8a 7690 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7691 r = -EAGAIN;
a0595000
JS		 7692 if (signal_pending(current)) {
7693 r = -EINTR;
7694 vcpu->run->exit_reason = KVM_EXIT_INTR;
7695 ++vcpu->stat.signal_exits;
7696 }
ac9f6dc0 7697 goto out;
b6c7a5dc
HB		 7698 }
7699
01643c51
KH		 7700 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7701 r = -EINVAL;
7702 goto out;
7703 }
7704
7705 if (vcpu->run->kvm_dirty_regs) {
7706 r = sync_regs(vcpu);
7707 if (r != 0)
7708 goto out;
7709 }
7710
b6c7a5dc 7711 /* re-sync apic's tpr */
35754c98 7712 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7713 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7714 r = -EINVAL;
7715 goto out;
7716 }
7717 }
b6c7a5dc 7718
716d51ab
GN		 7719 if (unlikely(vcpu->arch.complete_userspace_io)) {
7720 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7721 vcpu->arch.complete_userspace_io = NULL;
7722 r = cui(vcpu);
7723 if (r <= 0)
5663d8f9 7724 goto out;
716d51ab
GN		 7725 } else
7726 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7727
460df4c1
PB		 7728 if (kvm_run->immediate_exit)
7729 r = -EINTR;
7730 else
7731 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7732
7733out:
5663d8f9 7734 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7735 if (vcpu->run->kvm_valid_regs)
7736 store_regs(vcpu);
f1d86e46 7737 post_kvm_run_save(vcpu);
20b7035c 7738 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7739
accb757d 7740 vcpu_put(vcpu);
b6c7a5dc
HB		 7741 return r;
7742}
7743
01643c51 7744static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7745{
7ae441ea
GN		 7746 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7747 /*
7748 * We are here if userspace calls get_regs() in the middle of
7749 * instruction emulation. Registers state needs to be copied
4a969980 7750 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7751 * that usually, but some bad designed PV devices (vmware
7752 * backdoor interface) need this to work
7753 */
dd856efa 7754 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7755 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7756 }
5fdbf976
MT		 7757 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7758 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7759 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7760 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7761 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7762 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7763 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7764 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7765#ifdef CONFIG_X86_64
5fdbf976
MT		 7766 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7767 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7768 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7769 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7770 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7771 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7772 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7773 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7774#endif
7775
5fdbf976 7776 regs->rip = kvm_rip_read(vcpu);
91586a3b 7777 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7778}
b6c7a5dc 7779
01643c51
KH		 7780int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7781{
7782 vcpu_load(vcpu);
7783 __get_regs(vcpu, regs);
1fc9b76b 7784 vcpu_put(vcpu);
b6c7a5dc
HB		 7785 return 0;
7786}
7787
01643c51 7788static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7789{
7ae441ea
GN		 7790 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7791 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7792
5fdbf976
MT		 7793 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7794 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7795 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7796 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7797 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7798 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7799 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7800 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7801#ifdef CONFIG_X86_64
5fdbf976
MT		 7802 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7803 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7804 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7805 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7806 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7807 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7808 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7809 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7810#endif
7811
5fdbf976 7812 kvm_rip_write(vcpu, regs->rip);
d73235d1 7813 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7814
b4f14abd
JK		 7815 vcpu->arch.exception.pending = false;
7816
3842d135 7817 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7818}
3842d135 7819
01643c51
KH		 7820int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7821{
7822 vcpu_load(vcpu);
7823 __set_regs(vcpu, regs);
875656fe 7824 vcpu_put(vcpu);
b6c7a5dc
HB		 7825 return 0;
7826}
7827
b6c7a5dc
HB		 7828void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7829{
7830 struct kvm_segment cs;
7831
3e6e0aab 7832 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7833 *db = cs.db;
7834 *l = cs.l;
7835}
7836EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7837
01643c51 7838static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7839{
89a27f4d 7840 struct desc_ptr dt;
b6c7a5dc 7841
3e6e0aab
GT		 7842 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7843 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7844 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7845 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7846 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7847 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7848
3e6e0aab
GT		 7849 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7850 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7851
7852 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7853 sregs->idt.limit = dt.size;
7854 sregs->idt.base = dt.address;
b6c7a5dc 7855 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7856 sregs->gdt.limit = dt.size;
7857 sregs->gdt.base = dt.address;
b6c7a5dc 7858
4d4ec087 7859 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7860 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7861 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7862 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7863 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7864 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7865 sregs->apic_base = kvm_get_apic_base(vcpu);
7866
923c61bb 7867 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7868
04140b41 7869 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7870 set_bit(vcpu->arch.interrupt.nr,
7871 (unsigned long *)sregs->interrupt_bitmap);
01643c51 7872}
16d7a191 7873
01643c51
KH		 7874int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7875 struct kvm_sregs *sregs)
7876{
7877 vcpu_load(vcpu);
7878 __get_sregs(vcpu, sregs);
bcdec41c 7879 vcpu_put(vcpu);
b6c7a5dc
HB		 7880 return 0;
7881}
7882
62d9f0db
MT		 7883int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7884 struct kvm_mp_state *mp_state)
7885{
fd232561
CD		 7886 vcpu_load(vcpu);
7887
66450a21 7888 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7889 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7890 vcpu->arch.pv.pv_unhalted)
7891 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7892 else
7893 mp_state->mp_state = vcpu->arch.mp_state;
7894
fd232561 7895 vcpu_put(vcpu);
62d9f0db
MT		 7896 return 0;
7897}
7898
7899int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7900 struct kvm_mp_state *mp_state)
7901{
e83dff5e
CD		 7902 int ret = -EINVAL;
7903
7904 vcpu_load(vcpu);
7905
bce87cce 7906 if (!lapic_in_kernel(vcpu) &&
66450a21 7907 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7908 goto out;
66450a21 7909
28bf2888
DH		 7910 /* INITs are latched while in SMM */
7911 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7912 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7913 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7914 goto out;
28bf2888 7915
66450a21
JK		 7916 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7917 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7918 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7919 } else
7920 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7921 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7922
7923 ret = 0;
7924out:
7925 vcpu_put(vcpu);
7926 return ret;
62d9f0db
MT		 7927}
7928
7f3d35fd
KW		 7929int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7930 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7931{
9d74191a 7932 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7933 int ret;
e01c2426 7934
8ec4722d 7935 init_emulate_ctxt(vcpu);
c697518a 7936
7f3d35fd 7937 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7938 has_error_code, error_code);
c697518a 7939
c697518a 7940 if (ret)
19d04437 7941 return EMULATE_FAIL;
37817f29 7942
9d74191a
TY		 7943 kvm_rip_write(vcpu, ctxt->eip);
7944 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7945 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7946 return EMULATE_DONE;
37817f29
IE		 7947}
7948EXPORT_SYMBOL_GPL(kvm_task_switch);
7949
3140c156 7950static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 7951{
37b95951 7952 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7953 /*
7954 * When EFER.LME and CR0.PG are set, the processor is in
7955 * 64-bit mode (though maybe in a 32-bit code segment).
7956 * CR4.PAE and EFER.LMA must be set.
7957 */
37b95951 7958 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7959 || !(sregs->efer & EFER_LMA))
7960 return -EINVAL;
7961 } else {
7962 /*
7963 * Not in 64-bit mode: EFER.LMA is clear and the code
7964 * segment cannot be 64-bit.
7965 */
7966 if (sregs->efer & EFER_LMA || sregs->cs.l)
7967 return -EINVAL;
7968 }
7969
7970 return 0;
7971}
7972
01643c51 7973static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7974{
58cb628d 7975 struct msr_data apic_base_msr;
b6c7a5dc 7976 int mmu_reset_needed = 0;
63f42e02 7977 int pending_vec, max_bits, idx;
89a27f4d 7978 struct desc_ptr dt;
b4ef9d4e
CD		 7979 int ret = -EINVAL;
7980
d6321d49
RK		 7981 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7982 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7983 goto out;
6d1068b3 7984
f2981033 7985 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 7986 goto out;
f2981033 7987
d3802286
JM		 7988 apic_base_msr.data = sregs->apic_base;
7989 apic_base_msr.host_initiated = true;
7990 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 7991 goto out;
6d1068b3 7992
89a27f4d
GN		 7993 dt.size = sregs->idt.limit;
7994 dt.address = sregs->idt.base;
b6c7a5dc 7995 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7996 dt.size = sregs->gdt.limit;
7997 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7998 kvm_x86_ops->set_gdt(vcpu, &dt);
7999
ad312c7c 8000 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8001 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8002 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8003 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8004
2d3ad1f4 8005 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8006
f6801dff 8007 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8008 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8009
4d4ec087 8010 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8011 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8012 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8013
fc78f519 8014 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 8015 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 8016 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 8017 kvm_update_cpuid(vcpu);
63f42e02
XG		 8018
8019 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 8020 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 8021 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8022 mmu_reset_needed = 1;
8023 }
63f42e02 8024 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8025
8026 if (mmu_reset_needed)
8027 kvm_mmu_reset_context(vcpu);
8028
a50abc3b 8029 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8030 pending_vec = find_first_bit(
8031 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8032 if (pending_vec < max_bits) {
66fd3f7f 8033 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8034 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8035 }
8036
3e6e0aab
GT		 8037 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8038 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8039 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8040 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8041 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8042 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8043
3e6e0aab
GT		 8044 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8045 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8046
5f0269f5
ME		 8047 update_cr8_intercept(vcpu);
8048
9c3e4aab 8049 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8050 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8051 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8052 !is_protmode(vcpu))
9c3e4aab
MT		 8053 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8054
3842d135
AK		 8055 kvm_make_request(KVM_REQ_EVENT, vcpu);
8056
b4ef9d4e
CD		 8057 ret = 0;
8058out:
01643c51
KH		 8059 return ret;
8060}
8061
8062int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8063 struct kvm_sregs *sregs)
8064{
8065 int ret;
8066
8067 vcpu_load(vcpu);
8068 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8069 vcpu_put(vcpu);
8070 return ret;
b6c7a5dc
HB		 8071}
8072
d0bfb940
JK		 8073int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8074 struct kvm_guest_debug *dbg)
b6c7a5dc 8075{
355be0b9 8076 unsigned long rflags;
ae675ef0 8077 int i, r;
b6c7a5dc 8078
66b56562
CD		 8079 vcpu_load(vcpu);
8080
4f926bf2
JK		 8081 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8082 r = -EBUSY;
8083 if (vcpu->arch.exception.pending)
2122ff5e 8084 goto out;
4f926bf2
JK		 8085 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8086 kvm_queue_exception(vcpu, DB_VECTOR);
8087 else
8088 kvm_queue_exception(vcpu, BP_VECTOR);
8089 }
8090
91586a3b
JK		 8091 /*
8092 * Read rflags as long as potentially injected trace flags are still
8093 * filtered out.
8094 */
8095 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8096
8097 vcpu->guest_debug = dbg->control;
8098 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8099 vcpu->guest_debug = 0;
8100
8101 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8102 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8103 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8104 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8105 } else {
8106 for (i = 0; i < KVM_NR_DB_REGS; i++)
8107 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8108 }
c8639010 8109 kvm_update_dr7(vcpu);
ae675ef0 8110
f92653ee
JK		 8111 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8112 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8113 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8114
91586a3b
JK		 8115 /*
8116 * Trigger an rflags update that will inject or remove the trace
8117 * flags.
8118 */
8119 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8120
a96036b8 8121 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8122
4f926bf2 8123 r = 0;
d0bfb940 8124
2122ff5e 8125out:
66b56562 8126 vcpu_put(vcpu);
b6c7a5dc
HB		 8127 return r;
8128}
8129
8b006791
ZX		 8130/*
8131 * Translate a guest virtual address to a guest physical address.
8132 */
8133int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8134 struct kvm_translation *tr)
8135{
8136 unsigned long vaddr = tr->linear_address;
8137 gpa_t gpa;
f656ce01 8138 int idx;
8b006791 8139
1da5b61d
CD		 8140 vcpu_load(vcpu);
8141
f656ce01 8142 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8143 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8144 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8145 tr->physical_address = gpa;
8146 tr->valid = gpa != UNMAPPED_GVA;
8147 tr->writeable = 1;
8148 tr->usermode = 0;
8b006791 8149
1da5b61d 8150 vcpu_put(vcpu);
8b006791
ZX		 8151 return 0;
8152}
8153
d0752060
HB		 8154int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8155{
1393123e 8156 struct fxregs_state *fxsave;
d0752060 8157
1393123e 8158 vcpu_load(vcpu);
d0752060 8159
1393123e 8160 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8161 memcpy(fpu->fpr, fxsave->st_space, 128);
8162 fpu->fcw = fxsave->cwd;
8163 fpu->fsw = fxsave->swd;
8164 fpu->ftwx = fxsave->twd;
8165 fpu->last_opcode = fxsave->fop;
8166 fpu->last_ip = fxsave->rip;
8167 fpu->last_dp = fxsave->rdp;
8168 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8169
1393123e 8170 vcpu_put(vcpu);
d0752060
HB		 8171 return 0;
8172}
8173
8174int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8175{
6a96bc7f
CD		 8176 struct fxregs_state *fxsave;
8177
8178 vcpu_load(vcpu);
8179
8180 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8181
d0752060
HB		 8182 memcpy(fxsave->st_space, fpu->fpr, 128);
8183 fxsave->cwd = fpu->fcw;
8184 fxsave->swd = fpu->fsw;
8185 fxsave->twd = fpu->ftwx;
8186 fxsave->fop = fpu->last_opcode;
8187 fxsave->rip = fpu->last_ip;
8188 fxsave->rdp = fpu->last_dp;
8189 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8190
6a96bc7f 8191 vcpu_put(vcpu);
d0752060
HB		 8192 return 0;
8193}
8194
01643c51
KH		 8195static void store_regs(struct kvm_vcpu *vcpu)
8196{
8197 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8198
8199 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8200 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8201
8202 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8203 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8204
8205 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8206 kvm_vcpu_ioctl_x86_get_vcpu_events(
8207 vcpu, &vcpu->run->s.regs.events);
8208}
8209
8210static int sync_regs(struct kvm_vcpu *vcpu)
8211{
8212 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8213 return -EINVAL;
8214
8215 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8216 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8217 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8218 }
8219 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8220 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8221 return -EINVAL;
8222 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8223 }
8224 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8225 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8226 vcpu, &vcpu->run->s.regs.events))
8227 return -EINVAL;
8228 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8229 }
8230
8231 return 0;
8232}
8233
0ee6a517 8234static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8235{
bf935b0b 8236 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8237 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8238 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8239 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8240
2acf923e
DC		 8241 /*
8242 * Ensure guest xcr0 is valid for loading
8243 */
d91cab78 8244 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8245
ad312c7c 8246 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8247}
d0752060 8248
f775b13e 8249/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8250void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8251{
f775b13e
RR		 8252 preempt_disable();
8253 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8254 /* PKRU is separately restored in kvm_x86_ops->run. */
8255 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8256 ~XFEATURE_MASK_PKRU);
f775b13e 8257 preempt_enable();
0c04851c 8258 trace_kvm_fpu(1);
d0752060 8259}
d0752060 8260
f775b13e 8261/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8262void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8263{
f775b13e 8264 preempt_disable();
4f836347 8265 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8266 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8267 preempt_enable();
f096ed85 8268 ++vcpu->stat.fpu_reload;
0c04851c 8269 trace_kvm_fpu(0);
d0752060 8270}
e9b11c17
ZX		 8271
8272void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8273{
bd768e14
IY		 8274 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8275
12f9a48f 8276 kvmclock_reset(vcpu);
7f1ea208 8277
e9b11c17 8278 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8279 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8280}
8281
8282struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8283 unsigned int id)
8284{
c447e76b
LL		 8285 struct kvm_vcpu *vcpu;
8286
b0c39dc6 8287 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8288 printk_once(KERN_WARNING
8289 "kvm: SMP vm created on host with unstable TSC; "
8290 "guest TSC will not be reliable\n");
c447e76b
LL		 8291
8292 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8293
c447e76b 8294 return vcpu;
26e5215f 8295}
e9b11c17 8296
26e5215f
AK		 8297int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8298{
19efffa2 8299 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8300 vcpu_load(vcpu);
d28bc9dd 8301 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8302 kvm_mmu_setup(vcpu);
e9b11c17 8303 vcpu_put(vcpu);
ec7660cc 8304 return 0;
e9b11c17
ZX		 8305}
8306
31928aa5 8307void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8308{
8fe8ab46 8309 struct msr_data msr;
332967a3 8310 struct kvm *kvm = vcpu->kvm;
42897d86 8311
d3457c87
RK		 8312 kvm_hv_vcpu_postcreate(vcpu);
8313
ec7660cc 8314 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8315 return;
ec7660cc 8316 vcpu_load(vcpu);
8fe8ab46
WA		 8317 msr.data = 0x0;
8318 msr.index = MSR_IA32_TSC;
8319 msr.host_initiated = true;
8320 kvm_write_tsc(vcpu, &msr);
42897d86 8321 vcpu_put(vcpu);
ec7660cc 8322 mutex_unlock(&vcpu->mutex);
42897d86 8323
630994b3
MT		 8324 if (!kvmclock_periodic_sync)
8325 return;
8326
332967a3
AJ		 8327 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8328 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8329}
8330
d40ccc62 8331void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8332{
344d9588
GN		 8333 vcpu->arch.apf.msr_val = 0;
8334
ec7660cc 8335 vcpu_load(vcpu);
e9b11c17
ZX		 8336 kvm_mmu_unload(vcpu);
8337 vcpu_put(vcpu);
8338
8339 kvm_x86_ops->vcpu_free(vcpu);
8340}
8341
d28bc9dd 8342void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8343{
b7e31be3
RK		 8344 kvm_lapic_reset(vcpu, init_event);
8345
e69fab5d
PB		 8346 vcpu->arch.hflags = 0;
8347
c43203ca 8348 vcpu->arch.smi_pending = 0;
52797bf9 8349 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8350 atomic_set(&vcpu->arch.nmi_queued, 0);
8351 vcpu->arch.nmi_pending = 0;
448fa4a9 8352 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8353 kvm_clear_interrupt_queue(vcpu);
8354 kvm_clear_exception_queue(vcpu);
664f8e26 8355 vcpu->arch.exception.pending = false;
448fa4a9 8356
42dbaa5a 8357 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8358 kvm_update_dr0123(vcpu);
6f43ed01 8359 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8360 kvm_update_dr6(vcpu);
42dbaa5a 8361 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8362 kvm_update_dr7(vcpu);
42dbaa5a 8363
1119022c
NA		 8364 vcpu->arch.cr2 = 0;
8365
3842d135 8366 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8367 vcpu->arch.apf.msr_val = 0;
c9aaa895 8368 vcpu->arch.st.msr_val = 0;
3842d135 8369
12f9a48f
GC		 8370 kvmclock_reset(vcpu);
8371
af585b92
GN		 8372 kvm_clear_async_pf_completion_queue(vcpu);
8373 kvm_async_pf_hash_reset(vcpu);
8374 vcpu->arch.apf.halted = false;
3842d135 8375
a554d207
WL		 8376 if (kvm_mpx_supported()) {
8377 void *mpx_state_buffer;
8378
8379 /*
8380 * To avoid have the INIT path from kvm_apic_has_events() that be
8381 * called with loaded FPU and does not let userspace fix the state.
8382 */
f775b13e
RR		 8383 if (init_event)
8384 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8385 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8386 XFEATURE_MASK_BNDREGS);
8387 if (mpx_state_buffer)
8388 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8389 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8390 XFEATURE_MASK_BNDCSR);
8391 if (mpx_state_buffer)
8392 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8393 if (init_event)
8394 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8395 }
8396
64d60670 8397 if (!init_event) {
d28bc9dd 8398 kvm_pmu_reset(vcpu);
64d60670 8399 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8400
8401 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8402 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8403
8404 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8405 }
f5132b01 8406
66f7b72e
JS		 8407 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8408 vcpu->arch.regs_avail = ~0;
8409 vcpu->arch.regs_dirty = ~0;
8410
a554d207
WL		 8411 vcpu->arch.ia32_xss = 0;
8412
d28bc9dd 8413 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8414}
8415
2b4a273b 8416void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8417{
8418 struct kvm_segment cs;
8419
8420 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8421 cs.selector = vector << 8;
8422 cs.base = vector << 12;
8423 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8424 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8425}
8426
13a34e06 8427int kvm_arch_hardware_enable(void)
e9b11c17 8428{
ca84d1a2
ZA		 8429 struct kvm *kvm;
8430 struct kvm_vcpu *vcpu;
8431 int i;
0dd6a6ed
ZA		 8432 int ret;
8433 u64 local_tsc;
8434 u64 max_tsc = 0;
8435 bool stable, backwards_tsc = false;
18863bdd
AK		 8436
8437 kvm_shared_msr_cpu_online();
13a34e06 8438 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8439 if (ret != 0)
8440 return ret;
8441
4ea1636b 8442 local_tsc = rdtsc();
b0c39dc6 8443 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8444 list_for_each_entry(kvm, &vm_list, vm_list) {
8445 kvm_for_each_vcpu(i, vcpu, kvm) {
8446 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8447 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8448 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8449 backwards_tsc = true;
8450 if (vcpu->arch.last_host_tsc > max_tsc)
8451 max_tsc = vcpu->arch.last_host_tsc;
8452 }
8453 }
8454 }
8455
8456 /*
8457 * Sometimes, even reliable TSCs go backwards. This happens on
8458 * platforms that reset TSC during suspend or hibernate actions, but
8459 * maintain synchronization. We must compensate. Fortunately, we can
8460 * detect that condition here, which happens early in CPU bringup,
8461 * before any KVM threads can be running. Unfortunately, we can't
8462 * bring the TSCs fully up to date with real time, as we aren't yet far
8463 * enough into CPU bringup that we know how much real time has actually
108b249c 8464 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8465 * variables that haven't been updated yet.
8466 *
8467 * So we simply find the maximum observed TSC above, then record the
8468 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8469 * the adjustment will be applied. Note that we accumulate
8470 * adjustments, in case multiple suspend cycles happen before some VCPU
8471 * gets a chance to run again. In the event that no KVM threads get a
8472 * chance to run, we will miss the entire elapsed period, as we'll have
8473 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8474 * loose cycle time. This isn't too big a deal, since the loss will be
8475 * uniform across all VCPUs (not to mention the scenario is extremely
8476 * unlikely). It is possible that a second hibernate recovery happens
8477 * much faster than a first, causing the observed TSC here to be
8478 * smaller; this would require additional padding adjustment, which is
8479 * why we set last_host_tsc to the local tsc observed here.
8480 *
8481 * N.B. - this code below runs only on platforms with reliable TSC,
8482 * as that is the only way backwards_tsc is set above. Also note
8483 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8484 * have the same delta_cyc adjustment applied if backwards_tsc
8485 * is detected. Note further, this adjustment is only done once,
8486 * as we reset last_host_tsc on all VCPUs to stop this from being
8487 * called multiple times (one for each physical CPU bringup).
8488 *
4a969980 8489 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8490 * will be compensated by the logic in vcpu_load, which sets the TSC to
8491 * catchup mode. This will catchup all VCPUs to real time, but cannot
8492 * guarantee that they stay in perfect synchronization.
8493 */
8494 if (backwards_tsc) {
8495 u64 delta_cyc = max_tsc - local_tsc;
8496 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8497 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8498 kvm_for_each_vcpu(i, vcpu, kvm) {
8499 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8500 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8501 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8502 }
8503
8504 /*
8505 * We have to disable TSC offset matching.. if you were
8506 * booting a VM while issuing an S4 host suspend....
8507 * you may have some problem. Solving this issue is
8508 * left as an exercise to the reader.
8509 */
8510 kvm->arch.last_tsc_nsec = 0;
8511 kvm->arch.last_tsc_write = 0;
8512 }
8513
8514 }
8515 return 0;
e9b11c17
ZX		 8516}
8517
13a34e06 8518void kvm_arch_hardware_disable(void)
e9b11c17 8519{
13a34e06
RK		 8520 kvm_x86_ops->hardware_disable();
8521 drop_user_return_notifiers();
e9b11c17
ZX		 8522}
8523
8524int kvm_arch_hardware_setup(void)
8525{
9e9c3fe4
NA		 8526 int r;
8527
8528 r = kvm_x86_ops->hardware_setup();
8529 if (r != 0)
8530 return r;
8531
35181e86
HZ		 8532 if (kvm_has_tsc_control) {
8533 /*
8534 * Make sure the user can only configure tsc_khz values that
8535 * fit into a signed integer.
8536 * A min value is not calculated needed because it will always
8537 * be 1 on all machines.
8538 */
8539 u64 max = min(0x7fffffffULL,
8540 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8541 kvm_max_guest_tsc_khz = max;
8542
ad721883 8543 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8544 }
ad721883 8545
9e9c3fe4
NA		 8546 kvm_init_msr_list();
8547 return 0;
e9b11c17
ZX		 8548}
8549
8550void kvm_arch_hardware_unsetup(void)
8551{
8552 kvm_x86_ops->hardware_unsetup();
8553}
8554
8555void kvm_arch_check_processor_compat(void *rtn)
8556{
8557 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8558}
8559
8560bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8561{
8562 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8563}
8564EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8565
8566bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8567{
8568 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8569}
8570
54e9818f 8571struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8572EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8573
e9b11c17
ZX		 8574int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8575{
8576 struct page *page;
e9b11c17
ZX		 8577 int r;
8578
b2a05fef 8579 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8580 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8581 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8582 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8583 else
a4535290 8584 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8585
8586 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8587 if (!page) {
8588 r = -ENOMEM;
8589 goto fail;
8590 }
ad312c7c 8591 vcpu->arch.pio_data = page_address(page);
e9b11c17 8592
cc578287 8593 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8594
e9b11c17
ZX		 8595 r = kvm_mmu_create(vcpu);
8596 if (r < 0)
8597 goto fail_free_pio_data;
8598
26de7988 8599 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8600 r = kvm_create_lapic(vcpu);
8601 if (r < 0)
8602 goto fail_mmu_destroy;
54e9818f
GN		 8603 } else
8604 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8605
890ca9ae
HY		 8606 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8607 GFP_KERNEL);
8608 if (!vcpu->arch.mce_banks) {
8609 r = -ENOMEM;
443c39bc 8610 goto fail_free_lapic;
890ca9ae
HY		 8611 }
8612 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8613
f1797359
WY		 8614 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8615 r = -ENOMEM;
f5f48ee1 8616 goto fail_free_mce_banks;
f1797359 8617 }
f5f48ee1 8618
0ee6a517 8619 fx_init(vcpu);
66f7b72e 8620
4344ee98 8621 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8622
5a4f55cd
EK		 8623 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8624
74545705
RK		 8625 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8626
af585b92 8627 kvm_async_pf_hash_reset(vcpu);
f5132b01 8628 kvm_pmu_init(vcpu);
af585b92 8629
1c1a9ce9 8630 vcpu->arch.pending_external_vector = -1;
de63ad4c 8631 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8632
5c919412
AS		 8633 kvm_hv_vcpu_init(vcpu);
8634
e9b11c17 8635 return 0;
0ee6a517 8636
f5f48ee1
SY		 8637fail_free_mce_banks:
8638 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8639fail_free_lapic:
8640 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8641fail_mmu_destroy:
8642 kvm_mmu_destroy(vcpu);
8643fail_free_pio_data:
ad312c7c 8644 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8645fail:
8646 return r;
8647}
8648
8649void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8650{
f656ce01
MT		 8651 int idx;
8652
1f4b34f8 8653 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8654 kvm_pmu_destroy(vcpu);
36cb93fd 8655 kfree(vcpu->arch.mce_banks);
e9b11c17 8656 kvm_free_lapic(vcpu);
f656ce01 8657 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8658 kvm_mmu_destroy(vcpu);
f656ce01 8659 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8660 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8661 if (!lapic_in_kernel(vcpu))
54e9818f 8662 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8663}
d19a9cd2 8664
e790d9ef
RK		 8665void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8666{
ae97a3b8 8667 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8668}
8669
e08b9637 8670int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8671{
e08b9637
CO		 8672 if (type)
8673 return -EINVAL;
8674
6ef768fa 8675 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8676 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8677 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8678 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8679 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8680
5550af4d
SY		 8681 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8682 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8683 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8684 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8685 &kvm->arch.irq_sources_bitmap);
5550af4d 8686
038f8c11 8687 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8688 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8689 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8690
108b249c 8691 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8692 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8693
7e44e449 8694 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8695 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8696
cbc0236a 8697 kvm_hv_init_vm(kvm);
0eb05bf2 8698 kvm_page_track_init(kvm);
13d268ca 8699 kvm_mmu_init_vm(kvm);
0eb05bf2 8700
03543133
SS		 8701 if (kvm_x86_ops->vm_init)
8702 return kvm_x86_ops->vm_init(kvm);
8703
d89f5eff 8704 return 0;
d19a9cd2
ZX		 8705}
8706
8707static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8708{
ec7660cc 8709 vcpu_load(vcpu);
d19a9cd2
ZX		 8710 kvm_mmu_unload(vcpu);
8711 vcpu_put(vcpu);
8712}
8713
8714static void kvm_free_vcpus(struct kvm *kvm)
8715{
8716 unsigned int i;
988a2cae 8717 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8718
8719 /*
8720 * Unpin any mmu pages first.
8721 */
af585b92
GN		 8722 kvm_for_each_vcpu(i, vcpu, kvm) {
8723 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8724 kvm_unload_vcpu_mmu(vcpu);
af585b92 8725 }
988a2cae
GN		 8726 kvm_for_each_vcpu(i, vcpu, kvm)
8727 kvm_arch_vcpu_free(vcpu);
8728
8729 mutex_lock(&kvm->lock);
8730 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8731 kvm->vcpus[i] = NULL;
d19a9cd2 8732
988a2cae
GN		 8733 atomic_set(&kvm->online_vcpus, 0);
8734 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8735}
8736
ad8ba2cd
SY		 8737void kvm_arch_sync_events(struct kvm *kvm)
8738{
332967a3 8739 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8740 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8741 kvm_free_pit(kvm);
ad8ba2cd
SY		 8742}
8743
1d8007bd 8744int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8745{
8746 int i, r;
25188b99 8747 unsigned long hva;
f0d648bd
PB		 8748 struct kvm_memslots *slots = kvm_memslots(kvm);
8749 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8750
8751 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8752 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8753 return -EINVAL;
9da0e4d5 8754
f0d648bd
PB		 8755 slot = id_to_memslot(slots, id);
8756 if (size) {
b21629da 8757 if (slot->npages)
f0d648bd
PB		 8758 return -EEXIST;
8759
8760 /*
8761 * MAP_SHARED to prevent internal slot pages from being moved
8762 * by fork()/COW.
8763 */
8764 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8765 MAP_SHARED | MAP_ANONYMOUS, 0);
8766 if (IS_ERR((void *)hva))
8767 return PTR_ERR((void *)hva);
8768 } else {
8769 if (!slot->npages)
8770 return 0;
8771
8772 hva = 0;
8773 }
8774
8775 old = *slot;
9da0e4d5 8776 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8777 struct kvm_userspace_memory_region m;
9da0e4d5 8778
1d8007bd
PB		 8779 m.slot = id | (i << 16);
8780 m.flags = 0;
8781 m.guest_phys_addr = gpa;
f0d648bd 8782 m.userspace_addr = hva;
1d8007bd 8783 m.memory_size = size;
9da0e4d5
PB		 8784 r = __kvm_set_memory_region(kvm, &m);
8785 if (r < 0)
8786 return r;
8787 }
8788
103c763c
EB		 8789 if (!size)
8790 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8791
9da0e4d5
PB		 8792 return 0;
8793}
8794EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8795
1d8007bd 8796int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8797{
8798 int r;
8799
8800 mutex_lock(&kvm->slots_lock);
1d8007bd 8801 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8802 mutex_unlock(&kvm->slots_lock);
8803
8804 return r;
8805}
8806EXPORT_SYMBOL_GPL(x86_set_memory_region);
8807
d19a9cd2
ZX		 8808void kvm_arch_destroy_vm(struct kvm *kvm)
8809{
27469d29
AH		 8810 if (current->mm == kvm->mm) {
8811 /*
8812 * Free memory regions allocated on behalf of userspace,
8813 * unless the the memory map has changed due to process exit
8814 * or fd copying.
8815 */
1d8007bd
PB		 8816 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8817 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8818 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8819 }
03543133
SS		 8820 if (kvm_x86_ops->vm_destroy)
8821 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8822 kvm_pic_destroy(kvm);
8823 kvm_ioapic_destroy(kvm);
d19a9cd2 8824 kvm_free_vcpus(kvm);
af1bae54 8825 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8826 kvm_mmu_uninit_vm(kvm);
2beb6dad 8827 kvm_page_track_cleanup(kvm);
cbc0236a 8828 kvm_hv_destroy_vm(kvm);
d19a9cd2 8829}
0de10343 8830
5587027c 8831void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8832 struct kvm_memory_slot *dont)
8833{
8834 int i;
8835
d89cc617
TY		 8836 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8837 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8838 kvfree(free->arch.rmap[i]);
d89cc617 8839 free->arch.rmap[i] = NULL;
77d11309 8840 }
d89cc617
TY		 8841 if (i == 0)
8842 continue;
8843
8844 if (!dont || free->arch.lpage_info[i - 1] !=
8845 dont->arch.lpage_info[i - 1]) {
548ef284 8846 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8847 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8848 }
8849 }
21ebbeda
XG		 8850
8851 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8852}
8853
5587027c
AK		 8854int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8855 unsigned long npages)
db3fe4eb
TY		 8856{
8857 int i;
8858
d89cc617 8859 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8860 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8861 unsigned long ugfn;
8862 int lpages;
d89cc617 8863 int level = i + 1;
db3fe4eb
TY		 8864
8865 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8866 slot->base_gfn, level) + 1;
8867
d89cc617 8868 slot->arch.rmap[i] =
a7c3e901 8869 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8870 if (!slot->arch.rmap[i])
77d11309 8871 goto out_free;
d89cc617
TY		 8872 if (i == 0)
8873 continue;
77d11309 8874
a7c3e901 8875 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8876 if (!linfo)
db3fe4eb
TY		 8877 goto out_free;
8878
92f94f1e
XG		 8879 slot->arch.lpage_info[i - 1] = linfo;
8880
db3fe4eb 8881 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8882 linfo[0].disallow_lpage = 1;
db3fe4eb 8883 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8884 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8885 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8886 /*
8887 * If the gfn and userspace address are not aligned wrt each
8888 * other, or if explicitly asked to, disable large page
8889 * support for this slot
8890 */
8891 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8892 !kvm_largepages_enabled()) {
8893 unsigned long j;
8894
8895 for (j = 0; j < lpages; ++j)
92f94f1e 8896 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8897 }
8898 }
8899
21ebbeda
XG		 8900 if (kvm_page_track_create_memslot(slot, npages))
8901 goto out_free;
8902
db3fe4eb
TY		 8903 return 0;
8904
8905out_free:
d89cc617 8906 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8907 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8908 slot->arch.rmap[i] = NULL;
8909 if (i == 0)
8910 continue;
8911
548ef284 8912 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8913 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8914 }
8915 return -ENOMEM;
8916}
8917
15f46015 8918void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8919{
e6dff7d1
TY		 8920 /*
8921 * memslots->generation has been incremented.
8922 * mmio generation may have reached its maximum value.
8923 */
54bf36aa 8924 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8925}
8926
f7784b8e
MT		 8927int kvm_arch_prepare_memory_region(struct kvm *kvm,
8928 struct kvm_memory_slot *memslot,
09170a49 8929 const struct kvm_userspace_memory_region *mem,
7b6195a9 8930 enum kvm_mr_change change)
0de10343 8931{
f7784b8e
MT		 8932 return 0;
8933}
8934
88178fd4
KH		 8935static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8936 struct kvm_memory_slot *new)
8937{
8938 /* Still write protect RO slot */
8939 if (new->flags & KVM_MEM_READONLY) {
8940 kvm_mmu_slot_remove_write_access(kvm, new);
8941 return;
8942 }
8943
8944 /*
8945 * Call kvm_x86_ops dirty logging hooks when they are valid.
8946 *
8947 * kvm_x86_ops->slot_disable_log_dirty is called when:
8948 *
8949 * - KVM_MR_CREATE with dirty logging is disabled
8950 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8951 *
8952 * The reason is, in case of PML, we need to set D-bit for any slots
8953 * with dirty logging disabled in order to eliminate unnecessary GPA
8954 * logging in PML buffer (and potential PML buffer full VMEXT). This
8955 * guarantees leaving PML enabled during guest's lifetime won't have
8956 * any additonal overhead from PML when guest is running with dirty
8957 * logging disabled for memory slots.
8958 *
8959 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8960 * to dirty logging mode.
8961 *
8962 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8963 *
8964 * In case of write protect:
8965 *
8966 * Write protect all pages for dirty logging.
8967 *
8968 * All the sptes including the large sptes which point to this
8969 * slot are set to readonly. We can not create any new large
8970 * spte on this slot until the end of the logging.
8971 *
8972 * See the comments in fast_page_fault().
8973 */
8974 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8975 if (kvm_x86_ops->slot_enable_log_dirty)
8976 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8977 else
8978 kvm_mmu_slot_remove_write_access(kvm, new);
8979 } else {
8980 if (kvm_x86_ops->slot_disable_log_dirty)
8981 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8982 }
8983}
8984
f7784b8e 8985void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8986 const struct kvm_userspace_memory_region *mem,
8482644a 8987 const struct kvm_memory_slot *old,
f36f3f28 8988 const struct kvm_memory_slot *new,
8482644a 8989 enum kvm_mr_change change)
f7784b8e 8990{
8482644a 8991 int nr_mmu_pages = 0;
f7784b8e 8992
48c0e4e9
XG		 8993 if (!kvm->arch.n_requested_mmu_pages)
8994 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8995
48c0e4e9 8996 if (nr_mmu_pages)
0de10343 8997 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8998
3ea3b7fa
WL		 8999 /*
9000 * Dirty logging tracks sptes in 4k granularity, meaning that large
9001 * sptes have to be split. If live migration is successful, the guest
9002 * in the source machine will be destroyed and large sptes will be
9003 * created in the destination. However, if the guest continues to run
9004 * in the source machine (for example if live migration fails), small
9005 * sptes will remain around and cause bad performance.
9006 *
9007 * Scan sptes if dirty logging has been stopped, dropping those
9008 * which can be collapsed into a single large-page spte. Later
9009 * page faults will create the large-page sptes.
9010 */
9011 if ((change != KVM_MR_DELETE) &&
9012 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9013 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9014 kvm_mmu_zap_collapsible_sptes(kvm, new);
9015
c972f3b1 9016 /*
88178fd4 9017 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9018 *
88178fd4
KH		 9019 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9020 * been zapped so no dirty logging staff is needed for old slot. For
9021 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9022 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9023 *
9024 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9025 */
88178fd4 9026 if (change != KVM_MR_DELETE)
f36f3f28 9027 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9028}
1d737c8a 9029
2df72e9b 9030void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9031{
6ca18b69 9032 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9033}
9034
2df72e9b
MT		 9035void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9036 struct kvm_memory_slot *slot)
9037{
ae7cd873 9038 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9039}
9040
5d9bc648
PB		 9041static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9042{
9043 if (!list_empty_careful(&vcpu->async_pf.done))
9044 return true;
9045
9046 if (kvm_apic_has_events(vcpu))
9047 return true;
9048
9049 if (vcpu->arch.pv.pv_unhalted)
9050 return true;
9051
a5f01f8e
WL		 9052 if (vcpu->arch.exception.pending)
9053 return true;
9054
47a66eed
Z		 9055 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9056 (vcpu->arch.nmi_pending &&
9057 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9058 return true;
9059
47a66eed
Z		 9060 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9061 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9062 return true;
9063
5d9bc648
PB		 9064 if (kvm_arch_interrupt_allowed(vcpu) &&
9065 kvm_cpu_has_interrupt(vcpu))
9066 return true;
9067
1f4b34f8
AS		 9068 if (kvm_hv_has_stimer_pending(vcpu))
9069 return true;
9070
5d9bc648
PB		 9071 return false;
9072}
9073
1d737c8a
ZX		 9074int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9075{
5d9bc648 9076 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9077}
5736199a 9078
199b5763
LM		 9079bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9080{
de63ad4c 9081 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9082}
9083
b6d33834 9084int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9085{
b6d33834 9086 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9087}
78646121
GN		 9088
9089int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9090{
9091 return kvm_x86_ops->interrupt_allowed(vcpu);
9092}
229456fc 9093
82b32774 9094unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9095{
82b32774
NA		 9096 if (is_64_bit_mode(vcpu))
9097 return kvm_rip_read(vcpu);
9098 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9099 kvm_rip_read(vcpu));
9100}
9101EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9102
82b32774
NA		 9103bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9104{
9105 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9106}
9107EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9108
94fe45da
JK		 9109unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9110{
9111 unsigned long rflags;
9112
9113 rflags = kvm_x86_ops->get_rflags(vcpu);
9114 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9115 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9116 return rflags;
9117}
9118EXPORT_SYMBOL_GPL(kvm_get_rflags);
9119
6addfc42 9120static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9121{
9122 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9123 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9124 rflags |= X86_EFLAGS_TF;
94fe45da 9125 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9126}
9127
9128void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9129{
9130 __kvm_set_rflags(vcpu, rflags);
3842d135 9131 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9132}
9133EXPORT_SYMBOL_GPL(kvm_set_rflags);
9134
56028d08
GN		 9135void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9136{
9137 int r;
9138
fb67e14f 9139 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 9140 work->wakeup_all)
56028d08
GN		 9141 return;
9142
9143 r = kvm_mmu_reload(vcpu);
9144 if (unlikely(r))
9145 return;
9146
fb67e14f
XG		 9147 if (!vcpu->arch.mmu.direct_map &&
9148 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9149 return;
9150
56028d08
GN		 9151 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9152}
9153
af585b92
GN		 9154static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9155{
9156 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9157}
9158
9159static inline u32 kvm_async_pf_next_probe(u32 key)
9160{
9161 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9162}
9163
9164static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9165{
9166 u32 key = kvm_async_pf_hash_fn(gfn);
9167
9168 while (vcpu->arch.apf.gfns[key] != ~0)
9169 key = kvm_async_pf_next_probe(key);
9170
9171 vcpu->arch.apf.gfns[key] = gfn;
9172}
9173
9174static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9175{
9176 int i;
9177 u32 key = kvm_async_pf_hash_fn(gfn);
9178
9179 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9180 (vcpu->arch.apf.gfns[key] != gfn &&
9181 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9182 key = kvm_async_pf_next_probe(key);
9183
9184 return key;
9185}
9186
9187bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9188{
9189 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9190}
9191
9192static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9193{
9194 u32 i, j, k;
9195
9196 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9197 while (true) {
9198 vcpu->arch.apf.gfns[i] = ~0;
9199 do {
9200 j = kvm_async_pf_next_probe(j);
9201 if (vcpu->arch.apf.gfns[j] == ~0)
9202 return;
9203 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9204 /*
9205 * k lies cyclically in ]i,j]
9206 * | i.k.j |
9207 * |....j i.k.| or |.k..j i...|
9208 */
9209 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9210 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9211 i = j;
9212 }
9213}
9214
7c90705b
GN		 9215static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9216{
4e335d9e
PB		 9217
9218 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9219 sizeof(val));
7c90705b
GN		 9220}
9221
9a6e7c39
WL		 9222static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9223{
9224
9225 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9226 sizeof(u32));
9227}
9228
af585b92
GN		 9229void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9230 struct kvm_async_pf *work)
9231{
6389ee94
AK		 9232 struct x86_exception fault;
9233
7c90705b 9234 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9235 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9236
9237 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9238 (vcpu->arch.apf.send_user_only &&
9239 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9240 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9241 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9242 fault.vector = PF_VECTOR;
9243 fault.error_code_valid = true;
9244 fault.error_code = 0;
9245 fault.nested_page_fault = false;
9246 fault.address = work->arch.token;
adfe20fb 9247 fault.async_page_fault = true;
6389ee94 9248 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9249 }
af585b92
GN		 9250}
9251
9252void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9253 struct kvm_async_pf *work)
9254{
6389ee94 9255 struct x86_exception fault;
9a6e7c39 9256 u32 val;
6389ee94 9257
f2e10669 9258 if (work->wakeup_all)
7c90705b
GN		 9259 work->arch.token = ~0; /* broadcast wakeup */
9260 else
9261 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9262 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9263
9a6e7c39
WL		 9264 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9265 !apf_get_user(vcpu, &val)) {
9266 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9267 vcpu->arch.exception.pending &&
9268 vcpu->arch.exception.nr == PF_VECTOR &&
9269 !apf_put_user(vcpu, 0)) {
9270 vcpu->arch.exception.injected = false;
9271 vcpu->arch.exception.pending = false;
9272 vcpu->arch.exception.nr = 0;
9273 vcpu->arch.exception.has_error_code = false;
9274 vcpu->arch.exception.error_code = 0;
9275 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9276 fault.vector = PF_VECTOR;
9277 fault.error_code_valid = true;
9278 fault.error_code = 0;
9279 fault.nested_page_fault = false;
9280 fault.address = work->arch.token;
9281 fault.async_page_fault = true;
9282 kvm_inject_page_fault(vcpu, &fault);
9283 }
7c90705b 9284 }
e6d53e3b 9285 vcpu->arch.apf.halted = false;
a4fa1635 9286 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9287}
9288
9289bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9290{
9291 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9292 return true;
9293 else
9bc1f09f 9294 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9295}
9296
5544eb9b
PB		 9297void kvm_arch_start_assignment(struct kvm *kvm)
9298{
9299 atomic_inc(&kvm->arch.assigned_device_count);
9300}
9301EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9302
9303void kvm_arch_end_assignment(struct kvm *kvm)
9304{
9305 atomic_dec(&kvm->arch.assigned_device_count);
9306}
9307EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9308
9309bool kvm_arch_has_assigned_device(struct kvm *kvm)
9310{
9311 return atomic_read(&kvm->arch.assigned_device_count);
9312}
9313EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9314
e0f0bbc5
AW		 9315void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9316{
9317 atomic_inc(&kvm->arch.noncoherent_dma_count);
9318}
9319EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9320
9321void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9322{
9323 atomic_dec(&kvm->arch.noncoherent_dma_count);
9324}
9325EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9326
9327bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9328{
9329 return atomic_read(&kvm->arch.noncoherent_dma_count);
9330}
9331EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9332
14717e20
AW		 9333bool kvm_arch_has_irq_bypass(void)
9334{
9335 return kvm_x86_ops->update_pi_irte != NULL;
9336}
9337
87276880
FW		 9338int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9339 struct irq_bypass_producer *prod)
9340{
9341 struct kvm_kernel_irqfd *irqfd =
9342 container_of(cons, struct kvm_kernel_irqfd, consumer);
9343
14717e20 9344 irqfd->producer = prod;
87276880 9345
14717e20
AW		 9346 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9347 prod->irq, irqfd->gsi, 1);
87276880
FW		 9348}
9349
9350void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9351 struct irq_bypass_producer *prod)
9352{
9353 int ret;
9354 struct kvm_kernel_irqfd *irqfd =
9355 container_of(cons, struct kvm_kernel_irqfd, consumer);
9356
87276880
FW		 9357 WARN_ON(irqfd->producer != prod);
9358 irqfd->producer = NULL;
9359
9360 /*
9361 * When producer of consumer is unregistered, we change back to
9362 * remapped mode, so we can re-use the current implementation
bb3541f1 9363 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9364 * int this case doesn't want to receive the interrupts.
9365 */
9366 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9367 if (ret)
9368 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9369 " fails: %d\n", irqfd->consumer.token, ret);
9370}
9371
9372int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9373 uint32_t guest_irq, bool set)
9374{
9375 if (!kvm_x86_ops->update_pi_irte)
9376 return -EINVAL;
9377
9378 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9379}
9380
52004014
FW		 9381bool kvm_vector_hashing_enabled(void)
9382{
9383 return vector_hashing;
9384}
9385EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9386
229456fc 9387EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9388EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9389EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9390EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9391EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9392EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9393EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9394EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9395EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9396EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9397EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9398EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9399EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9400EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9401EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9402EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9403EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9404EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9405EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)