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x86: Define MSR_EBC_FREQUENCY_ID
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
221d059d 9 * Copyright 2010 Red Hat, Inc. and/or its affilates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
1d5f066e 58#include <asm/pvclock.h>
217fc9cf 59#include <asm/div64.h>
043405e1 60
313a3dc7 61#define MAX_IO_MSRS 256
a03490ed
CO		 62#define CR0_RESERVED_BITS \
63 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
64 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
65 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
66#define CR4_RESERVED_BITS \
67 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
68 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
69 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 70 | X86_CR4_OSXSAVE \
a03490ed
CO		 71 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
72
73#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 74
75#define KVM_MAX_MCE_BANKS 32
76#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
84#else
85static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
86#endif
313a3dc7 87
ba1389b7
AK		 88#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
89#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 90
cb142eb7 91static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 92static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
93 struct kvm_cpuid_entry2 __user *entries);
94
97896d04 95struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 96EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 97
ed85c068
AP		 98int ignore_msrs = 0;
99module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
100
18863bdd
AK		 101#define KVM_NR_SHARED_MSRS 16
102
103struct kvm_shared_msrs_global {
104 int nr;
2bf78fa7 105 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 106};
107
108struct kvm_shared_msrs {
109 struct user_return_notifier urn;
110 bool registered;
2bf78fa7
SY		 111 struct kvm_shared_msr_values {
112 u64 host;
113 u64 curr;
114 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 115};
116
117static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
118static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
119
417bc304 120struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 121 { "pf_fixed", VCPU_STAT(pf_fixed) },
122 { "pf_guest", VCPU_STAT(pf_guest) },
123 { "tlb_flush", VCPU_STAT(tlb_flush) },
124 { "invlpg", VCPU_STAT(invlpg) },
125 { "exits", VCPU_STAT(exits) },
126 { "io_exits", VCPU_STAT(io_exits) },
127 { "mmio_exits", VCPU_STAT(mmio_exits) },
128 { "signal_exits", VCPU_STAT(signal_exits) },
129 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 130 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 131 { "halt_exits", VCPU_STAT(halt_exits) },
132 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 133 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 134 { "request_irq", VCPU_STAT(request_irq_exits) },
135 { "irq_exits", VCPU_STAT(irq_exits) },
136 { "host_state_reload", VCPU_STAT(host_state_reload) },
137 { "efer_reload", VCPU_STAT(efer_reload) },
138 { "fpu_reload", VCPU_STAT(fpu_reload) },
139 { "insn_emulation", VCPU_STAT(insn_emulation) },
140 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 141 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 142 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 143 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
144 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
145 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
146 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
147 { "mmu_flooded", VM_STAT(mmu_flooded) },
148 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 149 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 150 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 151 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 152 { "largepages", VM_STAT(lpages) },
417bc304
HB		 153 { NULL }
154};
155
2acf923e
DC		 156u64 __read_mostly host_xcr0;
157
158static inline u32 bit(int bitno)
159{
160 return 1 << (bitno & 31);
161}
162
18863bdd
AK		 163static void kvm_on_user_return(struct user_return_notifier *urn)
164{
165 unsigned slot;
18863bdd
AK		 166 struct kvm_shared_msrs *locals
167 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 168 struct kvm_shared_msr_values *values;
18863bdd
AK		 169
170 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 171 values = &locals->values[slot];
172 if (values->host != values->curr) {
173 wrmsrl(shared_msrs_global.msrs[slot], values->host);
174 values->curr = values->host;
18863bdd
AK		 175 }
176 }
177 locals->registered = false;
178 user_return_notifier_unregister(urn);
179}
180
2bf78fa7 181static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 182{
2bf78fa7 183 struct kvm_shared_msrs *smsr;
18863bdd
AK		 184 u64 value;
185
2bf78fa7
SY		 186 smsr = &__get_cpu_var(shared_msrs);
187 /* only read, and nobody should modify it at this time,
188 * so don't need lock */
189 if (slot >= shared_msrs_global.nr) {
190 printk(KERN_ERR "kvm: invalid MSR slot!");
191 return;
192 }
193 rdmsrl_safe(msr, &value);
194 smsr->values[slot].host = value;
195 smsr->values[slot].curr = value;
196}
197
198void kvm_define_shared_msr(unsigned slot, u32 msr)
199{
18863bdd
AK		 200 if (slot >= shared_msrs_global.nr)
201 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 202 shared_msrs_global.msrs[slot] = msr;
203 /* we need ensured the shared_msr_global have been updated */
204 smp_wmb();
18863bdd
AK		 205}
206EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
207
208static void kvm_shared_msr_cpu_online(void)
209{
210 unsigned i;
18863bdd
AK		 211
212 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 213 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 214}
215
d5696725 216void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 217{
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
219
2bf78fa7 220 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 221 return;
2bf78fa7
SY		 222 smsr->values[slot].curr = value;
223 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 224 if (!smsr->registered) {
225 smsr->urn.on_user_return = kvm_on_user_return;
226 user_return_notifier_register(&smsr->urn);
227 smsr->registered = true;
228 }
229}
230EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
231
3548bab5
AK		 232static void drop_user_return_notifiers(void *ignore)
233{
234 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
235
236 if (smsr->registered)
237 kvm_on_user_return(&smsr->urn);
238}
239
6866b83e
CO		 240u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
241{
242 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e 244 else
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e
CO		 246}
247EXPORT_SYMBOL_GPL(kvm_get_apic_base);
248
249void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
250{
251 /* TODO: reserve bits check */
252 if (irqchip_in_kernel(vcpu->kvm))
253 kvm_lapic_set_base(vcpu, data);
254 else
ad312c7c 255 vcpu->arch.apic_base = data;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_set_apic_base);
258
3fd28fce
ED		 259#define EXCPT_BENIGN 0
260#define EXCPT_CONTRIBUTORY 1
261#define EXCPT_PF 2
262
263static int exception_class(int vector)
264{
265 switch (vector) {
266 case PF_VECTOR:
267 return EXCPT_PF;
268 case DE_VECTOR:
269 case TS_VECTOR:
270 case NP_VECTOR:
271 case SS_VECTOR:
272 case GP_VECTOR:
273 return EXCPT_CONTRIBUTORY;
274 default:
275 break;
276 }
277 return EXCPT_BENIGN;
278}
279
280static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 281 unsigned nr, bool has_error, u32 error_code,
282 bool reinject)
3fd28fce
ED		 283{
284 u32 prev_nr;
285 int class1, class2;
286
287 if (!vcpu->arch.exception.pending) {
288 queue:
289 vcpu->arch.exception.pending = true;
290 vcpu->arch.exception.has_error_code = has_error;
291 vcpu->arch.exception.nr = nr;
292 vcpu->arch.exception.error_code = error_code;
3f0fd292 293 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 294 return;
295 }
296
297 /* to check exception */
298 prev_nr = vcpu->arch.exception.nr;
299 if (prev_nr == DF_VECTOR) {
300 /* triple fault -> shutdown */
a8eeb04a 301 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 302 return;
303 }
304 class1 = exception_class(prev_nr);
305 class2 = exception_class(nr);
306 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
307 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
308 /* generate double fault per SDM Table 5-5 */
309 vcpu->arch.exception.pending = true;
310 vcpu->arch.exception.has_error_code = true;
311 vcpu->arch.exception.nr = DF_VECTOR;
312 vcpu->arch.exception.error_code = 0;
313 } else
314 /* replace previous exception with a new one in a hope
315 that instruction re-execution will regenerate lost
316 exception */
317 goto queue;
318}
319
298101da
AK		 320void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
321{
ce7ddec4 322 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 323}
324EXPORT_SYMBOL_GPL(kvm_queue_exception);
325
ce7ddec4
JR		 326void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
327{
328 kvm_multiple_exception(vcpu, nr, false, 0, true);
329}
330EXPORT_SYMBOL_GPL(kvm_requeue_exception);
331
c3c91fee
AK		 332void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
333 u32 error_code)
334{
335 ++vcpu->stat.pf_guest;
ad312c7c 336 vcpu->arch.cr2 = addr;
c3c91fee
AK		 337 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
338}
339
3419ffc8
SY		 340void kvm_inject_nmi(struct kvm_vcpu *vcpu)
341{
342 vcpu->arch.nmi_pending = 1;
343}
344EXPORT_SYMBOL_GPL(kvm_inject_nmi);
345
298101da
AK		 346void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
347{
ce7ddec4 348 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 349}
350EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
351
ce7ddec4
JR		 352void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
353{
354 kvm_multiple_exception(vcpu, nr, true, error_code, true);
355}
356EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
357
0a79b009
AK		 358/*
359 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
360 * a #GP and return false.
361 */
362bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 363{
0a79b009
AK		 364 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
365 return true;
366 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
367 return false;
298101da 368}
0a79b009 369EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 370
a03490ed
CO		 371/*
372 * Load the pae pdptrs. Return true is they are all valid.
373 */
374int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
375{
376 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
377 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
378 int i;
379 int ret;
ad312c7c 380 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 381
a03490ed
CO		 382 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
383 offset * sizeof(u64), sizeof(pdpte));
384 if (ret < 0) {
385 ret = 0;
386 goto out;
387 }
388 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 389 if (is_present_gpte(pdpte[i]) &&
20c466b5 390 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 391 ret = 0;
392 goto out;
393 }
394 }
395 ret = 1;
396
ad312c7c 397 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 398 __set_bit(VCPU_EXREG_PDPTR,
399 (unsigned long *)&vcpu->arch.regs_avail);
400 __set_bit(VCPU_EXREG_PDPTR,
401 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 402out:
a03490ed
CO		 403
404 return ret;
405}
cc4b6871 406EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 407
d835dfec
AK		 408static bool pdptrs_changed(struct kvm_vcpu *vcpu)
409{
ad312c7c 410 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 411 bool changed = true;
412 int r;
413
414 if (is_long_mode(vcpu) || !is_pae(vcpu))
415 return false;
416
6de4f3ad
AK		 417 if (!test_bit(VCPU_EXREG_PDPTR,
418 (unsigned long *)&vcpu->arch.regs_avail))
419 return true;
420
ad312c7c 421 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 422 if (r < 0)
423 goto out;
ad312c7c 424 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 425out:
d835dfec
AK		 426
427 return changed;
428}
429
49a9b07e 430int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 431{
aad82703
SY		 432 unsigned long old_cr0 = kvm_read_cr0(vcpu);
433 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
434 X86_CR0_CD | X86_CR0_NW;
435
f9a48e6a
AK		 436 cr0 |= X86_CR0_ET;
437
ab344828 438#ifdef CONFIG_X86_64
0f12244f
GN		 439 if (cr0 & 0xffffffff00000000UL)
440 return 1;
ab344828
GN		 441#endif
442
443 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 444
0f12244f
GN		 445 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
446 return 1;
a03490ed 447
0f12244f
GN		 448 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
449 return 1;
a03490ed
CO		 450
451 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
452#ifdef CONFIG_X86_64
f6801dff 453 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 454 int cs_db, cs_l;
455
0f12244f
GN		 456 if (!is_pae(vcpu))
457 return 1;
a03490ed 458 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 459 if (cs_l)
460 return 1;
a03490ed
CO		 461 } else
462#endif
0f12244f
GN		 463 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
464 return 1;
a03490ed
CO		 465 }
466
467 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 468
aad82703
SY		 469 if ((cr0 ^ old_cr0) & update_bits)
470 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 471 return 0;
472}
2d3ad1f4 473EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 474
2d3ad1f4 475void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 476{
49a9b07e 477 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 478}
2d3ad1f4 479EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 480
2acf923e
DC		 481int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
482{
483 u64 xcr0;
484
485 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
486 if (index != XCR_XFEATURE_ENABLED_MASK)
487 return 1;
488 xcr0 = xcr;
489 if (kvm_x86_ops->get_cpl(vcpu) != 0)
490 return 1;
491 if (!(xcr0 & XSTATE_FP))
492 return 1;
493 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
494 return 1;
495 if (xcr0 & ~host_xcr0)
496 return 1;
497 vcpu->arch.xcr0 = xcr0;
498 vcpu->guest_xcr0_loaded = 0;
499 return 0;
500}
501
502int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
503{
504 if (__kvm_set_xcr(vcpu, index, xcr)) {
505 kvm_inject_gp(vcpu, 0);
506 return 1;
507 }
508 return 0;
509}
510EXPORT_SYMBOL_GPL(kvm_set_xcr);
511
512static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
513{
514 struct kvm_cpuid_entry2 *best;
515
516 best = kvm_find_cpuid_entry(vcpu, 1, 0);
517 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
518}
519
520static void update_cpuid(struct kvm_vcpu *vcpu)
521{
522 struct kvm_cpuid_entry2 *best;
523
524 best = kvm_find_cpuid_entry(vcpu, 1, 0);
525 if (!best)
526 return;
527
528 /* Update OSXSAVE bit */
529 if (cpu_has_xsave && best->function == 0x1) {
530 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
531 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
532 best->ecx |= bit(X86_FEATURE_OSXSAVE);
533 }
534}
535
a83b29c6 536int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 537{
fc78f519 538 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 539 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
540
0f12244f
GN		 541 if (cr4 & CR4_RESERVED_BITS)
542 return 1;
a03490ed 543
2acf923e
DC		 544 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
545 return 1;
546
a03490ed 547 if (is_long_mode(vcpu)) {
0f12244f
GN		 548 if (!(cr4 & X86_CR4_PAE))
549 return 1;
a2edf57f
AK		 550 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
551 && ((cr4 ^ old_cr4) & pdptr_bits)
0f12244f
GN		 552 && !load_pdptrs(vcpu, vcpu->arch.cr3))
553 return 1;
554
555 if (cr4 & X86_CR4_VMXE)
556 return 1;
a03490ed 557
a03490ed 558 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 559
aad82703
SY		 560 if ((cr4 ^ old_cr4) & pdptr_bits)
561 kvm_mmu_reset_context(vcpu);
0f12244f 562
2acf923e
DC		 563 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
564 update_cpuid(vcpu);
565
0f12244f
GN		 566 return 0;
567}
2d3ad1f4 568EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 569
2390218b 570int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 571{
ad312c7c 572 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 573 kvm_mmu_sync_roots(vcpu);
d835dfec 574 kvm_mmu_flush_tlb(vcpu);
0f12244f 575 return 0;
d835dfec
AK		 576 }
577
a03490ed 578 if (is_long_mode(vcpu)) {
0f12244f
GN		 579 if (cr3 & CR3_L_MODE_RESERVED_BITS)
580 return 1;
a03490ed
CO		 581 } else {
582 if (is_pae(vcpu)) {
0f12244f
GN		 583 if (cr3 & CR3_PAE_RESERVED_BITS)
584 return 1;
585 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
586 return 1;
a03490ed
CO		 587 }
588 /*
589 * We don't check reserved bits in nonpae mode, because
590 * this isn't enforced, and VMware depends on this.
591 */
592 }
593
a03490ed
CO		 594 /*
595 * Does the new cr3 value map to physical memory? (Note, we
596 * catch an invalid cr3 even in real-mode, because it would
597 * cause trouble later on when we turn on paging anyway.)
598 *
599 * A real CPU would silently accept an invalid cr3 and would
600 * attempt to use it - with largely undefined (and often hard
601 * to debug) behavior on the guest side.
602 */
603 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 604 return 1;
605 vcpu->arch.cr3 = cr3;
606 vcpu->arch.mmu.new_cr3(vcpu);
607 return 0;
608}
2d3ad1f4 609EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 610
0f12244f 611int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 612{
0f12244f
GN		 613 if (cr8 & CR8_RESERVED_BITS)
614 return 1;
a03490ed
CO		 615 if (irqchip_in_kernel(vcpu->kvm))
616 kvm_lapic_set_tpr(vcpu, cr8);
617 else
ad312c7c 618 vcpu->arch.cr8 = cr8;
0f12244f
GN		 619 return 0;
620}
621
622void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
623{
624 if (__kvm_set_cr8(vcpu, cr8))
625 kvm_inject_gp(vcpu, 0);
a03490ed 626}
2d3ad1f4 627EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 628
2d3ad1f4 629unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 630{
631 if (irqchip_in_kernel(vcpu->kvm))
632 return kvm_lapic_get_cr8(vcpu);
633 else
ad312c7c 634 return vcpu->arch.cr8;
a03490ed 635}
2d3ad1f4 636EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 637
338dbc97 638static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 639{
640 switch (dr) {
641 case 0 ... 3:
642 vcpu->arch.db[dr] = val;
643 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
644 vcpu->arch.eff_db[dr] = val;
645 break;
646 case 4:
338dbc97
GN		 647 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
648 return 1; /* #UD */
020df079
GN		 649 /* fall through */
650 case 6:
338dbc97
GN		 651 if (val & 0xffffffff00000000ULL)
652 return -1; /* #GP */
020df079
GN		 653 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
654 break;
655 case 5:
338dbc97
GN		 656 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
657 return 1; /* #UD */
020df079
GN		 658 /* fall through */
659 default: /* 7 */
338dbc97
GN		 660 if (val & 0xffffffff00000000ULL)
661 return -1; /* #GP */
020df079
GN		 662 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
663 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
664 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
665 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
666 }
667 break;
668 }
669
670 return 0;
671}
338dbc97
GN		 672
673int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
674{
675 int res;
676
677 res = __kvm_set_dr(vcpu, dr, val);
678 if (res > 0)
679 kvm_queue_exception(vcpu, UD_VECTOR);
680 else if (res < 0)
681 kvm_inject_gp(vcpu, 0);
682
683 return res;
684}
020df079
GN		 685EXPORT_SYMBOL_GPL(kvm_set_dr);
686
338dbc97 687static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 688{
689 switch (dr) {
690 case 0 ... 3:
691 *val = vcpu->arch.db[dr];
692 break;
693 case 4:
338dbc97 694 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 695 return 1;
020df079
GN		 696 /* fall through */
697 case 6:
698 *val = vcpu->arch.dr6;
699 break;
700 case 5:
338dbc97 701 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 702 return 1;
020df079
GN		 703 /* fall through */
704 default: /* 7 */
705 *val = vcpu->arch.dr7;
706 break;
707 }
708
709 return 0;
710}
338dbc97
GN		 711
712int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
713{
714 if (_kvm_get_dr(vcpu, dr, val)) {
715 kvm_queue_exception(vcpu, UD_VECTOR);
716 return 1;
717 }
718 return 0;
719}
020df079
GN		 720EXPORT_SYMBOL_GPL(kvm_get_dr);
721
043405e1
CO		 722/*
723 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
724 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
725 *
726 * This list is modified at module load time to reflect the
e3267cbb
GC		 727 * capabilities of the host cpu. This capabilities test skips MSRs that are
728 * kvm-specific. Those are put in the beginning of the list.
043405e1 729 */
e3267cbb 730
11c6bffa 731#define KVM_SAVE_MSRS_BEGIN 7
043405e1 732static u32 msrs_to_save[] = {
e3267cbb 733 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 734 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 735 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 736 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 737 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 738 MSR_STAR,
043405e1
CO		 739#ifdef CONFIG_X86_64
740 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
741#endif
e90aa41e 742 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 743};
744
745static unsigned num_msrs_to_save;
746
747static u32 emulated_msrs[] = {
748 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 749 MSR_IA32_MCG_STATUS,
750 MSR_IA32_MCG_CTL,
043405e1
CO		 751};
752
b69e8cae 753static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 754{
aad82703
SY		 755 u64 old_efer = vcpu->arch.efer;
756
b69e8cae
RJ		 757 if (efer & efer_reserved_bits)
758 return 1;
15c4a640
CO		 759
760 if (is_paging(vcpu)
b69e8cae
RJ		 761 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
762 return 1;
15c4a640 763
1b2fd70c
AG		 764 if (efer & EFER_FFXSR) {
765 struct kvm_cpuid_entry2 *feat;
766
767 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 768 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
769 return 1;
1b2fd70c
AG		 770 }
771
d8017474
AG		 772 if (efer & EFER_SVME) {
773 struct kvm_cpuid_entry2 *feat;
774
775 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 776 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
777 return 1;
d8017474
AG		 778 }
779
15c4a640 780 efer &= ~EFER_LMA;
f6801dff 781 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 782
a3d204e2
SY		 783 kvm_x86_ops->set_efer(vcpu, efer);
784
9645bb56
AK		 785 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
786 kvm_mmu_reset_context(vcpu);
b69e8cae 787
aad82703
SY		 788 /* Update reserved bits */
789 if ((efer ^ old_efer) & EFER_NX)
790 kvm_mmu_reset_context(vcpu);
791
b69e8cae 792 return 0;
15c4a640
CO		 793}
794
f2b4b7dd
JR		 795void kvm_enable_efer_bits(u64 mask)
796{
797 efer_reserved_bits &= ~mask;
798}
799EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
800
801
15c4a640
CO		 802/*
803 * Writes msr value into into the appropriate "register".
804 * Returns 0 on success, non-0 otherwise.
805 * Assumes vcpu_load() was already called.
806 */
807int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
808{
809 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
810}
811
313a3dc7
CO		 812/*
813 * Adapt set_msr() to msr_io()'s calling convention
814 */
815static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
816{
817 return kvm_set_msr(vcpu, index, *data);
818}
819
18068523
GOC		 820static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
821{
9ed3c444
AK		 822 int version;
823 int r;
50d0a0f9 824 struct pvclock_wall_clock wc;
923de3cf 825 struct timespec boot;
18068523
GOC		 826
827 if (!wall_clock)
828 return;
829
9ed3c444
AK		 830 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
831 if (r)
832 return;
833
834 if (version & 1)
835 ++version; /* first time write, random junk */
836
837 ++version;
18068523 838
18068523
GOC		 839 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
840
50d0a0f9
GH		 841 /*
842 * The guest calculates current wall clock time by adding
843 * system time (updated by kvm_write_guest_time below) to the
844 * wall clock specified here. guest system time equals host
845 * system time for us, thus we must fill in host boot time here.
846 */
923de3cf 847 getboottime(&boot);
50d0a0f9
GH		 848
849 wc.sec = boot.tv_sec;
850 wc.nsec = boot.tv_nsec;
851 wc.version = version;
18068523
GOC		 852
853 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
854
855 version++;
856 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 857}
858
50d0a0f9
GH		 859static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
860{
861 uint32_t quotient, remainder;
862
863 /* Don't try to replace with do_div(), this one calculates
864 * "(dividend << 32) / divisor" */
865 __asm__ ( "divl %4"
866 : "=a" (quotient), "=d" (remainder)
867 : "0" (0), "1" (dividend), "r" (divisor) );
868 return quotient;
869}
870
871static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
872{
873 uint64_t nsecs = 1000000000LL;
874 int32_t shift = 0;
875 uint64_t tps64;
876 uint32_t tps32;
877
878 tps64 = tsc_khz * 1000LL;
879 while (tps64 > nsecs*2) {
880 tps64 >>= 1;
881 shift--;
882 }
883
884 tps32 = (uint32_t)tps64;
885 while (tps32 <= (uint32_t)nsecs) {
886 tps32 <<= 1;
887 shift++;
888 }
889
890 hv_clock->tsc_shift = shift;
891 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
892
893 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 894 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 895 hv_clock->tsc_to_system_mul);
896}
897
759379dd
ZA		 898static inline u64 get_kernel_ns(void)
899{
900 struct timespec ts;
901
902 WARN_ON(preemptible());
903 ktime_get_ts(&ts);
904 monotonic_to_bootbased(&ts);
905 return timespec_to_ns(&ts);
906}
907
c8076604
GH		 908static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
909
8cfdc000
ZA		 910static inline int kvm_tsc_changes_freq(void)
911{
912 int cpu = get_cpu();
913 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
914 cpufreq_quick_get(cpu) != 0;
915 put_cpu();
916 return ret;
917}
918
759379dd
ZA		 919static inline u64 nsec_to_cycles(u64 nsec)
920{
217fc9cf
AK		 921 u64 ret;
922
759379dd
ZA		 923 WARN_ON(preemptible());
924 if (kvm_tsc_changes_freq())
925 printk_once(KERN_WARNING
926 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 927 ret = nsec * __get_cpu_var(cpu_tsc_khz);
928 do_div(ret, USEC_PER_SEC);
929 return ret;
759379dd
ZA		 930}
931
99e3e30a
ZA		 932void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
933{
934 struct kvm *kvm = vcpu->kvm;
f38e098f 935 u64 offset, ns, elapsed;
99e3e30a 936 unsigned long flags;
46543ba4 937 s64 sdiff;
99e3e30a
ZA		 938
939 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
940 offset = data - native_read_tsc();
759379dd 941 ns = get_kernel_ns();
f38e098f 942 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 943 sdiff = data - kvm->arch.last_tsc_write;
944 if (sdiff < 0)
945 sdiff = -sdiff;
f38e098f
ZA		 946
947 /*
46543ba4 948 * Special case: close write to TSC within 5 seconds of
f38e098f 949 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 950 * The 5 seconds is to accomodate host load / swapping as
951 * well as any reset of TSC during the boot process.
f38e098f
ZA		 952 *
953 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 954 * or make a best guest using elapsed value.
f38e098f 955 */
46543ba4
ZA		 956 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
957 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 958 if (!check_tsc_unstable()) {
959 offset = kvm->arch.last_tsc_offset;
960 pr_debug("kvm: matched tsc offset for %llu\n", data);
961 } else {
759379dd
ZA		 962 u64 delta = nsec_to_cycles(elapsed);
963 offset += delta;
964 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 965 }
966 ns = kvm->arch.last_tsc_nsec;
967 }
968 kvm->arch.last_tsc_nsec = ns;
969 kvm->arch.last_tsc_write = data;
970 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 971 kvm_x86_ops->write_tsc_offset(vcpu, offset);
972 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
973
974 /* Reset of TSC must disable overshoot protection below */
975 vcpu->arch.hv_clock.tsc_timestamp = 0;
976}
977EXPORT_SYMBOL_GPL(kvm_write_tsc);
978
8cfdc000 979static int kvm_write_guest_time(struct kvm_vcpu *v)
18068523 980{
18068523
GOC		 981 unsigned long flags;
982 struct kvm_vcpu_arch *vcpu = &v->arch;
983 void *shared_kaddr;
463656c0 984 unsigned long this_tsc_khz;
1d5f066e
ZA		 985 s64 kernel_ns, max_kernel_ns;
986 u64 tsc_timestamp;
18068523
GOC		 987
988 if ((!vcpu->time_page))
8cfdc000 989 return 0;
50d0a0f9 990
18068523
GOC		 991 /* Keep irq disabled to prevent changes to the clock */
992 local_irq_save(flags);
1d5f066e 993 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 994 kernel_ns = get_kernel_ns();
8cfdc000 995 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523
GOC		 996 local_irq_restore(flags);
997
8cfdc000
ZA		 998 if (unlikely(this_tsc_khz == 0)) {
999 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
1000 return 1;
1001 }
18068523 1002
1d5f066e
ZA		 1003 /*
1004 * Time as measured by the TSC may go backwards when resetting the base
1005 * tsc_timestamp. The reason for this is that the TSC resolution is
1006 * higher than the resolution of the other clock scales. Thus, many
1007 * possible measurments of the TSC correspond to one measurement of any
1008 * other clock, and so a spread of values is possible. This is not a
1009 * problem for the computation of the nanosecond clock; with TSC rates
1010 * around 1GHZ, there can only be a few cycles which correspond to one
1011 * nanosecond value, and any path through this code will inevitably
1012 * take longer than that. However, with the kernel_ns value itself,
1013 * the precision may be much lower, down to HZ granularity. If the
1014 * first sampling of TSC against kernel_ns ends in the low part of the
1015 * range, and the second in the high end of the range, we can get:
1016 *
1017 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1018 *
1019 * As the sampling errors potentially range in the thousands of cycles,
1020 * it is possible such a time value has already been observed by the
1021 * guest. To protect against this, we must compute the system time as
1022 * observed by the guest and ensure the new system time is greater.
1023 */
1024 max_kernel_ns = 0;
1025 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1026 max_kernel_ns = vcpu->last_guest_tsc -
1027 vcpu->hv_clock.tsc_timestamp;
1028 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1029 vcpu->hv_clock.tsc_to_system_mul,
1030 vcpu->hv_clock.tsc_shift);
1031 max_kernel_ns += vcpu->last_kernel_ns;
1032 }
1033
e48672fa 1034 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
8cfdc000 1035 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
e48672fa 1036 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1037 }
1038
1d5f066e
ZA		 1039 if (max_kernel_ns > kernel_ns)
1040 kernel_ns = max_kernel_ns;
1041
8cfdc000 1042 /* With all the info we got, fill in the values */
1d5f066e 1043 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1044 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1045 vcpu->last_kernel_ns = kernel_ns;
371bcf64
GC		 1046 vcpu->hv_clock.flags = 0;
1047
18068523
GOC		 1048 /*
1049 * The interface expects us to write an even number signaling that the
1050 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1051 * state, we just increase by 2 at the end.
18068523 1052 */
50d0a0f9 1053 vcpu->hv_clock.version += 2;
18068523
GOC		 1054
1055 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1056
1057 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1058 sizeof(vcpu->hv_clock));
18068523
GOC		 1059
1060 kunmap_atomic(shared_kaddr, KM_USER0);
1061
1062 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1063 return 0;
18068523
GOC		 1064}
1065
c8076604
GH		 1066static int kvm_request_guest_time_update(struct kvm_vcpu *v)
1067{
1068 struct kvm_vcpu_arch *vcpu = &v->arch;
1069
1070 if (!vcpu->time_page)
1071 return 0;
a8eeb04a 1072 kvm_make_request(KVM_REQ_KVMCLOCK_UPDATE, v);
c8076604
GH		 1073 return 1;
1074}
1075
9ba075a6
AK		 1076static bool msr_mtrr_valid(unsigned msr)
1077{
1078 switch (msr) {
1079 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1080 case MSR_MTRRfix64K_00000:
1081 case MSR_MTRRfix16K_80000:
1082 case MSR_MTRRfix16K_A0000:
1083 case MSR_MTRRfix4K_C0000:
1084 case MSR_MTRRfix4K_C8000:
1085 case MSR_MTRRfix4K_D0000:
1086 case MSR_MTRRfix4K_D8000:
1087 case MSR_MTRRfix4K_E0000:
1088 case MSR_MTRRfix4K_E8000:
1089 case MSR_MTRRfix4K_F0000:
1090 case MSR_MTRRfix4K_F8000:
1091 case MSR_MTRRdefType:
1092 case MSR_IA32_CR_PAT:
1093 return true;
1094 case 0x2f8:
1095 return true;
1096 }
1097 return false;
1098}
1099
d6289b93
MT		 1100static bool valid_pat_type(unsigned t)
1101{
1102 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1103}
1104
1105static bool valid_mtrr_type(unsigned t)
1106{
1107 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1108}
1109
1110static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1111{
1112 int i;
1113
1114 if (!msr_mtrr_valid(msr))
1115 return false;
1116
1117 if (msr == MSR_IA32_CR_PAT) {
1118 for (i = 0; i < 8; i++)
1119 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1120 return false;
1121 return true;
1122 } else if (msr == MSR_MTRRdefType) {
1123 if (data & ~0xcff)
1124 return false;
1125 return valid_mtrr_type(data & 0xff);
1126 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1127 for (i = 0; i < 8 ; i++)
1128 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1129 return false;
1130 return true;
1131 }
1132
1133 /* variable MTRRs */
1134 return valid_mtrr_type(data & 0xff);
1135}
1136
9ba075a6
AK		 1137static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1138{
0bed3b56
SY		 1139 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1140
d6289b93 1141 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1142 return 1;
1143
0bed3b56
SY		 1144 if (msr == MSR_MTRRdefType) {
1145 vcpu->arch.mtrr_state.def_type = data;
1146 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1147 } else if (msr == MSR_MTRRfix64K_00000)
1148 p[0] = data;
1149 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1150 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1151 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1152 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1153 else if (msr == MSR_IA32_CR_PAT)
1154 vcpu->arch.pat = data;
1155 else { /* Variable MTRRs */
1156 int idx, is_mtrr_mask;
1157 u64 *pt;
1158
1159 idx = (msr - 0x200) / 2;
1160 is_mtrr_mask = msr - 0x200 - 2 * idx;
1161 if (!is_mtrr_mask)
1162 pt =
1163 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1164 else
1165 pt =
1166 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1167 *pt = data;
1168 }
1169
1170 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1171 return 0;
1172}
15c4a640 1173
890ca9ae 1174static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1175{
890ca9ae
HY		 1176 u64 mcg_cap = vcpu->arch.mcg_cap;
1177 unsigned bank_num = mcg_cap & 0xff;
1178
15c4a640 1179 switch (msr) {
15c4a640 1180 case MSR_IA32_MCG_STATUS:
890ca9ae 1181 vcpu->arch.mcg_status = data;
15c4a640 1182 break;
c7ac679c 1183 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1184 if (!(mcg_cap & MCG_CTL_P))
1185 return 1;
1186 if (data != 0 && data != ~(u64)0)
1187 return -1;
1188 vcpu->arch.mcg_ctl = data;
1189 break;
1190 default:
1191 if (msr >= MSR_IA32_MC0_CTL &&
1192 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1193 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1194 /* only 0 or all 1s can be written to IA32_MCi_CTL
1195 * some Linux kernels though clear bit 10 in bank 4 to
1196 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1197 * this to avoid an uncatched #GP in the guest
1198 */
890ca9ae 1199 if ((offset & 0x3) == 0 &&
114be429 1200 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1201 return -1;
1202 vcpu->arch.mce_banks[offset] = data;
1203 break;
1204 }
1205 return 1;
1206 }
1207 return 0;
1208}
1209
ffde22ac
ES		 1210static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1211{
1212 struct kvm *kvm = vcpu->kvm;
1213 int lm = is_long_mode(vcpu);
1214 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1215 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1216 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1217 : kvm->arch.xen_hvm_config.blob_size_32;
1218 u32 page_num = data & ~PAGE_MASK;
1219 u64 page_addr = data & PAGE_MASK;
1220 u8 *page;
1221 int r;
1222
1223 r = -E2BIG;
1224 if (page_num >= blob_size)
1225 goto out;
1226 r = -ENOMEM;
1227 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1228 if (!page)
1229 goto out;
1230 r = -EFAULT;
1231 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1232 goto out_free;
1233 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1234 goto out_free;
1235 r = 0;
1236out_free:
1237 kfree(page);
1238out:
1239 return r;
1240}
1241
55cd8e5a
GN		 1242static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1243{
1244 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1245}
1246
1247static bool kvm_hv_msr_partition_wide(u32 msr)
1248{
1249 bool r = false;
1250 switch (msr) {
1251 case HV_X64_MSR_GUEST_OS_ID:
1252 case HV_X64_MSR_HYPERCALL:
1253 r = true;
1254 break;
1255 }
1256
1257 return r;
1258}
1259
1260static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1261{
1262 struct kvm *kvm = vcpu->kvm;
1263
1264 switch (msr) {
1265 case HV_X64_MSR_GUEST_OS_ID:
1266 kvm->arch.hv_guest_os_id = data;
1267 /* setting guest os id to zero disables hypercall page */
1268 if (!kvm->arch.hv_guest_os_id)
1269 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1270 break;
1271 case HV_X64_MSR_HYPERCALL: {
1272 u64 gfn;
1273 unsigned long addr;
1274 u8 instructions[4];
1275
1276 /* if guest os id is not set hypercall should remain disabled */
1277 if (!kvm->arch.hv_guest_os_id)
1278 break;
1279 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1280 kvm->arch.hv_hypercall = data;
1281 break;
1282 }
1283 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1284 addr = gfn_to_hva(kvm, gfn);
1285 if (kvm_is_error_hva(addr))
1286 return 1;
1287 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1288 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1289 if (copy_to_user((void __user *)addr, instructions, 4))
1290 return 1;
1291 kvm->arch.hv_hypercall = data;
1292 break;
1293 }
1294 default:
1295 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1296 "data 0x%llx\n", msr, data);
1297 return 1;
1298 }
1299 return 0;
1300}
1301
1302static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1303{
10388a07
GN		 1304 switch (msr) {
1305 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1306 unsigned long addr;
55cd8e5a 1307
10388a07
GN		 1308 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1309 vcpu->arch.hv_vapic = data;
1310 break;
1311 }
1312 addr = gfn_to_hva(vcpu->kvm, data >>
1313 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1314 if (kvm_is_error_hva(addr))
1315 return 1;
1316 if (clear_user((void __user *)addr, PAGE_SIZE))
1317 return 1;
1318 vcpu->arch.hv_vapic = data;
1319 break;
1320 }
1321 case HV_X64_MSR_EOI:
1322 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1323 case HV_X64_MSR_ICR:
1324 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1325 case HV_X64_MSR_TPR:
1326 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1327 default:
1328 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1329 "data 0x%llx\n", msr, data);
1330 return 1;
1331 }
1332
1333 return 0;
55cd8e5a
GN		 1334}
1335
15c4a640
CO		 1336int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1337{
1338 switch (msr) {
15c4a640 1339 case MSR_EFER:
b69e8cae 1340 return set_efer(vcpu, data);
8f1589d9
AP		 1341 case MSR_K7_HWCR:
1342 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1343 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1344 if (data != 0) {
1345 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1346 data);
1347 return 1;
1348 }
15c4a640 1349 break;
f7c6d140
AP		 1350 case MSR_FAM10H_MMIO_CONF_BASE:
1351 if (data != 0) {
1352 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1353 "0x%llx\n", data);
1354 return 1;
1355 }
15c4a640 1356 break;
c323c0e5 1357 case MSR_AMD64_NB_CFG:
c7ac679c 1358 break;
b5e2fec0
AG		 1359 case MSR_IA32_DEBUGCTLMSR:
1360 if (!data) {
1361 /* We support the non-activated case already */
1362 break;
1363 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1364 /* Values other than LBR and BTF are vendor-specific,
1365 thus reserved and should throw a #GP */
1366 return 1;
1367 }
1368 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1369 __func__, data);
1370 break;
15c4a640
CO		 1371 case MSR_IA32_UCODE_REV:
1372 case MSR_IA32_UCODE_WRITE:
61a6bd67 1373 case MSR_VM_HSAVE_PA:
6098ca93 1374 case MSR_AMD64_PATCH_LOADER:
15c4a640 1375 break;
9ba075a6
AK		 1376 case 0x200 ... 0x2ff:
1377 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1378 case MSR_IA32_APICBASE:
1379 kvm_set_apic_base(vcpu, data);
1380 break;
0105d1a5
GN		 1381 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1382 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1383 case MSR_IA32_MISC_ENABLE:
ad312c7c 1384 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1385 break;
11c6bffa 1386 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1387 case MSR_KVM_WALL_CLOCK:
1388 vcpu->kvm->arch.wall_clock = data;
1389 kvm_write_wall_clock(vcpu->kvm, data);
1390 break;
11c6bffa 1391 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1392 case MSR_KVM_SYSTEM_TIME: {
1393 if (vcpu->arch.time_page) {
1394 kvm_release_page_dirty(vcpu->arch.time_page);
1395 vcpu->arch.time_page = NULL;
1396 }
1397
1398 vcpu->arch.time = data;
1399
1400 /* we verify if the enable bit is set... */
1401 if (!(data & 1))
1402 break;
1403
1404 /* ...but clean it before doing the actual write */
1405 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1406
18068523
GOC		 1407 vcpu->arch.time_page =
1408 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1409
1410 if (is_error_page(vcpu->arch.time_page)) {
1411 kvm_release_page_clean(vcpu->arch.time_page);
1412 vcpu->arch.time_page = NULL;
1413 }
1414
c8076604 1415 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1416 break;
1417 }
890ca9ae
HY		 1418 case MSR_IA32_MCG_CTL:
1419 case MSR_IA32_MCG_STATUS:
1420 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1421 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1422
1423 /* Performance counters are not protected by a CPUID bit,
1424 * so we should check all of them in the generic path for the sake of
1425 * cross vendor migration.
1426 * Writing a zero into the event select MSRs disables them,
1427 * which we perfectly emulate ;-). Any other value should be at least
1428 * reported, some guests depend on them.
1429 */
1430 case MSR_P6_EVNTSEL0:
1431 case MSR_P6_EVNTSEL1:
1432 case MSR_K7_EVNTSEL0:
1433 case MSR_K7_EVNTSEL1:
1434 case MSR_K7_EVNTSEL2:
1435 case MSR_K7_EVNTSEL3:
1436 if (data != 0)
1437 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1438 "0x%x data 0x%llx\n", msr, data);
1439 break;
1440 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1441 * so we ignore writes to make it happy.
1442 */
1443 case MSR_P6_PERFCTR0:
1444 case MSR_P6_PERFCTR1:
1445 case MSR_K7_PERFCTR0:
1446 case MSR_K7_PERFCTR1:
1447 case MSR_K7_PERFCTR2:
1448 case MSR_K7_PERFCTR3:
1449 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1450 "0x%x data 0x%llx\n", msr, data);
1451 break;
84e0cefa
JS		 1452 case MSR_K7_CLK_CTL:
1453 /*
1454 * Ignore all writes to this no longer documented MSR.
1455 * Writes are only relevant for old K7 processors,
1456 * all pre-dating SVM, but a recommended workaround from
1457 * AMD for these chips. It is possible to speicify the
1458 * affected processor models on the command line, hence
1459 * the need to ignore the workaround.
1460 */
1461 break;
55cd8e5a
GN		 1462 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1463 if (kvm_hv_msr_partition_wide(msr)) {
1464 int r;
1465 mutex_lock(&vcpu->kvm->lock);
1466 r = set_msr_hyperv_pw(vcpu, msr, data);
1467 mutex_unlock(&vcpu->kvm->lock);
1468 return r;
1469 } else
1470 return set_msr_hyperv(vcpu, msr, data);
1471 break;
15c4a640 1472 default:
ffde22ac
ES		 1473 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1474 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1475 if (!ignore_msrs) {
1476 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1477 msr, data);
1478 return 1;
1479 } else {
1480 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1481 msr, data);
1482 break;
1483 }
15c4a640
CO		 1484 }
1485 return 0;
1486}
1487EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1488
1489
1490/*
1491 * Reads an msr value (of 'msr_index') into 'pdata'.
1492 * Returns 0 on success, non-0 otherwise.
1493 * Assumes vcpu_load() was already called.
1494 */
1495int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1496{
1497 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1498}
1499
9ba075a6
AK		 1500static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1501{
0bed3b56
SY		 1502 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1503
9ba075a6
AK		 1504 if (!msr_mtrr_valid(msr))
1505 return 1;
1506
0bed3b56
SY		 1507 if (msr == MSR_MTRRdefType)
1508 *pdata = vcpu->arch.mtrr_state.def_type +
1509 (vcpu->arch.mtrr_state.enabled << 10);
1510 else if (msr == MSR_MTRRfix64K_00000)
1511 *pdata = p[0];
1512 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1513 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1514 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1515 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1516 else if (msr == MSR_IA32_CR_PAT)
1517 *pdata = vcpu->arch.pat;
1518 else { /* Variable MTRRs */
1519 int idx, is_mtrr_mask;
1520 u64 *pt;
1521
1522 idx = (msr - 0x200) / 2;
1523 is_mtrr_mask = msr - 0x200 - 2 * idx;
1524 if (!is_mtrr_mask)
1525 pt =
1526 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1527 else
1528 pt =
1529 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1530 *pdata = *pt;
1531 }
1532
9ba075a6
AK		 1533 return 0;
1534}
1535
890ca9ae 1536static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1537{
1538 u64 data;
890ca9ae
HY		 1539 u64 mcg_cap = vcpu->arch.mcg_cap;
1540 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1541
1542 switch (msr) {
15c4a640
CO		 1543 case MSR_IA32_P5_MC_ADDR:
1544 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1545 data = 0;
1546 break;
15c4a640 1547 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1548 data = vcpu->arch.mcg_cap;
1549 break;
c7ac679c 1550 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1551 if (!(mcg_cap & MCG_CTL_P))
1552 return 1;
1553 data = vcpu->arch.mcg_ctl;
1554 break;
1555 case MSR_IA32_MCG_STATUS:
1556 data = vcpu->arch.mcg_status;
1557 break;
1558 default:
1559 if (msr >= MSR_IA32_MC0_CTL &&
1560 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1561 u32 offset = msr - MSR_IA32_MC0_CTL;
1562 data = vcpu->arch.mce_banks[offset];
1563 break;
1564 }
1565 return 1;
1566 }
1567 *pdata = data;
1568 return 0;
1569}
1570
55cd8e5a
GN		 1571static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1572{
1573 u64 data = 0;
1574 struct kvm *kvm = vcpu->kvm;
1575
1576 switch (msr) {
1577 case HV_X64_MSR_GUEST_OS_ID:
1578 data = kvm->arch.hv_guest_os_id;
1579 break;
1580 case HV_X64_MSR_HYPERCALL:
1581 data = kvm->arch.hv_hypercall;
1582 break;
1583 default:
1584 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1585 return 1;
1586 }
1587
1588 *pdata = data;
1589 return 0;
1590}
1591
1592static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1593{
1594 u64 data = 0;
1595
1596 switch (msr) {
1597 case HV_X64_MSR_VP_INDEX: {
1598 int r;
1599 struct kvm_vcpu *v;
1600 kvm_for_each_vcpu(r, v, vcpu->kvm)
1601 if (v == vcpu)
1602 data = r;
1603 break;
1604 }
10388a07
GN		 1605 case HV_X64_MSR_EOI:
1606 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1607 case HV_X64_MSR_ICR:
1608 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1609 case HV_X64_MSR_TPR:
1610 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1611 default:
1612 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1613 return 1;
1614 }
1615 *pdata = data;
1616 return 0;
1617}
1618
890ca9ae
HY		 1619int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1620{
1621 u64 data;
1622
1623 switch (msr) {
890ca9ae 1624 case MSR_IA32_PLATFORM_ID:
15c4a640 1625 case MSR_IA32_UCODE_REV:
15c4a640 1626 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1627 case MSR_IA32_DEBUGCTLMSR:
1628 case MSR_IA32_LASTBRANCHFROMIP:
1629 case MSR_IA32_LASTBRANCHTOIP:
1630 case MSR_IA32_LASTINTFROMIP:
1631 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1632 case MSR_K8_SYSCFG:
1633 case MSR_K7_HWCR:
61a6bd67 1634 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1635 case MSR_P6_PERFCTR0:
1636 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1637 case MSR_P6_EVNTSEL0:
1638 case MSR_P6_EVNTSEL1:
9e699624 1639 case MSR_K7_EVNTSEL0:
1f3ee616 1640 case MSR_K7_PERFCTR0:
1fdbd48c 1641 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1642 case MSR_AMD64_NB_CFG:
f7c6d140 1643 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1644 data = 0;
1645 break;
9ba075a6
AK		 1646 case MSR_MTRRcap:
1647 data = 0x500 | KVM_NR_VAR_MTRR;
1648 break;
1649 case 0x200 ... 0x2ff:
1650 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1651 case 0xcd: /* fsb frequency */
1652 data = 3;
1653 break;
1654 case MSR_IA32_APICBASE:
1655 data = kvm_get_apic_base(vcpu);
1656 break;
0105d1a5
GN		 1657 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1658 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1659 break;
15c4a640 1660 case MSR_IA32_MISC_ENABLE:
ad312c7c 1661 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1662 break;
847f0ad8
AG		 1663 case MSR_IA32_PERF_STATUS:
1664 /* TSC increment by tick */
1665 data = 1000ULL;
1666 /* CPU multiplier */
1667 data |= (((uint64_t)4ULL) << 40);
1668 break;
15c4a640 1669 case MSR_EFER:
f6801dff 1670 data = vcpu->arch.efer;
15c4a640 1671 break;
18068523 1672 case MSR_KVM_WALL_CLOCK:
11c6bffa 1673 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1674 data = vcpu->kvm->arch.wall_clock;
1675 break;
1676 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1677 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1678 data = vcpu->arch.time;
1679 break;
890ca9ae
HY		 1680 case MSR_IA32_P5_MC_ADDR:
1681 case MSR_IA32_P5_MC_TYPE:
1682 case MSR_IA32_MCG_CAP:
1683 case MSR_IA32_MCG_CTL:
1684 case MSR_IA32_MCG_STATUS:
1685 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1686 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1687 case MSR_K7_CLK_CTL:
1688 /*
1689 * Provide expected ramp-up count for K7. All other
1690 * are set to zero, indicating minimum divisors for
1691 * every field.
1692 *
1693 * This prevents guest kernels on AMD host with CPU
1694 * type 6, model 8 and higher from exploding due to
1695 * the rdmsr failing.
1696 */
1697 data = 0x20000000;
1698 break;
55cd8e5a
GN		 1699 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1700 if (kvm_hv_msr_partition_wide(msr)) {
1701 int r;
1702 mutex_lock(&vcpu->kvm->lock);
1703 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1704 mutex_unlock(&vcpu->kvm->lock);
1705 return r;
1706 } else
1707 return get_msr_hyperv(vcpu, msr, pdata);
1708 break;
15c4a640 1709 default:
ed85c068
AP		 1710 if (!ignore_msrs) {
1711 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1712 return 1;
1713 } else {
1714 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1715 data = 0;
1716 }
1717 break;
15c4a640
CO		 1718 }
1719 *pdata = data;
1720 return 0;
1721}
1722EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1723
313a3dc7
CO		 1724/*
1725 * Read or write a bunch of msrs. All parameters are kernel addresses.
1726 *
1727 * @return number of msrs set successfully.
1728 */
1729static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1730 struct kvm_msr_entry *entries,
1731 int (*do_msr)(struct kvm_vcpu *vcpu,
1732 unsigned index, u64 *data))
1733{
f656ce01 1734 int i, idx;
313a3dc7 1735
f656ce01 1736 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1737 for (i = 0; i < msrs->nmsrs; ++i)
1738 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1739 break;
f656ce01 1740 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1741
313a3dc7
CO		 1742 return i;
1743}
1744
1745/*
1746 * Read or write a bunch of msrs. Parameters are user addresses.
1747 *
1748 * @return number of msrs set successfully.
1749 */
1750static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1751 int (*do_msr)(struct kvm_vcpu *vcpu,
1752 unsigned index, u64 *data),
1753 int writeback)
1754{
1755 struct kvm_msrs msrs;
1756 struct kvm_msr_entry *entries;
1757 int r, n;
1758 unsigned size;
1759
1760 r = -EFAULT;
1761 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1762 goto out;
1763
1764 r = -E2BIG;
1765 if (msrs.nmsrs >= MAX_IO_MSRS)
1766 goto out;
1767
1768 r = -ENOMEM;
1769 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1770 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1771 if (!entries)
1772 goto out;
1773
1774 r = -EFAULT;
1775 if (copy_from_user(entries, user_msrs->entries, size))
1776 goto out_free;
1777
1778 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1779 if (r < 0)
1780 goto out_free;
1781
1782 r = -EFAULT;
1783 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1784 goto out_free;
1785
1786 r = n;
1787
1788out_free:
7a73c028 1789 kfree(entries);
313a3dc7
CO		 1790out:
1791 return r;
1792}
1793
018d00d2
ZX		 1794int kvm_dev_ioctl_check_extension(long ext)
1795{
1796 int r;
1797
1798 switch (ext) {
1799 case KVM_CAP_IRQCHIP:
1800 case KVM_CAP_HLT:
1801 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1802 case KVM_CAP_SET_TSS_ADDR:
07716717 1803 case KVM_CAP_EXT_CPUID:
c8076604 1804 case KVM_CAP_CLOCKSOURCE:
7837699f 1805 case KVM_CAP_PIT:
a28e4f5a 1806 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1807 case KVM_CAP_MP_STATE:
ed848624 1808 case KVM_CAP_SYNC_MMU:
52d939a0 1809 case KVM_CAP_REINJECT_CONTROL:
4925663a 1810 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1811 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1812 case KVM_CAP_IRQFD:
d34e6b17 1813 case KVM_CAP_IOEVENTFD:
c5ff41ce 1814 case KVM_CAP_PIT2:
e9f42757 1815 case KVM_CAP_PIT_STATE2:
b927a3ce 1816 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1817 case KVM_CAP_XEN_HVM:
afbcf7ab 1818 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1819 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1820 case KVM_CAP_HYPERV:
10388a07 1821 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1822 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1823 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1824 case KVM_CAP_DEBUGREGS:
d2be1651 1825 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1826 case KVM_CAP_XSAVE:
018d00d2
ZX		 1827 r = 1;
1828 break;
542472b5
LV		 1829 case KVM_CAP_COALESCED_MMIO:
1830 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1831 break;
774ead3a
AK		 1832 case KVM_CAP_VAPIC:
1833 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1834 break;
f725230a
AK		 1835 case KVM_CAP_NR_VCPUS:
1836 r = KVM_MAX_VCPUS;
1837 break;
a988b910
AK		 1838 case KVM_CAP_NR_MEMSLOTS:
1839 r = KVM_MEMORY_SLOTS;
1840 break;
a68a6a72
MT		 1841 case KVM_CAP_PV_MMU: /* obsolete */
1842 r = 0;
2f333bcb 1843 break;
62c476c7 1844 case KVM_CAP_IOMMU:
19de40a8 1845 r = iommu_found();
62c476c7 1846 break;
890ca9ae
HY		 1847 case KVM_CAP_MCE:
1848 r = KVM_MAX_MCE_BANKS;
1849 break;
2d5b5a66
SY		 1850 case KVM_CAP_XCRS:
1851 r = cpu_has_xsave;
1852 break;
018d00d2
ZX		 1853 default:
1854 r = 0;
1855 break;
1856 }
1857 return r;
1858
1859}
1860
043405e1
CO		 1861long kvm_arch_dev_ioctl(struct file *filp,
1862 unsigned int ioctl, unsigned long arg)
1863{
1864 void __user *argp = (void __user *)arg;
1865 long r;
1866
1867 switch (ioctl) {
1868 case KVM_GET_MSR_INDEX_LIST: {
1869 struct kvm_msr_list __user *user_msr_list = argp;
1870 struct kvm_msr_list msr_list;
1871 unsigned n;
1872
1873 r = -EFAULT;
1874 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1875 goto out;
1876 n = msr_list.nmsrs;
1877 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1878 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1879 goto out;
1880 r = -E2BIG;
e125e7b6 1881 if (n < msr_list.nmsrs)
043405e1
CO		 1882 goto out;
1883 r = -EFAULT;
1884 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1885 num_msrs_to_save * sizeof(u32)))
1886 goto out;
e125e7b6 1887 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1888 &emulated_msrs,
1889 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1890 goto out;
1891 r = 0;
1892 break;
1893 }
674eea0f
AK		 1894 case KVM_GET_SUPPORTED_CPUID: {
1895 struct kvm_cpuid2 __user *cpuid_arg = argp;
1896 struct kvm_cpuid2 cpuid;
1897
1898 r = -EFAULT;
1899 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1900 goto out;
1901 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1902 cpuid_arg->entries);
674eea0f
AK		 1903 if (r)
1904 goto out;
1905
1906 r = -EFAULT;
1907 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1908 goto out;
1909 r = 0;
1910 break;
1911 }
890ca9ae
HY		 1912 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1913 u64 mce_cap;
1914
1915 mce_cap = KVM_MCE_CAP_SUPPORTED;
1916 r = -EFAULT;
1917 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1918 goto out;
1919 r = 0;
1920 break;
1921 }
043405e1
CO		 1922 default:
1923 r = -EINVAL;
1924 }
1925out:
1926 return r;
1927}
1928
f5f48ee1
SY		 1929static void wbinvd_ipi(void *garbage)
1930{
1931 wbinvd();
1932}
1933
1934static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
1935{
1936 return vcpu->kvm->arch.iommu_domain &&
1937 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
1938}
1939
313a3dc7
CO		 1940void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1941{
f5f48ee1
SY		 1942 /* Address WBINVD may be executed by guest */
1943 if (need_emulate_wbinvd(vcpu)) {
1944 if (kvm_x86_ops->has_wbinvd_exit())
1945 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
1946 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
1947 smp_call_function_single(vcpu->cpu,
1948 wbinvd_ipi, NULL, 1);
1949 }
1950
313a3dc7 1951 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 1952 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 1953 /* Make sure TSC doesn't go backwards */
1954 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
1955 native_read_tsc() - vcpu->arch.last_host_tsc;
1956 if (tsc_delta < 0)
1957 mark_tsc_unstable("KVM discovered backwards TSC");
1958 if (check_tsc_unstable())
1959 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
1960 kvm_migrate_timers(vcpu);
1961 vcpu->cpu = cpu;
1962 }
313a3dc7
CO		 1963}
1964
1965void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1966{
02daab21 1967 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 1968 kvm_put_guest_fpu(vcpu);
e48672fa 1969 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 1970}
1971
07716717 1972static int is_efer_nx(void)
313a3dc7 1973{
e286e86e 1974 unsigned long long efer = 0;
313a3dc7 1975
e286e86e 1976 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1977 return efer & EFER_NX;
1978}
1979
1980static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1981{
1982 int i;
1983 struct kvm_cpuid_entry2 *e, *entry;
1984
313a3dc7 1985 entry = NULL;
ad312c7c
ZX		 1986 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1987 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1988 if (e->function == 0x80000001) {
1989 entry = e;
1990 break;
1991 }
1992 }
07716717 1993 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1994 entry->edx &= ~(1 << 20);
1995 printk(KERN_INFO "kvm: guest NX capability removed\n");
1996 }
1997}
1998
07716717 1999/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2000static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2001 struct kvm_cpuid *cpuid,
2002 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2003{
2004 int r, i;
2005 struct kvm_cpuid_entry *cpuid_entries;
2006
2007 r = -E2BIG;
2008 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2009 goto out;
2010 r = -ENOMEM;
2011 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2012 if (!cpuid_entries)
2013 goto out;
2014 r = -EFAULT;
2015 if (copy_from_user(cpuid_entries, entries,
2016 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2017 goto out_free;
2018 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2019 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2020 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2021 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2022 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2023 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2024 vcpu->arch.cpuid_entries[i].index = 0;
2025 vcpu->arch.cpuid_entries[i].flags = 0;
2026 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2027 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2028 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2029 }
2030 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2031 cpuid_fix_nx_cap(vcpu);
2032 r = 0;
fc61b800 2033 kvm_apic_set_version(vcpu);
0e851880 2034 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2035 update_cpuid(vcpu);
07716717
DK		 2036
2037out_free:
2038 vfree(cpuid_entries);
2039out:
2040 return r;
2041}
2042
2043static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2044 struct kvm_cpuid2 *cpuid,
2045 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2046{
2047 int r;
2048
2049 r = -E2BIG;
2050 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2051 goto out;
2052 r = -EFAULT;
ad312c7c 2053 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2054 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2055 goto out;
ad312c7c 2056 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2057 kvm_apic_set_version(vcpu);
0e851880 2058 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2059 update_cpuid(vcpu);
313a3dc7
CO		 2060 return 0;
2061
2062out:
2063 return r;
2064}
2065
07716717 2066static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2067 struct kvm_cpuid2 *cpuid,
2068 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2069{
2070 int r;
2071
2072 r = -E2BIG;
ad312c7c 2073 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2074 goto out;
2075 r = -EFAULT;
ad312c7c 2076 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2077 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2078 goto out;
2079 return 0;
2080
2081out:
ad312c7c 2082 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2083 return r;
2084}
2085
07716717 2086static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2087 u32 index)
07716717
DK		 2088{
2089 entry->function = function;
2090 entry->index = index;
2091 cpuid_count(entry->function, entry->index,
19355475 2092 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2093 entry->flags = 0;
2094}
2095
7faa4ee1
AK		 2096#define F(x) bit(X86_FEATURE_##x)
2097
07716717
DK		 2098static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2099 u32 index, int *nent, int maxnent)
2100{
7faa4ee1 2101 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2102#ifdef CONFIG_X86_64
17cc3935
SY		 2103 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2104 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2105 unsigned f_lm = F(LM);
2106#else
17cc3935 2107 unsigned f_gbpages = 0;
7faa4ee1 2108 unsigned f_lm = 0;
07716717 2109#endif
4e47c7a6 2110 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2111
2112 /* cpuid 1.edx */
2113 const u32 kvm_supported_word0_x86_features =
2114 F(FPU) | F(VME) | F(DE) | F(PSE) |
2115 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2116 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2117 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2118 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2119 0 /* Reserved, DS, ACPI */ | F(MMX) |
2120 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2121 0 /* HTT, TM, Reserved, PBE */;
2122 /* cpuid 0x80000001.edx */
2123 const u32 kvm_supported_word1_x86_features =
2124 F(FPU) | F(VME) | F(DE) | F(PSE) |
2125 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2126 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2127 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2128 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2129 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2130 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2131 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2132 /* cpuid 1.ecx */
2133 const u32 kvm_supported_word4_x86_features =
6c3f6041 2134 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2135 0 /* DS-CPL, VMX, SMX, EST */ |
2136 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2137 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2138 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2139 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6c3f6041 2140 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
7faa4ee1 2141 /* cpuid 0x80000001.ecx */
07716717 2142 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 2143 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
2144 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2145 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2146 0 /* SKINIT */ | 0 /* WDT */;
07716717 2147
19355475 2148 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2149 get_cpu();
2150 do_cpuid_1_ent(entry, function, index);
2151 ++*nent;
2152
2153 switch (function) {
2154 case 0:
2acf923e 2155 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2156 break;
2157 case 1:
2158 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2159 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2160 /* we support x2apic emulation even if host does not support
2161 * it since we emulate x2apic in software */
2162 entry->ecx |= F(X2APIC);
07716717
DK		 2163 break;
2164 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2165 * may return different values. This forces us to get_cpu() before
2166 * issuing the first command, and also to emulate this annoying behavior
2167 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2168 case 2: {
2169 int t, times = entry->eax & 0xff;
2170
2171 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2172 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2173 for (t = 1; t < times && *nent < maxnent; ++t) {
2174 do_cpuid_1_ent(&entry[t], function, 0);
2175 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2176 ++*nent;
2177 }
2178 break;
2179 }
2180 /* function 4 and 0xb have additional index. */
2181 case 4: {
14af3f3c 2182 int i, cache_type;
07716717
DK		 2183
2184 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2185 /* read more entries until cache_type is zero */
14af3f3c
HH		 2186 for (i = 1; *nent < maxnent; ++i) {
2187 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2188 if (!cache_type)
2189 break;
14af3f3c
HH		 2190 do_cpuid_1_ent(&entry[i], function, i);
2191 entry[i].flags |=
07716717
DK		 2192 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2193 ++*nent;
2194 }
2195 break;
2196 }
2197 case 0xb: {
14af3f3c 2198 int i, level_type;
07716717
DK		 2199
2200 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2201 /* read more entries until level_type is zero */
14af3f3c 2202 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2203 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2204 if (!level_type)
2205 break;
14af3f3c
HH		 2206 do_cpuid_1_ent(&entry[i], function, i);
2207 entry[i].flags |=
07716717
DK		 2208 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2209 ++*nent;
2210 }
2211 break;
2212 }
2acf923e
DC		 2213 case 0xd: {
2214 int i;
2215
2216 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2217 for (i = 1; *nent < maxnent; ++i) {
2218 if (entry[i - 1].eax == 0 && i != 2)
2219 break;
2220 do_cpuid_1_ent(&entry[i], function, i);
2221 entry[i].flags |=
2222 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2223 ++*nent;
2224 }
2225 break;
2226 }
84478c82
GC		 2227 case KVM_CPUID_SIGNATURE: {
2228 char signature[12] = "KVMKVMKVM\0\0";
2229 u32 *sigptr = (u32 *)signature;
2230 entry->eax = 0;
2231 entry->ebx = sigptr[0];
2232 entry->ecx = sigptr[1];
2233 entry->edx = sigptr[2];
2234 break;
2235 }
2236 case KVM_CPUID_FEATURES:
2237 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2238 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2239 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2240 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2241 entry->ebx = 0;
2242 entry->ecx = 0;
2243 entry->edx = 0;
2244 break;
07716717
DK		 2245 case 0x80000000:
2246 entry->eax = min(entry->eax, 0x8000001a);
2247 break;
2248 case 0x80000001:
2249 entry->edx &= kvm_supported_word1_x86_features;
2250 entry->ecx &= kvm_supported_word6_x86_features;
2251 break;
2252 }
d4330ef2
JR		 2253
2254 kvm_x86_ops->set_supported_cpuid(function, entry);
2255
07716717
DK		 2256 put_cpu();
2257}
2258
7faa4ee1
AK		 2259#undef F
2260
674eea0f 2261static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2262 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2263{
2264 struct kvm_cpuid_entry2 *cpuid_entries;
2265 int limit, nent = 0, r = -E2BIG;
2266 u32 func;
2267
2268 if (cpuid->nent < 1)
2269 goto out;
6a544355
AK		 2270 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2271 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2272 r = -ENOMEM;
2273 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2274 if (!cpuid_entries)
2275 goto out;
2276
2277 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2278 limit = cpuid_entries[0].eax;
2279 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2280 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2281 &nent, cpuid->nent);
07716717
DK		 2282 r = -E2BIG;
2283 if (nent >= cpuid->nent)
2284 goto out_free;
2285
2286 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2287 limit = cpuid_entries[nent - 1].eax;
2288 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2289 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2290 &nent, cpuid->nent);
84478c82
GC		 2291
2292
2293
2294 r = -E2BIG;
2295 if (nent >= cpuid->nent)
2296 goto out_free;
2297
2298 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2299 cpuid->nent);
2300
2301 r = -E2BIG;
2302 if (nent >= cpuid->nent)
2303 goto out_free;
2304
2305 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2306 cpuid->nent);
2307
cb007648
MM		 2308 r = -E2BIG;
2309 if (nent >= cpuid->nent)
2310 goto out_free;
2311
07716717
DK		 2312 r = -EFAULT;
2313 if (copy_to_user(entries, cpuid_entries,
19355475 2314 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2315 goto out_free;
2316 cpuid->nent = nent;
2317 r = 0;
2318
2319out_free:
2320 vfree(cpuid_entries);
2321out:
2322 return r;
2323}
2324
313a3dc7
CO		 2325static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2326 struct kvm_lapic_state *s)
2327{
ad312c7c 2328 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2329
2330 return 0;
2331}
2332
2333static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2334 struct kvm_lapic_state *s)
2335{
ad312c7c 2336 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2337 kvm_apic_post_state_restore(vcpu);
cb142eb7 2338 update_cr8_intercept(vcpu);
313a3dc7
CO		 2339
2340 return 0;
2341}
2342
f77bc6a4
ZX		 2343static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2344 struct kvm_interrupt *irq)
2345{
2346 if (irq->irq < 0 || irq->irq >= 256)
2347 return -EINVAL;
2348 if (irqchip_in_kernel(vcpu->kvm))
2349 return -ENXIO;
f77bc6a4 2350
66fd3f7f 2351 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4 2352
f77bc6a4
ZX		 2353 return 0;
2354}
2355
c4abb7c9
JK		 2356static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2357{
c4abb7c9 2358 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2359
2360 return 0;
2361}
2362
b209749f
AK		 2363static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2364 struct kvm_tpr_access_ctl *tac)
2365{
2366 if (tac->flags)
2367 return -EINVAL;
2368 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2369 return 0;
2370}
2371
890ca9ae
HY		 2372static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2373 u64 mcg_cap)
2374{
2375 int r;
2376 unsigned bank_num = mcg_cap & 0xff, bank;
2377
2378 r = -EINVAL;
a9e38c3e 2379 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2380 goto out;
2381 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2382 goto out;
2383 r = 0;
2384 vcpu->arch.mcg_cap = mcg_cap;
2385 /* Init IA32_MCG_CTL to all 1s */
2386 if (mcg_cap & MCG_CTL_P)
2387 vcpu->arch.mcg_ctl = ~(u64)0;
2388 /* Init IA32_MCi_CTL to all 1s */
2389 for (bank = 0; bank < bank_num; bank++)
2390 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2391out:
2392 return r;
2393}
2394
2395static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2396 struct kvm_x86_mce *mce)
2397{
2398 u64 mcg_cap = vcpu->arch.mcg_cap;
2399 unsigned bank_num = mcg_cap & 0xff;
2400 u64 *banks = vcpu->arch.mce_banks;
2401
2402 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2403 return -EINVAL;
2404 /*
2405 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2406 * reporting is disabled
2407 */
2408 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2409 vcpu->arch.mcg_ctl != ~(u64)0)
2410 return 0;
2411 banks += 4 * mce->bank;
2412 /*
2413 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2414 * reporting is disabled for the bank
2415 */
2416 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2417 return 0;
2418 if (mce->status & MCI_STATUS_UC) {
2419 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2420 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2421 printk(KERN_DEBUG "kvm: set_mce: "
2422 "injects mce exception while "
2423 "previous one is in progress!\n");
a8eeb04a 2424 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2425 return 0;
2426 }
2427 if (banks[1] & MCI_STATUS_VAL)
2428 mce->status |= MCI_STATUS_OVER;
2429 banks[2] = mce->addr;
2430 banks[3] = mce->misc;
2431 vcpu->arch.mcg_status = mce->mcg_status;
2432 banks[1] = mce->status;
2433 kvm_queue_exception(vcpu, MC_VECTOR);
2434 } else if (!(banks[1] & MCI_STATUS_VAL)
2435 || !(banks[1] & MCI_STATUS_UC)) {
2436 if (banks[1] & MCI_STATUS_VAL)
2437 mce->status |= MCI_STATUS_OVER;
2438 banks[2] = mce->addr;
2439 banks[3] = mce->misc;
2440 banks[1] = mce->status;
2441 } else
2442 banks[1] |= MCI_STATUS_OVER;
2443 return 0;
2444}
2445
3cfc3092
JK		 2446static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2447 struct kvm_vcpu_events *events)
2448{
03b82a30
JK		 2449 events->exception.injected =
2450 vcpu->arch.exception.pending &&
2451 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2452 events->exception.nr = vcpu->arch.exception.nr;
2453 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2454 events->exception.error_code = vcpu->arch.exception.error_code;
2455
03b82a30
JK		 2456 events->interrupt.injected =
2457 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2458 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2459 events->interrupt.soft = 0;
48005f64
JK		 2460 events->interrupt.shadow =
2461 kvm_x86_ops->get_interrupt_shadow(vcpu,
2462 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2463
2464 events->nmi.injected = vcpu->arch.nmi_injected;
2465 events->nmi.pending = vcpu->arch.nmi_pending;
2466 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2467
2468 events->sipi_vector = vcpu->arch.sipi_vector;
2469
dab4b911 2470 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2471 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2472 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2473}
2474
2475static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2476 struct kvm_vcpu_events *events)
2477{
dab4b911 2478 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2479 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2480 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2481 return -EINVAL;
2482
3cfc3092
JK		 2483 vcpu->arch.exception.pending = events->exception.injected;
2484 vcpu->arch.exception.nr = events->exception.nr;
2485 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2486 vcpu->arch.exception.error_code = events->exception.error_code;
2487
2488 vcpu->arch.interrupt.pending = events->interrupt.injected;
2489 vcpu->arch.interrupt.nr = events->interrupt.nr;
2490 vcpu->arch.interrupt.soft = events->interrupt.soft;
2491 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2492 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2493 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2494 kvm_x86_ops->set_interrupt_shadow(vcpu,
2495 events->interrupt.shadow);
3cfc3092
JK		 2496
2497 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2498 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2499 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2500 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2501
dab4b911
JK		 2502 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2503 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2504
3cfc3092
JK		 2505 return 0;
2506}
2507
a1efbe77
JK		 2508static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2509 struct kvm_debugregs *dbgregs)
2510{
a1efbe77
JK		 2511 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2512 dbgregs->dr6 = vcpu->arch.dr6;
2513 dbgregs->dr7 = vcpu->arch.dr7;
2514 dbgregs->flags = 0;
a1efbe77
JK		 2515}
2516
2517static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2518 struct kvm_debugregs *dbgregs)
2519{
2520 if (dbgregs->flags)
2521 return -EINVAL;
2522
a1efbe77
JK		 2523 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2524 vcpu->arch.dr6 = dbgregs->dr6;
2525 vcpu->arch.dr7 = dbgregs->dr7;
2526
a1efbe77
JK		 2527 return 0;
2528}
2529
2d5b5a66
SY		 2530static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2531 struct kvm_xsave *guest_xsave)
2532{
2533 if (cpu_has_xsave)
2534 memcpy(guest_xsave->region,
2535 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2536 xstate_size);
2d5b5a66
SY		 2537 else {
2538 memcpy(guest_xsave->region,
2539 &vcpu->arch.guest_fpu.state->fxsave,
2540 sizeof(struct i387_fxsave_struct));
2541 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2542 XSTATE_FPSSE;
2543 }
2544}
2545
2546static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2547 struct kvm_xsave *guest_xsave)
2548{
2549 u64 xstate_bv =
2550 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2551
2552 if (cpu_has_xsave)
2553 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2554 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2555 else {
2556 if (xstate_bv & ~XSTATE_FPSSE)
2557 return -EINVAL;
2558 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2559 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2560 }
2561 return 0;
2562}
2563
2564static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2565 struct kvm_xcrs *guest_xcrs)
2566{
2567 if (!cpu_has_xsave) {
2568 guest_xcrs->nr_xcrs = 0;
2569 return;
2570 }
2571
2572 guest_xcrs->nr_xcrs = 1;
2573 guest_xcrs->flags = 0;
2574 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2575 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2576}
2577
2578static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2579 struct kvm_xcrs *guest_xcrs)
2580{
2581 int i, r = 0;
2582
2583 if (!cpu_has_xsave)
2584 return -EINVAL;
2585
2586 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2587 return -EINVAL;
2588
2589 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2590 /* Only support XCR0 currently */
2591 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2592 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2593 guest_xcrs->xcrs[0].value);
2594 break;
2595 }
2596 if (r)
2597 r = -EINVAL;
2598 return r;
2599}
2600
313a3dc7
CO		 2601long kvm_arch_vcpu_ioctl(struct file *filp,
2602 unsigned int ioctl, unsigned long arg)
2603{
2604 struct kvm_vcpu *vcpu = filp->private_data;
2605 void __user *argp = (void __user *)arg;
2606 int r;
d1ac91d8
AK		 2607 union {
2608 struct kvm_lapic_state *lapic;
2609 struct kvm_xsave *xsave;
2610 struct kvm_xcrs *xcrs;
2611 void *buffer;
2612 } u;
2613
2614 u.buffer = NULL;
313a3dc7
CO		 2615 switch (ioctl) {
2616 case KVM_GET_LAPIC: {
2204ae3c
MT		 2617 r = -EINVAL;
2618 if (!vcpu->arch.apic)
2619 goto out;
d1ac91d8 2620 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2621
b772ff36 2622 r = -ENOMEM;
d1ac91d8 2623 if (!u.lapic)
b772ff36 2624 goto out;
d1ac91d8 2625 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2626 if (r)
2627 goto out;
2628 r = -EFAULT;
d1ac91d8 2629 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2630 goto out;
2631 r = 0;
2632 break;
2633 }
2634 case KVM_SET_LAPIC: {
2204ae3c
MT		 2635 r = -EINVAL;
2636 if (!vcpu->arch.apic)
2637 goto out;
d1ac91d8 2638 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2639 r = -ENOMEM;
d1ac91d8 2640 if (!u.lapic)
b772ff36 2641 goto out;
313a3dc7 2642 r = -EFAULT;
d1ac91d8 2643 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2644 goto out;
d1ac91d8 2645 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2646 if (r)
2647 goto out;
2648 r = 0;
2649 break;
2650 }
f77bc6a4
ZX		 2651 case KVM_INTERRUPT: {
2652 struct kvm_interrupt irq;
2653
2654 r = -EFAULT;
2655 if (copy_from_user(&irq, argp, sizeof irq))
2656 goto out;
2657 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2658 if (r)
2659 goto out;
2660 r = 0;
2661 break;
2662 }
c4abb7c9
JK		 2663 case KVM_NMI: {
2664 r = kvm_vcpu_ioctl_nmi(vcpu);
2665 if (r)
2666 goto out;
2667 r = 0;
2668 break;
2669 }
313a3dc7
CO		 2670 case KVM_SET_CPUID: {
2671 struct kvm_cpuid __user *cpuid_arg = argp;
2672 struct kvm_cpuid cpuid;
2673
2674 r = -EFAULT;
2675 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2676 goto out;
2677 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2678 if (r)
2679 goto out;
2680 break;
2681 }
07716717
DK		 2682 case KVM_SET_CPUID2: {
2683 struct kvm_cpuid2 __user *cpuid_arg = argp;
2684 struct kvm_cpuid2 cpuid;
2685
2686 r = -EFAULT;
2687 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2688 goto out;
2689 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2690 cpuid_arg->entries);
07716717
DK		 2691 if (r)
2692 goto out;
2693 break;
2694 }
2695 case KVM_GET_CPUID2: {
2696 struct kvm_cpuid2 __user *cpuid_arg = argp;
2697 struct kvm_cpuid2 cpuid;
2698
2699 r = -EFAULT;
2700 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2701 goto out;
2702 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2703 cpuid_arg->entries);
07716717
DK		 2704 if (r)
2705 goto out;
2706 r = -EFAULT;
2707 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2708 goto out;
2709 r = 0;
2710 break;
2711 }
313a3dc7
CO		 2712 case KVM_GET_MSRS:
2713 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2714 break;
2715 case KVM_SET_MSRS:
2716 r = msr_io(vcpu, argp, do_set_msr, 0);
2717 break;
b209749f
AK		 2718 case KVM_TPR_ACCESS_REPORTING: {
2719 struct kvm_tpr_access_ctl tac;
2720
2721 r = -EFAULT;
2722 if (copy_from_user(&tac, argp, sizeof tac))
2723 goto out;
2724 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2725 if (r)
2726 goto out;
2727 r = -EFAULT;
2728 if (copy_to_user(argp, &tac, sizeof tac))
2729 goto out;
2730 r = 0;
2731 break;
2732 };
b93463aa
AK		 2733 case KVM_SET_VAPIC_ADDR: {
2734 struct kvm_vapic_addr va;
2735
2736 r = -EINVAL;
2737 if (!irqchip_in_kernel(vcpu->kvm))
2738 goto out;
2739 r = -EFAULT;
2740 if (copy_from_user(&va, argp, sizeof va))
2741 goto out;
2742 r = 0;
2743 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2744 break;
2745 }
890ca9ae
HY		 2746 case KVM_X86_SETUP_MCE: {
2747 u64 mcg_cap;
2748
2749 r = -EFAULT;
2750 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2751 goto out;
2752 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2753 break;
2754 }
2755 case KVM_X86_SET_MCE: {
2756 struct kvm_x86_mce mce;
2757
2758 r = -EFAULT;
2759 if (copy_from_user(&mce, argp, sizeof mce))
2760 goto out;
2761 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2762 break;
2763 }
3cfc3092
JK		 2764 case KVM_GET_VCPU_EVENTS: {
2765 struct kvm_vcpu_events events;
2766
2767 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2768
2769 r = -EFAULT;
2770 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2771 break;
2772 r = 0;
2773 break;
2774 }
2775 case KVM_SET_VCPU_EVENTS: {
2776 struct kvm_vcpu_events events;
2777
2778 r = -EFAULT;
2779 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2780 break;
2781
2782 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2783 break;
2784 }
a1efbe77
JK		 2785 case KVM_GET_DEBUGREGS: {
2786 struct kvm_debugregs dbgregs;
2787
2788 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2789
2790 r = -EFAULT;
2791 if (copy_to_user(argp, &dbgregs,
2792 sizeof(struct kvm_debugregs)))
2793 break;
2794 r = 0;
2795 break;
2796 }
2797 case KVM_SET_DEBUGREGS: {
2798 struct kvm_debugregs dbgregs;
2799
2800 r = -EFAULT;
2801 if (copy_from_user(&dbgregs, argp,
2802 sizeof(struct kvm_debugregs)))
2803 break;
2804
2805 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2806 break;
2807 }
2d5b5a66 2808 case KVM_GET_XSAVE: {
d1ac91d8 2809 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2810 r = -ENOMEM;
d1ac91d8 2811 if (!u.xsave)
2d5b5a66
SY		 2812 break;
2813
d1ac91d8 2814 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2815
2816 r = -EFAULT;
d1ac91d8 2817 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2818 break;
2819 r = 0;
2820 break;
2821 }
2822 case KVM_SET_XSAVE: {
d1ac91d8 2823 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2824 r = -ENOMEM;
d1ac91d8 2825 if (!u.xsave)
2d5b5a66
SY		 2826 break;
2827
2828 r = -EFAULT;
d1ac91d8 2829 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2830 break;
2831
d1ac91d8 2832 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2833 break;
2834 }
2835 case KVM_GET_XCRS: {
d1ac91d8 2836 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2837 r = -ENOMEM;
d1ac91d8 2838 if (!u.xcrs)
2d5b5a66
SY		 2839 break;
2840
d1ac91d8 2841 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2842
2843 r = -EFAULT;
d1ac91d8 2844 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2845 sizeof(struct kvm_xcrs)))
2846 break;
2847 r = 0;
2848 break;
2849 }
2850 case KVM_SET_XCRS: {
d1ac91d8 2851 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2852 r = -ENOMEM;
d1ac91d8 2853 if (!u.xcrs)
2d5b5a66
SY		 2854 break;
2855
2856 r = -EFAULT;
d1ac91d8 2857 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2858 sizeof(struct kvm_xcrs)))
2859 break;
2860
d1ac91d8 2861 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2862 break;
2863 }
313a3dc7
CO		 2864 default:
2865 r = -EINVAL;
2866 }
2867out:
d1ac91d8 2868 kfree(u.buffer);
313a3dc7
CO		 2869 return r;
2870}
2871
1fe779f8
CO		 2872static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2873{
2874 int ret;
2875
2876 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2877 return -1;
2878 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2879 return ret;
2880}
2881
b927a3ce
SY		 2882static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2883 u64 ident_addr)
2884{
2885 kvm->arch.ept_identity_map_addr = ident_addr;
2886 return 0;
2887}
2888
1fe779f8
CO		 2889static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2890 u32 kvm_nr_mmu_pages)
2891{
2892 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2893 return -EINVAL;
2894
79fac95e 2895 mutex_lock(&kvm->slots_lock);
7c8a83b7 2896 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2897
2898 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2899 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2900
7c8a83b7 2901 spin_unlock(&kvm->mmu_lock);
79fac95e 2902 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2903 return 0;
2904}
2905
2906static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2907{
39de71ec 2908 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2909}
2910
1fe779f8
CO		 2911static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2912{
2913 int r;
2914
2915 r = 0;
2916 switch (chip->chip_id) {
2917 case KVM_IRQCHIP_PIC_MASTER:
2918 memcpy(&chip->chip.pic,
2919 &pic_irqchip(kvm)->pics[0],
2920 sizeof(struct kvm_pic_state));
2921 break;
2922 case KVM_IRQCHIP_PIC_SLAVE:
2923 memcpy(&chip->chip.pic,
2924 &pic_irqchip(kvm)->pics[1],
2925 sizeof(struct kvm_pic_state));
2926 break;
2927 case KVM_IRQCHIP_IOAPIC:
eba0226b 2928 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2929 break;
2930 default:
2931 r = -EINVAL;
2932 break;
2933 }
2934 return r;
2935}
2936
2937static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2938{
2939 int r;
2940
2941 r = 0;
2942 switch (chip->chip_id) {
2943 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2944 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2945 memcpy(&pic_irqchip(kvm)->pics[0],
2946 &chip->chip.pic,
2947 sizeof(struct kvm_pic_state));
fa8273e9 2948 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2949 break;
2950 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2951 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2952 memcpy(&pic_irqchip(kvm)->pics[1],
2953 &chip->chip.pic,
2954 sizeof(struct kvm_pic_state));
fa8273e9 2955 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2956 break;
2957 case KVM_IRQCHIP_IOAPIC:
eba0226b 2958 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2959 break;
2960 default:
2961 r = -EINVAL;
2962 break;
2963 }
2964 kvm_pic_update_irq(pic_irqchip(kvm));
2965 return r;
2966}
2967
e0f63cb9
SY		 2968static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2969{
2970 int r = 0;
2971
894a9c55 2972 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2973 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2974 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2975 return r;
2976}
2977
2978static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2979{
2980 int r = 0;
2981
894a9c55 2982 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2983 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2984 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2985 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2986 return r;
2987}
2988
2989static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2990{
2991 int r = 0;
2992
2993 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2994 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2995 sizeof(ps->channels));
2996 ps->flags = kvm->arch.vpit->pit_state.flags;
2997 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2998 return r;
2999}
3000
3001static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3002{
3003 int r = 0, start = 0;
3004 u32 prev_legacy, cur_legacy;
3005 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3006 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3007 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3008 if (!prev_legacy && cur_legacy)
3009 start = 1;
3010 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3011 sizeof(kvm->arch.vpit->pit_state.channels));
3012 kvm->arch.vpit->pit_state.flags = ps->flags;
3013 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3014 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3015 return r;
3016}
3017
52d939a0
MT		 3018static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3019 struct kvm_reinject_control *control)
3020{
3021 if (!kvm->arch.vpit)
3022 return -ENXIO;
894a9c55 3023 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3024 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3025 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3026 return 0;
3027}
3028
5bb064dc
ZX		 3029/*
3030 * Get (and clear) the dirty memory log for a memory slot.
3031 */
3032int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3033 struct kvm_dirty_log *log)
3034{
87bf6e7d 3035 int r, i;
5bb064dc 3036 struct kvm_memory_slot *memslot;
87bf6e7d 3037 unsigned long n;
b050b015 3038 unsigned long is_dirty = 0;
5bb064dc 3039
79fac95e 3040 mutex_lock(&kvm->slots_lock);
5bb064dc 3041
b050b015
MT		 3042 r = -EINVAL;
3043 if (log->slot >= KVM_MEMORY_SLOTS)
3044 goto out;
3045
3046 memslot = &kvm->memslots->memslots[log->slot];
3047 r = -ENOENT;
3048 if (!memslot->dirty_bitmap)
3049 goto out;
3050
87bf6e7d 3051 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3052
b050b015
MT		 3053 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3054 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3055
3056 /* If nothing is dirty, don't bother messing with page tables. */
3057 if (is_dirty) {
b050b015 3058 struct kvm_memslots *slots, *old_slots;
914ebccd 3059 unsigned long *dirty_bitmap;
b050b015 3060
7c8a83b7 3061 spin_lock(&kvm->mmu_lock);
5bb064dc 3062 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 3063 spin_unlock(&kvm->mmu_lock);
b050b015 3064
914ebccd
TY		 3065 r = -ENOMEM;
3066 dirty_bitmap = vmalloc(n);
3067 if (!dirty_bitmap)
3068 goto out;
3069 memset(dirty_bitmap, 0, n);
b050b015 3070
914ebccd
TY		 3071 r = -ENOMEM;
3072 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3073 if (!slots) {
3074 vfree(dirty_bitmap);
3075 goto out;
3076 }
b050b015
MT		 3077 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3078 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3079
3080 old_slots = kvm->memslots;
3081 rcu_assign_pointer(kvm->memslots, slots);
3082 synchronize_srcu_expedited(&kvm->srcu);
3083 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3084 kfree(old_slots);
914ebccd
TY		 3085
3086 r = -EFAULT;
3087 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3088 vfree(dirty_bitmap);
3089 goto out;
3090 }
3091 vfree(dirty_bitmap);
3092 } else {
3093 r = -EFAULT;
3094 if (clear_user(log->dirty_bitmap, n))
3095 goto out;
5bb064dc 3096 }
b050b015 3097
5bb064dc
ZX		 3098 r = 0;
3099out:
79fac95e 3100 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3101 return r;
3102}
3103
1fe779f8
CO		 3104long kvm_arch_vm_ioctl(struct file *filp,
3105 unsigned int ioctl, unsigned long arg)
3106{
3107 struct kvm *kvm = filp->private_data;
3108 void __user *argp = (void __user *)arg;
367e1319 3109 int r = -ENOTTY;
f0d66275
DH		 3110 /*
3111 * This union makes it completely explicit to gcc-3.x
3112 * that these two variables' stack usage should be
3113 * combined, not added together.
3114 */
3115 union {
3116 struct kvm_pit_state ps;
e9f42757 3117 struct kvm_pit_state2 ps2;
c5ff41ce 3118 struct kvm_pit_config pit_config;
f0d66275 3119 } u;
1fe779f8
CO		 3120
3121 switch (ioctl) {
3122 case KVM_SET_TSS_ADDR:
3123 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3124 if (r < 0)
3125 goto out;
3126 break;
b927a3ce
SY		 3127 case KVM_SET_IDENTITY_MAP_ADDR: {
3128 u64 ident_addr;
3129
3130 r = -EFAULT;
3131 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3132 goto out;
3133 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3134 if (r < 0)
3135 goto out;
3136 break;
3137 }
1fe779f8
CO		 3138 case KVM_SET_NR_MMU_PAGES:
3139 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3140 if (r)
3141 goto out;
3142 break;
3143 case KVM_GET_NR_MMU_PAGES:
3144 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3145 break;
3ddea128
MT		 3146 case KVM_CREATE_IRQCHIP: {
3147 struct kvm_pic *vpic;
3148
3149 mutex_lock(&kvm->lock);
3150 r = -EEXIST;
3151 if (kvm->arch.vpic)
3152 goto create_irqchip_unlock;
1fe779f8 3153 r = -ENOMEM;
3ddea128
MT		 3154 vpic = kvm_create_pic(kvm);
3155 if (vpic) {
1fe779f8
CO		 3156 r = kvm_ioapic_init(kvm);
3157 if (r) {
72bb2fcd
WY		 3158 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3159 &vpic->dev);
3ddea128
MT		 3160 kfree(vpic);
3161 goto create_irqchip_unlock;
1fe779f8
CO		 3162 }
3163 } else
3ddea128
MT		 3164 goto create_irqchip_unlock;
3165 smp_wmb();
3166 kvm->arch.vpic = vpic;
3167 smp_wmb();
399ec807
AK		 3168 r = kvm_setup_default_irq_routing(kvm);
3169 if (r) {
3ddea128 3170 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3171 kvm_ioapic_destroy(kvm);
3172 kvm_destroy_pic(kvm);
3ddea128 3173 mutex_unlock(&kvm->irq_lock);
399ec807 3174 }
3ddea128
MT		 3175 create_irqchip_unlock:
3176 mutex_unlock(&kvm->lock);
1fe779f8 3177 break;
3ddea128 3178 }
7837699f 3179 case KVM_CREATE_PIT:
c5ff41ce
JK		 3180 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3181 goto create_pit;
3182 case KVM_CREATE_PIT2:
3183 r = -EFAULT;
3184 if (copy_from_user(&u.pit_config, argp,
3185 sizeof(struct kvm_pit_config)))
3186 goto out;
3187 create_pit:
79fac95e 3188 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3189 r = -EEXIST;
3190 if (kvm->arch.vpit)
3191 goto create_pit_unlock;
7837699f 3192 r = -ENOMEM;
c5ff41ce 3193 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3194 if (kvm->arch.vpit)
3195 r = 0;
269e05e4 3196 create_pit_unlock:
79fac95e 3197 mutex_unlock(&kvm->slots_lock);
7837699f 3198 break;
4925663a 3199 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3200 case KVM_IRQ_LINE: {
3201 struct kvm_irq_level irq_event;
3202
3203 r = -EFAULT;
3204 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3205 goto out;
160d2f6c 3206 r = -ENXIO;
1fe779f8 3207 if (irqchip_in_kernel(kvm)) {
4925663a 3208 __s32 status;
4925663a
GN		 3209 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3210 irq_event.irq, irq_event.level);
4925663a 3211 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3212 r = -EFAULT;
4925663a
GN		 3213 irq_event.status = status;
3214 if (copy_to_user(argp, &irq_event,
3215 sizeof irq_event))
3216 goto out;
3217 }
1fe779f8
CO		 3218 r = 0;
3219 }
3220 break;
3221 }
3222 case KVM_GET_IRQCHIP: {
3223 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3224 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3225
f0d66275
DH		 3226 r = -ENOMEM;
3227 if (!chip)
1fe779f8 3228 goto out;
f0d66275
DH		 3229 r = -EFAULT;
3230 if (copy_from_user(chip, argp, sizeof *chip))
3231 goto get_irqchip_out;
1fe779f8
CO		 3232 r = -ENXIO;
3233 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3234 goto get_irqchip_out;
3235 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3236 if (r)
f0d66275 3237 goto get_irqchip_out;
1fe779f8 3238 r = -EFAULT;
f0d66275
DH		 3239 if (copy_to_user(argp, chip, sizeof *chip))
3240 goto get_irqchip_out;
1fe779f8 3241 r = 0;
f0d66275
DH		 3242 get_irqchip_out:
3243 kfree(chip);
3244 if (r)
3245 goto out;
1fe779f8
CO		 3246 break;
3247 }
3248 case KVM_SET_IRQCHIP: {
3249 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3250 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3251
f0d66275
DH		 3252 r = -ENOMEM;
3253 if (!chip)
1fe779f8 3254 goto out;
f0d66275
DH		 3255 r = -EFAULT;
3256 if (copy_from_user(chip, argp, sizeof *chip))
3257 goto set_irqchip_out;
1fe779f8
CO		 3258 r = -ENXIO;
3259 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3260 goto set_irqchip_out;
3261 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3262 if (r)
f0d66275 3263 goto set_irqchip_out;
1fe779f8 3264 r = 0;
f0d66275
DH		 3265 set_irqchip_out:
3266 kfree(chip);
3267 if (r)
3268 goto out;
1fe779f8
CO		 3269 break;
3270 }
e0f63cb9 3271 case KVM_GET_PIT: {
e0f63cb9 3272 r = -EFAULT;
f0d66275 3273 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3274 goto out;
3275 r = -ENXIO;
3276 if (!kvm->arch.vpit)
3277 goto out;
f0d66275 3278 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3279 if (r)
3280 goto out;
3281 r = -EFAULT;
f0d66275 3282 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3283 goto out;
3284 r = 0;
3285 break;
3286 }
3287 case KVM_SET_PIT: {
e0f63cb9 3288 r = -EFAULT;
f0d66275 3289 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3290 goto out;
3291 r = -ENXIO;
3292 if (!kvm->arch.vpit)
3293 goto out;
f0d66275 3294 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3295 if (r)
3296 goto out;
3297 r = 0;
3298 break;
3299 }
e9f42757
BK		 3300 case KVM_GET_PIT2: {
3301 r = -ENXIO;
3302 if (!kvm->arch.vpit)
3303 goto out;
3304 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3305 if (r)
3306 goto out;
3307 r = -EFAULT;
3308 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3309 goto out;
3310 r = 0;
3311 break;
3312 }
3313 case KVM_SET_PIT2: {
3314 r = -EFAULT;
3315 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3316 goto out;
3317 r = -ENXIO;
3318 if (!kvm->arch.vpit)
3319 goto out;
3320 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3321 if (r)
3322 goto out;
3323 r = 0;
3324 break;
3325 }
52d939a0
MT		 3326 case KVM_REINJECT_CONTROL: {
3327 struct kvm_reinject_control control;
3328 r = -EFAULT;
3329 if (copy_from_user(&control, argp, sizeof(control)))
3330 goto out;
3331 r = kvm_vm_ioctl_reinject(kvm, &control);
3332 if (r)
3333 goto out;
3334 r = 0;
3335 break;
3336 }
ffde22ac
ES		 3337 case KVM_XEN_HVM_CONFIG: {
3338 r = -EFAULT;
3339 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3340 sizeof(struct kvm_xen_hvm_config)))
3341 goto out;
3342 r = -EINVAL;
3343 if (kvm->arch.xen_hvm_config.flags)
3344 goto out;
3345 r = 0;
3346 break;
3347 }
afbcf7ab 3348 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3349 struct kvm_clock_data user_ns;
3350 u64 now_ns;
3351 s64 delta;
3352
3353 r = -EFAULT;
3354 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3355 goto out;
3356
3357 r = -EINVAL;
3358 if (user_ns.flags)
3359 goto out;
3360
3361 r = 0;
759379dd 3362 now_ns = get_kernel_ns();
afbcf7ab
GC		 3363 delta = user_ns.clock - now_ns;
3364 kvm->arch.kvmclock_offset = delta;
3365 break;
3366 }
3367 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3368 struct kvm_clock_data user_ns;
3369 u64 now_ns;
3370
759379dd 3371 now_ns = get_kernel_ns();
afbcf7ab
GC		 3372 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3373 user_ns.flags = 0;
3374
3375 r = -EFAULT;
3376 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3377 goto out;
3378 r = 0;
3379 break;
3380 }
3381
1fe779f8
CO		 3382 default:
3383 ;
3384 }
3385out:
3386 return r;
3387}
3388
a16b043c 3389static void kvm_init_msr_list(void)
043405e1
CO		 3390{
3391 u32 dummy[2];
3392 unsigned i, j;
3393
e3267cbb
GC		 3394 /* skip the first msrs in the list. KVM-specific */
3395 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3396 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3397 continue;
3398 if (j < i)
3399 msrs_to_save[j] = msrs_to_save[i];
3400 j++;
3401 }
3402 num_msrs_to_save = j;
3403}
3404
bda9020e
MT		 3405static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3406 const void *v)
bbd9b64e 3407{
bda9020e
MT		 3408 if (vcpu->arch.apic &&
3409 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3410 return 0;
bbd9b64e 3411
e93f8a0f 3412 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3413}
3414
bda9020e 3415static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3416{
bda9020e
MT		 3417 if (vcpu->arch.apic &&
3418 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3419 return 0;
bbd9b64e 3420
e93f8a0f 3421 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3422}
3423
2dafc6c2
GN		 3424static void kvm_set_segment(struct kvm_vcpu *vcpu,
3425 struct kvm_segment *var, int seg)
3426{
3427 kvm_x86_ops->set_segment(vcpu, var, seg);
3428}
3429
3430void kvm_get_segment(struct kvm_vcpu *vcpu,
3431 struct kvm_segment *var, int seg)
3432{
3433 kvm_x86_ops->get_segment(vcpu, var, seg);
3434}
3435
1871c602
GN		 3436gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3437{
3438 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3439 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3440}
3441
3442 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3443{
3444 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3445 access |= PFERR_FETCH_MASK;
3446 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3447}
3448
3449gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3450{
3451 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3452 access |= PFERR_WRITE_MASK;
3453 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3454}
3455
3456/* uses this to access any guest's mapped memory without checking CPL */
3457gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3458{
3459 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3460}
3461
3462static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3463 struct kvm_vcpu *vcpu, u32 access,
3464 u32 *error)
bbd9b64e
CO		 3465{
3466 void *data = val;
10589a46 3467 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3468
3469 while (bytes) {
1871c602 3470 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3471 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3472 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3473 int ret;
3474
10589a46
MT		 3475 if (gpa == UNMAPPED_GVA) {
3476 r = X86EMUL_PROPAGATE_FAULT;
3477 goto out;
3478 }
77c2002e 3479 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3480 if (ret < 0) {
c3cd7ffa 3481 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3482 goto out;
3483 }
bbd9b64e 3484
77c2002e
IE		 3485 bytes -= toread;
3486 data += toread;
3487 addr += toread;
bbd9b64e 3488 }
10589a46 3489out:
10589a46 3490 return r;
bbd9b64e 3491}
77c2002e 3492
1871c602
GN		 3493/* used for instruction fetching */
3494static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3495 struct kvm_vcpu *vcpu, u32 *error)
3496{
3497 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3498 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3499 access | PFERR_FETCH_MASK, error);
3500}
3501
3502static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3503 struct kvm_vcpu *vcpu, u32 *error)
3504{
3505 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3506 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3507 error);
3508}
3509
3510static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3511 struct kvm_vcpu *vcpu, u32 *error)
3512{
3513 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3514}
3515
7972995b 3516static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3517 unsigned int bytes,
7972995b 3518 struct kvm_vcpu *vcpu,
2dafc6c2 3519 u32 *error)
77c2002e
IE		 3520{
3521 void *data = val;
3522 int r = X86EMUL_CONTINUE;
3523
3524 while (bytes) {
7972995b
GN		 3525 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3526 PFERR_WRITE_MASK, error);
77c2002e
IE		 3527 unsigned offset = addr & (PAGE_SIZE-1);
3528 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3529 int ret;
3530
3531 if (gpa == UNMAPPED_GVA) {
3532 r = X86EMUL_PROPAGATE_FAULT;
3533 goto out;
3534 }
3535 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3536 if (ret < 0) {
c3cd7ffa 3537 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3538 goto out;
3539 }
3540
3541 bytes -= towrite;
3542 data += towrite;
3543 addr += towrite;
3544 }
3545out:
3546 return r;
3547}
3548
bbd9b64e
CO		 3549static int emulator_read_emulated(unsigned long addr,
3550 void *val,
3551 unsigned int bytes,
8fe681e9 3552 unsigned int *error_code,
bbd9b64e
CO		 3553 struct kvm_vcpu *vcpu)
3554{
bbd9b64e
CO		 3555 gpa_t gpa;
3556
3557 if (vcpu->mmio_read_completed) {
3558 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3559 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3560 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3561 vcpu->mmio_read_completed = 0;
3562 return X86EMUL_CONTINUE;
3563 }
3564
8fe681e9 3565 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3566
8fe681e9 3567 if (gpa == UNMAPPED_GVA)
1871c602 3568 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3569
3570 /* For APIC access vmexit */
3571 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3572 goto mmio;
3573
1871c602 3574 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3575 == X86EMUL_CONTINUE)
bbd9b64e 3576 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3577
3578mmio:
3579 /*
3580 * Is this MMIO handled locally?
3581 */
aec51dc4
AK		 3582 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3583 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3584 return X86EMUL_CONTINUE;
3585 }
aec51dc4
AK		 3586
3587 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3588
3589 vcpu->mmio_needed = 1;
411c35b7
GN		 3590 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3591 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3592 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3593 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3594
c3cd7ffa 3595 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3596}
3597
3200f405 3598int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3599 const void *val, int bytes)
bbd9b64e
CO		 3600{
3601 int ret;
3602
3603 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3604 if (ret < 0)
bbd9b64e 3605 return 0;
ad218f85 3606 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3607 return 1;
3608}
3609
3610static int emulator_write_emulated_onepage(unsigned long addr,
3611 const void *val,
3612 unsigned int bytes,
8fe681e9 3613 unsigned int *error_code,
bbd9b64e
CO		 3614 struct kvm_vcpu *vcpu)
3615{
10589a46
MT		 3616 gpa_t gpa;
3617
8fe681e9 3618 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3619
8fe681e9 3620 if (gpa == UNMAPPED_GVA)
bbd9b64e 3621 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3622
3623 /* For APIC access vmexit */
3624 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3625 goto mmio;
3626
3627 if (emulator_write_phys(vcpu, gpa, val, bytes))
3628 return X86EMUL_CONTINUE;
3629
3630mmio:
aec51dc4 3631 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3632 /*
3633 * Is this MMIO handled locally?
3634 */
bda9020e 3635 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3636 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3637
3638 vcpu->mmio_needed = 1;
411c35b7
GN		 3639 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3640 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3641 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3642 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3643 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3644
3645 return X86EMUL_CONTINUE;
3646}
3647
3648int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3649 const void *val,
3650 unsigned int bytes,
8fe681e9 3651 unsigned int *error_code,
8f6abd06 3652 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3653{
3654 /* Crossing a page boundary? */
3655 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3656 int rc, now;
3657
3658 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3659 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3660 vcpu);
bbd9b64e
CO		 3661 if (rc != X86EMUL_CONTINUE)
3662 return rc;
3663 addr += now;
3664 val += now;
3665 bytes -= now;
3666 }
8fe681e9
GN		 3667 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3668 vcpu);
bbd9b64e 3669}
bbd9b64e 3670
daea3e73
AK		 3671#define CMPXCHG_TYPE(t, ptr, old, new) \
3672 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3673
3674#ifdef CONFIG_X86_64
3675# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3676#else
3677# define CMPXCHG64(ptr, old, new) \
9749a6c0 3678 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3679#endif
3680
bbd9b64e
CO		 3681static int emulator_cmpxchg_emulated(unsigned long addr,
3682 const void *old,
3683 const void *new,
3684 unsigned int bytes,
8fe681e9 3685 unsigned int *error_code,
bbd9b64e
CO		 3686 struct kvm_vcpu *vcpu)
3687{
daea3e73
AK		 3688 gpa_t gpa;
3689 struct page *page;
3690 char *kaddr;
3691 bool exchanged;
2bacc55c 3692
daea3e73
AK		 3693 /* guests cmpxchg8b have to be emulated atomically */
3694 if (bytes > 8 || (bytes & (bytes - 1)))
3695 goto emul_write;
10589a46 3696
daea3e73 3697 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3698
daea3e73
AK		 3699 if (gpa == UNMAPPED_GVA ||
3700 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3701 goto emul_write;
2bacc55c 3702
daea3e73
AK		 3703 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3704 goto emul_write;
72dc67a6 3705
daea3e73 3706 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3707 if (is_error_page(page)) {
3708 kvm_release_page_clean(page);
3709 goto emul_write;
3710 }
72dc67a6 3711
daea3e73
AK		 3712 kaddr = kmap_atomic(page, KM_USER0);
3713 kaddr += offset_in_page(gpa);
3714 switch (bytes) {
3715 case 1:
3716 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3717 break;
3718 case 2:
3719 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3720 break;
3721 case 4:
3722 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3723 break;
3724 case 8:
3725 exchanged = CMPXCHG64(kaddr, old, new);
3726 break;
3727 default:
3728 BUG();
2bacc55c 3729 }
daea3e73
AK		 3730 kunmap_atomic(kaddr, KM_USER0);
3731 kvm_release_page_dirty(page);
3732
3733 if (!exchanged)
3734 return X86EMUL_CMPXCHG_FAILED;
3735
8f6abd06
GN		 3736 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3737
3738 return X86EMUL_CONTINUE;
4a5f48f6 3739
3200f405 3740emul_write:
daea3e73 3741 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3742
8fe681e9 3743 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3744}
3745
cf8f70bf
GN		 3746static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3747{
3748 /* TODO: String I/O for in kernel device */
3749 int r;
3750
3751 if (vcpu->arch.pio.in)
3752 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3753 vcpu->arch.pio.size, pd);
3754 else
3755 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3756 vcpu->arch.pio.port, vcpu->arch.pio.size,
3757 pd);
3758 return r;
3759}
3760
3761
3762static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3763 unsigned int count, struct kvm_vcpu *vcpu)
3764{
7972995b 3765 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3766 goto data_avail;
3767
c41a15dd 3768 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3769
3770 vcpu->arch.pio.port = port;
3771 vcpu->arch.pio.in = 1;
7972995b 3772 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3773 vcpu->arch.pio.size = size;
3774
3775 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3776 data_avail:
3777 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3778 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3779 return 1;
3780 }
3781
3782 vcpu->run->exit_reason = KVM_EXIT_IO;
3783 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3784 vcpu->run->io.size = size;
3785 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3786 vcpu->run->io.count = count;
3787 vcpu->run->io.port = port;
3788
3789 return 0;
3790}
3791
3792static int emulator_pio_out_emulated(int size, unsigned short port,
3793 const void *val, unsigned int count,
3794 struct kvm_vcpu *vcpu)
3795{
c41a15dd 3796 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3797
3798 vcpu->arch.pio.port = port;
3799 vcpu->arch.pio.in = 0;
7972995b 3800 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3801 vcpu->arch.pio.size = size;
3802
3803 memcpy(vcpu->arch.pio_data, val, size * count);
3804
3805 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3806 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3807 return 1;
3808 }
3809
3810 vcpu->run->exit_reason = KVM_EXIT_IO;
3811 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3812 vcpu->run->io.size = size;
3813 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3814 vcpu->run->io.count = count;
3815 vcpu->run->io.port = port;
3816
3817 return 0;
3818}
3819
bbd9b64e
CO		 3820static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3821{
3822 return kvm_x86_ops->get_segment_base(vcpu, seg);
3823}
3824
3825int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3826{
a7052897 3827 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3828 return X86EMUL_CONTINUE;
3829}
3830
f5f48ee1
SY		 3831int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3832{
3833 if (!need_emulate_wbinvd(vcpu))
3834 return X86EMUL_CONTINUE;
3835
3836 if (kvm_x86_ops->has_wbinvd_exit()) {
3837 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3838 wbinvd_ipi, NULL, 1);
3839 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3840 }
3841 wbinvd();
3842 return X86EMUL_CONTINUE;
3843}
3844EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3845
bbd9b64e
CO		 3846int emulate_clts(struct kvm_vcpu *vcpu)
3847{
4d4ec087 3848 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3849 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3850 return X86EMUL_CONTINUE;
3851}
3852
35aa5375 3853int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3854{
338dbc97 3855 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3856}
3857
35aa5375 3858int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3859{
338dbc97
GN		 3860
3861 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3862}
3863
52a46617 3864static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3865{
52a46617 3866 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3867}
3868
52a46617 3869static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3870{
52a46617
GN		 3871 unsigned long value;
3872
3873 switch (cr) {
3874 case 0:
3875 value = kvm_read_cr0(vcpu);
3876 break;
3877 case 2:
3878 value = vcpu->arch.cr2;
3879 break;
3880 case 3:
3881 value = vcpu->arch.cr3;
3882 break;
3883 case 4:
3884 value = kvm_read_cr4(vcpu);
3885 break;
3886 case 8:
3887 value = kvm_get_cr8(vcpu);
3888 break;
3889 default:
3890 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3891 return 0;
3892 }
3893
3894 return value;
3895}
3896
0f12244f 3897static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3898{
0f12244f
GN		 3899 int res = 0;
3900
52a46617
GN		 3901 switch (cr) {
3902 case 0:
49a9b07e 3903 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3904 break;
3905 case 2:
3906 vcpu->arch.cr2 = val;
3907 break;
3908 case 3:
2390218b 3909 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 3910 break;
3911 case 4:
a83b29c6 3912 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 3913 break;
3914 case 8:
0f12244f 3915 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 3916 break;
3917 default:
3918 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 3919 res = -1;
52a46617 3920 }
0f12244f
GN		 3921
3922 return res;
52a46617
GN		 3923}
3924
9c537244
GN		 3925static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3926{
3927 return kvm_x86_ops->get_cpl(vcpu);
3928}
3929
2dafc6c2
GN		 3930static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3931{
3932 kvm_x86_ops->get_gdt(vcpu, dt);
3933}
3934
160ce1f1
MG		 3935static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3936{
3937 kvm_x86_ops->get_idt(vcpu, dt);
3938}
3939
5951c442
GN		 3940static unsigned long emulator_get_cached_segment_base(int seg,
3941 struct kvm_vcpu *vcpu)
3942{
3943 return get_segment_base(vcpu, seg);
3944}
3945
2dafc6c2
GN		 3946static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3947 struct kvm_vcpu *vcpu)
3948{
3949 struct kvm_segment var;
3950
3951 kvm_get_segment(vcpu, &var, seg);
3952
3953 if (var.unusable)
3954 return false;
3955
3956 if (var.g)
3957 var.limit >>= 12;
3958 set_desc_limit(desc, var.limit);
3959 set_desc_base(desc, (unsigned long)var.base);
3960 desc->type = var.type;
3961 desc->s = var.s;
3962 desc->dpl = var.dpl;
3963 desc->p = var.present;
3964 desc->avl = var.avl;
3965 desc->l = var.l;
3966 desc->d = var.db;
3967 desc->g = var.g;
3968
3969 return true;
3970}
3971
3972static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3973 struct kvm_vcpu *vcpu)
3974{
3975 struct kvm_segment var;
3976
3977 /* needed to preserve selector */
3978 kvm_get_segment(vcpu, &var, seg);
3979
3980 var.base = get_desc_base(desc);
3981 var.limit = get_desc_limit(desc);
3982 if (desc->g)
3983 var.limit = (var.limit << 12) | 0xfff;
3984 var.type = desc->type;
3985 var.present = desc->p;
3986 var.dpl = desc->dpl;
3987 var.db = desc->d;
3988 var.s = desc->s;
3989 var.l = desc->l;
3990 var.g = desc->g;
3991 var.avl = desc->avl;
3992 var.present = desc->p;
3993 var.unusable = !var.present;
3994 var.padding = 0;
3995
3996 kvm_set_segment(vcpu, &var, seg);
3997 return;
3998}
3999
4000static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4001{
4002 struct kvm_segment kvm_seg;
4003
4004 kvm_get_segment(vcpu, &kvm_seg, seg);
4005 return kvm_seg.selector;
4006}
4007
4008static void emulator_set_segment_selector(u16 sel, int seg,
4009 struct kvm_vcpu *vcpu)
4010{
4011 struct kvm_segment kvm_seg;
4012
4013 kvm_get_segment(vcpu, &kvm_seg, seg);
4014 kvm_seg.selector = sel;
4015 kvm_set_segment(vcpu, &kvm_seg, seg);
4016}
4017
14af3f3c 4018static struct x86_emulate_ops emulate_ops = {
1871c602 4019 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4020 .write_std = kvm_write_guest_virt_system,
1871c602 4021 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4022 .read_emulated = emulator_read_emulated,
4023 .write_emulated = emulator_write_emulated,
4024 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4025 .pio_in_emulated = emulator_pio_in_emulated,
4026 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4027 .get_cached_descriptor = emulator_get_cached_descriptor,
4028 .set_cached_descriptor = emulator_set_cached_descriptor,
4029 .get_segment_selector = emulator_get_segment_selector,
4030 .set_segment_selector = emulator_set_segment_selector,
5951c442 4031 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4032 .get_gdt = emulator_get_gdt,
160ce1f1 4033 .get_idt = emulator_get_idt,
52a46617
GN		 4034 .get_cr = emulator_get_cr,
4035 .set_cr = emulator_set_cr,
9c537244 4036 .cpl = emulator_get_cpl,
35aa5375
GN		 4037 .get_dr = emulator_get_dr,
4038 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4039 .set_msr = kvm_set_msr,
4040 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4041};
4042
5fdbf976
MT		 4043static void cache_all_regs(struct kvm_vcpu *vcpu)
4044{
4045 kvm_register_read(vcpu, VCPU_REGS_RAX);
4046 kvm_register_read(vcpu, VCPU_REGS_RSP);
4047 kvm_register_read(vcpu, VCPU_REGS_RIP);
4048 vcpu->arch.regs_dirty = ~0;
4049}
4050
95cb2295
GN		 4051static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4052{
4053 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4054 /*
4055 * an sti; sti; sequence only disable interrupts for the first
4056 * instruction. So, if the last instruction, be it emulated or
4057 * not, left the system with the INT_STI flag enabled, it
4058 * means that the last instruction is an sti. We should not
4059 * leave the flag on in this case. The same goes for mov ss
4060 */
4061 if (!(int_shadow & mask))
4062 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4063}
4064
54b8486f
GN		 4065static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4066{
4067 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4068 if (ctxt->exception == PF_VECTOR)
4069 kvm_inject_page_fault(vcpu, ctxt->cr2, ctxt->error_code);
4070 else if (ctxt->error_code_valid)
4071 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4072 else
4073 kvm_queue_exception(vcpu, ctxt->exception);
4074}
4075
8ec4722d
MG		 4076static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4077{
4078 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4079 int cs_db, cs_l;
4080
4081 cache_all_regs(vcpu);
4082
4083 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4084
4085 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4086 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4087 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4088 vcpu->arch.emulate_ctxt.mode =
4089 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4090 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4091 ? X86EMUL_MODE_VM86 : cs_l
4092 ? X86EMUL_MODE_PROT64 : cs_db
4093 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4094 memset(c, 0, sizeof(struct decode_cache));
4095 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4096}
4097
6d77dbfc
GN		 4098static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4099{
6d77dbfc
GN		 4100 ++vcpu->stat.insn_emulation_fail;
4101 trace_kvm_emulate_insn_failed(vcpu);
4102 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4103 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4104 vcpu->run->internal.ndata = 0;
4105 kvm_queue_exception(vcpu, UD_VECTOR);
4106 return EMULATE_FAIL;
4107}
4108
a6f177ef
GN		 4109static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4110{
4111 gpa_t gpa;
4112
68be0803
GN		 4113 if (tdp_enabled)
4114 return false;
4115
a6f177ef
GN		 4116 /*
4117 * if emulation was due to access to shadowed page table
4118 * and it failed try to unshadow page and re-entetr the
4119 * guest to let CPU execute the instruction.
4120 */
4121 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4122 return true;
4123
4124 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4125
4126 if (gpa == UNMAPPED_GVA)
4127 return true; /* let cpu generate fault */
4128
4129 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4130 return true;
4131
4132 return false;
4133}
4134
bbd9b64e 4135int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4136 unsigned long cr2,
4137 u16 error_code,
571008da 4138 int emulation_type)
bbd9b64e 4139{
95cb2295 4140 int r;
4d2179e1 4141 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4142
26eef70c 4143 kvm_clear_exception_queue(vcpu);
ad312c7c 4144 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4145 /*
56e82318 4146 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4147 * instead of direct ->regs accesses, can save hundred cycles
4148 * on Intel for instructions that don't read/change RSP, for
4149 * for example.
4150 */
4151 cache_all_regs(vcpu);
bbd9b64e 4152
571008da 4153 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4154 init_emulate_ctxt(vcpu);
95cb2295 4155 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4156 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4157 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4158
9aabc88f 4159 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
e46479f8 4160 trace_kvm_emulate_insn_start(vcpu);
571008da 4161
0cb5762e
AP		 4162 /* Only allow emulation of specific instructions on #UD
4163 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4164 if (emulation_type & EMULTYPE_TRAP_UD) {
4165 if (!c->twobyte)
4166 return EMULATE_FAIL;
4167 switch (c->b) {
4168 case 0x01: /* VMMCALL */
4169 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4170 return EMULATE_FAIL;
4171 break;
4172 case 0x34: /* sysenter */
4173 case 0x35: /* sysexit */
4174 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4175 return EMULATE_FAIL;
4176 break;
4177 case 0x05: /* syscall */
4178 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4179 return EMULATE_FAIL;
4180 break;
4181 default:
4182 return EMULATE_FAIL;
4183 }
4184
4185 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4186 return EMULATE_FAIL;
4187 }
571008da 4188
f2b5756b 4189 ++vcpu->stat.insn_emulation;
bbd9b64e 4190 if (r) {
a6f177ef 4191 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4192 return EMULATE_DONE;
6d77dbfc
GN		 4193 if (emulation_type & EMULTYPE_SKIP)
4194 return EMULATE_FAIL;
4195 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4196 }
4197 }
4198
ba8afb6b
GN		 4199 if (emulation_type & EMULTYPE_SKIP) {
4200 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4201 return EMULATE_DONE;
4202 }
4203
4d2179e1
GN		 4204 /* this is needed for vmware backdor interface to work since it
4205 changes registers values during IO operation */
4206 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4207
5cd21917 4208restart:
9aabc88f 4209 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4210
d2ddd1c4 4211 if (r == EMULATION_FAILED) {
a6f177ef 4212 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4213 return EMULATE_DONE;
4214
6d77dbfc 4215 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4216 }
4217
d2ddd1c4 4218 if (vcpu->arch.emulate_ctxt.exception >= 0) {
54b8486f 4219 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4220 r = EMULATE_DONE;
4221 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4222 if (!vcpu->arch.pio.in)
4223 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4224 r = EMULATE_DO_MMIO;
4225 } else if (vcpu->mmio_needed) {
3457e419
GN		 4226 if (vcpu->mmio_is_write)
4227 vcpu->mmio_needed = 0;
e85d28f8 4228 r = EMULATE_DO_MMIO;
d2ddd1c4 4229 } else if (r == EMULATION_RESTART)
5cd21917 4230 goto restart;
d2ddd1c4
GN		 4231 else
4232 r = EMULATE_DONE;
f850e2e6 4233
e85d28f8
GN		 4234 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4235 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4236 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4237 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4238
4239 return r;
de7d789a 4240}
bbd9b64e 4241EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4242
cf8f70bf 4243int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4244{
cf8f70bf
GN		 4245 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4246 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4247 /* do not return to emulator after return from userspace */
7972995b 4248 vcpu->arch.pio.count = 0;
de7d789a
CO		 4249 return ret;
4250}
cf8f70bf 4251EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4252
8cfdc000
ZA		 4253static void tsc_bad(void *info)
4254{
4255 __get_cpu_var(cpu_tsc_khz) = 0;
4256}
4257
4258static void tsc_khz_changed(void *data)
c8076604 4259{
8cfdc000
ZA		 4260 struct cpufreq_freqs *freq = data;
4261 unsigned long khz = 0;
4262
4263 if (data)
4264 khz = freq->new;
4265 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4266 khz = cpufreq_quick_get(raw_smp_processor_id());
4267 if (!khz)
4268 khz = tsc_khz;
4269 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4270}
4271
c8076604
GH		 4272static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4273 void *data)
4274{
4275 struct cpufreq_freqs *freq = data;
4276 struct kvm *kvm;
4277 struct kvm_vcpu *vcpu;
4278 int i, send_ipi = 0;
4279
8cfdc000
ZA		 4280 /*
4281 * We allow guests to temporarily run on slowing clocks,
4282 * provided we notify them after, or to run on accelerating
4283 * clocks, provided we notify them before. Thus time never
4284 * goes backwards.
4285 *
4286 * However, we have a problem. We can't atomically update
4287 * the frequency of a given CPU from this function; it is
4288 * merely a notifier, which can be called from any CPU.
4289 * Changing the TSC frequency at arbitrary points in time
4290 * requires a recomputation of local variables related to
4291 * the TSC for each VCPU. We must flag these local variables
4292 * to be updated and be sure the update takes place with the
4293 * new frequency before any guests proceed.
4294 *
4295 * Unfortunately, the combination of hotplug CPU and frequency
4296 * change creates an intractable locking scenario; the order
4297 * of when these callouts happen is undefined with respect to
4298 * CPU hotplug, and they can race with each other. As such,
4299 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4300 * undefined; you can actually have a CPU frequency change take
4301 * place in between the computation of X and the setting of the
4302 * variable. To protect against this problem, all updates of
4303 * the per_cpu tsc_khz variable are done in an interrupt
4304 * protected IPI, and all callers wishing to update the value
4305 * must wait for a synchronous IPI to complete (which is trivial
4306 * if the caller is on the CPU already). This establishes the
4307 * necessary total order on variable updates.
4308 *
4309 * Note that because a guest time update may take place
4310 * anytime after the setting of the VCPU's request bit, the
4311 * correct TSC value must be set before the request. However,
4312 * to ensure the update actually makes it to any guest which
4313 * starts running in hardware virtualization between the set
4314 * and the acquisition of the spinlock, we must also ping the
4315 * CPU after setting the request bit.
4316 *
4317 */
4318
c8076604
GH		 4319 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4320 return 0;
4321 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4322 return 0;
8cfdc000
ZA		 4323
4324 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4325
4326 spin_lock(&kvm_lock);
4327 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4328 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4329 if (vcpu->cpu != freq->cpu)
4330 continue;
4331 if (!kvm_request_guest_time_update(vcpu))
4332 continue;
4333 if (vcpu->cpu != smp_processor_id())
8cfdc000 4334 send_ipi = 1;
c8076604
GH		 4335 }
4336 }
4337 spin_unlock(&kvm_lock);
4338
4339 if (freq->old < freq->new && send_ipi) {
4340 /*
4341 * We upscale the frequency. Must make the guest
4342 * doesn't see old kvmclock values while running with
4343 * the new frequency, otherwise we risk the guest sees
4344 * time go backwards.
4345 *
4346 * In case we update the frequency for another cpu
4347 * (which might be in guest context) send an interrupt
4348 * to kick the cpu out of guest context. Next time
4349 * guest context is entered kvmclock will be updated,
4350 * so the guest will not see stale values.
4351 */
8cfdc000 4352 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4353 }
4354 return 0;
4355}
4356
4357static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4358 .notifier_call = kvmclock_cpufreq_notifier
4359};
4360
4361static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4362 unsigned long action, void *hcpu)
4363{
4364 unsigned int cpu = (unsigned long)hcpu;
4365
4366 switch (action) {
4367 case CPU_ONLINE:
4368 case CPU_DOWN_FAILED:
4369 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4370 break;
4371 case CPU_DOWN_PREPARE:
4372 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4373 break;
4374 }
4375 return NOTIFY_OK;
4376}
4377
4378static struct notifier_block kvmclock_cpu_notifier_block = {
4379 .notifier_call = kvmclock_cpu_notifier,
4380 .priority = -INT_MAX
c8076604
GH		 4381};
4382
b820cc0c
ZA		 4383static void kvm_timer_init(void)
4384{
4385 int cpu;
4386
8cfdc000 4387 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4388 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4389 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4390 CPUFREQ_TRANSITION_NOTIFIER);
4391 }
8cfdc000
ZA		 4392 for_each_online_cpu(cpu)
4393 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4394}
4395
ff9d07a0
ZY		 4396static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4397
4398static int kvm_is_in_guest(void)
4399{
4400 return percpu_read(current_vcpu) != NULL;
4401}
4402
4403static int kvm_is_user_mode(void)
4404{
4405 int user_mode = 3;
dcf46b94 4406
ff9d07a0
ZY		 4407 if (percpu_read(current_vcpu))
4408 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4409
ff9d07a0
ZY		 4410 return user_mode != 0;
4411}
4412
4413static unsigned long kvm_get_guest_ip(void)
4414{
4415 unsigned long ip = 0;
dcf46b94 4416
ff9d07a0
ZY		 4417 if (percpu_read(current_vcpu))
4418 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4419
ff9d07a0
ZY		 4420 return ip;
4421}
4422
4423static struct perf_guest_info_callbacks kvm_guest_cbs = {
4424 .is_in_guest = kvm_is_in_guest,
4425 .is_user_mode = kvm_is_user_mode,
4426 .get_guest_ip = kvm_get_guest_ip,
4427};
4428
4429void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4430{
4431 percpu_write(current_vcpu, vcpu);
4432}
4433EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4434
4435void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4436{
4437 percpu_write(current_vcpu, NULL);
4438}
4439EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4440
f8c16bba 4441int kvm_arch_init(void *opaque)
043405e1 4442{
b820cc0c 4443 int r;
f8c16bba
ZX		 4444 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4445
f8c16bba
ZX		 4446 if (kvm_x86_ops) {
4447 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4448 r = -EEXIST;
4449 goto out;
f8c16bba
ZX		 4450 }
4451
4452 if (!ops->cpu_has_kvm_support()) {
4453 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4454 r = -EOPNOTSUPP;
4455 goto out;
f8c16bba
ZX		 4456 }
4457 if (ops->disabled_by_bios()) {
4458 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4459 r = -EOPNOTSUPP;
4460 goto out;
f8c16bba
ZX		 4461 }
4462
97db56ce
AK		 4463 r = kvm_mmu_module_init();
4464 if (r)
4465 goto out;
4466
4467 kvm_init_msr_list();
4468
f8c16bba 4469 kvm_x86_ops = ops;
56c6d28a 4470 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4471 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4472 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4473 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4474
b820cc0c 4475 kvm_timer_init();
c8076604 4476
ff9d07a0
ZY		 4477 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4478
2acf923e
DC		 4479 if (cpu_has_xsave)
4480 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4481
f8c16bba 4482 return 0;
56c6d28a
ZX		 4483
4484out:
56c6d28a 4485 return r;
043405e1 4486}
8776e519 4487
f8c16bba
ZX		 4488void kvm_arch_exit(void)
4489{
ff9d07a0
ZY		 4490 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4491
888d256e
JK		 4492 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4493 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4494 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4495 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4496 kvm_x86_ops = NULL;
56c6d28a
ZX		 4497 kvm_mmu_module_exit();
4498}
f8c16bba 4499
8776e519
HB		 4500int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4501{
4502 ++vcpu->stat.halt_exits;
4503 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4504 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4505 return 1;
4506 } else {
4507 vcpu->run->exit_reason = KVM_EXIT_HLT;
4508 return 0;
4509 }
4510}
4511EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4512
2f333bcb
MT		 4513static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4514 unsigned long a1)
4515{
4516 if (is_long_mode(vcpu))
4517 return a0;
4518 else
4519 return a0 | ((gpa_t)a1 << 32);
4520}
4521
55cd8e5a
GN		 4522int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4523{
4524 u64 param, ingpa, outgpa, ret;
4525 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4526 bool fast, longmode;
4527 int cs_db, cs_l;
4528
4529 /*
4530 * hypercall generates UD from non zero cpl and real mode
4531 * per HYPER-V spec
4532 */
3eeb3288 4533 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4534 kvm_queue_exception(vcpu, UD_VECTOR);
4535 return 0;
4536 }
4537
4538 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4539 longmode = is_long_mode(vcpu) && cs_l == 1;
4540
4541 if (!longmode) {
ccd46936
GN		 4542 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4543 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4544 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4545 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4546 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4547 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4548 }
4549#ifdef CONFIG_X86_64
4550 else {
4551 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4552 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4553 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4554 }
4555#endif
4556
4557 code = param & 0xffff;
4558 fast = (param >> 16) & 0x1;
4559 rep_cnt = (param >> 32) & 0xfff;
4560 rep_idx = (param >> 48) & 0xfff;
4561
4562 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4563
c25bc163
GN		 4564 switch (code) {
4565 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4566 kvm_vcpu_on_spin(vcpu);
4567 break;
4568 default:
4569 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4570 break;
4571 }
55cd8e5a
GN		 4572
4573 ret = res | (((u64)rep_done & 0xfff) << 32);
4574 if (longmode) {
4575 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4576 } else {
4577 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4578 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4579 }
4580
4581 return 1;
4582}
4583
8776e519
HB		 4584int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4585{
4586 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4587 int r = 1;
8776e519 4588
55cd8e5a
GN		 4589 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4590 return kvm_hv_hypercall(vcpu);
4591
5fdbf976
MT		 4592 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4593 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4594 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4595 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4596 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4597
229456fc 4598 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4599
8776e519
HB		 4600 if (!is_long_mode(vcpu)) {
4601 nr &= 0xFFFFFFFF;
4602 a0 &= 0xFFFFFFFF;
4603 a1 &= 0xFFFFFFFF;
4604 a2 &= 0xFFFFFFFF;
4605 a3 &= 0xFFFFFFFF;
4606 }
4607
07708c4a
JK		 4608 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4609 ret = -KVM_EPERM;
4610 goto out;
4611 }
4612
8776e519 4613 switch (nr) {
b93463aa
AK		 4614 case KVM_HC_VAPIC_POLL_IRQ:
4615 ret = 0;
4616 break;
2f333bcb
MT		 4617 case KVM_HC_MMU_OP:
4618 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4619 break;
8776e519
HB		 4620 default:
4621 ret = -KVM_ENOSYS;
4622 break;
4623 }
07708c4a 4624out:
5fdbf976 4625 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4626 ++vcpu->stat.hypercalls;
2f333bcb 4627 return r;
8776e519
HB		 4628}
4629EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4630
4631int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4632{
4633 char instruction[3];
5fdbf976 4634 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4635
8776e519
HB		 4636 /*
4637 * Blow out the MMU to ensure that no other VCPU has an active mapping
4638 * to ensure that the updated hypercall appears atomically across all
4639 * VCPUs.
4640 */
4641 kvm_mmu_zap_all(vcpu->kvm);
4642
8776e519 4643 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4644
8fe681e9 4645 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4646}
4647
8776e519
HB		 4648void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4649{
89a27f4d 4650 struct desc_ptr dt = { limit, base };
8776e519
HB		 4651
4652 kvm_x86_ops->set_gdt(vcpu, &dt);
4653}
4654
4655void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4656{
89a27f4d 4657 struct desc_ptr dt = { limit, base };
8776e519
HB		 4658
4659 kvm_x86_ops->set_idt(vcpu, &dt);
4660}
4661
07716717
DK		 4662static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4663{
ad312c7c
ZX		 4664 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4665 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4666
4667 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4668 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4669 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4670 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4671 if (ej->function == e->function) {
4672 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4673 return j;
4674 }
4675 }
4676 return 0; /* silence gcc, even though control never reaches here */
4677}
4678
4679/* find an entry with matching function, matching index (if needed), and that
4680 * should be read next (if it's stateful) */
4681static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4682 u32 function, u32 index)
4683{
4684 if (e->function != function)
4685 return 0;
4686 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4687 return 0;
4688 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4689 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4690 return 0;
4691 return 1;
4692}
4693
d8017474
AG		 4694struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4695 u32 function, u32 index)
8776e519
HB		 4696{
4697 int i;
d8017474 4698 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4699
ad312c7c 4700 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4701 struct kvm_cpuid_entry2 *e;
4702
ad312c7c 4703 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4704 if (is_matching_cpuid_entry(e, function, index)) {
4705 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4706 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4707 best = e;
4708 break;
4709 }
4710 /*
4711 * Both basic or both extended?
4712 */
4713 if (((e->function ^ function) & 0x80000000) == 0)
4714 if (!best || e->function > best->function)
4715 best = e;
4716 }
d8017474
AG		 4717 return best;
4718}
0e851880 4719EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4720
82725b20
DE		 4721int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4722{
4723 struct kvm_cpuid_entry2 *best;
4724
f7a71197
AK		 4725 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4726 if (!best || best->eax < 0x80000008)
4727 goto not_found;
82725b20
DE		 4728 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4729 if (best)
4730 return best->eax & 0xff;
f7a71197 4731not_found:
82725b20
DE		 4732 return 36;
4733}
4734
d8017474
AG		 4735void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4736{
4737 u32 function, index;
4738 struct kvm_cpuid_entry2 *best;
4739
4740 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4741 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4742 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4743 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4744 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4745 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4746 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4747 if (best) {
5fdbf976
MT		 4748 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4749 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4750 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4751 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4752 }
8776e519 4753 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4754 trace_kvm_cpuid(function,
4755 kvm_register_read(vcpu, VCPU_REGS_RAX),
4756 kvm_register_read(vcpu, VCPU_REGS_RBX),
4757 kvm_register_read(vcpu, VCPU_REGS_RCX),
4758 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4759}
4760EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4761
b6c7a5dc
HB		 4762/*
4763 * Check if userspace requested an interrupt window, and that the
4764 * interrupt window is open.
4765 *
4766 * No need to exit to userspace if we already have an interrupt queued.
4767 */
851ba692 4768static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4769{
8061823a 4770 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4771 vcpu->run->request_interrupt_window &&
5df56646 4772 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4773}
4774
851ba692 4775static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4776{
851ba692
AK		 4777 struct kvm_run *kvm_run = vcpu->run;
4778
91586a3b 4779 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4780 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4781 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4782 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4783 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4784 else
b6c7a5dc 4785 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4786 kvm_arch_interrupt_allowed(vcpu) &&
4787 !kvm_cpu_has_interrupt(vcpu) &&
4788 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4789}
4790
b93463aa
AK		 4791static void vapic_enter(struct kvm_vcpu *vcpu)
4792{
4793 struct kvm_lapic *apic = vcpu->arch.apic;
4794 struct page *page;
4795
4796 if (!apic || !apic->vapic_addr)
4797 return;
4798
4799 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4800
4801 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4802}
4803
4804static void vapic_exit(struct kvm_vcpu *vcpu)
4805{
4806 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4807 int idx;
b93463aa
AK		 4808
4809 if (!apic || !apic->vapic_addr)
4810 return;
4811
f656ce01 4812 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4813 kvm_release_page_dirty(apic->vapic_page);
4814 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4815 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4816}
4817
95ba8273
GN		 4818static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4819{
4820 int max_irr, tpr;
4821
4822 if (!kvm_x86_ops->update_cr8_intercept)
4823 return;
4824
88c808fd
AK		 4825 if (!vcpu->arch.apic)
4826 return;
4827
8db3baa2
GN		 4828 if (!vcpu->arch.apic->vapic_addr)
4829 max_irr = kvm_lapic_find_highest_irr(vcpu);
4830 else
4831 max_irr = -1;
95ba8273
GN		 4832
4833 if (max_irr != -1)
4834 max_irr >>= 4;
4835
4836 tpr = kvm_lapic_get_cr8(vcpu);
4837
4838 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4839}
4840
851ba692 4841static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4842{
4843 /* try to reinject previous events if any */
b59bb7bd 4844 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4845 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4846 vcpu->arch.exception.has_error_code,
4847 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4848 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4849 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4850 vcpu->arch.exception.error_code,
4851 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4852 return;
4853 }
4854
95ba8273
GN		 4855 if (vcpu->arch.nmi_injected) {
4856 kvm_x86_ops->set_nmi(vcpu);
4857 return;
4858 }
4859
4860 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4861 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4862 return;
4863 }
4864
4865 /* try to inject new event if pending */
4866 if (vcpu->arch.nmi_pending) {
4867 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4868 vcpu->arch.nmi_pending = false;
4869 vcpu->arch.nmi_injected = true;
4870 kvm_x86_ops->set_nmi(vcpu);
4871 }
4872 } else if (kvm_cpu_has_interrupt(vcpu)) {
4873 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4874 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4875 false);
4876 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4877 }
4878 }
4879}
4880
2acf923e
DC		 4881static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
4882{
4883 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
4884 !vcpu->guest_xcr0_loaded) {
4885 /* kvm_set_xcr() also depends on this */
4886 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
4887 vcpu->guest_xcr0_loaded = 1;
4888 }
4889}
4890
4891static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
4892{
4893 if (vcpu->guest_xcr0_loaded) {
4894 if (vcpu->arch.xcr0 != host_xcr0)
4895 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
4896 vcpu->guest_xcr0_loaded = 0;
4897 }
4898}
4899
851ba692 4900static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4901{
4902 int r;
6a8b1d13 4903 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4904 vcpu->run->request_interrupt_window;
b6c7a5dc 4905
3e007509 4906 if (vcpu->requests) {
a8eeb04a 4907 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 4908 kvm_mmu_unload(vcpu);
a8eeb04a 4909 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 4910 __kvm_migrate_timers(vcpu);
8cfdc000
ZA		 4911 if (kvm_check_request(KVM_REQ_KVMCLOCK_UPDATE, vcpu)) {
4912 r = kvm_write_guest_time(vcpu);
4913 if (unlikely(r))
4914 goto out;
4915 }
a8eeb04a 4916 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 4917 kvm_mmu_sync_roots(vcpu);
a8eeb04a 4918 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 4919 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 4920 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 4921 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4922 r = 0;
4923 goto out;
4924 }
a8eeb04a 4925 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 4926 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4927 r = 0;
4928 goto out;
4929 }
a8eeb04a 4930 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 4931 vcpu->fpu_active = 0;
4932 kvm_x86_ops->fpu_deactivate(vcpu);
4933 }
2f52d58c 4934 }
b93463aa 4935
3e007509
AK		 4936 r = kvm_mmu_reload(vcpu);
4937 if (unlikely(r))
4938 goto out;
4939
b6c7a5dc
HB		 4940 preempt_disable();
4941
4942 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4943 if (vcpu->fpu_active)
4944 kvm_load_guest_fpu(vcpu);
2acf923e 4945 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 4946
d94e1dc9
AK		 4947 atomic_set(&vcpu->guest_mode, 1);
4948 smp_wmb();
b6c7a5dc 4949
d94e1dc9 4950 local_irq_disable();
32f88400 4951
d94e1dc9
AK		 4952 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
4953 || need_resched() || signal_pending(current)) {
4954 atomic_set(&vcpu->guest_mode, 0);
4955 smp_wmb();
6c142801
AK		 4956 local_irq_enable();
4957 preempt_enable();
4958 r = 1;
4959 goto out;
4960 }
4961
851ba692 4962 inject_pending_event(vcpu);
b6c7a5dc 4963
6a8b1d13
GN		 4964 /* enable NMI/IRQ window open exits if needed */
4965 if (vcpu->arch.nmi_pending)
4966 kvm_x86_ops->enable_nmi_window(vcpu);
4967 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4968 kvm_x86_ops->enable_irq_window(vcpu);
4969
95ba8273 4970 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4971 update_cr8_intercept(vcpu);
4972 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4973 }
b93463aa 4974
f656ce01 4975 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4976
b6c7a5dc
HB		 4977 kvm_guest_enter();
4978
42dbaa5a 4979 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4980 set_debugreg(0, 7);
4981 set_debugreg(vcpu->arch.eff_db[0], 0);
4982 set_debugreg(vcpu->arch.eff_db[1], 1);
4983 set_debugreg(vcpu->arch.eff_db[2], 2);
4984 set_debugreg(vcpu->arch.eff_db[3], 3);
4985 }
b6c7a5dc 4986
229456fc 4987 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4988 kvm_x86_ops->run(vcpu);
b6c7a5dc 4989
24f1e32c
FW		 4990 /*
4991 * If the guest has used debug registers, at least dr7
4992 * will be disabled while returning to the host.
4993 * If we don't have active breakpoints in the host, we don't
4994 * care about the messed up debug address registers. But if
4995 * we have some of them active, restore the old state.
4996 */
59d8eb53 4997 if (hw_breakpoint_active())
24f1e32c 4998 hw_breakpoint_restore();
42dbaa5a 4999
1d5f066e
ZA		 5000 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5001
d94e1dc9
AK		 5002 atomic_set(&vcpu->guest_mode, 0);
5003 smp_wmb();
b6c7a5dc
HB		 5004 local_irq_enable();
5005
5006 ++vcpu->stat.exits;
5007
5008 /*
5009 * We must have an instruction between local_irq_enable() and
5010 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5011 * the interrupt shadow. The stat.exits increment will do nicely.
5012 * But we need to prevent reordering, hence this barrier():
5013 */
5014 barrier();
5015
5016 kvm_guest_exit();
5017
5018 preempt_enable();
5019
f656ce01 5020 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5021
b6c7a5dc
HB		 5022 /*
5023 * Profile KVM exit RIPs:
5024 */
5025 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5026 unsigned long rip = kvm_rip_read(vcpu);
5027 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5028 }
5029
298101da 5030
b93463aa
AK		 5031 kvm_lapic_sync_from_vapic(vcpu);
5032
851ba692 5033 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5034out:
5035 return r;
5036}
b6c7a5dc 5037
09cec754 5038
851ba692 5039static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5040{
5041 int r;
f656ce01 5042 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5043
5044 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5045 pr_debug("vcpu %d received sipi with vector # %x\n",
5046 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5047 kvm_lapic_reset(vcpu);
5f179287 5048 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5049 if (r)
5050 return r;
5051 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5052 }
5053
f656ce01 5054 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5055 vapic_enter(vcpu);
5056
5057 r = 1;
5058 while (r > 0) {
af2152f5 5059 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 5060 r = vcpu_enter_guest(vcpu);
d7690175 5061 else {
f656ce01 5062 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5063 kvm_vcpu_block(vcpu);
f656ce01 5064 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5065 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5066 {
5067 switch(vcpu->arch.mp_state) {
5068 case KVM_MP_STATE_HALTED:
d7690175 5069 vcpu->arch.mp_state =
09cec754
GN		 5070 KVM_MP_STATE_RUNNABLE;
5071 case KVM_MP_STATE_RUNNABLE:
5072 break;
5073 case KVM_MP_STATE_SIPI_RECEIVED:
5074 default:
5075 r = -EINTR;
5076 break;
5077 }
5078 }
d7690175
MT		 5079 }
5080
09cec754
GN		 5081 if (r <= 0)
5082 break;
5083
5084 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5085 if (kvm_cpu_has_pending_timer(vcpu))
5086 kvm_inject_pending_timer_irqs(vcpu);
5087
851ba692 5088 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5089 r = -EINTR;
851ba692 5090 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5091 ++vcpu->stat.request_irq_exits;
5092 }
5093 if (signal_pending(current)) {
5094 r = -EINTR;
851ba692 5095 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5096 ++vcpu->stat.signal_exits;
5097 }
5098 if (need_resched()) {
f656ce01 5099 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5100 kvm_resched(vcpu);
f656ce01 5101 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5102 }
b6c7a5dc
HB		 5103 }
5104
f656ce01 5105 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5106
b93463aa
AK		 5107 vapic_exit(vcpu);
5108
b6c7a5dc
HB		 5109 return r;
5110}
5111
5112int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5113{
5114 int r;
5115 sigset_t sigsaved;
5116
ac9f6dc0
AK		 5117 if (vcpu->sigset_active)
5118 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5119
a4535290 5120 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5121 kvm_vcpu_block(vcpu);
d7690175 5122 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5123 r = -EAGAIN;
5124 goto out;
b6c7a5dc
HB		 5125 }
5126
b6c7a5dc
HB		 5127 /* re-sync apic's tpr */
5128 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5129 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5130
d2ddd1c4 5131 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5132 if (vcpu->mmio_needed) {
5133 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5134 vcpu->mmio_read_completed = 1;
5135 vcpu->mmio_needed = 0;
b6c7a5dc 5136 }
f656ce01 5137 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5138 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5139 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5140 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5141 r = 0;
5142 goto out;
5143 }
5144 }
5fdbf976
MT		 5145 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5146 kvm_register_write(vcpu, VCPU_REGS_RAX,
5147 kvm_run->hypercall.ret);
b6c7a5dc 5148
851ba692 5149 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5150
5151out:
f1d86e46 5152 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5153 if (vcpu->sigset_active)
5154 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5155
b6c7a5dc
HB		 5156 return r;
5157}
5158
5159int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5160{
5fdbf976
MT		 5161 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5162 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5163 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5164 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5165 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5166 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5167 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5168 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5169#ifdef CONFIG_X86_64
5fdbf976
MT		 5170 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5171 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5172 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5173 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5174 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5175 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5176 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5177 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5178#endif
5179
5fdbf976 5180 regs->rip = kvm_rip_read(vcpu);
91586a3b 5181 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5182
b6c7a5dc
HB		 5183 return 0;
5184}
5185
5186int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5187{
5fdbf976
MT		 5188 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5189 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5190 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5191 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5192 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5193 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5194 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5195 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5196#ifdef CONFIG_X86_64
5fdbf976
MT		 5197 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5198 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5199 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5200 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5201 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5202 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5203 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5204 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5205#endif
5206
5fdbf976 5207 kvm_rip_write(vcpu, regs->rip);
91586a3b 5208 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5209
b4f14abd
JK		 5210 vcpu->arch.exception.pending = false;
5211
b6c7a5dc
HB		 5212 return 0;
5213}
5214
b6c7a5dc
HB		 5215void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5216{
5217 struct kvm_segment cs;
5218
3e6e0aab 5219 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5220 *db = cs.db;
5221 *l = cs.l;
5222}
5223EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5224
5225int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5226 struct kvm_sregs *sregs)
5227{
89a27f4d 5228 struct desc_ptr dt;
b6c7a5dc 5229
3e6e0aab
GT		 5230 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5231 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5232 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5233 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5234 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5235 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5236
3e6e0aab
GT		 5237 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5238 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5239
5240 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5241 sregs->idt.limit = dt.size;
5242 sregs->idt.base = dt.address;
b6c7a5dc 5243 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5244 sregs->gdt.limit = dt.size;
5245 sregs->gdt.base = dt.address;
b6c7a5dc 5246
4d4ec087 5247 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5248 sregs->cr2 = vcpu->arch.cr2;
5249 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5250 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5251 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5252 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5253 sregs->apic_base = kvm_get_apic_base(vcpu);
5254
923c61bb 5255 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5256
36752c9b 5257 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5258 set_bit(vcpu->arch.interrupt.nr,
5259 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5260
b6c7a5dc
HB		 5261 return 0;
5262}
5263
62d9f0db
MT		 5264int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5265 struct kvm_mp_state *mp_state)
5266{
62d9f0db 5267 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5268 return 0;
5269}
5270
5271int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5272 struct kvm_mp_state *mp_state)
5273{
62d9f0db 5274 vcpu->arch.mp_state = mp_state->mp_state;
62d9f0db
MT		 5275 return 0;
5276}
5277
e269fb21
JK		 5278int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5279 bool has_error_code, u32 error_code)
b6c7a5dc 5280{
4d2179e1 5281 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5282 int ret;
e01c2426 5283
8ec4722d 5284 init_emulate_ctxt(vcpu);
c697518a 5285
9aabc88f 5286 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5287 tss_selector, reason, has_error_code,
5288 error_code);
c697518a 5289
c697518a 5290 if (ret)
19d04437 5291 return EMULATE_FAIL;
37817f29 5292
4d2179e1 5293 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5294 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437
GN		 5295 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
5296 return EMULATE_DONE;
37817f29
IE		 5297}
5298EXPORT_SYMBOL_GPL(kvm_task_switch);
5299
b6c7a5dc
HB		 5300int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5301 struct kvm_sregs *sregs)
5302{
5303 int mmu_reset_needed = 0;
923c61bb 5304 int pending_vec, max_bits;
89a27f4d 5305 struct desc_ptr dt;
b6c7a5dc 5306
89a27f4d
GN		 5307 dt.size = sregs->idt.limit;
5308 dt.address = sregs->idt.base;
b6c7a5dc 5309 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5310 dt.size = sregs->gdt.limit;
5311 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5312 kvm_x86_ops->set_gdt(vcpu, &dt);
5313
ad312c7c
ZX		 5314 vcpu->arch.cr2 = sregs->cr2;
5315 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5316 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5317
2d3ad1f4 5318 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5319
f6801dff 5320 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5321 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5322 kvm_set_apic_base(vcpu, sregs->apic_base);
5323
4d4ec087 5324 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5325 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5326 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5327
fc78f519 5328 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5329 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5330 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5331 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5332 mmu_reset_needed = 1;
5333 }
b6c7a5dc
HB		 5334
5335 if (mmu_reset_needed)
5336 kvm_mmu_reset_context(vcpu);
5337
923c61bb
GN		 5338 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5339 pending_vec = find_first_bit(
5340 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5341 if (pending_vec < max_bits) {
66fd3f7f 5342 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5343 pr_debug("Set back pending irq %d\n", pending_vec);
5344 if (irqchip_in_kernel(vcpu->kvm))
5345 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5346 }
5347
3e6e0aab
GT		 5348 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5349 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5350 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5351 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5352 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5353 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5354
3e6e0aab
GT		 5355 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5356 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5357
5f0269f5
ME		 5358 update_cr8_intercept(vcpu);
5359
9c3e4aab 5360 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5361 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5362 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5363 !is_protmode(vcpu))
9c3e4aab
MT		 5364 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5365
b6c7a5dc
HB		 5366 return 0;
5367}
5368
d0bfb940
JK		 5369int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5370 struct kvm_guest_debug *dbg)
b6c7a5dc 5371{
355be0b9 5372 unsigned long rflags;
ae675ef0 5373 int i, r;
b6c7a5dc 5374
4f926bf2
JK		 5375 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5376 r = -EBUSY;
5377 if (vcpu->arch.exception.pending)
2122ff5e 5378 goto out;
4f926bf2
JK		 5379 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5380 kvm_queue_exception(vcpu, DB_VECTOR);
5381 else
5382 kvm_queue_exception(vcpu, BP_VECTOR);
5383 }
5384
91586a3b
JK		 5385 /*
5386 * Read rflags as long as potentially injected trace flags are still
5387 * filtered out.
5388 */
5389 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5390
5391 vcpu->guest_debug = dbg->control;
5392 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5393 vcpu->guest_debug = 0;
5394
5395 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5396 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5397 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5398 vcpu->arch.switch_db_regs =
5399 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5400 } else {
5401 for (i = 0; i < KVM_NR_DB_REGS; i++)
5402 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5403 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5404 }
5405
f92653ee
JK		 5406 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5407 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5408 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5409
91586a3b
JK		 5410 /*
5411 * Trigger an rflags update that will inject or remove the trace
5412 * flags.
5413 */
5414 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5415
355be0b9 5416 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5417
4f926bf2 5418 r = 0;
d0bfb940 5419
2122ff5e 5420out:
b6c7a5dc
HB		 5421
5422 return r;
5423}
5424
8b006791
ZX		 5425/*
5426 * Translate a guest virtual address to a guest physical address.
5427 */
5428int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5429 struct kvm_translation *tr)
5430{
5431 unsigned long vaddr = tr->linear_address;
5432 gpa_t gpa;
f656ce01 5433 int idx;
8b006791 5434
f656ce01 5435 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5436 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5437 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5438 tr->physical_address = gpa;
5439 tr->valid = gpa != UNMAPPED_GVA;
5440 tr->writeable = 1;
5441 tr->usermode = 0;
8b006791
ZX		 5442
5443 return 0;
5444}
5445
d0752060
HB		 5446int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5447{
98918833
SY		 5448 struct i387_fxsave_struct *fxsave =
5449 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5450
d0752060
HB		 5451 memcpy(fpu->fpr, fxsave->st_space, 128);
5452 fpu->fcw = fxsave->cwd;
5453 fpu->fsw = fxsave->swd;
5454 fpu->ftwx = fxsave->twd;
5455 fpu->last_opcode = fxsave->fop;
5456 fpu->last_ip = fxsave->rip;
5457 fpu->last_dp = fxsave->rdp;
5458 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5459
d0752060
HB		 5460 return 0;
5461}
5462
5463int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5464{
98918833
SY		 5465 struct i387_fxsave_struct *fxsave =
5466 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5467
d0752060
HB		 5468 memcpy(fxsave->st_space, fpu->fpr, 128);
5469 fxsave->cwd = fpu->fcw;
5470 fxsave->swd = fpu->fsw;
5471 fxsave->twd = fpu->ftwx;
5472 fxsave->fop = fpu->last_opcode;
5473 fxsave->rip = fpu->last_ip;
5474 fxsave->rdp = fpu->last_dp;
5475 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5476
d0752060
HB		 5477 return 0;
5478}
5479
10ab25cd 5480int fx_init(struct kvm_vcpu *vcpu)
d0752060 5481{
10ab25cd
JK		 5482 int err;
5483
5484 err = fpu_alloc(&vcpu->arch.guest_fpu);
5485 if (err)
5486 return err;
5487
98918833 5488 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5489
2acf923e
DC		 5490 /*
5491 * Ensure guest xcr0 is valid for loading
5492 */
5493 vcpu->arch.xcr0 = XSTATE_FP;
5494
ad312c7c 5495 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5496
5497 return 0;
d0752060
HB		 5498}
5499EXPORT_SYMBOL_GPL(fx_init);
5500
98918833
SY		 5501static void fx_free(struct kvm_vcpu *vcpu)
5502{
5503 fpu_free(&vcpu->arch.guest_fpu);
5504}
5505
d0752060
HB		 5506void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5507{
2608d7a1 5508 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5509 return;
5510
2acf923e
DC		 5511 /*
5512 * Restore all possible states in the guest,
5513 * and assume host would use all available bits.
5514 * Guest xcr0 would be loaded later.
5515 */
5516 kvm_put_guest_xcr0(vcpu);
d0752060 5517 vcpu->guest_fpu_loaded = 1;
7cf30855 5518 unlazy_fpu(current);
98918833 5519 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5520 trace_kvm_fpu(1);
d0752060 5521}
d0752060
HB		 5522
5523void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5524{
2acf923e
DC		 5525 kvm_put_guest_xcr0(vcpu);
5526
d0752060
HB		 5527 if (!vcpu->guest_fpu_loaded)
5528 return;
5529
5530 vcpu->guest_fpu_loaded = 0;
98918833 5531 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5532 ++vcpu->stat.fpu_reload;
a8eeb04a 5533 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5534 trace_kvm_fpu(0);
d0752060 5535}
e9b11c17
ZX		 5536
5537void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5538{
7f1ea208
JR		 5539 if (vcpu->arch.time_page) {
5540 kvm_release_page_dirty(vcpu->arch.time_page);
5541 vcpu->arch.time_page = NULL;
5542 }
5543
f5f48ee1 5544 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5545 fx_free(vcpu);
e9b11c17
ZX		 5546 kvm_x86_ops->vcpu_free(vcpu);
5547}
5548
5549struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5550 unsigned int id)
5551{
6755bae8
ZA		 5552 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5553 printk_once(KERN_WARNING
5554 "kvm: SMP vm created on host with unstable TSC; "
5555 "guest TSC will not be reliable\n");
26e5215f
AK		 5556 return kvm_x86_ops->vcpu_create(kvm, id);
5557}
e9b11c17 5558
26e5215f
AK		 5559int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5560{
5561 int r;
e9b11c17 5562
0bed3b56 5563 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5564 vcpu_load(vcpu);
5565 r = kvm_arch_vcpu_reset(vcpu);
5566 if (r == 0)
5567 r = kvm_mmu_setup(vcpu);
5568 vcpu_put(vcpu);
5569 if (r < 0)
5570 goto free_vcpu;
5571
26e5215f 5572 return 0;
e9b11c17
ZX		 5573free_vcpu:
5574 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5575 return r;
e9b11c17
ZX		 5576}
5577
d40ccc62 5578void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5579{
5580 vcpu_load(vcpu);
5581 kvm_mmu_unload(vcpu);
5582 vcpu_put(vcpu);
5583
98918833 5584 fx_free(vcpu);
e9b11c17
ZX		 5585 kvm_x86_ops->vcpu_free(vcpu);
5586}
5587
5588int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5589{
448fa4a9
JK		 5590 vcpu->arch.nmi_pending = false;
5591 vcpu->arch.nmi_injected = false;
5592
42dbaa5a
JK		 5593 vcpu->arch.switch_db_regs = 0;
5594 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5595 vcpu->arch.dr6 = DR6_FIXED_1;
5596 vcpu->arch.dr7 = DR7_FIXED_1;
5597
e9b11c17
ZX		 5598 return kvm_x86_ops->vcpu_reset(vcpu);
5599}
5600
10474ae8 5601int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5602{
ca84d1a2
ZA		 5603 struct kvm *kvm;
5604 struct kvm_vcpu *vcpu;
5605 int i;
5606
18863bdd 5607 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5608 list_for_each_entry(kvm, &vm_list, vm_list)
5609 kvm_for_each_vcpu(i, vcpu, kvm)
5610 if (vcpu->cpu == smp_processor_id())
5611 kvm_request_guest_time_update(vcpu);
10474ae8 5612 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5613}
5614
5615void kvm_arch_hardware_disable(void *garbage)
5616{
5617 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5618 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5619}
5620
5621int kvm_arch_hardware_setup(void)
5622{
5623 return kvm_x86_ops->hardware_setup();
5624}
5625
5626void kvm_arch_hardware_unsetup(void)
5627{
5628 kvm_x86_ops->hardware_unsetup();
5629}
5630
5631void kvm_arch_check_processor_compat(void *rtn)
5632{
5633 kvm_x86_ops->check_processor_compatibility(rtn);
5634}
5635
5636int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5637{
5638 struct page *page;
5639 struct kvm *kvm;
5640 int r;
5641
5642 BUG_ON(vcpu->kvm == NULL);
5643 kvm = vcpu->kvm;
5644
9aabc88f 5645 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
ad312c7c 5646 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5647 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5648 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5649 else
a4535290 5650 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5651
5652 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5653 if (!page) {
5654 r = -ENOMEM;
5655 goto fail;
5656 }
ad312c7c 5657 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5658
5659 r = kvm_mmu_create(vcpu);
5660 if (r < 0)
5661 goto fail_free_pio_data;
5662
5663 if (irqchip_in_kernel(kvm)) {
5664 r = kvm_create_lapic(vcpu);
5665 if (r < 0)
5666 goto fail_mmu_destroy;
5667 }
5668
890ca9ae
HY		 5669 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5670 GFP_KERNEL);
5671 if (!vcpu->arch.mce_banks) {
5672 r = -ENOMEM;
443c39bc 5673 goto fail_free_lapic;
890ca9ae
HY		 5674 }
5675 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5676
f5f48ee1
SY		 5677 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5678 goto fail_free_mce_banks;
5679
e9b11c17 5680 return 0;
f5f48ee1
SY		 5681fail_free_mce_banks:
5682 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5683fail_free_lapic:
5684 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5685fail_mmu_destroy:
5686 kvm_mmu_destroy(vcpu);
5687fail_free_pio_data:
ad312c7c 5688 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5689fail:
5690 return r;
5691}
5692
5693void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5694{
f656ce01
MT		 5695 int idx;
5696
36cb93fd 5697 kfree(vcpu->arch.mce_banks);
e9b11c17 5698 kvm_free_lapic(vcpu);
f656ce01 5699 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5700 kvm_mmu_destroy(vcpu);
f656ce01 5701 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5702 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5703}
d19a9cd2
ZX		 5704
5705struct kvm *kvm_arch_create_vm(void)
5706{
5707 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5708
5709 if (!kvm)
5710 return ERR_PTR(-ENOMEM);
5711
f05e70ac 5712 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5713 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5714
5550af4d
SY		 5715 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5716 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5717
99e3e30a
ZA		 5718 spin_lock_init(&kvm->arch.tsc_write_lock);
5719
d19a9cd2
ZX		 5720 return kvm;
5721}
5722
5723static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5724{
5725 vcpu_load(vcpu);
5726 kvm_mmu_unload(vcpu);
5727 vcpu_put(vcpu);
5728}
5729
5730static void kvm_free_vcpus(struct kvm *kvm)
5731{
5732 unsigned int i;
988a2cae 5733 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5734
5735 /*
5736 * Unpin any mmu pages first.
5737 */
988a2cae
GN		 5738 kvm_for_each_vcpu(i, vcpu, kvm)
5739 kvm_unload_vcpu_mmu(vcpu);
5740 kvm_for_each_vcpu(i, vcpu, kvm)
5741 kvm_arch_vcpu_free(vcpu);
5742
5743 mutex_lock(&kvm->lock);
5744 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5745 kvm->vcpus[i] = NULL;
d19a9cd2 5746
988a2cae
GN		 5747 atomic_set(&kvm->online_vcpus, 0);
5748 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5749}
5750
ad8ba2cd
SY		 5751void kvm_arch_sync_events(struct kvm *kvm)
5752{
ba4cef31 5753 kvm_free_all_assigned_devices(kvm);
aea924f6 5754 kvm_free_pit(kvm);
ad8ba2cd
SY		 5755}
5756
d19a9cd2
ZX		 5757void kvm_arch_destroy_vm(struct kvm *kvm)
5758{
6eb55818 5759 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5760 kfree(kvm->arch.vpic);
5761 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5762 kvm_free_vcpus(kvm);
5763 kvm_free_physmem(kvm);
3d45830c
AK		 5764 if (kvm->arch.apic_access_page)
5765 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5766 if (kvm->arch.ept_identity_pagetable)
5767 put_page(kvm->arch.ept_identity_pagetable);
64749204 5768 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5769 kfree(kvm);
5770}
0de10343 5771
f7784b8e
MT		 5772int kvm_arch_prepare_memory_region(struct kvm *kvm,
5773 struct kvm_memory_slot *memslot,
0de10343 5774 struct kvm_memory_slot old,
f7784b8e 5775 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5776 int user_alloc)
5777{
f7784b8e 5778 int npages = memslot->npages;
7ac77099
AK		 5779 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5780
5781 /* Prevent internal slot pages from being moved by fork()/COW. */
5782 if (memslot->id >= KVM_MEMORY_SLOTS)
5783 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5784
5785 /*To keep backward compatibility with older userspace,
5786 *x86 needs to hanlde !user_alloc case.
5787 */
5788 if (!user_alloc) {
5789 if (npages && !old.rmap) {
604b38ac
AA		 5790 unsigned long userspace_addr;
5791
72dc67a6 5792 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5793 userspace_addr = do_mmap(NULL, 0,
5794 npages * PAGE_SIZE,
5795 PROT_READ | PROT_WRITE,
7ac77099 5796 map_flags,
604b38ac 5797 0);
72dc67a6 5798 up_write(&current->mm->mmap_sem);
0de10343 5799
604b38ac
AA		 5800 if (IS_ERR((void *)userspace_addr))
5801 return PTR_ERR((void *)userspace_addr);
5802
604b38ac 5803 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5804 }
5805 }
5806
f7784b8e
MT		 5807
5808 return 0;
5809}
5810
5811void kvm_arch_commit_memory_region(struct kvm *kvm,
5812 struct kvm_userspace_memory_region *mem,
5813 struct kvm_memory_slot old,
5814 int user_alloc)
5815{
5816
5817 int npages = mem->memory_size >> PAGE_SHIFT;
5818
5819 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5820 int ret;
5821
5822 down_write(&current->mm->mmap_sem);
5823 ret = do_munmap(current->mm, old.userspace_addr,
5824 old.npages * PAGE_SIZE);
5825 up_write(&current->mm->mmap_sem);
5826 if (ret < 0)
5827 printk(KERN_WARNING
5828 "kvm_vm_ioctl_set_memory_region: "
5829 "failed to munmap memory\n");
5830 }
5831
7c8a83b7 5832 spin_lock(&kvm->mmu_lock);
f05e70ac 5833 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5834 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5835 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5836 }
5837
5838 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5839 spin_unlock(&kvm->mmu_lock);
0de10343 5840}
1d737c8a 5841
34d4cb8f
MT		 5842void kvm_arch_flush_shadow(struct kvm *kvm)
5843{
5844 kvm_mmu_zap_all(kvm);
8986ecc0 5845 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5846}
5847
1d737c8a
ZX		 5848int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5849{
a4535290 5850 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5851 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5852 || vcpu->arch.nmi_pending ||
5853 (kvm_arch_interrupt_allowed(vcpu) &&
5854 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5855}
5736199a 5856
5736199a
ZX		 5857void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5858{
32f88400
MT		 5859 int me;
5860 int cpu = vcpu->cpu;
5736199a
ZX		 5861
5862 if (waitqueue_active(&vcpu->wq)) {
5863 wake_up_interruptible(&vcpu->wq);
5864 ++vcpu->stat.halt_wakeup;
5865 }
32f88400
MT		 5866
5867 me = get_cpu();
5868 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5869 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5870 smp_send_reschedule(cpu);
e9571ed5 5871 put_cpu();
5736199a 5872}
78646121
GN		 5873
5874int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5875{
5876 return kvm_x86_ops->interrupt_allowed(vcpu);
5877}
229456fc 5878
f92653ee
JK		 5879bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5880{
5881 unsigned long current_rip = kvm_rip_read(vcpu) +
5882 get_segment_base(vcpu, VCPU_SREG_CS);
5883
5884 return current_rip == linear_rip;
5885}
5886EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5887
94fe45da
JK		 5888unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5889{
5890 unsigned long rflags;
5891
5892 rflags = kvm_x86_ops->get_rflags(vcpu);
5893 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5894 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5895 return rflags;
5896}
5897EXPORT_SYMBOL_GPL(kvm_get_rflags);
5898
5899void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5900{
5901 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5902 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5903 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5904 kvm_x86_ops->set_rflags(vcpu, rflags);
5905}
5906EXPORT_SYMBOL_GPL(kvm_set_rflags);
5907
229456fc
MT		 5908EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5909EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5910EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5911EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5912EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5913EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5914EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5915EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5916EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5917EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5918EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5919EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux 6.x block layer and io_uring tree(s)