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KVM: x86: Setting rflags.rf during rep-string emulation
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
92a1f12d
JR		 101bool kvm_has_tsc_control;
102EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103u32 kvm_max_guest_tsc_khz;
104EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105
cc578287
ZA		 106/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107static u32 tsc_tolerance_ppm = 250;
108module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109
16a96021
MT		 110static bool backwards_tsc_observed = false;
111
18863bdd
AK		 112#define KVM_NR_SHARED_MSRS 16
113
114struct kvm_shared_msrs_global {
115 int nr;
2bf78fa7 116 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 117};
118
119struct kvm_shared_msrs {
120 struct user_return_notifier urn;
121 bool registered;
2bf78fa7
SY		 122 struct kvm_shared_msr_values {
123 u64 host;
124 u64 curr;
125 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 126};
127
128static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 129static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 130
417bc304 131struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 132 { "pf_fixed", VCPU_STAT(pf_fixed) },
133 { "pf_guest", VCPU_STAT(pf_guest) },
134 { "tlb_flush", VCPU_STAT(tlb_flush) },
135 { "invlpg", VCPU_STAT(invlpg) },
136 { "exits", VCPU_STAT(exits) },
137 { "io_exits", VCPU_STAT(io_exits) },
138 { "mmio_exits", VCPU_STAT(mmio_exits) },
139 { "signal_exits", VCPU_STAT(signal_exits) },
140 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 141 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 142 { "halt_exits", VCPU_STAT(halt_exits) },
143 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 144 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 145 { "request_irq", VCPU_STAT(request_irq_exits) },
146 { "irq_exits", VCPU_STAT(irq_exits) },
147 { "host_state_reload", VCPU_STAT(host_state_reload) },
148 { "efer_reload", VCPU_STAT(efer_reload) },
149 { "fpu_reload", VCPU_STAT(fpu_reload) },
150 { "insn_emulation", VCPU_STAT(insn_emulation) },
151 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 152 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 153 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 154 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
155 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
156 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
157 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
158 { "mmu_flooded", VM_STAT(mmu_flooded) },
159 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 160 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 161 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 162 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 163 { "largepages", VM_STAT(lpages) },
417bc304
HB		 164 { NULL }
165};
166
2acf923e
DC		 167u64 __read_mostly host_xcr0;
168
b6785def 169static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 170
af585b92
GN		 171static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
172{
173 int i;
174 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
175 vcpu->arch.apf.gfns[i] = ~0;
176}
177
18863bdd
AK		 178static void kvm_on_user_return(struct user_return_notifier *urn)
179{
180 unsigned slot;
18863bdd
AK		 181 struct kvm_shared_msrs *locals
182 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 183 struct kvm_shared_msr_values *values;
18863bdd
AK		 184
185 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 186 values = &locals->values[slot];
187 if (values->host != values->curr) {
188 wrmsrl(shared_msrs_global.msrs[slot], values->host);
189 values->curr = values->host;
18863bdd
AK		 190 }
191 }
192 locals->registered = false;
193 user_return_notifier_unregister(urn);
194}
195
2bf78fa7 196static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 197{
18863bdd 198 u64 value;
013f6a5d
MT		 199 unsigned int cpu = smp_processor_id();
200 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 201
2bf78fa7
SY		 202 /* only read, and nobody should modify it at this time,
203 * so don't need lock */
204 if (slot >= shared_msrs_global.nr) {
205 printk(KERN_ERR "kvm: invalid MSR slot!");
206 return;
207 }
208 rdmsrl_safe(msr, &value);
209 smsr->values[slot].host = value;
210 smsr->values[slot].curr = value;
211}
212
213void kvm_define_shared_msr(unsigned slot, u32 msr)
214{
18863bdd
AK		 215 if (slot >= shared_msrs_global.nr)
216 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 217 shared_msrs_global.msrs[slot] = msr;
218 /* we need ensured the shared_msr_global have been updated */
219 smp_wmb();
18863bdd
AK		 220}
221EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
222
223static void kvm_shared_msr_cpu_online(void)
224{
225 unsigned i;
18863bdd
AK		 226
227 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 228 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 229}
230
d5696725 231void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 232{
013f6a5d
MT		 233 unsigned int cpu = smp_processor_id();
234 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 235
2bf78fa7 236 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 237 return;
2bf78fa7
SY		 238 smsr->values[slot].curr = value;
239 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 240 if (!smsr->registered) {
241 smsr->urn.on_user_return = kvm_on_user_return;
242 user_return_notifier_register(&smsr->urn);
243 smsr->registered = true;
244 }
245}
246EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
247
3548bab5
AK		 248static void drop_user_return_notifiers(void *ignore)
249{
013f6a5d
MT		 250 unsigned int cpu = smp_processor_id();
251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 252
253 if (smsr->registered)
254 kvm_on_user_return(&smsr->urn);
255}
256
6866b83e
CO		 257u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
258{
8a5a87d9 259 return vcpu->arch.apic_base;
6866b83e
CO		 260}
261EXPORT_SYMBOL_GPL(kvm_get_apic_base);
262
58cb628d
JK		 263int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
264{
265 u64 old_state = vcpu->arch.apic_base &
266 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
267 u64 new_state = msr_info->data &
268 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
269 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
270 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
271
272 if (!msr_info->host_initiated &&
273 ((msr_info->data & reserved_bits) != 0 ||
274 new_state == X2APIC_ENABLE ||
275 (new_state == MSR_IA32_APICBASE_ENABLE &&
276 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
277 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
278 old_state == 0)))
279 return 1;
280
281 kvm_lapic_set_base(vcpu, msr_info->data);
282 return 0;
6866b83e
CO		 283}
284EXPORT_SYMBOL_GPL(kvm_set_apic_base);
285
2605fc21 286asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 287{
288 /* Fault while not rebooting. We want the trace. */
289 BUG();
290}
291EXPORT_SYMBOL_GPL(kvm_spurious_fault);
292
3fd28fce
ED		 293#define EXCPT_BENIGN 0
294#define EXCPT_CONTRIBUTORY 1
295#define EXCPT_PF 2
296
297static int exception_class(int vector)
298{
299 switch (vector) {
300 case PF_VECTOR:
301 return EXCPT_PF;
302 case DE_VECTOR:
303 case TS_VECTOR:
304 case NP_VECTOR:
305 case SS_VECTOR:
306 case GP_VECTOR:
307 return EXCPT_CONTRIBUTORY;
308 default:
309 break;
310 }
311 return EXCPT_BENIGN;
312}
313
314static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 315 unsigned nr, bool has_error, u32 error_code,
316 bool reinject)
3fd28fce
ED		 317{
318 u32 prev_nr;
319 int class1, class2;
320
3842d135
AK		 321 kvm_make_request(KVM_REQ_EVENT, vcpu);
322
3fd28fce
ED		 323 if (!vcpu->arch.exception.pending) {
324 queue:
325 vcpu->arch.exception.pending = true;
326 vcpu->arch.exception.has_error_code = has_error;
327 vcpu->arch.exception.nr = nr;
328 vcpu->arch.exception.error_code = error_code;
3f0fd292 329 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 330 return;
331 }
332
333 /* to check exception */
334 prev_nr = vcpu->arch.exception.nr;
335 if (prev_nr == DF_VECTOR) {
336 /* triple fault -> shutdown */
a8eeb04a 337 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 338 return;
339 }
340 class1 = exception_class(prev_nr);
341 class2 = exception_class(nr);
342 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
343 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
344 /* generate double fault per SDM Table 5-5 */
345 vcpu->arch.exception.pending = true;
346 vcpu->arch.exception.has_error_code = true;
347 vcpu->arch.exception.nr = DF_VECTOR;
348 vcpu->arch.exception.error_code = 0;
349 } else
350 /* replace previous exception with a new one in a hope
351 that instruction re-execution will regenerate lost
352 exception */
353 goto queue;
354}
355
298101da
AK		 356void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
357{
ce7ddec4 358 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 359}
360EXPORT_SYMBOL_GPL(kvm_queue_exception);
361
ce7ddec4
JR		 362void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
363{
364 kvm_multiple_exception(vcpu, nr, false, 0, true);
365}
366EXPORT_SYMBOL_GPL(kvm_requeue_exception);
367
db8fcefa 368void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 369{
db8fcefa
AP		 370 if (err)
371 kvm_inject_gp(vcpu, 0);
372 else
373 kvm_x86_ops->skip_emulated_instruction(vcpu);
374}
375EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 376
6389ee94 377void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 378{
379 ++vcpu->stat.pf_guest;
6389ee94
AK		 380 vcpu->arch.cr2 = fault->address;
381 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 382}
27d6c865 383EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 384
6389ee94 385void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 386{
6389ee94
AK		 387 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
388 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 389 else
6389ee94 390 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 391}
392
3419ffc8
SY		 393void kvm_inject_nmi(struct kvm_vcpu *vcpu)
394{
7460fb4a
AK		 395 atomic_inc(&vcpu->arch.nmi_queued);
396 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 397}
398EXPORT_SYMBOL_GPL(kvm_inject_nmi);
399
298101da
AK		 400void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
401{
ce7ddec4 402 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 403}
404EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
405
ce7ddec4
JR		 406void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
407{
408 kvm_multiple_exception(vcpu, nr, true, error_code, true);
409}
410EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
411
0a79b009
AK		 412/*
413 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
414 * a #GP and return false.
415 */
416bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 417{
0a79b009
AK		 418 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
419 return true;
420 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
421 return false;
298101da 422}
0a79b009 423EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 424
ec92fe44
JR		 425/*
426 * This function will be used to read from the physical memory of the currently
427 * running guest. The difference to kvm_read_guest_page is that this function
428 * can read from guest physical or from the guest's guest physical memory.
429 */
430int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
431 gfn_t ngfn, void *data, int offset, int len,
432 u32 access)
433{
434 gfn_t real_gfn;
435 gpa_t ngpa;
436
437 ngpa = gfn_to_gpa(ngfn);
438 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
439 if (real_gfn == UNMAPPED_GVA)
440 return -EFAULT;
441
442 real_gfn = gpa_to_gfn(real_gfn);
443
444 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
445}
446EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
447
3d06b8bf
JR		 448int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
449 void *data, int offset, int len, u32 access)
450{
451 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
452 data, offset, len, access);
453}
454
a03490ed
CO		 455/*
456 * Load the pae pdptrs. Return true is they are all valid.
457 */
ff03a073 458int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 459{
460 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
461 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
462 int i;
463 int ret;
ff03a073 464 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 465
ff03a073
JR		 466 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
467 offset * sizeof(u64), sizeof(pdpte),
468 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 469 if (ret < 0) {
470 ret = 0;
471 goto out;
472 }
473 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 474 if (is_present_gpte(pdpte[i]) &&
20c466b5 475 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 476 ret = 0;
477 goto out;
478 }
479 }
480 ret = 1;
481
ff03a073 482 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 483 __set_bit(VCPU_EXREG_PDPTR,
484 (unsigned long *)&vcpu->arch.regs_avail);
485 __set_bit(VCPU_EXREG_PDPTR,
486 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 487out:
a03490ed
CO		 488
489 return ret;
490}
cc4b6871 491EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 492
d835dfec
AK		 493static bool pdptrs_changed(struct kvm_vcpu *vcpu)
494{
ff03a073 495 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 496 bool changed = true;
3d06b8bf
JR		 497 int offset;
498 gfn_t gfn;
d835dfec
AK		 499 int r;
500
501 if (is_long_mode(vcpu) || !is_pae(vcpu))
502 return false;
503
6de4f3ad
AK		 504 if (!test_bit(VCPU_EXREG_PDPTR,
505 (unsigned long *)&vcpu->arch.regs_avail))
506 return true;
507
9f8fe504
AK		 508 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
509 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 510 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
511 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 512 if (r < 0)
513 goto out;
ff03a073 514 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 515out:
d835dfec
AK		 516
517 return changed;
518}
519
49a9b07e 520int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 521{
aad82703
SY		 522 unsigned long old_cr0 = kvm_read_cr0(vcpu);
523 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
524 X86_CR0_CD | X86_CR0_NW;
525
f9a48e6a
AK		 526 cr0 |= X86_CR0_ET;
527
ab344828 528#ifdef CONFIG_X86_64
0f12244f
GN		 529 if (cr0 & 0xffffffff00000000UL)
530 return 1;
ab344828
GN		 531#endif
532
533 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 534
0f12244f
GN		 535 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
536 return 1;
a03490ed 537
0f12244f
GN		 538 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
539 return 1;
a03490ed
CO		 540
541 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
542#ifdef CONFIG_X86_64
f6801dff 543 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 544 int cs_db, cs_l;
545
0f12244f
GN		 546 if (!is_pae(vcpu))
547 return 1;
a03490ed 548 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 549 if (cs_l)
550 return 1;
a03490ed
CO		 551 } else
552#endif
ff03a073 553 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 554 kvm_read_cr3(vcpu)))
0f12244f 555 return 1;
a03490ed
CO		 556 }
557
ad756a16
MJ		 558 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
559 return 1;
560
a03490ed 561 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 562
d170c419 563 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 564 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 565 kvm_async_pf_hash_reset(vcpu);
566 }
e5f3f027 567
aad82703
SY		 568 if ((cr0 ^ old_cr0) & update_bits)
569 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 570 return 0;
571}
2d3ad1f4 572EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 573
2d3ad1f4 574void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 575{
49a9b07e 576 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 577}
2d3ad1f4 578EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 579
42bdf991
MT		 580static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
581{
582 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
583 !vcpu->guest_xcr0_loaded) {
584 /* kvm_set_xcr() also depends on this */
585 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
586 vcpu->guest_xcr0_loaded = 1;
587 }
588}
589
590static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
591{
592 if (vcpu->guest_xcr0_loaded) {
593 if (vcpu->arch.xcr0 != host_xcr0)
594 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
595 vcpu->guest_xcr0_loaded = 0;
596 }
597}
598
2acf923e
DC		 599int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
600{
56c103ec
LJ		 601 u64 xcr0 = xcr;
602 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 603 u64 valid_bits;
2acf923e
DC		 604
605 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
606 if (index != XCR_XFEATURE_ENABLED_MASK)
607 return 1;
2acf923e
DC		 608 if (!(xcr0 & XSTATE_FP))
609 return 1;
610 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
611 return 1;
46c34cb0
PB		 612
613 /*
614 * Do not allow the guest to set bits that we do not support
615 * saving. However, xcr0 bit 0 is always set, even if the
616 * emulated CPU does not support XSAVE (see fx_init).
617 */
618 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
619 if (xcr0 & ~valid_bits)
2acf923e 620 return 1;
46c34cb0 621
390bd528
LJ		 622 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
623 return 1;
624
42bdf991 625 kvm_put_guest_xcr0(vcpu);
2acf923e 626 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 627
628 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
629 kvm_update_cpuid(vcpu);
2acf923e
DC		 630 return 0;
631}
632
633int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
634{
764bcbc5
Z		 635 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
636 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 637 kvm_inject_gp(vcpu, 0);
638 return 1;
639 }
640 return 0;
641}
642EXPORT_SYMBOL_GPL(kvm_set_xcr);
643
a83b29c6 644int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 645{
fc78f519 646 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 647 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
648 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 649 if (cr4 & CR4_RESERVED_BITS)
650 return 1;
a03490ed 651
2acf923e
DC		 652 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
653 return 1;
654
c68b734f
YW		 655 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
656 return 1;
657
97ec8c06
FW		 658 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
659 return 1;
660
afcbf13f 661 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 662 return 1;
663
a03490ed 664 if (is_long_mode(vcpu)) {
0f12244f
GN		 665 if (!(cr4 & X86_CR4_PAE))
666 return 1;
a2edf57f
AK		 667 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
668 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 669 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
670 kvm_read_cr3(vcpu)))
0f12244f
GN		 671 return 1;
672
ad756a16
MJ		 673 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
674 if (!guest_cpuid_has_pcid(vcpu))
675 return 1;
676
677 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
678 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
679 return 1;
680 }
681
5e1746d6 682 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 683 return 1;
a03490ed 684
ad756a16
MJ		 685 if (((cr4 ^ old_cr4) & pdptr_bits) ||
686 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 687 kvm_mmu_reset_context(vcpu);
0f12244f 688
97ec8c06
FW		 689 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
690 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
691
2acf923e 692 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 693 kvm_update_cpuid(vcpu);
2acf923e 694
0f12244f
GN		 695 return 0;
696}
2d3ad1f4 697EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 698
2390218b 699int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 700{
9f8fe504 701 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 702 kvm_mmu_sync_roots(vcpu);
d835dfec 703 kvm_mmu_flush_tlb(vcpu);
0f12244f 704 return 0;
d835dfec
AK		 705 }
706
a03490ed 707 if (is_long_mode(vcpu)) {
d9f89b88
JK		 708 if (cr3 & CR3_L_MODE_RESERVED_BITS)
709 return 1;
710 } else if (is_pae(vcpu) && is_paging(vcpu) &&
711 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 712 return 1;
a03490ed 713
0f12244f 714 vcpu->arch.cr3 = cr3;
aff48baa 715 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 716 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 717 return 0;
718}
2d3ad1f4 719EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 720
eea1cff9 721int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 722{
0f12244f
GN		 723 if (cr8 & CR8_RESERVED_BITS)
724 return 1;
a03490ed
CO		 725 if (irqchip_in_kernel(vcpu->kvm))
726 kvm_lapic_set_tpr(vcpu, cr8);
727 else
ad312c7c 728 vcpu->arch.cr8 = cr8;
0f12244f
GN		 729 return 0;
730}
2d3ad1f4 731EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 732
2d3ad1f4 733unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 734{
735 if (irqchip_in_kernel(vcpu->kvm))
736 return kvm_lapic_get_cr8(vcpu);
737 else
ad312c7c 738 return vcpu->arch.cr8;
a03490ed 739}
2d3ad1f4 740EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 741
73aaf249
JK		 742static void kvm_update_dr6(struct kvm_vcpu *vcpu)
743{
744 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
745 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
746}
747
c8639010
JK		 748static void kvm_update_dr7(struct kvm_vcpu *vcpu)
749{
750 unsigned long dr7;
751
752 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
753 dr7 = vcpu->arch.guest_debug_dr7;
754 else
755 dr7 = vcpu->arch.dr7;
756 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 757 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
758 if (dr7 & DR7_BP_EN_MASK)
759 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 760}
761
6f43ed01
NA		 762static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
763{
764 u64 fixed = DR6_FIXED_1;
765
766 if (!guest_cpuid_has_rtm(vcpu))
767 fixed |= DR6_RTM;
768 return fixed;
769}
770
338dbc97 771static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 772{
773 switch (dr) {
774 case 0 ... 3:
775 vcpu->arch.db[dr] = val;
776 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
777 vcpu->arch.eff_db[dr] = val;
778 break;
779 case 4:
338dbc97
GN		 780 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
781 return 1; /* #UD */
020df079
GN		 782 /* fall through */
783 case 6:
338dbc97
GN		 784 if (val & 0xffffffff00000000ULL)
785 return -1; /* #GP */
6f43ed01 786 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 787 kvm_update_dr6(vcpu);
020df079
GN		 788 break;
789 case 5:
338dbc97
GN		 790 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
791 return 1; /* #UD */
020df079
GN		 792 /* fall through */
793 default: /* 7 */
338dbc97
GN		 794 if (val & 0xffffffff00000000ULL)
795 return -1; /* #GP */
020df079 796 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 797 kvm_update_dr7(vcpu);
020df079
GN		 798 break;
799 }
800
801 return 0;
802}
338dbc97
GN		 803
804int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
805{
806 int res;
807
808 res = __kvm_set_dr(vcpu, dr, val);
809 if (res > 0)
810 kvm_queue_exception(vcpu, UD_VECTOR);
811 else if (res < 0)
812 kvm_inject_gp(vcpu, 0);
813
814 return res;
815}
020df079
GN		 816EXPORT_SYMBOL_GPL(kvm_set_dr);
817
338dbc97 818static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 819{
820 switch (dr) {
821 case 0 ... 3:
822 *val = vcpu->arch.db[dr];
823 break;
824 case 4:
338dbc97 825 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 826 return 1;
020df079
GN		 827 /* fall through */
828 case 6:
73aaf249
JK		 829 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
830 *val = vcpu->arch.dr6;
831 else
832 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 833 break;
834 case 5:
338dbc97 835 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 836 return 1;
020df079
GN		 837 /* fall through */
838 default: /* 7 */
839 *val = vcpu->arch.dr7;
840 break;
841 }
842
843 return 0;
844}
338dbc97
GN		 845
846int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
847{
848 if (_kvm_get_dr(vcpu, dr, val)) {
849 kvm_queue_exception(vcpu, UD_VECTOR);
850 return 1;
851 }
852 return 0;
853}
020df079
GN		 854EXPORT_SYMBOL_GPL(kvm_get_dr);
855
022cd0e8
AK		 856bool kvm_rdpmc(struct kvm_vcpu *vcpu)
857{
858 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
859 u64 data;
860 int err;
861
862 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
863 if (err)
864 return err;
865 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
866 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
867 return err;
868}
869EXPORT_SYMBOL_GPL(kvm_rdpmc);
870
043405e1
CO		 871/*
872 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
873 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
874 *
875 * This list is modified at module load time to reflect the
e3267cbb
GC		 876 * capabilities of the host cpu. This capabilities test skips MSRs that are
877 * kvm-specific. Those are put in the beginning of the list.
043405e1 878 */
e3267cbb 879
e984097b 880#define KVM_SAVE_MSRS_BEGIN 12
043405e1 881static u32 msrs_to_save[] = {
e3267cbb 882 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 883 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 884 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 885 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 886 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 887 MSR_KVM_PV_EOI_EN,
043405e1 888 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 889 MSR_STAR,
043405e1
CO		 890#ifdef CONFIG_X86_64
891 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
892#endif
b3897a49 893 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 894 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 895};
896
897static unsigned num_msrs_to_save;
898
f1d24831 899static const u32 emulated_msrs[] = {
ba904635 900 MSR_IA32_TSC_ADJUST,
a3e06bbe 901 MSR_IA32_TSCDEADLINE,
043405e1 902 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 903 MSR_IA32_MCG_STATUS,
904 MSR_IA32_MCG_CTL,
043405e1
CO		 905};
906
384bb783 907bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 908{
b69e8cae 909 if (efer & efer_reserved_bits)
384bb783 910 return false;
15c4a640 911
1b2fd70c
AG		 912 if (efer & EFER_FFXSR) {
913 struct kvm_cpuid_entry2 *feat;
914
915 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 916 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 917 return false;
1b2fd70c
AG		 918 }
919
d8017474
AG		 920 if (efer & EFER_SVME) {
921 struct kvm_cpuid_entry2 *feat;
922
923 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 924 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 925 return false;
d8017474
AG		 926 }
927
384bb783
JK		 928 return true;
929}
930EXPORT_SYMBOL_GPL(kvm_valid_efer);
931
932static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
933{
934 u64 old_efer = vcpu->arch.efer;
935
936 if (!kvm_valid_efer(vcpu, efer))
937 return 1;
938
939 if (is_paging(vcpu)
940 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
941 return 1;
942
15c4a640 943 efer &= ~EFER_LMA;
f6801dff 944 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 945
a3d204e2
SY		 946 kvm_x86_ops->set_efer(vcpu, efer);
947
aad82703
SY		 948 /* Update reserved bits */
949 if ((efer ^ old_efer) & EFER_NX)
950 kvm_mmu_reset_context(vcpu);
951
b69e8cae 952 return 0;
15c4a640
CO		 953}
954
f2b4b7dd
JR		 955void kvm_enable_efer_bits(u64 mask)
956{
957 efer_reserved_bits &= ~mask;
958}
959EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
960
961
15c4a640
CO		 962/*
963 * Writes msr value into into the appropriate "register".
964 * Returns 0 on success, non-0 otherwise.
965 * Assumes vcpu_load() was already called.
966 */
8fe8ab46 967int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 968{
8fe8ab46 969 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 970}
971
313a3dc7
CO		 972/*
973 * Adapt set_msr() to msr_io()'s calling convention
974 */
975static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
976{
8fe8ab46
WA		 977 struct msr_data msr;
978
979 msr.data = *data;
980 msr.index = index;
981 msr.host_initiated = true;
982 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 983}
984
16e8d74d
MT		 985#ifdef CONFIG_X86_64
986struct pvclock_gtod_data {
987 seqcount_t seq;
988
989 struct { /* extract of a clocksource struct */
990 int vclock_mode;
991 cycle_t cycle_last;
992 cycle_t mask;
993 u32 mult;
994 u32 shift;
995 } clock;
996
997 /* open coded 'struct timespec' */
998 u64 monotonic_time_snsec;
999 time_t monotonic_time_sec;
1000};
1001
1002static struct pvclock_gtod_data pvclock_gtod_data;
1003
1004static void update_pvclock_gtod(struct timekeeper *tk)
1005{
1006 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1007
1008 write_seqcount_begin(&vdata->seq);
1009
1010 /* copy pvclock gtod data */
1011 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1012 vdata->clock.cycle_last = tk->clock->cycle_last;
1013 vdata->clock.mask = tk->clock->mask;
1014 vdata->clock.mult = tk->mult;
1015 vdata->clock.shift = tk->shift;
1016
1017 vdata->monotonic_time_sec = tk->xtime_sec
1018 + tk->wall_to_monotonic.tv_sec;
1019 vdata->monotonic_time_snsec = tk->xtime_nsec
1020 + (tk->wall_to_monotonic.tv_nsec
1021 << tk->shift);
1022 while (vdata->monotonic_time_snsec >=
1023 (((u64)NSEC_PER_SEC) << tk->shift)) {
1024 vdata->monotonic_time_snsec -=
1025 ((u64)NSEC_PER_SEC) << tk->shift;
1026 vdata->monotonic_time_sec++;
1027 }
1028
1029 write_seqcount_end(&vdata->seq);
1030}
1031#endif
1032
1033
18068523
GOC		 1034static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1035{
9ed3c444
AK		 1036 int version;
1037 int r;
50d0a0f9 1038 struct pvclock_wall_clock wc;
923de3cf 1039 struct timespec boot;
18068523
GOC		 1040
1041 if (!wall_clock)
1042 return;
1043
9ed3c444
AK		 1044 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1045 if (r)
1046 return;
1047
1048 if (version & 1)
1049 ++version; /* first time write, random junk */
1050
1051 ++version;
18068523 1052
18068523
GOC		 1053 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1054
50d0a0f9
GH		 1055 /*
1056 * The guest calculates current wall clock time by adding
34c238a1 1057 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1058 * wall clock specified here. guest system time equals host
1059 * system time for us, thus we must fill in host boot time here.
1060 */
923de3cf 1061 getboottime(&boot);
50d0a0f9 1062
4b648665
BR		 1063 if (kvm->arch.kvmclock_offset) {
1064 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1065 boot = timespec_sub(boot, ts);
1066 }
50d0a0f9
GH		 1067 wc.sec = boot.tv_sec;
1068 wc.nsec = boot.tv_nsec;
1069 wc.version = version;
18068523
GOC		 1070
1071 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1072
1073 version++;
1074 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1075}
1076
50d0a0f9
GH		 1077static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1078{
1079 uint32_t quotient, remainder;
1080
1081 /* Don't try to replace with do_div(), this one calculates
1082 * "(dividend << 32) / divisor" */
1083 __asm__ ( "divl %4"
1084 : "=a" (quotient), "=d" (remainder)
1085 : "0" (0), "1" (dividend), "r" (divisor) );
1086 return quotient;
1087}
1088
5f4e3f88
ZA		 1089static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1090 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1091{
5f4e3f88 1092 uint64_t scaled64;
50d0a0f9
GH		 1093 int32_t shift = 0;
1094 uint64_t tps64;
1095 uint32_t tps32;
1096
5f4e3f88
ZA		 1097 tps64 = base_khz * 1000LL;
1098 scaled64 = scaled_khz * 1000LL;
50933623 1099 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1100 tps64 >>= 1;
1101 shift--;
1102 }
1103
1104 tps32 = (uint32_t)tps64;
50933623
JK		 1105 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1106 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1107 scaled64 >>= 1;
1108 else
1109 tps32 <<= 1;
50d0a0f9
GH		 1110 shift++;
1111 }
1112
5f4e3f88
ZA		 1113 *pshift = shift;
1114 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1115
5f4e3f88
ZA		 1116 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1117 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1118}
1119
759379dd
ZA		 1120static inline u64 get_kernel_ns(void)
1121{
1122 struct timespec ts;
1123
759379dd
ZA		 1124 ktime_get_ts(&ts);
1125 monotonic_to_bootbased(&ts);
1126 return timespec_to_ns(&ts);
50d0a0f9
GH		 1127}
1128
d828199e 1129#ifdef CONFIG_X86_64
16e8d74d 1130static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1131#endif
16e8d74d 1132
c8076604 1133static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1134unsigned long max_tsc_khz;
c8076604 1135
cc578287 1136static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1137{
cc578287
ZA		 1138 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1139 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1140}
1141
cc578287 1142static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1143{
cc578287
ZA		 1144 u64 v = (u64)khz * (1000000 + ppm);
1145 do_div(v, 1000000);
1146 return v;
1e993611
JR		 1147}
1148
cc578287 1149static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1150{
cc578287
ZA		 1151 u32 thresh_lo, thresh_hi;
1152 int use_scaling = 0;
217fc9cf 1153
03ba32ca
MT		 1154 /* tsc_khz can be zero if TSC calibration fails */
1155 if (this_tsc_khz == 0)
1156 return;
1157
c285545f
ZA		 1158 /* Compute a scale to convert nanoseconds in TSC cycles */
1159 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1160 &vcpu->arch.virtual_tsc_shift,
1161 &vcpu->arch.virtual_tsc_mult);
1162 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1163
1164 /*
1165 * Compute the variation in TSC rate which is acceptable
1166 * within the range of tolerance and decide if the
1167 * rate being applied is within that bounds of the hardware
1168 * rate. If so, no scaling or compensation need be done.
1169 */
1170 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1171 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1172 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1173 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1174 use_scaling = 1;
1175 }
1176 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1177}
1178
1179static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1180{
e26101b1 1181 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1182 vcpu->arch.virtual_tsc_mult,
1183 vcpu->arch.virtual_tsc_shift);
e26101b1 1184 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1185 return tsc;
1186}
1187
b48aa97e
MT		 1188void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1189{
1190#ifdef CONFIG_X86_64
1191 bool vcpus_matched;
1192 bool do_request = false;
1193 struct kvm_arch *ka = &vcpu->kvm->arch;
1194 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1195
1196 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1197 atomic_read(&vcpu->kvm->online_vcpus));
1198
1199 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1200 if (!ka->use_master_clock)
1201 do_request = 1;
1202
1203 if (!vcpus_matched && ka->use_master_clock)
1204 do_request = 1;
1205
1206 if (do_request)
1207 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1208
1209 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1210 atomic_read(&vcpu->kvm->online_vcpus),
1211 ka->use_master_clock, gtod->clock.vclock_mode);
1212#endif
1213}
1214
ba904635
WA		 1215static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1216{
1217 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1218 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1219}
1220
8fe8ab46 1221void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1222{
1223 struct kvm *kvm = vcpu->kvm;
f38e098f 1224 u64 offset, ns, elapsed;
99e3e30a 1225 unsigned long flags;
02626b6a 1226 s64 usdiff;
b48aa97e 1227 bool matched;
0d3da0d2 1228 bool already_matched;
8fe8ab46 1229 u64 data = msr->data;
99e3e30a 1230
038f8c11 1231 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1232 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1233 ns = get_kernel_ns();
f38e098f 1234 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1235
03ba32ca 1236 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1237 int faulted = 0;
1238
03ba32ca
MT		 1239 /* n.b - signed multiplication and division required */
1240 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1241#ifdef CONFIG_X86_64
03ba32ca 1242 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1243#else
03ba32ca 1244 /* do_div() only does unsigned */
8915aa27
MT		 1245 asm("1: idivl %[divisor]\n"
1246 "2: xor %%edx, %%edx\n"
1247 " movl $0, %[faulted]\n"
1248 "3:\n"
1249 ".section .fixup,\"ax\"\n"
1250 "4: movl $1, %[faulted]\n"
1251 " jmp 3b\n"
1252 ".previous\n"
1253
1254 _ASM_EXTABLE(1b, 4b)
1255
1256 : "=A"(usdiff), [faulted] "=r" (faulted)
1257 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1258
5d3cb0f6 1259#endif
03ba32ca
MT		 1260 do_div(elapsed, 1000);
1261 usdiff -= elapsed;
1262 if (usdiff < 0)
1263 usdiff = -usdiff;
8915aa27
MT		 1264
1265 /* idivl overflow => difference is larger than USEC_PER_SEC */
1266 if (faulted)
1267 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1268 } else
1269 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1270
1271 /*
5d3cb0f6
ZA		 1272 * Special case: TSC write with a small delta (1 second) of virtual
1273 * cycle time against real time is interpreted as an attempt to
1274 * synchronize the CPU.
1275 *
1276 * For a reliable TSC, we can match TSC offsets, and for an unstable
1277 * TSC, we add elapsed time in this computation. We could let the
1278 * compensation code attempt to catch up if we fall behind, but
1279 * it's better to try to match offsets from the beginning.
1280 */
02626b6a 1281 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1282 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1283 if (!check_tsc_unstable()) {
e26101b1 1284 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1285 pr_debug("kvm: matched tsc offset for %llu\n", data);
1286 } else {
857e4099 1287 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1288 data += delta;
1289 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1290 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1291 }
b48aa97e 1292 matched = true;
0d3da0d2 1293 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1294 } else {
1295 /*
1296 * We split periods of matched TSC writes into generations.
1297 * For each generation, we track the original measured
1298 * nanosecond time, offset, and write, so if TSCs are in
1299 * sync, we can match exact offset, and if not, we can match
4a969980 1300 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1301 *
1302 * These values are tracked in kvm->arch.cur_xxx variables.
1303 */
1304 kvm->arch.cur_tsc_generation++;
1305 kvm->arch.cur_tsc_nsec = ns;
1306 kvm->arch.cur_tsc_write = data;
1307 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1308 matched = false;
0d3da0d2 1309 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1310 kvm->arch.cur_tsc_generation, data);
f38e098f 1311 }
e26101b1
ZA		 1312
1313 /*
1314 * We also track th most recent recorded KHZ, write and time to
1315 * allow the matching interval to be extended at each write.
1316 */
f38e098f
ZA		 1317 kvm->arch.last_tsc_nsec = ns;
1318 kvm->arch.last_tsc_write = data;
5d3cb0f6 1319 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1320
b183aa58 1321 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1322
1323 /* Keep track of which generation this VCPU has synchronized to */
1324 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1325 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1326 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1327
ba904635
WA		 1328 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1329 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1330 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1331 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1332
1333 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1334 if (!matched) {
b48aa97e 1335 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1336 } else if (!already_matched) {
1337 kvm->arch.nr_vcpus_matched_tsc++;
1338 }
b48aa97e
MT		 1339
1340 kvm_track_tsc_matching(vcpu);
1341 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1342}
e26101b1 1343
99e3e30a
ZA		 1344EXPORT_SYMBOL_GPL(kvm_write_tsc);
1345
d828199e
MT		 1346#ifdef CONFIG_X86_64
1347
1348static cycle_t read_tsc(void)
1349{
1350 cycle_t ret;
1351 u64 last;
1352
1353 /*
1354 * Empirically, a fence (of type that depends on the CPU)
1355 * before rdtsc is enough to ensure that rdtsc is ordered
1356 * with respect to loads. The various CPU manuals are unclear
1357 * as to whether rdtsc can be reordered with later loads,
1358 * but no one has ever seen it happen.
1359 */
1360 rdtsc_barrier();
1361 ret = (cycle_t)vget_cycles();
1362
1363 last = pvclock_gtod_data.clock.cycle_last;
1364
1365 if (likely(ret >= last))
1366 return ret;
1367
1368 /*
1369 * GCC likes to generate cmov here, but this branch is extremely
1370 * predictable (it's just a funciton of time and the likely is
1371 * very likely) and there's a data dependence, so force GCC
1372 * to generate a branch instead. I don't barrier() because
1373 * we don't actually need a barrier, and if this function
1374 * ever gets inlined it will generate worse code.
1375 */
1376 asm volatile ("");
1377 return last;
1378}
1379
1380static inline u64 vgettsc(cycle_t *cycle_now)
1381{
1382 long v;
1383 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1384
1385 *cycle_now = read_tsc();
1386
1387 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1388 return v * gtod->clock.mult;
1389}
1390
1391static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1392{
1393 unsigned long seq;
1394 u64 ns;
1395 int mode;
1396 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1397
1398 ts->tv_nsec = 0;
1399 do {
1400 seq = read_seqcount_begin(&gtod->seq);
1401 mode = gtod->clock.vclock_mode;
1402 ts->tv_sec = gtod->monotonic_time_sec;
1403 ns = gtod->monotonic_time_snsec;
1404 ns += vgettsc(cycle_now);
1405 ns >>= gtod->clock.shift;
1406 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1407 timespec_add_ns(ts, ns);
1408
1409 return mode;
1410}
1411
1412/* returns true if host is using tsc clocksource */
1413static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1414{
1415 struct timespec ts;
1416
1417 /* checked again under seqlock below */
1418 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1419 return false;
1420
1421 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1422 return false;
1423
1424 monotonic_to_bootbased(&ts);
1425 *kernel_ns = timespec_to_ns(&ts);
1426
1427 return true;
1428}
1429#endif
1430
1431/*
1432 *
b48aa97e
MT		 1433 * Assuming a stable TSC across physical CPUS, and a stable TSC
1434 * across virtual CPUs, the following condition is possible.
1435 * Each numbered line represents an event visible to both
d828199e
MT		 1436 * CPUs at the next numbered event.
1437 *
1438 * "timespecX" represents host monotonic time. "tscX" represents
1439 * RDTSC value.
1440 *
1441 * VCPU0 on CPU0 | VCPU1 on CPU1
1442 *
1443 * 1. read timespec0,tsc0
1444 * 2. | timespec1 = timespec0 + N
1445 * | tsc1 = tsc0 + M
1446 * 3. transition to guest | transition to guest
1447 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1448 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1449 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1450 *
1451 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1452 *
1453 * - ret0 < ret1
1454 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1455 * ...
1456 * - 0 < N - M => M < N
1457 *
1458 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1459 * always the case (the difference between two distinct xtime instances
1460 * might be smaller then the difference between corresponding TSC reads,
1461 * when updating guest vcpus pvclock areas).
1462 *
1463 * To avoid that problem, do not allow visibility of distinct
1464 * system_timestamp/tsc_timestamp values simultaneously: use a master
1465 * copy of host monotonic time values. Update that master copy
1466 * in lockstep.
1467 *
b48aa97e 1468 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1469 *
1470 */
1471
1472static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1473{
1474#ifdef CONFIG_X86_64
1475 struct kvm_arch *ka = &kvm->arch;
1476 int vclock_mode;
b48aa97e
MT		 1477 bool host_tsc_clocksource, vcpus_matched;
1478
1479 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1480 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1481
1482 /*
1483 * If the host uses TSC clock, then passthrough TSC as stable
1484 * to the guest.
1485 */
b48aa97e 1486 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1487 &ka->master_kernel_ns,
1488 &ka->master_cycle_now);
1489
16a96021
MT		 1490 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1491 && !backwards_tsc_observed;
b48aa97e 1492
d828199e
MT		 1493 if (ka->use_master_clock)
1494 atomic_set(&kvm_guest_has_master_clock, 1);
1495
1496 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1497 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1498 vcpus_matched);
d828199e
MT		 1499#endif
1500}
1501
2e762ff7
MT		 1502static void kvm_gen_update_masterclock(struct kvm *kvm)
1503{
1504#ifdef CONFIG_X86_64
1505 int i;
1506 struct kvm_vcpu *vcpu;
1507 struct kvm_arch *ka = &kvm->arch;
1508
1509 spin_lock(&ka->pvclock_gtod_sync_lock);
1510 kvm_make_mclock_inprogress_request(kvm);
1511 /* no guest entries from this point */
1512 pvclock_update_vm_gtod_copy(kvm);
1513
1514 kvm_for_each_vcpu(i, vcpu, kvm)
1515 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1516
1517 /* guest entries allowed */
1518 kvm_for_each_vcpu(i, vcpu, kvm)
1519 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1520
1521 spin_unlock(&ka->pvclock_gtod_sync_lock);
1522#endif
1523}
1524
34c238a1 1525static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1526{
d828199e 1527 unsigned long flags, this_tsc_khz;
18068523 1528 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1529 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1530 s64 kernel_ns;
d828199e 1531 u64 tsc_timestamp, host_tsc;
0b79459b 1532 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1533 u8 pvclock_flags;
d828199e
MT		 1534 bool use_master_clock;
1535
1536 kernel_ns = 0;
1537 host_tsc = 0;
18068523 1538
d828199e
MT		 1539 /*
1540 * If the host uses TSC clock, then passthrough TSC as stable
1541 * to the guest.
1542 */
1543 spin_lock(&ka->pvclock_gtod_sync_lock);
1544 use_master_clock = ka->use_master_clock;
1545 if (use_master_clock) {
1546 host_tsc = ka->master_cycle_now;
1547 kernel_ns = ka->master_kernel_ns;
1548 }
1549 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1550
1551 /* Keep irq disabled to prevent changes to the clock */
1552 local_irq_save(flags);
1553 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1554 if (unlikely(this_tsc_khz == 0)) {
1555 local_irq_restore(flags);
1556 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1557 return 1;
1558 }
d828199e
MT		 1559 if (!use_master_clock) {
1560 host_tsc = native_read_tsc();
1561 kernel_ns = get_kernel_ns();
1562 }
1563
1564 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1565
c285545f
ZA		 1566 /*
1567 * We may have to catch up the TSC to match elapsed wall clock
1568 * time for two reasons, even if kvmclock is used.
1569 * 1) CPU could have been running below the maximum TSC rate
1570 * 2) Broken TSC compensation resets the base at each VCPU
1571 * entry to avoid unknown leaps of TSC even when running
1572 * again on the same CPU. This may cause apparent elapsed
1573 * time to disappear, and the guest to stand still or run
1574 * very slowly.
1575 */
1576 if (vcpu->tsc_catchup) {
1577 u64 tsc = compute_guest_tsc(v, kernel_ns);
1578 if (tsc > tsc_timestamp) {
f1e2b260 1579 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1580 tsc_timestamp = tsc;
1581 }
50d0a0f9
GH		 1582 }
1583
18068523
GOC		 1584 local_irq_restore(flags);
1585
0b79459b 1586 if (!vcpu->pv_time_enabled)
c285545f 1587 return 0;
18068523 1588
e48672fa 1589 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1590 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1591 &vcpu->hv_clock.tsc_shift,
1592 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1593 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1594 }
1595
1596 /* With all the info we got, fill in the values */
1d5f066e 1597 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1598 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1599 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1600
18068523
GOC		 1601 /*
1602 * The interface expects us to write an even number signaling that the
1603 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1604 * state, we just increase by 2 at the end.
18068523 1605 */
50d0a0f9 1606 vcpu->hv_clock.version += 2;
18068523 1607
0b79459b
AH		 1608 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1609 &guest_hv_clock, sizeof(guest_hv_clock))))
1610 return 0;
78c0337a
MT		 1611
1612 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1613 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1614
1615 if (vcpu->pvclock_set_guest_stopped_request) {
1616 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1617 vcpu->pvclock_set_guest_stopped_request = false;
1618 }
1619
d828199e
MT		 1620 /* If the host uses TSC clocksource, then it is stable */
1621 if (use_master_clock)
1622 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1623
78c0337a
MT		 1624 vcpu->hv_clock.flags = pvclock_flags;
1625
0b79459b
AH		 1626 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1627 &vcpu->hv_clock,
1628 sizeof(vcpu->hv_clock));
8cfdc000 1629 return 0;
c8076604
GH		 1630}
1631
0061d53d
MT		 1632/*
1633 * kvmclock updates which are isolated to a given vcpu, such as
1634 * vcpu->cpu migration, should not allow system_timestamp from
1635 * the rest of the vcpus to remain static. Otherwise ntp frequency
1636 * correction applies to one vcpu's system_timestamp but not
1637 * the others.
1638 *
1639 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1640 * We need to rate-limit these requests though, as they can
1641 * considerably slow guests that have a large number of vcpus.
1642 * The time for a remote vcpu to update its kvmclock is bound
1643 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1644 */
1645
7e44e449
AJ		 1646#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1647
1648static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1649{
1650 int i;
7e44e449
AJ		 1651 struct delayed_work *dwork = to_delayed_work(work);
1652 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1653 kvmclock_update_work);
1654 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1655 struct kvm_vcpu *vcpu;
1656
1657 kvm_for_each_vcpu(i, vcpu, kvm) {
1658 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1659 kvm_vcpu_kick(vcpu);
1660 }
1661}
1662
7e44e449
AJ		 1663static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1664{
1665 struct kvm *kvm = v->kvm;
1666
1667 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1668 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1669 KVMCLOCK_UPDATE_DELAY);
1670}
1671
332967a3
AJ		 1672#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1673
1674static void kvmclock_sync_fn(struct work_struct *work)
1675{
1676 struct delayed_work *dwork = to_delayed_work(work);
1677 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1678 kvmclock_sync_work);
1679 struct kvm *kvm = container_of(ka, struct kvm, arch);
1680
1681 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1682 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1683 KVMCLOCK_SYNC_PERIOD);
1684}
1685
9ba075a6
AK		 1686static bool msr_mtrr_valid(unsigned msr)
1687{
1688 switch (msr) {
1689 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1690 case MSR_MTRRfix64K_00000:
1691 case MSR_MTRRfix16K_80000:
1692 case MSR_MTRRfix16K_A0000:
1693 case MSR_MTRRfix4K_C0000:
1694 case MSR_MTRRfix4K_C8000:
1695 case MSR_MTRRfix4K_D0000:
1696 case MSR_MTRRfix4K_D8000:
1697 case MSR_MTRRfix4K_E0000:
1698 case MSR_MTRRfix4K_E8000:
1699 case MSR_MTRRfix4K_F0000:
1700 case MSR_MTRRfix4K_F8000:
1701 case MSR_MTRRdefType:
1702 case MSR_IA32_CR_PAT:
1703 return true;
1704 case 0x2f8:
1705 return true;
1706 }
1707 return false;
1708}
1709
d6289b93
MT		 1710static bool valid_pat_type(unsigned t)
1711{
1712 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1713}
1714
1715static bool valid_mtrr_type(unsigned t)
1716{
1717 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1718}
1719
1720static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1721{
1722 int i;
1723
1724 if (!msr_mtrr_valid(msr))
1725 return false;
1726
1727 if (msr == MSR_IA32_CR_PAT) {
1728 for (i = 0; i < 8; i++)
1729 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1730 return false;
1731 return true;
1732 } else if (msr == MSR_MTRRdefType) {
1733 if (data & ~0xcff)
1734 return false;
1735 return valid_mtrr_type(data & 0xff);
1736 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1737 for (i = 0; i < 8 ; i++)
1738 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1739 return false;
1740 return true;
1741 }
1742
1743 /* variable MTRRs */
1744 return valid_mtrr_type(data & 0xff);
1745}
1746
9ba075a6
AK		 1747static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1748{
0bed3b56
SY		 1749 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1750
d6289b93 1751 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1752 return 1;
1753
0bed3b56
SY		 1754 if (msr == MSR_MTRRdefType) {
1755 vcpu->arch.mtrr_state.def_type = data;
1756 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1757 } else if (msr == MSR_MTRRfix64K_00000)
1758 p[0] = data;
1759 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1760 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1761 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1762 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1763 else if (msr == MSR_IA32_CR_PAT)
1764 vcpu->arch.pat = data;
1765 else { /* Variable MTRRs */
1766 int idx, is_mtrr_mask;
1767 u64 *pt;
1768
1769 idx = (msr - 0x200) / 2;
1770 is_mtrr_mask = msr - 0x200 - 2 * idx;
1771 if (!is_mtrr_mask)
1772 pt =
1773 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1774 else
1775 pt =
1776 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1777 *pt = data;
1778 }
1779
1780 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1781 return 0;
1782}
15c4a640 1783
890ca9ae 1784static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1785{
890ca9ae
HY		 1786 u64 mcg_cap = vcpu->arch.mcg_cap;
1787 unsigned bank_num = mcg_cap & 0xff;
1788
15c4a640 1789 switch (msr) {
15c4a640 1790 case MSR_IA32_MCG_STATUS:
890ca9ae 1791 vcpu->arch.mcg_status = data;
15c4a640 1792 break;
c7ac679c 1793 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1794 if (!(mcg_cap & MCG_CTL_P))
1795 return 1;
1796 if (data != 0 && data != ~(u64)0)
1797 return -1;
1798 vcpu->arch.mcg_ctl = data;
1799 break;
1800 default:
1801 if (msr >= MSR_IA32_MC0_CTL &&
1802 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1803 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1804 /* only 0 or all 1s can be written to IA32_MCi_CTL
1805 * some Linux kernels though clear bit 10 in bank 4 to
1806 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1807 * this to avoid an uncatched #GP in the guest
1808 */
890ca9ae 1809 if ((offset & 0x3) == 0 &&
114be429 1810 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1811 return -1;
1812 vcpu->arch.mce_banks[offset] = data;
1813 break;
1814 }
1815 return 1;
1816 }
1817 return 0;
1818}
1819
ffde22ac
ES		 1820static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1821{
1822 struct kvm *kvm = vcpu->kvm;
1823 int lm = is_long_mode(vcpu);
1824 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1825 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1826 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1827 : kvm->arch.xen_hvm_config.blob_size_32;
1828 u32 page_num = data & ~PAGE_MASK;
1829 u64 page_addr = data & PAGE_MASK;
1830 u8 *page;
1831 int r;
1832
1833 r = -E2BIG;
1834 if (page_num >= blob_size)
1835 goto out;
1836 r = -ENOMEM;
ff5c2c03
SL		 1837 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1838 if (IS_ERR(page)) {
1839 r = PTR_ERR(page);
ffde22ac 1840 goto out;
ff5c2c03 1841 }
ffde22ac
ES		 1842 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1843 goto out_free;
1844 r = 0;
1845out_free:
1846 kfree(page);
1847out:
1848 return r;
1849}
1850
55cd8e5a
GN		 1851static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1852{
1853 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1854}
1855
1856static bool kvm_hv_msr_partition_wide(u32 msr)
1857{
1858 bool r = false;
1859 switch (msr) {
1860 case HV_X64_MSR_GUEST_OS_ID:
1861 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1862 case HV_X64_MSR_REFERENCE_TSC:
1863 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1864 r = true;
1865 break;
1866 }
1867
1868 return r;
1869}
1870
1871static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1872{
1873 struct kvm *kvm = vcpu->kvm;
1874
1875 switch (msr) {
1876 case HV_X64_MSR_GUEST_OS_ID:
1877 kvm->arch.hv_guest_os_id = data;
1878 /* setting guest os id to zero disables hypercall page */
1879 if (!kvm->arch.hv_guest_os_id)
1880 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1881 break;
1882 case HV_X64_MSR_HYPERCALL: {
1883 u64 gfn;
1884 unsigned long addr;
1885 u8 instructions[4];
1886
1887 /* if guest os id is not set hypercall should remain disabled */
1888 if (!kvm->arch.hv_guest_os_id)
1889 break;
1890 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1891 kvm->arch.hv_hypercall = data;
1892 break;
1893 }
1894 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1895 addr = gfn_to_hva(kvm, gfn);
1896 if (kvm_is_error_hva(addr))
1897 return 1;
1898 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1899 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1900 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1901 return 1;
1902 kvm->arch.hv_hypercall = data;
b94b64c9 1903 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1904 break;
1905 }
e984097b
VR		 1906 case HV_X64_MSR_REFERENCE_TSC: {
1907 u64 gfn;
1908 HV_REFERENCE_TSC_PAGE tsc_ref;
1909 memset(&tsc_ref, 0, sizeof(tsc_ref));
1910 kvm->arch.hv_tsc_page = data;
1911 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1912 break;
1913 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1914 if (kvm_write_guest(kvm, data,
1915 &tsc_ref, sizeof(tsc_ref)))
1916 return 1;
1917 mark_page_dirty(kvm, gfn);
1918 break;
1919 }
55cd8e5a 1920 default:
a737f256
CD		 1921 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1922 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1923 return 1;
1924 }
1925 return 0;
1926}
1927
1928static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1929{
10388a07
GN		 1930 switch (msr) {
1931 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1932 u64 gfn;
10388a07 1933 unsigned long addr;
55cd8e5a 1934
10388a07
GN		 1935 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1936 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1937 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1938 return 1;
10388a07
GN		 1939 break;
1940 }
b3af1e88
VR		 1941 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1942 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1943 if (kvm_is_error_hva(addr))
1944 return 1;
8b0cedff 1945 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1946 return 1;
1947 vcpu->arch.hv_vapic = data;
b3af1e88 1948 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 1949 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1950 return 1;
10388a07
GN		 1951 break;
1952 }
1953 case HV_X64_MSR_EOI:
1954 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1955 case HV_X64_MSR_ICR:
1956 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1957 case HV_X64_MSR_TPR:
1958 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1959 default:
a737f256
CD		 1960 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1961 "data 0x%llx\n", msr, data);
10388a07
GN		 1962 return 1;
1963 }
1964
1965 return 0;
55cd8e5a
GN		 1966}
1967
344d9588
GN		 1968static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1969{
1970 gpa_t gpa = data & ~0x3f;
1971
4a969980 1972 /* Bits 2:5 are reserved, Should be zero */
6adba527 1973 if (data & 0x3c)
344d9588
GN		 1974 return 1;
1975
1976 vcpu->arch.apf.msr_val = data;
1977
1978 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1979 kvm_clear_async_pf_completion_queue(vcpu);
1980 kvm_async_pf_hash_reset(vcpu);
1981 return 0;
1982 }
1983
8f964525
AH		 1984 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1985 sizeof(u32)))
344d9588
GN		 1986 return 1;
1987
6adba527 1988 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1989 kvm_async_pf_wakeup_all(vcpu);
1990 return 0;
1991}
1992
12f9a48f
GC		 1993static void kvmclock_reset(struct kvm_vcpu *vcpu)
1994{
0b79459b 1995 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1996}
1997
c9aaa895
GC		 1998static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1999{
2000 u64 delta;
2001
2002 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2003 return;
2004
2005 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2006 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2007 vcpu->arch.st.accum_steal = delta;
2008}
2009
2010static void record_steal_time(struct kvm_vcpu *vcpu)
2011{
2012 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2013 return;
2014
2015 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2016 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2017 return;
2018
2019 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2020 vcpu->arch.st.steal.version += 2;
2021 vcpu->arch.st.accum_steal = 0;
2022
2023 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2024 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2025}
2026
8fe8ab46 2027int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2028{
5753785f 2029 bool pr = false;
8fe8ab46
WA		 2030 u32 msr = msr_info->index;
2031 u64 data = msr_info->data;
5753785f 2032
15c4a640 2033 switch (msr) {
2e32b719
BP		 2034 case MSR_AMD64_NB_CFG:
2035 case MSR_IA32_UCODE_REV:
2036 case MSR_IA32_UCODE_WRITE:
2037 case MSR_VM_HSAVE_PA:
2038 case MSR_AMD64_PATCH_LOADER:
2039 case MSR_AMD64_BU_CFG2:
2040 break;
2041
15c4a640 2042 case MSR_EFER:
b69e8cae 2043 return set_efer(vcpu, data);
8f1589d9
AP		 2044 case MSR_K7_HWCR:
2045 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2046 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2047 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2048 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2049 if (data != 0) {
a737f256
CD		 2050 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2051 data);
8f1589d9
AP		 2052 return 1;
2053 }
15c4a640 2054 break;
f7c6d140
AP		 2055 case MSR_FAM10H_MMIO_CONF_BASE:
2056 if (data != 0) {
a737f256
CD		 2057 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2058 "0x%llx\n", data);
f7c6d140
AP		 2059 return 1;
2060 }
15c4a640 2061 break;
b5e2fec0
AG		 2062 case MSR_IA32_DEBUGCTLMSR:
2063 if (!data) {
2064 /* We support the non-activated case already */
2065 break;
2066 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2067 /* Values other than LBR and BTF are vendor-specific,
2068 thus reserved and should throw a #GP */
2069 return 1;
2070 }
a737f256
CD		 2071 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2072 __func__, data);
b5e2fec0 2073 break;
9ba075a6
AK		 2074 case 0x200 ... 0x2ff:
2075 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2076 case MSR_IA32_APICBASE:
58cb628d 2077 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2078 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2079 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2080 case MSR_IA32_TSCDEADLINE:
2081 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2082 break;
ba904635
WA		 2083 case MSR_IA32_TSC_ADJUST:
2084 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2085 if (!msr_info->host_initiated) {
2086 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2087 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2088 }
2089 vcpu->arch.ia32_tsc_adjust_msr = data;
2090 }
2091 break;
15c4a640 2092 case MSR_IA32_MISC_ENABLE:
ad312c7c 2093 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2094 break;
11c6bffa 2095 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2096 case MSR_KVM_WALL_CLOCK:
2097 vcpu->kvm->arch.wall_clock = data;
2098 kvm_write_wall_clock(vcpu->kvm, data);
2099 break;
11c6bffa 2100 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2101 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2102 u64 gpa_offset;
12f9a48f 2103 kvmclock_reset(vcpu);
18068523
GOC		 2104
2105 vcpu->arch.time = data;
0061d53d 2106 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2107
2108 /* we verify if the enable bit is set... */
2109 if (!(data & 1))
2110 break;
2111
0b79459b 2112 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2113
0b79459b 2114 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2115 &vcpu->arch.pv_time, data & ~1ULL,
2116 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2117 vcpu->arch.pv_time_enabled = false;
2118 else
2119 vcpu->arch.pv_time_enabled = true;
32cad84f 2120
18068523
GOC		 2121 break;
2122 }
344d9588
GN		 2123 case MSR_KVM_ASYNC_PF_EN:
2124 if (kvm_pv_enable_async_pf(vcpu, data))
2125 return 1;
2126 break;
c9aaa895
GC		 2127 case MSR_KVM_STEAL_TIME:
2128
2129 if (unlikely(!sched_info_on()))
2130 return 1;
2131
2132 if (data & KVM_STEAL_RESERVED_MASK)
2133 return 1;
2134
2135 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2136 data & KVM_STEAL_VALID_BITS,
2137 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2138 return 1;
2139
2140 vcpu->arch.st.msr_val = data;
2141
2142 if (!(data & KVM_MSR_ENABLED))
2143 break;
2144
2145 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2146
2147 preempt_disable();
2148 accumulate_steal_time(vcpu);
2149 preempt_enable();
2150
2151 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2152
2153 break;
ae7a2a3f
MT		 2154 case MSR_KVM_PV_EOI_EN:
2155 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2156 return 1;
2157 break;
c9aaa895 2158
890ca9ae
HY		 2159 case MSR_IA32_MCG_CTL:
2160 case MSR_IA32_MCG_STATUS:
2161 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2162 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2163
2164 /* Performance counters are not protected by a CPUID bit,
2165 * so we should check all of them in the generic path for the sake of
2166 * cross vendor migration.
2167 * Writing a zero into the event select MSRs disables them,
2168 * which we perfectly emulate ;-). Any other value should be at least
2169 * reported, some guests depend on them.
2170 */
71db6023
AP		 2171 case MSR_K7_EVNTSEL0:
2172 case MSR_K7_EVNTSEL1:
2173 case MSR_K7_EVNTSEL2:
2174 case MSR_K7_EVNTSEL3:
2175 if (data != 0)
a737f256
CD		 2176 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2177 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2178 break;
2179 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2180 * so we ignore writes to make it happy.
2181 */
71db6023
AP		 2182 case MSR_K7_PERFCTR0:
2183 case MSR_K7_PERFCTR1:
2184 case MSR_K7_PERFCTR2:
2185 case MSR_K7_PERFCTR3:
a737f256
CD		 2186 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2187 "0x%x data 0x%llx\n", msr, data);
71db6023 2188 break;
5753785f
GN		 2189 case MSR_P6_PERFCTR0:
2190 case MSR_P6_PERFCTR1:
2191 pr = true;
2192 case MSR_P6_EVNTSEL0:
2193 case MSR_P6_EVNTSEL1:
2194 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2195 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2196
2197 if (pr || data != 0)
a737f256
CD		 2198 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2199 "0x%x data 0x%llx\n", msr, data);
5753785f 2200 break;
84e0cefa
JS		 2201 case MSR_K7_CLK_CTL:
2202 /*
2203 * Ignore all writes to this no longer documented MSR.
2204 * Writes are only relevant for old K7 processors,
2205 * all pre-dating SVM, but a recommended workaround from
4a969980 2206 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2207 * affected processor models on the command line, hence
2208 * the need to ignore the workaround.
2209 */
2210 break;
55cd8e5a
GN		 2211 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2212 if (kvm_hv_msr_partition_wide(msr)) {
2213 int r;
2214 mutex_lock(&vcpu->kvm->lock);
2215 r = set_msr_hyperv_pw(vcpu, msr, data);
2216 mutex_unlock(&vcpu->kvm->lock);
2217 return r;
2218 } else
2219 return set_msr_hyperv(vcpu, msr, data);
2220 break;
91c9c3ed 2221 case MSR_IA32_BBL_CR_CTL3:
2222 /* Drop writes to this legacy MSR -- see rdmsr
2223 * counterpart for further detail.
2224 */
a737f256 2225 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2226 break;
2b036c6b
BO		 2227 case MSR_AMD64_OSVW_ID_LENGTH:
2228 if (!guest_cpuid_has_osvw(vcpu))
2229 return 1;
2230 vcpu->arch.osvw.length = data;
2231 break;
2232 case MSR_AMD64_OSVW_STATUS:
2233 if (!guest_cpuid_has_osvw(vcpu))
2234 return 1;
2235 vcpu->arch.osvw.status = data;
2236 break;
15c4a640 2237 default:
ffde22ac
ES		 2238 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2239 return xen_hvm_config(vcpu, data);
f5132b01 2240 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2241 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2242 if (!ignore_msrs) {
a737f256
CD		 2243 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2244 msr, data);
ed85c068
AP		 2245 return 1;
2246 } else {
a737f256
CD		 2247 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2248 msr, data);
ed85c068
AP		 2249 break;
2250 }
15c4a640
CO		 2251 }
2252 return 0;
2253}
2254EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2255
2256
2257/*
2258 * Reads an msr value (of 'msr_index') into 'pdata'.
2259 * Returns 0 on success, non-0 otherwise.
2260 * Assumes vcpu_load() was already called.
2261 */
2262int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2263{
2264 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2265}
2266
9ba075a6
AK		 2267static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2268{
0bed3b56
SY		 2269 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2270
9ba075a6
AK		 2271 if (!msr_mtrr_valid(msr))
2272 return 1;
2273
0bed3b56
SY		 2274 if (msr == MSR_MTRRdefType)
2275 *pdata = vcpu->arch.mtrr_state.def_type +
2276 (vcpu->arch.mtrr_state.enabled << 10);
2277 else if (msr == MSR_MTRRfix64K_00000)
2278 *pdata = p[0];
2279 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2280 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2281 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2282 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2283 else if (msr == MSR_IA32_CR_PAT)
2284 *pdata = vcpu->arch.pat;
2285 else { /* Variable MTRRs */
2286 int idx, is_mtrr_mask;
2287 u64 *pt;
2288
2289 idx = (msr - 0x200) / 2;
2290 is_mtrr_mask = msr - 0x200 - 2 * idx;
2291 if (!is_mtrr_mask)
2292 pt =
2293 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2294 else
2295 pt =
2296 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2297 *pdata = *pt;
2298 }
2299
9ba075a6
AK		 2300 return 0;
2301}
2302
890ca9ae 2303static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2304{
2305 u64 data;
890ca9ae
HY		 2306 u64 mcg_cap = vcpu->arch.mcg_cap;
2307 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2308
2309 switch (msr) {
15c4a640
CO		 2310 case MSR_IA32_P5_MC_ADDR:
2311 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2312 data = 0;
2313 break;
15c4a640 2314 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2315 data = vcpu->arch.mcg_cap;
2316 break;
c7ac679c 2317 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2318 if (!(mcg_cap & MCG_CTL_P))
2319 return 1;
2320 data = vcpu->arch.mcg_ctl;
2321 break;
2322 case MSR_IA32_MCG_STATUS:
2323 data = vcpu->arch.mcg_status;
2324 break;
2325 default:
2326 if (msr >= MSR_IA32_MC0_CTL &&
2327 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2328 u32 offset = msr - MSR_IA32_MC0_CTL;
2329 data = vcpu->arch.mce_banks[offset];
2330 break;
2331 }
2332 return 1;
2333 }
2334 *pdata = data;
2335 return 0;
2336}
2337
55cd8e5a
GN		 2338static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2339{
2340 u64 data = 0;
2341 struct kvm *kvm = vcpu->kvm;
2342
2343 switch (msr) {
2344 case HV_X64_MSR_GUEST_OS_ID:
2345 data = kvm->arch.hv_guest_os_id;
2346 break;
2347 case HV_X64_MSR_HYPERCALL:
2348 data = kvm->arch.hv_hypercall;
2349 break;
e984097b
VR		 2350 case HV_X64_MSR_TIME_REF_COUNT: {
2351 data =
2352 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2353 break;
2354 }
2355 case HV_X64_MSR_REFERENCE_TSC:
2356 data = kvm->arch.hv_tsc_page;
2357 break;
55cd8e5a 2358 default:
a737f256 2359 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2360 return 1;
2361 }
2362
2363 *pdata = data;
2364 return 0;
2365}
2366
2367static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2368{
2369 u64 data = 0;
2370
2371 switch (msr) {
2372 case HV_X64_MSR_VP_INDEX: {
2373 int r;
2374 struct kvm_vcpu *v;
684851a1
TY		 2375 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2376 if (v == vcpu) {
55cd8e5a 2377 data = r;
684851a1
TY		 2378 break;
2379 }
2380 }
55cd8e5a
GN		 2381 break;
2382 }
10388a07
GN		 2383 case HV_X64_MSR_EOI:
2384 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2385 case HV_X64_MSR_ICR:
2386 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2387 case HV_X64_MSR_TPR:
2388 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2389 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2390 data = vcpu->arch.hv_vapic;
2391 break;
55cd8e5a 2392 default:
a737f256 2393 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2394 return 1;
2395 }
2396 *pdata = data;
2397 return 0;
2398}
2399
890ca9ae
HY		 2400int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2401{
2402 u64 data;
2403
2404 switch (msr) {
890ca9ae 2405 case MSR_IA32_PLATFORM_ID:
15c4a640 2406 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2407 case MSR_IA32_DEBUGCTLMSR:
2408 case MSR_IA32_LASTBRANCHFROMIP:
2409 case MSR_IA32_LASTBRANCHTOIP:
2410 case MSR_IA32_LASTINTFROMIP:
2411 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2412 case MSR_K8_SYSCFG:
2413 case MSR_K7_HWCR:
61a6bd67 2414 case MSR_VM_HSAVE_PA:
9e699624 2415 case MSR_K7_EVNTSEL0:
1f3ee616 2416 case MSR_K7_PERFCTR0:
1fdbd48c 2417 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2418 case MSR_AMD64_NB_CFG:
f7c6d140 2419 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2420 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2421 data = 0;
2422 break;
5753785f
GN		 2423 case MSR_P6_PERFCTR0:
2424 case MSR_P6_PERFCTR1:
2425 case MSR_P6_EVNTSEL0:
2426 case MSR_P6_EVNTSEL1:
2427 if (kvm_pmu_msr(vcpu, msr))
2428 return kvm_pmu_get_msr(vcpu, msr, pdata);
2429 data = 0;
2430 break;
742bc670
MT		 2431 case MSR_IA32_UCODE_REV:
2432 data = 0x100000000ULL;
2433 break;
9ba075a6
AK		 2434 case MSR_MTRRcap:
2435 data = 0x500 | KVM_NR_VAR_MTRR;
2436 break;
2437 case 0x200 ... 0x2ff:
2438 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2439 case 0xcd: /* fsb frequency */
2440 data = 3;
2441 break;
7b914098
JS		 2442 /*
2443 * MSR_EBC_FREQUENCY_ID
2444 * Conservative value valid for even the basic CPU models.
2445 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2446 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2447 * and 266MHz for model 3, or 4. Set Core Clock
2448 * Frequency to System Bus Frequency Ratio to 1 (bits
2449 * 31:24) even though these are only valid for CPU
2450 * models > 2, however guests may end up dividing or
2451 * multiplying by zero otherwise.
2452 */
2453 case MSR_EBC_FREQUENCY_ID:
2454 data = 1 << 24;
2455 break;
15c4a640
CO		 2456 case MSR_IA32_APICBASE:
2457 data = kvm_get_apic_base(vcpu);
2458 break;
0105d1a5
GN		 2459 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2460 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2461 break;
a3e06bbe
LJ		 2462 case MSR_IA32_TSCDEADLINE:
2463 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2464 break;
ba904635
WA		 2465 case MSR_IA32_TSC_ADJUST:
2466 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2467 break;
15c4a640 2468 case MSR_IA32_MISC_ENABLE:
ad312c7c 2469 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2470 break;
847f0ad8
AG		 2471 case MSR_IA32_PERF_STATUS:
2472 /* TSC increment by tick */
2473 data = 1000ULL;
2474 /* CPU multiplier */
2475 data |= (((uint64_t)4ULL) << 40);
2476 break;
15c4a640 2477 case MSR_EFER:
f6801dff 2478 data = vcpu->arch.efer;
15c4a640 2479 break;
18068523 2480 case MSR_KVM_WALL_CLOCK:
11c6bffa 2481 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2482 data = vcpu->kvm->arch.wall_clock;
2483 break;
2484 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2485 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2486 data = vcpu->arch.time;
2487 break;
344d9588
GN		 2488 case MSR_KVM_ASYNC_PF_EN:
2489 data = vcpu->arch.apf.msr_val;
2490 break;
c9aaa895
GC		 2491 case MSR_KVM_STEAL_TIME:
2492 data = vcpu->arch.st.msr_val;
2493 break;
1d92128f
MT		 2494 case MSR_KVM_PV_EOI_EN:
2495 data = vcpu->arch.pv_eoi.msr_val;
2496 break;
890ca9ae
HY		 2497 case MSR_IA32_P5_MC_ADDR:
2498 case MSR_IA32_P5_MC_TYPE:
2499 case MSR_IA32_MCG_CAP:
2500 case MSR_IA32_MCG_CTL:
2501 case MSR_IA32_MCG_STATUS:
2502 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2503 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2504 case MSR_K7_CLK_CTL:
2505 /*
2506 * Provide expected ramp-up count for K7. All other
2507 * are set to zero, indicating minimum divisors for
2508 * every field.
2509 *
2510 * This prevents guest kernels on AMD host with CPU
2511 * type 6, model 8 and higher from exploding due to
2512 * the rdmsr failing.
2513 */
2514 data = 0x20000000;
2515 break;
55cd8e5a
GN		 2516 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2517 if (kvm_hv_msr_partition_wide(msr)) {
2518 int r;
2519 mutex_lock(&vcpu->kvm->lock);
2520 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2521 mutex_unlock(&vcpu->kvm->lock);
2522 return r;
2523 } else
2524 return get_msr_hyperv(vcpu, msr, pdata);
2525 break;
91c9c3ed 2526 case MSR_IA32_BBL_CR_CTL3:
2527 /* This legacy MSR exists but isn't fully documented in current
2528 * silicon. It is however accessed by winxp in very narrow
2529 * scenarios where it sets bit #19, itself documented as
2530 * a "reserved" bit. Best effort attempt to source coherent
2531 * read data here should the balance of the register be
2532 * interpreted by the guest:
2533 *
2534 * L2 cache control register 3: 64GB range, 256KB size,
2535 * enabled, latency 0x1, configured
2536 */
2537 data = 0xbe702111;
2538 break;
2b036c6b
BO		 2539 case MSR_AMD64_OSVW_ID_LENGTH:
2540 if (!guest_cpuid_has_osvw(vcpu))
2541 return 1;
2542 data = vcpu->arch.osvw.length;
2543 break;
2544 case MSR_AMD64_OSVW_STATUS:
2545 if (!guest_cpuid_has_osvw(vcpu))
2546 return 1;
2547 data = vcpu->arch.osvw.status;
2548 break;
15c4a640 2549 default:
f5132b01
GN		 2550 if (kvm_pmu_msr(vcpu, msr))
2551 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2552 if (!ignore_msrs) {
a737f256 2553 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2554 return 1;
2555 } else {
a737f256 2556 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2557 data = 0;
2558 }
2559 break;
15c4a640
CO		 2560 }
2561 *pdata = data;
2562 return 0;
2563}
2564EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2565
313a3dc7
CO		 2566/*
2567 * Read or write a bunch of msrs. All parameters are kernel addresses.
2568 *
2569 * @return number of msrs set successfully.
2570 */
2571static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2572 struct kvm_msr_entry *entries,
2573 int (*do_msr)(struct kvm_vcpu *vcpu,
2574 unsigned index, u64 *data))
2575{
f656ce01 2576 int i, idx;
313a3dc7 2577
f656ce01 2578 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2579 for (i = 0; i < msrs->nmsrs; ++i)
2580 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2581 break;
f656ce01 2582 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2583
313a3dc7
CO		 2584 return i;
2585}
2586
2587/*
2588 * Read or write a bunch of msrs. Parameters are user addresses.
2589 *
2590 * @return number of msrs set successfully.
2591 */
2592static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2593 int (*do_msr)(struct kvm_vcpu *vcpu,
2594 unsigned index, u64 *data),
2595 int writeback)
2596{
2597 struct kvm_msrs msrs;
2598 struct kvm_msr_entry *entries;
2599 int r, n;
2600 unsigned size;
2601
2602 r = -EFAULT;
2603 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2604 goto out;
2605
2606 r = -E2BIG;
2607 if (msrs.nmsrs >= MAX_IO_MSRS)
2608 goto out;
2609
313a3dc7 2610 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2611 entries = memdup_user(user_msrs->entries, size);
2612 if (IS_ERR(entries)) {
2613 r = PTR_ERR(entries);
313a3dc7 2614 goto out;
ff5c2c03 2615 }
313a3dc7
CO		 2616
2617 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2618 if (r < 0)
2619 goto out_free;
2620
2621 r = -EFAULT;
2622 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2623 goto out_free;
2624
2625 r = n;
2626
2627out_free:
7a73c028 2628 kfree(entries);
313a3dc7
CO		 2629out:
2630 return r;
2631}
2632
018d00d2
ZX		 2633int kvm_dev_ioctl_check_extension(long ext)
2634{
2635 int r;
2636
2637 switch (ext) {
2638 case KVM_CAP_IRQCHIP:
2639 case KVM_CAP_HLT:
2640 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2641 case KVM_CAP_SET_TSS_ADDR:
07716717 2642 case KVM_CAP_EXT_CPUID:
9c15bb1d 2643 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2644 case KVM_CAP_CLOCKSOURCE:
7837699f 2645 case KVM_CAP_PIT:
a28e4f5a 2646 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2647 case KVM_CAP_MP_STATE:
ed848624 2648 case KVM_CAP_SYNC_MMU:
a355c85c 2649 case KVM_CAP_USER_NMI:
52d939a0 2650 case KVM_CAP_REINJECT_CONTROL:
4925663a 2651 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2652 case KVM_CAP_IRQFD:
d34e6b17 2653 case KVM_CAP_IOEVENTFD:
f848a5a8 2654 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2655 case KVM_CAP_PIT2:
e9f42757 2656 case KVM_CAP_PIT_STATE2:
b927a3ce 2657 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2658 case KVM_CAP_XEN_HVM:
afbcf7ab 2659 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2660 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2661 case KVM_CAP_HYPERV:
10388a07 2662 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2663 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2664 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2665 case KVM_CAP_DEBUGREGS:
d2be1651 2666 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2667 case KVM_CAP_XSAVE:
344d9588 2668 case KVM_CAP_ASYNC_PF:
92a1f12d 2669 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2670 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2671 case KVM_CAP_READONLY_MEM:
5f66b620 2672 case KVM_CAP_HYPERV_TIME:
100943c5 2673 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2674#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2675 case KVM_CAP_ASSIGN_DEV_IRQ:
2676 case KVM_CAP_PCI_2_3:
2677#endif
018d00d2
ZX		 2678 r = 1;
2679 break;
542472b5
LV		 2680 case KVM_CAP_COALESCED_MMIO:
2681 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2682 break;
774ead3a
AK		 2683 case KVM_CAP_VAPIC:
2684 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2685 break;
f725230a 2686 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2687 r = KVM_SOFT_MAX_VCPUS;
2688 break;
2689 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2690 r = KVM_MAX_VCPUS;
2691 break;
a988b910 2692 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2693 r = KVM_USER_MEM_SLOTS;
a988b910 2694 break;
a68a6a72
MT		 2695 case KVM_CAP_PV_MMU: /* obsolete */
2696 r = 0;
2f333bcb 2697 break;
4cee4b72 2698#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2699 case KVM_CAP_IOMMU:
a1b60c1c 2700 r = iommu_present(&pci_bus_type);
62c476c7 2701 break;
4cee4b72 2702#endif
890ca9ae
HY		 2703 case KVM_CAP_MCE:
2704 r = KVM_MAX_MCE_BANKS;
2705 break;
2d5b5a66
SY		 2706 case KVM_CAP_XCRS:
2707 r = cpu_has_xsave;
2708 break;
92a1f12d
JR		 2709 case KVM_CAP_TSC_CONTROL:
2710 r = kvm_has_tsc_control;
2711 break;
4d25a066
JK		 2712 case KVM_CAP_TSC_DEADLINE_TIMER:
2713 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2714 break;
018d00d2
ZX		 2715 default:
2716 r = 0;
2717 break;
2718 }
2719 return r;
2720
2721}
2722
043405e1
CO		 2723long kvm_arch_dev_ioctl(struct file *filp,
2724 unsigned int ioctl, unsigned long arg)
2725{
2726 void __user *argp = (void __user *)arg;
2727 long r;
2728
2729 switch (ioctl) {
2730 case KVM_GET_MSR_INDEX_LIST: {
2731 struct kvm_msr_list __user *user_msr_list = argp;
2732 struct kvm_msr_list msr_list;
2733 unsigned n;
2734
2735 r = -EFAULT;
2736 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2737 goto out;
2738 n = msr_list.nmsrs;
2739 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2740 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2741 goto out;
2742 r = -E2BIG;
e125e7b6 2743 if (n < msr_list.nmsrs)
043405e1
CO		 2744 goto out;
2745 r = -EFAULT;
2746 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2747 num_msrs_to_save * sizeof(u32)))
2748 goto out;
e125e7b6 2749 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2750 &emulated_msrs,
2751 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2752 goto out;
2753 r = 0;
2754 break;
2755 }
9c15bb1d
BP		 2756 case KVM_GET_SUPPORTED_CPUID:
2757 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2758 struct kvm_cpuid2 __user *cpuid_arg = argp;
2759 struct kvm_cpuid2 cpuid;
2760
2761 r = -EFAULT;
2762 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2763 goto out;
9c15bb1d
BP		 2764
2765 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2766 ioctl);
674eea0f
AK		 2767 if (r)
2768 goto out;
2769
2770 r = -EFAULT;
2771 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2772 goto out;
2773 r = 0;
2774 break;
2775 }
890ca9ae
HY		 2776 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2777 u64 mce_cap;
2778
2779 mce_cap = KVM_MCE_CAP_SUPPORTED;
2780 r = -EFAULT;
2781 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2782 goto out;
2783 r = 0;
2784 break;
2785 }
043405e1
CO		 2786 default:
2787 r = -EINVAL;
2788 }
2789out:
2790 return r;
2791}
2792
f5f48ee1
SY		 2793static void wbinvd_ipi(void *garbage)
2794{
2795 wbinvd();
2796}
2797
2798static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2799{
e0f0bbc5 2800 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2801}
2802
313a3dc7
CO		 2803void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2804{
f5f48ee1
SY		 2805 /* Address WBINVD may be executed by guest */
2806 if (need_emulate_wbinvd(vcpu)) {
2807 if (kvm_x86_ops->has_wbinvd_exit())
2808 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2809 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2810 smp_call_function_single(vcpu->cpu,
2811 wbinvd_ipi, NULL, 1);
2812 }
2813
313a3dc7 2814 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2815
0dd6a6ed
ZA		 2816 /* Apply any externally detected TSC adjustments (due to suspend) */
2817 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2818 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2819 vcpu->arch.tsc_offset_adjustment = 0;
2820 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2821 }
8f6055cb 2822
48434c20 2823 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2824 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2825 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2826 if (tsc_delta < 0)
2827 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2828 if (check_tsc_unstable()) {
b183aa58
ZA		 2829 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2830 vcpu->arch.last_guest_tsc);
2831 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2832 vcpu->arch.tsc_catchup = 1;
c285545f 2833 }
d98d07ca
MT		 2834 /*
2835 * On a host with synchronized TSC, there is no need to update
2836 * kvmclock on vcpu->cpu migration
2837 */
2838 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2839 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2840 if (vcpu->cpu != cpu)
2841 kvm_migrate_timers(vcpu);
e48672fa 2842 vcpu->cpu = cpu;
6b7d7e76 2843 }
c9aaa895
GC		 2844
2845 accumulate_steal_time(vcpu);
2846 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2847}
2848
2849void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2850{
02daab21 2851 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2852 kvm_put_guest_fpu(vcpu);
6f526ec5 2853 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2854}
2855
313a3dc7
CO		 2856static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2857 struct kvm_lapic_state *s)
2858{
5a71785d 2859 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2860 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2861
2862 return 0;
2863}
2864
2865static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2866 struct kvm_lapic_state *s)
2867{
64eb0620 2868 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2869 update_cr8_intercept(vcpu);
313a3dc7
CO		 2870
2871 return 0;
2872}
2873
f77bc6a4
ZX		 2874static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2875 struct kvm_interrupt *irq)
2876{
02cdb50f 2877 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2878 return -EINVAL;
2879 if (irqchip_in_kernel(vcpu->kvm))
2880 return -ENXIO;
f77bc6a4 2881
66fd3f7f 2882 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2883 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2884
f77bc6a4
ZX		 2885 return 0;
2886}
2887
c4abb7c9
JK		 2888static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2889{
c4abb7c9 2890 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2891
2892 return 0;
2893}
2894
b209749f
AK		 2895static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2896 struct kvm_tpr_access_ctl *tac)
2897{
2898 if (tac->flags)
2899 return -EINVAL;
2900 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2901 return 0;
2902}
2903
890ca9ae
HY		 2904static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2905 u64 mcg_cap)
2906{
2907 int r;
2908 unsigned bank_num = mcg_cap & 0xff, bank;
2909
2910 r = -EINVAL;
a9e38c3e 2911 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2912 goto out;
2913 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2914 goto out;
2915 r = 0;
2916 vcpu->arch.mcg_cap = mcg_cap;
2917 /* Init IA32_MCG_CTL to all 1s */
2918 if (mcg_cap & MCG_CTL_P)
2919 vcpu->arch.mcg_ctl = ~(u64)0;
2920 /* Init IA32_MCi_CTL to all 1s */
2921 for (bank = 0; bank < bank_num; bank++)
2922 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2923out:
2924 return r;
2925}
2926
2927static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2928 struct kvm_x86_mce *mce)
2929{
2930 u64 mcg_cap = vcpu->arch.mcg_cap;
2931 unsigned bank_num = mcg_cap & 0xff;
2932 u64 *banks = vcpu->arch.mce_banks;
2933
2934 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2935 return -EINVAL;
2936 /*
2937 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2938 * reporting is disabled
2939 */
2940 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2941 vcpu->arch.mcg_ctl != ~(u64)0)
2942 return 0;
2943 banks += 4 * mce->bank;
2944 /*
2945 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2946 * reporting is disabled for the bank
2947 */
2948 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2949 return 0;
2950 if (mce->status & MCI_STATUS_UC) {
2951 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2952 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2953 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2954 return 0;
2955 }
2956 if (banks[1] & MCI_STATUS_VAL)
2957 mce->status |= MCI_STATUS_OVER;
2958 banks[2] = mce->addr;
2959 banks[3] = mce->misc;
2960 vcpu->arch.mcg_status = mce->mcg_status;
2961 banks[1] = mce->status;
2962 kvm_queue_exception(vcpu, MC_VECTOR);
2963 } else if (!(banks[1] & MCI_STATUS_VAL)
2964 || !(banks[1] & MCI_STATUS_UC)) {
2965 if (banks[1] & MCI_STATUS_VAL)
2966 mce->status |= MCI_STATUS_OVER;
2967 banks[2] = mce->addr;
2968 banks[3] = mce->misc;
2969 banks[1] = mce->status;
2970 } else
2971 banks[1] |= MCI_STATUS_OVER;
2972 return 0;
2973}
2974
3cfc3092
JK		 2975static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2976 struct kvm_vcpu_events *events)
2977{
7460fb4a 2978 process_nmi(vcpu);
03b82a30
JK		 2979 events->exception.injected =
2980 vcpu->arch.exception.pending &&
2981 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2982 events->exception.nr = vcpu->arch.exception.nr;
2983 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2984 events->exception.pad = 0;
3cfc3092
JK		 2985 events->exception.error_code = vcpu->arch.exception.error_code;
2986
03b82a30
JK		 2987 events->interrupt.injected =
2988 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2989 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2990 events->interrupt.soft = 0;
37ccdcbe 2991 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2992
2993 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2994 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2995 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2996 events->nmi.pad = 0;
3cfc3092 2997
66450a21 2998 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2999
dab4b911 3000 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3001 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3002 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3003}
3004
3005static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3006 struct kvm_vcpu_events *events)
3007{
dab4b911 3008 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3009 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3010 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3011 return -EINVAL;
3012
7460fb4a 3013 process_nmi(vcpu);
3cfc3092
JK		 3014 vcpu->arch.exception.pending = events->exception.injected;
3015 vcpu->arch.exception.nr = events->exception.nr;
3016 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3017 vcpu->arch.exception.error_code = events->exception.error_code;
3018
3019 vcpu->arch.interrupt.pending = events->interrupt.injected;
3020 vcpu->arch.interrupt.nr = events->interrupt.nr;
3021 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3022 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3023 kvm_x86_ops->set_interrupt_shadow(vcpu,
3024 events->interrupt.shadow);
3cfc3092
JK		 3025
3026 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3027 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3028 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3029 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3030
66450a21
JK		 3031 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3032 kvm_vcpu_has_lapic(vcpu))
3033 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3034
3842d135
AK		 3035 kvm_make_request(KVM_REQ_EVENT, vcpu);
3036
3cfc3092
JK		 3037 return 0;
3038}
3039
a1efbe77
JK		 3040static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3041 struct kvm_debugregs *dbgregs)
3042{
73aaf249
JK		 3043 unsigned long val;
3044
a1efbe77 3045 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3046 _kvm_get_dr(vcpu, 6, &val);
3047 dbgregs->dr6 = val;
a1efbe77
JK		 3048 dbgregs->dr7 = vcpu->arch.dr7;
3049 dbgregs->flags = 0;
97e69aa6 3050 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3051}
3052
3053static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3054 struct kvm_debugregs *dbgregs)
3055{
3056 if (dbgregs->flags)
3057 return -EINVAL;
3058
a1efbe77
JK		 3059 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3060 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3061 kvm_update_dr6(vcpu);
a1efbe77 3062 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3063 kvm_update_dr7(vcpu);
a1efbe77 3064
a1efbe77
JK		 3065 return 0;
3066}
3067
2d5b5a66
SY		 3068static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3069 struct kvm_xsave *guest_xsave)
3070{
4344ee98 3071 if (cpu_has_xsave) {
2d5b5a66
SY		 3072 memcpy(guest_xsave->region,
3073 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3074 vcpu->arch.guest_xstate_size);
3075 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3076 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3077 } else {
2d5b5a66
SY		 3078 memcpy(guest_xsave->region,
3079 &vcpu->arch.guest_fpu.state->fxsave,
3080 sizeof(struct i387_fxsave_struct));
3081 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3082 XSTATE_FPSSE;
3083 }
3084}
3085
3086static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3087 struct kvm_xsave *guest_xsave)
3088{
3089 u64 xstate_bv =
3090 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3091
d7876f1b
PB		 3092 if (cpu_has_xsave) {
3093 /*
3094 * Here we allow setting states that are not present in
3095 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3096 * with old userspace.
3097 */
4ff41732 3098 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3099 return -EINVAL;
2d5b5a66 3100 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3101 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3102 } else {
2d5b5a66
SY		 3103 if (xstate_bv & ~XSTATE_FPSSE)
3104 return -EINVAL;
3105 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3106 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3107 }
3108 return 0;
3109}
3110
3111static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3112 struct kvm_xcrs *guest_xcrs)
3113{
3114 if (!cpu_has_xsave) {
3115 guest_xcrs->nr_xcrs = 0;
3116 return;
3117 }
3118
3119 guest_xcrs->nr_xcrs = 1;
3120 guest_xcrs->flags = 0;
3121 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3122 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3123}
3124
3125static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3126 struct kvm_xcrs *guest_xcrs)
3127{
3128 int i, r = 0;
3129
3130 if (!cpu_has_xsave)
3131 return -EINVAL;
3132
3133 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3134 return -EINVAL;
3135
3136 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3137 /* Only support XCR0 currently */
c67a04cb 3138 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3139 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3140 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3141 break;
3142 }
3143 if (r)
3144 r = -EINVAL;
3145 return r;
3146}
3147
1c0b28c2
EM		 3148/*
3149 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3150 * stopped by the hypervisor. This function will be called from the host only.
3151 * EINVAL is returned when the host attempts to set the flag for a guest that
3152 * does not support pv clocks.
3153 */
3154static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3155{
0b79459b 3156 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3157 return -EINVAL;
51d59c6b 3158 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3159 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3160 return 0;
3161}
3162
313a3dc7
CO		 3163long kvm_arch_vcpu_ioctl(struct file *filp,
3164 unsigned int ioctl, unsigned long arg)
3165{
3166 struct kvm_vcpu *vcpu = filp->private_data;
3167 void __user *argp = (void __user *)arg;
3168 int r;
d1ac91d8
AK		 3169 union {
3170 struct kvm_lapic_state *lapic;
3171 struct kvm_xsave *xsave;
3172 struct kvm_xcrs *xcrs;
3173 void *buffer;
3174 } u;
3175
3176 u.buffer = NULL;
313a3dc7
CO		 3177 switch (ioctl) {
3178 case KVM_GET_LAPIC: {
2204ae3c
MT		 3179 r = -EINVAL;
3180 if (!vcpu->arch.apic)
3181 goto out;
d1ac91d8 3182 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3183
b772ff36 3184 r = -ENOMEM;
d1ac91d8 3185 if (!u.lapic)
b772ff36 3186 goto out;
d1ac91d8 3187 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3188 if (r)
3189 goto out;
3190 r = -EFAULT;
d1ac91d8 3191 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3192 goto out;
3193 r = 0;
3194 break;
3195 }
3196 case KVM_SET_LAPIC: {
2204ae3c
MT		 3197 r = -EINVAL;
3198 if (!vcpu->arch.apic)
3199 goto out;
ff5c2c03 3200 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3201 if (IS_ERR(u.lapic))
3202 return PTR_ERR(u.lapic);
ff5c2c03 3203
d1ac91d8 3204 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3205 break;
3206 }
f77bc6a4
ZX		 3207 case KVM_INTERRUPT: {
3208 struct kvm_interrupt irq;
3209
3210 r = -EFAULT;
3211 if (copy_from_user(&irq, argp, sizeof irq))
3212 goto out;
3213 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3214 break;
3215 }
c4abb7c9
JK		 3216 case KVM_NMI: {
3217 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3218 break;
3219 }
313a3dc7
CO		 3220 case KVM_SET_CPUID: {
3221 struct kvm_cpuid __user *cpuid_arg = argp;
3222 struct kvm_cpuid cpuid;
3223
3224 r = -EFAULT;
3225 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3226 goto out;
3227 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3228 break;
3229 }
07716717
DK		 3230 case KVM_SET_CPUID2: {
3231 struct kvm_cpuid2 __user *cpuid_arg = argp;
3232 struct kvm_cpuid2 cpuid;
3233
3234 r = -EFAULT;
3235 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3236 goto out;
3237 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3238 cpuid_arg->entries);
07716717
DK		 3239 break;
3240 }
3241 case KVM_GET_CPUID2: {
3242 struct kvm_cpuid2 __user *cpuid_arg = argp;
3243 struct kvm_cpuid2 cpuid;
3244
3245 r = -EFAULT;
3246 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3247 goto out;
3248 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3249 cpuid_arg->entries);
07716717
DK		 3250 if (r)
3251 goto out;
3252 r = -EFAULT;
3253 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3254 goto out;
3255 r = 0;
3256 break;
3257 }
313a3dc7
CO		 3258 case KVM_GET_MSRS:
3259 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3260 break;
3261 case KVM_SET_MSRS:
3262 r = msr_io(vcpu, argp, do_set_msr, 0);
3263 break;
b209749f
AK		 3264 case KVM_TPR_ACCESS_REPORTING: {
3265 struct kvm_tpr_access_ctl tac;
3266
3267 r = -EFAULT;
3268 if (copy_from_user(&tac, argp, sizeof tac))
3269 goto out;
3270 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3271 if (r)
3272 goto out;
3273 r = -EFAULT;
3274 if (copy_to_user(argp, &tac, sizeof tac))
3275 goto out;
3276 r = 0;
3277 break;
3278 };
b93463aa
AK		 3279 case KVM_SET_VAPIC_ADDR: {
3280 struct kvm_vapic_addr va;
3281
3282 r = -EINVAL;
3283 if (!irqchip_in_kernel(vcpu->kvm))
3284 goto out;
3285 r = -EFAULT;
3286 if (copy_from_user(&va, argp, sizeof va))
3287 goto out;
fda4e2e8 3288 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3289 break;
3290 }
890ca9ae
HY		 3291 case KVM_X86_SETUP_MCE: {
3292 u64 mcg_cap;
3293
3294 r = -EFAULT;
3295 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3296 goto out;
3297 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3298 break;
3299 }
3300 case KVM_X86_SET_MCE: {
3301 struct kvm_x86_mce mce;
3302
3303 r = -EFAULT;
3304 if (copy_from_user(&mce, argp, sizeof mce))
3305 goto out;
3306 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3307 break;
3308 }
3cfc3092
JK		 3309 case KVM_GET_VCPU_EVENTS: {
3310 struct kvm_vcpu_events events;
3311
3312 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3313
3314 r = -EFAULT;
3315 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3316 break;
3317 r = 0;
3318 break;
3319 }
3320 case KVM_SET_VCPU_EVENTS: {
3321 struct kvm_vcpu_events events;
3322
3323 r = -EFAULT;
3324 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3325 break;
3326
3327 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3328 break;
3329 }
a1efbe77
JK		 3330 case KVM_GET_DEBUGREGS: {
3331 struct kvm_debugregs dbgregs;
3332
3333 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3334
3335 r = -EFAULT;
3336 if (copy_to_user(argp, &dbgregs,
3337 sizeof(struct kvm_debugregs)))
3338 break;
3339 r = 0;
3340 break;
3341 }
3342 case KVM_SET_DEBUGREGS: {
3343 struct kvm_debugregs dbgregs;
3344
3345 r = -EFAULT;
3346 if (copy_from_user(&dbgregs, argp,
3347 sizeof(struct kvm_debugregs)))
3348 break;
3349
3350 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3351 break;
3352 }
2d5b5a66 3353 case KVM_GET_XSAVE: {
d1ac91d8 3354 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3355 r = -ENOMEM;
d1ac91d8 3356 if (!u.xsave)
2d5b5a66
SY		 3357 break;
3358
d1ac91d8 3359 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3360
3361 r = -EFAULT;
d1ac91d8 3362 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3363 break;
3364 r = 0;
3365 break;
3366 }
3367 case KVM_SET_XSAVE: {
ff5c2c03 3368 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3369 if (IS_ERR(u.xsave))
3370 return PTR_ERR(u.xsave);
2d5b5a66 3371
d1ac91d8 3372 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3373 break;
3374 }
3375 case KVM_GET_XCRS: {
d1ac91d8 3376 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3377 r = -ENOMEM;
d1ac91d8 3378 if (!u.xcrs)
2d5b5a66
SY		 3379 break;
3380
d1ac91d8 3381 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3382
3383 r = -EFAULT;
d1ac91d8 3384 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3385 sizeof(struct kvm_xcrs)))
3386 break;
3387 r = 0;
3388 break;
3389 }
3390 case KVM_SET_XCRS: {
ff5c2c03 3391 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3392 if (IS_ERR(u.xcrs))
3393 return PTR_ERR(u.xcrs);
2d5b5a66 3394
d1ac91d8 3395 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3396 break;
3397 }
92a1f12d
JR		 3398 case KVM_SET_TSC_KHZ: {
3399 u32 user_tsc_khz;
3400
3401 r = -EINVAL;
92a1f12d
JR		 3402 user_tsc_khz = (u32)arg;
3403
3404 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3405 goto out;
3406
cc578287
ZA		 3407 if (user_tsc_khz == 0)
3408 user_tsc_khz = tsc_khz;
3409
3410 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3411
3412 r = 0;
3413 goto out;
3414 }
3415 case KVM_GET_TSC_KHZ: {
cc578287 3416 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3417 goto out;
3418 }
1c0b28c2
EM		 3419 case KVM_KVMCLOCK_CTRL: {
3420 r = kvm_set_guest_paused(vcpu);
3421 goto out;
3422 }
313a3dc7
CO		 3423 default:
3424 r = -EINVAL;
3425 }
3426out:
d1ac91d8 3427 kfree(u.buffer);
313a3dc7
CO		 3428 return r;
3429}
3430
5b1c1493
CO		 3431int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3432{
3433 return VM_FAULT_SIGBUS;
3434}
3435
1fe779f8
CO		 3436static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3437{
3438 int ret;
3439
3440 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3441 return -EINVAL;
1fe779f8
CO		 3442 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3443 return ret;
3444}
3445
b927a3ce
SY		 3446static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3447 u64 ident_addr)
3448{
3449 kvm->arch.ept_identity_map_addr = ident_addr;
3450 return 0;
3451}
3452
1fe779f8
CO		 3453static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3454 u32 kvm_nr_mmu_pages)
3455{
3456 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3457 return -EINVAL;
3458
79fac95e 3459 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3460
3461 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3462 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3463
79fac95e 3464 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3465 return 0;
3466}
3467
3468static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3469{
39de71ec 3470 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3471}
3472
1fe779f8
CO		 3473static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3474{
3475 int r;
3476
3477 r = 0;
3478 switch (chip->chip_id) {
3479 case KVM_IRQCHIP_PIC_MASTER:
3480 memcpy(&chip->chip.pic,
3481 &pic_irqchip(kvm)->pics[0],
3482 sizeof(struct kvm_pic_state));
3483 break;
3484 case KVM_IRQCHIP_PIC_SLAVE:
3485 memcpy(&chip->chip.pic,
3486 &pic_irqchip(kvm)->pics[1],
3487 sizeof(struct kvm_pic_state));
3488 break;
3489 case KVM_IRQCHIP_IOAPIC:
eba0226b 3490 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3491 break;
3492 default:
3493 r = -EINVAL;
3494 break;
3495 }
3496 return r;
3497}
3498
3499static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3500{
3501 int r;
3502
3503 r = 0;
3504 switch (chip->chip_id) {
3505 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3506 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3507 memcpy(&pic_irqchip(kvm)->pics[0],
3508 &chip->chip.pic,
3509 sizeof(struct kvm_pic_state));
f4f51050 3510 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3511 break;
3512 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3513 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3514 memcpy(&pic_irqchip(kvm)->pics[1],
3515 &chip->chip.pic,
3516 sizeof(struct kvm_pic_state));
f4f51050 3517 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3518 break;
3519 case KVM_IRQCHIP_IOAPIC:
eba0226b 3520 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3521 break;
3522 default:
3523 r = -EINVAL;
3524 break;
3525 }
3526 kvm_pic_update_irq(pic_irqchip(kvm));
3527 return r;
3528}
3529
e0f63cb9
SY		 3530static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3531{
3532 int r = 0;
3533
894a9c55 3534 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3535 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3536 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3537 return r;
3538}
3539
3540static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3541{
3542 int r = 0;
3543
894a9c55 3544 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3545 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3546 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3547 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3548 return r;
3549}
3550
3551static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3552{
3553 int r = 0;
3554
3555 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3556 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3557 sizeof(ps->channels));
3558 ps->flags = kvm->arch.vpit->pit_state.flags;
3559 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3560 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3561 return r;
3562}
3563
3564static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3565{
3566 int r = 0, start = 0;
3567 u32 prev_legacy, cur_legacy;
3568 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3569 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3570 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3571 if (!prev_legacy && cur_legacy)
3572 start = 1;
3573 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3574 sizeof(kvm->arch.vpit->pit_state.channels));
3575 kvm->arch.vpit->pit_state.flags = ps->flags;
3576 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3577 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3578 return r;
3579}
3580
52d939a0
MT		 3581static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3582 struct kvm_reinject_control *control)
3583{
3584 if (!kvm->arch.vpit)
3585 return -ENXIO;
894a9c55 3586 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3587 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3588 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3589 return 0;
3590}
3591
95d4c16c 3592/**
60c34612
TY		 3593 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3594 * @kvm: kvm instance
3595 * @log: slot id and address to which we copy the log
95d4c16c 3596 *
60c34612
TY		 3597 * We need to keep it in mind that VCPU threads can write to the bitmap
3598 * concurrently. So, to avoid losing data, we keep the following order for
3599 * each bit:
95d4c16c 3600 *
60c34612
TY		 3601 * 1. Take a snapshot of the bit and clear it if needed.
3602 * 2. Write protect the corresponding page.
3603 * 3. Flush TLB's if needed.
3604 * 4. Copy the snapshot to the userspace.
95d4c16c 3605 *
60c34612
TY		 3606 * Between 2 and 3, the guest may write to the page using the remaining TLB
3607 * entry. This is not a problem because the page will be reported dirty at
3608 * step 4 using the snapshot taken before and step 3 ensures that successive
3609 * writes will be logged for the next call.
5bb064dc 3610 */
60c34612 3611int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3612{
7850ac54 3613 int r;
5bb064dc 3614 struct kvm_memory_slot *memslot;
60c34612
TY		 3615 unsigned long n, i;
3616 unsigned long *dirty_bitmap;
3617 unsigned long *dirty_bitmap_buffer;
3618 bool is_dirty = false;
5bb064dc 3619
79fac95e 3620 mutex_lock(&kvm->slots_lock);
5bb064dc 3621
b050b015 3622 r = -EINVAL;
bbacc0c1 3623 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3624 goto out;
3625
28a37544 3626 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3627
3628 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3629 r = -ENOENT;
60c34612 3630 if (!dirty_bitmap)
b050b015
MT		 3631 goto out;
3632
87bf6e7d 3633 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3634
60c34612
TY		 3635 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3636 memset(dirty_bitmap_buffer, 0, n);
b050b015 3637
60c34612 3638 spin_lock(&kvm->mmu_lock);
b050b015 3639
60c34612
TY		 3640 for (i = 0; i < n / sizeof(long); i++) {
3641 unsigned long mask;
3642 gfn_t offset;
cdfca7b3 3643
60c34612
TY		 3644 if (!dirty_bitmap[i])
3645 continue;
b050b015 3646
60c34612 3647 is_dirty = true;
914ebccd 3648
60c34612
TY		 3649 mask = xchg(&dirty_bitmap[i], 0);
3650 dirty_bitmap_buffer[i] = mask;
edde99ce 3651
60c34612
TY		 3652 offset = i * BITS_PER_LONG;
3653 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3654 }
60c34612
TY		 3655
3656 spin_unlock(&kvm->mmu_lock);
3657
198c74f4
XG		 3658 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3659 lockdep_assert_held(&kvm->slots_lock);
3660
3661 /*
3662 * All the TLBs can be flushed out of mmu lock, see the comments in
3663 * kvm_mmu_slot_remove_write_access().
3664 */
3665 if (is_dirty)
3666 kvm_flush_remote_tlbs(kvm);
3667
60c34612
TY		 3668 r = -EFAULT;
3669 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3670 goto out;
b050b015 3671
5bb064dc
ZX		 3672 r = 0;
3673out:
79fac95e 3674 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3675 return r;
3676}
3677
aa2fbe6d
YZ		 3678int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3679 bool line_status)
23d43cf9
CD		 3680{
3681 if (!irqchip_in_kernel(kvm))
3682 return -ENXIO;
3683
3684 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3685 irq_event->irq, irq_event->level,
3686 line_status);
23d43cf9
CD		 3687 return 0;
3688}
3689
1fe779f8
CO		 3690long kvm_arch_vm_ioctl(struct file *filp,
3691 unsigned int ioctl, unsigned long arg)
3692{
3693 struct kvm *kvm = filp->private_data;
3694 void __user *argp = (void __user *)arg;
367e1319 3695 int r = -ENOTTY;
f0d66275
DH		 3696 /*
3697 * This union makes it completely explicit to gcc-3.x
3698 * that these two variables' stack usage should be
3699 * combined, not added together.
3700 */
3701 union {
3702 struct kvm_pit_state ps;
e9f42757 3703 struct kvm_pit_state2 ps2;
c5ff41ce 3704 struct kvm_pit_config pit_config;
f0d66275 3705 } u;
1fe779f8
CO		 3706
3707 switch (ioctl) {
3708 case KVM_SET_TSS_ADDR:
3709 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3710 break;
b927a3ce
SY		 3711 case KVM_SET_IDENTITY_MAP_ADDR: {
3712 u64 ident_addr;
3713
3714 r = -EFAULT;
3715 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3716 goto out;
3717 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3718 break;
3719 }
1fe779f8
CO		 3720 case KVM_SET_NR_MMU_PAGES:
3721 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3722 break;
3723 case KVM_GET_NR_MMU_PAGES:
3724 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3725 break;
3ddea128
MT		 3726 case KVM_CREATE_IRQCHIP: {
3727 struct kvm_pic *vpic;
3728
3729 mutex_lock(&kvm->lock);
3730 r = -EEXIST;
3731 if (kvm->arch.vpic)
3732 goto create_irqchip_unlock;
3e515705
AK		 3733 r = -EINVAL;
3734 if (atomic_read(&kvm->online_vcpus))
3735 goto create_irqchip_unlock;
1fe779f8 3736 r = -ENOMEM;
3ddea128
MT		 3737 vpic = kvm_create_pic(kvm);
3738 if (vpic) {
1fe779f8
CO		 3739 r = kvm_ioapic_init(kvm);
3740 if (r) {
175504cd 3741 mutex_lock(&kvm->slots_lock);
72bb2fcd 3742 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3743 &vpic->dev_master);
3744 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3745 &vpic->dev_slave);
3746 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3747 &vpic->dev_eclr);
175504cd 3748 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3749 kfree(vpic);
3750 goto create_irqchip_unlock;
1fe779f8
CO		 3751 }
3752 } else
3ddea128
MT		 3753 goto create_irqchip_unlock;
3754 smp_wmb();
3755 kvm->arch.vpic = vpic;
3756 smp_wmb();
399ec807
AK		 3757 r = kvm_setup_default_irq_routing(kvm);
3758 if (r) {
175504cd 3759 mutex_lock(&kvm->slots_lock);
3ddea128 3760 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3761 kvm_ioapic_destroy(kvm);
3762 kvm_destroy_pic(kvm);
3ddea128 3763 mutex_unlock(&kvm->irq_lock);
175504cd 3764 mutex_unlock(&kvm->slots_lock);
399ec807 3765 }
3ddea128
MT		 3766 create_irqchip_unlock:
3767 mutex_unlock(&kvm->lock);
1fe779f8 3768 break;
3ddea128 3769 }
7837699f 3770 case KVM_CREATE_PIT:
c5ff41ce
JK		 3771 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3772 goto create_pit;
3773 case KVM_CREATE_PIT2:
3774 r = -EFAULT;
3775 if (copy_from_user(&u.pit_config, argp,
3776 sizeof(struct kvm_pit_config)))
3777 goto out;
3778 create_pit:
79fac95e 3779 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3780 r = -EEXIST;
3781 if (kvm->arch.vpit)
3782 goto create_pit_unlock;
7837699f 3783 r = -ENOMEM;
c5ff41ce 3784 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3785 if (kvm->arch.vpit)
3786 r = 0;
269e05e4 3787 create_pit_unlock:
79fac95e 3788 mutex_unlock(&kvm->slots_lock);
7837699f 3789 break;
1fe779f8
CO		 3790 case KVM_GET_IRQCHIP: {
3791 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3792 struct kvm_irqchip *chip;
1fe779f8 3793
ff5c2c03
SL		 3794 chip = memdup_user(argp, sizeof(*chip));
3795 if (IS_ERR(chip)) {
3796 r = PTR_ERR(chip);
1fe779f8 3797 goto out;
ff5c2c03
SL		 3798 }
3799
1fe779f8
CO		 3800 r = -ENXIO;
3801 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3802 goto get_irqchip_out;
3803 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3804 if (r)
f0d66275 3805 goto get_irqchip_out;
1fe779f8 3806 r = -EFAULT;
f0d66275
DH		 3807 if (copy_to_user(argp, chip, sizeof *chip))
3808 goto get_irqchip_out;
1fe779f8 3809 r = 0;
f0d66275
DH		 3810 get_irqchip_out:
3811 kfree(chip);
1fe779f8
CO		 3812 break;
3813 }
3814 case KVM_SET_IRQCHIP: {
3815 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3816 struct kvm_irqchip *chip;
1fe779f8 3817
ff5c2c03
SL		 3818 chip = memdup_user(argp, sizeof(*chip));
3819 if (IS_ERR(chip)) {
3820 r = PTR_ERR(chip);
1fe779f8 3821 goto out;
ff5c2c03
SL		 3822 }
3823
1fe779f8
CO		 3824 r = -ENXIO;
3825 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3826 goto set_irqchip_out;
3827 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3828 if (r)
f0d66275 3829 goto set_irqchip_out;
1fe779f8 3830 r = 0;
f0d66275
DH		 3831 set_irqchip_out:
3832 kfree(chip);
1fe779f8
CO		 3833 break;
3834 }
e0f63cb9 3835 case KVM_GET_PIT: {
e0f63cb9 3836 r = -EFAULT;
f0d66275 3837 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3838 goto out;
3839 r = -ENXIO;
3840 if (!kvm->arch.vpit)
3841 goto out;
f0d66275 3842 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3843 if (r)
3844 goto out;
3845 r = -EFAULT;
f0d66275 3846 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3847 goto out;
3848 r = 0;
3849 break;
3850 }
3851 case KVM_SET_PIT: {
e0f63cb9 3852 r = -EFAULT;
f0d66275 3853 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3854 goto out;
3855 r = -ENXIO;
3856 if (!kvm->arch.vpit)
3857 goto out;
f0d66275 3858 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3859 break;
3860 }
e9f42757
BK		 3861 case KVM_GET_PIT2: {
3862 r = -ENXIO;
3863 if (!kvm->arch.vpit)
3864 goto out;
3865 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3866 if (r)
3867 goto out;
3868 r = -EFAULT;
3869 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3870 goto out;
3871 r = 0;
3872 break;
3873 }
3874 case KVM_SET_PIT2: {
3875 r = -EFAULT;
3876 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3877 goto out;
3878 r = -ENXIO;
3879 if (!kvm->arch.vpit)
3880 goto out;
3881 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3882 break;
3883 }
52d939a0
MT		 3884 case KVM_REINJECT_CONTROL: {
3885 struct kvm_reinject_control control;
3886 r = -EFAULT;
3887 if (copy_from_user(&control, argp, sizeof(control)))
3888 goto out;
3889 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3890 break;
3891 }
ffde22ac
ES		 3892 case KVM_XEN_HVM_CONFIG: {
3893 r = -EFAULT;
3894 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3895 sizeof(struct kvm_xen_hvm_config)))
3896 goto out;
3897 r = -EINVAL;
3898 if (kvm->arch.xen_hvm_config.flags)
3899 goto out;
3900 r = 0;
3901 break;
3902 }
afbcf7ab 3903 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3904 struct kvm_clock_data user_ns;
3905 u64 now_ns;
3906 s64 delta;
3907
3908 r = -EFAULT;
3909 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3910 goto out;
3911
3912 r = -EINVAL;
3913 if (user_ns.flags)
3914 goto out;
3915
3916 r = 0;
395c6b0a 3917 local_irq_disable();
759379dd 3918 now_ns = get_kernel_ns();
afbcf7ab 3919 delta = user_ns.clock - now_ns;
395c6b0a 3920 local_irq_enable();
afbcf7ab 3921 kvm->arch.kvmclock_offset = delta;
2e762ff7 3922 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3923 break;
3924 }
3925 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3926 struct kvm_clock_data user_ns;
3927 u64 now_ns;
3928
395c6b0a 3929 local_irq_disable();
759379dd 3930 now_ns = get_kernel_ns();
afbcf7ab 3931 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3932 local_irq_enable();
afbcf7ab 3933 user_ns.flags = 0;
97e69aa6 3934 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3935
3936 r = -EFAULT;
3937 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3938 goto out;
3939 r = 0;
3940 break;
3941 }
3942
1fe779f8
CO		 3943 default:
3944 ;
3945 }
3946out:
3947 return r;
3948}
3949
a16b043c 3950static void kvm_init_msr_list(void)
043405e1
CO		 3951{
3952 u32 dummy[2];
3953 unsigned i, j;
3954
e3267cbb
GC		 3955 /* skip the first msrs in the list. KVM-specific */
3956 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3957 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3958 continue;
93c4adc7
PB		 3959
3960 /*
3961 * Even MSRs that are valid in the host may not be exposed
3962 * to the guests in some cases. We could work around this
3963 * in VMX with the generic MSR save/load machinery, but it
3964 * is not really worthwhile since it will really only
3965 * happen with nested virtualization.
3966 */
3967 switch (msrs_to_save[i]) {
3968 case MSR_IA32_BNDCFGS:
3969 if (!kvm_x86_ops->mpx_supported())
3970 continue;
3971 break;
3972 default:
3973 break;
3974 }
3975
043405e1
CO		 3976 if (j < i)
3977 msrs_to_save[j] = msrs_to_save[i];
3978 j++;
3979 }
3980 num_msrs_to_save = j;
3981}
3982
bda9020e
MT		 3983static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3984 const void *v)
bbd9b64e 3985{
70252a10
AK		 3986 int handled = 0;
3987 int n;
3988
3989 do {
3990 n = min(len, 8);
3991 if (!(vcpu->arch.apic &&
3992 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3993 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3994 break;
3995 handled += n;
3996 addr += n;
3997 len -= n;
3998 v += n;
3999 } while (len);
bbd9b64e 4000
70252a10 4001 return handled;
bbd9b64e
CO		 4002}
4003
bda9020e 4004static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4005{
70252a10
AK		 4006 int handled = 0;
4007 int n;
4008
4009 do {
4010 n = min(len, 8);
4011 if (!(vcpu->arch.apic &&
4012 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4013 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4014 break;
4015 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4016 handled += n;
4017 addr += n;
4018 len -= n;
4019 v += n;
4020 } while (len);
bbd9b64e 4021
70252a10 4022 return handled;
bbd9b64e
CO		 4023}
4024
2dafc6c2
GN		 4025static void kvm_set_segment(struct kvm_vcpu *vcpu,
4026 struct kvm_segment *var, int seg)
4027{
4028 kvm_x86_ops->set_segment(vcpu, var, seg);
4029}
4030
4031void kvm_get_segment(struct kvm_vcpu *vcpu,
4032 struct kvm_segment *var, int seg)
4033{
4034 kvm_x86_ops->get_segment(vcpu, var, seg);
4035}
4036
e459e322 4037gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 4038{
4039 gpa_t t_gpa;
ab9ae313 4040 struct x86_exception exception;
02f59dc9
JR		 4041
4042 BUG_ON(!mmu_is_nested(vcpu));
4043
4044 /* NPT walks are always user-walks */
4045 access |= PFERR_USER_MASK;
ab9ae313 4046 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 4047
4048 return t_gpa;
4049}
4050
ab9ae313
AK		 4051gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4052 struct x86_exception *exception)
1871c602
GN		 4053{
4054 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4055 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4056}
4057
ab9ae313
AK		 4058 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4059 struct x86_exception *exception)
1871c602
GN		 4060{
4061 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4062 access |= PFERR_FETCH_MASK;
ab9ae313 4063 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4064}
4065
ab9ae313
AK		 4066gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4067 struct x86_exception *exception)
1871c602
GN		 4068{
4069 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4070 access |= PFERR_WRITE_MASK;
ab9ae313 4071 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4072}
4073
4074/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4075gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4076 struct x86_exception *exception)
1871c602 4077{
ab9ae313 4078 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4079}
4080
4081static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4082 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4083 struct x86_exception *exception)
bbd9b64e
CO		 4084{
4085 void *data = val;
10589a46 4086 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4087
4088 while (bytes) {
14dfe855 4089 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4090 exception);
bbd9b64e 4091 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4092 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4093 int ret;
4094
bcc55cba 4095 if (gpa == UNMAPPED_GVA)
ab9ae313 4096 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4097 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4098 offset, toread);
10589a46 4099 if (ret < 0) {
c3cd7ffa 4100 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4101 goto out;
4102 }
bbd9b64e 4103
77c2002e
IE		 4104 bytes -= toread;
4105 data += toread;
4106 addr += toread;
bbd9b64e 4107 }
10589a46 4108out:
10589a46 4109 return r;
bbd9b64e 4110}
77c2002e 4111
1871c602 4112/* used for instruction fetching */
0f65dd70
AK		 4113static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4114 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4115 struct x86_exception *exception)
1871c602 4116{
0f65dd70 4117 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4118 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4119 unsigned offset;
4120 int ret;
0f65dd70 4121
44583cba
PB		 4122 /* Inline kvm_read_guest_virt_helper for speed. */
4123 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4124 exception);
4125 if (unlikely(gpa == UNMAPPED_GVA))
4126 return X86EMUL_PROPAGATE_FAULT;
4127
4128 offset = addr & (PAGE_SIZE-1);
4129 if (WARN_ON(offset + bytes > PAGE_SIZE))
4130 bytes = (unsigned)PAGE_SIZE - offset;
4131 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4132 offset, bytes);
4133 if (unlikely(ret < 0))
4134 return X86EMUL_IO_NEEDED;
4135
4136 return X86EMUL_CONTINUE;
1871c602
GN		 4137}
4138
064aea77 4139int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4140 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4141 struct x86_exception *exception)
1871c602 4142{
0f65dd70 4143 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4144 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4145
1871c602 4146 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4147 exception);
1871c602 4148}
064aea77 4149EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4150
0f65dd70
AK		 4151static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4152 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4153 struct x86_exception *exception)
1871c602 4154{
0f65dd70 4155 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4156 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4157}
4158
6a4d7550 4159int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4160 gva_t addr, void *val,
2dafc6c2 4161 unsigned int bytes,
bcc55cba 4162 struct x86_exception *exception)
77c2002e 4163{
0f65dd70 4164 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4165 void *data = val;
4166 int r = X86EMUL_CONTINUE;
4167
4168 while (bytes) {
14dfe855
JR		 4169 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4170 PFERR_WRITE_MASK,
ab9ae313 4171 exception);
77c2002e
IE		 4172 unsigned offset = addr & (PAGE_SIZE-1);
4173 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4174 int ret;
4175
bcc55cba 4176 if (gpa == UNMAPPED_GVA)
ab9ae313 4177 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4178 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4179 if (ret < 0) {
c3cd7ffa 4180 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4181 goto out;
4182 }
4183
4184 bytes -= towrite;
4185 data += towrite;
4186 addr += towrite;
4187 }
4188out:
4189 return r;
4190}
6a4d7550 4191EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4192
af7cc7d1
XG		 4193static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4194 gpa_t *gpa, struct x86_exception *exception,
4195 bool write)
4196{
97d64b78
AK		 4197 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4198 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4199
97d64b78 4200 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4201 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4202 vcpu->arch.access, access)) {
bebb106a
XG		 4203 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4204 (gva & (PAGE_SIZE - 1));
4f022648 4205 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4206 return 1;
4207 }
4208
af7cc7d1
XG		 4209 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4210
4211 if (*gpa == UNMAPPED_GVA)
4212 return -1;
4213
4214 /* For APIC access vmexit */
4215 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4216 return 1;
4217
4f022648
XG		 4218 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4219 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4220 return 1;
4f022648 4221 }
bebb106a 4222
af7cc7d1
XG		 4223 return 0;
4224}
4225
3200f405 4226int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4227 const void *val, int bytes)
bbd9b64e
CO		 4228{
4229 int ret;
4230
4231 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4232 if (ret < 0)
bbd9b64e 4233 return 0;
f57f2ef5 4234 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4235 return 1;
4236}
4237
77d197b2
XG		 4238struct read_write_emulator_ops {
4239 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4240 int bytes);
4241 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4242 void *val, int bytes);
4243 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4244 int bytes, void *val);
4245 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4246 void *val, int bytes);
4247 bool write;
4248};
4249
4250static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4251{
4252 if (vcpu->mmio_read_completed) {
77d197b2 4253 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4254 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4255 vcpu->mmio_read_completed = 0;
4256 return 1;
4257 }
4258
4259 return 0;
4260}
4261
4262static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4263 void *val, int bytes)
4264{
4265 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4266}
4267
4268static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4269 void *val, int bytes)
4270{
4271 return emulator_write_phys(vcpu, gpa, val, bytes);
4272}
4273
4274static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4275{
4276 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4277 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4278}
4279
4280static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4281 void *val, int bytes)
4282{
4283 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4284 return X86EMUL_IO_NEEDED;
4285}
4286
4287static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4288 void *val, int bytes)
4289{
f78146b0
AK		 4290 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4291
87da7e66 4292 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4293 return X86EMUL_CONTINUE;
4294}
4295
0fbe9b0b 4296static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4297 .read_write_prepare = read_prepare,
4298 .read_write_emulate = read_emulate,
4299 .read_write_mmio = vcpu_mmio_read,
4300 .read_write_exit_mmio = read_exit_mmio,
4301};
4302
0fbe9b0b 4303static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4304 .read_write_emulate = write_emulate,
4305 .read_write_mmio = write_mmio,
4306 .read_write_exit_mmio = write_exit_mmio,
4307 .write = true,
4308};
4309
22388a3c
XG		 4310static int emulator_read_write_onepage(unsigned long addr, void *val,
4311 unsigned int bytes,
4312 struct x86_exception *exception,
4313 struct kvm_vcpu *vcpu,
0fbe9b0b 4314 const struct read_write_emulator_ops *ops)
bbd9b64e 4315{
af7cc7d1
XG		 4316 gpa_t gpa;
4317 int handled, ret;
22388a3c 4318 bool write = ops->write;
f78146b0 4319 struct kvm_mmio_fragment *frag;
10589a46 4320
22388a3c 4321 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4322
af7cc7d1 4323 if (ret < 0)
bbd9b64e 4324 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4325
4326 /* For APIC access vmexit */
af7cc7d1 4327 if (ret)
bbd9b64e
CO		 4328 goto mmio;
4329
22388a3c 4330 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4331 return X86EMUL_CONTINUE;
4332
4333mmio:
4334 /*
4335 * Is this MMIO handled locally?
4336 */
22388a3c 4337 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4338 if (handled == bytes)
bbd9b64e 4339 return X86EMUL_CONTINUE;
bbd9b64e 4340
70252a10
AK		 4341 gpa += handled;
4342 bytes -= handled;
4343 val += handled;
4344
87da7e66
XG		 4345 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4346 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4347 frag->gpa = gpa;
4348 frag->data = val;
4349 frag->len = bytes;
f78146b0 4350 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4351}
4352
22388a3c
XG		 4353int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4354 void *val, unsigned int bytes,
4355 struct x86_exception *exception,
0fbe9b0b 4356 const struct read_write_emulator_ops *ops)
bbd9b64e 4357{
0f65dd70 4358 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4359 gpa_t gpa;
4360 int rc;
4361
4362 if (ops->read_write_prepare &&
4363 ops->read_write_prepare(vcpu, val, bytes))
4364 return X86EMUL_CONTINUE;
4365
4366 vcpu->mmio_nr_fragments = 0;
0f65dd70 4367
bbd9b64e
CO		 4368 /* Crossing a page boundary? */
4369 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4370 int now;
bbd9b64e
CO		 4371
4372 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4373 rc = emulator_read_write_onepage(addr, val, now, exception,
4374 vcpu, ops);
4375
bbd9b64e
CO		 4376 if (rc != X86EMUL_CONTINUE)
4377 return rc;
4378 addr += now;
4379 val += now;
4380 bytes -= now;
4381 }
22388a3c 4382
f78146b0
AK		 4383 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4384 vcpu, ops);
4385 if (rc != X86EMUL_CONTINUE)
4386 return rc;
4387
4388 if (!vcpu->mmio_nr_fragments)
4389 return rc;
4390
4391 gpa = vcpu->mmio_fragments[0].gpa;
4392
4393 vcpu->mmio_needed = 1;
4394 vcpu->mmio_cur_fragment = 0;
4395
87da7e66 4396 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4397 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4398 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4399 vcpu->run->mmio.phys_addr = gpa;
4400
4401 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4402}
4403
4404static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4405 unsigned long addr,
4406 void *val,
4407 unsigned int bytes,
4408 struct x86_exception *exception)
4409{
4410 return emulator_read_write(ctxt, addr, val, bytes,
4411 exception, &read_emultor);
4412}
4413
4414int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4415 unsigned long addr,
4416 const void *val,
4417 unsigned int bytes,
4418 struct x86_exception *exception)
4419{
4420 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4421 exception, &write_emultor);
bbd9b64e 4422}
bbd9b64e 4423
daea3e73
AK		 4424#define CMPXCHG_TYPE(t, ptr, old, new) \
4425 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4426
4427#ifdef CONFIG_X86_64
4428# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4429#else
4430# define CMPXCHG64(ptr, old, new) \
9749a6c0 4431 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4432#endif
4433
0f65dd70
AK		 4434static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4435 unsigned long addr,
bbd9b64e
CO		 4436 const void *old,
4437 const void *new,
4438 unsigned int bytes,
0f65dd70 4439 struct x86_exception *exception)
bbd9b64e 4440{
0f65dd70 4441 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4442 gpa_t gpa;
4443 struct page *page;
4444 char *kaddr;
4445 bool exchanged;
2bacc55c 4446
daea3e73
AK		 4447 /* guests cmpxchg8b have to be emulated atomically */
4448 if (bytes > 8 || (bytes & (bytes - 1)))
4449 goto emul_write;
10589a46 4450
daea3e73 4451 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4452
daea3e73
AK		 4453 if (gpa == UNMAPPED_GVA ||
4454 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4455 goto emul_write;
2bacc55c 4456
daea3e73
AK		 4457 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4458 goto emul_write;
72dc67a6 4459
daea3e73 4460 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4461 if (is_error_page(page))
c19b8bd6 4462 goto emul_write;
72dc67a6 4463
8fd75e12 4464 kaddr = kmap_atomic(page);
daea3e73
AK		 4465 kaddr += offset_in_page(gpa);
4466 switch (bytes) {
4467 case 1:
4468 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4469 break;
4470 case 2:
4471 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4472 break;
4473 case 4:
4474 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4475 break;
4476 case 8:
4477 exchanged = CMPXCHG64(kaddr, old, new);
4478 break;
4479 default:
4480 BUG();
2bacc55c 4481 }
8fd75e12 4482 kunmap_atomic(kaddr);
daea3e73
AK		 4483 kvm_release_page_dirty(page);
4484
4485 if (!exchanged)
4486 return X86EMUL_CMPXCHG_FAILED;
4487
d3714010 4488 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4489 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4490
4491 return X86EMUL_CONTINUE;
4a5f48f6 4492
3200f405 4493emul_write:
daea3e73 4494 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4495
0f65dd70 4496 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4497}
4498
cf8f70bf
GN		 4499static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4500{
4501 /* TODO: String I/O for in kernel device */
4502 int r;
4503
4504 if (vcpu->arch.pio.in)
4505 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4506 vcpu->arch.pio.size, pd);
4507 else
4508 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4509 vcpu->arch.pio.port, vcpu->arch.pio.size,
4510 pd);
4511 return r;
4512}
4513
6f6fbe98
XG		 4514static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4515 unsigned short port, void *val,
4516 unsigned int count, bool in)
cf8f70bf 4517{
cf8f70bf 4518 vcpu->arch.pio.port = port;
6f6fbe98 4519 vcpu->arch.pio.in = in;
7972995b 4520 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4521 vcpu->arch.pio.size = size;
4522
4523 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4524 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4525 return 1;
4526 }
4527
4528 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4529 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4530 vcpu->run->io.size = size;
4531 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4532 vcpu->run->io.count = count;
4533 vcpu->run->io.port = port;
4534
4535 return 0;
4536}
4537
6f6fbe98
XG		 4538static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4539 int size, unsigned short port, void *val,
4540 unsigned int count)
cf8f70bf 4541{
ca1d4a9e 4542 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4543 int ret;
ca1d4a9e 4544
6f6fbe98
XG		 4545 if (vcpu->arch.pio.count)
4546 goto data_avail;
cf8f70bf 4547
6f6fbe98
XG		 4548 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4549 if (ret) {
4550data_avail:
4551 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4552 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4553 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4554 return 1;
4555 }
4556
cf8f70bf
GN		 4557 return 0;
4558}
4559
6f6fbe98
XG		 4560static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4561 int size, unsigned short port,
4562 const void *val, unsigned int count)
4563{
4564 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4565
4566 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4567 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4568 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4569}
4570
bbd9b64e
CO		 4571static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4572{
4573 return kvm_x86_ops->get_segment_base(vcpu, seg);
4574}
4575
3cb16fe7 4576static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4577{
3cb16fe7 4578 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4579}
4580
f5f48ee1
SY		 4581int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4582{
4583 if (!need_emulate_wbinvd(vcpu))
4584 return X86EMUL_CONTINUE;
4585
4586 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4587 int cpu = get_cpu();
4588
4589 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4590 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4591 wbinvd_ipi, NULL, 1);
2eec7343 4592 put_cpu();
f5f48ee1 4593 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4594 } else
4595 wbinvd();
f5f48ee1
SY		 4596 return X86EMUL_CONTINUE;
4597}
4598EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4599
bcaf5cc5
AK		 4600static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4601{
4602 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4603}
4604
717746e3 4605int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4606{
717746e3 4607 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4608}
4609
717746e3 4610int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4611{
338dbc97 4612
717746e3 4613 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4614}
4615
52a46617 4616static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4617{
52a46617 4618 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4619}
4620
717746e3 4621static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4622{
717746e3 4623 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4624 unsigned long value;
4625
4626 switch (cr) {
4627 case 0:
4628 value = kvm_read_cr0(vcpu);
4629 break;
4630 case 2:
4631 value = vcpu->arch.cr2;
4632 break;
4633 case 3:
9f8fe504 4634 value = kvm_read_cr3(vcpu);
52a46617
GN		 4635 break;
4636 case 4:
4637 value = kvm_read_cr4(vcpu);
4638 break;
4639 case 8:
4640 value = kvm_get_cr8(vcpu);
4641 break;
4642 default:
a737f256 4643 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4644 return 0;
4645 }
4646
4647 return value;
4648}
4649
717746e3 4650static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4651{
717746e3 4652 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4653 int res = 0;
4654
52a46617
GN		 4655 switch (cr) {
4656 case 0:
49a9b07e 4657 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4658 break;
4659 case 2:
4660 vcpu->arch.cr2 = val;
4661 break;
4662 case 3:
2390218b 4663 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4664 break;
4665 case 4:
a83b29c6 4666 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4667 break;
4668 case 8:
eea1cff9 4669 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4670 break;
4671 default:
a737f256 4672 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4673 res = -1;
52a46617 4674 }
0f12244f
GN		 4675
4676 return res;
52a46617
GN		 4677}
4678
717746e3 4679static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4680{
717746e3 4681 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4682}
4683
4bff1e86 4684static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4685{
4bff1e86 4686 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4687}
4688
4bff1e86 4689static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4690{
4bff1e86 4691 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4692}
4693
1ac9d0cf
AK		 4694static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4695{
4696 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4697}
4698
4699static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4700{
4701 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4702}
4703
4bff1e86
AK		 4704static unsigned long emulator_get_cached_segment_base(
4705 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4706{
4bff1e86 4707 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4708}
4709
1aa36616
AK		 4710static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4711 struct desc_struct *desc, u32 *base3,
4712 int seg)
2dafc6c2
GN		 4713{
4714 struct kvm_segment var;
4715
4bff1e86 4716 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4717 *selector = var.selector;
2dafc6c2 4718
378a8b09
GN		 4719 if (var.unusable) {
4720 memset(desc, 0, sizeof(*desc));
2dafc6c2 4721 return false;
378a8b09 4722 }
2dafc6c2
GN		 4723
4724 if (var.g)
4725 var.limit >>= 12;
4726 set_desc_limit(desc, var.limit);
4727 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4728#ifdef CONFIG_X86_64
4729 if (base3)
4730 *base3 = var.base >> 32;
4731#endif
2dafc6c2
GN		 4732 desc->type = var.type;
4733 desc->s = var.s;
4734 desc->dpl = var.dpl;
4735 desc->p = var.present;
4736 desc->avl = var.avl;
4737 desc->l = var.l;
4738 desc->d = var.db;
4739 desc->g = var.g;
4740
4741 return true;
4742}
4743
1aa36616
AK		 4744static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4745 struct desc_struct *desc, u32 base3,
4746 int seg)
2dafc6c2 4747{
4bff1e86 4748 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4749 struct kvm_segment var;
4750
1aa36616 4751 var.selector = selector;
2dafc6c2 4752 var.base = get_desc_base(desc);
5601d05b
GN		 4753#ifdef CONFIG_X86_64
4754 var.base |= ((u64)base3) << 32;
4755#endif
2dafc6c2
GN		 4756 var.limit = get_desc_limit(desc);
4757 if (desc->g)
4758 var.limit = (var.limit << 12) | 0xfff;
4759 var.type = desc->type;
2dafc6c2
GN		 4760 var.dpl = desc->dpl;
4761 var.db = desc->d;
4762 var.s = desc->s;
4763 var.l = desc->l;
4764 var.g = desc->g;
4765 var.avl = desc->avl;
4766 var.present = desc->p;
4767 var.unusable = !var.present;
4768 var.padding = 0;
4769
4770 kvm_set_segment(vcpu, &var, seg);
4771 return;
4772}
4773
717746e3
AK		 4774static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4775 u32 msr_index, u64 *pdata)
4776{
4777 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4778}
4779
4780static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4781 u32 msr_index, u64 data)
4782{
8fe8ab46
WA		 4783 struct msr_data msr;
4784
4785 msr.data = data;
4786 msr.index = msr_index;
4787 msr.host_initiated = false;
4788 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4789}
4790
67f4d428
NA		 4791static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4792 u32 pmc)
4793{
4794 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4795}
4796
222d21aa
AK		 4797static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4798 u32 pmc, u64 *pdata)
4799{
4800 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4801}
4802
6c3287f7
AK		 4803static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4804{
4805 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4806}
4807
5037f6f3
AK		 4808static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4809{
4810 preempt_disable();
5197b808 4811 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4812 /*
4813 * CR0.TS may reference the host fpu state, not the guest fpu state,
4814 * so it may be clear at this point.
4815 */
4816 clts();
4817}
4818
4819static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4820{
4821 preempt_enable();
4822}
4823
2953538e 4824static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4825 struct x86_instruction_info *info,
c4f035c6
AK		 4826 enum x86_intercept_stage stage)
4827{
2953538e 4828 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4829}
4830
0017f93a 4831static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4832 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4833{
0017f93a 4834 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4835}
4836
dd856efa
AK		 4837static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4838{
4839 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4840}
4841
4842static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4843{
4844 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4845}
4846
0225fb50 4847static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4848 .read_gpr = emulator_read_gpr,
4849 .write_gpr = emulator_write_gpr,
1871c602 4850 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4851 .write_std = kvm_write_guest_virt_system,
1871c602 4852 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4853 .read_emulated = emulator_read_emulated,
4854 .write_emulated = emulator_write_emulated,
4855 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4856 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4857 .pio_in_emulated = emulator_pio_in_emulated,
4858 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4859 .get_segment = emulator_get_segment,
4860 .set_segment = emulator_set_segment,
5951c442 4861 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4862 .get_gdt = emulator_get_gdt,
160ce1f1 4863 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4864 .set_gdt = emulator_set_gdt,
4865 .set_idt = emulator_set_idt,
52a46617
GN		 4866 .get_cr = emulator_get_cr,
4867 .set_cr = emulator_set_cr,
9c537244 4868 .cpl = emulator_get_cpl,
35aa5375
GN		 4869 .get_dr = emulator_get_dr,
4870 .set_dr = emulator_set_dr,
717746e3
AK		 4871 .set_msr = emulator_set_msr,
4872 .get_msr = emulator_get_msr,
67f4d428 4873 .check_pmc = emulator_check_pmc,
222d21aa 4874 .read_pmc = emulator_read_pmc,
6c3287f7 4875 .halt = emulator_halt,
bcaf5cc5 4876 .wbinvd = emulator_wbinvd,
d6aa1000 4877 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4878 .get_fpu = emulator_get_fpu,
4879 .put_fpu = emulator_put_fpu,
c4f035c6 4880 .intercept = emulator_intercept,
bdb42f5a 4881 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4882};
4883
95cb2295
GN		 4884static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4885{
37ccdcbe 4886 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4887 /*
4888 * an sti; sti; sequence only disable interrupts for the first
4889 * instruction. So, if the last instruction, be it emulated or
4890 * not, left the system with the INT_STI flag enabled, it
4891 * means that the last instruction is an sti. We should not
4892 * leave the flag on in this case. The same goes for mov ss
4893 */
37ccdcbe
PB		 4894 if (int_shadow & mask)
4895 mask = 0;
6addfc42 4896 if (unlikely(int_shadow || mask)) {
95cb2295 4897 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4898 if (!mask)
4899 kvm_make_request(KVM_REQ_EVENT, vcpu);
4900 }
95cb2295
GN		 4901}
4902
54b8486f
GN		 4903static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4904{
4905 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4906 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4907 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4908 else if (ctxt->exception.error_code_valid)
4909 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4910 ctxt->exception.error_code);
54b8486f 4911 else
da9cb575 4912 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4913}
4914
8ec4722d
MG		 4915static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4916{
adf52235 4917 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4918 int cs_db, cs_l;
4919
8ec4722d
MG		 4920 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4921
adf52235
TY		 4922 ctxt->eflags = kvm_get_rflags(vcpu);
4923 ctxt->eip = kvm_rip_read(vcpu);
4924 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4925 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4926 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4927 cs_db ? X86EMUL_MODE_PROT32 :
4928 X86EMUL_MODE_PROT16;
4929 ctxt->guest_mode = is_guest_mode(vcpu);
4930
dd856efa 4931 init_decode_cache(ctxt);
7ae441ea 4932 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4933}
4934
71f9833b 4935int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4936{
9d74191a 4937 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4938 int ret;
4939
4940 init_emulate_ctxt(vcpu);
4941
9dac77fa
AK		 4942 ctxt->op_bytes = 2;
4943 ctxt->ad_bytes = 2;
4944 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4945 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4946
4947 if (ret != X86EMUL_CONTINUE)
4948 return EMULATE_FAIL;
4949
9dac77fa 4950 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4951 kvm_rip_write(vcpu, ctxt->eip);
4952 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4953
4954 if (irq == NMI_VECTOR)
7460fb4a 4955 vcpu->arch.nmi_pending = 0;
63995653
MG		 4956 else
4957 vcpu->arch.interrupt.pending = false;
4958
4959 return EMULATE_DONE;
4960}
4961EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4962
6d77dbfc
GN		 4963static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4964{
fc3a9157
JR		 4965 int r = EMULATE_DONE;
4966
6d77dbfc
GN		 4967 ++vcpu->stat.insn_emulation_fail;
4968 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4969 if (!is_guest_mode(vcpu)) {
4970 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4971 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4972 vcpu->run->internal.ndata = 0;
4973 r = EMULATE_FAIL;
4974 }
6d77dbfc 4975 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4976
4977 return r;
6d77dbfc
GN		 4978}
4979
93c05d3e 4980static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4981 bool write_fault_to_shadow_pgtable,
4982 int emulation_type)
a6f177ef 4983{
95b3cf69 4984 gpa_t gpa = cr2;
8e3d9d06 4985 pfn_t pfn;
a6f177ef 4986
991eebf9
GN		 4987 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4988 return false;
4989
95b3cf69
XG		 4990 if (!vcpu->arch.mmu.direct_map) {
4991 /*
4992 * Write permission should be allowed since only
4993 * write access need to be emulated.
4994 */
4995 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4996
95b3cf69
XG		 4997 /*
4998 * If the mapping is invalid in guest, let cpu retry
4999 * it to generate fault.
5000 */
5001 if (gpa == UNMAPPED_GVA)
5002 return true;
5003 }
a6f177ef 5004
8e3d9d06
XG		 5005 /*
5006 * Do not retry the unhandleable instruction if it faults on the
5007 * readonly host memory, otherwise it will goto a infinite loop:
5008 * retry instruction -> write #PF -> emulation fail -> retry
5009 * instruction -> ...
5010 */
5011 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5012
5013 /*
5014 * If the instruction failed on the error pfn, it can not be fixed,
5015 * report the error to userspace.
5016 */
5017 if (is_error_noslot_pfn(pfn))
5018 return false;
5019
5020 kvm_release_pfn_clean(pfn);
5021
5022 /* The instructions are well-emulated on direct mmu. */
5023 if (vcpu->arch.mmu.direct_map) {
5024 unsigned int indirect_shadow_pages;
5025
5026 spin_lock(&vcpu->kvm->mmu_lock);
5027 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5028 spin_unlock(&vcpu->kvm->mmu_lock);
5029
5030 if (indirect_shadow_pages)
5031 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5032
a6f177ef 5033 return true;
8e3d9d06 5034 }
a6f177ef 5035
95b3cf69
XG		 5036 /*
5037 * if emulation was due to access to shadowed page table
5038 * and it failed try to unshadow page and re-enter the
5039 * guest to let CPU execute the instruction.
5040 */
5041 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5042
5043 /*
5044 * If the access faults on its page table, it can not
5045 * be fixed by unprotecting shadow page and it should
5046 * be reported to userspace.
5047 */
5048 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5049}
5050
1cb3f3ae
XG		 5051static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5052 unsigned long cr2, int emulation_type)
5053{
5054 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5055 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5056
5057 last_retry_eip = vcpu->arch.last_retry_eip;
5058 last_retry_addr = vcpu->arch.last_retry_addr;
5059
5060 /*
5061 * If the emulation is caused by #PF and it is non-page_table
5062 * writing instruction, it means the VM-EXIT is caused by shadow
5063 * page protected, we can zap the shadow page and retry this
5064 * instruction directly.
5065 *
5066 * Note: if the guest uses a non-page-table modifying instruction
5067 * on the PDE that points to the instruction, then we will unmap
5068 * the instruction and go to an infinite loop. So, we cache the
5069 * last retried eip and the last fault address, if we meet the eip
5070 * and the address again, we can break out of the potential infinite
5071 * loop.
5072 */
5073 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5074
5075 if (!(emulation_type & EMULTYPE_RETRY))
5076 return false;
5077
5078 if (x86_page_table_writing_insn(ctxt))
5079 return false;
5080
5081 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5082 return false;
5083
5084 vcpu->arch.last_retry_eip = ctxt->eip;
5085 vcpu->arch.last_retry_addr = cr2;
5086
5087 if (!vcpu->arch.mmu.direct_map)
5088 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5089
22368028 5090 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5091
5092 return true;
5093}
5094
716d51ab
GN		 5095static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5096static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5097
4a1e10d5
PB		 5098static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5099 unsigned long *db)
5100{
5101 u32 dr6 = 0;
5102 int i;
5103 u32 enable, rwlen;
5104
5105 enable = dr7;
5106 rwlen = dr7 >> 16;
5107 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5108 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5109 dr6 |= (1 << i);
5110 return dr6;
5111}
5112
6addfc42 5113static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5114{
5115 struct kvm_run *kvm_run = vcpu->run;
5116
5117 /*
6addfc42
PB		 5118 * rflags is the old, "raw" value of the flags. The new value has
5119 * not been saved yet.
663f4c61
PB		 5120 *
5121 * This is correct even for TF set by the guest, because "the
5122 * processor will not generate this exception after the instruction
5123 * that sets the TF flag".
5124 */
663f4c61
PB		 5125 if (unlikely(rflags & X86_EFLAGS_TF)) {
5126 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5127 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5128 DR6_RTM;
663f4c61
PB		 5129 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5130 kvm_run->debug.arch.exception = DB_VECTOR;
5131 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5132 *r = EMULATE_USER_EXIT;
5133 } else {
5134 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5135 /*
5136 * "Certain debug exceptions may clear bit 0-3. The
5137 * remaining contents of the DR6 register are never
5138 * cleared by the processor".
5139 */
5140 vcpu->arch.dr6 &= ~15;
6f43ed01 5141 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5142 kvm_queue_exception(vcpu, DB_VECTOR);
5143 }
5144 }
5145}
5146
4a1e10d5
PB		 5147static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5148{
5149 struct kvm_run *kvm_run = vcpu->run;
5150 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5151 u32 dr6 = 0;
5152
5153 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5154 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5155 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5156 vcpu->arch.guest_debug_dr7,
5157 vcpu->arch.eff_db);
5158
5159 if (dr6 != 0) {
6f43ed01 5160 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
4a1e10d5
PB		 5161 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5162 get_segment_base(vcpu, VCPU_SREG_CS);
5163
5164 kvm_run->debug.arch.exception = DB_VECTOR;
5165 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5166 *r = EMULATE_USER_EXIT;
5167 return true;
5168 }
5169 }
5170
4161a569
NA		 5171 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5172 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
4a1e10d5
PB		 5173 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5174 vcpu->arch.dr7,
5175 vcpu->arch.db);
5176
5177 if (dr6 != 0) {
5178 vcpu->arch.dr6 &= ~15;
6f43ed01 5179 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5180 kvm_queue_exception(vcpu, DB_VECTOR);
5181 *r = EMULATE_DONE;
5182 return true;
5183 }
5184 }
5185
5186 return false;
5187}
5188
51d8b661
AP		 5189int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5190 unsigned long cr2,
dc25e89e
AP		 5191 int emulation_type,
5192 void *insn,
5193 int insn_len)
bbd9b64e 5194{
95cb2295 5195 int r;
9d74191a 5196 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5197 bool writeback = true;
93c05d3e 5198 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5199
93c05d3e
XG		 5200 /*
5201 * Clear write_fault_to_shadow_pgtable here to ensure it is
5202 * never reused.
5203 */
5204 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5205 kvm_clear_exception_queue(vcpu);
8d7d8102 5206
571008da 5207 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5208 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5209
5210 /*
5211 * We will reenter on the same instruction since
5212 * we do not set complete_userspace_io. This does not
5213 * handle watchpoints yet, those would be handled in
5214 * the emulate_ops.
5215 */
5216 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5217 return r;
5218
9d74191a
TY		 5219 ctxt->interruptibility = 0;
5220 ctxt->have_exception = false;
5221 ctxt->perm_ok = false;
bbd9b64e 5222
b51e974f 5223 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5224
9d74191a 5225 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5226
e46479f8 5227 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5228 ++vcpu->stat.insn_emulation;
1d2887e2 5229 if (r != EMULATION_OK) {
4005996e
AK		 5230 if (emulation_type & EMULTYPE_TRAP_UD)
5231 return EMULATE_FAIL;
991eebf9
GN		 5232 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5233 emulation_type))
bbd9b64e 5234 return EMULATE_DONE;
6d77dbfc
GN		 5235 if (emulation_type & EMULTYPE_SKIP)
5236 return EMULATE_FAIL;
5237 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5238 }
5239 }
5240
ba8afb6b 5241 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5242 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5243 if (ctxt->eflags & X86_EFLAGS_RF)
5244 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5245 return EMULATE_DONE;
5246 }
5247
1cb3f3ae
XG		 5248 if (retry_instruction(ctxt, cr2, emulation_type))
5249 return EMULATE_DONE;
5250
7ae441ea 5251 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5252 changes registers values during IO operation */
7ae441ea
GN		 5253 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5254 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5255 emulator_invalidate_register_cache(ctxt);
7ae441ea 5256 }
4d2179e1 5257
5cd21917 5258restart:
9d74191a 5259 r = x86_emulate_insn(ctxt);
bbd9b64e 5260
775fde86
JR		 5261 if (r == EMULATION_INTERCEPTED)
5262 return EMULATE_DONE;
5263
d2ddd1c4 5264 if (r == EMULATION_FAILED) {
991eebf9
GN		 5265 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5266 emulation_type))
c3cd7ffa
GN		 5267 return EMULATE_DONE;
5268
6d77dbfc 5269 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5270 }
5271
9d74191a 5272 if (ctxt->have_exception) {
54b8486f 5273 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5274 r = EMULATE_DONE;
5275 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5276 if (!vcpu->arch.pio.in) {
5277 /* FIXME: return into emulator if single-stepping. */
3457e419 5278 vcpu->arch.pio.count = 0;
0912c977 5279 } else {
7ae441ea 5280 writeback = false;
716d51ab
GN		 5281 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5282 }
ac0a48c3 5283 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5284 } else if (vcpu->mmio_needed) {
5285 if (!vcpu->mmio_is_write)
5286 writeback = false;
ac0a48c3 5287 r = EMULATE_USER_EXIT;
716d51ab 5288 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5289 } else if (r == EMULATION_RESTART)
5cd21917 5290 goto restart;
d2ddd1c4
GN		 5291 else
5292 r = EMULATE_DONE;
f850e2e6 5293
7ae441ea 5294 if (writeback) {
6addfc42 5295 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5296 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5297 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5298 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5299 if (r == EMULATE_DONE)
6addfc42
PB		 5300 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5301 __kvm_set_rflags(vcpu, ctxt->eflags);
5302
5303 /*
5304 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5305 * do nothing, and it will be requested again as soon as
5306 * the shadow expires. But we still need to check here,
5307 * because POPF has no interrupt shadow.
5308 */
5309 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5310 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5311 } else
5312 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5313
5314 return r;
de7d789a 5315}
51d8b661 5316EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5317
cf8f70bf 5318int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5319{
cf8f70bf 5320 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5321 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5322 size, port, &val, 1);
cf8f70bf 5323 /* do not return to emulator after return from userspace */
7972995b 5324 vcpu->arch.pio.count = 0;
de7d789a
CO		 5325 return ret;
5326}
cf8f70bf 5327EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5328
8cfdc000
ZA		 5329static void tsc_bad(void *info)
5330{
0a3aee0d 5331 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5332}
5333
5334static void tsc_khz_changed(void *data)
c8076604 5335{
8cfdc000
ZA		 5336 struct cpufreq_freqs *freq = data;
5337 unsigned long khz = 0;
5338
5339 if (data)
5340 khz = freq->new;
5341 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5342 khz = cpufreq_quick_get(raw_smp_processor_id());
5343 if (!khz)
5344 khz = tsc_khz;
0a3aee0d 5345 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5346}
5347
c8076604
GH		 5348static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5349 void *data)
5350{
5351 struct cpufreq_freqs *freq = data;
5352 struct kvm *kvm;
5353 struct kvm_vcpu *vcpu;
5354 int i, send_ipi = 0;
5355
8cfdc000
ZA		 5356 /*
5357 * We allow guests to temporarily run on slowing clocks,
5358 * provided we notify them after, or to run on accelerating
5359 * clocks, provided we notify them before. Thus time never
5360 * goes backwards.
5361 *
5362 * However, we have a problem. We can't atomically update
5363 * the frequency of a given CPU from this function; it is
5364 * merely a notifier, which can be called from any CPU.
5365 * Changing the TSC frequency at arbitrary points in time
5366 * requires a recomputation of local variables related to
5367 * the TSC for each VCPU. We must flag these local variables
5368 * to be updated and be sure the update takes place with the
5369 * new frequency before any guests proceed.
5370 *
5371 * Unfortunately, the combination of hotplug CPU and frequency
5372 * change creates an intractable locking scenario; the order
5373 * of when these callouts happen is undefined with respect to
5374 * CPU hotplug, and they can race with each other. As such,
5375 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5376 * undefined; you can actually have a CPU frequency change take
5377 * place in between the computation of X and the setting of the
5378 * variable. To protect against this problem, all updates of
5379 * the per_cpu tsc_khz variable are done in an interrupt
5380 * protected IPI, and all callers wishing to update the value
5381 * must wait for a synchronous IPI to complete (which is trivial
5382 * if the caller is on the CPU already). This establishes the
5383 * necessary total order on variable updates.
5384 *
5385 * Note that because a guest time update may take place
5386 * anytime after the setting of the VCPU's request bit, the
5387 * correct TSC value must be set before the request. However,
5388 * to ensure the update actually makes it to any guest which
5389 * starts running in hardware virtualization between the set
5390 * and the acquisition of the spinlock, we must also ping the
5391 * CPU after setting the request bit.
5392 *
5393 */
5394
c8076604
GH		 5395 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5396 return 0;
5397 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5398 return 0;
8cfdc000
ZA		 5399
5400 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5401
2f303b74 5402 spin_lock(&kvm_lock);
c8076604 5403 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5404 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5405 if (vcpu->cpu != freq->cpu)
5406 continue;
c285545f 5407 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5408 if (vcpu->cpu != smp_processor_id())
8cfdc000 5409 send_ipi = 1;
c8076604
GH		 5410 }
5411 }
2f303b74 5412 spin_unlock(&kvm_lock);
c8076604
GH		 5413
5414 if (freq->old < freq->new && send_ipi) {
5415 /*
5416 * We upscale the frequency. Must make the guest
5417 * doesn't see old kvmclock values while running with
5418 * the new frequency, otherwise we risk the guest sees
5419 * time go backwards.
5420 *
5421 * In case we update the frequency for another cpu
5422 * (which might be in guest context) send an interrupt
5423 * to kick the cpu out of guest context. Next time
5424 * guest context is entered kvmclock will be updated,
5425 * so the guest will not see stale values.
5426 */
8cfdc000 5427 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5428 }
5429 return 0;
5430}
5431
5432static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5433 .notifier_call = kvmclock_cpufreq_notifier
5434};
5435
5436static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5437 unsigned long action, void *hcpu)
5438{
5439 unsigned int cpu = (unsigned long)hcpu;
5440
5441 switch (action) {
5442 case CPU_ONLINE:
5443 case CPU_DOWN_FAILED:
5444 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5445 break;
5446 case CPU_DOWN_PREPARE:
5447 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5448 break;
5449 }
5450 return NOTIFY_OK;
5451}
5452
5453static struct notifier_block kvmclock_cpu_notifier_block = {
5454 .notifier_call = kvmclock_cpu_notifier,
5455 .priority = -INT_MAX
c8076604
GH		 5456};
5457
b820cc0c
ZA		 5458static void kvm_timer_init(void)
5459{
5460 int cpu;
5461
c285545f 5462 max_tsc_khz = tsc_khz;
460dd42e
SB		 5463
5464 cpu_notifier_register_begin();
b820cc0c 5465 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5466#ifdef CONFIG_CPU_FREQ
5467 struct cpufreq_policy policy;
5468 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5469 cpu = get_cpu();
5470 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5471 if (policy.cpuinfo.max_freq)
5472 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5473 put_cpu();
c285545f 5474#endif
b820cc0c
ZA		 5475 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5476 CPUFREQ_TRANSITION_NOTIFIER);
5477 }
c285545f 5478 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5479 for_each_online_cpu(cpu)
5480 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5481
5482 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5483 cpu_notifier_register_done();
5484
b820cc0c
ZA		 5485}
5486
ff9d07a0
ZY		 5487static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5488
f5132b01 5489int kvm_is_in_guest(void)
ff9d07a0 5490{
086c9855 5491 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5492}
5493
5494static int kvm_is_user_mode(void)
5495{
5496 int user_mode = 3;
dcf46b94 5497
086c9855
AS		 5498 if (__this_cpu_read(current_vcpu))
5499 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5500
ff9d07a0
ZY		 5501 return user_mode != 0;
5502}
5503
5504static unsigned long kvm_get_guest_ip(void)
5505{
5506 unsigned long ip = 0;
dcf46b94 5507
086c9855
AS		 5508 if (__this_cpu_read(current_vcpu))
5509 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5510
ff9d07a0
ZY		 5511 return ip;
5512}
5513
5514static struct perf_guest_info_callbacks kvm_guest_cbs = {
5515 .is_in_guest = kvm_is_in_guest,
5516 .is_user_mode = kvm_is_user_mode,
5517 .get_guest_ip = kvm_get_guest_ip,
5518};
5519
5520void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5521{
086c9855 5522 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5523}
5524EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5525
5526void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5527{
086c9855 5528 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5529}
5530EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5531
ce88decf
XG		 5532static void kvm_set_mmio_spte_mask(void)
5533{
5534 u64 mask;
5535 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5536
5537 /*
5538 * Set the reserved bits and the present bit of an paging-structure
5539 * entry to generate page fault with PFER.RSV = 1.
5540 */
885032b9
XG		 5541 /* Mask the reserved physical address bits. */
5542 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5543
5544 /* Bit 62 is always reserved for 32bit host. */
5545 mask |= 0x3ull << 62;
5546
5547 /* Set the present bit. */
ce88decf
XG		 5548 mask |= 1ull;
5549
5550#ifdef CONFIG_X86_64
5551 /*
5552 * If reserved bit is not supported, clear the present bit to disable
5553 * mmio page fault.
5554 */
5555 if (maxphyaddr == 52)
5556 mask &= ~1ull;
5557#endif
5558
5559 kvm_mmu_set_mmio_spte_mask(mask);
5560}
5561
16e8d74d
MT		 5562#ifdef CONFIG_X86_64
5563static void pvclock_gtod_update_fn(struct work_struct *work)
5564{
d828199e
MT		 5565 struct kvm *kvm;
5566
5567 struct kvm_vcpu *vcpu;
5568 int i;
5569
2f303b74 5570 spin_lock(&kvm_lock);
d828199e
MT		 5571 list_for_each_entry(kvm, &vm_list, vm_list)
5572 kvm_for_each_vcpu(i, vcpu, kvm)
5573 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5574 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5575 spin_unlock(&kvm_lock);
16e8d74d
MT		 5576}
5577
5578static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5579
5580/*
5581 * Notification about pvclock gtod data update.
5582 */
5583static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5584 void *priv)
5585{
5586 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5587 struct timekeeper *tk = priv;
5588
5589 update_pvclock_gtod(tk);
5590
5591 /* disable master clock if host does not trust, or does not
5592 * use, TSC clocksource
5593 */
5594 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5595 atomic_read(&kvm_guest_has_master_clock) != 0)
5596 queue_work(system_long_wq, &pvclock_gtod_work);
5597
5598 return 0;
5599}
5600
5601static struct notifier_block pvclock_gtod_notifier = {
5602 .notifier_call = pvclock_gtod_notify,
5603};
5604#endif
5605
f8c16bba 5606int kvm_arch_init(void *opaque)
043405e1 5607{
b820cc0c 5608 int r;
6b61edf7 5609 struct kvm_x86_ops *ops = opaque;
f8c16bba 5610
f8c16bba
ZX		 5611 if (kvm_x86_ops) {
5612 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5613 r = -EEXIST;
5614 goto out;
f8c16bba
ZX		 5615 }
5616
5617 if (!ops->cpu_has_kvm_support()) {
5618 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5619 r = -EOPNOTSUPP;
5620 goto out;
f8c16bba
ZX		 5621 }
5622 if (ops->disabled_by_bios()) {
5623 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5624 r = -EOPNOTSUPP;
5625 goto out;
f8c16bba
ZX		 5626 }
5627
013f6a5d
MT		 5628 r = -ENOMEM;
5629 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5630 if (!shared_msrs) {
5631 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5632 goto out;
5633 }
5634
97db56ce
AK		 5635 r = kvm_mmu_module_init();
5636 if (r)
013f6a5d 5637 goto out_free_percpu;
97db56ce 5638
ce88decf 5639 kvm_set_mmio_spte_mask();
97db56ce 5640
f8c16bba 5641 kvm_x86_ops = ops;
920c8377
PB		 5642 kvm_init_msr_list();
5643
7b52345e 5644 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5645 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5646
b820cc0c 5647 kvm_timer_init();
c8076604 5648
ff9d07a0
ZY		 5649 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5650
2acf923e
DC		 5651 if (cpu_has_xsave)
5652 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5653
c5cc421b 5654 kvm_lapic_init();
16e8d74d
MT		 5655#ifdef CONFIG_X86_64
5656 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5657#endif
5658
f8c16bba 5659 return 0;
56c6d28a 5660
013f6a5d
MT		 5661out_free_percpu:
5662 free_percpu(shared_msrs);
56c6d28a 5663out:
56c6d28a 5664 return r;
043405e1 5665}
8776e519 5666
f8c16bba
ZX		 5667void kvm_arch_exit(void)
5668{
ff9d07a0
ZY		 5669 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5670
888d256e
JK		 5671 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5672 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5673 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5674 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5675#ifdef CONFIG_X86_64
5676 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5677#endif
f8c16bba 5678 kvm_x86_ops = NULL;
56c6d28a 5679 kvm_mmu_module_exit();
013f6a5d 5680 free_percpu(shared_msrs);
56c6d28a 5681}
f8c16bba 5682
8776e519
HB		 5683int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5684{
5685 ++vcpu->stat.halt_exits;
5686 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5687 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5688 return 1;
5689 } else {
5690 vcpu->run->exit_reason = KVM_EXIT_HLT;
5691 return 0;
5692 }
5693}
5694EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5695
55cd8e5a
GN		 5696int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5697{
5698 u64 param, ingpa, outgpa, ret;
5699 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5700 bool fast, longmode;
55cd8e5a
GN		 5701
5702 /*
5703 * hypercall generates UD from non zero cpl and real mode
5704 * per HYPER-V spec
5705 */
3eeb3288 5706 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5707 kvm_queue_exception(vcpu, UD_VECTOR);
5708 return 0;
5709 }
5710
a449c7aa 5711 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5712
5713 if (!longmode) {
ccd46936
GN		 5714 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5715 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5716 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5717 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5718 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5719 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5720 }
5721#ifdef CONFIG_X86_64
5722 else {
5723 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5724 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5725 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5726 }
5727#endif
5728
5729 code = param & 0xffff;
5730 fast = (param >> 16) & 0x1;
5731 rep_cnt = (param >> 32) & 0xfff;
5732 rep_idx = (param >> 48) & 0xfff;
5733
5734 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5735
c25bc163
GN		 5736 switch (code) {
5737 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5738 kvm_vcpu_on_spin(vcpu);
5739 break;
5740 default:
5741 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5742 break;
5743 }
55cd8e5a
GN		 5744
5745 ret = res | (((u64)rep_done & 0xfff) << 32);
5746 if (longmode) {
5747 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5748 } else {
5749 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5750 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5751 }
5752
5753 return 1;
5754}
5755
6aef266c
SV		 5756/*
5757 * kvm_pv_kick_cpu_op: Kick a vcpu.
5758 *
5759 * @apicid - apicid of vcpu to be kicked.
5760 */
5761static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5762{
24d2166b 5763 struct kvm_lapic_irq lapic_irq;
6aef266c 5764
24d2166b
R		 5765 lapic_irq.shorthand = 0;
5766 lapic_irq.dest_mode = 0;
5767 lapic_irq.dest_id = apicid;
6aef266c 5768
24d2166b
R		 5769 lapic_irq.delivery_mode = APIC_DM_REMRD;
5770 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5771}
5772
8776e519
HB		 5773int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5774{
5775 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5776 int op_64_bit, r = 1;
8776e519 5777
55cd8e5a
GN		 5778 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5779 return kvm_hv_hypercall(vcpu);
5780
5fdbf976
MT		 5781 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5782 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5783 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5784 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5785 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5786
229456fc 5787 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5788
a449c7aa
NA		 5789 op_64_bit = is_64_bit_mode(vcpu);
5790 if (!op_64_bit) {
8776e519
HB		 5791 nr &= 0xFFFFFFFF;
5792 a0 &= 0xFFFFFFFF;
5793 a1 &= 0xFFFFFFFF;
5794 a2 &= 0xFFFFFFFF;
5795 a3 &= 0xFFFFFFFF;
5796 }
5797
07708c4a
JK		 5798 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5799 ret = -KVM_EPERM;
5800 goto out;
5801 }
5802
8776e519 5803 switch (nr) {
b93463aa
AK		 5804 case KVM_HC_VAPIC_POLL_IRQ:
5805 ret = 0;
5806 break;
6aef266c
SV		 5807 case KVM_HC_KICK_CPU:
5808 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5809 ret = 0;
5810 break;
8776e519
HB		 5811 default:
5812 ret = -KVM_ENOSYS;
5813 break;
5814 }
07708c4a 5815out:
a449c7aa
NA		 5816 if (!op_64_bit)
5817 ret = (u32)ret;
5fdbf976 5818 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5819 ++vcpu->stat.hypercalls;
2f333bcb 5820 return r;
8776e519
HB		 5821}
5822EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5823
b6785def 5824static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5825{
d6aa1000 5826 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5827 char instruction[3];
5fdbf976 5828 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5829
8776e519 5830 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5831
9d74191a 5832 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5833}
5834
b6c7a5dc
HB		 5835/*
5836 * Check if userspace requested an interrupt window, and that the
5837 * interrupt window is open.
5838 *
5839 * No need to exit to userspace if we already have an interrupt queued.
5840 */
851ba692 5841static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5842{
8061823a 5843 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5844 vcpu->run->request_interrupt_window &&
5df56646 5845 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5846}
5847
851ba692 5848static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5849{
851ba692
AK		 5850 struct kvm_run *kvm_run = vcpu->run;
5851
91586a3b 5852 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5853 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5854 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5855 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5856 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5857 else
b6c7a5dc 5858 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5859 kvm_arch_interrupt_allowed(vcpu) &&
5860 !kvm_cpu_has_interrupt(vcpu) &&
5861 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5862}
5863
95ba8273
GN		 5864static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5865{
5866 int max_irr, tpr;
5867
5868 if (!kvm_x86_ops->update_cr8_intercept)
5869 return;
5870
88c808fd
AK		 5871 if (!vcpu->arch.apic)
5872 return;
5873
8db3baa2
GN		 5874 if (!vcpu->arch.apic->vapic_addr)
5875 max_irr = kvm_lapic_find_highest_irr(vcpu);
5876 else
5877 max_irr = -1;
95ba8273
GN		 5878
5879 if (max_irr != -1)
5880 max_irr >>= 4;
5881
5882 tpr = kvm_lapic_get_cr8(vcpu);
5883
5884 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5885}
5886
b6b8a145 5887static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5888{
b6b8a145
JK		 5889 int r;
5890
95ba8273 5891 /* try to reinject previous events if any */
b59bb7bd 5892 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5893 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5894 vcpu->arch.exception.has_error_code,
5895 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5896 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5897 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5898 vcpu->arch.exception.error_code,
5899 vcpu->arch.exception.reinject);
b6b8a145 5900 return 0;
b59bb7bd
GN		 5901 }
5902
95ba8273
GN		 5903 if (vcpu->arch.nmi_injected) {
5904 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5905 return 0;
95ba8273
GN		 5906 }
5907
5908 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5909 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5910 return 0;
5911 }
5912
5913 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5914 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5915 if (r != 0)
5916 return r;
95ba8273
GN		 5917 }
5918
5919 /* try to inject new event if pending */
5920 if (vcpu->arch.nmi_pending) {
5921 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5922 --vcpu->arch.nmi_pending;
95ba8273
GN		 5923 vcpu->arch.nmi_injected = true;
5924 kvm_x86_ops->set_nmi(vcpu);
5925 }
c7c9c56c 5926 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5927 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5928 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5929 false);
5930 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5931 }
5932 }
b6b8a145 5933 return 0;
95ba8273
GN		 5934}
5935
7460fb4a
AK		 5936static void process_nmi(struct kvm_vcpu *vcpu)
5937{
5938 unsigned limit = 2;
5939
5940 /*
5941 * x86 is limited to one NMI running, and one NMI pending after it.
5942 * If an NMI is already in progress, limit further NMIs to just one.
5943 * Otherwise, allow two (and we'll inject the first one immediately).
5944 */
5945 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5946 limit = 1;
5947
5948 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5949 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5950 kvm_make_request(KVM_REQ_EVENT, vcpu);
5951}
5952
3d81bc7e 5953static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5954{
5955 u64 eoi_exit_bitmap[4];
cf9e65b7 5956 u32 tmr[8];
c7c9c56c 5957
3d81bc7e
YZ		 5958 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5959 return;
c7c9c56c
YZ		 5960
5961 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5962 memset(tmr, 0, 32);
c7c9c56c 5963
cf9e65b7 5964 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5965 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5966 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5967}
5968
9357d939
TY		 5969/*
5970 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5971 * exiting to the userspace. Otherwise, the value will be returned to the
5972 * userspace.
5973 */
851ba692 5974static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5975{
5976 int r;
6a8b1d13 5977 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5978 vcpu->run->request_interrupt_window;
730dca42 5979 bool req_immediate_exit = false;
b6c7a5dc 5980
3e007509 5981 if (vcpu->requests) {
a8eeb04a 5982 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5983 kvm_mmu_unload(vcpu);
a8eeb04a 5984 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5985 __kvm_migrate_timers(vcpu);
d828199e
MT		 5986 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5987 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5988 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5989 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5990 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5991 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5992 if (unlikely(r))
5993 goto out;
5994 }
a8eeb04a 5995 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5996 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5997 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5998 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5999 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6000 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6001 r = 0;
6002 goto out;
6003 }
a8eeb04a 6004 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6005 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6006 r = 0;
6007 goto out;
6008 }
a8eeb04a 6009 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6010 vcpu->fpu_active = 0;
6011 kvm_x86_ops->fpu_deactivate(vcpu);
6012 }
af585b92
GN		 6013 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6014 /* Page is swapped out. Do synthetic halt */
6015 vcpu->arch.apf.halted = true;
6016 r = 1;
6017 goto out;
6018 }
c9aaa895
GC		 6019 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6020 record_steal_time(vcpu);
7460fb4a
AK		 6021 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6022 process_nmi(vcpu);
f5132b01
GN		 6023 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6024 kvm_handle_pmu_event(vcpu);
6025 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6026 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6027 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6028 vcpu_scan_ioapic(vcpu);
2f52d58c 6029 }
b93463aa 6030
b463a6f7 6031 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6032 kvm_apic_accept_events(vcpu);
6033 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6034 r = 1;
6035 goto out;
6036 }
6037
b6b8a145
JK		 6038 if (inject_pending_event(vcpu, req_int_win) != 0)
6039 req_immediate_exit = true;
b463a6f7 6040 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6041 else if (vcpu->arch.nmi_pending)
c9a7953f 6042 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6043 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6044 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6045
6046 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6047 /*
6048 * Update architecture specific hints for APIC
6049 * virtual interrupt delivery.
6050 */
6051 if (kvm_x86_ops->hwapic_irr_update)
6052 kvm_x86_ops->hwapic_irr_update(vcpu,
6053 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6054 update_cr8_intercept(vcpu);
6055 kvm_lapic_sync_to_vapic(vcpu);
6056 }
6057 }
6058
d8368af8
AK		 6059 r = kvm_mmu_reload(vcpu);
6060 if (unlikely(r)) {
d905c069 6061 goto cancel_injection;
d8368af8
AK		 6062 }
6063
b6c7a5dc
HB		 6064 preempt_disable();
6065
6066 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6067 if (vcpu->fpu_active)
6068 kvm_load_guest_fpu(vcpu);
2acf923e 6069 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6070
6b7e2d09
XG		 6071 vcpu->mode = IN_GUEST_MODE;
6072
01b71917
MT		 6073 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6074
6b7e2d09
XG		 6075 /* We should set ->mode before check ->requests,
6076 * see the comment in make_all_cpus_request.
6077 */
01b71917 6078 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6079
d94e1dc9 6080 local_irq_disable();
32f88400 6081
6b7e2d09 6082 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6083 || need_resched() || signal_pending(current)) {
6b7e2d09 6084 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6085 smp_wmb();
6c142801
AK		 6086 local_irq_enable();
6087 preempt_enable();
01b71917 6088 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6089 r = 1;
d905c069 6090 goto cancel_injection;
6c142801
AK		 6091 }
6092
d6185f20
NHE		 6093 if (req_immediate_exit)
6094 smp_send_reschedule(vcpu->cpu);
6095
b6c7a5dc
HB		 6096 kvm_guest_enter();
6097
42dbaa5a 6098 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6099 set_debugreg(0, 7);
6100 set_debugreg(vcpu->arch.eff_db[0], 0);
6101 set_debugreg(vcpu->arch.eff_db[1], 1);
6102 set_debugreg(vcpu->arch.eff_db[2], 2);
6103 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6104 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6105 }
b6c7a5dc 6106
229456fc 6107 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6108 kvm_x86_ops->run(vcpu);
b6c7a5dc 6109
c77fb5fe
PB		 6110 /*
6111 * Do this here before restoring debug registers on the host. And
6112 * since we do this before handling the vmexit, a DR access vmexit
6113 * can (a) read the correct value of the debug registers, (b) set
6114 * KVM_DEBUGREG_WONT_EXIT again.
6115 */
6116 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6117 int i;
6118
6119 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6120 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6121 for (i = 0; i < KVM_NR_DB_REGS; i++)
6122 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6123 }
6124
24f1e32c
FW		 6125 /*
6126 * If the guest has used debug registers, at least dr7
6127 * will be disabled while returning to the host.
6128 * If we don't have active breakpoints in the host, we don't
6129 * care about the messed up debug address registers. But if
6130 * we have some of them active, restore the old state.
6131 */
59d8eb53 6132 if (hw_breakpoint_active())
24f1e32c 6133 hw_breakpoint_restore();
42dbaa5a 6134
886b470c
MT		 6135 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6136 native_read_tsc());
1d5f066e 6137
6b7e2d09 6138 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6139 smp_wmb();
a547c6db
YZ		 6140
6141 /* Interrupt is enabled by handle_external_intr() */
6142 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6143
6144 ++vcpu->stat.exits;
6145
6146 /*
6147 * We must have an instruction between local_irq_enable() and
6148 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6149 * the interrupt shadow. The stat.exits increment will do nicely.
6150 * But we need to prevent reordering, hence this barrier():
6151 */
6152 barrier();
6153
6154 kvm_guest_exit();
6155
6156 preempt_enable();
6157
f656ce01 6158 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6159
b6c7a5dc
HB		 6160 /*
6161 * Profile KVM exit RIPs:
6162 */
6163 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6164 unsigned long rip = kvm_rip_read(vcpu);
6165 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6166 }
6167
cc578287
ZA		 6168 if (unlikely(vcpu->arch.tsc_always_catchup))
6169 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6170
5cfb1d5a
MT		 6171 if (vcpu->arch.apic_attention)
6172 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6173
851ba692 6174 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6175 return r;
6176
6177cancel_injection:
6178 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6179 if (unlikely(vcpu->arch.apic_attention))
6180 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6181out:
6182 return r;
6183}
b6c7a5dc 6184
09cec754 6185
851ba692 6186static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6187{
6188 int r;
f656ce01 6189 struct kvm *kvm = vcpu->kvm;
d7690175 6190
f656ce01 6191 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6192
6193 r = 1;
6194 while (r > 0) {
af585b92
GN		 6195 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6196 !vcpu->arch.apf.halted)
851ba692 6197 r = vcpu_enter_guest(vcpu);
d7690175 6198 else {
f656ce01 6199 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6200 kvm_vcpu_block(vcpu);
f656ce01 6201 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6202 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6203 kvm_apic_accept_events(vcpu);
09cec754
GN		 6204 switch(vcpu->arch.mp_state) {
6205 case KVM_MP_STATE_HALTED:
6aef266c 6206 vcpu->arch.pv.pv_unhalted = false;
d7690175 6207 vcpu->arch.mp_state =
09cec754
GN		 6208 KVM_MP_STATE_RUNNABLE;
6209 case KVM_MP_STATE_RUNNABLE:
af585b92 6210 vcpu->arch.apf.halted = false;
09cec754 6211 break;
66450a21
JK		 6212 case KVM_MP_STATE_INIT_RECEIVED:
6213 break;
09cec754
GN		 6214 default:
6215 r = -EINTR;
6216 break;
6217 }
6218 }
d7690175
MT		 6219 }
6220
09cec754
GN		 6221 if (r <= 0)
6222 break;
6223
6224 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6225 if (kvm_cpu_has_pending_timer(vcpu))
6226 kvm_inject_pending_timer_irqs(vcpu);
6227
851ba692 6228 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6229 r = -EINTR;
851ba692 6230 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6231 ++vcpu->stat.request_irq_exits;
6232 }
af585b92
GN		 6233
6234 kvm_check_async_pf_completion(vcpu);
6235
09cec754
GN		 6236 if (signal_pending(current)) {
6237 r = -EINTR;
851ba692 6238 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6239 ++vcpu->stat.signal_exits;
6240 }
6241 if (need_resched()) {
f656ce01 6242 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6243 cond_resched();
f656ce01 6244 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6245 }
b6c7a5dc
HB		 6246 }
6247
f656ce01 6248 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6249
6250 return r;
6251}
6252
716d51ab
GN		 6253static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6254{
6255 int r;
6256 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6257 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6258 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6259 if (r != EMULATE_DONE)
6260 return 0;
6261 return 1;
6262}
6263
6264static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6265{
6266 BUG_ON(!vcpu->arch.pio.count);
6267
6268 return complete_emulated_io(vcpu);
6269}
6270
f78146b0
AK		 6271/*
6272 * Implements the following, as a state machine:
6273 *
6274 * read:
6275 * for each fragment
87da7e66
XG		 6276 * for each mmio piece in the fragment
6277 * write gpa, len
6278 * exit
6279 * copy data
f78146b0
AK		 6280 * execute insn
6281 *
6282 * write:
6283 * for each fragment
87da7e66
XG		 6284 * for each mmio piece in the fragment
6285 * write gpa, len
6286 * copy data
6287 * exit
f78146b0 6288 */
716d51ab 6289static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6290{
6291 struct kvm_run *run = vcpu->run;
f78146b0 6292 struct kvm_mmio_fragment *frag;
87da7e66 6293 unsigned len;
5287f194 6294
716d51ab 6295 BUG_ON(!vcpu->mmio_needed);
5287f194 6296
716d51ab 6297 /* Complete previous fragment */
87da7e66
XG		 6298 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6299 len = min(8u, frag->len);
716d51ab 6300 if (!vcpu->mmio_is_write)
87da7e66
XG		 6301 memcpy(frag->data, run->mmio.data, len);
6302
6303 if (frag->len <= 8) {
6304 /* Switch to the next fragment. */
6305 frag++;
6306 vcpu->mmio_cur_fragment++;
6307 } else {
6308 /* Go forward to the next mmio piece. */
6309 frag->data += len;
6310 frag->gpa += len;
6311 frag->len -= len;
6312 }
6313
a08d3b3b 6314 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6315 vcpu->mmio_needed = 0;
0912c977
PB		 6316
6317 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6318 if (vcpu->mmio_is_write)
716d51ab
GN		 6319 return 1;
6320 vcpu->mmio_read_completed = 1;
6321 return complete_emulated_io(vcpu);
6322 }
87da7e66 6323
716d51ab
GN		 6324 run->exit_reason = KVM_EXIT_MMIO;
6325 run->mmio.phys_addr = frag->gpa;
6326 if (vcpu->mmio_is_write)
87da7e66
XG		 6327 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6328 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6329 run->mmio.is_write = vcpu->mmio_is_write;
6330 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6331 return 0;
5287f194
AK		 6332}
6333
716d51ab 6334
b6c7a5dc
HB		 6335int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6336{
6337 int r;
6338 sigset_t sigsaved;
6339
e5c30142
AK		 6340 if (!tsk_used_math(current) && init_fpu(current))
6341 return -ENOMEM;
6342
ac9f6dc0
AK		 6343 if (vcpu->sigset_active)
6344 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6345
a4535290 6346 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6347 kvm_vcpu_block(vcpu);
66450a21 6348 kvm_apic_accept_events(vcpu);
d7690175 6349 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6350 r = -EAGAIN;
6351 goto out;
b6c7a5dc
HB		 6352 }
6353
b6c7a5dc 6354 /* re-sync apic's tpr */
eea1cff9
AP		 6355 if (!irqchip_in_kernel(vcpu->kvm)) {
6356 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6357 r = -EINVAL;
6358 goto out;
6359 }
6360 }
b6c7a5dc 6361
716d51ab
GN		 6362 if (unlikely(vcpu->arch.complete_userspace_io)) {
6363 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6364 vcpu->arch.complete_userspace_io = NULL;
6365 r = cui(vcpu);
6366 if (r <= 0)
6367 goto out;
6368 } else
6369 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6370
851ba692 6371 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6372
6373out:
f1d86e46 6374 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6375 if (vcpu->sigset_active)
6376 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6377
b6c7a5dc
HB		 6378 return r;
6379}
6380
6381int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6382{
7ae441ea
GN		 6383 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6384 /*
6385 * We are here if userspace calls get_regs() in the middle of
6386 * instruction emulation. Registers state needs to be copied
4a969980 6387 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6388 * that usually, but some bad designed PV devices (vmware
6389 * backdoor interface) need this to work
6390 */
dd856efa 6391 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6392 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6393 }
5fdbf976
MT		 6394 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6395 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6396 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6397 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6398 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6399 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6400 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6401 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6402#ifdef CONFIG_X86_64
5fdbf976
MT		 6403 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6404 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6405 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6406 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6407 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6408 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6409 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6410 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6411#endif
6412
5fdbf976 6413 regs->rip = kvm_rip_read(vcpu);
91586a3b 6414 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6415
b6c7a5dc
HB		 6416 return 0;
6417}
6418
6419int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6420{
7ae441ea
GN		 6421 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6422 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6423
5fdbf976
MT		 6424 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6425 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6426 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6427 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6428 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6429 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6430 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6431 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6432#ifdef CONFIG_X86_64
5fdbf976
MT		 6433 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6434 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6435 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6436 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6437 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6438 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6439 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6440 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6441#endif
6442
5fdbf976 6443 kvm_rip_write(vcpu, regs->rip);
91586a3b 6444 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6445
b4f14abd
JK		 6446 vcpu->arch.exception.pending = false;
6447
3842d135
AK		 6448 kvm_make_request(KVM_REQ_EVENT, vcpu);
6449
b6c7a5dc
HB		 6450 return 0;
6451}
6452
b6c7a5dc
HB		 6453void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6454{
6455 struct kvm_segment cs;
6456
3e6e0aab 6457 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6458 *db = cs.db;
6459 *l = cs.l;
6460}
6461EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6462
6463int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6464 struct kvm_sregs *sregs)
6465{
89a27f4d 6466 struct desc_ptr dt;
b6c7a5dc 6467
3e6e0aab
GT		 6468 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6469 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6470 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6471 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6472 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6473 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6474
3e6e0aab
GT		 6475 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6476 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6477
6478 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6479 sregs->idt.limit = dt.size;
6480 sregs->idt.base = dt.address;
b6c7a5dc 6481 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6482 sregs->gdt.limit = dt.size;
6483 sregs->gdt.base = dt.address;
b6c7a5dc 6484
4d4ec087 6485 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6486 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6487 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6488 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6489 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6490 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6491 sregs->apic_base = kvm_get_apic_base(vcpu);
6492
923c61bb 6493 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6494
36752c9b 6495 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6496 set_bit(vcpu->arch.interrupt.nr,
6497 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6498
b6c7a5dc
HB		 6499 return 0;
6500}
6501
62d9f0db
MT		 6502int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6503 struct kvm_mp_state *mp_state)
6504{
66450a21 6505 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6506 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6507 vcpu->arch.pv.pv_unhalted)
6508 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6509 else
6510 mp_state->mp_state = vcpu->arch.mp_state;
6511
62d9f0db
MT		 6512 return 0;
6513}
6514
6515int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6516 struct kvm_mp_state *mp_state)
6517{
66450a21
JK		 6518 if (!kvm_vcpu_has_lapic(vcpu) &&
6519 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6520 return -EINVAL;
6521
6522 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6523 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6524 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6525 } else
6526 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6527 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6528 return 0;
6529}
6530
7f3d35fd
KW		 6531int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6532 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6533{
9d74191a 6534 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6535 int ret;
e01c2426 6536
8ec4722d 6537 init_emulate_ctxt(vcpu);
c697518a 6538
7f3d35fd 6539 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6540 has_error_code, error_code);
c697518a 6541
c697518a 6542 if (ret)
19d04437 6543 return EMULATE_FAIL;
37817f29 6544
9d74191a
TY		 6545 kvm_rip_write(vcpu, ctxt->eip);
6546 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6547 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6548 return EMULATE_DONE;
37817f29
IE		 6549}
6550EXPORT_SYMBOL_GPL(kvm_task_switch);
6551
b6c7a5dc
HB		 6552int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6553 struct kvm_sregs *sregs)
6554{
58cb628d 6555 struct msr_data apic_base_msr;
b6c7a5dc 6556 int mmu_reset_needed = 0;
63f42e02 6557 int pending_vec, max_bits, idx;
89a27f4d 6558 struct desc_ptr dt;
b6c7a5dc 6559
6d1068b3
PM		 6560 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6561 return -EINVAL;
6562
89a27f4d
GN		 6563 dt.size = sregs->idt.limit;
6564 dt.address = sregs->idt.base;
b6c7a5dc 6565 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6566 dt.size = sregs->gdt.limit;
6567 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6568 kvm_x86_ops->set_gdt(vcpu, &dt);
6569
ad312c7c 6570 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6571 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6572 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6573 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6574
2d3ad1f4 6575 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6576
f6801dff 6577 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6578 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6579 apic_base_msr.data = sregs->apic_base;
6580 apic_base_msr.host_initiated = true;
6581 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6582
4d4ec087 6583 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6584 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6585 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6586
fc78f519 6587 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6588 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6589 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6590 kvm_update_cpuid(vcpu);
63f42e02
XG		 6591
6592 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6593 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6594 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6595 mmu_reset_needed = 1;
6596 }
63f42e02 6597 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6598
6599 if (mmu_reset_needed)
6600 kvm_mmu_reset_context(vcpu);
6601
a50abc3b 6602 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6603 pending_vec = find_first_bit(
6604 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6605 if (pending_vec < max_bits) {
66fd3f7f 6606 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6607 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6608 }
6609
3e6e0aab
GT		 6610 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6611 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6612 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6613 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6614 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6615 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6616
3e6e0aab
GT		 6617 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6618 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6619
5f0269f5
ME		 6620 update_cr8_intercept(vcpu);
6621
9c3e4aab 6622 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6623 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6624 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6625 !is_protmode(vcpu))
9c3e4aab
MT		 6626 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6627
3842d135
AK		 6628 kvm_make_request(KVM_REQ_EVENT, vcpu);
6629
b6c7a5dc
HB		 6630 return 0;
6631}
6632
d0bfb940
JK		 6633int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6634 struct kvm_guest_debug *dbg)
b6c7a5dc 6635{
355be0b9 6636 unsigned long rflags;
ae675ef0 6637 int i, r;
b6c7a5dc 6638
4f926bf2
JK		 6639 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6640 r = -EBUSY;
6641 if (vcpu->arch.exception.pending)
2122ff5e 6642 goto out;
4f926bf2
JK		 6643 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6644 kvm_queue_exception(vcpu, DB_VECTOR);
6645 else
6646 kvm_queue_exception(vcpu, BP_VECTOR);
6647 }
6648
91586a3b
JK		 6649 /*
6650 * Read rflags as long as potentially injected trace flags are still
6651 * filtered out.
6652 */
6653 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6654
6655 vcpu->guest_debug = dbg->control;
6656 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6657 vcpu->guest_debug = 0;
6658
6659 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6660 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6661 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6662 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6663 } else {
6664 for (i = 0; i < KVM_NR_DB_REGS; i++)
6665 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6666 }
c8639010 6667 kvm_update_dr7(vcpu);
ae675ef0 6668
f92653ee
JK		 6669 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6670 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6671 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6672
91586a3b
JK		 6673 /*
6674 * Trigger an rflags update that will inject or remove the trace
6675 * flags.
6676 */
6677 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6678
c8639010 6679 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6680
4f926bf2 6681 r = 0;
d0bfb940 6682
2122ff5e 6683out:
b6c7a5dc
HB		 6684
6685 return r;
6686}
6687
8b006791
ZX		 6688/*
6689 * Translate a guest virtual address to a guest physical address.
6690 */
6691int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6692 struct kvm_translation *tr)
6693{
6694 unsigned long vaddr = tr->linear_address;
6695 gpa_t gpa;
f656ce01 6696 int idx;
8b006791 6697
f656ce01 6698 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6699 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6700 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6701 tr->physical_address = gpa;
6702 tr->valid = gpa != UNMAPPED_GVA;
6703 tr->writeable = 1;
6704 tr->usermode = 0;
8b006791
ZX		 6705
6706 return 0;
6707}
6708
d0752060
HB		 6709int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6710{
98918833
SY		 6711 struct i387_fxsave_struct *fxsave =
6712 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6713
d0752060
HB		 6714 memcpy(fpu->fpr, fxsave->st_space, 128);
6715 fpu->fcw = fxsave->cwd;
6716 fpu->fsw = fxsave->swd;
6717 fpu->ftwx = fxsave->twd;
6718 fpu->last_opcode = fxsave->fop;
6719 fpu->last_ip = fxsave->rip;
6720 fpu->last_dp = fxsave->rdp;
6721 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6722
d0752060
HB		 6723 return 0;
6724}
6725
6726int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6727{
98918833
SY		 6728 struct i387_fxsave_struct *fxsave =
6729 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6730
d0752060
HB		 6731 memcpy(fxsave->st_space, fpu->fpr, 128);
6732 fxsave->cwd = fpu->fcw;
6733 fxsave->swd = fpu->fsw;
6734 fxsave->twd = fpu->ftwx;
6735 fxsave->fop = fpu->last_opcode;
6736 fxsave->rip = fpu->last_ip;
6737 fxsave->rdp = fpu->last_dp;
6738 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6739
d0752060
HB		 6740 return 0;
6741}
6742
10ab25cd 6743int fx_init(struct kvm_vcpu *vcpu)
d0752060 6744{
10ab25cd
JK		 6745 int err;
6746
6747 err = fpu_alloc(&vcpu->arch.guest_fpu);
6748 if (err)
6749 return err;
6750
98918833 6751 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6752
2acf923e
DC		 6753 /*
6754 * Ensure guest xcr0 is valid for loading
6755 */
6756 vcpu->arch.xcr0 = XSTATE_FP;
6757
ad312c7c 6758 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6759
6760 return 0;
d0752060
HB		 6761}
6762EXPORT_SYMBOL_GPL(fx_init);
6763
98918833
SY		 6764static void fx_free(struct kvm_vcpu *vcpu)
6765{
6766 fpu_free(&vcpu->arch.guest_fpu);
6767}
6768
d0752060
HB		 6769void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6770{
2608d7a1 6771 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6772 return;
6773
2acf923e
DC		 6774 /*
6775 * Restore all possible states in the guest,
6776 * and assume host would use all available bits.
6777 * Guest xcr0 would be loaded later.
6778 */
6779 kvm_put_guest_xcr0(vcpu);
d0752060 6780 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6781 __kernel_fpu_begin();
98918833 6782 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6783 trace_kvm_fpu(1);
d0752060 6784}
d0752060
HB		 6785
6786void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6787{
2acf923e
DC		 6788 kvm_put_guest_xcr0(vcpu);
6789
d0752060
HB		 6790 if (!vcpu->guest_fpu_loaded)
6791 return;
6792
6793 vcpu->guest_fpu_loaded = 0;
98918833 6794 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6795 __kernel_fpu_end();
f096ed85 6796 ++vcpu->stat.fpu_reload;
a8eeb04a 6797 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6798 trace_kvm_fpu(0);
d0752060 6799}
e9b11c17
ZX		 6800
6801void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6802{
12f9a48f 6803 kvmclock_reset(vcpu);
7f1ea208 6804
f5f48ee1 6805 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6806 fx_free(vcpu);
e9b11c17
ZX		 6807 kvm_x86_ops->vcpu_free(vcpu);
6808}
6809
6810struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6811 unsigned int id)
6812{
6755bae8
ZA		 6813 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6814 printk_once(KERN_WARNING
6815 "kvm: SMP vm created on host with unstable TSC; "
6816 "guest TSC will not be reliable\n");
26e5215f
AK		 6817 return kvm_x86_ops->vcpu_create(kvm, id);
6818}
e9b11c17 6819
26e5215f
AK		 6820int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6821{
6822 int r;
e9b11c17 6823
0bed3b56 6824 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6825 r = vcpu_load(vcpu);
6826 if (r)
6827 return r;
57f252f2 6828 kvm_vcpu_reset(vcpu);
8a3c1a33 6829 kvm_mmu_setup(vcpu);
e9b11c17 6830 vcpu_put(vcpu);
e9b11c17 6831
26e5215f 6832 return r;
e9b11c17
ZX		 6833}
6834
42897d86
MT		 6835int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6836{
6837 int r;
8fe8ab46 6838 struct msr_data msr;
332967a3 6839 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6840
6841 r = vcpu_load(vcpu);
6842 if (r)
6843 return r;
8fe8ab46
WA		 6844 msr.data = 0x0;
6845 msr.index = MSR_IA32_TSC;
6846 msr.host_initiated = true;
6847 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6848 vcpu_put(vcpu);
6849
332967a3
AJ		 6850 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6851 KVMCLOCK_SYNC_PERIOD);
6852
42897d86
MT		 6853 return r;
6854}
6855
d40ccc62 6856void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6857{
9fc77441 6858 int r;
344d9588
GN		 6859 vcpu->arch.apf.msr_val = 0;
6860
9fc77441
MT		 6861 r = vcpu_load(vcpu);
6862 BUG_ON(r);
e9b11c17
ZX		 6863 kvm_mmu_unload(vcpu);
6864 vcpu_put(vcpu);
6865
98918833 6866 fx_free(vcpu);
e9b11c17
ZX		 6867 kvm_x86_ops->vcpu_free(vcpu);
6868}
6869
66450a21 6870void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6871{
7460fb4a
AK		 6872 atomic_set(&vcpu->arch.nmi_queued, 0);
6873 vcpu->arch.nmi_pending = 0;
448fa4a9 6874 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 6875 kvm_clear_interrupt_queue(vcpu);
6876 kvm_clear_exception_queue(vcpu);
448fa4a9 6877
42dbaa5a 6878 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6f43ed01 6879 vcpu->arch.dr6 = DR6_INIT;
73aaf249 6880 kvm_update_dr6(vcpu);
42dbaa5a 6881 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6882 kvm_update_dr7(vcpu);
42dbaa5a 6883
3842d135 6884 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6885 vcpu->arch.apf.msr_val = 0;
c9aaa895 6886 vcpu->arch.st.msr_val = 0;
3842d135 6887
12f9a48f
GC		 6888 kvmclock_reset(vcpu);
6889
af585b92
GN		 6890 kvm_clear_async_pf_completion_queue(vcpu);
6891 kvm_async_pf_hash_reset(vcpu);
6892 vcpu->arch.apf.halted = false;
3842d135 6893
f5132b01
GN		 6894 kvm_pmu_reset(vcpu);
6895
66f7b72e
JS		 6896 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6897 vcpu->arch.regs_avail = ~0;
6898 vcpu->arch.regs_dirty = ~0;
6899
57f252f2 6900 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6901}
6902
66450a21
JK		 6903void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6904{
6905 struct kvm_segment cs;
6906
6907 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6908 cs.selector = vector << 8;
6909 cs.base = vector << 12;
6910 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6911 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6912}
6913
10474ae8 6914int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6915{
ca84d1a2
ZA		 6916 struct kvm *kvm;
6917 struct kvm_vcpu *vcpu;
6918 int i;
0dd6a6ed
ZA		 6919 int ret;
6920 u64 local_tsc;
6921 u64 max_tsc = 0;
6922 bool stable, backwards_tsc = false;
18863bdd
AK		 6923
6924 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6925 ret = kvm_x86_ops->hardware_enable(garbage);
6926 if (ret != 0)
6927 return ret;
6928
6929 local_tsc = native_read_tsc();
6930 stable = !check_tsc_unstable();
6931 list_for_each_entry(kvm, &vm_list, vm_list) {
6932 kvm_for_each_vcpu(i, vcpu, kvm) {
6933 if (!stable && vcpu->cpu == smp_processor_id())
6934 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6935 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6936 backwards_tsc = true;
6937 if (vcpu->arch.last_host_tsc > max_tsc)
6938 max_tsc = vcpu->arch.last_host_tsc;
6939 }
6940 }
6941 }
6942
6943 /*
6944 * Sometimes, even reliable TSCs go backwards. This happens on
6945 * platforms that reset TSC during suspend or hibernate actions, but
6946 * maintain synchronization. We must compensate. Fortunately, we can
6947 * detect that condition here, which happens early in CPU bringup,
6948 * before any KVM threads can be running. Unfortunately, we can't
6949 * bring the TSCs fully up to date with real time, as we aren't yet far
6950 * enough into CPU bringup that we know how much real time has actually
6951 * elapsed; our helper function, get_kernel_ns() will be using boot
6952 * variables that haven't been updated yet.
6953 *
6954 * So we simply find the maximum observed TSC above, then record the
6955 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6956 * the adjustment will be applied. Note that we accumulate
6957 * adjustments, in case multiple suspend cycles happen before some VCPU
6958 * gets a chance to run again. In the event that no KVM threads get a
6959 * chance to run, we will miss the entire elapsed period, as we'll have
6960 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6961 * loose cycle time. This isn't too big a deal, since the loss will be
6962 * uniform across all VCPUs (not to mention the scenario is extremely
6963 * unlikely). It is possible that a second hibernate recovery happens
6964 * much faster than a first, causing the observed TSC here to be
6965 * smaller; this would require additional padding adjustment, which is
6966 * why we set last_host_tsc to the local tsc observed here.
6967 *
6968 * N.B. - this code below runs only on platforms with reliable TSC,
6969 * as that is the only way backwards_tsc is set above. Also note
6970 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6971 * have the same delta_cyc adjustment applied if backwards_tsc
6972 * is detected. Note further, this adjustment is only done once,
6973 * as we reset last_host_tsc on all VCPUs to stop this from being
6974 * called multiple times (one for each physical CPU bringup).
6975 *
4a969980 6976 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6977 * will be compensated by the logic in vcpu_load, which sets the TSC to
6978 * catchup mode. This will catchup all VCPUs to real time, but cannot
6979 * guarantee that they stay in perfect synchronization.
6980 */
6981 if (backwards_tsc) {
6982 u64 delta_cyc = max_tsc - local_tsc;
16a96021 6983 backwards_tsc_observed = true;
0dd6a6ed
ZA		 6984 list_for_each_entry(kvm, &vm_list, vm_list) {
6985 kvm_for_each_vcpu(i, vcpu, kvm) {
6986 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6987 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6988 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6989 &vcpu->requests);
0dd6a6ed
ZA		 6990 }
6991
6992 /*
6993 * We have to disable TSC offset matching.. if you were
6994 * booting a VM while issuing an S4 host suspend....
6995 * you may have some problem. Solving this issue is
6996 * left as an exercise to the reader.
6997 */
6998 kvm->arch.last_tsc_nsec = 0;
6999 kvm->arch.last_tsc_write = 0;
7000 }
7001
7002 }
7003 return 0;
e9b11c17
ZX		 7004}
7005
7006void kvm_arch_hardware_disable(void *garbage)
7007{
7008 kvm_x86_ops->hardware_disable(garbage);
3548bab5 7009 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 7010}
7011
7012int kvm_arch_hardware_setup(void)
7013{
7014 return kvm_x86_ops->hardware_setup();
7015}
7016
7017void kvm_arch_hardware_unsetup(void)
7018{
7019 kvm_x86_ops->hardware_unsetup();
7020}
7021
7022void kvm_arch_check_processor_compat(void *rtn)
7023{
7024 kvm_x86_ops->check_processor_compatibility(rtn);
7025}
7026
3e515705
AK		 7027bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7028{
7029 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7030}
7031
54e9818f
GN		 7032struct static_key kvm_no_apic_vcpu __read_mostly;
7033
e9b11c17
ZX		 7034int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7035{
7036 struct page *page;
7037 struct kvm *kvm;
7038 int r;
7039
7040 BUG_ON(vcpu->kvm == NULL);
7041 kvm = vcpu->kvm;
7042
6aef266c 7043 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7044 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7045 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7046 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7047 else
a4535290 7048 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7049
7050 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7051 if (!page) {
7052 r = -ENOMEM;
7053 goto fail;
7054 }
ad312c7c 7055 vcpu->arch.pio_data = page_address(page);
e9b11c17 7056
cc578287 7057 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7058
e9b11c17
ZX		 7059 r = kvm_mmu_create(vcpu);
7060 if (r < 0)
7061 goto fail_free_pio_data;
7062
7063 if (irqchip_in_kernel(kvm)) {
7064 r = kvm_create_lapic(vcpu);
7065 if (r < 0)
7066 goto fail_mmu_destroy;
54e9818f
GN		 7067 } else
7068 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7069
890ca9ae
HY		 7070 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7071 GFP_KERNEL);
7072 if (!vcpu->arch.mce_banks) {
7073 r = -ENOMEM;
443c39bc 7074 goto fail_free_lapic;
890ca9ae
HY		 7075 }
7076 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7077
f1797359
WY		 7078 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7079 r = -ENOMEM;
f5f48ee1 7080 goto fail_free_mce_banks;
f1797359 7081 }
f5f48ee1 7082
66f7b72e
JS		 7083 r = fx_init(vcpu);
7084 if (r)
7085 goto fail_free_wbinvd_dirty_mask;
7086
ba904635 7087 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7088 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7089
7090 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7091 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7092
af585b92 7093 kvm_async_pf_hash_reset(vcpu);
f5132b01 7094 kvm_pmu_init(vcpu);
af585b92 7095
e9b11c17 7096 return 0;
66f7b72e
JS		 7097fail_free_wbinvd_dirty_mask:
7098 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7099fail_free_mce_banks:
7100 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7101fail_free_lapic:
7102 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7103fail_mmu_destroy:
7104 kvm_mmu_destroy(vcpu);
7105fail_free_pio_data:
ad312c7c 7106 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7107fail:
7108 return r;
7109}
7110
7111void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7112{
f656ce01
MT		 7113 int idx;
7114
f5132b01 7115 kvm_pmu_destroy(vcpu);
36cb93fd 7116 kfree(vcpu->arch.mce_banks);
e9b11c17 7117 kvm_free_lapic(vcpu);
f656ce01 7118 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7119 kvm_mmu_destroy(vcpu);
f656ce01 7120 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7121 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7122 if (!irqchip_in_kernel(vcpu->kvm))
7123 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7124}
d19a9cd2 7125
e08b9637 7126int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7127{
e08b9637
CO		 7128 if (type)
7129 return -EINVAL;
7130
f05e70ac 7131 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7132 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7133 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7134 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7135
5550af4d
SY		 7136 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7137 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7138 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7139 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7140 &kvm->arch.irq_sources_bitmap);
5550af4d 7141
038f8c11 7142 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7143 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7144 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7145
7146 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7147
7e44e449 7148 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7149 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7150
d89f5eff 7151 return 0;
d19a9cd2
ZX		 7152}
7153
7154static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7155{
9fc77441
MT		 7156 int r;
7157 r = vcpu_load(vcpu);
7158 BUG_ON(r);
d19a9cd2
ZX		 7159 kvm_mmu_unload(vcpu);
7160 vcpu_put(vcpu);
7161}
7162
7163static void kvm_free_vcpus(struct kvm *kvm)
7164{
7165 unsigned int i;
988a2cae 7166 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7167
7168 /*
7169 * Unpin any mmu pages first.
7170 */
af585b92
GN		 7171 kvm_for_each_vcpu(i, vcpu, kvm) {
7172 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7173 kvm_unload_vcpu_mmu(vcpu);
af585b92 7174 }
988a2cae
GN		 7175 kvm_for_each_vcpu(i, vcpu, kvm)
7176 kvm_arch_vcpu_free(vcpu);
7177
7178 mutex_lock(&kvm->lock);
7179 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7180 kvm->vcpus[i] = NULL;
d19a9cd2 7181
988a2cae
GN		 7182 atomic_set(&kvm->online_vcpus, 0);
7183 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7184}
7185
ad8ba2cd
SY		 7186void kvm_arch_sync_events(struct kvm *kvm)
7187{
332967a3 7188 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7189 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7190 kvm_free_all_assigned_devices(kvm);
aea924f6 7191 kvm_free_pit(kvm);
ad8ba2cd
SY		 7192}
7193
d19a9cd2
ZX		 7194void kvm_arch_destroy_vm(struct kvm *kvm)
7195{
27469d29
AH		 7196 if (current->mm == kvm->mm) {
7197 /*
7198 * Free memory regions allocated on behalf of userspace,
7199 * unless the the memory map has changed due to process exit
7200 * or fd copying.
7201 */
7202 struct kvm_userspace_memory_region mem;
7203 memset(&mem, 0, sizeof(mem));
7204 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7205 kvm_set_memory_region(kvm, &mem);
7206
7207 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7208 kvm_set_memory_region(kvm, &mem);
7209
7210 mem.slot = TSS_PRIVATE_MEMSLOT;
7211 kvm_set_memory_region(kvm, &mem);
7212 }
6eb55818 7213 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7214 kfree(kvm->arch.vpic);
7215 kfree(kvm->arch.vioapic);
d19a9cd2 7216 kvm_free_vcpus(kvm);
3d45830c
AK		 7217 if (kvm->arch.apic_access_page)
7218 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7219 if (kvm->arch.ept_identity_pagetable)
7220 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7221 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7222}
0de10343 7223
5587027c 7224void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7225 struct kvm_memory_slot *dont)
7226{
7227 int i;
7228
d89cc617
TY		 7229 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7230 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7231 kvm_kvfree(free->arch.rmap[i]);
7232 free->arch.rmap[i] = NULL;
77d11309 7233 }
d89cc617
TY		 7234 if (i == 0)
7235 continue;
7236
7237 if (!dont || free->arch.lpage_info[i - 1] !=
7238 dont->arch.lpage_info[i - 1]) {
7239 kvm_kvfree(free->arch.lpage_info[i - 1]);
7240 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7241 }
7242 }
7243}
7244
5587027c
AK		 7245int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7246 unsigned long npages)
db3fe4eb
TY		 7247{
7248 int i;
7249
d89cc617 7250 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7251 unsigned long ugfn;
7252 int lpages;
d89cc617 7253 int level = i + 1;
db3fe4eb
TY		 7254
7255 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7256 slot->base_gfn, level) + 1;
7257
d89cc617
TY		 7258 slot->arch.rmap[i] =
7259 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7260 if (!slot->arch.rmap[i])
77d11309 7261 goto out_free;
d89cc617
TY		 7262 if (i == 0)
7263 continue;
77d11309 7264
d89cc617
TY		 7265 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7266 sizeof(*slot->arch.lpage_info[i - 1]));
7267 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7268 goto out_free;
7269
7270 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7271 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7272 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7273 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7274 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7275 /*
7276 * If the gfn and userspace address are not aligned wrt each
7277 * other, or if explicitly asked to, disable large page
7278 * support for this slot
7279 */
7280 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7281 !kvm_largepages_enabled()) {
7282 unsigned long j;
7283
7284 for (j = 0; j < lpages; ++j)
d89cc617 7285 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7286 }
7287 }
7288
7289 return 0;
7290
7291out_free:
d89cc617
TY		 7292 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7293 kvm_kvfree(slot->arch.rmap[i]);
7294 slot->arch.rmap[i] = NULL;
7295 if (i == 0)
7296 continue;
7297
7298 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7299 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7300 }
7301 return -ENOMEM;
7302}
7303
e59dbe09
TY		 7304void kvm_arch_memslots_updated(struct kvm *kvm)
7305{
e6dff7d1
TY		 7306 /*
7307 * memslots->generation has been incremented.
7308 * mmio generation may have reached its maximum value.
7309 */
7310 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7311}
7312
f7784b8e
MT		 7313int kvm_arch_prepare_memory_region(struct kvm *kvm,
7314 struct kvm_memory_slot *memslot,
f7784b8e 7315 struct kvm_userspace_memory_region *mem,
7b6195a9 7316 enum kvm_mr_change change)
0de10343 7317{
7a905b14
TY		 7318 /*
7319 * Only private memory slots need to be mapped here since
7320 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7321 */
7b6195a9 7322 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7323 unsigned long userspace_addr;
604b38ac 7324
7a905b14
TY		 7325 /*
7326 * MAP_SHARED to prevent internal slot pages from being moved
7327 * by fork()/COW.
7328 */
7b6195a9 7329 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7330 PROT_READ | PROT_WRITE,
7331 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7332
7a905b14
TY		 7333 if (IS_ERR((void *)userspace_addr))
7334 return PTR_ERR((void *)userspace_addr);
604b38ac 7335
7a905b14 7336 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7337 }
7338
f7784b8e
MT		 7339 return 0;
7340}
7341
7342void kvm_arch_commit_memory_region(struct kvm *kvm,
7343 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7344 const struct kvm_memory_slot *old,
7345 enum kvm_mr_change change)
f7784b8e
MT		 7346{
7347
8482644a 7348 int nr_mmu_pages = 0;
f7784b8e 7349
8482644a 7350 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7351 int ret;
7352
8482644a
TY		 7353 ret = vm_munmap(old->userspace_addr,
7354 old->npages * PAGE_SIZE);
f7784b8e
MT		 7355 if (ret < 0)
7356 printk(KERN_WARNING
7357 "kvm_vm_ioctl_set_memory_region: "
7358 "failed to munmap memory\n");
7359 }
7360
48c0e4e9
XG		 7361 if (!kvm->arch.n_requested_mmu_pages)
7362 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7363
48c0e4e9 7364 if (nr_mmu_pages)
0de10343 7365 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7366 /*
7367 * Write protect all pages for dirty logging.
c126d94f
XG		 7368 *
7369 * All the sptes including the large sptes which point to this
7370 * slot are set to readonly. We can not create any new large
7371 * spte on this slot until the end of the logging.
7372 *
7373 * See the comments in fast_page_fault().
c972f3b1 7374 */
8482644a 7375 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7376 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7377}
1d737c8a 7378
2df72e9b 7379void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7380{
6ca18b69 7381 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7382}
7383
2df72e9b
MT		 7384void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7385 struct kvm_memory_slot *slot)
7386{
6ca18b69 7387 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7388}
7389
1d737c8a
ZX		 7390int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7391{
b6b8a145
JK		 7392 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7393 kvm_x86_ops->check_nested_events(vcpu, false);
7394
af585b92
GN		 7395 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7396 !vcpu->arch.apf.halted)
7397 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7398 || kvm_apic_has_events(vcpu)
6aef266c 7399 || vcpu->arch.pv.pv_unhalted
7460fb4a 7400 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7401 (kvm_arch_interrupt_allowed(vcpu) &&
7402 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7403}
5736199a 7404
b6d33834 7405int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7406{
b6d33834 7407 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7408}
78646121
GN		 7409
7410int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7411{
7412 return kvm_x86_ops->interrupt_allowed(vcpu);
7413}
229456fc 7414
f92653ee
JK		 7415bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7416{
7417 unsigned long current_rip = kvm_rip_read(vcpu) +
7418 get_segment_base(vcpu, VCPU_SREG_CS);
7419
7420 return current_rip == linear_rip;
7421}
7422EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7423
94fe45da
JK		 7424unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7425{
7426 unsigned long rflags;
7427
7428 rflags = kvm_x86_ops->get_rflags(vcpu);
7429 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7430 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7431 return rflags;
7432}
7433EXPORT_SYMBOL_GPL(kvm_get_rflags);
7434
6addfc42 7435static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7436{
7437 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7438 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7439 rflags |= X86_EFLAGS_TF;
94fe45da 7440 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7441}
7442
7443void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7444{
7445 __kvm_set_rflags(vcpu, rflags);
3842d135 7446 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7447}
7448EXPORT_SYMBOL_GPL(kvm_set_rflags);
7449
56028d08
GN		 7450void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7451{
7452 int r;
7453
fb67e14f 7454 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7455 work->wakeup_all)
56028d08
GN		 7456 return;
7457
7458 r = kvm_mmu_reload(vcpu);
7459 if (unlikely(r))
7460 return;
7461
fb67e14f
XG		 7462 if (!vcpu->arch.mmu.direct_map &&
7463 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7464 return;
7465
56028d08
GN		 7466 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7467}
7468
af585b92
GN		 7469static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7470{
7471 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7472}
7473
7474static inline u32 kvm_async_pf_next_probe(u32 key)
7475{
7476 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7477}
7478
7479static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7480{
7481 u32 key = kvm_async_pf_hash_fn(gfn);
7482
7483 while (vcpu->arch.apf.gfns[key] != ~0)
7484 key = kvm_async_pf_next_probe(key);
7485
7486 vcpu->arch.apf.gfns[key] = gfn;
7487}
7488
7489static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7490{
7491 int i;
7492 u32 key = kvm_async_pf_hash_fn(gfn);
7493
7494 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7495 (vcpu->arch.apf.gfns[key] != gfn &&
7496 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7497 key = kvm_async_pf_next_probe(key);
7498
7499 return key;
7500}
7501
7502bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7503{
7504 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7505}
7506
7507static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7508{
7509 u32 i, j, k;
7510
7511 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7512 while (true) {
7513 vcpu->arch.apf.gfns[i] = ~0;
7514 do {
7515 j = kvm_async_pf_next_probe(j);
7516 if (vcpu->arch.apf.gfns[j] == ~0)
7517 return;
7518 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7519 /*
7520 * k lies cyclically in ]i,j]
7521 * | i.k.j |
7522 * |....j i.k.| or |.k..j i...|
7523 */
7524 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7525 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7526 i = j;
7527 }
7528}
7529
7c90705b
GN		 7530static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7531{
7532
7533 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7534 sizeof(val));
7535}
7536
af585b92
GN		 7537void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7538 struct kvm_async_pf *work)
7539{
6389ee94
AK		 7540 struct x86_exception fault;
7541
7c90705b 7542 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7543 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7544
7545 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7546 (vcpu->arch.apf.send_user_only &&
7547 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7548 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7549 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7550 fault.vector = PF_VECTOR;
7551 fault.error_code_valid = true;
7552 fault.error_code = 0;
7553 fault.nested_page_fault = false;
7554 fault.address = work->arch.token;
7555 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7556 }
af585b92
GN		 7557}
7558
7559void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7560 struct kvm_async_pf *work)
7561{
6389ee94
AK		 7562 struct x86_exception fault;
7563
7c90705b 7564 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7565 if (work->wakeup_all)
7c90705b
GN		 7566 work->arch.token = ~0; /* broadcast wakeup */
7567 else
7568 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7569
7570 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7571 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7572 fault.vector = PF_VECTOR;
7573 fault.error_code_valid = true;
7574 fault.error_code = 0;
7575 fault.nested_page_fault = false;
7576 fault.address = work->arch.token;
7577 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7578 }
e6d53e3b 7579 vcpu->arch.apf.halted = false;
a4fa1635 7580 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7581}
7582
7583bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7584{
7585 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7586 return true;
7587 else
7588 return !kvm_event_needs_reinjection(vcpu) &&
7589 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7590}
7591
e0f0bbc5
AW		 7592void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7593{
7594 atomic_inc(&kvm->arch.noncoherent_dma_count);
7595}
7596EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7597
7598void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7599{
7600 atomic_dec(&kvm->arch.noncoherent_dma_count);
7601}
7602EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7603
7604bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7605{
7606 return atomic_read(&kvm->arch.noncoherent_dma_count);
7607}
7608EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7609
229456fc
MT		 7610EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7611EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7612EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7613EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7614EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7615EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7616EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7617EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7618EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7619EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7620EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7621EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7622EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Linux 6.x block layer and io_uring tree(s)