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KVM: x86: tweak types of fields in kvm_lapic_irq
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
313a3dc7 31
18068523 32#include <linux/clocksource.h>
4d5c5d0f 33#include <linux/interrupt.h>
313a3dc7
CO		 34#include <linux/kvm.h>
35#include <linux/fs.h>
36#include <linux/vmalloc.h>
5fb76f9b 37#include <linux/module.h>
0de10343 38#include <linux/mman.h>
2bacc55c 39#include <linux/highmem.h>
19de40a8 40#include <linux/iommu.h>
62c476c7 41#include <linux/intel-iommu.h>
c8076604 42#include <linux/cpufreq.h>
18863bdd 43#include <linux/user-return-notifier.h>
a983fb23 44#include <linux/srcu.h>
5a0e3ad6 45#include <linux/slab.h>
ff9d07a0 46#include <linux/perf_event.h>
7bee342a 47#include <linux/uaccess.h>
af585b92 48#include <linux/hash.h>
a1b60c1c 49#include <linux/pci.h>
16e8d74d
MT		 50#include <linux/timekeeper_internal.h>
51#include <linux/pvclock_gtod.h>
aec51dc4 52#include <trace/events/kvm.h>
2ed152af 53
229456fc
MT		 54#define CREATE_TRACE_POINTS
55#include "trace.h"
043405e1 56
24f1e32c 57#include <asm/debugreg.h>
d825ed0a 58#include <asm/msr.h>
a5f61300 59#include <asm/desc.h>
0bed3b56 60#include <asm/mtrr.h>
890ca9ae 61#include <asm/mce.h>
7cf30855 62#include <asm/i387.h>
1361b83a 63#include <asm/fpu-internal.h> /* Ugh! */
98918833 64#include <asm/xcr.h>
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
043405e1 67
313a3dc7 68#define MAX_IO_MSRS 256
890ca9ae 69#define KVM_MAX_MCE_BANKS 32
5854dbca 70#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 71
0f65dd70
AK		 72#define emul_to_vcpu(ctxt) \
73 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
74
50a37eb4
JR		 75/* EFER defaults:
76 * - enable syscall per default because its emulated by KVM
77 * - enable LME and LMA per default on 64 bit KVM
78 */
79#ifdef CONFIG_X86_64
1260edbe
LJ		 80static
81u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 82#else
1260edbe 83static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 84#endif
313a3dc7 85
ba1389b7
AK		 86#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
87#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 88
cb142eb7 89static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 90static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 91static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 92
97896d04 93struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 94EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 95
476bc001
RR		 96static bool ignore_msrs = 0;
97module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 98
9ed96e87
MT		 99unsigned int min_timer_period_us = 500;
100module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
101
92a1f12d
JR		 102bool kvm_has_tsc_control;
103EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
104u32 kvm_max_guest_tsc_khz;
105EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
106
cc578287
ZA		 107/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
108static u32 tsc_tolerance_ppm = 250;
109module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
110
d0659d94
MT		 111/* lapic timer advance (tscdeadline mode only) in nanoseconds */
112unsigned int lapic_timer_advance_ns = 0;
113module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
114
16a96021
MT		 115static bool backwards_tsc_observed = false;
116
18863bdd
AK		 117#define KVM_NR_SHARED_MSRS 16
118
119struct kvm_shared_msrs_global {
120 int nr;
2bf78fa7 121 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 122};
123
124struct kvm_shared_msrs {
125 struct user_return_notifier urn;
126 bool registered;
2bf78fa7
SY		 127 struct kvm_shared_msr_values {
128 u64 host;
129 u64 curr;
130 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 131};
132
133static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 134static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 135
417bc304 136struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 137 { "pf_fixed", VCPU_STAT(pf_fixed) },
138 { "pf_guest", VCPU_STAT(pf_guest) },
139 { "tlb_flush", VCPU_STAT(tlb_flush) },
140 { "invlpg", VCPU_STAT(invlpg) },
141 { "exits", VCPU_STAT(exits) },
142 { "io_exits", VCPU_STAT(io_exits) },
143 { "mmio_exits", VCPU_STAT(mmio_exits) },
144 { "signal_exits", VCPU_STAT(signal_exits) },
145 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 146 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 147 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 148 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
ba1389b7 149 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 150 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 151 { "request_irq", VCPU_STAT(request_irq_exits) },
152 { "irq_exits", VCPU_STAT(irq_exits) },
153 { "host_state_reload", VCPU_STAT(host_state_reload) },
154 { "efer_reload", VCPU_STAT(efer_reload) },
155 { "fpu_reload", VCPU_STAT(fpu_reload) },
156 { "insn_emulation", VCPU_STAT(insn_emulation) },
157 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 158 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 159 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 160 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
161 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
162 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
163 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
164 { "mmu_flooded", VM_STAT(mmu_flooded) },
165 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 166 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 167 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 168 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 169 { "largepages", VM_STAT(lpages) },
417bc304
HB		 170 { NULL }
171};
172
2acf923e
DC		 173u64 __read_mostly host_xcr0;
174
b6785def 175static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 176
af585b92
GN		 177static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
178{
179 int i;
180 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
181 vcpu->arch.apf.gfns[i] = ~0;
182}
183
18863bdd
AK		 184static void kvm_on_user_return(struct user_return_notifier *urn)
185{
186 unsigned slot;
18863bdd
AK		 187 struct kvm_shared_msrs *locals
188 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 189 struct kvm_shared_msr_values *values;
18863bdd
AK		 190
191 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 192 values = &locals->values[slot];
193 if (values->host != values->curr) {
194 wrmsrl(shared_msrs_global.msrs[slot], values->host);
195 values->curr = values->host;
18863bdd
AK		 196 }
197 }
198 locals->registered = false;
199 user_return_notifier_unregister(urn);
200}
201
2bf78fa7 202static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 203{
18863bdd 204 u64 value;
013f6a5d
MT		 205 unsigned int cpu = smp_processor_id();
206 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 207
2bf78fa7
SY		 208 /* only read, and nobody should modify it at this time,
209 * so don't need lock */
210 if (slot >= shared_msrs_global.nr) {
211 printk(KERN_ERR "kvm: invalid MSR slot!");
212 return;
213 }
214 rdmsrl_safe(msr, &value);
215 smsr->values[slot].host = value;
216 smsr->values[slot].curr = value;
217}
218
219void kvm_define_shared_msr(unsigned slot, u32 msr)
220{
0123be42 221 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 222 if (slot >= shared_msrs_global.nr)
223 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 224 shared_msrs_global.msrs[slot] = msr;
225 /* we need ensured the shared_msr_global have been updated */
226 smp_wmb();
18863bdd
AK		 227}
228EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
229
230static void kvm_shared_msr_cpu_online(void)
231{
232 unsigned i;
18863bdd
AK		 233
234 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 235 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 236}
237
8b3c3104 238int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 239{
013f6a5d
MT		 240 unsigned int cpu = smp_processor_id();
241 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 242 int err;
18863bdd 243
2bf78fa7 244 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 245 return 0;
2bf78fa7 246 smsr->values[slot].curr = value;
8b3c3104
AH		 247 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
248 if (err)
249 return 1;
250
18863bdd
AK		 251 if (!smsr->registered) {
252 smsr->urn.on_user_return = kvm_on_user_return;
253 user_return_notifier_register(&smsr->urn);
254 smsr->registered = true;
255 }
8b3c3104 256 return 0;
18863bdd
AK		 257}
258EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
259
13a34e06 260static void drop_user_return_notifiers(void)
3548bab5 261{
013f6a5d
MT		 262 unsigned int cpu = smp_processor_id();
263 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 264
265 if (smsr->registered)
266 kvm_on_user_return(&smsr->urn);
267}
268
6866b83e
CO		 269u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
270{
8a5a87d9 271 return vcpu->arch.apic_base;
6866b83e
CO		 272}
273EXPORT_SYMBOL_GPL(kvm_get_apic_base);
274
58cb628d
JK		 275int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
276{
277 u64 old_state = vcpu->arch.apic_base &
278 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
279 u64 new_state = msr_info->data &
280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
282 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
283
284 if (!msr_info->host_initiated &&
285 ((msr_info->data & reserved_bits) != 0 ||
286 new_state == X2APIC_ENABLE ||
287 (new_state == MSR_IA32_APICBASE_ENABLE &&
288 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
289 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
290 old_state == 0)))
291 return 1;
292
293 kvm_lapic_set_base(vcpu, msr_info->data);
294 return 0;
6866b83e
CO		 295}
296EXPORT_SYMBOL_GPL(kvm_set_apic_base);
297
2605fc21 298asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 299{
300 /* Fault while not rebooting. We want the trace. */
301 BUG();
302}
303EXPORT_SYMBOL_GPL(kvm_spurious_fault);
304
3fd28fce
ED		 305#define EXCPT_BENIGN 0
306#define EXCPT_CONTRIBUTORY 1
307#define EXCPT_PF 2
308
309static int exception_class(int vector)
310{
311 switch (vector) {
312 case PF_VECTOR:
313 return EXCPT_PF;
314 case DE_VECTOR:
315 case TS_VECTOR:
316 case NP_VECTOR:
317 case SS_VECTOR:
318 case GP_VECTOR:
319 return EXCPT_CONTRIBUTORY;
320 default:
321 break;
322 }
323 return EXCPT_BENIGN;
324}
325
d6e8c854
NA		 326#define EXCPT_FAULT 0
327#define EXCPT_TRAP 1
328#define EXCPT_ABORT 2
329#define EXCPT_INTERRUPT 3
330
331static int exception_type(int vector)
332{
333 unsigned int mask;
334
335 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
336 return EXCPT_INTERRUPT;
337
338 mask = 1 << vector;
339
340 /* #DB is trap, as instruction watchpoints are handled elsewhere */
341 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
342 return EXCPT_TRAP;
343
344 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
345 return EXCPT_ABORT;
346
347 /* Reserved exceptions will result in fault */
348 return EXCPT_FAULT;
349}
350
3fd28fce 351static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 352 unsigned nr, bool has_error, u32 error_code,
353 bool reinject)
3fd28fce
ED		 354{
355 u32 prev_nr;
356 int class1, class2;
357
3842d135
AK		 358 kvm_make_request(KVM_REQ_EVENT, vcpu);
359
3fd28fce
ED		 360 if (!vcpu->arch.exception.pending) {
361 queue:
3ffb2468
NA		 362 if (has_error && !is_protmode(vcpu))
363 has_error = false;
3fd28fce
ED		 364 vcpu->arch.exception.pending = true;
365 vcpu->arch.exception.has_error_code = has_error;
366 vcpu->arch.exception.nr = nr;
367 vcpu->arch.exception.error_code = error_code;
3f0fd292 368 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 369 return;
370 }
371
372 /* to check exception */
373 prev_nr = vcpu->arch.exception.nr;
374 if (prev_nr == DF_VECTOR) {
375 /* triple fault -> shutdown */
a8eeb04a 376 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 377 return;
378 }
379 class1 = exception_class(prev_nr);
380 class2 = exception_class(nr);
381 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
382 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
383 /* generate double fault per SDM Table 5-5 */
384 vcpu->arch.exception.pending = true;
385 vcpu->arch.exception.has_error_code = true;
386 vcpu->arch.exception.nr = DF_VECTOR;
387 vcpu->arch.exception.error_code = 0;
388 } else
389 /* replace previous exception with a new one in a hope
390 that instruction re-execution will regenerate lost
391 exception */
392 goto queue;
393}
394
298101da
AK		 395void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
396{
ce7ddec4 397 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 398}
399EXPORT_SYMBOL_GPL(kvm_queue_exception);
400
ce7ddec4
JR		 401void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
402{
403 kvm_multiple_exception(vcpu, nr, false, 0, true);
404}
405EXPORT_SYMBOL_GPL(kvm_requeue_exception);
406
db8fcefa 407void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 408{
db8fcefa
AP		 409 if (err)
410 kvm_inject_gp(vcpu, 0);
411 else
412 kvm_x86_ops->skip_emulated_instruction(vcpu);
413}
414EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 415
6389ee94 416void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 417{
418 ++vcpu->stat.pf_guest;
6389ee94
AK		 419 vcpu->arch.cr2 = fault->address;
420 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 421}
27d6c865 422EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 423
ef54bcfe 424static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 425{
6389ee94
AK		 426 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
427 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 428 else
6389ee94 429 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 430
431 return fault->nested_page_fault;
d4f8cf66
JR		 432}
433
3419ffc8
SY		 434void kvm_inject_nmi(struct kvm_vcpu *vcpu)
435{
7460fb4a
AK		 436 atomic_inc(&vcpu->arch.nmi_queued);
437 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 438}
439EXPORT_SYMBOL_GPL(kvm_inject_nmi);
440
298101da
AK		 441void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
442{
ce7ddec4 443 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 444}
445EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
446
ce7ddec4
JR		 447void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
448{
449 kvm_multiple_exception(vcpu, nr, true, error_code, true);
450}
451EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
452
0a79b009
AK		 453/*
454 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
455 * a #GP and return false.
456 */
457bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 458{
0a79b009
AK		 459 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
460 return true;
461 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
462 return false;
298101da 463}
0a79b009 464EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 465
16f8a6f9
NA		 466bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
467{
468 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
469 return true;
470
471 kvm_queue_exception(vcpu, UD_VECTOR);
472 return false;
473}
474EXPORT_SYMBOL_GPL(kvm_require_dr);
475
ec92fe44
JR		 476/*
477 * This function will be used to read from the physical memory of the currently
478 * running guest. The difference to kvm_read_guest_page is that this function
479 * can read from guest physical or from the guest's guest physical memory.
480 */
481int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
482 gfn_t ngfn, void *data, int offset, int len,
483 u32 access)
484{
54987b7a 485 struct x86_exception exception;
ec92fe44
JR		 486 gfn_t real_gfn;
487 gpa_t ngpa;
488
489 ngpa = gfn_to_gpa(ngfn);
54987b7a 490 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 491 if (real_gfn == UNMAPPED_GVA)
492 return -EFAULT;
493
494 real_gfn = gpa_to_gfn(real_gfn);
495
496 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
497}
498EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
499
69b0049a 500static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 501 void *data, int offset, int len, u32 access)
502{
503 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
504 data, offset, len, access);
505}
506
a03490ed
CO		 507/*
508 * Load the pae pdptrs. Return true is they are all valid.
509 */
ff03a073 510int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 511{
512 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
513 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
514 int i;
515 int ret;
ff03a073 516 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 517
ff03a073
JR		 518 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
519 offset * sizeof(u64), sizeof(pdpte),
520 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 521 if (ret < 0) {
522 ret = 0;
523 goto out;
524 }
525 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 526 if (is_present_gpte(pdpte[i]) &&
20c466b5 527 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 528 ret = 0;
529 goto out;
530 }
531 }
532 ret = 1;
533
ff03a073 534 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 535 __set_bit(VCPU_EXREG_PDPTR,
536 (unsigned long *)&vcpu->arch.regs_avail);
537 __set_bit(VCPU_EXREG_PDPTR,
538 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 539out:
a03490ed
CO		 540
541 return ret;
542}
cc4b6871 543EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 544
d835dfec
AK		 545static bool pdptrs_changed(struct kvm_vcpu *vcpu)
546{
ff03a073 547 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 548 bool changed = true;
3d06b8bf
JR		 549 int offset;
550 gfn_t gfn;
d835dfec
AK		 551 int r;
552
553 if (is_long_mode(vcpu) || !is_pae(vcpu))
554 return false;
555
6de4f3ad
AK		 556 if (!test_bit(VCPU_EXREG_PDPTR,
557 (unsigned long *)&vcpu->arch.regs_avail))
558 return true;
559
9f8fe504
AK		 560 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
561 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 562 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
563 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 564 if (r < 0)
565 goto out;
ff03a073 566 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 567out:
d835dfec
AK		 568
569 return changed;
570}
571
49a9b07e 572int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 573{
aad82703
SY		 574 unsigned long old_cr0 = kvm_read_cr0(vcpu);
575 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
576 X86_CR0_CD | X86_CR0_NW;
577
f9a48e6a
AK		 578 cr0 |= X86_CR0_ET;
579
ab344828 580#ifdef CONFIG_X86_64
0f12244f
GN		 581 if (cr0 & 0xffffffff00000000UL)
582 return 1;
ab344828
GN		 583#endif
584
585 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 586
0f12244f
GN		 587 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
588 return 1;
a03490ed 589
0f12244f
GN		 590 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
591 return 1;
a03490ed
CO		 592
593 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
594#ifdef CONFIG_X86_64
f6801dff 595 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 596 int cs_db, cs_l;
597
0f12244f
GN		 598 if (!is_pae(vcpu))
599 return 1;
a03490ed 600 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 601 if (cs_l)
602 return 1;
a03490ed
CO		 603 } else
604#endif
ff03a073 605 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 606 kvm_read_cr3(vcpu)))
0f12244f 607 return 1;
a03490ed
CO		 608 }
609
ad756a16
MJ		 610 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
611 return 1;
612
a03490ed 613 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 614
d170c419 615 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 616 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 617 kvm_async_pf_hash_reset(vcpu);
618 }
e5f3f027 619
aad82703
SY		 620 if ((cr0 ^ old_cr0) & update_bits)
621 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 622 return 0;
623}
2d3ad1f4 624EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 625
2d3ad1f4 626void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 627{
49a9b07e 628 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 629}
2d3ad1f4 630EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 631
42bdf991
MT		 632static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
633{
634 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
635 !vcpu->guest_xcr0_loaded) {
636 /* kvm_set_xcr() also depends on this */
637 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
638 vcpu->guest_xcr0_loaded = 1;
639 }
640}
641
642static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
643{
644 if (vcpu->guest_xcr0_loaded) {
645 if (vcpu->arch.xcr0 != host_xcr0)
646 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
647 vcpu->guest_xcr0_loaded = 0;
648 }
649}
650
69b0049a 651static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 652{
56c103ec
LJ		 653 u64 xcr0 = xcr;
654 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 655 u64 valid_bits;
2acf923e
DC		 656
657 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
658 if (index != XCR_XFEATURE_ENABLED_MASK)
659 return 1;
2acf923e
DC		 660 if (!(xcr0 & XSTATE_FP))
661 return 1;
662 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
663 return 1;
46c34cb0
PB		 664
665 /*
666 * Do not allow the guest to set bits that we do not support
667 * saving. However, xcr0 bit 0 is always set, even if the
668 * emulated CPU does not support XSAVE (see fx_init).
669 */
670 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
671 if (xcr0 & ~valid_bits)
2acf923e 672 return 1;
46c34cb0 673
390bd528
LJ		 674 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
675 return 1;
676
612263b3
CP		 677 if (xcr0 & XSTATE_AVX512) {
678 if (!(xcr0 & XSTATE_YMM))
679 return 1;
680 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
681 return 1;
682 }
42bdf991 683 kvm_put_guest_xcr0(vcpu);
2acf923e 684 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 685
686 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
687 kvm_update_cpuid(vcpu);
2acf923e
DC		 688 return 0;
689}
690
691int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
692{
764bcbc5
Z		 693 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
694 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 695 kvm_inject_gp(vcpu, 0);
696 return 1;
697 }
698 return 0;
699}
700EXPORT_SYMBOL_GPL(kvm_set_xcr);
701
a83b29c6 702int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 703{
fc78f519 704 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 705 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
706 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 707 if (cr4 & CR4_RESERVED_BITS)
708 return 1;
a03490ed 709
2acf923e
DC		 710 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
711 return 1;
712
c68b734f
YW		 713 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
714 return 1;
715
97ec8c06
FW		 716 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
717 return 1;
718
afcbf13f 719 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 720 return 1;
721
a03490ed 722 if (is_long_mode(vcpu)) {
0f12244f
GN		 723 if (!(cr4 & X86_CR4_PAE))
724 return 1;
a2edf57f
AK		 725 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
726 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 727 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
728 kvm_read_cr3(vcpu)))
0f12244f
GN		 729 return 1;
730
ad756a16
MJ		 731 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
732 if (!guest_cpuid_has_pcid(vcpu))
733 return 1;
734
735 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
736 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
737 return 1;
738 }
739
5e1746d6 740 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 741 return 1;
a03490ed 742
ad756a16
MJ		 743 if (((cr4 ^ old_cr4) & pdptr_bits) ||
744 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 745 kvm_mmu_reset_context(vcpu);
0f12244f 746
97ec8c06
FW		 747 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
748 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
749
2acf923e 750 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 751 kvm_update_cpuid(vcpu);
2acf923e 752
0f12244f
GN		 753 return 0;
754}
2d3ad1f4 755EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 756
2390218b 757int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 758{
ac146235 759#ifdef CONFIG_X86_64
9d88fca7 760 cr3 &= ~CR3_PCID_INVD;
ac146235 761#endif
9d88fca7 762
9f8fe504 763 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 764 kvm_mmu_sync_roots(vcpu);
77c3913b 765 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 766 return 0;
d835dfec
AK		 767 }
768
a03490ed 769 if (is_long_mode(vcpu)) {
d9f89b88
JK		 770 if (cr3 & CR3_L_MODE_RESERVED_BITS)
771 return 1;
772 } else if (is_pae(vcpu) && is_paging(vcpu) &&
773 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 774 return 1;
a03490ed 775
0f12244f 776 vcpu->arch.cr3 = cr3;
aff48baa 777 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 778 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 779 return 0;
780}
2d3ad1f4 781EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 782
eea1cff9 783int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 784{
0f12244f
GN		 785 if (cr8 & CR8_RESERVED_BITS)
786 return 1;
a03490ed
CO		 787 if (irqchip_in_kernel(vcpu->kvm))
788 kvm_lapic_set_tpr(vcpu, cr8);
789 else
ad312c7c 790 vcpu->arch.cr8 = cr8;
0f12244f
GN		 791 return 0;
792}
2d3ad1f4 793EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 794
2d3ad1f4 795unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 796{
797 if (irqchip_in_kernel(vcpu->kvm))
798 return kvm_lapic_get_cr8(vcpu);
799 else
ad312c7c 800 return vcpu->arch.cr8;
a03490ed 801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 803
ae561ede
NA		 804static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
805{
806 int i;
807
808 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
809 for (i = 0; i < KVM_NR_DB_REGS; i++)
810 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
811 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
812 }
813}
814
73aaf249
JK		 815static void kvm_update_dr6(struct kvm_vcpu *vcpu)
816{
817 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
818 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
819}
820
c8639010
JK		 821static void kvm_update_dr7(struct kvm_vcpu *vcpu)
822{
823 unsigned long dr7;
824
825 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
826 dr7 = vcpu->arch.guest_debug_dr7;
827 else
828 dr7 = vcpu->arch.dr7;
829 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 830 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
831 if (dr7 & DR7_BP_EN_MASK)
832 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 833}
834
6f43ed01
NA		 835static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
836{
837 u64 fixed = DR6_FIXED_1;
838
839 if (!guest_cpuid_has_rtm(vcpu))
840 fixed |= DR6_RTM;
841 return fixed;
842}
843
338dbc97 844static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 845{
846 switch (dr) {
847 case 0 ... 3:
848 vcpu->arch.db[dr] = val;
849 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
850 vcpu->arch.eff_db[dr] = val;
851 break;
852 case 4:
020df079
GN		 853 /* fall through */
854 case 6:
338dbc97
GN		 855 if (val & 0xffffffff00000000ULL)
856 return -1; /* #GP */
6f43ed01 857 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 858 kvm_update_dr6(vcpu);
020df079
GN		 859 break;
860 case 5:
020df079
GN		 861 /* fall through */
862 default: /* 7 */
338dbc97
GN		 863 if (val & 0xffffffff00000000ULL)
864 return -1; /* #GP */
020df079 865 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 866 kvm_update_dr7(vcpu);
020df079
GN		 867 break;
868 }
869
870 return 0;
871}
338dbc97
GN		 872
873int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
874{
16f8a6f9 875 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 876 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 877 return 1;
878 }
879 return 0;
338dbc97 880}
020df079
GN		 881EXPORT_SYMBOL_GPL(kvm_set_dr);
882
16f8a6f9 883int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 884{
885 switch (dr) {
886 case 0 ... 3:
887 *val = vcpu->arch.db[dr];
888 break;
889 case 4:
020df079
GN		 890 /* fall through */
891 case 6:
73aaf249
JK		 892 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
893 *val = vcpu->arch.dr6;
894 else
895 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 896 break;
897 case 5:
020df079
GN		 898 /* fall through */
899 default: /* 7 */
900 *val = vcpu->arch.dr7;
901 break;
902 }
338dbc97
GN		 903 return 0;
904}
020df079
GN		 905EXPORT_SYMBOL_GPL(kvm_get_dr);
906
022cd0e8
AK		 907bool kvm_rdpmc(struct kvm_vcpu *vcpu)
908{
909 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
910 u64 data;
911 int err;
912
913 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
914 if (err)
915 return err;
916 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
917 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
918 return err;
919}
920EXPORT_SYMBOL_GPL(kvm_rdpmc);
921
043405e1
CO		 922/*
923 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
924 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
925 *
926 * This list is modified at module load time to reflect the
e3267cbb
GC		 927 * capabilities of the host cpu. This capabilities test skips MSRs that are
928 * kvm-specific. Those are put in the beginning of the list.
043405e1 929 */
e3267cbb 930
e984097b 931#define KVM_SAVE_MSRS_BEGIN 12
043405e1 932static u32 msrs_to_save[] = {
e3267cbb 933 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 934 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 935 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 936 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 937 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 938 MSR_KVM_PV_EOI_EN,
043405e1 939 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 940 MSR_STAR,
043405e1
CO		 941#ifdef CONFIG_X86_64
942 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
943#endif
b3897a49 944 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 945 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 946};
947
948static unsigned num_msrs_to_save;
949
f1d24831 950static const u32 emulated_msrs[] = {
ba904635 951 MSR_IA32_TSC_ADJUST,
a3e06bbe 952 MSR_IA32_TSCDEADLINE,
043405e1 953 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 954 MSR_IA32_MCG_STATUS,
955 MSR_IA32_MCG_CTL,
043405e1
CO		 956};
957
384bb783 958bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 959{
b69e8cae 960 if (efer & efer_reserved_bits)
384bb783 961 return false;
15c4a640 962
1b2fd70c
AG		 963 if (efer & EFER_FFXSR) {
964 struct kvm_cpuid_entry2 *feat;
965
966 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 967 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 968 return false;
1b2fd70c
AG		 969 }
970
d8017474
AG		 971 if (efer & EFER_SVME) {
972 struct kvm_cpuid_entry2 *feat;
973
974 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 975 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 976 return false;
d8017474
AG		 977 }
978
384bb783
JK		 979 return true;
980}
981EXPORT_SYMBOL_GPL(kvm_valid_efer);
982
983static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
984{
985 u64 old_efer = vcpu->arch.efer;
986
987 if (!kvm_valid_efer(vcpu, efer))
988 return 1;
989
990 if (is_paging(vcpu)
991 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
992 return 1;
993
15c4a640 994 efer &= ~EFER_LMA;
f6801dff 995 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 996
a3d204e2
SY		 997 kvm_x86_ops->set_efer(vcpu, efer);
998
aad82703
SY		 999 /* Update reserved bits */
1000 if ((efer ^ old_efer) & EFER_NX)
1001 kvm_mmu_reset_context(vcpu);
1002
b69e8cae 1003 return 0;
15c4a640
CO		 1004}
1005
f2b4b7dd
JR		 1006void kvm_enable_efer_bits(u64 mask)
1007{
1008 efer_reserved_bits &= ~mask;
1009}
1010EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1011
15c4a640
CO		 1012/*
1013 * Writes msr value into into the appropriate "register".
1014 * Returns 0 on success, non-0 otherwise.
1015 * Assumes vcpu_load() was already called.
1016 */
8fe8ab46 1017int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1018{
854e8bb1
NA		 1019 switch (msr->index) {
1020 case MSR_FS_BASE:
1021 case MSR_GS_BASE:
1022 case MSR_KERNEL_GS_BASE:
1023 case MSR_CSTAR:
1024 case MSR_LSTAR:
1025 if (is_noncanonical_address(msr->data))
1026 return 1;
1027 break;
1028 case MSR_IA32_SYSENTER_EIP:
1029 case MSR_IA32_SYSENTER_ESP:
1030 /*
1031 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1032 * non-canonical address is written on Intel but not on
1033 * AMD (which ignores the top 32-bits, because it does
1034 * not implement 64-bit SYSENTER).
1035 *
1036 * 64-bit code should hence be able to write a non-canonical
1037 * value on AMD. Making the address canonical ensures that
1038 * vmentry does not fail on Intel after writing a non-canonical
1039 * value, and that something deterministic happens if the guest
1040 * invokes 64-bit SYSENTER.
1041 */
1042 msr->data = get_canonical(msr->data);
1043 }
8fe8ab46 1044 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1045}
854e8bb1 1046EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1047
313a3dc7
CO		 1048/*
1049 * Adapt set_msr() to msr_io()'s calling convention
1050 */
1051static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1052{
8fe8ab46
WA		 1053 struct msr_data msr;
1054
1055 msr.data = *data;
1056 msr.index = index;
1057 msr.host_initiated = true;
1058 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1059}
1060
16e8d74d
MT		 1061#ifdef CONFIG_X86_64
1062struct pvclock_gtod_data {
1063 seqcount_t seq;
1064
1065 struct { /* extract of a clocksource struct */
1066 int vclock_mode;
1067 cycle_t cycle_last;
1068 cycle_t mask;
1069 u32 mult;
1070 u32 shift;
1071 } clock;
1072
cbcf2dd3
TG		 1073 u64 boot_ns;
1074 u64 nsec_base;
16e8d74d
MT		 1075};
1076
1077static struct pvclock_gtod_data pvclock_gtod_data;
1078
1079static void update_pvclock_gtod(struct timekeeper *tk)
1080{
1081 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1082 u64 boot_ns;
1083
876e7881 1084 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1085
1086 write_seqcount_begin(&vdata->seq);
1087
1088 /* copy pvclock gtod data */
876e7881
PZ		 1089 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1090 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1091 vdata->clock.mask = tk->tkr_mono.mask;
1092 vdata->clock.mult = tk->tkr_mono.mult;
1093 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1094
cbcf2dd3 1095 vdata->boot_ns = boot_ns;
876e7881 1096 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1097
1098 write_seqcount_end(&vdata->seq);
1099}
1100#endif
1101
bab5bb39
NK		 1102void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1103{
1104 /*
1105 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1106 * vcpu_enter_guest. This function is only called from
1107 * the physical CPU that is running vcpu.
1108 */
1109 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1110}
16e8d74d 1111
18068523
GOC		 1112static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1113{
9ed3c444
AK		 1114 int version;
1115 int r;
50d0a0f9 1116 struct pvclock_wall_clock wc;
923de3cf 1117 struct timespec boot;
18068523
GOC		 1118
1119 if (!wall_clock)
1120 return;
1121
9ed3c444
AK		 1122 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1123 if (r)
1124 return;
1125
1126 if (version & 1)
1127 ++version; /* first time write, random junk */
1128
1129 ++version;
18068523 1130
18068523
GOC		 1131 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1132
50d0a0f9
GH		 1133 /*
1134 * The guest calculates current wall clock time by adding
34c238a1 1135 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1136 * wall clock specified here. guest system time equals host
1137 * system time for us, thus we must fill in host boot time here.
1138 */
923de3cf 1139 getboottime(&boot);
50d0a0f9 1140
4b648665
BR		 1141 if (kvm->arch.kvmclock_offset) {
1142 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1143 boot = timespec_sub(boot, ts);
1144 }
50d0a0f9
GH		 1145 wc.sec = boot.tv_sec;
1146 wc.nsec = boot.tv_nsec;
1147 wc.version = version;
18068523
GOC		 1148
1149 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1150
1151 version++;
1152 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1153}
1154
50d0a0f9
GH		 1155static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1156{
1157 uint32_t quotient, remainder;
1158
1159 /* Don't try to replace with do_div(), this one calculates
1160 * "(dividend << 32) / divisor" */
1161 __asm__ ( "divl %4"
1162 : "=a" (quotient), "=d" (remainder)
1163 : "0" (0), "1" (dividend), "r" (divisor) );
1164 return quotient;
1165}
1166
5f4e3f88
ZA		 1167static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1168 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1169{
5f4e3f88 1170 uint64_t scaled64;
50d0a0f9
GH		 1171 int32_t shift = 0;
1172 uint64_t tps64;
1173 uint32_t tps32;
1174
5f4e3f88
ZA		 1175 tps64 = base_khz * 1000LL;
1176 scaled64 = scaled_khz * 1000LL;
50933623 1177 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1178 tps64 >>= 1;
1179 shift--;
1180 }
1181
1182 tps32 = (uint32_t)tps64;
50933623
JK		 1183 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1184 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1185 scaled64 >>= 1;
1186 else
1187 tps32 <<= 1;
50d0a0f9
GH		 1188 shift++;
1189 }
1190
5f4e3f88
ZA		 1191 *pshift = shift;
1192 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1193
5f4e3f88
ZA		 1194 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1195 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1196}
1197
759379dd
ZA		 1198static inline u64 get_kernel_ns(void)
1199{
bb0b5812 1200 return ktime_get_boot_ns();
50d0a0f9
GH		 1201}
1202
d828199e 1203#ifdef CONFIG_X86_64
16e8d74d 1204static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1205#endif
16e8d74d 1206
c8076604 1207static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1208static unsigned long max_tsc_khz;
c8076604 1209
cc578287 1210static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1211{
cc578287
ZA		 1212 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1213 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1214}
1215
cc578287 1216static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1217{
cc578287
ZA		 1218 u64 v = (u64)khz * (1000000 + ppm);
1219 do_div(v, 1000000);
1220 return v;
1e993611
JR		 1221}
1222
cc578287 1223static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1224{
cc578287
ZA		 1225 u32 thresh_lo, thresh_hi;
1226 int use_scaling = 0;
217fc9cf 1227
03ba32ca
MT		 1228 /* tsc_khz can be zero if TSC calibration fails */
1229 if (this_tsc_khz == 0)
1230 return;
1231
c285545f
ZA		 1232 /* Compute a scale to convert nanoseconds in TSC cycles */
1233 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1234 &vcpu->arch.virtual_tsc_shift,
1235 &vcpu->arch.virtual_tsc_mult);
1236 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1237
1238 /*
1239 * Compute the variation in TSC rate which is acceptable
1240 * within the range of tolerance and decide if the
1241 * rate being applied is within that bounds of the hardware
1242 * rate. If so, no scaling or compensation need be done.
1243 */
1244 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1245 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1246 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1247 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1248 use_scaling = 1;
1249 }
1250 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1251}
1252
1253static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1254{
e26101b1 1255 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1256 vcpu->arch.virtual_tsc_mult,
1257 vcpu->arch.virtual_tsc_shift);
e26101b1 1258 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1259 return tsc;
1260}
1261
69b0049a 1262static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1263{
1264#ifdef CONFIG_X86_64
1265 bool vcpus_matched;
b48aa97e
MT		 1266 struct kvm_arch *ka = &vcpu->kvm->arch;
1267 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1268
1269 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1270 atomic_read(&vcpu->kvm->online_vcpus));
1271
7f187922
MT		 1272 /*
1273 * Once the masterclock is enabled, always perform request in
1274 * order to update it.
1275 *
1276 * In order to enable masterclock, the host clocksource must be TSC
1277 * and the vcpus need to have matched TSCs. When that happens,
1278 * perform request to enable masterclock.
1279 */
1280 if (ka->use_master_clock ||
1281 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1282 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1283
1284 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1285 atomic_read(&vcpu->kvm->online_vcpus),
1286 ka->use_master_clock, gtod->clock.vclock_mode);
1287#endif
1288}
1289
ba904635
WA		 1290static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1291{
1292 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1293 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1294}
1295
8fe8ab46 1296void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1297{
1298 struct kvm *kvm = vcpu->kvm;
f38e098f 1299 u64 offset, ns, elapsed;
99e3e30a 1300 unsigned long flags;
02626b6a 1301 s64 usdiff;
b48aa97e 1302 bool matched;
0d3da0d2 1303 bool already_matched;
8fe8ab46 1304 u64 data = msr->data;
99e3e30a 1305
038f8c11 1306 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1307 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1308 ns = get_kernel_ns();
f38e098f 1309 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1310
03ba32ca 1311 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1312 int faulted = 0;
1313
03ba32ca
MT		 1314 /* n.b - signed multiplication and division required */
1315 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1316#ifdef CONFIG_X86_64
03ba32ca 1317 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1318#else
03ba32ca 1319 /* do_div() only does unsigned */
8915aa27
MT		 1320 asm("1: idivl %[divisor]\n"
1321 "2: xor %%edx, %%edx\n"
1322 " movl $0, %[faulted]\n"
1323 "3:\n"
1324 ".section .fixup,\"ax\"\n"
1325 "4: movl $1, %[faulted]\n"
1326 " jmp 3b\n"
1327 ".previous\n"
1328
1329 _ASM_EXTABLE(1b, 4b)
1330
1331 : "=A"(usdiff), [faulted] "=r" (faulted)
1332 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1333
5d3cb0f6 1334#endif
03ba32ca
MT		 1335 do_div(elapsed, 1000);
1336 usdiff -= elapsed;
1337 if (usdiff < 0)
1338 usdiff = -usdiff;
8915aa27
MT		 1339
1340 /* idivl overflow => difference is larger than USEC_PER_SEC */
1341 if (faulted)
1342 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1343 } else
1344 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1345
1346 /*
5d3cb0f6
ZA		 1347 * Special case: TSC write with a small delta (1 second) of virtual
1348 * cycle time against real time is interpreted as an attempt to
1349 * synchronize the CPU.
1350 *
1351 * For a reliable TSC, we can match TSC offsets, and for an unstable
1352 * TSC, we add elapsed time in this computation. We could let the
1353 * compensation code attempt to catch up if we fall behind, but
1354 * it's better to try to match offsets from the beginning.
1355 */
02626b6a 1356 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1357 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1358 if (!check_tsc_unstable()) {
e26101b1 1359 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1360 pr_debug("kvm: matched tsc offset for %llu\n", data);
1361 } else {
857e4099 1362 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1363 data += delta;
1364 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1365 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1366 }
b48aa97e 1367 matched = true;
0d3da0d2 1368 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1369 } else {
1370 /*
1371 * We split periods of matched TSC writes into generations.
1372 * For each generation, we track the original measured
1373 * nanosecond time, offset, and write, so if TSCs are in
1374 * sync, we can match exact offset, and if not, we can match
4a969980 1375 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1376 *
1377 * These values are tracked in kvm->arch.cur_xxx variables.
1378 */
1379 kvm->arch.cur_tsc_generation++;
1380 kvm->arch.cur_tsc_nsec = ns;
1381 kvm->arch.cur_tsc_write = data;
1382 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1383 matched = false;
0d3da0d2 1384 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1385 kvm->arch.cur_tsc_generation, data);
f38e098f 1386 }
e26101b1
ZA		 1387
1388 /*
1389 * We also track th most recent recorded KHZ, write and time to
1390 * allow the matching interval to be extended at each write.
1391 */
f38e098f
ZA		 1392 kvm->arch.last_tsc_nsec = ns;
1393 kvm->arch.last_tsc_write = data;
5d3cb0f6 1394 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1395
b183aa58 1396 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1397
1398 /* Keep track of which generation this VCPU has synchronized to */
1399 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1400 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1401 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1402
ba904635
WA		 1403 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1404 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1405 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1406 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1407
1408 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1409 if (!matched) {
b48aa97e 1410 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1411 } else if (!already_matched) {
1412 kvm->arch.nr_vcpus_matched_tsc++;
1413 }
b48aa97e
MT		 1414
1415 kvm_track_tsc_matching(vcpu);
1416 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1417}
e26101b1 1418
99e3e30a
ZA		 1419EXPORT_SYMBOL_GPL(kvm_write_tsc);
1420
d828199e
MT		 1421#ifdef CONFIG_X86_64
1422
1423static cycle_t read_tsc(void)
1424{
1425 cycle_t ret;
1426 u64 last;
1427
1428 /*
1429 * Empirically, a fence (of type that depends on the CPU)
1430 * before rdtsc is enough to ensure that rdtsc is ordered
1431 * with respect to loads. The various CPU manuals are unclear
1432 * as to whether rdtsc can be reordered with later loads,
1433 * but no one has ever seen it happen.
1434 */
1435 rdtsc_barrier();
1436 ret = (cycle_t)vget_cycles();
1437
1438 last = pvclock_gtod_data.clock.cycle_last;
1439
1440 if (likely(ret >= last))
1441 return ret;
1442
1443 /*
1444 * GCC likes to generate cmov here, but this branch is extremely
1445 * predictable (it's just a funciton of time and the likely is
1446 * very likely) and there's a data dependence, so force GCC
1447 * to generate a branch instead. I don't barrier() because
1448 * we don't actually need a barrier, and if this function
1449 * ever gets inlined it will generate worse code.
1450 */
1451 asm volatile ("");
1452 return last;
1453}
1454
1455static inline u64 vgettsc(cycle_t *cycle_now)
1456{
1457 long v;
1458 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1459
1460 *cycle_now = read_tsc();
1461
1462 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1463 return v * gtod->clock.mult;
1464}
1465
cbcf2dd3 1466static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1467{
cbcf2dd3 1468 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1469 unsigned long seq;
d828199e 1470 int mode;
cbcf2dd3 1471 u64 ns;
d828199e 1472
d828199e
MT		 1473 do {
1474 seq = read_seqcount_begin(&gtod->seq);
1475 mode = gtod->clock.vclock_mode;
cbcf2dd3 1476 ns = gtod->nsec_base;
d828199e
MT		 1477 ns += vgettsc(cycle_now);
1478 ns >>= gtod->clock.shift;
cbcf2dd3 1479 ns += gtod->boot_ns;
d828199e 1480 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1481 *t = ns;
d828199e
MT		 1482
1483 return mode;
1484}
1485
1486/* returns true if host is using tsc clocksource */
1487static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1488{
d828199e
MT		 1489 /* checked again under seqlock below */
1490 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1491 return false;
1492
cbcf2dd3 1493 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1494}
1495#endif
1496
1497/*
1498 *
b48aa97e
MT		 1499 * Assuming a stable TSC across physical CPUS, and a stable TSC
1500 * across virtual CPUs, the following condition is possible.
1501 * Each numbered line represents an event visible to both
d828199e
MT		 1502 * CPUs at the next numbered event.
1503 *
1504 * "timespecX" represents host monotonic time. "tscX" represents
1505 * RDTSC value.
1506 *
1507 * VCPU0 on CPU0 | VCPU1 on CPU1
1508 *
1509 * 1. read timespec0,tsc0
1510 * 2. | timespec1 = timespec0 + N
1511 * | tsc1 = tsc0 + M
1512 * 3. transition to guest | transition to guest
1513 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1514 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1515 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1516 *
1517 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1518 *
1519 * - ret0 < ret1
1520 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1521 * ...
1522 * - 0 < N - M => M < N
1523 *
1524 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1525 * always the case (the difference between two distinct xtime instances
1526 * might be smaller then the difference between corresponding TSC reads,
1527 * when updating guest vcpus pvclock areas).
1528 *
1529 * To avoid that problem, do not allow visibility of distinct
1530 * system_timestamp/tsc_timestamp values simultaneously: use a master
1531 * copy of host monotonic time values. Update that master copy
1532 * in lockstep.
1533 *
b48aa97e 1534 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1535 *
1536 */
1537
1538static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1539{
1540#ifdef CONFIG_X86_64
1541 struct kvm_arch *ka = &kvm->arch;
1542 int vclock_mode;
b48aa97e
MT		 1543 bool host_tsc_clocksource, vcpus_matched;
1544
1545 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1546 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1547
1548 /*
1549 * If the host uses TSC clock, then passthrough TSC as stable
1550 * to the guest.
1551 */
b48aa97e 1552 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1553 &ka->master_kernel_ns,
1554 &ka->master_cycle_now);
1555
16a96021 1556 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1557 && !backwards_tsc_observed
1558 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1559
d828199e
MT		 1560 if (ka->use_master_clock)
1561 atomic_set(&kvm_guest_has_master_clock, 1);
1562
1563 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1564 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1565 vcpus_matched);
d828199e
MT		 1566#endif
1567}
1568
2e762ff7
MT		 1569static void kvm_gen_update_masterclock(struct kvm *kvm)
1570{
1571#ifdef CONFIG_X86_64
1572 int i;
1573 struct kvm_vcpu *vcpu;
1574 struct kvm_arch *ka = &kvm->arch;
1575
1576 spin_lock(&ka->pvclock_gtod_sync_lock);
1577 kvm_make_mclock_inprogress_request(kvm);
1578 /* no guest entries from this point */
1579 pvclock_update_vm_gtod_copy(kvm);
1580
1581 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1582 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1583
1584 /* guest entries allowed */
1585 kvm_for_each_vcpu(i, vcpu, kvm)
1586 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1587
1588 spin_unlock(&ka->pvclock_gtod_sync_lock);
1589#endif
1590}
1591
34c238a1 1592static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1593{
d828199e 1594 unsigned long flags, this_tsc_khz;
18068523 1595 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1596 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1597 s64 kernel_ns;
d828199e 1598 u64 tsc_timestamp, host_tsc;
0b79459b 1599 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1600 u8 pvclock_flags;
d828199e
MT		 1601 bool use_master_clock;
1602
1603 kernel_ns = 0;
1604 host_tsc = 0;
18068523 1605
d828199e
MT		 1606 /*
1607 * If the host uses TSC clock, then passthrough TSC as stable
1608 * to the guest.
1609 */
1610 spin_lock(&ka->pvclock_gtod_sync_lock);
1611 use_master_clock = ka->use_master_clock;
1612 if (use_master_clock) {
1613 host_tsc = ka->master_cycle_now;
1614 kernel_ns = ka->master_kernel_ns;
1615 }
1616 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1617
1618 /* Keep irq disabled to prevent changes to the clock */
1619 local_irq_save(flags);
89cbc767 1620 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1621 if (unlikely(this_tsc_khz == 0)) {
1622 local_irq_restore(flags);
1623 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1624 return 1;
1625 }
d828199e
MT		 1626 if (!use_master_clock) {
1627 host_tsc = native_read_tsc();
1628 kernel_ns = get_kernel_ns();
1629 }
1630
1631 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1632
c285545f
ZA		 1633 /*
1634 * We may have to catch up the TSC to match elapsed wall clock
1635 * time for two reasons, even if kvmclock is used.
1636 * 1) CPU could have been running below the maximum TSC rate
1637 * 2) Broken TSC compensation resets the base at each VCPU
1638 * entry to avoid unknown leaps of TSC even when running
1639 * again on the same CPU. This may cause apparent elapsed
1640 * time to disappear, and the guest to stand still or run
1641 * very slowly.
1642 */
1643 if (vcpu->tsc_catchup) {
1644 u64 tsc = compute_guest_tsc(v, kernel_ns);
1645 if (tsc > tsc_timestamp) {
f1e2b260 1646 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1647 tsc_timestamp = tsc;
1648 }
50d0a0f9
GH		 1649 }
1650
18068523
GOC		 1651 local_irq_restore(flags);
1652
0b79459b 1653 if (!vcpu->pv_time_enabled)
c285545f 1654 return 0;
18068523 1655
e48672fa 1656 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1657 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1658 &vcpu->hv_clock.tsc_shift,
1659 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1660 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1661 }
1662
1663 /* With all the info we got, fill in the values */
1d5f066e 1664 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1665 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1666 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1667
09a0c3f1
OH		 1668 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1669 &guest_hv_clock, sizeof(guest_hv_clock))))
1670 return 0;
1671
5dca0d91
RK		 1672 /* This VCPU is paused, but it's legal for a guest to read another
1673 * VCPU's kvmclock, so we really have to follow the specification where
1674 * it says that version is odd if data is being modified, and even after
1675 * it is consistent.
1676 *
1677 * Version field updates must be kept separate. This is because
1678 * kvm_write_guest_cached might use a "rep movs" instruction, and
1679 * writes within a string instruction are weakly ordered. So there
1680 * are three writes overall.
1681 *
1682 * As a small optimization, only write the version field in the first
1683 * and third write. The vcpu->pv_time cache is still valid, because the
1684 * version field is the first in the struct.
18068523 1685 */
5dca0d91
RK		 1686 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1687
1688 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1689 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1690 &vcpu->hv_clock,
1691 sizeof(vcpu->hv_clock.version));
1692
1693 smp_wmb();
78c0337a
MT		 1694
1695 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1696 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1697
1698 if (vcpu->pvclock_set_guest_stopped_request) {
1699 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1700 vcpu->pvclock_set_guest_stopped_request = false;
1701 }
1702
d828199e
MT		 1703 /* If the host uses TSC clocksource, then it is stable */
1704 if (use_master_clock)
1705 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1706
78c0337a
MT		 1707 vcpu->hv_clock.flags = pvclock_flags;
1708
ce1a5e60
DM		 1709 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1710
0b79459b
AH		 1711 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1712 &vcpu->hv_clock,
1713 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1714
1715 smp_wmb();
1716
1717 vcpu->hv_clock.version++;
1718 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1719 &vcpu->hv_clock,
1720 sizeof(vcpu->hv_clock.version));
8cfdc000 1721 return 0;
c8076604
GH		 1722}
1723
0061d53d
MT		 1724/*
1725 * kvmclock updates which are isolated to a given vcpu, such as
1726 * vcpu->cpu migration, should not allow system_timestamp from
1727 * the rest of the vcpus to remain static. Otherwise ntp frequency
1728 * correction applies to one vcpu's system_timestamp but not
1729 * the others.
1730 *
1731 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1732 * We need to rate-limit these requests though, as they can
1733 * considerably slow guests that have a large number of vcpus.
1734 * The time for a remote vcpu to update its kvmclock is bound
1735 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1736 */
1737
7e44e449
AJ		 1738#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1739
1740static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1741{
1742 int i;
7e44e449
AJ		 1743 struct delayed_work *dwork = to_delayed_work(work);
1744 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1745 kvmclock_update_work);
1746 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1747 struct kvm_vcpu *vcpu;
1748
1749 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1750 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1751 kvm_vcpu_kick(vcpu);
1752 }
1753}
1754
7e44e449
AJ		 1755static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1756{
1757 struct kvm *kvm = v->kvm;
1758
105b21bb 1759 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1760 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1761 KVMCLOCK_UPDATE_DELAY);
1762}
1763
332967a3
AJ		 1764#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1765
1766static void kvmclock_sync_fn(struct work_struct *work)
1767{
1768 struct delayed_work *dwork = to_delayed_work(work);
1769 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1770 kvmclock_sync_work);
1771 struct kvm *kvm = container_of(ka, struct kvm, arch);
1772
1773 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1774 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1775 KVMCLOCK_SYNC_PERIOD);
1776}
1777
9ba075a6
AK		 1778static bool msr_mtrr_valid(unsigned msr)
1779{
1780 switch (msr) {
1781 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1782 case MSR_MTRRfix64K_00000:
1783 case MSR_MTRRfix16K_80000:
1784 case MSR_MTRRfix16K_A0000:
1785 case MSR_MTRRfix4K_C0000:
1786 case MSR_MTRRfix4K_C8000:
1787 case MSR_MTRRfix4K_D0000:
1788 case MSR_MTRRfix4K_D8000:
1789 case MSR_MTRRfix4K_E0000:
1790 case MSR_MTRRfix4K_E8000:
1791 case MSR_MTRRfix4K_F0000:
1792 case MSR_MTRRfix4K_F8000:
1793 case MSR_MTRRdefType:
1794 case MSR_IA32_CR_PAT:
1795 return true;
1796 case 0x2f8:
1797 return true;
1798 }
1799 return false;
1800}
1801
d6289b93
MT		 1802static bool valid_pat_type(unsigned t)
1803{
1804 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1805}
1806
1807static bool valid_mtrr_type(unsigned t)
1808{
1809 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1810}
1811
4566654b 1812bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1813{
1814 int i;
fd275235 1815 u64 mask;
d6289b93
MT		 1816
1817 if (!msr_mtrr_valid(msr))
1818 return false;
1819
1820 if (msr == MSR_IA32_CR_PAT) {
1821 for (i = 0; i < 8; i++)
1822 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1823 return false;
1824 return true;
1825 } else if (msr == MSR_MTRRdefType) {
1826 if (data & ~0xcff)
1827 return false;
1828 return valid_mtrr_type(data & 0xff);
1829 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1830 for (i = 0; i < 8 ; i++)
1831 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1832 return false;
1833 return true;
1834 }
1835
1836 /* variable MTRRs */
adfb5d27
WL		 1837 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1838
fd275235 1839 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1840 if ((msr & 1) == 0) {
adfb5d27 1841 /* MTRR base */
d7a2a246
WL		 1842 if (!valid_mtrr_type(data & 0xff))
1843 return false;
1844 mask |= 0xf00;
1845 } else
1846 /* MTRR mask */
1847 mask |= 0x7ff;
1848 if (data & mask) {
1849 kvm_inject_gp(vcpu, 0);
1850 return false;
1851 }
1852
adfb5d27 1853 return true;
d6289b93 1854}
4566654b 1855EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1856
9ba075a6
AK		 1857static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1858{
0bed3b56
SY		 1859 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1860
4566654b 1861 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1862 return 1;
1863
0bed3b56
SY		 1864 if (msr == MSR_MTRRdefType) {
1865 vcpu->arch.mtrr_state.def_type = data;
1866 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1867 } else if (msr == MSR_MTRRfix64K_00000)
1868 p[0] = data;
1869 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1870 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1871 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1872 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1873 else if (msr == MSR_IA32_CR_PAT)
1874 vcpu->arch.pat = data;
1875 else { /* Variable MTRRs */
1876 int idx, is_mtrr_mask;
1877 u64 *pt;
1878
1879 idx = (msr - 0x200) / 2;
1880 is_mtrr_mask = msr - 0x200 - 2 * idx;
1881 if (!is_mtrr_mask)
1882 pt =
1883 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1884 else
1885 pt =
1886 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1887 *pt = data;
1888 }
1889
1890 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1891 return 0;
1892}
15c4a640 1893
890ca9ae 1894static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1895{
890ca9ae
HY		 1896 u64 mcg_cap = vcpu->arch.mcg_cap;
1897 unsigned bank_num = mcg_cap & 0xff;
1898
15c4a640 1899 switch (msr) {
15c4a640 1900 case MSR_IA32_MCG_STATUS:
890ca9ae 1901 vcpu->arch.mcg_status = data;
15c4a640 1902 break;
c7ac679c 1903 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1904 if (!(mcg_cap & MCG_CTL_P))
1905 return 1;
1906 if (data != 0 && data != ~(u64)0)
1907 return -1;
1908 vcpu->arch.mcg_ctl = data;
1909 break;
1910 default:
1911 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1912 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1913 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1914 /* only 0 or all 1s can be written to IA32_MCi_CTL
1915 * some Linux kernels though clear bit 10 in bank 4 to
1916 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1917 * this to avoid an uncatched #GP in the guest
1918 */
890ca9ae 1919 if ((offset & 0x3) == 0 &&
114be429 1920 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1921 return -1;
1922 vcpu->arch.mce_banks[offset] = data;
1923 break;
1924 }
1925 return 1;
1926 }
1927 return 0;
1928}
1929
ffde22ac
ES		 1930static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1931{
1932 struct kvm *kvm = vcpu->kvm;
1933 int lm = is_long_mode(vcpu);
1934 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1935 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1936 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1937 : kvm->arch.xen_hvm_config.blob_size_32;
1938 u32 page_num = data & ~PAGE_MASK;
1939 u64 page_addr = data & PAGE_MASK;
1940 u8 *page;
1941 int r;
1942
1943 r = -E2BIG;
1944 if (page_num >= blob_size)
1945 goto out;
1946 r = -ENOMEM;
ff5c2c03
SL		 1947 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1948 if (IS_ERR(page)) {
1949 r = PTR_ERR(page);
ffde22ac 1950 goto out;
ff5c2c03 1951 }
ffde22ac
ES		 1952 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1953 goto out_free;
1954 r = 0;
1955out_free:
1956 kfree(page);
1957out:
1958 return r;
1959}
1960
55cd8e5a
GN		 1961static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1962{
1963 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1964}
1965
1966static bool kvm_hv_msr_partition_wide(u32 msr)
1967{
1968 bool r = false;
1969 switch (msr) {
1970 case HV_X64_MSR_GUEST_OS_ID:
1971 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1972 case HV_X64_MSR_REFERENCE_TSC:
1973 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1974 r = true;
1975 break;
1976 }
1977
1978 return r;
1979}
1980
1981static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1982{
1983 struct kvm *kvm = vcpu->kvm;
1984
1985 switch (msr) {
1986 case HV_X64_MSR_GUEST_OS_ID:
1987 kvm->arch.hv_guest_os_id = data;
1988 /* setting guest os id to zero disables hypercall page */
1989 if (!kvm->arch.hv_guest_os_id)
1990 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1991 break;
1992 case HV_X64_MSR_HYPERCALL: {
1993 u64 gfn;
1994 unsigned long addr;
1995 u8 instructions[4];
1996
1997 /* if guest os id is not set hypercall should remain disabled */
1998 if (!kvm->arch.hv_guest_os_id)
1999 break;
2000 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
2001 kvm->arch.hv_hypercall = data;
2002 break;
2003 }
2004 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
2005 addr = gfn_to_hva(kvm, gfn);
2006 if (kvm_is_error_hva(addr))
2007 return 1;
2008 kvm_x86_ops->patch_hypercall(vcpu, instructions);
2009 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 2010 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 2011 return 1;
2012 kvm->arch.hv_hypercall = data;
b94b64c9 2013 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 2014 break;
2015 }
e984097b
VR		 2016 case HV_X64_MSR_REFERENCE_TSC: {
2017 u64 gfn;
2018 HV_REFERENCE_TSC_PAGE tsc_ref;
2019 memset(&tsc_ref, 0, sizeof(tsc_ref));
2020 kvm->arch.hv_tsc_page = data;
2021 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
2022 break;
2023 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 2024 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 2025 &tsc_ref, sizeof(tsc_ref)))
2026 return 1;
2027 mark_page_dirty(kvm, gfn);
2028 break;
2029 }
55cd8e5a 2030 default:
a737f256
CD		 2031 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2032 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 2033 return 1;
2034 }
2035 return 0;
2036}
2037
2038static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2039{
10388a07
GN		 2040 switch (msr) {
2041 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 2042 u64 gfn;
10388a07 2043 unsigned long addr;
55cd8e5a 2044
10388a07
GN		 2045 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
2046 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 2047 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
2048 return 1;
10388a07
GN		 2049 break;
2050 }
b3af1e88
VR		 2051 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
2052 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 2053 if (kvm_is_error_hva(addr))
2054 return 1;
8b0cedff 2055 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 2056 return 1;
2057 vcpu->arch.hv_vapic = data;
b3af1e88 2058 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2059 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2060 return 1;
10388a07
GN		 2061 break;
2062 }
2063 case HV_X64_MSR_EOI:
2064 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2065 case HV_X64_MSR_ICR:
2066 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2067 case HV_X64_MSR_TPR:
2068 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2069 default:
a737f256
CD		 2070 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2071 "data 0x%llx\n", msr, data);
10388a07
GN		 2072 return 1;
2073 }
2074
2075 return 0;
55cd8e5a
GN		 2076}
2077
344d9588
GN		 2078static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2079{
2080 gpa_t gpa = data & ~0x3f;
2081
4a969980 2082 /* Bits 2:5 are reserved, Should be zero */
6adba527 2083 if (data & 0x3c)
344d9588
GN		 2084 return 1;
2085
2086 vcpu->arch.apf.msr_val = data;
2087
2088 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2089 kvm_clear_async_pf_completion_queue(vcpu);
2090 kvm_async_pf_hash_reset(vcpu);
2091 return 0;
2092 }
2093
8f964525
AH		 2094 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2095 sizeof(u32)))
344d9588
GN		 2096 return 1;
2097
6adba527 2098 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2099 kvm_async_pf_wakeup_all(vcpu);
2100 return 0;
2101}
2102
12f9a48f
GC		 2103static void kvmclock_reset(struct kvm_vcpu *vcpu)
2104{
0b79459b 2105 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2106}
2107
c9aaa895
GC		 2108static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2109{
2110 u64 delta;
2111
2112 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2113 return;
2114
2115 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2116 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2117 vcpu->arch.st.accum_steal = delta;
2118}
2119
2120static void record_steal_time(struct kvm_vcpu *vcpu)
2121{
2122 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2123 return;
2124
2125 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2126 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2127 return;
2128
2129 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2130 vcpu->arch.st.steal.version += 2;
2131 vcpu->arch.st.accum_steal = 0;
2132
2133 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2134 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2135}
2136
8fe8ab46 2137int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2138{
5753785f 2139 bool pr = false;
8fe8ab46
WA		 2140 u32 msr = msr_info->index;
2141 u64 data = msr_info->data;
5753785f 2142
15c4a640 2143 switch (msr) {
2e32b719
BP		 2144 case MSR_AMD64_NB_CFG:
2145 case MSR_IA32_UCODE_REV:
2146 case MSR_IA32_UCODE_WRITE:
2147 case MSR_VM_HSAVE_PA:
2148 case MSR_AMD64_PATCH_LOADER:
2149 case MSR_AMD64_BU_CFG2:
2150 break;
2151
15c4a640 2152 case MSR_EFER:
b69e8cae 2153 return set_efer(vcpu, data);
8f1589d9
AP		 2154 case MSR_K7_HWCR:
2155 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2156 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2157 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2158 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2159 if (data != 0) {
a737f256
CD		 2160 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2161 data);
8f1589d9
AP		 2162 return 1;
2163 }
15c4a640 2164 break;
f7c6d140
AP		 2165 case MSR_FAM10H_MMIO_CONF_BASE:
2166 if (data != 0) {
a737f256
CD		 2167 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2168 "0x%llx\n", data);
f7c6d140
AP		 2169 return 1;
2170 }
15c4a640 2171 break;
b5e2fec0
AG		 2172 case MSR_IA32_DEBUGCTLMSR:
2173 if (!data) {
2174 /* We support the non-activated case already */
2175 break;
2176 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2177 /* Values other than LBR and BTF are vendor-specific,
2178 thus reserved and should throw a #GP */
2179 return 1;
2180 }
a737f256
CD		 2181 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2182 __func__, data);
b5e2fec0 2183 break;
9ba075a6
AK		 2184 case 0x200 ... 0x2ff:
2185 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2186 case MSR_IA32_APICBASE:
58cb628d 2187 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2188 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2189 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2190 case MSR_IA32_TSCDEADLINE:
2191 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2192 break;
ba904635
WA		 2193 case MSR_IA32_TSC_ADJUST:
2194 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2195 if (!msr_info->host_initiated) {
d913b904 2196 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2197 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2198 }
2199 vcpu->arch.ia32_tsc_adjust_msr = data;
2200 }
2201 break;
15c4a640 2202 case MSR_IA32_MISC_ENABLE:
ad312c7c 2203 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2204 break;
11c6bffa 2205 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2206 case MSR_KVM_WALL_CLOCK:
2207 vcpu->kvm->arch.wall_clock = data;
2208 kvm_write_wall_clock(vcpu->kvm, data);
2209 break;
11c6bffa 2210 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2211 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2212 u64 gpa_offset;
54750f2c
MT		 2213 struct kvm_arch *ka = &vcpu->kvm->arch;
2214
12f9a48f 2215 kvmclock_reset(vcpu);
18068523 2216
54750f2c
MT		 2217 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2218 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2219
2220 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2221 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2222 &vcpu->requests);
2223
2224 ka->boot_vcpu_runs_old_kvmclock = tmp;
2225 }
2226
18068523 2227 vcpu->arch.time = data;
0061d53d 2228 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2229
2230 /* we verify if the enable bit is set... */
2231 if (!(data & 1))
2232 break;
2233
0b79459b 2234 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2235
0b79459b 2236 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2237 &vcpu->arch.pv_time, data & ~1ULL,
2238 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2239 vcpu->arch.pv_time_enabled = false;
2240 else
2241 vcpu->arch.pv_time_enabled = true;
32cad84f 2242
18068523
GOC		 2243 break;
2244 }
344d9588
GN		 2245 case MSR_KVM_ASYNC_PF_EN:
2246 if (kvm_pv_enable_async_pf(vcpu, data))
2247 return 1;
2248 break;
c9aaa895
GC		 2249 case MSR_KVM_STEAL_TIME:
2250
2251 if (unlikely(!sched_info_on()))
2252 return 1;
2253
2254 if (data & KVM_STEAL_RESERVED_MASK)
2255 return 1;
2256
2257 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2258 data & KVM_STEAL_VALID_BITS,
2259 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2260 return 1;
2261
2262 vcpu->arch.st.msr_val = data;
2263
2264 if (!(data & KVM_MSR_ENABLED))
2265 break;
2266
2267 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2268
2269 preempt_disable();
2270 accumulate_steal_time(vcpu);
2271 preempt_enable();
2272
2273 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2274
2275 break;
ae7a2a3f
MT		 2276 case MSR_KVM_PV_EOI_EN:
2277 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2278 return 1;
2279 break;
c9aaa895 2280
890ca9ae
HY		 2281 case MSR_IA32_MCG_CTL:
2282 case MSR_IA32_MCG_STATUS:
81760dcc 2283 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2284 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2285
2286 /* Performance counters are not protected by a CPUID bit,
2287 * so we should check all of them in the generic path for the sake of
2288 * cross vendor migration.
2289 * Writing a zero into the event select MSRs disables them,
2290 * which we perfectly emulate ;-). Any other value should be at least
2291 * reported, some guests depend on them.
2292 */
71db6023
AP		 2293 case MSR_K7_EVNTSEL0:
2294 case MSR_K7_EVNTSEL1:
2295 case MSR_K7_EVNTSEL2:
2296 case MSR_K7_EVNTSEL3:
2297 if (data != 0)
a737f256
CD		 2298 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2299 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2300 break;
2301 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2302 * so we ignore writes to make it happy.
2303 */
71db6023
AP		 2304 case MSR_K7_PERFCTR0:
2305 case MSR_K7_PERFCTR1:
2306 case MSR_K7_PERFCTR2:
2307 case MSR_K7_PERFCTR3:
a737f256
CD		 2308 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2309 "0x%x data 0x%llx\n", msr, data);
71db6023 2310 break;
5753785f
GN		 2311 case MSR_P6_PERFCTR0:
2312 case MSR_P6_PERFCTR1:
2313 pr = true;
2314 case MSR_P6_EVNTSEL0:
2315 case MSR_P6_EVNTSEL1:
2316 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2317 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2318
2319 if (pr || data != 0)
a737f256
CD		 2320 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2321 "0x%x data 0x%llx\n", msr, data);
5753785f 2322 break;
84e0cefa
JS		 2323 case MSR_K7_CLK_CTL:
2324 /*
2325 * Ignore all writes to this no longer documented MSR.
2326 * Writes are only relevant for old K7 processors,
2327 * all pre-dating SVM, but a recommended workaround from
4a969980 2328 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2329 * affected processor models on the command line, hence
2330 * the need to ignore the workaround.
2331 */
2332 break;
55cd8e5a
GN		 2333 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2334 if (kvm_hv_msr_partition_wide(msr)) {
2335 int r;
2336 mutex_lock(&vcpu->kvm->lock);
2337 r = set_msr_hyperv_pw(vcpu, msr, data);
2338 mutex_unlock(&vcpu->kvm->lock);
2339 return r;
2340 } else
2341 return set_msr_hyperv(vcpu, msr, data);
2342 break;
91c9c3ed 2343 case MSR_IA32_BBL_CR_CTL3:
2344 /* Drop writes to this legacy MSR -- see rdmsr
2345 * counterpart for further detail.
2346 */
a737f256 2347 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2348 break;
2b036c6b
BO		 2349 case MSR_AMD64_OSVW_ID_LENGTH:
2350 if (!guest_cpuid_has_osvw(vcpu))
2351 return 1;
2352 vcpu->arch.osvw.length = data;
2353 break;
2354 case MSR_AMD64_OSVW_STATUS:
2355 if (!guest_cpuid_has_osvw(vcpu))
2356 return 1;
2357 vcpu->arch.osvw.status = data;
2358 break;
15c4a640 2359 default:
ffde22ac
ES		 2360 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2361 return xen_hvm_config(vcpu, data);
f5132b01 2362 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2363 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2364 if (!ignore_msrs) {
a737f256
CD		 2365 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2366 msr, data);
ed85c068
AP		 2367 return 1;
2368 } else {
a737f256
CD		 2369 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2370 msr, data);
ed85c068
AP		 2371 break;
2372 }
15c4a640
CO		 2373 }
2374 return 0;
2375}
2376EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2377
2378
2379/*
2380 * Reads an msr value (of 'msr_index') into 'pdata'.
2381 * Returns 0 on success, non-0 otherwise.
2382 * Assumes vcpu_load() was already called.
2383 */
2384int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2385{
2386 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2387}
ff651cb6 2388EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2389
9ba075a6
AK		 2390static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2391{
0bed3b56
SY		 2392 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2393
9ba075a6
AK		 2394 if (!msr_mtrr_valid(msr))
2395 return 1;
2396
0bed3b56
SY		 2397 if (msr == MSR_MTRRdefType)
2398 *pdata = vcpu->arch.mtrr_state.def_type +
2399 (vcpu->arch.mtrr_state.enabled << 10);
2400 else if (msr == MSR_MTRRfix64K_00000)
2401 *pdata = p[0];
2402 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2403 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2404 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2405 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2406 else if (msr == MSR_IA32_CR_PAT)
2407 *pdata = vcpu->arch.pat;
2408 else { /* Variable MTRRs */
2409 int idx, is_mtrr_mask;
2410 u64 *pt;
2411
2412 idx = (msr - 0x200) / 2;
2413 is_mtrr_mask = msr - 0x200 - 2 * idx;
2414 if (!is_mtrr_mask)
2415 pt =
2416 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2417 else
2418 pt =
2419 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2420 *pdata = *pt;
2421 }
2422
9ba075a6
AK		 2423 return 0;
2424}
2425
890ca9ae 2426static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2427{
2428 u64 data;
890ca9ae
HY		 2429 u64 mcg_cap = vcpu->arch.mcg_cap;
2430 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2431
2432 switch (msr) {
15c4a640
CO		 2433 case MSR_IA32_P5_MC_ADDR:
2434 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2435 data = 0;
2436 break;
15c4a640 2437 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2438 data = vcpu->arch.mcg_cap;
2439 break;
c7ac679c 2440 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2441 if (!(mcg_cap & MCG_CTL_P))
2442 return 1;
2443 data = vcpu->arch.mcg_ctl;
2444 break;
2445 case MSR_IA32_MCG_STATUS:
2446 data = vcpu->arch.mcg_status;
2447 break;
2448 default:
2449 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2450 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2451 u32 offset = msr - MSR_IA32_MC0_CTL;
2452 data = vcpu->arch.mce_banks[offset];
2453 break;
2454 }
2455 return 1;
2456 }
2457 *pdata = data;
2458 return 0;
2459}
2460
55cd8e5a
GN		 2461static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2462{
2463 u64 data = 0;
2464 struct kvm *kvm = vcpu->kvm;
2465
2466 switch (msr) {
2467 case HV_X64_MSR_GUEST_OS_ID:
2468 data = kvm->arch.hv_guest_os_id;
2469 break;
2470 case HV_X64_MSR_HYPERCALL:
2471 data = kvm->arch.hv_hypercall;
2472 break;
e984097b
VR		 2473 case HV_X64_MSR_TIME_REF_COUNT: {
2474 data =
2475 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2476 break;
2477 }
2478 case HV_X64_MSR_REFERENCE_TSC:
2479 data = kvm->arch.hv_tsc_page;
2480 break;
55cd8e5a 2481 default:
a737f256 2482 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2483 return 1;
2484 }
2485
2486 *pdata = data;
2487 return 0;
2488}
2489
2490static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2491{
2492 u64 data = 0;
2493
2494 switch (msr) {
2495 case HV_X64_MSR_VP_INDEX: {
2496 int r;
2497 struct kvm_vcpu *v;
684851a1
TY		 2498 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2499 if (v == vcpu) {
55cd8e5a 2500 data = r;
684851a1
TY		 2501 break;
2502 }
2503 }
55cd8e5a
GN		 2504 break;
2505 }
10388a07
GN		 2506 case HV_X64_MSR_EOI:
2507 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2508 case HV_X64_MSR_ICR:
2509 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2510 case HV_X64_MSR_TPR:
2511 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2512 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2513 data = vcpu->arch.hv_vapic;
2514 break;
55cd8e5a 2515 default:
a737f256 2516 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2517 return 1;
2518 }
2519 *pdata = data;
2520 return 0;
2521}
2522
890ca9ae
HY		 2523int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2524{
2525 u64 data;
2526
2527 switch (msr) {
890ca9ae 2528 case MSR_IA32_PLATFORM_ID:
15c4a640 2529 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2530 case MSR_IA32_DEBUGCTLMSR:
2531 case MSR_IA32_LASTBRANCHFROMIP:
2532 case MSR_IA32_LASTBRANCHTOIP:
2533 case MSR_IA32_LASTINTFROMIP:
2534 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2535 case MSR_K8_SYSCFG:
2536 case MSR_K7_HWCR:
61a6bd67 2537 case MSR_VM_HSAVE_PA:
9e699624 2538 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2539 case MSR_K7_EVNTSEL1:
2540 case MSR_K7_EVNTSEL2:
2541 case MSR_K7_EVNTSEL3:
1f3ee616 2542 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2543 case MSR_K7_PERFCTR1:
2544 case MSR_K7_PERFCTR2:
2545 case MSR_K7_PERFCTR3:
1fdbd48c 2546 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2547 case MSR_AMD64_NB_CFG:
f7c6d140 2548 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2549 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2550 data = 0;
2551 break;
5753785f
GN		 2552 case MSR_P6_PERFCTR0:
2553 case MSR_P6_PERFCTR1:
2554 case MSR_P6_EVNTSEL0:
2555 case MSR_P6_EVNTSEL1:
2556 if (kvm_pmu_msr(vcpu, msr))
2557 return kvm_pmu_get_msr(vcpu, msr, pdata);
2558 data = 0;
2559 break;
742bc670
MT		 2560 case MSR_IA32_UCODE_REV:
2561 data = 0x100000000ULL;
2562 break;
9ba075a6
AK		 2563 case MSR_MTRRcap:
2564 data = 0x500 | KVM_NR_VAR_MTRR;
2565 break;
2566 case 0x200 ... 0x2ff:
2567 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2568 case 0xcd: /* fsb frequency */
2569 data = 3;
2570 break;
7b914098
JS		 2571 /*
2572 * MSR_EBC_FREQUENCY_ID
2573 * Conservative value valid for even the basic CPU models.
2574 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2575 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2576 * and 266MHz for model 3, or 4. Set Core Clock
2577 * Frequency to System Bus Frequency Ratio to 1 (bits
2578 * 31:24) even though these are only valid for CPU
2579 * models > 2, however guests may end up dividing or
2580 * multiplying by zero otherwise.
2581 */
2582 case MSR_EBC_FREQUENCY_ID:
2583 data = 1 << 24;
2584 break;
15c4a640
CO		 2585 case MSR_IA32_APICBASE:
2586 data = kvm_get_apic_base(vcpu);
2587 break;
0105d1a5
GN		 2588 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2589 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2590 break;
a3e06bbe
LJ		 2591 case MSR_IA32_TSCDEADLINE:
2592 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2593 break;
ba904635
WA		 2594 case MSR_IA32_TSC_ADJUST:
2595 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2596 break;
15c4a640 2597 case MSR_IA32_MISC_ENABLE:
ad312c7c 2598 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2599 break;
847f0ad8
AG		 2600 case MSR_IA32_PERF_STATUS:
2601 /* TSC increment by tick */
2602 data = 1000ULL;
2603 /* CPU multiplier */
2604 data |= (((uint64_t)4ULL) << 40);
2605 break;
15c4a640 2606 case MSR_EFER:
f6801dff 2607 data = vcpu->arch.efer;
15c4a640 2608 break;
18068523 2609 case MSR_KVM_WALL_CLOCK:
11c6bffa 2610 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2611 data = vcpu->kvm->arch.wall_clock;
2612 break;
2613 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2614 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2615 data = vcpu->arch.time;
2616 break;
344d9588
GN		 2617 case MSR_KVM_ASYNC_PF_EN:
2618 data = vcpu->arch.apf.msr_val;
2619 break;
c9aaa895
GC		 2620 case MSR_KVM_STEAL_TIME:
2621 data = vcpu->arch.st.msr_val;
2622 break;
1d92128f
MT		 2623 case MSR_KVM_PV_EOI_EN:
2624 data = vcpu->arch.pv_eoi.msr_val;
2625 break;
890ca9ae
HY		 2626 case MSR_IA32_P5_MC_ADDR:
2627 case MSR_IA32_P5_MC_TYPE:
2628 case MSR_IA32_MCG_CAP:
2629 case MSR_IA32_MCG_CTL:
2630 case MSR_IA32_MCG_STATUS:
81760dcc 2631 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2632 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2633 case MSR_K7_CLK_CTL:
2634 /*
2635 * Provide expected ramp-up count for K7. All other
2636 * are set to zero, indicating minimum divisors for
2637 * every field.
2638 *
2639 * This prevents guest kernels on AMD host with CPU
2640 * type 6, model 8 and higher from exploding due to
2641 * the rdmsr failing.
2642 */
2643 data = 0x20000000;
2644 break;
55cd8e5a
GN		 2645 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2646 if (kvm_hv_msr_partition_wide(msr)) {
2647 int r;
2648 mutex_lock(&vcpu->kvm->lock);
2649 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2650 mutex_unlock(&vcpu->kvm->lock);
2651 return r;
2652 } else
2653 return get_msr_hyperv(vcpu, msr, pdata);
2654 break;
91c9c3ed 2655 case MSR_IA32_BBL_CR_CTL3:
2656 /* This legacy MSR exists but isn't fully documented in current
2657 * silicon. It is however accessed by winxp in very narrow
2658 * scenarios where it sets bit #19, itself documented as
2659 * a "reserved" bit. Best effort attempt to source coherent
2660 * read data here should the balance of the register be
2661 * interpreted by the guest:
2662 *
2663 * L2 cache control register 3: 64GB range, 256KB size,
2664 * enabled, latency 0x1, configured
2665 */
2666 data = 0xbe702111;
2667 break;
2b036c6b
BO		 2668 case MSR_AMD64_OSVW_ID_LENGTH:
2669 if (!guest_cpuid_has_osvw(vcpu))
2670 return 1;
2671 data = vcpu->arch.osvw.length;
2672 break;
2673 case MSR_AMD64_OSVW_STATUS:
2674 if (!guest_cpuid_has_osvw(vcpu))
2675 return 1;
2676 data = vcpu->arch.osvw.status;
2677 break;
15c4a640 2678 default:
f5132b01
GN		 2679 if (kvm_pmu_msr(vcpu, msr))
2680 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2681 if (!ignore_msrs) {
a737f256 2682 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2683 return 1;
2684 } else {
a737f256 2685 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2686 data = 0;
2687 }
2688 break;
15c4a640
CO		 2689 }
2690 *pdata = data;
2691 return 0;
2692}
2693EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2694
313a3dc7
CO		 2695/*
2696 * Read or write a bunch of msrs. All parameters are kernel addresses.
2697 *
2698 * @return number of msrs set successfully.
2699 */
2700static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2701 struct kvm_msr_entry *entries,
2702 int (*do_msr)(struct kvm_vcpu *vcpu,
2703 unsigned index, u64 *data))
2704{
f656ce01 2705 int i, idx;
313a3dc7 2706
f656ce01 2707 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2708 for (i = 0; i < msrs->nmsrs; ++i)
2709 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2710 break;
f656ce01 2711 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2712
313a3dc7
CO		 2713 return i;
2714}
2715
2716/*
2717 * Read or write a bunch of msrs. Parameters are user addresses.
2718 *
2719 * @return number of msrs set successfully.
2720 */
2721static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2722 int (*do_msr)(struct kvm_vcpu *vcpu,
2723 unsigned index, u64 *data),
2724 int writeback)
2725{
2726 struct kvm_msrs msrs;
2727 struct kvm_msr_entry *entries;
2728 int r, n;
2729 unsigned size;
2730
2731 r = -EFAULT;
2732 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2733 goto out;
2734
2735 r = -E2BIG;
2736 if (msrs.nmsrs >= MAX_IO_MSRS)
2737 goto out;
2738
313a3dc7 2739 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2740 entries = memdup_user(user_msrs->entries, size);
2741 if (IS_ERR(entries)) {
2742 r = PTR_ERR(entries);
313a3dc7 2743 goto out;
ff5c2c03 2744 }
313a3dc7
CO		 2745
2746 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2747 if (r < 0)
2748 goto out_free;
2749
2750 r = -EFAULT;
2751 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2752 goto out_free;
2753
2754 r = n;
2755
2756out_free:
7a73c028 2757 kfree(entries);
313a3dc7
CO		 2758out:
2759 return r;
2760}
2761
784aa3d7 2762int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2763{
2764 int r;
2765
2766 switch (ext) {
2767 case KVM_CAP_IRQCHIP:
2768 case KVM_CAP_HLT:
2769 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2770 case KVM_CAP_SET_TSS_ADDR:
07716717 2771 case KVM_CAP_EXT_CPUID:
9c15bb1d 2772 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2773 case KVM_CAP_CLOCKSOURCE:
7837699f 2774 case KVM_CAP_PIT:
a28e4f5a 2775 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2776 case KVM_CAP_MP_STATE:
ed848624 2777 case KVM_CAP_SYNC_MMU:
a355c85c 2778 case KVM_CAP_USER_NMI:
52d939a0 2779 case KVM_CAP_REINJECT_CONTROL:
4925663a 2780 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2781 case KVM_CAP_IOEVENTFD:
f848a5a8 2782 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2783 case KVM_CAP_PIT2:
e9f42757 2784 case KVM_CAP_PIT_STATE2:
b927a3ce 2785 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2786 case KVM_CAP_XEN_HVM:
afbcf7ab 2787 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2788 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2789 case KVM_CAP_HYPERV:
10388a07 2790 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2791 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2792 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2793 case KVM_CAP_DEBUGREGS:
d2be1651 2794 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2795 case KVM_CAP_XSAVE:
344d9588 2796 case KVM_CAP_ASYNC_PF:
92a1f12d 2797 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2798 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2799 case KVM_CAP_READONLY_MEM:
5f66b620 2800 case KVM_CAP_HYPERV_TIME:
100943c5 2801 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2802 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2803 case KVM_CAP_ENABLE_CAP_VM:
2804 case KVM_CAP_DISABLE_QUIRKS:
2a5bab10
AW		 2805#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2806 case KVM_CAP_ASSIGN_DEV_IRQ:
2807 case KVM_CAP_PCI_2_3:
2808#endif
018d00d2
ZX		 2809 r = 1;
2810 break;
542472b5
LV		 2811 case KVM_CAP_COALESCED_MMIO:
2812 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2813 break;
774ead3a
AK		 2814 case KVM_CAP_VAPIC:
2815 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2816 break;
f725230a 2817 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2818 r = KVM_SOFT_MAX_VCPUS;
2819 break;
2820 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2821 r = KVM_MAX_VCPUS;
2822 break;
a988b910 2823 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2824 r = KVM_USER_MEM_SLOTS;
a988b910 2825 break;
a68a6a72
MT		 2826 case KVM_CAP_PV_MMU: /* obsolete */
2827 r = 0;
2f333bcb 2828 break;
4cee4b72 2829#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2830 case KVM_CAP_IOMMU:
a1b60c1c 2831 r = iommu_present(&pci_bus_type);
62c476c7 2832 break;
4cee4b72 2833#endif
890ca9ae
HY		 2834 case KVM_CAP_MCE:
2835 r = KVM_MAX_MCE_BANKS;
2836 break;
2d5b5a66
SY		 2837 case KVM_CAP_XCRS:
2838 r = cpu_has_xsave;
2839 break;
92a1f12d
JR		 2840 case KVM_CAP_TSC_CONTROL:
2841 r = kvm_has_tsc_control;
2842 break;
018d00d2
ZX		 2843 default:
2844 r = 0;
2845 break;
2846 }
2847 return r;
2848
2849}
2850
043405e1
CO		 2851long kvm_arch_dev_ioctl(struct file *filp,
2852 unsigned int ioctl, unsigned long arg)
2853{
2854 void __user *argp = (void __user *)arg;
2855 long r;
2856
2857 switch (ioctl) {
2858 case KVM_GET_MSR_INDEX_LIST: {
2859 struct kvm_msr_list __user *user_msr_list = argp;
2860 struct kvm_msr_list msr_list;
2861 unsigned n;
2862
2863 r = -EFAULT;
2864 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2865 goto out;
2866 n = msr_list.nmsrs;
2867 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2868 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2869 goto out;
2870 r = -E2BIG;
e125e7b6 2871 if (n < msr_list.nmsrs)
043405e1
CO		 2872 goto out;
2873 r = -EFAULT;
2874 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2875 num_msrs_to_save * sizeof(u32)))
2876 goto out;
e125e7b6 2877 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2878 &emulated_msrs,
2879 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2880 goto out;
2881 r = 0;
2882 break;
2883 }
9c15bb1d
BP		 2884 case KVM_GET_SUPPORTED_CPUID:
2885 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2886 struct kvm_cpuid2 __user *cpuid_arg = argp;
2887 struct kvm_cpuid2 cpuid;
2888
2889 r = -EFAULT;
2890 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2891 goto out;
9c15bb1d
BP		 2892
2893 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2894 ioctl);
674eea0f
AK		 2895 if (r)
2896 goto out;
2897
2898 r = -EFAULT;
2899 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2900 goto out;
2901 r = 0;
2902 break;
2903 }
890ca9ae
HY		 2904 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2905 u64 mce_cap;
2906
2907 mce_cap = KVM_MCE_CAP_SUPPORTED;
2908 r = -EFAULT;
2909 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2910 goto out;
2911 r = 0;
2912 break;
2913 }
043405e1
CO		 2914 default:
2915 r = -EINVAL;
2916 }
2917out:
2918 return r;
2919}
2920
f5f48ee1
SY		 2921static void wbinvd_ipi(void *garbage)
2922{
2923 wbinvd();
2924}
2925
2926static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2927{
e0f0bbc5 2928 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2929}
2930
313a3dc7
CO		 2931void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2932{
f5f48ee1
SY		 2933 /* Address WBINVD may be executed by guest */
2934 if (need_emulate_wbinvd(vcpu)) {
2935 if (kvm_x86_ops->has_wbinvd_exit())
2936 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2937 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2938 smp_call_function_single(vcpu->cpu,
2939 wbinvd_ipi, NULL, 1);
2940 }
2941
313a3dc7 2942 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2943
0dd6a6ed
ZA		 2944 /* Apply any externally detected TSC adjustments (due to suspend) */
2945 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2946 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2947 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2948 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2949 }
8f6055cb 2950
48434c20 2951 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2952 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2953 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2954 if (tsc_delta < 0)
2955 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2956 if (check_tsc_unstable()) {
b183aa58
ZA		 2957 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2958 vcpu->arch.last_guest_tsc);
2959 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2960 vcpu->arch.tsc_catchup = 1;
c285545f 2961 }
d98d07ca
MT		 2962 /*
2963 * On a host with synchronized TSC, there is no need to update
2964 * kvmclock on vcpu->cpu migration
2965 */
2966 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2967 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2968 if (vcpu->cpu != cpu)
2969 kvm_migrate_timers(vcpu);
e48672fa 2970 vcpu->cpu = cpu;
6b7d7e76 2971 }
c9aaa895
GC		 2972
2973 accumulate_steal_time(vcpu);
2974 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2975}
2976
2977void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2978{
02daab21 2979 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2980 kvm_put_guest_fpu(vcpu);
6f526ec5 2981 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2982}
2983
313a3dc7
CO		 2984static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2985 struct kvm_lapic_state *s)
2986{
5a71785d 2987 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2988 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2989
2990 return 0;
2991}
2992
2993static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2994 struct kvm_lapic_state *s)
2995{
64eb0620 2996 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2997 update_cr8_intercept(vcpu);
313a3dc7
CO		 2998
2999 return 0;
3000}
3001
f77bc6a4
ZX		 3002static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3003 struct kvm_interrupt *irq)
3004{
02cdb50f 3005 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 3006 return -EINVAL;
3007 if (irqchip_in_kernel(vcpu->kvm))
3008 return -ENXIO;
f77bc6a4 3009
66fd3f7f 3010 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 3011 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 3012
f77bc6a4
ZX		 3013 return 0;
3014}
3015
c4abb7c9
JK		 3016static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3017{
c4abb7c9 3018 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3019
3020 return 0;
3021}
3022
b209749f
AK		 3023static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3024 struct kvm_tpr_access_ctl *tac)
3025{
3026 if (tac->flags)
3027 return -EINVAL;
3028 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3029 return 0;
3030}
3031
890ca9ae
HY		 3032static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3033 u64 mcg_cap)
3034{
3035 int r;
3036 unsigned bank_num = mcg_cap & 0xff, bank;
3037
3038 r = -EINVAL;
a9e38c3e 3039 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 3040 goto out;
3041 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
3042 goto out;
3043 r = 0;
3044 vcpu->arch.mcg_cap = mcg_cap;
3045 /* Init IA32_MCG_CTL to all 1s */
3046 if (mcg_cap & MCG_CTL_P)
3047 vcpu->arch.mcg_ctl = ~(u64)0;
3048 /* Init IA32_MCi_CTL to all 1s */
3049 for (bank = 0; bank < bank_num; bank++)
3050 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
3051out:
3052 return r;
3053}
3054
3055static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3056 struct kvm_x86_mce *mce)
3057{
3058 u64 mcg_cap = vcpu->arch.mcg_cap;
3059 unsigned bank_num = mcg_cap & 0xff;
3060 u64 *banks = vcpu->arch.mce_banks;
3061
3062 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3063 return -EINVAL;
3064 /*
3065 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3066 * reporting is disabled
3067 */
3068 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3069 vcpu->arch.mcg_ctl != ~(u64)0)
3070 return 0;
3071 banks += 4 * mce->bank;
3072 /*
3073 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3074 * reporting is disabled for the bank
3075 */
3076 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3077 return 0;
3078 if (mce->status & MCI_STATUS_UC) {
3079 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3080 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3081 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3082 return 0;
3083 }
3084 if (banks[1] & MCI_STATUS_VAL)
3085 mce->status |= MCI_STATUS_OVER;
3086 banks[2] = mce->addr;
3087 banks[3] = mce->misc;
3088 vcpu->arch.mcg_status = mce->mcg_status;
3089 banks[1] = mce->status;
3090 kvm_queue_exception(vcpu, MC_VECTOR);
3091 } else if (!(banks[1] & MCI_STATUS_VAL)
3092 || !(banks[1] & MCI_STATUS_UC)) {
3093 if (banks[1] & MCI_STATUS_VAL)
3094 mce->status |= MCI_STATUS_OVER;
3095 banks[2] = mce->addr;
3096 banks[3] = mce->misc;
3097 banks[1] = mce->status;
3098 } else
3099 banks[1] |= MCI_STATUS_OVER;
3100 return 0;
3101}
3102
3cfc3092
JK		 3103static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3104 struct kvm_vcpu_events *events)
3105{
7460fb4a 3106 process_nmi(vcpu);
03b82a30
JK		 3107 events->exception.injected =
3108 vcpu->arch.exception.pending &&
3109 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3110 events->exception.nr = vcpu->arch.exception.nr;
3111 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3112 events->exception.pad = 0;
3cfc3092
JK		 3113 events->exception.error_code = vcpu->arch.exception.error_code;
3114
03b82a30
JK		 3115 events->interrupt.injected =
3116 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3117 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3118 events->interrupt.soft = 0;
37ccdcbe 3119 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3120
3121 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3122 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3123 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3124 events->nmi.pad = 0;
3cfc3092 3125
66450a21 3126 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3127
dab4b911 3128 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3129 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3130 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3131}
3132
3133static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3134 struct kvm_vcpu_events *events)
3135{
dab4b911 3136 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3137 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3138 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3139 return -EINVAL;
3140
7460fb4a 3141 process_nmi(vcpu);
3cfc3092
JK		 3142 vcpu->arch.exception.pending = events->exception.injected;
3143 vcpu->arch.exception.nr = events->exception.nr;
3144 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3145 vcpu->arch.exception.error_code = events->exception.error_code;
3146
3147 vcpu->arch.interrupt.pending = events->interrupt.injected;
3148 vcpu->arch.interrupt.nr = events->interrupt.nr;
3149 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3150 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3151 kvm_x86_ops->set_interrupt_shadow(vcpu,
3152 events->interrupt.shadow);
3cfc3092
JK		 3153
3154 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3155 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3156 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3157 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3158
66450a21
JK		 3159 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3160 kvm_vcpu_has_lapic(vcpu))
3161 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3162
3842d135
AK		 3163 kvm_make_request(KVM_REQ_EVENT, vcpu);
3164
3cfc3092
JK		 3165 return 0;
3166}
3167
a1efbe77
JK		 3168static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3169 struct kvm_debugregs *dbgregs)
3170{
73aaf249
JK		 3171 unsigned long val;
3172
a1efbe77 3173 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3174 kvm_get_dr(vcpu, 6, &val);
73aaf249 3175 dbgregs->dr6 = val;
a1efbe77
JK		 3176 dbgregs->dr7 = vcpu->arch.dr7;
3177 dbgregs->flags = 0;
97e69aa6 3178 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3179}
3180
3181static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3182 struct kvm_debugregs *dbgregs)
3183{
3184 if (dbgregs->flags)
3185 return -EINVAL;
3186
a1efbe77 3187 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3188 kvm_update_dr0123(vcpu);
a1efbe77 3189 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3190 kvm_update_dr6(vcpu);
a1efbe77 3191 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3192 kvm_update_dr7(vcpu);
a1efbe77 3193
a1efbe77
JK		 3194 return 0;
3195}
3196
df1daba7
PB		 3197#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3198
3199static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3200{
3201 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3202 u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3203 u64 valid;
3204
3205 /*
3206 * Copy legacy XSAVE area, to avoid complications with CPUID
3207 * leaves 0 and 1 in the loop below.
3208 */
3209 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3210
3211 /* Set XSTATE_BV */
3212 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3213
3214 /*
3215 * Copy each region from the possibly compacted offset to the
3216 * non-compacted offset.
3217 */
3218 valid = xstate_bv & ~XSTATE_FPSSE;
3219 while (valid) {
3220 u64 feature = valid & -valid;
3221 int index = fls64(feature) - 1;
3222 void *src = get_xsave_addr(xsave, feature);
3223
3224 if (src) {
3225 u32 size, offset, ecx, edx;
3226 cpuid_count(XSTATE_CPUID, index,
3227 &size, &offset, &ecx, &edx);
3228 memcpy(dest + offset, src, size);
3229 }
3230
3231 valid -= feature;
3232 }
3233}
3234
3235static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3236{
3237 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3238 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3239 u64 valid;
3240
3241 /*
3242 * Copy legacy XSAVE area, to avoid complications with CPUID
3243 * leaves 0 and 1 in the loop below.
3244 */
3245 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3246
3247 /* Set XSTATE_BV and possibly XCOMP_BV. */
3248 xsave->xsave_hdr.xstate_bv = xstate_bv;
3249 if (cpu_has_xsaves)
3250 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3251
3252 /*
3253 * Copy each region from the non-compacted offset to the
3254 * possibly compacted offset.
3255 */
3256 valid = xstate_bv & ~XSTATE_FPSSE;
3257 while (valid) {
3258 u64 feature = valid & -valid;
3259 int index = fls64(feature) - 1;
3260 void *dest = get_xsave_addr(xsave, feature);
3261
3262 if (dest) {
3263 u32 size, offset, ecx, edx;
3264 cpuid_count(XSTATE_CPUID, index,
3265 &size, &offset, &ecx, &edx);
3266 memcpy(dest, src + offset, size);
3267 } else
3268 WARN_ON_ONCE(1);
3269
3270 valid -= feature;
3271 }
3272}
3273
2d5b5a66
SY		 3274static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3275 struct kvm_xsave *guest_xsave)
3276{
4344ee98 3277 if (cpu_has_xsave) {
df1daba7
PB		 3278 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3279 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3280 } else {
2d5b5a66
SY		 3281 memcpy(guest_xsave->region,
3282 &vcpu->arch.guest_fpu.state->fxsave,
3283 sizeof(struct i387_fxsave_struct));
3284 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3285 XSTATE_FPSSE;
3286 }
3287}
3288
3289static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3290 struct kvm_xsave *guest_xsave)
3291{
3292 u64 xstate_bv =
3293 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3294
d7876f1b
PB		 3295 if (cpu_has_xsave) {
3296 /*
3297 * Here we allow setting states that are not present in
3298 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3299 * with old userspace.
3300 */
4ff41732 3301 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3302 return -EINVAL;
df1daba7 3303 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3304 } else {
2d5b5a66
SY		 3305 if (xstate_bv & ~XSTATE_FPSSE)
3306 return -EINVAL;
3307 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3308 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3309 }
3310 return 0;
3311}
3312
3313static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3314 struct kvm_xcrs *guest_xcrs)
3315{
3316 if (!cpu_has_xsave) {
3317 guest_xcrs->nr_xcrs = 0;
3318 return;
3319 }
3320
3321 guest_xcrs->nr_xcrs = 1;
3322 guest_xcrs->flags = 0;
3323 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3324 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3325}
3326
3327static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3328 struct kvm_xcrs *guest_xcrs)
3329{
3330 int i, r = 0;
3331
3332 if (!cpu_has_xsave)
3333 return -EINVAL;
3334
3335 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3336 return -EINVAL;
3337
3338 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3339 /* Only support XCR0 currently */
c67a04cb 3340 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3341 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3342 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3343 break;
3344 }
3345 if (r)
3346 r = -EINVAL;
3347 return r;
3348}
3349
1c0b28c2
EM		 3350/*
3351 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3352 * stopped by the hypervisor. This function will be called from the host only.
3353 * EINVAL is returned when the host attempts to set the flag for a guest that
3354 * does not support pv clocks.
3355 */
3356static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3357{
0b79459b 3358 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3359 return -EINVAL;
51d59c6b 3360 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3361 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3362 return 0;
3363}
3364
313a3dc7
CO		 3365long kvm_arch_vcpu_ioctl(struct file *filp,
3366 unsigned int ioctl, unsigned long arg)
3367{
3368 struct kvm_vcpu *vcpu = filp->private_data;
3369 void __user *argp = (void __user *)arg;
3370 int r;
d1ac91d8
AK		 3371 union {
3372 struct kvm_lapic_state *lapic;
3373 struct kvm_xsave *xsave;
3374 struct kvm_xcrs *xcrs;
3375 void *buffer;
3376 } u;
3377
3378 u.buffer = NULL;
313a3dc7
CO		 3379 switch (ioctl) {
3380 case KVM_GET_LAPIC: {
2204ae3c
MT		 3381 r = -EINVAL;
3382 if (!vcpu->arch.apic)
3383 goto out;
d1ac91d8 3384 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3385
b772ff36 3386 r = -ENOMEM;
d1ac91d8 3387 if (!u.lapic)
b772ff36 3388 goto out;
d1ac91d8 3389 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3390 if (r)
3391 goto out;
3392 r = -EFAULT;
d1ac91d8 3393 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3394 goto out;
3395 r = 0;
3396 break;
3397 }
3398 case KVM_SET_LAPIC: {
2204ae3c
MT		 3399 r = -EINVAL;
3400 if (!vcpu->arch.apic)
3401 goto out;
ff5c2c03 3402 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3403 if (IS_ERR(u.lapic))
3404 return PTR_ERR(u.lapic);
ff5c2c03 3405
d1ac91d8 3406 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3407 break;
3408 }
f77bc6a4
ZX		 3409 case KVM_INTERRUPT: {
3410 struct kvm_interrupt irq;
3411
3412 r = -EFAULT;
3413 if (copy_from_user(&irq, argp, sizeof irq))
3414 goto out;
3415 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3416 break;
3417 }
c4abb7c9
JK		 3418 case KVM_NMI: {
3419 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3420 break;
3421 }
313a3dc7
CO		 3422 case KVM_SET_CPUID: {
3423 struct kvm_cpuid __user *cpuid_arg = argp;
3424 struct kvm_cpuid cpuid;
3425
3426 r = -EFAULT;
3427 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3428 goto out;
3429 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3430 break;
3431 }
07716717
DK		 3432 case KVM_SET_CPUID2: {
3433 struct kvm_cpuid2 __user *cpuid_arg = argp;
3434 struct kvm_cpuid2 cpuid;
3435
3436 r = -EFAULT;
3437 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3438 goto out;
3439 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3440 cpuid_arg->entries);
07716717
DK		 3441 break;
3442 }
3443 case KVM_GET_CPUID2: {
3444 struct kvm_cpuid2 __user *cpuid_arg = argp;
3445 struct kvm_cpuid2 cpuid;
3446
3447 r = -EFAULT;
3448 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3449 goto out;
3450 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3451 cpuid_arg->entries);
07716717
DK		 3452 if (r)
3453 goto out;
3454 r = -EFAULT;
3455 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3456 goto out;
3457 r = 0;
3458 break;
3459 }
313a3dc7
CO		 3460 case KVM_GET_MSRS:
3461 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3462 break;
3463 case KVM_SET_MSRS:
3464 r = msr_io(vcpu, argp, do_set_msr, 0);
3465 break;
b209749f
AK		 3466 case KVM_TPR_ACCESS_REPORTING: {
3467 struct kvm_tpr_access_ctl tac;
3468
3469 r = -EFAULT;
3470 if (copy_from_user(&tac, argp, sizeof tac))
3471 goto out;
3472 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3473 if (r)
3474 goto out;
3475 r = -EFAULT;
3476 if (copy_to_user(argp, &tac, sizeof tac))
3477 goto out;
3478 r = 0;
3479 break;
3480 };
b93463aa
AK		 3481 case KVM_SET_VAPIC_ADDR: {
3482 struct kvm_vapic_addr va;
3483
3484 r = -EINVAL;
3485 if (!irqchip_in_kernel(vcpu->kvm))
3486 goto out;
3487 r = -EFAULT;
3488 if (copy_from_user(&va, argp, sizeof va))
3489 goto out;
fda4e2e8 3490 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3491 break;
3492 }
890ca9ae
HY		 3493 case KVM_X86_SETUP_MCE: {
3494 u64 mcg_cap;
3495
3496 r = -EFAULT;
3497 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3498 goto out;
3499 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3500 break;
3501 }
3502 case KVM_X86_SET_MCE: {
3503 struct kvm_x86_mce mce;
3504
3505 r = -EFAULT;
3506 if (copy_from_user(&mce, argp, sizeof mce))
3507 goto out;
3508 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3509 break;
3510 }
3cfc3092
JK		 3511 case KVM_GET_VCPU_EVENTS: {
3512 struct kvm_vcpu_events events;
3513
3514 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3515
3516 r = -EFAULT;
3517 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3518 break;
3519 r = 0;
3520 break;
3521 }
3522 case KVM_SET_VCPU_EVENTS: {
3523 struct kvm_vcpu_events events;
3524
3525 r = -EFAULT;
3526 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3527 break;
3528
3529 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3530 break;
3531 }
a1efbe77
JK		 3532 case KVM_GET_DEBUGREGS: {
3533 struct kvm_debugregs dbgregs;
3534
3535 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3536
3537 r = -EFAULT;
3538 if (copy_to_user(argp, &dbgregs,
3539 sizeof(struct kvm_debugregs)))
3540 break;
3541 r = 0;
3542 break;
3543 }
3544 case KVM_SET_DEBUGREGS: {
3545 struct kvm_debugregs dbgregs;
3546
3547 r = -EFAULT;
3548 if (copy_from_user(&dbgregs, argp,
3549 sizeof(struct kvm_debugregs)))
3550 break;
3551
3552 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3553 break;
3554 }
2d5b5a66 3555 case KVM_GET_XSAVE: {
d1ac91d8 3556 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3557 r = -ENOMEM;
d1ac91d8 3558 if (!u.xsave)
2d5b5a66
SY		 3559 break;
3560
d1ac91d8 3561 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3562
3563 r = -EFAULT;
d1ac91d8 3564 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3565 break;
3566 r = 0;
3567 break;
3568 }
3569 case KVM_SET_XSAVE: {
ff5c2c03 3570 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3571 if (IS_ERR(u.xsave))
3572 return PTR_ERR(u.xsave);
2d5b5a66 3573
d1ac91d8 3574 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3575 break;
3576 }
3577 case KVM_GET_XCRS: {
d1ac91d8 3578 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3579 r = -ENOMEM;
d1ac91d8 3580 if (!u.xcrs)
2d5b5a66
SY		 3581 break;
3582
d1ac91d8 3583 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3584
3585 r = -EFAULT;
d1ac91d8 3586 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3587 sizeof(struct kvm_xcrs)))
3588 break;
3589 r = 0;
3590 break;
3591 }
3592 case KVM_SET_XCRS: {
ff5c2c03 3593 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3594 if (IS_ERR(u.xcrs))
3595 return PTR_ERR(u.xcrs);
2d5b5a66 3596
d1ac91d8 3597 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3598 break;
3599 }
92a1f12d
JR		 3600 case KVM_SET_TSC_KHZ: {
3601 u32 user_tsc_khz;
3602
3603 r = -EINVAL;
92a1f12d
JR		 3604 user_tsc_khz = (u32)arg;
3605
3606 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3607 goto out;
3608
cc578287
ZA		 3609 if (user_tsc_khz == 0)
3610 user_tsc_khz = tsc_khz;
3611
3612 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3613
3614 r = 0;
3615 goto out;
3616 }
3617 case KVM_GET_TSC_KHZ: {
cc578287 3618 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3619 goto out;
3620 }
1c0b28c2
EM		 3621 case KVM_KVMCLOCK_CTRL: {
3622 r = kvm_set_guest_paused(vcpu);
3623 goto out;
3624 }
313a3dc7
CO		 3625 default:
3626 r = -EINVAL;
3627 }
3628out:
d1ac91d8 3629 kfree(u.buffer);
313a3dc7
CO		 3630 return r;
3631}
3632
5b1c1493
CO		 3633int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3634{
3635 return VM_FAULT_SIGBUS;
3636}
3637
1fe779f8
CO		 3638static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3639{
3640 int ret;
3641
3642 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3643 return -EINVAL;
1fe779f8
CO		 3644 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3645 return ret;
3646}
3647
b927a3ce
SY		 3648static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3649 u64 ident_addr)
3650{
3651 kvm->arch.ept_identity_map_addr = ident_addr;
3652 return 0;
3653}
3654
1fe779f8
CO		 3655static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3656 u32 kvm_nr_mmu_pages)
3657{
3658 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3659 return -EINVAL;
3660
79fac95e 3661 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3662
3663 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3664 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3665
79fac95e 3666 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3667 return 0;
3668}
3669
3670static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3671{
39de71ec 3672 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3673}
3674
1fe779f8
CO		 3675static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3676{
3677 int r;
3678
3679 r = 0;
3680 switch (chip->chip_id) {
3681 case KVM_IRQCHIP_PIC_MASTER:
3682 memcpy(&chip->chip.pic,
3683 &pic_irqchip(kvm)->pics[0],
3684 sizeof(struct kvm_pic_state));
3685 break;
3686 case KVM_IRQCHIP_PIC_SLAVE:
3687 memcpy(&chip->chip.pic,
3688 &pic_irqchip(kvm)->pics[1],
3689 sizeof(struct kvm_pic_state));
3690 break;
3691 case KVM_IRQCHIP_IOAPIC:
eba0226b 3692 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3693 break;
3694 default:
3695 r = -EINVAL;
3696 break;
3697 }
3698 return r;
3699}
3700
3701static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3702{
3703 int r;
3704
3705 r = 0;
3706 switch (chip->chip_id) {
3707 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3708 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3709 memcpy(&pic_irqchip(kvm)->pics[0],
3710 &chip->chip.pic,
3711 sizeof(struct kvm_pic_state));
f4f51050 3712 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3713 break;
3714 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3715 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3716 memcpy(&pic_irqchip(kvm)->pics[1],
3717 &chip->chip.pic,
3718 sizeof(struct kvm_pic_state));
f4f51050 3719 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3720 break;
3721 case KVM_IRQCHIP_IOAPIC:
eba0226b 3722 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3723 break;
3724 default:
3725 r = -EINVAL;
3726 break;
3727 }
3728 kvm_pic_update_irq(pic_irqchip(kvm));
3729 return r;
3730}
3731
e0f63cb9
SY		 3732static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3733{
3734 int r = 0;
3735
894a9c55 3736 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3737 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3738 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3739 return r;
3740}
3741
3742static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3743{
3744 int r = 0;
3745
894a9c55 3746 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3747 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3748 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3749 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3750 return r;
3751}
3752
3753static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3754{
3755 int r = 0;
3756
3757 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3758 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3759 sizeof(ps->channels));
3760 ps->flags = kvm->arch.vpit->pit_state.flags;
3761 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3762 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3763 return r;
3764}
3765
3766static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3767{
3768 int r = 0, start = 0;
3769 u32 prev_legacy, cur_legacy;
3770 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3771 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3772 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3773 if (!prev_legacy && cur_legacy)
3774 start = 1;
3775 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3776 sizeof(kvm->arch.vpit->pit_state.channels));
3777 kvm->arch.vpit->pit_state.flags = ps->flags;
3778 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3779 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3780 return r;
3781}
3782
52d939a0
MT		 3783static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3784 struct kvm_reinject_control *control)
3785{
3786 if (!kvm->arch.vpit)
3787 return -ENXIO;
894a9c55 3788 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3789 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3790 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3791 return 0;
3792}
3793
95d4c16c 3794/**
60c34612
TY		 3795 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3796 * @kvm: kvm instance
3797 * @log: slot id and address to which we copy the log
95d4c16c 3798 *
e108ff2f
PB		 3799 * Steps 1-4 below provide general overview of dirty page logging. See
3800 * kvm_get_dirty_log_protect() function description for additional details.
3801 *
3802 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3803 * always flush the TLB (step 4) even if previous step failed and the dirty
3804 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3805 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3806 * writes will be marked dirty for next log read.
95d4c16c 3807 *
60c34612
TY		 3808 * 1. Take a snapshot of the bit and clear it if needed.
3809 * 2. Write protect the corresponding page.
e108ff2f
PB		 3810 * 3. Copy the snapshot to the userspace.
3811 * 4. Flush TLB's if needed.
5bb064dc 3812 */
60c34612 3813int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3814{
60c34612 3815 bool is_dirty = false;
e108ff2f 3816 int r;
5bb064dc 3817
79fac95e 3818 mutex_lock(&kvm->slots_lock);
5bb064dc 3819
88178fd4
KH		 3820 /*
3821 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3822 */
3823 if (kvm_x86_ops->flush_log_dirty)
3824 kvm_x86_ops->flush_log_dirty(kvm);
3825
e108ff2f 3826 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3827
3828 /*
3829 * All the TLBs can be flushed out of mmu lock, see the comments in
3830 * kvm_mmu_slot_remove_write_access().
3831 */
e108ff2f 3832 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3833 if (is_dirty)
3834 kvm_flush_remote_tlbs(kvm);
3835
79fac95e 3836 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3837 return r;
3838}
3839
aa2fbe6d
YZ		 3840int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3841 bool line_status)
23d43cf9
CD		 3842{
3843 if (!irqchip_in_kernel(kvm))
3844 return -ENXIO;
3845
3846 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3847 irq_event->irq, irq_event->level,
3848 line_status);
23d43cf9
CD		 3849 return 0;
3850}
3851
90de4a18
NA		 3852static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3853 struct kvm_enable_cap *cap)
3854{
3855 int r;
3856
3857 if (cap->flags)
3858 return -EINVAL;
3859
3860 switch (cap->cap) {
3861 case KVM_CAP_DISABLE_QUIRKS:
3862 kvm->arch.disabled_quirks = cap->args[0];
3863 r = 0;
3864 break;
3865 default:
3866 r = -EINVAL;
3867 break;
3868 }
3869 return r;
3870}
3871
1fe779f8
CO		 3872long kvm_arch_vm_ioctl(struct file *filp,
3873 unsigned int ioctl, unsigned long arg)
3874{
3875 struct kvm *kvm = filp->private_data;
3876 void __user *argp = (void __user *)arg;
367e1319 3877 int r = -ENOTTY;
f0d66275
DH		 3878 /*
3879 * This union makes it completely explicit to gcc-3.x
3880 * that these two variables' stack usage should be
3881 * combined, not added together.
3882 */
3883 union {
3884 struct kvm_pit_state ps;
e9f42757 3885 struct kvm_pit_state2 ps2;
c5ff41ce 3886 struct kvm_pit_config pit_config;
f0d66275 3887 } u;
1fe779f8
CO		 3888
3889 switch (ioctl) {
3890 case KVM_SET_TSS_ADDR:
3891 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3892 break;
b927a3ce
SY		 3893 case KVM_SET_IDENTITY_MAP_ADDR: {
3894 u64 ident_addr;
3895
3896 r = -EFAULT;
3897 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3898 goto out;
3899 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3900 break;
3901 }
1fe779f8
CO		 3902 case KVM_SET_NR_MMU_PAGES:
3903 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3904 break;
3905 case KVM_GET_NR_MMU_PAGES:
3906 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3907 break;
3ddea128
MT		 3908 case KVM_CREATE_IRQCHIP: {
3909 struct kvm_pic *vpic;
3910
3911 mutex_lock(&kvm->lock);
3912 r = -EEXIST;
3913 if (kvm->arch.vpic)
3914 goto create_irqchip_unlock;
3e515705
AK		 3915 r = -EINVAL;
3916 if (atomic_read(&kvm->online_vcpus))
3917 goto create_irqchip_unlock;
1fe779f8 3918 r = -ENOMEM;
3ddea128
MT		 3919 vpic = kvm_create_pic(kvm);
3920 if (vpic) {
1fe779f8
CO		 3921 r = kvm_ioapic_init(kvm);
3922 if (r) {
175504cd 3923 mutex_lock(&kvm->slots_lock);
72bb2fcd 3924 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3925 &vpic->dev_master);
3926 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3927 &vpic->dev_slave);
3928 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3929 &vpic->dev_eclr);
175504cd 3930 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3931 kfree(vpic);
3932 goto create_irqchip_unlock;
1fe779f8
CO		 3933 }
3934 } else
3ddea128
MT		 3935 goto create_irqchip_unlock;
3936 smp_wmb();
3937 kvm->arch.vpic = vpic;
3938 smp_wmb();
399ec807
AK		 3939 r = kvm_setup_default_irq_routing(kvm);
3940 if (r) {
175504cd 3941 mutex_lock(&kvm->slots_lock);
3ddea128 3942 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3943 kvm_ioapic_destroy(kvm);
3944 kvm_destroy_pic(kvm);
3ddea128 3945 mutex_unlock(&kvm->irq_lock);
175504cd 3946 mutex_unlock(&kvm->slots_lock);
399ec807 3947 }
3ddea128
MT		 3948 create_irqchip_unlock:
3949 mutex_unlock(&kvm->lock);
1fe779f8 3950 break;
3ddea128 3951 }
7837699f 3952 case KVM_CREATE_PIT:
c5ff41ce
JK		 3953 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3954 goto create_pit;
3955 case KVM_CREATE_PIT2:
3956 r = -EFAULT;
3957 if (copy_from_user(&u.pit_config, argp,
3958 sizeof(struct kvm_pit_config)))
3959 goto out;
3960 create_pit:
79fac95e 3961 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3962 r = -EEXIST;
3963 if (kvm->arch.vpit)
3964 goto create_pit_unlock;
7837699f 3965 r = -ENOMEM;
c5ff41ce 3966 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3967 if (kvm->arch.vpit)
3968 r = 0;
269e05e4 3969 create_pit_unlock:
79fac95e 3970 mutex_unlock(&kvm->slots_lock);
7837699f 3971 break;
1fe779f8
CO		 3972 case KVM_GET_IRQCHIP: {
3973 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3974 struct kvm_irqchip *chip;
1fe779f8 3975
ff5c2c03
SL		 3976 chip = memdup_user(argp, sizeof(*chip));
3977 if (IS_ERR(chip)) {
3978 r = PTR_ERR(chip);
1fe779f8 3979 goto out;
ff5c2c03
SL		 3980 }
3981
1fe779f8
CO		 3982 r = -ENXIO;
3983 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3984 goto get_irqchip_out;
3985 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3986 if (r)
f0d66275 3987 goto get_irqchip_out;
1fe779f8 3988 r = -EFAULT;
f0d66275
DH		 3989 if (copy_to_user(argp, chip, sizeof *chip))
3990 goto get_irqchip_out;
1fe779f8 3991 r = 0;
f0d66275
DH		 3992 get_irqchip_out:
3993 kfree(chip);
1fe779f8
CO		 3994 break;
3995 }
3996 case KVM_SET_IRQCHIP: {
3997 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3998 struct kvm_irqchip *chip;
1fe779f8 3999
ff5c2c03
SL		 4000 chip = memdup_user(argp, sizeof(*chip));
4001 if (IS_ERR(chip)) {
4002 r = PTR_ERR(chip);
1fe779f8 4003 goto out;
ff5c2c03
SL		 4004 }
4005
1fe779f8
CO		 4006 r = -ENXIO;
4007 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 4008 goto set_irqchip_out;
4009 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4010 if (r)
f0d66275 4011 goto set_irqchip_out;
1fe779f8 4012 r = 0;
f0d66275
DH		 4013 set_irqchip_out:
4014 kfree(chip);
1fe779f8
CO		 4015 break;
4016 }
e0f63cb9 4017 case KVM_GET_PIT: {
e0f63cb9 4018 r = -EFAULT;
f0d66275 4019 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4020 goto out;
4021 r = -ENXIO;
4022 if (!kvm->arch.vpit)
4023 goto out;
f0d66275 4024 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4025 if (r)
4026 goto out;
4027 r = -EFAULT;
f0d66275 4028 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4029 goto out;
4030 r = 0;
4031 break;
4032 }
4033 case KVM_SET_PIT: {
e0f63cb9 4034 r = -EFAULT;
f0d66275 4035 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4036 goto out;
4037 r = -ENXIO;
4038 if (!kvm->arch.vpit)
4039 goto out;
f0d66275 4040 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4041 break;
4042 }
e9f42757
BK		 4043 case KVM_GET_PIT2: {
4044 r = -ENXIO;
4045 if (!kvm->arch.vpit)
4046 goto out;
4047 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4048 if (r)
4049 goto out;
4050 r = -EFAULT;
4051 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4052 goto out;
4053 r = 0;
4054 break;
4055 }
4056 case KVM_SET_PIT2: {
4057 r = -EFAULT;
4058 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4059 goto out;
4060 r = -ENXIO;
4061 if (!kvm->arch.vpit)
4062 goto out;
4063 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4064 break;
4065 }
52d939a0
MT		 4066 case KVM_REINJECT_CONTROL: {
4067 struct kvm_reinject_control control;
4068 r = -EFAULT;
4069 if (copy_from_user(&control, argp, sizeof(control)))
4070 goto out;
4071 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4072 break;
4073 }
ffde22ac
ES		 4074 case KVM_XEN_HVM_CONFIG: {
4075 r = -EFAULT;
4076 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4077 sizeof(struct kvm_xen_hvm_config)))
4078 goto out;
4079 r = -EINVAL;
4080 if (kvm->arch.xen_hvm_config.flags)
4081 goto out;
4082 r = 0;
4083 break;
4084 }
afbcf7ab 4085 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4086 struct kvm_clock_data user_ns;
4087 u64 now_ns;
4088 s64 delta;
4089
4090 r = -EFAULT;
4091 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4092 goto out;
4093
4094 r = -EINVAL;
4095 if (user_ns.flags)
4096 goto out;
4097
4098 r = 0;
395c6b0a 4099 local_irq_disable();
759379dd 4100 now_ns = get_kernel_ns();
afbcf7ab 4101 delta = user_ns.clock - now_ns;
395c6b0a 4102 local_irq_enable();
afbcf7ab 4103 kvm->arch.kvmclock_offset = delta;
2e762ff7 4104 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4105 break;
4106 }
4107 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4108 struct kvm_clock_data user_ns;
4109 u64 now_ns;
4110
395c6b0a 4111 local_irq_disable();
759379dd 4112 now_ns = get_kernel_ns();
afbcf7ab 4113 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4114 local_irq_enable();
afbcf7ab 4115 user_ns.flags = 0;
97e69aa6 4116 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4117
4118 r = -EFAULT;
4119 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4120 goto out;
4121 r = 0;
4122 break;
4123 }
90de4a18
NA		 4124 case KVM_ENABLE_CAP: {
4125 struct kvm_enable_cap cap;
afbcf7ab 4126
90de4a18
NA		 4127 r = -EFAULT;
4128 if (copy_from_user(&cap, argp, sizeof(cap)))
4129 goto out;
4130 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4131 break;
4132 }
1fe779f8 4133 default:
c274e03a 4134 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4135 }
4136out:
4137 return r;
4138}
4139
a16b043c 4140static void kvm_init_msr_list(void)
043405e1
CO		 4141{
4142 u32 dummy[2];
4143 unsigned i, j;
4144
e3267cbb
GC		 4145 /* skip the first msrs in the list. KVM-specific */
4146 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4147 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4148 continue;
93c4adc7
PB		 4149
4150 /*
4151 * Even MSRs that are valid in the host may not be exposed
4152 * to the guests in some cases. We could work around this
4153 * in VMX with the generic MSR save/load machinery, but it
4154 * is not really worthwhile since it will really only
4155 * happen with nested virtualization.
4156 */
4157 switch (msrs_to_save[i]) {
4158 case MSR_IA32_BNDCFGS:
4159 if (!kvm_x86_ops->mpx_supported())
4160 continue;
4161 break;
4162 default:
4163 break;
4164 }
4165
043405e1
CO		 4166 if (j < i)
4167 msrs_to_save[j] = msrs_to_save[i];
4168 j++;
4169 }
4170 num_msrs_to_save = j;
4171}
4172
bda9020e
MT		 4173static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4174 const void *v)
bbd9b64e 4175{
70252a10
AK		 4176 int handled = 0;
4177 int n;
4178
4179 do {
4180 n = min(len, 8);
4181 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4182 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4183 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4184 break;
4185 handled += n;
4186 addr += n;
4187 len -= n;
4188 v += n;
4189 } while (len);
bbd9b64e 4190
70252a10 4191 return handled;
bbd9b64e
CO		 4192}
4193
bda9020e 4194static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4195{
70252a10
AK		 4196 int handled = 0;
4197 int n;
4198
4199 do {
4200 n = min(len, 8);
4201 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4202 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4203 addr, n, v))
4204 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4205 break;
4206 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4207 handled += n;
4208 addr += n;
4209 len -= n;
4210 v += n;
4211 } while (len);
bbd9b64e 4212
70252a10 4213 return handled;
bbd9b64e
CO		 4214}
4215
2dafc6c2
GN		 4216static void kvm_set_segment(struct kvm_vcpu *vcpu,
4217 struct kvm_segment *var, int seg)
4218{
4219 kvm_x86_ops->set_segment(vcpu, var, seg);
4220}
4221
4222void kvm_get_segment(struct kvm_vcpu *vcpu,
4223 struct kvm_segment *var, int seg)
4224{
4225 kvm_x86_ops->get_segment(vcpu, var, seg);
4226}
4227
54987b7a
PB		 4228gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4229 struct x86_exception *exception)
02f59dc9
JR		 4230{
4231 gpa_t t_gpa;
02f59dc9
JR		 4232
4233 BUG_ON(!mmu_is_nested(vcpu));
4234
4235 /* NPT walks are always user-walks */
4236 access |= PFERR_USER_MASK;
54987b7a 4237 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4238
4239 return t_gpa;
4240}
4241
ab9ae313
AK		 4242gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4243 struct x86_exception *exception)
1871c602
GN		 4244{
4245 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4246 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4247}
4248
ab9ae313
AK		 4249 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4250 struct x86_exception *exception)
1871c602
GN		 4251{
4252 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4253 access |= PFERR_FETCH_MASK;
ab9ae313 4254 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4255}
4256
ab9ae313
AK		 4257gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4258 struct x86_exception *exception)
1871c602
GN		 4259{
4260 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4261 access |= PFERR_WRITE_MASK;
ab9ae313 4262 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4263}
4264
4265/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4266gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4267 struct x86_exception *exception)
1871c602 4268{
ab9ae313 4269 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4270}
4271
4272static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4273 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4274 struct x86_exception *exception)
bbd9b64e
CO		 4275{
4276 void *data = val;
10589a46 4277 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4278
4279 while (bytes) {
14dfe855 4280 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4281 exception);
bbd9b64e 4282 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4283 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4284 int ret;
4285
bcc55cba 4286 if (gpa == UNMAPPED_GVA)
ab9ae313 4287 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4288 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4289 offset, toread);
10589a46 4290 if (ret < 0) {
c3cd7ffa 4291 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4292 goto out;
4293 }
bbd9b64e 4294
77c2002e
IE		 4295 bytes -= toread;
4296 data += toread;
4297 addr += toread;
bbd9b64e 4298 }
10589a46 4299out:
10589a46 4300 return r;
bbd9b64e 4301}
77c2002e 4302
1871c602 4303/* used for instruction fetching */
0f65dd70
AK		 4304static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4305 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4306 struct x86_exception *exception)
1871c602 4307{
0f65dd70 4308 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4309 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4310 unsigned offset;
4311 int ret;
0f65dd70 4312
44583cba
PB		 4313 /* Inline kvm_read_guest_virt_helper for speed. */
4314 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4315 exception);
4316 if (unlikely(gpa == UNMAPPED_GVA))
4317 return X86EMUL_PROPAGATE_FAULT;
4318
4319 offset = addr & (PAGE_SIZE-1);
4320 if (WARN_ON(offset + bytes > PAGE_SIZE))
4321 bytes = (unsigned)PAGE_SIZE - offset;
4322 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4323 offset, bytes);
4324 if (unlikely(ret < 0))
4325 return X86EMUL_IO_NEEDED;
4326
4327 return X86EMUL_CONTINUE;
1871c602
GN		 4328}
4329
064aea77 4330int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4331 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4332 struct x86_exception *exception)
1871c602 4333{
0f65dd70 4334 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4335 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4336
1871c602 4337 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4338 exception);
1871c602 4339}
064aea77 4340EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4341
0f65dd70
AK		 4342static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4343 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4344 struct x86_exception *exception)
1871c602 4345{
0f65dd70 4346 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4347 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4348}
4349
6a4d7550 4350int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4351 gva_t addr, void *val,
2dafc6c2 4352 unsigned int bytes,
bcc55cba 4353 struct x86_exception *exception)
77c2002e 4354{
0f65dd70 4355 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4356 void *data = val;
4357 int r = X86EMUL_CONTINUE;
4358
4359 while (bytes) {
14dfe855
JR		 4360 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4361 PFERR_WRITE_MASK,
ab9ae313 4362 exception);
77c2002e
IE		 4363 unsigned offset = addr & (PAGE_SIZE-1);
4364 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4365 int ret;
4366
bcc55cba 4367 if (gpa == UNMAPPED_GVA)
ab9ae313 4368 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4369 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4370 if (ret < 0) {
c3cd7ffa 4371 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4372 goto out;
4373 }
4374
4375 bytes -= towrite;
4376 data += towrite;
4377 addr += towrite;
4378 }
4379out:
4380 return r;
4381}
6a4d7550 4382EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4383
af7cc7d1
XG		 4384static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4385 gpa_t *gpa, struct x86_exception *exception,
4386 bool write)
4387{
97d64b78
AK		 4388 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4389 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4390
97d64b78 4391 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4392 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4393 vcpu->arch.access, access)) {
bebb106a
XG		 4394 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4395 (gva & (PAGE_SIZE - 1));
4f022648 4396 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4397 return 1;
4398 }
4399
af7cc7d1
XG		 4400 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4401
4402 if (*gpa == UNMAPPED_GVA)
4403 return -1;
4404
4405 /* For APIC access vmexit */
4406 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4407 return 1;
4408
4f022648
XG		 4409 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4410 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4411 return 1;
4f022648 4412 }
bebb106a 4413
af7cc7d1
XG		 4414 return 0;
4415}
4416
3200f405 4417int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4418 const void *val, int bytes)
bbd9b64e
CO		 4419{
4420 int ret;
4421
4422 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4423 if (ret < 0)
bbd9b64e 4424 return 0;
f57f2ef5 4425 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4426 return 1;
4427}
4428
77d197b2
XG		 4429struct read_write_emulator_ops {
4430 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4431 int bytes);
4432 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4433 void *val, int bytes);
4434 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4435 int bytes, void *val);
4436 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4437 void *val, int bytes);
4438 bool write;
4439};
4440
4441static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4442{
4443 if (vcpu->mmio_read_completed) {
77d197b2 4444 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4445 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4446 vcpu->mmio_read_completed = 0;
4447 return 1;
4448 }
4449
4450 return 0;
4451}
4452
4453static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4454 void *val, int bytes)
4455{
4456 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4457}
4458
4459static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4460 void *val, int bytes)
4461{
4462 return emulator_write_phys(vcpu, gpa, val, bytes);
4463}
4464
4465static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4466{
4467 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4468 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4469}
4470
4471static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4472 void *val, int bytes)
4473{
4474 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4475 return X86EMUL_IO_NEEDED;
4476}
4477
4478static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4479 void *val, int bytes)
4480{
f78146b0
AK		 4481 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4482
87da7e66 4483 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4484 return X86EMUL_CONTINUE;
4485}
4486
0fbe9b0b 4487static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4488 .read_write_prepare = read_prepare,
4489 .read_write_emulate = read_emulate,
4490 .read_write_mmio = vcpu_mmio_read,
4491 .read_write_exit_mmio = read_exit_mmio,
4492};
4493
0fbe9b0b 4494static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4495 .read_write_emulate = write_emulate,
4496 .read_write_mmio = write_mmio,
4497 .read_write_exit_mmio = write_exit_mmio,
4498 .write = true,
4499};
4500
22388a3c
XG		 4501static int emulator_read_write_onepage(unsigned long addr, void *val,
4502 unsigned int bytes,
4503 struct x86_exception *exception,
4504 struct kvm_vcpu *vcpu,
0fbe9b0b 4505 const struct read_write_emulator_ops *ops)
bbd9b64e 4506{
af7cc7d1
XG		 4507 gpa_t gpa;
4508 int handled, ret;
22388a3c 4509 bool write = ops->write;
f78146b0 4510 struct kvm_mmio_fragment *frag;
10589a46 4511
22388a3c 4512 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4513
af7cc7d1 4514 if (ret < 0)
bbd9b64e 4515 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4516
4517 /* For APIC access vmexit */
af7cc7d1 4518 if (ret)
bbd9b64e
CO		 4519 goto mmio;
4520
22388a3c 4521 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4522 return X86EMUL_CONTINUE;
4523
4524mmio:
4525 /*
4526 * Is this MMIO handled locally?
4527 */
22388a3c 4528 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4529 if (handled == bytes)
bbd9b64e 4530 return X86EMUL_CONTINUE;
bbd9b64e 4531
70252a10
AK		 4532 gpa += handled;
4533 bytes -= handled;
4534 val += handled;
4535
87da7e66
XG		 4536 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4537 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4538 frag->gpa = gpa;
4539 frag->data = val;
4540 frag->len = bytes;
f78146b0 4541 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4542}
4543
52eb5a6d
XL		 4544static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4545 unsigned long addr,
22388a3c
XG		 4546 void *val, unsigned int bytes,
4547 struct x86_exception *exception,
0fbe9b0b 4548 const struct read_write_emulator_ops *ops)
bbd9b64e 4549{
0f65dd70 4550 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4551 gpa_t gpa;
4552 int rc;
4553
4554 if (ops->read_write_prepare &&
4555 ops->read_write_prepare(vcpu, val, bytes))
4556 return X86EMUL_CONTINUE;
4557
4558 vcpu->mmio_nr_fragments = 0;
0f65dd70 4559
bbd9b64e
CO		 4560 /* Crossing a page boundary? */
4561 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4562 int now;
bbd9b64e
CO		 4563
4564 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4565 rc = emulator_read_write_onepage(addr, val, now, exception,
4566 vcpu, ops);
4567
bbd9b64e
CO		 4568 if (rc != X86EMUL_CONTINUE)
4569 return rc;
4570 addr += now;
bac15531
NA		 4571 if (ctxt->mode != X86EMUL_MODE_PROT64)
4572 addr = (u32)addr;
bbd9b64e
CO		 4573 val += now;
4574 bytes -= now;
4575 }
22388a3c 4576
f78146b0
AK		 4577 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4578 vcpu, ops);
4579 if (rc != X86EMUL_CONTINUE)
4580 return rc;
4581
4582 if (!vcpu->mmio_nr_fragments)
4583 return rc;
4584
4585 gpa = vcpu->mmio_fragments[0].gpa;
4586
4587 vcpu->mmio_needed = 1;
4588 vcpu->mmio_cur_fragment = 0;
4589
87da7e66 4590 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4591 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4592 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4593 vcpu->run->mmio.phys_addr = gpa;
4594
4595 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4596}
4597
4598static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4599 unsigned long addr,
4600 void *val,
4601 unsigned int bytes,
4602 struct x86_exception *exception)
4603{
4604 return emulator_read_write(ctxt, addr, val, bytes,
4605 exception, &read_emultor);
4606}
4607
52eb5a6d 4608static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4609 unsigned long addr,
4610 const void *val,
4611 unsigned int bytes,
4612 struct x86_exception *exception)
4613{
4614 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4615 exception, &write_emultor);
bbd9b64e 4616}
bbd9b64e 4617
daea3e73
AK		 4618#define CMPXCHG_TYPE(t, ptr, old, new) \
4619 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4620
4621#ifdef CONFIG_X86_64
4622# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4623#else
4624# define CMPXCHG64(ptr, old, new) \
9749a6c0 4625 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4626#endif
4627
0f65dd70
AK		 4628static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4629 unsigned long addr,
bbd9b64e
CO		 4630 const void *old,
4631 const void *new,
4632 unsigned int bytes,
0f65dd70 4633 struct x86_exception *exception)
bbd9b64e 4634{
0f65dd70 4635 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4636 gpa_t gpa;
4637 struct page *page;
4638 char *kaddr;
4639 bool exchanged;
2bacc55c 4640
daea3e73
AK		 4641 /* guests cmpxchg8b have to be emulated atomically */
4642 if (bytes > 8 || (bytes & (bytes - 1)))
4643 goto emul_write;
10589a46 4644
daea3e73 4645 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4646
daea3e73
AK		 4647 if (gpa == UNMAPPED_GVA ||
4648 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4649 goto emul_write;
2bacc55c 4650
daea3e73
AK		 4651 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4652 goto emul_write;
72dc67a6 4653
daea3e73 4654 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4655 if (is_error_page(page))
c19b8bd6 4656 goto emul_write;
72dc67a6 4657
8fd75e12 4658 kaddr = kmap_atomic(page);
daea3e73
AK		 4659 kaddr += offset_in_page(gpa);
4660 switch (bytes) {
4661 case 1:
4662 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4663 break;
4664 case 2:
4665 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4666 break;
4667 case 4:
4668 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4669 break;
4670 case 8:
4671 exchanged = CMPXCHG64(kaddr, old, new);
4672 break;
4673 default:
4674 BUG();
2bacc55c 4675 }
8fd75e12 4676 kunmap_atomic(kaddr);
daea3e73
AK		 4677 kvm_release_page_dirty(page);
4678
4679 if (!exchanged)
4680 return X86EMUL_CMPXCHG_FAILED;
4681
d3714010 4682 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4683 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4684
4685 return X86EMUL_CONTINUE;
4a5f48f6 4686
3200f405 4687emul_write:
daea3e73 4688 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4689
0f65dd70 4690 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4691}
4692
cf8f70bf
GN		 4693static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4694{
4695 /* TODO: String I/O for in kernel device */
4696 int r;
4697
4698 if (vcpu->arch.pio.in)
e32edf4f 4699 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4700 vcpu->arch.pio.size, pd);
4701 else
e32edf4f 4702 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4703 vcpu->arch.pio.port, vcpu->arch.pio.size,
4704 pd);
4705 return r;
4706}
4707
6f6fbe98
XG		 4708static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4709 unsigned short port, void *val,
4710 unsigned int count, bool in)
cf8f70bf 4711{
cf8f70bf 4712 vcpu->arch.pio.port = port;
6f6fbe98 4713 vcpu->arch.pio.in = in;
7972995b 4714 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4715 vcpu->arch.pio.size = size;
4716
4717 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4718 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4719 return 1;
4720 }
4721
4722 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4723 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4724 vcpu->run->io.size = size;
4725 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4726 vcpu->run->io.count = count;
4727 vcpu->run->io.port = port;
4728
4729 return 0;
4730}
4731
6f6fbe98
XG		 4732static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4733 int size, unsigned short port, void *val,
4734 unsigned int count)
cf8f70bf 4735{
ca1d4a9e 4736 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4737 int ret;
ca1d4a9e 4738
6f6fbe98
XG		 4739 if (vcpu->arch.pio.count)
4740 goto data_avail;
cf8f70bf 4741
6f6fbe98
XG		 4742 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4743 if (ret) {
4744data_avail:
4745 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4746 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4747 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4748 return 1;
4749 }
4750
cf8f70bf
GN		 4751 return 0;
4752}
4753
6f6fbe98
XG		 4754static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4755 int size, unsigned short port,
4756 const void *val, unsigned int count)
4757{
4758 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4759
4760 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4761 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4762 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4763}
4764
bbd9b64e
CO		 4765static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4766{
4767 return kvm_x86_ops->get_segment_base(vcpu, seg);
4768}
4769
3cb16fe7 4770static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4771{
3cb16fe7 4772 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4773}
4774
5cb56059 4775int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4776{
4777 if (!need_emulate_wbinvd(vcpu))
4778 return X86EMUL_CONTINUE;
4779
4780 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4781 int cpu = get_cpu();
4782
4783 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4784 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4785 wbinvd_ipi, NULL, 1);
2eec7343 4786 put_cpu();
f5f48ee1 4787 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4788 } else
4789 wbinvd();
f5f48ee1
SY		 4790 return X86EMUL_CONTINUE;
4791}
5cb56059
JS		 4792
4793int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4794{
4795 kvm_x86_ops->skip_emulated_instruction(vcpu);
4796 return kvm_emulate_wbinvd_noskip(vcpu);
4797}
f5f48ee1
SY		 4798EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4799
5cb56059
JS		 4800
4801
bcaf5cc5
AK		 4802static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4803{
5cb56059 4804 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4805}
4806
52eb5a6d
XL		 4807static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4808 unsigned long *dest)
bbd9b64e 4809{
16f8a6f9 4810 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4811}
4812
52eb5a6d
XL		 4813static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4814 unsigned long value)
bbd9b64e 4815{
338dbc97 4816
717746e3 4817 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4818}
4819
52a46617 4820static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4821{
52a46617 4822 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4823}
4824
717746e3 4825static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4826{
717746e3 4827 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4828 unsigned long value;
4829
4830 switch (cr) {
4831 case 0:
4832 value = kvm_read_cr0(vcpu);
4833 break;
4834 case 2:
4835 value = vcpu->arch.cr2;
4836 break;
4837 case 3:
9f8fe504 4838 value = kvm_read_cr3(vcpu);
52a46617
GN		 4839 break;
4840 case 4:
4841 value = kvm_read_cr4(vcpu);
4842 break;
4843 case 8:
4844 value = kvm_get_cr8(vcpu);
4845 break;
4846 default:
a737f256 4847 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4848 return 0;
4849 }
4850
4851 return value;
4852}
4853
717746e3 4854static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4855{
717746e3 4856 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4857 int res = 0;
4858
52a46617
GN		 4859 switch (cr) {
4860 case 0:
49a9b07e 4861 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4862 break;
4863 case 2:
4864 vcpu->arch.cr2 = val;
4865 break;
4866 case 3:
2390218b 4867 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4868 break;
4869 case 4:
a83b29c6 4870 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4871 break;
4872 case 8:
eea1cff9 4873 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4874 break;
4875 default:
a737f256 4876 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4877 res = -1;
52a46617 4878 }
0f12244f
GN		 4879
4880 return res;
52a46617
GN		 4881}
4882
717746e3 4883static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4884{
717746e3 4885 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4886}
4887
4bff1e86 4888static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4889{
4bff1e86 4890 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4891}
4892
4bff1e86 4893static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4894{
4bff1e86 4895 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4896}
4897
1ac9d0cf
AK		 4898static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4899{
4900 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4901}
4902
4903static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4904{
4905 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4906}
4907
4bff1e86
AK		 4908static unsigned long emulator_get_cached_segment_base(
4909 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4910{
4bff1e86 4911 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4912}
4913
1aa36616
AK		 4914static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4915 struct desc_struct *desc, u32 *base3,
4916 int seg)
2dafc6c2
GN		 4917{
4918 struct kvm_segment var;
4919
4bff1e86 4920 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4921 *selector = var.selector;
2dafc6c2 4922
378a8b09
GN		 4923 if (var.unusable) {
4924 memset(desc, 0, sizeof(*desc));
2dafc6c2 4925 return false;
378a8b09 4926 }
2dafc6c2
GN		 4927
4928 if (var.g)
4929 var.limit >>= 12;
4930 set_desc_limit(desc, var.limit);
4931 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4932#ifdef CONFIG_X86_64
4933 if (base3)
4934 *base3 = var.base >> 32;
4935#endif
2dafc6c2
GN		 4936 desc->type = var.type;
4937 desc->s = var.s;
4938 desc->dpl = var.dpl;
4939 desc->p = var.present;
4940 desc->avl = var.avl;
4941 desc->l = var.l;
4942 desc->d = var.db;
4943 desc->g = var.g;
4944
4945 return true;
4946}
4947
1aa36616
AK		 4948static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4949 struct desc_struct *desc, u32 base3,
4950 int seg)
2dafc6c2 4951{
4bff1e86 4952 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4953 struct kvm_segment var;
4954
1aa36616 4955 var.selector = selector;
2dafc6c2 4956 var.base = get_desc_base(desc);
5601d05b
GN		 4957#ifdef CONFIG_X86_64
4958 var.base |= ((u64)base3) << 32;
4959#endif
2dafc6c2
GN		 4960 var.limit = get_desc_limit(desc);
4961 if (desc->g)
4962 var.limit = (var.limit << 12) | 0xfff;
4963 var.type = desc->type;
2dafc6c2
GN		 4964 var.dpl = desc->dpl;
4965 var.db = desc->d;
4966 var.s = desc->s;
4967 var.l = desc->l;
4968 var.g = desc->g;
4969 var.avl = desc->avl;
4970 var.present = desc->p;
4971 var.unusable = !var.present;
4972 var.padding = 0;
4973
4974 kvm_set_segment(vcpu, &var, seg);
4975 return;
4976}
4977
717746e3
AK		 4978static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4979 u32 msr_index, u64 *pdata)
4980{
4981 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4982}
4983
4984static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4985 u32 msr_index, u64 data)
4986{
8fe8ab46
WA		 4987 struct msr_data msr;
4988
4989 msr.data = data;
4990 msr.index = msr_index;
4991 msr.host_initiated = false;
4992 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4993}
4994
67f4d428
NA		 4995static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4996 u32 pmc)
4997{
4998 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4999}
5000
222d21aa
AK		 5001static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5002 u32 pmc, u64 *pdata)
5003{
5004 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
5005}
5006
6c3287f7
AK		 5007static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5008{
5009 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5010}
5011
5037f6f3
AK		 5012static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5013{
5014 preempt_disable();
5197b808 5015 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5016 /*
5017 * CR0.TS may reference the host fpu state, not the guest fpu state,
5018 * so it may be clear at this point.
5019 */
5020 clts();
5021}
5022
5023static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5024{
5025 preempt_enable();
5026}
5027
2953538e 5028static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5029 struct x86_instruction_info *info,
c4f035c6
AK		 5030 enum x86_intercept_stage stage)
5031{
2953538e 5032 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5033}
5034
0017f93a 5035static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5036 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5037{
0017f93a 5038 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5039}
5040
dd856efa
AK		 5041static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5042{
5043 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5044}
5045
5046static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5047{
5048 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5049}
5050
801806d9
NA		 5051static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5052{
5053 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5054}
5055
0225fb50 5056static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5057 .read_gpr = emulator_read_gpr,
5058 .write_gpr = emulator_write_gpr,
1871c602 5059 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5060 .write_std = kvm_write_guest_virt_system,
1871c602 5061 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5062 .read_emulated = emulator_read_emulated,
5063 .write_emulated = emulator_write_emulated,
5064 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5065 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5066 .pio_in_emulated = emulator_pio_in_emulated,
5067 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5068 .get_segment = emulator_get_segment,
5069 .set_segment = emulator_set_segment,
5951c442 5070 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5071 .get_gdt = emulator_get_gdt,
160ce1f1 5072 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5073 .set_gdt = emulator_set_gdt,
5074 .set_idt = emulator_set_idt,
52a46617
GN		 5075 .get_cr = emulator_get_cr,
5076 .set_cr = emulator_set_cr,
9c537244 5077 .cpl = emulator_get_cpl,
35aa5375
GN		 5078 .get_dr = emulator_get_dr,
5079 .set_dr = emulator_set_dr,
717746e3
AK		 5080 .set_msr = emulator_set_msr,
5081 .get_msr = emulator_get_msr,
67f4d428 5082 .check_pmc = emulator_check_pmc,
222d21aa 5083 .read_pmc = emulator_read_pmc,
6c3287f7 5084 .halt = emulator_halt,
bcaf5cc5 5085 .wbinvd = emulator_wbinvd,
d6aa1000 5086 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5087 .get_fpu = emulator_get_fpu,
5088 .put_fpu = emulator_put_fpu,
c4f035c6 5089 .intercept = emulator_intercept,
bdb42f5a 5090 .get_cpuid = emulator_get_cpuid,
801806d9 5091 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5092};
5093
95cb2295
GN		 5094static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5095{
37ccdcbe 5096 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5097 /*
5098 * an sti; sti; sequence only disable interrupts for the first
5099 * instruction. So, if the last instruction, be it emulated or
5100 * not, left the system with the INT_STI flag enabled, it
5101 * means that the last instruction is an sti. We should not
5102 * leave the flag on in this case. The same goes for mov ss
5103 */
37ccdcbe
PB		 5104 if (int_shadow & mask)
5105 mask = 0;
6addfc42 5106 if (unlikely(int_shadow || mask)) {
95cb2295 5107 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5108 if (!mask)
5109 kvm_make_request(KVM_REQ_EVENT, vcpu);
5110 }
95cb2295
GN		 5111}
5112
ef54bcfe 5113static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5114{
5115 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5116 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5117 return kvm_propagate_fault(vcpu, &ctxt->exception);
5118
5119 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5120 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5121 ctxt->exception.error_code);
54b8486f 5122 else
da9cb575 5123 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5124 return false;
54b8486f
GN		 5125}
5126
8ec4722d
MG		 5127static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5128{
adf52235 5129 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5130 int cs_db, cs_l;
5131
8ec4722d
MG		 5132 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5133
adf52235
TY		 5134 ctxt->eflags = kvm_get_rflags(vcpu);
5135 ctxt->eip = kvm_rip_read(vcpu);
5136 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5137 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5138 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5139 cs_db ? X86EMUL_MODE_PROT32 :
5140 X86EMUL_MODE_PROT16;
5141 ctxt->guest_mode = is_guest_mode(vcpu);
5142
dd856efa 5143 init_decode_cache(ctxt);
7ae441ea 5144 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5145}
5146
71f9833b 5147int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5148{
9d74191a 5149 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5150 int ret;
5151
5152 init_emulate_ctxt(vcpu);
5153
9dac77fa
AK		 5154 ctxt->op_bytes = 2;
5155 ctxt->ad_bytes = 2;
5156 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5157 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5158
5159 if (ret != X86EMUL_CONTINUE)
5160 return EMULATE_FAIL;
5161
9dac77fa 5162 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5163 kvm_rip_write(vcpu, ctxt->eip);
5164 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5165
5166 if (irq == NMI_VECTOR)
7460fb4a 5167 vcpu->arch.nmi_pending = 0;
63995653
MG		 5168 else
5169 vcpu->arch.interrupt.pending = false;
5170
5171 return EMULATE_DONE;
5172}
5173EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5174
6d77dbfc
GN		 5175static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5176{
fc3a9157
JR		 5177 int r = EMULATE_DONE;
5178
6d77dbfc
GN		 5179 ++vcpu->stat.insn_emulation_fail;
5180 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5181 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5182 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5183 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5184 vcpu->run->internal.ndata = 0;
5185 r = EMULATE_FAIL;
5186 }
6d77dbfc 5187 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5188
5189 return r;
6d77dbfc
GN		 5190}
5191
93c05d3e 5192static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5193 bool write_fault_to_shadow_pgtable,
5194 int emulation_type)
a6f177ef 5195{
95b3cf69 5196 gpa_t gpa = cr2;
8e3d9d06 5197 pfn_t pfn;
a6f177ef 5198
991eebf9
GN		 5199 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5200 return false;
5201
95b3cf69
XG		 5202 if (!vcpu->arch.mmu.direct_map) {
5203 /*
5204 * Write permission should be allowed since only
5205 * write access need to be emulated.
5206 */
5207 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5208
95b3cf69
XG		 5209 /*
5210 * If the mapping is invalid in guest, let cpu retry
5211 * it to generate fault.
5212 */
5213 if (gpa == UNMAPPED_GVA)
5214 return true;
5215 }
a6f177ef 5216
8e3d9d06
XG		 5217 /*
5218 * Do not retry the unhandleable instruction if it faults on the
5219 * readonly host memory, otherwise it will goto a infinite loop:
5220 * retry instruction -> write #PF -> emulation fail -> retry
5221 * instruction -> ...
5222 */
5223 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5224
5225 /*
5226 * If the instruction failed on the error pfn, it can not be fixed,
5227 * report the error to userspace.
5228 */
5229 if (is_error_noslot_pfn(pfn))
5230 return false;
5231
5232 kvm_release_pfn_clean(pfn);
5233
5234 /* The instructions are well-emulated on direct mmu. */
5235 if (vcpu->arch.mmu.direct_map) {
5236 unsigned int indirect_shadow_pages;
5237
5238 spin_lock(&vcpu->kvm->mmu_lock);
5239 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5240 spin_unlock(&vcpu->kvm->mmu_lock);
5241
5242 if (indirect_shadow_pages)
5243 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5244
a6f177ef 5245 return true;
8e3d9d06 5246 }
a6f177ef 5247
95b3cf69
XG		 5248 /*
5249 * if emulation was due to access to shadowed page table
5250 * and it failed try to unshadow page and re-enter the
5251 * guest to let CPU execute the instruction.
5252 */
5253 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5254
5255 /*
5256 * If the access faults on its page table, it can not
5257 * be fixed by unprotecting shadow page and it should
5258 * be reported to userspace.
5259 */
5260 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5261}
5262
1cb3f3ae
XG		 5263static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5264 unsigned long cr2, int emulation_type)
5265{
5266 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5267 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5268
5269 last_retry_eip = vcpu->arch.last_retry_eip;
5270 last_retry_addr = vcpu->arch.last_retry_addr;
5271
5272 /*
5273 * If the emulation is caused by #PF and it is non-page_table
5274 * writing instruction, it means the VM-EXIT is caused by shadow
5275 * page protected, we can zap the shadow page and retry this
5276 * instruction directly.
5277 *
5278 * Note: if the guest uses a non-page-table modifying instruction
5279 * on the PDE that points to the instruction, then we will unmap
5280 * the instruction and go to an infinite loop. So, we cache the
5281 * last retried eip and the last fault address, if we meet the eip
5282 * and the address again, we can break out of the potential infinite
5283 * loop.
5284 */
5285 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5286
5287 if (!(emulation_type & EMULTYPE_RETRY))
5288 return false;
5289
5290 if (x86_page_table_writing_insn(ctxt))
5291 return false;
5292
5293 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5294 return false;
5295
5296 vcpu->arch.last_retry_eip = ctxt->eip;
5297 vcpu->arch.last_retry_addr = cr2;
5298
5299 if (!vcpu->arch.mmu.direct_map)
5300 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5301
22368028 5302 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5303
5304 return true;
5305}
5306
716d51ab
GN		 5307static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5308static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5309
4a1e10d5
PB		 5310static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5311 unsigned long *db)
5312{
5313 u32 dr6 = 0;
5314 int i;
5315 u32 enable, rwlen;
5316
5317 enable = dr7;
5318 rwlen = dr7 >> 16;
5319 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5320 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5321 dr6 |= (1 << i);
5322 return dr6;
5323}
5324
6addfc42 5325static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5326{
5327 struct kvm_run *kvm_run = vcpu->run;
5328
5329 /*
6addfc42
PB		 5330 * rflags is the old, "raw" value of the flags. The new value has
5331 * not been saved yet.
663f4c61
PB		 5332 *
5333 * This is correct even for TF set by the guest, because "the
5334 * processor will not generate this exception after the instruction
5335 * that sets the TF flag".
5336 */
663f4c61
PB		 5337 if (unlikely(rflags & X86_EFLAGS_TF)) {
5338 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5339 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5340 DR6_RTM;
663f4c61
PB		 5341 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5342 kvm_run->debug.arch.exception = DB_VECTOR;
5343 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5344 *r = EMULATE_USER_EXIT;
5345 } else {
5346 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5347 /*
5348 * "Certain debug exceptions may clear bit 0-3. The
5349 * remaining contents of the DR6 register are never
5350 * cleared by the processor".
5351 */
5352 vcpu->arch.dr6 &= ~15;
6f43ed01 5353 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5354 kvm_queue_exception(vcpu, DB_VECTOR);
5355 }
5356 }
5357}
5358
4a1e10d5
PB		 5359static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5360{
4a1e10d5
PB		 5361 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5362 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5363 struct kvm_run *kvm_run = vcpu->run;
5364 unsigned long eip = kvm_get_linear_rip(vcpu);
5365 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5366 vcpu->arch.guest_debug_dr7,
5367 vcpu->arch.eff_db);
5368
5369 if (dr6 != 0) {
6f43ed01 5370 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5371 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5372 kvm_run->debug.arch.exception = DB_VECTOR;
5373 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5374 *r = EMULATE_USER_EXIT;
5375 return true;
5376 }
5377 }
5378
4161a569
NA		 5379 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5380 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5381 unsigned long eip = kvm_get_linear_rip(vcpu);
5382 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5383 vcpu->arch.dr7,
5384 vcpu->arch.db);
5385
5386 if (dr6 != 0) {
5387 vcpu->arch.dr6 &= ~15;
6f43ed01 5388 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5389 kvm_queue_exception(vcpu, DB_VECTOR);
5390 *r = EMULATE_DONE;
5391 return true;
5392 }
5393 }
5394
5395 return false;
5396}
5397
51d8b661
AP		 5398int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5399 unsigned long cr2,
dc25e89e
AP		 5400 int emulation_type,
5401 void *insn,
5402 int insn_len)
bbd9b64e 5403{
95cb2295 5404 int r;
9d74191a 5405 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5406 bool writeback = true;
93c05d3e 5407 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5408
93c05d3e
XG		 5409 /*
5410 * Clear write_fault_to_shadow_pgtable here to ensure it is
5411 * never reused.
5412 */
5413 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5414 kvm_clear_exception_queue(vcpu);
8d7d8102 5415
571008da 5416 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5417 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5418
5419 /*
5420 * We will reenter on the same instruction since
5421 * we do not set complete_userspace_io. This does not
5422 * handle watchpoints yet, those would be handled in
5423 * the emulate_ops.
5424 */
5425 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5426 return r;
5427
9d74191a
TY		 5428 ctxt->interruptibility = 0;
5429 ctxt->have_exception = false;
e0ad0b47 5430 ctxt->exception.vector = -1;
9d74191a 5431 ctxt->perm_ok = false;
bbd9b64e 5432
b51e974f 5433 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5434
9d74191a 5435 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5436
e46479f8 5437 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5438 ++vcpu->stat.insn_emulation;
1d2887e2 5439 if (r != EMULATION_OK) {
4005996e
AK		 5440 if (emulation_type & EMULTYPE_TRAP_UD)
5441 return EMULATE_FAIL;
991eebf9
GN		 5442 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5443 emulation_type))
bbd9b64e 5444 return EMULATE_DONE;
6d77dbfc
GN		 5445 if (emulation_type & EMULTYPE_SKIP)
5446 return EMULATE_FAIL;
5447 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5448 }
5449 }
5450
ba8afb6b 5451 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5452 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5453 if (ctxt->eflags & X86_EFLAGS_RF)
5454 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5455 return EMULATE_DONE;
5456 }
5457
1cb3f3ae
XG		 5458 if (retry_instruction(ctxt, cr2, emulation_type))
5459 return EMULATE_DONE;
5460
7ae441ea 5461 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5462 changes registers values during IO operation */
7ae441ea
GN		 5463 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5464 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5465 emulator_invalidate_register_cache(ctxt);
7ae441ea 5466 }
4d2179e1 5467
5cd21917 5468restart:
9d74191a 5469 r = x86_emulate_insn(ctxt);
bbd9b64e 5470
775fde86
JR		 5471 if (r == EMULATION_INTERCEPTED)
5472 return EMULATE_DONE;
5473
d2ddd1c4 5474 if (r == EMULATION_FAILED) {
991eebf9
GN		 5475 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5476 emulation_type))
c3cd7ffa
GN		 5477 return EMULATE_DONE;
5478
6d77dbfc 5479 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5480 }
5481
9d74191a 5482 if (ctxt->have_exception) {
d2ddd1c4 5483 r = EMULATE_DONE;
ef54bcfe
PB		 5484 if (inject_emulated_exception(vcpu))
5485 return r;
d2ddd1c4 5486 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5487 if (!vcpu->arch.pio.in) {
5488 /* FIXME: return into emulator if single-stepping. */
3457e419 5489 vcpu->arch.pio.count = 0;
0912c977 5490 } else {
7ae441ea 5491 writeback = false;
716d51ab
GN		 5492 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5493 }
ac0a48c3 5494 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5495 } else if (vcpu->mmio_needed) {
5496 if (!vcpu->mmio_is_write)
5497 writeback = false;
ac0a48c3 5498 r = EMULATE_USER_EXIT;
716d51ab 5499 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5500 } else if (r == EMULATION_RESTART)
5cd21917 5501 goto restart;
d2ddd1c4
GN		 5502 else
5503 r = EMULATE_DONE;
f850e2e6 5504
7ae441ea 5505 if (writeback) {
6addfc42 5506 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5507 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5508 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5509 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5510 if (r == EMULATE_DONE)
6addfc42 5511 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5512 if (!ctxt->have_exception ||
5513 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5514 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5515
5516 /*
5517 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5518 * do nothing, and it will be requested again as soon as
5519 * the shadow expires. But we still need to check here,
5520 * because POPF has no interrupt shadow.
5521 */
5522 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5523 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5524 } else
5525 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5526
5527 return r;
de7d789a 5528}
51d8b661 5529EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5530
cf8f70bf 5531int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5532{
cf8f70bf 5533 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5534 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5535 size, port, &val, 1);
cf8f70bf 5536 /* do not return to emulator after return from userspace */
7972995b 5537 vcpu->arch.pio.count = 0;
de7d789a
CO		 5538 return ret;
5539}
cf8f70bf 5540EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5541
8cfdc000
ZA		 5542static void tsc_bad(void *info)
5543{
0a3aee0d 5544 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5545}
5546
5547static void tsc_khz_changed(void *data)
c8076604 5548{
8cfdc000
ZA		 5549 struct cpufreq_freqs *freq = data;
5550 unsigned long khz = 0;
5551
5552 if (data)
5553 khz = freq->new;
5554 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5555 khz = cpufreq_quick_get(raw_smp_processor_id());
5556 if (!khz)
5557 khz = tsc_khz;
0a3aee0d 5558 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5559}
5560
c8076604
GH		 5561static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5562 void *data)
5563{
5564 struct cpufreq_freqs *freq = data;
5565 struct kvm *kvm;
5566 struct kvm_vcpu *vcpu;
5567 int i, send_ipi = 0;
5568
8cfdc000
ZA		 5569 /*
5570 * We allow guests to temporarily run on slowing clocks,
5571 * provided we notify them after, or to run on accelerating
5572 * clocks, provided we notify them before. Thus time never
5573 * goes backwards.
5574 *
5575 * However, we have a problem. We can't atomically update
5576 * the frequency of a given CPU from this function; it is
5577 * merely a notifier, which can be called from any CPU.
5578 * Changing the TSC frequency at arbitrary points in time
5579 * requires a recomputation of local variables related to
5580 * the TSC for each VCPU. We must flag these local variables
5581 * to be updated and be sure the update takes place with the
5582 * new frequency before any guests proceed.
5583 *
5584 * Unfortunately, the combination of hotplug CPU and frequency
5585 * change creates an intractable locking scenario; the order
5586 * of when these callouts happen is undefined with respect to
5587 * CPU hotplug, and they can race with each other. As such,
5588 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5589 * undefined; you can actually have a CPU frequency change take
5590 * place in between the computation of X and the setting of the
5591 * variable. To protect against this problem, all updates of
5592 * the per_cpu tsc_khz variable are done in an interrupt
5593 * protected IPI, and all callers wishing to update the value
5594 * must wait for a synchronous IPI to complete (which is trivial
5595 * if the caller is on the CPU already). This establishes the
5596 * necessary total order on variable updates.
5597 *
5598 * Note that because a guest time update may take place
5599 * anytime after the setting of the VCPU's request bit, the
5600 * correct TSC value must be set before the request. However,
5601 * to ensure the update actually makes it to any guest which
5602 * starts running in hardware virtualization between the set
5603 * and the acquisition of the spinlock, we must also ping the
5604 * CPU after setting the request bit.
5605 *
5606 */
5607
c8076604
GH		 5608 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5609 return 0;
5610 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5611 return 0;
8cfdc000
ZA		 5612
5613 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5614
2f303b74 5615 spin_lock(&kvm_lock);
c8076604 5616 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5617 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5618 if (vcpu->cpu != freq->cpu)
5619 continue;
c285545f 5620 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5621 if (vcpu->cpu != smp_processor_id())
8cfdc000 5622 send_ipi = 1;
c8076604
GH		 5623 }
5624 }
2f303b74 5625 spin_unlock(&kvm_lock);
c8076604
GH		 5626
5627 if (freq->old < freq->new && send_ipi) {
5628 /*
5629 * We upscale the frequency. Must make the guest
5630 * doesn't see old kvmclock values while running with
5631 * the new frequency, otherwise we risk the guest sees
5632 * time go backwards.
5633 *
5634 * In case we update the frequency for another cpu
5635 * (which might be in guest context) send an interrupt
5636 * to kick the cpu out of guest context. Next time
5637 * guest context is entered kvmclock will be updated,
5638 * so the guest will not see stale values.
5639 */
8cfdc000 5640 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5641 }
5642 return 0;
5643}
5644
5645static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5646 .notifier_call = kvmclock_cpufreq_notifier
5647};
5648
5649static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5650 unsigned long action, void *hcpu)
5651{
5652 unsigned int cpu = (unsigned long)hcpu;
5653
5654 switch (action) {
5655 case CPU_ONLINE:
5656 case CPU_DOWN_FAILED:
5657 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5658 break;
5659 case CPU_DOWN_PREPARE:
5660 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5661 break;
5662 }
5663 return NOTIFY_OK;
5664}
5665
5666static struct notifier_block kvmclock_cpu_notifier_block = {
5667 .notifier_call = kvmclock_cpu_notifier,
5668 .priority = -INT_MAX
c8076604
GH		 5669};
5670
b820cc0c
ZA		 5671static void kvm_timer_init(void)
5672{
5673 int cpu;
5674
c285545f 5675 max_tsc_khz = tsc_khz;
460dd42e
SB		 5676
5677 cpu_notifier_register_begin();
b820cc0c 5678 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5679#ifdef CONFIG_CPU_FREQ
5680 struct cpufreq_policy policy;
5681 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5682 cpu = get_cpu();
5683 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5684 if (policy.cpuinfo.max_freq)
5685 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5686 put_cpu();
c285545f 5687#endif
b820cc0c
ZA		 5688 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5689 CPUFREQ_TRANSITION_NOTIFIER);
5690 }
c285545f 5691 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5692 for_each_online_cpu(cpu)
5693 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5694
5695 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5696 cpu_notifier_register_done();
5697
b820cc0c
ZA		 5698}
5699
ff9d07a0
ZY		 5700static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5701
f5132b01 5702int kvm_is_in_guest(void)
ff9d07a0 5703{
086c9855 5704 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5705}
5706
5707static int kvm_is_user_mode(void)
5708{
5709 int user_mode = 3;
dcf46b94 5710
086c9855
AS		 5711 if (__this_cpu_read(current_vcpu))
5712 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5713
ff9d07a0
ZY		 5714 return user_mode != 0;
5715}
5716
5717static unsigned long kvm_get_guest_ip(void)
5718{
5719 unsigned long ip = 0;
dcf46b94 5720
086c9855
AS		 5721 if (__this_cpu_read(current_vcpu))
5722 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5723
ff9d07a0
ZY		 5724 return ip;
5725}
5726
5727static struct perf_guest_info_callbacks kvm_guest_cbs = {
5728 .is_in_guest = kvm_is_in_guest,
5729 .is_user_mode = kvm_is_user_mode,
5730 .get_guest_ip = kvm_get_guest_ip,
5731};
5732
5733void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5734{
086c9855 5735 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5736}
5737EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5738
5739void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5740{
086c9855 5741 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5742}
5743EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5744
ce88decf
XG		 5745static void kvm_set_mmio_spte_mask(void)
5746{
5747 u64 mask;
5748 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5749
5750 /*
5751 * Set the reserved bits and the present bit of an paging-structure
5752 * entry to generate page fault with PFER.RSV = 1.
5753 */
885032b9 5754 /* Mask the reserved physical address bits. */
d1431483 5755 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5756
5757 /* Bit 62 is always reserved for 32bit host. */
5758 mask |= 0x3ull << 62;
5759
5760 /* Set the present bit. */
ce88decf
XG		 5761 mask |= 1ull;
5762
5763#ifdef CONFIG_X86_64
5764 /*
5765 * If reserved bit is not supported, clear the present bit to disable
5766 * mmio page fault.
5767 */
5768 if (maxphyaddr == 52)
5769 mask &= ~1ull;
5770#endif
5771
5772 kvm_mmu_set_mmio_spte_mask(mask);
5773}
5774
16e8d74d
MT		 5775#ifdef CONFIG_X86_64
5776static void pvclock_gtod_update_fn(struct work_struct *work)
5777{
d828199e
MT		 5778 struct kvm *kvm;
5779
5780 struct kvm_vcpu *vcpu;
5781 int i;
5782
2f303b74 5783 spin_lock(&kvm_lock);
d828199e
MT		 5784 list_for_each_entry(kvm, &vm_list, vm_list)
5785 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5786 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5787 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5788 spin_unlock(&kvm_lock);
16e8d74d
MT		 5789}
5790
5791static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5792
5793/*
5794 * Notification about pvclock gtod data update.
5795 */
5796static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5797 void *priv)
5798{
5799 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5800 struct timekeeper *tk = priv;
5801
5802 update_pvclock_gtod(tk);
5803
5804 /* disable master clock if host does not trust, or does not
5805 * use, TSC clocksource
5806 */
5807 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5808 atomic_read(&kvm_guest_has_master_clock) != 0)
5809 queue_work(system_long_wq, &pvclock_gtod_work);
5810
5811 return 0;
5812}
5813
5814static struct notifier_block pvclock_gtod_notifier = {
5815 .notifier_call = pvclock_gtod_notify,
5816};
5817#endif
5818
f8c16bba 5819int kvm_arch_init(void *opaque)
043405e1 5820{
b820cc0c 5821 int r;
6b61edf7 5822 struct kvm_x86_ops *ops = opaque;
f8c16bba 5823
f8c16bba
ZX		 5824 if (kvm_x86_ops) {
5825 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5826 r = -EEXIST;
5827 goto out;
f8c16bba
ZX		 5828 }
5829
5830 if (!ops->cpu_has_kvm_support()) {
5831 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5832 r = -EOPNOTSUPP;
5833 goto out;
f8c16bba
ZX		 5834 }
5835 if (ops->disabled_by_bios()) {
5836 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5837 r = -EOPNOTSUPP;
5838 goto out;
f8c16bba
ZX		 5839 }
5840
013f6a5d
MT		 5841 r = -ENOMEM;
5842 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5843 if (!shared_msrs) {
5844 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5845 goto out;
5846 }
5847
97db56ce
AK		 5848 r = kvm_mmu_module_init();
5849 if (r)
013f6a5d 5850 goto out_free_percpu;
97db56ce 5851
ce88decf 5852 kvm_set_mmio_spte_mask();
97db56ce 5853
f8c16bba 5854 kvm_x86_ops = ops;
920c8377 5855
7b52345e 5856 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5857 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5858
b820cc0c 5859 kvm_timer_init();
c8076604 5860
ff9d07a0
ZY		 5861 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5862
2acf923e
DC		 5863 if (cpu_has_xsave)
5864 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5865
c5cc421b 5866 kvm_lapic_init();
16e8d74d
MT		 5867#ifdef CONFIG_X86_64
5868 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5869#endif
5870
f8c16bba 5871 return 0;
56c6d28a 5872
013f6a5d
MT		 5873out_free_percpu:
5874 free_percpu(shared_msrs);
56c6d28a 5875out:
56c6d28a 5876 return r;
043405e1 5877}
8776e519 5878
f8c16bba
ZX		 5879void kvm_arch_exit(void)
5880{
ff9d07a0
ZY		 5881 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5882
888d256e
JK		 5883 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5884 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5885 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5886 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5887#ifdef CONFIG_X86_64
5888 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5889#endif
f8c16bba 5890 kvm_x86_ops = NULL;
56c6d28a 5891 kvm_mmu_module_exit();
013f6a5d 5892 free_percpu(shared_msrs);
56c6d28a 5893}
f8c16bba 5894
5cb56059 5895int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5896{
5897 ++vcpu->stat.halt_exits;
5898 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5899 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5900 return 1;
5901 } else {
5902 vcpu->run->exit_reason = KVM_EXIT_HLT;
5903 return 0;
5904 }
5905}
5cb56059
JS		 5906EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5907
5908int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5909{
5910 kvm_x86_ops->skip_emulated_instruction(vcpu);
5911 return kvm_vcpu_halt(vcpu);
5912}
8776e519
HB		 5913EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5914
55cd8e5a
GN		 5915int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5916{
5917 u64 param, ingpa, outgpa, ret;
5918 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5919 bool fast, longmode;
55cd8e5a
GN		 5920
5921 /*
5922 * hypercall generates UD from non zero cpl and real mode
5923 * per HYPER-V spec
5924 */
3eeb3288 5925 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5926 kvm_queue_exception(vcpu, UD_VECTOR);
5927 return 0;
5928 }
5929
a449c7aa 5930 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5931
5932 if (!longmode) {
ccd46936
GN		 5933 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5934 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5935 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5936 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5937 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5938 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5939 }
5940#ifdef CONFIG_X86_64
5941 else {
5942 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5943 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5944 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5945 }
5946#endif
5947
5948 code = param & 0xffff;
5949 fast = (param >> 16) & 0x1;
5950 rep_cnt = (param >> 32) & 0xfff;
5951 rep_idx = (param >> 48) & 0xfff;
5952
5953 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5954
c25bc163
GN		 5955 switch (code) {
5956 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5957 kvm_vcpu_on_spin(vcpu);
5958 break;
5959 default:
5960 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5961 break;
5962 }
55cd8e5a
GN		 5963
5964 ret = res | (((u64)rep_done & 0xfff) << 32);
5965 if (longmode) {
5966 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5967 } else {
5968 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5969 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5970 }
5971
5972 return 1;
5973}
5974
6aef266c
SV		 5975/*
5976 * kvm_pv_kick_cpu_op: Kick a vcpu.
5977 *
5978 * @apicid - apicid of vcpu to be kicked.
5979 */
5980static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5981{
24d2166b 5982 struct kvm_lapic_irq lapic_irq;
6aef266c 5983
24d2166b
R		 5984 lapic_irq.shorthand = 0;
5985 lapic_irq.dest_mode = 0;
5986 lapic_irq.dest_id = apicid;
6aef266c 5987
24d2166b 5988 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5989 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5990}
5991
8776e519
HB		 5992int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5993{
5994 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5995 int op_64_bit, r = 1;
8776e519 5996
5cb56059
JS		 5997 kvm_x86_ops->skip_emulated_instruction(vcpu);
5998
55cd8e5a
GN		 5999 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6000 return kvm_hv_hypercall(vcpu);
6001
5fdbf976
MT		 6002 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6003 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6004 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6005 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6006 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6007
229456fc 6008 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6009
a449c7aa
NA		 6010 op_64_bit = is_64_bit_mode(vcpu);
6011 if (!op_64_bit) {
8776e519
HB		 6012 nr &= 0xFFFFFFFF;
6013 a0 &= 0xFFFFFFFF;
6014 a1 &= 0xFFFFFFFF;
6015 a2 &= 0xFFFFFFFF;
6016 a3 &= 0xFFFFFFFF;
6017 }
6018
07708c4a
JK		 6019 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6020 ret = -KVM_EPERM;
6021 goto out;
6022 }
6023
8776e519 6024 switch (nr) {
b93463aa
AK		 6025 case KVM_HC_VAPIC_POLL_IRQ:
6026 ret = 0;
6027 break;
6aef266c
SV		 6028 case KVM_HC_KICK_CPU:
6029 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6030 ret = 0;
6031 break;
8776e519
HB		 6032 default:
6033 ret = -KVM_ENOSYS;
6034 break;
6035 }
07708c4a 6036out:
a449c7aa
NA		 6037 if (!op_64_bit)
6038 ret = (u32)ret;
5fdbf976 6039 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6040 ++vcpu->stat.hypercalls;
2f333bcb 6041 return r;
8776e519
HB		 6042}
6043EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6044
b6785def 6045static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6046{
d6aa1000 6047 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6048 char instruction[3];
5fdbf976 6049 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6050
8776e519 6051 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6052
9d74191a 6053 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6054}
6055
b6c7a5dc
HB		 6056/*
6057 * Check if userspace requested an interrupt window, and that the
6058 * interrupt window is open.
6059 *
6060 * No need to exit to userspace if we already have an interrupt queued.
6061 */
851ba692 6062static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6063{
8061823a 6064 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 6065 vcpu->run->request_interrupt_window &&
5df56646 6066 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 6067}
6068
851ba692 6069static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6070{
851ba692
AK		 6071 struct kvm_run *kvm_run = vcpu->run;
6072
91586a3b 6073 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 6074 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6075 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 6076 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 6077 kvm_run->ready_for_interrupt_injection = 1;
4531220b 6078 else
b6c7a5dc 6079 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 6080 kvm_arch_interrupt_allowed(vcpu) &&
6081 !kvm_cpu_has_interrupt(vcpu) &&
6082 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 6083}
6084
95ba8273
GN		 6085static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6086{
6087 int max_irr, tpr;
6088
6089 if (!kvm_x86_ops->update_cr8_intercept)
6090 return;
6091
88c808fd
AK		 6092 if (!vcpu->arch.apic)
6093 return;
6094
8db3baa2
GN		 6095 if (!vcpu->arch.apic->vapic_addr)
6096 max_irr = kvm_lapic_find_highest_irr(vcpu);
6097 else
6098 max_irr = -1;
95ba8273
GN		 6099
6100 if (max_irr != -1)
6101 max_irr >>= 4;
6102
6103 tpr = kvm_lapic_get_cr8(vcpu);
6104
6105 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6106}
6107
b6b8a145 6108static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6109{
b6b8a145
JK		 6110 int r;
6111
95ba8273 6112 /* try to reinject previous events if any */
b59bb7bd 6113 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6114 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6115 vcpu->arch.exception.has_error_code,
6116 vcpu->arch.exception.error_code);
d6e8c854
NA		 6117
6118 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6119 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6120 X86_EFLAGS_RF);
6121
6bdf0662
NA		 6122 if (vcpu->arch.exception.nr == DB_VECTOR &&
6123 (vcpu->arch.dr7 & DR7_GD)) {
6124 vcpu->arch.dr7 &= ~DR7_GD;
6125 kvm_update_dr7(vcpu);
6126 }
6127
b59bb7bd
GN		 6128 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6129 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6130 vcpu->arch.exception.error_code,
6131 vcpu->arch.exception.reinject);
b6b8a145 6132 return 0;
b59bb7bd
GN		 6133 }
6134
95ba8273
GN		 6135 if (vcpu->arch.nmi_injected) {
6136 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6137 return 0;
95ba8273
GN		 6138 }
6139
6140 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6141 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6142 return 0;
6143 }
6144
6145 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6146 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6147 if (r != 0)
6148 return r;
95ba8273
GN		 6149 }
6150
6151 /* try to inject new event if pending */
6152 if (vcpu->arch.nmi_pending) {
6153 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6154 --vcpu->arch.nmi_pending;
95ba8273
GN		 6155 vcpu->arch.nmi_injected = true;
6156 kvm_x86_ops->set_nmi(vcpu);
6157 }
c7c9c56c 6158 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6159 /*
6160 * Because interrupts can be injected asynchronously, we are
6161 * calling check_nested_events again here to avoid a race condition.
6162 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6163 * proposal and current concerns. Perhaps we should be setting
6164 * KVM_REQ_EVENT only on certain events and not unconditionally?
6165 */
6166 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6167 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6168 if (r != 0)
6169 return r;
6170 }
95ba8273 6171 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6172 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6173 false);
6174 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6175 }
6176 }
b6b8a145 6177 return 0;
95ba8273
GN		 6178}
6179
7460fb4a
AK		 6180static void process_nmi(struct kvm_vcpu *vcpu)
6181{
6182 unsigned limit = 2;
6183
6184 /*
6185 * x86 is limited to one NMI running, and one NMI pending after it.
6186 * If an NMI is already in progress, limit further NMIs to just one.
6187 * Otherwise, allow two (and we'll inject the first one immediately).
6188 */
6189 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6190 limit = 1;
6191
6192 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6193 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6194 kvm_make_request(KVM_REQ_EVENT, vcpu);
6195}
6196
3d81bc7e 6197static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6198{
6199 u64 eoi_exit_bitmap[4];
cf9e65b7 6200 u32 tmr[8];
c7c9c56c 6201
3d81bc7e
YZ		 6202 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6203 return;
c7c9c56c
YZ		 6204
6205 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6206 memset(tmr, 0, 32);
c7c9c56c 6207
cf9e65b7 6208 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6209 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6210 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6211}
6212
a70656b6
RK		 6213static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6214{
6215 ++vcpu->stat.tlb_flush;
6216 kvm_x86_ops->tlb_flush(vcpu);
6217}
6218
4256f43f
TC		 6219void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6220{
c24ae0dc
TC		 6221 struct page *page = NULL;
6222
f439ed27
PB		 6223 if (!irqchip_in_kernel(vcpu->kvm))
6224 return;
6225
4256f43f
TC		 6226 if (!kvm_x86_ops->set_apic_access_page_addr)
6227 return;
6228
c24ae0dc
TC		 6229 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6230 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6231
6232 /*
6233 * Do not pin apic access page in memory, the MMU notifier
6234 * will call us again if it is migrated or swapped out.
6235 */
6236 put_page(page);
4256f43f
TC		 6237}
6238EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6239
fe71557a
TC		 6240void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6241 unsigned long address)
6242{
c24ae0dc
TC		 6243 /*
6244 * The physical address of apic access page is stored in the VMCS.
6245 * Update it when it becomes invalid.
6246 */
6247 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6248 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6249}
6250
9357d939 6251/*
362c698f 6252 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6253 * exiting to the userspace. Otherwise, the value will be returned to the
6254 * userspace.
6255 */
851ba692 6256static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6257{
6258 int r;
6a8b1d13 6259 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6260 vcpu->run->request_interrupt_window;
730dca42 6261 bool req_immediate_exit = false;
b6c7a5dc 6262
3e007509 6263 if (vcpu->requests) {
a8eeb04a 6264 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6265 kvm_mmu_unload(vcpu);
a8eeb04a 6266 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6267 __kvm_migrate_timers(vcpu);
d828199e
MT		 6268 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6269 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6270 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6271 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6272 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6273 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6274 if (unlikely(r))
6275 goto out;
6276 }
a8eeb04a 6277 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6278 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6279 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6280 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6281 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6282 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6283 r = 0;
6284 goto out;
6285 }
a8eeb04a 6286 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6287 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6288 r = 0;
6289 goto out;
6290 }
a8eeb04a 6291 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6292 vcpu->fpu_active = 0;
6293 kvm_x86_ops->fpu_deactivate(vcpu);
6294 }
af585b92
GN		 6295 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6296 /* Page is swapped out. Do synthetic halt */
6297 vcpu->arch.apf.halted = true;
6298 r = 1;
6299 goto out;
6300 }
c9aaa895
GC		 6301 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6302 record_steal_time(vcpu);
7460fb4a
AK		 6303 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6304 process_nmi(vcpu);
f5132b01
GN		 6305 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6306 kvm_handle_pmu_event(vcpu);
6307 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6308 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6309 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6310 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6311 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6312 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6313 }
b93463aa 6314
b463a6f7 6315 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6316 kvm_apic_accept_events(vcpu);
6317 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6318 r = 1;
6319 goto out;
6320 }
6321
b6b8a145
JK		 6322 if (inject_pending_event(vcpu, req_int_win) != 0)
6323 req_immediate_exit = true;
b463a6f7 6324 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6325 else if (vcpu->arch.nmi_pending)
c9a7953f 6326 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6327 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6328 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6329
6330 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6331 /*
6332 * Update architecture specific hints for APIC
6333 * virtual interrupt delivery.
6334 */
6335 if (kvm_x86_ops->hwapic_irr_update)
6336 kvm_x86_ops->hwapic_irr_update(vcpu,
6337 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6338 update_cr8_intercept(vcpu);
6339 kvm_lapic_sync_to_vapic(vcpu);
6340 }
6341 }
6342
d8368af8
AK		 6343 r = kvm_mmu_reload(vcpu);
6344 if (unlikely(r)) {
d905c069 6345 goto cancel_injection;
d8368af8
AK		 6346 }
6347
b6c7a5dc
HB		 6348 preempt_disable();
6349
6350 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6351 if (vcpu->fpu_active)
6352 kvm_load_guest_fpu(vcpu);
2acf923e 6353 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6354
6b7e2d09
XG		 6355 vcpu->mode = IN_GUEST_MODE;
6356
01b71917
MT		 6357 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6358
6b7e2d09
XG		 6359 /* We should set ->mode before check ->requests,
6360 * see the comment in make_all_cpus_request.
6361 */
01b71917 6362 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6363
d94e1dc9 6364 local_irq_disable();
32f88400 6365
6b7e2d09 6366 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6367 || need_resched() || signal_pending(current)) {
6b7e2d09 6368 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6369 smp_wmb();
6c142801
AK		 6370 local_irq_enable();
6371 preempt_enable();
01b71917 6372 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6373 r = 1;
d905c069 6374 goto cancel_injection;
6c142801
AK		 6375 }
6376
d6185f20
NHE		 6377 if (req_immediate_exit)
6378 smp_send_reschedule(vcpu->cpu);
6379
ccf73aaf 6380 __kvm_guest_enter();
b6c7a5dc 6381
42dbaa5a 6382 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6383 set_debugreg(0, 7);
6384 set_debugreg(vcpu->arch.eff_db[0], 0);
6385 set_debugreg(vcpu->arch.eff_db[1], 1);
6386 set_debugreg(vcpu->arch.eff_db[2], 2);
6387 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6388 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6389 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6390 }
b6c7a5dc 6391
229456fc 6392 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6393 wait_lapic_expire(vcpu);
851ba692 6394 kvm_x86_ops->run(vcpu);
b6c7a5dc 6395
c77fb5fe
PB		 6396 /*
6397 * Do this here before restoring debug registers on the host. And
6398 * since we do this before handling the vmexit, a DR access vmexit
6399 * can (a) read the correct value of the debug registers, (b) set
6400 * KVM_DEBUGREG_WONT_EXIT again.
6401 */
6402 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6403 int i;
6404
6405 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6406 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6407 for (i = 0; i < KVM_NR_DB_REGS; i++)
6408 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6409 }
6410
24f1e32c
FW		 6411 /*
6412 * If the guest has used debug registers, at least dr7
6413 * will be disabled while returning to the host.
6414 * If we don't have active breakpoints in the host, we don't
6415 * care about the messed up debug address registers. But if
6416 * we have some of them active, restore the old state.
6417 */
59d8eb53 6418 if (hw_breakpoint_active())
24f1e32c 6419 hw_breakpoint_restore();
42dbaa5a 6420
886b470c
MT		 6421 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6422 native_read_tsc());
1d5f066e 6423
6b7e2d09 6424 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6425 smp_wmb();
a547c6db
YZ		 6426
6427 /* Interrupt is enabled by handle_external_intr() */
6428 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6429
6430 ++vcpu->stat.exits;
6431
6432 /*
6433 * We must have an instruction between local_irq_enable() and
6434 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6435 * the interrupt shadow. The stat.exits increment will do nicely.
6436 * But we need to prevent reordering, hence this barrier():
6437 */
6438 barrier();
6439
6440 kvm_guest_exit();
6441
6442 preempt_enable();
6443
f656ce01 6444 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6445
b6c7a5dc
HB		 6446 /*
6447 * Profile KVM exit RIPs:
6448 */
6449 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6450 unsigned long rip = kvm_rip_read(vcpu);
6451 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6452 }
6453
cc578287
ZA		 6454 if (unlikely(vcpu->arch.tsc_always_catchup))
6455 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6456
5cfb1d5a
MT		 6457 if (vcpu->arch.apic_attention)
6458 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6459
851ba692 6460 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6461 return r;
6462
6463cancel_injection:
6464 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6465 if (unlikely(vcpu->arch.apic_attention))
6466 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6467out:
6468 return r;
6469}
b6c7a5dc 6470
362c698f
PB		 6471static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6472{
9c8fd1ba
PB		 6473 if (!kvm_arch_vcpu_runnable(vcpu)) {
6474 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6475 kvm_vcpu_block(vcpu);
6476 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6477 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6478 return 1;
6479 }
362c698f
PB		 6480
6481 kvm_apic_accept_events(vcpu);
6482 switch(vcpu->arch.mp_state) {
6483 case KVM_MP_STATE_HALTED:
6484 vcpu->arch.pv.pv_unhalted = false;
6485 vcpu->arch.mp_state =
6486 KVM_MP_STATE_RUNNABLE;
6487 case KVM_MP_STATE_RUNNABLE:
6488 vcpu->arch.apf.halted = false;
6489 break;
6490 case KVM_MP_STATE_INIT_RECEIVED:
6491 break;
6492 default:
6493 return -EINTR;
6494 break;
6495 }
6496 return 1;
6497}
09cec754 6498
362c698f 6499static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6500{
6501 int r;
f656ce01 6502 struct kvm *kvm = vcpu->kvm;
d7690175 6503
f656ce01 6504 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6505
362c698f 6506 for (;;) {
af585b92
GN		 6507 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6508 !vcpu->arch.apf.halted)
851ba692 6509 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6510 else
6511 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6512 if (r <= 0)
6513 break;
6514
6515 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6516 if (kvm_cpu_has_pending_timer(vcpu))
6517 kvm_inject_pending_timer_irqs(vcpu);
6518
851ba692 6519 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6520 r = -EINTR;
851ba692 6521 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6522 ++vcpu->stat.request_irq_exits;
362c698f 6523 break;
09cec754 6524 }
af585b92
GN		 6525
6526 kvm_check_async_pf_completion(vcpu);
6527
09cec754
GN		 6528 if (signal_pending(current)) {
6529 r = -EINTR;
851ba692 6530 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6531 ++vcpu->stat.signal_exits;
362c698f 6532 break;
09cec754
GN		 6533 }
6534 if (need_resched()) {
f656ce01 6535 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6536 cond_resched();
f656ce01 6537 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6538 }
b6c7a5dc
HB		 6539 }
6540
f656ce01 6541 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6542
6543 return r;
6544}
6545
716d51ab
GN		 6546static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6547{
6548 int r;
6549 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6550 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6551 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6552 if (r != EMULATE_DONE)
6553 return 0;
6554 return 1;
6555}
6556
6557static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6558{
6559 BUG_ON(!vcpu->arch.pio.count);
6560
6561 return complete_emulated_io(vcpu);
6562}
6563
f78146b0
AK		 6564/*
6565 * Implements the following, as a state machine:
6566 *
6567 * read:
6568 * for each fragment
87da7e66
XG		 6569 * for each mmio piece in the fragment
6570 * write gpa, len
6571 * exit
6572 * copy data
f78146b0
AK		 6573 * execute insn
6574 *
6575 * write:
6576 * for each fragment
87da7e66
XG		 6577 * for each mmio piece in the fragment
6578 * write gpa, len
6579 * copy data
6580 * exit
f78146b0 6581 */
716d51ab 6582static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6583{
6584 struct kvm_run *run = vcpu->run;
f78146b0 6585 struct kvm_mmio_fragment *frag;
87da7e66 6586 unsigned len;
5287f194 6587
716d51ab 6588 BUG_ON(!vcpu->mmio_needed);
5287f194 6589
716d51ab 6590 /* Complete previous fragment */
87da7e66
XG		 6591 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6592 len = min(8u, frag->len);
716d51ab 6593 if (!vcpu->mmio_is_write)
87da7e66
XG		 6594 memcpy(frag->data, run->mmio.data, len);
6595
6596 if (frag->len <= 8) {
6597 /* Switch to the next fragment. */
6598 frag++;
6599 vcpu->mmio_cur_fragment++;
6600 } else {
6601 /* Go forward to the next mmio piece. */
6602 frag->data += len;
6603 frag->gpa += len;
6604 frag->len -= len;
6605 }
6606
a08d3b3b 6607 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6608 vcpu->mmio_needed = 0;
0912c977
PB		 6609
6610 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6611 if (vcpu->mmio_is_write)
716d51ab
GN		 6612 return 1;
6613 vcpu->mmio_read_completed = 1;
6614 return complete_emulated_io(vcpu);
6615 }
87da7e66 6616
716d51ab
GN		 6617 run->exit_reason = KVM_EXIT_MMIO;
6618 run->mmio.phys_addr = frag->gpa;
6619 if (vcpu->mmio_is_write)
87da7e66
XG		 6620 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6621 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6622 run->mmio.is_write = vcpu->mmio_is_write;
6623 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6624 return 0;
5287f194
AK		 6625}
6626
716d51ab 6627
b6c7a5dc
HB		 6628int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6629{
6630 int r;
6631 sigset_t sigsaved;
6632
e5c30142
AK		 6633 if (!tsk_used_math(current) && init_fpu(current))
6634 return -ENOMEM;
6635
ac9f6dc0
AK		 6636 if (vcpu->sigset_active)
6637 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6638
a4535290 6639 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6640 kvm_vcpu_block(vcpu);
66450a21 6641 kvm_apic_accept_events(vcpu);
d7690175 6642 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6643 r = -EAGAIN;
6644 goto out;
b6c7a5dc
HB		 6645 }
6646
b6c7a5dc 6647 /* re-sync apic's tpr */
eea1cff9
AP		 6648 if (!irqchip_in_kernel(vcpu->kvm)) {
6649 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6650 r = -EINVAL;
6651 goto out;
6652 }
6653 }
b6c7a5dc 6654
716d51ab
GN		 6655 if (unlikely(vcpu->arch.complete_userspace_io)) {
6656 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6657 vcpu->arch.complete_userspace_io = NULL;
6658 r = cui(vcpu);
6659 if (r <= 0)
6660 goto out;
6661 } else
6662 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6663
362c698f 6664 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6665
6666out:
f1d86e46 6667 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6668 if (vcpu->sigset_active)
6669 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6670
b6c7a5dc
HB		 6671 return r;
6672}
6673
6674int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6675{
7ae441ea
GN		 6676 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6677 /*
6678 * We are here if userspace calls get_regs() in the middle of
6679 * instruction emulation. Registers state needs to be copied
4a969980 6680 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6681 * that usually, but some bad designed PV devices (vmware
6682 * backdoor interface) need this to work
6683 */
dd856efa 6684 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6685 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6686 }
5fdbf976
MT		 6687 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6688 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6689 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6690 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6691 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6692 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6693 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6694 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6695#ifdef CONFIG_X86_64
5fdbf976
MT		 6696 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6697 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6698 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6699 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6700 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6701 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6702 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6703 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6704#endif
6705
5fdbf976 6706 regs->rip = kvm_rip_read(vcpu);
91586a3b 6707 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6708
b6c7a5dc
HB		 6709 return 0;
6710}
6711
6712int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6713{
7ae441ea
GN		 6714 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6715 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6716
5fdbf976
MT		 6717 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6718 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6719 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6720 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6721 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6722 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6723 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6724 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6725#ifdef CONFIG_X86_64
5fdbf976
MT		 6726 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6727 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6728 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6729 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6730 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6731 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6732 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6733 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6734#endif
6735
5fdbf976 6736 kvm_rip_write(vcpu, regs->rip);
91586a3b 6737 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6738
b4f14abd
JK		 6739 vcpu->arch.exception.pending = false;
6740
3842d135
AK		 6741 kvm_make_request(KVM_REQ_EVENT, vcpu);
6742
b6c7a5dc
HB		 6743 return 0;
6744}
6745
b6c7a5dc
HB		 6746void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6747{
6748 struct kvm_segment cs;
6749
3e6e0aab 6750 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6751 *db = cs.db;
6752 *l = cs.l;
6753}
6754EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6755
6756int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6757 struct kvm_sregs *sregs)
6758{
89a27f4d 6759 struct desc_ptr dt;
b6c7a5dc 6760
3e6e0aab
GT		 6761 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6762 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6763 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6764 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6765 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6766 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6767
3e6e0aab
GT		 6768 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6769 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6770
6771 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6772 sregs->idt.limit = dt.size;
6773 sregs->idt.base = dt.address;
b6c7a5dc 6774 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6775 sregs->gdt.limit = dt.size;
6776 sregs->gdt.base = dt.address;
b6c7a5dc 6777
4d4ec087 6778 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6779 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6780 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6781 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6782 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6783 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6784 sregs->apic_base = kvm_get_apic_base(vcpu);
6785
923c61bb 6786 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6787
36752c9b 6788 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6789 set_bit(vcpu->arch.interrupt.nr,
6790 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6791
b6c7a5dc
HB		 6792 return 0;
6793}
6794
62d9f0db
MT		 6795int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6796 struct kvm_mp_state *mp_state)
6797{
66450a21 6798 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6799 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6800 vcpu->arch.pv.pv_unhalted)
6801 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6802 else
6803 mp_state->mp_state = vcpu->arch.mp_state;
6804
62d9f0db
MT		 6805 return 0;
6806}
6807
6808int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6809 struct kvm_mp_state *mp_state)
6810{
66450a21
JK		 6811 if (!kvm_vcpu_has_lapic(vcpu) &&
6812 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6813 return -EINVAL;
6814
6815 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6816 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6817 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6818 } else
6819 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6820 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6821 return 0;
6822}
6823
7f3d35fd
KW		 6824int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6825 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6826{
9d74191a 6827 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6828 int ret;
e01c2426 6829
8ec4722d 6830 init_emulate_ctxt(vcpu);
c697518a 6831
7f3d35fd 6832 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6833 has_error_code, error_code);
c697518a 6834
c697518a 6835 if (ret)
19d04437 6836 return EMULATE_FAIL;
37817f29 6837
9d74191a
TY		 6838 kvm_rip_write(vcpu, ctxt->eip);
6839 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6840 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6841 return EMULATE_DONE;
37817f29
IE		 6842}
6843EXPORT_SYMBOL_GPL(kvm_task_switch);
6844
b6c7a5dc
HB		 6845int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6846 struct kvm_sregs *sregs)
6847{
58cb628d 6848 struct msr_data apic_base_msr;
b6c7a5dc 6849 int mmu_reset_needed = 0;
63f42e02 6850 int pending_vec, max_bits, idx;
89a27f4d 6851 struct desc_ptr dt;
b6c7a5dc 6852
6d1068b3
PM		 6853 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6854 return -EINVAL;
6855
89a27f4d
GN		 6856 dt.size = sregs->idt.limit;
6857 dt.address = sregs->idt.base;
b6c7a5dc 6858 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6859 dt.size = sregs->gdt.limit;
6860 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6861 kvm_x86_ops->set_gdt(vcpu, &dt);
6862
ad312c7c 6863 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6864 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6865 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6866 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6867
2d3ad1f4 6868 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6869
f6801dff 6870 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6871 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6872 apic_base_msr.data = sregs->apic_base;
6873 apic_base_msr.host_initiated = true;
6874 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6875
4d4ec087 6876 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6877 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6878 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6879
fc78f519 6880 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6881 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6882 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6883 kvm_update_cpuid(vcpu);
63f42e02
XG		 6884
6885 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6886 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6887 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6888 mmu_reset_needed = 1;
6889 }
63f42e02 6890 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6891
6892 if (mmu_reset_needed)
6893 kvm_mmu_reset_context(vcpu);
6894
a50abc3b 6895 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6896 pending_vec = find_first_bit(
6897 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6898 if (pending_vec < max_bits) {
66fd3f7f 6899 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6900 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6901 }
6902
3e6e0aab
GT		 6903 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6904 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6905 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6906 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6907 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6908 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6909
3e6e0aab
GT		 6910 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6911 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6912
5f0269f5
ME		 6913 update_cr8_intercept(vcpu);
6914
9c3e4aab 6915 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6916 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6917 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6918 !is_protmode(vcpu))
9c3e4aab
MT		 6919 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6920
3842d135
AK		 6921 kvm_make_request(KVM_REQ_EVENT, vcpu);
6922
b6c7a5dc
HB		 6923 return 0;
6924}
6925
d0bfb940
JK		 6926int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6927 struct kvm_guest_debug *dbg)
b6c7a5dc 6928{
355be0b9 6929 unsigned long rflags;
ae675ef0 6930 int i, r;
b6c7a5dc 6931
4f926bf2
JK		 6932 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6933 r = -EBUSY;
6934 if (vcpu->arch.exception.pending)
2122ff5e 6935 goto out;
4f926bf2
JK		 6936 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6937 kvm_queue_exception(vcpu, DB_VECTOR);
6938 else
6939 kvm_queue_exception(vcpu, BP_VECTOR);
6940 }
6941
91586a3b
JK		 6942 /*
6943 * Read rflags as long as potentially injected trace flags are still
6944 * filtered out.
6945 */
6946 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6947
6948 vcpu->guest_debug = dbg->control;
6949 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6950 vcpu->guest_debug = 0;
6951
6952 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6953 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6954 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6955 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6956 } else {
6957 for (i = 0; i < KVM_NR_DB_REGS; i++)
6958 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6959 }
c8639010 6960 kvm_update_dr7(vcpu);
ae675ef0 6961
f92653ee
JK		 6962 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6963 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6964 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6965
91586a3b
JK		 6966 /*
6967 * Trigger an rflags update that will inject or remove the trace
6968 * flags.
6969 */
6970 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6971
c8639010 6972 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6973
4f926bf2 6974 r = 0;
d0bfb940 6975
2122ff5e 6976out:
b6c7a5dc
HB		 6977
6978 return r;
6979}
6980
8b006791
ZX		 6981/*
6982 * Translate a guest virtual address to a guest physical address.
6983 */
6984int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6985 struct kvm_translation *tr)
6986{
6987 unsigned long vaddr = tr->linear_address;
6988 gpa_t gpa;
f656ce01 6989 int idx;
8b006791 6990
f656ce01 6991 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6992 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6993 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6994 tr->physical_address = gpa;
6995 tr->valid = gpa != UNMAPPED_GVA;
6996 tr->writeable = 1;
6997 tr->usermode = 0;
8b006791
ZX		 6998
6999 return 0;
7000}
7001
d0752060
HB		 7002int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7003{
98918833
SY		 7004 struct i387_fxsave_struct *fxsave =
7005 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7006
d0752060
HB		 7007 memcpy(fpu->fpr, fxsave->st_space, 128);
7008 fpu->fcw = fxsave->cwd;
7009 fpu->fsw = fxsave->swd;
7010 fpu->ftwx = fxsave->twd;
7011 fpu->last_opcode = fxsave->fop;
7012 fpu->last_ip = fxsave->rip;
7013 fpu->last_dp = fxsave->rdp;
7014 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7015
d0752060
HB		 7016 return 0;
7017}
7018
7019int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7020{
98918833
SY		 7021 struct i387_fxsave_struct *fxsave =
7022 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7023
d0752060
HB		 7024 memcpy(fxsave->st_space, fpu->fpr, 128);
7025 fxsave->cwd = fpu->fcw;
7026 fxsave->swd = fpu->fsw;
7027 fxsave->twd = fpu->ftwx;
7028 fxsave->fop = fpu->last_opcode;
7029 fxsave->rip = fpu->last_ip;
7030 fxsave->rdp = fpu->last_dp;
7031 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7032
d0752060
HB		 7033 return 0;
7034}
7035
d28bc9dd 7036int fx_init(struct kvm_vcpu *vcpu, bool init_event)
d0752060 7037{
10ab25cd
JK		 7038 int err;
7039
7040 err = fpu_alloc(&vcpu->arch.guest_fpu);
7041 if (err)
7042 return err;
7043
d28bc9dd
NA		 7044 if (!init_event)
7045 fpu_finit(&vcpu->arch.guest_fpu);
7046
df1daba7
PB		 7047 if (cpu_has_xsaves)
7048 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
7049 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7050
2acf923e
DC		 7051 /*
7052 * Ensure guest xcr0 is valid for loading
7053 */
7054 vcpu->arch.xcr0 = XSTATE_FP;
7055
ad312c7c 7056 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 7057
7058 return 0;
d0752060
HB		 7059}
7060EXPORT_SYMBOL_GPL(fx_init);
7061
98918833
SY		 7062static void fx_free(struct kvm_vcpu *vcpu)
7063{
7064 fpu_free(&vcpu->arch.guest_fpu);
7065}
7066
d0752060
HB		 7067void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7068{
2608d7a1 7069 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7070 return;
7071
2acf923e
DC		 7072 /*
7073 * Restore all possible states in the guest,
7074 * and assume host would use all available bits.
7075 * Guest xcr0 would be loaded later.
7076 */
7077 kvm_put_guest_xcr0(vcpu);
d0752060 7078 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7079 __kernel_fpu_begin();
98918833 7080 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 7081 trace_kvm_fpu(1);
d0752060 7082}
d0752060
HB		 7083
7084void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7085{
2acf923e
DC		 7086 kvm_put_guest_xcr0(vcpu);
7087
d0752060
HB		 7088 if (!vcpu->guest_fpu_loaded)
7089 return;
7090
7091 vcpu->guest_fpu_loaded = 0;
98918833 7092 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 7093 __kernel_fpu_end();
f096ed85 7094 ++vcpu->stat.fpu_reload;
a8eeb04a 7095 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 7096 trace_kvm_fpu(0);
d0752060 7097}
e9b11c17
ZX		 7098
7099void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7100{
12f9a48f 7101 kvmclock_reset(vcpu);
7f1ea208 7102
f5f48ee1 7103 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 7104 fx_free(vcpu);
e9b11c17
ZX		 7105 kvm_x86_ops->vcpu_free(vcpu);
7106}
7107
7108struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7109 unsigned int id)
7110{
6755bae8
ZA		 7111 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7112 printk_once(KERN_WARNING
7113 "kvm: SMP vm created on host with unstable TSC; "
7114 "guest TSC will not be reliable\n");
26e5215f
AK		 7115 return kvm_x86_ops->vcpu_create(kvm, id);
7116}
e9b11c17 7117
26e5215f
AK		 7118int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7119{
7120 int r;
e9b11c17 7121
0bed3b56 7122 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 7123 r = vcpu_load(vcpu);
7124 if (r)
7125 return r;
d28bc9dd 7126 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7127 kvm_mmu_setup(vcpu);
e9b11c17 7128 vcpu_put(vcpu);
e9b11c17 7129
26e5215f 7130 return r;
e9b11c17
ZX		 7131}
7132
31928aa5 7133void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7134{
8fe8ab46 7135 struct msr_data msr;
332967a3 7136 struct kvm *kvm = vcpu->kvm;
42897d86 7137
31928aa5
DD		 7138 if (vcpu_load(vcpu))
7139 return;
8fe8ab46
WA		 7140 msr.data = 0x0;
7141 msr.index = MSR_IA32_TSC;
7142 msr.host_initiated = true;
7143 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7144 vcpu_put(vcpu);
7145
332967a3
AJ		 7146 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7147 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7148}
7149
d40ccc62 7150void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7151{
9fc77441 7152 int r;
344d9588
GN		 7153 vcpu->arch.apf.msr_val = 0;
7154
9fc77441
MT		 7155 r = vcpu_load(vcpu);
7156 BUG_ON(r);
e9b11c17
ZX		 7157 kvm_mmu_unload(vcpu);
7158 vcpu_put(vcpu);
7159
98918833 7160 fx_free(vcpu);
e9b11c17
ZX		 7161 kvm_x86_ops->vcpu_free(vcpu);
7162}
7163
d28bc9dd 7164void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7165{
7460fb4a
AK		 7166 atomic_set(&vcpu->arch.nmi_queued, 0);
7167 vcpu->arch.nmi_pending = 0;
448fa4a9 7168 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7169 kvm_clear_interrupt_queue(vcpu);
7170 kvm_clear_exception_queue(vcpu);
448fa4a9 7171
42dbaa5a 7172 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7173 kvm_update_dr0123(vcpu);
6f43ed01 7174 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7175 kvm_update_dr6(vcpu);
42dbaa5a 7176 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7177 kvm_update_dr7(vcpu);
42dbaa5a 7178
1119022c
NA		 7179 vcpu->arch.cr2 = 0;
7180
3842d135 7181 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7182 vcpu->arch.apf.msr_val = 0;
c9aaa895 7183 vcpu->arch.st.msr_val = 0;
3842d135 7184
12f9a48f
GC		 7185 kvmclock_reset(vcpu);
7186
af585b92
GN		 7187 kvm_clear_async_pf_completion_queue(vcpu);
7188 kvm_async_pf_hash_reset(vcpu);
7189 vcpu->arch.apf.halted = false;
3842d135 7190
d28bc9dd
NA		 7191 if (!init_event)
7192 kvm_pmu_reset(vcpu);
f5132b01 7193
66f7b72e
JS		 7194 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7195 vcpu->arch.regs_avail = ~0;
7196 vcpu->arch.regs_dirty = ~0;
7197
d28bc9dd 7198 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7199}
7200
2b4a273b 7201void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7202{
7203 struct kvm_segment cs;
7204
7205 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7206 cs.selector = vector << 8;
7207 cs.base = vector << 12;
7208 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7209 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7210}
7211
13a34e06 7212int kvm_arch_hardware_enable(void)
e9b11c17 7213{
ca84d1a2
ZA		 7214 struct kvm *kvm;
7215 struct kvm_vcpu *vcpu;
7216 int i;
0dd6a6ed
ZA		 7217 int ret;
7218 u64 local_tsc;
7219 u64 max_tsc = 0;
7220 bool stable, backwards_tsc = false;
18863bdd
AK		 7221
7222 kvm_shared_msr_cpu_online();
13a34e06 7223 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7224 if (ret != 0)
7225 return ret;
7226
7227 local_tsc = native_read_tsc();
7228 stable = !check_tsc_unstable();
7229 list_for_each_entry(kvm, &vm_list, vm_list) {
7230 kvm_for_each_vcpu(i, vcpu, kvm) {
7231 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7232 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7233 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7234 backwards_tsc = true;
7235 if (vcpu->arch.last_host_tsc > max_tsc)
7236 max_tsc = vcpu->arch.last_host_tsc;
7237 }
7238 }
7239 }
7240
7241 /*
7242 * Sometimes, even reliable TSCs go backwards. This happens on
7243 * platforms that reset TSC during suspend or hibernate actions, but
7244 * maintain synchronization. We must compensate. Fortunately, we can
7245 * detect that condition here, which happens early in CPU bringup,
7246 * before any KVM threads can be running. Unfortunately, we can't
7247 * bring the TSCs fully up to date with real time, as we aren't yet far
7248 * enough into CPU bringup that we know how much real time has actually
7249 * elapsed; our helper function, get_kernel_ns() will be using boot
7250 * variables that haven't been updated yet.
7251 *
7252 * So we simply find the maximum observed TSC above, then record the
7253 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7254 * the adjustment will be applied. Note that we accumulate
7255 * adjustments, in case multiple suspend cycles happen before some VCPU
7256 * gets a chance to run again. In the event that no KVM threads get a
7257 * chance to run, we will miss the entire elapsed period, as we'll have
7258 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7259 * loose cycle time. This isn't too big a deal, since the loss will be
7260 * uniform across all VCPUs (not to mention the scenario is extremely
7261 * unlikely). It is possible that a second hibernate recovery happens
7262 * much faster than a first, causing the observed TSC here to be
7263 * smaller; this would require additional padding adjustment, which is
7264 * why we set last_host_tsc to the local tsc observed here.
7265 *
7266 * N.B. - this code below runs only on platforms with reliable TSC,
7267 * as that is the only way backwards_tsc is set above. Also note
7268 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7269 * have the same delta_cyc adjustment applied if backwards_tsc
7270 * is detected. Note further, this adjustment is only done once,
7271 * as we reset last_host_tsc on all VCPUs to stop this from being
7272 * called multiple times (one for each physical CPU bringup).
7273 *
4a969980 7274 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7275 * will be compensated by the logic in vcpu_load, which sets the TSC to
7276 * catchup mode. This will catchup all VCPUs to real time, but cannot
7277 * guarantee that they stay in perfect synchronization.
7278 */
7279 if (backwards_tsc) {
7280 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7281 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7282 list_for_each_entry(kvm, &vm_list, vm_list) {
7283 kvm_for_each_vcpu(i, vcpu, kvm) {
7284 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7285 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7286 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7287 }
7288
7289 /*
7290 * We have to disable TSC offset matching.. if you were
7291 * booting a VM while issuing an S4 host suspend....
7292 * you may have some problem. Solving this issue is
7293 * left as an exercise to the reader.
7294 */
7295 kvm->arch.last_tsc_nsec = 0;
7296 kvm->arch.last_tsc_write = 0;
7297 }
7298
7299 }
7300 return 0;
e9b11c17
ZX		 7301}
7302
13a34e06 7303void kvm_arch_hardware_disable(void)
e9b11c17 7304{
13a34e06
RK		 7305 kvm_x86_ops->hardware_disable();
7306 drop_user_return_notifiers();
e9b11c17
ZX		 7307}
7308
7309int kvm_arch_hardware_setup(void)
7310{
9e9c3fe4
NA		 7311 int r;
7312
7313 r = kvm_x86_ops->hardware_setup();
7314 if (r != 0)
7315 return r;
7316
7317 kvm_init_msr_list();
7318 return 0;
e9b11c17
ZX		 7319}
7320
7321void kvm_arch_hardware_unsetup(void)
7322{
7323 kvm_x86_ops->hardware_unsetup();
7324}
7325
7326void kvm_arch_check_processor_compat(void *rtn)
7327{
7328 kvm_x86_ops->check_processor_compatibility(rtn);
7329}
7330
3e515705
AK		 7331bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7332{
7333 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7334}
7335
54e9818f
GN		 7336struct static_key kvm_no_apic_vcpu __read_mostly;
7337
e9b11c17
ZX		 7338int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7339{
7340 struct page *page;
7341 struct kvm *kvm;
7342 int r;
7343
7344 BUG_ON(vcpu->kvm == NULL);
7345 kvm = vcpu->kvm;
7346
6aef266c 7347 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7348 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7349 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7350 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7351 else
a4535290 7352 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7353
7354 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7355 if (!page) {
7356 r = -ENOMEM;
7357 goto fail;
7358 }
ad312c7c 7359 vcpu->arch.pio_data = page_address(page);
e9b11c17 7360
cc578287 7361 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7362
e9b11c17
ZX		 7363 r = kvm_mmu_create(vcpu);
7364 if (r < 0)
7365 goto fail_free_pio_data;
7366
7367 if (irqchip_in_kernel(kvm)) {
7368 r = kvm_create_lapic(vcpu);
7369 if (r < 0)
7370 goto fail_mmu_destroy;
54e9818f
GN		 7371 } else
7372 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7373
890ca9ae
HY		 7374 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7375 GFP_KERNEL);
7376 if (!vcpu->arch.mce_banks) {
7377 r = -ENOMEM;
443c39bc 7378 goto fail_free_lapic;
890ca9ae
HY		 7379 }
7380 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7381
f1797359
WY		 7382 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7383 r = -ENOMEM;
f5f48ee1 7384 goto fail_free_mce_banks;
f1797359 7385 }
f5f48ee1 7386
d28bc9dd 7387 r = fx_init(vcpu, false);
66f7b72e
JS		 7388 if (r)
7389 goto fail_free_wbinvd_dirty_mask;
7390
ba904635 7391 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7392 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7393
7394 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7395 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7396
5a4f55cd
EK		 7397 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7398
af585b92 7399 kvm_async_pf_hash_reset(vcpu);
f5132b01 7400 kvm_pmu_init(vcpu);
af585b92 7401
e9b11c17 7402 return 0;
66f7b72e
JS		 7403fail_free_wbinvd_dirty_mask:
7404 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7405fail_free_mce_banks:
7406 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7407fail_free_lapic:
7408 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7409fail_mmu_destroy:
7410 kvm_mmu_destroy(vcpu);
7411fail_free_pio_data:
ad312c7c 7412 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7413fail:
7414 return r;
7415}
7416
7417void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7418{
f656ce01
MT		 7419 int idx;
7420
f5132b01 7421 kvm_pmu_destroy(vcpu);
36cb93fd 7422 kfree(vcpu->arch.mce_banks);
e9b11c17 7423 kvm_free_lapic(vcpu);
f656ce01 7424 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7425 kvm_mmu_destroy(vcpu);
f656ce01 7426 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7427 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7428 if (!irqchip_in_kernel(vcpu->kvm))
7429 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7430}
d19a9cd2 7431
e790d9ef
RK		 7432void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7433{
ae97a3b8 7434 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7435}
7436
e08b9637 7437int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7438{
e08b9637
CO		 7439 if (type)
7440 return -EINVAL;
7441
6ef768fa 7442 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7443 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7444 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7445 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7446 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7447
5550af4d
SY		 7448 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7449 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7450 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7451 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7452 &kvm->arch.irq_sources_bitmap);
5550af4d 7453
038f8c11 7454 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7455 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7456 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7457
7458 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7459
7e44e449 7460 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7461 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7462
d89f5eff 7463 return 0;
d19a9cd2
ZX		 7464}
7465
7466static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7467{
9fc77441
MT		 7468 int r;
7469 r = vcpu_load(vcpu);
7470 BUG_ON(r);
d19a9cd2
ZX		 7471 kvm_mmu_unload(vcpu);
7472 vcpu_put(vcpu);
7473}
7474
7475static void kvm_free_vcpus(struct kvm *kvm)
7476{
7477 unsigned int i;
988a2cae 7478 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7479
7480 /*
7481 * Unpin any mmu pages first.
7482 */
af585b92
GN		 7483 kvm_for_each_vcpu(i, vcpu, kvm) {
7484 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7485 kvm_unload_vcpu_mmu(vcpu);
af585b92 7486 }
988a2cae
GN		 7487 kvm_for_each_vcpu(i, vcpu, kvm)
7488 kvm_arch_vcpu_free(vcpu);
7489
7490 mutex_lock(&kvm->lock);
7491 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7492 kvm->vcpus[i] = NULL;
d19a9cd2 7493
988a2cae
GN		 7494 atomic_set(&kvm->online_vcpus, 0);
7495 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7496}
7497
ad8ba2cd
SY		 7498void kvm_arch_sync_events(struct kvm *kvm)
7499{
332967a3 7500 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7501 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7502 kvm_free_all_assigned_devices(kvm);
aea924f6 7503 kvm_free_pit(kvm);
ad8ba2cd
SY		 7504}
7505
d19a9cd2
ZX		 7506void kvm_arch_destroy_vm(struct kvm *kvm)
7507{
27469d29
AH		 7508 if (current->mm == kvm->mm) {
7509 /*
7510 * Free memory regions allocated on behalf of userspace,
7511 * unless the the memory map has changed due to process exit
7512 * or fd copying.
7513 */
7514 struct kvm_userspace_memory_region mem;
7515 memset(&mem, 0, sizeof(mem));
7516 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7517 kvm_set_memory_region(kvm, &mem);
7518
7519 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7520 kvm_set_memory_region(kvm, &mem);
7521
7522 mem.slot = TSS_PRIVATE_MEMSLOT;
7523 kvm_set_memory_region(kvm, &mem);
7524 }
6eb55818 7525 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7526 kfree(kvm->arch.vpic);
7527 kfree(kvm->arch.vioapic);
d19a9cd2 7528 kvm_free_vcpus(kvm);
1e08ec4a 7529 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7530}
0de10343 7531
5587027c 7532void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7533 struct kvm_memory_slot *dont)
7534{
7535 int i;
7536
d89cc617
TY		 7537 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7538 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7539 kvfree(free->arch.rmap[i]);
d89cc617 7540 free->arch.rmap[i] = NULL;
77d11309 7541 }
d89cc617
TY		 7542 if (i == 0)
7543 continue;
7544
7545 if (!dont || free->arch.lpage_info[i - 1] !=
7546 dont->arch.lpage_info[i - 1]) {
548ef284 7547 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7548 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7549 }
7550 }
7551}
7552
5587027c
AK		 7553int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7554 unsigned long npages)
db3fe4eb
TY		 7555{
7556 int i;
7557
d89cc617 7558 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7559 unsigned long ugfn;
7560 int lpages;
d89cc617 7561 int level = i + 1;
db3fe4eb
TY		 7562
7563 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7564 slot->base_gfn, level) + 1;
7565
d89cc617
TY		 7566 slot->arch.rmap[i] =
7567 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7568 if (!slot->arch.rmap[i])
77d11309 7569 goto out_free;
d89cc617
TY		 7570 if (i == 0)
7571 continue;
77d11309 7572
d89cc617
TY		 7573 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7574 sizeof(*slot->arch.lpage_info[i - 1]));
7575 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7576 goto out_free;
7577
7578 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7579 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7580 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7581 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7582 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7583 /*
7584 * If the gfn and userspace address are not aligned wrt each
7585 * other, or if explicitly asked to, disable large page
7586 * support for this slot
7587 */
7588 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7589 !kvm_largepages_enabled()) {
7590 unsigned long j;
7591
7592 for (j = 0; j < lpages; ++j)
d89cc617 7593 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7594 }
7595 }
7596
7597 return 0;
7598
7599out_free:
d89cc617 7600 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7601 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7602 slot->arch.rmap[i] = NULL;
7603 if (i == 0)
7604 continue;
7605
548ef284 7606 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7607 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7608 }
7609 return -ENOMEM;
7610}
7611
e59dbe09
TY		 7612void kvm_arch_memslots_updated(struct kvm *kvm)
7613{
e6dff7d1
TY		 7614 /*
7615 * memslots->generation has been incremented.
7616 * mmio generation may have reached its maximum value.
7617 */
7618 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7619}
7620
f7784b8e
MT		 7621int kvm_arch_prepare_memory_region(struct kvm *kvm,
7622 struct kvm_memory_slot *memslot,
f7784b8e 7623 struct kvm_userspace_memory_region *mem,
7b6195a9 7624 enum kvm_mr_change change)
0de10343 7625{
7a905b14
TY		 7626 /*
7627 * Only private memory slots need to be mapped here since
7628 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7629 */
7b6195a9 7630 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7631 unsigned long userspace_addr;
604b38ac 7632
7a905b14
TY		 7633 /*
7634 * MAP_SHARED to prevent internal slot pages from being moved
7635 * by fork()/COW.
7636 */
7b6195a9 7637 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7638 PROT_READ | PROT_WRITE,
7639 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7640
7a905b14
TY		 7641 if (IS_ERR((void *)userspace_addr))
7642 return PTR_ERR((void *)userspace_addr);
604b38ac 7643
7a905b14 7644 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7645 }
7646
f7784b8e
MT		 7647 return 0;
7648}
7649
88178fd4
KH		 7650static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7651 struct kvm_memory_slot *new)
7652{
7653 /* Still write protect RO slot */
7654 if (new->flags & KVM_MEM_READONLY) {
7655 kvm_mmu_slot_remove_write_access(kvm, new);
7656 return;
7657 }
7658
7659 /*
7660 * Call kvm_x86_ops dirty logging hooks when they are valid.
7661 *
7662 * kvm_x86_ops->slot_disable_log_dirty is called when:
7663 *
7664 * - KVM_MR_CREATE with dirty logging is disabled
7665 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7666 *
7667 * The reason is, in case of PML, we need to set D-bit for any slots
7668 * with dirty logging disabled in order to eliminate unnecessary GPA
7669 * logging in PML buffer (and potential PML buffer full VMEXT). This
7670 * guarantees leaving PML enabled during guest's lifetime won't have
7671 * any additonal overhead from PML when guest is running with dirty
7672 * logging disabled for memory slots.
7673 *
7674 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7675 * to dirty logging mode.
7676 *
7677 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7678 *
7679 * In case of write protect:
7680 *
7681 * Write protect all pages for dirty logging.
7682 *
7683 * All the sptes including the large sptes which point to this
7684 * slot are set to readonly. We can not create any new large
7685 * spte on this slot until the end of the logging.
7686 *
7687 * See the comments in fast_page_fault().
7688 */
7689 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7690 if (kvm_x86_ops->slot_enable_log_dirty)
7691 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7692 else
7693 kvm_mmu_slot_remove_write_access(kvm, new);
7694 } else {
7695 if (kvm_x86_ops->slot_disable_log_dirty)
7696 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7697 }
7698}
7699
f7784b8e
MT		 7700void kvm_arch_commit_memory_region(struct kvm *kvm,
7701 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7702 const struct kvm_memory_slot *old,
7703 enum kvm_mr_change change)
f7784b8e 7704{
1c91cad4 7705 struct kvm_memory_slot *new;
8482644a 7706 int nr_mmu_pages = 0;
f7784b8e 7707
8482644a 7708 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7709 int ret;
7710
8482644a
TY		 7711 ret = vm_munmap(old->userspace_addr,
7712 old->npages * PAGE_SIZE);
f7784b8e
MT		 7713 if (ret < 0)
7714 printk(KERN_WARNING
7715 "kvm_vm_ioctl_set_memory_region: "
7716 "failed to munmap memory\n");
7717 }
7718
48c0e4e9
XG		 7719 if (!kvm->arch.n_requested_mmu_pages)
7720 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7721
48c0e4e9 7722 if (nr_mmu_pages)
0de10343 7723 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4
KH		 7724
7725 /* It's OK to get 'new' slot here as it has already been installed */
7726 new = id_to_memslot(kvm->memslots, mem->slot);
7727
3ea3b7fa
WL		 7728 /*
7729 * Dirty logging tracks sptes in 4k granularity, meaning that large
7730 * sptes have to be split. If live migration is successful, the guest
7731 * in the source machine will be destroyed and large sptes will be
7732 * created in the destination. However, if the guest continues to run
7733 * in the source machine (for example if live migration fails), small
7734 * sptes will remain around and cause bad performance.
7735 *
7736 * Scan sptes if dirty logging has been stopped, dropping those
7737 * which can be collapsed into a single large-page spte. Later
7738 * page faults will create the large-page sptes.
7739 */
7740 if ((change != KVM_MR_DELETE) &&
7741 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7742 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7743 kvm_mmu_zap_collapsible_sptes(kvm, new);
7744
c972f3b1 7745 /*
88178fd4 7746 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7747 *
88178fd4
KH		 7748 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7749 * been zapped so no dirty logging staff is needed for old slot. For
7750 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7751 * new and it's also covered when dealing with the new slot.
c972f3b1 7752 */
88178fd4
KH		 7753 if (change != KVM_MR_DELETE)
7754 kvm_mmu_slot_apply_flags(kvm, new);
0de10343 7755}
1d737c8a 7756
2df72e9b 7757void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7758{
6ca18b69 7759 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7760}
7761
2df72e9b
MT		 7762void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7763 struct kvm_memory_slot *slot)
7764{
6ca18b69 7765 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7766}
7767
1d737c8a
ZX		 7768int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7769{
b6b8a145
JK		 7770 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7771 kvm_x86_ops->check_nested_events(vcpu, false);
7772
af585b92
GN		 7773 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7774 !vcpu->arch.apf.halted)
7775 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7776 || kvm_apic_has_events(vcpu)
6aef266c 7777 || vcpu->arch.pv.pv_unhalted
7460fb4a 7778 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7779 (kvm_arch_interrupt_allowed(vcpu) &&
7780 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7781}
5736199a 7782
b6d33834 7783int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7784{
b6d33834 7785 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7786}
78646121
GN		 7787
7788int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7789{
7790 return kvm_x86_ops->interrupt_allowed(vcpu);
7791}
229456fc 7792
82b32774 7793unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7794{
82b32774
NA		 7795 if (is_64_bit_mode(vcpu))
7796 return kvm_rip_read(vcpu);
7797 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7798 kvm_rip_read(vcpu));
7799}
7800EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7801
82b32774
NA		 7802bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7803{
7804 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7805}
7806EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7807
94fe45da
JK		 7808unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7809{
7810 unsigned long rflags;
7811
7812 rflags = kvm_x86_ops->get_rflags(vcpu);
7813 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7814 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7815 return rflags;
7816}
7817EXPORT_SYMBOL_GPL(kvm_get_rflags);
7818
6addfc42 7819static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7820{
7821 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7822 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7823 rflags |= X86_EFLAGS_TF;
94fe45da 7824 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7825}
7826
7827void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7828{
7829 __kvm_set_rflags(vcpu, rflags);
3842d135 7830 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7831}
7832EXPORT_SYMBOL_GPL(kvm_set_rflags);
7833
56028d08
GN		 7834void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7835{
7836 int r;
7837
fb67e14f 7838 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7839 work->wakeup_all)
56028d08
GN		 7840 return;
7841
7842 r = kvm_mmu_reload(vcpu);
7843 if (unlikely(r))
7844 return;
7845
fb67e14f
XG		 7846 if (!vcpu->arch.mmu.direct_map &&
7847 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7848 return;
7849
56028d08
GN		 7850 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7851}
7852
af585b92
GN		 7853static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7854{
7855 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7856}
7857
7858static inline u32 kvm_async_pf_next_probe(u32 key)
7859{
7860 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7861}
7862
7863static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7864{
7865 u32 key = kvm_async_pf_hash_fn(gfn);
7866
7867 while (vcpu->arch.apf.gfns[key] != ~0)
7868 key = kvm_async_pf_next_probe(key);
7869
7870 vcpu->arch.apf.gfns[key] = gfn;
7871}
7872
7873static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7874{
7875 int i;
7876 u32 key = kvm_async_pf_hash_fn(gfn);
7877
7878 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7879 (vcpu->arch.apf.gfns[key] != gfn &&
7880 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7881 key = kvm_async_pf_next_probe(key);
7882
7883 return key;
7884}
7885
7886bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7887{
7888 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7889}
7890
7891static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7892{
7893 u32 i, j, k;
7894
7895 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7896 while (true) {
7897 vcpu->arch.apf.gfns[i] = ~0;
7898 do {
7899 j = kvm_async_pf_next_probe(j);
7900 if (vcpu->arch.apf.gfns[j] == ~0)
7901 return;
7902 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7903 /*
7904 * k lies cyclically in ]i,j]
7905 * | i.k.j |
7906 * |....j i.k.| or |.k..j i...|
7907 */
7908 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7909 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7910 i = j;
7911 }
7912}
7913
7c90705b
GN		 7914static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7915{
7916
7917 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7918 sizeof(val));
7919}
7920
af585b92
GN		 7921void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7922 struct kvm_async_pf *work)
7923{
6389ee94
AK		 7924 struct x86_exception fault;
7925
7c90705b 7926 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7927 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7928
7929 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7930 (vcpu->arch.apf.send_user_only &&
7931 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7932 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7933 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7934 fault.vector = PF_VECTOR;
7935 fault.error_code_valid = true;
7936 fault.error_code = 0;
7937 fault.nested_page_fault = false;
7938 fault.address = work->arch.token;
7939 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7940 }
af585b92
GN		 7941}
7942
7943void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7944 struct kvm_async_pf *work)
7945{
6389ee94
AK		 7946 struct x86_exception fault;
7947
7c90705b 7948 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7949 if (work->wakeup_all)
7c90705b
GN		 7950 work->arch.token = ~0; /* broadcast wakeup */
7951 else
7952 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7953
7954 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7955 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7956 fault.vector = PF_VECTOR;
7957 fault.error_code_valid = true;
7958 fault.error_code = 0;
7959 fault.nested_page_fault = false;
7960 fault.address = work->arch.token;
7961 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7962 }
e6d53e3b 7963 vcpu->arch.apf.halted = false;
a4fa1635 7964 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7965}
7966
7967bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7968{
7969 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7970 return true;
7971 else
7972 return !kvm_event_needs_reinjection(vcpu) &&
7973 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7974}
7975
e0f0bbc5
AW		 7976void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7977{
7978 atomic_inc(&kvm->arch.noncoherent_dma_count);
7979}
7980EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7981
7982void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7983{
7984 atomic_dec(&kvm->arch.noncoherent_dma_count);
7985}
7986EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7987
7988bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7989{
7990 return atomic_read(&kvm->arch.noncoherent_dma_count);
7991}
7992EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7993
229456fc
MT		 7994EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7995EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7996EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7997EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7998EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7999EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8000EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8001EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8002EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8003EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8004EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8005EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8006EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8007EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8008EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux 6.x block layer and io_uring tree(s)