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KVM: x86: mark hyper-v vapic assist page as dirty
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
18863bdd
AK		 109#define KVM_NR_SHARED_MSRS 16
110
111struct kvm_shared_msrs_global {
112 int nr;
2bf78fa7 113 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
2bf78fa7
SY		 119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 123};
124
125static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 126static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 127
417bc304 128struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 141 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 149 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 150 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 158 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 160 { "largepages", VM_STAT(lpages) },
417bc304
HB		 161 { NULL }
162};
163
2acf923e
DC		 164u64 __read_mostly host_xcr0;
165
b6785def 166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 167
af585b92
GN		 168static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169{
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173}
174
18863bdd
AK		 175static void kvm_on_user_return(struct user_return_notifier *urn)
176{
177 unsigned slot;
18863bdd
AK		 178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 180 struct kvm_shared_msr_values *values;
18863bdd
AK		 181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
18863bdd
AK		 187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191}
192
2bf78fa7 193static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 194{
18863bdd 195 u64 value;
013f6a5d
MT		 196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 198
2bf78fa7
SY		 199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208}
209
210void kvm_define_shared_msr(unsigned slot, u32 msr)
211{
18863bdd
AK		 212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
18863bdd
AK		 217}
218EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220static void kvm_shared_msr_cpu_online(void)
221{
222 unsigned i;
18863bdd
AK		 223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 225 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 226}
227
d5696725 228void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 229{
013f6a5d
MT		 230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 232
2bf78fa7 233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 234 return;
2bf78fa7
SY		 235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242}
243EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
3548bab5
AK		 245static void drop_user_return_notifiers(void *ignore)
246{
013f6a5d
MT		 247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252}
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
8a5a87d9 256 return vcpu->arch.apic_base;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
260void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
261{
262 /* TODO: reserve bits check */
8a5a87d9 263 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 264}
265EXPORT_SYMBOL_GPL(kvm_set_apic_base);
266
e3ba45b8
GL		 267asmlinkage void kvm_spurious_fault(void)
268{
269 /* Fault while not rebooting. We want the trace. */
270 BUG();
271}
272EXPORT_SYMBOL_GPL(kvm_spurious_fault);
273
3fd28fce
ED		 274#define EXCPT_BENIGN 0
275#define EXCPT_CONTRIBUTORY 1
276#define EXCPT_PF 2
277
278static int exception_class(int vector)
279{
280 switch (vector) {
281 case PF_VECTOR:
282 return EXCPT_PF;
283 case DE_VECTOR:
284 case TS_VECTOR:
285 case NP_VECTOR:
286 case SS_VECTOR:
287 case GP_VECTOR:
288 return EXCPT_CONTRIBUTORY;
289 default:
290 break;
291 }
292 return EXCPT_BENIGN;
293}
294
295static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 296 unsigned nr, bool has_error, u32 error_code,
297 bool reinject)
3fd28fce
ED		 298{
299 u32 prev_nr;
300 int class1, class2;
301
3842d135
AK		 302 kvm_make_request(KVM_REQ_EVENT, vcpu);
303
3fd28fce
ED		 304 if (!vcpu->arch.exception.pending) {
305 queue:
306 vcpu->arch.exception.pending = true;
307 vcpu->arch.exception.has_error_code = has_error;
308 vcpu->arch.exception.nr = nr;
309 vcpu->arch.exception.error_code = error_code;
3f0fd292 310 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 311 return;
312 }
313
314 /* to check exception */
315 prev_nr = vcpu->arch.exception.nr;
316 if (prev_nr == DF_VECTOR) {
317 /* triple fault -> shutdown */
a8eeb04a 318 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 319 return;
320 }
321 class1 = exception_class(prev_nr);
322 class2 = exception_class(nr);
323 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
324 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
325 /* generate double fault per SDM Table 5-5 */
326 vcpu->arch.exception.pending = true;
327 vcpu->arch.exception.has_error_code = true;
328 vcpu->arch.exception.nr = DF_VECTOR;
329 vcpu->arch.exception.error_code = 0;
330 } else
331 /* replace previous exception with a new one in a hope
332 that instruction re-execution will regenerate lost
333 exception */
334 goto queue;
335}
336
298101da
AK		 337void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
338{
ce7ddec4 339 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 340}
341EXPORT_SYMBOL_GPL(kvm_queue_exception);
342
ce7ddec4
JR		 343void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
344{
345 kvm_multiple_exception(vcpu, nr, false, 0, true);
346}
347EXPORT_SYMBOL_GPL(kvm_requeue_exception);
348
db8fcefa 349void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 350{
db8fcefa
AP		 351 if (err)
352 kvm_inject_gp(vcpu, 0);
353 else
354 kvm_x86_ops->skip_emulated_instruction(vcpu);
355}
356EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 357
6389ee94 358void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 359{
360 ++vcpu->stat.pf_guest;
6389ee94
AK		 361 vcpu->arch.cr2 = fault->address;
362 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 363}
27d6c865 364EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 365
6389ee94 366void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 367{
6389ee94
AK		 368 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
369 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 370 else
6389ee94 371 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 372}
373
3419ffc8
SY		 374void kvm_inject_nmi(struct kvm_vcpu *vcpu)
375{
7460fb4a
AK		 376 atomic_inc(&vcpu->arch.nmi_queued);
377 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 378}
379EXPORT_SYMBOL_GPL(kvm_inject_nmi);
380
298101da
AK		 381void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
382{
ce7ddec4 383 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 384}
385EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
386
ce7ddec4
JR		 387void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
388{
389 kvm_multiple_exception(vcpu, nr, true, error_code, true);
390}
391EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
392
0a79b009
AK		 393/*
394 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
395 * a #GP and return false.
396 */
397bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 398{
0a79b009
AK		 399 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
400 return true;
401 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
402 return false;
298101da 403}
0a79b009 404EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 405
ec92fe44
JR		 406/*
407 * This function will be used to read from the physical memory of the currently
408 * running guest. The difference to kvm_read_guest_page is that this function
409 * can read from guest physical or from the guest's guest physical memory.
410 */
411int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
412 gfn_t ngfn, void *data, int offset, int len,
413 u32 access)
414{
415 gfn_t real_gfn;
416 gpa_t ngpa;
417
418 ngpa = gfn_to_gpa(ngfn);
419 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
420 if (real_gfn == UNMAPPED_GVA)
421 return -EFAULT;
422
423 real_gfn = gpa_to_gfn(real_gfn);
424
425 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
426}
427EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
428
3d06b8bf
JR		 429int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
430 void *data, int offset, int len, u32 access)
431{
432 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
433 data, offset, len, access);
434}
435
a03490ed
CO		 436/*
437 * Load the pae pdptrs. Return true is they are all valid.
438 */
ff03a073 439int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 440{
441 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
442 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
443 int i;
444 int ret;
ff03a073 445 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 446
ff03a073
JR		 447 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
448 offset * sizeof(u64), sizeof(pdpte),
449 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 450 if (ret < 0) {
451 ret = 0;
452 goto out;
453 }
454 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 455 if (is_present_gpte(pdpte[i]) &&
20c466b5 456 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 457 ret = 0;
458 goto out;
459 }
460 }
461 ret = 1;
462
ff03a073 463 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 464 __set_bit(VCPU_EXREG_PDPTR,
465 (unsigned long *)&vcpu->arch.regs_avail);
466 __set_bit(VCPU_EXREG_PDPTR,
467 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 468out:
a03490ed
CO		 469
470 return ret;
471}
cc4b6871 472EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 473
d835dfec
AK		 474static bool pdptrs_changed(struct kvm_vcpu *vcpu)
475{
ff03a073 476 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 477 bool changed = true;
3d06b8bf
JR		 478 int offset;
479 gfn_t gfn;
d835dfec
AK		 480 int r;
481
482 if (is_long_mode(vcpu) || !is_pae(vcpu))
483 return false;
484
6de4f3ad
AK		 485 if (!test_bit(VCPU_EXREG_PDPTR,
486 (unsigned long *)&vcpu->arch.regs_avail))
487 return true;
488
9f8fe504
AK		 489 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
490 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 491 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
492 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 493 if (r < 0)
494 goto out;
ff03a073 495 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 496out:
d835dfec
AK		 497
498 return changed;
499}
500
49a9b07e 501int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 502{
aad82703
SY		 503 unsigned long old_cr0 = kvm_read_cr0(vcpu);
504 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
505 X86_CR0_CD | X86_CR0_NW;
506
f9a48e6a
AK		 507 cr0 |= X86_CR0_ET;
508
ab344828 509#ifdef CONFIG_X86_64
0f12244f
GN		 510 if (cr0 & 0xffffffff00000000UL)
511 return 1;
ab344828
GN		 512#endif
513
514 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 515
0f12244f
GN		 516 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
517 return 1;
a03490ed 518
0f12244f
GN		 519 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
520 return 1;
a03490ed
CO		 521
522 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
523#ifdef CONFIG_X86_64
f6801dff 524 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 525 int cs_db, cs_l;
526
0f12244f
GN		 527 if (!is_pae(vcpu))
528 return 1;
a03490ed 529 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 530 if (cs_l)
531 return 1;
a03490ed
CO		 532 } else
533#endif
ff03a073 534 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 535 kvm_read_cr3(vcpu)))
0f12244f 536 return 1;
a03490ed
CO		 537 }
538
ad756a16
MJ		 539 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
540 return 1;
541
a03490ed 542 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 543
d170c419 544 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 545 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 546 kvm_async_pf_hash_reset(vcpu);
547 }
e5f3f027 548
aad82703
SY		 549 if ((cr0 ^ old_cr0) & update_bits)
550 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 551 return 0;
552}
2d3ad1f4 553EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 554
2d3ad1f4 555void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 556{
49a9b07e 557 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 558}
2d3ad1f4 559EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 560
42bdf991
MT		 561static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
562{
563 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
564 !vcpu->guest_xcr0_loaded) {
565 /* kvm_set_xcr() also depends on this */
566 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
567 vcpu->guest_xcr0_loaded = 1;
568 }
569}
570
571static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
572{
573 if (vcpu->guest_xcr0_loaded) {
574 if (vcpu->arch.xcr0 != host_xcr0)
575 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
576 vcpu->guest_xcr0_loaded = 0;
577 }
578}
579
2acf923e
DC		 580int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
581{
582 u64 xcr0;
46c34cb0 583 u64 valid_bits;
2acf923e
DC		 584
585 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
586 if (index != XCR_XFEATURE_ENABLED_MASK)
587 return 1;
588 xcr0 = xcr;
2acf923e
DC		 589 if (!(xcr0 & XSTATE_FP))
590 return 1;
591 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
592 return 1;
46c34cb0
PB		 593
594 /*
595 * Do not allow the guest to set bits that we do not support
596 * saving. However, xcr0 bit 0 is always set, even if the
597 * emulated CPU does not support XSAVE (see fx_init).
598 */
599 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
600 if (xcr0 & ~valid_bits)
2acf923e 601 return 1;
46c34cb0 602
42bdf991 603 kvm_put_guest_xcr0(vcpu);
2acf923e 604 vcpu->arch.xcr0 = xcr0;
2acf923e
DC		 605 return 0;
606}
607
608int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
609{
764bcbc5
Z		 610 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
611 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 612 kvm_inject_gp(vcpu, 0);
613 return 1;
614 }
615 return 0;
616}
617EXPORT_SYMBOL_GPL(kvm_set_xcr);
618
a83b29c6 619int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 620{
fc78f519 621 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 622 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
623 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 624 if (cr4 & CR4_RESERVED_BITS)
625 return 1;
a03490ed 626
2acf923e
DC		 627 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
628 return 1;
629
c68b734f
YW		 630 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
631 return 1;
632
afcbf13f 633 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 634 return 1;
635
a03490ed 636 if (is_long_mode(vcpu)) {
0f12244f
GN		 637 if (!(cr4 & X86_CR4_PAE))
638 return 1;
a2edf57f
AK		 639 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
640 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 641 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
642 kvm_read_cr3(vcpu)))
0f12244f
GN		 643 return 1;
644
ad756a16
MJ		 645 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
646 if (!guest_cpuid_has_pcid(vcpu))
647 return 1;
648
649 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
650 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
651 return 1;
652 }
653
5e1746d6 654 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 655 return 1;
a03490ed 656
ad756a16
MJ		 657 if (((cr4 ^ old_cr4) & pdptr_bits) ||
658 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 659 kvm_mmu_reset_context(vcpu);
0f12244f 660
2acf923e 661 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 662 kvm_update_cpuid(vcpu);
2acf923e 663
0f12244f
GN		 664 return 0;
665}
2d3ad1f4 666EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 667
2390218b 668int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 669{
9f8fe504 670 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 671 kvm_mmu_sync_roots(vcpu);
d835dfec 672 kvm_mmu_flush_tlb(vcpu);
0f12244f 673 return 0;
d835dfec
AK		 674 }
675
a03490ed 676 if (is_long_mode(vcpu)) {
471842ec 677 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 678 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
679 return 1;
680 } else
681 if (cr3 & CR3_L_MODE_RESERVED_BITS)
682 return 1;
a03490ed
CO		 683 } else {
684 if (is_pae(vcpu)) {
0f12244f
GN		 685 if (cr3 & CR3_PAE_RESERVED_BITS)
686 return 1;
ff03a073
JR		 687 if (is_paging(vcpu) &&
688 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 689 return 1;
a03490ed
CO		 690 }
691 /*
692 * We don't check reserved bits in nonpae mode, because
693 * this isn't enforced, and VMware depends on this.
694 */
695 }
696
0f12244f 697 vcpu->arch.cr3 = cr3;
aff48baa 698 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 699 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 700 return 0;
701}
2d3ad1f4 702EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 703
eea1cff9 704int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 705{
0f12244f
GN		 706 if (cr8 & CR8_RESERVED_BITS)
707 return 1;
a03490ed
CO		 708 if (irqchip_in_kernel(vcpu->kvm))
709 kvm_lapic_set_tpr(vcpu, cr8);
710 else
ad312c7c 711 vcpu->arch.cr8 = cr8;
0f12244f
GN		 712 return 0;
713}
2d3ad1f4 714EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 715
2d3ad1f4 716unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 717{
718 if (irqchip_in_kernel(vcpu->kvm))
719 return kvm_lapic_get_cr8(vcpu);
720 else
ad312c7c 721 return vcpu->arch.cr8;
a03490ed 722}
2d3ad1f4 723EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 724
73aaf249
JK		 725static void kvm_update_dr6(struct kvm_vcpu *vcpu)
726{
727 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
728 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
729}
730
c8639010
JK		 731static void kvm_update_dr7(struct kvm_vcpu *vcpu)
732{
733 unsigned long dr7;
734
735 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
736 dr7 = vcpu->arch.guest_debug_dr7;
737 else
738 dr7 = vcpu->arch.dr7;
739 kvm_x86_ops->set_dr7(vcpu, dr7);
740 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
741}
742
338dbc97 743static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 744{
745 switch (dr) {
746 case 0 ... 3:
747 vcpu->arch.db[dr] = val;
748 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
749 vcpu->arch.eff_db[dr] = val;
750 break;
751 case 4:
338dbc97
GN		 752 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
753 return 1; /* #UD */
020df079
GN		 754 /* fall through */
755 case 6:
338dbc97
GN		 756 if (val & 0xffffffff00000000ULL)
757 return -1; /* #GP */
020df079 758 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
73aaf249 759 kvm_update_dr6(vcpu);
020df079
GN		 760 break;
761 case 5:
338dbc97
GN		 762 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
763 return 1; /* #UD */
020df079
GN		 764 /* fall through */
765 default: /* 7 */
338dbc97
GN		 766 if (val & 0xffffffff00000000ULL)
767 return -1; /* #GP */
020df079 768 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 769 kvm_update_dr7(vcpu);
020df079
GN		 770 break;
771 }
772
773 return 0;
774}
338dbc97
GN		 775
776int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
777{
778 int res;
779
780 res = __kvm_set_dr(vcpu, dr, val);
781 if (res > 0)
782 kvm_queue_exception(vcpu, UD_VECTOR);
783 else if (res < 0)
784 kvm_inject_gp(vcpu, 0);
785
786 return res;
787}
020df079
GN		 788EXPORT_SYMBOL_GPL(kvm_set_dr);
789
338dbc97 790static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 791{
792 switch (dr) {
793 case 0 ... 3:
794 *val = vcpu->arch.db[dr];
795 break;
796 case 4:
338dbc97 797 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 798 return 1;
020df079
GN		 799 /* fall through */
800 case 6:
73aaf249
JK		 801 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
802 *val = vcpu->arch.dr6;
803 else
804 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 805 break;
806 case 5:
338dbc97 807 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 808 return 1;
020df079
GN		 809 /* fall through */
810 default: /* 7 */
811 *val = vcpu->arch.dr7;
812 break;
813 }
814
815 return 0;
816}
338dbc97
GN		 817
818int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
819{
820 if (_kvm_get_dr(vcpu, dr, val)) {
821 kvm_queue_exception(vcpu, UD_VECTOR);
822 return 1;
823 }
824 return 0;
825}
020df079
GN		 826EXPORT_SYMBOL_GPL(kvm_get_dr);
827
022cd0e8
AK		 828bool kvm_rdpmc(struct kvm_vcpu *vcpu)
829{
830 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
831 u64 data;
832 int err;
833
834 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
835 if (err)
836 return err;
837 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
838 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
839 return err;
840}
841EXPORT_SYMBOL_GPL(kvm_rdpmc);
842
043405e1
CO		 843/*
844 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
845 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
846 *
847 * This list is modified at module load time to reflect the
e3267cbb
GC		 848 * capabilities of the host cpu. This capabilities test skips MSRs that are
849 * kvm-specific. Those are put in the beginning of the list.
043405e1 850 */
e3267cbb 851
e984097b 852#define KVM_SAVE_MSRS_BEGIN 12
043405e1 853static u32 msrs_to_save[] = {
e3267cbb 854 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 855 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 856 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 857 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 858 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 859 MSR_KVM_PV_EOI_EN,
043405e1 860 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 861 MSR_STAR,
043405e1
CO		 862#ifdef CONFIG_X86_64
863 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
864#endif
b3897a49
NHE		 865 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
866 MSR_IA32_FEATURE_CONTROL
043405e1
CO		 867};
868
869static unsigned num_msrs_to_save;
870
f1d24831 871static const u32 emulated_msrs[] = {
ba904635 872 MSR_IA32_TSC_ADJUST,
a3e06bbe 873 MSR_IA32_TSCDEADLINE,
043405e1 874 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 875 MSR_IA32_MCG_STATUS,
876 MSR_IA32_MCG_CTL,
043405e1
CO		 877};
878
384bb783 879bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 880{
b69e8cae 881 if (efer & efer_reserved_bits)
384bb783 882 return false;
15c4a640 883
1b2fd70c
AG		 884 if (efer & EFER_FFXSR) {
885 struct kvm_cpuid_entry2 *feat;
886
887 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 888 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 889 return false;
1b2fd70c
AG		 890 }
891
d8017474
AG		 892 if (efer & EFER_SVME) {
893 struct kvm_cpuid_entry2 *feat;
894
895 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 896 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 897 return false;
d8017474
AG		 898 }
899
384bb783
JK		 900 return true;
901}
902EXPORT_SYMBOL_GPL(kvm_valid_efer);
903
904static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
905{
906 u64 old_efer = vcpu->arch.efer;
907
908 if (!kvm_valid_efer(vcpu, efer))
909 return 1;
910
911 if (is_paging(vcpu)
912 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
913 return 1;
914
15c4a640 915 efer &= ~EFER_LMA;
f6801dff 916 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 917
a3d204e2
SY		 918 kvm_x86_ops->set_efer(vcpu, efer);
919
aad82703
SY		 920 /* Update reserved bits */
921 if ((efer ^ old_efer) & EFER_NX)
922 kvm_mmu_reset_context(vcpu);
923
b69e8cae 924 return 0;
15c4a640
CO		 925}
926
f2b4b7dd
JR		 927void kvm_enable_efer_bits(u64 mask)
928{
929 efer_reserved_bits &= ~mask;
930}
931EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
932
933
15c4a640
CO		 934/*
935 * Writes msr value into into the appropriate "register".
936 * Returns 0 on success, non-0 otherwise.
937 * Assumes vcpu_load() was already called.
938 */
8fe8ab46 939int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 940{
8fe8ab46 941 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 942}
943
313a3dc7
CO		 944/*
945 * Adapt set_msr() to msr_io()'s calling convention
946 */
947static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
948{
8fe8ab46
WA		 949 struct msr_data msr;
950
951 msr.data = *data;
952 msr.index = index;
953 msr.host_initiated = true;
954 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 955}
956
16e8d74d
MT		 957#ifdef CONFIG_X86_64
958struct pvclock_gtod_data {
959 seqcount_t seq;
960
961 struct { /* extract of a clocksource struct */
962 int vclock_mode;
963 cycle_t cycle_last;
964 cycle_t mask;
965 u32 mult;
966 u32 shift;
967 } clock;
968
969 /* open coded 'struct timespec' */
970 u64 monotonic_time_snsec;
971 time_t monotonic_time_sec;
972};
973
974static struct pvclock_gtod_data pvclock_gtod_data;
975
976static void update_pvclock_gtod(struct timekeeper *tk)
977{
978 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
979
980 write_seqcount_begin(&vdata->seq);
981
982 /* copy pvclock gtod data */
983 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
984 vdata->clock.cycle_last = tk->clock->cycle_last;
985 vdata->clock.mask = tk->clock->mask;
986 vdata->clock.mult = tk->mult;
987 vdata->clock.shift = tk->shift;
988
989 vdata->monotonic_time_sec = tk->xtime_sec
990 + tk->wall_to_monotonic.tv_sec;
991 vdata->monotonic_time_snsec = tk->xtime_nsec
992 + (tk->wall_to_monotonic.tv_nsec
993 << tk->shift);
994 while (vdata->monotonic_time_snsec >=
995 (((u64)NSEC_PER_SEC) << tk->shift)) {
996 vdata->monotonic_time_snsec -=
997 ((u64)NSEC_PER_SEC) << tk->shift;
998 vdata->monotonic_time_sec++;
999 }
1000
1001 write_seqcount_end(&vdata->seq);
1002}
1003#endif
1004
1005
18068523
GOC		 1006static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1007{
9ed3c444
AK		 1008 int version;
1009 int r;
50d0a0f9 1010 struct pvclock_wall_clock wc;
923de3cf 1011 struct timespec boot;
18068523
GOC		 1012
1013 if (!wall_clock)
1014 return;
1015
9ed3c444
AK		 1016 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1017 if (r)
1018 return;
1019
1020 if (version & 1)
1021 ++version; /* first time write, random junk */
1022
1023 ++version;
18068523 1024
18068523
GOC		 1025 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1026
50d0a0f9
GH		 1027 /*
1028 * The guest calculates current wall clock time by adding
34c238a1 1029 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1030 * wall clock specified here. guest system time equals host
1031 * system time for us, thus we must fill in host boot time here.
1032 */
923de3cf 1033 getboottime(&boot);
50d0a0f9 1034
4b648665
BR		 1035 if (kvm->arch.kvmclock_offset) {
1036 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1037 boot = timespec_sub(boot, ts);
1038 }
50d0a0f9
GH		 1039 wc.sec = boot.tv_sec;
1040 wc.nsec = boot.tv_nsec;
1041 wc.version = version;
18068523
GOC		 1042
1043 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1044
1045 version++;
1046 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1047}
1048
50d0a0f9
GH		 1049static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1050{
1051 uint32_t quotient, remainder;
1052
1053 /* Don't try to replace with do_div(), this one calculates
1054 * "(dividend << 32) / divisor" */
1055 __asm__ ( "divl %4"
1056 : "=a" (quotient), "=d" (remainder)
1057 : "0" (0), "1" (dividend), "r" (divisor) );
1058 return quotient;
1059}
1060
5f4e3f88
ZA		 1061static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1062 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1063{
5f4e3f88 1064 uint64_t scaled64;
50d0a0f9
GH		 1065 int32_t shift = 0;
1066 uint64_t tps64;
1067 uint32_t tps32;
1068
5f4e3f88
ZA		 1069 tps64 = base_khz * 1000LL;
1070 scaled64 = scaled_khz * 1000LL;
50933623 1071 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1072 tps64 >>= 1;
1073 shift--;
1074 }
1075
1076 tps32 = (uint32_t)tps64;
50933623
JK		 1077 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1078 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1079 scaled64 >>= 1;
1080 else
1081 tps32 <<= 1;
50d0a0f9
GH		 1082 shift++;
1083 }
1084
5f4e3f88
ZA		 1085 *pshift = shift;
1086 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1087
5f4e3f88
ZA		 1088 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1089 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1090}
1091
759379dd
ZA		 1092static inline u64 get_kernel_ns(void)
1093{
1094 struct timespec ts;
1095
1096 WARN_ON(preemptible());
1097 ktime_get_ts(&ts);
1098 monotonic_to_bootbased(&ts);
1099 return timespec_to_ns(&ts);
50d0a0f9
GH		 1100}
1101
d828199e 1102#ifdef CONFIG_X86_64
16e8d74d 1103static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1104#endif
16e8d74d 1105
c8076604 1106static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1107unsigned long max_tsc_khz;
c8076604 1108
cc578287 1109static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1110{
cc578287
ZA		 1111 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1112 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1113}
1114
cc578287 1115static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1116{
cc578287
ZA		 1117 u64 v = (u64)khz * (1000000 + ppm);
1118 do_div(v, 1000000);
1119 return v;
1e993611
JR		 1120}
1121
cc578287 1122static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1123{
cc578287
ZA		 1124 u32 thresh_lo, thresh_hi;
1125 int use_scaling = 0;
217fc9cf 1126
03ba32ca
MT		 1127 /* tsc_khz can be zero if TSC calibration fails */
1128 if (this_tsc_khz == 0)
1129 return;
1130
c285545f
ZA		 1131 /* Compute a scale to convert nanoseconds in TSC cycles */
1132 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1133 &vcpu->arch.virtual_tsc_shift,
1134 &vcpu->arch.virtual_tsc_mult);
1135 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1136
1137 /*
1138 * Compute the variation in TSC rate which is acceptable
1139 * within the range of tolerance and decide if the
1140 * rate being applied is within that bounds of the hardware
1141 * rate. If so, no scaling or compensation need be done.
1142 */
1143 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1144 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1145 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1146 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1147 use_scaling = 1;
1148 }
1149 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1150}
1151
1152static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1153{
e26101b1 1154 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1155 vcpu->arch.virtual_tsc_mult,
1156 vcpu->arch.virtual_tsc_shift);
e26101b1 1157 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1158 return tsc;
1159}
1160
b48aa97e
MT		 1161void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1162{
1163#ifdef CONFIG_X86_64
1164 bool vcpus_matched;
1165 bool do_request = false;
1166 struct kvm_arch *ka = &vcpu->kvm->arch;
1167 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1168
1169 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1170 atomic_read(&vcpu->kvm->online_vcpus));
1171
1172 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1173 if (!ka->use_master_clock)
1174 do_request = 1;
1175
1176 if (!vcpus_matched && ka->use_master_clock)
1177 do_request = 1;
1178
1179 if (do_request)
1180 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1181
1182 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1183 atomic_read(&vcpu->kvm->online_vcpus),
1184 ka->use_master_clock, gtod->clock.vclock_mode);
1185#endif
1186}
1187
ba904635
WA		 1188static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1189{
1190 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1191 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1192}
1193
8fe8ab46 1194void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1195{
1196 struct kvm *kvm = vcpu->kvm;
f38e098f 1197 u64 offset, ns, elapsed;
99e3e30a 1198 unsigned long flags;
02626b6a 1199 s64 usdiff;
b48aa97e 1200 bool matched;
8fe8ab46 1201 u64 data = msr->data;
99e3e30a 1202
038f8c11 1203 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1204 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1205 ns = get_kernel_ns();
f38e098f 1206 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1207
03ba32ca 1208 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1209 int faulted = 0;
1210
03ba32ca
MT		 1211 /* n.b - signed multiplication and division required */
1212 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1213#ifdef CONFIG_X86_64
03ba32ca 1214 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1215#else
03ba32ca 1216 /* do_div() only does unsigned */
8915aa27
MT		 1217 asm("1: idivl %[divisor]\n"
1218 "2: xor %%edx, %%edx\n"
1219 " movl $0, %[faulted]\n"
1220 "3:\n"
1221 ".section .fixup,\"ax\"\n"
1222 "4: movl $1, %[faulted]\n"
1223 " jmp 3b\n"
1224 ".previous\n"
1225
1226 _ASM_EXTABLE(1b, 4b)
1227
1228 : "=A"(usdiff), [faulted] "=r" (faulted)
1229 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1230
5d3cb0f6 1231#endif
03ba32ca
MT		 1232 do_div(elapsed, 1000);
1233 usdiff -= elapsed;
1234 if (usdiff < 0)
1235 usdiff = -usdiff;
8915aa27
MT		 1236
1237 /* idivl overflow => difference is larger than USEC_PER_SEC */
1238 if (faulted)
1239 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1240 } else
1241 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1242
1243 /*
5d3cb0f6
ZA		 1244 * Special case: TSC write with a small delta (1 second) of virtual
1245 * cycle time against real time is interpreted as an attempt to
1246 * synchronize the CPU.
1247 *
1248 * For a reliable TSC, we can match TSC offsets, and for an unstable
1249 * TSC, we add elapsed time in this computation. We could let the
1250 * compensation code attempt to catch up if we fall behind, but
1251 * it's better to try to match offsets from the beginning.
1252 */
02626b6a 1253 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1254 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1255 if (!check_tsc_unstable()) {
e26101b1 1256 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1257 pr_debug("kvm: matched tsc offset for %llu\n", data);
1258 } else {
857e4099 1259 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1260 data += delta;
1261 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1262 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1263 }
b48aa97e 1264 matched = true;
e26101b1
ZA		 1265 } else {
1266 /*
1267 * We split periods of matched TSC writes into generations.
1268 * For each generation, we track the original measured
1269 * nanosecond time, offset, and write, so if TSCs are in
1270 * sync, we can match exact offset, and if not, we can match
4a969980 1271 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1272 *
1273 * These values are tracked in kvm->arch.cur_xxx variables.
1274 */
1275 kvm->arch.cur_tsc_generation++;
1276 kvm->arch.cur_tsc_nsec = ns;
1277 kvm->arch.cur_tsc_write = data;
1278 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1279 matched = false;
e26101b1
ZA		 1280 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1281 kvm->arch.cur_tsc_generation, data);
f38e098f 1282 }
e26101b1
ZA		 1283
1284 /*
1285 * We also track th most recent recorded KHZ, write and time to
1286 * allow the matching interval to be extended at each write.
1287 */
f38e098f
ZA		 1288 kvm->arch.last_tsc_nsec = ns;
1289 kvm->arch.last_tsc_write = data;
5d3cb0f6 1290 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1291
b183aa58 1292 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1293
1294 /* Keep track of which generation this VCPU has synchronized to */
1295 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1296 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1297 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1298
ba904635
WA		 1299 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1300 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1301 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1302 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1303
1304 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1305 if (matched)
1306 kvm->arch.nr_vcpus_matched_tsc++;
1307 else
1308 kvm->arch.nr_vcpus_matched_tsc = 0;
1309
1310 kvm_track_tsc_matching(vcpu);
1311 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1312}
e26101b1 1313
99e3e30a
ZA		 1314EXPORT_SYMBOL_GPL(kvm_write_tsc);
1315
d828199e
MT		 1316#ifdef CONFIG_X86_64
1317
1318static cycle_t read_tsc(void)
1319{
1320 cycle_t ret;
1321 u64 last;
1322
1323 /*
1324 * Empirically, a fence (of type that depends on the CPU)
1325 * before rdtsc is enough to ensure that rdtsc is ordered
1326 * with respect to loads. The various CPU manuals are unclear
1327 * as to whether rdtsc can be reordered with later loads,
1328 * but no one has ever seen it happen.
1329 */
1330 rdtsc_barrier();
1331 ret = (cycle_t)vget_cycles();
1332
1333 last = pvclock_gtod_data.clock.cycle_last;
1334
1335 if (likely(ret >= last))
1336 return ret;
1337
1338 /*
1339 * GCC likes to generate cmov here, but this branch is extremely
1340 * predictable (it's just a funciton of time and the likely is
1341 * very likely) and there's a data dependence, so force GCC
1342 * to generate a branch instead. I don't barrier() because
1343 * we don't actually need a barrier, and if this function
1344 * ever gets inlined it will generate worse code.
1345 */
1346 asm volatile ("");
1347 return last;
1348}
1349
1350static inline u64 vgettsc(cycle_t *cycle_now)
1351{
1352 long v;
1353 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1354
1355 *cycle_now = read_tsc();
1356
1357 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1358 return v * gtod->clock.mult;
1359}
1360
1361static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1362{
1363 unsigned long seq;
1364 u64 ns;
1365 int mode;
1366 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1367
1368 ts->tv_nsec = 0;
1369 do {
1370 seq = read_seqcount_begin(&gtod->seq);
1371 mode = gtod->clock.vclock_mode;
1372 ts->tv_sec = gtod->monotonic_time_sec;
1373 ns = gtod->monotonic_time_snsec;
1374 ns += vgettsc(cycle_now);
1375 ns >>= gtod->clock.shift;
1376 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1377 timespec_add_ns(ts, ns);
1378
1379 return mode;
1380}
1381
1382/* returns true if host is using tsc clocksource */
1383static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1384{
1385 struct timespec ts;
1386
1387 /* checked again under seqlock below */
1388 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1389 return false;
1390
1391 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1392 return false;
1393
1394 monotonic_to_bootbased(&ts);
1395 *kernel_ns = timespec_to_ns(&ts);
1396
1397 return true;
1398}
1399#endif
1400
1401/*
1402 *
b48aa97e
MT		 1403 * Assuming a stable TSC across physical CPUS, and a stable TSC
1404 * across virtual CPUs, the following condition is possible.
1405 * Each numbered line represents an event visible to both
d828199e
MT		 1406 * CPUs at the next numbered event.
1407 *
1408 * "timespecX" represents host monotonic time. "tscX" represents
1409 * RDTSC value.
1410 *
1411 * VCPU0 on CPU0 | VCPU1 on CPU1
1412 *
1413 * 1. read timespec0,tsc0
1414 * 2. | timespec1 = timespec0 + N
1415 * | tsc1 = tsc0 + M
1416 * 3. transition to guest | transition to guest
1417 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1418 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1419 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1420 *
1421 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1422 *
1423 * - ret0 < ret1
1424 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1425 * ...
1426 * - 0 < N - M => M < N
1427 *
1428 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1429 * always the case (the difference between two distinct xtime instances
1430 * might be smaller then the difference between corresponding TSC reads,
1431 * when updating guest vcpus pvclock areas).
1432 *
1433 * To avoid that problem, do not allow visibility of distinct
1434 * system_timestamp/tsc_timestamp values simultaneously: use a master
1435 * copy of host monotonic time values. Update that master copy
1436 * in lockstep.
1437 *
b48aa97e 1438 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1439 *
1440 */
1441
1442static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1443{
1444#ifdef CONFIG_X86_64
1445 struct kvm_arch *ka = &kvm->arch;
1446 int vclock_mode;
b48aa97e
MT		 1447 bool host_tsc_clocksource, vcpus_matched;
1448
1449 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1450 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1451
1452 /*
1453 * If the host uses TSC clock, then passthrough TSC as stable
1454 * to the guest.
1455 */
b48aa97e 1456 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1457 &ka->master_kernel_ns,
1458 &ka->master_cycle_now);
1459
b48aa97e
MT		 1460 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1461
d828199e
MT		 1462 if (ka->use_master_clock)
1463 atomic_set(&kvm_guest_has_master_clock, 1);
1464
1465 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1466 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1467 vcpus_matched);
d828199e
MT		 1468#endif
1469}
1470
2e762ff7
MT		 1471static void kvm_gen_update_masterclock(struct kvm *kvm)
1472{
1473#ifdef CONFIG_X86_64
1474 int i;
1475 struct kvm_vcpu *vcpu;
1476 struct kvm_arch *ka = &kvm->arch;
1477
1478 spin_lock(&ka->pvclock_gtod_sync_lock);
1479 kvm_make_mclock_inprogress_request(kvm);
1480 /* no guest entries from this point */
1481 pvclock_update_vm_gtod_copy(kvm);
1482
1483 kvm_for_each_vcpu(i, vcpu, kvm)
1484 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1485
1486 /* guest entries allowed */
1487 kvm_for_each_vcpu(i, vcpu, kvm)
1488 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1489
1490 spin_unlock(&ka->pvclock_gtod_sync_lock);
1491#endif
1492}
1493
34c238a1 1494static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1495{
d828199e 1496 unsigned long flags, this_tsc_khz;
18068523 1497 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1498 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1499 s64 kernel_ns;
d828199e 1500 u64 tsc_timestamp, host_tsc;
0b79459b 1501 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1502 u8 pvclock_flags;
d828199e
MT		 1503 bool use_master_clock;
1504
1505 kernel_ns = 0;
1506 host_tsc = 0;
18068523 1507
d828199e
MT		 1508 /*
1509 * If the host uses TSC clock, then passthrough TSC as stable
1510 * to the guest.
1511 */
1512 spin_lock(&ka->pvclock_gtod_sync_lock);
1513 use_master_clock = ka->use_master_clock;
1514 if (use_master_clock) {
1515 host_tsc = ka->master_cycle_now;
1516 kernel_ns = ka->master_kernel_ns;
1517 }
1518 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1519
1520 /* Keep irq disabled to prevent changes to the clock */
1521 local_irq_save(flags);
1522 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1523 if (unlikely(this_tsc_khz == 0)) {
1524 local_irq_restore(flags);
1525 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1526 return 1;
1527 }
d828199e
MT		 1528 if (!use_master_clock) {
1529 host_tsc = native_read_tsc();
1530 kernel_ns = get_kernel_ns();
1531 }
1532
1533 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1534
c285545f
ZA		 1535 /*
1536 * We may have to catch up the TSC to match elapsed wall clock
1537 * time for two reasons, even if kvmclock is used.
1538 * 1) CPU could have been running below the maximum TSC rate
1539 * 2) Broken TSC compensation resets the base at each VCPU
1540 * entry to avoid unknown leaps of TSC even when running
1541 * again on the same CPU. This may cause apparent elapsed
1542 * time to disappear, and the guest to stand still or run
1543 * very slowly.
1544 */
1545 if (vcpu->tsc_catchup) {
1546 u64 tsc = compute_guest_tsc(v, kernel_ns);
1547 if (tsc > tsc_timestamp) {
f1e2b260 1548 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1549 tsc_timestamp = tsc;
1550 }
50d0a0f9
GH		 1551 }
1552
18068523
GOC		 1553 local_irq_restore(flags);
1554
0b79459b 1555 if (!vcpu->pv_time_enabled)
c285545f 1556 return 0;
18068523 1557
e48672fa 1558 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1559 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1560 &vcpu->hv_clock.tsc_shift,
1561 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1562 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1563 }
1564
1565 /* With all the info we got, fill in the values */
1d5f066e 1566 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1567 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1568 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1569 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1570
18068523
GOC		 1571 /*
1572 * The interface expects us to write an even number signaling that the
1573 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1574 * state, we just increase by 2 at the end.
18068523 1575 */
50d0a0f9 1576 vcpu->hv_clock.version += 2;
18068523 1577
0b79459b
AH		 1578 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1579 &guest_hv_clock, sizeof(guest_hv_clock))))
1580 return 0;
78c0337a
MT		 1581
1582 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1583 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1584
1585 if (vcpu->pvclock_set_guest_stopped_request) {
1586 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1587 vcpu->pvclock_set_guest_stopped_request = false;
1588 }
1589
d828199e
MT		 1590 /* If the host uses TSC clocksource, then it is stable */
1591 if (use_master_clock)
1592 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1593
78c0337a
MT		 1594 vcpu->hv_clock.flags = pvclock_flags;
1595
0b79459b
AH		 1596 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1597 &vcpu->hv_clock,
1598 sizeof(vcpu->hv_clock));
8cfdc000 1599 return 0;
c8076604
GH		 1600}
1601
0061d53d
MT		 1602/*
1603 * kvmclock updates which are isolated to a given vcpu, such as
1604 * vcpu->cpu migration, should not allow system_timestamp from
1605 * the rest of the vcpus to remain static. Otherwise ntp frequency
1606 * correction applies to one vcpu's system_timestamp but not
1607 * the others.
1608 *
1609 * So in those cases, request a kvmclock update for all vcpus.
1610 * The worst case for a remote vcpu to update its kvmclock
1611 * is then bounded by maximum nohz sleep latency.
1612 */
1613
1614static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1615{
1616 int i;
1617 struct kvm *kvm = v->kvm;
1618 struct kvm_vcpu *vcpu;
1619
1620 kvm_for_each_vcpu(i, vcpu, kvm) {
1621 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1622 kvm_vcpu_kick(vcpu);
1623 }
1624}
1625
9ba075a6
AK		 1626static bool msr_mtrr_valid(unsigned msr)
1627{
1628 switch (msr) {
1629 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1630 case MSR_MTRRfix64K_00000:
1631 case MSR_MTRRfix16K_80000:
1632 case MSR_MTRRfix16K_A0000:
1633 case MSR_MTRRfix4K_C0000:
1634 case MSR_MTRRfix4K_C8000:
1635 case MSR_MTRRfix4K_D0000:
1636 case MSR_MTRRfix4K_D8000:
1637 case MSR_MTRRfix4K_E0000:
1638 case MSR_MTRRfix4K_E8000:
1639 case MSR_MTRRfix4K_F0000:
1640 case MSR_MTRRfix4K_F8000:
1641 case MSR_MTRRdefType:
1642 case MSR_IA32_CR_PAT:
1643 return true;
1644 case 0x2f8:
1645 return true;
1646 }
1647 return false;
1648}
1649
d6289b93
MT		 1650static bool valid_pat_type(unsigned t)
1651{
1652 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1653}
1654
1655static bool valid_mtrr_type(unsigned t)
1656{
1657 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1658}
1659
1660static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1661{
1662 int i;
1663
1664 if (!msr_mtrr_valid(msr))
1665 return false;
1666
1667 if (msr == MSR_IA32_CR_PAT) {
1668 for (i = 0; i < 8; i++)
1669 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1670 return false;
1671 return true;
1672 } else if (msr == MSR_MTRRdefType) {
1673 if (data & ~0xcff)
1674 return false;
1675 return valid_mtrr_type(data & 0xff);
1676 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1677 for (i = 0; i < 8 ; i++)
1678 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1679 return false;
1680 return true;
1681 }
1682
1683 /* variable MTRRs */
1684 return valid_mtrr_type(data & 0xff);
1685}
1686
9ba075a6
AK		 1687static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1688{
0bed3b56
SY		 1689 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1690
d6289b93 1691 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1692 return 1;
1693
0bed3b56
SY		 1694 if (msr == MSR_MTRRdefType) {
1695 vcpu->arch.mtrr_state.def_type = data;
1696 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1697 } else if (msr == MSR_MTRRfix64K_00000)
1698 p[0] = data;
1699 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1700 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1701 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1702 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1703 else if (msr == MSR_IA32_CR_PAT)
1704 vcpu->arch.pat = data;
1705 else { /* Variable MTRRs */
1706 int idx, is_mtrr_mask;
1707 u64 *pt;
1708
1709 idx = (msr - 0x200) / 2;
1710 is_mtrr_mask = msr - 0x200 - 2 * idx;
1711 if (!is_mtrr_mask)
1712 pt =
1713 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1714 else
1715 pt =
1716 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1717 *pt = data;
1718 }
1719
1720 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1721 return 0;
1722}
15c4a640 1723
890ca9ae 1724static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1725{
890ca9ae
HY		 1726 u64 mcg_cap = vcpu->arch.mcg_cap;
1727 unsigned bank_num = mcg_cap & 0xff;
1728
15c4a640 1729 switch (msr) {
15c4a640 1730 case MSR_IA32_MCG_STATUS:
890ca9ae 1731 vcpu->arch.mcg_status = data;
15c4a640 1732 break;
c7ac679c 1733 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1734 if (!(mcg_cap & MCG_CTL_P))
1735 return 1;
1736 if (data != 0 && data != ~(u64)0)
1737 return -1;
1738 vcpu->arch.mcg_ctl = data;
1739 break;
1740 default:
1741 if (msr >= MSR_IA32_MC0_CTL &&
1742 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1743 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1744 /* only 0 or all 1s can be written to IA32_MCi_CTL
1745 * some Linux kernels though clear bit 10 in bank 4 to
1746 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1747 * this to avoid an uncatched #GP in the guest
1748 */
890ca9ae 1749 if ((offset & 0x3) == 0 &&
114be429 1750 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1751 return -1;
1752 vcpu->arch.mce_banks[offset] = data;
1753 break;
1754 }
1755 return 1;
1756 }
1757 return 0;
1758}
1759
ffde22ac
ES		 1760static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1761{
1762 struct kvm *kvm = vcpu->kvm;
1763 int lm = is_long_mode(vcpu);
1764 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1765 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1766 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1767 : kvm->arch.xen_hvm_config.blob_size_32;
1768 u32 page_num = data & ~PAGE_MASK;
1769 u64 page_addr = data & PAGE_MASK;
1770 u8 *page;
1771 int r;
1772
1773 r = -E2BIG;
1774 if (page_num >= blob_size)
1775 goto out;
1776 r = -ENOMEM;
ff5c2c03
SL		 1777 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1778 if (IS_ERR(page)) {
1779 r = PTR_ERR(page);
ffde22ac 1780 goto out;
ff5c2c03 1781 }
ffde22ac
ES		 1782 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1783 goto out_free;
1784 r = 0;
1785out_free:
1786 kfree(page);
1787out:
1788 return r;
1789}
1790
55cd8e5a
GN		 1791static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1792{
1793 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1794}
1795
1796static bool kvm_hv_msr_partition_wide(u32 msr)
1797{
1798 bool r = false;
1799 switch (msr) {
1800 case HV_X64_MSR_GUEST_OS_ID:
1801 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1802 case HV_X64_MSR_REFERENCE_TSC:
1803 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1804 r = true;
1805 break;
1806 }
1807
1808 return r;
1809}
1810
1811static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1812{
1813 struct kvm *kvm = vcpu->kvm;
1814
1815 switch (msr) {
1816 case HV_X64_MSR_GUEST_OS_ID:
1817 kvm->arch.hv_guest_os_id = data;
1818 /* setting guest os id to zero disables hypercall page */
1819 if (!kvm->arch.hv_guest_os_id)
1820 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1821 break;
1822 case HV_X64_MSR_HYPERCALL: {
1823 u64 gfn;
1824 unsigned long addr;
1825 u8 instructions[4];
1826
1827 /* if guest os id is not set hypercall should remain disabled */
1828 if (!kvm->arch.hv_guest_os_id)
1829 break;
1830 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1831 kvm->arch.hv_hypercall = data;
1832 break;
1833 }
1834 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1835 addr = gfn_to_hva(kvm, gfn);
1836 if (kvm_is_error_hva(addr))
1837 return 1;
1838 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1839 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1840 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1841 return 1;
1842 kvm->arch.hv_hypercall = data;
b94b64c9 1843 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1844 break;
1845 }
e984097b
VR		 1846 case HV_X64_MSR_REFERENCE_TSC: {
1847 u64 gfn;
1848 HV_REFERENCE_TSC_PAGE tsc_ref;
1849 memset(&tsc_ref, 0, sizeof(tsc_ref));
1850 kvm->arch.hv_tsc_page = data;
1851 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1852 break;
1853 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1854 if (kvm_write_guest(kvm, data,
1855 &tsc_ref, sizeof(tsc_ref)))
1856 return 1;
1857 mark_page_dirty(kvm, gfn);
1858 break;
1859 }
55cd8e5a 1860 default:
a737f256
CD		 1861 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1862 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1863 return 1;
1864 }
1865 return 0;
1866}
1867
1868static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1869{
10388a07
GN		 1870 switch (msr) {
1871 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1872 u64 gfn;
10388a07 1873 unsigned long addr;
55cd8e5a 1874
10388a07
GN		 1875 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1876 vcpu->arch.hv_vapic = data;
1877 break;
1878 }
b3af1e88
VR		 1879 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1880 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1881 if (kvm_is_error_hva(addr))
1882 return 1;
8b0cedff 1883 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1884 return 1;
1885 vcpu->arch.hv_vapic = data;
b3af1e88 1886 mark_page_dirty(vcpu->kvm, gfn);
10388a07
GN		 1887 break;
1888 }
1889 case HV_X64_MSR_EOI:
1890 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1891 case HV_X64_MSR_ICR:
1892 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1893 case HV_X64_MSR_TPR:
1894 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1895 default:
a737f256
CD		 1896 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1897 "data 0x%llx\n", msr, data);
10388a07
GN		 1898 return 1;
1899 }
1900
1901 return 0;
55cd8e5a
GN		 1902}
1903
344d9588
GN		 1904static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1905{
1906 gpa_t gpa = data & ~0x3f;
1907
4a969980 1908 /* Bits 2:5 are reserved, Should be zero */
6adba527 1909 if (data & 0x3c)
344d9588
GN		 1910 return 1;
1911
1912 vcpu->arch.apf.msr_val = data;
1913
1914 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1915 kvm_clear_async_pf_completion_queue(vcpu);
1916 kvm_async_pf_hash_reset(vcpu);
1917 return 0;
1918 }
1919
8f964525
AH		 1920 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1921 sizeof(u32)))
344d9588
GN		 1922 return 1;
1923
6adba527 1924 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1925 kvm_async_pf_wakeup_all(vcpu);
1926 return 0;
1927}
1928
12f9a48f
GC		 1929static void kvmclock_reset(struct kvm_vcpu *vcpu)
1930{
0b79459b 1931 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1932}
1933
c9aaa895
GC		 1934static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1935{
1936 u64 delta;
1937
1938 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1939 return;
1940
1941 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1942 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1943 vcpu->arch.st.accum_steal = delta;
1944}
1945
1946static void record_steal_time(struct kvm_vcpu *vcpu)
1947{
1948 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1949 return;
1950
1951 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1952 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1953 return;
1954
1955 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1956 vcpu->arch.st.steal.version += 2;
1957 vcpu->arch.st.accum_steal = 0;
1958
1959 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1960 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1961}
1962
8fe8ab46 1963int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1964{
5753785f 1965 bool pr = false;
8fe8ab46
WA		 1966 u32 msr = msr_info->index;
1967 u64 data = msr_info->data;
5753785f 1968
15c4a640 1969 switch (msr) {
2e32b719
BP		 1970 case MSR_AMD64_NB_CFG:
1971 case MSR_IA32_UCODE_REV:
1972 case MSR_IA32_UCODE_WRITE:
1973 case MSR_VM_HSAVE_PA:
1974 case MSR_AMD64_PATCH_LOADER:
1975 case MSR_AMD64_BU_CFG2:
1976 break;
1977
15c4a640 1978 case MSR_EFER:
b69e8cae 1979 return set_efer(vcpu, data);
8f1589d9
AP		 1980 case MSR_K7_HWCR:
1981 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1982 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1983 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1984 if (data != 0) {
a737f256
CD		 1985 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1986 data);
8f1589d9
AP		 1987 return 1;
1988 }
15c4a640 1989 break;
f7c6d140
AP		 1990 case MSR_FAM10H_MMIO_CONF_BASE:
1991 if (data != 0) {
a737f256
CD		 1992 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1993 "0x%llx\n", data);
f7c6d140
AP		 1994 return 1;
1995 }
15c4a640 1996 break;
b5e2fec0
AG		 1997 case MSR_IA32_DEBUGCTLMSR:
1998 if (!data) {
1999 /* We support the non-activated case already */
2000 break;
2001 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2002 /* Values other than LBR and BTF are vendor-specific,
2003 thus reserved and should throw a #GP */
2004 return 1;
2005 }
a737f256
CD		 2006 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2007 __func__, data);
b5e2fec0 2008 break;
9ba075a6
AK		 2009 case 0x200 ... 0x2ff:
2010 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 2011 case MSR_IA32_APICBASE:
2012 kvm_set_apic_base(vcpu, data);
2013 break;
0105d1a5
GN		 2014 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2015 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2016 case MSR_IA32_TSCDEADLINE:
2017 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2018 break;
ba904635
WA		 2019 case MSR_IA32_TSC_ADJUST:
2020 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2021 if (!msr_info->host_initiated) {
2022 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2023 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2024 }
2025 vcpu->arch.ia32_tsc_adjust_msr = data;
2026 }
2027 break;
15c4a640 2028 case MSR_IA32_MISC_ENABLE:
ad312c7c 2029 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2030 break;
11c6bffa 2031 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2032 case MSR_KVM_WALL_CLOCK:
2033 vcpu->kvm->arch.wall_clock = data;
2034 kvm_write_wall_clock(vcpu->kvm, data);
2035 break;
11c6bffa 2036 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2037 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2038 u64 gpa_offset;
12f9a48f 2039 kvmclock_reset(vcpu);
18068523
GOC		 2040
2041 vcpu->arch.time = data;
0061d53d 2042 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2043
2044 /* we verify if the enable bit is set... */
2045 if (!(data & 1))
2046 break;
2047
0b79459b 2048 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2049
0b79459b 2050 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2051 &vcpu->arch.pv_time, data & ~1ULL,
2052 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2053 vcpu->arch.pv_time_enabled = false;
2054 else
2055 vcpu->arch.pv_time_enabled = true;
32cad84f 2056
18068523
GOC		 2057 break;
2058 }
344d9588
GN		 2059 case MSR_KVM_ASYNC_PF_EN:
2060 if (kvm_pv_enable_async_pf(vcpu, data))
2061 return 1;
2062 break;
c9aaa895
GC		 2063 case MSR_KVM_STEAL_TIME:
2064
2065 if (unlikely(!sched_info_on()))
2066 return 1;
2067
2068 if (data & KVM_STEAL_RESERVED_MASK)
2069 return 1;
2070
2071 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2072 data & KVM_STEAL_VALID_BITS,
2073 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2074 return 1;
2075
2076 vcpu->arch.st.msr_val = data;
2077
2078 if (!(data & KVM_MSR_ENABLED))
2079 break;
2080
2081 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2082
2083 preempt_disable();
2084 accumulate_steal_time(vcpu);
2085 preempt_enable();
2086
2087 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2088
2089 break;
ae7a2a3f
MT		 2090 case MSR_KVM_PV_EOI_EN:
2091 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2092 return 1;
2093 break;
c9aaa895 2094
890ca9ae
HY		 2095 case MSR_IA32_MCG_CTL:
2096 case MSR_IA32_MCG_STATUS:
2097 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2098 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2099
2100 /* Performance counters are not protected by a CPUID bit,
2101 * so we should check all of them in the generic path for the sake of
2102 * cross vendor migration.
2103 * Writing a zero into the event select MSRs disables them,
2104 * which we perfectly emulate ;-). Any other value should be at least
2105 * reported, some guests depend on them.
2106 */
71db6023
AP		 2107 case MSR_K7_EVNTSEL0:
2108 case MSR_K7_EVNTSEL1:
2109 case MSR_K7_EVNTSEL2:
2110 case MSR_K7_EVNTSEL3:
2111 if (data != 0)
a737f256
CD		 2112 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2113 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2114 break;
2115 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2116 * so we ignore writes to make it happy.
2117 */
71db6023
AP		 2118 case MSR_K7_PERFCTR0:
2119 case MSR_K7_PERFCTR1:
2120 case MSR_K7_PERFCTR2:
2121 case MSR_K7_PERFCTR3:
a737f256
CD		 2122 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2123 "0x%x data 0x%llx\n", msr, data);
71db6023 2124 break;
5753785f
GN		 2125 case MSR_P6_PERFCTR0:
2126 case MSR_P6_PERFCTR1:
2127 pr = true;
2128 case MSR_P6_EVNTSEL0:
2129 case MSR_P6_EVNTSEL1:
2130 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2131 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2132
2133 if (pr || data != 0)
a737f256
CD		 2134 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2135 "0x%x data 0x%llx\n", msr, data);
5753785f 2136 break;
84e0cefa
JS		 2137 case MSR_K7_CLK_CTL:
2138 /*
2139 * Ignore all writes to this no longer documented MSR.
2140 * Writes are only relevant for old K7 processors,
2141 * all pre-dating SVM, but a recommended workaround from
4a969980 2142 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2143 * affected processor models on the command line, hence
2144 * the need to ignore the workaround.
2145 */
2146 break;
55cd8e5a
GN		 2147 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2148 if (kvm_hv_msr_partition_wide(msr)) {
2149 int r;
2150 mutex_lock(&vcpu->kvm->lock);
2151 r = set_msr_hyperv_pw(vcpu, msr, data);
2152 mutex_unlock(&vcpu->kvm->lock);
2153 return r;
2154 } else
2155 return set_msr_hyperv(vcpu, msr, data);
2156 break;
91c9c3ed 2157 case MSR_IA32_BBL_CR_CTL3:
2158 /* Drop writes to this legacy MSR -- see rdmsr
2159 * counterpart for further detail.
2160 */
a737f256 2161 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2162 break;
2b036c6b
BO		 2163 case MSR_AMD64_OSVW_ID_LENGTH:
2164 if (!guest_cpuid_has_osvw(vcpu))
2165 return 1;
2166 vcpu->arch.osvw.length = data;
2167 break;
2168 case MSR_AMD64_OSVW_STATUS:
2169 if (!guest_cpuid_has_osvw(vcpu))
2170 return 1;
2171 vcpu->arch.osvw.status = data;
2172 break;
15c4a640 2173 default:
ffde22ac
ES		 2174 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2175 return xen_hvm_config(vcpu, data);
f5132b01 2176 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2177 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2178 if (!ignore_msrs) {
a737f256
CD		 2179 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2180 msr, data);
ed85c068
AP		 2181 return 1;
2182 } else {
a737f256
CD		 2183 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2184 msr, data);
ed85c068
AP		 2185 break;
2186 }
15c4a640
CO		 2187 }
2188 return 0;
2189}
2190EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2191
2192
2193/*
2194 * Reads an msr value (of 'msr_index') into 'pdata'.
2195 * Returns 0 on success, non-0 otherwise.
2196 * Assumes vcpu_load() was already called.
2197 */
2198int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2199{
2200 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2201}
2202
9ba075a6
AK		 2203static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2204{
0bed3b56
SY		 2205 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2206
9ba075a6
AK		 2207 if (!msr_mtrr_valid(msr))
2208 return 1;
2209
0bed3b56
SY		 2210 if (msr == MSR_MTRRdefType)
2211 *pdata = vcpu->arch.mtrr_state.def_type +
2212 (vcpu->arch.mtrr_state.enabled << 10);
2213 else if (msr == MSR_MTRRfix64K_00000)
2214 *pdata = p[0];
2215 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2216 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2217 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2218 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2219 else if (msr == MSR_IA32_CR_PAT)
2220 *pdata = vcpu->arch.pat;
2221 else { /* Variable MTRRs */
2222 int idx, is_mtrr_mask;
2223 u64 *pt;
2224
2225 idx = (msr - 0x200) / 2;
2226 is_mtrr_mask = msr - 0x200 - 2 * idx;
2227 if (!is_mtrr_mask)
2228 pt =
2229 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2230 else
2231 pt =
2232 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2233 *pdata = *pt;
2234 }
2235
9ba075a6
AK		 2236 return 0;
2237}
2238
890ca9ae 2239static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2240{
2241 u64 data;
890ca9ae
HY		 2242 u64 mcg_cap = vcpu->arch.mcg_cap;
2243 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2244
2245 switch (msr) {
15c4a640
CO		 2246 case MSR_IA32_P5_MC_ADDR:
2247 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2248 data = 0;
2249 break;
15c4a640 2250 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2251 data = vcpu->arch.mcg_cap;
2252 break;
c7ac679c 2253 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2254 if (!(mcg_cap & MCG_CTL_P))
2255 return 1;
2256 data = vcpu->arch.mcg_ctl;
2257 break;
2258 case MSR_IA32_MCG_STATUS:
2259 data = vcpu->arch.mcg_status;
2260 break;
2261 default:
2262 if (msr >= MSR_IA32_MC0_CTL &&
2263 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2264 u32 offset = msr - MSR_IA32_MC0_CTL;
2265 data = vcpu->arch.mce_banks[offset];
2266 break;
2267 }
2268 return 1;
2269 }
2270 *pdata = data;
2271 return 0;
2272}
2273
55cd8e5a
GN		 2274static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2275{
2276 u64 data = 0;
2277 struct kvm *kvm = vcpu->kvm;
2278
2279 switch (msr) {
2280 case HV_X64_MSR_GUEST_OS_ID:
2281 data = kvm->arch.hv_guest_os_id;
2282 break;
2283 case HV_X64_MSR_HYPERCALL:
2284 data = kvm->arch.hv_hypercall;
2285 break;
e984097b
VR		 2286 case HV_X64_MSR_TIME_REF_COUNT: {
2287 data =
2288 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2289 break;
2290 }
2291 case HV_X64_MSR_REFERENCE_TSC:
2292 data = kvm->arch.hv_tsc_page;
2293 break;
55cd8e5a 2294 default:
a737f256 2295 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2296 return 1;
2297 }
2298
2299 *pdata = data;
2300 return 0;
2301}
2302
2303static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2304{
2305 u64 data = 0;
2306
2307 switch (msr) {
2308 case HV_X64_MSR_VP_INDEX: {
2309 int r;
2310 struct kvm_vcpu *v;
2311 kvm_for_each_vcpu(r, v, vcpu->kvm)
2312 if (v == vcpu)
2313 data = r;
2314 break;
2315 }
10388a07
GN		 2316 case HV_X64_MSR_EOI:
2317 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2318 case HV_X64_MSR_ICR:
2319 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2320 case HV_X64_MSR_TPR:
2321 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2322 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2323 data = vcpu->arch.hv_vapic;
2324 break;
55cd8e5a 2325 default:
a737f256 2326 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2327 return 1;
2328 }
2329 *pdata = data;
2330 return 0;
2331}
2332
890ca9ae
HY		 2333int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2334{
2335 u64 data;
2336
2337 switch (msr) {
890ca9ae 2338 case MSR_IA32_PLATFORM_ID:
15c4a640 2339 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2340 case MSR_IA32_DEBUGCTLMSR:
2341 case MSR_IA32_LASTBRANCHFROMIP:
2342 case MSR_IA32_LASTBRANCHTOIP:
2343 case MSR_IA32_LASTINTFROMIP:
2344 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2345 case MSR_K8_SYSCFG:
2346 case MSR_K7_HWCR:
61a6bd67 2347 case MSR_VM_HSAVE_PA:
9e699624 2348 case MSR_K7_EVNTSEL0:
1f3ee616 2349 case MSR_K7_PERFCTR0:
1fdbd48c 2350 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2351 case MSR_AMD64_NB_CFG:
f7c6d140 2352 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2353 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2354 data = 0;
2355 break;
5753785f
GN		 2356 case MSR_P6_PERFCTR0:
2357 case MSR_P6_PERFCTR1:
2358 case MSR_P6_EVNTSEL0:
2359 case MSR_P6_EVNTSEL1:
2360 if (kvm_pmu_msr(vcpu, msr))
2361 return kvm_pmu_get_msr(vcpu, msr, pdata);
2362 data = 0;
2363 break;
742bc670
MT		 2364 case MSR_IA32_UCODE_REV:
2365 data = 0x100000000ULL;
2366 break;
9ba075a6
AK		 2367 case MSR_MTRRcap:
2368 data = 0x500 | KVM_NR_VAR_MTRR;
2369 break;
2370 case 0x200 ... 0x2ff:
2371 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2372 case 0xcd: /* fsb frequency */
2373 data = 3;
2374 break;
7b914098
JS		 2375 /*
2376 * MSR_EBC_FREQUENCY_ID
2377 * Conservative value valid for even the basic CPU models.
2378 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2379 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2380 * and 266MHz for model 3, or 4. Set Core Clock
2381 * Frequency to System Bus Frequency Ratio to 1 (bits
2382 * 31:24) even though these are only valid for CPU
2383 * models > 2, however guests may end up dividing or
2384 * multiplying by zero otherwise.
2385 */
2386 case MSR_EBC_FREQUENCY_ID:
2387 data = 1 << 24;
2388 break;
15c4a640
CO		 2389 case MSR_IA32_APICBASE:
2390 data = kvm_get_apic_base(vcpu);
2391 break;
0105d1a5
GN		 2392 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2393 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2394 break;
a3e06bbe
LJ		 2395 case MSR_IA32_TSCDEADLINE:
2396 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2397 break;
ba904635
WA		 2398 case MSR_IA32_TSC_ADJUST:
2399 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2400 break;
15c4a640 2401 case MSR_IA32_MISC_ENABLE:
ad312c7c 2402 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2403 break;
847f0ad8
AG		 2404 case MSR_IA32_PERF_STATUS:
2405 /* TSC increment by tick */
2406 data = 1000ULL;
2407 /* CPU multiplier */
2408 data |= (((uint64_t)4ULL) << 40);
2409 break;
15c4a640 2410 case MSR_EFER:
f6801dff 2411 data = vcpu->arch.efer;
15c4a640 2412 break;
18068523 2413 case MSR_KVM_WALL_CLOCK:
11c6bffa 2414 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2415 data = vcpu->kvm->arch.wall_clock;
2416 break;
2417 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2418 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2419 data = vcpu->arch.time;
2420 break;
344d9588
GN		 2421 case MSR_KVM_ASYNC_PF_EN:
2422 data = vcpu->arch.apf.msr_val;
2423 break;
c9aaa895
GC		 2424 case MSR_KVM_STEAL_TIME:
2425 data = vcpu->arch.st.msr_val;
2426 break;
1d92128f
MT		 2427 case MSR_KVM_PV_EOI_EN:
2428 data = vcpu->arch.pv_eoi.msr_val;
2429 break;
890ca9ae
HY		 2430 case MSR_IA32_P5_MC_ADDR:
2431 case MSR_IA32_P5_MC_TYPE:
2432 case MSR_IA32_MCG_CAP:
2433 case MSR_IA32_MCG_CTL:
2434 case MSR_IA32_MCG_STATUS:
2435 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2436 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2437 case MSR_K7_CLK_CTL:
2438 /*
2439 * Provide expected ramp-up count for K7. All other
2440 * are set to zero, indicating minimum divisors for
2441 * every field.
2442 *
2443 * This prevents guest kernels on AMD host with CPU
2444 * type 6, model 8 and higher from exploding due to
2445 * the rdmsr failing.
2446 */
2447 data = 0x20000000;
2448 break;
55cd8e5a
GN		 2449 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2450 if (kvm_hv_msr_partition_wide(msr)) {
2451 int r;
2452 mutex_lock(&vcpu->kvm->lock);
2453 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2454 mutex_unlock(&vcpu->kvm->lock);
2455 return r;
2456 } else
2457 return get_msr_hyperv(vcpu, msr, pdata);
2458 break;
91c9c3ed 2459 case MSR_IA32_BBL_CR_CTL3:
2460 /* This legacy MSR exists but isn't fully documented in current
2461 * silicon. It is however accessed by winxp in very narrow
2462 * scenarios where it sets bit #19, itself documented as
2463 * a "reserved" bit. Best effort attempt to source coherent
2464 * read data here should the balance of the register be
2465 * interpreted by the guest:
2466 *
2467 * L2 cache control register 3: 64GB range, 256KB size,
2468 * enabled, latency 0x1, configured
2469 */
2470 data = 0xbe702111;
2471 break;
2b036c6b
BO		 2472 case MSR_AMD64_OSVW_ID_LENGTH:
2473 if (!guest_cpuid_has_osvw(vcpu))
2474 return 1;
2475 data = vcpu->arch.osvw.length;
2476 break;
2477 case MSR_AMD64_OSVW_STATUS:
2478 if (!guest_cpuid_has_osvw(vcpu))
2479 return 1;
2480 data = vcpu->arch.osvw.status;
2481 break;
15c4a640 2482 default:
f5132b01
GN		 2483 if (kvm_pmu_msr(vcpu, msr))
2484 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2485 if (!ignore_msrs) {
a737f256 2486 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2487 return 1;
2488 } else {
a737f256 2489 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2490 data = 0;
2491 }
2492 break;
15c4a640
CO		 2493 }
2494 *pdata = data;
2495 return 0;
2496}
2497EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2498
313a3dc7
CO		 2499/*
2500 * Read or write a bunch of msrs. All parameters are kernel addresses.
2501 *
2502 * @return number of msrs set successfully.
2503 */
2504static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2505 struct kvm_msr_entry *entries,
2506 int (*do_msr)(struct kvm_vcpu *vcpu,
2507 unsigned index, u64 *data))
2508{
f656ce01 2509 int i, idx;
313a3dc7 2510
f656ce01 2511 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2512 for (i = 0; i < msrs->nmsrs; ++i)
2513 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2514 break;
f656ce01 2515 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2516
313a3dc7
CO		 2517 return i;
2518}
2519
2520/*
2521 * Read or write a bunch of msrs. Parameters are user addresses.
2522 *
2523 * @return number of msrs set successfully.
2524 */
2525static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2526 int (*do_msr)(struct kvm_vcpu *vcpu,
2527 unsigned index, u64 *data),
2528 int writeback)
2529{
2530 struct kvm_msrs msrs;
2531 struct kvm_msr_entry *entries;
2532 int r, n;
2533 unsigned size;
2534
2535 r = -EFAULT;
2536 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2537 goto out;
2538
2539 r = -E2BIG;
2540 if (msrs.nmsrs >= MAX_IO_MSRS)
2541 goto out;
2542
313a3dc7 2543 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2544 entries = memdup_user(user_msrs->entries, size);
2545 if (IS_ERR(entries)) {
2546 r = PTR_ERR(entries);
313a3dc7 2547 goto out;
ff5c2c03 2548 }
313a3dc7
CO		 2549
2550 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2551 if (r < 0)
2552 goto out_free;
2553
2554 r = -EFAULT;
2555 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2556 goto out_free;
2557
2558 r = n;
2559
2560out_free:
7a73c028 2561 kfree(entries);
313a3dc7
CO		 2562out:
2563 return r;
2564}
2565
018d00d2
ZX		 2566int kvm_dev_ioctl_check_extension(long ext)
2567{
2568 int r;
2569
2570 switch (ext) {
2571 case KVM_CAP_IRQCHIP:
2572 case KVM_CAP_HLT:
2573 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2574 case KVM_CAP_SET_TSS_ADDR:
07716717 2575 case KVM_CAP_EXT_CPUID:
9c15bb1d 2576 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2577 case KVM_CAP_CLOCKSOURCE:
7837699f 2578 case KVM_CAP_PIT:
a28e4f5a 2579 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2580 case KVM_CAP_MP_STATE:
ed848624 2581 case KVM_CAP_SYNC_MMU:
a355c85c 2582 case KVM_CAP_USER_NMI:
52d939a0 2583 case KVM_CAP_REINJECT_CONTROL:
4925663a 2584 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2585 case KVM_CAP_IRQFD:
d34e6b17 2586 case KVM_CAP_IOEVENTFD:
c5ff41ce 2587 case KVM_CAP_PIT2:
e9f42757 2588 case KVM_CAP_PIT_STATE2:
b927a3ce 2589 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2590 case KVM_CAP_XEN_HVM:
afbcf7ab 2591 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2592 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2593 case KVM_CAP_HYPERV:
10388a07 2594 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2595 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2596 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2597 case KVM_CAP_DEBUGREGS:
d2be1651 2598 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2599 case KVM_CAP_XSAVE:
344d9588 2600 case KVM_CAP_ASYNC_PF:
92a1f12d 2601 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2602 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2603 case KVM_CAP_READONLY_MEM:
2a5bab10
AW		 2604#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2605 case KVM_CAP_ASSIGN_DEV_IRQ:
2606 case KVM_CAP_PCI_2_3:
e984097b 2607 case KVM_CAP_HYPERV_TIME:
2a5bab10 2608#endif
018d00d2
ZX		 2609 r = 1;
2610 break;
542472b5
LV		 2611 case KVM_CAP_COALESCED_MMIO:
2612 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2613 break;
774ead3a
AK		 2614 case KVM_CAP_VAPIC:
2615 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2616 break;
f725230a 2617 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2618 r = KVM_SOFT_MAX_VCPUS;
2619 break;
2620 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2621 r = KVM_MAX_VCPUS;
2622 break;
a988b910 2623 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2624 r = KVM_USER_MEM_SLOTS;
a988b910 2625 break;
a68a6a72
MT		 2626 case KVM_CAP_PV_MMU: /* obsolete */
2627 r = 0;
2f333bcb 2628 break;
4cee4b72 2629#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2630 case KVM_CAP_IOMMU:
a1b60c1c 2631 r = iommu_present(&pci_bus_type);
62c476c7 2632 break;
4cee4b72 2633#endif
890ca9ae
HY		 2634 case KVM_CAP_MCE:
2635 r = KVM_MAX_MCE_BANKS;
2636 break;
2d5b5a66
SY		 2637 case KVM_CAP_XCRS:
2638 r = cpu_has_xsave;
2639 break;
92a1f12d
JR		 2640 case KVM_CAP_TSC_CONTROL:
2641 r = kvm_has_tsc_control;
2642 break;
4d25a066
JK		 2643 case KVM_CAP_TSC_DEADLINE_TIMER:
2644 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2645 break;
018d00d2
ZX		 2646 default:
2647 r = 0;
2648 break;
2649 }
2650 return r;
2651
2652}
2653
043405e1
CO		 2654long kvm_arch_dev_ioctl(struct file *filp,
2655 unsigned int ioctl, unsigned long arg)
2656{
2657 void __user *argp = (void __user *)arg;
2658 long r;
2659
2660 switch (ioctl) {
2661 case KVM_GET_MSR_INDEX_LIST: {
2662 struct kvm_msr_list __user *user_msr_list = argp;
2663 struct kvm_msr_list msr_list;
2664 unsigned n;
2665
2666 r = -EFAULT;
2667 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2668 goto out;
2669 n = msr_list.nmsrs;
2670 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2671 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2672 goto out;
2673 r = -E2BIG;
e125e7b6 2674 if (n < msr_list.nmsrs)
043405e1
CO		 2675 goto out;
2676 r = -EFAULT;
2677 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2678 num_msrs_to_save * sizeof(u32)))
2679 goto out;
e125e7b6 2680 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2681 &emulated_msrs,
2682 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2683 goto out;
2684 r = 0;
2685 break;
2686 }
9c15bb1d
BP		 2687 case KVM_GET_SUPPORTED_CPUID:
2688 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2689 struct kvm_cpuid2 __user *cpuid_arg = argp;
2690 struct kvm_cpuid2 cpuid;
2691
2692 r = -EFAULT;
2693 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2694 goto out;
9c15bb1d
BP		 2695
2696 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2697 ioctl);
674eea0f
AK		 2698 if (r)
2699 goto out;
2700
2701 r = -EFAULT;
2702 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2703 goto out;
2704 r = 0;
2705 break;
2706 }
890ca9ae
HY		 2707 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2708 u64 mce_cap;
2709
2710 mce_cap = KVM_MCE_CAP_SUPPORTED;
2711 r = -EFAULT;
2712 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2713 goto out;
2714 r = 0;
2715 break;
2716 }
043405e1
CO		 2717 default:
2718 r = -EINVAL;
2719 }
2720out:
2721 return r;
2722}
2723
f5f48ee1
SY		 2724static void wbinvd_ipi(void *garbage)
2725{
2726 wbinvd();
2727}
2728
2729static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2730{
e0f0bbc5 2731 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2732}
2733
313a3dc7
CO		 2734void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2735{
f5f48ee1
SY		 2736 /* Address WBINVD may be executed by guest */
2737 if (need_emulate_wbinvd(vcpu)) {
2738 if (kvm_x86_ops->has_wbinvd_exit())
2739 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2740 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2741 smp_call_function_single(vcpu->cpu,
2742 wbinvd_ipi, NULL, 1);
2743 }
2744
313a3dc7 2745 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2746
0dd6a6ed
ZA		 2747 /* Apply any externally detected TSC adjustments (due to suspend) */
2748 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2749 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2750 vcpu->arch.tsc_offset_adjustment = 0;
2751 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2752 }
8f6055cb 2753
48434c20 2754 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2755 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2756 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2757 if (tsc_delta < 0)
2758 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2759 if (check_tsc_unstable()) {
b183aa58
ZA		 2760 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2761 vcpu->arch.last_guest_tsc);
2762 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2763 vcpu->arch.tsc_catchup = 1;
c285545f 2764 }
d98d07ca
MT		 2765 /*
2766 * On a host with synchronized TSC, there is no need to update
2767 * kvmclock on vcpu->cpu migration
2768 */
2769 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2770 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2771 if (vcpu->cpu != cpu)
2772 kvm_migrate_timers(vcpu);
e48672fa 2773 vcpu->cpu = cpu;
6b7d7e76 2774 }
c9aaa895
GC		 2775
2776 accumulate_steal_time(vcpu);
2777 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2778}
2779
2780void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2781{
02daab21 2782 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2783 kvm_put_guest_fpu(vcpu);
6f526ec5 2784 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2785}
2786
313a3dc7
CO		 2787static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2788 struct kvm_lapic_state *s)
2789{
5a71785d 2790 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2791 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2792
2793 return 0;
2794}
2795
2796static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2797 struct kvm_lapic_state *s)
2798{
64eb0620 2799 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2800 update_cr8_intercept(vcpu);
313a3dc7
CO		 2801
2802 return 0;
2803}
2804
f77bc6a4
ZX		 2805static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2806 struct kvm_interrupt *irq)
2807{
02cdb50f 2808 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2809 return -EINVAL;
2810 if (irqchip_in_kernel(vcpu->kvm))
2811 return -ENXIO;
f77bc6a4 2812
66fd3f7f 2813 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2814 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2815
f77bc6a4
ZX		 2816 return 0;
2817}
2818
c4abb7c9
JK		 2819static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2820{
c4abb7c9 2821 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2822
2823 return 0;
2824}
2825
b209749f
AK		 2826static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2827 struct kvm_tpr_access_ctl *tac)
2828{
2829 if (tac->flags)
2830 return -EINVAL;
2831 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2832 return 0;
2833}
2834
890ca9ae
HY		 2835static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2836 u64 mcg_cap)
2837{
2838 int r;
2839 unsigned bank_num = mcg_cap & 0xff, bank;
2840
2841 r = -EINVAL;
a9e38c3e 2842 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2843 goto out;
2844 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2845 goto out;
2846 r = 0;
2847 vcpu->arch.mcg_cap = mcg_cap;
2848 /* Init IA32_MCG_CTL to all 1s */
2849 if (mcg_cap & MCG_CTL_P)
2850 vcpu->arch.mcg_ctl = ~(u64)0;
2851 /* Init IA32_MCi_CTL to all 1s */
2852 for (bank = 0; bank < bank_num; bank++)
2853 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2854out:
2855 return r;
2856}
2857
2858static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2859 struct kvm_x86_mce *mce)
2860{
2861 u64 mcg_cap = vcpu->arch.mcg_cap;
2862 unsigned bank_num = mcg_cap & 0xff;
2863 u64 *banks = vcpu->arch.mce_banks;
2864
2865 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2866 return -EINVAL;
2867 /*
2868 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2869 * reporting is disabled
2870 */
2871 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2872 vcpu->arch.mcg_ctl != ~(u64)0)
2873 return 0;
2874 banks += 4 * mce->bank;
2875 /*
2876 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2877 * reporting is disabled for the bank
2878 */
2879 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2880 return 0;
2881 if (mce->status & MCI_STATUS_UC) {
2882 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2883 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2884 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2885 return 0;
2886 }
2887 if (banks[1] & MCI_STATUS_VAL)
2888 mce->status |= MCI_STATUS_OVER;
2889 banks[2] = mce->addr;
2890 banks[3] = mce->misc;
2891 vcpu->arch.mcg_status = mce->mcg_status;
2892 banks[1] = mce->status;
2893 kvm_queue_exception(vcpu, MC_VECTOR);
2894 } else if (!(banks[1] & MCI_STATUS_VAL)
2895 || !(banks[1] & MCI_STATUS_UC)) {
2896 if (banks[1] & MCI_STATUS_VAL)
2897 mce->status |= MCI_STATUS_OVER;
2898 banks[2] = mce->addr;
2899 banks[3] = mce->misc;
2900 banks[1] = mce->status;
2901 } else
2902 banks[1] |= MCI_STATUS_OVER;
2903 return 0;
2904}
2905
3cfc3092
JK		 2906static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2907 struct kvm_vcpu_events *events)
2908{
7460fb4a 2909 process_nmi(vcpu);
03b82a30
JK		 2910 events->exception.injected =
2911 vcpu->arch.exception.pending &&
2912 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2913 events->exception.nr = vcpu->arch.exception.nr;
2914 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2915 events->exception.pad = 0;
3cfc3092
JK		 2916 events->exception.error_code = vcpu->arch.exception.error_code;
2917
03b82a30
JK		 2918 events->interrupt.injected =
2919 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2920 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2921 events->interrupt.soft = 0;
48005f64
JK		 2922 events->interrupt.shadow =
2923 kvm_x86_ops->get_interrupt_shadow(vcpu,
2924 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2925
2926 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2927 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2928 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2929 events->nmi.pad = 0;
3cfc3092 2930
66450a21 2931 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2932
dab4b911 2933 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2934 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2935 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2936}
2937
2938static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2939 struct kvm_vcpu_events *events)
2940{
dab4b911 2941 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2942 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2943 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2944 return -EINVAL;
2945
7460fb4a 2946 process_nmi(vcpu);
3cfc3092
JK		 2947 vcpu->arch.exception.pending = events->exception.injected;
2948 vcpu->arch.exception.nr = events->exception.nr;
2949 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2950 vcpu->arch.exception.error_code = events->exception.error_code;
2951
2952 vcpu->arch.interrupt.pending = events->interrupt.injected;
2953 vcpu->arch.interrupt.nr = events->interrupt.nr;
2954 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2955 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2956 kvm_x86_ops->set_interrupt_shadow(vcpu,
2957 events->interrupt.shadow);
3cfc3092
JK		 2958
2959 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2960 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2961 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2962 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2963
66450a21
JK		 2964 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2965 kvm_vcpu_has_lapic(vcpu))
2966 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2967
3842d135
AK		 2968 kvm_make_request(KVM_REQ_EVENT, vcpu);
2969
3cfc3092
JK		 2970 return 0;
2971}
2972
a1efbe77
JK		 2973static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2974 struct kvm_debugregs *dbgregs)
2975{
73aaf249
JK		 2976 unsigned long val;
2977
a1efbe77 2978 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 2979 _kvm_get_dr(vcpu, 6, &val);
2980 dbgregs->dr6 = val;
a1efbe77
JK		 2981 dbgregs->dr7 = vcpu->arch.dr7;
2982 dbgregs->flags = 0;
97e69aa6 2983 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2984}
2985
2986static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2987 struct kvm_debugregs *dbgregs)
2988{
2989 if (dbgregs->flags)
2990 return -EINVAL;
2991
a1efbe77
JK		 2992 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2993 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 2994 kvm_update_dr6(vcpu);
a1efbe77 2995 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 2996 kvm_update_dr7(vcpu);
a1efbe77 2997
a1efbe77
JK		 2998 return 0;
2999}
3000
2d5b5a66
SY		 3001static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3002 struct kvm_xsave *guest_xsave)
3003{
4344ee98 3004 if (cpu_has_xsave) {
2d5b5a66
SY		 3005 memcpy(guest_xsave->region,
3006 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3007 vcpu->arch.guest_xstate_size);
3008 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3009 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3010 } else {
2d5b5a66
SY		 3011 memcpy(guest_xsave->region,
3012 &vcpu->arch.guest_fpu.state->fxsave,
3013 sizeof(struct i387_fxsave_struct));
3014 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3015 XSTATE_FPSSE;
3016 }
3017}
3018
3019static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3020 struct kvm_xsave *guest_xsave)
3021{
3022 u64 xstate_bv =
3023 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3024
d7876f1b
PB		 3025 if (cpu_has_xsave) {
3026 /*
3027 * Here we allow setting states that are not present in
3028 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3029 * with old userspace.
3030 */
3031 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
3032 return -EINVAL;
3033 if (xstate_bv & ~host_xcr0)
3034 return -EINVAL;
2d5b5a66 3035 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3036 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3037 } else {
2d5b5a66
SY		 3038 if (xstate_bv & ~XSTATE_FPSSE)
3039 return -EINVAL;
3040 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3041 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3042 }
3043 return 0;
3044}
3045
3046static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3047 struct kvm_xcrs *guest_xcrs)
3048{
3049 if (!cpu_has_xsave) {
3050 guest_xcrs->nr_xcrs = 0;
3051 return;
3052 }
3053
3054 guest_xcrs->nr_xcrs = 1;
3055 guest_xcrs->flags = 0;
3056 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3057 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3058}
3059
3060static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3061 struct kvm_xcrs *guest_xcrs)
3062{
3063 int i, r = 0;
3064
3065 if (!cpu_has_xsave)
3066 return -EINVAL;
3067
3068 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3069 return -EINVAL;
3070
3071 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3072 /* Only support XCR0 currently */
c67a04cb 3073 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3074 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3075 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3076 break;
3077 }
3078 if (r)
3079 r = -EINVAL;
3080 return r;
3081}
3082
1c0b28c2
EM		 3083/*
3084 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3085 * stopped by the hypervisor. This function will be called from the host only.
3086 * EINVAL is returned when the host attempts to set the flag for a guest that
3087 * does not support pv clocks.
3088 */
3089static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3090{
0b79459b 3091 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3092 return -EINVAL;
51d59c6b 3093 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3094 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3095 return 0;
3096}
3097
313a3dc7
CO		 3098long kvm_arch_vcpu_ioctl(struct file *filp,
3099 unsigned int ioctl, unsigned long arg)
3100{
3101 struct kvm_vcpu *vcpu = filp->private_data;
3102 void __user *argp = (void __user *)arg;
3103 int r;
d1ac91d8
AK		 3104 union {
3105 struct kvm_lapic_state *lapic;
3106 struct kvm_xsave *xsave;
3107 struct kvm_xcrs *xcrs;
3108 void *buffer;
3109 } u;
3110
3111 u.buffer = NULL;
313a3dc7
CO		 3112 switch (ioctl) {
3113 case KVM_GET_LAPIC: {
2204ae3c
MT		 3114 r = -EINVAL;
3115 if (!vcpu->arch.apic)
3116 goto out;
d1ac91d8 3117 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3118
b772ff36 3119 r = -ENOMEM;
d1ac91d8 3120 if (!u.lapic)
b772ff36 3121 goto out;
d1ac91d8 3122 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3123 if (r)
3124 goto out;
3125 r = -EFAULT;
d1ac91d8 3126 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3127 goto out;
3128 r = 0;
3129 break;
3130 }
3131 case KVM_SET_LAPIC: {
2204ae3c
MT		 3132 r = -EINVAL;
3133 if (!vcpu->arch.apic)
3134 goto out;
ff5c2c03 3135 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3136 if (IS_ERR(u.lapic))
3137 return PTR_ERR(u.lapic);
ff5c2c03 3138
d1ac91d8 3139 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3140 break;
3141 }
f77bc6a4
ZX		 3142 case KVM_INTERRUPT: {
3143 struct kvm_interrupt irq;
3144
3145 r = -EFAULT;
3146 if (copy_from_user(&irq, argp, sizeof irq))
3147 goto out;
3148 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3149 break;
3150 }
c4abb7c9
JK		 3151 case KVM_NMI: {
3152 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3153 break;
3154 }
313a3dc7
CO		 3155 case KVM_SET_CPUID: {
3156 struct kvm_cpuid __user *cpuid_arg = argp;
3157 struct kvm_cpuid cpuid;
3158
3159 r = -EFAULT;
3160 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3161 goto out;
3162 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3163 break;
3164 }
07716717
DK		 3165 case KVM_SET_CPUID2: {
3166 struct kvm_cpuid2 __user *cpuid_arg = argp;
3167 struct kvm_cpuid2 cpuid;
3168
3169 r = -EFAULT;
3170 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3171 goto out;
3172 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3173 cpuid_arg->entries);
07716717
DK		 3174 break;
3175 }
3176 case KVM_GET_CPUID2: {
3177 struct kvm_cpuid2 __user *cpuid_arg = argp;
3178 struct kvm_cpuid2 cpuid;
3179
3180 r = -EFAULT;
3181 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3182 goto out;
3183 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3184 cpuid_arg->entries);
07716717
DK		 3185 if (r)
3186 goto out;
3187 r = -EFAULT;
3188 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3189 goto out;
3190 r = 0;
3191 break;
3192 }
313a3dc7
CO		 3193 case KVM_GET_MSRS:
3194 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3195 break;
3196 case KVM_SET_MSRS:
3197 r = msr_io(vcpu, argp, do_set_msr, 0);
3198 break;
b209749f
AK		 3199 case KVM_TPR_ACCESS_REPORTING: {
3200 struct kvm_tpr_access_ctl tac;
3201
3202 r = -EFAULT;
3203 if (copy_from_user(&tac, argp, sizeof tac))
3204 goto out;
3205 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3206 if (r)
3207 goto out;
3208 r = -EFAULT;
3209 if (copy_to_user(argp, &tac, sizeof tac))
3210 goto out;
3211 r = 0;
3212 break;
3213 };
b93463aa
AK		 3214 case KVM_SET_VAPIC_ADDR: {
3215 struct kvm_vapic_addr va;
3216
3217 r = -EINVAL;
3218 if (!irqchip_in_kernel(vcpu->kvm))
3219 goto out;
3220 r = -EFAULT;
3221 if (copy_from_user(&va, argp, sizeof va))
3222 goto out;
fda4e2e8 3223 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3224 break;
3225 }
890ca9ae
HY		 3226 case KVM_X86_SETUP_MCE: {
3227 u64 mcg_cap;
3228
3229 r = -EFAULT;
3230 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3231 goto out;
3232 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3233 break;
3234 }
3235 case KVM_X86_SET_MCE: {
3236 struct kvm_x86_mce mce;
3237
3238 r = -EFAULT;
3239 if (copy_from_user(&mce, argp, sizeof mce))
3240 goto out;
3241 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3242 break;
3243 }
3cfc3092
JK		 3244 case KVM_GET_VCPU_EVENTS: {
3245 struct kvm_vcpu_events events;
3246
3247 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3248
3249 r = -EFAULT;
3250 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3251 break;
3252 r = 0;
3253 break;
3254 }
3255 case KVM_SET_VCPU_EVENTS: {
3256 struct kvm_vcpu_events events;
3257
3258 r = -EFAULT;
3259 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3260 break;
3261
3262 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3263 break;
3264 }
a1efbe77
JK		 3265 case KVM_GET_DEBUGREGS: {
3266 struct kvm_debugregs dbgregs;
3267
3268 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3269
3270 r = -EFAULT;
3271 if (copy_to_user(argp, &dbgregs,
3272 sizeof(struct kvm_debugregs)))
3273 break;
3274 r = 0;
3275 break;
3276 }
3277 case KVM_SET_DEBUGREGS: {
3278 struct kvm_debugregs dbgregs;
3279
3280 r = -EFAULT;
3281 if (copy_from_user(&dbgregs, argp,
3282 sizeof(struct kvm_debugregs)))
3283 break;
3284
3285 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3286 break;
3287 }
2d5b5a66 3288 case KVM_GET_XSAVE: {
d1ac91d8 3289 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3290 r = -ENOMEM;
d1ac91d8 3291 if (!u.xsave)
2d5b5a66
SY		 3292 break;
3293
d1ac91d8 3294 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3295
3296 r = -EFAULT;
d1ac91d8 3297 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3298 break;
3299 r = 0;
3300 break;
3301 }
3302 case KVM_SET_XSAVE: {
ff5c2c03 3303 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3304 if (IS_ERR(u.xsave))
3305 return PTR_ERR(u.xsave);
2d5b5a66 3306
d1ac91d8 3307 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3308 break;
3309 }
3310 case KVM_GET_XCRS: {
d1ac91d8 3311 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3312 r = -ENOMEM;
d1ac91d8 3313 if (!u.xcrs)
2d5b5a66
SY		 3314 break;
3315
d1ac91d8 3316 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3317
3318 r = -EFAULT;
d1ac91d8 3319 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3320 sizeof(struct kvm_xcrs)))
3321 break;
3322 r = 0;
3323 break;
3324 }
3325 case KVM_SET_XCRS: {
ff5c2c03 3326 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3327 if (IS_ERR(u.xcrs))
3328 return PTR_ERR(u.xcrs);
2d5b5a66 3329
d1ac91d8 3330 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3331 break;
3332 }
92a1f12d
JR		 3333 case KVM_SET_TSC_KHZ: {
3334 u32 user_tsc_khz;
3335
3336 r = -EINVAL;
92a1f12d
JR		 3337 user_tsc_khz = (u32)arg;
3338
3339 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3340 goto out;
3341
cc578287
ZA		 3342 if (user_tsc_khz == 0)
3343 user_tsc_khz = tsc_khz;
3344
3345 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3346
3347 r = 0;
3348 goto out;
3349 }
3350 case KVM_GET_TSC_KHZ: {
cc578287 3351 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3352 goto out;
3353 }
1c0b28c2
EM		 3354 case KVM_KVMCLOCK_CTRL: {
3355 r = kvm_set_guest_paused(vcpu);
3356 goto out;
3357 }
313a3dc7
CO		 3358 default:
3359 r = -EINVAL;
3360 }
3361out:
d1ac91d8 3362 kfree(u.buffer);
313a3dc7
CO		 3363 return r;
3364}
3365
5b1c1493
CO		 3366int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3367{
3368 return VM_FAULT_SIGBUS;
3369}
3370
1fe779f8
CO		 3371static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3372{
3373 int ret;
3374
3375 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3376 return -EINVAL;
1fe779f8
CO		 3377 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3378 return ret;
3379}
3380
b927a3ce
SY		 3381static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3382 u64 ident_addr)
3383{
3384 kvm->arch.ept_identity_map_addr = ident_addr;
3385 return 0;
3386}
3387
1fe779f8
CO		 3388static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3389 u32 kvm_nr_mmu_pages)
3390{
3391 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3392 return -EINVAL;
3393
79fac95e 3394 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3395
3396 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3397 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3398
79fac95e 3399 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3400 return 0;
3401}
3402
3403static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3404{
39de71ec 3405 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3406}
3407
1fe779f8
CO		 3408static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3409{
3410 int r;
3411
3412 r = 0;
3413 switch (chip->chip_id) {
3414 case KVM_IRQCHIP_PIC_MASTER:
3415 memcpy(&chip->chip.pic,
3416 &pic_irqchip(kvm)->pics[0],
3417 sizeof(struct kvm_pic_state));
3418 break;
3419 case KVM_IRQCHIP_PIC_SLAVE:
3420 memcpy(&chip->chip.pic,
3421 &pic_irqchip(kvm)->pics[1],
3422 sizeof(struct kvm_pic_state));
3423 break;
3424 case KVM_IRQCHIP_IOAPIC:
eba0226b 3425 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3426 break;
3427 default:
3428 r = -EINVAL;
3429 break;
3430 }
3431 return r;
3432}
3433
3434static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3435{
3436 int r;
3437
3438 r = 0;
3439 switch (chip->chip_id) {
3440 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3441 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3442 memcpy(&pic_irqchip(kvm)->pics[0],
3443 &chip->chip.pic,
3444 sizeof(struct kvm_pic_state));
f4f51050 3445 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3446 break;
3447 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3448 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3449 memcpy(&pic_irqchip(kvm)->pics[1],
3450 &chip->chip.pic,
3451 sizeof(struct kvm_pic_state));
f4f51050 3452 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3453 break;
3454 case KVM_IRQCHIP_IOAPIC:
eba0226b 3455 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3456 break;
3457 default:
3458 r = -EINVAL;
3459 break;
3460 }
3461 kvm_pic_update_irq(pic_irqchip(kvm));
3462 return r;
3463}
3464
e0f63cb9
SY		 3465static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3466{
3467 int r = 0;
3468
894a9c55 3469 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3470 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3471 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3472 return r;
3473}
3474
3475static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3476{
3477 int r = 0;
3478
894a9c55 3479 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3480 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3481 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3482 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3483 return r;
3484}
3485
3486static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3487{
3488 int r = 0;
3489
3490 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3491 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3492 sizeof(ps->channels));
3493 ps->flags = kvm->arch.vpit->pit_state.flags;
3494 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3495 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3496 return r;
3497}
3498
3499static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3500{
3501 int r = 0, start = 0;
3502 u32 prev_legacy, cur_legacy;
3503 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3504 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3505 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3506 if (!prev_legacy && cur_legacy)
3507 start = 1;
3508 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3509 sizeof(kvm->arch.vpit->pit_state.channels));
3510 kvm->arch.vpit->pit_state.flags = ps->flags;
3511 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3512 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3513 return r;
3514}
3515
52d939a0
MT		 3516static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3517 struct kvm_reinject_control *control)
3518{
3519 if (!kvm->arch.vpit)
3520 return -ENXIO;
894a9c55 3521 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3522 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3523 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3524 return 0;
3525}
3526
95d4c16c 3527/**
60c34612
TY		 3528 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3529 * @kvm: kvm instance
3530 * @log: slot id and address to which we copy the log
95d4c16c 3531 *
60c34612
TY		 3532 * We need to keep it in mind that VCPU threads can write to the bitmap
3533 * concurrently. So, to avoid losing data, we keep the following order for
3534 * each bit:
95d4c16c 3535 *
60c34612
TY		 3536 * 1. Take a snapshot of the bit and clear it if needed.
3537 * 2. Write protect the corresponding page.
3538 * 3. Flush TLB's if needed.
3539 * 4. Copy the snapshot to the userspace.
95d4c16c 3540 *
60c34612
TY		 3541 * Between 2 and 3, the guest may write to the page using the remaining TLB
3542 * entry. This is not a problem because the page will be reported dirty at
3543 * step 4 using the snapshot taken before and step 3 ensures that successive
3544 * writes will be logged for the next call.
5bb064dc 3545 */
60c34612 3546int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3547{
7850ac54 3548 int r;
5bb064dc 3549 struct kvm_memory_slot *memslot;
60c34612
TY		 3550 unsigned long n, i;
3551 unsigned long *dirty_bitmap;
3552 unsigned long *dirty_bitmap_buffer;
3553 bool is_dirty = false;
5bb064dc 3554
79fac95e 3555 mutex_lock(&kvm->slots_lock);
5bb064dc 3556
b050b015 3557 r = -EINVAL;
bbacc0c1 3558 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3559 goto out;
3560
28a37544 3561 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3562
3563 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3564 r = -ENOENT;
60c34612 3565 if (!dirty_bitmap)
b050b015
MT		 3566 goto out;
3567
87bf6e7d 3568 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3569
60c34612
TY		 3570 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3571 memset(dirty_bitmap_buffer, 0, n);
b050b015 3572
60c34612 3573 spin_lock(&kvm->mmu_lock);
b050b015 3574
60c34612
TY		 3575 for (i = 0; i < n / sizeof(long); i++) {
3576 unsigned long mask;
3577 gfn_t offset;
cdfca7b3 3578
60c34612
TY		 3579 if (!dirty_bitmap[i])
3580 continue;
b050b015 3581
60c34612 3582 is_dirty = true;
914ebccd 3583
60c34612
TY		 3584 mask = xchg(&dirty_bitmap[i], 0);
3585 dirty_bitmap_buffer[i] = mask;
edde99ce 3586
60c34612
TY		 3587 offset = i * BITS_PER_LONG;
3588 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3589 }
60c34612
TY		 3590 if (is_dirty)
3591 kvm_flush_remote_tlbs(kvm);
3592
3593 spin_unlock(&kvm->mmu_lock);
3594
3595 r = -EFAULT;
3596 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3597 goto out;
b050b015 3598
5bb064dc
ZX		 3599 r = 0;
3600out:
79fac95e 3601 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3602 return r;
3603}
3604
aa2fbe6d
YZ		 3605int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3606 bool line_status)
23d43cf9
CD		 3607{
3608 if (!irqchip_in_kernel(kvm))
3609 return -ENXIO;
3610
3611 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3612 irq_event->irq, irq_event->level,
3613 line_status);
23d43cf9
CD		 3614 return 0;
3615}
3616
1fe779f8
CO		 3617long kvm_arch_vm_ioctl(struct file *filp,
3618 unsigned int ioctl, unsigned long arg)
3619{
3620 struct kvm *kvm = filp->private_data;
3621 void __user *argp = (void __user *)arg;
367e1319 3622 int r = -ENOTTY;
f0d66275
DH		 3623 /*
3624 * This union makes it completely explicit to gcc-3.x
3625 * that these two variables' stack usage should be
3626 * combined, not added together.
3627 */
3628 union {
3629 struct kvm_pit_state ps;
e9f42757 3630 struct kvm_pit_state2 ps2;
c5ff41ce 3631 struct kvm_pit_config pit_config;
f0d66275 3632 } u;
1fe779f8
CO		 3633
3634 switch (ioctl) {
3635 case KVM_SET_TSS_ADDR:
3636 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3637 break;
b927a3ce
SY		 3638 case KVM_SET_IDENTITY_MAP_ADDR: {
3639 u64 ident_addr;
3640
3641 r = -EFAULT;
3642 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3643 goto out;
3644 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3645 break;
3646 }
1fe779f8
CO		 3647 case KVM_SET_NR_MMU_PAGES:
3648 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3649 break;
3650 case KVM_GET_NR_MMU_PAGES:
3651 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3652 break;
3ddea128
MT		 3653 case KVM_CREATE_IRQCHIP: {
3654 struct kvm_pic *vpic;
3655
3656 mutex_lock(&kvm->lock);
3657 r = -EEXIST;
3658 if (kvm->arch.vpic)
3659 goto create_irqchip_unlock;
3e515705
AK		 3660 r = -EINVAL;
3661 if (atomic_read(&kvm->online_vcpus))
3662 goto create_irqchip_unlock;
1fe779f8 3663 r = -ENOMEM;
3ddea128
MT		 3664 vpic = kvm_create_pic(kvm);
3665 if (vpic) {
1fe779f8
CO		 3666 r = kvm_ioapic_init(kvm);
3667 if (r) {
175504cd 3668 mutex_lock(&kvm->slots_lock);
72bb2fcd 3669 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3670 &vpic->dev_master);
3671 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3672 &vpic->dev_slave);
3673 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3674 &vpic->dev_eclr);
175504cd 3675 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3676 kfree(vpic);
3677 goto create_irqchip_unlock;
1fe779f8
CO		 3678 }
3679 } else
3ddea128
MT		 3680 goto create_irqchip_unlock;
3681 smp_wmb();
3682 kvm->arch.vpic = vpic;
3683 smp_wmb();
399ec807
AK		 3684 r = kvm_setup_default_irq_routing(kvm);
3685 if (r) {
175504cd 3686 mutex_lock(&kvm->slots_lock);
3ddea128 3687 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3688 kvm_ioapic_destroy(kvm);
3689 kvm_destroy_pic(kvm);
3ddea128 3690 mutex_unlock(&kvm->irq_lock);
175504cd 3691 mutex_unlock(&kvm->slots_lock);
399ec807 3692 }
3ddea128
MT		 3693 create_irqchip_unlock:
3694 mutex_unlock(&kvm->lock);
1fe779f8 3695 break;
3ddea128 3696 }
7837699f 3697 case KVM_CREATE_PIT:
c5ff41ce
JK		 3698 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3699 goto create_pit;
3700 case KVM_CREATE_PIT2:
3701 r = -EFAULT;
3702 if (copy_from_user(&u.pit_config, argp,
3703 sizeof(struct kvm_pit_config)))
3704 goto out;
3705 create_pit:
79fac95e 3706 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3707 r = -EEXIST;
3708 if (kvm->arch.vpit)
3709 goto create_pit_unlock;
7837699f 3710 r = -ENOMEM;
c5ff41ce 3711 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3712 if (kvm->arch.vpit)
3713 r = 0;
269e05e4 3714 create_pit_unlock:
79fac95e 3715 mutex_unlock(&kvm->slots_lock);
7837699f 3716 break;
1fe779f8
CO		 3717 case KVM_GET_IRQCHIP: {
3718 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3719 struct kvm_irqchip *chip;
1fe779f8 3720
ff5c2c03
SL		 3721 chip = memdup_user(argp, sizeof(*chip));
3722 if (IS_ERR(chip)) {
3723 r = PTR_ERR(chip);
1fe779f8 3724 goto out;
ff5c2c03
SL		 3725 }
3726
1fe779f8
CO		 3727 r = -ENXIO;
3728 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3729 goto get_irqchip_out;
3730 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3731 if (r)
f0d66275 3732 goto get_irqchip_out;
1fe779f8 3733 r = -EFAULT;
f0d66275
DH		 3734 if (copy_to_user(argp, chip, sizeof *chip))
3735 goto get_irqchip_out;
1fe779f8 3736 r = 0;
f0d66275
DH		 3737 get_irqchip_out:
3738 kfree(chip);
1fe779f8
CO		 3739 break;
3740 }
3741 case KVM_SET_IRQCHIP: {
3742 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3743 struct kvm_irqchip *chip;
1fe779f8 3744
ff5c2c03
SL		 3745 chip = memdup_user(argp, sizeof(*chip));
3746 if (IS_ERR(chip)) {
3747 r = PTR_ERR(chip);
1fe779f8 3748 goto out;
ff5c2c03
SL		 3749 }
3750
1fe779f8
CO		 3751 r = -ENXIO;
3752 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3753 goto set_irqchip_out;
3754 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3755 if (r)
f0d66275 3756 goto set_irqchip_out;
1fe779f8 3757 r = 0;
f0d66275
DH		 3758 set_irqchip_out:
3759 kfree(chip);
1fe779f8
CO		 3760 break;
3761 }
e0f63cb9 3762 case KVM_GET_PIT: {
e0f63cb9 3763 r = -EFAULT;
f0d66275 3764 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3765 goto out;
3766 r = -ENXIO;
3767 if (!kvm->arch.vpit)
3768 goto out;
f0d66275 3769 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3770 if (r)
3771 goto out;
3772 r = -EFAULT;
f0d66275 3773 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3774 goto out;
3775 r = 0;
3776 break;
3777 }
3778 case KVM_SET_PIT: {
e0f63cb9 3779 r = -EFAULT;
f0d66275 3780 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3781 goto out;
3782 r = -ENXIO;
3783 if (!kvm->arch.vpit)
3784 goto out;
f0d66275 3785 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3786 break;
3787 }
e9f42757
BK		 3788 case KVM_GET_PIT2: {
3789 r = -ENXIO;
3790 if (!kvm->arch.vpit)
3791 goto out;
3792 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3793 if (r)
3794 goto out;
3795 r = -EFAULT;
3796 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3797 goto out;
3798 r = 0;
3799 break;
3800 }
3801 case KVM_SET_PIT2: {
3802 r = -EFAULT;
3803 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3804 goto out;
3805 r = -ENXIO;
3806 if (!kvm->arch.vpit)
3807 goto out;
3808 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3809 break;
3810 }
52d939a0
MT		 3811 case KVM_REINJECT_CONTROL: {
3812 struct kvm_reinject_control control;
3813 r = -EFAULT;
3814 if (copy_from_user(&control, argp, sizeof(control)))
3815 goto out;
3816 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3817 break;
3818 }
ffde22ac
ES		 3819 case KVM_XEN_HVM_CONFIG: {
3820 r = -EFAULT;
3821 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3822 sizeof(struct kvm_xen_hvm_config)))
3823 goto out;
3824 r = -EINVAL;
3825 if (kvm->arch.xen_hvm_config.flags)
3826 goto out;
3827 r = 0;
3828 break;
3829 }
afbcf7ab 3830 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3831 struct kvm_clock_data user_ns;
3832 u64 now_ns;
3833 s64 delta;
3834
3835 r = -EFAULT;
3836 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3837 goto out;
3838
3839 r = -EINVAL;
3840 if (user_ns.flags)
3841 goto out;
3842
3843 r = 0;
395c6b0a 3844 local_irq_disable();
759379dd 3845 now_ns = get_kernel_ns();
afbcf7ab 3846 delta = user_ns.clock - now_ns;
395c6b0a 3847 local_irq_enable();
afbcf7ab 3848 kvm->arch.kvmclock_offset = delta;
2e762ff7 3849 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3850 break;
3851 }
3852 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3853 struct kvm_clock_data user_ns;
3854 u64 now_ns;
3855
395c6b0a 3856 local_irq_disable();
759379dd 3857 now_ns = get_kernel_ns();
afbcf7ab 3858 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3859 local_irq_enable();
afbcf7ab 3860 user_ns.flags = 0;
97e69aa6 3861 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3862
3863 r = -EFAULT;
3864 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3865 goto out;
3866 r = 0;
3867 break;
3868 }
3869
1fe779f8
CO		 3870 default:
3871 ;
3872 }
3873out:
3874 return r;
3875}
3876
a16b043c 3877static void kvm_init_msr_list(void)
043405e1
CO		 3878{
3879 u32 dummy[2];
3880 unsigned i, j;
3881
e3267cbb
GC		 3882 /* skip the first msrs in the list. KVM-specific */
3883 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3884 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3885 continue;
3886 if (j < i)
3887 msrs_to_save[j] = msrs_to_save[i];
3888 j++;
3889 }
3890 num_msrs_to_save = j;
3891}
3892
bda9020e
MT		 3893static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3894 const void *v)
bbd9b64e 3895{
70252a10
AK		 3896 int handled = 0;
3897 int n;
3898
3899 do {
3900 n = min(len, 8);
3901 if (!(vcpu->arch.apic &&
3902 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3903 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3904 break;
3905 handled += n;
3906 addr += n;
3907 len -= n;
3908 v += n;
3909 } while (len);
bbd9b64e 3910
70252a10 3911 return handled;
bbd9b64e
CO		 3912}
3913
bda9020e 3914static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3915{
70252a10
AK		 3916 int handled = 0;
3917 int n;
3918
3919 do {
3920 n = min(len, 8);
3921 if (!(vcpu->arch.apic &&
3922 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3923 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3924 break;
3925 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3926 handled += n;
3927 addr += n;
3928 len -= n;
3929 v += n;
3930 } while (len);
bbd9b64e 3931
70252a10 3932 return handled;
bbd9b64e
CO		 3933}
3934
2dafc6c2
GN		 3935static void kvm_set_segment(struct kvm_vcpu *vcpu,
3936 struct kvm_segment *var, int seg)
3937{
3938 kvm_x86_ops->set_segment(vcpu, var, seg);
3939}
3940
3941void kvm_get_segment(struct kvm_vcpu *vcpu,
3942 struct kvm_segment *var, int seg)
3943{
3944 kvm_x86_ops->get_segment(vcpu, var, seg);
3945}
3946
e459e322 3947gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3948{
3949 gpa_t t_gpa;
ab9ae313 3950 struct x86_exception exception;
02f59dc9
JR		 3951
3952 BUG_ON(!mmu_is_nested(vcpu));
3953
3954 /* NPT walks are always user-walks */
3955 access |= PFERR_USER_MASK;
ab9ae313 3956 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3957
3958 return t_gpa;
3959}
3960
ab9ae313
AK		 3961gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3962 struct x86_exception *exception)
1871c602
GN		 3963{
3964 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3965 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3966}
3967
ab9ae313
AK		 3968 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3969 struct x86_exception *exception)
1871c602
GN		 3970{
3971 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3972 access |= PFERR_FETCH_MASK;
ab9ae313 3973 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3974}
3975
ab9ae313
AK		 3976gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3977 struct x86_exception *exception)
1871c602
GN		 3978{
3979 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3980 access |= PFERR_WRITE_MASK;
ab9ae313 3981 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3982}
3983
3984/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3985gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3986 struct x86_exception *exception)
1871c602 3987{
ab9ae313 3988 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3989}
3990
3991static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3992 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3993 struct x86_exception *exception)
bbd9b64e
CO		 3994{
3995 void *data = val;
10589a46 3996 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3997
3998 while (bytes) {
14dfe855 3999 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4000 exception);
bbd9b64e 4001 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4002 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4003 int ret;
4004
bcc55cba 4005 if (gpa == UNMAPPED_GVA)
ab9ae313 4006 return X86EMUL_PROPAGATE_FAULT;
77c2002e 4007 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 4008 if (ret < 0) {
c3cd7ffa 4009 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4010 goto out;
4011 }
bbd9b64e 4012
77c2002e
IE		 4013 bytes -= toread;
4014 data += toread;
4015 addr += toread;
bbd9b64e 4016 }
10589a46 4017out:
10589a46 4018 return r;
bbd9b64e 4019}
77c2002e 4020
1871c602 4021/* used for instruction fetching */
0f65dd70
AK		 4022static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4023 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4024 struct x86_exception *exception)
1871c602 4025{
0f65dd70 4026 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4027 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4028
1871c602 4029 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4030 access | PFERR_FETCH_MASK,
4031 exception);
1871c602
GN		 4032}
4033
064aea77 4034int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4035 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4036 struct x86_exception *exception)
1871c602 4037{
0f65dd70 4038 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4039 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4040
1871c602 4041 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4042 exception);
1871c602 4043}
064aea77 4044EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4045
0f65dd70
AK		 4046static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4047 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4048 struct x86_exception *exception)
1871c602 4049{
0f65dd70 4050 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4051 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4052}
4053
6a4d7550 4054int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4055 gva_t addr, void *val,
2dafc6c2 4056 unsigned int bytes,
bcc55cba 4057 struct x86_exception *exception)
77c2002e 4058{
0f65dd70 4059 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4060 void *data = val;
4061 int r = X86EMUL_CONTINUE;
4062
4063 while (bytes) {
14dfe855
JR		 4064 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4065 PFERR_WRITE_MASK,
ab9ae313 4066 exception);
77c2002e
IE		 4067 unsigned offset = addr & (PAGE_SIZE-1);
4068 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4069 int ret;
4070
bcc55cba 4071 if (gpa == UNMAPPED_GVA)
ab9ae313 4072 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4073 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4074 if (ret < 0) {
c3cd7ffa 4075 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4076 goto out;
4077 }
4078
4079 bytes -= towrite;
4080 data += towrite;
4081 addr += towrite;
4082 }
4083out:
4084 return r;
4085}
6a4d7550 4086EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4087
af7cc7d1
XG		 4088static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4089 gpa_t *gpa, struct x86_exception *exception,
4090 bool write)
4091{
97d64b78
AK		 4092 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4093 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4094
97d64b78
AK		 4095 if (vcpu_match_mmio_gva(vcpu, gva)
4096 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4097 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4098 (gva & (PAGE_SIZE - 1));
4f022648 4099 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4100 return 1;
4101 }
4102
af7cc7d1
XG		 4103 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4104
4105 if (*gpa == UNMAPPED_GVA)
4106 return -1;
4107
4108 /* For APIC access vmexit */
4109 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4110 return 1;
4111
4f022648
XG		 4112 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4113 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4114 return 1;
4f022648 4115 }
bebb106a 4116
af7cc7d1
XG		 4117 return 0;
4118}
4119
3200f405 4120int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4121 const void *val, int bytes)
bbd9b64e
CO		 4122{
4123 int ret;
4124
4125 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4126 if (ret < 0)
bbd9b64e 4127 return 0;
f57f2ef5 4128 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4129 return 1;
4130}
4131
77d197b2
XG		 4132struct read_write_emulator_ops {
4133 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4134 int bytes);
4135 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4136 void *val, int bytes);
4137 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4138 int bytes, void *val);
4139 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4140 void *val, int bytes);
4141 bool write;
4142};
4143
4144static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4145{
4146 if (vcpu->mmio_read_completed) {
77d197b2 4147 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4148 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4149 vcpu->mmio_read_completed = 0;
4150 return 1;
4151 }
4152
4153 return 0;
4154}
4155
4156static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4157 void *val, int bytes)
4158{
4159 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4160}
4161
4162static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4163 void *val, int bytes)
4164{
4165 return emulator_write_phys(vcpu, gpa, val, bytes);
4166}
4167
4168static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4169{
4170 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4171 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4172}
4173
4174static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4175 void *val, int bytes)
4176{
4177 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4178 return X86EMUL_IO_NEEDED;
4179}
4180
4181static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4182 void *val, int bytes)
4183{
f78146b0
AK		 4184 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4185
87da7e66 4186 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4187 return X86EMUL_CONTINUE;
4188}
4189
0fbe9b0b 4190static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4191 .read_write_prepare = read_prepare,
4192 .read_write_emulate = read_emulate,
4193 .read_write_mmio = vcpu_mmio_read,
4194 .read_write_exit_mmio = read_exit_mmio,
4195};
4196
0fbe9b0b 4197static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4198 .read_write_emulate = write_emulate,
4199 .read_write_mmio = write_mmio,
4200 .read_write_exit_mmio = write_exit_mmio,
4201 .write = true,
4202};
4203
22388a3c
XG		 4204static int emulator_read_write_onepage(unsigned long addr, void *val,
4205 unsigned int bytes,
4206 struct x86_exception *exception,
4207 struct kvm_vcpu *vcpu,
0fbe9b0b 4208 const struct read_write_emulator_ops *ops)
bbd9b64e 4209{
af7cc7d1
XG		 4210 gpa_t gpa;
4211 int handled, ret;
22388a3c 4212 bool write = ops->write;
f78146b0 4213 struct kvm_mmio_fragment *frag;
10589a46 4214
22388a3c 4215 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4216
af7cc7d1 4217 if (ret < 0)
bbd9b64e 4218 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4219
4220 /* For APIC access vmexit */
af7cc7d1 4221 if (ret)
bbd9b64e
CO		 4222 goto mmio;
4223
22388a3c 4224 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4225 return X86EMUL_CONTINUE;
4226
4227mmio:
4228 /*
4229 * Is this MMIO handled locally?
4230 */
22388a3c 4231 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4232 if (handled == bytes)
bbd9b64e 4233 return X86EMUL_CONTINUE;
bbd9b64e 4234
70252a10
AK		 4235 gpa += handled;
4236 bytes -= handled;
4237 val += handled;
4238
87da7e66
XG		 4239 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4240 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4241 frag->gpa = gpa;
4242 frag->data = val;
4243 frag->len = bytes;
f78146b0 4244 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4245}
4246
22388a3c
XG		 4247int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4248 void *val, unsigned int bytes,
4249 struct x86_exception *exception,
0fbe9b0b 4250 const struct read_write_emulator_ops *ops)
bbd9b64e 4251{
0f65dd70 4252 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4253 gpa_t gpa;
4254 int rc;
4255
4256 if (ops->read_write_prepare &&
4257 ops->read_write_prepare(vcpu, val, bytes))
4258 return X86EMUL_CONTINUE;
4259
4260 vcpu->mmio_nr_fragments = 0;
0f65dd70 4261
bbd9b64e
CO		 4262 /* Crossing a page boundary? */
4263 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4264 int now;
bbd9b64e
CO		 4265
4266 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4267 rc = emulator_read_write_onepage(addr, val, now, exception,
4268 vcpu, ops);
4269
bbd9b64e
CO		 4270 if (rc != X86EMUL_CONTINUE)
4271 return rc;
4272 addr += now;
4273 val += now;
4274 bytes -= now;
4275 }
22388a3c 4276
f78146b0
AK		 4277 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4278 vcpu, ops);
4279 if (rc != X86EMUL_CONTINUE)
4280 return rc;
4281
4282 if (!vcpu->mmio_nr_fragments)
4283 return rc;
4284
4285 gpa = vcpu->mmio_fragments[0].gpa;
4286
4287 vcpu->mmio_needed = 1;
4288 vcpu->mmio_cur_fragment = 0;
4289
87da7e66 4290 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4291 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4292 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4293 vcpu->run->mmio.phys_addr = gpa;
4294
4295 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4296}
4297
4298static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4299 unsigned long addr,
4300 void *val,
4301 unsigned int bytes,
4302 struct x86_exception *exception)
4303{
4304 return emulator_read_write(ctxt, addr, val, bytes,
4305 exception, &read_emultor);
4306}
4307
4308int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4309 unsigned long addr,
4310 const void *val,
4311 unsigned int bytes,
4312 struct x86_exception *exception)
4313{
4314 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4315 exception, &write_emultor);
bbd9b64e 4316}
bbd9b64e 4317
daea3e73
AK		 4318#define CMPXCHG_TYPE(t, ptr, old, new) \
4319 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4320
4321#ifdef CONFIG_X86_64
4322# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4323#else
4324# define CMPXCHG64(ptr, old, new) \
9749a6c0 4325 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4326#endif
4327
0f65dd70
AK		 4328static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4329 unsigned long addr,
bbd9b64e
CO		 4330 const void *old,
4331 const void *new,
4332 unsigned int bytes,
0f65dd70 4333 struct x86_exception *exception)
bbd9b64e 4334{
0f65dd70 4335 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4336 gpa_t gpa;
4337 struct page *page;
4338 char *kaddr;
4339 bool exchanged;
2bacc55c 4340
daea3e73
AK		 4341 /* guests cmpxchg8b have to be emulated atomically */
4342 if (bytes > 8 || (bytes & (bytes - 1)))
4343 goto emul_write;
10589a46 4344
daea3e73 4345 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4346
daea3e73
AK		 4347 if (gpa == UNMAPPED_GVA ||
4348 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4349 goto emul_write;
2bacc55c 4350
daea3e73
AK		 4351 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4352 goto emul_write;
72dc67a6 4353
daea3e73 4354 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4355 if (is_error_page(page))
c19b8bd6 4356 goto emul_write;
72dc67a6 4357
8fd75e12 4358 kaddr = kmap_atomic(page);
daea3e73
AK		 4359 kaddr += offset_in_page(gpa);
4360 switch (bytes) {
4361 case 1:
4362 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4363 break;
4364 case 2:
4365 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4366 break;
4367 case 4:
4368 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4369 break;
4370 case 8:
4371 exchanged = CMPXCHG64(kaddr, old, new);
4372 break;
4373 default:
4374 BUG();
2bacc55c 4375 }
8fd75e12 4376 kunmap_atomic(kaddr);
daea3e73
AK		 4377 kvm_release_page_dirty(page);
4378
4379 if (!exchanged)
4380 return X86EMUL_CMPXCHG_FAILED;
4381
f57f2ef5 4382 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4383
4384 return X86EMUL_CONTINUE;
4a5f48f6 4385
3200f405 4386emul_write:
daea3e73 4387 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4388
0f65dd70 4389 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4390}
4391
cf8f70bf
GN		 4392static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4393{
4394 /* TODO: String I/O for in kernel device */
4395 int r;
4396
4397 if (vcpu->arch.pio.in)
4398 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4399 vcpu->arch.pio.size, pd);
4400 else
4401 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4402 vcpu->arch.pio.port, vcpu->arch.pio.size,
4403 pd);
4404 return r;
4405}
4406
6f6fbe98
XG		 4407static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4408 unsigned short port, void *val,
4409 unsigned int count, bool in)
cf8f70bf 4410{
6f6fbe98 4411 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4412
4413 vcpu->arch.pio.port = port;
6f6fbe98 4414 vcpu->arch.pio.in = in;
7972995b 4415 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4416 vcpu->arch.pio.size = size;
4417
4418 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4419 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4420 return 1;
4421 }
4422
4423 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4424 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4425 vcpu->run->io.size = size;
4426 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4427 vcpu->run->io.count = count;
4428 vcpu->run->io.port = port;
4429
4430 return 0;
4431}
4432
6f6fbe98
XG		 4433static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4434 int size, unsigned short port, void *val,
4435 unsigned int count)
cf8f70bf 4436{
ca1d4a9e 4437 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4438 int ret;
ca1d4a9e 4439
6f6fbe98
XG		 4440 if (vcpu->arch.pio.count)
4441 goto data_avail;
cf8f70bf 4442
6f6fbe98
XG		 4443 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4444 if (ret) {
4445data_avail:
4446 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4447 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4448 return 1;
4449 }
4450
cf8f70bf
GN		 4451 return 0;
4452}
4453
6f6fbe98
XG		 4454static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4455 int size, unsigned short port,
4456 const void *val, unsigned int count)
4457{
4458 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4459
4460 memcpy(vcpu->arch.pio_data, val, size * count);
4461 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4462}
4463
bbd9b64e
CO		 4464static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4465{
4466 return kvm_x86_ops->get_segment_base(vcpu, seg);
4467}
4468
3cb16fe7 4469static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4470{
3cb16fe7 4471 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4472}
4473
f5f48ee1
SY		 4474int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4475{
4476 if (!need_emulate_wbinvd(vcpu))
4477 return X86EMUL_CONTINUE;
4478
4479 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4480 int cpu = get_cpu();
4481
4482 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4483 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4484 wbinvd_ipi, NULL, 1);
2eec7343 4485 put_cpu();
f5f48ee1 4486 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4487 } else
4488 wbinvd();
f5f48ee1
SY		 4489 return X86EMUL_CONTINUE;
4490}
4491EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4492
bcaf5cc5
AK		 4493static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4494{
4495 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4496}
4497
717746e3 4498int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4499{
717746e3 4500 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4501}
4502
717746e3 4503int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4504{
338dbc97 4505
717746e3 4506 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4507}
4508
52a46617 4509static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4510{
52a46617 4511 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4512}
4513
717746e3 4514static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4515{
717746e3 4516 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4517 unsigned long value;
4518
4519 switch (cr) {
4520 case 0:
4521 value = kvm_read_cr0(vcpu);
4522 break;
4523 case 2:
4524 value = vcpu->arch.cr2;
4525 break;
4526 case 3:
9f8fe504 4527 value = kvm_read_cr3(vcpu);
52a46617
GN		 4528 break;
4529 case 4:
4530 value = kvm_read_cr4(vcpu);
4531 break;
4532 case 8:
4533 value = kvm_get_cr8(vcpu);
4534 break;
4535 default:
a737f256 4536 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4537 return 0;
4538 }
4539
4540 return value;
4541}
4542
717746e3 4543static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4544{
717746e3 4545 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4546 int res = 0;
4547
52a46617
GN		 4548 switch (cr) {
4549 case 0:
49a9b07e 4550 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4551 break;
4552 case 2:
4553 vcpu->arch.cr2 = val;
4554 break;
4555 case 3:
2390218b 4556 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4557 break;
4558 case 4:
a83b29c6 4559 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4560 break;
4561 case 8:
eea1cff9 4562 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4563 break;
4564 default:
a737f256 4565 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4566 res = -1;
52a46617 4567 }
0f12244f
GN		 4568
4569 return res;
52a46617
GN		 4570}
4571
4cee4798
KW		 4572static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4573{
4574 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4575}
4576
717746e3 4577static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4578{
717746e3 4579 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4580}
4581
4bff1e86 4582static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4583{
4bff1e86 4584 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4585}
4586
4bff1e86 4587static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4588{
4bff1e86 4589 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4590}
4591
1ac9d0cf
AK		 4592static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4593{
4594 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4595}
4596
4597static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4598{
4599 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4600}
4601
4bff1e86
AK		 4602static unsigned long emulator_get_cached_segment_base(
4603 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4604{
4bff1e86 4605 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4606}
4607
1aa36616
AK		 4608static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4609 struct desc_struct *desc, u32 *base3,
4610 int seg)
2dafc6c2
GN		 4611{
4612 struct kvm_segment var;
4613
4bff1e86 4614 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4615 *selector = var.selector;
2dafc6c2 4616
378a8b09
GN		 4617 if (var.unusable) {
4618 memset(desc, 0, sizeof(*desc));
2dafc6c2 4619 return false;
378a8b09 4620 }
2dafc6c2
GN		 4621
4622 if (var.g)
4623 var.limit >>= 12;
4624 set_desc_limit(desc, var.limit);
4625 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4626#ifdef CONFIG_X86_64
4627 if (base3)
4628 *base3 = var.base >> 32;
4629#endif
2dafc6c2
GN		 4630 desc->type = var.type;
4631 desc->s = var.s;
4632 desc->dpl = var.dpl;
4633 desc->p = var.present;
4634 desc->avl = var.avl;
4635 desc->l = var.l;
4636 desc->d = var.db;
4637 desc->g = var.g;
4638
4639 return true;
4640}
4641
1aa36616
AK		 4642static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4643 struct desc_struct *desc, u32 base3,
4644 int seg)
2dafc6c2 4645{
4bff1e86 4646 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4647 struct kvm_segment var;
4648
1aa36616 4649 var.selector = selector;
2dafc6c2 4650 var.base = get_desc_base(desc);
5601d05b
GN		 4651#ifdef CONFIG_X86_64
4652 var.base |= ((u64)base3) << 32;
4653#endif
2dafc6c2
GN		 4654 var.limit = get_desc_limit(desc);
4655 if (desc->g)
4656 var.limit = (var.limit << 12) | 0xfff;
4657 var.type = desc->type;
4658 var.present = desc->p;
4659 var.dpl = desc->dpl;
4660 var.db = desc->d;
4661 var.s = desc->s;
4662 var.l = desc->l;
4663 var.g = desc->g;
4664 var.avl = desc->avl;
4665 var.present = desc->p;
4666 var.unusable = !var.present;
4667 var.padding = 0;
4668
4669 kvm_set_segment(vcpu, &var, seg);
4670 return;
4671}
4672
717746e3
AK		 4673static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4674 u32 msr_index, u64 *pdata)
4675{
4676 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4677}
4678
4679static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4680 u32 msr_index, u64 data)
4681{
8fe8ab46
WA		 4682 struct msr_data msr;
4683
4684 msr.data = data;
4685 msr.index = msr_index;
4686 msr.host_initiated = false;
4687 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4688}
4689
222d21aa
AK		 4690static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4691 u32 pmc, u64 *pdata)
4692{
4693 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4694}
4695
6c3287f7
AK		 4696static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4697{
4698 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4699}
4700
5037f6f3
AK		 4701static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4702{
4703 preempt_disable();
5197b808 4704 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4705 /*
4706 * CR0.TS may reference the host fpu state, not the guest fpu state,
4707 * so it may be clear at this point.
4708 */
4709 clts();
4710}
4711
4712static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4713{
4714 preempt_enable();
4715}
4716
2953538e 4717static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4718 struct x86_instruction_info *info,
c4f035c6
AK		 4719 enum x86_intercept_stage stage)
4720{
2953538e 4721 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4722}
4723
0017f93a 4724static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4725 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4726{
0017f93a 4727 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4728}
4729
dd856efa
AK		 4730static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4731{
4732 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4733}
4734
4735static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4736{
4737 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4738}
4739
0225fb50 4740static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4741 .read_gpr = emulator_read_gpr,
4742 .write_gpr = emulator_write_gpr,
1871c602 4743 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4744 .write_std = kvm_write_guest_virt_system,
1871c602 4745 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4746 .read_emulated = emulator_read_emulated,
4747 .write_emulated = emulator_write_emulated,
4748 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4749 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4750 .pio_in_emulated = emulator_pio_in_emulated,
4751 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4752 .get_segment = emulator_get_segment,
4753 .set_segment = emulator_set_segment,
5951c442 4754 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4755 .get_gdt = emulator_get_gdt,
160ce1f1 4756 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4757 .set_gdt = emulator_set_gdt,
4758 .set_idt = emulator_set_idt,
52a46617
GN		 4759 .get_cr = emulator_get_cr,
4760 .set_cr = emulator_set_cr,
4cee4798 4761 .set_rflags = emulator_set_rflags,
9c537244 4762 .cpl = emulator_get_cpl,
35aa5375
GN		 4763 .get_dr = emulator_get_dr,
4764 .set_dr = emulator_set_dr,
717746e3
AK		 4765 .set_msr = emulator_set_msr,
4766 .get_msr = emulator_get_msr,
222d21aa 4767 .read_pmc = emulator_read_pmc,
6c3287f7 4768 .halt = emulator_halt,
bcaf5cc5 4769 .wbinvd = emulator_wbinvd,
d6aa1000 4770 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4771 .get_fpu = emulator_get_fpu,
4772 .put_fpu = emulator_put_fpu,
c4f035c6 4773 .intercept = emulator_intercept,
bdb42f5a 4774 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4775};
4776
95cb2295
GN		 4777static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4778{
4779 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4780 /*
4781 * an sti; sti; sequence only disable interrupts for the first
4782 * instruction. So, if the last instruction, be it emulated or
4783 * not, left the system with the INT_STI flag enabled, it
4784 * means that the last instruction is an sti. We should not
4785 * leave the flag on in this case. The same goes for mov ss
4786 */
4787 if (!(int_shadow & mask))
4788 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4789}
4790
54b8486f
GN		 4791static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4792{
4793 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4794 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4795 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4796 else if (ctxt->exception.error_code_valid)
4797 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4798 ctxt->exception.error_code);
54b8486f 4799 else
da9cb575 4800 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4801}
4802
dd856efa 4803static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4804{
1ce19dc1
BP		 4805 memset(&ctxt->opcode_len, 0,
4806 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4807
9dac77fa
AK		 4808 ctxt->fetch.start = 0;
4809 ctxt->fetch.end = 0;
4810 ctxt->io_read.pos = 0;
4811 ctxt->io_read.end = 0;
4812 ctxt->mem_read.pos = 0;
4813 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4814}
4815
8ec4722d
MG		 4816static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4817{
adf52235 4818 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4819 int cs_db, cs_l;
4820
8ec4722d
MG		 4821 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4822
adf52235
TY		 4823 ctxt->eflags = kvm_get_rflags(vcpu);
4824 ctxt->eip = kvm_rip_read(vcpu);
4825 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4826 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4827 cs_l ? X86EMUL_MODE_PROT64 :
4828 cs_db ? X86EMUL_MODE_PROT32 :
4829 X86EMUL_MODE_PROT16;
4830 ctxt->guest_mode = is_guest_mode(vcpu);
4831
dd856efa 4832 init_decode_cache(ctxt);
7ae441ea 4833 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4834}
4835
71f9833b 4836int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4837{
9d74191a 4838 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4839 int ret;
4840
4841 init_emulate_ctxt(vcpu);
4842
9dac77fa
AK		 4843 ctxt->op_bytes = 2;
4844 ctxt->ad_bytes = 2;
4845 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4846 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4847
4848 if (ret != X86EMUL_CONTINUE)
4849 return EMULATE_FAIL;
4850
9dac77fa 4851 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4852 kvm_rip_write(vcpu, ctxt->eip);
4853 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4854
4855 if (irq == NMI_VECTOR)
7460fb4a 4856 vcpu->arch.nmi_pending = 0;
63995653
MG		 4857 else
4858 vcpu->arch.interrupt.pending = false;
4859
4860 return EMULATE_DONE;
4861}
4862EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4863
6d77dbfc
GN		 4864static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4865{
fc3a9157
JR		 4866 int r = EMULATE_DONE;
4867
6d77dbfc
GN		 4868 ++vcpu->stat.insn_emulation_fail;
4869 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4870 if (!is_guest_mode(vcpu)) {
4871 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4872 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4873 vcpu->run->internal.ndata = 0;
4874 r = EMULATE_FAIL;
4875 }
6d77dbfc 4876 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4877
4878 return r;
6d77dbfc
GN		 4879}
4880
93c05d3e 4881static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4882 bool write_fault_to_shadow_pgtable,
4883 int emulation_type)
a6f177ef 4884{
95b3cf69 4885 gpa_t gpa = cr2;
8e3d9d06 4886 pfn_t pfn;
a6f177ef 4887
991eebf9
GN		 4888 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4889 return false;
4890
95b3cf69
XG		 4891 if (!vcpu->arch.mmu.direct_map) {
4892 /*
4893 * Write permission should be allowed since only
4894 * write access need to be emulated.
4895 */
4896 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4897
95b3cf69
XG		 4898 /*
4899 * If the mapping is invalid in guest, let cpu retry
4900 * it to generate fault.
4901 */
4902 if (gpa == UNMAPPED_GVA)
4903 return true;
4904 }
a6f177ef 4905
8e3d9d06
XG		 4906 /*
4907 * Do not retry the unhandleable instruction if it faults on the
4908 * readonly host memory, otherwise it will goto a infinite loop:
4909 * retry instruction -> write #PF -> emulation fail -> retry
4910 * instruction -> ...
4911 */
4912 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4913
4914 /*
4915 * If the instruction failed on the error pfn, it can not be fixed,
4916 * report the error to userspace.
4917 */
4918 if (is_error_noslot_pfn(pfn))
4919 return false;
4920
4921 kvm_release_pfn_clean(pfn);
4922
4923 /* The instructions are well-emulated on direct mmu. */
4924 if (vcpu->arch.mmu.direct_map) {
4925 unsigned int indirect_shadow_pages;
4926
4927 spin_lock(&vcpu->kvm->mmu_lock);
4928 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4929 spin_unlock(&vcpu->kvm->mmu_lock);
4930
4931 if (indirect_shadow_pages)
4932 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4933
a6f177ef 4934 return true;
8e3d9d06 4935 }
a6f177ef 4936
95b3cf69
XG		 4937 /*
4938 * if emulation was due to access to shadowed page table
4939 * and it failed try to unshadow page and re-enter the
4940 * guest to let CPU execute the instruction.
4941 */
4942 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4943
4944 /*
4945 * If the access faults on its page table, it can not
4946 * be fixed by unprotecting shadow page and it should
4947 * be reported to userspace.
4948 */
4949 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4950}
4951
1cb3f3ae
XG		 4952static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4953 unsigned long cr2, int emulation_type)
4954{
4955 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4956 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4957
4958 last_retry_eip = vcpu->arch.last_retry_eip;
4959 last_retry_addr = vcpu->arch.last_retry_addr;
4960
4961 /*
4962 * If the emulation is caused by #PF and it is non-page_table
4963 * writing instruction, it means the VM-EXIT is caused by shadow
4964 * page protected, we can zap the shadow page and retry this
4965 * instruction directly.
4966 *
4967 * Note: if the guest uses a non-page-table modifying instruction
4968 * on the PDE that points to the instruction, then we will unmap
4969 * the instruction and go to an infinite loop. So, we cache the
4970 * last retried eip and the last fault address, if we meet the eip
4971 * and the address again, we can break out of the potential infinite
4972 * loop.
4973 */
4974 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4975
4976 if (!(emulation_type & EMULTYPE_RETRY))
4977 return false;
4978
4979 if (x86_page_table_writing_insn(ctxt))
4980 return false;
4981
4982 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4983 return false;
4984
4985 vcpu->arch.last_retry_eip = ctxt->eip;
4986 vcpu->arch.last_retry_addr = cr2;
4987
4988 if (!vcpu->arch.mmu.direct_map)
4989 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4990
22368028 4991 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4992
4993 return true;
4994}
4995
716d51ab
GN		 4996static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4997static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4998
4a1e10d5
PB		 4999static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5000 unsigned long *db)
5001{
5002 u32 dr6 = 0;
5003 int i;
5004 u32 enable, rwlen;
5005
5006 enable = dr7;
5007 rwlen = dr7 >> 16;
5008 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5009 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5010 dr6 |= (1 << i);
5011 return dr6;
5012}
5013
663f4c61
PB		 5014static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5015{
5016 struct kvm_run *kvm_run = vcpu->run;
5017
5018 /*
5019 * Use the "raw" value to see if TF was passed to the processor.
5020 * Note that the new value of the flags has not been saved yet.
5021 *
5022 * This is correct even for TF set by the guest, because "the
5023 * processor will not generate this exception after the instruction
5024 * that sets the TF flag".
5025 */
5026 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5027
5028 if (unlikely(rflags & X86_EFLAGS_TF)) {
5029 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5030 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5031 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5032 kvm_run->debug.arch.exception = DB_VECTOR;
5033 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5034 *r = EMULATE_USER_EXIT;
5035 } else {
5036 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5037 /*
5038 * "Certain debug exceptions may clear bit 0-3. The
5039 * remaining contents of the DR6 register are never
5040 * cleared by the processor".
5041 */
5042 vcpu->arch.dr6 &= ~15;
5043 vcpu->arch.dr6 |= DR6_BS;
5044 kvm_queue_exception(vcpu, DB_VECTOR);
5045 }
5046 }
5047}
5048
4a1e10d5
PB		 5049static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5050{
5051 struct kvm_run *kvm_run = vcpu->run;
5052 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5053 u32 dr6 = 0;
5054
5055 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5056 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5057 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5058 vcpu->arch.guest_debug_dr7,
5059 vcpu->arch.eff_db);
5060
5061 if (dr6 != 0) {
5062 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5063 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5064 get_segment_base(vcpu, VCPU_SREG_CS);
5065
5066 kvm_run->debug.arch.exception = DB_VECTOR;
5067 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5068 *r = EMULATE_USER_EXIT;
5069 return true;
5070 }
5071 }
5072
5073 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5074 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5075 vcpu->arch.dr7,
5076 vcpu->arch.db);
5077
5078 if (dr6 != 0) {
5079 vcpu->arch.dr6 &= ~15;
5080 vcpu->arch.dr6 |= dr6;
5081 kvm_queue_exception(vcpu, DB_VECTOR);
5082 *r = EMULATE_DONE;
5083 return true;
5084 }
5085 }
5086
5087 return false;
5088}
5089
51d8b661
AP		 5090int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5091 unsigned long cr2,
dc25e89e
AP		 5092 int emulation_type,
5093 void *insn,
5094 int insn_len)
bbd9b64e 5095{
95cb2295 5096 int r;
9d74191a 5097 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5098 bool writeback = true;
93c05d3e 5099 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5100
93c05d3e
XG		 5101 /*
5102 * Clear write_fault_to_shadow_pgtable here to ensure it is
5103 * never reused.
5104 */
5105 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5106 kvm_clear_exception_queue(vcpu);
8d7d8102 5107
571008da 5108 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5109 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5110
5111 /*
5112 * We will reenter on the same instruction since
5113 * we do not set complete_userspace_io. This does not
5114 * handle watchpoints yet, those would be handled in
5115 * the emulate_ops.
5116 */
5117 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5118 return r;
5119
9d74191a
TY		 5120 ctxt->interruptibility = 0;
5121 ctxt->have_exception = false;
5122 ctxt->perm_ok = false;
bbd9b64e 5123
b51e974f 5124 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5125
9d74191a 5126 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5127
e46479f8 5128 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5129 ++vcpu->stat.insn_emulation;
1d2887e2 5130 if (r != EMULATION_OK) {
4005996e
AK		 5131 if (emulation_type & EMULTYPE_TRAP_UD)
5132 return EMULATE_FAIL;
991eebf9
GN		 5133 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5134 emulation_type))
bbd9b64e 5135 return EMULATE_DONE;
6d77dbfc
GN		 5136 if (emulation_type & EMULTYPE_SKIP)
5137 return EMULATE_FAIL;
5138 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5139 }
5140 }
5141
ba8afb6b 5142 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5143 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5144 return EMULATE_DONE;
5145 }
5146
1cb3f3ae
XG		 5147 if (retry_instruction(ctxt, cr2, emulation_type))
5148 return EMULATE_DONE;
5149
7ae441ea 5150 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5151 changes registers values during IO operation */
7ae441ea
GN		 5152 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5153 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5154 emulator_invalidate_register_cache(ctxt);
7ae441ea 5155 }
4d2179e1 5156
5cd21917 5157restart:
9d74191a 5158 r = x86_emulate_insn(ctxt);
bbd9b64e 5159
775fde86
JR		 5160 if (r == EMULATION_INTERCEPTED)
5161 return EMULATE_DONE;
5162
d2ddd1c4 5163 if (r == EMULATION_FAILED) {
991eebf9
GN		 5164 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5165 emulation_type))
c3cd7ffa
GN		 5166 return EMULATE_DONE;
5167
6d77dbfc 5168 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5169 }
5170
9d74191a 5171 if (ctxt->have_exception) {
54b8486f 5172 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5173 r = EMULATE_DONE;
5174 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5175 if (!vcpu->arch.pio.in) {
5176 /* FIXME: return into emulator if single-stepping. */
3457e419 5177 vcpu->arch.pio.count = 0;
0912c977 5178 } else {
7ae441ea 5179 writeback = false;
716d51ab
GN		 5180 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5181 }
ac0a48c3 5182 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5183 } else if (vcpu->mmio_needed) {
5184 if (!vcpu->mmio_is_write)
5185 writeback = false;
ac0a48c3 5186 r = EMULATE_USER_EXIT;
716d51ab 5187 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5188 } else if (r == EMULATION_RESTART)
5cd21917 5189 goto restart;
d2ddd1c4
GN		 5190 else
5191 r = EMULATE_DONE;
f850e2e6 5192
7ae441ea 5193 if (writeback) {
9d74191a 5194 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5195 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5196 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5197 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5198 if (r == EMULATE_DONE)
5199 kvm_vcpu_check_singlestep(vcpu, &r);
5200 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5201 } else
5202 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5203
5204 return r;
de7d789a 5205}
51d8b661 5206EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5207
cf8f70bf 5208int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5209{
cf8f70bf 5210 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5211 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5212 size, port, &val, 1);
cf8f70bf 5213 /* do not return to emulator after return from userspace */
7972995b 5214 vcpu->arch.pio.count = 0;
de7d789a
CO		 5215 return ret;
5216}
cf8f70bf 5217EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5218
8cfdc000
ZA		 5219static void tsc_bad(void *info)
5220{
0a3aee0d 5221 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5222}
5223
5224static void tsc_khz_changed(void *data)
c8076604 5225{
8cfdc000
ZA		 5226 struct cpufreq_freqs *freq = data;
5227 unsigned long khz = 0;
5228
5229 if (data)
5230 khz = freq->new;
5231 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5232 khz = cpufreq_quick_get(raw_smp_processor_id());
5233 if (!khz)
5234 khz = tsc_khz;
0a3aee0d 5235 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5236}
5237
c8076604
GH		 5238static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5239 void *data)
5240{
5241 struct cpufreq_freqs *freq = data;
5242 struct kvm *kvm;
5243 struct kvm_vcpu *vcpu;
5244 int i, send_ipi = 0;
5245
8cfdc000
ZA		 5246 /*
5247 * We allow guests to temporarily run on slowing clocks,
5248 * provided we notify them after, or to run on accelerating
5249 * clocks, provided we notify them before. Thus time never
5250 * goes backwards.
5251 *
5252 * However, we have a problem. We can't atomically update
5253 * the frequency of a given CPU from this function; it is
5254 * merely a notifier, which can be called from any CPU.
5255 * Changing the TSC frequency at arbitrary points in time
5256 * requires a recomputation of local variables related to
5257 * the TSC for each VCPU. We must flag these local variables
5258 * to be updated and be sure the update takes place with the
5259 * new frequency before any guests proceed.
5260 *
5261 * Unfortunately, the combination of hotplug CPU and frequency
5262 * change creates an intractable locking scenario; the order
5263 * of when these callouts happen is undefined with respect to
5264 * CPU hotplug, and they can race with each other. As such,
5265 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5266 * undefined; you can actually have a CPU frequency change take
5267 * place in between the computation of X and the setting of the
5268 * variable. To protect against this problem, all updates of
5269 * the per_cpu tsc_khz variable are done in an interrupt
5270 * protected IPI, and all callers wishing to update the value
5271 * must wait for a synchronous IPI to complete (which is trivial
5272 * if the caller is on the CPU already). This establishes the
5273 * necessary total order on variable updates.
5274 *
5275 * Note that because a guest time update may take place
5276 * anytime after the setting of the VCPU's request bit, the
5277 * correct TSC value must be set before the request. However,
5278 * to ensure the update actually makes it to any guest which
5279 * starts running in hardware virtualization between the set
5280 * and the acquisition of the spinlock, we must also ping the
5281 * CPU after setting the request bit.
5282 *
5283 */
5284
c8076604
GH		 5285 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5286 return 0;
5287 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5288 return 0;
8cfdc000
ZA		 5289
5290 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5291
2f303b74 5292 spin_lock(&kvm_lock);
c8076604 5293 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5294 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5295 if (vcpu->cpu != freq->cpu)
5296 continue;
c285545f 5297 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5298 if (vcpu->cpu != smp_processor_id())
8cfdc000 5299 send_ipi = 1;
c8076604
GH		 5300 }
5301 }
2f303b74 5302 spin_unlock(&kvm_lock);
c8076604
GH		 5303
5304 if (freq->old < freq->new && send_ipi) {
5305 /*
5306 * We upscale the frequency. Must make the guest
5307 * doesn't see old kvmclock values while running with
5308 * the new frequency, otherwise we risk the guest sees
5309 * time go backwards.
5310 *
5311 * In case we update the frequency for another cpu
5312 * (which might be in guest context) send an interrupt
5313 * to kick the cpu out of guest context. Next time
5314 * guest context is entered kvmclock will be updated,
5315 * so the guest will not see stale values.
5316 */
8cfdc000 5317 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5318 }
5319 return 0;
5320}
5321
5322static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5323 .notifier_call = kvmclock_cpufreq_notifier
5324};
5325
5326static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5327 unsigned long action, void *hcpu)
5328{
5329 unsigned int cpu = (unsigned long)hcpu;
5330
5331 switch (action) {
5332 case CPU_ONLINE:
5333 case CPU_DOWN_FAILED:
5334 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5335 break;
5336 case CPU_DOWN_PREPARE:
5337 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5338 break;
5339 }
5340 return NOTIFY_OK;
5341}
5342
5343static struct notifier_block kvmclock_cpu_notifier_block = {
5344 .notifier_call = kvmclock_cpu_notifier,
5345 .priority = -INT_MAX
c8076604
GH		 5346};
5347
b820cc0c
ZA		 5348static void kvm_timer_init(void)
5349{
5350 int cpu;
5351
c285545f 5352 max_tsc_khz = tsc_khz;
8cfdc000 5353 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5354 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5355#ifdef CONFIG_CPU_FREQ
5356 struct cpufreq_policy policy;
5357 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5358 cpu = get_cpu();
5359 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5360 if (policy.cpuinfo.max_freq)
5361 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5362 put_cpu();
c285545f 5363#endif
b820cc0c
ZA		 5364 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5365 CPUFREQ_TRANSITION_NOTIFIER);
5366 }
c285545f 5367 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5368 for_each_online_cpu(cpu)
5369 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5370}
5371
ff9d07a0
ZY		 5372static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5373
f5132b01 5374int kvm_is_in_guest(void)
ff9d07a0 5375{
086c9855 5376 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5377}
5378
5379static int kvm_is_user_mode(void)
5380{
5381 int user_mode = 3;
dcf46b94 5382
086c9855
AS		 5383 if (__this_cpu_read(current_vcpu))
5384 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5385
ff9d07a0
ZY		 5386 return user_mode != 0;
5387}
5388
5389static unsigned long kvm_get_guest_ip(void)
5390{
5391 unsigned long ip = 0;
dcf46b94 5392
086c9855
AS		 5393 if (__this_cpu_read(current_vcpu))
5394 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5395
ff9d07a0
ZY		 5396 return ip;
5397}
5398
5399static struct perf_guest_info_callbacks kvm_guest_cbs = {
5400 .is_in_guest = kvm_is_in_guest,
5401 .is_user_mode = kvm_is_user_mode,
5402 .get_guest_ip = kvm_get_guest_ip,
5403};
5404
5405void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5406{
086c9855 5407 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5408}
5409EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5410
5411void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5412{
086c9855 5413 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5414}
5415EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5416
ce88decf
XG		 5417static void kvm_set_mmio_spte_mask(void)
5418{
5419 u64 mask;
5420 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5421
5422 /*
5423 * Set the reserved bits and the present bit of an paging-structure
5424 * entry to generate page fault with PFER.RSV = 1.
5425 */
885032b9
XG		 5426 /* Mask the reserved physical address bits. */
5427 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5428
5429 /* Bit 62 is always reserved for 32bit host. */
5430 mask |= 0x3ull << 62;
5431
5432 /* Set the present bit. */
ce88decf
XG		 5433 mask |= 1ull;
5434
5435#ifdef CONFIG_X86_64
5436 /*
5437 * If reserved bit is not supported, clear the present bit to disable
5438 * mmio page fault.
5439 */
5440 if (maxphyaddr == 52)
5441 mask &= ~1ull;
5442#endif
5443
5444 kvm_mmu_set_mmio_spte_mask(mask);
5445}
5446
16e8d74d
MT		 5447#ifdef CONFIG_X86_64
5448static void pvclock_gtod_update_fn(struct work_struct *work)
5449{
d828199e
MT		 5450 struct kvm *kvm;
5451
5452 struct kvm_vcpu *vcpu;
5453 int i;
5454
2f303b74 5455 spin_lock(&kvm_lock);
d828199e
MT		 5456 list_for_each_entry(kvm, &vm_list, vm_list)
5457 kvm_for_each_vcpu(i, vcpu, kvm)
5458 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5459 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5460 spin_unlock(&kvm_lock);
16e8d74d
MT		 5461}
5462
5463static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5464
5465/*
5466 * Notification about pvclock gtod data update.
5467 */
5468static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5469 void *priv)
5470{
5471 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5472 struct timekeeper *tk = priv;
5473
5474 update_pvclock_gtod(tk);
5475
5476 /* disable master clock if host does not trust, or does not
5477 * use, TSC clocksource
5478 */
5479 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5480 atomic_read(&kvm_guest_has_master_clock) != 0)
5481 queue_work(system_long_wq, &pvclock_gtod_work);
5482
5483 return 0;
5484}
5485
5486static struct notifier_block pvclock_gtod_notifier = {
5487 .notifier_call = pvclock_gtod_notify,
5488};
5489#endif
5490
f8c16bba 5491int kvm_arch_init(void *opaque)
043405e1 5492{
b820cc0c 5493 int r;
6b61edf7 5494 struct kvm_x86_ops *ops = opaque;
f8c16bba 5495
f8c16bba
ZX		 5496 if (kvm_x86_ops) {
5497 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5498 r = -EEXIST;
5499 goto out;
f8c16bba
ZX		 5500 }
5501
5502 if (!ops->cpu_has_kvm_support()) {
5503 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5504 r = -EOPNOTSUPP;
5505 goto out;
f8c16bba
ZX		 5506 }
5507 if (ops->disabled_by_bios()) {
5508 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5509 r = -EOPNOTSUPP;
5510 goto out;
f8c16bba
ZX		 5511 }
5512
013f6a5d
MT		 5513 r = -ENOMEM;
5514 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5515 if (!shared_msrs) {
5516 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5517 goto out;
5518 }
5519
97db56ce
AK		 5520 r = kvm_mmu_module_init();
5521 if (r)
013f6a5d 5522 goto out_free_percpu;
97db56ce 5523
ce88decf 5524 kvm_set_mmio_spte_mask();
97db56ce
AK		 5525 kvm_init_msr_list();
5526
f8c16bba 5527 kvm_x86_ops = ops;
7b52345e 5528 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5529 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5530
b820cc0c 5531 kvm_timer_init();
c8076604 5532
ff9d07a0
ZY		 5533 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5534
2acf923e
DC		 5535 if (cpu_has_xsave)
5536 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5537
c5cc421b 5538 kvm_lapic_init();
16e8d74d
MT		 5539#ifdef CONFIG_X86_64
5540 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5541#endif
5542
f8c16bba 5543 return 0;
56c6d28a 5544
013f6a5d
MT		 5545out_free_percpu:
5546 free_percpu(shared_msrs);
56c6d28a 5547out:
56c6d28a 5548 return r;
043405e1 5549}
8776e519 5550
f8c16bba
ZX		 5551void kvm_arch_exit(void)
5552{
ff9d07a0
ZY		 5553 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5554
888d256e
JK		 5555 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5556 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5557 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5558 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5559#ifdef CONFIG_X86_64
5560 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5561#endif
f8c16bba 5562 kvm_x86_ops = NULL;
56c6d28a 5563 kvm_mmu_module_exit();
013f6a5d 5564 free_percpu(shared_msrs);
56c6d28a 5565}
f8c16bba 5566
8776e519
HB		 5567int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5568{
5569 ++vcpu->stat.halt_exits;
5570 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5571 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5572 return 1;
5573 } else {
5574 vcpu->run->exit_reason = KVM_EXIT_HLT;
5575 return 0;
5576 }
5577}
5578EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5579
55cd8e5a
GN		 5580int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5581{
5582 u64 param, ingpa, outgpa, ret;
5583 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5584 bool fast, longmode;
5585 int cs_db, cs_l;
5586
5587 /*
5588 * hypercall generates UD from non zero cpl and real mode
5589 * per HYPER-V spec
5590 */
3eeb3288 5591 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5592 kvm_queue_exception(vcpu, UD_VECTOR);
5593 return 0;
5594 }
5595
5596 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5597 longmode = is_long_mode(vcpu) && cs_l == 1;
5598
5599 if (!longmode) {
ccd46936
GN		 5600 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5601 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5602 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5603 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5604 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5605 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5606 }
5607#ifdef CONFIG_X86_64
5608 else {
5609 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5610 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5611 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5612 }
5613#endif
5614
5615 code = param & 0xffff;
5616 fast = (param >> 16) & 0x1;
5617 rep_cnt = (param >> 32) & 0xfff;
5618 rep_idx = (param >> 48) & 0xfff;
5619
5620 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5621
c25bc163
GN		 5622 switch (code) {
5623 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5624 kvm_vcpu_on_spin(vcpu);
5625 break;
5626 default:
5627 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5628 break;
5629 }
55cd8e5a
GN		 5630
5631 ret = res | (((u64)rep_done & 0xfff) << 32);
5632 if (longmode) {
5633 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5634 } else {
5635 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5636 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5637 }
5638
5639 return 1;
5640}
5641
6aef266c
SV		 5642/*
5643 * kvm_pv_kick_cpu_op: Kick a vcpu.
5644 *
5645 * @apicid - apicid of vcpu to be kicked.
5646 */
5647static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5648{
24d2166b 5649 struct kvm_lapic_irq lapic_irq;
6aef266c 5650
24d2166b
R		 5651 lapic_irq.shorthand = 0;
5652 lapic_irq.dest_mode = 0;
5653 lapic_irq.dest_id = apicid;
6aef266c 5654
24d2166b
R		 5655 lapic_irq.delivery_mode = APIC_DM_REMRD;
5656 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5657}
5658
8776e519
HB		 5659int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5660{
5661 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5662 int r = 1;
8776e519 5663
55cd8e5a
GN		 5664 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5665 return kvm_hv_hypercall(vcpu);
5666
5fdbf976
MT		 5667 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5668 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5669 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5670 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5671 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5672
229456fc 5673 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5674
8776e519
HB		 5675 if (!is_long_mode(vcpu)) {
5676 nr &= 0xFFFFFFFF;
5677 a0 &= 0xFFFFFFFF;
5678 a1 &= 0xFFFFFFFF;
5679 a2 &= 0xFFFFFFFF;
5680 a3 &= 0xFFFFFFFF;
5681 }
5682
07708c4a
JK		 5683 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5684 ret = -KVM_EPERM;
5685 goto out;
5686 }
5687
8776e519 5688 switch (nr) {
b93463aa
AK		 5689 case KVM_HC_VAPIC_POLL_IRQ:
5690 ret = 0;
5691 break;
6aef266c
SV		 5692 case KVM_HC_KICK_CPU:
5693 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5694 ret = 0;
5695 break;
8776e519
HB		 5696 default:
5697 ret = -KVM_ENOSYS;
5698 break;
5699 }
07708c4a 5700out:
5fdbf976 5701 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5702 ++vcpu->stat.hypercalls;
2f333bcb 5703 return r;
8776e519
HB		 5704}
5705EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5706
b6785def 5707static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5708{
d6aa1000 5709 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5710 char instruction[3];
5fdbf976 5711 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5712
8776e519 5713 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5714
9d74191a 5715 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5716}
5717
b6c7a5dc
HB		 5718/*
5719 * Check if userspace requested an interrupt window, and that the
5720 * interrupt window is open.
5721 *
5722 * No need to exit to userspace if we already have an interrupt queued.
5723 */
851ba692 5724static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5725{
8061823a 5726 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5727 vcpu->run->request_interrupt_window &&
5df56646 5728 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5729}
5730
851ba692 5731static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5732{
851ba692
AK		 5733 struct kvm_run *kvm_run = vcpu->run;
5734
91586a3b 5735 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5736 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5737 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5738 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5739 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5740 else
b6c7a5dc 5741 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5742 kvm_arch_interrupt_allowed(vcpu) &&
5743 !kvm_cpu_has_interrupt(vcpu) &&
5744 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5745}
5746
95ba8273
GN		 5747static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5748{
5749 int max_irr, tpr;
5750
5751 if (!kvm_x86_ops->update_cr8_intercept)
5752 return;
5753
88c808fd
AK		 5754 if (!vcpu->arch.apic)
5755 return;
5756
8db3baa2
GN		 5757 if (!vcpu->arch.apic->vapic_addr)
5758 max_irr = kvm_lapic_find_highest_irr(vcpu);
5759 else
5760 max_irr = -1;
95ba8273
GN		 5761
5762 if (max_irr != -1)
5763 max_irr >>= 4;
5764
5765 tpr = kvm_lapic_get_cr8(vcpu);
5766
5767 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5768}
5769
851ba692 5770static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5771{
5772 /* try to reinject previous events if any */
b59bb7bd 5773 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5774 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5775 vcpu->arch.exception.has_error_code,
5776 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5777 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5778 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5779 vcpu->arch.exception.error_code,
5780 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5781 return;
5782 }
5783
95ba8273
GN		 5784 if (vcpu->arch.nmi_injected) {
5785 kvm_x86_ops->set_nmi(vcpu);
5786 return;
5787 }
5788
5789 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5790 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5791 return;
5792 }
5793
5794 /* try to inject new event if pending */
5795 if (vcpu->arch.nmi_pending) {
5796 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5797 --vcpu->arch.nmi_pending;
95ba8273
GN		 5798 vcpu->arch.nmi_injected = true;
5799 kvm_x86_ops->set_nmi(vcpu);
5800 }
c7c9c56c 5801 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5802 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5803 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5804 false);
5805 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5806 }
5807 }
5808}
5809
7460fb4a
AK		 5810static void process_nmi(struct kvm_vcpu *vcpu)
5811{
5812 unsigned limit = 2;
5813
5814 /*
5815 * x86 is limited to one NMI running, and one NMI pending after it.
5816 * If an NMI is already in progress, limit further NMIs to just one.
5817 * Otherwise, allow two (and we'll inject the first one immediately).
5818 */
5819 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5820 limit = 1;
5821
5822 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5823 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5824 kvm_make_request(KVM_REQ_EVENT, vcpu);
5825}
5826
3d81bc7e 5827static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5828{
5829 u64 eoi_exit_bitmap[4];
cf9e65b7 5830 u32 tmr[8];
c7c9c56c 5831
3d81bc7e
YZ		 5832 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5833 return;
c7c9c56c
YZ		 5834
5835 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5836 memset(tmr, 0, 32);
c7c9c56c 5837
cf9e65b7 5838 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5839 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5840 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5841}
5842
9357d939
TY		 5843/*
5844 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5845 * exiting to the userspace. Otherwise, the value will be returned to the
5846 * userspace.
5847 */
851ba692 5848static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5849{
5850 int r;
6a8b1d13 5851 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5852 vcpu->run->request_interrupt_window;
730dca42 5853 bool req_immediate_exit = false;
b6c7a5dc 5854
3e007509 5855 if (vcpu->requests) {
a8eeb04a 5856 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5857 kvm_mmu_unload(vcpu);
a8eeb04a 5858 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5859 __kvm_migrate_timers(vcpu);
d828199e
MT		 5860 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5861 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5862 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5863 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5864 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5865 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5866 if (unlikely(r))
5867 goto out;
5868 }
a8eeb04a 5869 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5870 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5871 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5872 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5873 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5874 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5875 r = 0;
5876 goto out;
5877 }
a8eeb04a 5878 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5879 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5880 r = 0;
5881 goto out;
5882 }
a8eeb04a 5883 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5884 vcpu->fpu_active = 0;
5885 kvm_x86_ops->fpu_deactivate(vcpu);
5886 }
af585b92
GN		 5887 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5888 /* Page is swapped out. Do synthetic halt */
5889 vcpu->arch.apf.halted = true;
5890 r = 1;
5891 goto out;
5892 }
c9aaa895
GC		 5893 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5894 record_steal_time(vcpu);
7460fb4a
AK		 5895 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5896 process_nmi(vcpu);
f5132b01
GN		 5897 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5898 kvm_handle_pmu_event(vcpu);
5899 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5900 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5901 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5902 vcpu_scan_ioapic(vcpu);
2f52d58c 5903 }
b93463aa 5904
b463a6f7 5905 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5906 kvm_apic_accept_events(vcpu);
5907 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5908 r = 1;
5909 goto out;
5910 }
5911
b463a6f7
AK		 5912 inject_pending_event(vcpu);
5913
5914 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5915 if (vcpu->arch.nmi_pending)
03b28f81
JK		 5916 req_immediate_exit =
5917 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
c7c9c56c 5918 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
730dca42
JK		 5919 req_immediate_exit =
5920 kvm_x86_ops->enable_irq_window(vcpu) != 0;
b463a6f7
AK		 5921
5922 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5923 /*
5924 * Update architecture specific hints for APIC
5925 * virtual interrupt delivery.
5926 */
5927 if (kvm_x86_ops->hwapic_irr_update)
5928 kvm_x86_ops->hwapic_irr_update(vcpu,
5929 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5930 update_cr8_intercept(vcpu);
5931 kvm_lapic_sync_to_vapic(vcpu);
5932 }
5933 }
5934
d8368af8
AK		 5935 r = kvm_mmu_reload(vcpu);
5936 if (unlikely(r)) {
d905c069 5937 goto cancel_injection;
d8368af8
AK		 5938 }
5939
b6c7a5dc
HB		 5940 preempt_disable();
5941
5942 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5943 if (vcpu->fpu_active)
5944 kvm_load_guest_fpu(vcpu);
2acf923e 5945 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5946
6b7e2d09
XG		 5947 vcpu->mode = IN_GUEST_MODE;
5948
01b71917
MT		 5949 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5950
6b7e2d09
XG		 5951 /* We should set ->mode before check ->requests,
5952 * see the comment in make_all_cpus_request.
5953 */
01b71917 5954 smp_mb__after_srcu_read_unlock();
b6c7a5dc 5955
d94e1dc9 5956 local_irq_disable();
32f88400 5957
6b7e2d09 5958 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5959 || need_resched() || signal_pending(current)) {
6b7e2d09 5960 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5961 smp_wmb();
6c142801
AK		 5962 local_irq_enable();
5963 preempt_enable();
01b71917 5964 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 5965 r = 1;
d905c069 5966 goto cancel_injection;
6c142801
AK		 5967 }
5968
d6185f20
NHE		 5969 if (req_immediate_exit)
5970 smp_send_reschedule(vcpu->cpu);
5971
b6c7a5dc
HB		 5972 kvm_guest_enter();
5973
42dbaa5a 5974 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5975 set_debugreg(0, 7);
5976 set_debugreg(vcpu->arch.eff_db[0], 0);
5977 set_debugreg(vcpu->arch.eff_db[1], 1);
5978 set_debugreg(vcpu->arch.eff_db[2], 2);
5979 set_debugreg(vcpu->arch.eff_db[3], 3);
5980 }
b6c7a5dc 5981
229456fc 5982 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5983 kvm_x86_ops->run(vcpu);
b6c7a5dc 5984
24f1e32c
FW		 5985 /*
5986 * If the guest has used debug registers, at least dr7
5987 * will be disabled while returning to the host.
5988 * If we don't have active breakpoints in the host, we don't
5989 * care about the messed up debug address registers. But if
5990 * we have some of them active, restore the old state.
5991 */
59d8eb53 5992 if (hw_breakpoint_active())
24f1e32c 5993 hw_breakpoint_restore();
42dbaa5a 5994
886b470c
MT		 5995 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5996 native_read_tsc());
1d5f066e 5997
6b7e2d09 5998 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5999 smp_wmb();
a547c6db
YZ		 6000
6001 /* Interrupt is enabled by handle_external_intr() */
6002 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6003
6004 ++vcpu->stat.exits;
6005
6006 /*
6007 * We must have an instruction between local_irq_enable() and
6008 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6009 * the interrupt shadow. The stat.exits increment will do nicely.
6010 * But we need to prevent reordering, hence this barrier():
6011 */
6012 barrier();
6013
6014 kvm_guest_exit();
6015
6016 preempt_enable();
6017
f656ce01 6018 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6019
b6c7a5dc
HB		 6020 /*
6021 * Profile KVM exit RIPs:
6022 */
6023 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6024 unsigned long rip = kvm_rip_read(vcpu);
6025 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6026 }
6027
cc578287
ZA		 6028 if (unlikely(vcpu->arch.tsc_always_catchup))
6029 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6030
5cfb1d5a
MT		 6031 if (vcpu->arch.apic_attention)
6032 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6033
851ba692 6034 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6035 return r;
6036
6037cancel_injection:
6038 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6039 if (unlikely(vcpu->arch.apic_attention))
6040 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6041out:
6042 return r;
6043}
b6c7a5dc 6044
09cec754 6045
851ba692 6046static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6047{
6048 int r;
f656ce01 6049 struct kvm *kvm = vcpu->kvm;
d7690175 6050
f656ce01 6051 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6052
6053 r = 1;
6054 while (r > 0) {
af585b92
GN		 6055 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6056 !vcpu->arch.apf.halted)
851ba692 6057 r = vcpu_enter_guest(vcpu);
d7690175 6058 else {
f656ce01 6059 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6060 kvm_vcpu_block(vcpu);
f656ce01 6061 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6062 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6063 kvm_apic_accept_events(vcpu);
09cec754
GN		 6064 switch(vcpu->arch.mp_state) {
6065 case KVM_MP_STATE_HALTED:
6aef266c 6066 vcpu->arch.pv.pv_unhalted = false;
d7690175 6067 vcpu->arch.mp_state =
09cec754
GN		 6068 KVM_MP_STATE_RUNNABLE;
6069 case KVM_MP_STATE_RUNNABLE:
af585b92 6070 vcpu->arch.apf.halted = false;
09cec754 6071 break;
66450a21
JK		 6072 case KVM_MP_STATE_INIT_RECEIVED:
6073 break;
09cec754
GN		 6074 default:
6075 r = -EINTR;
6076 break;
6077 }
6078 }
d7690175
MT		 6079 }
6080
09cec754
GN		 6081 if (r <= 0)
6082 break;
6083
6084 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6085 if (kvm_cpu_has_pending_timer(vcpu))
6086 kvm_inject_pending_timer_irqs(vcpu);
6087
851ba692 6088 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6089 r = -EINTR;
851ba692 6090 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6091 ++vcpu->stat.request_irq_exits;
6092 }
af585b92
GN		 6093
6094 kvm_check_async_pf_completion(vcpu);
6095
09cec754
GN		 6096 if (signal_pending(current)) {
6097 r = -EINTR;
851ba692 6098 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6099 ++vcpu->stat.signal_exits;
6100 }
6101 if (need_resched()) {
f656ce01 6102 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6103 cond_resched();
f656ce01 6104 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6105 }
b6c7a5dc
HB		 6106 }
6107
f656ce01 6108 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6109
6110 return r;
6111}
6112
716d51ab
GN		 6113static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6114{
6115 int r;
6116 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6117 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6118 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6119 if (r != EMULATE_DONE)
6120 return 0;
6121 return 1;
6122}
6123
6124static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6125{
6126 BUG_ON(!vcpu->arch.pio.count);
6127
6128 return complete_emulated_io(vcpu);
6129}
6130
f78146b0
AK		 6131/*
6132 * Implements the following, as a state machine:
6133 *
6134 * read:
6135 * for each fragment
87da7e66
XG		 6136 * for each mmio piece in the fragment
6137 * write gpa, len
6138 * exit
6139 * copy data
f78146b0
AK		 6140 * execute insn
6141 *
6142 * write:
6143 * for each fragment
87da7e66
XG		 6144 * for each mmio piece in the fragment
6145 * write gpa, len
6146 * copy data
6147 * exit
f78146b0 6148 */
716d51ab 6149static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6150{
6151 struct kvm_run *run = vcpu->run;
f78146b0 6152 struct kvm_mmio_fragment *frag;
87da7e66 6153 unsigned len;
5287f194 6154
716d51ab 6155 BUG_ON(!vcpu->mmio_needed);
5287f194 6156
716d51ab 6157 /* Complete previous fragment */
87da7e66
XG		 6158 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6159 len = min(8u, frag->len);
716d51ab 6160 if (!vcpu->mmio_is_write)
87da7e66
XG		 6161 memcpy(frag->data, run->mmio.data, len);
6162
6163 if (frag->len <= 8) {
6164 /* Switch to the next fragment. */
6165 frag++;
6166 vcpu->mmio_cur_fragment++;
6167 } else {
6168 /* Go forward to the next mmio piece. */
6169 frag->data += len;
6170 frag->gpa += len;
6171 frag->len -= len;
6172 }
6173
716d51ab
GN		 6174 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6175 vcpu->mmio_needed = 0;
0912c977
PB		 6176
6177 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6178 if (vcpu->mmio_is_write)
716d51ab
GN		 6179 return 1;
6180 vcpu->mmio_read_completed = 1;
6181 return complete_emulated_io(vcpu);
6182 }
87da7e66 6183
716d51ab
GN		 6184 run->exit_reason = KVM_EXIT_MMIO;
6185 run->mmio.phys_addr = frag->gpa;
6186 if (vcpu->mmio_is_write)
87da7e66
XG		 6187 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6188 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6189 run->mmio.is_write = vcpu->mmio_is_write;
6190 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6191 return 0;
5287f194
AK		 6192}
6193
716d51ab 6194
b6c7a5dc
HB		 6195int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6196{
6197 int r;
6198 sigset_t sigsaved;
6199
e5c30142
AK		 6200 if (!tsk_used_math(current) && init_fpu(current))
6201 return -ENOMEM;
6202
ac9f6dc0
AK		 6203 if (vcpu->sigset_active)
6204 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6205
a4535290 6206 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6207 kvm_vcpu_block(vcpu);
66450a21 6208 kvm_apic_accept_events(vcpu);
d7690175 6209 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6210 r = -EAGAIN;
6211 goto out;
b6c7a5dc
HB		 6212 }
6213
b6c7a5dc 6214 /* re-sync apic's tpr */
eea1cff9
AP		 6215 if (!irqchip_in_kernel(vcpu->kvm)) {
6216 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6217 r = -EINVAL;
6218 goto out;
6219 }
6220 }
b6c7a5dc 6221
716d51ab
GN		 6222 if (unlikely(vcpu->arch.complete_userspace_io)) {
6223 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6224 vcpu->arch.complete_userspace_io = NULL;
6225 r = cui(vcpu);
6226 if (r <= 0)
6227 goto out;
6228 } else
6229 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6230
851ba692 6231 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6232
6233out:
f1d86e46 6234 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6235 if (vcpu->sigset_active)
6236 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6237
b6c7a5dc
HB		 6238 return r;
6239}
6240
6241int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6242{
7ae441ea
GN		 6243 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6244 /*
6245 * We are here if userspace calls get_regs() in the middle of
6246 * instruction emulation. Registers state needs to be copied
4a969980 6247 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6248 * that usually, but some bad designed PV devices (vmware
6249 * backdoor interface) need this to work
6250 */
dd856efa 6251 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6252 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6253 }
5fdbf976
MT		 6254 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6255 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6256 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6257 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6258 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6259 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6260 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6261 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6262#ifdef CONFIG_X86_64
5fdbf976
MT		 6263 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6264 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6265 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6266 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6267 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6268 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6269 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6270 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6271#endif
6272
5fdbf976 6273 regs->rip = kvm_rip_read(vcpu);
91586a3b 6274 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6275
b6c7a5dc
HB		 6276 return 0;
6277}
6278
6279int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6280{
7ae441ea
GN		 6281 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6282 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6283
5fdbf976
MT		 6284 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6285 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6286 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6287 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6288 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6289 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6290 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6291 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6292#ifdef CONFIG_X86_64
5fdbf976
MT		 6293 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6294 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6295 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6296 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6297 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6298 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6299 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6300 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6301#endif
6302
5fdbf976 6303 kvm_rip_write(vcpu, regs->rip);
91586a3b 6304 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6305
b4f14abd
JK		 6306 vcpu->arch.exception.pending = false;
6307
3842d135
AK		 6308 kvm_make_request(KVM_REQ_EVENT, vcpu);
6309
b6c7a5dc
HB		 6310 return 0;
6311}
6312
b6c7a5dc
HB		 6313void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6314{
6315 struct kvm_segment cs;
6316
3e6e0aab 6317 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6318 *db = cs.db;
6319 *l = cs.l;
6320}
6321EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6322
6323int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6324 struct kvm_sregs *sregs)
6325{
89a27f4d 6326 struct desc_ptr dt;
b6c7a5dc 6327
3e6e0aab
GT		 6328 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6329 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6330 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6331 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6332 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6333 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6334
3e6e0aab
GT		 6335 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6336 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6337
6338 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6339 sregs->idt.limit = dt.size;
6340 sregs->idt.base = dt.address;
b6c7a5dc 6341 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6342 sregs->gdt.limit = dt.size;
6343 sregs->gdt.base = dt.address;
b6c7a5dc 6344
4d4ec087 6345 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6346 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6347 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6348 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6349 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6350 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6351 sregs->apic_base = kvm_get_apic_base(vcpu);
6352
923c61bb 6353 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6354
36752c9b 6355 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6356 set_bit(vcpu->arch.interrupt.nr,
6357 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6358
b6c7a5dc
HB		 6359 return 0;
6360}
6361
62d9f0db
MT		 6362int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6363 struct kvm_mp_state *mp_state)
6364{
66450a21 6365 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6366 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6367 vcpu->arch.pv.pv_unhalted)
6368 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6369 else
6370 mp_state->mp_state = vcpu->arch.mp_state;
6371
62d9f0db
MT		 6372 return 0;
6373}
6374
6375int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6376 struct kvm_mp_state *mp_state)
6377{
66450a21
JK		 6378 if (!kvm_vcpu_has_lapic(vcpu) &&
6379 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6380 return -EINVAL;
6381
6382 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6383 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6384 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6385 } else
6386 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6387 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6388 return 0;
6389}
6390
7f3d35fd
KW		 6391int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6392 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6393{
9d74191a 6394 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6395 int ret;
e01c2426 6396
8ec4722d 6397 init_emulate_ctxt(vcpu);
c697518a 6398
7f3d35fd 6399 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6400 has_error_code, error_code);
c697518a 6401
c697518a 6402 if (ret)
19d04437 6403 return EMULATE_FAIL;
37817f29 6404
9d74191a
TY		 6405 kvm_rip_write(vcpu, ctxt->eip);
6406 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6407 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6408 return EMULATE_DONE;
37817f29
IE		 6409}
6410EXPORT_SYMBOL_GPL(kvm_task_switch);
6411
b6c7a5dc
HB		 6412int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6413 struct kvm_sregs *sregs)
6414{
6415 int mmu_reset_needed = 0;
63f42e02 6416 int pending_vec, max_bits, idx;
89a27f4d 6417 struct desc_ptr dt;
b6c7a5dc 6418
6d1068b3
PM		 6419 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6420 return -EINVAL;
6421
89a27f4d
GN		 6422 dt.size = sregs->idt.limit;
6423 dt.address = sregs->idt.base;
b6c7a5dc 6424 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6425 dt.size = sregs->gdt.limit;
6426 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6427 kvm_x86_ops->set_gdt(vcpu, &dt);
6428
ad312c7c 6429 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6430 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6431 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6432 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6433
2d3ad1f4 6434 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6435
f6801dff 6436 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6437 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6438 kvm_set_apic_base(vcpu, sregs->apic_base);
6439
4d4ec087 6440 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6441 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6442 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6443
fc78f519 6444 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6445 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6446 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6447 kvm_update_cpuid(vcpu);
63f42e02
XG		 6448
6449 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6450 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6451 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6452 mmu_reset_needed = 1;
6453 }
63f42e02 6454 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6455
6456 if (mmu_reset_needed)
6457 kvm_mmu_reset_context(vcpu);
6458
a50abc3b 6459 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6460 pending_vec = find_first_bit(
6461 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6462 if (pending_vec < max_bits) {
66fd3f7f 6463 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6464 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6465 }
6466
3e6e0aab
GT		 6467 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6468 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6469 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6470 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6471 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6472 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6473
3e6e0aab
GT		 6474 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6475 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6476
5f0269f5
ME		 6477 update_cr8_intercept(vcpu);
6478
9c3e4aab 6479 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6480 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6481 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6482 !is_protmode(vcpu))
9c3e4aab
MT		 6483 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6484
3842d135
AK		 6485 kvm_make_request(KVM_REQ_EVENT, vcpu);
6486
b6c7a5dc
HB		 6487 return 0;
6488}
6489
d0bfb940
JK		 6490int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6491 struct kvm_guest_debug *dbg)
b6c7a5dc 6492{
355be0b9 6493 unsigned long rflags;
ae675ef0 6494 int i, r;
b6c7a5dc 6495
4f926bf2
JK		 6496 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6497 r = -EBUSY;
6498 if (vcpu->arch.exception.pending)
2122ff5e 6499 goto out;
4f926bf2
JK		 6500 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6501 kvm_queue_exception(vcpu, DB_VECTOR);
6502 else
6503 kvm_queue_exception(vcpu, BP_VECTOR);
6504 }
6505
91586a3b
JK		 6506 /*
6507 * Read rflags as long as potentially injected trace flags are still
6508 * filtered out.
6509 */
6510 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6511
6512 vcpu->guest_debug = dbg->control;
6513 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6514 vcpu->guest_debug = 0;
6515
6516 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6517 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6518 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6519 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6520 } else {
6521 for (i = 0; i < KVM_NR_DB_REGS; i++)
6522 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6523 }
c8639010 6524 kvm_update_dr7(vcpu);
ae675ef0 6525
f92653ee
JK		 6526 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6527 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6528 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6529
91586a3b
JK		 6530 /*
6531 * Trigger an rflags update that will inject or remove the trace
6532 * flags.
6533 */
6534 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6535
c8639010 6536 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6537
4f926bf2 6538 r = 0;
d0bfb940 6539
2122ff5e 6540out:
b6c7a5dc
HB		 6541
6542 return r;
6543}
6544
8b006791
ZX		 6545/*
6546 * Translate a guest virtual address to a guest physical address.
6547 */
6548int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6549 struct kvm_translation *tr)
6550{
6551 unsigned long vaddr = tr->linear_address;
6552 gpa_t gpa;
f656ce01 6553 int idx;
8b006791 6554
f656ce01 6555 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6556 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6557 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6558 tr->physical_address = gpa;
6559 tr->valid = gpa != UNMAPPED_GVA;
6560 tr->writeable = 1;
6561 tr->usermode = 0;
8b006791
ZX		 6562
6563 return 0;
6564}
6565
d0752060
HB		 6566int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6567{
98918833
SY		 6568 struct i387_fxsave_struct *fxsave =
6569 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6570
d0752060
HB		 6571 memcpy(fpu->fpr, fxsave->st_space, 128);
6572 fpu->fcw = fxsave->cwd;
6573 fpu->fsw = fxsave->swd;
6574 fpu->ftwx = fxsave->twd;
6575 fpu->last_opcode = fxsave->fop;
6576 fpu->last_ip = fxsave->rip;
6577 fpu->last_dp = fxsave->rdp;
6578 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6579
d0752060
HB		 6580 return 0;
6581}
6582
6583int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6584{
98918833
SY		 6585 struct i387_fxsave_struct *fxsave =
6586 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6587
d0752060
HB		 6588 memcpy(fxsave->st_space, fpu->fpr, 128);
6589 fxsave->cwd = fpu->fcw;
6590 fxsave->swd = fpu->fsw;
6591 fxsave->twd = fpu->ftwx;
6592 fxsave->fop = fpu->last_opcode;
6593 fxsave->rip = fpu->last_ip;
6594 fxsave->rdp = fpu->last_dp;
6595 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6596
d0752060
HB		 6597 return 0;
6598}
6599
10ab25cd 6600int fx_init(struct kvm_vcpu *vcpu)
d0752060 6601{
10ab25cd
JK		 6602 int err;
6603
6604 err = fpu_alloc(&vcpu->arch.guest_fpu);
6605 if (err)
6606 return err;
6607
98918833 6608 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6609
2acf923e
DC		 6610 /*
6611 * Ensure guest xcr0 is valid for loading
6612 */
6613 vcpu->arch.xcr0 = XSTATE_FP;
6614
ad312c7c 6615 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6616
6617 return 0;
d0752060
HB		 6618}
6619EXPORT_SYMBOL_GPL(fx_init);
6620
98918833
SY		 6621static void fx_free(struct kvm_vcpu *vcpu)
6622{
6623 fpu_free(&vcpu->arch.guest_fpu);
6624}
6625
d0752060
HB		 6626void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6627{
2608d7a1 6628 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6629 return;
6630
2acf923e
DC		 6631 /*
6632 * Restore all possible states in the guest,
6633 * and assume host would use all available bits.
6634 * Guest xcr0 would be loaded later.
6635 */
6636 kvm_put_guest_xcr0(vcpu);
d0752060 6637 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6638 __kernel_fpu_begin();
98918833 6639 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6640 trace_kvm_fpu(1);
d0752060 6641}
d0752060
HB		 6642
6643void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6644{
2acf923e
DC		 6645 kvm_put_guest_xcr0(vcpu);
6646
d0752060
HB		 6647 if (!vcpu->guest_fpu_loaded)
6648 return;
6649
6650 vcpu->guest_fpu_loaded = 0;
98918833 6651 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6652 __kernel_fpu_end();
f096ed85 6653 ++vcpu->stat.fpu_reload;
a8eeb04a 6654 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6655 trace_kvm_fpu(0);
d0752060 6656}
e9b11c17
ZX		 6657
6658void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6659{
12f9a48f 6660 kvmclock_reset(vcpu);
7f1ea208 6661
f5f48ee1 6662 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6663 fx_free(vcpu);
e9b11c17
ZX		 6664 kvm_x86_ops->vcpu_free(vcpu);
6665}
6666
6667struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6668 unsigned int id)
6669{
6755bae8
ZA		 6670 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6671 printk_once(KERN_WARNING
6672 "kvm: SMP vm created on host with unstable TSC; "
6673 "guest TSC will not be reliable\n");
26e5215f
AK		 6674 return kvm_x86_ops->vcpu_create(kvm, id);
6675}
e9b11c17 6676
26e5215f
AK		 6677int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6678{
6679 int r;
e9b11c17 6680
0bed3b56 6681 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6682 r = vcpu_load(vcpu);
6683 if (r)
6684 return r;
57f252f2 6685 kvm_vcpu_reset(vcpu);
8a3c1a33 6686 kvm_mmu_setup(vcpu);
e9b11c17 6687 vcpu_put(vcpu);
e9b11c17 6688
26e5215f 6689 return r;
e9b11c17
ZX		 6690}
6691
42897d86
MT		 6692int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6693{
6694 int r;
8fe8ab46 6695 struct msr_data msr;
42897d86
MT		 6696
6697 r = vcpu_load(vcpu);
6698 if (r)
6699 return r;
8fe8ab46
WA		 6700 msr.data = 0x0;
6701 msr.index = MSR_IA32_TSC;
6702 msr.host_initiated = true;
6703 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6704 vcpu_put(vcpu);
6705
6706 return r;
6707}
6708
d40ccc62 6709void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6710{
9fc77441 6711 int r;
344d9588
GN		 6712 vcpu->arch.apf.msr_val = 0;
6713
9fc77441
MT		 6714 r = vcpu_load(vcpu);
6715 BUG_ON(r);
e9b11c17
ZX		 6716 kvm_mmu_unload(vcpu);
6717 vcpu_put(vcpu);
6718
98918833 6719 fx_free(vcpu);
e9b11c17
ZX		 6720 kvm_x86_ops->vcpu_free(vcpu);
6721}
6722
66450a21 6723void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6724{
7460fb4a
AK		 6725 atomic_set(&vcpu->arch.nmi_queued, 0);
6726 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6727 vcpu->arch.nmi_injected = false;
6728
42dbaa5a
JK		 6729 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6730 vcpu->arch.dr6 = DR6_FIXED_1;
73aaf249 6731 kvm_update_dr6(vcpu);
42dbaa5a 6732 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6733 kvm_update_dr7(vcpu);
42dbaa5a 6734
3842d135 6735 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6736 vcpu->arch.apf.msr_val = 0;
c9aaa895 6737 vcpu->arch.st.msr_val = 0;
3842d135 6738
12f9a48f
GC		 6739 kvmclock_reset(vcpu);
6740
af585b92
GN		 6741 kvm_clear_async_pf_completion_queue(vcpu);
6742 kvm_async_pf_hash_reset(vcpu);
6743 vcpu->arch.apf.halted = false;
3842d135 6744
f5132b01
GN		 6745 kvm_pmu_reset(vcpu);
6746
66f7b72e
JS		 6747 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6748 vcpu->arch.regs_avail = ~0;
6749 vcpu->arch.regs_dirty = ~0;
6750
57f252f2 6751 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6752}
6753
66450a21
JK		 6754void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6755{
6756 struct kvm_segment cs;
6757
6758 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6759 cs.selector = vector << 8;
6760 cs.base = vector << 12;
6761 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6762 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6763}
6764
10474ae8 6765int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6766{
ca84d1a2
ZA		 6767 struct kvm *kvm;
6768 struct kvm_vcpu *vcpu;
6769 int i;
0dd6a6ed
ZA		 6770 int ret;
6771 u64 local_tsc;
6772 u64 max_tsc = 0;
6773 bool stable, backwards_tsc = false;
18863bdd
AK		 6774
6775 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6776 ret = kvm_x86_ops->hardware_enable(garbage);
6777 if (ret != 0)
6778 return ret;
6779
6780 local_tsc = native_read_tsc();
6781 stable = !check_tsc_unstable();
6782 list_for_each_entry(kvm, &vm_list, vm_list) {
6783 kvm_for_each_vcpu(i, vcpu, kvm) {
6784 if (!stable && vcpu->cpu == smp_processor_id())
6785 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6786 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6787 backwards_tsc = true;
6788 if (vcpu->arch.last_host_tsc > max_tsc)
6789 max_tsc = vcpu->arch.last_host_tsc;
6790 }
6791 }
6792 }
6793
6794 /*
6795 * Sometimes, even reliable TSCs go backwards. This happens on
6796 * platforms that reset TSC during suspend or hibernate actions, but
6797 * maintain synchronization. We must compensate. Fortunately, we can
6798 * detect that condition here, which happens early in CPU bringup,
6799 * before any KVM threads can be running. Unfortunately, we can't
6800 * bring the TSCs fully up to date with real time, as we aren't yet far
6801 * enough into CPU bringup that we know how much real time has actually
6802 * elapsed; our helper function, get_kernel_ns() will be using boot
6803 * variables that haven't been updated yet.
6804 *
6805 * So we simply find the maximum observed TSC above, then record the
6806 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6807 * the adjustment will be applied. Note that we accumulate
6808 * adjustments, in case multiple suspend cycles happen before some VCPU
6809 * gets a chance to run again. In the event that no KVM threads get a
6810 * chance to run, we will miss the entire elapsed period, as we'll have
6811 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6812 * loose cycle time. This isn't too big a deal, since the loss will be
6813 * uniform across all VCPUs (not to mention the scenario is extremely
6814 * unlikely). It is possible that a second hibernate recovery happens
6815 * much faster than a first, causing the observed TSC here to be
6816 * smaller; this would require additional padding adjustment, which is
6817 * why we set last_host_tsc to the local tsc observed here.
6818 *
6819 * N.B. - this code below runs only on platforms with reliable TSC,
6820 * as that is the only way backwards_tsc is set above. Also note
6821 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6822 * have the same delta_cyc adjustment applied if backwards_tsc
6823 * is detected. Note further, this adjustment is only done once,
6824 * as we reset last_host_tsc on all VCPUs to stop this from being
6825 * called multiple times (one for each physical CPU bringup).
6826 *
4a969980 6827 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6828 * will be compensated by the logic in vcpu_load, which sets the TSC to
6829 * catchup mode. This will catchup all VCPUs to real time, but cannot
6830 * guarantee that they stay in perfect synchronization.
6831 */
6832 if (backwards_tsc) {
6833 u64 delta_cyc = max_tsc - local_tsc;
6834 list_for_each_entry(kvm, &vm_list, vm_list) {
6835 kvm_for_each_vcpu(i, vcpu, kvm) {
6836 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6837 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6838 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6839 &vcpu->requests);
0dd6a6ed
ZA		 6840 }
6841
6842 /*
6843 * We have to disable TSC offset matching.. if you were
6844 * booting a VM while issuing an S4 host suspend....
6845 * you may have some problem. Solving this issue is
6846 * left as an exercise to the reader.
6847 */
6848 kvm->arch.last_tsc_nsec = 0;
6849 kvm->arch.last_tsc_write = 0;
6850 }
6851
6852 }
6853 return 0;
e9b11c17
ZX		 6854}
6855
6856void kvm_arch_hardware_disable(void *garbage)
6857{
6858 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6859 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6860}
6861
6862int kvm_arch_hardware_setup(void)
6863{
6864 return kvm_x86_ops->hardware_setup();
6865}
6866
6867void kvm_arch_hardware_unsetup(void)
6868{
6869 kvm_x86_ops->hardware_unsetup();
6870}
6871
6872void kvm_arch_check_processor_compat(void *rtn)
6873{
6874 kvm_x86_ops->check_processor_compatibility(rtn);
6875}
6876
3e515705
AK		 6877bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6878{
6879 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6880}
6881
54e9818f
GN		 6882struct static_key kvm_no_apic_vcpu __read_mostly;
6883
e9b11c17
ZX		 6884int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6885{
6886 struct page *page;
6887 struct kvm *kvm;
6888 int r;
6889
6890 BUG_ON(vcpu->kvm == NULL);
6891 kvm = vcpu->kvm;
6892
6aef266c 6893 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 6894 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6895 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6896 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6897 else
a4535290 6898 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6899
6900 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6901 if (!page) {
6902 r = -ENOMEM;
6903 goto fail;
6904 }
ad312c7c 6905 vcpu->arch.pio_data = page_address(page);
e9b11c17 6906
cc578287 6907 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6908
e9b11c17
ZX		 6909 r = kvm_mmu_create(vcpu);
6910 if (r < 0)
6911 goto fail_free_pio_data;
6912
6913 if (irqchip_in_kernel(kvm)) {
6914 r = kvm_create_lapic(vcpu);
6915 if (r < 0)
6916 goto fail_mmu_destroy;
54e9818f
GN		 6917 } else
6918 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6919
890ca9ae
HY		 6920 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6921 GFP_KERNEL);
6922 if (!vcpu->arch.mce_banks) {
6923 r = -ENOMEM;
443c39bc 6924 goto fail_free_lapic;
890ca9ae
HY		 6925 }
6926 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6927
f1797359
WY		 6928 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6929 r = -ENOMEM;
f5f48ee1 6930 goto fail_free_mce_banks;
f1797359 6931 }
f5f48ee1 6932
66f7b72e
JS		 6933 r = fx_init(vcpu);
6934 if (r)
6935 goto fail_free_wbinvd_dirty_mask;
6936
ba904635 6937 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6938 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 6939
6940 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 6941 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 6942
af585b92 6943 kvm_async_pf_hash_reset(vcpu);
f5132b01 6944 kvm_pmu_init(vcpu);
af585b92 6945
e9b11c17 6946 return 0;
66f7b72e
JS		 6947fail_free_wbinvd_dirty_mask:
6948 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6949fail_free_mce_banks:
6950 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6951fail_free_lapic:
6952 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6953fail_mmu_destroy:
6954 kvm_mmu_destroy(vcpu);
6955fail_free_pio_data:
ad312c7c 6956 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6957fail:
6958 return r;
6959}
6960
6961void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6962{
f656ce01
MT		 6963 int idx;
6964
f5132b01 6965 kvm_pmu_destroy(vcpu);
36cb93fd 6966 kfree(vcpu->arch.mce_banks);
e9b11c17 6967 kvm_free_lapic(vcpu);
f656ce01 6968 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6969 kvm_mmu_destroy(vcpu);
f656ce01 6970 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6971 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6972 if (!irqchip_in_kernel(vcpu->kvm))
6973 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6974}
d19a9cd2 6975
e08b9637 6976int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6977{
e08b9637
CO		 6978 if (type)
6979 return -EINVAL;
6980
f05e70ac 6981 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 6982 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 6983 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 6984 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 6985
5550af4d
SY		 6986 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6987 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6988 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6989 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6990 &kvm->arch.irq_sources_bitmap);
5550af4d 6991
038f8c11 6992 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6993 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 6994 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6995
6996 pvclock_update_vm_gtod_copy(kvm);
53f658b3 6997
d89f5eff 6998 return 0;
d19a9cd2
ZX		 6999}
7000
7001static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7002{
9fc77441
MT		 7003 int r;
7004 r = vcpu_load(vcpu);
7005 BUG_ON(r);
d19a9cd2
ZX		 7006 kvm_mmu_unload(vcpu);
7007 vcpu_put(vcpu);
7008}
7009
7010static void kvm_free_vcpus(struct kvm *kvm)
7011{
7012 unsigned int i;
988a2cae 7013 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7014
7015 /*
7016 * Unpin any mmu pages first.
7017 */
af585b92
GN		 7018 kvm_for_each_vcpu(i, vcpu, kvm) {
7019 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7020 kvm_unload_vcpu_mmu(vcpu);
af585b92 7021 }
988a2cae
GN		 7022 kvm_for_each_vcpu(i, vcpu, kvm)
7023 kvm_arch_vcpu_free(vcpu);
7024
7025 mutex_lock(&kvm->lock);
7026 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7027 kvm->vcpus[i] = NULL;
d19a9cd2 7028
988a2cae
GN		 7029 atomic_set(&kvm->online_vcpus, 0);
7030 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7031}
7032
ad8ba2cd
SY		 7033void kvm_arch_sync_events(struct kvm *kvm)
7034{
ba4cef31 7035 kvm_free_all_assigned_devices(kvm);
aea924f6 7036 kvm_free_pit(kvm);
ad8ba2cd
SY		 7037}
7038
d19a9cd2
ZX		 7039void kvm_arch_destroy_vm(struct kvm *kvm)
7040{
27469d29
AH		 7041 if (current->mm == kvm->mm) {
7042 /*
7043 * Free memory regions allocated on behalf of userspace,
7044 * unless the the memory map has changed due to process exit
7045 * or fd copying.
7046 */
7047 struct kvm_userspace_memory_region mem;
7048 memset(&mem, 0, sizeof(mem));
7049 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7050 kvm_set_memory_region(kvm, &mem);
7051
7052 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7053 kvm_set_memory_region(kvm, &mem);
7054
7055 mem.slot = TSS_PRIVATE_MEMSLOT;
7056 kvm_set_memory_region(kvm, &mem);
7057 }
6eb55818 7058 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7059 kfree(kvm->arch.vpic);
7060 kfree(kvm->arch.vioapic);
d19a9cd2 7061 kvm_free_vcpus(kvm);
3d45830c
AK		 7062 if (kvm->arch.apic_access_page)
7063 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7064 if (kvm->arch.ept_identity_pagetable)
7065 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7066 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7067}
0de10343 7068
5587027c 7069void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7070 struct kvm_memory_slot *dont)
7071{
7072 int i;
7073
d89cc617
TY		 7074 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7075 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7076 kvm_kvfree(free->arch.rmap[i]);
7077 free->arch.rmap[i] = NULL;
77d11309 7078 }
d89cc617
TY		 7079 if (i == 0)
7080 continue;
7081
7082 if (!dont || free->arch.lpage_info[i - 1] !=
7083 dont->arch.lpage_info[i - 1]) {
7084 kvm_kvfree(free->arch.lpage_info[i - 1]);
7085 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7086 }
7087 }
7088}
7089
5587027c
AK		 7090int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7091 unsigned long npages)
db3fe4eb
TY		 7092{
7093 int i;
7094
d89cc617 7095 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7096 unsigned long ugfn;
7097 int lpages;
d89cc617 7098 int level = i + 1;
db3fe4eb
TY		 7099
7100 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7101 slot->base_gfn, level) + 1;
7102
d89cc617
TY		 7103 slot->arch.rmap[i] =
7104 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7105 if (!slot->arch.rmap[i])
77d11309 7106 goto out_free;
d89cc617
TY		 7107 if (i == 0)
7108 continue;
77d11309 7109
d89cc617
TY		 7110 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7111 sizeof(*slot->arch.lpage_info[i - 1]));
7112 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7113 goto out_free;
7114
7115 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7116 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7117 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7118 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7119 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7120 /*
7121 * If the gfn and userspace address are not aligned wrt each
7122 * other, or if explicitly asked to, disable large page
7123 * support for this slot
7124 */
7125 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7126 !kvm_largepages_enabled()) {
7127 unsigned long j;
7128
7129 for (j = 0; j < lpages; ++j)
d89cc617 7130 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7131 }
7132 }
7133
7134 return 0;
7135
7136out_free:
d89cc617
TY		 7137 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7138 kvm_kvfree(slot->arch.rmap[i]);
7139 slot->arch.rmap[i] = NULL;
7140 if (i == 0)
7141 continue;
7142
7143 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7144 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7145 }
7146 return -ENOMEM;
7147}
7148
e59dbe09
TY		 7149void kvm_arch_memslots_updated(struct kvm *kvm)
7150{
e6dff7d1
TY		 7151 /*
7152 * memslots->generation has been incremented.
7153 * mmio generation may have reached its maximum value.
7154 */
7155 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7156}
7157
f7784b8e
MT		 7158int kvm_arch_prepare_memory_region(struct kvm *kvm,
7159 struct kvm_memory_slot *memslot,
f7784b8e 7160 struct kvm_userspace_memory_region *mem,
7b6195a9 7161 enum kvm_mr_change change)
0de10343 7162{
7a905b14
TY		 7163 /*
7164 * Only private memory slots need to be mapped here since
7165 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7166 */
7b6195a9 7167 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7168 unsigned long userspace_addr;
604b38ac 7169
7a905b14
TY		 7170 /*
7171 * MAP_SHARED to prevent internal slot pages from being moved
7172 * by fork()/COW.
7173 */
7b6195a9 7174 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7175 PROT_READ | PROT_WRITE,
7176 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7177
7a905b14
TY		 7178 if (IS_ERR((void *)userspace_addr))
7179 return PTR_ERR((void *)userspace_addr);
604b38ac 7180
7a905b14 7181 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7182 }
7183
f7784b8e
MT		 7184 return 0;
7185}
7186
7187void kvm_arch_commit_memory_region(struct kvm *kvm,
7188 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7189 const struct kvm_memory_slot *old,
7190 enum kvm_mr_change change)
f7784b8e
MT		 7191{
7192
8482644a 7193 int nr_mmu_pages = 0;
f7784b8e 7194
8482644a 7195 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7196 int ret;
7197
8482644a
TY		 7198 ret = vm_munmap(old->userspace_addr,
7199 old->npages * PAGE_SIZE);
f7784b8e
MT		 7200 if (ret < 0)
7201 printk(KERN_WARNING
7202 "kvm_vm_ioctl_set_memory_region: "
7203 "failed to munmap memory\n");
7204 }
7205
48c0e4e9
XG		 7206 if (!kvm->arch.n_requested_mmu_pages)
7207 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7208
48c0e4e9 7209 if (nr_mmu_pages)
0de10343 7210 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7211 /*
7212 * Write protect all pages for dirty logging.
7213 * Existing largepage mappings are destroyed here and new ones will
7214 * not be created until the end of the logging.
7215 */
8482644a 7216 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7217 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7218}
1d737c8a 7219
2df72e9b 7220void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7221{
6ca18b69 7222 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7223}
7224
2df72e9b
MT		 7225void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7226 struct kvm_memory_slot *slot)
7227{
6ca18b69 7228 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7229}
7230
1d737c8a
ZX		 7231int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7232{
af585b92
GN		 7233 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7234 !vcpu->arch.apf.halted)
7235 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7236 || kvm_apic_has_events(vcpu)
6aef266c 7237 || vcpu->arch.pv.pv_unhalted
7460fb4a 7238 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7239 (kvm_arch_interrupt_allowed(vcpu) &&
7240 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7241}
5736199a 7242
b6d33834 7243int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7244{
b6d33834 7245 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7246}
78646121
GN		 7247
7248int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7249{
7250 return kvm_x86_ops->interrupt_allowed(vcpu);
7251}
229456fc 7252
f92653ee
JK		 7253bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7254{
7255 unsigned long current_rip = kvm_rip_read(vcpu) +
7256 get_segment_base(vcpu, VCPU_SREG_CS);
7257
7258 return current_rip == linear_rip;
7259}
7260EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7261
94fe45da
JK		 7262unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7263{
7264 unsigned long rflags;
7265
7266 rflags = kvm_x86_ops->get_rflags(vcpu);
7267 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7268 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7269 return rflags;
7270}
7271EXPORT_SYMBOL_GPL(kvm_get_rflags);
7272
7273void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7274{
7275 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7276 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7277 rflags |= X86_EFLAGS_TF;
94fe45da 7278 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7279 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7280}
7281EXPORT_SYMBOL_GPL(kvm_set_rflags);
7282
56028d08
GN		 7283void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7284{
7285 int r;
7286
fb67e14f 7287 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7288 work->wakeup_all)
56028d08
GN		 7289 return;
7290
7291 r = kvm_mmu_reload(vcpu);
7292 if (unlikely(r))
7293 return;
7294
fb67e14f
XG		 7295 if (!vcpu->arch.mmu.direct_map &&
7296 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7297 return;
7298
56028d08
GN		 7299 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7300}
7301
af585b92
GN		 7302static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7303{
7304 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7305}
7306
7307static inline u32 kvm_async_pf_next_probe(u32 key)
7308{
7309 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7310}
7311
7312static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7313{
7314 u32 key = kvm_async_pf_hash_fn(gfn);
7315
7316 while (vcpu->arch.apf.gfns[key] != ~0)
7317 key = kvm_async_pf_next_probe(key);
7318
7319 vcpu->arch.apf.gfns[key] = gfn;
7320}
7321
7322static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7323{
7324 int i;
7325 u32 key = kvm_async_pf_hash_fn(gfn);
7326
7327 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7328 (vcpu->arch.apf.gfns[key] != gfn &&
7329 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7330 key = kvm_async_pf_next_probe(key);
7331
7332 return key;
7333}
7334
7335bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7336{
7337 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7338}
7339
7340static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7341{
7342 u32 i, j, k;
7343
7344 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7345 while (true) {
7346 vcpu->arch.apf.gfns[i] = ~0;
7347 do {
7348 j = kvm_async_pf_next_probe(j);
7349 if (vcpu->arch.apf.gfns[j] == ~0)
7350 return;
7351 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7352 /*
7353 * k lies cyclically in ]i,j]
7354 * | i.k.j |
7355 * |....j i.k.| or |.k..j i...|
7356 */
7357 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7358 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7359 i = j;
7360 }
7361}
7362
7c90705b
GN		 7363static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7364{
7365
7366 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7367 sizeof(val));
7368}
7369
af585b92
GN		 7370void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7371 struct kvm_async_pf *work)
7372{
6389ee94
AK		 7373 struct x86_exception fault;
7374
7c90705b 7375 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7376 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7377
7378 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7379 (vcpu->arch.apf.send_user_only &&
7380 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7381 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7382 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7383 fault.vector = PF_VECTOR;
7384 fault.error_code_valid = true;
7385 fault.error_code = 0;
7386 fault.nested_page_fault = false;
7387 fault.address = work->arch.token;
7388 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7389 }
af585b92
GN		 7390}
7391
7392void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7393 struct kvm_async_pf *work)
7394{
6389ee94
AK		 7395 struct x86_exception fault;
7396
7c90705b 7397 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7398 if (work->wakeup_all)
7c90705b
GN		 7399 work->arch.token = ~0; /* broadcast wakeup */
7400 else
7401 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7402
7403 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7404 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7405 fault.vector = PF_VECTOR;
7406 fault.error_code_valid = true;
7407 fault.error_code = 0;
7408 fault.nested_page_fault = false;
7409 fault.address = work->arch.token;
7410 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7411 }
e6d53e3b 7412 vcpu->arch.apf.halted = false;
a4fa1635 7413 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7414}
7415
7416bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7417{
7418 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7419 return true;
7420 else
7421 return !kvm_event_needs_reinjection(vcpu) &&
7422 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7423}
7424
e0f0bbc5
AW		 7425void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7426{
7427 atomic_inc(&kvm->arch.noncoherent_dma_count);
7428}
7429EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7430
7431void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7432{
7433 atomic_dec(&kvm->arch.noncoherent_dma_count);
7434}
7435EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7436
7437bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7438{
7439 return atomic_read(&kvm->arch.noncoherent_dma_count);
7440}
7441EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7442
229456fc
MT		 7443EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7444EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7445EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7446EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7447EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7448EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7449EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7450EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7451EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7452EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7453EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7454EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7455EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
Linux 6.x block layer and io_uring tree(s)