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kvm: Add memcg accounting to KVM allocations
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
bf8c55d8 72#include <asm/intel_pt.h>
043405e1 73
d1898b73
DH		 74#define CREATE_TRACE_POINTS
75#include "trace.h"
76
313a3dc7 77#define MAX_IO_MSRS 256
890ca9ae 78#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 79u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
80EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 81
0f65dd70
AK		 82#define emul_to_vcpu(ctxt) \
83 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
84
50a37eb4
JR		 85/* EFER defaults:
86 * - enable syscall per default because its emulated by KVM
87 * - enable LME and LMA per default on 64 bit KVM
88 */
89#ifdef CONFIG_X86_64
1260edbe
LJ		 90static
91u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 92#else
1260edbe 93static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 94#endif
313a3dc7 95
ba1389b7
AK		 96#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
97#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 98
c519265f
RK		 99#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
100 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 101
cb142eb7 102static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 103static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 104static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 105static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 106static void store_regs(struct kvm_vcpu *vcpu);
107static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 108
893590c7 109struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 110EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 111
893590c7 112static bool __read_mostly ignore_msrs = 0;
476bc001 113module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 114
fab0aa3b
EM		 115static bool __read_mostly report_ignored_msrs = true;
116module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
117
4c27625b 118unsigned int min_timer_period_us = 200;
9ed96e87
MT		 119module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
120
630994b3
MT		 121static bool __read_mostly kvmclock_periodic_sync = true;
122module_param(kvmclock_periodic_sync, bool, S_IRUGO);
123
893590c7 124bool __read_mostly kvm_has_tsc_control;
92a1f12d 125EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 126u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 127EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 128u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
129EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
130u64 __read_mostly kvm_max_tsc_scaling_ratio;
131EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 132u64 __read_mostly kvm_default_tsc_scaling_ratio;
133EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 134
cc578287 135/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 136static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 137module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
138
d0659d94 139/* lapic timer advance (tscdeadline mode only) in nanoseconds */
3b8a5df6 140unsigned int __read_mostly lapic_timer_advance_ns = 1000;
d0659d94 141module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 142EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 143
52004014
FW		 144static bool __read_mostly vector_hashing = true;
145module_param(vector_hashing, bool, S_IRUGO);
146
c4ae60e4
LA		 147bool __read_mostly enable_vmware_backdoor = false;
148module_param(enable_vmware_backdoor, bool, S_IRUGO);
149EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
150
6c86eedc
WL		 151static bool __read_mostly force_emulation_prefix = false;
152module_param(force_emulation_prefix, bool, S_IRUGO);
153
18863bdd
AK		 154#define KVM_NR_SHARED_MSRS 16
155
156struct kvm_shared_msrs_global {
157 int nr;
2bf78fa7 158 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 159};
160
161struct kvm_shared_msrs {
162 struct user_return_notifier urn;
163 bool registered;
2bf78fa7
SY		 164 struct kvm_shared_msr_values {
165 u64 host;
166 u64 curr;
167 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 168};
169
170static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 171static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 172
417bc304 173struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 174 { "pf_fixed", VCPU_STAT(pf_fixed) },
175 { "pf_guest", VCPU_STAT(pf_guest) },
176 { "tlb_flush", VCPU_STAT(tlb_flush) },
177 { "invlpg", VCPU_STAT(invlpg) },
178 { "exits", VCPU_STAT(exits) },
179 { "io_exits", VCPU_STAT(io_exits) },
180 { "mmio_exits", VCPU_STAT(mmio_exits) },
181 { "signal_exits", VCPU_STAT(signal_exits) },
182 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 183 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 184 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 185 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 186 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 187 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 188 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 189 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 190 { "request_irq", VCPU_STAT(request_irq_exits) },
191 { "irq_exits", VCPU_STAT(irq_exits) },
192 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 193 { "fpu_reload", VCPU_STAT(fpu_reload) },
194 { "insn_emulation", VCPU_STAT(insn_emulation) },
195 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 196 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 197 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 198 { "req_event", VCPU_STAT(req_event) },
c595ceee 199 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 200 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
201 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
202 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
203 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
204 { "mmu_flooded", VM_STAT(mmu_flooded) },
205 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 206 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 207 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 208 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 209 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 210 { "max_mmu_page_hash_collisions",
211 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 212 { NULL }
213};
214
2acf923e
DC		 215u64 __read_mostly host_xcr0;
216
b666a4b6
MO		 217struct kmem_cache *x86_fpu_cache;
218EXPORT_SYMBOL_GPL(x86_fpu_cache);
219
b6785def 220static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 221
af585b92
GN		 222static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
223{
224 int i;
225 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
226 vcpu->arch.apf.gfns[i] = ~0;
227}
228
18863bdd
AK		 229static void kvm_on_user_return(struct user_return_notifier *urn)
230{
231 unsigned slot;
18863bdd
AK		 232 struct kvm_shared_msrs *locals
233 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 234 struct kvm_shared_msr_values *values;
1650b4eb
IA		 235 unsigned long flags;
236
237 /*
238 * Disabling irqs at this point since the following code could be
239 * interrupted and executed through kvm_arch_hardware_disable()
240 */
241 local_irq_save(flags);
242 if (locals->registered) {
243 locals->registered = false;
244 user_return_notifier_unregister(urn);
245 }
246 local_irq_restore(flags);
18863bdd 247 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 248 values = &locals->values[slot];
249 if (values->host != values->curr) {
250 wrmsrl(shared_msrs_global.msrs[slot], values->host);
251 values->curr = values->host;
18863bdd
AK		 252 }
253 }
18863bdd
AK		 254}
255
2bf78fa7 256static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 257{
18863bdd 258 u64 value;
013f6a5d
MT		 259 unsigned int cpu = smp_processor_id();
260 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 261
2bf78fa7
SY		 262 /* only read, and nobody should modify it at this time,
263 * so don't need lock */
264 if (slot >= shared_msrs_global.nr) {
265 printk(KERN_ERR "kvm: invalid MSR slot!");
266 return;
267 }
268 rdmsrl_safe(msr, &value);
269 smsr->values[slot].host = value;
270 smsr->values[slot].curr = value;
271}
272
273void kvm_define_shared_msr(unsigned slot, u32 msr)
274{
0123be42 275 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 276 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 277 if (slot >= shared_msrs_global.nr)
278 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 279}
280EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
281
282static void kvm_shared_msr_cpu_online(void)
283{
284 unsigned i;
18863bdd
AK		 285
286 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 287 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 288}
289
8b3c3104 290int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 291{
013f6a5d
MT		 292 unsigned int cpu = smp_processor_id();
293 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 294 int err;
18863bdd 295
2bf78fa7 296 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 297 return 0;
2bf78fa7 298 smsr->values[slot].curr = value;
8b3c3104
AH		 299 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
300 if (err)
301 return 1;
302
18863bdd
AK		 303 if (!smsr->registered) {
304 smsr->urn.on_user_return = kvm_on_user_return;
305 user_return_notifier_register(&smsr->urn);
306 smsr->registered = true;
307 }
8b3c3104 308 return 0;
18863bdd
AK		 309}
310EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
311
13a34e06 312static void drop_user_return_notifiers(void)
3548bab5 313{
013f6a5d
MT		 314 unsigned int cpu = smp_processor_id();
315 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 316
317 if (smsr->registered)
318 kvm_on_user_return(&smsr->urn);
319}
320
6866b83e
CO		 321u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
322{
8a5a87d9 323 return vcpu->arch.apic_base;
6866b83e
CO		 324}
325EXPORT_SYMBOL_GPL(kvm_get_apic_base);
326
58871649
JM		 327enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
328{
329 return kvm_apic_mode(kvm_get_apic_base(vcpu));
330}
331EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
332
58cb628d
JK		 333int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
334{
58871649
JM		 335 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
336 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 337 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
338 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 339
58871649 340 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 341 return 1;
58871649
JM		 342 if (!msr_info->host_initiated) {
343 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
344 return 1;
345 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
346 return 1;
347 }
58cb628d
JK		 348
349 kvm_lapic_set_base(vcpu, msr_info->data);
350 return 0;
6866b83e
CO		 351}
352EXPORT_SYMBOL_GPL(kvm_set_apic_base);
353
2605fc21 354asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 355{
356 /* Fault while not rebooting. We want the trace. */
357 BUG();
358}
359EXPORT_SYMBOL_GPL(kvm_spurious_fault);
360
3fd28fce
ED		 361#define EXCPT_BENIGN 0
362#define EXCPT_CONTRIBUTORY 1
363#define EXCPT_PF 2
364
365static int exception_class(int vector)
366{
367 switch (vector) {
368 case PF_VECTOR:
369 return EXCPT_PF;
370 case DE_VECTOR:
371 case TS_VECTOR:
372 case NP_VECTOR:
373 case SS_VECTOR:
374 case GP_VECTOR:
375 return EXCPT_CONTRIBUTORY;
376 default:
377 break;
378 }
379 return EXCPT_BENIGN;
380}
381
d6e8c854
NA		 382#define EXCPT_FAULT 0
383#define EXCPT_TRAP 1
384#define EXCPT_ABORT 2
385#define EXCPT_INTERRUPT 3
386
387static int exception_type(int vector)
388{
389 unsigned int mask;
390
391 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
392 return EXCPT_INTERRUPT;
393
394 mask = 1 << vector;
395
396 /* #DB is trap, as instruction watchpoints are handled elsewhere */
397 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
398 return EXCPT_TRAP;
399
400 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
401 return EXCPT_ABORT;
402
403 /* Reserved exceptions will result in fault */
404 return EXCPT_FAULT;
405}
406
da998b46
JM		 407void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
408{
409 unsigned nr = vcpu->arch.exception.nr;
410 bool has_payload = vcpu->arch.exception.has_payload;
411 unsigned long payload = vcpu->arch.exception.payload;
412
413 if (!has_payload)
414 return;
415
416 switch (nr) {
f10c729f
JM		 417 case DB_VECTOR:
418 /*
419 * "Certain debug exceptions may clear bit 0-3. The
420 * remaining contents of the DR6 register are never
421 * cleared by the processor".
422 */
423 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
424 /*
425 * DR6.RTM is set by all #DB exceptions that don't clear it.
426 */
427 vcpu->arch.dr6 |= DR6_RTM;
428 vcpu->arch.dr6 |= payload;
429 /*
430 * Bit 16 should be set in the payload whenever the #DB
431 * exception should clear DR6.RTM. This makes the payload
432 * compatible with the pending debug exceptions under VMX.
433 * Though not currently documented in the SDM, this also
434 * makes the payload compatible with the exit qualification
435 * for #DB exceptions under VMX.
436 */
437 vcpu->arch.dr6 ^= payload & DR6_RTM;
438 break;
da998b46
JM		 439 case PF_VECTOR:
440 vcpu->arch.cr2 = payload;
441 break;
442 }
443
444 vcpu->arch.exception.has_payload = false;
445 vcpu->arch.exception.payload = 0;
446}
447EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
448
3fd28fce 449static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 450 unsigned nr, bool has_error, u32 error_code,
91e86d22 451 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 452{
453 u32 prev_nr;
454 int class1, class2;
455
3842d135
AK		 456 kvm_make_request(KVM_REQ_EVENT, vcpu);
457
664f8e26 458 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 459 queue:
3ffb2468
NA		 460 if (has_error && !is_protmode(vcpu))
461 has_error = false;
664f8e26
WL		 462 if (reinject) {
463 /*
464 * On vmentry, vcpu->arch.exception.pending is only
465 * true if an event injection was blocked by
466 * nested_run_pending. In that case, however,
467 * vcpu_enter_guest requests an immediate exit,
468 * and the guest shouldn't proceed far enough to
469 * need reinjection.
470 */
471 WARN_ON_ONCE(vcpu->arch.exception.pending);
472 vcpu->arch.exception.injected = true;
91e86d22
JM		 473 if (WARN_ON_ONCE(has_payload)) {
474 /*
475 * A reinjected event has already
476 * delivered its payload.
477 */
478 has_payload = false;
479 payload = 0;
480 }
664f8e26
WL		 481 } else {
482 vcpu->arch.exception.pending = true;
483 vcpu->arch.exception.injected = false;
484 }
3fd28fce
ED		 485 vcpu->arch.exception.has_error_code = has_error;
486 vcpu->arch.exception.nr = nr;
487 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 488 vcpu->arch.exception.has_payload = has_payload;
489 vcpu->arch.exception.payload = payload;
da998b46
JM		 490 /*
491 * In guest mode, payload delivery should be deferred,
492 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 493 * CR2 is modified (or intercept #DB before DR6 is
494 * modified under nVMX). However, for ABI
495 * compatibility with KVM_GET_VCPU_EVENTS and
496 * KVM_SET_VCPU_EVENTS, we can't delay payload
497 * delivery unless userspace has enabled this
498 * functionality via the per-VM capability,
499 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 500 */
501 if (!vcpu->kvm->arch.exception_payload_enabled ||
502 !is_guest_mode(vcpu))
503 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 504 return;
505 }
506
507 /* to check exception */
508 prev_nr = vcpu->arch.exception.nr;
509 if (prev_nr == DF_VECTOR) {
510 /* triple fault -> shutdown */
a8eeb04a 511 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 512 return;
513 }
514 class1 = exception_class(prev_nr);
515 class2 = exception_class(nr);
516 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
517 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 518 /*
519 * Generate double fault per SDM Table 5-5. Set
520 * exception.pending = true so that the double fault
521 * can trigger a nested vmexit.
522 */
3fd28fce 523 vcpu->arch.exception.pending = true;
664f8e26 524 vcpu->arch.exception.injected = false;
3fd28fce
ED		 525 vcpu->arch.exception.has_error_code = true;
526 vcpu->arch.exception.nr = DF_VECTOR;
527 vcpu->arch.exception.error_code = 0;
c851436a
JM		 528 vcpu->arch.exception.has_payload = false;
529 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 530 } else
531 /* replace previous exception with a new one in a hope
532 that instruction re-execution will regenerate lost
533 exception */
534 goto queue;
535}
536
298101da
AK		 537void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
538{
91e86d22 539 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 540}
541EXPORT_SYMBOL_GPL(kvm_queue_exception);
542
ce7ddec4
JR		 543void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
544{
91e86d22 545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 546}
547EXPORT_SYMBOL_GPL(kvm_requeue_exception);
548
f10c729f
JM		 549static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
550 unsigned long payload)
551{
552 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
553}
554
da998b46
JM		 555static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
556 u32 error_code, unsigned long payload)
557{
558 kvm_multiple_exception(vcpu, nr, true, error_code,
559 true, payload, false);
560}
561
6affcbed 562int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 563{
db8fcefa
AP		 564 if (err)
565 kvm_inject_gp(vcpu, 0);
566 else
6affcbed
KH		 567 return kvm_skip_emulated_instruction(vcpu);
568
569 return 1;
db8fcefa
AP		 570}
571EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 572
6389ee94 573void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 574{
575 ++vcpu->stat.pf_guest;
adfe20fb
WL		 576 vcpu->arch.exception.nested_apf =
577 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 578 if (vcpu->arch.exception.nested_apf) {
adfe20fb 579 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 580 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
581 } else {
582 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
583 fault->address);
584 }
c3c91fee 585}
27d6c865 586EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 587
ef54bcfe 588static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 589{
6389ee94
AK		 590 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
591 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 592 else
44dd3ffa 593 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 594
595 return fault->nested_page_fault;
d4f8cf66
JR		 596}
597
3419ffc8
SY		 598void kvm_inject_nmi(struct kvm_vcpu *vcpu)
599{
7460fb4a
AK		 600 atomic_inc(&vcpu->arch.nmi_queued);
601 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 602}
603EXPORT_SYMBOL_GPL(kvm_inject_nmi);
604
298101da
AK		 605void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
606{
91e86d22 607 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 608}
609EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
610
ce7ddec4
JR		 611void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
612{
91e86d22 613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 614}
615EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
616
0a79b009
AK		 617/*
618 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
619 * a #GP and return false.
620 */
621bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 622{
0a79b009
AK		 623 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
624 return true;
625 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
626 return false;
298101da 627}
0a79b009 628EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 629
16f8a6f9
NA		 630bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
631{
632 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
633 return true;
634
635 kvm_queue_exception(vcpu, UD_VECTOR);
636 return false;
637}
638EXPORT_SYMBOL_GPL(kvm_require_dr);
639
ec92fe44
JR		 640/*
641 * This function will be used to read from the physical memory of the currently
54bf36aa 642 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 643 * can read from guest physical or from the guest's guest physical memory.
644 */
645int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
646 gfn_t ngfn, void *data, int offset, int len,
647 u32 access)
648{
54987b7a 649 struct x86_exception exception;
ec92fe44
JR		 650 gfn_t real_gfn;
651 gpa_t ngpa;
652
653 ngpa = gfn_to_gpa(ngfn);
54987b7a 654 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 655 if (real_gfn == UNMAPPED_GVA)
656 return -EFAULT;
657
658 real_gfn = gpa_to_gfn(real_gfn);
659
54bf36aa 660 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 661}
662EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
663
69b0049a 664static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 665 void *data, int offset, int len, u32 access)
666{
667 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
668 data, offset, len, access);
669}
670
a03490ed
CO		 671/*
672 * Load the pae pdptrs. Return true is they are all valid.
673 */
ff03a073 674int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 675{
676 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
677 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
678 int i;
679 int ret;
ff03a073 680 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 681
ff03a073
JR		 682 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
683 offset * sizeof(u64), sizeof(pdpte),
684 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 685 if (ret < 0) {
686 ret = 0;
687 goto out;
688 }
689 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 690 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50 691 (pdpte[i] &
44dd3ffa 692 vcpu->arch.mmu->guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 693 ret = 0;
694 goto out;
695 }
696 }
697 ret = 1;
698
ff03a073 699 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 700 __set_bit(VCPU_EXREG_PDPTR,
701 (unsigned long *)&vcpu->arch.regs_avail);
702 __set_bit(VCPU_EXREG_PDPTR,
703 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 704out:
a03490ed
CO		 705
706 return ret;
707}
cc4b6871 708EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 709
9ed38ffa 710bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 711{
ff03a073 712 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 713 bool changed = true;
3d06b8bf
JR		 714 int offset;
715 gfn_t gfn;
d835dfec
AK		 716 int r;
717
d35b34a9 718 if (is_long_mode(vcpu) || !is_pae(vcpu) || !is_paging(vcpu))
d835dfec
AK		 719 return false;
720
6de4f3ad
AK		 721 if (!test_bit(VCPU_EXREG_PDPTR,
722 (unsigned long *)&vcpu->arch.regs_avail))
723 return true;
724
a512177e
PB		 725 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
726 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 727 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
728 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 729 if (r < 0)
730 goto out;
ff03a073 731 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 732out:
d835dfec
AK		 733
734 return changed;
735}
9ed38ffa 736EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 737
49a9b07e 738int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 739{
aad82703 740 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 741 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 742
f9a48e6a
AK		 743 cr0 |= X86_CR0_ET;
744
ab344828 745#ifdef CONFIG_X86_64
0f12244f
GN		 746 if (cr0 & 0xffffffff00000000UL)
747 return 1;
ab344828
GN		 748#endif
749
750 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 751
0f12244f
GN		 752 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
753 return 1;
a03490ed 754
0f12244f
GN		 755 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
756 return 1;
a03490ed
CO		 757
758 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
759#ifdef CONFIG_X86_64
f6801dff 760 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 761 int cs_db, cs_l;
762
0f12244f
GN		 763 if (!is_pae(vcpu))
764 return 1;
a03490ed 765 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 766 if (cs_l)
767 return 1;
a03490ed
CO		 768 } else
769#endif
ff03a073 770 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 771 kvm_read_cr3(vcpu)))
0f12244f 772 return 1;
a03490ed
CO		 773 }
774
ad756a16
MJ		 775 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
776 return 1;
777
a03490ed 778 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 779
d170c419 780 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 781 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 782 kvm_async_pf_hash_reset(vcpu);
783 }
e5f3f027 784
aad82703
SY		 785 if ((cr0 ^ old_cr0) & update_bits)
786 kvm_mmu_reset_context(vcpu);
b18d5431 787
879ae188
LE		 788 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
789 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
790 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 791 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
792
0f12244f
GN		 793 return 0;
794}
2d3ad1f4 795EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 796
2d3ad1f4 797void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 798{
49a9b07e 799 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 800}
2d3ad1f4 801EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 802
42bdf991
MT		 803static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
804{
805 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
806 !vcpu->guest_xcr0_loaded) {
807 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 808 if (vcpu->arch.xcr0 != host_xcr0)
809 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 810 vcpu->guest_xcr0_loaded = 1;
811 }
812}
813
814static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
815{
816 if (vcpu->guest_xcr0_loaded) {
817 if (vcpu->arch.xcr0 != host_xcr0)
818 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
819 vcpu->guest_xcr0_loaded = 0;
820 }
821}
822
69b0049a 823static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 824{
56c103ec
LJ		 825 u64 xcr0 = xcr;
826 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 827 u64 valid_bits;
2acf923e
DC		 828
829 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
830 if (index != XCR_XFEATURE_ENABLED_MASK)
831 return 1;
d91cab78 832 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 833 return 1;
d91cab78 834 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 835 return 1;
46c34cb0
PB		 836
837 /*
838 * Do not allow the guest to set bits that we do not support
839 * saving. However, xcr0 bit 0 is always set, even if the
840 * emulated CPU does not support XSAVE (see fx_init).
841 */
d91cab78 842 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 843 if (xcr0 & ~valid_bits)
2acf923e 844 return 1;
46c34cb0 845
d91cab78
DH		 846 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
847 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 848 return 1;
849
d91cab78
DH		 850 if (xcr0 & XFEATURE_MASK_AVX512) {
851 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 852 return 1;
d91cab78 853 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 854 return 1;
855 }
2acf923e 856 vcpu->arch.xcr0 = xcr0;
56c103ec 857
d91cab78 858 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 859 kvm_update_cpuid(vcpu);
2acf923e
DC		 860 return 0;
861}
862
863int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
864{
764bcbc5
Z		 865 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
866 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 867 kvm_inject_gp(vcpu, 0);
868 return 1;
869 }
870 return 0;
871}
872EXPORT_SYMBOL_GPL(kvm_set_xcr);
873
a83b29c6 874int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 875{
fc78f519 876 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 877 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 878 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 879
0f12244f
GN		 880 if (cr4 & CR4_RESERVED_BITS)
881 return 1;
a03490ed 882
d6321d49 883 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 884 return 1;
885
d6321d49 886 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 887 return 1;
888
d6321d49 889 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 890 return 1;
891
d6321d49 892 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 893 return 1;
894
d6321d49 895 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 896 return 1;
897
fd8cb433 898 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 899 return 1;
900
ae3e61e1
PB		 901 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
902 return 1;
903
a03490ed 904 if (is_long_mode(vcpu)) {
0f12244f
GN		 905 if (!(cr4 & X86_CR4_PAE))
906 return 1;
a2edf57f
AK		 907 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
908 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 909 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
910 kvm_read_cr3(vcpu)))
0f12244f
GN		 911 return 1;
912
ad756a16 913 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 914 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 915 return 1;
916
917 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
918 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
919 return 1;
920 }
921
5e1746d6 922 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 923 return 1;
a03490ed 924
ad756a16
MJ		 925 if (((cr4 ^ old_cr4) & pdptr_bits) ||
926 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 927 kvm_mmu_reset_context(vcpu);
0f12244f 928
b9baba86 929 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 930 kvm_update_cpuid(vcpu);
2acf923e 931
0f12244f
GN		 932 return 0;
933}
2d3ad1f4 934EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 935
2390218b 936int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 937{
ade61e28 938 bool skip_tlb_flush = false;
ac146235 939#ifdef CONFIG_X86_64
c19986fe
JS		 940 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
941
ade61e28 942 if (pcid_enabled) {
208320ba
JS		 943 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
944 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 945 }
ac146235 946#endif
9d88fca7 947
9f8fe504 948 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 949 if (!skip_tlb_flush) {
950 kvm_mmu_sync_roots(vcpu);
ade61e28 951 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 952 }
0f12244f 953 return 0;
d835dfec
AK		 954 }
955
d1cd3ce9 956 if (is_long_mode(vcpu) &&
a780a3ea 957 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 958 return 1;
959 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 960 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 961 return 1;
a03490ed 962
ade61e28 963 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 964 vcpu->arch.cr3 = cr3;
aff48baa 965 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 966
0f12244f
GN		 967 return 0;
968}
2d3ad1f4 969EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 970
eea1cff9 971int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 972{
0f12244f
GN		 973 if (cr8 & CR8_RESERVED_BITS)
974 return 1;
35754c98 975 if (lapic_in_kernel(vcpu))
a03490ed
CO		 976 kvm_lapic_set_tpr(vcpu, cr8);
977 else
ad312c7c 978 vcpu->arch.cr8 = cr8;
0f12244f
GN		 979 return 0;
980}
2d3ad1f4 981EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 982
2d3ad1f4 983unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 984{
35754c98 985 if (lapic_in_kernel(vcpu))
a03490ed
CO		 986 return kvm_lapic_get_cr8(vcpu);
987 else
ad312c7c 988 return vcpu->arch.cr8;
a03490ed 989}
2d3ad1f4 990EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 991
ae561ede
NA		 992static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
993{
994 int i;
995
996 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
997 for (i = 0; i < KVM_NR_DB_REGS; i++)
998 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
999 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1000 }
1001}
1002
73aaf249
JK		 1003static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1004{
1005 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1006 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1007}
1008
c8639010
JK		 1009static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1010{
1011 unsigned long dr7;
1012
1013 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1014 dr7 = vcpu->arch.guest_debug_dr7;
1015 else
1016 dr7 = vcpu->arch.dr7;
1017 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1018 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1019 if (dr7 & DR7_BP_EN_MASK)
1020 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1021}
1022
6f43ed01
NA		 1023static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1024{
1025 u64 fixed = DR6_FIXED_1;
1026
d6321d49 1027 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1028 fixed |= DR6_RTM;
1029 return fixed;
1030}
1031
338dbc97 1032static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1033{
1034 switch (dr) {
1035 case 0 ... 3:
1036 vcpu->arch.db[dr] = val;
1037 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1038 vcpu->arch.eff_db[dr] = val;
1039 break;
1040 case 4:
020df079
GN		 1041 /* fall through */
1042 case 6:
338dbc97
GN		 1043 if (val & 0xffffffff00000000ULL)
1044 return -1; /* #GP */
6f43ed01 1045 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1046 kvm_update_dr6(vcpu);
020df079
GN		 1047 break;
1048 case 5:
020df079
GN		 1049 /* fall through */
1050 default: /* 7 */
338dbc97
GN		 1051 if (val & 0xffffffff00000000ULL)
1052 return -1; /* #GP */
020df079 1053 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1054 kvm_update_dr7(vcpu);
020df079
GN		 1055 break;
1056 }
1057
1058 return 0;
1059}
338dbc97
GN		 1060
1061int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1062{
16f8a6f9 1063 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1064 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1065 return 1;
1066 }
1067 return 0;
338dbc97 1068}
020df079
GN		 1069EXPORT_SYMBOL_GPL(kvm_set_dr);
1070
16f8a6f9 1071int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1072{
1073 switch (dr) {
1074 case 0 ... 3:
1075 *val = vcpu->arch.db[dr];
1076 break;
1077 case 4:
020df079
GN		 1078 /* fall through */
1079 case 6:
73aaf249
JK		 1080 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1081 *val = vcpu->arch.dr6;
1082 else
1083 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1084 break;
1085 case 5:
020df079
GN		 1086 /* fall through */
1087 default: /* 7 */
1088 *val = vcpu->arch.dr7;
1089 break;
1090 }
338dbc97
GN		 1091 return 0;
1092}
020df079
GN		 1093EXPORT_SYMBOL_GPL(kvm_get_dr);
1094
022cd0e8
AK		 1095bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1096{
1097 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1098 u64 data;
1099 int err;
1100
c6702c9d 1101 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1102 if (err)
1103 return err;
1104 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1105 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1106 return err;
1107}
1108EXPORT_SYMBOL_GPL(kvm_rdpmc);
1109
043405e1
CO		 1110/*
1111 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1112 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1113 *
1114 * This list is modified at module load time to reflect the
e3267cbb 1115 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1116 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1117 * may depend on host virtualization features rather than host cpu features.
043405e1 1118 */
e3267cbb 1119
043405e1
CO		 1120static u32 msrs_to_save[] = {
1121 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1122 MSR_STAR,
043405e1
CO		 1123#ifdef CONFIG_X86_64
1124 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1125#endif
b3897a49 1126 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1127 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
bf8c55d8
CP		 1128 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES,
1129 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1130 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1131 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1132 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1133 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1134 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
043405e1
CO		 1135};
1136
1137static unsigned num_msrs_to_save;
1138
62ef68bb
PB		 1139static u32 emulated_msrs[] = {
1140 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1141 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1142 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1143 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1144 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1145 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1146 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1147 HV_X64_MSR_RESET,
11c4b1ca 1148 HV_X64_MSR_VP_INDEX,
9eec50b8 1149 HV_X64_MSR_VP_RUNTIME,
5c919412 1150 HV_X64_MSR_SCONTROL,
1f4b34f8 1151 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1152 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1153 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1154 HV_X64_MSR_TSC_EMULATION_STATUS,
1155
1156 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1157 MSR_KVM_PV_EOI_EN,
1158
ba904635 1159 MSR_IA32_TSC_ADJUST,
a3e06bbe 1160 MSR_IA32_TSCDEADLINE,
043405e1 1161 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1162 MSR_IA32_MCG_STATUS,
1163 MSR_IA32_MCG_CTL,
c45dcc71 1164 MSR_IA32_MCG_EXT_CTL,
64d60670 1165 MSR_IA32_SMBASE,
52797bf9 1166 MSR_SMI_COUNT,
db2336a8
KH		 1167 MSR_PLATFORM_INFO,
1168 MSR_MISC_FEATURES_ENABLES,
bc226f07 1169 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1170};
1171
62ef68bb
PB		 1172static unsigned num_emulated_msrs;
1173
801e459a
TL		 1174/*
1175 * List of msr numbers which are used to expose MSR-based features that
1176 * can be used by a hypervisor to validate requested CPU features.
1177 */
1178static u32 msr_based_features[] = {
1389309c
PB		 1179 MSR_IA32_VMX_BASIC,
1180 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1181 MSR_IA32_VMX_PINBASED_CTLS,
1182 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1183 MSR_IA32_VMX_PROCBASED_CTLS,
1184 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1185 MSR_IA32_VMX_EXIT_CTLS,
1186 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1187 MSR_IA32_VMX_ENTRY_CTLS,
1188 MSR_IA32_VMX_MISC,
1189 MSR_IA32_VMX_CR0_FIXED0,
1190 MSR_IA32_VMX_CR0_FIXED1,
1191 MSR_IA32_VMX_CR4_FIXED0,
1192 MSR_IA32_VMX_CR4_FIXED1,
1193 MSR_IA32_VMX_VMCS_ENUM,
1194 MSR_IA32_VMX_PROCBASED_CTLS2,
1195 MSR_IA32_VMX_EPT_VPID_CAP,
1196 MSR_IA32_VMX_VMFUNC,
1197
d1d93fa9 1198 MSR_F10H_DECFG,
518e7b94 1199 MSR_IA32_UCODE_REV,
cd283252 1200 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1201};
1202
1203static unsigned int num_msr_based_features;
1204
5b76a3cf
PB		 1205u64 kvm_get_arch_capabilities(void)
1206{
1207 u64 data;
1208
1209 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1210
1211 /*
1212 * If we're doing cache flushes (either "always" or "cond")
1213 * we will do one whenever the guest does a vmlaunch/vmresume.
1214 * If an outer hypervisor is doing the cache flush for us
1215 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1216 * capability to the guest too, and if EPT is disabled we're not
1217 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1218 * require a nested hypervisor to do a flush of its own.
1219 */
1220 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1221 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1222
1223 return data;
1224}
1225EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1226
66421c1e
WL		 1227static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1228{
1229 switch (msr->index) {
cd283252 1230 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1231 msr->data = kvm_get_arch_capabilities();
1232 break;
1233 case MSR_IA32_UCODE_REV:
cd283252 1234 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1235 break;
66421c1e
WL		 1236 default:
1237 if (kvm_x86_ops->get_msr_feature(msr))
1238 return 1;
1239 }
1240 return 0;
1241}
1242
801e459a
TL		 1243static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1244{
1245 struct kvm_msr_entry msr;
66421c1e 1246 int r;
801e459a
TL		 1247
1248 msr.index = index;
66421c1e
WL		 1249 r = kvm_get_msr_feature(&msr);
1250 if (r)
1251 return r;
801e459a
TL		 1252
1253 *data = msr.data;
1254
1255 return 0;
1256}
1257
384bb783 1258bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1259{
b69e8cae 1260 if (efer & efer_reserved_bits)
384bb783 1261 return false;
15c4a640 1262
1b4d56b8 1263 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1264 return false;
1b2fd70c 1265
1b4d56b8 1266 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1267 return false;
d8017474 1268
384bb783
JK		 1269 return true;
1270}
1271EXPORT_SYMBOL_GPL(kvm_valid_efer);
1272
1273static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1274{
1275 u64 old_efer = vcpu->arch.efer;
1276
1277 if (!kvm_valid_efer(vcpu, efer))
1278 return 1;
1279
1280 if (is_paging(vcpu)
1281 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1282 return 1;
1283
15c4a640 1284 efer &= ~EFER_LMA;
f6801dff 1285 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1286
a3d204e2
SY		 1287 kvm_x86_ops->set_efer(vcpu, efer);
1288
aad82703
SY		 1289 /* Update reserved bits */
1290 if ((efer ^ old_efer) & EFER_NX)
1291 kvm_mmu_reset_context(vcpu);
1292
b69e8cae 1293 return 0;
15c4a640
CO		 1294}
1295
f2b4b7dd
JR		 1296void kvm_enable_efer_bits(u64 mask)
1297{
1298 efer_reserved_bits &= ~mask;
1299}
1300EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1301
15c4a640
CO		 1302/*
1303 * Writes msr value into into the appropriate "register".
1304 * Returns 0 on success, non-0 otherwise.
1305 * Assumes vcpu_load() was already called.
1306 */
8fe8ab46 1307int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1308{
854e8bb1
NA		 1309 switch (msr->index) {
1310 case MSR_FS_BASE:
1311 case MSR_GS_BASE:
1312 case MSR_KERNEL_GS_BASE:
1313 case MSR_CSTAR:
1314 case MSR_LSTAR:
fd8cb433 1315 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1316 return 1;
1317 break;
1318 case MSR_IA32_SYSENTER_EIP:
1319 case MSR_IA32_SYSENTER_ESP:
1320 /*
1321 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1322 * non-canonical address is written on Intel but not on
1323 * AMD (which ignores the top 32-bits, because it does
1324 * not implement 64-bit SYSENTER).
1325 *
1326 * 64-bit code should hence be able to write a non-canonical
1327 * value on AMD. Making the address canonical ensures that
1328 * vmentry does not fail on Intel after writing a non-canonical
1329 * value, and that something deterministic happens if the guest
1330 * invokes 64-bit SYSENTER.
1331 */
fd8cb433 1332 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1333 }
8fe8ab46 1334 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1335}
854e8bb1 1336EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1337
313a3dc7
CO		 1338/*
1339 * Adapt set_msr() to msr_io()'s calling convention
1340 */
609e36d3
PB		 1341static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1342{
1343 struct msr_data msr;
1344 int r;
1345
1346 msr.index = index;
1347 msr.host_initiated = true;
1348 r = kvm_get_msr(vcpu, &msr);
1349 if (r)
1350 return r;
1351
1352 *data = msr.data;
1353 return 0;
1354}
1355
313a3dc7
CO		 1356static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1357{
8fe8ab46
WA		 1358 struct msr_data msr;
1359
1360 msr.data = *data;
1361 msr.index = index;
1362 msr.host_initiated = true;
1363 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1364}
1365
16e8d74d
MT		 1366#ifdef CONFIG_X86_64
1367struct pvclock_gtod_data {
1368 seqcount_t seq;
1369
1370 struct { /* extract of a clocksource struct */
1371 int vclock_mode;
a5a1d1c2
TG		 1372 u64 cycle_last;
1373 u64 mask;
16e8d74d
MT		 1374 u32 mult;
1375 u32 shift;
1376 } clock;
1377
cbcf2dd3
TG		 1378 u64 boot_ns;
1379 u64 nsec_base;
55dd00a7 1380 u64 wall_time_sec;
16e8d74d
MT		 1381};
1382
1383static struct pvclock_gtod_data pvclock_gtod_data;
1384
1385static void update_pvclock_gtod(struct timekeeper *tk)
1386{
1387 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1388 u64 boot_ns;
1389
876e7881 1390 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1391
1392 write_seqcount_begin(&vdata->seq);
1393
1394 /* copy pvclock gtod data */
876e7881
PZ		 1395 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1396 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1397 vdata->clock.mask = tk->tkr_mono.mask;
1398 vdata->clock.mult = tk->tkr_mono.mult;
1399 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1400
cbcf2dd3 1401 vdata->boot_ns = boot_ns;
876e7881 1402 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1403
55dd00a7
MT		 1404 vdata->wall_time_sec = tk->xtime_sec;
1405
16e8d74d
MT		 1406 write_seqcount_end(&vdata->seq);
1407}
1408#endif
1409
bab5bb39
NK		 1410void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1411{
1412 /*
1413 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1414 * vcpu_enter_guest. This function is only called from
1415 * the physical CPU that is running vcpu.
1416 */
1417 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1418}
16e8d74d 1419
18068523
GOC		 1420static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1421{
9ed3c444
AK		 1422 int version;
1423 int r;
50d0a0f9 1424 struct pvclock_wall_clock wc;
87aeb54f 1425 struct timespec64 boot;
18068523
GOC		 1426
1427 if (!wall_clock)
1428 return;
1429
9ed3c444
AK		 1430 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1431 if (r)
1432 return;
1433
1434 if (version & 1)
1435 ++version; /* first time write, random junk */
1436
1437 ++version;
18068523 1438
1dab1345
NK		 1439 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1440 return;
18068523 1441
50d0a0f9
GH		 1442 /*
1443 * The guest calculates current wall clock time by adding
34c238a1 1444 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1445 * wall clock specified here. guest system time equals host
1446 * system time for us, thus we must fill in host boot time here.
1447 */
87aeb54f 1448 getboottime64(&boot);
50d0a0f9 1449
4b648665 1450 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1451 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1452 boot = timespec64_sub(boot, ts);
4b648665 1453 }
87aeb54f 1454 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1455 wc.nsec = boot.tv_nsec;
1456 wc.version = version;
18068523
GOC		 1457
1458 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1459
1460 version++;
1461 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1462}
1463
50d0a0f9
GH		 1464static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1465{
b51012de
PB		 1466 do_shl32_div32(dividend, divisor);
1467 return dividend;
50d0a0f9
GH		 1468}
1469
3ae13faa 1470static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1471 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1472{
5f4e3f88 1473 uint64_t scaled64;
50d0a0f9
GH		 1474 int32_t shift = 0;
1475 uint64_t tps64;
1476 uint32_t tps32;
1477
3ae13faa
PB		 1478 tps64 = base_hz;
1479 scaled64 = scaled_hz;
50933623 1480 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1481 tps64 >>= 1;
1482 shift--;
1483 }
1484
1485 tps32 = (uint32_t)tps64;
50933623
JK		 1486 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1487 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1488 scaled64 >>= 1;
1489 else
1490 tps32 <<= 1;
50d0a0f9
GH		 1491 shift++;
1492 }
1493
5f4e3f88
ZA		 1494 *pshift = shift;
1495 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1496
3ae13faa
PB		 1497 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1498 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1499}
1500
d828199e 1501#ifdef CONFIG_X86_64
16e8d74d 1502static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1503#endif
16e8d74d 1504
c8076604 1505static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1506static unsigned long max_tsc_khz;
c8076604 1507
cc578287 1508static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1509{
cc578287
ZA		 1510 u64 v = (u64)khz * (1000000 + ppm);
1511 do_div(v, 1000000);
1512 return v;
1e993611
JR		 1513}
1514
381d585c
HZ		 1515static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1516{
1517 u64 ratio;
1518
1519 /* Guest TSC same frequency as host TSC? */
1520 if (!scale) {
1521 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1522 return 0;
1523 }
1524
1525 /* TSC scaling supported? */
1526 if (!kvm_has_tsc_control) {
1527 if (user_tsc_khz > tsc_khz) {
1528 vcpu->arch.tsc_catchup = 1;
1529 vcpu->arch.tsc_always_catchup = 1;
1530 return 0;
1531 } else {
1532 WARN(1, "user requested TSC rate below hardware speed\n");
1533 return -1;
1534 }
1535 }
1536
1537 /* TSC scaling required - calculate ratio */
1538 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1539 user_tsc_khz, tsc_khz);
1540
1541 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1542 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1543 user_tsc_khz);
1544 return -1;
1545 }
1546
1547 vcpu->arch.tsc_scaling_ratio = ratio;
1548 return 0;
1549}
1550
4941b8cb 1551static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1552{
cc578287
ZA		 1553 u32 thresh_lo, thresh_hi;
1554 int use_scaling = 0;
217fc9cf 1555
03ba32ca 1556 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1557 if (user_tsc_khz == 0) {
ad721883
HZ		 1558 /* set tsc_scaling_ratio to a safe value */
1559 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1560 return -1;
ad721883 1561 }
03ba32ca 1562
c285545f 1563 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1564 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1565 &vcpu->arch.virtual_tsc_shift,
1566 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1567 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1568
1569 /*
1570 * Compute the variation in TSC rate which is acceptable
1571 * within the range of tolerance and decide if the
1572 * rate being applied is within that bounds of the hardware
1573 * rate. If so, no scaling or compensation need be done.
1574 */
1575 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1576 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1577 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1578 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1579 use_scaling = 1;
1580 }
4941b8cb 1581 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1582}
1583
1584static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1585{
e26101b1 1586 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1587 vcpu->arch.virtual_tsc_mult,
1588 vcpu->arch.virtual_tsc_shift);
e26101b1 1589 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1590 return tsc;
1591}
1592
b0c39dc6
VK		 1593static inline int gtod_is_based_on_tsc(int mode)
1594{
1595 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1596}
1597
69b0049a 1598static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1599{
1600#ifdef CONFIG_X86_64
1601 bool vcpus_matched;
b48aa97e
MT		 1602 struct kvm_arch *ka = &vcpu->kvm->arch;
1603 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1604
1605 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1606 atomic_read(&vcpu->kvm->online_vcpus));
1607
7f187922
MT		 1608 /*
1609 * Once the masterclock is enabled, always perform request in
1610 * order to update it.
1611 *
1612 * In order to enable masterclock, the host clocksource must be TSC
1613 * and the vcpus need to have matched TSCs. When that happens,
1614 * perform request to enable masterclock.
1615 */
1616 if (ka->use_master_clock ||
b0c39dc6 1617 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1618 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1619
1620 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1621 atomic_read(&vcpu->kvm->online_vcpus),
1622 ka->use_master_clock, gtod->clock.vclock_mode);
1623#endif
1624}
1625
ba904635
WA		 1626static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1627{
e79f245d 1628 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1629 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1630}
1631
35181e86
HZ		 1632/*
1633 * Multiply tsc by a fixed point number represented by ratio.
1634 *
1635 * The most significant 64-N bits (mult) of ratio represent the
1636 * integral part of the fixed point number; the remaining N bits
1637 * (frac) represent the fractional part, ie. ratio represents a fixed
1638 * point number (mult + frac * 2^(-N)).
1639 *
1640 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1641 */
1642static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1643{
1644 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1645}
1646
1647u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1648{
1649 u64 _tsc = tsc;
1650 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1651
1652 if (ratio != kvm_default_tsc_scaling_ratio)
1653 _tsc = __scale_tsc(ratio, tsc);
1654
1655 return _tsc;
1656}
1657EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1658
07c1419a
HZ		 1659static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1660{
1661 u64 tsc;
1662
1663 tsc = kvm_scale_tsc(vcpu, rdtsc());
1664
1665 return target_tsc - tsc;
1666}
1667
4ba76538
HZ		 1668u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1669{
e79f245d
KA		 1670 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1671
1672 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1673}
1674EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1675
a545ab6a
LC		 1676static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1677{
326e7425 1678 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1679}
1680
b0c39dc6
VK		 1681static inline bool kvm_check_tsc_unstable(void)
1682{
1683#ifdef CONFIG_X86_64
1684 /*
1685 * TSC is marked unstable when we're running on Hyper-V,
1686 * 'TSC page' clocksource is good.
1687 */
1688 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1689 return false;
1690#endif
1691 return check_tsc_unstable();
1692}
1693
8fe8ab46 1694void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1695{
1696 struct kvm *kvm = vcpu->kvm;
f38e098f 1697 u64 offset, ns, elapsed;
99e3e30a 1698 unsigned long flags;
b48aa97e 1699 bool matched;
0d3da0d2 1700 bool already_matched;
8fe8ab46 1701 u64 data = msr->data;
c5e8ec8e 1702 bool synchronizing = false;
99e3e30a 1703
038f8c11 1704 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1705 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1706 ns = ktime_get_boot_ns();
f38e098f 1707 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1708
03ba32ca 1709 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1710 if (data == 0 && msr->host_initiated) {
1711 /*
1712 * detection of vcpu initialization -- need to sync
1713 * with other vCPUs. This particularly helps to keep
1714 * kvm_clock stable after CPU hotplug
1715 */
1716 synchronizing = true;
1717 } else {
1718 u64 tsc_exp = kvm->arch.last_tsc_write +
1719 nsec_to_cycles(vcpu, elapsed);
1720 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1721 /*
1722 * Special case: TSC write with a small delta (1 second)
1723 * of virtual cycle time against real time is
1724 * interpreted as an attempt to synchronize the CPU.
1725 */
1726 synchronizing = data < tsc_exp + tsc_hz &&
1727 data + tsc_hz > tsc_exp;
1728 }
c5e8ec8e 1729 }
f38e098f
ZA		 1730
1731 /*
5d3cb0f6
ZA		 1732 * For a reliable TSC, we can match TSC offsets, and for an unstable
1733 * TSC, we add elapsed time in this computation. We could let the
1734 * compensation code attempt to catch up if we fall behind, but
1735 * it's better to try to match offsets from the beginning.
1736 */
c5e8ec8e 1737 if (synchronizing &&
5d3cb0f6 1738 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1739 if (!kvm_check_tsc_unstable()) {
e26101b1 1740 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1741 pr_debug("kvm: matched tsc offset for %llu\n", data);
1742 } else {
857e4099 1743 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1744 data += delta;
07c1419a 1745 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1746 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1747 }
b48aa97e 1748 matched = true;
0d3da0d2 1749 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1750 } else {
1751 /*
1752 * We split periods of matched TSC writes into generations.
1753 * For each generation, we track the original measured
1754 * nanosecond time, offset, and write, so if TSCs are in
1755 * sync, we can match exact offset, and if not, we can match
4a969980 1756 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1757 *
1758 * These values are tracked in kvm->arch.cur_xxx variables.
1759 */
1760 kvm->arch.cur_tsc_generation++;
1761 kvm->arch.cur_tsc_nsec = ns;
1762 kvm->arch.cur_tsc_write = data;
1763 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1764 matched = false;
0d3da0d2 1765 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1766 kvm->arch.cur_tsc_generation, data);
f38e098f 1767 }
e26101b1
ZA		 1768
1769 /*
1770 * We also track th most recent recorded KHZ, write and time to
1771 * allow the matching interval to be extended at each write.
1772 */
f38e098f
ZA		 1773 kvm->arch.last_tsc_nsec = ns;
1774 kvm->arch.last_tsc_write = data;
5d3cb0f6 1775 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1776
b183aa58 1777 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1778
1779 /* Keep track of which generation this VCPU has synchronized to */
1780 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1781 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1782 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1783
d6321d49 1784 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1785 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1786
a545ab6a 1787 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1788 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1789
1790 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1791 if (!matched) {
b48aa97e 1792 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1793 } else if (!already_matched) {
1794 kvm->arch.nr_vcpus_matched_tsc++;
1795 }
b48aa97e
MT		 1796
1797 kvm_track_tsc_matching(vcpu);
1798 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1799}
e26101b1 1800
99e3e30a
ZA		 1801EXPORT_SYMBOL_GPL(kvm_write_tsc);
1802
58ea6767
HZ		 1803static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1804 s64 adjustment)
1805{
326e7425
LS		 1806 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1807 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 1808}
1809
1810static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1811{
1812 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1813 WARN_ON(adjustment < 0);
1814 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1815 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1816}
1817
d828199e
MT		 1818#ifdef CONFIG_X86_64
1819
a5a1d1c2 1820static u64 read_tsc(void)
d828199e 1821{
a5a1d1c2 1822 u64 ret = (u64)rdtsc_ordered();
03b9730b 1823 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1824
1825 if (likely(ret >= last))
1826 return ret;
1827
1828 /*
1829 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1830 * predictable (it's just a function of time and the likely is
d828199e
MT		 1831 * very likely) and there's a data dependence, so force GCC
1832 * to generate a branch instead. I don't barrier() because
1833 * we don't actually need a barrier, and if this function
1834 * ever gets inlined it will generate worse code.
1835 */
1836 asm volatile ("");
1837 return last;
1838}
1839
b0c39dc6 1840static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1841{
1842 long v;
1843 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1844 u64 tsc_pg_val;
1845
1846 switch (gtod->clock.vclock_mode) {
1847 case VCLOCK_HVCLOCK:
1848 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1849 tsc_timestamp);
1850 if (tsc_pg_val != U64_MAX) {
1851 /* TSC page valid */
1852 *mode = VCLOCK_HVCLOCK;
1853 v = (tsc_pg_val - gtod->clock.cycle_last) &
1854 gtod->clock.mask;
1855 } else {
1856 /* TSC page invalid */
1857 *mode = VCLOCK_NONE;
1858 }
1859 break;
1860 case VCLOCK_TSC:
1861 *mode = VCLOCK_TSC;
1862 *tsc_timestamp = read_tsc();
1863 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1864 gtod->clock.mask;
1865 break;
1866 default:
1867 *mode = VCLOCK_NONE;
1868 }
d828199e 1869
b0c39dc6
VK		 1870 if (*mode == VCLOCK_NONE)
1871 *tsc_timestamp = v = 0;
d828199e 1872
d828199e
MT		 1873 return v * gtod->clock.mult;
1874}
1875
b0c39dc6 1876static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1877{
cbcf2dd3 1878 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1879 unsigned long seq;
d828199e 1880 int mode;
cbcf2dd3 1881 u64 ns;
d828199e 1882
d828199e
MT		 1883 do {
1884 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1885 ns = gtod->nsec_base;
b0c39dc6 1886 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1887 ns >>= gtod->clock.shift;
cbcf2dd3 1888 ns += gtod->boot_ns;
d828199e 1889 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1890 *t = ns;
d828199e
MT		 1891
1892 return mode;
1893}
1894
899a31f5 1895static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1896{
1897 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1898 unsigned long seq;
1899 int mode;
1900 u64 ns;
1901
1902 do {
1903 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1904 ts->tv_sec = gtod->wall_time_sec;
1905 ns = gtod->nsec_base;
b0c39dc6 1906 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1907 ns >>= gtod->clock.shift;
1908 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1909
1910 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1911 ts->tv_nsec = ns;
1912
1913 return mode;
1914}
1915
b0c39dc6
VK		 1916/* returns true if host is using TSC based clocksource */
1917static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1918{
d828199e 1919 /* checked again under seqlock below */
b0c39dc6 1920 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1921 return false;
1922
b0c39dc6
VK		 1923 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1924 tsc_timestamp));
d828199e 1925}
55dd00a7 1926
b0c39dc6 1927/* returns true if host is using TSC based clocksource */
899a31f5 1928static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1929 u64 *tsc_timestamp)
55dd00a7
MT		 1930{
1931 /* checked again under seqlock below */
b0c39dc6 1932 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1933 return false;
1934
b0c39dc6 1935 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1936}
d828199e
MT		 1937#endif
1938
1939/*
1940 *
b48aa97e
MT		 1941 * Assuming a stable TSC across physical CPUS, and a stable TSC
1942 * across virtual CPUs, the following condition is possible.
1943 * Each numbered line represents an event visible to both
d828199e
MT		 1944 * CPUs at the next numbered event.
1945 *
1946 * "timespecX" represents host monotonic time. "tscX" represents
1947 * RDTSC value.
1948 *
1949 * VCPU0 on CPU0 | VCPU1 on CPU1
1950 *
1951 * 1. read timespec0,tsc0
1952 * 2. | timespec1 = timespec0 + N
1953 * | tsc1 = tsc0 + M
1954 * 3. transition to guest | transition to guest
1955 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1956 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1957 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1958 *
1959 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1960 *
1961 * - ret0 < ret1
1962 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1963 * ...
1964 * - 0 < N - M => M < N
1965 *
1966 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1967 * always the case (the difference between two distinct xtime instances
1968 * might be smaller then the difference between corresponding TSC reads,
1969 * when updating guest vcpus pvclock areas).
1970 *
1971 * To avoid that problem, do not allow visibility of distinct
1972 * system_timestamp/tsc_timestamp values simultaneously: use a master
1973 * copy of host monotonic time values. Update that master copy
1974 * in lockstep.
1975 *
b48aa97e 1976 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1977 *
1978 */
1979
1980static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1981{
1982#ifdef CONFIG_X86_64
1983 struct kvm_arch *ka = &kvm->arch;
1984 int vclock_mode;
b48aa97e
MT		 1985 bool host_tsc_clocksource, vcpus_matched;
1986
1987 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1988 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1989
1990 /*
1991 * If the host uses TSC clock, then passthrough TSC as stable
1992 * to the guest.
1993 */
b48aa97e 1994 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1995 &ka->master_kernel_ns,
1996 &ka->master_cycle_now);
1997
16a96021 1998 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1999 && !ka->backwards_tsc_observed
54750f2c 2000 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 2001
d828199e
MT		 2002 if (ka->use_master_clock)
2003 atomic_set(&kvm_guest_has_master_clock, 1);
2004
2005 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 2006 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2007 vcpus_matched);
d828199e
MT		 2008#endif
2009}
2010
2860c4b1
PB		 2011void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2012{
2013 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2014}
2015
2e762ff7
MT		 2016static void kvm_gen_update_masterclock(struct kvm *kvm)
2017{
2018#ifdef CONFIG_X86_64
2019 int i;
2020 struct kvm_vcpu *vcpu;
2021 struct kvm_arch *ka = &kvm->arch;
2022
2023 spin_lock(&ka->pvclock_gtod_sync_lock);
2024 kvm_make_mclock_inprogress_request(kvm);
2025 /* no guest entries from this point */
2026 pvclock_update_vm_gtod_copy(kvm);
2027
2028 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2029 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2030
2031 /* guest entries allowed */
2032 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2033 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2034
2035 spin_unlock(&ka->pvclock_gtod_sync_lock);
2036#endif
2037}
2038
e891a32e 2039u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2040{
108b249c 2041 struct kvm_arch *ka = &kvm->arch;
8b953440 2042 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2043 u64 ret;
108b249c 2044
8b953440
PB		 2045 spin_lock(&ka->pvclock_gtod_sync_lock);
2046 if (!ka->use_master_clock) {
2047 spin_unlock(&ka->pvclock_gtod_sync_lock);
2048 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 2049 }
2050
8b953440
PB		 2051 hv_clock.tsc_timestamp = ka->master_cycle_now;
2052 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2053 spin_unlock(&ka->pvclock_gtod_sync_lock);
2054
e2c2206a
WL		 2055 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2056 get_cpu();
2057
e70b57a6
WL		 2058 if (__this_cpu_read(cpu_tsc_khz)) {
2059 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2060 &hv_clock.tsc_shift,
2061 &hv_clock.tsc_to_system_mul);
2062 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2063 } else
2064 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2065
2066 put_cpu();
2067
2068 return ret;
108b249c
PB		 2069}
2070
0d6dd2ff
PB		 2071static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2072{
2073 struct kvm_vcpu_arch *vcpu = &v->arch;
2074 struct pvclock_vcpu_time_info guest_hv_clock;
2075
4e335d9e 2076 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2077 &guest_hv_clock, sizeof(guest_hv_clock))))
2078 return;
2079
2080 /* This VCPU is paused, but it's legal for a guest to read another
2081 * VCPU's kvmclock, so we really have to follow the specification where
2082 * it says that version is odd if data is being modified, and even after
2083 * it is consistent.
2084 *
2085 * Version field updates must be kept separate. This is because
2086 * kvm_write_guest_cached might use a "rep movs" instruction, and
2087 * writes within a string instruction are weakly ordered. So there
2088 * are three writes overall.
2089 *
2090 * As a small optimization, only write the version field in the first
2091 * and third write. The vcpu->pv_time cache is still valid, because the
2092 * version field is the first in the struct.
2093 */
2094 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2095
51c4b8bb
LA		 2096 if (guest_hv_clock.version & 1)
2097 ++guest_hv_clock.version; /* first time write, random junk */
2098
0d6dd2ff 2099 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2100 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2101 &vcpu->hv_clock,
2102 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2103
2104 smp_wmb();
2105
2106 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2107 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2108
2109 if (vcpu->pvclock_set_guest_stopped_request) {
2110 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2111 vcpu->pvclock_set_guest_stopped_request = false;
2112 }
2113
2114 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2115
4e335d9e
PB		 2116 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2117 &vcpu->hv_clock,
2118 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2119
2120 smp_wmb();
2121
2122 vcpu->hv_clock.version++;
4e335d9e
PB		 2123 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2124 &vcpu->hv_clock,
2125 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2126}
2127
34c238a1 2128static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2129{
78db6a50 2130 unsigned long flags, tgt_tsc_khz;
18068523 2131 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2132 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2133 s64 kernel_ns;
d828199e 2134 u64 tsc_timestamp, host_tsc;
51d59c6b 2135 u8 pvclock_flags;
d828199e
MT		 2136 bool use_master_clock;
2137
2138 kernel_ns = 0;
2139 host_tsc = 0;
18068523 2140
d828199e
MT		 2141 /*
2142 * If the host uses TSC clock, then passthrough TSC as stable
2143 * to the guest.
2144 */
2145 spin_lock(&ka->pvclock_gtod_sync_lock);
2146 use_master_clock = ka->use_master_clock;
2147 if (use_master_clock) {
2148 host_tsc = ka->master_cycle_now;
2149 kernel_ns = ka->master_kernel_ns;
2150 }
2151 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2152
2153 /* Keep irq disabled to prevent changes to the clock */
2154 local_irq_save(flags);
78db6a50
PB		 2155 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2156 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2157 local_irq_restore(flags);
2158 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2159 return 1;
2160 }
d828199e 2161 if (!use_master_clock) {
4ea1636b 2162 host_tsc = rdtsc();
108b249c 2163 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2164 }
2165
4ba76538 2166 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2167
c285545f
ZA		 2168 /*
2169 * We may have to catch up the TSC to match elapsed wall clock
2170 * time for two reasons, even if kvmclock is used.
2171 * 1) CPU could have been running below the maximum TSC rate
2172 * 2) Broken TSC compensation resets the base at each VCPU
2173 * entry to avoid unknown leaps of TSC even when running
2174 * again on the same CPU. This may cause apparent elapsed
2175 * time to disappear, and the guest to stand still or run
2176 * very slowly.
2177 */
2178 if (vcpu->tsc_catchup) {
2179 u64 tsc = compute_guest_tsc(v, kernel_ns);
2180 if (tsc > tsc_timestamp) {
f1e2b260 2181 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2182 tsc_timestamp = tsc;
2183 }
50d0a0f9
GH		 2184 }
2185
18068523
GOC		 2186 local_irq_restore(flags);
2187
0d6dd2ff 2188 /* With all the info we got, fill in the values */
18068523 2189
78db6a50
PB		 2190 if (kvm_has_tsc_control)
2191 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2192
2193 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2194 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2195 &vcpu->hv_clock.tsc_shift,
2196 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2197 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2198 }
2199
1d5f066e 2200 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2201 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2202 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2203
d828199e 2204 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2205 pvclock_flags = 0;
d828199e
MT		 2206 if (use_master_clock)
2207 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2208
78c0337a
MT		 2209 vcpu->hv_clock.flags = pvclock_flags;
2210
095cf55d
PB		 2211 if (vcpu->pv_time_enabled)
2212 kvm_setup_pvclock_page(v);
2213 if (v == kvm_get_vcpu(v->kvm, 0))
2214 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2215 return 0;
c8076604
GH		 2216}
2217
0061d53d
MT		 2218/*
2219 * kvmclock updates which are isolated to a given vcpu, such as
2220 * vcpu->cpu migration, should not allow system_timestamp from
2221 * the rest of the vcpus to remain static. Otherwise ntp frequency
2222 * correction applies to one vcpu's system_timestamp but not
2223 * the others.
2224 *
2225 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2226 * We need to rate-limit these requests though, as they can
2227 * considerably slow guests that have a large number of vcpus.
2228 * The time for a remote vcpu to update its kvmclock is bound
2229 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2230 */
2231
7e44e449
AJ		 2232#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2233
2234static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2235{
2236 int i;
7e44e449
AJ		 2237 struct delayed_work *dwork = to_delayed_work(work);
2238 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2239 kvmclock_update_work);
2240 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2241 struct kvm_vcpu *vcpu;
2242
2243 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2244 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2245 kvm_vcpu_kick(vcpu);
2246 }
2247}
2248
7e44e449
AJ		 2249static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2250{
2251 struct kvm *kvm = v->kvm;
2252
105b21bb 2253 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2254 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2255 KVMCLOCK_UPDATE_DELAY);
2256}
2257
332967a3
AJ		 2258#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2259
2260static void kvmclock_sync_fn(struct work_struct *work)
2261{
2262 struct delayed_work *dwork = to_delayed_work(work);
2263 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2264 kvmclock_sync_work);
2265 struct kvm *kvm = container_of(ka, struct kvm, arch);
2266
630994b3
MT		 2267 if (!kvmclock_periodic_sync)
2268 return;
2269
332967a3
AJ		 2270 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2271 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2272 KVMCLOCK_SYNC_PERIOD);
2273}
2274
9ffd986c 2275static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2276{
890ca9ae
HY		 2277 u64 mcg_cap = vcpu->arch.mcg_cap;
2278 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2279 u32 msr = msr_info->index;
2280 u64 data = msr_info->data;
890ca9ae 2281
15c4a640 2282 switch (msr) {
15c4a640 2283 case MSR_IA32_MCG_STATUS:
890ca9ae 2284 vcpu->arch.mcg_status = data;
15c4a640 2285 break;
c7ac679c 2286 case MSR_IA32_MCG_CTL:
44883f01
PB		 2287 if (!(mcg_cap & MCG_CTL_P) &&
2288 (data || !msr_info->host_initiated))
890ca9ae
HY		 2289 return 1;
2290 if (data != 0 && data != ~(u64)0)
44883f01 2291 return 1;
890ca9ae
HY		 2292 vcpu->arch.mcg_ctl = data;
2293 break;
2294 default:
2295 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2296 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2297 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2298 /* only 0 or all 1s can be written to IA32_MCi_CTL
2299 * some Linux kernels though clear bit 10 in bank 4 to
2300 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2301 * this to avoid an uncatched #GP in the guest
2302 */
890ca9ae 2303 if ((offset & 0x3) == 0 &&
114be429 2304 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2305 return -1;
9ffd986c
WL		 2306 if (!msr_info->host_initiated &&
2307 (offset & 0x3) == 1 && data != 0)
2308 return -1;
890ca9ae
HY		 2309 vcpu->arch.mce_banks[offset] = data;
2310 break;
2311 }
2312 return 1;
2313 }
2314 return 0;
2315}
2316
ffde22ac
ES		 2317static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2318{
2319 struct kvm *kvm = vcpu->kvm;
2320 int lm = is_long_mode(vcpu);
2321 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2322 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2323 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2324 : kvm->arch.xen_hvm_config.blob_size_32;
2325 u32 page_num = data & ~PAGE_MASK;
2326 u64 page_addr = data & PAGE_MASK;
2327 u8 *page;
2328 int r;
2329
2330 r = -E2BIG;
2331 if (page_num >= blob_size)
2332 goto out;
2333 r = -ENOMEM;
ff5c2c03
SL		 2334 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2335 if (IS_ERR(page)) {
2336 r = PTR_ERR(page);
ffde22ac 2337 goto out;
ff5c2c03 2338 }
54bf36aa 2339 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2340 goto out_free;
2341 r = 0;
2342out_free:
2343 kfree(page);
2344out:
2345 return r;
2346}
2347
344d9588
GN		 2348static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2349{
2350 gpa_t gpa = data & ~0x3f;
2351
52a5c155
WL		 2352 /* Bits 3:5 are reserved, Should be zero */
2353 if (data & 0x38)
344d9588
GN		 2354 return 1;
2355
2356 vcpu->arch.apf.msr_val = data;
2357
2358 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2359 kvm_clear_async_pf_completion_queue(vcpu);
2360 kvm_async_pf_hash_reset(vcpu);
2361 return 0;
2362 }
2363
4e335d9e 2364 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2365 sizeof(u32)))
344d9588
GN		 2366 return 1;
2367
6adba527 2368 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2369 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2370 kvm_async_pf_wakeup_all(vcpu);
2371 return 0;
2372}
2373
12f9a48f
GC		 2374static void kvmclock_reset(struct kvm_vcpu *vcpu)
2375{
0b79459b 2376 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2377}
2378
f38a7b75
WL		 2379static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2380{
2381 ++vcpu->stat.tlb_flush;
2382 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2383}
2384
c9aaa895
GC		 2385static void record_steal_time(struct kvm_vcpu *vcpu)
2386{
2387 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2388 return;
2389
4e335d9e 2390 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2391 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2392 return;
2393
f38a7b75
WL		 2394 /*
2395 * Doing a TLB flush here, on the guest's behalf, can avoid
2396 * expensive IPIs.
2397 */
2398 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2399 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2400
35f3fae1
WL		 2401 if (vcpu->arch.st.steal.version & 1)
2402 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2403
2404 vcpu->arch.st.steal.version += 1;
2405
4e335d9e 2406 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2407 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2408
2409 smp_wmb();
2410
c54cdf14
LC		 2411 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2412 vcpu->arch.st.last_steal;
2413 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2414
4e335d9e 2415 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2416 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2417
2418 smp_wmb();
2419
2420 vcpu->arch.st.steal.version += 1;
c9aaa895 2421
4e335d9e 2422 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2423 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2424}
2425
8fe8ab46 2426int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2427{
5753785f 2428 bool pr = false;
8fe8ab46
WA		 2429 u32 msr = msr_info->index;
2430 u64 data = msr_info->data;
5753785f 2431
15c4a640 2432 switch (msr) {
2e32b719 2433 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2434 case MSR_IA32_UCODE_WRITE:
2435 case MSR_VM_HSAVE_PA:
2436 case MSR_AMD64_PATCH_LOADER:
2437 case MSR_AMD64_BU_CFG2:
405a353a 2438 case MSR_AMD64_DC_CFG:
0e1b869f 2439 case MSR_F15H_EX_CFG:
2e32b719
BP		 2440 break;
2441
518e7b94
WL		 2442 case MSR_IA32_UCODE_REV:
2443 if (msr_info->host_initiated)
2444 vcpu->arch.microcode_version = data;
2445 break;
15c4a640 2446 case MSR_EFER:
b69e8cae 2447 return set_efer(vcpu, data);
8f1589d9
AP		 2448 case MSR_K7_HWCR:
2449 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2450 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2451 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2452 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2453 if (data != 0) {
a737f256
CD		 2454 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2455 data);
8f1589d9
AP		 2456 return 1;
2457 }
15c4a640 2458 break;
f7c6d140
AP		 2459 case MSR_FAM10H_MMIO_CONF_BASE:
2460 if (data != 0) {
a737f256
CD		 2461 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2462 "0x%llx\n", data);
f7c6d140
AP		 2463 return 1;
2464 }
15c4a640 2465 break;
b5e2fec0
AG		 2466 case MSR_IA32_DEBUGCTLMSR:
2467 if (!data) {
2468 /* We support the non-activated case already */
2469 break;
2470 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2471 /* Values other than LBR and BTF are vendor-specific,
2472 thus reserved and should throw a #GP */
2473 return 1;
2474 }
a737f256
CD		 2475 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2476 __func__, data);
b5e2fec0 2477 break;
9ba075a6 2478 case 0x200 ... 0x2ff:
ff53604b 2479 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2480 case MSR_IA32_APICBASE:
58cb628d 2481 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2482 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2483 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2484 case MSR_IA32_TSCDEADLINE:
2485 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2486 break;
ba904635 2487 case MSR_IA32_TSC_ADJUST:
d6321d49 2488 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2489 if (!msr_info->host_initiated) {
d913b904 2490 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2491 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2492 }
2493 vcpu->arch.ia32_tsc_adjust_msr = data;
2494 }
2495 break;
15c4a640 2496 case MSR_IA32_MISC_ENABLE:
ad312c7c 2497 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2498 break;
64d60670
PB		 2499 case MSR_IA32_SMBASE:
2500 if (!msr_info->host_initiated)
2501 return 1;
2502 vcpu->arch.smbase = data;
2503 break;
dd259935
PB		 2504 case MSR_IA32_TSC:
2505 kvm_write_tsc(vcpu, msr_info);
2506 break;
52797bf9
LA		 2507 case MSR_SMI_COUNT:
2508 if (!msr_info->host_initiated)
2509 return 1;
2510 vcpu->arch.smi_count = data;
2511 break;
11c6bffa 2512 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2513 case MSR_KVM_WALL_CLOCK:
2514 vcpu->kvm->arch.wall_clock = data;
2515 kvm_write_wall_clock(vcpu->kvm, data);
2516 break;
11c6bffa 2517 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2518 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2519 struct kvm_arch *ka = &vcpu->kvm->arch;
2520
12f9a48f 2521 kvmclock_reset(vcpu);
18068523 2522
54750f2c
MT		 2523 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2524 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2525
2526 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2527 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2528
2529 ka->boot_vcpu_runs_old_kvmclock = tmp;
2530 }
2531
18068523 2532 vcpu->arch.time = data;
0061d53d 2533 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2534
2535 /* we verify if the enable bit is set... */
2536 if (!(data & 1))
2537 break;
2538
4e335d9e 2539 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2540 &vcpu->arch.pv_time, data & ~1ULL,
2541 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2542 vcpu->arch.pv_time_enabled = false;
2543 else
2544 vcpu->arch.pv_time_enabled = true;
32cad84f 2545
18068523
GOC		 2546 break;
2547 }
344d9588
GN		 2548 case MSR_KVM_ASYNC_PF_EN:
2549 if (kvm_pv_enable_async_pf(vcpu, data))
2550 return 1;
2551 break;
c9aaa895
GC		 2552 case MSR_KVM_STEAL_TIME:
2553
2554 if (unlikely(!sched_info_on()))
2555 return 1;
2556
2557 if (data & KVM_STEAL_RESERVED_MASK)
2558 return 1;
2559
4e335d9e 2560 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2561 data & KVM_STEAL_VALID_BITS,
2562 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2563 return 1;
2564
2565 vcpu->arch.st.msr_val = data;
2566
2567 if (!(data & KVM_MSR_ENABLED))
2568 break;
2569
c9aaa895
GC		 2570 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2571
2572 break;
ae7a2a3f 2573 case MSR_KVM_PV_EOI_EN:
72bbf935 2574 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2575 return 1;
2576 break;
c9aaa895 2577
890ca9ae
HY		 2578 case MSR_IA32_MCG_CTL:
2579 case MSR_IA32_MCG_STATUS:
81760dcc 2580 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2581 return set_msr_mce(vcpu, msr_info);
71db6023 2582
6912ac32
WH		 2583 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2584 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2585 pr = true; /* fall through */
2586 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2587 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2588 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2589 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2590
2591 if (pr || data != 0)
a737f256
CD		 2592 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2593 "0x%x data 0x%llx\n", msr, data);
5753785f 2594 break;
84e0cefa
JS		 2595 case MSR_K7_CLK_CTL:
2596 /*
2597 * Ignore all writes to this no longer documented MSR.
2598 * Writes are only relevant for old K7 processors,
2599 * all pre-dating SVM, but a recommended workaround from
4a969980 2600 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2601 * affected processor models on the command line, hence
2602 * the need to ignore the workaround.
2603 */
2604 break;
55cd8e5a 2605 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2606 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2607 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2608 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2609 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2610 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2611 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2612 return kvm_hv_set_msr_common(vcpu, msr, data,
2613 msr_info->host_initiated);
91c9c3ed 2614 case MSR_IA32_BBL_CR_CTL3:
2615 /* Drop writes to this legacy MSR -- see rdmsr
2616 * counterpart for further detail.
2617 */
fab0aa3b
EM		 2618 if (report_ignored_msrs)
2619 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2620 msr, data);
91c9c3ed 2621 break;
2b036c6b 2622 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2623 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2624 return 1;
2625 vcpu->arch.osvw.length = data;
2626 break;
2627 case MSR_AMD64_OSVW_STATUS:
d6321d49 2628 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2629 return 1;
2630 vcpu->arch.osvw.status = data;
2631 break;
db2336a8
KH		 2632 case MSR_PLATFORM_INFO:
2633 if (!msr_info->host_initiated ||
db2336a8
KH		 2634 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2635 cpuid_fault_enabled(vcpu)))
2636 return 1;
2637 vcpu->arch.msr_platform_info = data;
2638 break;
2639 case MSR_MISC_FEATURES_ENABLES:
2640 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2641 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2642 !supports_cpuid_fault(vcpu)))
2643 return 1;
2644 vcpu->arch.msr_misc_features_enables = data;
2645 break;
15c4a640 2646 default:
ffde22ac
ES		 2647 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2648 return xen_hvm_config(vcpu, data);
c6702c9d 2649 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2650 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2651 if (!ignore_msrs) {
ae0f5499 2652 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2653 msr, data);
ed85c068
AP		 2654 return 1;
2655 } else {
fab0aa3b
EM		 2656 if (report_ignored_msrs)
2657 vcpu_unimpl(vcpu,
2658 "ignored wrmsr: 0x%x data 0x%llx\n",
2659 msr, data);
ed85c068
AP		 2660 break;
2661 }
15c4a640
CO		 2662 }
2663 return 0;
2664}
2665EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2666
2667
2668/*
2669 * Reads an msr value (of 'msr_index') into 'pdata'.
2670 * Returns 0 on success, non-0 otherwise.
2671 * Assumes vcpu_load() was already called.
2672 */
609e36d3 2673int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2674{
609e36d3 2675 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2676}
ff651cb6 2677EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2678
44883f01 2679static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2680{
2681 u64 data;
890ca9ae
HY		 2682 u64 mcg_cap = vcpu->arch.mcg_cap;
2683 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2684
2685 switch (msr) {
15c4a640
CO		 2686 case MSR_IA32_P5_MC_ADDR:
2687 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2688 data = 0;
2689 break;
15c4a640 2690 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2691 data = vcpu->arch.mcg_cap;
2692 break;
c7ac679c 2693 case MSR_IA32_MCG_CTL:
44883f01 2694 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2695 return 1;
2696 data = vcpu->arch.mcg_ctl;
2697 break;
2698 case MSR_IA32_MCG_STATUS:
2699 data = vcpu->arch.mcg_status;
2700 break;
2701 default:
2702 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2703 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2704 u32 offset = msr - MSR_IA32_MC0_CTL;
2705 data = vcpu->arch.mce_banks[offset];
2706 break;
2707 }
2708 return 1;
2709 }
2710 *pdata = data;
2711 return 0;
2712}
2713
609e36d3 2714int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2715{
609e36d3 2716 switch (msr_info->index) {
890ca9ae 2717 case MSR_IA32_PLATFORM_ID:
15c4a640 2718 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2719 case MSR_IA32_DEBUGCTLMSR:
2720 case MSR_IA32_LASTBRANCHFROMIP:
2721 case MSR_IA32_LASTBRANCHTOIP:
2722 case MSR_IA32_LASTINTFROMIP:
2723 case MSR_IA32_LASTINTTOIP:
60af2ecd 2724 case MSR_K8_SYSCFG:
3afb1121
PB		 2725 case MSR_K8_TSEG_ADDR:
2726 case MSR_K8_TSEG_MASK:
60af2ecd 2727 case MSR_K7_HWCR:
61a6bd67 2728 case MSR_VM_HSAVE_PA:
1fdbd48c 2729 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2730 case MSR_AMD64_NB_CFG:
f7c6d140 2731 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2732 case MSR_AMD64_BU_CFG2:
0c2df2a1 2733 case MSR_IA32_PERF_CTL:
405a353a 2734 case MSR_AMD64_DC_CFG:
0e1b869f 2735 case MSR_F15H_EX_CFG:
609e36d3 2736 msr_info->data = 0;
15c4a640 2737 break;
c51eb52b 2738 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2739 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2740 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2741 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2742 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2743 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2744 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2745 msr_info->data = 0;
5753785f 2746 break;
742bc670 2747 case MSR_IA32_UCODE_REV:
518e7b94 2748 msr_info->data = vcpu->arch.microcode_version;
742bc670 2749 break;
dd259935
PB		 2750 case MSR_IA32_TSC:
2751 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2752 break;
9ba075a6 2753 case MSR_MTRRcap:
9ba075a6 2754 case 0x200 ... 0x2ff:
ff53604b 2755 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2756 case 0xcd: /* fsb frequency */
609e36d3 2757 msr_info->data = 3;
15c4a640 2758 break;
7b914098
JS		 2759 /*
2760 * MSR_EBC_FREQUENCY_ID
2761 * Conservative value valid for even the basic CPU models.
2762 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2763 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2764 * and 266MHz for model 3, or 4. Set Core Clock
2765 * Frequency to System Bus Frequency Ratio to 1 (bits
2766 * 31:24) even though these are only valid for CPU
2767 * models > 2, however guests may end up dividing or
2768 * multiplying by zero otherwise.
2769 */
2770 case MSR_EBC_FREQUENCY_ID:
609e36d3 2771 msr_info->data = 1 << 24;
7b914098 2772 break;
15c4a640 2773 case MSR_IA32_APICBASE:
609e36d3 2774 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2775 break;
0105d1a5 2776 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2777 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2778 break;
a3e06bbe 2779 case MSR_IA32_TSCDEADLINE:
609e36d3 2780 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2781 break;
ba904635 2782 case MSR_IA32_TSC_ADJUST:
609e36d3 2783 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2784 break;
15c4a640 2785 case MSR_IA32_MISC_ENABLE:
609e36d3 2786 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2787 break;
64d60670
PB		 2788 case MSR_IA32_SMBASE:
2789 if (!msr_info->host_initiated)
2790 return 1;
2791 msr_info->data = vcpu->arch.smbase;
15c4a640 2792 break;
52797bf9
LA		 2793 case MSR_SMI_COUNT:
2794 msr_info->data = vcpu->arch.smi_count;
2795 break;
847f0ad8
AG		 2796 case MSR_IA32_PERF_STATUS:
2797 /* TSC increment by tick */
609e36d3 2798 msr_info->data = 1000ULL;
847f0ad8 2799 /* CPU multiplier */
b0996ae4 2800 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2801 break;
15c4a640 2802 case MSR_EFER:
609e36d3 2803 msr_info->data = vcpu->arch.efer;
15c4a640 2804 break;
18068523 2805 case MSR_KVM_WALL_CLOCK:
11c6bffa 2806 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2807 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2808 break;
2809 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2810 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2811 msr_info->data = vcpu->arch.time;
18068523 2812 break;
344d9588 2813 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2814 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2815 break;
c9aaa895 2816 case MSR_KVM_STEAL_TIME:
609e36d3 2817 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2818 break;
1d92128f 2819 case MSR_KVM_PV_EOI_EN:
609e36d3 2820 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2821 break;
890ca9ae
HY		 2822 case MSR_IA32_P5_MC_ADDR:
2823 case MSR_IA32_P5_MC_TYPE:
2824 case MSR_IA32_MCG_CAP:
2825 case MSR_IA32_MCG_CTL:
2826 case MSR_IA32_MCG_STATUS:
81760dcc 2827 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2828 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2829 msr_info->host_initiated);
84e0cefa
JS		 2830 case MSR_K7_CLK_CTL:
2831 /*
2832 * Provide expected ramp-up count for K7. All other
2833 * are set to zero, indicating minimum divisors for
2834 * every field.
2835 *
2836 * This prevents guest kernels on AMD host with CPU
2837 * type 6, model 8 and higher from exploding due to
2838 * the rdmsr failing.
2839 */
609e36d3 2840 msr_info->data = 0x20000000;
84e0cefa 2841 break;
55cd8e5a 2842 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2843 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2844 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2845 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2846 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2847 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2848 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2849 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2850 msr_info->index, &msr_info->data,
2851 msr_info->host_initiated);
55cd8e5a 2852 break;
91c9c3ed 2853 case MSR_IA32_BBL_CR_CTL3:
2854 /* This legacy MSR exists but isn't fully documented in current
2855 * silicon. It is however accessed by winxp in very narrow
2856 * scenarios where it sets bit #19, itself documented as
2857 * a "reserved" bit. Best effort attempt to source coherent
2858 * read data here should the balance of the register be
2859 * interpreted by the guest:
2860 *
2861 * L2 cache control register 3: 64GB range, 256KB size,
2862 * enabled, latency 0x1, configured
2863 */
609e36d3 2864 msr_info->data = 0xbe702111;
91c9c3ed 2865 break;
2b036c6b 2866 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2867 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2868 return 1;
609e36d3 2869 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2870 break;
2871 case MSR_AMD64_OSVW_STATUS:
d6321d49 2872 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2873 return 1;
609e36d3 2874 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2875 break;
db2336a8 2876 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 2877 if (!msr_info->host_initiated &&
2878 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
2879 return 1;
db2336a8
KH		 2880 msr_info->data = vcpu->arch.msr_platform_info;
2881 break;
2882 case MSR_MISC_FEATURES_ENABLES:
2883 msr_info->data = vcpu->arch.msr_misc_features_enables;
2884 break;
15c4a640 2885 default:
c6702c9d 2886 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2887 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2888 if (!ignore_msrs) {
ae0f5499
BD		 2889 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2890 msr_info->index);
ed85c068
AP		 2891 return 1;
2892 } else {
fab0aa3b
EM		 2893 if (report_ignored_msrs)
2894 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2895 msr_info->index);
609e36d3 2896 msr_info->data = 0;
ed85c068
AP		 2897 }
2898 break;
15c4a640 2899 }
15c4a640
CO		 2900 return 0;
2901}
2902EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2903
313a3dc7
CO		 2904/*
2905 * Read or write a bunch of msrs. All parameters are kernel addresses.
2906 *
2907 * @return number of msrs set successfully.
2908 */
2909static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2910 struct kvm_msr_entry *entries,
2911 int (*do_msr)(struct kvm_vcpu *vcpu,
2912 unsigned index, u64 *data))
2913{
801e459a 2914 int i;
313a3dc7 2915
313a3dc7
CO		 2916 for (i = 0; i < msrs->nmsrs; ++i)
2917 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2918 break;
2919
313a3dc7
CO		 2920 return i;
2921}
2922
2923/*
2924 * Read or write a bunch of msrs. Parameters are user addresses.
2925 *
2926 * @return number of msrs set successfully.
2927 */
2928static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2929 int (*do_msr)(struct kvm_vcpu *vcpu,
2930 unsigned index, u64 *data),
2931 int writeback)
2932{
2933 struct kvm_msrs msrs;
2934 struct kvm_msr_entry *entries;
2935 int r, n;
2936 unsigned size;
2937
2938 r = -EFAULT;
0e96f31e 2939 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 2940 goto out;
2941
2942 r = -E2BIG;
2943 if (msrs.nmsrs >= MAX_IO_MSRS)
2944 goto out;
2945
313a3dc7 2946 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2947 entries = memdup_user(user_msrs->entries, size);
2948 if (IS_ERR(entries)) {
2949 r = PTR_ERR(entries);
313a3dc7 2950 goto out;
ff5c2c03 2951 }
313a3dc7
CO		 2952
2953 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2954 if (r < 0)
2955 goto out_free;
2956
2957 r = -EFAULT;
2958 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2959 goto out_free;
2960
2961 r = n;
2962
2963out_free:
7a73c028 2964 kfree(entries);
313a3dc7
CO		 2965out:
2966 return r;
2967}
2968
4d5422ce
WL		 2969static inline bool kvm_can_mwait_in_guest(void)
2970{
2971 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2972 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2973 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2974}
2975
784aa3d7 2976int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2977{
4d5422ce 2978 int r = 0;
018d00d2
ZX		 2979
2980 switch (ext) {
2981 case KVM_CAP_IRQCHIP:
2982 case KVM_CAP_HLT:
2983 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2984 case KVM_CAP_SET_TSS_ADDR:
07716717 2985 case KVM_CAP_EXT_CPUID:
9c15bb1d 2986 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2987 case KVM_CAP_CLOCKSOURCE:
7837699f 2988 case KVM_CAP_PIT:
a28e4f5a 2989 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2990 case KVM_CAP_MP_STATE:
ed848624 2991 case KVM_CAP_SYNC_MMU:
a355c85c 2992 case KVM_CAP_USER_NMI:
52d939a0 2993 case KVM_CAP_REINJECT_CONTROL:
4925663a 2994 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2995 case KVM_CAP_IOEVENTFD:
f848a5a8 2996 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2997 case KVM_CAP_PIT2:
e9f42757 2998 case KVM_CAP_PIT_STATE2:
b927a3ce 2999 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 3000 case KVM_CAP_XEN_HVM:
3cfc3092 3001 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 3002 case KVM_CAP_HYPERV:
10388a07 3003 case KVM_CAP_HYPERV_VAPIC:
c25bc163 3004 case KVM_CAP_HYPERV_SPIN:
5c919412 3005 case KVM_CAP_HYPERV_SYNIC:
efc479e6 3006 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 3007 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 3008 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3009 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3010 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 3011 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
2bc39970 3012 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3013 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3014 case KVM_CAP_DEBUGREGS:
d2be1651 3015 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3016 case KVM_CAP_XSAVE:
344d9588 3017 case KVM_CAP_ASYNC_PF:
92a1f12d 3018 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3019 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3020 case KVM_CAP_READONLY_MEM:
5f66b620 3021 case KVM_CAP_HYPERV_TIME:
100943c5 3022 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3023 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3024 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3025 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3026 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3027 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 3028 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3029 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3030 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3031 r = 1;
3032 break;
01643c51
KH		 3033 case KVM_CAP_SYNC_REGS:
3034 r = KVM_SYNC_X86_VALID_FIELDS;
3035 break;
e3fd9a93
PB		 3036 case KVM_CAP_ADJUST_CLOCK:
3037 r = KVM_CLOCK_TSC_STABLE;
3038 break;
4d5422ce 3039 case KVM_CAP_X86_DISABLE_EXITS:
766d3571 3040 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 3041 if(kvm_can_mwait_in_guest())
3042 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3043 break;
6d396b55
PB		 3044 case KVM_CAP_X86_SMM:
3045 /* SMBASE is usually relocated above 1M on modern chipsets,
3046 * and SMM handlers might indeed rely on 4G segment limits,
3047 * so do not report SMM to be available if real mode is
3048 * emulated via vm86 mode. Still, do not go to great lengths
3049 * to avoid userspace's usage of the feature, because it is a
3050 * fringe case that is not enabled except via specific settings
3051 * of the module parameters.
3052 */
bc226f07 3053 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3054 break;
774ead3a
AK		 3055 case KVM_CAP_VAPIC:
3056 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3057 break;
f725230a 3058 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3059 r = KVM_SOFT_MAX_VCPUS;
3060 break;
3061 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3062 r = KVM_MAX_VCPUS;
3063 break;
a988b910 3064 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 3065 r = KVM_USER_MEM_SLOTS;
a988b910 3066 break;
a68a6a72
MT		 3067 case KVM_CAP_PV_MMU: /* obsolete */
3068 r = 0;
2f333bcb 3069 break;
890ca9ae
HY		 3070 case KVM_CAP_MCE:
3071 r = KVM_MAX_MCE_BANKS;
3072 break;
2d5b5a66 3073 case KVM_CAP_XCRS:
d366bf7e 3074 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3075 break;
92a1f12d
JR		 3076 case KVM_CAP_TSC_CONTROL:
3077 r = kvm_has_tsc_control;
3078 break;
37131313
RK		 3079 case KVM_CAP_X2APIC_API:
3080 r = KVM_X2APIC_API_VALID_FLAGS;
3081 break;
8fcc4b59
JM		 3082 case KVM_CAP_NESTED_STATE:
3083 r = kvm_x86_ops->get_nested_state ?
3084 kvm_x86_ops->get_nested_state(NULL, 0, 0) : 0;
3085 break;
018d00d2 3086 default:
018d00d2
ZX		 3087 break;
3088 }
3089 return r;
3090
3091}
3092
043405e1
CO		 3093long kvm_arch_dev_ioctl(struct file *filp,
3094 unsigned int ioctl, unsigned long arg)
3095{
3096 void __user *argp = (void __user *)arg;
3097 long r;
3098
3099 switch (ioctl) {
3100 case KVM_GET_MSR_INDEX_LIST: {
3101 struct kvm_msr_list __user *user_msr_list = argp;
3102 struct kvm_msr_list msr_list;
3103 unsigned n;
3104
3105 r = -EFAULT;
0e96f31e 3106 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3107 goto out;
3108 n = msr_list.nmsrs;
62ef68bb 3109 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3110 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3111 goto out;
3112 r = -E2BIG;
e125e7b6 3113 if (n < msr_list.nmsrs)
043405e1
CO		 3114 goto out;
3115 r = -EFAULT;
3116 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3117 num_msrs_to_save * sizeof(u32)))
3118 goto out;
e125e7b6 3119 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3120 &emulated_msrs,
62ef68bb 3121 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3122 goto out;
3123 r = 0;
3124 break;
3125 }
9c15bb1d
BP		 3126 case KVM_GET_SUPPORTED_CPUID:
3127 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3128 struct kvm_cpuid2 __user *cpuid_arg = argp;
3129 struct kvm_cpuid2 cpuid;
3130
3131 r = -EFAULT;
0e96f31e 3132 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3133 goto out;
9c15bb1d
BP		 3134
3135 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3136 ioctl);
674eea0f
AK		 3137 if (r)
3138 goto out;
3139
3140 r = -EFAULT;
0e96f31e 3141 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3142 goto out;
3143 r = 0;
3144 break;
3145 }
890ca9ae 3146 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3147 r = -EFAULT;
c45dcc71
AR		 3148 if (copy_to_user(argp, &kvm_mce_cap_supported,
3149 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3150 goto out;
3151 r = 0;
3152 break;
801e459a
TL		 3153 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3154 struct kvm_msr_list __user *user_msr_list = argp;
3155 struct kvm_msr_list msr_list;
3156 unsigned int n;
3157
3158 r = -EFAULT;
3159 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3160 goto out;
3161 n = msr_list.nmsrs;
3162 msr_list.nmsrs = num_msr_based_features;
3163 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3164 goto out;
3165 r = -E2BIG;
3166 if (n < msr_list.nmsrs)
3167 goto out;
3168 r = -EFAULT;
3169 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3170 num_msr_based_features * sizeof(u32)))
3171 goto out;
3172 r = 0;
3173 break;
3174 }
3175 case KVM_GET_MSRS:
3176 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3177 break;
890ca9ae 3178 }
043405e1
CO		 3179 default:
3180 r = -EINVAL;
3181 }
3182out:
3183 return r;
3184}
3185
f5f48ee1
SY		 3186static void wbinvd_ipi(void *garbage)
3187{
3188 wbinvd();
3189}
3190
3191static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3192{
e0f0bbc5 3193 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3194}
3195
313a3dc7
CO		 3196void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3197{
f5f48ee1
SY		 3198 /* Address WBINVD may be executed by guest */
3199 if (need_emulate_wbinvd(vcpu)) {
3200 if (kvm_x86_ops->has_wbinvd_exit())
3201 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3202 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3203 smp_call_function_single(vcpu->cpu,
3204 wbinvd_ipi, NULL, 1);
3205 }
3206
313a3dc7 3207 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3208
0dd6a6ed
ZA		 3209 /* Apply any externally detected TSC adjustments (due to suspend) */
3210 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3211 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3212 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3213 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3214 }
8f6055cb 3215
b0c39dc6 3216 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3217 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3218 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3219 if (tsc_delta < 0)
3220 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3221
b0c39dc6 3222 if (kvm_check_tsc_unstable()) {
07c1419a 3223 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3224 vcpu->arch.last_guest_tsc);
a545ab6a 3225 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3226 vcpu->arch.tsc_catchup = 1;
c285545f 3227 }
a749e247
PB		 3228
3229 if (kvm_lapic_hv_timer_in_use(vcpu))
3230 kvm_lapic_restart_hv_timer(vcpu);
3231
d98d07ca
MT		 3232 /*
3233 * On a host with synchronized TSC, there is no need to update
3234 * kvmclock on vcpu->cpu migration
3235 */
3236 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3237 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3238 if (vcpu->cpu != cpu)
1bd2009e 3239 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3240 vcpu->cpu = cpu;
6b7d7e76 3241 }
c9aaa895 3242
c9aaa895 3243 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3244}
3245
0b9f6c46
PX		 3246static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3247{
3248 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3249 return;
3250
fa55eedd 3251 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3252
4e335d9e 3253 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3254 &vcpu->arch.st.steal.preempted,
3255 offsetof(struct kvm_steal_time, preempted),
3256 sizeof(vcpu->arch.st.steal.preempted));
3257}
3258
313a3dc7
CO		 3259void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3260{
cc0d907c 3261 int idx;
de63ad4c
LM		 3262
3263 if (vcpu->preempted)
3264 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3265
931f261b
AA		 3266 /*
3267 * Disable page faults because we're in atomic context here.
3268 * kvm_write_guest_offset_cached() would call might_fault()
3269 * that relies on pagefault_disable() to tell if there's a
3270 * bug. NOTE: the write to guest memory may not go through if
3271 * during postcopy live migration or if there's heavy guest
3272 * paging.
3273 */
3274 pagefault_disable();
cc0d907c
AA		 3275 /*
3276 * kvm_memslots() will be called by
3277 * kvm_write_guest_offset_cached() so take the srcu lock.
3278 */
3279 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3280 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3281 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3282 pagefault_enable();
02daab21 3283 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3284 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3285 /*
f9dcf08e
RK		 3286 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3287 * on every vmexit, but if not, we might have a stale dr6 from the
3288 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3289 */
f9dcf08e 3290 set_debugreg(0, 6);
313a3dc7
CO		 3291}
3292
313a3dc7
CO		 3293static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3294 struct kvm_lapic_state *s)
3295{
fa59cc00 3296 if (vcpu->arch.apicv_active)
d62caabb
AS		 3297 kvm_x86_ops->sync_pir_to_irr(vcpu);
3298
a92e2543 3299 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3300}
3301
3302static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3303 struct kvm_lapic_state *s)
3304{
a92e2543
RK		 3305 int r;
3306
3307 r = kvm_apic_set_state(vcpu, s);
3308 if (r)
3309 return r;
cb142eb7 3310 update_cr8_intercept(vcpu);
313a3dc7
CO		 3311
3312 return 0;
3313}
3314
127a457a
MG		 3315static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3316{
3317 return (!lapic_in_kernel(vcpu) ||
3318 kvm_apic_accept_pic_intr(vcpu));
3319}
3320
782d422b
MG		 3321/*
3322 * if userspace requested an interrupt window, check that the
3323 * interrupt window is open.
3324 *
3325 * No need to exit to userspace if we already have an interrupt queued.
3326 */
3327static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3328{
3329 return kvm_arch_interrupt_allowed(vcpu) &&
3330 !kvm_cpu_has_interrupt(vcpu) &&
3331 !kvm_event_needs_reinjection(vcpu) &&
3332 kvm_cpu_accept_dm_intr(vcpu);
3333}
3334
f77bc6a4
ZX		 3335static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3336 struct kvm_interrupt *irq)
3337{
02cdb50f 3338 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3339 return -EINVAL;
1c1a9ce9
SR		 3340
3341 if (!irqchip_in_kernel(vcpu->kvm)) {
3342 kvm_queue_interrupt(vcpu, irq->irq, false);
3343 kvm_make_request(KVM_REQ_EVENT, vcpu);
3344 return 0;
3345 }
3346
3347 /*
3348 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3349 * fail for in-kernel 8259.
3350 */
3351 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3352 return -ENXIO;
f77bc6a4 3353
1c1a9ce9
SR		 3354 if (vcpu->arch.pending_external_vector != -1)
3355 return -EEXIST;
f77bc6a4 3356
1c1a9ce9 3357 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3358 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3359 return 0;
3360}
3361
c4abb7c9
JK		 3362static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3363{
c4abb7c9 3364 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3365
3366 return 0;
3367}
3368
f077825a
PB		 3369static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3370{
64d60670
PB		 3371 kvm_make_request(KVM_REQ_SMI, vcpu);
3372
f077825a
PB		 3373 return 0;
3374}
3375
b209749f
AK		 3376static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3377 struct kvm_tpr_access_ctl *tac)
3378{
3379 if (tac->flags)
3380 return -EINVAL;
3381 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3382 return 0;
3383}
3384
890ca9ae
HY		 3385static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3386 u64 mcg_cap)
3387{
3388 int r;
3389 unsigned bank_num = mcg_cap & 0xff, bank;
3390
3391 r = -EINVAL;
a9e38c3e 3392 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3393 goto out;
c45dcc71 3394 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3395 goto out;
3396 r = 0;
3397 vcpu->arch.mcg_cap = mcg_cap;
3398 /* Init IA32_MCG_CTL to all 1s */
3399 if (mcg_cap & MCG_CTL_P)
3400 vcpu->arch.mcg_ctl = ~(u64)0;
3401 /* Init IA32_MCi_CTL to all 1s */
3402 for (bank = 0; bank < bank_num; bank++)
3403 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3404
3405 if (kvm_x86_ops->setup_mce)
3406 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3407out:
3408 return r;
3409}
3410
3411static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3412 struct kvm_x86_mce *mce)
3413{
3414 u64 mcg_cap = vcpu->arch.mcg_cap;
3415 unsigned bank_num = mcg_cap & 0xff;
3416 u64 *banks = vcpu->arch.mce_banks;
3417
3418 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3419 return -EINVAL;
3420 /*
3421 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3422 * reporting is disabled
3423 */
3424 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3425 vcpu->arch.mcg_ctl != ~(u64)0)
3426 return 0;
3427 banks += 4 * mce->bank;
3428 /*
3429 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3430 * reporting is disabled for the bank
3431 */
3432 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3433 return 0;
3434 if (mce->status & MCI_STATUS_UC) {
3435 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3436 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3437 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3438 return 0;
3439 }
3440 if (banks[1] & MCI_STATUS_VAL)
3441 mce->status |= MCI_STATUS_OVER;
3442 banks[2] = mce->addr;
3443 banks[3] = mce->misc;
3444 vcpu->arch.mcg_status = mce->mcg_status;
3445 banks[1] = mce->status;
3446 kvm_queue_exception(vcpu, MC_VECTOR);
3447 } else if (!(banks[1] & MCI_STATUS_VAL)
3448 || !(banks[1] & MCI_STATUS_UC)) {
3449 if (banks[1] & MCI_STATUS_VAL)
3450 mce->status |= MCI_STATUS_OVER;
3451 banks[2] = mce->addr;
3452 banks[3] = mce->misc;
3453 banks[1] = mce->status;
3454 } else
3455 banks[1] |= MCI_STATUS_OVER;
3456 return 0;
3457}
3458
3cfc3092
JK		 3459static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3460 struct kvm_vcpu_events *events)
3461{
7460fb4a 3462 process_nmi(vcpu);
59073aaf 3463
664f8e26 3464 /*
59073aaf
JM		 3465 * The API doesn't provide the instruction length for software
3466 * exceptions, so don't report them. As long as the guest RIP
3467 * isn't advanced, we should expect to encounter the exception
3468 * again.
664f8e26 3469 */
59073aaf
JM		 3470 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3471 events->exception.injected = 0;
3472 events->exception.pending = 0;
3473 } else {
3474 events->exception.injected = vcpu->arch.exception.injected;
3475 events->exception.pending = vcpu->arch.exception.pending;
3476 /*
3477 * For ABI compatibility, deliberately conflate
3478 * pending and injected exceptions when
3479 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3480 */
3481 if (!vcpu->kvm->arch.exception_payload_enabled)
3482 events->exception.injected |=
3483 vcpu->arch.exception.pending;
3484 }
3cfc3092
JK		 3485 events->exception.nr = vcpu->arch.exception.nr;
3486 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3487 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3488 events->exception_has_payload = vcpu->arch.exception.has_payload;
3489 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3490
03b82a30 3491 events->interrupt.injected =
04140b41 3492 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3493 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3494 events->interrupt.soft = 0;
37ccdcbe 3495 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3496
3497 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3498 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3499 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3500 events->nmi.pad = 0;
3cfc3092 3501
66450a21 3502 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3503
f077825a
PB		 3504 events->smi.smm = is_smm(vcpu);
3505 events->smi.pending = vcpu->arch.smi_pending;
3506 events->smi.smm_inside_nmi =
3507 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3508 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3509
dab4b911 3510 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3511 | KVM_VCPUEVENT_VALID_SHADOW
3512 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3513 if (vcpu->kvm->arch.exception_payload_enabled)
3514 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3515
97e69aa6 3516 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3517}
3518
6ef4e07e
XG		 3519static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3520
3cfc3092
JK		 3521static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3522 struct kvm_vcpu_events *events)
3523{
dab4b911 3524 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3525 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3526 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3527 | KVM_VCPUEVENT_VALID_SMM
3528 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3529 return -EINVAL;
3530
59073aaf
JM		 3531 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3532 if (!vcpu->kvm->arch.exception_payload_enabled)
3533 return -EINVAL;
3534 if (events->exception.pending)
3535 events->exception.injected = 0;
3536 else
3537 events->exception_has_payload = 0;
3538 } else {
3539 events->exception.pending = 0;
3540 events->exception_has_payload = 0;
3541 }
3542
3543 if ((events->exception.injected || events->exception.pending) &&
3544 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3545 return -EINVAL;
3546
28bf2888
DH		 3547 /* INITs are latched while in SMM */
3548 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3549 (events->smi.smm || events->smi.pending) &&
3550 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3551 return -EINVAL;
3552
7460fb4a 3553 process_nmi(vcpu);
59073aaf
JM		 3554 vcpu->arch.exception.injected = events->exception.injected;
3555 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3556 vcpu->arch.exception.nr = events->exception.nr;
3557 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3558 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3559 vcpu->arch.exception.has_payload = events->exception_has_payload;
3560 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3561
04140b41 3562 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3563 vcpu->arch.interrupt.nr = events->interrupt.nr;
3564 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3565 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3566 kvm_x86_ops->set_interrupt_shadow(vcpu,
3567 events->interrupt.shadow);
3cfc3092
JK		 3568
3569 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3570 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3571 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3572 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3573
66450a21 3574 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3575 lapic_in_kernel(vcpu))
66450a21 3576 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3577
f077825a 3578 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3579 u32 hflags = vcpu->arch.hflags;
f077825a 3580 if (events->smi.smm)
6ef4e07e 3581 hflags |= HF_SMM_MASK;
f077825a 3582 else
6ef4e07e
XG		 3583 hflags &= ~HF_SMM_MASK;
3584 kvm_set_hflags(vcpu, hflags);
3585
f077825a 3586 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3587
3588 if (events->smi.smm) {
3589 if (events->smi.smm_inside_nmi)
3590 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3591 else
f4ef1910
WL		 3592 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3593 if (lapic_in_kernel(vcpu)) {
3594 if (events->smi.latched_init)
3595 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3596 else
3597 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3598 }
f077825a
PB		 3599 }
3600 }
3601
3842d135
AK		 3602 kvm_make_request(KVM_REQ_EVENT, vcpu);
3603
3cfc3092
JK		 3604 return 0;
3605}
3606
a1efbe77
JK		 3607static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3608 struct kvm_debugregs *dbgregs)
3609{
73aaf249
JK		 3610 unsigned long val;
3611
a1efbe77 3612 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3613 kvm_get_dr(vcpu, 6, &val);
73aaf249 3614 dbgregs->dr6 = val;
a1efbe77
JK		 3615 dbgregs->dr7 = vcpu->arch.dr7;
3616 dbgregs->flags = 0;
97e69aa6 3617 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3618}
3619
3620static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3621 struct kvm_debugregs *dbgregs)
3622{
3623 if (dbgregs->flags)
3624 return -EINVAL;
3625
d14bdb55
PB		 3626 if (dbgregs->dr6 & ~0xffffffffull)
3627 return -EINVAL;
3628 if (dbgregs->dr7 & ~0xffffffffull)
3629 return -EINVAL;
3630
a1efbe77 3631 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3632 kvm_update_dr0123(vcpu);
a1efbe77 3633 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3634 kvm_update_dr6(vcpu);
a1efbe77 3635 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3636 kvm_update_dr7(vcpu);
a1efbe77 3637
a1efbe77
JK		 3638 return 0;
3639}
3640
df1daba7
PB		 3641#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3642
3643static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3644{
b666a4b6 3645 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3646 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3647 u64 valid;
3648
3649 /*
3650 * Copy legacy XSAVE area, to avoid complications with CPUID
3651 * leaves 0 and 1 in the loop below.
3652 */
3653 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3654
3655 /* Set XSTATE_BV */
00c87e9a 3656 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3657 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3658
3659 /*
3660 * Copy each region from the possibly compacted offset to the
3661 * non-compacted offset.
3662 */
d91cab78 3663 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3664 while (valid) {
3665 u64 feature = valid & -valid;
3666 int index = fls64(feature) - 1;
3667 void *src = get_xsave_addr(xsave, feature);
3668
3669 if (src) {
3670 u32 size, offset, ecx, edx;
3671 cpuid_count(XSTATE_CPUID, index,
3672 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3673 if (feature == XFEATURE_MASK_PKRU)
3674 memcpy(dest + offset, &vcpu->arch.pkru,
3675 sizeof(vcpu->arch.pkru));
3676 else
3677 memcpy(dest + offset, src, size);
3678
df1daba7
PB		 3679 }
3680
3681 valid -= feature;
3682 }
3683}
3684
3685static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3686{
b666a4b6 3687 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 3688 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3689 u64 valid;
3690
3691 /*
3692 * Copy legacy XSAVE area, to avoid complications with CPUID
3693 * leaves 0 and 1 in the loop below.
3694 */
3695 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3696
3697 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3698 xsave->header.xfeatures = xstate_bv;
782511b0 3699 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3700 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3701
3702 /*
3703 * Copy each region from the non-compacted offset to the
3704 * possibly compacted offset.
3705 */
d91cab78 3706 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3707 while (valid) {
3708 u64 feature = valid & -valid;
3709 int index = fls64(feature) - 1;
3710 void *dest = get_xsave_addr(xsave, feature);
3711
3712 if (dest) {
3713 u32 size, offset, ecx, edx;
3714 cpuid_count(XSTATE_CPUID, index,
3715 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3716 if (feature == XFEATURE_MASK_PKRU)
3717 memcpy(&vcpu->arch.pkru, src + offset,
3718 sizeof(vcpu->arch.pkru));
3719 else
3720 memcpy(dest, src + offset, size);
ee4100da 3721 }
df1daba7
PB		 3722
3723 valid -= feature;
3724 }
3725}
3726
2d5b5a66
SY		 3727static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3728 struct kvm_xsave *guest_xsave)
3729{
d366bf7e 3730 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3731 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3732 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3733 } else {
2d5b5a66 3734 memcpy(guest_xsave->region,
b666a4b6 3735 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3736 sizeof(struct fxregs_state));
2d5b5a66 3737 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3738 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3739 }
3740}
3741
a575813b
WL		 3742#define XSAVE_MXCSR_OFFSET 24
3743
2d5b5a66
SY		 3744static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3745 struct kvm_xsave *guest_xsave)
3746{
3747 u64 xstate_bv =
3748 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3749 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3750
d366bf7e 3751 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3752 /*
3753 * Here we allow setting states that are not present in
3754 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3755 * with old userspace.
3756 */
a575813b
WL		 3757 if (xstate_bv & ~kvm_supported_xcr0() ||
3758 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3759 return -EINVAL;
df1daba7 3760 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3761 } else {
a575813b
WL		 3762 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3763 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3764 return -EINVAL;
b666a4b6 3765 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3766 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3767 }
3768 return 0;
3769}
3770
3771static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3772 struct kvm_xcrs *guest_xcrs)
3773{
d366bf7e 3774 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3775 guest_xcrs->nr_xcrs = 0;
3776 return;
3777 }
3778
3779 guest_xcrs->nr_xcrs = 1;
3780 guest_xcrs->flags = 0;
3781 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3782 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3783}
3784
3785static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3786 struct kvm_xcrs *guest_xcrs)
3787{
3788 int i, r = 0;
3789
d366bf7e 3790 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3791 return -EINVAL;
3792
3793 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3794 return -EINVAL;
3795
3796 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3797 /* Only support XCR0 currently */
c67a04cb 3798 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3799 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3800 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3801 break;
3802 }
3803 if (r)
3804 r = -EINVAL;
3805 return r;
3806}
3807
1c0b28c2
EM		 3808/*
3809 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3810 * stopped by the hypervisor. This function will be called from the host only.
3811 * EINVAL is returned when the host attempts to set the flag for a guest that
3812 * does not support pv clocks.
3813 */
3814static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3815{
0b79459b 3816 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3817 return -EINVAL;
51d59c6b 3818 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3819 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3820 return 0;
3821}
3822
5c919412
AS		 3823static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3824 struct kvm_enable_cap *cap)
3825{
57b119da
VK		 3826 int r;
3827 uint16_t vmcs_version;
3828 void __user *user_ptr;
3829
5c919412
AS		 3830 if (cap->flags)
3831 return -EINVAL;
3832
3833 switch (cap->cap) {
efc479e6
RK		 3834 case KVM_CAP_HYPERV_SYNIC2:
3835 if (cap->args[0])
3836 return -EINVAL;
b2869f28
GS		 3837 /* fall through */
3838
5c919412 3839 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3840 if (!irqchip_in_kernel(vcpu->kvm))
3841 return -EINVAL;
efc479e6
RK		 3842 return kvm_hv_activate_synic(vcpu, cap->cap ==
3843 KVM_CAP_HYPERV_SYNIC2);
57b119da 3844 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 3845 if (!kvm_x86_ops->nested_enable_evmcs)
3846 return -ENOTTY;
57b119da
VK		 3847 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
3848 if (!r) {
3849 user_ptr = (void __user *)(uintptr_t)cap->args[0];
3850 if (copy_to_user(user_ptr, &vmcs_version,
3851 sizeof(vmcs_version)))
3852 r = -EFAULT;
3853 }
3854 return r;
3855
5c919412
AS		 3856 default:
3857 return -EINVAL;
3858 }
3859}
3860
313a3dc7
CO		 3861long kvm_arch_vcpu_ioctl(struct file *filp,
3862 unsigned int ioctl, unsigned long arg)
3863{
3864 struct kvm_vcpu *vcpu = filp->private_data;
3865 void __user *argp = (void __user *)arg;
3866 int r;
d1ac91d8
AK		 3867 union {
3868 struct kvm_lapic_state *lapic;
3869 struct kvm_xsave *xsave;
3870 struct kvm_xcrs *xcrs;
3871 void *buffer;
3872 } u;
3873
9b062471
CD		 3874 vcpu_load(vcpu);
3875
d1ac91d8 3876 u.buffer = NULL;
313a3dc7
CO		 3877 switch (ioctl) {
3878 case KVM_GET_LAPIC: {
2204ae3c 3879 r = -EINVAL;
bce87cce 3880 if (!lapic_in_kernel(vcpu))
2204ae3c 3881 goto out;
d1ac91d8 3882 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3883
b772ff36 3884 r = -ENOMEM;
d1ac91d8 3885 if (!u.lapic)
b772ff36 3886 goto out;
d1ac91d8 3887 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3888 if (r)
3889 goto out;
3890 r = -EFAULT;
d1ac91d8 3891 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3892 goto out;
3893 r = 0;
3894 break;
3895 }
3896 case KVM_SET_LAPIC: {
2204ae3c 3897 r = -EINVAL;
bce87cce 3898 if (!lapic_in_kernel(vcpu))
2204ae3c 3899 goto out;
ff5c2c03 3900 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3901 if (IS_ERR(u.lapic)) {
3902 r = PTR_ERR(u.lapic);
3903 goto out_nofree;
3904 }
ff5c2c03 3905
d1ac91d8 3906 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3907 break;
3908 }
f77bc6a4
ZX		 3909 case KVM_INTERRUPT: {
3910 struct kvm_interrupt irq;
3911
3912 r = -EFAULT;
0e96f31e 3913 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 3914 goto out;
3915 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3916 break;
3917 }
c4abb7c9
JK		 3918 case KVM_NMI: {
3919 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3920 break;
3921 }
f077825a
PB		 3922 case KVM_SMI: {
3923 r = kvm_vcpu_ioctl_smi(vcpu);
3924 break;
3925 }
313a3dc7
CO		 3926 case KVM_SET_CPUID: {
3927 struct kvm_cpuid __user *cpuid_arg = argp;
3928 struct kvm_cpuid cpuid;
3929
3930 r = -EFAULT;
0e96f31e 3931 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 3932 goto out;
3933 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3934 break;
3935 }
07716717
DK		 3936 case KVM_SET_CPUID2: {
3937 struct kvm_cpuid2 __user *cpuid_arg = argp;
3938 struct kvm_cpuid2 cpuid;
3939
3940 r = -EFAULT;
0e96f31e 3941 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 3942 goto out;
3943 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3944 cpuid_arg->entries);
07716717
DK		 3945 break;
3946 }
3947 case KVM_GET_CPUID2: {
3948 struct kvm_cpuid2 __user *cpuid_arg = argp;
3949 struct kvm_cpuid2 cpuid;
3950
3951 r = -EFAULT;
0e96f31e 3952 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 3953 goto out;
3954 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3955 cpuid_arg->entries);
07716717
DK		 3956 if (r)
3957 goto out;
3958 r = -EFAULT;
0e96f31e 3959 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 3960 goto out;
3961 r = 0;
3962 break;
3963 }
801e459a
TL		 3964 case KVM_GET_MSRS: {
3965 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3966 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3967 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3968 break;
801e459a
TL		 3969 }
3970 case KVM_SET_MSRS: {
3971 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3972 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3973 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3974 break;
801e459a 3975 }
b209749f
AK		 3976 case KVM_TPR_ACCESS_REPORTING: {
3977 struct kvm_tpr_access_ctl tac;
3978
3979 r = -EFAULT;
0e96f31e 3980 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 3981 goto out;
3982 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3983 if (r)
3984 goto out;
3985 r = -EFAULT;
0e96f31e 3986 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 3987 goto out;
3988 r = 0;
3989 break;
3990 };
b93463aa
AK		 3991 case KVM_SET_VAPIC_ADDR: {
3992 struct kvm_vapic_addr va;
7301d6ab 3993 int idx;
b93463aa
AK		 3994
3995 r = -EINVAL;
35754c98 3996 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3997 goto out;
3998 r = -EFAULT;
0e96f31e 3999 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 4000 goto out;
7301d6ab 4001 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 4002 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 4003 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4004 break;
4005 }
890ca9ae
HY		 4006 case KVM_X86_SETUP_MCE: {
4007 u64 mcg_cap;
4008
4009 r = -EFAULT;
0e96f31e 4010 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4011 goto out;
4012 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4013 break;
4014 }
4015 case KVM_X86_SET_MCE: {
4016 struct kvm_x86_mce mce;
4017
4018 r = -EFAULT;
0e96f31e 4019 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4020 goto out;
4021 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4022 break;
4023 }
3cfc3092
JK		 4024 case KVM_GET_VCPU_EVENTS: {
4025 struct kvm_vcpu_events events;
4026
4027 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4028
4029 r = -EFAULT;
4030 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4031 break;
4032 r = 0;
4033 break;
4034 }
4035 case KVM_SET_VCPU_EVENTS: {
4036 struct kvm_vcpu_events events;
4037
4038 r = -EFAULT;
4039 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4040 break;
4041
4042 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4043 break;
4044 }
a1efbe77
JK		 4045 case KVM_GET_DEBUGREGS: {
4046 struct kvm_debugregs dbgregs;
4047
4048 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4049
4050 r = -EFAULT;
4051 if (copy_to_user(argp, &dbgregs,
4052 sizeof(struct kvm_debugregs)))
4053 break;
4054 r = 0;
4055 break;
4056 }
4057 case KVM_SET_DEBUGREGS: {
4058 struct kvm_debugregs dbgregs;
4059
4060 r = -EFAULT;
4061 if (copy_from_user(&dbgregs, argp,
4062 sizeof(struct kvm_debugregs)))
4063 break;
4064
4065 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4066 break;
4067 }
2d5b5a66 4068 case KVM_GET_XSAVE: {
d1ac91d8 4069 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 4070 r = -ENOMEM;
d1ac91d8 4071 if (!u.xsave)
2d5b5a66
SY		 4072 break;
4073
d1ac91d8 4074 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4075
4076 r = -EFAULT;
d1ac91d8 4077 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4078 break;
4079 r = 0;
4080 break;
4081 }
4082 case KVM_SET_XSAVE: {
ff5c2c03 4083 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4084 if (IS_ERR(u.xsave)) {
4085 r = PTR_ERR(u.xsave);
4086 goto out_nofree;
4087 }
2d5b5a66 4088
d1ac91d8 4089 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4090 break;
4091 }
4092 case KVM_GET_XCRS: {
d1ac91d8 4093 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 4094 r = -ENOMEM;
d1ac91d8 4095 if (!u.xcrs)
2d5b5a66
SY		 4096 break;
4097
d1ac91d8 4098 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4099
4100 r = -EFAULT;
d1ac91d8 4101 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4102 sizeof(struct kvm_xcrs)))
4103 break;
4104 r = 0;
4105 break;
4106 }
4107 case KVM_SET_XCRS: {
ff5c2c03 4108 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4109 if (IS_ERR(u.xcrs)) {
4110 r = PTR_ERR(u.xcrs);
4111 goto out_nofree;
4112 }
2d5b5a66 4113
d1ac91d8 4114 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4115 break;
4116 }
92a1f12d
JR		 4117 case KVM_SET_TSC_KHZ: {
4118 u32 user_tsc_khz;
4119
4120 r = -EINVAL;
92a1f12d
JR		 4121 user_tsc_khz = (u32)arg;
4122
4123 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4124 goto out;
4125
cc578287
ZA		 4126 if (user_tsc_khz == 0)
4127 user_tsc_khz = tsc_khz;
4128
381d585c
HZ		 4129 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4130 r = 0;
92a1f12d 4131
92a1f12d
JR		 4132 goto out;
4133 }
4134 case KVM_GET_TSC_KHZ: {
cc578287 4135 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4136 goto out;
4137 }
1c0b28c2
EM		 4138 case KVM_KVMCLOCK_CTRL: {
4139 r = kvm_set_guest_paused(vcpu);
4140 goto out;
4141 }
5c919412
AS		 4142 case KVM_ENABLE_CAP: {
4143 struct kvm_enable_cap cap;
4144
4145 r = -EFAULT;
4146 if (copy_from_user(&cap, argp, sizeof(cap)))
4147 goto out;
4148 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4149 break;
4150 }
8fcc4b59
JM		 4151 case KVM_GET_NESTED_STATE: {
4152 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4153 u32 user_data_size;
4154
4155 r = -EINVAL;
4156 if (!kvm_x86_ops->get_nested_state)
4157 break;
4158
4159 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4160 r = -EFAULT;
8fcc4b59 4161 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4162 break;
8fcc4b59
JM		 4163
4164 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4165 user_data_size);
4166 if (r < 0)
26b471c7 4167 break;
8fcc4b59
JM		 4168
4169 if (r > user_data_size) {
4170 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4171 r = -EFAULT;
4172 else
4173 r = -E2BIG;
4174 break;
8fcc4b59 4175 }
26b471c7 4176
8fcc4b59
JM		 4177 r = 0;
4178 break;
4179 }
4180 case KVM_SET_NESTED_STATE: {
4181 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4182 struct kvm_nested_state kvm_state;
4183
4184 r = -EINVAL;
4185 if (!kvm_x86_ops->set_nested_state)
4186 break;
4187
26b471c7 4188 r = -EFAULT;
8fcc4b59 4189 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4190 break;
8fcc4b59 4191
26b471c7 4192 r = -EINVAL;
8fcc4b59 4193 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4194 break;
8fcc4b59
JM		 4195
4196 if (kvm_state.flags &
8cab6507
VK		 4197 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4198 | KVM_STATE_NESTED_EVMCS))
26b471c7 4199 break;
8fcc4b59
JM		 4200
4201 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4202 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4203 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4204 break;
8fcc4b59
JM		 4205
4206 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4207 break;
4208 }
2bc39970
VK		 4209 case KVM_GET_SUPPORTED_HV_CPUID: {
4210 struct kvm_cpuid2 __user *cpuid_arg = argp;
4211 struct kvm_cpuid2 cpuid;
4212
4213 r = -EFAULT;
4214 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4215 goto out;
4216
4217 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4218 cpuid_arg->entries);
4219 if (r)
4220 goto out;
4221
4222 r = -EFAULT;
4223 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4224 goto out;
4225 r = 0;
4226 break;
4227 }
313a3dc7
CO		 4228 default:
4229 r = -EINVAL;
4230 }
4231out:
d1ac91d8 4232 kfree(u.buffer);
9b062471
CD		 4233out_nofree:
4234 vcpu_put(vcpu);
313a3dc7
CO		 4235 return r;
4236}
4237
1499fa80 4238vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4239{
4240 return VM_FAULT_SIGBUS;
4241}
4242
1fe779f8
CO		 4243static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4244{
4245 int ret;
4246
4247 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4248 return -EINVAL;
1fe779f8
CO		 4249 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4250 return ret;
4251}
4252
b927a3ce
SY		 4253static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4254 u64 ident_addr)
4255{
2ac52ab8 4256 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4257}
4258
1fe779f8
CO		 4259static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4260 u32 kvm_nr_mmu_pages)
4261{
4262 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4263 return -EINVAL;
4264
79fac95e 4265 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4266
4267 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4268 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4269
79fac95e 4270 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4271 return 0;
4272}
4273
4274static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4275{
39de71ec 4276 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4277}
4278
1fe779f8
CO		 4279static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4280{
90bca052 4281 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4282 int r;
4283
4284 r = 0;
4285 switch (chip->chip_id) {
4286 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4287 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4288 sizeof(struct kvm_pic_state));
4289 break;
4290 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4291 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4292 sizeof(struct kvm_pic_state));
4293 break;
4294 case KVM_IRQCHIP_IOAPIC:
33392b49 4295 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4296 break;
4297 default:
4298 r = -EINVAL;
4299 break;
4300 }
4301 return r;
4302}
4303
4304static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4305{
90bca052 4306 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4307 int r;
4308
4309 r = 0;
4310 switch (chip->chip_id) {
4311 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4312 spin_lock(&pic->lock);
4313 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4314 sizeof(struct kvm_pic_state));
90bca052 4315 spin_unlock(&pic->lock);
1fe779f8
CO		 4316 break;
4317 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4318 spin_lock(&pic->lock);
4319 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4320 sizeof(struct kvm_pic_state));
90bca052 4321 spin_unlock(&pic->lock);
1fe779f8
CO		 4322 break;
4323 case KVM_IRQCHIP_IOAPIC:
33392b49 4324 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4325 break;
4326 default:
4327 r = -EINVAL;
4328 break;
4329 }
90bca052 4330 kvm_pic_update_irq(pic);
1fe779f8
CO		 4331 return r;
4332}
4333
e0f63cb9
SY		 4334static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4335{
34f3941c
RK		 4336 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4337
4338 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4339
4340 mutex_lock(&kps->lock);
4341 memcpy(ps, &kps->channels, sizeof(*ps));
4342 mutex_unlock(&kps->lock);
2da29bcc 4343 return 0;
e0f63cb9
SY		 4344}
4345
4346static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4347{
0185604c 4348 int i;
09edea72
RK		 4349 struct kvm_pit *pit = kvm->arch.vpit;
4350
4351 mutex_lock(&pit->pit_state.lock);
34f3941c 4352 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4353 for (i = 0; i < 3; i++)
09edea72
RK		 4354 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4355 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4356 return 0;
e9f42757
BK		 4357}
4358
4359static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4360{
e9f42757
BK		 4361 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4362 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4363 sizeof(ps->channels));
4364 ps->flags = kvm->arch.vpit->pit_state.flags;
4365 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4366 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4367 return 0;
e9f42757
BK		 4368}
4369
4370static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4371{
2da29bcc 4372 int start = 0;
0185604c 4373 int i;
e9f42757 4374 u32 prev_legacy, cur_legacy;
09edea72
RK		 4375 struct kvm_pit *pit = kvm->arch.vpit;
4376
4377 mutex_lock(&pit->pit_state.lock);
4378 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4379 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4380 if (!prev_legacy && cur_legacy)
4381 start = 1;
09edea72
RK		 4382 memcpy(&pit->pit_state.channels, &ps->channels,
4383 sizeof(pit->pit_state.channels));
4384 pit->pit_state.flags = ps->flags;
0185604c 4385 for (i = 0; i < 3; i++)
09edea72 4386 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4387 start && i == 0);
09edea72 4388 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4389 return 0;
e0f63cb9
SY		 4390}
4391
52d939a0
MT		 4392static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4393 struct kvm_reinject_control *control)
4394{
71474e2f
RK		 4395 struct kvm_pit *pit = kvm->arch.vpit;
4396
4397 if (!pit)
52d939a0 4398 return -ENXIO;
b39c90b6 4399
71474e2f
RK		 4400 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4401 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4402 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4403 */
4404 mutex_lock(&pit->pit_state.lock);
4405 kvm_pit_set_reinject(pit, control->pit_reinject);
4406 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4407
52d939a0
MT		 4408 return 0;
4409}
4410
95d4c16c 4411/**
60c34612
TY		 4412 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4413 * @kvm: kvm instance
4414 * @log: slot id and address to which we copy the log
95d4c16c 4415 *
e108ff2f
PB		 4416 * Steps 1-4 below provide general overview of dirty page logging. See
4417 * kvm_get_dirty_log_protect() function description for additional details.
4418 *
4419 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4420 * always flush the TLB (step 4) even if previous step failed and the dirty
4421 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4422 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4423 * writes will be marked dirty for next log read.
95d4c16c 4424 *
60c34612
TY		 4425 * 1. Take a snapshot of the bit and clear it if needed.
4426 * 2. Write protect the corresponding page.
e108ff2f
PB		 4427 * 3. Copy the snapshot to the userspace.
4428 * 4. Flush TLB's if needed.
5bb064dc 4429 */
60c34612 4430int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4431{
8fe65a82 4432 bool flush = false;
e108ff2f 4433 int r;
5bb064dc 4434
79fac95e 4435 mutex_lock(&kvm->slots_lock);
5bb064dc 4436
88178fd4
KH		 4437 /*
4438 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4439 */
4440 if (kvm_x86_ops->flush_log_dirty)
4441 kvm_x86_ops->flush_log_dirty(kvm);
4442
8fe65a82 4443 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4444
4445 /*
4446 * All the TLBs can be flushed out of mmu lock, see the comments in
4447 * kvm_mmu_slot_remove_write_access().
4448 */
e108ff2f 4449 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4450 if (flush)
2a31b9db
PB		 4451 kvm_flush_remote_tlbs(kvm);
4452
4453 mutex_unlock(&kvm->slots_lock);
4454 return r;
4455}
4456
4457int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4458{
4459 bool flush = false;
4460 int r;
4461
4462 mutex_lock(&kvm->slots_lock);
4463
4464 /*
4465 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4466 */
4467 if (kvm_x86_ops->flush_log_dirty)
4468 kvm_x86_ops->flush_log_dirty(kvm);
4469
4470 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4471
4472 /*
4473 * All the TLBs can be flushed out of mmu lock, see the comments in
4474 * kvm_mmu_slot_remove_write_access().
4475 */
4476 lockdep_assert_held(&kvm->slots_lock);
4477 if (flush)
198c74f4
XG		 4478 kvm_flush_remote_tlbs(kvm);
4479
79fac95e 4480 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4481 return r;
4482}
4483
aa2fbe6d
YZ		 4484int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4485 bool line_status)
23d43cf9
CD		 4486{
4487 if (!irqchip_in_kernel(kvm))
4488 return -ENXIO;
4489
4490 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4491 irq_event->irq, irq_event->level,
4492 line_status);
23d43cf9
CD		 4493 return 0;
4494}
4495
e5d83c74
PB		 4496int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4497 struct kvm_enable_cap *cap)
90de4a18
NA		 4498{
4499 int r;
4500
4501 if (cap->flags)
4502 return -EINVAL;
4503
4504 switch (cap->cap) {
4505 case KVM_CAP_DISABLE_QUIRKS:
4506 kvm->arch.disabled_quirks = cap->args[0];
4507 r = 0;
4508 break;
49df6397
SR		 4509 case KVM_CAP_SPLIT_IRQCHIP: {
4510 mutex_lock(&kvm->lock);
b053b2ae
SR		 4511 r = -EINVAL;
4512 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4513 goto split_irqchip_unlock;
49df6397
SR		 4514 r = -EEXIST;
4515 if (irqchip_in_kernel(kvm))
4516 goto split_irqchip_unlock;
557abc40 4517 if (kvm->created_vcpus)
49df6397
SR		 4518 goto split_irqchip_unlock;
4519 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4520 if (r)
49df6397
SR		 4521 goto split_irqchip_unlock;
4522 /* Pairs with irqchip_in_kernel. */
4523 smp_wmb();
49776faf 4524 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4525 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4526 r = 0;
4527split_irqchip_unlock:
4528 mutex_unlock(&kvm->lock);
4529 break;
4530 }
37131313
RK		 4531 case KVM_CAP_X2APIC_API:
4532 r = -EINVAL;
4533 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4534 break;
4535
4536 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4537 kvm->arch.x2apic_format = true;
c519265f
RK		 4538 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4539 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4540
4541 r = 0;
4542 break;
4d5422ce
WL		 4543 case KVM_CAP_X86_DISABLE_EXITS:
4544 r = -EINVAL;
4545 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4546 break;
4547
4548 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4549 kvm_can_mwait_in_guest())
4550 kvm->arch.mwait_in_guest = true;
766d3571 4551 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4552 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4553 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4554 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4555 r = 0;
4556 break;
6fbbde9a
DS		 4557 case KVM_CAP_MSR_PLATFORM_INFO:
4558 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4559 r = 0;
c4f55198
JM		 4560 break;
4561 case KVM_CAP_EXCEPTION_PAYLOAD:
4562 kvm->arch.exception_payload_enabled = cap->args[0];
4563 r = 0;
6fbbde9a 4564 break;
90de4a18
NA		 4565 default:
4566 r = -EINVAL;
4567 break;
4568 }
4569 return r;
4570}
4571
1fe779f8
CO		 4572long kvm_arch_vm_ioctl(struct file *filp,
4573 unsigned int ioctl, unsigned long arg)
4574{
4575 struct kvm *kvm = filp->private_data;
4576 void __user *argp = (void __user *)arg;
367e1319 4577 int r = -ENOTTY;
f0d66275
DH		 4578 /*
4579 * This union makes it completely explicit to gcc-3.x
4580 * that these two variables' stack usage should be
4581 * combined, not added together.
4582 */
4583 union {
4584 struct kvm_pit_state ps;
e9f42757 4585 struct kvm_pit_state2 ps2;
c5ff41ce 4586 struct kvm_pit_config pit_config;
f0d66275 4587 } u;
1fe779f8
CO		 4588
4589 switch (ioctl) {
4590 case KVM_SET_TSS_ADDR:
4591 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4592 break;
b927a3ce
SY		 4593 case KVM_SET_IDENTITY_MAP_ADDR: {
4594 u64 ident_addr;
4595
1af1ac91
DH		 4596 mutex_lock(&kvm->lock);
4597 r = -EINVAL;
4598 if (kvm->created_vcpus)
4599 goto set_identity_unlock;
b927a3ce 4600 r = -EFAULT;
0e96f31e 4601 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4602 goto set_identity_unlock;
b927a3ce 4603 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4604set_identity_unlock:
4605 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4606 break;
4607 }
1fe779f8
CO		 4608 case KVM_SET_NR_MMU_PAGES:
4609 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4610 break;
4611 case KVM_GET_NR_MMU_PAGES:
4612 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4613 break;
3ddea128 4614 case KVM_CREATE_IRQCHIP: {
3ddea128 4615 mutex_lock(&kvm->lock);
09941366 4616
3ddea128 4617 r = -EEXIST;
35e6eaa3 4618 if (irqchip_in_kernel(kvm))
3ddea128 4619 goto create_irqchip_unlock;
09941366 4620
3e515705 4621 r = -EINVAL;
557abc40 4622 if (kvm->created_vcpus)
3e515705 4623 goto create_irqchip_unlock;
09941366
RK		 4624
4625 r = kvm_pic_init(kvm);
4626 if (r)
3ddea128 4627 goto create_irqchip_unlock;
09941366
RK		 4628
4629 r = kvm_ioapic_init(kvm);
4630 if (r) {
09941366 4631 kvm_pic_destroy(kvm);
3ddea128 4632 goto create_irqchip_unlock;
09941366
RK		 4633 }
4634
399ec807
AK		 4635 r = kvm_setup_default_irq_routing(kvm);
4636 if (r) {
72bb2fcd 4637 kvm_ioapic_destroy(kvm);
09941366 4638 kvm_pic_destroy(kvm);
71ba994c 4639 goto create_irqchip_unlock;
399ec807 4640 }
49776faf 4641 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4642 smp_wmb();
49776faf 4643 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4644 create_irqchip_unlock:
4645 mutex_unlock(&kvm->lock);
1fe779f8 4646 break;
3ddea128 4647 }
7837699f 4648 case KVM_CREATE_PIT:
c5ff41ce
JK		 4649 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4650 goto create_pit;
4651 case KVM_CREATE_PIT2:
4652 r = -EFAULT;
4653 if (copy_from_user(&u.pit_config, argp,
4654 sizeof(struct kvm_pit_config)))
4655 goto out;
4656 create_pit:
250715a6 4657 mutex_lock(&kvm->lock);
269e05e4
AK		 4658 r = -EEXIST;
4659 if (kvm->arch.vpit)
4660 goto create_pit_unlock;
7837699f 4661 r = -ENOMEM;
c5ff41ce 4662 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4663 if (kvm->arch.vpit)
4664 r = 0;
269e05e4 4665 create_pit_unlock:
250715a6 4666 mutex_unlock(&kvm->lock);
7837699f 4667 break;
1fe779f8
CO		 4668 case KVM_GET_IRQCHIP: {
4669 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4670 struct kvm_irqchip *chip;
1fe779f8 4671
ff5c2c03
SL		 4672 chip = memdup_user(argp, sizeof(*chip));
4673 if (IS_ERR(chip)) {
4674 r = PTR_ERR(chip);
1fe779f8 4675 goto out;
ff5c2c03
SL		 4676 }
4677
1fe779f8 4678 r = -ENXIO;
826da321 4679 if (!irqchip_kernel(kvm))
f0d66275
DH		 4680 goto get_irqchip_out;
4681 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4682 if (r)
f0d66275 4683 goto get_irqchip_out;
1fe779f8 4684 r = -EFAULT;
0e96f31e 4685 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 4686 goto get_irqchip_out;
1fe779f8 4687 r = 0;
f0d66275
DH		 4688 get_irqchip_out:
4689 kfree(chip);
1fe779f8
CO		 4690 break;
4691 }
4692 case KVM_SET_IRQCHIP: {
4693 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4694 struct kvm_irqchip *chip;
1fe779f8 4695
ff5c2c03
SL		 4696 chip = memdup_user(argp, sizeof(*chip));
4697 if (IS_ERR(chip)) {
4698 r = PTR_ERR(chip);
1fe779f8 4699 goto out;
ff5c2c03
SL		 4700 }
4701
1fe779f8 4702 r = -ENXIO;
826da321 4703 if (!irqchip_kernel(kvm))
f0d66275
DH		 4704 goto set_irqchip_out;
4705 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4706 if (r)
f0d66275 4707 goto set_irqchip_out;
1fe779f8 4708 r = 0;
f0d66275
DH		 4709 set_irqchip_out:
4710 kfree(chip);
1fe779f8
CO		 4711 break;
4712 }
e0f63cb9 4713 case KVM_GET_PIT: {
e0f63cb9 4714 r = -EFAULT;
f0d66275 4715 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4716 goto out;
4717 r = -ENXIO;
4718 if (!kvm->arch.vpit)
4719 goto out;
f0d66275 4720 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4721 if (r)
4722 goto out;
4723 r = -EFAULT;
f0d66275 4724 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4725 goto out;
4726 r = 0;
4727 break;
4728 }
4729 case KVM_SET_PIT: {
e0f63cb9 4730 r = -EFAULT;
0e96f31e 4731 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 4732 goto out;
4733 r = -ENXIO;
4734 if (!kvm->arch.vpit)
4735 goto out;
f0d66275 4736 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4737 break;
4738 }
e9f42757
BK		 4739 case KVM_GET_PIT2: {
4740 r = -ENXIO;
4741 if (!kvm->arch.vpit)
4742 goto out;
4743 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4744 if (r)
4745 goto out;
4746 r = -EFAULT;
4747 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4748 goto out;
4749 r = 0;
4750 break;
4751 }
4752 case KVM_SET_PIT2: {
4753 r = -EFAULT;
4754 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4755 goto out;
4756 r = -ENXIO;
4757 if (!kvm->arch.vpit)
4758 goto out;
4759 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4760 break;
4761 }
52d939a0
MT		 4762 case KVM_REINJECT_CONTROL: {
4763 struct kvm_reinject_control control;
4764 r = -EFAULT;
4765 if (copy_from_user(&control, argp, sizeof(control)))
4766 goto out;
4767 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4768 break;
4769 }
d71ba788
PB		 4770 case KVM_SET_BOOT_CPU_ID:
4771 r = 0;
4772 mutex_lock(&kvm->lock);
557abc40 4773 if (kvm->created_vcpus)
d71ba788
PB		 4774 r = -EBUSY;
4775 else
4776 kvm->arch.bsp_vcpu_id = arg;
4777 mutex_unlock(&kvm->lock);
4778 break;
ffde22ac 4779 case KVM_XEN_HVM_CONFIG: {
51776043 4780 struct kvm_xen_hvm_config xhc;
ffde22ac 4781 r = -EFAULT;
51776043 4782 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4783 goto out;
4784 r = -EINVAL;
51776043 4785 if (xhc.flags)
ffde22ac 4786 goto out;
51776043 4787 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4788 r = 0;
4789 break;
4790 }
afbcf7ab 4791 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4792 struct kvm_clock_data user_ns;
4793 u64 now_ns;
afbcf7ab
GC		 4794
4795 r = -EFAULT;
4796 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4797 goto out;
4798
4799 r = -EINVAL;
4800 if (user_ns.flags)
4801 goto out;
4802
4803 r = 0;
0bc48bea
RK		 4804 /*
4805 * TODO: userspace has to take care of races with VCPU_RUN, so
4806 * kvm_gen_update_masterclock() can be cut down to locked
4807 * pvclock_update_vm_gtod_copy().
4808 */
4809 kvm_gen_update_masterclock(kvm);
e891a32e 4810 now_ns = get_kvmclock_ns(kvm);
108b249c 4811 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4812 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4813 break;
4814 }
4815 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4816 struct kvm_clock_data user_ns;
4817 u64 now_ns;
4818
e891a32e 4819 now_ns = get_kvmclock_ns(kvm);
108b249c 4820 user_ns.clock = now_ns;
e3fd9a93 4821 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4822 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4823
4824 r = -EFAULT;
4825 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4826 goto out;
4827 r = 0;
4828 break;
4829 }
5acc5c06
BS		 4830 case KVM_MEMORY_ENCRYPT_OP: {
4831 r = -ENOTTY;
4832 if (kvm_x86_ops->mem_enc_op)
4833 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4834 break;
4835 }
69eaedee
BS		 4836 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4837 struct kvm_enc_region region;
4838
4839 r = -EFAULT;
4840 if (copy_from_user(&region, argp, sizeof(region)))
4841 goto out;
4842
4843 r = -ENOTTY;
4844 if (kvm_x86_ops->mem_enc_reg_region)
4845 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4846 break;
4847 }
4848 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4849 struct kvm_enc_region region;
4850
4851 r = -EFAULT;
4852 if (copy_from_user(&region, argp, sizeof(region)))
4853 goto out;
4854
4855 r = -ENOTTY;
4856 if (kvm_x86_ops->mem_enc_unreg_region)
4857 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4858 break;
4859 }
faeb7833
RK		 4860 case KVM_HYPERV_EVENTFD: {
4861 struct kvm_hyperv_eventfd hvevfd;
4862
4863 r = -EFAULT;
4864 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4865 goto out;
4866 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4867 break;
4868 }
1fe779f8 4869 default:
ad6260da 4870 r = -ENOTTY;
1fe779f8
CO		 4871 }
4872out:
4873 return r;
4874}
4875
a16b043c 4876static void kvm_init_msr_list(void)
043405e1
CO		 4877{
4878 u32 dummy[2];
4879 unsigned i, j;
4880
62ef68bb 4881 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4882 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4883 continue;
93c4adc7
PB		 4884
4885 /*
4886 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4887 * to the guests in some cases.
93c4adc7
PB		 4888 */
4889 switch (msrs_to_save[i]) {
4890 case MSR_IA32_BNDCFGS:
503234b3 4891 if (!kvm_mpx_supported())
93c4adc7
PB		 4892 continue;
4893 break;
9dbe6cf9
PB		 4894 case MSR_TSC_AUX:
4895 if (!kvm_x86_ops->rdtscp_supported())
4896 continue;
4897 break;
bf8c55d8
CP		 4898 case MSR_IA32_RTIT_CTL:
4899 case MSR_IA32_RTIT_STATUS:
4900 if (!kvm_x86_ops->pt_supported())
4901 continue;
4902 break;
4903 case MSR_IA32_RTIT_CR3_MATCH:
4904 if (!kvm_x86_ops->pt_supported() ||
4905 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
4906 continue;
4907 break;
4908 case MSR_IA32_RTIT_OUTPUT_BASE:
4909 case MSR_IA32_RTIT_OUTPUT_MASK:
4910 if (!kvm_x86_ops->pt_supported() ||
4911 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
4912 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
4913 continue;
4914 break;
4915 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
4916 if (!kvm_x86_ops->pt_supported() ||
4917 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
4918 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
4919 continue;
4920 break;
4921 }
93c4adc7
PB		 4922 default:
4923 break;
4924 }
4925
043405e1
CO		 4926 if (j < i)
4927 msrs_to_save[j] = msrs_to_save[i];
4928 j++;
4929 }
4930 num_msrs_to_save = j;
62ef68bb
PB		 4931
4932 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4933 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4934 continue;
62ef68bb
PB		 4935
4936 if (j < i)
4937 emulated_msrs[j] = emulated_msrs[i];
4938 j++;
4939 }
4940 num_emulated_msrs = j;
801e459a
TL		 4941
4942 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4943 struct kvm_msr_entry msr;
4944
4945 msr.index = msr_based_features[i];
66421c1e 4946 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4947 continue;
4948
4949 if (j < i)
4950 msr_based_features[j] = msr_based_features[i];
4951 j++;
4952 }
4953 num_msr_based_features = j;
043405e1
CO		 4954}
4955
bda9020e
MT		 4956static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4957 const void *v)
bbd9b64e 4958{
70252a10
AK		 4959 int handled = 0;
4960 int n;
4961
4962 do {
4963 n = min(len, 8);
bce87cce 4964 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4965 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4966 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4967 break;
4968 handled += n;
4969 addr += n;
4970 len -= n;
4971 v += n;
4972 } while (len);
bbd9b64e 4973
70252a10 4974 return handled;
bbd9b64e
CO		 4975}
4976
bda9020e 4977static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4978{
70252a10
AK		 4979 int handled = 0;
4980 int n;
4981
4982 do {
4983 n = min(len, 8);
bce87cce 4984 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4985 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4986 addr, n, v))
4987 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4988 break;
e39d200f 4989 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4990 handled += n;
4991 addr += n;
4992 len -= n;
4993 v += n;
4994 } while (len);
bbd9b64e 4995
70252a10 4996 return handled;
bbd9b64e
CO		 4997}
4998
2dafc6c2
GN		 4999static void kvm_set_segment(struct kvm_vcpu *vcpu,
5000 struct kvm_segment *var, int seg)
5001{
5002 kvm_x86_ops->set_segment(vcpu, var, seg);
5003}
5004
5005void kvm_get_segment(struct kvm_vcpu *vcpu,
5006 struct kvm_segment *var, int seg)
5007{
5008 kvm_x86_ops->get_segment(vcpu, var, seg);
5009}
5010
54987b7a
PB		 5011gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5012 struct x86_exception *exception)
02f59dc9
JR		 5013{
5014 gpa_t t_gpa;
02f59dc9
JR		 5015
5016 BUG_ON(!mmu_is_nested(vcpu));
5017
5018 /* NPT walks are always user-walks */
5019 access |= PFERR_USER_MASK;
44dd3ffa 5020 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 5021
5022 return t_gpa;
5023}
5024
ab9ae313
AK		 5025gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5026 struct x86_exception *exception)
1871c602
GN		 5027{
5028 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 5029 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5030}
5031
ab9ae313
AK		 5032 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5033 struct x86_exception *exception)
1871c602
GN		 5034{
5035 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5036 access |= PFERR_FETCH_MASK;
ab9ae313 5037 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5038}
5039
ab9ae313
AK		 5040gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5041 struct x86_exception *exception)
1871c602
GN		 5042{
5043 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5044 access |= PFERR_WRITE_MASK;
ab9ae313 5045 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5046}
5047
5048/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5049gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5050 struct x86_exception *exception)
1871c602 5051{
ab9ae313 5052 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5053}
5054
5055static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5056 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5057 struct x86_exception *exception)
bbd9b64e
CO		 5058{
5059 void *data = val;
10589a46 5060 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5061
5062 while (bytes) {
14dfe855 5063 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5064 exception);
bbd9b64e 5065 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5066 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5067 int ret;
5068
bcc55cba 5069 if (gpa == UNMAPPED_GVA)
ab9ae313 5070 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5071 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5072 offset, toread);
10589a46 5073 if (ret < 0) {
c3cd7ffa 5074 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5075 goto out;
5076 }
bbd9b64e 5077
77c2002e
IE		 5078 bytes -= toread;
5079 data += toread;
5080 addr += toread;
bbd9b64e 5081 }
10589a46 5082out:
10589a46 5083 return r;
bbd9b64e 5084}
77c2002e 5085
1871c602 5086/* used for instruction fetching */
0f65dd70
AK		 5087static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5088 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5089 struct x86_exception *exception)
1871c602 5090{
0f65dd70 5091 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5092 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5093 unsigned offset;
5094 int ret;
0f65dd70 5095
44583cba
PB		 5096 /* Inline kvm_read_guest_virt_helper for speed. */
5097 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5098 exception);
5099 if (unlikely(gpa == UNMAPPED_GVA))
5100 return X86EMUL_PROPAGATE_FAULT;
5101
5102 offset = addr & (PAGE_SIZE-1);
5103 if (WARN_ON(offset + bytes > PAGE_SIZE))
5104 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5105 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5106 offset, bytes);
44583cba
PB		 5107 if (unlikely(ret < 0))
5108 return X86EMUL_IO_NEEDED;
5109
5110 return X86EMUL_CONTINUE;
1871c602
GN		 5111}
5112
ce14e868 5113int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5114 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5115 struct x86_exception *exception)
1871c602
GN		 5116{
5117 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5118
353c0956
PB		 5119 /*
5120 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5121 * is returned, but our callers are not ready for that and they blindly
5122 * call kvm_inject_page_fault. Ensure that they at least do not leak
5123 * uninitialized kernel stack memory into cr2 and error code.
5124 */
5125 memset(exception, 0, sizeof(*exception));
1871c602 5126 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5127 exception);
1871c602 5128}
064aea77 5129EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5130
ce14e868
PB		 5131static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5132 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5133 struct x86_exception *exception, bool system)
1871c602 5134{
0f65dd70 5135 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5136 u32 access = 0;
5137
5138 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5139 access |= PFERR_USER_MASK;
5140
5141 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5142}
5143
7a036a6f
RK		 5144static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5145 unsigned long addr, void *val, unsigned int bytes)
5146{
5147 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5148 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5149
5150 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5151}
5152
ce14e868
PB		 5153static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5154 struct kvm_vcpu *vcpu, u32 access,
5155 struct x86_exception *exception)
77c2002e
IE		 5156{
5157 void *data = val;
5158 int r = X86EMUL_CONTINUE;
5159
5160 while (bytes) {
14dfe855 5161 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5162 access,
ab9ae313 5163 exception);
77c2002e
IE		 5164 unsigned offset = addr & (PAGE_SIZE-1);
5165 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5166 int ret;
5167
bcc55cba 5168 if (gpa == UNMAPPED_GVA)
ab9ae313 5169 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5170 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5171 if (ret < 0) {
c3cd7ffa 5172 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5173 goto out;
5174 }
5175
5176 bytes -= towrite;
5177 data += towrite;
5178 addr += towrite;
5179 }
5180out:
5181 return r;
5182}
ce14e868
PB		 5183
5184static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5185 unsigned int bytes, struct x86_exception *exception,
5186 bool system)
ce14e868
PB		 5187{
5188 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5189 u32 access = PFERR_WRITE_MASK;
5190
5191 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5192 access |= PFERR_USER_MASK;
ce14e868
PB		 5193
5194 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5195 access, exception);
ce14e868
PB		 5196}
5197
5198int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5199 unsigned int bytes, struct x86_exception *exception)
5200{
c595ceee
PB		 5201 /* kvm_write_guest_virt_system can pull in tons of pages. */
5202 vcpu->arch.l1tf_flush_l1d = true;
5203
ce14e868
PB		 5204 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5205 PFERR_WRITE_MASK, exception);
5206}
6a4d7550 5207EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5208
082d06ed
WL		 5209int handle_ud(struct kvm_vcpu *vcpu)
5210{
6c86eedc 5211 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5212 enum emulation_result er;
6c86eedc
WL		 5213 char sig[5]; /* ud2; .ascii "kvm" */
5214 struct x86_exception e;
5215
5216 if (force_emulation_prefix &&
3c9fa24c
PB		 5217 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5218 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5219 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5220 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5221 emul_type = 0;
5222 }
082d06ed 5223
0ce97a2b 5224 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5225 if (er == EMULATE_USER_EXIT)
5226 return 0;
5227 if (er != EMULATE_DONE)
5228 kvm_queue_exception(vcpu, UD_VECTOR);
5229 return 1;
5230}
5231EXPORT_SYMBOL_GPL(handle_ud);
5232
0f89b207
TL		 5233static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5234 gpa_t gpa, bool write)
5235{
5236 /* For APIC access vmexit */
5237 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5238 return 1;
5239
5240 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5241 trace_vcpu_match_mmio(gva, gpa, write, true);
5242 return 1;
5243 }
5244
5245 return 0;
5246}
5247
af7cc7d1
XG		 5248static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5249 gpa_t *gpa, struct x86_exception *exception,
5250 bool write)
5251{
97d64b78
AK		 5252 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5253 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5254
be94f6b7
HH		 5255 /*
5256 * currently PKRU is only applied to ept enabled guest so
5257 * there is no pkey in EPT page table for L1 guest or EPT
5258 * shadow page table for L2 guest.
5259 */
97d64b78 5260 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5261 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5262 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5263 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5264 (gva & (PAGE_SIZE - 1));
4f022648 5265 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5266 return 1;
5267 }
5268
af7cc7d1
XG		 5269 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5270
5271 if (*gpa == UNMAPPED_GVA)
5272 return -1;
5273
0f89b207 5274 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5275}
5276
3200f405 5277int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5278 const void *val, int bytes)
bbd9b64e
CO		 5279{
5280 int ret;
5281
54bf36aa 5282 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5283 if (ret < 0)
bbd9b64e 5284 return 0;
0eb05bf2 5285 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5286 return 1;
5287}
5288
77d197b2
XG		 5289struct read_write_emulator_ops {
5290 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5291 int bytes);
5292 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5293 void *val, int bytes);
5294 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5295 int bytes, void *val);
5296 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5297 void *val, int bytes);
5298 bool write;
5299};
5300
5301static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5302{
5303 if (vcpu->mmio_read_completed) {
77d197b2 5304 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5305 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5306 vcpu->mmio_read_completed = 0;
5307 return 1;
5308 }
5309
5310 return 0;
5311}
5312
5313static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5314 void *val, int bytes)
5315{
54bf36aa 5316 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5317}
5318
5319static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5320 void *val, int bytes)
5321{
5322 return emulator_write_phys(vcpu, gpa, val, bytes);
5323}
5324
5325static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5326{
e39d200f 5327 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5328 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5329}
5330
5331static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5332 void *val, int bytes)
5333{
e39d200f 5334 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5335 return X86EMUL_IO_NEEDED;
5336}
5337
5338static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5339 void *val, int bytes)
5340{
f78146b0
AK		 5341 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5342
87da7e66 5343 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5344 return X86EMUL_CONTINUE;
5345}
5346
0fbe9b0b 5347static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5348 .read_write_prepare = read_prepare,
5349 .read_write_emulate = read_emulate,
5350 .read_write_mmio = vcpu_mmio_read,
5351 .read_write_exit_mmio = read_exit_mmio,
5352};
5353
0fbe9b0b 5354static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5355 .read_write_emulate = write_emulate,
5356 .read_write_mmio = write_mmio,
5357 .read_write_exit_mmio = write_exit_mmio,
5358 .write = true,
5359};
5360
22388a3c
XG		 5361static int emulator_read_write_onepage(unsigned long addr, void *val,
5362 unsigned int bytes,
5363 struct x86_exception *exception,
5364 struct kvm_vcpu *vcpu,
0fbe9b0b 5365 const struct read_write_emulator_ops *ops)
bbd9b64e 5366{
af7cc7d1
XG		 5367 gpa_t gpa;
5368 int handled, ret;
22388a3c 5369 bool write = ops->write;
f78146b0 5370 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5371 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5372
5373 /*
5374 * If the exit was due to a NPF we may already have a GPA.
5375 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5376 * Note, this cannot be used on string operations since string
5377 * operation using rep will only have the initial GPA from the NPF
5378 * occurred.
5379 */
5380 if (vcpu->arch.gpa_available &&
5381 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5382 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5383 gpa = vcpu->arch.gpa_val;
5384 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5385 } else {
5386 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5387 if (ret < 0)
5388 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5389 }
10589a46 5390
618232e2 5391 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5392 return X86EMUL_CONTINUE;
5393
bbd9b64e
CO		 5394 /*
5395 * Is this MMIO handled locally?
5396 */
22388a3c 5397 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5398 if (handled == bytes)
bbd9b64e 5399 return X86EMUL_CONTINUE;
bbd9b64e 5400
70252a10
AK		 5401 gpa += handled;
5402 bytes -= handled;
5403 val += handled;
5404
87da7e66
XG		 5405 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5406 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5407 frag->gpa = gpa;
5408 frag->data = val;
5409 frag->len = bytes;
f78146b0 5410 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5411}
5412
52eb5a6d
XL		 5413static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5414 unsigned long addr,
22388a3c
XG		 5415 void *val, unsigned int bytes,
5416 struct x86_exception *exception,
0fbe9b0b 5417 const struct read_write_emulator_ops *ops)
bbd9b64e 5418{
0f65dd70 5419 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5420 gpa_t gpa;
5421 int rc;
5422
5423 if (ops->read_write_prepare &&
5424 ops->read_write_prepare(vcpu, val, bytes))
5425 return X86EMUL_CONTINUE;
5426
5427 vcpu->mmio_nr_fragments = 0;
0f65dd70 5428
bbd9b64e
CO		 5429 /* Crossing a page boundary? */
5430 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5431 int now;
bbd9b64e
CO		 5432
5433 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5434 rc = emulator_read_write_onepage(addr, val, now, exception,
5435 vcpu, ops);
5436
bbd9b64e
CO		 5437 if (rc != X86EMUL_CONTINUE)
5438 return rc;
5439 addr += now;
bac15531
NA		 5440 if (ctxt->mode != X86EMUL_MODE_PROT64)
5441 addr = (u32)addr;
bbd9b64e
CO		 5442 val += now;
5443 bytes -= now;
5444 }
22388a3c 5445
f78146b0
AK		 5446 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5447 vcpu, ops);
5448 if (rc != X86EMUL_CONTINUE)
5449 return rc;
5450
5451 if (!vcpu->mmio_nr_fragments)
5452 return rc;
5453
5454 gpa = vcpu->mmio_fragments[0].gpa;
5455
5456 vcpu->mmio_needed = 1;
5457 vcpu->mmio_cur_fragment = 0;
5458
87da7e66 5459 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5460 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5461 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5462 vcpu->run->mmio.phys_addr = gpa;
5463
5464 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5465}
5466
5467static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5468 unsigned long addr,
5469 void *val,
5470 unsigned int bytes,
5471 struct x86_exception *exception)
5472{
5473 return emulator_read_write(ctxt, addr, val, bytes,
5474 exception, &read_emultor);
5475}
5476
52eb5a6d 5477static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5478 unsigned long addr,
5479 const void *val,
5480 unsigned int bytes,
5481 struct x86_exception *exception)
5482{
5483 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5484 exception, &write_emultor);
bbd9b64e 5485}
bbd9b64e 5486
daea3e73
AK		 5487#define CMPXCHG_TYPE(t, ptr, old, new) \
5488 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5489
5490#ifdef CONFIG_X86_64
5491# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5492#else
5493# define CMPXCHG64(ptr, old, new) \
9749a6c0 5494 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5495#endif
5496
0f65dd70
AK		 5497static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5498 unsigned long addr,
bbd9b64e
CO		 5499 const void *old,
5500 const void *new,
5501 unsigned int bytes,
0f65dd70 5502 struct x86_exception *exception)
bbd9b64e 5503{
0f65dd70 5504 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5505 gpa_t gpa;
5506 struct page *page;
5507 char *kaddr;
5508 bool exchanged;
2bacc55c 5509
daea3e73
AK		 5510 /* guests cmpxchg8b have to be emulated atomically */
5511 if (bytes > 8 || (bytes & (bytes - 1)))
5512 goto emul_write;
10589a46 5513
daea3e73 5514 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5515
daea3e73
AK		 5516 if (gpa == UNMAPPED_GVA ||
5517 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5518 goto emul_write;
2bacc55c 5519
daea3e73
AK		 5520 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5521 goto emul_write;
72dc67a6 5522
54bf36aa 5523 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5524 if (is_error_page(page))
c19b8bd6 5525 goto emul_write;
72dc67a6 5526
8fd75e12 5527 kaddr = kmap_atomic(page);
daea3e73
AK		 5528 kaddr += offset_in_page(gpa);
5529 switch (bytes) {
5530 case 1:
5531 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5532 break;
5533 case 2:
5534 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5535 break;
5536 case 4:
5537 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5538 break;
5539 case 8:
5540 exchanged = CMPXCHG64(kaddr, old, new);
5541 break;
5542 default:
5543 BUG();
2bacc55c 5544 }
8fd75e12 5545 kunmap_atomic(kaddr);
daea3e73
AK		 5546 kvm_release_page_dirty(page);
5547
5548 if (!exchanged)
5549 return X86EMUL_CMPXCHG_FAILED;
5550
54bf36aa 5551 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5552 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5553
5554 return X86EMUL_CONTINUE;
4a5f48f6 5555
3200f405 5556emul_write:
daea3e73 5557 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5558
0f65dd70 5559 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5560}
5561
cf8f70bf
GN		 5562static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5563{
cbfc6c91 5564 int r = 0, i;
cf8f70bf 5565
cbfc6c91
WL		 5566 for (i = 0; i < vcpu->arch.pio.count; i++) {
5567 if (vcpu->arch.pio.in)
5568 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5569 vcpu->arch.pio.size, pd);
5570 else
5571 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5572 vcpu->arch.pio.port, vcpu->arch.pio.size,
5573 pd);
5574 if (r)
5575 break;
5576 pd += vcpu->arch.pio.size;
5577 }
cf8f70bf
GN		 5578 return r;
5579}
5580
6f6fbe98
XG		 5581static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5582 unsigned short port, void *val,
5583 unsigned int count, bool in)
cf8f70bf 5584{
cf8f70bf 5585 vcpu->arch.pio.port = port;
6f6fbe98 5586 vcpu->arch.pio.in = in;
7972995b 5587 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5588 vcpu->arch.pio.size = size;
5589
5590 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5591 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5592 return 1;
5593 }
5594
5595 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5596 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5597 vcpu->run->io.size = size;
5598 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5599 vcpu->run->io.count = count;
5600 vcpu->run->io.port = port;
5601
5602 return 0;
5603}
5604
6f6fbe98
XG		 5605static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5606 int size, unsigned short port, void *val,
5607 unsigned int count)
cf8f70bf 5608{
ca1d4a9e 5609 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5610 int ret;
ca1d4a9e 5611
6f6fbe98
XG		 5612 if (vcpu->arch.pio.count)
5613 goto data_avail;
cf8f70bf 5614
cbfc6c91
WL		 5615 memset(vcpu->arch.pio_data, 0, size * count);
5616
6f6fbe98
XG		 5617 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5618 if (ret) {
5619data_avail:
5620 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5621 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5622 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5623 return 1;
5624 }
5625
cf8f70bf
GN		 5626 return 0;
5627}
5628
6f6fbe98
XG		 5629static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5630 int size, unsigned short port,
5631 const void *val, unsigned int count)
5632{
5633 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5634
5635 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5636 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5637 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5638}
5639
bbd9b64e
CO		 5640static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5641{
5642 return kvm_x86_ops->get_segment_base(vcpu, seg);
5643}
5644
3cb16fe7 5645static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5646{
3cb16fe7 5647 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5648}
5649
ae6a2375 5650static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5651{
5652 if (!need_emulate_wbinvd(vcpu))
5653 return X86EMUL_CONTINUE;
5654
5655 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5656 int cpu = get_cpu();
5657
5658 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5659 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5660 wbinvd_ipi, NULL, 1);
2eec7343 5661 put_cpu();
f5f48ee1 5662 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5663 } else
5664 wbinvd();
f5f48ee1
SY		 5665 return X86EMUL_CONTINUE;
5666}
5cb56059
JS		 5667
5668int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5669{
6affcbed
KH		 5670 kvm_emulate_wbinvd_noskip(vcpu);
5671 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5672}
f5f48ee1
SY		 5673EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5674
5cb56059
JS		 5675
5676
bcaf5cc5
AK		 5677static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5678{
5cb56059 5679 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5680}
5681
52eb5a6d
XL		 5682static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5683 unsigned long *dest)
bbd9b64e 5684{
16f8a6f9 5685 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5686}
5687
52eb5a6d
XL		 5688static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5689 unsigned long value)
bbd9b64e 5690{
338dbc97 5691
717746e3 5692 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5693}
5694
52a46617 5695static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5696{
52a46617 5697 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5698}
5699
717746e3 5700static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5701{
717746e3 5702 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5703 unsigned long value;
5704
5705 switch (cr) {
5706 case 0:
5707 value = kvm_read_cr0(vcpu);
5708 break;
5709 case 2:
5710 value = vcpu->arch.cr2;
5711 break;
5712 case 3:
9f8fe504 5713 value = kvm_read_cr3(vcpu);
52a46617
GN		 5714 break;
5715 case 4:
5716 value = kvm_read_cr4(vcpu);
5717 break;
5718 case 8:
5719 value = kvm_get_cr8(vcpu);
5720 break;
5721 default:
a737f256 5722 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5723 return 0;
5724 }
5725
5726 return value;
5727}
5728
717746e3 5729static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5730{
717746e3 5731 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5732 int res = 0;
5733
52a46617
GN		 5734 switch (cr) {
5735 case 0:
49a9b07e 5736 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5737 break;
5738 case 2:
5739 vcpu->arch.cr2 = val;
5740 break;
5741 case 3:
2390218b 5742 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5743 break;
5744 case 4:
a83b29c6 5745 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5746 break;
5747 case 8:
eea1cff9 5748 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5749 break;
5750 default:
a737f256 5751 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5752 res = -1;
52a46617 5753 }
0f12244f
GN		 5754
5755 return res;
52a46617
GN		 5756}
5757
717746e3 5758static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5759{
717746e3 5760 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5761}
5762
4bff1e86 5763static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5764{
4bff1e86 5765 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5766}
5767
4bff1e86 5768static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5769{
4bff1e86 5770 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5771}
5772
1ac9d0cf
AK		 5773static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5774{
5775 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5776}
5777
5778static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5779{
5780 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5781}
5782
4bff1e86
AK		 5783static unsigned long emulator_get_cached_segment_base(
5784 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5785{
4bff1e86 5786 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5787}
5788
1aa36616
AK		 5789static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5790 struct desc_struct *desc, u32 *base3,
5791 int seg)
2dafc6c2
GN		 5792{
5793 struct kvm_segment var;
5794
4bff1e86 5795 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5796 *selector = var.selector;
2dafc6c2 5797
378a8b09
GN		 5798 if (var.unusable) {
5799 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5800 if (base3)
5801 *base3 = 0;
2dafc6c2 5802 return false;
378a8b09 5803 }
2dafc6c2
GN		 5804
5805 if (var.g)
5806 var.limit >>= 12;
5807 set_desc_limit(desc, var.limit);
5808 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5809#ifdef CONFIG_X86_64
5810 if (base3)
5811 *base3 = var.base >> 32;
5812#endif
2dafc6c2
GN		 5813 desc->type = var.type;
5814 desc->s = var.s;
5815 desc->dpl = var.dpl;
5816 desc->p = var.present;
5817 desc->avl = var.avl;
5818 desc->l = var.l;
5819 desc->d = var.db;
5820 desc->g = var.g;
5821
5822 return true;
5823}
5824
1aa36616
AK		 5825static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5826 struct desc_struct *desc, u32 base3,
5827 int seg)
2dafc6c2 5828{
4bff1e86 5829 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5830 struct kvm_segment var;
5831
1aa36616 5832 var.selector = selector;
2dafc6c2 5833 var.base = get_desc_base(desc);
5601d05b
GN		 5834#ifdef CONFIG_X86_64
5835 var.base |= ((u64)base3) << 32;
5836#endif
2dafc6c2
GN		 5837 var.limit = get_desc_limit(desc);
5838 if (desc->g)
5839 var.limit = (var.limit << 12) | 0xfff;
5840 var.type = desc->type;
2dafc6c2
GN		 5841 var.dpl = desc->dpl;
5842 var.db = desc->d;
5843 var.s = desc->s;
5844 var.l = desc->l;
5845 var.g = desc->g;
5846 var.avl = desc->avl;
5847 var.present = desc->p;
5848 var.unusable = !var.present;
5849 var.padding = 0;
5850
5851 kvm_set_segment(vcpu, &var, seg);
5852 return;
5853}
5854
717746e3
AK		 5855static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5856 u32 msr_index, u64 *pdata)
5857{
609e36d3
PB		 5858 struct msr_data msr;
5859 int r;
5860
5861 msr.index = msr_index;
5862 msr.host_initiated = false;
5863 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5864 if (r)
5865 return r;
5866
5867 *pdata = msr.data;
5868 return 0;
717746e3
AK		 5869}
5870
5871static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5872 u32 msr_index, u64 data)
5873{
8fe8ab46
WA		 5874 struct msr_data msr;
5875
5876 msr.data = data;
5877 msr.index = msr_index;
5878 msr.host_initiated = false;
5879 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5880}
5881
64d60670
PB		 5882static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5883{
5884 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5885
5886 return vcpu->arch.smbase;
5887}
5888
5889static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5890{
5891 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5892
5893 vcpu->arch.smbase = smbase;
5894}
5895
67f4d428
NA		 5896static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5897 u32 pmc)
5898{
c6702c9d 5899 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5900}
5901
222d21aa
AK		 5902static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5903 u32 pmc, u64 *pdata)
5904{
c6702c9d 5905 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5906}
5907
6c3287f7
AK		 5908static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5909{
5910 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5911}
5912
2953538e 5913static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5914 struct x86_instruction_info *info,
c4f035c6
AK		 5915 enum x86_intercept_stage stage)
5916{
2953538e 5917 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5918}
5919
e911eb3b
YZ		 5920static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5921 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5922{
e911eb3b 5923 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5924}
5925
dd856efa
AK		 5926static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5927{
5928 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5929}
5930
5931static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5932{
5933 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5934}
5935
801806d9
NA		 5936static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5937{
5938 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5939}
5940
6ed071f0
LP		 5941static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5942{
5943 return emul_to_vcpu(ctxt)->arch.hflags;
5944}
5945
5946static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5947{
5948 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5949}
5950
0234bf88
LP		 5951static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5952{
5953 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5954}
5955
0225fb50 5956static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5957 .read_gpr = emulator_read_gpr,
5958 .write_gpr = emulator_write_gpr,
ce14e868
PB		 5959 .read_std = emulator_read_std,
5960 .write_std = emulator_write_std,
7a036a6f 5961 .read_phys = kvm_read_guest_phys_system,
1871c602 5962 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5963 .read_emulated = emulator_read_emulated,
5964 .write_emulated = emulator_write_emulated,
5965 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5966 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5967 .pio_in_emulated = emulator_pio_in_emulated,
5968 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5969 .get_segment = emulator_get_segment,
5970 .set_segment = emulator_set_segment,
5951c442 5971 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5972 .get_gdt = emulator_get_gdt,
160ce1f1 5973 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5974 .set_gdt = emulator_set_gdt,
5975 .set_idt = emulator_set_idt,
52a46617
GN		 5976 .get_cr = emulator_get_cr,
5977 .set_cr = emulator_set_cr,
9c537244 5978 .cpl = emulator_get_cpl,
35aa5375
GN		 5979 .get_dr = emulator_get_dr,
5980 .set_dr = emulator_set_dr,
64d60670
PB		 5981 .get_smbase = emulator_get_smbase,
5982 .set_smbase = emulator_set_smbase,
717746e3
AK		 5983 .set_msr = emulator_set_msr,
5984 .get_msr = emulator_get_msr,
67f4d428 5985 .check_pmc = emulator_check_pmc,
222d21aa 5986 .read_pmc = emulator_read_pmc,
6c3287f7 5987 .halt = emulator_halt,
bcaf5cc5 5988 .wbinvd = emulator_wbinvd,
d6aa1000 5989 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5990 .intercept = emulator_intercept,
bdb42f5a 5991 .get_cpuid = emulator_get_cpuid,
801806d9 5992 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5993 .get_hflags = emulator_get_hflags,
5994 .set_hflags = emulator_set_hflags,
0234bf88 5995 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5996};
5997
95cb2295
GN		 5998static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5999{
37ccdcbe 6000 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 6001 /*
6002 * an sti; sti; sequence only disable interrupts for the first
6003 * instruction. So, if the last instruction, be it emulated or
6004 * not, left the system with the INT_STI flag enabled, it
6005 * means that the last instruction is an sti. We should not
6006 * leave the flag on in this case. The same goes for mov ss
6007 */
37ccdcbe
PB		 6008 if (int_shadow & mask)
6009 mask = 0;
6addfc42 6010 if (unlikely(int_shadow || mask)) {
95cb2295 6011 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 6012 if (!mask)
6013 kvm_make_request(KVM_REQ_EVENT, vcpu);
6014 }
95cb2295
GN		 6015}
6016
ef54bcfe 6017static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 6018{
6019 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 6020 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 6021 return kvm_propagate_fault(vcpu, &ctxt->exception);
6022
6023 if (ctxt->exception.error_code_valid)
da9cb575
AK		 6024 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6025 ctxt->exception.error_code);
54b8486f 6026 else
da9cb575 6027 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 6028 return false;
54b8486f
GN		 6029}
6030
8ec4722d
MG		 6031static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6032{
adf52235 6033 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 6034 int cs_db, cs_l;
6035
8ec4722d
MG		 6036 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6037
adf52235 6038 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 6039 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6040
adf52235
TY		 6041 ctxt->eip = kvm_rip_read(vcpu);
6042 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6043 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6044 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6045 cs_db ? X86EMUL_MODE_PROT32 :
6046 X86EMUL_MODE_PROT16;
a584539b 6047 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6048 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6049 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6050
dd856efa 6051 init_decode_cache(ctxt);
7ae441ea 6052 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6053}
6054
71f9833b 6055int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6056{
9d74191a 6057 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6058 int ret;
6059
6060 init_emulate_ctxt(vcpu);
6061
9dac77fa
AK		 6062 ctxt->op_bytes = 2;
6063 ctxt->ad_bytes = 2;
6064 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6065 ret = emulate_int_real(ctxt, irq);
63995653
MG		 6066
6067 if (ret != X86EMUL_CONTINUE)
6068 return EMULATE_FAIL;
6069
9dac77fa 6070 ctxt->eip = ctxt->_eip;
9d74191a
TY		 6071 kvm_rip_write(vcpu, ctxt->eip);
6072 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 6073
63995653
MG		 6074 return EMULATE_DONE;
6075}
6076EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6077
e2366171 6078static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6079{
fc3a9157
JR		 6080 int r = EMULATE_DONE;
6081
6d77dbfc
GN		 6082 ++vcpu->stat.insn_emulation_fail;
6083 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 6084
6085 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6086 return EMULATE_FAIL;
6087
a2b9e6c1 6088 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6089 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6090 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6091 vcpu->run->internal.ndata = 0;
1f4dcb3b 6092 r = EMULATE_USER_EXIT;
fc3a9157 6093 }
e2366171 6094
6d77dbfc 6095 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 6096
6097 return r;
6d77dbfc
GN		 6098}
6099
93c05d3e 6100static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6101 bool write_fault_to_shadow_pgtable,
6102 int emulation_type)
a6f177ef 6103{
95b3cf69 6104 gpa_t gpa = cr2;
ba049e93 6105 kvm_pfn_t pfn;
a6f177ef 6106
384bf221 6107 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6108 return false;
6109
6c3dfeb6
SC		 6110 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6111 return false;
6112
44dd3ffa 6113 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6114 /*
6115 * Write permission should be allowed since only
6116 * write access need to be emulated.
6117 */
6118 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6119
95b3cf69
XG		 6120 /*
6121 * If the mapping is invalid in guest, let cpu retry
6122 * it to generate fault.
6123 */
6124 if (gpa == UNMAPPED_GVA)
6125 return true;
6126 }
a6f177ef 6127
8e3d9d06
XG		 6128 /*
6129 * Do not retry the unhandleable instruction if it faults on the
6130 * readonly host memory, otherwise it will goto a infinite loop:
6131 * retry instruction -> write #PF -> emulation fail -> retry
6132 * instruction -> ...
6133 */
6134 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6135
6136 /*
6137 * If the instruction failed on the error pfn, it can not be fixed,
6138 * report the error to userspace.
6139 */
6140 if (is_error_noslot_pfn(pfn))
6141 return false;
6142
6143 kvm_release_pfn_clean(pfn);
6144
6145 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6146 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6147 unsigned int indirect_shadow_pages;
6148
6149 spin_lock(&vcpu->kvm->mmu_lock);
6150 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6151 spin_unlock(&vcpu->kvm->mmu_lock);
6152
6153 if (indirect_shadow_pages)
6154 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6155
a6f177ef 6156 return true;
8e3d9d06 6157 }
a6f177ef 6158
95b3cf69
XG		 6159 /*
6160 * if emulation was due to access to shadowed page table
6161 * and it failed try to unshadow page and re-enter the
6162 * guest to let CPU execute the instruction.
6163 */
6164 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6165
6166 /*
6167 * If the access faults on its page table, it can not
6168 * be fixed by unprotecting shadow page and it should
6169 * be reported to userspace.
6170 */
6171 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6172}
6173
1cb3f3ae
XG		 6174static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6175 unsigned long cr2, int emulation_type)
6176{
6177 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6178 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6179
6180 last_retry_eip = vcpu->arch.last_retry_eip;
6181 last_retry_addr = vcpu->arch.last_retry_addr;
6182
6183 /*
6184 * If the emulation is caused by #PF and it is non-page_table
6185 * writing instruction, it means the VM-EXIT is caused by shadow
6186 * page protected, we can zap the shadow page and retry this
6187 * instruction directly.
6188 *
6189 * Note: if the guest uses a non-page-table modifying instruction
6190 * on the PDE that points to the instruction, then we will unmap
6191 * the instruction and go to an infinite loop. So, we cache the
6192 * last retried eip and the last fault address, if we meet the eip
6193 * and the address again, we can break out of the potential infinite
6194 * loop.
6195 */
6196 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6197
384bf221 6198 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6199 return false;
6200
6c3dfeb6
SC		 6201 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6202 return false;
6203
1cb3f3ae
XG		 6204 if (x86_page_table_writing_insn(ctxt))
6205 return false;
6206
6207 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6208 return false;
6209
6210 vcpu->arch.last_retry_eip = ctxt->eip;
6211 vcpu->arch.last_retry_addr = cr2;
6212
44dd3ffa 6213 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6214 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6215
22368028 6216 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6217
6218 return true;
6219}
6220
716d51ab
GN		 6221static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6222static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6223
64d60670 6224static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6225{
64d60670 6226 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6227 /* This is a good place to trace that we are exiting SMM. */
6228 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6229
c43203ca
PB		 6230 /* Process a latched INIT or SMI, if any. */
6231 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6232 }
699023e2
PB		 6233
6234 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6235}
6236
6237static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
6238{
6239 unsigned changed = vcpu->arch.hflags ^ emul_flags;
6240
a584539b 6241 vcpu->arch.hflags = emul_flags;
64d60670
PB		 6242
6243 if (changed & HF_SMM_MASK)
6244 kvm_smm_changed(vcpu);
a584539b
PB		 6245}
6246
4a1e10d5
PB		 6247static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6248 unsigned long *db)
6249{
6250 u32 dr6 = 0;
6251 int i;
6252 u32 enable, rwlen;
6253
6254 enable = dr7;
6255 rwlen = dr7 >> 16;
6256 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6257 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6258 dr6 |= (1 << i);
6259 return dr6;
6260}
6261
c8401dda 6262static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6263{
6264 struct kvm_run *kvm_run = vcpu->run;
6265
c8401dda
PB		 6266 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6267 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6268 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6269 kvm_run->debug.arch.exception = DB_VECTOR;
6270 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6271 *r = EMULATE_USER_EXIT;
6272 } else {
f10c729f 6273 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
663f4c61
PB		 6274 }
6275}
6276
6affcbed
KH		 6277int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6278{
6279 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6280 int r = EMULATE_DONE;
6281
6282 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6283
6284 /*
6285 * rflags is the old, "raw" value of the flags. The new value has
6286 * not been saved yet.
6287 *
6288 * This is correct even for TF set by the guest, because "the
6289 * processor will not generate this exception after the instruction
6290 * that sets the TF flag".
6291 */
6292 if (unlikely(rflags & X86_EFLAGS_TF))
6293 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6294 return r == EMULATE_DONE;
6295}
6296EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6297
4a1e10d5
PB		 6298static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6299{
4a1e10d5
PB		 6300 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6301 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6302 struct kvm_run *kvm_run = vcpu->run;
6303 unsigned long eip = kvm_get_linear_rip(vcpu);
6304 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6305 vcpu->arch.guest_debug_dr7,
6306 vcpu->arch.eff_db);
6307
6308 if (dr6 != 0) {
6f43ed01 6309 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6310 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6311 kvm_run->debug.arch.exception = DB_VECTOR;
6312 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6313 *r = EMULATE_USER_EXIT;
6314 return true;
6315 }
6316 }
6317
4161a569
NA		 6318 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6319 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6320 unsigned long eip = kvm_get_linear_rip(vcpu);
6321 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6322 vcpu->arch.dr7,
6323 vcpu->arch.db);
6324
6325 if (dr6 != 0) {
6326 vcpu->arch.dr6 &= ~15;
6f43ed01 6327 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6328 kvm_queue_exception(vcpu, DB_VECTOR);
6329 *r = EMULATE_DONE;
6330 return true;
6331 }
6332 }
6333
6334 return false;
6335}
6336
04789b66
LA		 6337static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6338{
2d7921c4
AM		 6339 switch (ctxt->opcode_len) {
6340 case 1:
6341 switch (ctxt->b) {
6342 case 0xe4: /* IN */
6343 case 0xe5:
6344 case 0xec:
6345 case 0xed:
6346 case 0xe6: /* OUT */
6347 case 0xe7:
6348 case 0xee:
6349 case 0xef:
6350 case 0x6c: /* INS */
6351 case 0x6d:
6352 case 0x6e: /* OUTS */
6353 case 0x6f:
6354 return true;
6355 }
6356 break;
6357 case 2:
6358 switch (ctxt->b) {
6359 case 0x33: /* RDPMC */
6360 return true;
6361 }
6362 break;
04789b66
LA		 6363 }
6364
6365 return false;
6366}
6367
51d8b661
AP		 6368int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6369 unsigned long cr2,
dc25e89e
AP		 6370 int emulation_type,
6371 void *insn,
6372 int insn_len)
bbd9b64e 6373{
95cb2295 6374 int r;
9d74191a 6375 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6376 bool writeback = true;
93c05d3e 6377 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6378
c595ceee
PB		 6379 vcpu->arch.l1tf_flush_l1d = true;
6380
93c05d3e
XG		 6381 /*
6382 * Clear write_fault_to_shadow_pgtable here to ensure it is
6383 * never reused.
6384 */
6385 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6386 kvm_clear_exception_queue(vcpu);
8d7d8102 6387
571008da 6388 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6389 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6390
6391 /*
6392 * We will reenter on the same instruction since
6393 * we do not set complete_userspace_io. This does not
6394 * handle watchpoints yet, those would be handled in
6395 * the emulate_ops.
6396 */
d391f120
VK		 6397 if (!(emulation_type & EMULTYPE_SKIP) &&
6398 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6399 return r;
6400
9d74191a
TY		 6401 ctxt->interruptibility = 0;
6402 ctxt->have_exception = false;
e0ad0b47 6403 ctxt->exception.vector = -1;
9d74191a 6404 ctxt->perm_ok = false;
bbd9b64e 6405
b51e974f 6406 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6407
9d74191a 6408 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6409
e46479f8 6410 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6411 ++vcpu->stat.insn_emulation;
1d2887e2 6412 if (r != EMULATION_OK) {
4005996e
AK		 6413 if (emulation_type & EMULTYPE_TRAP_UD)
6414 return EMULATE_FAIL;
991eebf9
GN		 6415 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6416 emulation_type))
bbd9b64e 6417 return EMULATE_DONE;
6ea6e843
PB		 6418 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6419 return EMULATE_DONE;
6d77dbfc
GN		 6420 if (emulation_type & EMULTYPE_SKIP)
6421 return EMULATE_FAIL;
e2366171 6422 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6423 }
6424 }
6425
04789b66
LA		 6426 if ((emulation_type & EMULTYPE_VMWARE) &&
6427 !is_vmware_backdoor_opcode(ctxt))
6428 return EMULATE_FAIL;
6429
ba8afb6b 6430 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6431 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6432 if (ctxt->eflags & X86_EFLAGS_RF)
6433 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6434 return EMULATE_DONE;
6435 }
6436
1cb3f3ae
XG		 6437 if (retry_instruction(ctxt, cr2, emulation_type))
6438 return EMULATE_DONE;
6439
7ae441ea 6440 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6441 changes registers values during IO operation */
7ae441ea
GN		 6442 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6443 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6444 emulator_invalidate_register_cache(ctxt);
7ae441ea 6445 }
4d2179e1 6446
5cd21917 6447restart:
0f89b207
TL		 6448 /* Save the faulting GPA (cr2) in the address field */
6449 ctxt->exception.address = cr2;
6450
9d74191a 6451 r = x86_emulate_insn(ctxt);
bbd9b64e 6452
775fde86
JR		 6453 if (r == EMULATION_INTERCEPTED)
6454 return EMULATE_DONE;
6455
d2ddd1c4 6456 if (r == EMULATION_FAILED) {
991eebf9
GN		 6457 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6458 emulation_type))
c3cd7ffa
GN		 6459 return EMULATE_DONE;
6460
e2366171 6461 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6462 }
6463
9d74191a 6464 if (ctxt->have_exception) {
d2ddd1c4 6465 r = EMULATE_DONE;
ef54bcfe
PB		 6466 if (inject_emulated_exception(vcpu))
6467 return r;
d2ddd1c4 6468 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6469 if (!vcpu->arch.pio.in) {
6470 /* FIXME: return into emulator if single-stepping. */
3457e419 6471 vcpu->arch.pio.count = 0;
0912c977 6472 } else {
7ae441ea 6473 writeback = false;
716d51ab
GN		 6474 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6475 }
ac0a48c3 6476 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6477 } else if (vcpu->mmio_needed) {
6478 if (!vcpu->mmio_is_write)
6479 writeback = false;
ac0a48c3 6480 r = EMULATE_USER_EXIT;
716d51ab 6481 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6482 } else if (r == EMULATION_RESTART)
5cd21917 6483 goto restart;
d2ddd1c4
GN		 6484 else
6485 r = EMULATE_DONE;
f850e2e6 6486
7ae441ea 6487 if (writeback) {
6addfc42 6488 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6489 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6490 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6491 kvm_rip_write(vcpu, ctxt->eip);
5cc244a2 6492 if (r == EMULATE_DONE && ctxt->tf)
c8401dda 6493 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6494 if (!ctxt->have_exception ||
6495 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6496 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6497
6498 /*
6499 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6500 * do nothing, and it will be requested again as soon as
6501 * the shadow expires. But we still need to check here,
6502 * because POPF has no interrupt shadow.
6503 */
6504 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6505 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6506 } else
6507 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6508
6509 return r;
de7d789a 6510}
c60658d1
SC		 6511
6512int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6513{
6514 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6515}
6516EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6517
6518int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6519 void *insn, int insn_len)
6520{
6521 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6522}
6523EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6524
dca7f128
SC		 6525static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6526 unsigned short port)
de7d789a 6527{
cf8f70bf 6528 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6529 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6530 size, port, &val, 1);
cf8f70bf 6531 /* do not return to emulator after return from userspace */
7972995b 6532 vcpu->arch.pio.count = 0;
de7d789a
CO		 6533 return ret;
6534}
de7d789a 6535
8370c3d0
TL		 6536static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6537{
6538 unsigned long val;
6539
6540 /* We should only ever be called with arch.pio.count equal to 1 */
6541 BUG_ON(vcpu->arch.pio.count != 1);
6542
6543 /* For size less than 4 we merge, else we zero extend */
6544 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6545 : 0;
6546
6547 /*
6548 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6549 * the copy and tracing
6550 */
6551 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6552 vcpu->arch.pio.port, &val, 1);
6553 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6554
6555 return 1;
6556}
6557
dca7f128
SC		 6558static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6559 unsigned short port)
8370c3d0
TL		 6560{
6561 unsigned long val;
6562 int ret;
6563
6564 /* For size less than 4 we merge, else we zero extend */
6565 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6566
6567 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6568 &val, 1);
6569 if (ret) {
6570 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6571 return ret;
6572 }
6573
6574 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6575
6576 return 0;
6577}
dca7f128
SC		 6578
6579int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6580{
6581 int ret = kvm_skip_emulated_instruction(vcpu);
6582
6583 /*
6584 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6585 * KVM_EXIT_DEBUG here.
6586 */
6587 if (in)
6588 return kvm_fast_pio_in(vcpu, size, port) && ret;
6589 else
6590 return kvm_fast_pio_out(vcpu, size, port) && ret;
6591}
6592EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6593
251a5fd6 6594static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6595{
0a3aee0d 6596 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6597 return 0;
8cfdc000
ZA		 6598}
6599
6600static void tsc_khz_changed(void *data)
c8076604 6601{
8cfdc000
ZA		 6602 struct cpufreq_freqs *freq = data;
6603 unsigned long khz = 0;
6604
6605 if (data)
6606 khz = freq->new;
6607 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6608 khz = cpufreq_quick_get(raw_smp_processor_id());
6609 if (!khz)
6610 khz = tsc_khz;
0a3aee0d 6611 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6612}
6613
5fa4ec9c 6614#ifdef CONFIG_X86_64
0092e434
VK		 6615static void kvm_hyperv_tsc_notifier(void)
6616{
0092e434
VK		 6617 struct kvm *kvm;
6618 struct kvm_vcpu *vcpu;
6619 int cpu;
6620
6621 spin_lock(&kvm_lock);
6622 list_for_each_entry(kvm, &vm_list, vm_list)
6623 kvm_make_mclock_inprogress_request(kvm);
6624
6625 hyperv_stop_tsc_emulation();
6626
6627 /* TSC frequency always matches when on Hyper-V */
6628 for_each_present_cpu(cpu)
6629 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6630 kvm_max_guest_tsc_khz = tsc_khz;
6631
6632 list_for_each_entry(kvm, &vm_list, vm_list) {
6633 struct kvm_arch *ka = &kvm->arch;
6634
6635 spin_lock(&ka->pvclock_gtod_sync_lock);
6636
6637 pvclock_update_vm_gtod_copy(kvm);
6638
6639 kvm_for_each_vcpu(cpu, vcpu, kvm)
6640 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6641
6642 kvm_for_each_vcpu(cpu, vcpu, kvm)
6643 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6644
6645 spin_unlock(&ka->pvclock_gtod_sync_lock);
6646 }
6647 spin_unlock(&kvm_lock);
0092e434 6648}
5fa4ec9c 6649#endif
0092e434 6650
c8076604
GH		 6651static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6652 void *data)
6653{
6654 struct cpufreq_freqs *freq = data;
6655 struct kvm *kvm;
6656 struct kvm_vcpu *vcpu;
6657 int i, send_ipi = 0;
6658
8cfdc000
ZA		 6659 /*
6660 * We allow guests to temporarily run on slowing clocks,
6661 * provided we notify them after, or to run on accelerating
6662 * clocks, provided we notify them before. Thus time never
6663 * goes backwards.
6664 *
6665 * However, we have a problem. We can't atomically update
6666 * the frequency of a given CPU from this function; it is
6667 * merely a notifier, which can be called from any CPU.
6668 * Changing the TSC frequency at arbitrary points in time
6669 * requires a recomputation of local variables related to
6670 * the TSC for each VCPU. We must flag these local variables
6671 * to be updated and be sure the update takes place with the
6672 * new frequency before any guests proceed.
6673 *
6674 * Unfortunately, the combination of hotplug CPU and frequency
6675 * change creates an intractable locking scenario; the order
6676 * of when these callouts happen is undefined with respect to
6677 * CPU hotplug, and they can race with each other. As such,
6678 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6679 * undefined; you can actually have a CPU frequency change take
6680 * place in between the computation of X and the setting of the
6681 * variable. To protect against this problem, all updates of
6682 * the per_cpu tsc_khz variable are done in an interrupt
6683 * protected IPI, and all callers wishing to update the value
6684 * must wait for a synchronous IPI to complete (which is trivial
6685 * if the caller is on the CPU already). This establishes the
6686 * necessary total order on variable updates.
6687 *
6688 * Note that because a guest time update may take place
6689 * anytime after the setting of the VCPU's request bit, the
6690 * correct TSC value must be set before the request. However,
6691 * to ensure the update actually makes it to any guest which
6692 * starts running in hardware virtualization between the set
6693 * and the acquisition of the spinlock, we must also ping the
6694 * CPU after setting the request bit.
6695 *
6696 */
6697
c8076604
GH		 6698 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6699 return 0;
6700 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6701 return 0;
8cfdc000
ZA		 6702
6703 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6704
2f303b74 6705 spin_lock(&kvm_lock);
c8076604 6706 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6707 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6708 if (vcpu->cpu != freq->cpu)
6709 continue;
c285545f 6710 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6711 if (vcpu->cpu != smp_processor_id())
8cfdc000 6712 send_ipi = 1;
c8076604
GH		 6713 }
6714 }
2f303b74 6715 spin_unlock(&kvm_lock);
c8076604
GH		 6716
6717 if (freq->old < freq->new && send_ipi) {
6718 /*
6719 * We upscale the frequency. Must make the guest
6720 * doesn't see old kvmclock values while running with
6721 * the new frequency, otherwise we risk the guest sees
6722 * time go backwards.
6723 *
6724 * In case we update the frequency for another cpu
6725 * (which might be in guest context) send an interrupt
6726 * to kick the cpu out of guest context. Next time
6727 * guest context is entered kvmclock will be updated,
6728 * so the guest will not see stale values.
6729 */
8cfdc000 6730 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6731 }
6732 return 0;
6733}
6734
6735static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6736 .notifier_call = kvmclock_cpufreq_notifier
6737};
6738
251a5fd6 6739static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6740{
251a5fd6
SAS		 6741 tsc_khz_changed(NULL);
6742 return 0;
8cfdc000
ZA		 6743}
6744
b820cc0c
ZA		 6745static void kvm_timer_init(void)
6746{
c285545f 6747 max_tsc_khz = tsc_khz;
460dd42e 6748
b820cc0c 6749 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6750#ifdef CONFIG_CPU_FREQ
6751 struct cpufreq_policy policy;
758f588d
BP		 6752 int cpu;
6753
c285545f 6754 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6755 cpu = get_cpu();
6756 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6757 if (policy.cpuinfo.max_freq)
6758 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6759 put_cpu();
c285545f 6760#endif
b820cc0c
ZA		 6761 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6762 CPUFREQ_TRANSITION_NOTIFIER);
6763 }
c285545f 6764 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6765
73c1b41e 6766 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6767 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6768}
6769
dd60d217
AK		 6770DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6771EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6772
f5132b01 6773int kvm_is_in_guest(void)
ff9d07a0 6774{
086c9855 6775 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6776}
6777
6778static int kvm_is_user_mode(void)
6779{
6780 int user_mode = 3;
dcf46b94 6781
086c9855
AS		 6782 if (__this_cpu_read(current_vcpu))
6783 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6784
ff9d07a0
ZY		 6785 return user_mode != 0;
6786}
6787
6788static unsigned long kvm_get_guest_ip(void)
6789{
6790 unsigned long ip = 0;
dcf46b94 6791
086c9855
AS		 6792 if (__this_cpu_read(current_vcpu))
6793 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6794
ff9d07a0
ZY		 6795 return ip;
6796}
6797
6798static struct perf_guest_info_callbacks kvm_guest_cbs = {
6799 .is_in_guest = kvm_is_in_guest,
6800 .is_user_mode = kvm_is_user_mode,
6801 .get_guest_ip = kvm_get_guest_ip,
6802};
6803
ce88decf
XG		 6804static void kvm_set_mmio_spte_mask(void)
6805{
6806 u64 mask;
6807 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6808
6809 /*
6810 * Set the reserved bits and the present bit of an paging-structure
6811 * entry to generate page fault with PFER.RSV = 1.
6812 */
28a1f3ac
JS		 6813
6814 /*
6815 * Mask the uppermost physical address bit, which would be reserved as
6816 * long as the supported physical address width is less than 52.
6817 */
6818 mask = 1ull << 51;
885032b9 6819
885032b9 6820 /* Set the present bit. */
ce88decf
XG		 6821 mask |= 1ull;
6822
ce88decf
XG		 6823 /*
6824 * If reserved bit is not supported, clear the present bit to disable
6825 * mmio page fault.
6826 */
7288bde1 6827 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
ce88decf 6828 mask &= ~1ull;
ce88decf 6829
dcdca5fe 6830 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6831}
6832
16e8d74d
MT		 6833#ifdef CONFIG_X86_64
6834static void pvclock_gtod_update_fn(struct work_struct *work)
6835{
d828199e
MT		 6836 struct kvm *kvm;
6837
6838 struct kvm_vcpu *vcpu;
6839 int i;
6840
2f303b74 6841 spin_lock(&kvm_lock);
d828199e
MT		 6842 list_for_each_entry(kvm, &vm_list, vm_list)
6843 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6844 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6845 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6846 spin_unlock(&kvm_lock);
16e8d74d
MT		 6847}
6848
6849static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6850
6851/*
6852 * Notification about pvclock gtod data update.
6853 */
6854static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6855 void *priv)
6856{
6857 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6858 struct timekeeper *tk = priv;
6859
6860 update_pvclock_gtod(tk);
6861
6862 /* disable master clock if host does not trust, or does not
b0c39dc6 6863 * use, TSC based clocksource.
16e8d74d 6864 */
b0c39dc6 6865 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6866 atomic_read(&kvm_guest_has_master_clock) != 0)
6867 queue_work(system_long_wq, &pvclock_gtod_work);
6868
6869 return 0;
6870}
6871
6872static struct notifier_block pvclock_gtod_notifier = {
6873 .notifier_call = pvclock_gtod_notify,
6874};
6875#endif
6876
f8c16bba 6877int kvm_arch_init(void *opaque)
043405e1 6878{
b820cc0c 6879 int r;
6b61edf7 6880 struct kvm_x86_ops *ops = opaque;
f8c16bba 6881
f8c16bba
ZX		 6882 if (kvm_x86_ops) {
6883 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6884 r = -EEXIST;
6885 goto out;
f8c16bba
ZX		 6886 }
6887
6888 if (!ops->cpu_has_kvm_support()) {
6889 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6890 r = -EOPNOTSUPP;
6891 goto out;
f8c16bba
ZX		 6892 }
6893 if (ops->disabled_by_bios()) {
6894 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6895 r = -EOPNOTSUPP;
6896 goto out;
f8c16bba
ZX		 6897 }
6898
b666a4b6
MO		 6899 /*
6900 * KVM explicitly assumes that the guest has an FPU and
6901 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
6902 * vCPU's FPU state as a fxregs_state struct.
6903 */
6904 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
6905 printk(KERN_ERR "kvm: inadequate fpu\n");
6906 r = -EOPNOTSUPP;
6907 goto out;
6908 }
6909
013f6a5d 6910 r = -ENOMEM;
ed8e4812 6911 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 6912 __alignof__(struct fpu), SLAB_ACCOUNT,
6913 NULL);
6914 if (!x86_fpu_cache) {
6915 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
6916 goto out;
6917 }
6918
013f6a5d
MT		 6919 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6920 if (!shared_msrs) {
6921 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 6922 goto out_free_x86_fpu_cache;
013f6a5d
MT		 6923 }
6924
97db56ce
AK		 6925 r = kvm_mmu_module_init();
6926 if (r)
013f6a5d 6927 goto out_free_percpu;
97db56ce 6928
ce88decf 6929 kvm_set_mmio_spte_mask();
97db56ce 6930
f8c16bba 6931 kvm_x86_ops = ops;
920c8377 6932
7b52345e 6933 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6934 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6935 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6936 kvm_timer_init();
c8076604 6937
ff9d07a0
ZY		 6938 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6939
d366bf7e 6940 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6941 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6942
c5cc421b 6943 kvm_lapic_init();
16e8d74d
MT		 6944#ifdef CONFIG_X86_64
6945 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6946
5fa4ec9c 6947 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6948 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6949#endif
6950
f8c16bba 6951 return 0;
56c6d28a 6952
013f6a5d
MT		 6953out_free_percpu:
6954 free_percpu(shared_msrs);
b666a4b6
MO		 6955out_free_x86_fpu_cache:
6956 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 6957out:
56c6d28a 6958 return r;
043405e1 6959}
8776e519 6960
f8c16bba
ZX		 6961void kvm_arch_exit(void)
6962{
0092e434 6963#ifdef CONFIG_X86_64
5fa4ec9c 6964 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6965 clear_hv_tscchange_cb();
6966#endif
cef84c30 6967 kvm_lapic_exit();
ff9d07a0
ZY		 6968 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6969
888d256e
JK		 6970 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6971 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6972 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6973 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6974#ifdef CONFIG_X86_64
6975 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6976#endif
f8c16bba 6977 kvm_x86_ops = NULL;
56c6d28a 6978 kvm_mmu_module_exit();
013f6a5d 6979 free_percpu(shared_msrs);
b666a4b6 6980 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 6981}
f8c16bba 6982
5cb56059 6983int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6984{
6985 ++vcpu->stat.halt_exits;
35754c98 6986 if (lapic_in_kernel(vcpu)) {
a4535290 6987 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6988 return 1;
6989 } else {
6990 vcpu->run->exit_reason = KVM_EXIT_HLT;
6991 return 0;
6992 }
6993}
5cb56059
JS		 6994EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6995
6996int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6997{
6affcbed
KH		 6998 int ret = kvm_skip_emulated_instruction(vcpu);
6999 /*
7000 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7001 * KVM_EXIT_DEBUG here.
7002 */
7003 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 7004}
8776e519
HB		 7005EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7006
8ef81a9a 7007#ifdef CONFIG_X86_64
55dd00a7
MT		 7008static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7009 unsigned long clock_type)
7010{
7011 struct kvm_clock_pairing clock_pairing;
899a31f5 7012 struct timespec64 ts;
80fbd89c 7013 u64 cycle;
55dd00a7
MT		 7014 int ret;
7015
7016 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7017 return -KVM_EOPNOTSUPP;
7018
7019 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7020 return -KVM_EOPNOTSUPP;
7021
7022 clock_pairing.sec = ts.tv_sec;
7023 clock_pairing.nsec = ts.tv_nsec;
7024 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7025 clock_pairing.flags = 0;
bcbfbd8e 7026 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 7027
7028 ret = 0;
7029 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7030 sizeof(struct kvm_clock_pairing)))
7031 ret = -KVM_EFAULT;
7032
7033 return ret;
7034}
8ef81a9a 7035#endif
55dd00a7 7036
6aef266c
SV		 7037/*
7038 * kvm_pv_kick_cpu_op: Kick a vcpu.
7039 *
7040 * @apicid - apicid of vcpu to be kicked.
7041 */
7042static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7043{
24d2166b 7044 struct kvm_lapic_irq lapic_irq;
6aef266c 7045
24d2166b
R		 7046 lapic_irq.shorthand = 0;
7047 lapic_irq.dest_mode = 0;
ebd28fcb 7048 lapic_irq.level = 0;
24d2166b 7049 lapic_irq.dest_id = apicid;
93bbf0b8 7050 lapic_irq.msi_redir_hint = false;
6aef266c 7051
24d2166b 7052 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7053 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7054}
7055
d62caabb
AS		 7056void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7057{
f7589cca
PB		 7058 if (!lapic_in_kernel(vcpu)) {
7059 WARN_ON_ONCE(vcpu->arch.apicv_active);
7060 return;
7061 }
7062 if (!vcpu->arch.apicv_active)
7063 return;
7064
d62caabb
AS		 7065 vcpu->arch.apicv_active = false;
7066 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7067}
7068
8776e519
HB		 7069int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7070{
7071 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7072 int op_64_bit;
8776e519 7073
696ca779
RK		 7074 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7075 return kvm_hv_hypercall(vcpu);
55cd8e5a 7076
5fdbf976
MT		 7077 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
7078 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
7079 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
7080 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
7081 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 7082
229456fc 7083 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7084
a449c7aa
NA		 7085 op_64_bit = is_64_bit_mode(vcpu);
7086 if (!op_64_bit) {
8776e519
HB		 7087 nr &= 0xFFFFFFFF;
7088 a0 &= 0xFFFFFFFF;
7089 a1 &= 0xFFFFFFFF;
7090 a2 &= 0xFFFFFFFF;
7091 a3 &= 0xFFFFFFFF;
7092 }
7093
07708c4a
JK		 7094 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7095 ret = -KVM_EPERM;
696ca779 7096 goto out;
07708c4a
JK		 7097 }
7098
8776e519 7099 switch (nr) {
b93463aa
AK		 7100 case KVM_HC_VAPIC_POLL_IRQ:
7101 ret = 0;
7102 break;
6aef266c
SV		 7103 case KVM_HC_KICK_CPU:
7104 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
7105 ret = 0;
7106 break;
8ef81a9a 7107#ifdef CONFIG_X86_64
55dd00a7
MT		 7108 case KVM_HC_CLOCK_PAIRING:
7109 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7110 break;
1ed199a4 7111#endif
4180bf1b
WL		 7112 case KVM_HC_SEND_IPI:
7113 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7114 break;
8776e519
HB		 7115 default:
7116 ret = -KVM_ENOSYS;
7117 break;
7118 }
696ca779 7119out:
a449c7aa
NA		 7120 if (!op_64_bit)
7121 ret = (u32)ret;
5fdbf976 7122 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 7123
f11c3a8d 7124 ++vcpu->stat.hypercalls;
6356ee0c 7125 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7126}
7127EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7128
b6785def 7129static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7130{
d6aa1000 7131 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7132 char instruction[3];
5fdbf976 7133 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7134
8776e519 7135 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7136
ce2e852e
DV		 7137 return emulator_write_emulated(ctxt, rip, instruction, 3,
7138 &ctxt->exception);
8776e519
HB		 7139}
7140
851ba692 7141static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7142{
782d422b
MG		 7143 return vcpu->run->request_interrupt_window &&
7144 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7145}
7146
851ba692 7147static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7148{
851ba692
AK		 7149 struct kvm_run *kvm_run = vcpu->run;
7150
91586a3b 7151 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7152 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7153 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7154 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7155 kvm_run->ready_for_interrupt_injection =
7156 pic_in_kernel(vcpu->kvm) ||
782d422b 7157 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7158}
7159
95ba8273
GN		 7160static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7161{
7162 int max_irr, tpr;
7163
7164 if (!kvm_x86_ops->update_cr8_intercept)
7165 return;
7166
bce87cce 7167 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7168 return;
7169
d62caabb
AS		 7170 if (vcpu->arch.apicv_active)
7171 return;
7172
8db3baa2
GN		 7173 if (!vcpu->arch.apic->vapic_addr)
7174 max_irr = kvm_lapic_find_highest_irr(vcpu);
7175 else
7176 max_irr = -1;
95ba8273
GN		 7177
7178 if (max_irr != -1)
7179 max_irr >>= 4;
7180
7181 tpr = kvm_lapic_get_cr8(vcpu);
7182
7183 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7184}
7185
b6b8a145 7186static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7187{
b6b8a145
JK		 7188 int r;
7189
95ba8273 7190 /* try to reinject previous events if any */
664f8e26 7191
1a680e35
LA		 7192 if (vcpu->arch.exception.injected)
7193 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7194 /*
a042c26f
LA		 7195 * Do not inject an NMI or interrupt if there is a pending
7196 * exception. Exceptions and interrupts are recognized at
7197 * instruction boundaries, i.e. the start of an instruction.
7198 * Trap-like exceptions, e.g. #DB, have higher priority than
7199 * NMIs and interrupts, i.e. traps are recognized before an
7200 * NMI/interrupt that's pending on the same instruction.
7201 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7202 * priority, but are only generated (pended) during instruction
7203 * execution, i.e. a pending fault-like exception means the
7204 * fault occurred on the *previous* instruction and must be
7205 * serviced prior to recognizing any new events in order to
7206 * fully complete the previous instruction.
664f8e26 7207 */
1a680e35
LA		 7208 else if (!vcpu->arch.exception.pending) {
7209 if (vcpu->arch.nmi_injected)
664f8e26 7210 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7211 else if (vcpu->arch.interrupt.injected)
664f8e26 7212 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7213 }
7214
1a680e35
LA		 7215 /*
7216 * Call check_nested_events() even if we reinjected a previous event
7217 * in order for caller to determine if it should require immediate-exit
7218 * from L2 to L1 due to pending L1 events which require exit
7219 * from L2 to L1.
7220 */
664f8e26
WL		 7221 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7222 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7223 if (r != 0)
7224 return r;
7225 }
7226
7227 /* try to inject new event if pending */
b59bb7bd 7228 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7229 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7230 vcpu->arch.exception.has_error_code,
7231 vcpu->arch.exception.error_code);
d6e8c854 7232
1a680e35 7233 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7234 vcpu->arch.exception.pending = false;
7235 vcpu->arch.exception.injected = true;
7236
d6e8c854
NA		 7237 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7238 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7239 X86_EFLAGS_RF);
7240
f10c729f
JM		 7241 if (vcpu->arch.exception.nr == DB_VECTOR) {
7242 /*
7243 * This code assumes that nSVM doesn't use
7244 * check_nested_events(). If it does, the
7245 * DR6/DR7 changes should happen before L1
7246 * gets a #VMEXIT for an intercepted #DB in
7247 * L2. (Under VMX, on the other hand, the
7248 * DR6/DR7 changes should not happen in the
7249 * event of a VM-exit to L1 for an intercepted
7250 * #DB in L2.)
7251 */
7252 kvm_deliver_exception_payload(vcpu);
7253 if (vcpu->arch.dr7 & DR7_GD) {
7254 vcpu->arch.dr7 &= ~DR7_GD;
7255 kvm_update_dr7(vcpu);
7256 }
6bdf0662
NA		 7257 }
7258
cfcd20e5 7259 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7260 }
7261
7262 /* Don't consider new event if we re-injected an event */
7263 if (kvm_event_needs_reinjection(vcpu))
7264 return 0;
7265
7266 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7267 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7268 vcpu->arch.smi_pending = false;
52797bf9 7269 ++vcpu->arch.smi_count;
ee2cd4b7 7270 enter_smm(vcpu);
c43203ca 7271 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7272 --vcpu->arch.nmi_pending;
7273 vcpu->arch.nmi_injected = true;
7274 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7275 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7276 /*
7277 * Because interrupts can be injected asynchronously, we are
7278 * calling check_nested_events again here to avoid a race condition.
7279 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7280 * proposal and current concerns. Perhaps we should be setting
7281 * KVM_REQ_EVENT only on certain events and not unconditionally?
7282 */
7283 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7284 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7285 if (r != 0)
7286 return r;
7287 }
95ba8273 7288 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7289 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7290 false);
7291 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7292 }
7293 }
ee2cd4b7 7294
b6b8a145 7295 return 0;
95ba8273
GN		 7296}
7297
7460fb4a
AK		 7298static void process_nmi(struct kvm_vcpu *vcpu)
7299{
7300 unsigned limit = 2;
7301
7302 /*
7303 * x86 is limited to one NMI running, and one NMI pending after it.
7304 * If an NMI is already in progress, limit further NMIs to just one.
7305 * Otherwise, allow two (and we'll inject the first one immediately).
7306 */
7307 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7308 limit = 1;
7309
7310 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7311 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7312 kvm_make_request(KVM_REQ_EVENT, vcpu);
7313}
7314
ee2cd4b7 7315static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7316{
7317 u32 flags = 0;
7318 flags |= seg->g << 23;
7319 flags |= seg->db << 22;
7320 flags |= seg->l << 21;
7321 flags |= seg->avl << 20;
7322 flags |= seg->present << 15;
7323 flags |= seg->dpl << 13;
7324 flags |= seg->s << 12;
7325 flags |= seg->type << 8;
7326 return flags;
7327}
7328
ee2cd4b7 7329static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7330{
7331 struct kvm_segment seg;
7332 int offset;
7333
7334 kvm_get_segment(vcpu, &seg, n);
7335 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7336
7337 if (n < 3)
7338 offset = 0x7f84 + n * 12;
7339 else
7340 offset = 0x7f2c + (n - 3) * 12;
7341
7342 put_smstate(u32, buf, offset + 8, seg.base);
7343 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7344 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7345}
7346
efbb288a 7347#ifdef CONFIG_X86_64
ee2cd4b7 7348static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7349{
7350 struct kvm_segment seg;
7351 int offset;
7352 u16 flags;
7353
7354 kvm_get_segment(vcpu, &seg, n);
7355 offset = 0x7e00 + n * 16;
7356
ee2cd4b7 7357 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7358 put_smstate(u16, buf, offset, seg.selector);
7359 put_smstate(u16, buf, offset + 2, flags);
7360 put_smstate(u32, buf, offset + 4, seg.limit);
7361 put_smstate(u64, buf, offset + 8, seg.base);
7362}
efbb288a 7363#endif
660a5d51 7364
ee2cd4b7 7365static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7366{
7367 struct desc_ptr dt;
7368 struct kvm_segment seg;
7369 unsigned long val;
7370 int i;
7371
7372 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7373 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7374 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7375 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7376
7377 for (i = 0; i < 8; i++)
7378 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7379
7380 kvm_get_dr(vcpu, 6, &val);
7381 put_smstate(u32, buf, 0x7fcc, (u32)val);
7382 kvm_get_dr(vcpu, 7, &val);
7383 put_smstate(u32, buf, 0x7fc8, (u32)val);
7384
7385 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7386 put_smstate(u32, buf, 0x7fc4, seg.selector);
7387 put_smstate(u32, buf, 0x7f64, seg.base);
7388 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7389 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7390
7391 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7392 put_smstate(u32, buf, 0x7fc0, seg.selector);
7393 put_smstate(u32, buf, 0x7f80, seg.base);
7394 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7395 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7396
7397 kvm_x86_ops->get_gdt(vcpu, &dt);
7398 put_smstate(u32, buf, 0x7f74, dt.address);
7399 put_smstate(u32, buf, 0x7f70, dt.size);
7400
7401 kvm_x86_ops->get_idt(vcpu, &dt);
7402 put_smstate(u32, buf, 0x7f58, dt.address);
7403 put_smstate(u32, buf, 0x7f54, dt.size);
7404
7405 for (i = 0; i < 6; i++)
ee2cd4b7 7406 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7407
7408 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7409
7410 /* revision id */
7411 put_smstate(u32, buf, 0x7efc, 0x00020000);
7412 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7413}
7414
ee2cd4b7 7415static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7416{
7417#ifdef CONFIG_X86_64
7418 struct desc_ptr dt;
7419 struct kvm_segment seg;
7420 unsigned long val;
7421 int i;
7422
7423 for (i = 0; i < 16; i++)
7424 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7425
7426 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7427 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7428
7429 kvm_get_dr(vcpu, 6, &val);
7430 put_smstate(u64, buf, 0x7f68, val);
7431 kvm_get_dr(vcpu, 7, &val);
7432 put_smstate(u64, buf, 0x7f60, val);
7433
7434 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7435 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7436 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7437
7438 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7439
7440 /* revision id */
7441 put_smstate(u32, buf, 0x7efc, 0x00020064);
7442
7443 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7444
7445 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7446 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7447 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7448 put_smstate(u32, buf, 0x7e94, seg.limit);
7449 put_smstate(u64, buf, 0x7e98, seg.base);
7450
7451 kvm_x86_ops->get_idt(vcpu, &dt);
7452 put_smstate(u32, buf, 0x7e84, dt.size);
7453 put_smstate(u64, buf, 0x7e88, dt.address);
7454
7455 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7456 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7457 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7458 put_smstate(u32, buf, 0x7e74, seg.limit);
7459 put_smstate(u64, buf, 0x7e78, seg.base);
7460
7461 kvm_x86_ops->get_gdt(vcpu, &dt);
7462 put_smstate(u32, buf, 0x7e64, dt.size);
7463 put_smstate(u64, buf, 0x7e68, dt.address);
7464
7465 for (i = 0; i < 6; i++)
ee2cd4b7 7466 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7467#else
7468 WARN_ON_ONCE(1);
7469#endif
7470}
7471
ee2cd4b7 7472static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7473{
660a5d51 7474 struct kvm_segment cs, ds;
18c3626e 7475 struct desc_ptr dt;
660a5d51
PB		 7476 char buf[512];
7477 u32 cr0;
7478
660a5d51 7479 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7480 memset(buf, 0, 512);
d6321d49 7481 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7482 enter_smm_save_state_64(vcpu, buf);
660a5d51 7483 else
ee2cd4b7 7484 enter_smm_save_state_32(vcpu, buf);
660a5d51 7485
0234bf88
LP		 7486 /*
7487 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7488 * vCPU state (e.g. leave guest mode) after we've saved the state into
7489 * the SMM state-save area.
7490 */
7491 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7492
7493 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7494 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7495
7496 if (kvm_x86_ops->get_nmi_mask(vcpu))
7497 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7498 else
7499 kvm_x86_ops->set_nmi_mask(vcpu, true);
7500
7501 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7502 kvm_rip_write(vcpu, 0x8000);
7503
7504 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7505 kvm_x86_ops->set_cr0(vcpu, cr0);
7506 vcpu->arch.cr0 = cr0;
7507
7508 kvm_x86_ops->set_cr4(vcpu, 0);
7509
18c3626e
PB		 7510 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7511 dt.address = dt.size = 0;
7512 kvm_x86_ops->set_idt(vcpu, &dt);
7513
660a5d51
PB		 7514 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7515
7516 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7517 cs.base = vcpu->arch.smbase;
7518
7519 ds.selector = 0;
7520 ds.base = 0;
7521
7522 cs.limit = ds.limit = 0xffffffff;
7523 cs.type = ds.type = 0x3;
7524 cs.dpl = ds.dpl = 0;
7525 cs.db = ds.db = 0;
7526 cs.s = ds.s = 1;
7527 cs.l = ds.l = 0;
7528 cs.g = ds.g = 1;
7529 cs.avl = ds.avl = 0;
7530 cs.present = ds.present = 1;
7531 cs.unusable = ds.unusable = 0;
7532 cs.padding = ds.padding = 0;
7533
7534 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7535 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7536 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7537 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7538 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7539 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7540
d6321d49 7541 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7542 kvm_x86_ops->set_efer(vcpu, 0);
7543
7544 kvm_update_cpuid(vcpu);
7545 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7546}
7547
ee2cd4b7 7548static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7549{
7550 vcpu->arch.smi_pending = true;
7551 kvm_make_request(KVM_REQ_EVENT, vcpu);
7552}
7553
2860c4b1
PB		 7554void kvm_make_scan_ioapic_request(struct kvm *kvm)
7555{
7556 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7557}
7558
3d81bc7e 7559static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7560{
dcbd3e49 7561 if (!kvm_apic_present(vcpu))
3d81bc7e 7562 return;
c7c9c56c 7563
6308630b 7564 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7565
b053b2ae 7566 if (irqchip_split(vcpu->kvm))
6308630b 7567 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7568 else {
fa59cc00 7569 if (vcpu->arch.apicv_active)
d62caabb 7570 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 7571 if (ioapic_in_kernel(vcpu->kvm))
7572 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7573 }
e40ff1d6
LA		 7574
7575 if (is_guest_mode(vcpu))
7576 vcpu->arch.load_eoi_exitmap_pending = true;
7577 else
7578 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7579}
7580
7581static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7582{
7583 u64 eoi_exit_bitmap[4];
7584
7585 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7586 return;
7587
5c919412
AS		 7588 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7589 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7590 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7591}
7592
93065ac7
MH		 7593int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7594 unsigned long start, unsigned long end,
7595 bool blockable)
b1394e74
RK		 7596{
7597 unsigned long apic_address;
7598
7599 /*
7600 * The physical address of apic access page is stored in the VMCS.
7601 * Update it when it becomes invalid.
7602 */
7603 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7604 if (start <= apic_address && apic_address < end)
7605 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7606
7607 return 0;
b1394e74
RK		 7608}
7609
4256f43f
TC		 7610void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7611{
c24ae0dc
TC		 7612 struct page *page = NULL;
7613
35754c98 7614 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7615 return;
7616
4256f43f
TC		 7617 if (!kvm_x86_ops->set_apic_access_page_addr)
7618 return;
7619
c24ae0dc 7620 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7621 if (is_error_page(page))
7622 return;
c24ae0dc
TC		 7623 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7624
7625 /*
7626 * Do not pin apic access page in memory, the MMU notifier
7627 * will call us again if it is migrated or swapped out.
7628 */
7629 put_page(page);
4256f43f
TC		 7630}
7631EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7632
d264ee0c
SC		 7633void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7634{
7635 smp_send_reschedule(vcpu->cpu);
7636}
7637EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7638
9357d939 7639/*
362c698f 7640 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7641 * exiting to the userspace. Otherwise, the value will be returned to the
7642 * userspace.
7643 */
851ba692 7644static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7645{
7646 int r;
62a193ed
MG		 7647 bool req_int_win =
7648 dm_request_for_irq_injection(vcpu) &&
7649 kvm_cpu_accept_dm_intr(vcpu);
7650
730dca42 7651 bool req_immediate_exit = false;
b6c7a5dc 7652
2fa6e1e1 7653 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7654 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7655 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7656 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7657 kvm_mmu_unload(vcpu);
a8eeb04a 7658 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7659 __kvm_migrate_timers(vcpu);
d828199e
MT		 7660 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7661 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7662 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7663 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7664 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7665 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7666 if (unlikely(r))
7667 goto out;
7668 }
a8eeb04a 7669 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7670 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7671 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7672 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7673 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7674 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7675 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7676 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7677 r = 0;
7678 goto out;
7679 }
a8eeb04a 7680 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7681 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7682 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7683 r = 0;
7684 goto out;
7685 }
af585b92
GN		 7686 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7687 /* Page is swapped out. Do synthetic halt */
7688 vcpu->arch.apf.halted = true;
7689 r = 1;
7690 goto out;
7691 }
c9aaa895
GC		 7692 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7693 record_steal_time(vcpu);
64d60670
PB		 7694 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7695 process_smi(vcpu);
7460fb4a
AK		 7696 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7697 process_nmi(vcpu);
f5132b01 7698 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7699 kvm_pmu_handle_event(vcpu);
f5132b01 7700 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7701 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7702 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7703 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7704 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7705 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7706 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7707 vcpu->run->eoi.vector =
7708 vcpu->arch.pending_ioapic_eoi;
7709 r = 0;
7710 goto out;
7711 }
7712 }
3d81bc7e
YZ		 7713 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7714 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7715 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7716 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7717 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7718 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7719 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7720 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7721 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7722 r = 0;
7723 goto out;
7724 }
e516cebb
AS		 7725 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7726 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7727 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7728 r = 0;
7729 goto out;
7730 }
db397571
AS		 7731 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7732 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7733 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7734 r = 0;
7735 goto out;
7736 }
f3b138c5
AS		 7737
7738 /*
7739 * KVM_REQ_HV_STIMER has to be processed after
7740 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7741 * depend on the guest clock being up-to-date
7742 */
1f4b34f8
AS		 7743 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7744 kvm_hv_process_stimers(vcpu);
2f52d58c 7745 }
b93463aa 7746
b463a6f7 7747 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7748 ++vcpu->stat.req_event;
66450a21
JK		 7749 kvm_apic_accept_events(vcpu);
7750 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7751 r = 1;
7752 goto out;
7753 }
7754
b6b8a145
JK		 7755 if (inject_pending_event(vcpu, req_int_win) != 0)
7756 req_immediate_exit = true;
321c5658 7757 else {
cc3d967f 7758 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7759 *
cc3d967f
LP		 7760 * SMIs have three cases:
7761 * 1) They can be nested, and then there is nothing to
7762 * do here because RSM will cause a vmexit anyway.
7763 * 2) There is an ISA-specific reason why SMI cannot be
7764 * injected, and the moment when this changes can be
7765 * intercepted.
7766 * 3) Or the SMI can be pending because
7767 * inject_pending_event has completed the injection
7768 * of an IRQ or NMI from the previous vmexit, and
7769 * then we request an immediate exit to inject the
7770 * SMI.
c43203ca
PB		 7771 */
7772 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7773 if (!kvm_x86_ops->enable_smi_window(vcpu))
7774 req_immediate_exit = true;
321c5658
YS		 7775 if (vcpu->arch.nmi_pending)
7776 kvm_x86_ops->enable_nmi_window(vcpu);
7777 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7778 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7779 WARN_ON(vcpu->arch.exception.pending);
321c5658 7780 }
b463a6f7
AK		 7781
7782 if (kvm_lapic_enabled(vcpu)) {
7783 update_cr8_intercept(vcpu);
7784 kvm_lapic_sync_to_vapic(vcpu);
7785 }
7786 }
7787
d8368af8
AK		 7788 r = kvm_mmu_reload(vcpu);
7789 if (unlikely(r)) {
d905c069 7790 goto cancel_injection;
d8368af8
AK		 7791 }
7792
b6c7a5dc
HB		 7793 preempt_disable();
7794
7795 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7796
7797 /*
7798 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7799 * IPI are then delayed after guest entry, which ensures that they
7800 * result in virtual interrupt delivery.
7801 */
7802 local_irq_disable();
6b7e2d09
XG		 7803 vcpu->mode = IN_GUEST_MODE;
7804
01b71917
MT		 7805 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7806
0f127d12 7807 /*
b95234c8 7808 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7809 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8 7810 *
81b01667 7811 * 2) For APICv, we should set ->mode before checking PID.ON. This
b95234c8
PB		 7812 * pairs with the memory barrier implicit in pi_test_and_set_on
7813 * (see vmx_deliver_posted_interrupt).
7814 *
7815 * 3) This also orders the write to mode from any reads to the page
7816 * tables done while the VCPU is running. Please see the comment
7817 * in kvm_flush_remote_tlbs.
6b7e2d09 7818 */
01b71917 7819 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7820
b95234c8
PB		 7821 /*
7822 * This handles the case where a posted interrupt was
7823 * notified with kvm_vcpu_kick.
7824 */
fa59cc00
LA		 7825 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7826 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7827
2fa6e1e1 7828 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7829 || need_resched() || signal_pending(current)) {
6b7e2d09 7830 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7831 smp_wmb();
6c142801
AK		 7832 local_irq_enable();
7833 preempt_enable();
01b71917 7834 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7835 r = 1;
d905c069 7836 goto cancel_injection;
6c142801
AK		 7837 }
7838
fc5b7f3b
DM		 7839 kvm_load_guest_xcr0(vcpu);
7840
c43203ca
PB		 7841 if (req_immediate_exit) {
7842 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 7843 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 7844 }
d6185f20 7845
8b89fe1f 7846 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7847 if (lapic_timer_advance_ns)
7848 wait_lapic_expire(vcpu);
6edaa530 7849 guest_enter_irqoff();
b6c7a5dc 7850
42dbaa5a 7851 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7852 set_debugreg(0, 7);
7853 set_debugreg(vcpu->arch.eff_db[0], 0);
7854 set_debugreg(vcpu->arch.eff_db[1], 1);
7855 set_debugreg(vcpu->arch.eff_db[2], 2);
7856 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7857 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7858 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7859 }
b6c7a5dc 7860
851ba692 7861 kvm_x86_ops->run(vcpu);
b6c7a5dc 7862
c77fb5fe
PB		 7863 /*
7864 * Do this here before restoring debug registers on the host. And
7865 * since we do this before handling the vmexit, a DR access vmexit
7866 * can (a) read the correct value of the debug registers, (b) set
7867 * KVM_DEBUGREG_WONT_EXIT again.
7868 */
7869 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7870 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7871 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7872 kvm_update_dr0123(vcpu);
7873 kvm_update_dr6(vcpu);
7874 kvm_update_dr7(vcpu);
7875 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7876 }
7877
24f1e32c
FW		 7878 /*
7879 * If the guest has used debug registers, at least dr7
7880 * will be disabled while returning to the host.
7881 * If we don't have active breakpoints in the host, we don't
7882 * care about the messed up debug address registers. But if
7883 * we have some of them active, restore the old state.
7884 */
59d8eb53 7885 if (hw_breakpoint_active())
24f1e32c 7886 hw_breakpoint_restore();
42dbaa5a 7887
4ba76538 7888 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7889
6b7e2d09 7890 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7891 smp_wmb();
a547c6db 7892
fc5b7f3b
DM		 7893 kvm_put_guest_xcr0(vcpu);
7894
dd60d217 7895 kvm_before_interrupt(vcpu);
a547c6db 7896 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7897 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7898
7899 ++vcpu->stat.exits;
7900
f2485b3e 7901 guest_exit_irqoff();
b6c7a5dc 7902
f2485b3e 7903 local_irq_enable();
b6c7a5dc
HB		 7904 preempt_enable();
7905
f656ce01 7906 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7907
b6c7a5dc
HB		 7908 /*
7909 * Profile KVM exit RIPs:
7910 */
7911 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7912 unsigned long rip = kvm_rip_read(vcpu);
7913 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7914 }
7915
cc578287
ZA		 7916 if (unlikely(vcpu->arch.tsc_always_catchup))
7917 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7918
5cfb1d5a
MT		 7919 if (vcpu->arch.apic_attention)
7920 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7921
618232e2 7922 vcpu->arch.gpa_available = false;
851ba692 7923 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7924 return r;
7925
7926cancel_injection:
7927 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7928 if (unlikely(vcpu->arch.apic_attention))
7929 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7930out:
7931 return r;
7932}
b6c7a5dc 7933
362c698f
PB		 7934static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7935{
bf9f6ac8
FW		 7936 if (!kvm_arch_vcpu_runnable(vcpu) &&
7937 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7938 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7939 kvm_vcpu_block(vcpu);
7940 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7941
7942 if (kvm_x86_ops->post_block)
7943 kvm_x86_ops->post_block(vcpu);
7944
9c8fd1ba
PB		 7945 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7946 return 1;
7947 }
362c698f
PB		 7948
7949 kvm_apic_accept_events(vcpu);
7950 switch(vcpu->arch.mp_state) {
7951 case KVM_MP_STATE_HALTED:
7952 vcpu->arch.pv.pv_unhalted = false;
7953 vcpu->arch.mp_state =
7954 KVM_MP_STATE_RUNNABLE;
b2869f28 7955 /* fall through */
362c698f
PB		 7956 case KVM_MP_STATE_RUNNABLE:
7957 vcpu->arch.apf.halted = false;
7958 break;
7959 case KVM_MP_STATE_INIT_RECEIVED:
7960 break;
7961 default:
7962 return -EINTR;
7963 break;
7964 }
7965 return 1;
7966}
09cec754 7967
5d9bc648
PB		 7968static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7969{
0ad3bed6
PB		 7970 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7971 kvm_x86_ops->check_nested_events(vcpu, false);
7972
5d9bc648
PB		 7973 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7974 !vcpu->arch.apf.halted);
7975}
7976
362c698f 7977static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7978{
7979 int r;
f656ce01 7980 struct kvm *kvm = vcpu->kvm;
d7690175 7981
f656ce01 7982 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 7983 vcpu->arch.l1tf_flush_l1d = true;
d7690175 7984
362c698f 7985 for (;;) {
58f800d5 7986 if (kvm_vcpu_running(vcpu)) {
851ba692 7987 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7988 } else {
362c698f 7989 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7990 }
7991
09cec754
GN		 7992 if (r <= 0)
7993 break;
7994
72875d8a 7995 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7996 if (kvm_cpu_has_pending_timer(vcpu))
7997 kvm_inject_pending_timer_irqs(vcpu);
7998
782d422b
MG		 7999 if (dm_request_for_irq_injection(vcpu) &&
8000 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 8001 r = 0;
8002 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 8003 ++vcpu->stat.request_irq_exits;
362c698f 8004 break;
09cec754 8005 }
af585b92
GN		 8006
8007 kvm_check_async_pf_completion(vcpu);
8008
09cec754
GN		 8009 if (signal_pending(current)) {
8010 r = -EINTR;
851ba692 8011 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 8012 ++vcpu->stat.signal_exits;
362c698f 8013 break;
09cec754
GN		 8014 }
8015 if (need_resched()) {
f656ce01 8016 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 8017 cond_resched();
f656ce01 8018 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 8019 }
b6c7a5dc
HB		 8020 }
8021
f656ce01 8022 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 8023
8024 return r;
8025}
8026
716d51ab
GN		 8027static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8028{
8029 int r;
8030 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 8031 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 8032 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8033 if (r != EMULATE_DONE)
8034 return 0;
8035 return 1;
8036}
8037
8038static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8039{
8040 BUG_ON(!vcpu->arch.pio.count);
8041
8042 return complete_emulated_io(vcpu);
8043}
8044
f78146b0
AK		 8045/*
8046 * Implements the following, as a state machine:
8047 *
8048 * read:
8049 * for each fragment
87da7e66
XG		 8050 * for each mmio piece in the fragment
8051 * write gpa, len
8052 * exit
8053 * copy data
f78146b0
AK		 8054 * execute insn
8055 *
8056 * write:
8057 * for each fragment
87da7e66
XG		 8058 * for each mmio piece in the fragment
8059 * write gpa, len
8060 * copy data
8061 * exit
f78146b0 8062 */
716d51ab 8063static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8064{
8065 struct kvm_run *run = vcpu->run;
f78146b0 8066 struct kvm_mmio_fragment *frag;
87da7e66 8067 unsigned len;
5287f194 8068
716d51ab 8069 BUG_ON(!vcpu->mmio_needed);
5287f194 8070
716d51ab 8071 /* Complete previous fragment */
87da7e66
XG		 8072 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8073 len = min(8u, frag->len);
716d51ab 8074 if (!vcpu->mmio_is_write)
87da7e66
XG		 8075 memcpy(frag->data, run->mmio.data, len);
8076
8077 if (frag->len <= 8) {
8078 /* Switch to the next fragment. */
8079 frag++;
8080 vcpu->mmio_cur_fragment++;
8081 } else {
8082 /* Go forward to the next mmio piece. */
8083 frag->data += len;
8084 frag->gpa += len;
8085 frag->len -= len;
8086 }
8087
a08d3b3b 8088 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8089 vcpu->mmio_needed = 0;
0912c977
PB		 8090
8091 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8092 if (vcpu->mmio_is_write)
716d51ab
GN		 8093 return 1;
8094 vcpu->mmio_read_completed = 1;
8095 return complete_emulated_io(vcpu);
8096 }
87da7e66 8097
716d51ab
GN		 8098 run->exit_reason = KVM_EXIT_MMIO;
8099 run->mmio.phys_addr = frag->gpa;
8100 if (vcpu->mmio_is_write)
87da7e66
XG		 8101 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8102 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8103 run->mmio.is_write = vcpu->mmio_is_write;
8104 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8105 return 0;
5287f194
AK		 8106}
8107
822f312d
SAS		 8108/* Swap (qemu) user FPU context for the guest FPU context. */
8109static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8110{
8111 preempt_disable();
240c35a3 8112 copy_fpregs_to_fpstate(&current->thread.fpu);
822f312d 8113 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8114 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d
SAS		 8115 ~XFEATURE_MASK_PKRU);
8116 preempt_enable();
8117 trace_kvm_fpu(1);
8118}
8119
8120/* When vcpu_run ends, restore user space FPU context. */
8121static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8122{
8123 preempt_disable();
b666a4b6 8124 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
240c35a3 8125 copy_kernel_to_fpregs(&current->thread.fpu.state);
822f312d
SAS		 8126 preempt_enable();
8127 ++vcpu->stat.fpu_reload;
8128 trace_kvm_fpu(0);
8129}
8130
b6c7a5dc
HB		 8131int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8132{
8133 int r;
b6c7a5dc 8134
accb757d 8135 vcpu_load(vcpu);
20b7035c 8136 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8137 kvm_load_guest_fpu(vcpu);
8138
a4535290 8139 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8140 if (kvm_run->immediate_exit) {
8141 r = -EINTR;
8142 goto out;
8143 }
b6c7a5dc 8144 kvm_vcpu_block(vcpu);
66450a21 8145 kvm_apic_accept_events(vcpu);
72875d8a 8146 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8147 r = -EAGAIN;
a0595000
JS		 8148 if (signal_pending(current)) {
8149 r = -EINTR;
8150 vcpu->run->exit_reason = KVM_EXIT_INTR;
8151 ++vcpu->stat.signal_exits;
8152 }
ac9f6dc0 8153 goto out;
b6c7a5dc
HB		 8154 }
8155
01643c51
KH		 8156 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8157 r = -EINVAL;
8158 goto out;
8159 }
8160
8161 if (vcpu->run->kvm_dirty_regs) {
8162 r = sync_regs(vcpu);
8163 if (r != 0)
8164 goto out;
8165 }
8166
b6c7a5dc 8167 /* re-sync apic's tpr */
35754c98 8168 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8169 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8170 r = -EINVAL;
8171 goto out;
8172 }
8173 }
b6c7a5dc 8174
716d51ab
GN		 8175 if (unlikely(vcpu->arch.complete_userspace_io)) {
8176 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8177 vcpu->arch.complete_userspace_io = NULL;
8178 r = cui(vcpu);
8179 if (r <= 0)
5663d8f9 8180 goto out;
716d51ab
GN		 8181 } else
8182 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8183
460df4c1
PB		 8184 if (kvm_run->immediate_exit)
8185 r = -EINTR;
8186 else
8187 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8188
8189out:
5663d8f9 8190 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8191 if (vcpu->run->kvm_valid_regs)
8192 store_regs(vcpu);
f1d86e46 8193 post_kvm_run_save(vcpu);
20b7035c 8194 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8195
accb757d 8196 vcpu_put(vcpu);
b6c7a5dc
HB		 8197 return r;
8198}
8199
01643c51 8200static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8201{
7ae441ea
GN		 8202 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8203 /*
8204 * We are here if userspace calls get_regs() in the middle of
8205 * instruction emulation. Registers state needs to be copied
4a969980 8206 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8207 * that usually, but some bad designed PV devices (vmware
8208 * backdoor interface) need this to work
8209 */
dd856efa 8210 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8211 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8212 }
5fdbf976
MT		 8213 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
8214 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
8215 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
8216 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
8217 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
8218 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
8219 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8220 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 8221#ifdef CONFIG_X86_64
5fdbf976
MT		 8222 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
8223 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
8224 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
8225 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
8226 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
8227 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
8228 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
8229 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 8230#endif
8231
5fdbf976 8232 regs->rip = kvm_rip_read(vcpu);
91586a3b 8233 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8234}
b6c7a5dc 8235
01643c51
KH		 8236int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8237{
8238 vcpu_load(vcpu);
8239 __get_regs(vcpu, regs);
1fc9b76b 8240 vcpu_put(vcpu);
b6c7a5dc
HB		 8241 return 0;
8242}
8243
01643c51 8244static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8245{
7ae441ea
GN		 8246 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8247 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8248
5fdbf976
MT		 8249 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
8250 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
8251 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
8252 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
8253 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
8254 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
8255 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
8256 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 8257#ifdef CONFIG_X86_64
5fdbf976
MT		 8258 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
8259 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
8260 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
8261 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
8262 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
8263 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
8264 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
8265 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 8266#endif
8267
5fdbf976 8268 kvm_rip_write(vcpu, regs->rip);
d73235d1 8269 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8270
b4f14abd
JK		 8271 vcpu->arch.exception.pending = false;
8272
3842d135 8273 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8274}
3842d135 8275
01643c51
KH		 8276int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8277{
8278 vcpu_load(vcpu);
8279 __set_regs(vcpu, regs);
875656fe 8280 vcpu_put(vcpu);
b6c7a5dc
HB		 8281 return 0;
8282}
8283
b6c7a5dc
HB		 8284void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8285{
8286 struct kvm_segment cs;
8287
3e6e0aab 8288 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8289 *db = cs.db;
8290 *l = cs.l;
8291}
8292EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8293
01643c51 8294static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8295{
89a27f4d 8296 struct desc_ptr dt;
b6c7a5dc 8297
3e6e0aab
GT		 8298 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8299 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8300 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8301 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8302 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8303 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8304
3e6e0aab
GT		 8305 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8306 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8307
8308 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8309 sregs->idt.limit = dt.size;
8310 sregs->idt.base = dt.address;
b6c7a5dc 8311 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8312 sregs->gdt.limit = dt.size;
8313 sregs->gdt.base = dt.address;
b6c7a5dc 8314
4d4ec087 8315 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8316 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8317 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8318 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8319 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8320 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8321 sregs->apic_base = kvm_get_apic_base(vcpu);
8322
0e96f31e 8323 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8324
04140b41 8325 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8326 set_bit(vcpu->arch.interrupt.nr,
8327 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8328}
16d7a191 8329
01643c51
KH		 8330int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8331 struct kvm_sregs *sregs)
8332{
8333 vcpu_load(vcpu);
8334 __get_sregs(vcpu, sregs);
bcdec41c 8335 vcpu_put(vcpu);
b6c7a5dc
HB		 8336 return 0;
8337}
8338
62d9f0db
MT		 8339int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8340 struct kvm_mp_state *mp_state)
8341{
fd232561
CD		 8342 vcpu_load(vcpu);
8343
66450a21 8344 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8345 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8346 vcpu->arch.pv.pv_unhalted)
8347 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8348 else
8349 mp_state->mp_state = vcpu->arch.mp_state;
8350
fd232561 8351 vcpu_put(vcpu);
62d9f0db
MT		 8352 return 0;
8353}
8354
8355int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8356 struct kvm_mp_state *mp_state)
8357{
e83dff5e
CD		 8358 int ret = -EINVAL;
8359
8360 vcpu_load(vcpu);
8361
bce87cce 8362 if (!lapic_in_kernel(vcpu) &&
66450a21 8363 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8364 goto out;
66450a21 8365
28bf2888
DH		 8366 /* INITs are latched while in SMM */
8367 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8368 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8369 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8370 goto out;
28bf2888 8371
66450a21
JK		 8372 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8373 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8374 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8375 } else
8376 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8377 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8378
8379 ret = 0;
8380out:
8381 vcpu_put(vcpu);
8382 return ret;
62d9f0db
MT		 8383}
8384
7f3d35fd
KW		 8385int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8386 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8387{
9d74191a 8388 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8389 int ret;
e01c2426 8390
8ec4722d 8391 init_emulate_ctxt(vcpu);
c697518a 8392
7f3d35fd 8393 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8394 has_error_code, error_code);
c697518a 8395
c697518a 8396 if (ret)
19d04437 8397 return EMULATE_FAIL;
37817f29 8398
9d74191a
TY		 8399 kvm_rip_write(vcpu, ctxt->eip);
8400 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8401 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8402 return EMULATE_DONE;
37817f29
IE		 8403}
8404EXPORT_SYMBOL_GPL(kvm_task_switch);
8405
3140c156 8406static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8407{
74fec5b9
TL		 8408 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8409 (sregs->cr4 & X86_CR4_OSXSAVE))
8410 return -EINVAL;
8411
37b95951 8412 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8413 /*
8414 * When EFER.LME and CR0.PG are set, the processor is in
8415 * 64-bit mode (though maybe in a 32-bit code segment).
8416 * CR4.PAE and EFER.LMA must be set.
8417 */
37b95951 8418 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8419 || !(sregs->efer & EFER_LMA))
8420 return -EINVAL;
8421 } else {
8422 /*
8423 * Not in 64-bit mode: EFER.LMA is clear and the code
8424 * segment cannot be 64-bit.
8425 */
8426 if (sregs->efer & EFER_LMA || sregs->cs.l)
8427 return -EINVAL;
8428 }
8429
8430 return 0;
8431}
8432
01643c51 8433static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8434{
58cb628d 8435 struct msr_data apic_base_msr;
b6c7a5dc 8436 int mmu_reset_needed = 0;
c4d21882 8437 int cpuid_update_needed = 0;
63f42e02 8438 int pending_vec, max_bits, idx;
89a27f4d 8439 struct desc_ptr dt;
b4ef9d4e
CD		 8440 int ret = -EINVAL;
8441
f2981033 8442 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8443 goto out;
f2981033 8444
d3802286
JM		 8445 apic_base_msr.data = sregs->apic_base;
8446 apic_base_msr.host_initiated = true;
8447 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8448 goto out;
6d1068b3 8449
89a27f4d
GN		 8450 dt.size = sregs->idt.limit;
8451 dt.address = sregs->idt.base;
b6c7a5dc 8452 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8453 dt.size = sregs->gdt.limit;
8454 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8455 kvm_x86_ops->set_gdt(vcpu, &dt);
8456
ad312c7c 8457 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8458 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8459 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8460 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8461
2d3ad1f4 8462 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8463
f6801dff 8464 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8465 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8466
4d4ec087 8467 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8468 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8469 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8470
fc78f519 8471 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8472 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8473 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8474 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8475 if (cpuid_update_needed)
00b27a3e 8476 kvm_update_cpuid(vcpu);
63f42e02
XG		 8477
8478 idx = srcu_read_lock(&vcpu->kvm->srcu);
d35b34a9 8479 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu)) {
9f8fe504 8480 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8481 mmu_reset_needed = 1;
8482 }
63f42e02 8483 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8484
8485 if (mmu_reset_needed)
8486 kvm_mmu_reset_context(vcpu);
8487
a50abc3b 8488 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8489 pending_vec = find_first_bit(
8490 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8491 if (pending_vec < max_bits) {
66fd3f7f 8492 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8493 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8494 }
8495
3e6e0aab
GT		 8496 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8497 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8498 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8499 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8500 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8501 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8502
3e6e0aab
GT		 8503 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8504 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8505
5f0269f5
ME		 8506 update_cr8_intercept(vcpu);
8507
9c3e4aab 8508 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8509 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8510 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8511 !is_protmode(vcpu))
9c3e4aab
MT		 8512 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8513
3842d135
AK		 8514 kvm_make_request(KVM_REQ_EVENT, vcpu);
8515
b4ef9d4e
CD		 8516 ret = 0;
8517out:
01643c51
KH		 8518 return ret;
8519}
8520
8521int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8522 struct kvm_sregs *sregs)
8523{
8524 int ret;
8525
8526 vcpu_load(vcpu);
8527 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8528 vcpu_put(vcpu);
8529 return ret;
b6c7a5dc
HB		 8530}
8531
d0bfb940
JK		 8532int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8533 struct kvm_guest_debug *dbg)
b6c7a5dc 8534{
355be0b9 8535 unsigned long rflags;
ae675ef0 8536 int i, r;
b6c7a5dc 8537
66b56562
CD		 8538 vcpu_load(vcpu);
8539
4f926bf2
JK		 8540 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8541 r = -EBUSY;
8542 if (vcpu->arch.exception.pending)
2122ff5e 8543 goto out;
4f926bf2
JK		 8544 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8545 kvm_queue_exception(vcpu, DB_VECTOR);
8546 else
8547 kvm_queue_exception(vcpu, BP_VECTOR);
8548 }
8549
91586a3b
JK		 8550 /*
8551 * Read rflags as long as potentially injected trace flags are still
8552 * filtered out.
8553 */
8554 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8555
8556 vcpu->guest_debug = dbg->control;
8557 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8558 vcpu->guest_debug = 0;
8559
8560 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8561 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8562 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8563 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8564 } else {
8565 for (i = 0; i < KVM_NR_DB_REGS; i++)
8566 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8567 }
c8639010 8568 kvm_update_dr7(vcpu);
ae675ef0 8569
f92653ee
JK		 8570 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8571 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8572 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8573
91586a3b
JK		 8574 /*
8575 * Trigger an rflags update that will inject or remove the trace
8576 * flags.
8577 */
8578 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8579
a96036b8 8580 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8581
4f926bf2 8582 r = 0;
d0bfb940 8583
2122ff5e 8584out:
66b56562 8585 vcpu_put(vcpu);
b6c7a5dc
HB		 8586 return r;
8587}
8588
8b006791
ZX		 8589/*
8590 * Translate a guest virtual address to a guest physical address.
8591 */
8592int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8593 struct kvm_translation *tr)
8594{
8595 unsigned long vaddr = tr->linear_address;
8596 gpa_t gpa;
f656ce01 8597 int idx;
8b006791 8598
1da5b61d
CD		 8599 vcpu_load(vcpu);
8600
f656ce01 8601 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8602 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8603 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8604 tr->physical_address = gpa;
8605 tr->valid = gpa != UNMAPPED_GVA;
8606 tr->writeable = 1;
8607 tr->usermode = 0;
8b006791 8608
1da5b61d 8609 vcpu_put(vcpu);
8b006791
ZX		 8610 return 0;
8611}
8612
d0752060
HB		 8613int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8614{
1393123e 8615 struct fxregs_state *fxsave;
d0752060 8616
1393123e 8617 vcpu_load(vcpu);
d0752060 8618
b666a4b6 8619 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 8620 memcpy(fpu->fpr, fxsave->st_space, 128);
8621 fpu->fcw = fxsave->cwd;
8622 fpu->fsw = fxsave->swd;
8623 fpu->ftwx = fxsave->twd;
8624 fpu->last_opcode = fxsave->fop;
8625 fpu->last_ip = fxsave->rip;
8626 fpu->last_dp = fxsave->rdp;
0e96f31e 8627 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 8628
1393123e 8629 vcpu_put(vcpu);
d0752060
HB		 8630 return 0;
8631}
8632
8633int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8634{
6a96bc7f
CD		 8635 struct fxregs_state *fxsave;
8636
8637 vcpu_load(vcpu);
8638
b666a4b6 8639 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 8640
d0752060
HB		 8641 memcpy(fxsave->st_space, fpu->fpr, 128);
8642 fxsave->cwd = fpu->fcw;
8643 fxsave->swd = fpu->fsw;
8644 fxsave->twd = fpu->ftwx;
8645 fxsave->fop = fpu->last_opcode;
8646 fxsave->rip = fpu->last_ip;
8647 fxsave->rdp = fpu->last_dp;
0e96f31e 8648 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 8649
6a96bc7f 8650 vcpu_put(vcpu);
d0752060
HB		 8651 return 0;
8652}
8653
01643c51
KH		 8654static void store_regs(struct kvm_vcpu *vcpu)
8655{
8656 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8657
8658 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8659 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8660
8661 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8662 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8663
8664 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8665 kvm_vcpu_ioctl_x86_get_vcpu_events(
8666 vcpu, &vcpu->run->s.regs.events);
8667}
8668
8669static int sync_regs(struct kvm_vcpu *vcpu)
8670{
8671 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8672 return -EINVAL;
8673
8674 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8675 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8676 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8677 }
8678 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8679 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8680 return -EINVAL;
8681 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8682 }
8683 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8684 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8685 vcpu, &vcpu->run->s.regs.events))
8686 return -EINVAL;
8687 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8688 }
8689
8690 return 0;
8691}
8692
0ee6a517 8693static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8694{
b666a4b6 8695 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 8696 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 8697 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 8698 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8699
2acf923e
DC		 8700 /*
8701 * Ensure guest xcr0 is valid for loading
8702 */
d91cab78 8703 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8704
ad312c7c 8705 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8706}
d0752060 8707
e9b11c17
ZX		 8708void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8709{
bd768e14
IY		 8710 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8711
12f9a48f 8712 kvmclock_reset(vcpu);
7f1ea208 8713
e9b11c17 8714 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8715 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8716}
8717
8718struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8719 unsigned int id)
8720{
c447e76b
LL		 8721 struct kvm_vcpu *vcpu;
8722
b0c39dc6 8723 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8724 printk_once(KERN_WARNING
8725 "kvm: SMP vm created on host with unstable TSC; "
8726 "guest TSC will not be reliable\n");
c447e76b
LL		 8727
8728 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8729
c447e76b 8730 return vcpu;
26e5215f 8731}
e9b11c17 8732
26e5215f
AK		 8733int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8734{
e53d88af 8735 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 8736 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8737 vcpu_load(vcpu);
d28bc9dd 8738 kvm_vcpu_reset(vcpu, false);
e1732991 8739 kvm_init_mmu(vcpu, false);
e9b11c17 8740 vcpu_put(vcpu);
ec7660cc 8741 return 0;
e9b11c17
ZX		 8742}
8743
31928aa5 8744void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8745{
8fe8ab46 8746 struct msr_data msr;
332967a3 8747 struct kvm *kvm = vcpu->kvm;
42897d86 8748
d3457c87
RK		 8749 kvm_hv_vcpu_postcreate(vcpu);
8750
ec7660cc 8751 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8752 return;
ec7660cc 8753 vcpu_load(vcpu);
8fe8ab46
WA		 8754 msr.data = 0x0;
8755 msr.index = MSR_IA32_TSC;
8756 msr.host_initiated = true;
8757 kvm_write_tsc(vcpu, &msr);
42897d86 8758 vcpu_put(vcpu);
ec7660cc 8759 mutex_unlock(&vcpu->mutex);
42897d86 8760
630994b3
MT		 8761 if (!kvmclock_periodic_sync)
8762 return;
8763
332967a3
AJ		 8764 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8765 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8766}
8767
d40ccc62 8768void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8769{
344d9588
GN		 8770 vcpu->arch.apf.msr_val = 0;
8771
ec7660cc 8772 vcpu_load(vcpu);
e9b11c17
ZX		 8773 kvm_mmu_unload(vcpu);
8774 vcpu_put(vcpu);
8775
8776 kvm_x86_ops->vcpu_free(vcpu);
8777}
8778
d28bc9dd 8779void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8780{
b7e31be3
RK		 8781 kvm_lapic_reset(vcpu, init_event);
8782
e69fab5d
PB		 8783 vcpu->arch.hflags = 0;
8784
c43203ca 8785 vcpu->arch.smi_pending = 0;
52797bf9 8786 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8787 atomic_set(&vcpu->arch.nmi_queued, 0);
8788 vcpu->arch.nmi_pending = 0;
448fa4a9 8789 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8790 kvm_clear_interrupt_queue(vcpu);
8791 kvm_clear_exception_queue(vcpu);
664f8e26 8792 vcpu->arch.exception.pending = false;
448fa4a9 8793
42dbaa5a 8794 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8795 kvm_update_dr0123(vcpu);
6f43ed01 8796 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8797 kvm_update_dr6(vcpu);
42dbaa5a 8798 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8799 kvm_update_dr7(vcpu);
42dbaa5a 8800
1119022c
NA		 8801 vcpu->arch.cr2 = 0;
8802
3842d135 8803 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8804 vcpu->arch.apf.msr_val = 0;
c9aaa895 8805 vcpu->arch.st.msr_val = 0;
3842d135 8806
12f9a48f
GC		 8807 kvmclock_reset(vcpu);
8808
af585b92
GN		 8809 kvm_clear_async_pf_completion_queue(vcpu);
8810 kvm_async_pf_hash_reset(vcpu);
8811 vcpu->arch.apf.halted = false;
3842d135 8812
a554d207
WL		 8813 if (kvm_mpx_supported()) {
8814 void *mpx_state_buffer;
8815
8816 /*
8817 * To avoid have the INIT path from kvm_apic_has_events() that be
8818 * called with loaded FPU and does not let userspace fix the state.
8819 */
f775b13e
RR		 8820 if (init_event)
8821 kvm_put_guest_fpu(vcpu);
b666a4b6 8822 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
a554d207
WL		 8823 XFEATURE_MASK_BNDREGS);
8824 if (mpx_state_buffer)
8825 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 8826 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
a554d207
WL		 8827 XFEATURE_MASK_BNDCSR);
8828 if (mpx_state_buffer)
8829 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8830 if (init_event)
8831 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8832 }
8833
64d60670 8834 if (!init_event) {
d28bc9dd 8835 kvm_pmu_reset(vcpu);
64d60670 8836 vcpu->arch.smbase = 0x30000;
db2336a8 8837
db2336a8 8838 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8839
8840 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8841 }
f5132b01 8842
66f7b72e
JS		 8843 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8844 vcpu->arch.regs_avail = ~0;
8845 vcpu->arch.regs_dirty = ~0;
8846
a554d207
WL		 8847 vcpu->arch.ia32_xss = 0;
8848
d28bc9dd 8849 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8850}
8851
2b4a273b 8852void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8853{
8854 struct kvm_segment cs;
8855
8856 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8857 cs.selector = vector << 8;
8858 cs.base = vector << 12;
8859 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8860 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8861}
8862
13a34e06 8863int kvm_arch_hardware_enable(void)
e9b11c17 8864{
ca84d1a2
ZA		 8865 struct kvm *kvm;
8866 struct kvm_vcpu *vcpu;
8867 int i;
0dd6a6ed
ZA		 8868 int ret;
8869 u64 local_tsc;
8870 u64 max_tsc = 0;
8871 bool stable, backwards_tsc = false;
18863bdd
AK		 8872
8873 kvm_shared_msr_cpu_online();
13a34e06 8874 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8875 if (ret != 0)
8876 return ret;
8877
4ea1636b 8878 local_tsc = rdtsc();
b0c39dc6 8879 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8880 list_for_each_entry(kvm, &vm_list, vm_list) {
8881 kvm_for_each_vcpu(i, vcpu, kvm) {
8882 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8883 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8884 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8885 backwards_tsc = true;
8886 if (vcpu->arch.last_host_tsc > max_tsc)
8887 max_tsc = vcpu->arch.last_host_tsc;
8888 }
8889 }
8890 }
8891
8892 /*
8893 * Sometimes, even reliable TSCs go backwards. This happens on
8894 * platforms that reset TSC during suspend or hibernate actions, but
8895 * maintain synchronization. We must compensate. Fortunately, we can
8896 * detect that condition here, which happens early in CPU bringup,
8897 * before any KVM threads can be running. Unfortunately, we can't
8898 * bring the TSCs fully up to date with real time, as we aren't yet far
8899 * enough into CPU bringup that we know how much real time has actually
108b249c 8900 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8901 * variables that haven't been updated yet.
8902 *
8903 * So we simply find the maximum observed TSC above, then record the
8904 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8905 * the adjustment will be applied. Note that we accumulate
8906 * adjustments, in case multiple suspend cycles happen before some VCPU
8907 * gets a chance to run again. In the event that no KVM threads get a
8908 * chance to run, we will miss the entire elapsed period, as we'll have
8909 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8910 * loose cycle time. This isn't too big a deal, since the loss will be
8911 * uniform across all VCPUs (not to mention the scenario is extremely
8912 * unlikely). It is possible that a second hibernate recovery happens
8913 * much faster than a first, causing the observed TSC here to be
8914 * smaller; this would require additional padding adjustment, which is
8915 * why we set last_host_tsc to the local tsc observed here.
8916 *
8917 * N.B. - this code below runs only on platforms with reliable TSC,
8918 * as that is the only way backwards_tsc is set above. Also note
8919 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8920 * have the same delta_cyc adjustment applied if backwards_tsc
8921 * is detected. Note further, this adjustment is only done once,
8922 * as we reset last_host_tsc on all VCPUs to stop this from being
8923 * called multiple times (one for each physical CPU bringup).
8924 *
4a969980 8925 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8926 * will be compensated by the logic in vcpu_load, which sets the TSC to
8927 * catchup mode. This will catchup all VCPUs to real time, but cannot
8928 * guarantee that they stay in perfect synchronization.
8929 */
8930 if (backwards_tsc) {
8931 u64 delta_cyc = max_tsc - local_tsc;
8932 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8933 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8934 kvm_for_each_vcpu(i, vcpu, kvm) {
8935 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8936 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8937 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8938 }
8939
8940 /*
8941 * We have to disable TSC offset matching.. if you were
8942 * booting a VM while issuing an S4 host suspend....
8943 * you may have some problem. Solving this issue is
8944 * left as an exercise to the reader.
8945 */
8946 kvm->arch.last_tsc_nsec = 0;
8947 kvm->arch.last_tsc_write = 0;
8948 }
8949
8950 }
8951 return 0;
e9b11c17
ZX		 8952}
8953
13a34e06 8954void kvm_arch_hardware_disable(void)
e9b11c17 8955{
13a34e06
RK		 8956 kvm_x86_ops->hardware_disable();
8957 drop_user_return_notifiers();
e9b11c17
ZX		 8958}
8959
8960int kvm_arch_hardware_setup(void)
8961{
9e9c3fe4
NA		 8962 int r;
8963
8964 r = kvm_x86_ops->hardware_setup();
8965 if (r != 0)
8966 return r;
8967
35181e86
HZ		 8968 if (kvm_has_tsc_control) {
8969 /*
8970 * Make sure the user can only configure tsc_khz values that
8971 * fit into a signed integer.
273ba457 8972 * A min value is not calculated because it will always
35181e86
HZ		 8973 * be 1 on all machines.
8974 */
8975 u64 max = min(0x7fffffffULL,
8976 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8977 kvm_max_guest_tsc_khz = max;
8978
ad721883 8979 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8980 }
ad721883 8981
9e9c3fe4
NA		 8982 kvm_init_msr_list();
8983 return 0;
e9b11c17
ZX		 8984}
8985
8986void kvm_arch_hardware_unsetup(void)
8987{
8988 kvm_x86_ops->hardware_unsetup();
8989}
8990
8991void kvm_arch_check_processor_compat(void *rtn)
8992{
8993 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8994}
8995
8996bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8997{
8998 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8999}
9000EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9001
9002bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9003{
9004 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 9005}
9006
54e9818f 9007struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 9008EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 9009
e9b11c17
ZX		 9010int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9011{
9012 struct page *page;
e9b11c17
ZX		 9013 int r;
9014
9aabc88f 9015 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 9016 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 9017 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 9018 else
a4535290 9019 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 9020
9021 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9022 if (!page) {
9023 r = -ENOMEM;
9024 goto fail;
9025 }
ad312c7c 9026 vcpu->arch.pio_data = page_address(page);
e9b11c17 9027
cc578287 9028 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 9029
e9b11c17
ZX		 9030 r = kvm_mmu_create(vcpu);
9031 if (r < 0)
9032 goto fail_free_pio_data;
9033
26de7988 9034 if (irqchip_in_kernel(vcpu->kvm)) {
f7589cca 9035 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
e9b11c17
ZX		 9036 r = kvm_create_lapic(vcpu);
9037 if (r < 0)
9038 goto fail_mmu_destroy;
54e9818f
GN		 9039 } else
9040 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 9041
890ca9ae
HY		 9042 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9043 GFP_KERNEL);
9044 if (!vcpu->arch.mce_banks) {
9045 r = -ENOMEM;
443c39bc 9046 goto fail_free_lapic;
890ca9ae
HY		 9047 }
9048 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9049
f1797359
WY		 9050 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
9051 r = -ENOMEM;
f5f48ee1 9052 goto fail_free_mce_banks;
f1797359 9053 }
f5f48ee1 9054
0ee6a517 9055 fx_init(vcpu);
66f7b72e 9056
4344ee98 9057 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 9058
5a4f55cd
EK		 9059 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9060
74545705
RK		 9061 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9062
af585b92 9063 kvm_async_pf_hash_reset(vcpu);
f5132b01 9064 kvm_pmu_init(vcpu);
af585b92 9065
1c1a9ce9 9066 vcpu->arch.pending_external_vector = -1;
de63ad4c 9067 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 9068
5c919412
AS		 9069 kvm_hv_vcpu_init(vcpu);
9070
e9b11c17 9071 return 0;
0ee6a517 9072
f5f48ee1
SY		 9073fail_free_mce_banks:
9074 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 9075fail_free_lapic:
9076 kvm_free_lapic(vcpu);
e9b11c17
ZX		 9077fail_mmu_destroy:
9078 kvm_mmu_destroy(vcpu);
9079fail_free_pio_data:
ad312c7c 9080 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 9081fail:
9082 return r;
9083}
9084
9085void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9086{
f656ce01
MT		 9087 int idx;
9088
1f4b34f8 9089 kvm_hv_vcpu_uninit(vcpu);
f5132b01 9090 kvm_pmu_destroy(vcpu);
36cb93fd 9091 kfree(vcpu->arch.mce_banks);
e9b11c17 9092 kvm_free_lapic(vcpu);
f656ce01 9093 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 9094 kvm_mmu_destroy(vcpu);
f656ce01 9095 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 9096 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 9097 if (!lapic_in_kernel(vcpu))
54e9818f 9098 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 9099}
d19a9cd2 9100
e790d9ef
RK		 9101void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9102{
c595ceee 9103 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 9104 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9105}
9106
e08b9637 9107int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9108{
e08b9637
CO		 9109 if (type)
9110 return -EINVAL;
9111
6ef768fa 9112 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9113 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 9114 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 9115 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9116 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9117
5550af4d
SY		 9118 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9119 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9120 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9121 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9122 &kvm->arch.irq_sources_bitmap);
5550af4d 9123
038f8c11 9124 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9125 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9126 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9127
108b249c 9128 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 9129 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9130
6fbbde9a
DS		 9131 kvm->arch.guest_can_read_msr_platform_info = true;
9132
7e44e449 9133 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9134 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9135
cbc0236a 9136 kvm_hv_init_vm(kvm);
0eb05bf2 9137 kvm_page_track_init(kvm);
13d268ca 9138 kvm_mmu_init_vm(kvm);
0eb05bf2 9139
03543133
SS		 9140 if (kvm_x86_ops->vm_init)
9141 return kvm_x86_ops->vm_init(kvm);
9142
d89f5eff 9143 return 0;
d19a9cd2
ZX		 9144}
9145
9146static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9147{
ec7660cc 9148 vcpu_load(vcpu);
d19a9cd2
ZX		 9149 kvm_mmu_unload(vcpu);
9150 vcpu_put(vcpu);
9151}
9152
9153static void kvm_free_vcpus(struct kvm *kvm)
9154{
9155 unsigned int i;
988a2cae 9156 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9157
9158 /*
9159 * Unpin any mmu pages first.
9160 */
af585b92
GN		 9161 kvm_for_each_vcpu(i, vcpu, kvm) {
9162 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9163 kvm_unload_vcpu_mmu(vcpu);
af585b92 9164 }
988a2cae
GN		 9165 kvm_for_each_vcpu(i, vcpu, kvm)
9166 kvm_arch_vcpu_free(vcpu);
9167
9168 mutex_lock(&kvm->lock);
9169 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9170 kvm->vcpus[i] = NULL;
d19a9cd2 9171
988a2cae
GN		 9172 atomic_set(&kvm->online_vcpus, 0);
9173 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9174}
9175
ad8ba2cd
SY		 9176void kvm_arch_sync_events(struct kvm *kvm)
9177{
332967a3 9178 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9179 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9180 kvm_free_pit(kvm);
ad8ba2cd
SY		 9181}
9182
1d8007bd 9183int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9184{
9185 int i, r;
25188b99 9186 unsigned long hva;
f0d648bd
PB		 9187 struct kvm_memslots *slots = kvm_memslots(kvm);
9188 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9189
9190 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9191 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9192 return -EINVAL;
9da0e4d5 9193
f0d648bd
PB		 9194 slot = id_to_memslot(slots, id);
9195 if (size) {
b21629da 9196 if (slot->npages)
f0d648bd
PB		 9197 return -EEXIST;
9198
9199 /*
9200 * MAP_SHARED to prevent internal slot pages from being moved
9201 * by fork()/COW.
9202 */
9203 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9204 MAP_SHARED | MAP_ANONYMOUS, 0);
9205 if (IS_ERR((void *)hva))
9206 return PTR_ERR((void *)hva);
9207 } else {
9208 if (!slot->npages)
9209 return 0;
9210
9211 hva = 0;
9212 }
9213
9214 old = *slot;
9da0e4d5 9215 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9216 struct kvm_userspace_memory_region m;
9da0e4d5 9217
1d8007bd
PB		 9218 m.slot = id | (i << 16);
9219 m.flags = 0;
9220 m.guest_phys_addr = gpa;
f0d648bd 9221 m.userspace_addr = hva;
1d8007bd 9222 m.memory_size = size;
9da0e4d5
PB		 9223 r = __kvm_set_memory_region(kvm, &m);
9224 if (r < 0)
9225 return r;
9226 }
9227
103c763c
EB		 9228 if (!size)
9229 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9230
9da0e4d5
PB		 9231 return 0;
9232}
9233EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9234
1d8007bd 9235int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9236{
9237 int r;
9238
9239 mutex_lock(&kvm->slots_lock);
1d8007bd 9240 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9241 mutex_unlock(&kvm->slots_lock);
9242
9243 return r;
9244}
9245EXPORT_SYMBOL_GPL(x86_set_memory_region);
9246
d19a9cd2
ZX		 9247void kvm_arch_destroy_vm(struct kvm *kvm)
9248{
27469d29
AH		 9249 if (current->mm == kvm->mm) {
9250 /*
9251 * Free memory regions allocated on behalf of userspace,
9252 * unless the the memory map has changed due to process exit
9253 * or fd copying.
9254 */
1d8007bd
PB		 9255 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9256 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9257 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9258 }
03543133
SS		 9259 if (kvm_x86_ops->vm_destroy)
9260 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9261 kvm_pic_destroy(kvm);
9262 kvm_ioapic_destroy(kvm);
d19a9cd2 9263 kvm_free_vcpus(kvm);
af1bae54 9264 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 9265 kvm_mmu_uninit_vm(kvm);
2beb6dad 9266 kvm_page_track_cleanup(kvm);
cbc0236a 9267 kvm_hv_destroy_vm(kvm);
d19a9cd2 9268}
0de10343 9269
5587027c 9270void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9271 struct kvm_memory_slot *dont)
9272{
9273 int i;
9274
d89cc617
TY		 9275 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9276 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9277 kvfree(free->arch.rmap[i]);
d89cc617 9278 free->arch.rmap[i] = NULL;
77d11309 9279 }
d89cc617
TY		 9280 if (i == 0)
9281 continue;
9282
9283 if (!dont || free->arch.lpage_info[i - 1] !=
9284 dont->arch.lpage_info[i - 1]) {
548ef284 9285 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9286 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9287 }
9288 }
21ebbeda
XG		 9289
9290 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9291}
9292
5587027c
AK		 9293int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9294 unsigned long npages)
db3fe4eb
TY		 9295{
9296 int i;
9297
d89cc617 9298 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9299 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9300 unsigned long ugfn;
9301 int lpages;
d89cc617 9302 int level = i + 1;
db3fe4eb
TY		 9303
9304 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9305 slot->base_gfn, level) + 1;
9306
d89cc617 9307 slot->arch.rmap[i] =
778e1cdd
KC		 9308 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9309 GFP_KERNEL);
d89cc617 9310 if (!slot->arch.rmap[i])
77d11309 9311 goto out_free;
d89cc617
TY		 9312 if (i == 0)
9313 continue;
77d11309 9314
778e1cdd 9315 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
92f94f1e 9316 if (!linfo)
db3fe4eb
TY		 9317 goto out_free;
9318
92f94f1e
XG		 9319 slot->arch.lpage_info[i - 1] = linfo;
9320
db3fe4eb 9321 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9322 linfo[0].disallow_lpage = 1;
db3fe4eb 9323 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9324 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9325 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9326 /*
9327 * If the gfn and userspace address are not aligned wrt each
9328 * other, or if explicitly asked to, disable large page
9329 * support for this slot
9330 */
9331 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9332 !kvm_largepages_enabled()) {
9333 unsigned long j;
9334
9335 for (j = 0; j < lpages; ++j)
92f94f1e 9336 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9337 }
9338 }
9339
21ebbeda
XG		 9340 if (kvm_page_track_create_memslot(slot, npages))
9341 goto out_free;
9342
db3fe4eb
TY		 9343 return 0;
9344
9345out_free:
d89cc617 9346 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9347 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9348 slot->arch.rmap[i] = NULL;
9349 if (i == 0)
9350 continue;
9351
548ef284 9352 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9353 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9354 }
9355 return -ENOMEM;
9356}
9357
15f46015 9358void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 9359{
e6dff7d1
TY		 9360 /*
9361 * memslots->generation has been incremented.
9362 * mmio generation may have reached its maximum value.
9363 */
54bf36aa 9364 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 9365}
9366
f7784b8e
MT		 9367int kvm_arch_prepare_memory_region(struct kvm *kvm,
9368 struct kvm_memory_slot *memslot,
09170a49 9369 const struct kvm_userspace_memory_region *mem,
7b6195a9 9370 enum kvm_mr_change change)
0de10343 9371{
f7784b8e
MT		 9372 return 0;
9373}
9374
88178fd4
KH		 9375static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9376 struct kvm_memory_slot *new)
9377{
9378 /* Still write protect RO slot */
9379 if (new->flags & KVM_MEM_READONLY) {
9380 kvm_mmu_slot_remove_write_access(kvm, new);
9381 return;
9382 }
9383
9384 /*
9385 * Call kvm_x86_ops dirty logging hooks when they are valid.
9386 *
9387 * kvm_x86_ops->slot_disable_log_dirty is called when:
9388 *
9389 * - KVM_MR_CREATE with dirty logging is disabled
9390 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9391 *
9392 * The reason is, in case of PML, we need to set D-bit for any slots
9393 * with dirty logging disabled in order to eliminate unnecessary GPA
9394 * logging in PML buffer (and potential PML buffer full VMEXT). This
9395 * guarantees leaving PML enabled during guest's lifetime won't have
bdd303cb 9396 * any additional overhead from PML when guest is running with dirty
88178fd4
KH		 9397 * logging disabled for memory slots.
9398 *
9399 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9400 * to dirty logging mode.
9401 *
9402 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9403 *
9404 * In case of write protect:
9405 *
9406 * Write protect all pages for dirty logging.
9407 *
9408 * All the sptes including the large sptes which point to this
9409 * slot are set to readonly. We can not create any new large
9410 * spte on this slot until the end of the logging.
9411 *
9412 * See the comments in fast_page_fault().
9413 */
9414 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9415 if (kvm_x86_ops->slot_enable_log_dirty)
9416 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9417 else
9418 kvm_mmu_slot_remove_write_access(kvm, new);
9419 } else {
9420 if (kvm_x86_ops->slot_disable_log_dirty)
9421 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9422 }
9423}
9424
f7784b8e 9425void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9426 const struct kvm_userspace_memory_region *mem,
8482644a 9427 const struct kvm_memory_slot *old,
f36f3f28 9428 const struct kvm_memory_slot *new,
8482644a 9429 enum kvm_mr_change change)
f7784b8e 9430{
8482644a 9431 int nr_mmu_pages = 0;
f7784b8e 9432
48c0e4e9
XG		 9433 if (!kvm->arch.n_requested_mmu_pages)
9434 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9435
48c0e4e9 9436 if (nr_mmu_pages)
0de10343 9437 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9438
3ea3b7fa
WL		 9439 /*
9440 * Dirty logging tracks sptes in 4k granularity, meaning that large
9441 * sptes have to be split. If live migration is successful, the guest
9442 * in the source machine will be destroyed and large sptes will be
9443 * created in the destination. However, if the guest continues to run
9444 * in the source machine (for example if live migration fails), small
9445 * sptes will remain around and cause bad performance.
9446 *
9447 * Scan sptes if dirty logging has been stopped, dropping those
9448 * which can be collapsed into a single large-page spte. Later
9449 * page faults will create the large-page sptes.
9450 */
9451 if ((change != KVM_MR_DELETE) &&
9452 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9453 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9454 kvm_mmu_zap_collapsible_sptes(kvm, new);
9455
c972f3b1 9456 /*
88178fd4 9457 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9458 *
88178fd4
KH		 9459 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9460 * been zapped so no dirty logging staff is needed for old slot. For
9461 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9462 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9463 *
9464 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9465 */
88178fd4 9466 if (change != KVM_MR_DELETE)
f36f3f28 9467 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9468}
1d737c8a 9469
2df72e9b 9470void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9471{
6ca18b69 9472 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9473}
9474
2df72e9b
MT		 9475void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9476 struct kvm_memory_slot *slot)
9477{
ae7cd873 9478 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9479}
9480
e6c67d8c
LA		 9481static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9482{
9483 return (is_guest_mode(vcpu) &&
9484 kvm_x86_ops->guest_apic_has_interrupt &&
9485 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9486}
9487
5d9bc648
PB		 9488static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9489{
9490 if (!list_empty_careful(&vcpu->async_pf.done))
9491 return true;
9492
9493 if (kvm_apic_has_events(vcpu))
9494 return true;
9495
9496 if (vcpu->arch.pv.pv_unhalted)
9497 return true;
9498
a5f01f8e
WL		 9499 if (vcpu->arch.exception.pending)
9500 return true;
9501
47a66eed
Z		 9502 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9503 (vcpu->arch.nmi_pending &&
9504 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9505 return true;
9506
47a66eed
Z		 9507 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9508 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9509 return true;
9510
5d9bc648 9511 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9512 (kvm_cpu_has_interrupt(vcpu) ||
9513 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9514 return true;
9515
1f4b34f8
AS		 9516 if (kvm_hv_has_stimer_pending(vcpu))
9517 return true;
9518
5d9bc648
PB		 9519 return false;
9520}
9521
1d737c8a
ZX		 9522int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9523{
5d9bc648 9524 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9525}
5736199a 9526
199b5763
LM		 9527bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9528{
de63ad4c 9529 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9530}
9531
b6d33834 9532int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9533{
b6d33834 9534 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9535}
78646121
GN		 9536
9537int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9538{
9539 return kvm_x86_ops->interrupt_allowed(vcpu);
9540}
229456fc 9541
82b32774 9542unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9543{
82b32774
NA		 9544 if (is_64_bit_mode(vcpu))
9545 return kvm_rip_read(vcpu);
9546 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9547 kvm_rip_read(vcpu));
9548}
9549EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9550
82b32774
NA		 9551bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9552{
9553 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9554}
9555EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9556
94fe45da
JK		 9557unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9558{
9559 unsigned long rflags;
9560
9561 rflags = kvm_x86_ops->get_rflags(vcpu);
9562 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9563 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9564 return rflags;
9565}
9566EXPORT_SYMBOL_GPL(kvm_get_rflags);
9567
6addfc42 9568static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9569{
9570 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9571 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9572 rflags |= X86_EFLAGS_TF;
94fe45da 9573 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9574}
9575
9576void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9577{
9578 __kvm_set_rflags(vcpu, rflags);
3842d135 9579 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9580}
9581EXPORT_SYMBOL_GPL(kvm_set_rflags);
9582
56028d08
GN		 9583void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9584{
9585 int r;
9586
44dd3ffa 9587 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9588 work->wakeup_all)
56028d08
GN		 9589 return;
9590
9591 r = kvm_mmu_reload(vcpu);
9592 if (unlikely(r))
9593 return;
9594
44dd3ffa
VK		 9595 if (!vcpu->arch.mmu->direct_map &&
9596 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9597 return;
9598
44dd3ffa 9599 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9600}
9601
af585b92
GN		 9602static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9603{
9604 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9605}
9606
9607static inline u32 kvm_async_pf_next_probe(u32 key)
9608{
9609 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9610}
9611
9612static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9613{
9614 u32 key = kvm_async_pf_hash_fn(gfn);
9615
9616 while (vcpu->arch.apf.gfns[key] != ~0)
9617 key = kvm_async_pf_next_probe(key);
9618
9619 vcpu->arch.apf.gfns[key] = gfn;
9620}
9621
9622static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9623{
9624 int i;
9625 u32 key = kvm_async_pf_hash_fn(gfn);
9626
9627 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9628 (vcpu->arch.apf.gfns[key] != gfn &&
9629 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9630 key = kvm_async_pf_next_probe(key);
9631
9632 return key;
9633}
9634
9635bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9636{
9637 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9638}
9639
9640static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9641{
9642 u32 i, j, k;
9643
9644 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9645 while (true) {
9646 vcpu->arch.apf.gfns[i] = ~0;
9647 do {
9648 j = kvm_async_pf_next_probe(j);
9649 if (vcpu->arch.apf.gfns[j] == ~0)
9650 return;
9651 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9652 /*
9653 * k lies cyclically in ]i,j]
9654 * | i.k.j |
9655 * |....j i.k.| or |.k..j i...|
9656 */
9657 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9658 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9659 i = j;
9660 }
9661}
9662
7c90705b
GN		 9663static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9664{
4e335d9e
PB		 9665
9666 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9667 sizeof(val));
7c90705b
GN		 9668}
9669
9a6e7c39
WL		 9670static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9671{
9672
9673 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9674 sizeof(u32));
9675}
9676
af585b92
GN		 9677void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9678 struct kvm_async_pf *work)
9679{
6389ee94
AK		 9680 struct x86_exception fault;
9681
7c90705b 9682 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9683 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9684
9685 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9686 (vcpu->arch.apf.send_user_only &&
9687 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9688 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9689 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9690 fault.vector = PF_VECTOR;
9691 fault.error_code_valid = true;
9692 fault.error_code = 0;
9693 fault.nested_page_fault = false;
9694 fault.address = work->arch.token;
adfe20fb 9695 fault.async_page_fault = true;
6389ee94 9696 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9697 }
af585b92
GN		 9698}
9699
9700void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9701 struct kvm_async_pf *work)
9702{
6389ee94 9703 struct x86_exception fault;
9a6e7c39 9704 u32 val;
6389ee94 9705
f2e10669 9706 if (work->wakeup_all)
7c90705b
GN		 9707 work->arch.token = ~0; /* broadcast wakeup */
9708 else
9709 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9710 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9711
9a6e7c39
WL		 9712 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9713 !apf_get_user(vcpu, &val)) {
9714 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9715 vcpu->arch.exception.pending &&
9716 vcpu->arch.exception.nr == PF_VECTOR &&
9717 !apf_put_user(vcpu, 0)) {
9718 vcpu->arch.exception.injected = false;
9719 vcpu->arch.exception.pending = false;
9720 vcpu->arch.exception.nr = 0;
9721 vcpu->arch.exception.has_error_code = false;
9722 vcpu->arch.exception.error_code = 0;
c851436a
JM		 9723 vcpu->arch.exception.has_payload = false;
9724 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 9725 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9726 fault.vector = PF_VECTOR;
9727 fault.error_code_valid = true;
9728 fault.error_code = 0;
9729 fault.nested_page_fault = false;
9730 fault.address = work->arch.token;
9731 fault.async_page_fault = true;
9732 kvm_inject_page_fault(vcpu, &fault);
9733 }
7c90705b 9734 }
e6d53e3b 9735 vcpu->arch.apf.halted = false;
a4fa1635 9736 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9737}
9738
9739bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9740{
9741 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9742 return true;
9743 else
9bc1f09f 9744 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9745}
9746
5544eb9b
PB		 9747void kvm_arch_start_assignment(struct kvm *kvm)
9748{
9749 atomic_inc(&kvm->arch.assigned_device_count);
9750}
9751EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9752
9753void kvm_arch_end_assignment(struct kvm *kvm)
9754{
9755 atomic_dec(&kvm->arch.assigned_device_count);
9756}
9757EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9758
9759bool kvm_arch_has_assigned_device(struct kvm *kvm)
9760{
9761 return atomic_read(&kvm->arch.assigned_device_count);
9762}
9763EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9764
e0f0bbc5
AW		 9765void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9766{
9767 atomic_inc(&kvm->arch.noncoherent_dma_count);
9768}
9769EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9770
9771void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9772{
9773 atomic_dec(&kvm->arch.noncoherent_dma_count);
9774}
9775EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9776
9777bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9778{
9779 return atomic_read(&kvm->arch.noncoherent_dma_count);
9780}
9781EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9782
14717e20
AW		 9783bool kvm_arch_has_irq_bypass(void)
9784{
9785 return kvm_x86_ops->update_pi_irte != NULL;
9786}
9787
87276880
FW		 9788int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9789 struct irq_bypass_producer *prod)
9790{
9791 struct kvm_kernel_irqfd *irqfd =
9792 container_of(cons, struct kvm_kernel_irqfd, consumer);
9793
14717e20 9794 irqfd->producer = prod;
87276880 9795
14717e20
AW		 9796 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9797 prod->irq, irqfd->gsi, 1);
87276880
FW		 9798}
9799
9800void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9801 struct irq_bypass_producer *prod)
9802{
9803 int ret;
9804 struct kvm_kernel_irqfd *irqfd =
9805 container_of(cons, struct kvm_kernel_irqfd, consumer);
9806
87276880
FW		 9807 WARN_ON(irqfd->producer != prod);
9808 irqfd->producer = NULL;
9809
9810 /*
9811 * When producer of consumer is unregistered, we change back to
9812 * remapped mode, so we can re-use the current implementation
bb3541f1 9813 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9814 * int this case doesn't want to receive the interrupts.
9815 */
9816 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9817 if (ret)
9818 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9819 " fails: %d\n", irqfd->consumer.token, ret);
9820}
9821
9822int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9823 uint32_t guest_irq, bool set)
9824{
9825 if (!kvm_x86_ops->update_pi_irte)
9826 return -EINVAL;
9827
9828 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9829}
9830
52004014
FW		 9831bool kvm_vector_hashing_enabled(void)
9832{
9833 return vector_hashing;
9834}
9835EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9836
229456fc 9837EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9838EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9839EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9840EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9841EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9842EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9843EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9844EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9845EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9846EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9847EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9848EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9849EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9850EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9851EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9852EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9853EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9854EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9855EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)