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x86/kvm: Pass stable clocksource to guests when running nested on Hyper-V
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
043405e1 71
d1898b73
DH		 72#define CREATE_TRACE_POINTS
73#include "trace.h"
74
313a3dc7 75#define MAX_IO_MSRS 256
890ca9ae 76#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 77u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
78EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 79
0f65dd70
AK		 80#define emul_to_vcpu(ctxt) \
81 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
82
50a37eb4
JR		 83/* EFER defaults:
84 * - enable syscall per default because its emulated by KVM
85 * - enable LME and LMA per default on 64 bit KVM
86 */
87#ifdef CONFIG_X86_64
1260edbe
LJ		 88static
89u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 90#else
1260edbe 91static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 92#endif
313a3dc7 93
ba1389b7
AK		 94#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
95#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 96
c519265f
RK		 97#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
98 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 99
cb142eb7 100static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 101static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 102static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 103static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 104
893590c7 105struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 106EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 107
893590c7 108static bool __read_mostly ignore_msrs = 0;
476bc001 109module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 110
fab0aa3b
EM		 111static bool __read_mostly report_ignored_msrs = true;
112module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
113
9ed96e87
MT		 114unsigned int min_timer_period_us = 500;
115module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
116
630994b3
MT		 117static bool __read_mostly kvmclock_periodic_sync = true;
118module_param(kvmclock_periodic_sync, bool, S_IRUGO);
119
893590c7 120bool __read_mostly kvm_has_tsc_control;
92a1f12d 121EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 122u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 123EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 124u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
125EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
126u64 __read_mostly kvm_max_tsc_scaling_ratio;
127EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 128u64 __read_mostly kvm_default_tsc_scaling_ratio;
129EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 130
cc578287 131/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 132static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 133module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
134
d0659d94 135/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 136unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 137module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
138
52004014
FW		 139static bool __read_mostly vector_hashing = true;
140module_param(vector_hashing, bool, S_IRUGO);
141
18863bdd
AK		 142#define KVM_NR_SHARED_MSRS 16
143
144struct kvm_shared_msrs_global {
145 int nr;
2bf78fa7 146 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 147};
148
149struct kvm_shared_msrs {
150 struct user_return_notifier urn;
151 bool registered;
2bf78fa7
SY		 152 struct kvm_shared_msr_values {
153 u64 host;
154 u64 curr;
155 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 156};
157
158static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 159static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 160
417bc304 161struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 162 { "pf_fixed", VCPU_STAT(pf_fixed) },
163 { "pf_guest", VCPU_STAT(pf_guest) },
164 { "tlb_flush", VCPU_STAT(tlb_flush) },
165 { "invlpg", VCPU_STAT(invlpg) },
166 { "exits", VCPU_STAT(exits) },
167 { "io_exits", VCPU_STAT(io_exits) },
168 { "mmio_exits", VCPU_STAT(mmio_exits) },
169 { "signal_exits", VCPU_STAT(signal_exits) },
170 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 171 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 172 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 173 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 174 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 175 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 176 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 177 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 178 { "request_irq", VCPU_STAT(request_irq_exits) },
179 { "irq_exits", VCPU_STAT(irq_exits) },
180 { "host_state_reload", VCPU_STAT(host_state_reload) },
181 { "efer_reload", VCPU_STAT(efer_reload) },
182 { "fpu_reload", VCPU_STAT(fpu_reload) },
183 { "insn_emulation", VCPU_STAT(insn_emulation) },
184 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 185 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 186 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 187 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 188 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
189 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
190 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
191 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
192 { "mmu_flooded", VM_STAT(mmu_flooded) },
193 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 194 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 195 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 196 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 197 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 198 { "max_mmu_page_hash_collisions",
199 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 200 { NULL }
201};
202
2acf923e
DC		 203u64 __read_mostly host_xcr0;
204
b6785def 205static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 206
af585b92
GN		 207static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
208{
209 int i;
210 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
211 vcpu->arch.apf.gfns[i] = ~0;
212}
213
18863bdd
AK		 214static void kvm_on_user_return(struct user_return_notifier *urn)
215{
216 unsigned slot;
18863bdd
AK		 217 struct kvm_shared_msrs *locals
218 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 219 struct kvm_shared_msr_values *values;
1650b4eb
IA		 220 unsigned long flags;
221
222 /*
223 * Disabling irqs at this point since the following code could be
224 * interrupted and executed through kvm_arch_hardware_disable()
225 */
226 local_irq_save(flags);
227 if (locals->registered) {
228 locals->registered = false;
229 user_return_notifier_unregister(urn);
230 }
231 local_irq_restore(flags);
18863bdd 232 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 233 values = &locals->values[slot];
234 if (values->host != values->curr) {
235 wrmsrl(shared_msrs_global.msrs[slot], values->host);
236 values->curr = values->host;
18863bdd
AK		 237 }
238 }
18863bdd
AK		 239}
240
2bf78fa7 241static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 242{
18863bdd 243 u64 value;
013f6a5d
MT		 244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 246
2bf78fa7
SY		 247 /* only read, and nobody should modify it at this time,
248 * so don't need lock */
249 if (slot >= shared_msrs_global.nr) {
250 printk(KERN_ERR "kvm: invalid MSR slot!");
251 return;
252 }
253 rdmsrl_safe(msr, &value);
254 smsr->values[slot].host = value;
255 smsr->values[slot].curr = value;
256}
257
258void kvm_define_shared_msr(unsigned slot, u32 msr)
259{
0123be42 260 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 261 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 262 if (slot >= shared_msrs_global.nr)
263 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 264}
265EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
266
267static void kvm_shared_msr_cpu_online(void)
268{
269 unsigned i;
18863bdd
AK		 270
271 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 272 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 273}
274
8b3c3104 275int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 276{
013f6a5d
MT		 277 unsigned int cpu = smp_processor_id();
278 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 279 int err;
18863bdd 280
2bf78fa7 281 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 282 return 0;
2bf78fa7 283 smsr->values[slot].curr = value;
8b3c3104
AH		 284 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
285 if (err)
286 return 1;
287
18863bdd
AK		 288 if (!smsr->registered) {
289 smsr->urn.on_user_return = kvm_on_user_return;
290 user_return_notifier_register(&smsr->urn);
291 smsr->registered = true;
292 }
8b3c3104 293 return 0;
18863bdd
AK		 294}
295EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
296
13a34e06 297static void drop_user_return_notifiers(void)
3548bab5 298{
013f6a5d
MT		 299 unsigned int cpu = smp_processor_id();
300 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 301
302 if (smsr->registered)
303 kvm_on_user_return(&smsr->urn);
304}
305
6866b83e
CO		 306u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
307{
8a5a87d9 308 return vcpu->arch.apic_base;
6866b83e
CO		 309}
310EXPORT_SYMBOL_GPL(kvm_get_apic_base);
311
58cb628d
JK		 312int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
313{
314 u64 old_state = vcpu->arch.apic_base &
315 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
316 u64 new_state = msr_info->data &
317 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 318 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
319 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 320
d3802286
JM		 321 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
322 return 1;
58cb628d 323 if (!msr_info->host_initiated &&
d3802286 324 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 325 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
326 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
327 old_state == 0)))
328 return 1;
329
330 kvm_lapic_set_base(vcpu, msr_info->data);
331 return 0;
6866b83e
CO		 332}
333EXPORT_SYMBOL_GPL(kvm_set_apic_base);
334
2605fc21 335asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 336{
337 /* Fault while not rebooting. We want the trace. */
338 BUG();
339}
340EXPORT_SYMBOL_GPL(kvm_spurious_fault);
341
3fd28fce
ED		 342#define EXCPT_BENIGN 0
343#define EXCPT_CONTRIBUTORY 1
344#define EXCPT_PF 2
345
346static int exception_class(int vector)
347{
348 switch (vector) {
349 case PF_VECTOR:
350 return EXCPT_PF;
351 case DE_VECTOR:
352 case TS_VECTOR:
353 case NP_VECTOR:
354 case SS_VECTOR:
355 case GP_VECTOR:
356 return EXCPT_CONTRIBUTORY;
357 default:
358 break;
359 }
360 return EXCPT_BENIGN;
361}
362
d6e8c854
NA		 363#define EXCPT_FAULT 0
364#define EXCPT_TRAP 1
365#define EXCPT_ABORT 2
366#define EXCPT_INTERRUPT 3
367
368static int exception_type(int vector)
369{
370 unsigned int mask;
371
372 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
373 return EXCPT_INTERRUPT;
374
375 mask = 1 << vector;
376
377 /* #DB is trap, as instruction watchpoints are handled elsewhere */
378 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
379 return EXCPT_TRAP;
380
381 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
382 return EXCPT_ABORT;
383
384 /* Reserved exceptions will result in fault */
385 return EXCPT_FAULT;
386}
387
3fd28fce 388static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 389 unsigned nr, bool has_error, u32 error_code,
390 bool reinject)
3fd28fce
ED		 391{
392 u32 prev_nr;
393 int class1, class2;
394
3842d135
AK		 395 kvm_make_request(KVM_REQ_EVENT, vcpu);
396
664f8e26 397 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 398 queue:
3ffb2468
NA		 399 if (has_error && !is_protmode(vcpu))
400 has_error = false;
664f8e26
WL		 401 if (reinject) {
402 /*
403 * On vmentry, vcpu->arch.exception.pending is only
404 * true if an event injection was blocked by
405 * nested_run_pending. In that case, however,
406 * vcpu_enter_guest requests an immediate exit,
407 * and the guest shouldn't proceed far enough to
408 * need reinjection.
409 */
410 WARN_ON_ONCE(vcpu->arch.exception.pending);
411 vcpu->arch.exception.injected = true;
412 } else {
413 vcpu->arch.exception.pending = true;
414 vcpu->arch.exception.injected = false;
415 }
3fd28fce
ED		 416 vcpu->arch.exception.has_error_code = has_error;
417 vcpu->arch.exception.nr = nr;
418 vcpu->arch.exception.error_code = error_code;
419 return;
420 }
421
422 /* to check exception */
423 prev_nr = vcpu->arch.exception.nr;
424 if (prev_nr == DF_VECTOR) {
425 /* triple fault -> shutdown */
a8eeb04a 426 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 427 return;
428 }
429 class1 = exception_class(prev_nr);
430 class2 = exception_class(nr);
431 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
432 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 433 /*
434 * Generate double fault per SDM Table 5-5. Set
435 * exception.pending = true so that the double fault
436 * can trigger a nested vmexit.
437 */
3fd28fce 438 vcpu->arch.exception.pending = true;
664f8e26 439 vcpu->arch.exception.injected = false;
3fd28fce
ED		 440 vcpu->arch.exception.has_error_code = true;
441 vcpu->arch.exception.nr = DF_VECTOR;
442 vcpu->arch.exception.error_code = 0;
443 } else
444 /* replace previous exception with a new one in a hope
445 that instruction re-execution will regenerate lost
446 exception */
447 goto queue;
448}
449
298101da
AK		 450void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
451{
ce7ddec4 452 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 453}
454EXPORT_SYMBOL_GPL(kvm_queue_exception);
455
ce7ddec4
JR		 456void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
457{
458 kvm_multiple_exception(vcpu, nr, false, 0, true);
459}
460EXPORT_SYMBOL_GPL(kvm_requeue_exception);
461
6affcbed 462int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 463{
db8fcefa
AP		 464 if (err)
465 kvm_inject_gp(vcpu, 0);
466 else
6affcbed
KH		 467 return kvm_skip_emulated_instruction(vcpu);
468
469 return 1;
db8fcefa
AP		 470}
471EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 472
6389ee94 473void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 474{
475 ++vcpu->stat.pf_guest;
adfe20fb
WL		 476 vcpu->arch.exception.nested_apf =
477 is_guest_mode(vcpu) && fault->async_page_fault;
478 if (vcpu->arch.exception.nested_apf)
479 vcpu->arch.apf.nested_apf_token = fault->address;
480 else
481 vcpu->arch.cr2 = fault->address;
6389ee94 482 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 483}
27d6c865 484EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 485
ef54bcfe 486static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 487{
6389ee94
AK		 488 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
489 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 490 else
6389ee94 491 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 492
493 return fault->nested_page_fault;
d4f8cf66
JR		 494}
495
3419ffc8
SY		 496void kvm_inject_nmi(struct kvm_vcpu *vcpu)
497{
7460fb4a
AK		 498 atomic_inc(&vcpu->arch.nmi_queued);
499 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 500}
501EXPORT_SYMBOL_GPL(kvm_inject_nmi);
502
298101da
AK		 503void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
504{
ce7ddec4 505 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 506}
507EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
508
ce7ddec4
JR		 509void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
510{
511 kvm_multiple_exception(vcpu, nr, true, error_code, true);
512}
513EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
514
0a79b009
AK		 515/*
516 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
517 * a #GP and return false.
518 */
519bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 520{
0a79b009
AK		 521 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
522 return true;
523 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
524 return false;
298101da 525}
0a79b009 526EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 527
16f8a6f9
NA		 528bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
529{
530 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
531 return true;
532
533 kvm_queue_exception(vcpu, UD_VECTOR);
534 return false;
535}
536EXPORT_SYMBOL_GPL(kvm_require_dr);
537
ec92fe44
JR		 538/*
539 * This function will be used to read from the physical memory of the currently
54bf36aa 540 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 541 * can read from guest physical or from the guest's guest physical memory.
542 */
543int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
544 gfn_t ngfn, void *data, int offset, int len,
545 u32 access)
546{
54987b7a 547 struct x86_exception exception;
ec92fe44
JR		 548 gfn_t real_gfn;
549 gpa_t ngpa;
550
551 ngpa = gfn_to_gpa(ngfn);
54987b7a 552 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 553 if (real_gfn == UNMAPPED_GVA)
554 return -EFAULT;
555
556 real_gfn = gpa_to_gfn(real_gfn);
557
54bf36aa 558 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 559}
560EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
561
69b0049a 562static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 563 void *data, int offset, int len, u32 access)
564{
565 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
566 data, offset, len, access);
567}
568
a03490ed
CO		 569/*
570 * Load the pae pdptrs. Return true is they are all valid.
571 */
ff03a073 572int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 573{
574 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
575 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
576 int i;
577 int ret;
ff03a073 578 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 579
ff03a073
JR		 580 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
581 offset * sizeof(u64), sizeof(pdpte),
582 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 583 if (ret < 0) {
584 ret = 0;
585 goto out;
586 }
587 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 588 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 589 (pdpte[i] &
590 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 591 ret = 0;
592 goto out;
593 }
594 }
595 ret = 1;
596
ff03a073 597 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 598 __set_bit(VCPU_EXREG_PDPTR,
599 (unsigned long *)&vcpu->arch.regs_avail);
600 __set_bit(VCPU_EXREG_PDPTR,
601 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 602out:
a03490ed
CO		 603
604 return ret;
605}
cc4b6871 606EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 607
9ed38ffa 608bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 609{
ff03a073 610 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 611 bool changed = true;
3d06b8bf
JR		 612 int offset;
613 gfn_t gfn;
d835dfec
AK		 614 int r;
615
616 if (is_long_mode(vcpu) || !is_pae(vcpu))
617 return false;
618
6de4f3ad
AK		 619 if (!test_bit(VCPU_EXREG_PDPTR,
620 (unsigned long *)&vcpu->arch.regs_avail))
621 return true;
622
a512177e
PB		 623 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
624 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 625 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
626 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 627 if (r < 0)
628 goto out;
ff03a073 629 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 630out:
d835dfec
AK		 631
632 return changed;
633}
9ed38ffa 634EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 635
49a9b07e 636int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 637{
aad82703 638 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 639 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 640
f9a48e6a
AK		 641 cr0 |= X86_CR0_ET;
642
ab344828 643#ifdef CONFIG_X86_64
0f12244f
GN		 644 if (cr0 & 0xffffffff00000000UL)
645 return 1;
ab344828
GN		 646#endif
647
648 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 649
0f12244f
GN		 650 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
651 return 1;
a03490ed 652
0f12244f
GN		 653 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
654 return 1;
a03490ed
CO		 655
656 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
657#ifdef CONFIG_X86_64
f6801dff 658 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 659 int cs_db, cs_l;
660
0f12244f
GN		 661 if (!is_pae(vcpu))
662 return 1;
a03490ed 663 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 664 if (cs_l)
665 return 1;
a03490ed
CO		 666 } else
667#endif
ff03a073 668 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 669 kvm_read_cr3(vcpu)))
0f12244f 670 return 1;
a03490ed
CO		 671 }
672
ad756a16
MJ		 673 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
674 return 1;
675
a03490ed 676 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 677
d170c419 678 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 679 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 680 kvm_async_pf_hash_reset(vcpu);
681 }
e5f3f027 682
aad82703
SY		 683 if ((cr0 ^ old_cr0) & update_bits)
684 kvm_mmu_reset_context(vcpu);
b18d5431 685
879ae188
LE		 686 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
687 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
688 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 689 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
690
0f12244f
GN		 691 return 0;
692}
2d3ad1f4 693EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 694
2d3ad1f4 695void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 696{
49a9b07e 697 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 698}
2d3ad1f4 699EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 700
42bdf991
MT		 701static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
702{
703 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
704 !vcpu->guest_xcr0_loaded) {
705 /* kvm_set_xcr() also depends on this */
706 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
707 vcpu->guest_xcr0_loaded = 1;
708 }
709}
710
711static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
712{
713 if (vcpu->guest_xcr0_loaded) {
714 if (vcpu->arch.xcr0 != host_xcr0)
715 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
716 vcpu->guest_xcr0_loaded = 0;
717 }
718}
719
69b0049a 720static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 721{
56c103ec
LJ		 722 u64 xcr0 = xcr;
723 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 724 u64 valid_bits;
2acf923e
DC		 725
726 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
727 if (index != XCR_XFEATURE_ENABLED_MASK)
728 return 1;
d91cab78 729 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 730 return 1;
d91cab78 731 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 732 return 1;
46c34cb0
PB		 733
734 /*
735 * Do not allow the guest to set bits that we do not support
736 * saving. However, xcr0 bit 0 is always set, even if the
737 * emulated CPU does not support XSAVE (see fx_init).
738 */
d91cab78 739 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 740 if (xcr0 & ~valid_bits)
2acf923e 741 return 1;
46c34cb0 742
d91cab78
DH		 743 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
744 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 745 return 1;
746
d91cab78
DH		 747 if (xcr0 & XFEATURE_MASK_AVX512) {
748 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 749 return 1;
d91cab78 750 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 751 return 1;
752 }
2acf923e 753 vcpu->arch.xcr0 = xcr0;
56c103ec 754
d91cab78 755 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 756 kvm_update_cpuid(vcpu);
2acf923e
DC		 757 return 0;
758}
759
760int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
761{
764bcbc5
Z		 762 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
763 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 764 kvm_inject_gp(vcpu, 0);
765 return 1;
766 }
767 return 0;
768}
769EXPORT_SYMBOL_GPL(kvm_set_xcr);
770
a83b29c6 771int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 772{
fc78f519 773 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 774 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 775 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 776
0f12244f
GN		 777 if (cr4 & CR4_RESERVED_BITS)
778 return 1;
a03490ed 779
d6321d49 780 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 781 return 1;
782
d6321d49 783 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 784 return 1;
785
d6321d49 786 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 787 return 1;
788
d6321d49 789 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 790 return 1;
791
d6321d49 792 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 793 return 1;
794
fd8cb433 795 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 796 return 1;
797
a03490ed 798 if (is_long_mode(vcpu)) {
0f12244f
GN		 799 if (!(cr4 & X86_CR4_PAE))
800 return 1;
a2edf57f
AK		 801 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
802 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 803 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
804 kvm_read_cr3(vcpu)))
0f12244f
GN		 805 return 1;
806
ad756a16 807 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 808 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 809 return 1;
810
811 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
812 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
813 return 1;
814 }
815
5e1746d6 816 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 817 return 1;
a03490ed 818
ad756a16
MJ		 819 if (((cr4 ^ old_cr4) & pdptr_bits) ||
820 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 821 kvm_mmu_reset_context(vcpu);
0f12244f 822
b9baba86 823 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 824 kvm_update_cpuid(vcpu);
2acf923e 825
0f12244f
GN		 826 return 0;
827}
2d3ad1f4 828EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 829
2390218b 830int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 831{
ac146235 832#ifdef CONFIG_X86_64
9d88fca7 833 cr3 &= ~CR3_PCID_INVD;
ac146235 834#endif
9d88fca7 835
9f8fe504 836 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 837 kvm_mmu_sync_roots(vcpu);
77c3913b 838 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 839 return 0;
d835dfec
AK		 840 }
841
d1cd3ce9
YZ		 842 if (is_long_mode(vcpu) &&
843 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
844 return 1;
845 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 846 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 847 return 1;
a03490ed 848
0f12244f 849 vcpu->arch.cr3 = cr3;
aff48baa 850 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 851 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 852 return 0;
853}
2d3ad1f4 854EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 855
eea1cff9 856int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 857{
0f12244f
GN		 858 if (cr8 & CR8_RESERVED_BITS)
859 return 1;
35754c98 860 if (lapic_in_kernel(vcpu))
a03490ed
CO		 861 kvm_lapic_set_tpr(vcpu, cr8);
862 else
ad312c7c 863 vcpu->arch.cr8 = cr8;
0f12244f
GN		 864 return 0;
865}
2d3ad1f4 866EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 867
2d3ad1f4 868unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 869{
35754c98 870 if (lapic_in_kernel(vcpu))
a03490ed
CO		 871 return kvm_lapic_get_cr8(vcpu);
872 else
ad312c7c 873 return vcpu->arch.cr8;
a03490ed 874}
2d3ad1f4 875EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 876
ae561ede
NA		 877static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
878{
879 int i;
880
881 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
882 for (i = 0; i < KVM_NR_DB_REGS; i++)
883 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
884 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
885 }
886}
887
73aaf249
JK		 888static void kvm_update_dr6(struct kvm_vcpu *vcpu)
889{
890 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
891 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
892}
893
c8639010
JK		 894static void kvm_update_dr7(struct kvm_vcpu *vcpu)
895{
896 unsigned long dr7;
897
898 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
899 dr7 = vcpu->arch.guest_debug_dr7;
900 else
901 dr7 = vcpu->arch.dr7;
902 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 903 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
904 if (dr7 & DR7_BP_EN_MASK)
905 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 906}
907
6f43ed01
NA		 908static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
909{
910 u64 fixed = DR6_FIXED_1;
911
d6321d49 912 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 913 fixed |= DR6_RTM;
914 return fixed;
915}
916
338dbc97 917static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 918{
919 switch (dr) {
920 case 0 ... 3:
921 vcpu->arch.db[dr] = val;
922 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
923 vcpu->arch.eff_db[dr] = val;
924 break;
925 case 4:
020df079
GN		 926 /* fall through */
927 case 6:
338dbc97
GN		 928 if (val & 0xffffffff00000000ULL)
929 return -1; /* #GP */
6f43ed01 930 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 931 kvm_update_dr6(vcpu);
020df079
GN		 932 break;
933 case 5:
020df079
GN		 934 /* fall through */
935 default: /* 7 */
338dbc97
GN		 936 if (val & 0xffffffff00000000ULL)
937 return -1; /* #GP */
020df079 938 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 939 kvm_update_dr7(vcpu);
020df079
GN		 940 break;
941 }
942
943 return 0;
944}
338dbc97
GN		 945
946int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
947{
16f8a6f9 948 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 949 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 950 return 1;
951 }
952 return 0;
338dbc97 953}
020df079
GN		 954EXPORT_SYMBOL_GPL(kvm_set_dr);
955
16f8a6f9 956int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 957{
958 switch (dr) {
959 case 0 ... 3:
960 *val = vcpu->arch.db[dr];
961 break;
962 case 4:
020df079
GN		 963 /* fall through */
964 case 6:
73aaf249
JK		 965 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
966 *val = vcpu->arch.dr6;
967 else
968 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 969 break;
970 case 5:
020df079
GN		 971 /* fall through */
972 default: /* 7 */
973 *val = vcpu->arch.dr7;
974 break;
975 }
338dbc97
GN		 976 return 0;
977}
020df079
GN		 978EXPORT_SYMBOL_GPL(kvm_get_dr);
979
022cd0e8
AK		 980bool kvm_rdpmc(struct kvm_vcpu *vcpu)
981{
982 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
983 u64 data;
984 int err;
985
c6702c9d 986 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 987 if (err)
988 return err;
989 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
990 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
991 return err;
992}
993EXPORT_SYMBOL_GPL(kvm_rdpmc);
994
043405e1
CO		 995/*
996 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
997 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
998 *
999 * This list is modified at module load time to reflect the
e3267cbb 1000 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1001 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1002 * may depend on host virtualization features rather than host cpu features.
043405e1 1003 */
e3267cbb 1004
043405e1
CO		 1005static u32 msrs_to_save[] = {
1006 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1007 MSR_STAR,
043405e1
CO		 1008#ifdef CONFIG_X86_64
1009 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1010#endif
b3897a49 1011 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1012 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 1013};
1014
1015static unsigned num_msrs_to_save;
1016
62ef68bb
PB		 1017static u32 emulated_msrs[] = {
1018 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1019 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1020 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1021 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1022 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1023 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1024 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1025 HV_X64_MSR_RESET,
11c4b1ca 1026 HV_X64_MSR_VP_INDEX,
9eec50b8 1027 HV_X64_MSR_VP_RUNTIME,
5c919412 1028 HV_X64_MSR_SCONTROL,
1f4b34f8 1029 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1030 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1031 MSR_KVM_PV_EOI_EN,
1032
ba904635 1033 MSR_IA32_TSC_ADJUST,
a3e06bbe 1034 MSR_IA32_TSCDEADLINE,
043405e1 1035 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1036 MSR_IA32_MCG_STATUS,
1037 MSR_IA32_MCG_CTL,
c45dcc71 1038 MSR_IA32_MCG_EXT_CTL,
64d60670 1039 MSR_IA32_SMBASE,
db2336a8
KH		 1040 MSR_PLATFORM_INFO,
1041 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1042};
1043
62ef68bb
PB		 1044static unsigned num_emulated_msrs;
1045
384bb783 1046bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1047{
b69e8cae 1048 if (efer & efer_reserved_bits)
384bb783 1049 return false;
15c4a640 1050
1b4d56b8 1051 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1052 return false;
1b2fd70c 1053
1b4d56b8 1054 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1055 return false;
d8017474 1056
384bb783
JK		 1057 return true;
1058}
1059EXPORT_SYMBOL_GPL(kvm_valid_efer);
1060
1061static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1062{
1063 u64 old_efer = vcpu->arch.efer;
1064
1065 if (!kvm_valid_efer(vcpu, efer))
1066 return 1;
1067
1068 if (is_paging(vcpu)
1069 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1070 return 1;
1071
15c4a640 1072 efer &= ~EFER_LMA;
f6801dff 1073 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1074
a3d204e2
SY		 1075 kvm_x86_ops->set_efer(vcpu, efer);
1076
aad82703
SY		 1077 /* Update reserved bits */
1078 if ((efer ^ old_efer) & EFER_NX)
1079 kvm_mmu_reset_context(vcpu);
1080
b69e8cae 1081 return 0;
15c4a640
CO		 1082}
1083
f2b4b7dd
JR		 1084void kvm_enable_efer_bits(u64 mask)
1085{
1086 efer_reserved_bits &= ~mask;
1087}
1088EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1089
15c4a640
CO		 1090/*
1091 * Writes msr value into into the appropriate "register".
1092 * Returns 0 on success, non-0 otherwise.
1093 * Assumes vcpu_load() was already called.
1094 */
8fe8ab46 1095int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1096{
854e8bb1
NA		 1097 switch (msr->index) {
1098 case MSR_FS_BASE:
1099 case MSR_GS_BASE:
1100 case MSR_KERNEL_GS_BASE:
1101 case MSR_CSTAR:
1102 case MSR_LSTAR:
fd8cb433 1103 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1104 return 1;
1105 break;
1106 case MSR_IA32_SYSENTER_EIP:
1107 case MSR_IA32_SYSENTER_ESP:
1108 /*
1109 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1110 * non-canonical address is written on Intel but not on
1111 * AMD (which ignores the top 32-bits, because it does
1112 * not implement 64-bit SYSENTER).
1113 *
1114 * 64-bit code should hence be able to write a non-canonical
1115 * value on AMD. Making the address canonical ensures that
1116 * vmentry does not fail on Intel after writing a non-canonical
1117 * value, and that something deterministic happens if the guest
1118 * invokes 64-bit SYSENTER.
1119 */
fd8cb433 1120 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1121 }
8fe8ab46 1122 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1123}
854e8bb1 1124EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1125
313a3dc7
CO		 1126/*
1127 * Adapt set_msr() to msr_io()'s calling convention
1128 */
609e36d3
PB		 1129static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1130{
1131 struct msr_data msr;
1132 int r;
1133
1134 msr.index = index;
1135 msr.host_initiated = true;
1136 r = kvm_get_msr(vcpu, &msr);
1137 if (r)
1138 return r;
1139
1140 *data = msr.data;
1141 return 0;
1142}
1143
313a3dc7
CO		 1144static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1145{
8fe8ab46
WA		 1146 struct msr_data msr;
1147
1148 msr.data = *data;
1149 msr.index = index;
1150 msr.host_initiated = true;
1151 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1152}
1153
16e8d74d
MT		 1154#ifdef CONFIG_X86_64
1155struct pvclock_gtod_data {
1156 seqcount_t seq;
1157
1158 struct { /* extract of a clocksource struct */
1159 int vclock_mode;
a5a1d1c2
TG		 1160 u64 cycle_last;
1161 u64 mask;
16e8d74d
MT		 1162 u32 mult;
1163 u32 shift;
1164 } clock;
1165
cbcf2dd3
TG		 1166 u64 boot_ns;
1167 u64 nsec_base;
55dd00a7 1168 u64 wall_time_sec;
16e8d74d
MT		 1169};
1170
1171static struct pvclock_gtod_data pvclock_gtod_data;
1172
1173static void update_pvclock_gtod(struct timekeeper *tk)
1174{
1175 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1176 u64 boot_ns;
1177
876e7881 1178 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1179
1180 write_seqcount_begin(&vdata->seq);
1181
1182 /* copy pvclock gtod data */
876e7881
PZ		 1183 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1184 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1185 vdata->clock.mask = tk->tkr_mono.mask;
1186 vdata->clock.mult = tk->tkr_mono.mult;
1187 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1188
cbcf2dd3 1189 vdata->boot_ns = boot_ns;
876e7881 1190 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1191
55dd00a7
MT		 1192 vdata->wall_time_sec = tk->xtime_sec;
1193
16e8d74d
MT		 1194 write_seqcount_end(&vdata->seq);
1195}
1196#endif
1197
bab5bb39
NK		 1198void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1199{
1200 /*
1201 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1202 * vcpu_enter_guest. This function is only called from
1203 * the physical CPU that is running vcpu.
1204 */
1205 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1206}
16e8d74d 1207
18068523
GOC		 1208static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1209{
9ed3c444
AK		 1210 int version;
1211 int r;
50d0a0f9 1212 struct pvclock_wall_clock wc;
87aeb54f 1213 struct timespec64 boot;
18068523
GOC		 1214
1215 if (!wall_clock)
1216 return;
1217
9ed3c444
AK		 1218 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1219 if (r)
1220 return;
1221
1222 if (version & 1)
1223 ++version; /* first time write, random junk */
1224
1225 ++version;
18068523 1226
1dab1345
NK		 1227 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1228 return;
18068523 1229
50d0a0f9
GH		 1230 /*
1231 * The guest calculates current wall clock time by adding
34c238a1 1232 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1233 * wall clock specified here. guest system time equals host
1234 * system time for us, thus we must fill in host boot time here.
1235 */
87aeb54f 1236 getboottime64(&boot);
50d0a0f9 1237
4b648665 1238 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1239 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1240 boot = timespec64_sub(boot, ts);
4b648665 1241 }
87aeb54f 1242 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1243 wc.nsec = boot.tv_nsec;
1244 wc.version = version;
18068523
GOC		 1245
1246 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1247
1248 version++;
1249 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1250}
1251
50d0a0f9
GH		 1252static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1253{
b51012de
PB		 1254 do_shl32_div32(dividend, divisor);
1255 return dividend;
50d0a0f9
GH		 1256}
1257
3ae13faa 1258static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1259 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1260{
5f4e3f88 1261 uint64_t scaled64;
50d0a0f9
GH		 1262 int32_t shift = 0;
1263 uint64_t tps64;
1264 uint32_t tps32;
1265
3ae13faa
PB		 1266 tps64 = base_hz;
1267 scaled64 = scaled_hz;
50933623 1268 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1269 tps64 >>= 1;
1270 shift--;
1271 }
1272
1273 tps32 = (uint32_t)tps64;
50933623
JK		 1274 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1275 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1276 scaled64 >>= 1;
1277 else
1278 tps32 <<= 1;
50d0a0f9
GH		 1279 shift++;
1280 }
1281
5f4e3f88
ZA		 1282 *pshift = shift;
1283 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1284
3ae13faa
PB		 1285 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1286 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1287}
1288
d828199e 1289#ifdef CONFIG_X86_64
16e8d74d 1290static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1291#endif
16e8d74d 1292
c8076604 1293static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1294static unsigned long max_tsc_khz;
c8076604 1295
cc578287 1296static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1297{
cc578287
ZA		 1298 u64 v = (u64)khz * (1000000 + ppm);
1299 do_div(v, 1000000);
1300 return v;
1e993611
JR		 1301}
1302
381d585c
HZ		 1303static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1304{
1305 u64 ratio;
1306
1307 /* Guest TSC same frequency as host TSC? */
1308 if (!scale) {
1309 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1310 return 0;
1311 }
1312
1313 /* TSC scaling supported? */
1314 if (!kvm_has_tsc_control) {
1315 if (user_tsc_khz > tsc_khz) {
1316 vcpu->arch.tsc_catchup = 1;
1317 vcpu->arch.tsc_always_catchup = 1;
1318 return 0;
1319 } else {
1320 WARN(1, "user requested TSC rate below hardware speed\n");
1321 return -1;
1322 }
1323 }
1324
1325 /* TSC scaling required - calculate ratio */
1326 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1327 user_tsc_khz, tsc_khz);
1328
1329 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1330 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1331 user_tsc_khz);
1332 return -1;
1333 }
1334
1335 vcpu->arch.tsc_scaling_ratio = ratio;
1336 return 0;
1337}
1338
4941b8cb 1339static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1340{
cc578287
ZA		 1341 u32 thresh_lo, thresh_hi;
1342 int use_scaling = 0;
217fc9cf 1343
03ba32ca 1344 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1345 if (user_tsc_khz == 0) {
ad721883
HZ		 1346 /* set tsc_scaling_ratio to a safe value */
1347 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1348 return -1;
ad721883 1349 }
03ba32ca 1350
c285545f 1351 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1352 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1353 &vcpu->arch.virtual_tsc_shift,
1354 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1355 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1356
1357 /*
1358 * Compute the variation in TSC rate which is acceptable
1359 * within the range of tolerance and decide if the
1360 * rate being applied is within that bounds of the hardware
1361 * rate. If so, no scaling or compensation need be done.
1362 */
1363 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1364 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1365 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1366 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1367 use_scaling = 1;
1368 }
4941b8cb 1369 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1370}
1371
1372static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1373{
e26101b1 1374 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1375 vcpu->arch.virtual_tsc_mult,
1376 vcpu->arch.virtual_tsc_shift);
e26101b1 1377 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1378 return tsc;
1379}
1380
b0c39dc6
VK		 1381static inline int gtod_is_based_on_tsc(int mode)
1382{
1383 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1384}
1385
69b0049a 1386static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1387{
1388#ifdef CONFIG_X86_64
1389 bool vcpus_matched;
b48aa97e
MT		 1390 struct kvm_arch *ka = &vcpu->kvm->arch;
1391 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1392
1393 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1394 atomic_read(&vcpu->kvm->online_vcpus));
1395
7f187922
MT		 1396 /*
1397 * Once the masterclock is enabled, always perform request in
1398 * order to update it.
1399 *
1400 * In order to enable masterclock, the host clocksource must be TSC
1401 * and the vcpus need to have matched TSCs. When that happens,
1402 * perform request to enable masterclock.
1403 */
1404 if (ka->use_master_clock ||
b0c39dc6 1405 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1406 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1407
1408 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1409 atomic_read(&vcpu->kvm->online_vcpus),
1410 ka->use_master_clock, gtod->clock.vclock_mode);
1411#endif
1412}
1413
ba904635
WA		 1414static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1415{
3e3f5026 1416 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1417 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1418}
1419
35181e86
HZ		 1420/*
1421 * Multiply tsc by a fixed point number represented by ratio.
1422 *
1423 * The most significant 64-N bits (mult) of ratio represent the
1424 * integral part of the fixed point number; the remaining N bits
1425 * (frac) represent the fractional part, ie. ratio represents a fixed
1426 * point number (mult + frac * 2^(-N)).
1427 *
1428 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1429 */
1430static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1431{
1432 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1433}
1434
1435u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1436{
1437 u64 _tsc = tsc;
1438 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1439
1440 if (ratio != kvm_default_tsc_scaling_ratio)
1441 _tsc = __scale_tsc(ratio, tsc);
1442
1443 return _tsc;
1444}
1445EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1446
07c1419a
HZ		 1447static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1448{
1449 u64 tsc;
1450
1451 tsc = kvm_scale_tsc(vcpu, rdtsc());
1452
1453 return target_tsc - tsc;
1454}
1455
4ba76538
HZ		 1456u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1457{
ea26e4ec 1458 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1459}
1460EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1461
a545ab6a
LC		 1462static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1463{
1464 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1465 vcpu->arch.tsc_offset = offset;
1466}
1467
b0c39dc6
VK		 1468static inline bool kvm_check_tsc_unstable(void)
1469{
1470#ifdef CONFIG_X86_64
1471 /*
1472 * TSC is marked unstable when we're running on Hyper-V,
1473 * 'TSC page' clocksource is good.
1474 */
1475 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1476 return false;
1477#endif
1478 return check_tsc_unstable();
1479}
1480
8fe8ab46 1481void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1482{
1483 struct kvm *kvm = vcpu->kvm;
f38e098f 1484 u64 offset, ns, elapsed;
99e3e30a 1485 unsigned long flags;
b48aa97e 1486 bool matched;
0d3da0d2 1487 bool already_matched;
8fe8ab46 1488 u64 data = msr->data;
c5e8ec8e 1489 bool synchronizing = false;
99e3e30a 1490
038f8c11 1491 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1492 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1493 ns = ktime_get_boot_ns();
f38e098f 1494 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1495
03ba32ca 1496 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1497 if (data == 0 && msr->host_initiated) {
1498 /*
1499 * detection of vcpu initialization -- need to sync
1500 * with other vCPUs. This particularly helps to keep
1501 * kvm_clock stable after CPU hotplug
1502 */
1503 synchronizing = true;
1504 } else {
1505 u64 tsc_exp = kvm->arch.last_tsc_write +
1506 nsec_to_cycles(vcpu, elapsed);
1507 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1508 /*
1509 * Special case: TSC write with a small delta (1 second)
1510 * of virtual cycle time against real time is
1511 * interpreted as an attempt to synchronize the CPU.
1512 */
1513 synchronizing = data < tsc_exp + tsc_hz &&
1514 data + tsc_hz > tsc_exp;
1515 }
c5e8ec8e 1516 }
f38e098f
ZA		 1517
1518 /*
5d3cb0f6
ZA		 1519 * For a reliable TSC, we can match TSC offsets, and for an unstable
1520 * TSC, we add elapsed time in this computation. We could let the
1521 * compensation code attempt to catch up if we fall behind, but
1522 * it's better to try to match offsets from the beginning.
1523 */
c5e8ec8e 1524 if (synchronizing &&
5d3cb0f6 1525 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1526 if (!kvm_check_tsc_unstable()) {
e26101b1 1527 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1528 pr_debug("kvm: matched tsc offset for %llu\n", data);
1529 } else {
857e4099 1530 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1531 data += delta;
07c1419a 1532 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1533 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1534 }
b48aa97e 1535 matched = true;
0d3da0d2 1536 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1537 } else {
1538 /*
1539 * We split periods of matched TSC writes into generations.
1540 * For each generation, we track the original measured
1541 * nanosecond time, offset, and write, so if TSCs are in
1542 * sync, we can match exact offset, and if not, we can match
4a969980 1543 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1544 *
1545 * These values are tracked in kvm->arch.cur_xxx variables.
1546 */
1547 kvm->arch.cur_tsc_generation++;
1548 kvm->arch.cur_tsc_nsec = ns;
1549 kvm->arch.cur_tsc_write = data;
1550 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1551 matched = false;
0d3da0d2 1552 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1553 kvm->arch.cur_tsc_generation, data);
f38e098f 1554 }
e26101b1
ZA		 1555
1556 /*
1557 * We also track th most recent recorded KHZ, write and time to
1558 * allow the matching interval to be extended at each write.
1559 */
f38e098f
ZA		 1560 kvm->arch.last_tsc_nsec = ns;
1561 kvm->arch.last_tsc_write = data;
5d3cb0f6 1562 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1563
b183aa58 1564 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1565
1566 /* Keep track of which generation this VCPU has synchronized to */
1567 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1568 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1569 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1570
d6321d49 1571 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1572 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1573
a545ab6a 1574 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1575 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1576
1577 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1578 if (!matched) {
b48aa97e 1579 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1580 } else if (!already_matched) {
1581 kvm->arch.nr_vcpus_matched_tsc++;
1582 }
b48aa97e
MT		 1583
1584 kvm_track_tsc_matching(vcpu);
1585 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1586}
e26101b1 1587
99e3e30a
ZA		 1588EXPORT_SYMBOL_GPL(kvm_write_tsc);
1589
58ea6767
HZ		 1590static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1591 s64 adjustment)
1592{
ea26e4ec 1593 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1594}
1595
1596static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1597{
1598 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1599 WARN_ON(adjustment < 0);
1600 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1601 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1602}
1603
d828199e
MT		 1604#ifdef CONFIG_X86_64
1605
a5a1d1c2 1606static u64 read_tsc(void)
d828199e 1607{
a5a1d1c2 1608 u64 ret = (u64)rdtsc_ordered();
03b9730b 1609 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1610
1611 if (likely(ret >= last))
1612 return ret;
1613
1614 /*
1615 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1616 * predictable (it's just a function of time and the likely is
d828199e
MT		 1617 * very likely) and there's a data dependence, so force GCC
1618 * to generate a branch instead. I don't barrier() because
1619 * we don't actually need a barrier, and if this function
1620 * ever gets inlined it will generate worse code.
1621 */
1622 asm volatile ("");
1623 return last;
1624}
1625
b0c39dc6 1626static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1627{
1628 long v;
1629 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1630 u64 tsc_pg_val;
1631
1632 switch (gtod->clock.vclock_mode) {
1633 case VCLOCK_HVCLOCK:
1634 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1635 tsc_timestamp);
1636 if (tsc_pg_val != U64_MAX) {
1637 /* TSC page valid */
1638 *mode = VCLOCK_HVCLOCK;
1639 v = (tsc_pg_val - gtod->clock.cycle_last) &
1640 gtod->clock.mask;
1641 } else {
1642 /* TSC page invalid */
1643 *mode = VCLOCK_NONE;
1644 }
1645 break;
1646 case VCLOCK_TSC:
1647 *mode = VCLOCK_TSC;
1648 *tsc_timestamp = read_tsc();
1649 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1650 gtod->clock.mask;
1651 break;
1652 default:
1653 *mode = VCLOCK_NONE;
1654 }
d828199e 1655
b0c39dc6
VK		 1656 if (*mode == VCLOCK_NONE)
1657 *tsc_timestamp = v = 0;
d828199e 1658
d828199e
MT		 1659 return v * gtod->clock.mult;
1660}
1661
b0c39dc6 1662static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1663{
cbcf2dd3 1664 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1665 unsigned long seq;
d828199e 1666 int mode;
cbcf2dd3 1667 u64 ns;
d828199e 1668
d828199e
MT		 1669 do {
1670 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1671 ns = gtod->nsec_base;
b0c39dc6 1672 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1673 ns >>= gtod->clock.shift;
cbcf2dd3 1674 ns += gtod->boot_ns;
d828199e 1675 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1676 *t = ns;
d828199e
MT		 1677
1678 return mode;
1679}
1680
b0c39dc6 1681static int do_realtime(struct timespec *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1682{
1683 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1684 unsigned long seq;
1685 int mode;
1686 u64 ns;
1687
1688 do {
1689 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1690 ts->tv_sec = gtod->wall_time_sec;
1691 ns = gtod->nsec_base;
b0c39dc6 1692 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1693 ns >>= gtod->clock.shift;
1694 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1695
1696 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1697 ts->tv_nsec = ns;
1698
1699 return mode;
1700}
1701
b0c39dc6
VK		 1702/* returns true if host is using TSC based clocksource */
1703static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1704{
d828199e 1705 /* checked again under seqlock below */
b0c39dc6 1706 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1707 return false;
1708
b0c39dc6
VK		 1709 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1710 tsc_timestamp));
d828199e 1711}
55dd00a7 1712
b0c39dc6 1713/* returns true if host is using TSC based clocksource */
55dd00a7 1714static bool kvm_get_walltime_and_clockread(struct timespec *ts,
b0c39dc6 1715 u64 *tsc_timestamp)
55dd00a7
MT		 1716{
1717 /* checked again under seqlock below */
b0c39dc6 1718 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1719 return false;
1720
b0c39dc6 1721 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1722}
d828199e
MT		 1723#endif
1724
1725/*
1726 *
b48aa97e
MT		 1727 * Assuming a stable TSC across physical CPUS, and a stable TSC
1728 * across virtual CPUs, the following condition is possible.
1729 * Each numbered line represents an event visible to both
d828199e
MT		 1730 * CPUs at the next numbered event.
1731 *
1732 * "timespecX" represents host monotonic time. "tscX" represents
1733 * RDTSC value.
1734 *
1735 * VCPU0 on CPU0 | VCPU1 on CPU1
1736 *
1737 * 1. read timespec0,tsc0
1738 * 2. | timespec1 = timespec0 + N
1739 * | tsc1 = tsc0 + M
1740 * 3. transition to guest | transition to guest
1741 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1742 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1743 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1744 *
1745 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1746 *
1747 * - ret0 < ret1
1748 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1749 * ...
1750 * - 0 < N - M => M < N
1751 *
1752 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1753 * always the case (the difference between two distinct xtime instances
1754 * might be smaller then the difference between corresponding TSC reads,
1755 * when updating guest vcpus pvclock areas).
1756 *
1757 * To avoid that problem, do not allow visibility of distinct
1758 * system_timestamp/tsc_timestamp values simultaneously: use a master
1759 * copy of host monotonic time values. Update that master copy
1760 * in lockstep.
1761 *
b48aa97e 1762 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1763 *
1764 */
1765
1766static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1767{
1768#ifdef CONFIG_X86_64
1769 struct kvm_arch *ka = &kvm->arch;
1770 int vclock_mode;
b48aa97e
MT		 1771 bool host_tsc_clocksource, vcpus_matched;
1772
1773 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1774 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1775
1776 /*
1777 * If the host uses TSC clock, then passthrough TSC as stable
1778 * to the guest.
1779 */
b48aa97e 1780 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1781 &ka->master_kernel_ns,
1782 &ka->master_cycle_now);
1783
16a96021 1784 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1785 && !ka->backwards_tsc_observed
54750f2c 1786 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1787
d828199e
MT		 1788 if (ka->use_master_clock)
1789 atomic_set(&kvm_guest_has_master_clock, 1);
1790
1791 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1792 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1793 vcpus_matched);
d828199e
MT		 1794#endif
1795}
1796
2860c4b1
PB		 1797void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1798{
1799 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1800}
1801
2e762ff7
MT		 1802static void kvm_gen_update_masterclock(struct kvm *kvm)
1803{
1804#ifdef CONFIG_X86_64
1805 int i;
1806 struct kvm_vcpu *vcpu;
1807 struct kvm_arch *ka = &kvm->arch;
1808
1809 spin_lock(&ka->pvclock_gtod_sync_lock);
1810 kvm_make_mclock_inprogress_request(kvm);
1811 /* no guest entries from this point */
1812 pvclock_update_vm_gtod_copy(kvm);
1813
1814 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1815 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1816
1817 /* guest entries allowed */
1818 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1819 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1820
1821 spin_unlock(&ka->pvclock_gtod_sync_lock);
1822#endif
1823}
1824
e891a32e 1825u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1826{
108b249c 1827 struct kvm_arch *ka = &kvm->arch;
8b953440 1828 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1829 u64 ret;
108b249c 1830
8b953440
PB		 1831 spin_lock(&ka->pvclock_gtod_sync_lock);
1832 if (!ka->use_master_clock) {
1833 spin_unlock(&ka->pvclock_gtod_sync_lock);
1834 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1835 }
1836
8b953440
PB		 1837 hv_clock.tsc_timestamp = ka->master_cycle_now;
1838 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1839 spin_unlock(&ka->pvclock_gtod_sync_lock);
1840
e2c2206a
WL		 1841 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1842 get_cpu();
1843
e70b57a6
WL		 1844 if (__this_cpu_read(cpu_tsc_khz)) {
1845 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1846 &hv_clock.tsc_shift,
1847 &hv_clock.tsc_to_system_mul);
1848 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1849 } else
1850 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1851
1852 put_cpu();
1853
1854 return ret;
108b249c
PB		 1855}
1856
0d6dd2ff
PB		 1857static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1858{
1859 struct kvm_vcpu_arch *vcpu = &v->arch;
1860 struct pvclock_vcpu_time_info guest_hv_clock;
1861
4e335d9e 1862 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1863 &guest_hv_clock, sizeof(guest_hv_clock))))
1864 return;
1865
1866 /* This VCPU is paused, but it's legal for a guest to read another
1867 * VCPU's kvmclock, so we really have to follow the specification where
1868 * it says that version is odd if data is being modified, and even after
1869 * it is consistent.
1870 *
1871 * Version field updates must be kept separate. This is because
1872 * kvm_write_guest_cached might use a "rep movs" instruction, and
1873 * writes within a string instruction are weakly ordered. So there
1874 * are three writes overall.
1875 *
1876 * As a small optimization, only write the version field in the first
1877 * and third write. The vcpu->pv_time cache is still valid, because the
1878 * version field is the first in the struct.
1879 */
1880 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1881
51c4b8bb
LA		 1882 if (guest_hv_clock.version & 1)
1883 ++guest_hv_clock.version; /* first time write, random junk */
1884
0d6dd2ff 1885 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1886 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1887 &vcpu->hv_clock,
1888 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1889
1890 smp_wmb();
1891
1892 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1893 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1894
1895 if (vcpu->pvclock_set_guest_stopped_request) {
1896 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1897 vcpu->pvclock_set_guest_stopped_request = false;
1898 }
1899
1900 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1901
4e335d9e
PB		 1902 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1903 &vcpu->hv_clock,
1904 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1905
1906 smp_wmb();
1907
1908 vcpu->hv_clock.version++;
4e335d9e
PB		 1909 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1910 &vcpu->hv_clock,
1911 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1912}
1913
34c238a1 1914static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1915{
78db6a50 1916 unsigned long flags, tgt_tsc_khz;
18068523 1917 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1918 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1919 s64 kernel_ns;
d828199e 1920 u64 tsc_timestamp, host_tsc;
51d59c6b 1921 u8 pvclock_flags;
d828199e
MT		 1922 bool use_master_clock;
1923
1924 kernel_ns = 0;
1925 host_tsc = 0;
18068523 1926
d828199e
MT		 1927 /*
1928 * If the host uses TSC clock, then passthrough TSC as stable
1929 * to the guest.
1930 */
1931 spin_lock(&ka->pvclock_gtod_sync_lock);
1932 use_master_clock = ka->use_master_clock;
1933 if (use_master_clock) {
1934 host_tsc = ka->master_cycle_now;
1935 kernel_ns = ka->master_kernel_ns;
1936 }
1937 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1938
1939 /* Keep irq disabled to prevent changes to the clock */
1940 local_irq_save(flags);
78db6a50
PB		 1941 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1942 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1943 local_irq_restore(flags);
1944 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1945 return 1;
1946 }
d828199e 1947 if (!use_master_clock) {
4ea1636b 1948 host_tsc = rdtsc();
108b249c 1949 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1950 }
1951
4ba76538 1952 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1953
c285545f
ZA		 1954 /*
1955 * We may have to catch up the TSC to match elapsed wall clock
1956 * time for two reasons, even if kvmclock is used.
1957 * 1) CPU could have been running below the maximum TSC rate
1958 * 2) Broken TSC compensation resets the base at each VCPU
1959 * entry to avoid unknown leaps of TSC even when running
1960 * again on the same CPU. This may cause apparent elapsed
1961 * time to disappear, and the guest to stand still or run
1962 * very slowly.
1963 */
1964 if (vcpu->tsc_catchup) {
1965 u64 tsc = compute_guest_tsc(v, kernel_ns);
1966 if (tsc > tsc_timestamp) {
f1e2b260 1967 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1968 tsc_timestamp = tsc;
1969 }
50d0a0f9
GH		 1970 }
1971
18068523
GOC		 1972 local_irq_restore(flags);
1973
0d6dd2ff 1974 /* With all the info we got, fill in the values */
18068523 1975
78db6a50
PB		 1976 if (kvm_has_tsc_control)
1977 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1978
1979 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1980 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1981 &vcpu->hv_clock.tsc_shift,
1982 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1983 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1984 }
1985
1d5f066e 1986 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1987 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1988 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1989
d828199e 1990 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1991 pvclock_flags = 0;
d828199e
MT		 1992 if (use_master_clock)
1993 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1994
78c0337a
MT		 1995 vcpu->hv_clock.flags = pvclock_flags;
1996
095cf55d
PB		 1997 if (vcpu->pv_time_enabled)
1998 kvm_setup_pvclock_page(v);
1999 if (v == kvm_get_vcpu(v->kvm, 0))
2000 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2001 return 0;
c8076604
GH		 2002}
2003
0061d53d
MT		 2004/*
2005 * kvmclock updates which are isolated to a given vcpu, such as
2006 * vcpu->cpu migration, should not allow system_timestamp from
2007 * the rest of the vcpus to remain static. Otherwise ntp frequency
2008 * correction applies to one vcpu's system_timestamp but not
2009 * the others.
2010 *
2011 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2012 * We need to rate-limit these requests though, as they can
2013 * considerably slow guests that have a large number of vcpus.
2014 * The time for a remote vcpu to update its kvmclock is bound
2015 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2016 */
2017
7e44e449
AJ		 2018#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2019
2020static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2021{
2022 int i;
7e44e449
AJ		 2023 struct delayed_work *dwork = to_delayed_work(work);
2024 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2025 kvmclock_update_work);
2026 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2027 struct kvm_vcpu *vcpu;
2028
2029 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2030 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2031 kvm_vcpu_kick(vcpu);
2032 }
2033}
2034
7e44e449
AJ		 2035static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2036{
2037 struct kvm *kvm = v->kvm;
2038
105b21bb 2039 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2040 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2041 KVMCLOCK_UPDATE_DELAY);
2042}
2043
332967a3
AJ		 2044#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2045
2046static void kvmclock_sync_fn(struct work_struct *work)
2047{
2048 struct delayed_work *dwork = to_delayed_work(work);
2049 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2050 kvmclock_sync_work);
2051 struct kvm *kvm = container_of(ka, struct kvm, arch);
2052
630994b3
MT		 2053 if (!kvmclock_periodic_sync)
2054 return;
2055
332967a3
AJ		 2056 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2057 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2058 KVMCLOCK_SYNC_PERIOD);
2059}
2060
9ffd986c 2061static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2062{
890ca9ae
HY		 2063 u64 mcg_cap = vcpu->arch.mcg_cap;
2064 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2065 u32 msr = msr_info->index;
2066 u64 data = msr_info->data;
890ca9ae 2067
15c4a640 2068 switch (msr) {
15c4a640 2069 case MSR_IA32_MCG_STATUS:
890ca9ae 2070 vcpu->arch.mcg_status = data;
15c4a640 2071 break;
c7ac679c 2072 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2073 if (!(mcg_cap & MCG_CTL_P))
2074 return 1;
2075 if (data != 0 && data != ~(u64)0)
2076 return -1;
2077 vcpu->arch.mcg_ctl = data;
2078 break;
2079 default:
2080 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2081 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2082 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2083 /* only 0 or all 1s can be written to IA32_MCi_CTL
2084 * some Linux kernels though clear bit 10 in bank 4 to
2085 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2086 * this to avoid an uncatched #GP in the guest
2087 */
890ca9ae 2088 if ((offset & 0x3) == 0 &&
114be429 2089 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2090 return -1;
9ffd986c
WL		 2091 if (!msr_info->host_initiated &&
2092 (offset & 0x3) == 1 && data != 0)
2093 return -1;
890ca9ae
HY		 2094 vcpu->arch.mce_banks[offset] = data;
2095 break;
2096 }
2097 return 1;
2098 }
2099 return 0;
2100}
2101
ffde22ac
ES		 2102static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2103{
2104 struct kvm *kvm = vcpu->kvm;
2105 int lm = is_long_mode(vcpu);
2106 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2107 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2108 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2109 : kvm->arch.xen_hvm_config.blob_size_32;
2110 u32 page_num = data & ~PAGE_MASK;
2111 u64 page_addr = data & PAGE_MASK;
2112 u8 *page;
2113 int r;
2114
2115 r = -E2BIG;
2116 if (page_num >= blob_size)
2117 goto out;
2118 r = -ENOMEM;
ff5c2c03
SL		 2119 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2120 if (IS_ERR(page)) {
2121 r = PTR_ERR(page);
ffde22ac 2122 goto out;
ff5c2c03 2123 }
54bf36aa 2124 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2125 goto out_free;
2126 r = 0;
2127out_free:
2128 kfree(page);
2129out:
2130 return r;
2131}
2132
344d9588
GN		 2133static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2134{
2135 gpa_t gpa = data & ~0x3f;
2136
52a5c155
WL		 2137 /* Bits 3:5 are reserved, Should be zero */
2138 if (data & 0x38)
344d9588
GN		 2139 return 1;
2140
2141 vcpu->arch.apf.msr_val = data;
2142
2143 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2144 kvm_clear_async_pf_completion_queue(vcpu);
2145 kvm_async_pf_hash_reset(vcpu);
2146 return 0;
2147 }
2148
4e335d9e 2149 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2150 sizeof(u32)))
344d9588
GN		 2151 return 1;
2152
6adba527 2153 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2154 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2155 kvm_async_pf_wakeup_all(vcpu);
2156 return 0;
2157}
2158
12f9a48f
GC		 2159static void kvmclock_reset(struct kvm_vcpu *vcpu)
2160{
0b79459b 2161 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2162}
2163
c9aaa895
GC		 2164static void record_steal_time(struct kvm_vcpu *vcpu)
2165{
2166 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2167 return;
2168
4e335d9e 2169 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2170 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2171 return;
2172
0b9f6c46
PX		 2173 vcpu->arch.st.steal.preempted = 0;
2174
35f3fae1
WL		 2175 if (vcpu->arch.st.steal.version & 1)
2176 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2177
2178 vcpu->arch.st.steal.version += 1;
2179
4e335d9e 2180 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2181 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2182
2183 smp_wmb();
2184
c54cdf14
LC		 2185 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2186 vcpu->arch.st.last_steal;
2187 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2188
4e335d9e 2189 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2190 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2191
2192 smp_wmb();
2193
2194 vcpu->arch.st.steal.version += 1;
c9aaa895 2195
4e335d9e 2196 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2197 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2198}
2199
8fe8ab46 2200int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2201{
5753785f 2202 bool pr = false;
8fe8ab46
WA		 2203 u32 msr = msr_info->index;
2204 u64 data = msr_info->data;
5753785f 2205
15c4a640 2206 switch (msr) {
2e32b719
BP		 2207 case MSR_AMD64_NB_CFG:
2208 case MSR_IA32_UCODE_REV:
2209 case MSR_IA32_UCODE_WRITE:
2210 case MSR_VM_HSAVE_PA:
2211 case MSR_AMD64_PATCH_LOADER:
2212 case MSR_AMD64_BU_CFG2:
405a353a 2213 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2214 break;
2215
15c4a640 2216 case MSR_EFER:
b69e8cae 2217 return set_efer(vcpu, data);
8f1589d9
AP		 2218 case MSR_K7_HWCR:
2219 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2220 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2221 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2222 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2223 if (data != 0) {
a737f256
CD		 2224 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2225 data);
8f1589d9
AP		 2226 return 1;
2227 }
15c4a640 2228 break;
f7c6d140
AP		 2229 case MSR_FAM10H_MMIO_CONF_BASE:
2230 if (data != 0) {
a737f256
CD		 2231 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2232 "0x%llx\n", data);
f7c6d140
AP		 2233 return 1;
2234 }
15c4a640 2235 break;
b5e2fec0
AG		 2236 case MSR_IA32_DEBUGCTLMSR:
2237 if (!data) {
2238 /* We support the non-activated case already */
2239 break;
2240 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2241 /* Values other than LBR and BTF are vendor-specific,
2242 thus reserved and should throw a #GP */
2243 return 1;
2244 }
a737f256
CD		 2245 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2246 __func__, data);
b5e2fec0 2247 break;
9ba075a6 2248 case 0x200 ... 0x2ff:
ff53604b 2249 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2250 case MSR_IA32_APICBASE:
58cb628d 2251 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2252 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2253 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2254 case MSR_IA32_TSCDEADLINE:
2255 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2256 break;
ba904635 2257 case MSR_IA32_TSC_ADJUST:
d6321d49 2258 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2259 if (!msr_info->host_initiated) {
d913b904 2260 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2261 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2262 }
2263 vcpu->arch.ia32_tsc_adjust_msr = data;
2264 }
2265 break;
15c4a640 2266 case MSR_IA32_MISC_ENABLE:
ad312c7c 2267 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2268 break;
64d60670
PB		 2269 case MSR_IA32_SMBASE:
2270 if (!msr_info->host_initiated)
2271 return 1;
2272 vcpu->arch.smbase = data;
2273 break;
11c6bffa 2274 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2275 case MSR_KVM_WALL_CLOCK:
2276 vcpu->kvm->arch.wall_clock = data;
2277 kvm_write_wall_clock(vcpu->kvm, data);
2278 break;
11c6bffa 2279 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2280 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2281 struct kvm_arch *ka = &vcpu->kvm->arch;
2282
12f9a48f 2283 kvmclock_reset(vcpu);
18068523 2284
54750f2c
MT		 2285 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2286 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2287
2288 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2289 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2290
2291 ka->boot_vcpu_runs_old_kvmclock = tmp;
2292 }
2293
18068523 2294 vcpu->arch.time = data;
0061d53d 2295 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2296
2297 /* we verify if the enable bit is set... */
2298 if (!(data & 1))
2299 break;
2300
4e335d9e 2301 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2302 &vcpu->arch.pv_time, data & ~1ULL,
2303 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2304 vcpu->arch.pv_time_enabled = false;
2305 else
2306 vcpu->arch.pv_time_enabled = true;
32cad84f 2307
18068523
GOC		 2308 break;
2309 }
344d9588
GN		 2310 case MSR_KVM_ASYNC_PF_EN:
2311 if (kvm_pv_enable_async_pf(vcpu, data))
2312 return 1;
2313 break;
c9aaa895
GC		 2314 case MSR_KVM_STEAL_TIME:
2315
2316 if (unlikely(!sched_info_on()))
2317 return 1;
2318
2319 if (data & KVM_STEAL_RESERVED_MASK)
2320 return 1;
2321
4e335d9e 2322 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2323 data & KVM_STEAL_VALID_BITS,
2324 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2325 return 1;
2326
2327 vcpu->arch.st.msr_val = data;
2328
2329 if (!(data & KVM_MSR_ENABLED))
2330 break;
2331
c9aaa895
GC		 2332 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2333
2334 break;
ae7a2a3f
MT		 2335 case MSR_KVM_PV_EOI_EN:
2336 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2337 return 1;
2338 break;
c9aaa895 2339
890ca9ae
HY		 2340 case MSR_IA32_MCG_CTL:
2341 case MSR_IA32_MCG_STATUS:
81760dcc 2342 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2343 return set_msr_mce(vcpu, msr_info);
71db6023 2344
6912ac32
WH		 2345 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2346 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2347 pr = true; /* fall through */
2348 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2349 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2350 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2351 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2352
2353 if (pr || data != 0)
a737f256
CD		 2354 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2355 "0x%x data 0x%llx\n", msr, data);
5753785f 2356 break;
84e0cefa
JS		 2357 case MSR_K7_CLK_CTL:
2358 /*
2359 * Ignore all writes to this no longer documented MSR.
2360 * Writes are only relevant for old K7 processors,
2361 * all pre-dating SVM, but a recommended workaround from
4a969980 2362 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2363 * affected processor models on the command line, hence
2364 * the need to ignore the workaround.
2365 */
2366 break;
55cd8e5a 2367 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2368 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2369 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2370 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2371 return kvm_hv_set_msr_common(vcpu, msr, data,
2372 msr_info->host_initiated);
91c9c3ed 2373 case MSR_IA32_BBL_CR_CTL3:
2374 /* Drop writes to this legacy MSR -- see rdmsr
2375 * counterpart for further detail.
2376 */
fab0aa3b
EM		 2377 if (report_ignored_msrs)
2378 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2379 msr, data);
91c9c3ed 2380 break;
2b036c6b 2381 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2382 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2383 return 1;
2384 vcpu->arch.osvw.length = data;
2385 break;
2386 case MSR_AMD64_OSVW_STATUS:
d6321d49 2387 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2388 return 1;
2389 vcpu->arch.osvw.status = data;
2390 break;
db2336a8
KH		 2391 case MSR_PLATFORM_INFO:
2392 if (!msr_info->host_initiated ||
2393 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2394 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2395 cpuid_fault_enabled(vcpu)))
2396 return 1;
2397 vcpu->arch.msr_platform_info = data;
2398 break;
2399 case MSR_MISC_FEATURES_ENABLES:
2400 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2401 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2402 !supports_cpuid_fault(vcpu)))
2403 return 1;
2404 vcpu->arch.msr_misc_features_enables = data;
2405 break;
15c4a640 2406 default:
ffde22ac
ES		 2407 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2408 return xen_hvm_config(vcpu, data);
c6702c9d 2409 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2410 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2411 if (!ignore_msrs) {
ae0f5499 2412 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2413 msr, data);
ed85c068
AP		 2414 return 1;
2415 } else {
fab0aa3b
EM		 2416 if (report_ignored_msrs)
2417 vcpu_unimpl(vcpu,
2418 "ignored wrmsr: 0x%x data 0x%llx\n",
2419 msr, data);
ed85c068
AP		 2420 break;
2421 }
15c4a640
CO		 2422 }
2423 return 0;
2424}
2425EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2426
2427
2428/*
2429 * Reads an msr value (of 'msr_index') into 'pdata'.
2430 * Returns 0 on success, non-0 otherwise.
2431 * Assumes vcpu_load() was already called.
2432 */
609e36d3 2433int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2434{
609e36d3 2435 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2436}
ff651cb6 2437EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2438
890ca9ae 2439static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2440{
2441 u64 data;
890ca9ae
HY		 2442 u64 mcg_cap = vcpu->arch.mcg_cap;
2443 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2444
2445 switch (msr) {
15c4a640
CO		 2446 case MSR_IA32_P5_MC_ADDR:
2447 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2448 data = 0;
2449 break;
15c4a640 2450 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2451 data = vcpu->arch.mcg_cap;
2452 break;
c7ac679c 2453 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2454 if (!(mcg_cap & MCG_CTL_P))
2455 return 1;
2456 data = vcpu->arch.mcg_ctl;
2457 break;
2458 case MSR_IA32_MCG_STATUS:
2459 data = vcpu->arch.mcg_status;
2460 break;
2461 default:
2462 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2463 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2464 u32 offset = msr - MSR_IA32_MC0_CTL;
2465 data = vcpu->arch.mce_banks[offset];
2466 break;
2467 }
2468 return 1;
2469 }
2470 *pdata = data;
2471 return 0;
2472}
2473
609e36d3 2474int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2475{
609e36d3 2476 switch (msr_info->index) {
890ca9ae 2477 case MSR_IA32_PLATFORM_ID:
15c4a640 2478 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2479 case MSR_IA32_DEBUGCTLMSR:
2480 case MSR_IA32_LASTBRANCHFROMIP:
2481 case MSR_IA32_LASTBRANCHTOIP:
2482 case MSR_IA32_LASTINTFROMIP:
2483 case MSR_IA32_LASTINTTOIP:
60af2ecd 2484 case MSR_K8_SYSCFG:
3afb1121
PB		 2485 case MSR_K8_TSEG_ADDR:
2486 case MSR_K8_TSEG_MASK:
60af2ecd 2487 case MSR_K7_HWCR:
61a6bd67 2488 case MSR_VM_HSAVE_PA:
1fdbd48c 2489 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2490 case MSR_AMD64_NB_CFG:
f7c6d140 2491 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2492 case MSR_AMD64_BU_CFG2:
0c2df2a1 2493 case MSR_IA32_PERF_CTL:
405a353a 2494 case MSR_AMD64_DC_CFG:
609e36d3 2495 msr_info->data = 0;
15c4a640 2496 break;
6912ac32
WH		 2497 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2498 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2499 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2500 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2501 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2502 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2503 msr_info->data = 0;
5753785f 2504 break;
742bc670 2505 case MSR_IA32_UCODE_REV:
609e36d3 2506 msr_info->data = 0x100000000ULL;
742bc670 2507 break;
9ba075a6 2508 case MSR_MTRRcap:
9ba075a6 2509 case 0x200 ... 0x2ff:
ff53604b 2510 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2511 case 0xcd: /* fsb frequency */
609e36d3 2512 msr_info->data = 3;
15c4a640 2513 break;
7b914098
JS		 2514 /*
2515 * MSR_EBC_FREQUENCY_ID
2516 * Conservative value valid for even the basic CPU models.
2517 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2518 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2519 * and 266MHz for model 3, or 4. Set Core Clock
2520 * Frequency to System Bus Frequency Ratio to 1 (bits
2521 * 31:24) even though these are only valid for CPU
2522 * models > 2, however guests may end up dividing or
2523 * multiplying by zero otherwise.
2524 */
2525 case MSR_EBC_FREQUENCY_ID:
609e36d3 2526 msr_info->data = 1 << 24;
7b914098 2527 break;
15c4a640 2528 case MSR_IA32_APICBASE:
609e36d3 2529 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2530 break;
0105d1a5 2531 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2532 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2533 break;
a3e06bbe 2534 case MSR_IA32_TSCDEADLINE:
609e36d3 2535 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2536 break;
ba904635 2537 case MSR_IA32_TSC_ADJUST:
609e36d3 2538 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2539 break;
15c4a640 2540 case MSR_IA32_MISC_ENABLE:
609e36d3 2541 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2542 break;
64d60670
PB		 2543 case MSR_IA32_SMBASE:
2544 if (!msr_info->host_initiated)
2545 return 1;
2546 msr_info->data = vcpu->arch.smbase;
15c4a640 2547 break;
847f0ad8
AG		 2548 case MSR_IA32_PERF_STATUS:
2549 /* TSC increment by tick */
609e36d3 2550 msr_info->data = 1000ULL;
847f0ad8 2551 /* CPU multiplier */
b0996ae4 2552 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2553 break;
15c4a640 2554 case MSR_EFER:
609e36d3 2555 msr_info->data = vcpu->arch.efer;
15c4a640 2556 break;
18068523 2557 case MSR_KVM_WALL_CLOCK:
11c6bffa 2558 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2559 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2560 break;
2561 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2562 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2563 msr_info->data = vcpu->arch.time;
18068523 2564 break;
344d9588 2565 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2566 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2567 break;
c9aaa895 2568 case MSR_KVM_STEAL_TIME:
609e36d3 2569 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2570 break;
1d92128f 2571 case MSR_KVM_PV_EOI_EN:
609e36d3 2572 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2573 break;
890ca9ae
HY		 2574 case MSR_IA32_P5_MC_ADDR:
2575 case MSR_IA32_P5_MC_TYPE:
2576 case MSR_IA32_MCG_CAP:
2577 case MSR_IA32_MCG_CTL:
2578 case MSR_IA32_MCG_STATUS:
81760dcc 2579 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2580 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2581 case MSR_K7_CLK_CTL:
2582 /*
2583 * Provide expected ramp-up count for K7. All other
2584 * are set to zero, indicating minimum divisors for
2585 * every field.
2586 *
2587 * This prevents guest kernels on AMD host with CPU
2588 * type 6, model 8 and higher from exploding due to
2589 * the rdmsr failing.
2590 */
609e36d3 2591 msr_info->data = 0x20000000;
84e0cefa 2592 break;
55cd8e5a 2593 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2594 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2595 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2596 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2597 return kvm_hv_get_msr_common(vcpu,
2598 msr_info->index, &msr_info->data);
55cd8e5a 2599 break;
91c9c3ed 2600 case MSR_IA32_BBL_CR_CTL3:
2601 /* This legacy MSR exists but isn't fully documented in current
2602 * silicon. It is however accessed by winxp in very narrow
2603 * scenarios where it sets bit #19, itself documented as
2604 * a "reserved" bit. Best effort attempt to source coherent
2605 * read data here should the balance of the register be
2606 * interpreted by the guest:
2607 *
2608 * L2 cache control register 3: 64GB range, 256KB size,
2609 * enabled, latency 0x1, configured
2610 */
609e36d3 2611 msr_info->data = 0xbe702111;
91c9c3ed 2612 break;
2b036c6b 2613 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2614 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2615 return 1;
609e36d3 2616 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2617 break;
2618 case MSR_AMD64_OSVW_STATUS:
d6321d49 2619 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2620 return 1;
609e36d3 2621 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2622 break;
db2336a8
KH		 2623 case MSR_PLATFORM_INFO:
2624 msr_info->data = vcpu->arch.msr_platform_info;
2625 break;
2626 case MSR_MISC_FEATURES_ENABLES:
2627 msr_info->data = vcpu->arch.msr_misc_features_enables;
2628 break;
15c4a640 2629 default:
c6702c9d 2630 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2631 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2632 if (!ignore_msrs) {
ae0f5499
BD		 2633 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2634 msr_info->index);
ed85c068
AP		 2635 return 1;
2636 } else {
fab0aa3b
EM		 2637 if (report_ignored_msrs)
2638 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2639 msr_info->index);
609e36d3 2640 msr_info->data = 0;
ed85c068
AP		 2641 }
2642 break;
15c4a640 2643 }
15c4a640
CO		 2644 return 0;
2645}
2646EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2647
313a3dc7
CO		 2648/*
2649 * Read or write a bunch of msrs. All parameters are kernel addresses.
2650 *
2651 * @return number of msrs set successfully.
2652 */
2653static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2654 struct kvm_msr_entry *entries,
2655 int (*do_msr)(struct kvm_vcpu *vcpu,
2656 unsigned index, u64 *data))
2657{
f656ce01 2658 int i, idx;
313a3dc7 2659
f656ce01 2660 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2661 for (i = 0; i < msrs->nmsrs; ++i)
2662 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2663 break;
f656ce01 2664 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2665
313a3dc7
CO		 2666 return i;
2667}
2668
2669/*
2670 * Read or write a bunch of msrs. Parameters are user addresses.
2671 *
2672 * @return number of msrs set successfully.
2673 */
2674static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2675 int (*do_msr)(struct kvm_vcpu *vcpu,
2676 unsigned index, u64 *data),
2677 int writeback)
2678{
2679 struct kvm_msrs msrs;
2680 struct kvm_msr_entry *entries;
2681 int r, n;
2682 unsigned size;
2683
2684 r = -EFAULT;
2685 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2686 goto out;
2687
2688 r = -E2BIG;
2689 if (msrs.nmsrs >= MAX_IO_MSRS)
2690 goto out;
2691
313a3dc7 2692 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2693 entries = memdup_user(user_msrs->entries, size);
2694 if (IS_ERR(entries)) {
2695 r = PTR_ERR(entries);
313a3dc7 2696 goto out;
ff5c2c03 2697 }
313a3dc7
CO		 2698
2699 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2700 if (r < 0)
2701 goto out_free;
2702
2703 r = -EFAULT;
2704 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2705 goto out_free;
2706
2707 r = n;
2708
2709out_free:
7a73c028 2710 kfree(entries);
313a3dc7
CO		 2711out:
2712 return r;
2713}
2714
784aa3d7 2715int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2716{
2717 int r;
2718
2719 switch (ext) {
2720 case KVM_CAP_IRQCHIP:
2721 case KVM_CAP_HLT:
2722 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2723 case KVM_CAP_SET_TSS_ADDR:
07716717 2724 case KVM_CAP_EXT_CPUID:
9c15bb1d 2725 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2726 case KVM_CAP_CLOCKSOURCE:
7837699f 2727 case KVM_CAP_PIT:
a28e4f5a 2728 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2729 case KVM_CAP_MP_STATE:
ed848624 2730 case KVM_CAP_SYNC_MMU:
a355c85c 2731 case KVM_CAP_USER_NMI:
52d939a0 2732 case KVM_CAP_REINJECT_CONTROL:
4925663a 2733 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2734 case KVM_CAP_IOEVENTFD:
f848a5a8 2735 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2736 case KVM_CAP_PIT2:
e9f42757 2737 case KVM_CAP_PIT_STATE2:
b927a3ce 2738 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2739 case KVM_CAP_XEN_HVM:
3cfc3092 2740 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2741 case KVM_CAP_HYPERV:
10388a07 2742 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2743 case KVM_CAP_HYPERV_SPIN:
5c919412 2744 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2745 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2746 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2747 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2748 case KVM_CAP_DEBUGREGS:
d2be1651 2749 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2750 case KVM_CAP_XSAVE:
344d9588 2751 case KVM_CAP_ASYNC_PF:
92a1f12d 2752 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2753 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2754 case KVM_CAP_READONLY_MEM:
5f66b620 2755 case KVM_CAP_HYPERV_TIME:
100943c5 2756 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2757 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2758 case KVM_CAP_ENABLE_CAP_VM:
2759 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2760 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2761 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2762 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2763 r = 1;
2764 break;
e3fd9a93
PB		 2765 case KVM_CAP_ADJUST_CLOCK:
2766 r = KVM_CLOCK_TSC_STABLE;
2767 break;
668fffa3
MT		 2768 case KVM_CAP_X86_GUEST_MWAIT:
2769 r = kvm_mwait_in_guest();
2770 break;
6d396b55
PB		 2771 case KVM_CAP_X86_SMM:
2772 /* SMBASE is usually relocated above 1M on modern chipsets,
2773 * and SMM handlers might indeed rely on 4G segment limits,
2774 * so do not report SMM to be available if real mode is
2775 * emulated via vm86 mode. Still, do not go to great lengths
2776 * to avoid userspace's usage of the feature, because it is a
2777 * fringe case that is not enabled except via specific settings
2778 * of the module parameters.
2779 */
2780 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2781 break;
774ead3a
AK		 2782 case KVM_CAP_VAPIC:
2783 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2784 break;
f725230a 2785 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2786 r = KVM_SOFT_MAX_VCPUS;
2787 break;
2788 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2789 r = KVM_MAX_VCPUS;
2790 break;
a988b910 2791 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2792 r = KVM_USER_MEM_SLOTS;
a988b910 2793 break;
a68a6a72
MT		 2794 case KVM_CAP_PV_MMU: /* obsolete */
2795 r = 0;
2f333bcb 2796 break;
890ca9ae
HY		 2797 case KVM_CAP_MCE:
2798 r = KVM_MAX_MCE_BANKS;
2799 break;
2d5b5a66 2800 case KVM_CAP_XCRS:
d366bf7e 2801 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2802 break;
92a1f12d
JR		 2803 case KVM_CAP_TSC_CONTROL:
2804 r = kvm_has_tsc_control;
2805 break;
37131313
RK		 2806 case KVM_CAP_X2APIC_API:
2807 r = KVM_X2APIC_API_VALID_FLAGS;
2808 break;
018d00d2
ZX		 2809 default:
2810 r = 0;
2811 break;
2812 }
2813 return r;
2814
2815}
2816
043405e1
CO		 2817long kvm_arch_dev_ioctl(struct file *filp,
2818 unsigned int ioctl, unsigned long arg)
2819{
2820 void __user *argp = (void __user *)arg;
2821 long r;
2822
2823 switch (ioctl) {
2824 case KVM_GET_MSR_INDEX_LIST: {
2825 struct kvm_msr_list __user *user_msr_list = argp;
2826 struct kvm_msr_list msr_list;
2827 unsigned n;
2828
2829 r = -EFAULT;
2830 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2831 goto out;
2832 n = msr_list.nmsrs;
62ef68bb 2833 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2834 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2835 goto out;
2836 r = -E2BIG;
e125e7b6 2837 if (n < msr_list.nmsrs)
043405e1
CO		 2838 goto out;
2839 r = -EFAULT;
2840 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2841 num_msrs_to_save * sizeof(u32)))
2842 goto out;
e125e7b6 2843 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2844 &emulated_msrs,
62ef68bb 2845 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2846 goto out;
2847 r = 0;
2848 break;
2849 }
9c15bb1d
BP		 2850 case KVM_GET_SUPPORTED_CPUID:
2851 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2852 struct kvm_cpuid2 __user *cpuid_arg = argp;
2853 struct kvm_cpuid2 cpuid;
2854
2855 r = -EFAULT;
2856 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2857 goto out;
9c15bb1d
BP		 2858
2859 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2860 ioctl);
674eea0f
AK		 2861 if (r)
2862 goto out;
2863
2864 r = -EFAULT;
2865 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2866 goto out;
2867 r = 0;
2868 break;
2869 }
890ca9ae 2870 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2871 r = -EFAULT;
c45dcc71
AR		 2872 if (copy_to_user(argp, &kvm_mce_cap_supported,
2873 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2874 goto out;
2875 r = 0;
2876 break;
2877 }
043405e1
CO		 2878 default:
2879 r = -EINVAL;
2880 }
2881out:
2882 return r;
2883}
2884
f5f48ee1
SY		 2885static void wbinvd_ipi(void *garbage)
2886{
2887 wbinvd();
2888}
2889
2890static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2891{
e0f0bbc5 2892 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2893}
2894
313a3dc7
CO		 2895void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2896{
f5f48ee1
SY		 2897 /* Address WBINVD may be executed by guest */
2898 if (need_emulate_wbinvd(vcpu)) {
2899 if (kvm_x86_ops->has_wbinvd_exit())
2900 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2901 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2902 smp_call_function_single(vcpu->cpu,
2903 wbinvd_ipi, NULL, 1);
2904 }
2905
313a3dc7 2906 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2907
0dd6a6ed
ZA		 2908 /* Apply any externally detected TSC adjustments (due to suspend) */
2909 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2910 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2911 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2912 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2913 }
8f6055cb 2914
b0c39dc6 2915 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 2916 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2917 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2918 if (tsc_delta < 0)
2919 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2920
b0c39dc6 2921 if (kvm_check_tsc_unstable()) {
07c1419a 2922 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2923 vcpu->arch.last_guest_tsc);
a545ab6a 2924 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2925 vcpu->arch.tsc_catchup = 1;
c285545f 2926 }
a749e247
PB		 2927
2928 if (kvm_lapic_hv_timer_in_use(vcpu))
2929 kvm_lapic_restart_hv_timer(vcpu);
2930
d98d07ca
MT		 2931 /*
2932 * On a host with synchronized TSC, there is no need to update
2933 * kvmclock on vcpu->cpu migration
2934 */
2935 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2936 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2937 if (vcpu->cpu != cpu)
1bd2009e 2938 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2939 vcpu->cpu = cpu;
6b7d7e76 2940 }
c9aaa895 2941
c9aaa895 2942 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2943}
2944
0b9f6c46
PX		 2945static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2946{
2947 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2948 return;
2949
2950 vcpu->arch.st.steal.preempted = 1;
2951
4e335d9e 2952 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 2953 &vcpu->arch.st.steal.preempted,
2954 offsetof(struct kvm_steal_time, preempted),
2955 sizeof(vcpu->arch.st.steal.preempted));
2956}
2957
313a3dc7
CO		 2958void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2959{
cc0d907c 2960 int idx;
de63ad4c
LM		 2961
2962 if (vcpu->preempted)
2963 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2964
931f261b
AA		 2965 /*
2966 * Disable page faults because we're in atomic context here.
2967 * kvm_write_guest_offset_cached() would call might_fault()
2968 * that relies on pagefault_disable() to tell if there's a
2969 * bug. NOTE: the write to guest memory may not go through if
2970 * during postcopy live migration or if there's heavy guest
2971 * paging.
2972 */
2973 pagefault_disable();
cc0d907c
AA		 2974 /*
2975 * kvm_memslots() will be called by
2976 * kvm_write_guest_offset_cached() so take the srcu lock.
2977 */
2978 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2979 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2980 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2981 pagefault_enable();
02daab21 2982 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 2983 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2984}
2985
313a3dc7
CO		 2986static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2987 struct kvm_lapic_state *s)
2988{
76dfafd5 2989 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2990 kvm_x86_ops->sync_pir_to_irr(vcpu);
2991
a92e2543 2992 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2993}
2994
2995static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2996 struct kvm_lapic_state *s)
2997{
a92e2543
RK		 2998 int r;
2999
3000 r = kvm_apic_set_state(vcpu, s);
3001 if (r)
3002 return r;
cb142eb7 3003 update_cr8_intercept(vcpu);
313a3dc7
CO		 3004
3005 return 0;
3006}
3007
127a457a
MG		 3008static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3009{
3010 return (!lapic_in_kernel(vcpu) ||
3011 kvm_apic_accept_pic_intr(vcpu));
3012}
3013
782d422b
MG		 3014/*
3015 * if userspace requested an interrupt window, check that the
3016 * interrupt window is open.
3017 *
3018 * No need to exit to userspace if we already have an interrupt queued.
3019 */
3020static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3021{
3022 return kvm_arch_interrupt_allowed(vcpu) &&
3023 !kvm_cpu_has_interrupt(vcpu) &&
3024 !kvm_event_needs_reinjection(vcpu) &&
3025 kvm_cpu_accept_dm_intr(vcpu);
3026}
3027
f77bc6a4
ZX		 3028static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3029 struct kvm_interrupt *irq)
3030{
02cdb50f 3031 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3032 return -EINVAL;
1c1a9ce9
SR		 3033
3034 if (!irqchip_in_kernel(vcpu->kvm)) {
3035 kvm_queue_interrupt(vcpu, irq->irq, false);
3036 kvm_make_request(KVM_REQ_EVENT, vcpu);
3037 return 0;
3038 }
3039
3040 /*
3041 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3042 * fail for in-kernel 8259.
3043 */
3044 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3045 return -ENXIO;
f77bc6a4 3046
1c1a9ce9
SR		 3047 if (vcpu->arch.pending_external_vector != -1)
3048 return -EEXIST;
f77bc6a4 3049
1c1a9ce9 3050 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3051 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3052 return 0;
3053}
3054
c4abb7c9
JK		 3055static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3056{
c4abb7c9 3057 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3058
3059 return 0;
3060}
3061
f077825a
PB		 3062static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3063{
64d60670
PB		 3064 kvm_make_request(KVM_REQ_SMI, vcpu);
3065
f077825a
PB		 3066 return 0;
3067}
3068
b209749f
AK		 3069static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3070 struct kvm_tpr_access_ctl *tac)
3071{
3072 if (tac->flags)
3073 return -EINVAL;
3074 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3075 return 0;
3076}
3077
890ca9ae
HY		 3078static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3079 u64 mcg_cap)
3080{
3081 int r;
3082 unsigned bank_num = mcg_cap & 0xff, bank;
3083
3084 r = -EINVAL;
a9e38c3e 3085 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3086 goto out;
c45dcc71 3087 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3088 goto out;
3089 r = 0;
3090 vcpu->arch.mcg_cap = mcg_cap;
3091 /* Init IA32_MCG_CTL to all 1s */
3092 if (mcg_cap & MCG_CTL_P)
3093 vcpu->arch.mcg_ctl = ~(u64)0;
3094 /* Init IA32_MCi_CTL to all 1s */
3095 for (bank = 0; bank < bank_num; bank++)
3096 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3097
3098 if (kvm_x86_ops->setup_mce)
3099 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3100out:
3101 return r;
3102}
3103
3104static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3105 struct kvm_x86_mce *mce)
3106{
3107 u64 mcg_cap = vcpu->arch.mcg_cap;
3108 unsigned bank_num = mcg_cap & 0xff;
3109 u64 *banks = vcpu->arch.mce_banks;
3110
3111 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3112 return -EINVAL;
3113 /*
3114 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3115 * reporting is disabled
3116 */
3117 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3118 vcpu->arch.mcg_ctl != ~(u64)0)
3119 return 0;
3120 banks += 4 * mce->bank;
3121 /*
3122 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3123 * reporting is disabled for the bank
3124 */
3125 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3126 return 0;
3127 if (mce->status & MCI_STATUS_UC) {
3128 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3129 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3130 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3131 return 0;
3132 }
3133 if (banks[1] & MCI_STATUS_VAL)
3134 mce->status |= MCI_STATUS_OVER;
3135 banks[2] = mce->addr;
3136 banks[3] = mce->misc;
3137 vcpu->arch.mcg_status = mce->mcg_status;
3138 banks[1] = mce->status;
3139 kvm_queue_exception(vcpu, MC_VECTOR);
3140 } else if (!(banks[1] & MCI_STATUS_VAL)
3141 || !(banks[1] & MCI_STATUS_UC)) {
3142 if (banks[1] & MCI_STATUS_VAL)
3143 mce->status |= MCI_STATUS_OVER;
3144 banks[2] = mce->addr;
3145 banks[3] = mce->misc;
3146 banks[1] = mce->status;
3147 } else
3148 banks[1] |= MCI_STATUS_OVER;
3149 return 0;
3150}
3151
3cfc3092
JK		 3152static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3153 struct kvm_vcpu_events *events)
3154{
7460fb4a 3155 process_nmi(vcpu);
664f8e26
WL		 3156 /*
3157 * FIXME: pass injected and pending separately. This is only
3158 * needed for nested virtualization, whose state cannot be
3159 * migrated yet. For now we can combine them.
3160 */
03b82a30 3161 events->exception.injected =
664f8e26
WL		 3162 (vcpu->arch.exception.pending ||
3163 vcpu->arch.exception.injected) &&
03b82a30 3164 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3165 events->exception.nr = vcpu->arch.exception.nr;
3166 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3167 events->exception.pad = 0;
3cfc3092
JK		 3168 events->exception.error_code = vcpu->arch.exception.error_code;
3169
03b82a30
JK		 3170 events->interrupt.injected =
3171 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3172 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3173 events->interrupt.soft = 0;
37ccdcbe 3174 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3175
3176 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3177 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3178 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3179 events->nmi.pad = 0;
3cfc3092 3180
66450a21 3181 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3182
f077825a
PB		 3183 events->smi.smm = is_smm(vcpu);
3184 events->smi.pending = vcpu->arch.smi_pending;
3185 events->smi.smm_inside_nmi =
3186 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3187 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3188
dab4b911 3189 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3190 | KVM_VCPUEVENT_VALID_SHADOW
3191 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3192 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3193}
3194
6ef4e07e
XG		 3195static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3196
3cfc3092
JK		 3197static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3198 struct kvm_vcpu_events *events)
3199{
dab4b911 3200 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3201 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3202 | KVM_VCPUEVENT_VALID_SHADOW
3203 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3204 return -EINVAL;
3205
78e546c8 3206 if (events->exception.injected &&
28d06353
JM		 3207 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3208 is_guest_mode(vcpu)))
78e546c8
PB		 3209 return -EINVAL;
3210
28bf2888
DH		 3211 /* INITs are latched while in SMM */
3212 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3213 (events->smi.smm || events->smi.pending) &&
3214 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3215 return -EINVAL;
3216
7460fb4a 3217 process_nmi(vcpu);
664f8e26 3218 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3219 vcpu->arch.exception.pending = events->exception.injected;
3220 vcpu->arch.exception.nr = events->exception.nr;
3221 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3222 vcpu->arch.exception.error_code = events->exception.error_code;
3223
3224 vcpu->arch.interrupt.pending = events->interrupt.injected;
3225 vcpu->arch.interrupt.nr = events->interrupt.nr;
3226 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3227 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3228 kvm_x86_ops->set_interrupt_shadow(vcpu,
3229 events->interrupt.shadow);
3cfc3092
JK		 3230
3231 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3232 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3233 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3234 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3235
66450a21 3236 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3237 lapic_in_kernel(vcpu))
66450a21 3238 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3239
f077825a 3240 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3241 u32 hflags = vcpu->arch.hflags;
f077825a 3242 if (events->smi.smm)
6ef4e07e 3243 hflags |= HF_SMM_MASK;
f077825a 3244 else
6ef4e07e
XG		 3245 hflags &= ~HF_SMM_MASK;
3246 kvm_set_hflags(vcpu, hflags);
3247
f077825a 3248 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3249
3250 if (events->smi.smm) {
3251 if (events->smi.smm_inside_nmi)
3252 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3253 else
f4ef1910
WL		 3254 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3255 if (lapic_in_kernel(vcpu)) {
3256 if (events->smi.latched_init)
3257 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3258 else
3259 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3260 }
f077825a
PB		 3261 }
3262 }
3263
3842d135
AK		 3264 kvm_make_request(KVM_REQ_EVENT, vcpu);
3265
3cfc3092
JK		 3266 return 0;
3267}
3268
a1efbe77
JK		 3269static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3270 struct kvm_debugregs *dbgregs)
3271{
73aaf249
JK		 3272 unsigned long val;
3273
a1efbe77 3274 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3275 kvm_get_dr(vcpu, 6, &val);
73aaf249 3276 dbgregs->dr6 = val;
a1efbe77
JK		 3277 dbgregs->dr7 = vcpu->arch.dr7;
3278 dbgregs->flags = 0;
97e69aa6 3279 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3280}
3281
3282static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3283 struct kvm_debugregs *dbgregs)
3284{
3285 if (dbgregs->flags)
3286 return -EINVAL;
3287
d14bdb55
PB		 3288 if (dbgregs->dr6 & ~0xffffffffull)
3289 return -EINVAL;
3290 if (dbgregs->dr7 & ~0xffffffffull)
3291 return -EINVAL;
3292
a1efbe77 3293 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3294 kvm_update_dr0123(vcpu);
a1efbe77 3295 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3296 kvm_update_dr6(vcpu);
a1efbe77 3297 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3298 kvm_update_dr7(vcpu);
a1efbe77 3299
a1efbe77
JK		 3300 return 0;
3301}
3302
df1daba7
PB		 3303#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3304
3305static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3306{
c47ada30 3307 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3308 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3309 u64 valid;
3310
3311 /*
3312 * Copy legacy XSAVE area, to avoid complications with CPUID
3313 * leaves 0 and 1 in the loop below.
3314 */
3315 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3316
3317 /* Set XSTATE_BV */
00c87e9a 3318 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3319 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3320
3321 /*
3322 * Copy each region from the possibly compacted offset to the
3323 * non-compacted offset.
3324 */
d91cab78 3325 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3326 while (valid) {
3327 u64 feature = valid & -valid;
3328 int index = fls64(feature) - 1;
3329 void *src = get_xsave_addr(xsave, feature);
3330
3331 if (src) {
3332 u32 size, offset, ecx, edx;
3333 cpuid_count(XSTATE_CPUID, index,
3334 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3335 if (feature == XFEATURE_MASK_PKRU)
3336 memcpy(dest + offset, &vcpu->arch.pkru,
3337 sizeof(vcpu->arch.pkru));
3338 else
3339 memcpy(dest + offset, src, size);
3340
df1daba7
PB		 3341 }
3342
3343 valid -= feature;
3344 }
3345}
3346
3347static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3348{
c47ada30 3349 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3350 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3351 u64 valid;
3352
3353 /*
3354 * Copy legacy XSAVE area, to avoid complications with CPUID
3355 * leaves 0 and 1 in the loop below.
3356 */
3357 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3358
3359 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3360 xsave->header.xfeatures = xstate_bv;
782511b0 3361 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3362 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3363
3364 /*
3365 * Copy each region from the non-compacted offset to the
3366 * possibly compacted offset.
3367 */
d91cab78 3368 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3369 while (valid) {
3370 u64 feature = valid & -valid;
3371 int index = fls64(feature) - 1;
3372 void *dest = get_xsave_addr(xsave, feature);
3373
3374 if (dest) {
3375 u32 size, offset, ecx, edx;
3376 cpuid_count(XSTATE_CPUID, index,
3377 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3378 if (feature == XFEATURE_MASK_PKRU)
3379 memcpy(&vcpu->arch.pkru, src + offset,
3380 sizeof(vcpu->arch.pkru));
3381 else
3382 memcpy(dest, src + offset, size);
ee4100da 3383 }
df1daba7
PB		 3384
3385 valid -= feature;
3386 }
3387}
3388
2d5b5a66
SY		 3389static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3390 struct kvm_xsave *guest_xsave)
3391{
d366bf7e 3392 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3393 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3394 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3395 } else {
2d5b5a66 3396 memcpy(guest_xsave->region,
7366ed77 3397 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3398 sizeof(struct fxregs_state));
2d5b5a66 3399 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3400 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3401 }
3402}
3403
a575813b
WL		 3404#define XSAVE_MXCSR_OFFSET 24
3405
2d5b5a66
SY		 3406static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3407 struct kvm_xsave *guest_xsave)
3408{
3409 u64 xstate_bv =
3410 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3411 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3412
d366bf7e 3413 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3414 /*
3415 * Here we allow setting states that are not present in
3416 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3417 * with old userspace.
3418 */
a575813b
WL		 3419 if (xstate_bv & ~kvm_supported_xcr0() ||
3420 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3421 return -EINVAL;
df1daba7 3422 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3423 } else {
a575813b
WL		 3424 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3425 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3426 return -EINVAL;
7366ed77 3427 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3428 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3429 }
3430 return 0;
3431}
3432
3433static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3434 struct kvm_xcrs *guest_xcrs)
3435{
d366bf7e 3436 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3437 guest_xcrs->nr_xcrs = 0;
3438 return;
3439 }
3440
3441 guest_xcrs->nr_xcrs = 1;
3442 guest_xcrs->flags = 0;
3443 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3444 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3445}
3446
3447static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3448 struct kvm_xcrs *guest_xcrs)
3449{
3450 int i, r = 0;
3451
d366bf7e 3452 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3453 return -EINVAL;
3454
3455 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3456 return -EINVAL;
3457
3458 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3459 /* Only support XCR0 currently */
c67a04cb 3460 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3461 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3462 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3463 break;
3464 }
3465 if (r)
3466 r = -EINVAL;
3467 return r;
3468}
3469
1c0b28c2
EM		 3470/*
3471 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3472 * stopped by the hypervisor. This function will be called from the host only.
3473 * EINVAL is returned when the host attempts to set the flag for a guest that
3474 * does not support pv clocks.
3475 */
3476static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3477{
0b79459b 3478 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3479 return -EINVAL;
51d59c6b 3480 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3481 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3482 return 0;
3483}
3484
5c919412
AS		 3485static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3486 struct kvm_enable_cap *cap)
3487{
3488 if (cap->flags)
3489 return -EINVAL;
3490
3491 switch (cap->cap) {
efc479e6
RK		 3492 case KVM_CAP_HYPERV_SYNIC2:
3493 if (cap->args[0])
3494 return -EINVAL;
5c919412 3495 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3496 if (!irqchip_in_kernel(vcpu->kvm))
3497 return -EINVAL;
efc479e6
RK		 3498 return kvm_hv_activate_synic(vcpu, cap->cap ==
3499 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3500 default:
3501 return -EINVAL;
3502 }
3503}
3504
313a3dc7
CO		 3505long kvm_arch_vcpu_ioctl(struct file *filp,
3506 unsigned int ioctl, unsigned long arg)
3507{
3508 struct kvm_vcpu *vcpu = filp->private_data;
3509 void __user *argp = (void __user *)arg;
3510 int r;
d1ac91d8
AK		 3511 union {
3512 struct kvm_lapic_state *lapic;
3513 struct kvm_xsave *xsave;
3514 struct kvm_xcrs *xcrs;
3515 void *buffer;
3516 } u;
3517
3518 u.buffer = NULL;
313a3dc7
CO		 3519 switch (ioctl) {
3520 case KVM_GET_LAPIC: {
2204ae3c 3521 r = -EINVAL;
bce87cce 3522 if (!lapic_in_kernel(vcpu))
2204ae3c 3523 goto out;
d1ac91d8 3524 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3525
b772ff36 3526 r = -ENOMEM;
d1ac91d8 3527 if (!u.lapic)
b772ff36 3528 goto out;
d1ac91d8 3529 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3530 if (r)
3531 goto out;
3532 r = -EFAULT;
d1ac91d8 3533 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3534 goto out;
3535 r = 0;
3536 break;
3537 }
3538 case KVM_SET_LAPIC: {
2204ae3c 3539 r = -EINVAL;
bce87cce 3540 if (!lapic_in_kernel(vcpu))
2204ae3c 3541 goto out;
ff5c2c03 3542 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3543 if (IS_ERR(u.lapic))
3544 return PTR_ERR(u.lapic);
ff5c2c03 3545
d1ac91d8 3546 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3547 break;
3548 }
f77bc6a4
ZX		 3549 case KVM_INTERRUPT: {
3550 struct kvm_interrupt irq;
3551
3552 r = -EFAULT;
3553 if (copy_from_user(&irq, argp, sizeof irq))
3554 goto out;
3555 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3556 break;
3557 }
c4abb7c9
JK		 3558 case KVM_NMI: {
3559 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3560 break;
3561 }
f077825a
PB		 3562 case KVM_SMI: {
3563 r = kvm_vcpu_ioctl_smi(vcpu);
3564 break;
3565 }
313a3dc7
CO		 3566 case KVM_SET_CPUID: {
3567 struct kvm_cpuid __user *cpuid_arg = argp;
3568 struct kvm_cpuid cpuid;
3569
3570 r = -EFAULT;
3571 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3572 goto out;
3573 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3574 break;
3575 }
07716717
DK		 3576 case KVM_SET_CPUID2: {
3577 struct kvm_cpuid2 __user *cpuid_arg = argp;
3578 struct kvm_cpuid2 cpuid;
3579
3580 r = -EFAULT;
3581 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3582 goto out;
3583 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3584 cpuid_arg->entries);
07716717
DK		 3585 break;
3586 }
3587 case KVM_GET_CPUID2: {
3588 struct kvm_cpuid2 __user *cpuid_arg = argp;
3589 struct kvm_cpuid2 cpuid;
3590
3591 r = -EFAULT;
3592 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3593 goto out;
3594 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3595 cpuid_arg->entries);
07716717
DK		 3596 if (r)
3597 goto out;
3598 r = -EFAULT;
3599 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3600 goto out;
3601 r = 0;
3602 break;
3603 }
313a3dc7 3604 case KVM_GET_MSRS:
609e36d3 3605 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3606 break;
3607 case KVM_SET_MSRS:
3608 r = msr_io(vcpu, argp, do_set_msr, 0);
3609 break;
b209749f
AK		 3610 case KVM_TPR_ACCESS_REPORTING: {
3611 struct kvm_tpr_access_ctl tac;
3612
3613 r = -EFAULT;
3614 if (copy_from_user(&tac, argp, sizeof tac))
3615 goto out;
3616 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3617 if (r)
3618 goto out;
3619 r = -EFAULT;
3620 if (copy_to_user(argp, &tac, sizeof tac))
3621 goto out;
3622 r = 0;
3623 break;
3624 };
b93463aa
AK		 3625 case KVM_SET_VAPIC_ADDR: {
3626 struct kvm_vapic_addr va;
7301d6ab 3627 int idx;
b93463aa
AK		 3628
3629 r = -EINVAL;
35754c98 3630 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3631 goto out;
3632 r = -EFAULT;
3633 if (copy_from_user(&va, argp, sizeof va))
3634 goto out;
7301d6ab 3635 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3636 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3637 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3638 break;
3639 }
890ca9ae
HY		 3640 case KVM_X86_SETUP_MCE: {
3641 u64 mcg_cap;
3642
3643 r = -EFAULT;
3644 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3645 goto out;
3646 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3647 break;
3648 }
3649 case KVM_X86_SET_MCE: {
3650 struct kvm_x86_mce mce;
3651
3652 r = -EFAULT;
3653 if (copy_from_user(&mce, argp, sizeof mce))
3654 goto out;
3655 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3656 break;
3657 }
3cfc3092
JK		 3658 case KVM_GET_VCPU_EVENTS: {
3659 struct kvm_vcpu_events events;
3660
3661 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3662
3663 r = -EFAULT;
3664 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3665 break;
3666 r = 0;
3667 break;
3668 }
3669 case KVM_SET_VCPU_EVENTS: {
3670 struct kvm_vcpu_events events;
3671
3672 r = -EFAULT;
3673 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3674 break;
3675
3676 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3677 break;
3678 }
a1efbe77
JK		 3679 case KVM_GET_DEBUGREGS: {
3680 struct kvm_debugregs dbgregs;
3681
3682 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3683
3684 r = -EFAULT;
3685 if (copy_to_user(argp, &dbgregs,
3686 sizeof(struct kvm_debugregs)))
3687 break;
3688 r = 0;
3689 break;
3690 }
3691 case KVM_SET_DEBUGREGS: {
3692 struct kvm_debugregs dbgregs;
3693
3694 r = -EFAULT;
3695 if (copy_from_user(&dbgregs, argp,
3696 sizeof(struct kvm_debugregs)))
3697 break;
3698
3699 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3700 break;
3701 }
2d5b5a66 3702 case KVM_GET_XSAVE: {
d1ac91d8 3703 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3704 r = -ENOMEM;
d1ac91d8 3705 if (!u.xsave)
2d5b5a66
SY		 3706 break;
3707
d1ac91d8 3708 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3709
3710 r = -EFAULT;
d1ac91d8 3711 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3712 break;
3713 r = 0;
3714 break;
3715 }
3716 case KVM_SET_XSAVE: {
ff5c2c03 3717 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3718 if (IS_ERR(u.xsave))
3719 return PTR_ERR(u.xsave);
2d5b5a66 3720
d1ac91d8 3721 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3722 break;
3723 }
3724 case KVM_GET_XCRS: {
d1ac91d8 3725 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3726 r = -ENOMEM;
d1ac91d8 3727 if (!u.xcrs)
2d5b5a66
SY		 3728 break;
3729
d1ac91d8 3730 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3731
3732 r = -EFAULT;
d1ac91d8 3733 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3734 sizeof(struct kvm_xcrs)))
3735 break;
3736 r = 0;
3737 break;
3738 }
3739 case KVM_SET_XCRS: {
ff5c2c03 3740 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3741 if (IS_ERR(u.xcrs))
3742 return PTR_ERR(u.xcrs);
2d5b5a66 3743
d1ac91d8 3744 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3745 break;
3746 }
92a1f12d
JR		 3747 case KVM_SET_TSC_KHZ: {
3748 u32 user_tsc_khz;
3749
3750 r = -EINVAL;
92a1f12d
JR		 3751 user_tsc_khz = (u32)arg;
3752
3753 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3754 goto out;
3755
cc578287
ZA		 3756 if (user_tsc_khz == 0)
3757 user_tsc_khz = tsc_khz;
3758
381d585c
HZ		 3759 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3760 r = 0;
92a1f12d 3761
92a1f12d
JR		 3762 goto out;
3763 }
3764 case KVM_GET_TSC_KHZ: {
cc578287 3765 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3766 goto out;
3767 }
1c0b28c2
EM		 3768 case KVM_KVMCLOCK_CTRL: {
3769 r = kvm_set_guest_paused(vcpu);
3770 goto out;
3771 }
5c919412
AS		 3772 case KVM_ENABLE_CAP: {
3773 struct kvm_enable_cap cap;
3774
3775 r = -EFAULT;
3776 if (copy_from_user(&cap, argp, sizeof(cap)))
3777 goto out;
3778 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3779 break;
3780 }
313a3dc7
CO		 3781 default:
3782 r = -EINVAL;
3783 }
3784out:
d1ac91d8 3785 kfree(u.buffer);
313a3dc7
CO		 3786 return r;
3787}
3788
5b1c1493
CO		 3789int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3790{
3791 return VM_FAULT_SIGBUS;
3792}
3793
1fe779f8
CO		 3794static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3795{
3796 int ret;
3797
3798 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3799 return -EINVAL;
1fe779f8
CO		 3800 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3801 return ret;
3802}
3803
b927a3ce
SY		 3804static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3805 u64 ident_addr)
3806{
3807 kvm->arch.ept_identity_map_addr = ident_addr;
3808 return 0;
3809}
3810
1fe779f8
CO		 3811static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3812 u32 kvm_nr_mmu_pages)
3813{
3814 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3815 return -EINVAL;
3816
79fac95e 3817 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3818
3819 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3820 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3821
79fac95e 3822 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3823 return 0;
3824}
3825
3826static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3827{
39de71ec 3828 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3829}
3830
1fe779f8
CO		 3831static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3832{
90bca052 3833 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3834 int r;
3835
3836 r = 0;
3837 switch (chip->chip_id) {
3838 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3839 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3840 sizeof(struct kvm_pic_state));
3841 break;
3842 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3843 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3844 sizeof(struct kvm_pic_state));
3845 break;
3846 case KVM_IRQCHIP_IOAPIC:
33392b49 3847 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3848 break;
3849 default:
3850 r = -EINVAL;
3851 break;
3852 }
3853 return r;
3854}
3855
3856static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3857{
90bca052 3858 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3859 int r;
3860
3861 r = 0;
3862 switch (chip->chip_id) {
3863 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3864 spin_lock(&pic->lock);
3865 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3866 sizeof(struct kvm_pic_state));
90bca052 3867 spin_unlock(&pic->lock);
1fe779f8
CO		 3868 break;
3869 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3870 spin_lock(&pic->lock);
3871 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3872 sizeof(struct kvm_pic_state));
90bca052 3873 spin_unlock(&pic->lock);
1fe779f8
CO		 3874 break;
3875 case KVM_IRQCHIP_IOAPIC:
33392b49 3876 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3877 break;
3878 default:
3879 r = -EINVAL;
3880 break;
3881 }
90bca052 3882 kvm_pic_update_irq(pic);
1fe779f8
CO		 3883 return r;
3884}
3885
e0f63cb9
SY		 3886static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3887{
34f3941c
RK		 3888 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3889
3890 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3891
3892 mutex_lock(&kps->lock);
3893 memcpy(ps, &kps->channels, sizeof(*ps));
3894 mutex_unlock(&kps->lock);
2da29bcc 3895 return 0;
e0f63cb9
SY		 3896}
3897
3898static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3899{
0185604c 3900 int i;
09edea72
RK		 3901 struct kvm_pit *pit = kvm->arch.vpit;
3902
3903 mutex_lock(&pit->pit_state.lock);
34f3941c 3904 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3905 for (i = 0; i < 3; i++)
09edea72
RK		 3906 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3907 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3908 return 0;
e9f42757
BK		 3909}
3910
3911static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3912{
e9f42757
BK		 3913 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3914 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3915 sizeof(ps->channels));
3916 ps->flags = kvm->arch.vpit->pit_state.flags;
3917 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3918 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3919 return 0;
e9f42757
BK		 3920}
3921
3922static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3923{
2da29bcc 3924 int start = 0;
0185604c 3925 int i;
e9f42757 3926 u32 prev_legacy, cur_legacy;
09edea72
RK		 3927 struct kvm_pit *pit = kvm->arch.vpit;
3928
3929 mutex_lock(&pit->pit_state.lock);
3930 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3931 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3932 if (!prev_legacy && cur_legacy)
3933 start = 1;
09edea72
RK		 3934 memcpy(&pit->pit_state.channels, &ps->channels,
3935 sizeof(pit->pit_state.channels));
3936 pit->pit_state.flags = ps->flags;
0185604c 3937 for (i = 0; i < 3; i++)
09edea72 3938 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3939 start && i == 0);
09edea72 3940 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3941 return 0;
e0f63cb9
SY		 3942}
3943
52d939a0
MT		 3944static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3945 struct kvm_reinject_control *control)
3946{
71474e2f
RK		 3947 struct kvm_pit *pit = kvm->arch.vpit;
3948
3949 if (!pit)
52d939a0 3950 return -ENXIO;
b39c90b6 3951
71474e2f
RK		 3952 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3953 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3954 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3955 */
3956 mutex_lock(&pit->pit_state.lock);
3957 kvm_pit_set_reinject(pit, control->pit_reinject);
3958 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3959
52d939a0
MT		 3960 return 0;
3961}
3962
95d4c16c 3963/**
60c34612
TY		 3964 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3965 * @kvm: kvm instance
3966 * @log: slot id and address to which we copy the log
95d4c16c 3967 *
e108ff2f
PB		 3968 * Steps 1-4 below provide general overview of dirty page logging. See
3969 * kvm_get_dirty_log_protect() function description for additional details.
3970 *
3971 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3972 * always flush the TLB (step 4) even if previous step failed and the dirty
3973 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3974 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3975 * writes will be marked dirty for next log read.
95d4c16c 3976 *
60c34612
TY		 3977 * 1. Take a snapshot of the bit and clear it if needed.
3978 * 2. Write protect the corresponding page.
e108ff2f
PB		 3979 * 3. Copy the snapshot to the userspace.
3980 * 4. Flush TLB's if needed.
5bb064dc 3981 */
60c34612 3982int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3983{
60c34612 3984 bool is_dirty = false;
e108ff2f 3985 int r;
5bb064dc 3986
79fac95e 3987 mutex_lock(&kvm->slots_lock);
5bb064dc 3988
88178fd4
KH		 3989 /*
3990 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3991 */
3992 if (kvm_x86_ops->flush_log_dirty)
3993 kvm_x86_ops->flush_log_dirty(kvm);
3994
e108ff2f 3995 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3996
3997 /*
3998 * All the TLBs can be flushed out of mmu lock, see the comments in
3999 * kvm_mmu_slot_remove_write_access().
4000 */
e108ff2f 4001 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4002 if (is_dirty)
4003 kvm_flush_remote_tlbs(kvm);
4004
79fac95e 4005 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4006 return r;
4007}
4008
aa2fbe6d
YZ		 4009int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4010 bool line_status)
23d43cf9
CD		 4011{
4012 if (!irqchip_in_kernel(kvm))
4013 return -ENXIO;
4014
4015 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4016 irq_event->irq, irq_event->level,
4017 line_status);
23d43cf9
CD		 4018 return 0;
4019}
4020
90de4a18
NA		 4021static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4022 struct kvm_enable_cap *cap)
4023{
4024 int r;
4025
4026 if (cap->flags)
4027 return -EINVAL;
4028
4029 switch (cap->cap) {
4030 case KVM_CAP_DISABLE_QUIRKS:
4031 kvm->arch.disabled_quirks = cap->args[0];
4032 r = 0;
4033 break;
49df6397
SR		 4034 case KVM_CAP_SPLIT_IRQCHIP: {
4035 mutex_lock(&kvm->lock);
b053b2ae
SR		 4036 r = -EINVAL;
4037 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4038 goto split_irqchip_unlock;
49df6397
SR		 4039 r = -EEXIST;
4040 if (irqchip_in_kernel(kvm))
4041 goto split_irqchip_unlock;
557abc40 4042 if (kvm->created_vcpus)
49df6397
SR		 4043 goto split_irqchip_unlock;
4044 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4045 if (r)
49df6397
SR		 4046 goto split_irqchip_unlock;
4047 /* Pairs with irqchip_in_kernel. */
4048 smp_wmb();
49776faf 4049 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4050 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4051 r = 0;
4052split_irqchip_unlock:
4053 mutex_unlock(&kvm->lock);
4054 break;
4055 }
37131313
RK		 4056 case KVM_CAP_X2APIC_API:
4057 r = -EINVAL;
4058 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4059 break;
4060
4061 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4062 kvm->arch.x2apic_format = true;
c519265f
RK		 4063 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4064 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4065
4066 r = 0;
4067 break;
90de4a18
NA		 4068 default:
4069 r = -EINVAL;
4070 break;
4071 }
4072 return r;
4073}
4074
1fe779f8
CO		 4075long kvm_arch_vm_ioctl(struct file *filp,
4076 unsigned int ioctl, unsigned long arg)
4077{
4078 struct kvm *kvm = filp->private_data;
4079 void __user *argp = (void __user *)arg;
367e1319 4080 int r = -ENOTTY;
f0d66275
DH		 4081 /*
4082 * This union makes it completely explicit to gcc-3.x
4083 * that these two variables' stack usage should be
4084 * combined, not added together.
4085 */
4086 union {
4087 struct kvm_pit_state ps;
e9f42757 4088 struct kvm_pit_state2 ps2;
c5ff41ce 4089 struct kvm_pit_config pit_config;
f0d66275 4090 } u;
1fe779f8
CO		 4091
4092 switch (ioctl) {
4093 case KVM_SET_TSS_ADDR:
4094 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4095 break;
b927a3ce
SY		 4096 case KVM_SET_IDENTITY_MAP_ADDR: {
4097 u64 ident_addr;
4098
1af1ac91
DH		 4099 mutex_lock(&kvm->lock);
4100 r = -EINVAL;
4101 if (kvm->created_vcpus)
4102 goto set_identity_unlock;
b927a3ce
SY		 4103 r = -EFAULT;
4104 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4105 goto set_identity_unlock;
b927a3ce 4106 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4107set_identity_unlock:
4108 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4109 break;
4110 }
1fe779f8
CO		 4111 case KVM_SET_NR_MMU_PAGES:
4112 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4113 break;
4114 case KVM_GET_NR_MMU_PAGES:
4115 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4116 break;
3ddea128 4117 case KVM_CREATE_IRQCHIP: {
3ddea128 4118 mutex_lock(&kvm->lock);
09941366 4119
3ddea128 4120 r = -EEXIST;
35e6eaa3 4121 if (irqchip_in_kernel(kvm))
3ddea128 4122 goto create_irqchip_unlock;
09941366 4123
3e515705 4124 r = -EINVAL;
557abc40 4125 if (kvm->created_vcpus)
3e515705 4126 goto create_irqchip_unlock;
09941366
RK		 4127
4128 r = kvm_pic_init(kvm);
4129 if (r)
3ddea128 4130 goto create_irqchip_unlock;
09941366
RK		 4131
4132 r = kvm_ioapic_init(kvm);
4133 if (r) {
09941366 4134 kvm_pic_destroy(kvm);
3ddea128 4135 goto create_irqchip_unlock;
09941366
RK		 4136 }
4137
399ec807
AK		 4138 r = kvm_setup_default_irq_routing(kvm);
4139 if (r) {
72bb2fcd 4140 kvm_ioapic_destroy(kvm);
09941366 4141 kvm_pic_destroy(kvm);
71ba994c 4142 goto create_irqchip_unlock;
399ec807 4143 }
49776faf 4144 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4145 smp_wmb();
49776faf 4146 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4147 create_irqchip_unlock:
4148 mutex_unlock(&kvm->lock);
1fe779f8 4149 break;
3ddea128 4150 }
7837699f 4151 case KVM_CREATE_PIT:
c5ff41ce
JK		 4152 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4153 goto create_pit;
4154 case KVM_CREATE_PIT2:
4155 r = -EFAULT;
4156 if (copy_from_user(&u.pit_config, argp,
4157 sizeof(struct kvm_pit_config)))
4158 goto out;
4159 create_pit:
250715a6 4160 mutex_lock(&kvm->lock);
269e05e4
AK		 4161 r = -EEXIST;
4162 if (kvm->arch.vpit)
4163 goto create_pit_unlock;
7837699f 4164 r = -ENOMEM;
c5ff41ce 4165 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4166 if (kvm->arch.vpit)
4167 r = 0;
269e05e4 4168 create_pit_unlock:
250715a6 4169 mutex_unlock(&kvm->lock);
7837699f 4170 break;
1fe779f8
CO		 4171 case KVM_GET_IRQCHIP: {
4172 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4173 struct kvm_irqchip *chip;
1fe779f8 4174
ff5c2c03
SL		 4175 chip = memdup_user(argp, sizeof(*chip));
4176 if (IS_ERR(chip)) {
4177 r = PTR_ERR(chip);
1fe779f8 4178 goto out;
ff5c2c03
SL		 4179 }
4180
1fe779f8 4181 r = -ENXIO;
826da321 4182 if (!irqchip_kernel(kvm))
f0d66275
DH		 4183 goto get_irqchip_out;
4184 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4185 if (r)
f0d66275 4186 goto get_irqchip_out;
1fe779f8 4187 r = -EFAULT;
f0d66275
DH		 4188 if (copy_to_user(argp, chip, sizeof *chip))
4189 goto get_irqchip_out;
1fe779f8 4190 r = 0;
f0d66275
DH		 4191 get_irqchip_out:
4192 kfree(chip);
1fe779f8
CO		 4193 break;
4194 }
4195 case KVM_SET_IRQCHIP: {
4196 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4197 struct kvm_irqchip *chip;
1fe779f8 4198
ff5c2c03
SL		 4199 chip = memdup_user(argp, sizeof(*chip));
4200 if (IS_ERR(chip)) {
4201 r = PTR_ERR(chip);
1fe779f8 4202 goto out;
ff5c2c03
SL		 4203 }
4204
1fe779f8 4205 r = -ENXIO;
826da321 4206 if (!irqchip_kernel(kvm))
f0d66275
DH		 4207 goto set_irqchip_out;
4208 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4209 if (r)
f0d66275 4210 goto set_irqchip_out;
1fe779f8 4211 r = 0;
f0d66275
DH		 4212 set_irqchip_out:
4213 kfree(chip);
1fe779f8
CO		 4214 break;
4215 }
e0f63cb9 4216 case KVM_GET_PIT: {
e0f63cb9 4217 r = -EFAULT;
f0d66275 4218 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4219 goto out;
4220 r = -ENXIO;
4221 if (!kvm->arch.vpit)
4222 goto out;
f0d66275 4223 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4224 if (r)
4225 goto out;
4226 r = -EFAULT;
f0d66275 4227 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4228 goto out;
4229 r = 0;
4230 break;
4231 }
4232 case KVM_SET_PIT: {
e0f63cb9 4233 r = -EFAULT;
f0d66275 4234 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4235 goto out;
4236 r = -ENXIO;
4237 if (!kvm->arch.vpit)
4238 goto out;
f0d66275 4239 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4240 break;
4241 }
e9f42757
BK		 4242 case KVM_GET_PIT2: {
4243 r = -ENXIO;
4244 if (!kvm->arch.vpit)
4245 goto out;
4246 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4247 if (r)
4248 goto out;
4249 r = -EFAULT;
4250 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4251 goto out;
4252 r = 0;
4253 break;
4254 }
4255 case KVM_SET_PIT2: {
4256 r = -EFAULT;
4257 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4258 goto out;
4259 r = -ENXIO;
4260 if (!kvm->arch.vpit)
4261 goto out;
4262 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4263 break;
4264 }
52d939a0
MT		 4265 case KVM_REINJECT_CONTROL: {
4266 struct kvm_reinject_control control;
4267 r = -EFAULT;
4268 if (copy_from_user(&control, argp, sizeof(control)))
4269 goto out;
4270 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4271 break;
4272 }
d71ba788
PB		 4273 case KVM_SET_BOOT_CPU_ID:
4274 r = 0;
4275 mutex_lock(&kvm->lock);
557abc40 4276 if (kvm->created_vcpus)
d71ba788
PB		 4277 r = -EBUSY;
4278 else
4279 kvm->arch.bsp_vcpu_id = arg;
4280 mutex_unlock(&kvm->lock);
4281 break;
ffde22ac
ES		 4282 case KVM_XEN_HVM_CONFIG: {
4283 r = -EFAULT;
4284 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4285 sizeof(struct kvm_xen_hvm_config)))
4286 goto out;
4287 r = -EINVAL;
4288 if (kvm->arch.xen_hvm_config.flags)
4289 goto out;
4290 r = 0;
4291 break;
4292 }
afbcf7ab 4293 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4294 struct kvm_clock_data user_ns;
4295 u64 now_ns;
afbcf7ab
GC		 4296
4297 r = -EFAULT;
4298 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4299 goto out;
4300
4301 r = -EINVAL;
4302 if (user_ns.flags)
4303 goto out;
4304
4305 r = 0;
0bc48bea
RK		 4306 /*
4307 * TODO: userspace has to take care of races with VCPU_RUN, so
4308 * kvm_gen_update_masterclock() can be cut down to locked
4309 * pvclock_update_vm_gtod_copy().
4310 */
4311 kvm_gen_update_masterclock(kvm);
e891a32e 4312 now_ns = get_kvmclock_ns(kvm);
108b249c 4313 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4314 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4315 break;
4316 }
4317 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4318 struct kvm_clock_data user_ns;
4319 u64 now_ns;
4320
e891a32e 4321 now_ns = get_kvmclock_ns(kvm);
108b249c 4322 user_ns.clock = now_ns;
e3fd9a93 4323 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4324 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4325
4326 r = -EFAULT;
4327 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4328 goto out;
4329 r = 0;
4330 break;
4331 }
90de4a18
NA		 4332 case KVM_ENABLE_CAP: {
4333 struct kvm_enable_cap cap;
afbcf7ab 4334
90de4a18
NA		 4335 r = -EFAULT;
4336 if (copy_from_user(&cap, argp, sizeof(cap)))
4337 goto out;
4338 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4339 break;
4340 }
1fe779f8 4341 default:
ad6260da 4342 r = -ENOTTY;
1fe779f8
CO		 4343 }
4344out:
4345 return r;
4346}
4347
a16b043c 4348static void kvm_init_msr_list(void)
043405e1
CO		 4349{
4350 u32 dummy[2];
4351 unsigned i, j;
4352
62ef68bb 4353 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4354 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4355 continue;
93c4adc7
PB		 4356
4357 /*
4358 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4359 * to the guests in some cases.
93c4adc7
PB		 4360 */
4361 switch (msrs_to_save[i]) {
4362 case MSR_IA32_BNDCFGS:
4363 if (!kvm_x86_ops->mpx_supported())
4364 continue;
4365 break;
9dbe6cf9
PB		 4366 case MSR_TSC_AUX:
4367 if (!kvm_x86_ops->rdtscp_supported())
4368 continue;
4369 break;
93c4adc7
PB		 4370 default:
4371 break;
4372 }
4373
043405e1
CO		 4374 if (j < i)
4375 msrs_to_save[j] = msrs_to_save[i];
4376 j++;
4377 }
4378 num_msrs_to_save = j;
62ef68bb
PB		 4379
4380 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4381 switch (emulated_msrs[i]) {
6d396b55
PB		 4382 case MSR_IA32_SMBASE:
4383 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4384 continue;
4385 break;
62ef68bb
PB		 4386 default:
4387 break;
4388 }
4389
4390 if (j < i)
4391 emulated_msrs[j] = emulated_msrs[i];
4392 j++;
4393 }
4394 num_emulated_msrs = j;
043405e1
CO		 4395}
4396
bda9020e
MT		 4397static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4398 const void *v)
bbd9b64e 4399{
70252a10
AK		 4400 int handled = 0;
4401 int n;
4402
4403 do {
4404 n = min(len, 8);
bce87cce 4405 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4406 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4407 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4408 break;
4409 handled += n;
4410 addr += n;
4411 len -= n;
4412 v += n;
4413 } while (len);
bbd9b64e 4414
70252a10 4415 return handled;
bbd9b64e
CO		 4416}
4417
bda9020e 4418static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4419{
70252a10
AK		 4420 int handled = 0;
4421 int n;
4422
4423 do {
4424 n = min(len, 8);
bce87cce 4425 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4426 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4427 addr, n, v))
4428 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4429 break;
e39d200f 4430 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4431 handled += n;
4432 addr += n;
4433 len -= n;
4434 v += n;
4435 } while (len);
bbd9b64e 4436
70252a10 4437 return handled;
bbd9b64e
CO		 4438}
4439
2dafc6c2
GN		 4440static void kvm_set_segment(struct kvm_vcpu *vcpu,
4441 struct kvm_segment *var, int seg)
4442{
4443 kvm_x86_ops->set_segment(vcpu, var, seg);
4444}
4445
4446void kvm_get_segment(struct kvm_vcpu *vcpu,
4447 struct kvm_segment *var, int seg)
4448{
4449 kvm_x86_ops->get_segment(vcpu, var, seg);
4450}
4451
54987b7a
PB		 4452gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4453 struct x86_exception *exception)
02f59dc9
JR		 4454{
4455 gpa_t t_gpa;
02f59dc9
JR		 4456
4457 BUG_ON(!mmu_is_nested(vcpu));
4458
4459 /* NPT walks are always user-walks */
4460 access |= PFERR_USER_MASK;
54987b7a 4461 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4462
4463 return t_gpa;
4464}
4465
ab9ae313
AK		 4466gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4467 struct x86_exception *exception)
1871c602
GN		 4468{
4469 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4470 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4471}
4472
ab9ae313
AK		 4473 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4474 struct x86_exception *exception)
1871c602
GN		 4475{
4476 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4477 access |= PFERR_FETCH_MASK;
ab9ae313 4478 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4479}
4480
ab9ae313
AK		 4481gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4482 struct x86_exception *exception)
1871c602
GN		 4483{
4484 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4485 access |= PFERR_WRITE_MASK;
ab9ae313 4486 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4487}
4488
4489/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4490gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4491 struct x86_exception *exception)
1871c602 4492{
ab9ae313 4493 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4494}
4495
4496static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4497 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4498 struct x86_exception *exception)
bbd9b64e
CO		 4499{
4500 void *data = val;
10589a46 4501 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4502
4503 while (bytes) {
14dfe855 4504 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4505 exception);
bbd9b64e 4506 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4507 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4508 int ret;
4509
bcc55cba 4510 if (gpa == UNMAPPED_GVA)
ab9ae313 4511 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4512 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4513 offset, toread);
10589a46 4514 if (ret < 0) {
c3cd7ffa 4515 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4516 goto out;
4517 }
bbd9b64e 4518
77c2002e
IE		 4519 bytes -= toread;
4520 data += toread;
4521 addr += toread;
bbd9b64e 4522 }
10589a46 4523out:
10589a46 4524 return r;
bbd9b64e 4525}
77c2002e 4526
1871c602 4527/* used for instruction fetching */
0f65dd70
AK		 4528static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4529 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4530 struct x86_exception *exception)
1871c602 4531{
0f65dd70 4532 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4533 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4534 unsigned offset;
4535 int ret;
0f65dd70 4536
44583cba
PB		 4537 /* Inline kvm_read_guest_virt_helper for speed. */
4538 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4539 exception);
4540 if (unlikely(gpa == UNMAPPED_GVA))
4541 return X86EMUL_PROPAGATE_FAULT;
4542
4543 offset = addr & (PAGE_SIZE-1);
4544 if (WARN_ON(offset + bytes > PAGE_SIZE))
4545 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4546 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4547 offset, bytes);
44583cba
PB		 4548 if (unlikely(ret < 0))
4549 return X86EMUL_IO_NEEDED;
4550
4551 return X86EMUL_CONTINUE;
1871c602
GN		 4552}
4553
064aea77 4554int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4555 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4556 struct x86_exception *exception)
1871c602 4557{
0f65dd70 4558 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4559 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4560
1871c602 4561 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4562 exception);
1871c602 4563}
064aea77 4564EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4565
0f65dd70
AK		 4566static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4567 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4568 struct x86_exception *exception)
1871c602 4569{
0f65dd70 4570 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4571 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4572}
4573
7a036a6f
RK		 4574static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4575 unsigned long addr, void *val, unsigned int bytes)
4576{
4577 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4578 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4579
4580 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4581}
4582
6a4d7550 4583int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4584 gva_t addr, void *val,
2dafc6c2 4585 unsigned int bytes,
bcc55cba 4586 struct x86_exception *exception)
77c2002e 4587{
0f65dd70 4588 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4589 void *data = val;
4590 int r = X86EMUL_CONTINUE;
4591
4592 while (bytes) {
14dfe855
JR		 4593 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4594 PFERR_WRITE_MASK,
ab9ae313 4595 exception);
77c2002e
IE		 4596 unsigned offset = addr & (PAGE_SIZE-1);
4597 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4598 int ret;
4599
bcc55cba 4600 if (gpa == UNMAPPED_GVA)
ab9ae313 4601 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4602 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4603 if (ret < 0) {
c3cd7ffa 4604 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4605 goto out;
4606 }
4607
4608 bytes -= towrite;
4609 data += towrite;
4610 addr += towrite;
4611 }
4612out:
4613 return r;
4614}
6a4d7550 4615EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4616
0f89b207
TL		 4617static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4618 gpa_t gpa, bool write)
4619{
4620 /* For APIC access vmexit */
4621 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4622 return 1;
4623
4624 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4625 trace_vcpu_match_mmio(gva, gpa, write, true);
4626 return 1;
4627 }
4628
4629 return 0;
4630}
4631
af7cc7d1
XG		 4632static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4633 gpa_t *gpa, struct x86_exception *exception,
4634 bool write)
4635{
97d64b78
AK		 4636 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4637 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4638
be94f6b7
HH		 4639 /*
4640 * currently PKRU is only applied to ept enabled guest so
4641 * there is no pkey in EPT page table for L1 guest or EPT
4642 * shadow page table for L2 guest.
4643 */
97d64b78 4644 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4645 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4646 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4647 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4648 (gva & (PAGE_SIZE - 1));
4f022648 4649 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4650 return 1;
4651 }
4652
af7cc7d1
XG		 4653 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4654
4655 if (*gpa == UNMAPPED_GVA)
4656 return -1;
4657
0f89b207 4658 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4659}
4660
3200f405 4661int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4662 const void *val, int bytes)
bbd9b64e
CO		 4663{
4664 int ret;
4665
54bf36aa 4666 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4667 if (ret < 0)
bbd9b64e 4668 return 0;
0eb05bf2 4669 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4670 return 1;
4671}
4672
77d197b2
XG		 4673struct read_write_emulator_ops {
4674 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4675 int bytes);
4676 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4677 void *val, int bytes);
4678 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4679 int bytes, void *val);
4680 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4681 void *val, int bytes);
4682 bool write;
4683};
4684
4685static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4686{
4687 if (vcpu->mmio_read_completed) {
77d197b2 4688 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4689 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4690 vcpu->mmio_read_completed = 0;
4691 return 1;
4692 }
4693
4694 return 0;
4695}
4696
4697static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4698 void *val, int bytes)
4699{
54bf36aa 4700 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4701}
4702
4703static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4704 void *val, int bytes)
4705{
4706 return emulator_write_phys(vcpu, gpa, val, bytes);
4707}
4708
4709static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4710{
e39d200f 4711 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4712 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4713}
4714
4715static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4716 void *val, int bytes)
4717{
e39d200f 4718 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4719 return X86EMUL_IO_NEEDED;
4720}
4721
4722static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4723 void *val, int bytes)
4724{
f78146b0
AK		 4725 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4726
87da7e66 4727 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4728 return X86EMUL_CONTINUE;
4729}
4730
0fbe9b0b 4731static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4732 .read_write_prepare = read_prepare,
4733 .read_write_emulate = read_emulate,
4734 .read_write_mmio = vcpu_mmio_read,
4735 .read_write_exit_mmio = read_exit_mmio,
4736};
4737
0fbe9b0b 4738static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4739 .read_write_emulate = write_emulate,
4740 .read_write_mmio = write_mmio,
4741 .read_write_exit_mmio = write_exit_mmio,
4742 .write = true,
4743};
4744
22388a3c
XG		 4745static int emulator_read_write_onepage(unsigned long addr, void *val,
4746 unsigned int bytes,
4747 struct x86_exception *exception,
4748 struct kvm_vcpu *vcpu,
0fbe9b0b 4749 const struct read_write_emulator_ops *ops)
bbd9b64e 4750{
af7cc7d1
XG		 4751 gpa_t gpa;
4752 int handled, ret;
22388a3c 4753 bool write = ops->write;
f78146b0 4754 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4755 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4756
4757 /*
4758 * If the exit was due to a NPF we may already have a GPA.
4759 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4760 * Note, this cannot be used on string operations since string
4761 * operation using rep will only have the initial GPA from the NPF
4762 * occurred.
4763 */
4764 if (vcpu->arch.gpa_available &&
4765 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4766 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4767 gpa = vcpu->arch.gpa_val;
4768 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4769 } else {
4770 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4771 if (ret < 0)
4772 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4773 }
10589a46 4774
618232e2 4775 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4776 return X86EMUL_CONTINUE;
4777
bbd9b64e
CO		 4778 /*
4779 * Is this MMIO handled locally?
4780 */
22388a3c 4781 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4782 if (handled == bytes)
bbd9b64e 4783 return X86EMUL_CONTINUE;
bbd9b64e 4784
70252a10
AK		 4785 gpa += handled;
4786 bytes -= handled;
4787 val += handled;
4788
87da7e66
XG		 4789 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4790 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4791 frag->gpa = gpa;
4792 frag->data = val;
4793 frag->len = bytes;
f78146b0 4794 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4795}
4796
52eb5a6d
XL		 4797static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4798 unsigned long addr,
22388a3c
XG		 4799 void *val, unsigned int bytes,
4800 struct x86_exception *exception,
0fbe9b0b 4801 const struct read_write_emulator_ops *ops)
bbd9b64e 4802{
0f65dd70 4803 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4804 gpa_t gpa;
4805 int rc;
4806
4807 if (ops->read_write_prepare &&
4808 ops->read_write_prepare(vcpu, val, bytes))
4809 return X86EMUL_CONTINUE;
4810
4811 vcpu->mmio_nr_fragments = 0;
0f65dd70 4812
bbd9b64e
CO		 4813 /* Crossing a page boundary? */
4814 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4815 int now;
bbd9b64e
CO		 4816
4817 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4818 rc = emulator_read_write_onepage(addr, val, now, exception,
4819 vcpu, ops);
4820
bbd9b64e
CO		 4821 if (rc != X86EMUL_CONTINUE)
4822 return rc;
4823 addr += now;
bac15531
NA		 4824 if (ctxt->mode != X86EMUL_MODE_PROT64)
4825 addr = (u32)addr;
bbd9b64e
CO		 4826 val += now;
4827 bytes -= now;
4828 }
22388a3c 4829
f78146b0
AK		 4830 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4831 vcpu, ops);
4832 if (rc != X86EMUL_CONTINUE)
4833 return rc;
4834
4835 if (!vcpu->mmio_nr_fragments)
4836 return rc;
4837
4838 gpa = vcpu->mmio_fragments[0].gpa;
4839
4840 vcpu->mmio_needed = 1;
4841 vcpu->mmio_cur_fragment = 0;
4842
87da7e66 4843 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4844 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4845 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4846 vcpu->run->mmio.phys_addr = gpa;
4847
4848 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4849}
4850
4851static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4852 unsigned long addr,
4853 void *val,
4854 unsigned int bytes,
4855 struct x86_exception *exception)
4856{
4857 return emulator_read_write(ctxt, addr, val, bytes,
4858 exception, &read_emultor);
4859}
4860
52eb5a6d 4861static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4862 unsigned long addr,
4863 const void *val,
4864 unsigned int bytes,
4865 struct x86_exception *exception)
4866{
4867 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4868 exception, &write_emultor);
bbd9b64e 4869}
bbd9b64e 4870
daea3e73
AK		 4871#define CMPXCHG_TYPE(t, ptr, old, new) \
4872 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4873
4874#ifdef CONFIG_X86_64
4875# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4876#else
4877# define CMPXCHG64(ptr, old, new) \
9749a6c0 4878 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4879#endif
4880
0f65dd70
AK		 4881static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4882 unsigned long addr,
bbd9b64e
CO		 4883 const void *old,
4884 const void *new,
4885 unsigned int bytes,
0f65dd70 4886 struct x86_exception *exception)
bbd9b64e 4887{
0f65dd70 4888 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4889 gpa_t gpa;
4890 struct page *page;
4891 char *kaddr;
4892 bool exchanged;
2bacc55c 4893
daea3e73
AK		 4894 /* guests cmpxchg8b have to be emulated atomically */
4895 if (bytes > 8 || (bytes & (bytes - 1)))
4896 goto emul_write;
10589a46 4897
daea3e73 4898 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4899
daea3e73
AK		 4900 if (gpa == UNMAPPED_GVA ||
4901 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4902 goto emul_write;
2bacc55c 4903
daea3e73
AK		 4904 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4905 goto emul_write;
72dc67a6 4906
54bf36aa 4907 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4908 if (is_error_page(page))
c19b8bd6 4909 goto emul_write;
72dc67a6 4910
8fd75e12 4911 kaddr = kmap_atomic(page);
daea3e73
AK		 4912 kaddr += offset_in_page(gpa);
4913 switch (bytes) {
4914 case 1:
4915 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4916 break;
4917 case 2:
4918 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4919 break;
4920 case 4:
4921 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4922 break;
4923 case 8:
4924 exchanged = CMPXCHG64(kaddr, old, new);
4925 break;
4926 default:
4927 BUG();
2bacc55c 4928 }
8fd75e12 4929 kunmap_atomic(kaddr);
daea3e73
AK		 4930 kvm_release_page_dirty(page);
4931
4932 if (!exchanged)
4933 return X86EMUL_CMPXCHG_FAILED;
4934
54bf36aa 4935 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4936 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4937
4938 return X86EMUL_CONTINUE;
4a5f48f6 4939
3200f405 4940emul_write:
daea3e73 4941 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4942
0f65dd70 4943 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4944}
4945
cf8f70bf
GN		 4946static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4947{
cbfc6c91 4948 int r = 0, i;
cf8f70bf 4949
cbfc6c91
WL		 4950 for (i = 0; i < vcpu->arch.pio.count; i++) {
4951 if (vcpu->arch.pio.in)
4952 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
4953 vcpu->arch.pio.size, pd);
4954 else
4955 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
4956 vcpu->arch.pio.port, vcpu->arch.pio.size,
4957 pd);
4958 if (r)
4959 break;
4960 pd += vcpu->arch.pio.size;
4961 }
cf8f70bf
GN		 4962 return r;
4963}
4964
6f6fbe98
XG		 4965static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4966 unsigned short port, void *val,
4967 unsigned int count, bool in)
cf8f70bf 4968{
cf8f70bf 4969 vcpu->arch.pio.port = port;
6f6fbe98 4970 vcpu->arch.pio.in = in;
7972995b 4971 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4972 vcpu->arch.pio.size = size;
4973
4974 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4975 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4976 return 1;
4977 }
4978
4979 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4980 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4981 vcpu->run->io.size = size;
4982 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4983 vcpu->run->io.count = count;
4984 vcpu->run->io.port = port;
4985
4986 return 0;
4987}
4988
6f6fbe98
XG		 4989static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4990 int size, unsigned short port, void *val,
4991 unsigned int count)
cf8f70bf 4992{
ca1d4a9e 4993 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4994 int ret;
ca1d4a9e 4995
6f6fbe98
XG		 4996 if (vcpu->arch.pio.count)
4997 goto data_avail;
cf8f70bf 4998
cbfc6c91
WL		 4999 memset(vcpu->arch.pio_data, 0, size * count);
5000
6f6fbe98
XG		 5001 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5002 if (ret) {
5003data_avail:
5004 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5005 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5006 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5007 return 1;
5008 }
5009
cf8f70bf
GN		 5010 return 0;
5011}
5012
6f6fbe98
XG		 5013static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5014 int size, unsigned short port,
5015 const void *val, unsigned int count)
5016{
5017 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5018
5019 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5020 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5021 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5022}
5023
bbd9b64e
CO		 5024static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5025{
5026 return kvm_x86_ops->get_segment_base(vcpu, seg);
5027}
5028
3cb16fe7 5029static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5030{
3cb16fe7 5031 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5032}
5033
ae6a2375 5034static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5035{
5036 if (!need_emulate_wbinvd(vcpu))
5037 return X86EMUL_CONTINUE;
5038
5039 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5040 int cpu = get_cpu();
5041
5042 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5043 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5044 wbinvd_ipi, NULL, 1);
2eec7343 5045 put_cpu();
f5f48ee1 5046 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5047 } else
5048 wbinvd();
f5f48ee1
SY		 5049 return X86EMUL_CONTINUE;
5050}
5cb56059
JS		 5051
5052int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5053{
6affcbed
KH		 5054 kvm_emulate_wbinvd_noskip(vcpu);
5055 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5056}
f5f48ee1
SY		 5057EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5058
5cb56059
JS		 5059
5060
bcaf5cc5
AK		 5061static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5062{
5cb56059 5063 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5064}
5065
52eb5a6d
XL		 5066static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5067 unsigned long *dest)
bbd9b64e 5068{
16f8a6f9 5069 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5070}
5071
52eb5a6d
XL		 5072static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5073 unsigned long value)
bbd9b64e 5074{
338dbc97 5075
717746e3 5076 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5077}
5078
52a46617 5079static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5080{
52a46617 5081 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5082}
5083
717746e3 5084static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5085{
717746e3 5086 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5087 unsigned long value;
5088
5089 switch (cr) {
5090 case 0:
5091 value = kvm_read_cr0(vcpu);
5092 break;
5093 case 2:
5094 value = vcpu->arch.cr2;
5095 break;
5096 case 3:
9f8fe504 5097 value = kvm_read_cr3(vcpu);
52a46617
GN		 5098 break;
5099 case 4:
5100 value = kvm_read_cr4(vcpu);
5101 break;
5102 case 8:
5103 value = kvm_get_cr8(vcpu);
5104 break;
5105 default:
a737f256 5106 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5107 return 0;
5108 }
5109
5110 return value;
5111}
5112
717746e3 5113static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5114{
717746e3 5115 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5116 int res = 0;
5117
52a46617
GN		 5118 switch (cr) {
5119 case 0:
49a9b07e 5120 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5121 break;
5122 case 2:
5123 vcpu->arch.cr2 = val;
5124 break;
5125 case 3:
2390218b 5126 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5127 break;
5128 case 4:
a83b29c6 5129 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5130 break;
5131 case 8:
eea1cff9 5132 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5133 break;
5134 default:
a737f256 5135 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5136 res = -1;
52a46617 5137 }
0f12244f
GN		 5138
5139 return res;
52a46617
GN		 5140}
5141
717746e3 5142static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5143{
717746e3 5144 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5145}
5146
4bff1e86 5147static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5148{
4bff1e86 5149 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5150}
5151
4bff1e86 5152static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5153{
4bff1e86 5154 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5155}
5156
1ac9d0cf
AK		 5157static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5158{
5159 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5160}
5161
5162static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5163{
5164 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5165}
5166
4bff1e86
AK		 5167static unsigned long emulator_get_cached_segment_base(
5168 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5169{
4bff1e86 5170 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5171}
5172
1aa36616
AK		 5173static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5174 struct desc_struct *desc, u32 *base3,
5175 int seg)
2dafc6c2
GN		 5176{
5177 struct kvm_segment var;
5178
4bff1e86 5179 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5180 *selector = var.selector;
2dafc6c2 5181
378a8b09
GN		 5182 if (var.unusable) {
5183 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5184 if (base3)
5185 *base3 = 0;
2dafc6c2 5186 return false;
378a8b09 5187 }
2dafc6c2
GN		 5188
5189 if (var.g)
5190 var.limit >>= 12;
5191 set_desc_limit(desc, var.limit);
5192 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5193#ifdef CONFIG_X86_64
5194 if (base3)
5195 *base3 = var.base >> 32;
5196#endif
2dafc6c2
GN		 5197 desc->type = var.type;
5198 desc->s = var.s;
5199 desc->dpl = var.dpl;
5200 desc->p = var.present;
5201 desc->avl = var.avl;
5202 desc->l = var.l;
5203 desc->d = var.db;
5204 desc->g = var.g;
5205
5206 return true;
5207}
5208
1aa36616
AK		 5209static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5210 struct desc_struct *desc, u32 base3,
5211 int seg)
2dafc6c2 5212{
4bff1e86 5213 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5214 struct kvm_segment var;
5215
1aa36616 5216 var.selector = selector;
2dafc6c2 5217 var.base = get_desc_base(desc);
5601d05b
GN		 5218#ifdef CONFIG_X86_64
5219 var.base |= ((u64)base3) << 32;
5220#endif
2dafc6c2
GN		 5221 var.limit = get_desc_limit(desc);
5222 if (desc->g)
5223 var.limit = (var.limit << 12) | 0xfff;
5224 var.type = desc->type;
2dafc6c2
GN		 5225 var.dpl = desc->dpl;
5226 var.db = desc->d;
5227 var.s = desc->s;
5228 var.l = desc->l;
5229 var.g = desc->g;
5230 var.avl = desc->avl;
5231 var.present = desc->p;
5232 var.unusable = !var.present;
5233 var.padding = 0;
5234
5235 kvm_set_segment(vcpu, &var, seg);
5236 return;
5237}
5238
717746e3
AK		 5239static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5240 u32 msr_index, u64 *pdata)
5241{
609e36d3
PB		 5242 struct msr_data msr;
5243 int r;
5244
5245 msr.index = msr_index;
5246 msr.host_initiated = false;
5247 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5248 if (r)
5249 return r;
5250
5251 *pdata = msr.data;
5252 return 0;
717746e3
AK		 5253}
5254
5255static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5256 u32 msr_index, u64 data)
5257{
8fe8ab46
WA		 5258 struct msr_data msr;
5259
5260 msr.data = data;
5261 msr.index = msr_index;
5262 msr.host_initiated = false;
5263 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5264}
5265
64d60670
PB		 5266static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5267{
5268 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5269
5270 return vcpu->arch.smbase;
5271}
5272
5273static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5274{
5275 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5276
5277 vcpu->arch.smbase = smbase;
5278}
5279
67f4d428
NA		 5280static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5281 u32 pmc)
5282{
c6702c9d 5283 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5284}
5285
222d21aa
AK		 5286static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5287 u32 pmc, u64 *pdata)
5288{
c6702c9d 5289 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5290}
5291
6c3287f7
AK		 5292static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5293{
5294 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5295}
5296
2953538e 5297static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5298 struct x86_instruction_info *info,
c4f035c6
AK		 5299 enum x86_intercept_stage stage)
5300{
2953538e 5301 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5302}
5303
e911eb3b
YZ		 5304static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5305 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5306{
e911eb3b 5307 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5308}
5309
dd856efa
AK		 5310static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5311{
5312 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5313}
5314
5315static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5316{
5317 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5318}
5319
801806d9
NA		 5320static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5321{
5322 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5323}
5324
6ed071f0
LP		 5325static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5326{
5327 return emul_to_vcpu(ctxt)->arch.hflags;
5328}
5329
5330static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5331{
5332 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5333}
5334
0234bf88
LP		 5335static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5336{
5337 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5338}
5339
0225fb50 5340static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5341 .read_gpr = emulator_read_gpr,
5342 .write_gpr = emulator_write_gpr,
1871c602 5343 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5344 .write_std = kvm_write_guest_virt_system,
7a036a6f 5345 .read_phys = kvm_read_guest_phys_system,
1871c602 5346 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5347 .read_emulated = emulator_read_emulated,
5348 .write_emulated = emulator_write_emulated,
5349 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5350 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5351 .pio_in_emulated = emulator_pio_in_emulated,
5352 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5353 .get_segment = emulator_get_segment,
5354 .set_segment = emulator_set_segment,
5951c442 5355 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5356 .get_gdt = emulator_get_gdt,
160ce1f1 5357 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5358 .set_gdt = emulator_set_gdt,
5359 .set_idt = emulator_set_idt,
52a46617
GN		 5360 .get_cr = emulator_get_cr,
5361 .set_cr = emulator_set_cr,
9c537244 5362 .cpl = emulator_get_cpl,
35aa5375
GN		 5363 .get_dr = emulator_get_dr,
5364 .set_dr = emulator_set_dr,
64d60670
PB		 5365 .get_smbase = emulator_get_smbase,
5366 .set_smbase = emulator_set_smbase,
717746e3
AK		 5367 .set_msr = emulator_set_msr,
5368 .get_msr = emulator_get_msr,
67f4d428 5369 .check_pmc = emulator_check_pmc,
222d21aa 5370 .read_pmc = emulator_read_pmc,
6c3287f7 5371 .halt = emulator_halt,
bcaf5cc5 5372 .wbinvd = emulator_wbinvd,
d6aa1000 5373 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5374 .intercept = emulator_intercept,
bdb42f5a 5375 .get_cpuid = emulator_get_cpuid,
801806d9 5376 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5377 .get_hflags = emulator_get_hflags,
5378 .set_hflags = emulator_set_hflags,
0234bf88 5379 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5380};
5381
95cb2295
GN		 5382static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5383{
37ccdcbe 5384 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5385 /*
5386 * an sti; sti; sequence only disable interrupts for the first
5387 * instruction. So, if the last instruction, be it emulated or
5388 * not, left the system with the INT_STI flag enabled, it
5389 * means that the last instruction is an sti. We should not
5390 * leave the flag on in this case. The same goes for mov ss
5391 */
37ccdcbe
PB		 5392 if (int_shadow & mask)
5393 mask = 0;
6addfc42 5394 if (unlikely(int_shadow || mask)) {
95cb2295 5395 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5396 if (!mask)
5397 kvm_make_request(KVM_REQ_EVENT, vcpu);
5398 }
95cb2295
GN		 5399}
5400
ef54bcfe 5401static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5402{
5403 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5404 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5405 return kvm_propagate_fault(vcpu, &ctxt->exception);
5406
5407 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5408 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5409 ctxt->exception.error_code);
54b8486f 5410 else
da9cb575 5411 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5412 return false;
54b8486f
GN		 5413}
5414
8ec4722d
MG		 5415static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5416{
adf52235 5417 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5418 int cs_db, cs_l;
5419
8ec4722d
MG		 5420 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5421
adf52235 5422 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5423 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5424
adf52235
TY		 5425 ctxt->eip = kvm_rip_read(vcpu);
5426 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5427 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5428 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5429 cs_db ? X86EMUL_MODE_PROT32 :
5430 X86EMUL_MODE_PROT16;
a584539b 5431 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5432 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5433 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5434
dd856efa 5435 init_decode_cache(ctxt);
7ae441ea 5436 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5437}
5438
71f9833b 5439int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5440{
9d74191a 5441 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5442 int ret;
5443
5444 init_emulate_ctxt(vcpu);
5445
9dac77fa
AK		 5446 ctxt->op_bytes = 2;
5447 ctxt->ad_bytes = 2;
5448 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5449 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5450
5451 if (ret != X86EMUL_CONTINUE)
5452 return EMULATE_FAIL;
5453
9dac77fa 5454 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5455 kvm_rip_write(vcpu, ctxt->eip);
5456 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5457
5458 if (irq == NMI_VECTOR)
7460fb4a 5459 vcpu->arch.nmi_pending = 0;
63995653
MG		 5460 else
5461 vcpu->arch.interrupt.pending = false;
5462
5463 return EMULATE_DONE;
5464}
5465EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5466
6d77dbfc
GN		 5467static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5468{
fc3a9157
JR		 5469 int r = EMULATE_DONE;
5470
6d77dbfc
GN		 5471 ++vcpu->stat.insn_emulation_fail;
5472 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5473 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5474 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5475 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5476 vcpu->run->internal.ndata = 0;
1f4dcb3b 5477 r = EMULATE_USER_EXIT;
fc3a9157 5478 }
6d77dbfc 5479 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5480
5481 return r;
6d77dbfc
GN		 5482}
5483
93c05d3e 5484static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5485 bool write_fault_to_shadow_pgtable,
5486 int emulation_type)
a6f177ef 5487{
95b3cf69 5488 gpa_t gpa = cr2;
ba049e93 5489 kvm_pfn_t pfn;
a6f177ef 5490
991eebf9
GN		 5491 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5492 return false;
5493
95b3cf69
XG		 5494 if (!vcpu->arch.mmu.direct_map) {
5495 /*
5496 * Write permission should be allowed since only
5497 * write access need to be emulated.
5498 */
5499 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5500
95b3cf69
XG		 5501 /*
5502 * If the mapping is invalid in guest, let cpu retry
5503 * it to generate fault.
5504 */
5505 if (gpa == UNMAPPED_GVA)
5506 return true;
5507 }
a6f177ef 5508
8e3d9d06
XG		 5509 /*
5510 * Do not retry the unhandleable instruction if it faults on the
5511 * readonly host memory, otherwise it will goto a infinite loop:
5512 * retry instruction -> write #PF -> emulation fail -> retry
5513 * instruction -> ...
5514 */
5515 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5516
5517 /*
5518 * If the instruction failed on the error pfn, it can not be fixed,
5519 * report the error to userspace.
5520 */
5521 if (is_error_noslot_pfn(pfn))
5522 return false;
5523
5524 kvm_release_pfn_clean(pfn);
5525
5526 /* The instructions are well-emulated on direct mmu. */
5527 if (vcpu->arch.mmu.direct_map) {
5528 unsigned int indirect_shadow_pages;
5529
5530 spin_lock(&vcpu->kvm->mmu_lock);
5531 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5532 spin_unlock(&vcpu->kvm->mmu_lock);
5533
5534 if (indirect_shadow_pages)
5535 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5536
a6f177ef 5537 return true;
8e3d9d06 5538 }
a6f177ef 5539
95b3cf69
XG		 5540 /*
5541 * if emulation was due to access to shadowed page table
5542 * and it failed try to unshadow page and re-enter the
5543 * guest to let CPU execute the instruction.
5544 */
5545 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5546
5547 /*
5548 * If the access faults on its page table, it can not
5549 * be fixed by unprotecting shadow page and it should
5550 * be reported to userspace.
5551 */
5552 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5553}
5554
1cb3f3ae
XG		 5555static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5556 unsigned long cr2, int emulation_type)
5557{
5558 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5559 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5560
5561 last_retry_eip = vcpu->arch.last_retry_eip;
5562 last_retry_addr = vcpu->arch.last_retry_addr;
5563
5564 /*
5565 * If the emulation is caused by #PF and it is non-page_table
5566 * writing instruction, it means the VM-EXIT is caused by shadow
5567 * page protected, we can zap the shadow page and retry this
5568 * instruction directly.
5569 *
5570 * Note: if the guest uses a non-page-table modifying instruction
5571 * on the PDE that points to the instruction, then we will unmap
5572 * the instruction and go to an infinite loop. So, we cache the
5573 * last retried eip and the last fault address, if we meet the eip
5574 * and the address again, we can break out of the potential infinite
5575 * loop.
5576 */
5577 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5578
5579 if (!(emulation_type & EMULTYPE_RETRY))
5580 return false;
5581
5582 if (x86_page_table_writing_insn(ctxt))
5583 return false;
5584
5585 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5586 return false;
5587
5588 vcpu->arch.last_retry_eip = ctxt->eip;
5589 vcpu->arch.last_retry_addr = cr2;
5590
5591 if (!vcpu->arch.mmu.direct_map)
5592 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5593
22368028 5594 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5595
5596 return true;
5597}
5598
716d51ab
GN		 5599static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5600static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5601
64d60670 5602static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5603{
64d60670 5604 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5605 /* This is a good place to trace that we are exiting SMM. */
5606 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5607
c43203ca
PB		 5608 /* Process a latched INIT or SMI, if any. */
5609 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5610 }
699023e2
PB		 5611
5612 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5613}
5614
5615static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5616{
5617 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5618
a584539b 5619 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5620
5621 if (changed & HF_SMM_MASK)
5622 kvm_smm_changed(vcpu);
a584539b
PB		 5623}
5624
4a1e10d5
PB		 5625static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5626 unsigned long *db)
5627{
5628 u32 dr6 = 0;
5629 int i;
5630 u32 enable, rwlen;
5631
5632 enable = dr7;
5633 rwlen = dr7 >> 16;
5634 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5635 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5636 dr6 |= (1 << i);
5637 return dr6;
5638}
5639
c8401dda 5640static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5641{
5642 struct kvm_run *kvm_run = vcpu->run;
5643
c8401dda
PB		 5644 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5645 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5646 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5647 kvm_run->debug.arch.exception = DB_VECTOR;
5648 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5649 *r = EMULATE_USER_EXIT;
5650 } else {
5651 /*
5652 * "Certain debug exceptions may clear bit 0-3. The
5653 * remaining contents of the DR6 register are never
5654 * cleared by the processor".
5655 */
5656 vcpu->arch.dr6 &= ~15;
5657 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5658 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5659 }
5660}
5661
6affcbed
KH		 5662int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5663{
5664 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5665 int r = EMULATE_DONE;
5666
5667 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5668
5669 /*
5670 * rflags is the old, "raw" value of the flags. The new value has
5671 * not been saved yet.
5672 *
5673 * This is correct even for TF set by the guest, because "the
5674 * processor will not generate this exception after the instruction
5675 * that sets the TF flag".
5676 */
5677 if (unlikely(rflags & X86_EFLAGS_TF))
5678 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5679 return r == EMULATE_DONE;
5680}
5681EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5682
4a1e10d5
PB		 5683static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5684{
4a1e10d5
PB		 5685 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5686 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5687 struct kvm_run *kvm_run = vcpu->run;
5688 unsigned long eip = kvm_get_linear_rip(vcpu);
5689 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5690 vcpu->arch.guest_debug_dr7,
5691 vcpu->arch.eff_db);
5692
5693 if (dr6 != 0) {
6f43ed01 5694 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5695 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5696 kvm_run->debug.arch.exception = DB_VECTOR;
5697 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5698 *r = EMULATE_USER_EXIT;
5699 return true;
5700 }
5701 }
5702
4161a569
NA		 5703 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5704 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5705 unsigned long eip = kvm_get_linear_rip(vcpu);
5706 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5707 vcpu->arch.dr7,
5708 vcpu->arch.db);
5709
5710 if (dr6 != 0) {
5711 vcpu->arch.dr6 &= ~15;
6f43ed01 5712 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5713 kvm_queue_exception(vcpu, DB_VECTOR);
5714 *r = EMULATE_DONE;
5715 return true;
5716 }
5717 }
5718
5719 return false;
5720}
5721
51d8b661
AP		 5722int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5723 unsigned long cr2,
dc25e89e
AP		 5724 int emulation_type,
5725 void *insn,
5726 int insn_len)
bbd9b64e 5727{
95cb2295 5728 int r;
9d74191a 5729 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5730 bool writeback = true;
93c05d3e 5731 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5732
93c05d3e
XG		 5733 /*
5734 * Clear write_fault_to_shadow_pgtable here to ensure it is
5735 * never reused.
5736 */
5737 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5738 kvm_clear_exception_queue(vcpu);
8d7d8102 5739
571008da 5740 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5741 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5742
5743 /*
5744 * We will reenter on the same instruction since
5745 * we do not set complete_userspace_io. This does not
5746 * handle watchpoints yet, those would be handled in
5747 * the emulate_ops.
5748 */
5749 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5750 return r;
5751
9d74191a
TY		 5752 ctxt->interruptibility = 0;
5753 ctxt->have_exception = false;
e0ad0b47 5754 ctxt->exception.vector = -1;
9d74191a 5755 ctxt->perm_ok = false;
bbd9b64e 5756
b51e974f 5757 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5758
9d74191a 5759 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5760
e46479f8 5761 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5762 ++vcpu->stat.insn_emulation;
1d2887e2 5763 if (r != EMULATION_OK) {
4005996e
AK		 5764 if (emulation_type & EMULTYPE_TRAP_UD)
5765 return EMULATE_FAIL;
991eebf9
GN		 5766 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5767 emulation_type))
bbd9b64e 5768 return EMULATE_DONE;
6ea6e843
PB		 5769 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5770 return EMULATE_DONE;
6d77dbfc
GN		 5771 if (emulation_type & EMULTYPE_SKIP)
5772 return EMULATE_FAIL;
5773 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5774 }
5775 }
5776
ba8afb6b 5777 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5778 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5779 if (ctxt->eflags & X86_EFLAGS_RF)
5780 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5781 return EMULATE_DONE;
5782 }
5783
1cb3f3ae
XG		 5784 if (retry_instruction(ctxt, cr2, emulation_type))
5785 return EMULATE_DONE;
5786
7ae441ea 5787 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5788 changes registers values during IO operation */
7ae441ea
GN		 5789 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5790 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5791 emulator_invalidate_register_cache(ctxt);
7ae441ea 5792 }
4d2179e1 5793
5cd21917 5794restart:
0f89b207
TL		 5795 /* Save the faulting GPA (cr2) in the address field */
5796 ctxt->exception.address = cr2;
5797
9d74191a 5798 r = x86_emulate_insn(ctxt);
bbd9b64e 5799
775fde86
JR		 5800 if (r == EMULATION_INTERCEPTED)
5801 return EMULATE_DONE;
5802
d2ddd1c4 5803 if (r == EMULATION_FAILED) {
991eebf9
GN		 5804 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5805 emulation_type))
c3cd7ffa
GN		 5806 return EMULATE_DONE;
5807
6d77dbfc 5808 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5809 }
5810
9d74191a 5811 if (ctxt->have_exception) {
d2ddd1c4 5812 r = EMULATE_DONE;
ef54bcfe
PB		 5813 if (inject_emulated_exception(vcpu))
5814 return r;
d2ddd1c4 5815 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5816 if (!vcpu->arch.pio.in) {
5817 /* FIXME: return into emulator if single-stepping. */
3457e419 5818 vcpu->arch.pio.count = 0;
0912c977 5819 } else {
7ae441ea 5820 writeback = false;
716d51ab
GN		 5821 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5822 }
ac0a48c3 5823 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5824 } else if (vcpu->mmio_needed) {
5825 if (!vcpu->mmio_is_write)
5826 writeback = false;
ac0a48c3 5827 r = EMULATE_USER_EXIT;
716d51ab 5828 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5829 } else if (r == EMULATION_RESTART)
5cd21917 5830 goto restart;
d2ddd1c4
GN		 5831 else
5832 r = EMULATE_DONE;
f850e2e6 5833
7ae441ea 5834 if (writeback) {
6addfc42 5835 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5836 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5837 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5838 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 5839 if (r == EMULATE_DONE &&
5840 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5841 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 5842 if (!ctxt->have_exception ||
5843 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5844 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5845
5846 /*
5847 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5848 * do nothing, and it will be requested again as soon as
5849 * the shadow expires. But we still need to check here,
5850 * because POPF has no interrupt shadow.
5851 */
5852 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5853 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5854 } else
5855 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5856
5857 return r;
de7d789a 5858}
51d8b661 5859EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5860
cf8f70bf 5861int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5862{
cf8f70bf 5863 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5864 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5865 size, port, &val, 1);
cf8f70bf 5866 /* do not return to emulator after return from userspace */
7972995b 5867 vcpu->arch.pio.count = 0;
de7d789a
CO		 5868 return ret;
5869}
cf8f70bf 5870EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5871
8370c3d0
TL		 5872static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5873{
5874 unsigned long val;
5875
5876 /* We should only ever be called with arch.pio.count equal to 1 */
5877 BUG_ON(vcpu->arch.pio.count != 1);
5878
5879 /* For size less than 4 we merge, else we zero extend */
5880 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5881 : 0;
5882
5883 /*
5884 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5885 * the copy and tracing
5886 */
5887 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5888 vcpu->arch.pio.port, &val, 1);
5889 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5890
5891 return 1;
5892}
5893
5894int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5895{
5896 unsigned long val;
5897 int ret;
5898
5899 /* For size less than 4 we merge, else we zero extend */
5900 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5901
5902 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5903 &val, 1);
5904 if (ret) {
5905 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5906 return ret;
5907 }
5908
5909 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5910
5911 return 0;
5912}
5913EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5914
251a5fd6 5915static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5916{
0a3aee0d 5917 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5918 return 0;
8cfdc000
ZA		 5919}
5920
5921static void tsc_khz_changed(void *data)
c8076604 5922{
8cfdc000
ZA		 5923 struct cpufreq_freqs *freq = data;
5924 unsigned long khz = 0;
5925
5926 if (data)
5927 khz = freq->new;
5928 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5929 khz = cpufreq_quick_get(raw_smp_processor_id());
5930 if (!khz)
5931 khz = tsc_khz;
0a3aee0d 5932 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5933}
5934
c8076604
GH		 5935static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5936 void *data)
5937{
5938 struct cpufreq_freqs *freq = data;
5939 struct kvm *kvm;
5940 struct kvm_vcpu *vcpu;
5941 int i, send_ipi = 0;
5942
8cfdc000
ZA		 5943 /*
5944 * We allow guests to temporarily run on slowing clocks,
5945 * provided we notify them after, or to run on accelerating
5946 * clocks, provided we notify them before. Thus time never
5947 * goes backwards.
5948 *
5949 * However, we have a problem. We can't atomically update
5950 * the frequency of a given CPU from this function; it is
5951 * merely a notifier, which can be called from any CPU.
5952 * Changing the TSC frequency at arbitrary points in time
5953 * requires a recomputation of local variables related to
5954 * the TSC for each VCPU. We must flag these local variables
5955 * to be updated and be sure the update takes place with the
5956 * new frequency before any guests proceed.
5957 *
5958 * Unfortunately, the combination of hotplug CPU and frequency
5959 * change creates an intractable locking scenario; the order
5960 * of when these callouts happen is undefined with respect to
5961 * CPU hotplug, and they can race with each other. As such,
5962 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5963 * undefined; you can actually have a CPU frequency change take
5964 * place in between the computation of X and the setting of the
5965 * variable. To protect against this problem, all updates of
5966 * the per_cpu tsc_khz variable are done in an interrupt
5967 * protected IPI, and all callers wishing to update the value
5968 * must wait for a synchronous IPI to complete (which is trivial
5969 * if the caller is on the CPU already). This establishes the
5970 * necessary total order on variable updates.
5971 *
5972 * Note that because a guest time update may take place
5973 * anytime after the setting of the VCPU's request bit, the
5974 * correct TSC value must be set before the request. However,
5975 * to ensure the update actually makes it to any guest which
5976 * starts running in hardware virtualization between the set
5977 * and the acquisition of the spinlock, we must also ping the
5978 * CPU after setting the request bit.
5979 *
5980 */
5981
c8076604
GH		 5982 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5983 return 0;
5984 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5985 return 0;
8cfdc000
ZA		 5986
5987 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5988
2f303b74 5989 spin_lock(&kvm_lock);
c8076604 5990 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5991 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5992 if (vcpu->cpu != freq->cpu)
5993 continue;
c285545f 5994 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5995 if (vcpu->cpu != smp_processor_id())
8cfdc000 5996 send_ipi = 1;
c8076604
GH		 5997 }
5998 }
2f303b74 5999 spin_unlock(&kvm_lock);
c8076604
GH		 6000
6001 if (freq->old < freq->new && send_ipi) {
6002 /*
6003 * We upscale the frequency. Must make the guest
6004 * doesn't see old kvmclock values while running with
6005 * the new frequency, otherwise we risk the guest sees
6006 * time go backwards.
6007 *
6008 * In case we update the frequency for another cpu
6009 * (which might be in guest context) send an interrupt
6010 * to kick the cpu out of guest context. Next time
6011 * guest context is entered kvmclock will be updated,
6012 * so the guest will not see stale values.
6013 */
8cfdc000 6014 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6015 }
6016 return 0;
6017}
6018
6019static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6020 .notifier_call = kvmclock_cpufreq_notifier
6021};
6022
251a5fd6 6023static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6024{
251a5fd6
SAS		 6025 tsc_khz_changed(NULL);
6026 return 0;
8cfdc000
ZA		 6027}
6028
b820cc0c
ZA		 6029static void kvm_timer_init(void)
6030{
c285545f 6031 max_tsc_khz = tsc_khz;
460dd42e 6032
b820cc0c 6033 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6034#ifdef CONFIG_CPU_FREQ
6035 struct cpufreq_policy policy;
758f588d
BP		 6036 int cpu;
6037
c285545f 6038 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6039 cpu = get_cpu();
6040 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6041 if (policy.cpuinfo.max_freq)
6042 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6043 put_cpu();
c285545f 6044#endif
b820cc0c
ZA		 6045 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6046 CPUFREQ_TRANSITION_NOTIFIER);
6047 }
c285545f 6048 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6049
73c1b41e 6050 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6051 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6052}
6053
ff9d07a0
ZY		 6054static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6055
f5132b01 6056int kvm_is_in_guest(void)
ff9d07a0 6057{
086c9855 6058 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6059}
6060
6061static int kvm_is_user_mode(void)
6062{
6063 int user_mode = 3;
dcf46b94 6064
086c9855
AS		 6065 if (__this_cpu_read(current_vcpu))
6066 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6067
ff9d07a0
ZY		 6068 return user_mode != 0;
6069}
6070
6071static unsigned long kvm_get_guest_ip(void)
6072{
6073 unsigned long ip = 0;
dcf46b94 6074
086c9855
AS		 6075 if (__this_cpu_read(current_vcpu))
6076 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6077
ff9d07a0
ZY		 6078 return ip;
6079}
6080
6081static struct perf_guest_info_callbacks kvm_guest_cbs = {
6082 .is_in_guest = kvm_is_in_guest,
6083 .is_user_mode = kvm_is_user_mode,
6084 .get_guest_ip = kvm_get_guest_ip,
6085};
6086
6087void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6088{
086c9855 6089 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6090}
6091EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6092
6093void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6094{
086c9855 6095 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6096}
6097EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6098
ce88decf
XG		 6099static void kvm_set_mmio_spte_mask(void)
6100{
6101 u64 mask;
6102 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6103
6104 /*
6105 * Set the reserved bits and the present bit of an paging-structure
6106 * entry to generate page fault with PFER.RSV = 1.
6107 */
885032b9 6108 /* Mask the reserved physical address bits. */
d1431483 6109 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6110
885032b9 6111 /* Set the present bit. */
ce88decf
XG		 6112 mask |= 1ull;
6113
6114#ifdef CONFIG_X86_64
6115 /*
6116 * If reserved bit is not supported, clear the present bit to disable
6117 * mmio page fault.
6118 */
6119 if (maxphyaddr == 52)
6120 mask &= ~1ull;
6121#endif
6122
dcdca5fe 6123 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6124}
6125
16e8d74d
MT		 6126#ifdef CONFIG_X86_64
6127static void pvclock_gtod_update_fn(struct work_struct *work)
6128{
d828199e
MT		 6129 struct kvm *kvm;
6130
6131 struct kvm_vcpu *vcpu;
6132 int i;
6133
2f303b74 6134 spin_lock(&kvm_lock);
d828199e
MT		 6135 list_for_each_entry(kvm, &vm_list, vm_list)
6136 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6137 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6138 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6139 spin_unlock(&kvm_lock);
16e8d74d
MT		 6140}
6141
6142static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6143
6144/*
6145 * Notification about pvclock gtod data update.
6146 */
6147static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6148 void *priv)
6149{
6150 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6151 struct timekeeper *tk = priv;
6152
6153 update_pvclock_gtod(tk);
6154
6155 /* disable master clock if host does not trust, or does not
b0c39dc6 6156 * use, TSC based clocksource.
16e8d74d 6157 */
b0c39dc6 6158 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6159 atomic_read(&kvm_guest_has_master_clock) != 0)
6160 queue_work(system_long_wq, &pvclock_gtod_work);
6161
6162 return 0;
6163}
6164
6165static struct notifier_block pvclock_gtod_notifier = {
6166 .notifier_call = pvclock_gtod_notify,
6167};
6168#endif
6169
f8c16bba 6170int kvm_arch_init(void *opaque)
043405e1 6171{
b820cc0c 6172 int r;
6b61edf7 6173 struct kvm_x86_ops *ops = opaque;
f8c16bba 6174
f8c16bba
ZX		 6175 if (kvm_x86_ops) {
6176 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6177 r = -EEXIST;
6178 goto out;
f8c16bba
ZX		 6179 }
6180
6181 if (!ops->cpu_has_kvm_support()) {
6182 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6183 r = -EOPNOTSUPP;
6184 goto out;
f8c16bba
ZX		 6185 }
6186 if (ops->disabled_by_bios()) {
6187 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6188 r = -EOPNOTSUPP;
6189 goto out;
f8c16bba
ZX		 6190 }
6191
013f6a5d
MT		 6192 r = -ENOMEM;
6193 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6194 if (!shared_msrs) {
6195 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6196 goto out;
6197 }
6198
97db56ce
AK		 6199 r = kvm_mmu_module_init();
6200 if (r)
013f6a5d 6201 goto out_free_percpu;
97db56ce 6202
ce88decf 6203 kvm_set_mmio_spte_mask();
97db56ce 6204
f8c16bba 6205 kvm_x86_ops = ops;
920c8377 6206
7b52345e 6207 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6208 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6209 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6210 kvm_timer_init();
c8076604 6211
ff9d07a0
ZY		 6212 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6213
d366bf7e 6214 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6215 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6216
c5cc421b 6217 kvm_lapic_init();
16e8d74d
MT		 6218#ifdef CONFIG_X86_64
6219 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6220#endif
6221
f8c16bba 6222 return 0;
56c6d28a 6223
013f6a5d
MT		 6224out_free_percpu:
6225 free_percpu(shared_msrs);
56c6d28a 6226out:
56c6d28a 6227 return r;
043405e1 6228}
8776e519 6229
f8c16bba
ZX		 6230void kvm_arch_exit(void)
6231{
cef84c30 6232 kvm_lapic_exit();
ff9d07a0
ZY		 6233 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6234
888d256e
JK		 6235 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6236 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6237 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6238 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6239#ifdef CONFIG_X86_64
6240 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6241#endif
f8c16bba 6242 kvm_x86_ops = NULL;
56c6d28a 6243 kvm_mmu_module_exit();
013f6a5d 6244 free_percpu(shared_msrs);
56c6d28a 6245}
f8c16bba 6246
5cb56059 6247int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6248{
6249 ++vcpu->stat.halt_exits;
35754c98 6250 if (lapic_in_kernel(vcpu)) {
a4535290 6251 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6252 return 1;
6253 } else {
6254 vcpu->run->exit_reason = KVM_EXIT_HLT;
6255 return 0;
6256 }
6257}
5cb56059
JS		 6258EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6259
6260int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6261{
6affcbed
KH		 6262 int ret = kvm_skip_emulated_instruction(vcpu);
6263 /*
6264 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6265 * KVM_EXIT_DEBUG here.
6266 */
6267 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6268}
8776e519
HB		 6269EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6270
8ef81a9a 6271#ifdef CONFIG_X86_64
55dd00a7
MT		 6272static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6273 unsigned long clock_type)
6274{
6275 struct kvm_clock_pairing clock_pairing;
6276 struct timespec ts;
80fbd89c 6277 u64 cycle;
55dd00a7
MT		 6278 int ret;
6279
6280 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6281 return -KVM_EOPNOTSUPP;
6282
6283 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6284 return -KVM_EOPNOTSUPP;
6285
6286 clock_pairing.sec = ts.tv_sec;
6287 clock_pairing.nsec = ts.tv_nsec;
6288 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6289 clock_pairing.flags = 0;
6290
6291 ret = 0;
6292 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6293 sizeof(struct kvm_clock_pairing)))
6294 ret = -KVM_EFAULT;
6295
6296 return ret;
6297}
8ef81a9a 6298#endif
55dd00a7 6299
6aef266c
SV		 6300/*
6301 * kvm_pv_kick_cpu_op: Kick a vcpu.
6302 *
6303 * @apicid - apicid of vcpu to be kicked.
6304 */
6305static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6306{
24d2166b 6307 struct kvm_lapic_irq lapic_irq;
6aef266c 6308
24d2166b
R		 6309 lapic_irq.shorthand = 0;
6310 lapic_irq.dest_mode = 0;
ebd28fcb 6311 lapic_irq.level = 0;
24d2166b 6312 lapic_irq.dest_id = apicid;
93bbf0b8 6313 lapic_irq.msi_redir_hint = false;
6aef266c 6314
24d2166b 6315 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6316 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6317}
6318
d62caabb
AS		 6319void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6320{
6321 vcpu->arch.apicv_active = false;
6322 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6323}
6324
8776e519
HB		 6325int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6326{
6327 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6328 int op_64_bit, r;
8776e519 6329
6affcbed 6330 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6331
55cd8e5a
GN		 6332 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6333 return kvm_hv_hypercall(vcpu);
6334
5fdbf976
MT		 6335 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6336 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6337 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6338 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6339 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6340
229456fc 6341 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6342
a449c7aa
NA		 6343 op_64_bit = is_64_bit_mode(vcpu);
6344 if (!op_64_bit) {
8776e519
HB		 6345 nr &= 0xFFFFFFFF;
6346 a0 &= 0xFFFFFFFF;
6347 a1 &= 0xFFFFFFFF;
6348 a2 &= 0xFFFFFFFF;
6349 a3 &= 0xFFFFFFFF;
6350 }
6351
07708c4a
JK		 6352 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6353 ret = -KVM_EPERM;
6354 goto out;
6355 }
6356
8776e519 6357 switch (nr) {
b93463aa
AK		 6358 case KVM_HC_VAPIC_POLL_IRQ:
6359 ret = 0;
6360 break;
6aef266c
SV		 6361 case KVM_HC_KICK_CPU:
6362 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6363 ret = 0;
6364 break;
8ef81a9a 6365#ifdef CONFIG_X86_64
55dd00a7
MT		 6366 case KVM_HC_CLOCK_PAIRING:
6367 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6368 break;
8ef81a9a 6369#endif
8776e519
HB		 6370 default:
6371 ret = -KVM_ENOSYS;
6372 break;
6373 }
07708c4a 6374out:
a449c7aa
NA		 6375 if (!op_64_bit)
6376 ret = (u32)ret;
5fdbf976 6377 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6378 ++vcpu->stat.hypercalls;
2f333bcb 6379 return r;
8776e519
HB		 6380}
6381EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6382
b6785def 6383static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6384{
d6aa1000 6385 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6386 char instruction[3];
5fdbf976 6387 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6388
8776e519 6389 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6390
ce2e852e
DV		 6391 return emulator_write_emulated(ctxt, rip, instruction, 3,
6392 &ctxt->exception);
8776e519
HB		 6393}
6394
851ba692 6395static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6396{
782d422b
MG		 6397 return vcpu->run->request_interrupt_window &&
6398 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6399}
6400
851ba692 6401static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6402{
851ba692
AK		 6403 struct kvm_run *kvm_run = vcpu->run;
6404
91586a3b 6405 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6406 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6407 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6408 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6409 kvm_run->ready_for_interrupt_injection =
6410 pic_in_kernel(vcpu->kvm) ||
782d422b 6411 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6412}
6413
95ba8273
GN		 6414static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6415{
6416 int max_irr, tpr;
6417
6418 if (!kvm_x86_ops->update_cr8_intercept)
6419 return;
6420
bce87cce 6421 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6422 return;
6423
d62caabb
AS		 6424 if (vcpu->arch.apicv_active)
6425 return;
6426
8db3baa2
GN		 6427 if (!vcpu->arch.apic->vapic_addr)
6428 max_irr = kvm_lapic_find_highest_irr(vcpu);
6429 else
6430 max_irr = -1;
95ba8273
GN		 6431
6432 if (max_irr != -1)
6433 max_irr >>= 4;
6434
6435 tpr = kvm_lapic_get_cr8(vcpu);
6436
6437 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6438}
6439
b6b8a145 6440static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6441{
b6b8a145
JK		 6442 int r;
6443
95ba8273 6444 /* try to reinject previous events if any */
664f8e26
WL		 6445 if (vcpu->arch.exception.injected) {
6446 kvm_x86_ops->queue_exception(vcpu);
6447 return 0;
6448 }
6449
6450 /*
6451 * Exceptions must be injected immediately, or the exception
6452 * frame will have the address of the NMI or interrupt handler.
6453 */
6454 if (!vcpu->arch.exception.pending) {
6455 if (vcpu->arch.nmi_injected) {
6456 kvm_x86_ops->set_nmi(vcpu);
6457 return 0;
6458 }
6459
6460 if (vcpu->arch.interrupt.pending) {
6461 kvm_x86_ops->set_irq(vcpu);
6462 return 0;
6463 }
6464 }
6465
6466 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6467 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6468 if (r != 0)
6469 return r;
6470 }
6471
6472 /* try to inject new event if pending */
b59bb7bd 6473 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6474 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6475 vcpu->arch.exception.has_error_code,
6476 vcpu->arch.exception.error_code);
d6e8c854 6477
664f8e26
WL		 6478 vcpu->arch.exception.pending = false;
6479 vcpu->arch.exception.injected = true;
6480
d6e8c854
NA		 6481 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6482 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6483 X86_EFLAGS_RF);
6484
6bdf0662
NA		 6485 if (vcpu->arch.exception.nr == DB_VECTOR &&
6486 (vcpu->arch.dr7 & DR7_GD)) {
6487 vcpu->arch.dr7 &= ~DR7_GD;
6488 kvm_update_dr7(vcpu);
6489 }
6490
cfcd20e5 6491 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6492 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6493 vcpu->arch.smi_pending = false;
ee2cd4b7 6494 enter_smm(vcpu);
c43203ca 6495 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6496 --vcpu->arch.nmi_pending;
6497 vcpu->arch.nmi_injected = true;
6498 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6499 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6500 /*
6501 * Because interrupts can be injected asynchronously, we are
6502 * calling check_nested_events again here to avoid a race condition.
6503 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6504 * proposal and current concerns. Perhaps we should be setting
6505 * KVM_REQ_EVENT only on certain events and not unconditionally?
6506 */
6507 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6508 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6509 if (r != 0)
6510 return r;
6511 }
95ba8273 6512 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6513 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6514 false);
6515 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6516 }
6517 }
ee2cd4b7 6518
b6b8a145 6519 return 0;
95ba8273
GN		 6520}
6521
7460fb4a
AK		 6522static void process_nmi(struct kvm_vcpu *vcpu)
6523{
6524 unsigned limit = 2;
6525
6526 /*
6527 * x86 is limited to one NMI running, and one NMI pending after it.
6528 * If an NMI is already in progress, limit further NMIs to just one.
6529 * Otherwise, allow two (and we'll inject the first one immediately).
6530 */
6531 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6532 limit = 1;
6533
6534 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6535 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6536 kvm_make_request(KVM_REQ_EVENT, vcpu);
6537}
6538
ee2cd4b7 6539static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6540{
6541 u32 flags = 0;
6542 flags |= seg->g << 23;
6543 flags |= seg->db << 22;
6544 flags |= seg->l << 21;
6545 flags |= seg->avl << 20;
6546 flags |= seg->present << 15;
6547 flags |= seg->dpl << 13;
6548 flags |= seg->s << 12;
6549 flags |= seg->type << 8;
6550 return flags;
6551}
6552
ee2cd4b7 6553static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6554{
6555 struct kvm_segment seg;
6556 int offset;
6557
6558 kvm_get_segment(vcpu, &seg, n);
6559 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6560
6561 if (n < 3)
6562 offset = 0x7f84 + n * 12;
6563 else
6564 offset = 0x7f2c + (n - 3) * 12;
6565
6566 put_smstate(u32, buf, offset + 8, seg.base);
6567 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6568 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6569}
6570
efbb288a 6571#ifdef CONFIG_X86_64
ee2cd4b7 6572static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6573{
6574 struct kvm_segment seg;
6575 int offset;
6576 u16 flags;
6577
6578 kvm_get_segment(vcpu, &seg, n);
6579 offset = 0x7e00 + n * 16;
6580
ee2cd4b7 6581 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6582 put_smstate(u16, buf, offset, seg.selector);
6583 put_smstate(u16, buf, offset + 2, flags);
6584 put_smstate(u32, buf, offset + 4, seg.limit);
6585 put_smstate(u64, buf, offset + 8, seg.base);
6586}
efbb288a 6587#endif
660a5d51 6588
ee2cd4b7 6589static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6590{
6591 struct desc_ptr dt;
6592 struct kvm_segment seg;
6593 unsigned long val;
6594 int i;
6595
6596 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6597 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6598 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6599 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6600
6601 for (i = 0; i < 8; i++)
6602 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6603
6604 kvm_get_dr(vcpu, 6, &val);
6605 put_smstate(u32, buf, 0x7fcc, (u32)val);
6606 kvm_get_dr(vcpu, 7, &val);
6607 put_smstate(u32, buf, 0x7fc8, (u32)val);
6608
6609 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6610 put_smstate(u32, buf, 0x7fc4, seg.selector);
6611 put_smstate(u32, buf, 0x7f64, seg.base);
6612 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6613 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6614
6615 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6616 put_smstate(u32, buf, 0x7fc0, seg.selector);
6617 put_smstate(u32, buf, 0x7f80, seg.base);
6618 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6619 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6620
6621 kvm_x86_ops->get_gdt(vcpu, &dt);
6622 put_smstate(u32, buf, 0x7f74, dt.address);
6623 put_smstate(u32, buf, 0x7f70, dt.size);
6624
6625 kvm_x86_ops->get_idt(vcpu, &dt);
6626 put_smstate(u32, buf, 0x7f58, dt.address);
6627 put_smstate(u32, buf, 0x7f54, dt.size);
6628
6629 for (i = 0; i < 6; i++)
ee2cd4b7 6630 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6631
6632 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6633
6634 /* revision id */
6635 put_smstate(u32, buf, 0x7efc, 0x00020000);
6636 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6637}
6638
ee2cd4b7 6639static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6640{
6641#ifdef CONFIG_X86_64
6642 struct desc_ptr dt;
6643 struct kvm_segment seg;
6644 unsigned long val;
6645 int i;
6646
6647 for (i = 0; i < 16; i++)
6648 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6649
6650 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6651 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6652
6653 kvm_get_dr(vcpu, 6, &val);
6654 put_smstate(u64, buf, 0x7f68, val);
6655 kvm_get_dr(vcpu, 7, &val);
6656 put_smstate(u64, buf, 0x7f60, val);
6657
6658 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6659 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6660 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6661
6662 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6663
6664 /* revision id */
6665 put_smstate(u32, buf, 0x7efc, 0x00020064);
6666
6667 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6668
6669 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6670 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6671 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6672 put_smstate(u32, buf, 0x7e94, seg.limit);
6673 put_smstate(u64, buf, 0x7e98, seg.base);
6674
6675 kvm_x86_ops->get_idt(vcpu, &dt);
6676 put_smstate(u32, buf, 0x7e84, dt.size);
6677 put_smstate(u64, buf, 0x7e88, dt.address);
6678
6679 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6680 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6681 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6682 put_smstate(u32, buf, 0x7e74, seg.limit);
6683 put_smstate(u64, buf, 0x7e78, seg.base);
6684
6685 kvm_x86_ops->get_gdt(vcpu, &dt);
6686 put_smstate(u32, buf, 0x7e64, dt.size);
6687 put_smstate(u64, buf, 0x7e68, dt.address);
6688
6689 for (i = 0; i < 6; i++)
ee2cd4b7 6690 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6691#else
6692 WARN_ON_ONCE(1);
6693#endif
6694}
6695
ee2cd4b7 6696static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6697{
660a5d51 6698 struct kvm_segment cs, ds;
18c3626e 6699 struct desc_ptr dt;
660a5d51
PB		 6700 char buf[512];
6701 u32 cr0;
6702
660a5d51 6703 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6704 memset(buf, 0, 512);
d6321d49 6705 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6706 enter_smm_save_state_64(vcpu, buf);
660a5d51 6707 else
ee2cd4b7 6708 enter_smm_save_state_32(vcpu, buf);
660a5d51 6709
0234bf88
LP		 6710 /*
6711 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6712 * vCPU state (e.g. leave guest mode) after we've saved the state into
6713 * the SMM state-save area.
6714 */
6715 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6716
6717 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6718 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6719
6720 if (kvm_x86_ops->get_nmi_mask(vcpu))
6721 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6722 else
6723 kvm_x86_ops->set_nmi_mask(vcpu, true);
6724
6725 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6726 kvm_rip_write(vcpu, 0x8000);
6727
6728 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6729 kvm_x86_ops->set_cr0(vcpu, cr0);
6730 vcpu->arch.cr0 = cr0;
6731
6732 kvm_x86_ops->set_cr4(vcpu, 0);
6733
18c3626e
PB		 6734 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6735 dt.address = dt.size = 0;
6736 kvm_x86_ops->set_idt(vcpu, &dt);
6737
660a5d51
PB		 6738 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6739
6740 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6741 cs.base = vcpu->arch.smbase;
6742
6743 ds.selector = 0;
6744 ds.base = 0;
6745
6746 cs.limit = ds.limit = 0xffffffff;
6747 cs.type = ds.type = 0x3;
6748 cs.dpl = ds.dpl = 0;
6749 cs.db = ds.db = 0;
6750 cs.s = ds.s = 1;
6751 cs.l = ds.l = 0;
6752 cs.g = ds.g = 1;
6753 cs.avl = ds.avl = 0;
6754 cs.present = ds.present = 1;
6755 cs.unusable = ds.unusable = 0;
6756 cs.padding = ds.padding = 0;
6757
6758 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6759 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6760 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6761 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6762 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6763 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6764
d6321d49 6765 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6766 kvm_x86_ops->set_efer(vcpu, 0);
6767
6768 kvm_update_cpuid(vcpu);
6769 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6770}
6771
ee2cd4b7 6772static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6773{
6774 vcpu->arch.smi_pending = true;
6775 kvm_make_request(KVM_REQ_EVENT, vcpu);
6776}
6777
2860c4b1
PB		 6778void kvm_make_scan_ioapic_request(struct kvm *kvm)
6779{
6780 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6781}
6782
3d81bc7e 6783static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6784{
5c919412
AS		 6785 u64 eoi_exit_bitmap[4];
6786
3d81bc7e
YZ		 6787 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6788 return;
c7c9c56c 6789
6308630b 6790 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6791
b053b2ae 6792 if (irqchip_split(vcpu->kvm))
6308630b 6793 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6794 else {
76dfafd5 6795 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6796 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6797 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6798 }
5c919412
AS		 6799 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6800 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6801 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6802}
6803
a70656b6
RK		 6804static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6805{
6806 ++vcpu->stat.tlb_flush;
6807 kvm_x86_ops->tlb_flush(vcpu);
6808}
6809
b1394e74
RK		 6810void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6811 unsigned long start, unsigned long end)
6812{
6813 unsigned long apic_address;
6814
6815 /*
6816 * The physical address of apic access page is stored in the VMCS.
6817 * Update it when it becomes invalid.
6818 */
6819 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6820 if (start <= apic_address && apic_address < end)
6821 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6822}
6823
4256f43f
TC		 6824void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6825{
c24ae0dc
TC		 6826 struct page *page = NULL;
6827
35754c98 6828 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6829 return;
6830
4256f43f
TC		 6831 if (!kvm_x86_ops->set_apic_access_page_addr)
6832 return;
6833
c24ae0dc 6834 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6835 if (is_error_page(page))
6836 return;
c24ae0dc
TC		 6837 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6838
6839 /*
6840 * Do not pin apic access page in memory, the MMU notifier
6841 * will call us again if it is migrated or swapped out.
6842 */
6843 put_page(page);
4256f43f
TC		 6844}
6845EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6846
9357d939 6847/*
362c698f 6848 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6849 * exiting to the userspace. Otherwise, the value will be returned to the
6850 * userspace.
6851 */
851ba692 6852static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6853{
6854 int r;
62a193ed
MG		 6855 bool req_int_win =
6856 dm_request_for_irq_injection(vcpu) &&
6857 kvm_cpu_accept_dm_intr(vcpu);
6858
730dca42 6859 bool req_immediate_exit = false;
b6c7a5dc 6860
2fa6e1e1 6861 if (kvm_request_pending(vcpu)) {
a8eeb04a 6862 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6863 kvm_mmu_unload(vcpu);
a8eeb04a 6864 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6865 __kvm_migrate_timers(vcpu);
d828199e
MT		 6866 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6867 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6868 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6869 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6870 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6871 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6872 if (unlikely(r))
6873 goto out;
6874 }
a8eeb04a 6875 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6876 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6877 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6878 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6879 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6880 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6881 r = 0;
6882 goto out;
6883 }
a8eeb04a 6884 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6885 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6886 vcpu->mmio_needed = 0;
71c4dfaf
JR		 6887 r = 0;
6888 goto out;
6889 }
af585b92
GN		 6890 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6891 /* Page is swapped out. Do synthetic halt */
6892 vcpu->arch.apf.halted = true;
6893 r = 1;
6894 goto out;
6895 }
c9aaa895
GC		 6896 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6897 record_steal_time(vcpu);
64d60670
PB		 6898 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6899 process_smi(vcpu);
7460fb4a
AK		 6900 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6901 process_nmi(vcpu);
f5132b01 6902 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6903 kvm_pmu_handle_event(vcpu);
f5132b01 6904 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6905 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6906 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6907 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6908 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6909 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6910 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6911 vcpu->run->eoi.vector =
6912 vcpu->arch.pending_ioapic_eoi;
6913 r = 0;
6914 goto out;
6915 }
6916 }
3d81bc7e
YZ		 6917 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6918 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6919 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6920 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6921 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6922 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6923 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6924 r = 0;
6925 goto out;
6926 }
e516cebb
AS		 6927 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6928 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6929 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6930 r = 0;
6931 goto out;
6932 }
db397571
AS		 6933 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6934 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6935 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6936 r = 0;
6937 goto out;
6938 }
f3b138c5
AS		 6939
6940 /*
6941 * KVM_REQ_HV_STIMER has to be processed after
6942 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6943 * depend on the guest clock being up-to-date
6944 */
1f4b34f8
AS		 6945 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6946 kvm_hv_process_stimers(vcpu);
2f52d58c 6947 }
b93463aa 6948
b463a6f7 6949 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6950 ++vcpu->stat.req_event;
66450a21
JK		 6951 kvm_apic_accept_events(vcpu);
6952 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6953 r = 1;
6954 goto out;
6955 }
6956
b6b8a145
JK		 6957 if (inject_pending_event(vcpu, req_int_win) != 0)
6958 req_immediate_exit = true;
321c5658 6959 else {
cc3d967f 6960 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 6961 *
cc3d967f
LP		 6962 * SMIs have three cases:
6963 * 1) They can be nested, and then there is nothing to
6964 * do here because RSM will cause a vmexit anyway.
6965 * 2) There is an ISA-specific reason why SMI cannot be
6966 * injected, and the moment when this changes can be
6967 * intercepted.
6968 * 3) Or the SMI can be pending because
6969 * inject_pending_event has completed the injection
6970 * of an IRQ or NMI from the previous vmexit, and
6971 * then we request an immediate exit to inject the
6972 * SMI.
c43203ca
PB		 6973 */
6974 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 6975 if (!kvm_x86_ops->enable_smi_window(vcpu))
6976 req_immediate_exit = true;
321c5658
YS		 6977 if (vcpu->arch.nmi_pending)
6978 kvm_x86_ops->enable_nmi_window(vcpu);
6979 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6980 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 6981 WARN_ON(vcpu->arch.exception.pending);
321c5658 6982 }
b463a6f7
AK		 6983
6984 if (kvm_lapic_enabled(vcpu)) {
6985 update_cr8_intercept(vcpu);
6986 kvm_lapic_sync_to_vapic(vcpu);
6987 }
6988 }
6989
d8368af8
AK		 6990 r = kvm_mmu_reload(vcpu);
6991 if (unlikely(r)) {
d905c069 6992 goto cancel_injection;
d8368af8
AK		 6993 }
6994
b6c7a5dc
HB		 6995 preempt_disable();
6996
6997 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 6998
6999 /*
7000 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7001 * IPI are then delayed after guest entry, which ensures that they
7002 * result in virtual interrupt delivery.
7003 */
7004 local_irq_disable();
6b7e2d09
XG		 7005 vcpu->mode = IN_GUEST_MODE;
7006
01b71917
MT		 7007 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7008
0f127d12 7009 /*
b95234c8 7010 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7011 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7012 *
7013 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7014 * pairs with the memory barrier implicit in pi_test_and_set_on
7015 * (see vmx_deliver_posted_interrupt).
7016 *
7017 * 3) This also orders the write to mode from any reads to the page
7018 * tables done while the VCPU is running. Please see the comment
7019 * in kvm_flush_remote_tlbs.
6b7e2d09 7020 */
01b71917 7021 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7022
b95234c8
PB		 7023 /*
7024 * This handles the case where a posted interrupt was
7025 * notified with kvm_vcpu_kick.
7026 */
7027 if (kvm_lapic_enabled(vcpu)) {
7028 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
7029 kvm_x86_ops->sync_pir_to_irr(vcpu);
7030 }
32f88400 7031
2fa6e1e1 7032 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7033 || need_resched() || signal_pending(current)) {
6b7e2d09 7034 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7035 smp_wmb();
6c142801
AK		 7036 local_irq_enable();
7037 preempt_enable();
01b71917 7038 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7039 r = 1;
d905c069 7040 goto cancel_injection;
6c142801
AK		 7041 }
7042
fc5b7f3b
DM		 7043 kvm_load_guest_xcr0(vcpu);
7044
c43203ca
PB		 7045 if (req_immediate_exit) {
7046 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7047 smp_send_reschedule(vcpu->cpu);
c43203ca 7048 }
d6185f20 7049
8b89fe1f
PB		 7050 trace_kvm_entry(vcpu->vcpu_id);
7051 wait_lapic_expire(vcpu);
6edaa530 7052 guest_enter_irqoff();
b6c7a5dc 7053
42dbaa5a 7054 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7055 set_debugreg(0, 7);
7056 set_debugreg(vcpu->arch.eff_db[0], 0);
7057 set_debugreg(vcpu->arch.eff_db[1], 1);
7058 set_debugreg(vcpu->arch.eff_db[2], 2);
7059 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7060 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7061 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7062 }
b6c7a5dc 7063
851ba692 7064 kvm_x86_ops->run(vcpu);
b6c7a5dc 7065
c77fb5fe
PB		 7066 /*
7067 * Do this here before restoring debug registers on the host. And
7068 * since we do this before handling the vmexit, a DR access vmexit
7069 * can (a) read the correct value of the debug registers, (b) set
7070 * KVM_DEBUGREG_WONT_EXIT again.
7071 */
7072 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7073 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7074 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7075 kvm_update_dr0123(vcpu);
7076 kvm_update_dr6(vcpu);
7077 kvm_update_dr7(vcpu);
7078 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7079 }
7080
24f1e32c
FW		 7081 /*
7082 * If the guest has used debug registers, at least dr7
7083 * will be disabled while returning to the host.
7084 * If we don't have active breakpoints in the host, we don't
7085 * care about the messed up debug address registers. But if
7086 * we have some of them active, restore the old state.
7087 */
59d8eb53 7088 if (hw_breakpoint_active())
24f1e32c 7089 hw_breakpoint_restore();
42dbaa5a 7090
4ba76538 7091 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7092
6b7e2d09 7093 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7094 smp_wmb();
a547c6db 7095
fc5b7f3b
DM		 7096 kvm_put_guest_xcr0(vcpu);
7097
a547c6db 7098 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7099
7100 ++vcpu->stat.exits;
7101
f2485b3e 7102 guest_exit_irqoff();
b6c7a5dc 7103
f2485b3e 7104 local_irq_enable();
b6c7a5dc
HB		 7105 preempt_enable();
7106
f656ce01 7107 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7108
b6c7a5dc
HB		 7109 /*
7110 * Profile KVM exit RIPs:
7111 */
7112 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7113 unsigned long rip = kvm_rip_read(vcpu);
7114 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7115 }
7116
cc578287
ZA		 7117 if (unlikely(vcpu->arch.tsc_always_catchup))
7118 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7119
5cfb1d5a
MT		 7120 if (vcpu->arch.apic_attention)
7121 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7122
618232e2 7123 vcpu->arch.gpa_available = false;
851ba692 7124 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7125 return r;
7126
7127cancel_injection:
7128 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7129 if (unlikely(vcpu->arch.apic_attention))
7130 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7131out:
7132 return r;
7133}
b6c7a5dc 7134
362c698f
PB		 7135static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7136{
bf9f6ac8
FW		 7137 if (!kvm_arch_vcpu_runnable(vcpu) &&
7138 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7139 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7140 kvm_vcpu_block(vcpu);
7141 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7142
7143 if (kvm_x86_ops->post_block)
7144 kvm_x86_ops->post_block(vcpu);
7145
9c8fd1ba
PB		 7146 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7147 return 1;
7148 }
362c698f
PB		 7149
7150 kvm_apic_accept_events(vcpu);
7151 switch(vcpu->arch.mp_state) {
7152 case KVM_MP_STATE_HALTED:
7153 vcpu->arch.pv.pv_unhalted = false;
7154 vcpu->arch.mp_state =
7155 KVM_MP_STATE_RUNNABLE;
7156 case KVM_MP_STATE_RUNNABLE:
7157 vcpu->arch.apf.halted = false;
7158 break;
7159 case KVM_MP_STATE_INIT_RECEIVED:
7160 break;
7161 default:
7162 return -EINTR;
7163 break;
7164 }
7165 return 1;
7166}
09cec754 7167
5d9bc648
PB		 7168static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7169{
0ad3bed6
PB		 7170 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7171 kvm_x86_ops->check_nested_events(vcpu, false);
7172
5d9bc648
PB		 7173 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7174 !vcpu->arch.apf.halted);
7175}
7176
362c698f 7177static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7178{
7179 int r;
f656ce01 7180 struct kvm *kvm = vcpu->kvm;
d7690175 7181
f656ce01 7182 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7183
362c698f 7184 for (;;) {
58f800d5 7185 if (kvm_vcpu_running(vcpu)) {
851ba692 7186 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7187 } else {
362c698f 7188 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7189 }
7190
09cec754
GN		 7191 if (r <= 0)
7192 break;
7193
72875d8a 7194 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7195 if (kvm_cpu_has_pending_timer(vcpu))
7196 kvm_inject_pending_timer_irqs(vcpu);
7197
782d422b
MG		 7198 if (dm_request_for_irq_injection(vcpu) &&
7199 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7200 r = 0;
7201 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7202 ++vcpu->stat.request_irq_exits;
362c698f 7203 break;
09cec754 7204 }
af585b92
GN		 7205
7206 kvm_check_async_pf_completion(vcpu);
7207
09cec754
GN		 7208 if (signal_pending(current)) {
7209 r = -EINTR;
851ba692 7210 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7211 ++vcpu->stat.signal_exits;
362c698f 7212 break;
09cec754
GN		 7213 }
7214 if (need_resched()) {
f656ce01 7215 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7216 cond_resched();
f656ce01 7217 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7218 }
b6c7a5dc
HB		 7219 }
7220
f656ce01 7221 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7222
7223 return r;
7224}
7225
716d51ab
GN		 7226static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7227{
7228 int r;
7229 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7230 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7231 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7232 if (r != EMULATE_DONE)
7233 return 0;
7234 return 1;
7235}
7236
7237static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7238{
7239 BUG_ON(!vcpu->arch.pio.count);
7240
7241 return complete_emulated_io(vcpu);
7242}
7243
f78146b0
AK		 7244/*
7245 * Implements the following, as a state machine:
7246 *
7247 * read:
7248 * for each fragment
87da7e66
XG		 7249 * for each mmio piece in the fragment
7250 * write gpa, len
7251 * exit
7252 * copy data
f78146b0
AK		 7253 * execute insn
7254 *
7255 * write:
7256 * for each fragment
87da7e66
XG		 7257 * for each mmio piece in the fragment
7258 * write gpa, len
7259 * copy data
7260 * exit
f78146b0 7261 */
716d51ab 7262static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7263{
7264 struct kvm_run *run = vcpu->run;
f78146b0 7265 struct kvm_mmio_fragment *frag;
87da7e66 7266 unsigned len;
5287f194 7267
716d51ab 7268 BUG_ON(!vcpu->mmio_needed);
5287f194 7269
716d51ab 7270 /* Complete previous fragment */
87da7e66
XG		 7271 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7272 len = min(8u, frag->len);
716d51ab 7273 if (!vcpu->mmio_is_write)
87da7e66
XG		 7274 memcpy(frag->data, run->mmio.data, len);
7275
7276 if (frag->len <= 8) {
7277 /* Switch to the next fragment. */
7278 frag++;
7279 vcpu->mmio_cur_fragment++;
7280 } else {
7281 /* Go forward to the next mmio piece. */
7282 frag->data += len;
7283 frag->gpa += len;
7284 frag->len -= len;
7285 }
7286
a08d3b3b 7287 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7288 vcpu->mmio_needed = 0;
0912c977
PB		 7289
7290 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7291 if (vcpu->mmio_is_write)
716d51ab
GN		 7292 return 1;
7293 vcpu->mmio_read_completed = 1;
7294 return complete_emulated_io(vcpu);
7295 }
87da7e66 7296
716d51ab
GN		 7297 run->exit_reason = KVM_EXIT_MMIO;
7298 run->mmio.phys_addr = frag->gpa;
7299 if (vcpu->mmio_is_write)
87da7e66
XG		 7300 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7301 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7302 run->mmio.is_write = vcpu->mmio_is_write;
7303 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7304 return 0;
5287f194
AK		 7305}
7306
716d51ab 7307
b6c7a5dc
HB		 7308int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7309{
7310 int r;
b6c7a5dc 7311
20b7035c 7312 kvm_sigset_activate(vcpu);
ac9f6dc0 7313
5663d8f9
PX		 7314 kvm_load_guest_fpu(vcpu);
7315
a4535290 7316 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7317 if (kvm_run->immediate_exit) {
7318 r = -EINTR;
7319 goto out;
7320 }
b6c7a5dc 7321 kvm_vcpu_block(vcpu);
66450a21 7322 kvm_apic_accept_events(vcpu);
72875d8a 7323 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7324 r = -EAGAIN;
a0595000
JS		 7325 if (signal_pending(current)) {
7326 r = -EINTR;
7327 vcpu->run->exit_reason = KVM_EXIT_INTR;
7328 ++vcpu->stat.signal_exits;
7329 }
ac9f6dc0 7330 goto out;
b6c7a5dc
HB		 7331 }
7332
b6c7a5dc 7333 /* re-sync apic's tpr */
35754c98 7334 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7335 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7336 r = -EINVAL;
7337 goto out;
7338 }
7339 }
b6c7a5dc 7340
716d51ab
GN		 7341 if (unlikely(vcpu->arch.complete_userspace_io)) {
7342 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7343 vcpu->arch.complete_userspace_io = NULL;
7344 r = cui(vcpu);
7345 if (r <= 0)
5663d8f9 7346 goto out;
716d51ab
GN		 7347 } else
7348 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7349
460df4c1
PB		 7350 if (kvm_run->immediate_exit)
7351 r = -EINTR;
7352 else
7353 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7354
7355out:
5663d8f9 7356 kvm_put_guest_fpu(vcpu);
f1d86e46 7357 post_kvm_run_save(vcpu);
20b7035c 7358 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7359
b6c7a5dc
HB		 7360 return r;
7361}
7362
7363int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7364{
7ae441ea
GN		 7365 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7366 /*
7367 * We are here if userspace calls get_regs() in the middle of
7368 * instruction emulation. Registers state needs to be copied
4a969980 7369 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7370 * that usually, but some bad designed PV devices (vmware
7371 * backdoor interface) need this to work
7372 */
dd856efa 7373 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7374 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7375 }
5fdbf976
MT		 7376 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7377 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7378 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7379 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7380 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7381 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7382 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7383 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7384#ifdef CONFIG_X86_64
5fdbf976
MT		 7385 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7386 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7387 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7388 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7389 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7390 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7391 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7392 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7393#endif
7394
5fdbf976 7395 regs->rip = kvm_rip_read(vcpu);
91586a3b 7396 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7397
b6c7a5dc
HB		 7398 return 0;
7399}
7400
7401int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7402{
7ae441ea
GN		 7403 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7404 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7405
5fdbf976
MT		 7406 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7407 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7408 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7409 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7410 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7411 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7412 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7413 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7414#ifdef CONFIG_X86_64
5fdbf976
MT		 7415 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7416 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7417 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7418 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7419 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7420 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7421 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7422 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7423#endif
7424
5fdbf976 7425 kvm_rip_write(vcpu, regs->rip);
d73235d1 7426 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7427
b4f14abd
JK		 7428 vcpu->arch.exception.pending = false;
7429
3842d135
AK		 7430 kvm_make_request(KVM_REQ_EVENT, vcpu);
7431
b6c7a5dc
HB		 7432 return 0;
7433}
7434
b6c7a5dc
HB		 7435void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7436{
7437 struct kvm_segment cs;
7438
3e6e0aab 7439 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7440 *db = cs.db;
7441 *l = cs.l;
7442}
7443EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7444
7445int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7446 struct kvm_sregs *sregs)
7447{
89a27f4d 7448 struct desc_ptr dt;
b6c7a5dc 7449
3e6e0aab
GT		 7450 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7451 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7452 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7453 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7454 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7455 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7456
3e6e0aab
GT		 7457 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7458 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7459
7460 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7461 sregs->idt.limit = dt.size;
7462 sregs->idt.base = dt.address;
b6c7a5dc 7463 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7464 sregs->gdt.limit = dt.size;
7465 sregs->gdt.base = dt.address;
b6c7a5dc 7466
4d4ec087 7467 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7468 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7469 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7470 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7471 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7472 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7473 sregs->apic_base = kvm_get_apic_base(vcpu);
7474
923c61bb 7475 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7476
36752c9b 7477 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7478 set_bit(vcpu->arch.interrupt.nr,
7479 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7480
b6c7a5dc
HB		 7481 return 0;
7482}
7483
62d9f0db
MT		 7484int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7485 struct kvm_mp_state *mp_state)
7486{
66450a21 7487 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7488 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7489 vcpu->arch.pv.pv_unhalted)
7490 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7491 else
7492 mp_state->mp_state = vcpu->arch.mp_state;
7493
62d9f0db
MT		 7494 return 0;
7495}
7496
7497int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7498 struct kvm_mp_state *mp_state)
7499{
bce87cce 7500 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7501 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7502 return -EINVAL;
7503
28bf2888
DH		 7504 /* INITs are latched while in SMM */
7505 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7506 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7507 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7508 return -EINVAL;
7509
66450a21
JK		 7510 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7511 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7512 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7513 } else
7514 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7515 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7516 return 0;
7517}
7518
7f3d35fd
KW		 7519int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7520 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7521{
9d74191a 7522 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7523 int ret;
e01c2426 7524
8ec4722d 7525 init_emulate_ctxt(vcpu);
c697518a 7526
7f3d35fd 7527 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7528 has_error_code, error_code);
c697518a 7529
c697518a 7530 if (ret)
19d04437 7531 return EMULATE_FAIL;
37817f29 7532
9d74191a
TY		 7533 kvm_rip_write(vcpu, ctxt->eip);
7534 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7535 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7536 return EMULATE_DONE;
37817f29
IE		 7537}
7538EXPORT_SYMBOL_GPL(kvm_task_switch);
7539
f2981033
LT		 7540int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7541{
37b95951 7542 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7543 /*
7544 * When EFER.LME and CR0.PG are set, the processor is in
7545 * 64-bit mode (though maybe in a 32-bit code segment).
7546 * CR4.PAE and EFER.LMA must be set.
7547 */
37b95951 7548 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7549 || !(sregs->efer & EFER_LMA))
7550 return -EINVAL;
7551 } else {
7552 /*
7553 * Not in 64-bit mode: EFER.LMA is clear and the code
7554 * segment cannot be 64-bit.
7555 */
7556 if (sregs->efer & EFER_LMA || sregs->cs.l)
7557 return -EINVAL;
7558 }
7559
7560 return 0;
7561}
7562
b6c7a5dc
HB		 7563int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7564 struct kvm_sregs *sregs)
7565{
58cb628d 7566 struct msr_data apic_base_msr;
b6c7a5dc 7567 int mmu_reset_needed = 0;
63f42e02 7568 int pending_vec, max_bits, idx;
89a27f4d 7569 struct desc_ptr dt;
b6c7a5dc 7570
d6321d49
RK		 7571 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7572 (sregs->cr4 & X86_CR4_OSXSAVE))
6d1068b3
PM		 7573 return -EINVAL;
7574
f2981033
LT		 7575 if (kvm_valid_sregs(vcpu, sregs))
7576 return -EINVAL;
7577
d3802286
JM		 7578 apic_base_msr.data = sregs->apic_base;
7579 apic_base_msr.host_initiated = true;
7580 if (kvm_set_apic_base(vcpu, &apic_base_msr))
6d1068b3
PM		 7581 return -EINVAL;
7582
89a27f4d
GN		 7583 dt.size = sregs->idt.limit;
7584 dt.address = sregs->idt.base;
b6c7a5dc 7585 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7586 dt.size = sregs->gdt.limit;
7587 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7588 kvm_x86_ops->set_gdt(vcpu, &dt);
7589
ad312c7c 7590 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7591 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7592 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7593 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7594
2d3ad1f4 7595 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7596
f6801dff 7597 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7598 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7599
4d4ec087 7600 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7601 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7602 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7603
fc78f519 7604 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7605 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7606 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7607 kvm_update_cpuid(vcpu);
63f42e02
XG		 7608
7609 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7610 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7611 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7612 mmu_reset_needed = 1;
7613 }
63f42e02 7614 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7615
7616 if (mmu_reset_needed)
7617 kvm_mmu_reset_context(vcpu);
7618
a50abc3b 7619 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7620 pending_vec = find_first_bit(
7621 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7622 if (pending_vec < max_bits) {
66fd3f7f 7623 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7624 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7625 }
7626
3e6e0aab
GT		 7627 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7628 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7629 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7630 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7631 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7632 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7633
3e6e0aab
GT		 7634 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7635 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7636
5f0269f5
ME		 7637 update_cr8_intercept(vcpu);
7638
9c3e4aab 7639 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7640 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7641 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7642 !is_protmode(vcpu))
9c3e4aab
MT		 7643 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7644
3842d135
AK		 7645 kvm_make_request(KVM_REQ_EVENT, vcpu);
7646
b6c7a5dc
HB		 7647 return 0;
7648}
7649
d0bfb940
JK		 7650int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7651 struct kvm_guest_debug *dbg)
b6c7a5dc 7652{
355be0b9 7653 unsigned long rflags;
ae675ef0 7654 int i, r;
b6c7a5dc 7655
4f926bf2
JK		 7656 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7657 r = -EBUSY;
7658 if (vcpu->arch.exception.pending)
2122ff5e 7659 goto out;
4f926bf2
JK		 7660 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7661 kvm_queue_exception(vcpu, DB_VECTOR);
7662 else
7663 kvm_queue_exception(vcpu, BP_VECTOR);
7664 }
7665
91586a3b
JK		 7666 /*
7667 * Read rflags as long as potentially injected trace flags are still
7668 * filtered out.
7669 */
7670 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7671
7672 vcpu->guest_debug = dbg->control;
7673 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7674 vcpu->guest_debug = 0;
7675
7676 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7677 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7678 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7679 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7680 } else {
7681 for (i = 0; i < KVM_NR_DB_REGS; i++)
7682 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7683 }
c8639010 7684 kvm_update_dr7(vcpu);
ae675ef0 7685
f92653ee
JK		 7686 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7687 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7688 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7689
91586a3b
JK		 7690 /*
7691 * Trigger an rflags update that will inject or remove the trace
7692 * flags.
7693 */
7694 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7695
a96036b8 7696 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7697
4f926bf2 7698 r = 0;
d0bfb940 7699
2122ff5e 7700out:
b6c7a5dc
HB		 7701
7702 return r;
7703}
7704
8b006791
ZX		 7705/*
7706 * Translate a guest virtual address to a guest physical address.
7707 */
7708int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7709 struct kvm_translation *tr)
7710{
7711 unsigned long vaddr = tr->linear_address;
7712 gpa_t gpa;
f656ce01 7713 int idx;
8b006791 7714
f656ce01 7715 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7716 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7717 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7718 tr->physical_address = gpa;
7719 tr->valid = gpa != UNMAPPED_GVA;
7720 tr->writeable = 1;
7721 tr->usermode = 0;
8b006791
ZX		 7722
7723 return 0;
7724}
7725
d0752060
HB		 7726int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7727{
c47ada30 7728 struct fxregs_state *fxsave =
7366ed77 7729 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7730
d0752060
HB		 7731 memcpy(fpu->fpr, fxsave->st_space, 128);
7732 fpu->fcw = fxsave->cwd;
7733 fpu->fsw = fxsave->swd;
7734 fpu->ftwx = fxsave->twd;
7735 fpu->last_opcode = fxsave->fop;
7736 fpu->last_ip = fxsave->rip;
7737 fpu->last_dp = fxsave->rdp;
7738 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7739
d0752060
HB		 7740 return 0;
7741}
7742
7743int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7744{
c47ada30 7745 struct fxregs_state *fxsave =
7366ed77 7746 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7747
d0752060
HB		 7748 memcpy(fxsave->st_space, fpu->fpr, 128);
7749 fxsave->cwd = fpu->fcw;
7750 fxsave->swd = fpu->fsw;
7751 fxsave->twd = fpu->ftwx;
7752 fxsave->fop = fpu->last_opcode;
7753 fxsave->rip = fpu->last_ip;
7754 fxsave->rdp = fpu->last_dp;
7755 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7756
d0752060
HB		 7757 return 0;
7758}
7759
0ee6a517 7760static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7761{
bf935b0b 7762 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7763 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7764 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7765 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7766
2acf923e
DC		 7767 /*
7768 * Ensure guest xcr0 is valid for loading
7769 */
d91cab78 7770 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7771
ad312c7c 7772 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7773}
d0752060 7774
f775b13e 7775/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 7776void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7777{
f775b13e
RR		 7778 preempt_disable();
7779 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 7780 /* PKRU is separately restored in kvm_x86_ops->run. */
7781 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7782 ~XFEATURE_MASK_PKRU);
f775b13e 7783 preempt_enable();
0c04851c 7784 trace_kvm_fpu(1);
d0752060 7785}
d0752060 7786
f775b13e 7787/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 7788void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7789{
f775b13e 7790 preempt_disable();
4f836347 7791 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 7792 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7793 preempt_enable();
f096ed85 7794 ++vcpu->stat.fpu_reload;
0c04851c 7795 trace_kvm_fpu(0);
d0752060 7796}
e9b11c17
ZX		 7797
7798void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7799{
bd768e14
IY		 7800 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7801
12f9a48f 7802 kvmclock_reset(vcpu);
7f1ea208 7803
e9b11c17 7804 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7805 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7806}
7807
7808struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7809 unsigned int id)
7810{
c447e76b
LL		 7811 struct kvm_vcpu *vcpu;
7812
b0c39dc6 7813 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 7814 printk_once(KERN_WARNING
7815 "kvm: SMP vm created on host with unstable TSC; "
7816 "guest TSC will not be reliable\n");
c447e76b
LL		 7817
7818 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7819
c447e76b 7820 return vcpu;
26e5215f 7821}
e9b11c17 7822
26e5215f
AK		 7823int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7824{
7825 int r;
e9b11c17 7826
19efffa2 7827 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7828 r = vcpu_load(vcpu);
7829 if (r)
7830 return r;
d28bc9dd 7831 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7832 kvm_mmu_setup(vcpu);
e9b11c17 7833 vcpu_put(vcpu);
26e5215f 7834 return r;
e9b11c17
ZX		 7835}
7836
31928aa5 7837void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7838{
8fe8ab46 7839 struct msr_data msr;
332967a3 7840 struct kvm *kvm = vcpu->kvm;
42897d86 7841
d3457c87
RK		 7842 kvm_hv_vcpu_postcreate(vcpu);
7843
31928aa5
DD		 7844 if (vcpu_load(vcpu))
7845 return;
8fe8ab46
WA		 7846 msr.data = 0x0;
7847 msr.index = MSR_IA32_TSC;
7848 msr.host_initiated = true;
7849 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7850 vcpu_put(vcpu);
7851
630994b3
MT		 7852 if (!kvmclock_periodic_sync)
7853 return;
7854
332967a3
AJ		 7855 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7856 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7857}
7858
d40ccc62 7859void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7860{
9fc77441 7861 int r;
344d9588
GN		 7862 vcpu->arch.apf.msr_val = 0;
7863
9fc77441
MT		 7864 r = vcpu_load(vcpu);
7865 BUG_ON(r);
e9b11c17
ZX		 7866 kvm_mmu_unload(vcpu);
7867 vcpu_put(vcpu);
7868
7869 kvm_x86_ops->vcpu_free(vcpu);
7870}
7871
d28bc9dd 7872void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7873{
e69fab5d
PB		 7874 vcpu->arch.hflags = 0;
7875
c43203ca 7876 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7877 atomic_set(&vcpu->arch.nmi_queued, 0);
7878 vcpu->arch.nmi_pending = 0;
448fa4a9 7879 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7880 kvm_clear_interrupt_queue(vcpu);
7881 kvm_clear_exception_queue(vcpu);
664f8e26 7882 vcpu->arch.exception.pending = false;
448fa4a9 7883
42dbaa5a 7884 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7885 kvm_update_dr0123(vcpu);
6f43ed01 7886 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7887 kvm_update_dr6(vcpu);
42dbaa5a 7888 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7889 kvm_update_dr7(vcpu);
42dbaa5a 7890
1119022c
NA		 7891 vcpu->arch.cr2 = 0;
7892
3842d135 7893 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7894 vcpu->arch.apf.msr_val = 0;
c9aaa895 7895 vcpu->arch.st.msr_val = 0;
3842d135 7896
12f9a48f
GC		 7897 kvmclock_reset(vcpu);
7898
af585b92
GN		 7899 kvm_clear_async_pf_completion_queue(vcpu);
7900 kvm_async_pf_hash_reset(vcpu);
7901 vcpu->arch.apf.halted = false;
3842d135 7902
a554d207
WL		 7903 if (kvm_mpx_supported()) {
7904 void *mpx_state_buffer;
7905
7906 /*
7907 * To avoid have the INIT path from kvm_apic_has_events() that be
7908 * called with loaded FPU and does not let userspace fix the state.
7909 */
f775b13e
RR		 7910 if (init_event)
7911 kvm_put_guest_fpu(vcpu);
a554d207
WL		 7912 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7913 XFEATURE_MASK_BNDREGS);
7914 if (mpx_state_buffer)
7915 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
7916 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7917 XFEATURE_MASK_BNDCSR);
7918 if (mpx_state_buffer)
7919 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 7920 if (init_event)
7921 kvm_load_guest_fpu(vcpu);
a554d207
WL		 7922 }
7923
64d60670 7924 if (!init_event) {
d28bc9dd 7925 kvm_pmu_reset(vcpu);
64d60670 7926 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 7927
7928 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7929 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 7930
7931 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 7932 }
f5132b01 7933
66f7b72e
JS		 7934 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7935 vcpu->arch.regs_avail = ~0;
7936 vcpu->arch.regs_dirty = ~0;
7937
a554d207
WL		 7938 vcpu->arch.ia32_xss = 0;
7939
d28bc9dd 7940 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7941}
7942
2b4a273b 7943void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7944{
7945 struct kvm_segment cs;
7946
7947 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7948 cs.selector = vector << 8;
7949 cs.base = vector << 12;
7950 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7951 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7952}
7953
13a34e06 7954int kvm_arch_hardware_enable(void)
e9b11c17 7955{
ca84d1a2
ZA		 7956 struct kvm *kvm;
7957 struct kvm_vcpu *vcpu;
7958 int i;
0dd6a6ed
ZA		 7959 int ret;
7960 u64 local_tsc;
7961 u64 max_tsc = 0;
7962 bool stable, backwards_tsc = false;
18863bdd
AK		 7963
7964 kvm_shared_msr_cpu_online();
13a34e06 7965 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7966 if (ret != 0)
7967 return ret;
7968
4ea1636b 7969 local_tsc = rdtsc();
b0c39dc6 7970 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 7971 list_for_each_entry(kvm, &vm_list, vm_list) {
7972 kvm_for_each_vcpu(i, vcpu, kvm) {
7973 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7974 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7975 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7976 backwards_tsc = true;
7977 if (vcpu->arch.last_host_tsc > max_tsc)
7978 max_tsc = vcpu->arch.last_host_tsc;
7979 }
7980 }
7981 }
7982
7983 /*
7984 * Sometimes, even reliable TSCs go backwards. This happens on
7985 * platforms that reset TSC during suspend or hibernate actions, but
7986 * maintain synchronization. We must compensate. Fortunately, we can
7987 * detect that condition here, which happens early in CPU bringup,
7988 * before any KVM threads can be running. Unfortunately, we can't
7989 * bring the TSCs fully up to date with real time, as we aren't yet far
7990 * enough into CPU bringup that we know how much real time has actually
108b249c 7991 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7992 * variables that haven't been updated yet.
7993 *
7994 * So we simply find the maximum observed TSC above, then record the
7995 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7996 * the adjustment will be applied. Note that we accumulate
7997 * adjustments, in case multiple suspend cycles happen before some VCPU
7998 * gets a chance to run again. In the event that no KVM threads get a
7999 * chance to run, we will miss the entire elapsed period, as we'll have
8000 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8001 * loose cycle time. This isn't too big a deal, since the loss will be
8002 * uniform across all VCPUs (not to mention the scenario is extremely
8003 * unlikely). It is possible that a second hibernate recovery happens
8004 * much faster than a first, causing the observed TSC here to be
8005 * smaller; this would require additional padding adjustment, which is
8006 * why we set last_host_tsc to the local tsc observed here.
8007 *
8008 * N.B. - this code below runs only on platforms with reliable TSC,
8009 * as that is the only way backwards_tsc is set above. Also note
8010 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8011 * have the same delta_cyc adjustment applied if backwards_tsc
8012 * is detected. Note further, this adjustment is only done once,
8013 * as we reset last_host_tsc on all VCPUs to stop this from being
8014 * called multiple times (one for each physical CPU bringup).
8015 *
4a969980 8016 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8017 * will be compensated by the logic in vcpu_load, which sets the TSC to
8018 * catchup mode. This will catchup all VCPUs to real time, but cannot
8019 * guarantee that they stay in perfect synchronization.
8020 */
8021 if (backwards_tsc) {
8022 u64 delta_cyc = max_tsc - local_tsc;
8023 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8024 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8025 kvm_for_each_vcpu(i, vcpu, kvm) {
8026 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8027 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8028 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8029 }
8030
8031 /*
8032 * We have to disable TSC offset matching.. if you were
8033 * booting a VM while issuing an S4 host suspend....
8034 * you may have some problem. Solving this issue is
8035 * left as an exercise to the reader.
8036 */
8037 kvm->arch.last_tsc_nsec = 0;
8038 kvm->arch.last_tsc_write = 0;
8039 }
8040
8041 }
8042 return 0;
e9b11c17
ZX		 8043}
8044
13a34e06 8045void kvm_arch_hardware_disable(void)
e9b11c17 8046{
13a34e06
RK		 8047 kvm_x86_ops->hardware_disable();
8048 drop_user_return_notifiers();
e9b11c17
ZX		 8049}
8050
8051int kvm_arch_hardware_setup(void)
8052{
9e9c3fe4
NA		 8053 int r;
8054
8055 r = kvm_x86_ops->hardware_setup();
8056 if (r != 0)
8057 return r;
8058
35181e86
HZ		 8059 if (kvm_has_tsc_control) {
8060 /*
8061 * Make sure the user can only configure tsc_khz values that
8062 * fit into a signed integer.
8063 * A min value is not calculated needed because it will always
8064 * be 1 on all machines.
8065 */
8066 u64 max = min(0x7fffffffULL,
8067 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8068 kvm_max_guest_tsc_khz = max;
8069
ad721883 8070 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8071 }
ad721883 8072
9e9c3fe4
NA		 8073 kvm_init_msr_list();
8074 return 0;
e9b11c17
ZX		 8075}
8076
8077void kvm_arch_hardware_unsetup(void)
8078{
8079 kvm_x86_ops->hardware_unsetup();
8080}
8081
8082void kvm_arch_check_processor_compat(void *rtn)
8083{
8084 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8085}
8086
8087bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8088{
8089 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8090}
8091EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8092
8093bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8094{
8095 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8096}
8097
54e9818f 8098struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8099EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8100
e9b11c17
ZX		 8101int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8102{
8103 struct page *page;
e9b11c17
ZX		 8104 int r;
8105
b2a05fef 8106 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8107 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8108 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8109 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8110 else
a4535290 8111 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8112
8113 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8114 if (!page) {
8115 r = -ENOMEM;
8116 goto fail;
8117 }
ad312c7c 8118 vcpu->arch.pio_data = page_address(page);
e9b11c17 8119
cc578287 8120 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8121
e9b11c17
ZX		 8122 r = kvm_mmu_create(vcpu);
8123 if (r < 0)
8124 goto fail_free_pio_data;
8125
26de7988 8126 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8127 r = kvm_create_lapic(vcpu);
8128 if (r < 0)
8129 goto fail_mmu_destroy;
54e9818f
GN		 8130 } else
8131 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8132
890ca9ae
HY		 8133 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8134 GFP_KERNEL);
8135 if (!vcpu->arch.mce_banks) {
8136 r = -ENOMEM;
443c39bc 8137 goto fail_free_lapic;
890ca9ae
HY		 8138 }
8139 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8140
f1797359
WY		 8141 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8142 r = -ENOMEM;
f5f48ee1 8143 goto fail_free_mce_banks;
f1797359 8144 }
f5f48ee1 8145
0ee6a517 8146 fx_init(vcpu);
66f7b72e 8147
4344ee98 8148 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8149
5a4f55cd
EK		 8150 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8151
74545705
RK		 8152 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8153
af585b92 8154 kvm_async_pf_hash_reset(vcpu);
f5132b01 8155 kvm_pmu_init(vcpu);
af585b92 8156
1c1a9ce9 8157 vcpu->arch.pending_external_vector = -1;
de63ad4c 8158 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8159
5c919412
AS		 8160 kvm_hv_vcpu_init(vcpu);
8161
e9b11c17 8162 return 0;
0ee6a517 8163
f5f48ee1
SY		 8164fail_free_mce_banks:
8165 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8166fail_free_lapic:
8167 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8168fail_mmu_destroy:
8169 kvm_mmu_destroy(vcpu);
8170fail_free_pio_data:
ad312c7c 8171 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8172fail:
8173 return r;
8174}
8175
8176void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8177{
f656ce01
MT		 8178 int idx;
8179
1f4b34f8 8180 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8181 kvm_pmu_destroy(vcpu);
36cb93fd 8182 kfree(vcpu->arch.mce_banks);
e9b11c17 8183 kvm_free_lapic(vcpu);
f656ce01 8184 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8185 kvm_mmu_destroy(vcpu);
f656ce01 8186 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8187 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8188 if (!lapic_in_kernel(vcpu))
54e9818f 8189 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8190}
d19a9cd2 8191
e790d9ef
RK		 8192void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8193{
ae97a3b8 8194 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8195}
8196
e08b9637 8197int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8198{
e08b9637
CO		 8199 if (type)
8200 return -EINVAL;
8201
6ef768fa 8202 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8203 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8204 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8205 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8206 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8207
5550af4d
SY		 8208 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8209 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8210 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8211 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8212 &kvm->arch.irq_sources_bitmap);
5550af4d 8213
038f8c11 8214 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8215 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8216 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8217 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8218
108b249c 8219 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8220 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8221
7e44e449 8222 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8223 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8224
0eb05bf2 8225 kvm_page_track_init(kvm);
13d268ca 8226 kvm_mmu_init_vm(kvm);
0eb05bf2 8227
03543133
SS		 8228 if (kvm_x86_ops->vm_init)
8229 return kvm_x86_ops->vm_init(kvm);
8230
d89f5eff 8231 return 0;
d19a9cd2
ZX		 8232}
8233
8234static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8235{
9fc77441
MT		 8236 int r;
8237 r = vcpu_load(vcpu);
8238 BUG_ON(r);
d19a9cd2
ZX		 8239 kvm_mmu_unload(vcpu);
8240 vcpu_put(vcpu);
8241}
8242
8243static void kvm_free_vcpus(struct kvm *kvm)
8244{
8245 unsigned int i;
988a2cae 8246 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8247
8248 /*
8249 * Unpin any mmu pages first.
8250 */
af585b92
GN		 8251 kvm_for_each_vcpu(i, vcpu, kvm) {
8252 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8253 kvm_unload_vcpu_mmu(vcpu);
af585b92 8254 }
988a2cae
GN		 8255 kvm_for_each_vcpu(i, vcpu, kvm)
8256 kvm_arch_vcpu_free(vcpu);
8257
8258 mutex_lock(&kvm->lock);
8259 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8260 kvm->vcpus[i] = NULL;
d19a9cd2 8261
988a2cae
GN		 8262 atomic_set(&kvm->online_vcpus, 0);
8263 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8264}
8265
ad8ba2cd
SY		 8266void kvm_arch_sync_events(struct kvm *kvm)
8267{
332967a3 8268 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8269 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8270 kvm_free_pit(kvm);
ad8ba2cd
SY		 8271}
8272
1d8007bd 8273int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8274{
8275 int i, r;
25188b99 8276 unsigned long hva;
f0d648bd
PB		 8277 struct kvm_memslots *slots = kvm_memslots(kvm);
8278 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8279
8280 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8281 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8282 return -EINVAL;
9da0e4d5 8283
f0d648bd
PB		 8284 slot = id_to_memslot(slots, id);
8285 if (size) {
b21629da 8286 if (slot->npages)
f0d648bd
PB		 8287 return -EEXIST;
8288
8289 /*
8290 * MAP_SHARED to prevent internal slot pages from being moved
8291 * by fork()/COW.
8292 */
8293 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8294 MAP_SHARED | MAP_ANONYMOUS, 0);
8295 if (IS_ERR((void *)hva))
8296 return PTR_ERR((void *)hva);
8297 } else {
8298 if (!slot->npages)
8299 return 0;
8300
8301 hva = 0;
8302 }
8303
8304 old = *slot;
9da0e4d5 8305 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8306 struct kvm_userspace_memory_region m;
9da0e4d5 8307
1d8007bd
PB		 8308 m.slot = id | (i << 16);
8309 m.flags = 0;
8310 m.guest_phys_addr = gpa;
f0d648bd 8311 m.userspace_addr = hva;
1d8007bd 8312 m.memory_size = size;
9da0e4d5
PB		 8313 r = __kvm_set_memory_region(kvm, &m);
8314 if (r < 0)
8315 return r;
8316 }
8317
f0d648bd
PB		 8318 if (!size) {
8319 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8320 WARN_ON(r < 0);
8321 }
8322
9da0e4d5
PB		 8323 return 0;
8324}
8325EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8326
1d8007bd 8327int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8328{
8329 int r;
8330
8331 mutex_lock(&kvm->slots_lock);
1d8007bd 8332 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8333 mutex_unlock(&kvm->slots_lock);
8334
8335 return r;
8336}
8337EXPORT_SYMBOL_GPL(x86_set_memory_region);
8338
d19a9cd2
ZX		 8339void kvm_arch_destroy_vm(struct kvm *kvm)
8340{
27469d29
AH		 8341 if (current->mm == kvm->mm) {
8342 /*
8343 * Free memory regions allocated on behalf of userspace,
8344 * unless the the memory map has changed due to process exit
8345 * or fd copying.
8346 */
1d8007bd
PB		 8347 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8348 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8349 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8350 }
03543133
SS		 8351 if (kvm_x86_ops->vm_destroy)
8352 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8353 kvm_pic_destroy(kvm);
8354 kvm_ioapic_destroy(kvm);
d19a9cd2 8355 kvm_free_vcpus(kvm);
af1bae54 8356 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8357 kvm_mmu_uninit_vm(kvm);
2beb6dad 8358 kvm_page_track_cleanup(kvm);
d19a9cd2 8359}
0de10343 8360
5587027c 8361void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8362 struct kvm_memory_slot *dont)
8363{
8364 int i;
8365
d89cc617
TY		 8366 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8367 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8368 kvfree(free->arch.rmap[i]);
d89cc617 8369 free->arch.rmap[i] = NULL;
77d11309 8370 }
d89cc617
TY		 8371 if (i == 0)
8372 continue;
8373
8374 if (!dont || free->arch.lpage_info[i - 1] !=
8375 dont->arch.lpage_info[i - 1]) {
548ef284 8376 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8377 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8378 }
8379 }
21ebbeda
XG		 8380
8381 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8382}
8383
5587027c
AK		 8384int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8385 unsigned long npages)
db3fe4eb
TY		 8386{
8387 int i;
8388
d89cc617 8389 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8390 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8391 unsigned long ugfn;
8392 int lpages;
d89cc617 8393 int level = i + 1;
db3fe4eb
TY		 8394
8395 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8396 slot->base_gfn, level) + 1;
8397
d89cc617 8398 slot->arch.rmap[i] =
a7c3e901 8399 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8400 if (!slot->arch.rmap[i])
77d11309 8401 goto out_free;
d89cc617
TY		 8402 if (i == 0)
8403 continue;
77d11309 8404
a7c3e901 8405 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8406 if (!linfo)
db3fe4eb
TY		 8407 goto out_free;
8408
92f94f1e
XG		 8409 slot->arch.lpage_info[i - 1] = linfo;
8410
db3fe4eb 8411 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8412 linfo[0].disallow_lpage = 1;
db3fe4eb 8413 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8414 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8415 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8416 /*
8417 * If the gfn and userspace address are not aligned wrt each
8418 * other, or if explicitly asked to, disable large page
8419 * support for this slot
8420 */
8421 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8422 !kvm_largepages_enabled()) {
8423 unsigned long j;
8424
8425 for (j = 0; j < lpages; ++j)
92f94f1e 8426 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8427 }
8428 }
8429
21ebbeda
XG		 8430 if (kvm_page_track_create_memslot(slot, npages))
8431 goto out_free;
8432
db3fe4eb
TY		 8433 return 0;
8434
8435out_free:
d89cc617 8436 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8437 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8438 slot->arch.rmap[i] = NULL;
8439 if (i == 0)
8440 continue;
8441
548ef284 8442 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8443 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8444 }
8445 return -ENOMEM;
8446}
8447
15f46015 8448void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8449{
e6dff7d1
TY		 8450 /*
8451 * memslots->generation has been incremented.
8452 * mmio generation may have reached its maximum value.
8453 */
54bf36aa 8454 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8455}
8456
f7784b8e
MT		 8457int kvm_arch_prepare_memory_region(struct kvm *kvm,
8458 struct kvm_memory_slot *memslot,
09170a49 8459 const struct kvm_userspace_memory_region *mem,
7b6195a9 8460 enum kvm_mr_change change)
0de10343 8461{
f7784b8e
MT		 8462 return 0;
8463}
8464
88178fd4
KH		 8465static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8466 struct kvm_memory_slot *new)
8467{
8468 /* Still write protect RO slot */
8469 if (new->flags & KVM_MEM_READONLY) {
8470 kvm_mmu_slot_remove_write_access(kvm, new);
8471 return;
8472 }
8473
8474 /*
8475 * Call kvm_x86_ops dirty logging hooks when they are valid.
8476 *
8477 * kvm_x86_ops->slot_disable_log_dirty is called when:
8478 *
8479 * - KVM_MR_CREATE with dirty logging is disabled
8480 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8481 *
8482 * The reason is, in case of PML, we need to set D-bit for any slots
8483 * with dirty logging disabled in order to eliminate unnecessary GPA
8484 * logging in PML buffer (and potential PML buffer full VMEXT). This
8485 * guarantees leaving PML enabled during guest's lifetime won't have
8486 * any additonal overhead from PML when guest is running with dirty
8487 * logging disabled for memory slots.
8488 *
8489 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8490 * to dirty logging mode.
8491 *
8492 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8493 *
8494 * In case of write protect:
8495 *
8496 * Write protect all pages for dirty logging.
8497 *
8498 * All the sptes including the large sptes which point to this
8499 * slot are set to readonly. We can not create any new large
8500 * spte on this slot until the end of the logging.
8501 *
8502 * See the comments in fast_page_fault().
8503 */
8504 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8505 if (kvm_x86_ops->slot_enable_log_dirty)
8506 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8507 else
8508 kvm_mmu_slot_remove_write_access(kvm, new);
8509 } else {
8510 if (kvm_x86_ops->slot_disable_log_dirty)
8511 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8512 }
8513}
8514
f7784b8e 8515void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8516 const struct kvm_userspace_memory_region *mem,
8482644a 8517 const struct kvm_memory_slot *old,
f36f3f28 8518 const struct kvm_memory_slot *new,
8482644a 8519 enum kvm_mr_change change)
f7784b8e 8520{
8482644a 8521 int nr_mmu_pages = 0;
f7784b8e 8522
48c0e4e9
XG		 8523 if (!kvm->arch.n_requested_mmu_pages)
8524 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8525
48c0e4e9 8526 if (nr_mmu_pages)
0de10343 8527 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8528
3ea3b7fa
WL		 8529 /*
8530 * Dirty logging tracks sptes in 4k granularity, meaning that large
8531 * sptes have to be split. If live migration is successful, the guest
8532 * in the source machine will be destroyed and large sptes will be
8533 * created in the destination. However, if the guest continues to run
8534 * in the source machine (for example if live migration fails), small
8535 * sptes will remain around and cause bad performance.
8536 *
8537 * Scan sptes if dirty logging has been stopped, dropping those
8538 * which can be collapsed into a single large-page spte. Later
8539 * page faults will create the large-page sptes.
8540 */
8541 if ((change != KVM_MR_DELETE) &&
8542 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8543 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8544 kvm_mmu_zap_collapsible_sptes(kvm, new);
8545
c972f3b1 8546 /*
88178fd4 8547 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8548 *
88178fd4
KH		 8549 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8550 * been zapped so no dirty logging staff is needed for old slot. For
8551 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8552 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8553 *
8554 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8555 */
88178fd4 8556 if (change != KVM_MR_DELETE)
f36f3f28 8557 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8558}
1d737c8a 8559
2df72e9b 8560void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8561{
6ca18b69 8562 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8563}
8564
2df72e9b
MT		 8565void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8566 struct kvm_memory_slot *slot)
8567{
ae7cd873 8568 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8569}
8570
5d9bc648
PB		 8571static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8572{
8573 if (!list_empty_careful(&vcpu->async_pf.done))
8574 return true;
8575
8576 if (kvm_apic_has_events(vcpu))
8577 return true;
8578
8579 if (vcpu->arch.pv.pv_unhalted)
8580 return true;
8581
a5f01f8e
WL		 8582 if (vcpu->arch.exception.pending)
8583 return true;
8584
47a66eed
Z		 8585 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8586 (vcpu->arch.nmi_pending &&
8587 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8588 return true;
8589
47a66eed
Z		 8590 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8591 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8592 return true;
8593
5d9bc648
PB		 8594 if (kvm_arch_interrupt_allowed(vcpu) &&
8595 kvm_cpu_has_interrupt(vcpu))
8596 return true;
8597
1f4b34f8
AS		 8598 if (kvm_hv_has_stimer_pending(vcpu))
8599 return true;
8600
5d9bc648
PB		 8601 return false;
8602}
8603
1d737c8a
ZX		 8604int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8605{
5d9bc648 8606 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8607}
5736199a 8608
199b5763
LM		 8609bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8610{
de63ad4c 8611 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8612}
8613
b6d33834 8614int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8615{
b6d33834 8616 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8617}
78646121
GN		 8618
8619int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8620{
8621 return kvm_x86_ops->interrupt_allowed(vcpu);
8622}
229456fc 8623
82b32774 8624unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8625{
82b32774
NA		 8626 if (is_64_bit_mode(vcpu))
8627 return kvm_rip_read(vcpu);
8628 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8629 kvm_rip_read(vcpu));
8630}
8631EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8632
82b32774
NA		 8633bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8634{
8635 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8636}
8637EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8638
94fe45da
JK		 8639unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8640{
8641 unsigned long rflags;
8642
8643 rflags = kvm_x86_ops->get_rflags(vcpu);
8644 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8645 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8646 return rflags;
8647}
8648EXPORT_SYMBOL_GPL(kvm_get_rflags);
8649
6addfc42 8650static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8651{
8652 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8653 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8654 rflags |= X86_EFLAGS_TF;
94fe45da 8655 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8656}
8657
8658void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8659{
8660 __kvm_set_rflags(vcpu, rflags);
3842d135 8661 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8662}
8663EXPORT_SYMBOL_GPL(kvm_set_rflags);
8664
56028d08
GN		 8665void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8666{
8667 int r;
8668
fb67e14f 8669 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8670 work->wakeup_all)
56028d08
GN		 8671 return;
8672
8673 r = kvm_mmu_reload(vcpu);
8674 if (unlikely(r))
8675 return;
8676
fb67e14f
XG		 8677 if (!vcpu->arch.mmu.direct_map &&
8678 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8679 return;
8680
56028d08
GN		 8681 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8682}
8683
af585b92
GN		 8684static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8685{
8686 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8687}
8688
8689static inline u32 kvm_async_pf_next_probe(u32 key)
8690{
8691 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8692}
8693
8694static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8695{
8696 u32 key = kvm_async_pf_hash_fn(gfn);
8697
8698 while (vcpu->arch.apf.gfns[key] != ~0)
8699 key = kvm_async_pf_next_probe(key);
8700
8701 vcpu->arch.apf.gfns[key] = gfn;
8702}
8703
8704static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8705{
8706 int i;
8707 u32 key = kvm_async_pf_hash_fn(gfn);
8708
8709 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8710 (vcpu->arch.apf.gfns[key] != gfn &&
8711 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8712 key = kvm_async_pf_next_probe(key);
8713
8714 return key;
8715}
8716
8717bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8718{
8719 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8720}
8721
8722static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8723{
8724 u32 i, j, k;
8725
8726 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8727 while (true) {
8728 vcpu->arch.apf.gfns[i] = ~0;
8729 do {
8730 j = kvm_async_pf_next_probe(j);
8731 if (vcpu->arch.apf.gfns[j] == ~0)
8732 return;
8733 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8734 /*
8735 * k lies cyclically in ]i,j]
8736 * | i.k.j |
8737 * |....j i.k.| or |.k..j i...|
8738 */
8739 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8740 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8741 i = j;
8742 }
8743}
8744
7c90705b
GN		 8745static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8746{
4e335d9e
PB		 8747
8748 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8749 sizeof(val));
7c90705b
GN		 8750}
8751
9a6e7c39
WL		 8752static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8753{
8754
8755 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8756 sizeof(u32));
8757}
8758
af585b92
GN		 8759void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8760 struct kvm_async_pf *work)
8761{
6389ee94
AK		 8762 struct x86_exception fault;
8763
7c90705b 8764 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8765 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8766
8767 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8768 (vcpu->arch.apf.send_user_only &&
8769 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8770 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8771 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8772 fault.vector = PF_VECTOR;
8773 fault.error_code_valid = true;
8774 fault.error_code = 0;
8775 fault.nested_page_fault = false;
8776 fault.address = work->arch.token;
adfe20fb 8777 fault.async_page_fault = true;
6389ee94 8778 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8779 }
af585b92
GN		 8780}
8781
8782void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8783 struct kvm_async_pf *work)
8784{
6389ee94 8785 struct x86_exception fault;
9a6e7c39 8786 u32 val;
6389ee94 8787
f2e10669 8788 if (work->wakeup_all)
7c90705b
GN		 8789 work->arch.token = ~0; /* broadcast wakeup */
8790 else
8791 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8792 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8793
9a6e7c39
WL		 8794 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8795 !apf_get_user(vcpu, &val)) {
8796 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8797 vcpu->arch.exception.pending &&
8798 vcpu->arch.exception.nr == PF_VECTOR &&
8799 !apf_put_user(vcpu, 0)) {
8800 vcpu->arch.exception.injected = false;
8801 vcpu->arch.exception.pending = false;
8802 vcpu->arch.exception.nr = 0;
8803 vcpu->arch.exception.has_error_code = false;
8804 vcpu->arch.exception.error_code = 0;
8805 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8806 fault.vector = PF_VECTOR;
8807 fault.error_code_valid = true;
8808 fault.error_code = 0;
8809 fault.nested_page_fault = false;
8810 fault.address = work->arch.token;
8811 fault.async_page_fault = true;
8812 kvm_inject_page_fault(vcpu, &fault);
8813 }
7c90705b 8814 }
e6d53e3b 8815 vcpu->arch.apf.halted = false;
a4fa1635 8816 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8817}
8818
8819bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8820{
8821 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8822 return true;
8823 else
9bc1f09f 8824 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 8825}
8826
5544eb9b
PB		 8827void kvm_arch_start_assignment(struct kvm *kvm)
8828{
8829 atomic_inc(&kvm->arch.assigned_device_count);
8830}
8831EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8832
8833void kvm_arch_end_assignment(struct kvm *kvm)
8834{
8835 atomic_dec(&kvm->arch.assigned_device_count);
8836}
8837EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8838
8839bool kvm_arch_has_assigned_device(struct kvm *kvm)
8840{
8841 return atomic_read(&kvm->arch.assigned_device_count);
8842}
8843EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8844
e0f0bbc5
AW		 8845void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8846{
8847 atomic_inc(&kvm->arch.noncoherent_dma_count);
8848}
8849EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8850
8851void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8852{
8853 atomic_dec(&kvm->arch.noncoherent_dma_count);
8854}
8855EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8856
8857bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8858{
8859 return atomic_read(&kvm->arch.noncoherent_dma_count);
8860}
8861EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8862
14717e20
AW		 8863bool kvm_arch_has_irq_bypass(void)
8864{
8865 return kvm_x86_ops->update_pi_irte != NULL;
8866}
8867
87276880
FW		 8868int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8869 struct irq_bypass_producer *prod)
8870{
8871 struct kvm_kernel_irqfd *irqfd =
8872 container_of(cons, struct kvm_kernel_irqfd, consumer);
8873
14717e20 8874 irqfd->producer = prod;
87276880 8875
14717e20
AW		 8876 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8877 prod->irq, irqfd->gsi, 1);
87276880
FW		 8878}
8879
8880void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8881 struct irq_bypass_producer *prod)
8882{
8883 int ret;
8884 struct kvm_kernel_irqfd *irqfd =
8885 container_of(cons, struct kvm_kernel_irqfd, consumer);
8886
87276880
FW		 8887 WARN_ON(irqfd->producer != prod);
8888 irqfd->producer = NULL;
8889
8890 /*
8891 * When producer of consumer is unregistered, we change back to
8892 * remapped mode, so we can re-use the current implementation
bb3541f1 8893 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8894 * int this case doesn't want to receive the interrupts.
8895 */
8896 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8897 if (ret)
8898 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8899 " fails: %d\n", irqfd->consumer.token, ret);
8900}
8901
8902int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8903 uint32_t guest_irq, bool set)
8904{
8905 if (!kvm_x86_ops->update_pi_irte)
8906 return -EINVAL;
8907
8908 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8909}
8910
52004014
FW		 8911bool kvm_vector_hashing_enabled(void)
8912{
8913 return vector_hashing;
8914}
8915EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8916
229456fc 8917EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8918EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8919EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8920EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8921EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8922EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8923EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8924EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8925EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8926EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8927EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8928EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8929EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8930EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8931EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8932EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8933EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8934EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8935EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)