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KVM: SVM: correctly trace irq injection
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
ff9d07a0 43#include <linux/perf_event.h>
aec51dc4 44#include <trace/events/kvm.h>
2ed152af 45
229456fc
MT		 46#define CREATE_TRACE_POINTS
47#include "trace.h"
043405e1 48
24f1e32c 49#include <asm/debugreg.h>
043405e1 50#include <asm/uaccess.h>
d825ed0a 51#include <asm/msr.h>
a5f61300 52#include <asm/desc.h>
0bed3b56 53#include <asm/mtrr.h>
890ca9ae 54#include <asm/mce.h>
7cf30855 55#include <asm/i387.h>
98918833 56#include <asm/xcr.h>
043405e1 57
313a3dc7 58#define MAX_IO_MSRS 256
a03490ed
CO		 59#define CR0_RESERVED_BITS \
60 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
61 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
62 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
63#define CR4_RESERVED_BITS \
64 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
65 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
66 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
67 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
68
69#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 70
71#define KVM_MAX_MCE_BANKS 32
72#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
79static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
80#else
81static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
82#endif
313a3dc7 83
ba1389b7
AK		 84#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
85#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 86
cb142eb7 87static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 88static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
89 struct kvm_cpuid_entry2 __user *entries);
90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
ed85c068
AP		 94int ignore_msrs = 0;
95module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
96
18863bdd
AK		 97#define KVM_NR_SHARED_MSRS 16
98
99struct kvm_shared_msrs_global {
100 int nr;
2bf78fa7 101 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 102};
103
104struct kvm_shared_msrs {
105 struct user_return_notifier urn;
106 bool registered;
2bf78fa7
SY		 107 struct kvm_shared_msr_values {
108 u64 host;
109 u64 curr;
110 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 111};
112
113static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
114static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
115
417bc304 116struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 117 { "pf_fixed", VCPU_STAT(pf_fixed) },
118 { "pf_guest", VCPU_STAT(pf_guest) },
119 { "tlb_flush", VCPU_STAT(tlb_flush) },
120 { "invlpg", VCPU_STAT(invlpg) },
121 { "exits", VCPU_STAT(exits) },
122 { "io_exits", VCPU_STAT(io_exits) },
123 { "mmio_exits", VCPU_STAT(mmio_exits) },
124 { "signal_exits", VCPU_STAT(signal_exits) },
125 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 126 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 127 { "halt_exits", VCPU_STAT(halt_exits) },
128 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 129 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 130 { "request_irq", VCPU_STAT(request_irq_exits) },
131 { "irq_exits", VCPU_STAT(irq_exits) },
132 { "host_state_reload", VCPU_STAT(host_state_reload) },
133 { "efer_reload", VCPU_STAT(efer_reload) },
134 { "fpu_reload", VCPU_STAT(fpu_reload) },
135 { "insn_emulation", VCPU_STAT(insn_emulation) },
136 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 137 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 138 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 139 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
140 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
141 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
142 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
143 { "mmu_flooded", VM_STAT(mmu_flooded) },
144 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 145 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 146 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 147 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 148 { "largepages", VM_STAT(lpages) },
417bc304
HB		 149 { NULL }
150};
151
18863bdd
AK		 152static void kvm_on_user_return(struct user_return_notifier *urn)
153{
154 unsigned slot;
18863bdd
AK		 155 struct kvm_shared_msrs *locals
156 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 157 struct kvm_shared_msr_values *values;
18863bdd
AK		 158
159 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 160 values = &locals->values[slot];
161 if (values->host != values->curr) {
162 wrmsrl(shared_msrs_global.msrs[slot], values->host);
163 values->curr = values->host;
18863bdd
AK		 164 }
165 }
166 locals->registered = false;
167 user_return_notifier_unregister(urn);
168}
169
2bf78fa7 170static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 171{
2bf78fa7 172 struct kvm_shared_msrs *smsr;
18863bdd
AK		 173 u64 value;
174
2bf78fa7
SY		 175 smsr = &__get_cpu_var(shared_msrs);
176 /* only read, and nobody should modify it at this time,
177 * so don't need lock */
178 if (slot >= shared_msrs_global.nr) {
179 printk(KERN_ERR "kvm: invalid MSR slot!");
180 return;
181 }
182 rdmsrl_safe(msr, &value);
183 smsr->values[slot].host = value;
184 smsr->values[slot].curr = value;
185}
186
187void kvm_define_shared_msr(unsigned slot, u32 msr)
188{
18863bdd
AK		 189 if (slot >= shared_msrs_global.nr)
190 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 191 shared_msrs_global.msrs[slot] = msr;
192 /* we need ensured the shared_msr_global have been updated */
193 smp_wmb();
18863bdd
AK		 194}
195EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
196
197static void kvm_shared_msr_cpu_online(void)
198{
199 unsigned i;
18863bdd
AK		 200
201 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 202 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 203}
204
d5696725 205void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 206{
207 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
208
2bf78fa7 209 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 210 return;
2bf78fa7
SY		 211 smsr->values[slot].curr = value;
212 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 213 if (!smsr->registered) {
214 smsr->urn.on_user_return = kvm_on_user_return;
215 user_return_notifier_register(&smsr->urn);
216 smsr->registered = true;
217 }
218}
219EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
220
3548bab5
AK		 221static void drop_user_return_notifiers(void *ignore)
222{
223 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
224
225 if (smsr->registered)
226 kvm_on_user_return(&smsr->urn);
227}
228
6866b83e
CO		 229u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
230{
231 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 232 return vcpu->arch.apic_base;
6866b83e 233 else
ad312c7c 234 return vcpu->arch.apic_base;
6866b83e
CO		 235}
236EXPORT_SYMBOL_GPL(kvm_get_apic_base);
237
238void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
239{
240 /* TODO: reserve bits check */
241 if (irqchip_in_kernel(vcpu->kvm))
242 kvm_lapic_set_base(vcpu, data);
243 else
ad312c7c 244 vcpu->arch.apic_base = data;
6866b83e
CO		 245}
246EXPORT_SYMBOL_GPL(kvm_set_apic_base);
247
3fd28fce
ED		 248#define EXCPT_BENIGN 0
249#define EXCPT_CONTRIBUTORY 1
250#define EXCPT_PF 2
251
252static int exception_class(int vector)
253{
254 switch (vector) {
255 case PF_VECTOR:
256 return EXCPT_PF;
257 case DE_VECTOR:
258 case TS_VECTOR:
259 case NP_VECTOR:
260 case SS_VECTOR:
261 case GP_VECTOR:
262 return EXCPT_CONTRIBUTORY;
263 default:
264 break;
265 }
266 return EXCPT_BENIGN;
267}
268
269static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 270 unsigned nr, bool has_error, u32 error_code,
271 bool reinject)
3fd28fce
ED		 272{
273 u32 prev_nr;
274 int class1, class2;
275
276 if (!vcpu->arch.exception.pending) {
277 queue:
278 vcpu->arch.exception.pending = true;
279 vcpu->arch.exception.has_error_code = has_error;
280 vcpu->arch.exception.nr = nr;
281 vcpu->arch.exception.error_code = error_code;
3f0fd292 282 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 283 return;
284 }
285
286 /* to check exception */
287 prev_nr = vcpu->arch.exception.nr;
288 if (prev_nr == DF_VECTOR) {
289 /* triple fault -> shutdown */
290 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
291 return;
292 }
293 class1 = exception_class(prev_nr);
294 class2 = exception_class(nr);
295 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
296 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
297 /* generate double fault per SDM Table 5-5 */
298 vcpu->arch.exception.pending = true;
299 vcpu->arch.exception.has_error_code = true;
300 vcpu->arch.exception.nr = DF_VECTOR;
301 vcpu->arch.exception.error_code = 0;
302 } else
303 /* replace previous exception with a new one in a hope
304 that instruction re-execution will regenerate lost
305 exception */
306 goto queue;
307}
308
298101da
AK		 309void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
310{
ce7ddec4 311 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 312}
313EXPORT_SYMBOL_GPL(kvm_queue_exception);
314
ce7ddec4
JR		 315void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
316{
317 kvm_multiple_exception(vcpu, nr, false, 0, true);
318}
319EXPORT_SYMBOL_GPL(kvm_requeue_exception);
320
c3c91fee
AK		 321void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
322 u32 error_code)
323{
324 ++vcpu->stat.pf_guest;
ad312c7c 325 vcpu->arch.cr2 = addr;
c3c91fee
AK		 326 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
327}
328
3419ffc8
SY		 329void kvm_inject_nmi(struct kvm_vcpu *vcpu)
330{
331 vcpu->arch.nmi_pending = 1;
332}
333EXPORT_SYMBOL_GPL(kvm_inject_nmi);
334
298101da
AK		 335void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
336{
ce7ddec4 337 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 338}
339EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
340
ce7ddec4
JR		 341void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
342{
343 kvm_multiple_exception(vcpu, nr, true, error_code, true);
344}
345EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
346
0a79b009
AK		 347/*
348 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
349 * a #GP and return false.
350 */
351bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 352{
0a79b009
AK		 353 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
354 return true;
355 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
356 return false;
298101da 357}
0a79b009 358EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 359
a03490ed
CO		 360/*
361 * Load the pae pdptrs. Return true is they are all valid.
362 */
363int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
364{
365 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
366 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
367 int i;
368 int ret;
ad312c7c 369 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 370
a03490ed
CO		 371 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
372 offset * sizeof(u64), sizeof(pdpte));
373 if (ret < 0) {
374 ret = 0;
375 goto out;
376 }
377 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 378 if (is_present_gpte(pdpte[i]) &&
20c466b5 379 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 380 ret = 0;
381 goto out;
382 }
383 }
384 ret = 1;
385
ad312c7c 386 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 387 __set_bit(VCPU_EXREG_PDPTR,
388 (unsigned long *)&vcpu->arch.regs_avail);
389 __set_bit(VCPU_EXREG_PDPTR,
390 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 391out:
a03490ed
CO		 392
393 return ret;
394}
cc4b6871 395EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 396
d835dfec
AK		 397static bool pdptrs_changed(struct kvm_vcpu *vcpu)
398{
ad312c7c 399 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 400 bool changed = true;
401 int r;
402
403 if (is_long_mode(vcpu) || !is_pae(vcpu))
404 return false;
405
6de4f3ad
AK		 406 if (!test_bit(VCPU_EXREG_PDPTR,
407 (unsigned long *)&vcpu->arch.regs_avail))
408 return true;
409
ad312c7c 410 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 411 if (r < 0)
412 goto out;
ad312c7c 413 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 414out:
d835dfec
AK		 415
416 return changed;
417}
418
0f12244f 419static int __kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 420{
aad82703
SY		 421 unsigned long old_cr0 = kvm_read_cr0(vcpu);
422 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
423 X86_CR0_CD | X86_CR0_NW;
424
f9a48e6a
AK		 425 cr0 |= X86_CR0_ET;
426
ab344828 427#ifdef CONFIG_X86_64
0f12244f
GN		 428 if (cr0 & 0xffffffff00000000UL)
429 return 1;
ab344828
GN		 430#endif
431
432 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 433
0f12244f
GN		 434 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
435 return 1;
a03490ed 436
0f12244f
GN		 437 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
438 return 1;
a03490ed
CO		 439
440 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
441#ifdef CONFIG_X86_64
f6801dff 442 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 443 int cs_db, cs_l;
444
0f12244f
GN		 445 if (!is_pae(vcpu))
446 return 1;
a03490ed 447 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 448 if (cs_l)
449 return 1;
a03490ed
CO		 450 } else
451#endif
0f12244f
GN		 452 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3))
453 return 1;
a03490ed
CO		 454 }
455
456 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 457
aad82703
SY		 458 if ((cr0 ^ old_cr0) & update_bits)
459 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 460 return 0;
461}
462
463void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
464{
465 if (__kvm_set_cr0(vcpu, cr0))
466 kvm_inject_gp(vcpu, 0);
a03490ed 467}
2d3ad1f4 468EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 469
2d3ad1f4 470void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 471{
f78e9176 472 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 473}
2d3ad1f4 474EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 475
0f12244f 476int __kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 477{
fc78f519 478 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 479 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
480
0f12244f
GN		 481 if (cr4 & CR4_RESERVED_BITS)
482 return 1;
a03490ed
CO		 483
484 if (is_long_mode(vcpu)) {
0f12244f
GN		 485 if (!(cr4 & X86_CR4_PAE))
486 return 1;
a2edf57f
AK		 487 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
488 && ((cr4 ^ old_cr4) & pdptr_bits)
0f12244f
GN		 489 && !load_pdptrs(vcpu, vcpu->arch.cr3))
490 return 1;
491
492 if (cr4 & X86_CR4_VMXE)
493 return 1;
a03490ed 494
a03490ed 495 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 496
aad82703
SY		 497 if ((cr4 ^ old_cr4) & pdptr_bits)
498 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 499
500 return 0;
501}
502
503void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
504{
505 if (__kvm_set_cr4(vcpu, cr4))
506 kvm_inject_gp(vcpu, 0);
a03490ed 507}
2d3ad1f4 508EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 509
0f12244f 510static int __kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 511{
ad312c7c 512 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 513 kvm_mmu_sync_roots(vcpu);
d835dfec 514 kvm_mmu_flush_tlb(vcpu);
0f12244f 515 return 0;
d835dfec
AK		 516 }
517
a03490ed 518 if (is_long_mode(vcpu)) {
0f12244f
GN		 519 if (cr3 & CR3_L_MODE_RESERVED_BITS)
520 return 1;
a03490ed
CO		 521 } else {
522 if (is_pae(vcpu)) {
0f12244f
GN		 523 if (cr3 & CR3_PAE_RESERVED_BITS)
524 return 1;
525 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3))
526 return 1;
a03490ed
CO		 527 }
528 /*
529 * We don't check reserved bits in nonpae mode, because
530 * this isn't enforced, and VMware depends on this.
531 */
532 }
533
a03490ed
CO		 534 /*
535 * Does the new cr3 value map to physical memory? (Note, we
536 * catch an invalid cr3 even in real-mode, because it would
537 * cause trouble later on when we turn on paging anyway.)
538 *
539 * A real CPU would silently accept an invalid cr3 and would
540 * attempt to use it - with largely undefined (and often hard
541 * to debug) behavior on the guest side.
542 */
543 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 544 return 1;
545 vcpu->arch.cr3 = cr3;
546 vcpu->arch.mmu.new_cr3(vcpu);
547 return 0;
548}
549
550void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
551{
552 if (__kvm_set_cr3(vcpu, cr3))
c1a5d4f9 553 kvm_inject_gp(vcpu, 0);
a03490ed 554}
2d3ad1f4 555EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 556
0f12244f 557int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 558{
0f12244f
GN		 559 if (cr8 & CR8_RESERVED_BITS)
560 return 1;
a03490ed
CO		 561 if (irqchip_in_kernel(vcpu->kvm))
562 kvm_lapic_set_tpr(vcpu, cr8);
563 else
ad312c7c 564 vcpu->arch.cr8 = cr8;
0f12244f
GN		 565 return 0;
566}
567
568void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
569{
570 if (__kvm_set_cr8(vcpu, cr8))
571 kvm_inject_gp(vcpu, 0);
a03490ed 572}
2d3ad1f4 573EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 574
2d3ad1f4 575unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 576{
577 if (irqchip_in_kernel(vcpu->kvm))
578 return kvm_lapic_get_cr8(vcpu);
579 else
ad312c7c 580 return vcpu->arch.cr8;
a03490ed 581}
2d3ad1f4 582EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 583
338dbc97 584static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 585{
586 switch (dr) {
587 case 0 ... 3:
588 vcpu->arch.db[dr] = val;
589 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
590 vcpu->arch.eff_db[dr] = val;
591 break;
592 case 4:
338dbc97
GN		 593 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
594 return 1; /* #UD */
020df079
GN		 595 /* fall through */
596 case 6:
338dbc97
GN		 597 if (val & 0xffffffff00000000ULL)
598 return -1; /* #GP */
020df079
GN		 599 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
600 break;
601 case 5:
338dbc97
GN		 602 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
603 return 1; /* #UD */
020df079
GN		 604 /* fall through */
605 default: /* 7 */
338dbc97
GN		 606 if (val & 0xffffffff00000000ULL)
607 return -1; /* #GP */
020df079
GN		 608 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
609 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
610 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
611 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
612 }
613 break;
614 }
615
616 return 0;
617}
338dbc97
GN		 618
619int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
620{
621 int res;
622
623 res = __kvm_set_dr(vcpu, dr, val);
624 if (res > 0)
625 kvm_queue_exception(vcpu, UD_VECTOR);
626 else if (res < 0)
627 kvm_inject_gp(vcpu, 0);
628
629 return res;
630}
020df079
GN		 631EXPORT_SYMBOL_GPL(kvm_set_dr);
632
338dbc97 633static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 634{
635 switch (dr) {
636 case 0 ... 3:
637 *val = vcpu->arch.db[dr];
638 break;
639 case 4:
338dbc97 640 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 641 return 1;
020df079
GN		 642 /* fall through */
643 case 6:
644 *val = vcpu->arch.dr6;
645 break;
646 case 5:
338dbc97 647 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 648 return 1;
020df079
GN		 649 /* fall through */
650 default: /* 7 */
651 *val = vcpu->arch.dr7;
652 break;
653 }
654
655 return 0;
656}
338dbc97
GN		 657
658int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
659{
660 if (_kvm_get_dr(vcpu, dr, val)) {
661 kvm_queue_exception(vcpu, UD_VECTOR);
662 return 1;
663 }
664 return 0;
665}
020df079
GN		 666EXPORT_SYMBOL_GPL(kvm_get_dr);
667
d8017474
AG		 668static inline u32 bit(int bitno)
669{
670 return 1 << (bitno & 31);
671}
672
043405e1
CO		 673/*
674 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
675 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
676 *
677 * This list is modified at module load time to reflect the
e3267cbb
GC		 678 * capabilities of the host cpu. This capabilities test skips MSRs that are
679 * kvm-specific. Those are put in the beginning of the list.
043405e1 680 */
e3267cbb 681
11c6bffa 682#define KVM_SAVE_MSRS_BEGIN 7
043405e1 683static u32 msrs_to_save[] = {
e3267cbb 684 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 685 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 686 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 687 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 688 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
689 MSR_K6_STAR,
690#ifdef CONFIG_X86_64
691 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
692#endif
e3267cbb 693 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 694};
695
696static unsigned num_msrs_to_save;
697
698static u32 emulated_msrs[] = {
699 MSR_IA32_MISC_ENABLE,
700};
701
b69e8cae 702static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 703{
aad82703
SY		 704 u64 old_efer = vcpu->arch.efer;
705
b69e8cae
RJ		 706 if (efer & efer_reserved_bits)
707 return 1;
15c4a640
CO		 708
709 if (is_paging(vcpu)
b69e8cae
RJ		 710 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
711 return 1;
15c4a640 712
1b2fd70c
AG		 713 if (efer & EFER_FFXSR) {
714 struct kvm_cpuid_entry2 *feat;
715
716 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 717 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
718 return 1;
1b2fd70c
AG		 719 }
720
d8017474
AG		 721 if (efer & EFER_SVME) {
722 struct kvm_cpuid_entry2 *feat;
723
724 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 725 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
726 return 1;
d8017474
AG		 727 }
728
15c4a640 729 efer &= ~EFER_LMA;
f6801dff 730 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 731
a3d204e2
SY		 732 kvm_x86_ops->set_efer(vcpu, efer);
733
9645bb56
AK		 734 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
735 kvm_mmu_reset_context(vcpu);
b69e8cae 736
aad82703
SY		 737 /* Update reserved bits */
738 if ((efer ^ old_efer) & EFER_NX)
739 kvm_mmu_reset_context(vcpu);
740
b69e8cae 741 return 0;
15c4a640
CO		 742}
743
f2b4b7dd
JR		 744void kvm_enable_efer_bits(u64 mask)
745{
746 efer_reserved_bits &= ~mask;
747}
748EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
749
750
15c4a640
CO		 751/*
752 * Writes msr value into into the appropriate "register".
753 * Returns 0 on success, non-0 otherwise.
754 * Assumes vcpu_load() was already called.
755 */
756int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
757{
758 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
759}
760
313a3dc7
CO		 761/*
762 * Adapt set_msr() to msr_io()'s calling convention
763 */
764static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
765{
766 return kvm_set_msr(vcpu, index, *data);
767}
768
18068523
GOC		 769static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
770{
9ed3c444
AK		 771 int version;
772 int r;
50d0a0f9 773 struct pvclock_wall_clock wc;
923de3cf 774 struct timespec boot;
18068523
GOC		 775
776 if (!wall_clock)
777 return;
778
9ed3c444
AK		 779 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
780 if (r)
781 return;
782
783 if (version & 1)
784 ++version; /* first time write, random junk */
785
786 ++version;
18068523 787
18068523
GOC		 788 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
789
50d0a0f9
GH		 790 /*
791 * The guest calculates current wall clock time by adding
792 * system time (updated by kvm_write_guest_time below) to the
793 * wall clock specified here. guest system time equals host
794 * system time for us, thus we must fill in host boot time here.
795 */
923de3cf 796 getboottime(&boot);
50d0a0f9
GH		 797
798 wc.sec = boot.tv_sec;
799 wc.nsec = boot.tv_nsec;
800 wc.version = version;
18068523
GOC		 801
802 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
803
804 version++;
805 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 806}
807
50d0a0f9
GH		 808static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
809{
810 uint32_t quotient, remainder;
811
812 /* Don't try to replace with do_div(), this one calculates
813 * "(dividend << 32) / divisor" */
814 __asm__ ( "divl %4"
815 : "=a" (quotient), "=d" (remainder)
816 : "0" (0), "1" (dividend), "r" (divisor) );
817 return quotient;
818}
819
820static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
821{
822 uint64_t nsecs = 1000000000LL;
823 int32_t shift = 0;
824 uint64_t tps64;
825 uint32_t tps32;
826
827 tps64 = tsc_khz * 1000LL;
828 while (tps64 > nsecs*2) {
829 tps64 >>= 1;
830 shift--;
831 }
832
833 tps32 = (uint32_t)tps64;
834 while (tps32 <= (uint32_t)nsecs) {
835 tps32 <<= 1;
836 shift++;
837 }
838
839 hv_clock->tsc_shift = shift;
840 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
841
842 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 843 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 844 hv_clock->tsc_to_system_mul);
845}
846
c8076604
GH		 847static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
848
18068523
GOC		 849static void kvm_write_guest_time(struct kvm_vcpu *v)
850{
851 struct timespec ts;
852 unsigned long flags;
853 struct kvm_vcpu_arch *vcpu = &v->arch;
854 void *shared_kaddr;
463656c0 855 unsigned long this_tsc_khz;
18068523
GOC		 856
857 if ((!vcpu->time_page))
858 return;
859
463656c0
AK		 860 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
861 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
862 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
863 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 864 }
463656c0 865 put_cpu_var(cpu_tsc_khz);
50d0a0f9 866
18068523
GOC		 867 /* Keep irq disabled to prevent changes to the clock */
868 local_irq_save(flags);
af24a4e4 869 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 870 ktime_get_ts(&ts);
923de3cf 871 monotonic_to_bootbased(&ts);
18068523
GOC		 872 local_irq_restore(flags);
873
874 /* With all the info we got, fill in the values */
875
876 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 877 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
878
371bcf64
GC		 879 vcpu->hv_clock.flags = 0;
880
18068523
GOC		 881 /*
882 * The interface expects us to write an even number signaling that the
883 * update is finished. Since the guest won't see the intermediate
50d0a0f9 884 * state, we just increase by 2 at the end.
18068523 885 */
50d0a0f9 886 vcpu->hv_clock.version += 2;
18068523
GOC		 887
888 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
889
890 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 891 sizeof(vcpu->hv_clock));
18068523
GOC		 892
893 kunmap_atomic(shared_kaddr, KM_USER0);
894
895 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
896}
897
c8076604
GH		 898static int kvm_request_guest_time_update(struct kvm_vcpu *v)
899{
900 struct kvm_vcpu_arch *vcpu = &v->arch;
901
902 if (!vcpu->time_page)
903 return 0;
904 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
905 return 1;
906}
907
9ba075a6
AK		 908static bool msr_mtrr_valid(unsigned msr)
909{
910 switch (msr) {
911 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
912 case MSR_MTRRfix64K_00000:
913 case MSR_MTRRfix16K_80000:
914 case MSR_MTRRfix16K_A0000:
915 case MSR_MTRRfix4K_C0000:
916 case MSR_MTRRfix4K_C8000:
917 case MSR_MTRRfix4K_D0000:
918 case MSR_MTRRfix4K_D8000:
919 case MSR_MTRRfix4K_E0000:
920 case MSR_MTRRfix4K_E8000:
921 case MSR_MTRRfix4K_F0000:
922 case MSR_MTRRfix4K_F8000:
923 case MSR_MTRRdefType:
924 case MSR_IA32_CR_PAT:
925 return true;
926 case 0x2f8:
927 return true;
928 }
929 return false;
930}
931
d6289b93
MT		 932static bool valid_pat_type(unsigned t)
933{
934 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
935}
936
937static bool valid_mtrr_type(unsigned t)
938{
939 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
940}
941
942static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
943{
944 int i;
945
946 if (!msr_mtrr_valid(msr))
947 return false;
948
949 if (msr == MSR_IA32_CR_PAT) {
950 for (i = 0; i < 8; i++)
951 if (!valid_pat_type((data >> (i * 8)) & 0xff))
952 return false;
953 return true;
954 } else if (msr == MSR_MTRRdefType) {
955 if (data & ~0xcff)
956 return false;
957 return valid_mtrr_type(data & 0xff);
958 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
959 for (i = 0; i < 8 ; i++)
960 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
961 return false;
962 return true;
963 }
964
965 /* variable MTRRs */
966 return valid_mtrr_type(data & 0xff);
967}
968
9ba075a6
AK		 969static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
970{
0bed3b56
SY		 971 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
972
d6289b93 973 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 974 return 1;
975
0bed3b56
SY		 976 if (msr == MSR_MTRRdefType) {
977 vcpu->arch.mtrr_state.def_type = data;
978 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
979 } else if (msr == MSR_MTRRfix64K_00000)
980 p[0] = data;
981 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
982 p[1 + msr - MSR_MTRRfix16K_80000] = data;
983 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
984 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
985 else if (msr == MSR_IA32_CR_PAT)
986 vcpu->arch.pat = data;
987 else { /* Variable MTRRs */
988 int idx, is_mtrr_mask;
989 u64 *pt;
990
991 idx = (msr - 0x200) / 2;
992 is_mtrr_mask = msr - 0x200 - 2 * idx;
993 if (!is_mtrr_mask)
994 pt =
995 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
996 else
997 pt =
998 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
999 *pt = data;
1000 }
1001
1002 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1003 return 0;
1004}
15c4a640 1005
890ca9ae 1006static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1007{
890ca9ae
HY		 1008 u64 mcg_cap = vcpu->arch.mcg_cap;
1009 unsigned bank_num = mcg_cap & 0xff;
1010
15c4a640 1011 switch (msr) {
15c4a640 1012 case MSR_IA32_MCG_STATUS:
890ca9ae 1013 vcpu->arch.mcg_status = data;
15c4a640 1014 break;
c7ac679c 1015 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1016 if (!(mcg_cap & MCG_CTL_P))
1017 return 1;
1018 if (data != 0 && data != ~(u64)0)
1019 return -1;
1020 vcpu->arch.mcg_ctl = data;
1021 break;
1022 default:
1023 if (msr >= MSR_IA32_MC0_CTL &&
1024 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1025 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1026 /* only 0 or all 1s can be written to IA32_MCi_CTL
1027 * some Linux kernels though clear bit 10 in bank 4 to
1028 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1029 * this to avoid an uncatched #GP in the guest
1030 */
890ca9ae 1031 if ((offset & 0x3) == 0 &&
114be429 1032 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1033 return -1;
1034 vcpu->arch.mce_banks[offset] = data;
1035 break;
1036 }
1037 return 1;
1038 }
1039 return 0;
1040}
1041
ffde22ac
ES		 1042static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1043{
1044 struct kvm *kvm = vcpu->kvm;
1045 int lm = is_long_mode(vcpu);
1046 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1047 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1048 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1049 : kvm->arch.xen_hvm_config.blob_size_32;
1050 u32 page_num = data & ~PAGE_MASK;
1051 u64 page_addr = data & PAGE_MASK;
1052 u8 *page;
1053 int r;
1054
1055 r = -E2BIG;
1056 if (page_num >= blob_size)
1057 goto out;
1058 r = -ENOMEM;
1059 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1060 if (!page)
1061 goto out;
1062 r = -EFAULT;
1063 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1064 goto out_free;
1065 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1066 goto out_free;
1067 r = 0;
1068out_free:
1069 kfree(page);
1070out:
1071 return r;
1072}
1073
55cd8e5a
GN		 1074static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1075{
1076 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1077}
1078
1079static bool kvm_hv_msr_partition_wide(u32 msr)
1080{
1081 bool r = false;
1082 switch (msr) {
1083 case HV_X64_MSR_GUEST_OS_ID:
1084 case HV_X64_MSR_HYPERCALL:
1085 r = true;
1086 break;
1087 }
1088
1089 return r;
1090}
1091
1092static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1093{
1094 struct kvm *kvm = vcpu->kvm;
1095
1096 switch (msr) {
1097 case HV_X64_MSR_GUEST_OS_ID:
1098 kvm->arch.hv_guest_os_id = data;
1099 /* setting guest os id to zero disables hypercall page */
1100 if (!kvm->arch.hv_guest_os_id)
1101 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1102 break;
1103 case HV_X64_MSR_HYPERCALL: {
1104 u64 gfn;
1105 unsigned long addr;
1106 u8 instructions[4];
1107
1108 /* if guest os id is not set hypercall should remain disabled */
1109 if (!kvm->arch.hv_guest_os_id)
1110 break;
1111 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1112 kvm->arch.hv_hypercall = data;
1113 break;
1114 }
1115 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1116 addr = gfn_to_hva(kvm, gfn);
1117 if (kvm_is_error_hva(addr))
1118 return 1;
1119 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1120 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1121 if (copy_to_user((void __user *)addr, instructions, 4))
1122 return 1;
1123 kvm->arch.hv_hypercall = data;
1124 break;
1125 }
1126 default:
1127 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1128 "data 0x%llx\n", msr, data);
1129 return 1;
1130 }
1131 return 0;
1132}
1133
1134static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1135{
10388a07
GN		 1136 switch (msr) {
1137 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1138 unsigned long addr;
55cd8e5a 1139
10388a07
GN		 1140 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1141 vcpu->arch.hv_vapic = data;
1142 break;
1143 }
1144 addr = gfn_to_hva(vcpu->kvm, data >>
1145 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1146 if (kvm_is_error_hva(addr))
1147 return 1;
1148 if (clear_user((void __user *)addr, PAGE_SIZE))
1149 return 1;
1150 vcpu->arch.hv_vapic = data;
1151 break;
1152 }
1153 case HV_X64_MSR_EOI:
1154 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1155 case HV_X64_MSR_ICR:
1156 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1157 case HV_X64_MSR_TPR:
1158 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1159 default:
1160 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1161 "data 0x%llx\n", msr, data);
1162 return 1;
1163 }
1164
1165 return 0;
55cd8e5a
GN		 1166}
1167
15c4a640
CO		 1168int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1169{
1170 switch (msr) {
15c4a640 1171 case MSR_EFER:
b69e8cae 1172 return set_efer(vcpu, data);
8f1589d9
AP		 1173 case MSR_K7_HWCR:
1174 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1175 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1176 if (data != 0) {
1177 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1178 data);
1179 return 1;
1180 }
15c4a640 1181 break;
f7c6d140
AP		 1182 case MSR_FAM10H_MMIO_CONF_BASE:
1183 if (data != 0) {
1184 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1185 "0x%llx\n", data);
1186 return 1;
1187 }
15c4a640 1188 break;
c323c0e5 1189 case MSR_AMD64_NB_CFG:
c7ac679c 1190 break;
b5e2fec0
AG		 1191 case MSR_IA32_DEBUGCTLMSR:
1192 if (!data) {
1193 /* We support the non-activated case already */
1194 break;
1195 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1196 /* Values other than LBR and BTF are vendor-specific,
1197 thus reserved and should throw a #GP */
1198 return 1;
1199 }
1200 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1201 __func__, data);
1202 break;
15c4a640
CO		 1203 case MSR_IA32_UCODE_REV:
1204 case MSR_IA32_UCODE_WRITE:
61a6bd67 1205 case MSR_VM_HSAVE_PA:
6098ca93 1206 case MSR_AMD64_PATCH_LOADER:
15c4a640 1207 break;
9ba075a6
AK		 1208 case 0x200 ... 0x2ff:
1209 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1210 case MSR_IA32_APICBASE:
1211 kvm_set_apic_base(vcpu, data);
1212 break;
0105d1a5
GN		 1213 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1214 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1215 case MSR_IA32_MISC_ENABLE:
ad312c7c 1216 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1217 break;
11c6bffa 1218 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1219 case MSR_KVM_WALL_CLOCK:
1220 vcpu->kvm->arch.wall_clock = data;
1221 kvm_write_wall_clock(vcpu->kvm, data);
1222 break;
11c6bffa 1223 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1224 case MSR_KVM_SYSTEM_TIME: {
1225 if (vcpu->arch.time_page) {
1226 kvm_release_page_dirty(vcpu->arch.time_page);
1227 vcpu->arch.time_page = NULL;
1228 }
1229
1230 vcpu->arch.time = data;
1231
1232 /* we verify if the enable bit is set... */
1233 if (!(data & 1))
1234 break;
1235
1236 /* ...but clean it before doing the actual write */
1237 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1238
18068523
GOC		 1239 vcpu->arch.time_page =
1240 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1241
1242 if (is_error_page(vcpu->arch.time_page)) {
1243 kvm_release_page_clean(vcpu->arch.time_page);
1244 vcpu->arch.time_page = NULL;
1245 }
1246
c8076604 1247 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1248 break;
1249 }
890ca9ae
HY		 1250 case MSR_IA32_MCG_CTL:
1251 case MSR_IA32_MCG_STATUS:
1252 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1253 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1254
1255 /* Performance counters are not protected by a CPUID bit,
1256 * so we should check all of them in the generic path for the sake of
1257 * cross vendor migration.
1258 * Writing a zero into the event select MSRs disables them,
1259 * which we perfectly emulate ;-). Any other value should be at least
1260 * reported, some guests depend on them.
1261 */
1262 case MSR_P6_EVNTSEL0:
1263 case MSR_P6_EVNTSEL1:
1264 case MSR_K7_EVNTSEL0:
1265 case MSR_K7_EVNTSEL1:
1266 case MSR_K7_EVNTSEL2:
1267 case MSR_K7_EVNTSEL3:
1268 if (data != 0)
1269 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1270 "0x%x data 0x%llx\n", msr, data);
1271 break;
1272 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1273 * so we ignore writes to make it happy.
1274 */
1275 case MSR_P6_PERFCTR0:
1276 case MSR_P6_PERFCTR1:
1277 case MSR_K7_PERFCTR0:
1278 case MSR_K7_PERFCTR1:
1279 case MSR_K7_PERFCTR2:
1280 case MSR_K7_PERFCTR3:
1281 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1282 "0x%x data 0x%llx\n", msr, data);
1283 break;
55cd8e5a
GN		 1284 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1285 if (kvm_hv_msr_partition_wide(msr)) {
1286 int r;
1287 mutex_lock(&vcpu->kvm->lock);
1288 r = set_msr_hyperv_pw(vcpu, msr, data);
1289 mutex_unlock(&vcpu->kvm->lock);
1290 return r;
1291 } else
1292 return set_msr_hyperv(vcpu, msr, data);
1293 break;
15c4a640 1294 default:
ffde22ac
ES		 1295 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1296 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1297 if (!ignore_msrs) {
1298 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1299 msr, data);
1300 return 1;
1301 } else {
1302 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1303 msr, data);
1304 break;
1305 }
15c4a640
CO		 1306 }
1307 return 0;
1308}
1309EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1310
1311
1312/*
1313 * Reads an msr value (of 'msr_index') into 'pdata'.
1314 * Returns 0 on success, non-0 otherwise.
1315 * Assumes vcpu_load() was already called.
1316 */
1317int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1318{
1319 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1320}
1321
9ba075a6
AK		 1322static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1323{
0bed3b56
SY		 1324 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1325
9ba075a6
AK		 1326 if (!msr_mtrr_valid(msr))
1327 return 1;
1328
0bed3b56
SY		 1329 if (msr == MSR_MTRRdefType)
1330 *pdata = vcpu->arch.mtrr_state.def_type +
1331 (vcpu->arch.mtrr_state.enabled << 10);
1332 else if (msr == MSR_MTRRfix64K_00000)
1333 *pdata = p[0];
1334 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1335 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1336 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1337 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1338 else if (msr == MSR_IA32_CR_PAT)
1339 *pdata = vcpu->arch.pat;
1340 else { /* Variable MTRRs */
1341 int idx, is_mtrr_mask;
1342 u64 *pt;
1343
1344 idx = (msr - 0x200) / 2;
1345 is_mtrr_mask = msr - 0x200 - 2 * idx;
1346 if (!is_mtrr_mask)
1347 pt =
1348 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1349 else
1350 pt =
1351 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1352 *pdata = *pt;
1353 }
1354
9ba075a6
AK		 1355 return 0;
1356}
1357
890ca9ae 1358static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1359{
1360 u64 data;
890ca9ae
HY		 1361 u64 mcg_cap = vcpu->arch.mcg_cap;
1362 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1363
1364 switch (msr) {
15c4a640
CO		 1365 case MSR_IA32_P5_MC_ADDR:
1366 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1367 data = 0;
1368 break;
15c4a640 1369 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1370 data = vcpu->arch.mcg_cap;
1371 break;
c7ac679c 1372 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1373 if (!(mcg_cap & MCG_CTL_P))
1374 return 1;
1375 data = vcpu->arch.mcg_ctl;
1376 break;
1377 case MSR_IA32_MCG_STATUS:
1378 data = vcpu->arch.mcg_status;
1379 break;
1380 default:
1381 if (msr >= MSR_IA32_MC0_CTL &&
1382 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1383 u32 offset = msr - MSR_IA32_MC0_CTL;
1384 data = vcpu->arch.mce_banks[offset];
1385 break;
1386 }
1387 return 1;
1388 }
1389 *pdata = data;
1390 return 0;
1391}
1392
55cd8e5a
GN		 1393static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1394{
1395 u64 data = 0;
1396 struct kvm *kvm = vcpu->kvm;
1397
1398 switch (msr) {
1399 case HV_X64_MSR_GUEST_OS_ID:
1400 data = kvm->arch.hv_guest_os_id;
1401 break;
1402 case HV_X64_MSR_HYPERCALL:
1403 data = kvm->arch.hv_hypercall;
1404 break;
1405 default:
1406 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1407 return 1;
1408 }
1409
1410 *pdata = data;
1411 return 0;
1412}
1413
1414static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1415{
1416 u64 data = 0;
1417
1418 switch (msr) {
1419 case HV_X64_MSR_VP_INDEX: {
1420 int r;
1421 struct kvm_vcpu *v;
1422 kvm_for_each_vcpu(r, v, vcpu->kvm)
1423 if (v == vcpu)
1424 data = r;
1425 break;
1426 }
10388a07
GN		 1427 case HV_X64_MSR_EOI:
1428 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1429 case HV_X64_MSR_ICR:
1430 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1431 case HV_X64_MSR_TPR:
1432 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1433 default:
1434 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1435 return 1;
1436 }
1437 *pdata = data;
1438 return 0;
1439}
1440
890ca9ae
HY		 1441int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1442{
1443 u64 data;
1444
1445 switch (msr) {
890ca9ae 1446 case MSR_IA32_PLATFORM_ID:
15c4a640 1447 case MSR_IA32_UCODE_REV:
15c4a640 1448 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1449 case MSR_IA32_DEBUGCTLMSR:
1450 case MSR_IA32_LASTBRANCHFROMIP:
1451 case MSR_IA32_LASTBRANCHTOIP:
1452 case MSR_IA32_LASTINTFROMIP:
1453 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1454 case MSR_K8_SYSCFG:
1455 case MSR_K7_HWCR:
61a6bd67 1456 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1457 case MSR_P6_PERFCTR0:
1458 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1459 case MSR_P6_EVNTSEL0:
1460 case MSR_P6_EVNTSEL1:
9e699624 1461 case MSR_K7_EVNTSEL0:
1f3ee616 1462 case MSR_K7_PERFCTR0:
1fdbd48c 1463 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1464 case MSR_AMD64_NB_CFG:
f7c6d140 1465 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1466 data = 0;
1467 break;
9ba075a6
AK		 1468 case MSR_MTRRcap:
1469 data = 0x500 | KVM_NR_VAR_MTRR;
1470 break;
1471 case 0x200 ... 0x2ff:
1472 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1473 case 0xcd: /* fsb frequency */
1474 data = 3;
1475 break;
1476 case MSR_IA32_APICBASE:
1477 data = kvm_get_apic_base(vcpu);
1478 break;
0105d1a5
GN		 1479 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1480 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1481 break;
15c4a640 1482 case MSR_IA32_MISC_ENABLE:
ad312c7c 1483 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1484 break;
847f0ad8
AG		 1485 case MSR_IA32_PERF_STATUS:
1486 /* TSC increment by tick */
1487 data = 1000ULL;
1488 /* CPU multiplier */
1489 data |= (((uint64_t)4ULL) << 40);
1490 break;
15c4a640 1491 case MSR_EFER:
f6801dff 1492 data = vcpu->arch.efer;
15c4a640 1493 break;
18068523 1494 case MSR_KVM_WALL_CLOCK:
11c6bffa 1495 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1496 data = vcpu->kvm->arch.wall_clock;
1497 break;
1498 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1499 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1500 data = vcpu->arch.time;
1501 break;
890ca9ae
HY		 1502 case MSR_IA32_P5_MC_ADDR:
1503 case MSR_IA32_P5_MC_TYPE:
1504 case MSR_IA32_MCG_CAP:
1505 case MSR_IA32_MCG_CTL:
1506 case MSR_IA32_MCG_STATUS:
1507 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1508 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1509 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1510 if (kvm_hv_msr_partition_wide(msr)) {
1511 int r;
1512 mutex_lock(&vcpu->kvm->lock);
1513 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1514 mutex_unlock(&vcpu->kvm->lock);
1515 return r;
1516 } else
1517 return get_msr_hyperv(vcpu, msr, pdata);
1518 break;
15c4a640 1519 default:
ed85c068
AP		 1520 if (!ignore_msrs) {
1521 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1522 return 1;
1523 } else {
1524 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1525 data = 0;
1526 }
1527 break;
15c4a640
CO		 1528 }
1529 *pdata = data;
1530 return 0;
1531}
1532EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1533
313a3dc7
CO		 1534/*
1535 * Read or write a bunch of msrs. All parameters are kernel addresses.
1536 *
1537 * @return number of msrs set successfully.
1538 */
1539static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1540 struct kvm_msr_entry *entries,
1541 int (*do_msr)(struct kvm_vcpu *vcpu,
1542 unsigned index, u64 *data))
1543{
f656ce01 1544 int i, idx;
313a3dc7 1545
f656ce01 1546 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1547 for (i = 0; i < msrs->nmsrs; ++i)
1548 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1549 break;
f656ce01 1550 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1551
313a3dc7
CO		 1552 return i;
1553}
1554
1555/*
1556 * Read or write a bunch of msrs. Parameters are user addresses.
1557 *
1558 * @return number of msrs set successfully.
1559 */
1560static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1561 int (*do_msr)(struct kvm_vcpu *vcpu,
1562 unsigned index, u64 *data),
1563 int writeback)
1564{
1565 struct kvm_msrs msrs;
1566 struct kvm_msr_entry *entries;
1567 int r, n;
1568 unsigned size;
1569
1570 r = -EFAULT;
1571 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1572 goto out;
1573
1574 r = -E2BIG;
1575 if (msrs.nmsrs >= MAX_IO_MSRS)
1576 goto out;
1577
1578 r = -ENOMEM;
1579 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1580 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1581 if (!entries)
1582 goto out;
1583
1584 r = -EFAULT;
1585 if (copy_from_user(entries, user_msrs->entries, size))
1586 goto out_free;
1587
1588 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1589 if (r < 0)
1590 goto out_free;
1591
1592 r = -EFAULT;
1593 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1594 goto out_free;
1595
1596 r = n;
1597
1598out_free:
7a73c028 1599 kfree(entries);
313a3dc7
CO		 1600out:
1601 return r;
1602}
1603
018d00d2
ZX		 1604int kvm_dev_ioctl_check_extension(long ext)
1605{
1606 int r;
1607
1608 switch (ext) {
1609 case KVM_CAP_IRQCHIP:
1610 case KVM_CAP_HLT:
1611 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1612 case KVM_CAP_SET_TSS_ADDR:
07716717 1613 case KVM_CAP_EXT_CPUID:
c8076604 1614 case KVM_CAP_CLOCKSOURCE:
7837699f 1615 case KVM_CAP_PIT:
a28e4f5a 1616 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1617 case KVM_CAP_MP_STATE:
ed848624 1618 case KVM_CAP_SYNC_MMU:
52d939a0 1619 case KVM_CAP_REINJECT_CONTROL:
4925663a 1620 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1621 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1622 case KVM_CAP_IRQFD:
d34e6b17 1623 case KVM_CAP_IOEVENTFD:
c5ff41ce 1624 case KVM_CAP_PIT2:
e9f42757 1625 case KVM_CAP_PIT_STATE2:
b927a3ce 1626 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1627 case KVM_CAP_XEN_HVM:
afbcf7ab 1628 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1629 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1630 case KVM_CAP_HYPERV:
10388a07 1631 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1632 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1633 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1634 case KVM_CAP_DEBUGREGS:
d2be1651 1635 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1636 r = 1;
1637 break;
542472b5
LV		 1638 case KVM_CAP_COALESCED_MMIO:
1639 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1640 break;
774ead3a
AK		 1641 case KVM_CAP_VAPIC:
1642 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1643 break;
f725230a
AK		 1644 case KVM_CAP_NR_VCPUS:
1645 r = KVM_MAX_VCPUS;
1646 break;
a988b910
AK		 1647 case KVM_CAP_NR_MEMSLOTS:
1648 r = KVM_MEMORY_SLOTS;
1649 break;
a68a6a72
MT		 1650 case KVM_CAP_PV_MMU: /* obsolete */
1651 r = 0;
2f333bcb 1652 break;
62c476c7 1653 case KVM_CAP_IOMMU:
19de40a8 1654 r = iommu_found();
62c476c7 1655 break;
890ca9ae
HY		 1656 case KVM_CAP_MCE:
1657 r = KVM_MAX_MCE_BANKS;
1658 break;
018d00d2
ZX		 1659 default:
1660 r = 0;
1661 break;
1662 }
1663 return r;
1664
1665}
1666
043405e1
CO		 1667long kvm_arch_dev_ioctl(struct file *filp,
1668 unsigned int ioctl, unsigned long arg)
1669{
1670 void __user *argp = (void __user *)arg;
1671 long r;
1672
1673 switch (ioctl) {
1674 case KVM_GET_MSR_INDEX_LIST: {
1675 struct kvm_msr_list __user *user_msr_list = argp;
1676 struct kvm_msr_list msr_list;
1677 unsigned n;
1678
1679 r = -EFAULT;
1680 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1681 goto out;
1682 n = msr_list.nmsrs;
1683 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1684 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1685 goto out;
1686 r = -E2BIG;
e125e7b6 1687 if (n < msr_list.nmsrs)
043405e1
CO		 1688 goto out;
1689 r = -EFAULT;
1690 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1691 num_msrs_to_save * sizeof(u32)))
1692 goto out;
e125e7b6 1693 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1694 &emulated_msrs,
1695 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1696 goto out;
1697 r = 0;
1698 break;
1699 }
674eea0f
AK		 1700 case KVM_GET_SUPPORTED_CPUID: {
1701 struct kvm_cpuid2 __user *cpuid_arg = argp;
1702 struct kvm_cpuid2 cpuid;
1703
1704 r = -EFAULT;
1705 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1706 goto out;
1707 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1708 cpuid_arg->entries);
674eea0f
AK		 1709 if (r)
1710 goto out;
1711
1712 r = -EFAULT;
1713 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1714 goto out;
1715 r = 0;
1716 break;
1717 }
890ca9ae
HY		 1718 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1719 u64 mce_cap;
1720
1721 mce_cap = KVM_MCE_CAP_SUPPORTED;
1722 r = -EFAULT;
1723 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1724 goto out;
1725 r = 0;
1726 break;
1727 }
043405e1
CO		 1728 default:
1729 r = -EINVAL;
1730 }
1731out:
1732 return r;
1733}
1734
313a3dc7
CO		 1735void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1736{
1737 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1738 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1739 unsigned long khz = cpufreq_quick_get(cpu);
1740 if (!khz)
1741 khz = tsc_khz;
1742 per_cpu(cpu_tsc_khz, cpu) = khz;
1743 }
c8076604 1744 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1745}
1746
1747void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1748{
02daab21 1749 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 1750 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1751}
1752
07716717 1753static int is_efer_nx(void)
313a3dc7 1754{
e286e86e 1755 unsigned long long efer = 0;
313a3dc7 1756
e286e86e 1757 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1758 return efer & EFER_NX;
1759}
1760
1761static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1762{
1763 int i;
1764 struct kvm_cpuid_entry2 *e, *entry;
1765
313a3dc7 1766 entry = NULL;
ad312c7c
ZX		 1767 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1768 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1769 if (e->function == 0x80000001) {
1770 entry = e;
1771 break;
1772 }
1773 }
07716717 1774 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1775 entry->edx &= ~(1 << 20);
1776 printk(KERN_INFO "kvm: guest NX capability removed\n");
1777 }
1778}
1779
07716717 1780/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1781static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1782 struct kvm_cpuid *cpuid,
1783 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1784{
1785 int r, i;
1786 struct kvm_cpuid_entry *cpuid_entries;
1787
1788 r = -E2BIG;
1789 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1790 goto out;
1791 r = -ENOMEM;
1792 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1793 if (!cpuid_entries)
1794 goto out;
1795 r = -EFAULT;
1796 if (copy_from_user(cpuid_entries, entries,
1797 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1798 goto out_free;
1799 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1800 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1801 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1802 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1803 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1804 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1805 vcpu->arch.cpuid_entries[i].index = 0;
1806 vcpu->arch.cpuid_entries[i].flags = 0;
1807 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1808 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1809 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1810 }
1811 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1812 cpuid_fix_nx_cap(vcpu);
1813 r = 0;
fc61b800 1814 kvm_apic_set_version(vcpu);
0e851880 1815 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1816
1817out_free:
1818 vfree(cpuid_entries);
1819out:
1820 return r;
1821}
1822
1823static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1824 struct kvm_cpuid2 *cpuid,
1825 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1826{
1827 int r;
1828
1829 r = -E2BIG;
1830 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1831 goto out;
1832 r = -EFAULT;
ad312c7c 1833 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1834 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1835 goto out;
ad312c7c 1836 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1837 kvm_apic_set_version(vcpu);
0e851880 1838 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1839 return 0;
1840
1841out:
1842 return r;
1843}
1844
07716717 1845static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1846 struct kvm_cpuid2 *cpuid,
1847 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1848{
1849 int r;
1850
1851 r = -E2BIG;
ad312c7c 1852 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1853 goto out;
1854 r = -EFAULT;
ad312c7c 1855 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1856 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1857 goto out;
1858 return 0;
1859
1860out:
ad312c7c 1861 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1862 return r;
1863}
1864
07716717 1865static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1866 u32 index)
07716717
DK		 1867{
1868 entry->function = function;
1869 entry->index = index;
1870 cpuid_count(entry->function, entry->index,
19355475 1871 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1872 entry->flags = 0;
1873}
1874
7faa4ee1
AK		 1875#define F(x) bit(X86_FEATURE_##x)
1876
07716717
DK		 1877static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1878 u32 index, int *nent, int maxnent)
1879{
7faa4ee1 1880 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1881#ifdef CONFIG_X86_64
17cc3935
SY		 1882 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1883 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1884 unsigned f_lm = F(LM);
1885#else
17cc3935 1886 unsigned f_gbpages = 0;
7faa4ee1 1887 unsigned f_lm = 0;
07716717 1888#endif
4e47c7a6 1889 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1890
1891 /* cpuid 1.edx */
1892 const u32 kvm_supported_word0_x86_features =
1893 F(FPU) | F(VME) | F(DE) | F(PSE) |
1894 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1895 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1896 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1897 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1898 0 /* Reserved, DS, ACPI */ | F(MMX) |
1899 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1900 0 /* HTT, TM, Reserved, PBE */;
1901 /* cpuid 0x80000001.edx */
1902 const u32 kvm_supported_word1_x86_features =
1903 F(FPU) | F(VME) | F(DE) | F(PSE) |
1904 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1905 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1906 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1907 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1908 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1909 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1910 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1911 /* cpuid 1.ecx */
1912 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1913 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1914 0 /* DS-CPL, VMX, SMX, EST */ |
1915 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1916 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1917 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1918 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1919 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1920 /* cpuid 0x80000001.ecx */
07716717 1921 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1922 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1923 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1924 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1925 0 /* SKINIT */ | 0 /* WDT */;
07716717 1926
19355475 1927 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1928 get_cpu();
1929 do_cpuid_1_ent(entry, function, index);
1930 ++*nent;
1931
1932 switch (function) {
1933 case 0:
1934 entry->eax = min(entry->eax, (u32)0xb);
1935 break;
1936 case 1:
1937 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1938 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1939 /* we support x2apic emulation even if host does not support
1940 * it since we emulate x2apic in software */
1941 entry->ecx |= F(X2APIC);
07716717
DK		 1942 break;
1943 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1944 * may return different values. This forces us to get_cpu() before
1945 * issuing the first command, and also to emulate this annoying behavior
1946 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1947 case 2: {
1948 int t, times = entry->eax & 0xff;
1949
1950 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1951 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1952 for (t = 1; t < times && *nent < maxnent; ++t) {
1953 do_cpuid_1_ent(&entry[t], function, 0);
1954 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1955 ++*nent;
1956 }
1957 break;
1958 }
1959 /* function 4 and 0xb have additional index. */
1960 case 4: {
14af3f3c 1961 int i, cache_type;
07716717
DK		 1962
1963 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1964 /* read more entries until cache_type is zero */
14af3f3c
HH		 1965 for (i = 1; *nent < maxnent; ++i) {
1966 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1967 if (!cache_type)
1968 break;
14af3f3c
HH		 1969 do_cpuid_1_ent(&entry[i], function, i);
1970 entry[i].flags |=
07716717
DK		 1971 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1972 ++*nent;
1973 }
1974 break;
1975 }
1976 case 0xb: {
14af3f3c 1977 int i, level_type;
07716717
DK		 1978
1979 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1980 /* read more entries until level_type is zero */
14af3f3c 1981 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1982 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1983 if (!level_type)
1984 break;
14af3f3c
HH		 1985 do_cpuid_1_ent(&entry[i], function, i);
1986 entry[i].flags |=
07716717
DK		 1987 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1988 ++*nent;
1989 }
1990 break;
1991 }
84478c82
GC		 1992 case KVM_CPUID_SIGNATURE: {
1993 char signature[12] = "KVMKVMKVM\0\0";
1994 u32 *sigptr = (u32 *)signature;
1995 entry->eax = 0;
1996 entry->ebx = sigptr[0];
1997 entry->ecx = sigptr[1];
1998 entry->edx = sigptr[2];
1999 break;
2000 }
2001 case KVM_CPUID_FEATURES:
2002 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2003 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2004 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2005 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2006 entry->ebx = 0;
2007 entry->ecx = 0;
2008 entry->edx = 0;
2009 break;
07716717
DK		 2010 case 0x80000000:
2011 entry->eax = min(entry->eax, 0x8000001a);
2012 break;
2013 case 0x80000001:
2014 entry->edx &= kvm_supported_word1_x86_features;
2015 entry->ecx &= kvm_supported_word6_x86_features;
2016 break;
2017 }
d4330ef2
JR		 2018
2019 kvm_x86_ops->set_supported_cpuid(function, entry);
2020
07716717
DK		 2021 put_cpu();
2022}
2023
7faa4ee1
AK		 2024#undef F
2025
674eea0f 2026static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2027 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2028{
2029 struct kvm_cpuid_entry2 *cpuid_entries;
2030 int limit, nent = 0, r = -E2BIG;
2031 u32 func;
2032
2033 if (cpuid->nent < 1)
2034 goto out;
6a544355
AK		 2035 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2036 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2037 r = -ENOMEM;
2038 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2039 if (!cpuid_entries)
2040 goto out;
2041
2042 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2043 limit = cpuid_entries[0].eax;
2044 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2045 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2046 &nent, cpuid->nent);
07716717
DK		 2047 r = -E2BIG;
2048 if (nent >= cpuid->nent)
2049 goto out_free;
2050
2051 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2052 limit = cpuid_entries[nent - 1].eax;
2053 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2054 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2055 &nent, cpuid->nent);
84478c82
GC		 2056
2057
2058
2059 r = -E2BIG;
2060 if (nent >= cpuid->nent)
2061 goto out_free;
2062
2063 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2064 cpuid->nent);
2065
2066 r = -E2BIG;
2067 if (nent >= cpuid->nent)
2068 goto out_free;
2069
2070 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2071 cpuid->nent);
2072
cb007648
MM		 2073 r = -E2BIG;
2074 if (nent >= cpuid->nent)
2075 goto out_free;
2076
07716717
DK		 2077 r = -EFAULT;
2078 if (copy_to_user(entries, cpuid_entries,
19355475 2079 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2080 goto out_free;
2081 cpuid->nent = nent;
2082 r = 0;
2083
2084out_free:
2085 vfree(cpuid_entries);
2086out:
2087 return r;
2088}
2089
313a3dc7
CO		 2090static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2091 struct kvm_lapic_state *s)
2092{
ad312c7c 2093 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2094
2095 return 0;
2096}
2097
2098static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2099 struct kvm_lapic_state *s)
2100{
ad312c7c 2101 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2102 kvm_apic_post_state_restore(vcpu);
cb142eb7 2103 update_cr8_intercept(vcpu);
313a3dc7
CO		 2104
2105 return 0;
2106}
2107
f77bc6a4
ZX		 2108static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2109 struct kvm_interrupt *irq)
2110{
2111 if (irq->irq < 0 || irq->irq >= 256)
2112 return -EINVAL;
2113 if (irqchip_in_kernel(vcpu->kvm))
2114 return -ENXIO;
f77bc6a4 2115
66fd3f7f 2116 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4 2117
f77bc6a4
ZX		 2118 return 0;
2119}
2120
c4abb7c9
JK		 2121static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2122{
c4abb7c9 2123 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2124
2125 return 0;
2126}
2127
b209749f
AK		 2128static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2129 struct kvm_tpr_access_ctl *tac)
2130{
2131 if (tac->flags)
2132 return -EINVAL;
2133 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2134 return 0;
2135}
2136
890ca9ae
HY		 2137static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2138 u64 mcg_cap)
2139{
2140 int r;
2141 unsigned bank_num = mcg_cap & 0xff, bank;
2142
2143 r = -EINVAL;
a9e38c3e 2144 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2145 goto out;
2146 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2147 goto out;
2148 r = 0;
2149 vcpu->arch.mcg_cap = mcg_cap;
2150 /* Init IA32_MCG_CTL to all 1s */
2151 if (mcg_cap & MCG_CTL_P)
2152 vcpu->arch.mcg_ctl = ~(u64)0;
2153 /* Init IA32_MCi_CTL to all 1s */
2154 for (bank = 0; bank < bank_num; bank++)
2155 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2156out:
2157 return r;
2158}
2159
2160static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2161 struct kvm_x86_mce *mce)
2162{
2163 u64 mcg_cap = vcpu->arch.mcg_cap;
2164 unsigned bank_num = mcg_cap & 0xff;
2165 u64 *banks = vcpu->arch.mce_banks;
2166
2167 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2168 return -EINVAL;
2169 /*
2170 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2171 * reporting is disabled
2172 */
2173 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2174 vcpu->arch.mcg_ctl != ~(u64)0)
2175 return 0;
2176 banks += 4 * mce->bank;
2177 /*
2178 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2179 * reporting is disabled for the bank
2180 */
2181 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2182 return 0;
2183 if (mce->status & MCI_STATUS_UC) {
2184 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2185 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2186 printk(KERN_DEBUG "kvm: set_mce: "
2187 "injects mce exception while "
2188 "previous one is in progress!\n");
2189 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2190 return 0;
2191 }
2192 if (banks[1] & MCI_STATUS_VAL)
2193 mce->status |= MCI_STATUS_OVER;
2194 banks[2] = mce->addr;
2195 banks[3] = mce->misc;
2196 vcpu->arch.mcg_status = mce->mcg_status;
2197 banks[1] = mce->status;
2198 kvm_queue_exception(vcpu, MC_VECTOR);
2199 } else if (!(banks[1] & MCI_STATUS_VAL)
2200 || !(banks[1] & MCI_STATUS_UC)) {
2201 if (banks[1] & MCI_STATUS_VAL)
2202 mce->status |= MCI_STATUS_OVER;
2203 banks[2] = mce->addr;
2204 banks[3] = mce->misc;
2205 banks[1] = mce->status;
2206 } else
2207 banks[1] |= MCI_STATUS_OVER;
2208 return 0;
2209}
2210
3cfc3092
JK		 2211static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2212 struct kvm_vcpu_events *events)
2213{
03b82a30
JK		 2214 events->exception.injected =
2215 vcpu->arch.exception.pending &&
2216 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2217 events->exception.nr = vcpu->arch.exception.nr;
2218 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2219 events->exception.error_code = vcpu->arch.exception.error_code;
2220
03b82a30
JK		 2221 events->interrupt.injected =
2222 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2223 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2224 events->interrupt.soft = 0;
48005f64
JK		 2225 events->interrupt.shadow =
2226 kvm_x86_ops->get_interrupt_shadow(vcpu,
2227 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2228
2229 events->nmi.injected = vcpu->arch.nmi_injected;
2230 events->nmi.pending = vcpu->arch.nmi_pending;
2231 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2232
2233 events->sipi_vector = vcpu->arch.sipi_vector;
2234
dab4b911 2235 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2236 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2237 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2238}
2239
2240static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2241 struct kvm_vcpu_events *events)
2242{
dab4b911 2243 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2244 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2245 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2246 return -EINVAL;
2247
3cfc3092
JK		 2248 vcpu->arch.exception.pending = events->exception.injected;
2249 vcpu->arch.exception.nr = events->exception.nr;
2250 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2251 vcpu->arch.exception.error_code = events->exception.error_code;
2252
2253 vcpu->arch.interrupt.pending = events->interrupt.injected;
2254 vcpu->arch.interrupt.nr = events->interrupt.nr;
2255 vcpu->arch.interrupt.soft = events->interrupt.soft;
2256 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2257 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2258 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2259 kvm_x86_ops->set_interrupt_shadow(vcpu,
2260 events->interrupt.shadow);
3cfc3092
JK		 2261
2262 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2263 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2264 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2265 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2266
dab4b911
JK		 2267 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2268 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2269
3cfc3092
JK		 2270 return 0;
2271}
2272
a1efbe77
JK		 2273static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2274 struct kvm_debugregs *dbgregs)
2275{
a1efbe77
JK		 2276 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2277 dbgregs->dr6 = vcpu->arch.dr6;
2278 dbgregs->dr7 = vcpu->arch.dr7;
2279 dbgregs->flags = 0;
a1efbe77
JK		 2280}
2281
2282static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2283 struct kvm_debugregs *dbgregs)
2284{
2285 if (dbgregs->flags)
2286 return -EINVAL;
2287
a1efbe77
JK		 2288 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2289 vcpu->arch.dr6 = dbgregs->dr6;
2290 vcpu->arch.dr7 = dbgregs->dr7;
2291
a1efbe77
JK		 2292 return 0;
2293}
2294
313a3dc7
CO		 2295long kvm_arch_vcpu_ioctl(struct file *filp,
2296 unsigned int ioctl, unsigned long arg)
2297{
2298 struct kvm_vcpu *vcpu = filp->private_data;
2299 void __user *argp = (void __user *)arg;
2300 int r;
b772ff36 2301 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2302
2303 switch (ioctl) {
2304 case KVM_GET_LAPIC: {
2204ae3c
MT		 2305 r = -EINVAL;
2306 if (!vcpu->arch.apic)
2307 goto out;
b772ff36 2308 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2309
b772ff36
DH		 2310 r = -ENOMEM;
2311 if (!lapic)
2312 goto out;
2313 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2314 if (r)
2315 goto out;
2316 r = -EFAULT;
b772ff36 2317 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2318 goto out;
2319 r = 0;
2320 break;
2321 }
2322 case KVM_SET_LAPIC: {
2204ae3c
MT		 2323 r = -EINVAL;
2324 if (!vcpu->arch.apic)
2325 goto out;
b772ff36
DH		 2326 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2327 r = -ENOMEM;
2328 if (!lapic)
2329 goto out;
313a3dc7 2330 r = -EFAULT;
b772ff36 2331 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2332 goto out;
b772ff36 2333 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2334 if (r)
2335 goto out;
2336 r = 0;
2337 break;
2338 }
f77bc6a4
ZX		 2339 case KVM_INTERRUPT: {
2340 struct kvm_interrupt irq;
2341
2342 r = -EFAULT;
2343 if (copy_from_user(&irq, argp, sizeof irq))
2344 goto out;
2345 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2346 if (r)
2347 goto out;
2348 r = 0;
2349 break;
2350 }
c4abb7c9
JK		 2351 case KVM_NMI: {
2352 r = kvm_vcpu_ioctl_nmi(vcpu);
2353 if (r)
2354 goto out;
2355 r = 0;
2356 break;
2357 }
313a3dc7
CO		 2358 case KVM_SET_CPUID: {
2359 struct kvm_cpuid __user *cpuid_arg = argp;
2360 struct kvm_cpuid cpuid;
2361
2362 r = -EFAULT;
2363 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2364 goto out;
2365 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2366 if (r)
2367 goto out;
2368 break;
2369 }
07716717
DK		 2370 case KVM_SET_CPUID2: {
2371 struct kvm_cpuid2 __user *cpuid_arg = argp;
2372 struct kvm_cpuid2 cpuid;
2373
2374 r = -EFAULT;
2375 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2376 goto out;
2377 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2378 cpuid_arg->entries);
07716717
DK		 2379 if (r)
2380 goto out;
2381 break;
2382 }
2383 case KVM_GET_CPUID2: {
2384 struct kvm_cpuid2 __user *cpuid_arg = argp;
2385 struct kvm_cpuid2 cpuid;
2386
2387 r = -EFAULT;
2388 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2389 goto out;
2390 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2391 cpuid_arg->entries);
07716717
DK		 2392 if (r)
2393 goto out;
2394 r = -EFAULT;
2395 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2396 goto out;
2397 r = 0;
2398 break;
2399 }
313a3dc7
CO		 2400 case KVM_GET_MSRS:
2401 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2402 break;
2403 case KVM_SET_MSRS:
2404 r = msr_io(vcpu, argp, do_set_msr, 0);
2405 break;
b209749f
AK		 2406 case KVM_TPR_ACCESS_REPORTING: {
2407 struct kvm_tpr_access_ctl tac;
2408
2409 r = -EFAULT;
2410 if (copy_from_user(&tac, argp, sizeof tac))
2411 goto out;
2412 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2413 if (r)
2414 goto out;
2415 r = -EFAULT;
2416 if (copy_to_user(argp, &tac, sizeof tac))
2417 goto out;
2418 r = 0;
2419 break;
2420 };
b93463aa
AK		 2421 case KVM_SET_VAPIC_ADDR: {
2422 struct kvm_vapic_addr va;
2423
2424 r = -EINVAL;
2425 if (!irqchip_in_kernel(vcpu->kvm))
2426 goto out;
2427 r = -EFAULT;
2428 if (copy_from_user(&va, argp, sizeof va))
2429 goto out;
2430 r = 0;
2431 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2432 break;
2433 }
890ca9ae
HY		 2434 case KVM_X86_SETUP_MCE: {
2435 u64 mcg_cap;
2436
2437 r = -EFAULT;
2438 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2439 goto out;
2440 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2441 break;
2442 }
2443 case KVM_X86_SET_MCE: {
2444 struct kvm_x86_mce mce;
2445
2446 r = -EFAULT;
2447 if (copy_from_user(&mce, argp, sizeof mce))
2448 goto out;
2449 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2450 break;
2451 }
3cfc3092
JK		 2452 case KVM_GET_VCPU_EVENTS: {
2453 struct kvm_vcpu_events events;
2454
2455 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2456
2457 r = -EFAULT;
2458 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2459 break;
2460 r = 0;
2461 break;
2462 }
2463 case KVM_SET_VCPU_EVENTS: {
2464 struct kvm_vcpu_events events;
2465
2466 r = -EFAULT;
2467 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2468 break;
2469
2470 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2471 break;
2472 }
a1efbe77
JK		 2473 case KVM_GET_DEBUGREGS: {
2474 struct kvm_debugregs dbgregs;
2475
2476 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2477
2478 r = -EFAULT;
2479 if (copy_to_user(argp, &dbgregs,
2480 sizeof(struct kvm_debugregs)))
2481 break;
2482 r = 0;
2483 break;
2484 }
2485 case KVM_SET_DEBUGREGS: {
2486 struct kvm_debugregs dbgregs;
2487
2488 r = -EFAULT;
2489 if (copy_from_user(&dbgregs, argp,
2490 sizeof(struct kvm_debugregs)))
2491 break;
2492
2493 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2494 break;
2495 }
313a3dc7
CO		 2496 default:
2497 r = -EINVAL;
2498 }
2499out:
7a6ce84c 2500 kfree(lapic);
313a3dc7
CO		 2501 return r;
2502}
2503
1fe779f8
CO		 2504static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2505{
2506 int ret;
2507
2508 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2509 return -1;
2510 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2511 return ret;
2512}
2513
b927a3ce
SY		 2514static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2515 u64 ident_addr)
2516{
2517 kvm->arch.ept_identity_map_addr = ident_addr;
2518 return 0;
2519}
2520
1fe779f8
CO		 2521static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2522 u32 kvm_nr_mmu_pages)
2523{
2524 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2525 return -EINVAL;
2526
79fac95e 2527 mutex_lock(&kvm->slots_lock);
7c8a83b7 2528 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2529
2530 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2531 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2532
7c8a83b7 2533 spin_unlock(&kvm->mmu_lock);
79fac95e 2534 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2535 return 0;
2536}
2537
2538static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2539{
f05e70ac 2540 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2541}
2542
a983fb23
MT		 2543gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2544{
2545 int i;
2546 struct kvm_mem_alias *alias;
2547 struct kvm_mem_aliases *aliases;
2548
90d83dc3 2549 aliases = kvm_aliases(kvm);
a983fb23
MT		 2550
2551 for (i = 0; i < aliases->naliases; ++i) {
2552 alias = &aliases->aliases[i];
2553 if (alias->flags & KVM_ALIAS_INVALID)
2554 continue;
2555 if (gfn >= alias->base_gfn
2556 && gfn < alias->base_gfn + alias->npages)
2557 return alias->target_gfn + gfn - alias->base_gfn;
2558 }
2559 return gfn;
2560}
2561
e9f85cde
ZX		 2562gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2563{
2564 int i;
2565 struct kvm_mem_alias *alias;
a983fb23
MT		 2566 struct kvm_mem_aliases *aliases;
2567
90d83dc3 2568 aliases = kvm_aliases(kvm);
e9f85cde 2569
fef9cce0
MT		 2570 for (i = 0; i < aliases->naliases; ++i) {
2571 alias = &aliases->aliases[i];
e9f85cde
ZX		 2572 if (gfn >= alias->base_gfn
2573 && gfn < alias->base_gfn + alias->npages)
2574 return alias->target_gfn + gfn - alias->base_gfn;
2575 }
2576 return gfn;
2577}
2578
1fe779f8
CO		 2579/*
2580 * Set a new alias region. Aliases map a portion of physical memory into
2581 * another portion. This is useful for memory windows, for example the PC
2582 * VGA region.
2583 */
2584static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2585 struct kvm_memory_alias *alias)
2586{
2587 int r, n;
2588 struct kvm_mem_alias *p;
a983fb23 2589 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2590
2591 r = -EINVAL;
2592 /* General sanity checks */
2593 if (alias->memory_size & (PAGE_SIZE - 1))
2594 goto out;
2595 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2596 goto out;
2597 if (alias->slot >= KVM_ALIAS_SLOTS)
2598 goto out;
2599 if (alias->guest_phys_addr + alias->memory_size
2600 < alias->guest_phys_addr)
2601 goto out;
2602 if (alias->target_phys_addr + alias->memory_size
2603 < alias->target_phys_addr)
2604 goto out;
2605
a983fb23
MT		 2606 r = -ENOMEM;
2607 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2608 if (!aliases)
2609 goto out;
2610
79fac95e 2611 mutex_lock(&kvm->slots_lock);
1fe779f8 2612
a983fb23
MT		 2613 /* invalidate any gfn reference in case of deletion/shrinking */
2614 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2615 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2616 old_aliases = kvm->arch.aliases;
2617 rcu_assign_pointer(kvm->arch.aliases, aliases);
2618 synchronize_srcu_expedited(&kvm->srcu);
2619 kvm_mmu_zap_all(kvm);
2620 kfree(old_aliases);
2621
2622 r = -ENOMEM;
2623 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2624 if (!aliases)
2625 goto out_unlock;
2626
2627 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2628
2629 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2630 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2631 p->npages = alias->memory_size >> PAGE_SHIFT;
2632 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2633 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2634
2635 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2636 if (aliases->aliases[n - 1].npages)
1fe779f8 2637 break;
fef9cce0 2638 aliases->naliases = n;
1fe779f8 2639
a983fb23
MT		 2640 old_aliases = kvm->arch.aliases;
2641 rcu_assign_pointer(kvm->arch.aliases, aliases);
2642 synchronize_srcu_expedited(&kvm->srcu);
2643 kfree(old_aliases);
2644 r = 0;
1fe779f8 2645
a983fb23 2646out_unlock:
79fac95e 2647 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2648out:
2649 return r;
2650}
2651
2652static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2653{
2654 int r;
2655
2656 r = 0;
2657 switch (chip->chip_id) {
2658 case KVM_IRQCHIP_PIC_MASTER:
2659 memcpy(&chip->chip.pic,
2660 &pic_irqchip(kvm)->pics[0],
2661 sizeof(struct kvm_pic_state));
2662 break;
2663 case KVM_IRQCHIP_PIC_SLAVE:
2664 memcpy(&chip->chip.pic,
2665 &pic_irqchip(kvm)->pics[1],
2666 sizeof(struct kvm_pic_state));
2667 break;
2668 case KVM_IRQCHIP_IOAPIC:
eba0226b 2669 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2670 break;
2671 default:
2672 r = -EINVAL;
2673 break;
2674 }
2675 return r;
2676}
2677
2678static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2679{
2680 int r;
2681
2682 r = 0;
2683 switch (chip->chip_id) {
2684 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2685 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2686 memcpy(&pic_irqchip(kvm)->pics[0],
2687 &chip->chip.pic,
2688 sizeof(struct kvm_pic_state));
fa8273e9 2689 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2690 break;
2691 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2692 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2693 memcpy(&pic_irqchip(kvm)->pics[1],
2694 &chip->chip.pic,
2695 sizeof(struct kvm_pic_state));
fa8273e9 2696 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2697 break;
2698 case KVM_IRQCHIP_IOAPIC:
eba0226b 2699 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2700 break;
2701 default:
2702 r = -EINVAL;
2703 break;
2704 }
2705 kvm_pic_update_irq(pic_irqchip(kvm));
2706 return r;
2707}
2708
e0f63cb9
SY		 2709static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2710{
2711 int r = 0;
2712
894a9c55 2713 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2714 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2715 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2716 return r;
2717}
2718
2719static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2720{
2721 int r = 0;
2722
894a9c55 2723 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2724 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2725 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2726 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2727 return r;
2728}
2729
2730static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2731{
2732 int r = 0;
2733
2734 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2735 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2736 sizeof(ps->channels));
2737 ps->flags = kvm->arch.vpit->pit_state.flags;
2738 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2739 return r;
2740}
2741
2742static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2743{
2744 int r = 0, start = 0;
2745 u32 prev_legacy, cur_legacy;
2746 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2747 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2748 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2749 if (!prev_legacy && cur_legacy)
2750 start = 1;
2751 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2752 sizeof(kvm->arch.vpit->pit_state.channels));
2753 kvm->arch.vpit->pit_state.flags = ps->flags;
2754 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2755 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2756 return r;
2757}
2758
52d939a0
MT		 2759static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2760 struct kvm_reinject_control *control)
2761{
2762 if (!kvm->arch.vpit)
2763 return -ENXIO;
894a9c55 2764 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2765 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2766 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2767 return 0;
2768}
2769
5bb064dc
ZX		 2770/*
2771 * Get (and clear) the dirty memory log for a memory slot.
2772 */
2773int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2774 struct kvm_dirty_log *log)
2775{
87bf6e7d 2776 int r, i;
5bb064dc 2777 struct kvm_memory_slot *memslot;
87bf6e7d 2778 unsigned long n;
b050b015 2779 unsigned long is_dirty = 0;
5bb064dc 2780
79fac95e 2781 mutex_lock(&kvm->slots_lock);
5bb064dc 2782
b050b015
MT		 2783 r = -EINVAL;
2784 if (log->slot >= KVM_MEMORY_SLOTS)
2785 goto out;
2786
2787 memslot = &kvm->memslots->memslots[log->slot];
2788 r = -ENOENT;
2789 if (!memslot->dirty_bitmap)
2790 goto out;
2791
87bf6e7d 2792 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 2793
b050b015
MT		 2794 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2795 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2796
2797 /* If nothing is dirty, don't bother messing with page tables. */
2798 if (is_dirty) {
b050b015 2799 struct kvm_memslots *slots, *old_slots;
914ebccd 2800 unsigned long *dirty_bitmap;
b050b015 2801
7c8a83b7 2802 spin_lock(&kvm->mmu_lock);
5bb064dc 2803 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2804 spin_unlock(&kvm->mmu_lock);
b050b015 2805
914ebccd
TY		 2806 r = -ENOMEM;
2807 dirty_bitmap = vmalloc(n);
2808 if (!dirty_bitmap)
2809 goto out;
2810 memset(dirty_bitmap, 0, n);
b050b015 2811
914ebccd
TY		 2812 r = -ENOMEM;
2813 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2814 if (!slots) {
2815 vfree(dirty_bitmap);
2816 goto out;
2817 }
b050b015
MT		 2818 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2819 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2820
2821 old_slots = kvm->memslots;
2822 rcu_assign_pointer(kvm->memslots, slots);
2823 synchronize_srcu_expedited(&kvm->srcu);
2824 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2825 kfree(old_slots);
914ebccd
TY		 2826
2827 r = -EFAULT;
2828 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
2829 vfree(dirty_bitmap);
2830 goto out;
2831 }
2832 vfree(dirty_bitmap);
2833 } else {
2834 r = -EFAULT;
2835 if (clear_user(log->dirty_bitmap, n))
2836 goto out;
5bb064dc 2837 }
b050b015 2838
5bb064dc
ZX		 2839 r = 0;
2840out:
79fac95e 2841 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2842 return r;
2843}
2844
1fe779f8
CO		 2845long kvm_arch_vm_ioctl(struct file *filp,
2846 unsigned int ioctl, unsigned long arg)
2847{
2848 struct kvm *kvm = filp->private_data;
2849 void __user *argp = (void __user *)arg;
367e1319 2850 int r = -ENOTTY;
f0d66275
DH		 2851 /*
2852 * This union makes it completely explicit to gcc-3.x
2853 * that these two variables' stack usage should be
2854 * combined, not added together.
2855 */
2856 union {
2857 struct kvm_pit_state ps;
e9f42757 2858 struct kvm_pit_state2 ps2;
f0d66275 2859 struct kvm_memory_alias alias;
c5ff41ce 2860 struct kvm_pit_config pit_config;
f0d66275 2861 } u;
1fe779f8
CO		 2862
2863 switch (ioctl) {
2864 case KVM_SET_TSS_ADDR:
2865 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2866 if (r < 0)
2867 goto out;
2868 break;
b927a3ce
SY		 2869 case KVM_SET_IDENTITY_MAP_ADDR: {
2870 u64 ident_addr;
2871
2872 r = -EFAULT;
2873 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2874 goto out;
2875 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2876 if (r < 0)
2877 goto out;
2878 break;
2879 }
1fe779f8
CO		 2880 case KVM_SET_MEMORY_REGION: {
2881 struct kvm_memory_region kvm_mem;
2882 struct kvm_userspace_memory_region kvm_userspace_mem;
2883
2884 r = -EFAULT;
2885 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2886 goto out;
2887 kvm_userspace_mem.slot = kvm_mem.slot;
2888 kvm_userspace_mem.flags = kvm_mem.flags;
2889 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2890 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2891 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2892 if (r)
2893 goto out;
2894 break;
2895 }
2896 case KVM_SET_NR_MMU_PAGES:
2897 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2898 if (r)
2899 goto out;
2900 break;
2901 case KVM_GET_NR_MMU_PAGES:
2902 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2903 break;
f0d66275 2904 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2905 r = -EFAULT;
f0d66275 2906 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2907 goto out;
f0d66275 2908 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2909 if (r)
2910 goto out;
2911 break;
3ddea128
MT		 2912 case KVM_CREATE_IRQCHIP: {
2913 struct kvm_pic *vpic;
2914
2915 mutex_lock(&kvm->lock);
2916 r = -EEXIST;
2917 if (kvm->arch.vpic)
2918 goto create_irqchip_unlock;
1fe779f8 2919 r = -ENOMEM;
3ddea128
MT		 2920 vpic = kvm_create_pic(kvm);
2921 if (vpic) {
1fe779f8
CO		 2922 r = kvm_ioapic_init(kvm);
2923 if (r) {
72bb2fcd
WY		 2924 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2925 &vpic->dev);
3ddea128
MT		 2926 kfree(vpic);
2927 goto create_irqchip_unlock;
1fe779f8
CO		 2928 }
2929 } else
3ddea128
MT		 2930 goto create_irqchip_unlock;
2931 smp_wmb();
2932 kvm->arch.vpic = vpic;
2933 smp_wmb();
399ec807
AK		 2934 r = kvm_setup_default_irq_routing(kvm);
2935 if (r) {
3ddea128 2936 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2937 kvm_ioapic_destroy(kvm);
2938 kvm_destroy_pic(kvm);
3ddea128 2939 mutex_unlock(&kvm->irq_lock);
399ec807 2940 }
3ddea128
MT		 2941 create_irqchip_unlock:
2942 mutex_unlock(&kvm->lock);
1fe779f8 2943 break;
3ddea128 2944 }
7837699f 2945 case KVM_CREATE_PIT:
c5ff41ce
JK		 2946 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2947 goto create_pit;
2948 case KVM_CREATE_PIT2:
2949 r = -EFAULT;
2950 if (copy_from_user(&u.pit_config, argp,
2951 sizeof(struct kvm_pit_config)))
2952 goto out;
2953 create_pit:
79fac95e 2954 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2955 r = -EEXIST;
2956 if (kvm->arch.vpit)
2957 goto create_pit_unlock;
7837699f 2958 r = -ENOMEM;
c5ff41ce 2959 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2960 if (kvm->arch.vpit)
2961 r = 0;
269e05e4 2962 create_pit_unlock:
79fac95e 2963 mutex_unlock(&kvm->slots_lock);
7837699f 2964 break;
4925663a 2965 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2966 case KVM_IRQ_LINE: {
2967 struct kvm_irq_level irq_event;
2968
2969 r = -EFAULT;
2970 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2971 goto out;
160d2f6c 2972 r = -ENXIO;
1fe779f8 2973 if (irqchip_in_kernel(kvm)) {
4925663a 2974 __s32 status;
4925663a
GN		 2975 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2976 irq_event.irq, irq_event.level);
4925663a 2977 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 2978 r = -EFAULT;
4925663a
GN		 2979 irq_event.status = status;
2980 if (copy_to_user(argp, &irq_event,
2981 sizeof irq_event))
2982 goto out;
2983 }
1fe779f8
CO		 2984 r = 0;
2985 }
2986 break;
2987 }
2988 case KVM_GET_IRQCHIP: {
2989 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2990 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2991
f0d66275
DH		 2992 r = -ENOMEM;
2993 if (!chip)
1fe779f8 2994 goto out;
f0d66275
DH		 2995 r = -EFAULT;
2996 if (copy_from_user(chip, argp, sizeof *chip))
2997 goto get_irqchip_out;
1fe779f8
CO		 2998 r = -ENXIO;
2999 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3000 goto get_irqchip_out;
3001 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3002 if (r)
f0d66275 3003 goto get_irqchip_out;
1fe779f8 3004 r = -EFAULT;
f0d66275
DH		 3005 if (copy_to_user(argp, chip, sizeof *chip))
3006 goto get_irqchip_out;
1fe779f8 3007 r = 0;
f0d66275
DH		 3008 get_irqchip_out:
3009 kfree(chip);
3010 if (r)
3011 goto out;
1fe779f8
CO		 3012 break;
3013 }
3014 case KVM_SET_IRQCHIP: {
3015 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3016 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3017
f0d66275
DH		 3018 r = -ENOMEM;
3019 if (!chip)
1fe779f8 3020 goto out;
f0d66275
DH		 3021 r = -EFAULT;
3022 if (copy_from_user(chip, argp, sizeof *chip))
3023 goto set_irqchip_out;
1fe779f8
CO		 3024 r = -ENXIO;
3025 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3026 goto set_irqchip_out;
3027 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3028 if (r)
f0d66275 3029 goto set_irqchip_out;
1fe779f8 3030 r = 0;
f0d66275
DH		 3031 set_irqchip_out:
3032 kfree(chip);
3033 if (r)
3034 goto out;
1fe779f8
CO		 3035 break;
3036 }
e0f63cb9 3037 case KVM_GET_PIT: {
e0f63cb9 3038 r = -EFAULT;
f0d66275 3039 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3040 goto out;
3041 r = -ENXIO;
3042 if (!kvm->arch.vpit)
3043 goto out;
f0d66275 3044 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3045 if (r)
3046 goto out;
3047 r = -EFAULT;
f0d66275 3048 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3049 goto out;
3050 r = 0;
3051 break;
3052 }
3053 case KVM_SET_PIT: {
e0f63cb9 3054 r = -EFAULT;
f0d66275 3055 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3056 goto out;
3057 r = -ENXIO;
3058 if (!kvm->arch.vpit)
3059 goto out;
f0d66275 3060 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3061 if (r)
3062 goto out;
3063 r = 0;
3064 break;
3065 }
e9f42757
BK		 3066 case KVM_GET_PIT2: {
3067 r = -ENXIO;
3068 if (!kvm->arch.vpit)
3069 goto out;
3070 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3071 if (r)
3072 goto out;
3073 r = -EFAULT;
3074 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3075 goto out;
3076 r = 0;
3077 break;
3078 }
3079 case KVM_SET_PIT2: {
3080 r = -EFAULT;
3081 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3082 goto out;
3083 r = -ENXIO;
3084 if (!kvm->arch.vpit)
3085 goto out;
3086 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3087 if (r)
3088 goto out;
3089 r = 0;
3090 break;
3091 }
52d939a0
MT		 3092 case KVM_REINJECT_CONTROL: {
3093 struct kvm_reinject_control control;
3094 r = -EFAULT;
3095 if (copy_from_user(&control, argp, sizeof(control)))
3096 goto out;
3097 r = kvm_vm_ioctl_reinject(kvm, &control);
3098 if (r)
3099 goto out;
3100 r = 0;
3101 break;
3102 }
ffde22ac
ES		 3103 case KVM_XEN_HVM_CONFIG: {
3104 r = -EFAULT;
3105 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3106 sizeof(struct kvm_xen_hvm_config)))
3107 goto out;
3108 r = -EINVAL;
3109 if (kvm->arch.xen_hvm_config.flags)
3110 goto out;
3111 r = 0;
3112 break;
3113 }
afbcf7ab
GC		 3114 case KVM_SET_CLOCK: {
3115 struct timespec now;
3116 struct kvm_clock_data user_ns;
3117 u64 now_ns;
3118 s64 delta;
3119
3120 r = -EFAULT;
3121 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3122 goto out;
3123
3124 r = -EINVAL;
3125 if (user_ns.flags)
3126 goto out;
3127
3128 r = 0;
3129 ktime_get_ts(&now);
3130 now_ns = timespec_to_ns(&now);
3131 delta = user_ns.clock - now_ns;
3132 kvm->arch.kvmclock_offset = delta;
3133 break;
3134 }
3135 case KVM_GET_CLOCK: {
3136 struct timespec now;
3137 struct kvm_clock_data user_ns;
3138 u64 now_ns;
3139
3140 ktime_get_ts(&now);
3141 now_ns = timespec_to_ns(&now);
3142 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3143 user_ns.flags = 0;
3144
3145 r = -EFAULT;
3146 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3147 goto out;
3148 r = 0;
3149 break;
3150 }
3151
1fe779f8
CO		 3152 default:
3153 ;
3154 }
3155out:
3156 return r;
3157}
3158
a16b043c 3159static void kvm_init_msr_list(void)
043405e1
CO		 3160{
3161 u32 dummy[2];
3162 unsigned i, j;
3163
e3267cbb
GC		 3164 /* skip the first msrs in the list. KVM-specific */
3165 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3166 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3167 continue;
3168 if (j < i)
3169 msrs_to_save[j] = msrs_to_save[i];
3170 j++;
3171 }
3172 num_msrs_to_save = j;
3173}
3174
bda9020e
MT		 3175static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3176 const void *v)
bbd9b64e 3177{
bda9020e
MT		 3178 if (vcpu->arch.apic &&
3179 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3180 return 0;
bbd9b64e 3181
e93f8a0f 3182 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3183}
3184
bda9020e 3185static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3186{
bda9020e
MT		 3187 if (vcpu->arch.apic &&
3188 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3189 return 0;
bbd9b64e 3190
e93f8a0f 3191 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3192}
3193
2dafc6c2
GN		 3194static void kvm_set_segment(struct kvm_vcpu *vcpu,
3195 struct kvm_segment *var, int seg)
3196{
3197 kvm_x86_ops->set_segment(vcpu, var, seg);
3198}
3199
3200void kvm_get_segment(struct kvm_vcpu *vcpu,
3201 struct kvm_segment *var, int seg)
3202{
3203 kvm_x86_ops->get_segment(vcpu, var, seg);
3204}
3205
1871c602
GN		 3206gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3207{
3208 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3209 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3210}
3211
3212 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3213{
3214 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3215 access |= PFERR_FETCH_MASK;
3216 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3217}
3218
3219gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3220{
3221 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3222 access |= PFERR_WRITE_MASK;
3223 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3224}
3225
3226/* uses this to access any guest's mapped memory without checking CPL */
3227gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3228{
3229 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3230}
3231
3232static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3233 struct kvm_vcpu *vcpu, u32 access,
3234 u32 *error)
bbd9b64e
CO		 3235{
3236 void *data = val;
10589a46 3237 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3238
3239 while (bytes) {
1871c602 3240 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3241 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3242 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3243 int ret;
3244
10589a46
MT		 3245 if (gpa == UNMAPPED_GVA) {
3246 r = X86EMUL_PROPAGATE_FAULT;
3247 goto out;
3248 }
77c2002e 3249 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3250 if (ret < 0) {
c3cd7ffa 3251 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3252 goto out;
3253 }
bbd9b64e 3254
77c2002e
IE		 3255 bytes -= toread;
3256 data += toread;
3257 addr += toread;
bbd9b64e 3258 }
10589a46 3259out:
10589a46 3260 return r;
bbd9b64e 3261}
77c2002e 3262
1871c602
GN		 3263/* used for instruction fetching */
3264static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3265 struct kvm_vcpu *vcpu, u32 *error)
3266{
3267 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3268 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3269 access | PFERR_FETCH_MASK, error);
3270}
3271
3272static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3273 struct kvm_vcpu *vcpu, u32 *error)
3274{
3275 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3276 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3277 error);
3278}
3279
3280static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3281 struct kvm_vcpu *vcpu, u32 *error)
3282{
3283 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3284}
3285
7972995b 3286static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3287 unsigned int bytes,
7972995b 3288 struct kvm_vcpu *vcpu,
2dafc6c2 3289 u32 *error)
77c2002e
IE		 3290{
3291 void *data = val;
3292 int r = X86EMUL_CONTINUE;
3293
3294 while (bytes) {
7972995b
GN		 3295 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3296 PFERR_WRITE_MASK, error);
77c2002e
IE		 3297 unsigned offset = addr & (PAGE_SIZE-1);
3298 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3299 int ret;
3300
3301 if (gpa == UNMAPPED_GVA) {
3302 r = X86EMUL_PROPAGATE_FAULT;
3303 goto out;
3304 }
3305 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3306 if (ret < 0) {
c3cd7ffa 3307 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3308 goto out;
3309 }
3310
3311 bytes -= towrite;
3312 data += towrite;
3313 addr += towrite;
3314 }
3315out:
3316 return r;
3317}
3318
bbd9b64e
CO		 3319static int emulator_read_emulated(unsigned long addr,
3320 void *val,
3321 unsigned int bytes,
8fe681e9 3322 unsigned int *error_code,
bbd9b64e
CO		 3323 struct kvm_vcpu *vcpu)
3324{
bbd9b64e
CO		 3325 gpa_t gpa;
3326
3327 if (vcpu->mmio_read_completed) {
3328 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3329 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3330 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3331 vcpu->mmio_read_completed = 0;
3332 return X86EMUL_CONTINUE;
3333 }
3334
8fe681e9 3335 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3336
8fe681e9 3337 if (gpa == UNMAPPED_GVA)
1871c602 3338 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3339
3340 /* For APIC access vmexit */
3341 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3342 goto mmio;
3343
1871c602 3344 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3345 == X86EMUL_CONTINUE)
bbd9b64e 3346 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3347
3348mmio:
3349 /*
3350 * Is this MMIO handled locally?
3351 */
aec51dc4
AK		 3352 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3353 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3354 return X86EMUL_CONTINUE;
3355 }
aec51dc4
AK		 3356
3357 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3358
3359 vcpu->mmio_needed = 1;
411c35b7
GN		 3360 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3361 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3362 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3363 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3364
c3cd7ffa 3365 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3366}
3367
3200f405 3368int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3369 const void *val, int bytes)
bbd9b64e
CO		 3370{
3371 int ret;
3372
3373 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3374 if (ret < 0)
bbd9b64e 3375 return 0;
ad218f85 3376 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3377 return 1;
3378}
3379
3380static int emulator_write_emulated_onepage(unsigned long addr,
3381 const void *val,
3382 unsigned int bytes,
8fe681e9 3383 unsigned int *error_code,
bbd9b64e
CO		 3384 struct kvm_vcpu *vcpu)
3385{
10589a46
MT		 3386 gpa_t gpa;
3387
8fe681e9 3388 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3389
8fe681e9 3390 if (gpa == UNMAPPED_GVA)
bbd9b64e 3391 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3392
3393 /* For APIC access vmexit */
3394 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3395 goto mmio;
3396
3397 if (emulator_write_phys(vcpu, gpa, val, bytes))
3398 return X86EMUL_CONTINUE;
3399
3400mmio:
aec51dc4 3401 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3402 /*
3403 * Is this MMIO handled locally?
3404 */
bda9020e 3405 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3406 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3407
3408 vcpu->mmio_needed = 1;
411c35b7
GN		 3409 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3410 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3411 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3412 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3413 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3414
3415 return X86EMUL_CONTINUE;
3416}
3417
3418int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3419 const void *val,
3420 unsigned int bytes,
8fe681e9 3421 unsigned int *error_code,
8f6abd06 3422 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3423{
3424 /* Crossing a page boundary? */
3425 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3426 int rc, now;
3427
3428 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3429 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3430 vcpu);
bbd9b64e
CO		 3431 if (rc != X86EMUL_CONTINUE)
3432 return rc;
3433 addr += now;
3434 val += now;
3435 bytes -= now;
3436 }
8fe681e9
GN		 3437 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3438 vcpu);
bbd9b64e 3439}
bbd9b64e 3440
daea3e73
AK		 3441#define CMPXCHG_TYPE(t, ptr, old, new) \
3442 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3443
3444#ifdef CONFIG_X86_64
3445# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3446#else
3447# define CMPXCHG64(ptr, old, new) \
9749a6c0 3448 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3449#endif
3450
bbd9b64e
CO		 3451static int emulator_cmpxchg_emulated(unsigned long addr,
3452 const void *old,
3453 const void *new,
3454 unsigned int bytes,
8fe681e9 3455 unsigned int *error_code,
bbd9b64e
CO		 3456 struct kvm_vcpu *vcpu)
3457{
daea3e73
AK		 3458 gpa_t gpa;
3459 struct page *page;
3460 char *kaddr;
3461 bool exchanged;
2bacc55c 3462
daea3e73
AK		 3463 /* guests cmpxchg8b have to be emulated atomically */
3464 if (bytes > 8 || (bytes & (bytes - 1)))
3465 goto emul_write;
10589a46 3466
daea3e73 3467 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3468
daea3e73
AK		 3469 if (gpa == UNMAPPED_GVA ||
3470 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3471 goto emul_write;
2bacc55c 3472
daea3e73
AK		 3473 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3474 goto emul_write;
72dc67a6 3475
daea3e73 3476 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3477
daea3e73
AK		 3478 kaddr = kmap_atomic(page, KM_USER0);
3479 kaddr += offset_in_page(gpa);
3480 switch (bytes) {
3481 case 1:
3482 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3483 break;
3484 case 2:
3485 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3486 break;
3487 case 4:
3488 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3489 break;
3490 case 8:
3491 exchanged = CMPXCHG64(kaddr, old, new);
3492 break;
3493 default:
3494 BUG();
2bacc55c 3495 }
daea3e73
AK		 3496 kunmap_atomic(kaddr, KM_USER0);
3497 kvm_release_page_dirty(page);
3498
3499 if (!exchanged)
3500 return X86EMUL_CMPXCHG_FAILED;
3501
8f6abd06
GN		 3502 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3503
3504 return X86EMUL_CONTINUE;
4a5f48f6 3505
3200f405 3506emul_write:
daea3e73 3507 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3508
8fe681e9 3509 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3510}
3511
cf8f70bf
GN		 3512static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3513{
3514 /* TODO: String I/O for in kernel device */
3515 int r;
3516
3517 if (vcpu->arch.pio.in)
3518 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3519 vcpu->arch.pio.size, pd);
3520 else
3521 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3522 vcpu->arch.pio.port, vcpu->arch.pio.size,
3523 pd);
3524 return r;
3525}
3526
3527
3528static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3529 unsigned int count, struct kvm_vcpu *vcpu)
3530{
7972995b 3531 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3532 goto data_avail;
3533
3534 trace_kvm_pio(1, port, size, 1);
3535
3536 vcpu->arch.pio.port = port;
3537 vcpu->arch.pio.in = 1;
7972995b 3538 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3539 vcpu->arch.pio.size = size;
3540
3541 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3542 data_avail:
3543 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3544 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3545 return 1;
3546 }
3547
3548 vcpu->run->exit_reason = KVM_EXIT_IO;
3549 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3550 vcpu->run->io.size = size;
3551 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3552 vcpu->run->io.count = count;
3553 vcpu->run->io.port = port;
3554
3555 return 0;
3556}
3557
3558static int emulator_pio_out_emulated(int size, unsigned short port,
3559 const void *val, unsigned int count,
3560 struct kvm_vcpu *vcpu)
3561{
3562 trace_kvm_pio(0, port, size, 1);
3563
3564 vcpu->arch.pio.port = port;
3565 vcpu->arch.pio.in = 0;
7972995b 3566 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3567 vcpu->arch.pio.size = size;
3568
3569 memcpy(vcpu->arch.pio_data, val, size * count);
3570
3571 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3572 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3573 return 1;
3574 }
3575
3576 vcpu->run->exit_reason = KVM_EXIT_IO;
3577 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3578 vcpu->run->io.size = size;
3579 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3580 vcpu->run->io.count = count;
3581 vcpu->run->io.port = port;
3582
3583 return 0;
3584}
3585
bbd9b64e
CO		 3586static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3587{
3588 return kvm_x86_ops->get_segment_base(vcpu, seg);
3589}
3590
3591int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3592{
a7052897 3593 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3594 return X86EMUL_CONTINUE;
3595}
3596
3597int emulate_clts(struct kvm_vcpu *vcpu)
3598{
4d4ec087 3599 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3600 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3601 return X86EMUL_CONTINUE;
3602}
3603
35aa5375 3604int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3605{
338dbc97 3606 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3607}
3608
35aa5375 3609int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3610{
338dbc97
GN		 3611
3612 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3613}
3614
52a46617 3615static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 3616{
52a46617 3617 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 3618}
3619
52a46617 3620static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 3621{
52a46617
GN		 3622 unsigned long value;
3623
3624 switch (cr) {
3625 case 0:
3626 value = kvm_read_cr0(vcpu);
3627 break;
3628 case 2:
3629 value = vcpu->arch.cr2;
3630 break;
3631 case 3:
3632 value = vcpu->arch.cr3;
3633 break;
3634 case 4:
3635 value = kvm_read_cr4(vcpu);
3636 break;
3637 case 8:
3638 value = kvm_get_cr8(vcpu);
3639 break;
3640 default:
3641 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3642 return 0;
3643 }
3644
3645 return value;
3646}
3647
0f12244f 3648static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 3649{
0f12244f
GN		 3650 int res = 0;
3651
52a46617
GN		 3652 switch (cr) {
3653 case 0:
0f12244f 3654 res = __kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 3655 break;
3656 case 2:
3657 vcpu->arch.cr2 = val;
3658 break;
3659 case 3:
0f12244f 3660 res = __kvm_set_cr3(vcpu, val);
52a46617
GN		 3661 break;
3662 case 4:
0f12244f 3663 res = __kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 3664 break;
3665 case 8:
0f12244f 3666 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 3667 break;
3668 default:
3669 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 3670 res = -1;
52a46617 3671 }
0f12244f
GN		 3672
3673 return res;
52a46617
GN		 3674}
3675
9c537244
GN		 3676static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3677{
3678 return kvm_x86_ops->get_cpl(vcpu);
3679}
3680
2dafc6c2
GN		 3681static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3682{
3683 kvm_x86_ops->get_gdt(vcpu, dt);
3684}
3685
5951c442
GN		 3686static unsigned long emulator_get_cached_segment_base(int seg,
3687 struct kvm_vcpu *vcpu)
3688{
3689 return get_segment_base(vcpu, seg);
3690}
3691
2dafc6c2
GN		 3692static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3693 struct kvm_vcpu *vcpu)
3694{
3695 struct kvm_segment var;
3696
3697 kvm_get_segment(vcpu, &var, seg);
3698
3699 if (var.unusable)
3700 return false;
3701
3702 if (var.g)
3703 var.limit >>= 12;
3704 set_desc_limit(desc, var.limit);
3705 set_desc_base(desc, (unsigned long)var.base);
3706 desc->type = var.type;
3707 desc->s = var.s;
3708 desc->dpl = var.dpl;
3709 desc->p = var.present;
3710 desc->avl = var.avl;
3711 desc->l = var.l;
3712 desc->d = var.db;
3713 desc->g = var.g;
3714
3715 return true;
3716}
3717
3718static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3719 struct kvm_vcpu *vcpu)
3720{
3721 struct kvm_segment var;
3722
3723 /* needed to preserve selector */
3724 kvm_get_segment(vcpu, &var, seg);
3725
3726 var.base = get_desc_base(desc);
3727 var.limit = get_desc_limit(desc);
3728 if (desc->g)
3729 var.limit = (var.limit << 12) | 0xfff;
3730 var.type = desc->type;
3731 var.present = desc->p;
3732 var.dpl = desc->dpl;
3733 var.db = desc->d;
3734 var.s = desc->s;
3735 var.l = desc->l;
3736 var.g = desc->g;
3737 var.avl = desc->avl;
3738 var.present = desc->p;
3739 var.unusable = !var.present;
3740 var.padding = 0;
3741
3742 kvm_set_segment(vcpu, &var, seg);
3743 return;
3744}
3745
3746static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3747{
3748 struct kvm_segment kvm_seg;
3749
3750 kvm_get_segment(vcpu, &kvm_seg, seg);
3751 return kvm_seg.selector;
3752}
3753
3754static void emulator_set_segment_selector(u16 sel, int seg,
3755 struct kvm_vcpu *vcpu)
3756{
3757 struct kvm_segment kvm_seg;
3758
3759 kvm_get_segment(vcpu, &kvm_seg, seg);
3760 kvm_seg.selector = sel;
3761 kvm_set_segment(vcpu, &kvm_seg, seg);
3762}
3763
14af3f3c 3764static struct x86_emulate_ops emulate_ops = {
1871c602 3765 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3766 .write_std = kvm_write_guest_virt_system,
1871c602 3767 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3768 .read_emulated = emulator_read_emulated,
3769 .write_emulated = emulator_write_emulated,
3770 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3771 .pio_in_emulated = emulator_pio_in_emulated,
3772 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 3773 .get_cached_descriptor = emulator_get_cached_descriptor,
3774 .set_cached_descriptor = emulator_set_cached_descriptor,
3775 .get_segment_selector = emulator_get_segment_selector,
3776 .set_segment_selector = emulator_set_segment_selector,
5951c442 3777 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 3778 .get_gdt = emulator_get_gdt,
52a46617
GN		 3779 .get_cr = emulator_get_cr,
3780 .set_cr = emulator_set_cr,
9c537244 3781 .cpl = emulator_get_cpl,
35aa5375
GN		 3782 .get_dr = emulator_get_dr,
3783 .set_dr = emulator_set_dr,
3fb1b5db
GN		 3784 .set_msr = kvm_set_msr,
3785 .get_msr = kvm_get_msr,
bbd9b64e
CO		 3786};
3787
5fdbf976
MT		 3788static void cache_all_regs(struct kvm_vcpu *vcpu)
3789{
3790 kvm_register_read(vcpu, VCPU_REGS_RAX);
3791 kvm_register_read(vcpu, VCPU_REGS_RSP);
3792 kvm_register_read(vcpu, VCPU_REGS_RIP);
3793 vcpu->arch.regs_dirty = ~0;
3794}
3795
95cb2295
GN		 3796static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
3797{
3798 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
3799 /*
3800 * an sti; sti; sequence only disable interrupts for the first
3801 * instruction. So, if the last instruction, be it emulated or
3802 * not, left the system with the INT_STI flag enabled, it
3803 * means that the last instruction is an sti. We should not
3804 * leave the flag on in this case. The same goes for mov ss
3805 */
3806 if (!(int_shadow & mask))
3807 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
3808}
3809
54b8486f
GN		 3810static void inject_emulated_exception(struct kvm_vcpu *vcpu)
3811{
3812 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
3813 if (ctxt->exception == PF_VECTOR)
3814 kvm_inject_page_fault(vcpu, ctxt->cr2, ctxt->error_code);
3815 else if (ctxt->error_code_valid)
3816 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
3817 else
3818 kvm_queue_exception(vcpu, ctxt->exception);
3819}
3820
6d77dbfc
GN		 3821static int handle_emulation_failure(struct kvm_vcpu *vcpu)
3822{
6d77dbfc
GN		 3823 ++vcpu->stat.insn_emulation_fail;
3824 trace_kvm_emulate_insn_failed(vcpu);
3825 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3826 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3827 vcpu->run->internal.ndata = 0;
3828 kvm_queue_exception(vcpu, UD_VECTOR);
3829 return EMULATE_FAIL;
3830}
3831
bbd9b64e 3832int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3833 unsigned long cr2,
3834 u16 error_code,
571008da 3835 int emulation_type)
bbd9b64e 3836{
95cb2295 3837 int r;
4d2179e1 3838 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 3839
26eef70c 3840 kvm_clear_exception_queue(vcpu);
ad312c7c 3841 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3842 /*
56e82318 3843 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3844 * instead of direct ->regs accesses, can save hundred cycles
3845 * on Intel for instructions that don't read/change RSP, for
3846 * for example.
3847 */
3848 cache_all_regs(vcpu);
bbd9b64e 3849
571008da 3850 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3851 int cs_db, cs_l;
3852 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3853
ad312c7c 3854 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3855 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
063db061 3856 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
ad312c7c 3857 vcpu->arch.emulate_ctxt.mode =
a0044755 3858 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3859 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3860 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3861 ? X86EMUL_MODE_PROT64 : cs_db
3862 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 3863 memset(c, 0, sizeof(struct decode_cache));
3864 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
95cb2295 3865 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 3866 vcpu->arch.emulate_ctxt.exception = -1;
bbd9b64e 3867
ad312c7c 3868 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
e46479f8 3869 trace_kvm_emulate_insn_start(vcpu);
571008da 3870
0cb5762e
AP		 3871 /* Only allow emulation of specific instructions on #UD
3872 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 3873 if (emulation_type & EMULTYPE_TRAP_UD) {
3874 if (!c->twobyte)
3875 return EMULATE_FAIL;
3876 switch (c->b) {
3877 case 0x01: /* VMMCALL */
3878 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3879 return EMULATE_FAIL;
3880 break;
3881 case 0x34: /* sysenter */
3882 case 0x35: /* sysexit */
3883 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3884 return EMULATE_FAIL;
3885 break;
3886 case 0x05: /* syscall */
3887 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3888 return EMULATE_FAIL;
3889 break;
3890 default:
3891 return EMULATE_FAIL;
3892 }
3893
3894 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3895 return EMULATE_FAIL;
3896 }
571008da 3897
f2b5756b 3898 ++vcpu->stat.insn_emulation;
bbd9b64e
CO		 3899 if (r) {
3900 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3901 return EMULATE_DONE;
6d77dbfc
GN		 3902 if (emulation_type & EMULTYPE_SKIP)
3903 return EMULATE_FAIL;
3904 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 3905 }
3906 }
3907
ba8afb6b
GN		 3908 if (emulation_type & EMULTYPE_SKIP) {
3909 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3910 return EMULATE_DONE;
3911 }
3912
4d2179e1
GN		 3913 /* this is needed for vmware backdor interface to work since it
3914 changes registers values during IO operation */
3915 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
3916
5cd21917 3917restart:
ad312c7c 3918 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 3919
c3cd7ffa
GN		 3920 if (r) { /* emulation failed */
3921 /*
3922 * if emulation was due to access to shadowed page table
3923 * and it failed try to unshadow page and re-entetr the
3924 * guest to let CPU execute the instruction.
3925 */
3926 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3927 return EMULATE_DONE;
3928
6d77dbfc 3929 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 3930 }
3931
95cb2295 3932 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
ef050dc0 3933 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4d2179e1 3934 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 3935 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
3457e419 3936
54b8486f
GN		 3937 if (vcpu->arch.emulate_ctxt.exception >= 0) {
3938 inject_emulated_exception(vcpu);
3939 return EMULATE_DONE;
3940 }
3941
3457e419
GN		 3942 if (vcpu->arch.pio.count) {
3943 if (!vcpu->arch.pio.in)
3944 vcpu->arch.pio.count = 0;
3945 return EMULATE_DO_MMIO;
3946 }
3947
3948 if (vcpu->mmio_needed) {
3949 if (vcpu->mmio_is_write)
3950 vcpu->mmio_needed = 0;
3951 return EMULATE_DO_MMIO;
3952 }
3953
5cd21917
GN		 3954 if (vcpu->arch.emulate_ctxt.restart)
3955 goto restart;
f850e2e6 3956
bbd9b64e 3957 return EMULATE_DONE;
de7d789a 3958}
bbd9b64e 3959EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 3960
cf8f70bf 3961int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 3962{
cf8f70bf
GN		 3963 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3964 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
3965 /* do not return to emulator after return from userspace */
7972995b 3966 vcpu->arch.pio.count = 0;
de7d789a
CO		 3967 return ret;
3968}
cf8f70bf 3969EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 3970
c8076604
GH		 3971static void bounce_off(void *info)
3972{
3973 /* nothing */
3974}
3975
c8076604
GH		 3976static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3977 void *data)
3978{
3979 struct cpufreq_freqs *freq = data;
3980 struct kvm *kvm;
3981 struct kvm_vcpu *vcpu;
3982 int i, send_ipi = 0;
3983
c8076604
GH		 3984 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3985 return 0;
3986 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3987 return 0;
0cca7907 3988 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3989
3990 spin_lock(&kvm_lock);
3991 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3992 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3993 if (vcpu->cpu != freq->cpu)
3994 continue;
3995 if (!kvm_request_guest_time_update(vcpu))
3996 continue;
3997 if (vcpu->cpu != smp_processor_id())
3998 send_ipi++;
3999 }
4000 }
4001 spin_unlock(&kvm_lock);
4002
4003 if (freq->old < freq->new && send_ipi) {
4004 /*
4005 * We upscale the frequency. Must make the guest
4006 * doesn't see old kvmclock values while running with
4007 * the new frequency, otherwise we risk the guest sees
4008 * time go backwards.
4009 *
4010 * In case we update the frequency for another cpu
4011 * (which might be in guest context) send an interrupt
4012 * to kick the cpu out of guest context. Next time
4013 * guest context is entered kvmclock will be updated,
4014 * so the guest will not see stale values.
4015 */
4016 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
4017 }
4018 return 0;
4019}
4020
4021static struct notifier_block kvmclock_cpufreq_notifier_block = {
4022 .notifier_call = kvmclock_cpufreq_notifier
4023};
4024
b820cc0c
ZA		 4025static void kvm_timer_init(void)
4026{
4027 int cpu;
4028
b820cc0c 4029 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 4030 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4031 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 4032 for_each_online_cpu(cpu) {
4033 unsigned long khz = cpufreq_get(cpu);
4034 if (!khz)
4035 khz = tsc_khz;
4036 per_cpu(cpu_tsc_khz, cpu) = khz;
4037 }
0cca7907
ZA		 4038 } else {
4039 for_each_possible_cpu(cpu)
4040 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 4041 }
4042}
4043
ff9d07a0
ZY		 4044static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4045
4046static int kvm_is_in_guest(void)
4047{
4048 return percpu_read(current_vcpu) != NULL;
4049}
4050
4051static int kvm_is_user_mode(void)
4052{
4053 int user_mode = 3;
dcf46b94 4054
ff9d07a0
ZY		 4055 if (percpu_read(current_vcpu))
4056 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4057
ff9d07a0
ZY		 4058 return user_mode != 0;
4059}
4060
4061static unsigned long kvm_get_guest_ip(void)
4062{
4063 unsigned long ip = 0;
dcf46b94 4064
ff9d07a0
ZY		 4065 if (percpu_read(current_vcpu))
4066 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4067
ff9d07a0
ZY		 4068 return ip;
4069}
4070
4071static struct perf_guest_info_callbacks kvm_guest_cbs = {
4072 .is_in_guest = kvm_is_in_guest,
4073 .is_user_mode = kvm_is_user_mode,
4074 .get_guest_ip = kvm_get_guest_ip,
4075};
4076
4077void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4078{
4079 percpu_write(current_vcpu, vcpu);
4080}
4081EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4082
4083void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4084{
4085 percpu_write(current_vcpu, NULL);
4086}
4087EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4088
f8c16bba 4089int kvm_arch_init(void *opaque)
043405e1 4090{
b820cc0c 4091 int r;
f8c16bba
ZX		 4092 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4093
f8c16bba
ZX		 4094 if (kvm_x86_ops) {
4095 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4096 r = -EEXIST;
4097 goto out;
f8c16bba
ZX		 4098 }
4099
4100 if (!ops->cpu_has_kvm_support()) {
4101 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4102 r = -EOPNOTSUPP;
4103 goto out;
f8c16bba
ZX		 4104 }
4105 if (ops->disabled_by_bios()) {
4106 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4107 r = -EOPNOTSUPP;
4108 goto out;
f8c16bba
ZX		 4109 }
4110
97db56ce
AK		 4111 r = kvm_mmu_module_init();
4112 if (r)
4113 goto out;
4114
4115 kvm_init_msr_list();
4116
f8c16bba 4117 kvm_x86_ops = ops;
56c6d28a 4118 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4119 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4120 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4121 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4122
b820cc0c 4123 kvm_timer_init();
c8076604 4124
ff9d07a0
ZY		 4125 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4126
f8c16bba 4127 return 0;
56c6d28a
ZX		 4128
4129out:
56c6d28a 4130 return r;
043405e1 4131}
8776e519 4132
f8c16bba
ZX		 4133void kvm_arch_exit(void)
4134{
ff9d07a0
ZY		 4135 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4136
888d256e
JK		 4137 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4138 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4139 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 4140 kvm_x86_ops = NULL;
56c6d28a
ZX		 4141 kvm_mmu_module_exit();
4142}
f8c16bba 4143
8776e519
HB		 4144int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4145{
4146 ++vcpu->stat.halt_exits;
4147 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4148 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4149 return 1;
4150 } else {
4151 vcpu->run->exit_reason = KVM_EXIT_HLT;
4152 return 0;
4153 }
4154}
4155EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4156
2f333bcb
MT		 4157static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4158 unsigned long a1)
4159{
4160 if (is_long_mode(vcpu))
4161 return a0;
4162 else
4163 return a0 | ((gpa_t)a1 << 32);
4164}
4165
55cd8e5a
GN		 4166int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4167{
4168 u64 param, ingpa, outgpa, ret;
4169 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4170 bool fast, longmode;
4171 int cs_db, cs_l;
4172
4173 /*
4174 * hypercall generates UD from non zero cpl and real mode
4175 * per HYPER-V spec
4176 */
3eeb3288 4177 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4178 kvm_queue_exception(vcpu, UD_VECTOR);
4179 return 0;
4180 }
4181
4182 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4183 longmode = is_long_mode(vcpu) && cs_l == 1;
4184
4185 if (!longmode) {
ccd46936
GN		 4186 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4187 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4188 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4189 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4190 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4191 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4192 }
4193#ifdef CONFIG_X86_64
4194 else {
4195 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4196 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4197 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4198 }
4199#endif
4200
4201 code = param & 0xffff;
4202 fast = (param >> 16) & 0x1;
4203 rep_cnt = (param >> 32) & 0xfff;
4204 rep_idx = (param >> 48) & 0xfff;
4205
4206 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4207
c25bc163
GN		 4208 switch (code) {
4209 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4210 kvm_vcpu_on_spin(vcpu);
4211 break;
4212 default:
4213 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4214 break;
4215 }
55cd8e5a
GN		 4216
4217 ret = res | (((u64)rep_done & 0xfff) << 32);
4218 if (longmode) {
4219 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4220 } else {
4221 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4222 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4223 }
4224
4225 return 1;
4226}
4227
8776e519
HB		 4228int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4229{
4230 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4231 int r = 1;
8776e519 4232
55cd8e5a
GN		 4233 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4234 return kvm_hv_hypercall(vcpu);
4235
5fdbf976
MT		 4236 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4237 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4238 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4239 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4240 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4241
229456fc 4242 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4243
8776e519
HB		 4244 if (!is_long_mode(vcpu)) {
4245 nr &= 0xFFFFFFFF;
4246 a0 &= 0xFFFFFFFF;
4247 a1 &= 0xFFFFFFFF;
4248 a2 &= 0xFFFFFFFF;
4249 a3 &= 0xFFFFFFFF;
4250 }
4251
07708c4a
JK		 4252 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4253 ret = -KVM_EPERM;
4254 goto out;
4255 }
4256
8776e519 4257 switch (nr) {
b93463aa
AK		 4258 case KVM_HC_VAPIC_POLL_IRQ:
4259 ret = 0;
4260 break;
2f333bcb
MT		 4261 case KVM_HC_MMU_OP:
4262 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4263 break;
8776e519
HB		 4264 default:
4265 ret = -KVM_ENOSYS;
4266 break;
4267 }
07708c4a 4268out:
5fdbf976 4269 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4270 ++vcpu->stat.hypercalls;
2f333bcb 4271 return r;
8776e519
HB		 4272}
4273EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4274
4275int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4276{
4277 char instruction[3];
5fdbf976 4278 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4279
8776e519
HB		 4280 /*
4281 * Blow out the MMU to ensure that no other VCPU has an active mapping
4282 * to ensure that the updated hypercall appears atomically across all
4283 * VCPUs.
4284 */
4285 kvm_mmu_zap_all(vcpu->kvm);
4286
8776e519 4287 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4288
8fe681e9 4289 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4290}
4291
8776e519
HB		 4292void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4293{
89a27f4d 4294 struct desc_ptr dt = { limit, base };
8776e519
HB		 4295
4296 kvm_x86_ops->set_gdt(vcpu, &dt);
4297}
4298
4299void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4300{
89a27f4d 4301 struct desc_ptr dt = { limit, base };
8776e519
HB		 4302
4303 kvm_x86_ops->set_idt(vcpu, &dt);
4304}
4305
07716717
DK		 4306static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4307{
ad312c7c
ZX		 4308 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4309 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4310
4311 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4312 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4313 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4314 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4315 if (ej->function == e->function) {
4316 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4317 return j;
4318 }
4319 }
4320 return 0; /* silence gcc, even though control never reaches here */
4321}
4322
4323/* find an entry with matching function, matching index (if needed), and that
4324 * should be read next (if it's stateful) */
4325static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4326 u32 function, u32 index)
4327{
4328 if (e->function != function)
4329 return 0;
4330 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4331 return 0;
4332 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4333 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4334 return 0;
4335 return 1;
4336}
4337
d8017474
AG		 4338struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4339 u32 function, u32 index)
8776e519
HB		 4340{
4341 int i;
d8017474 4342 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4343
ad312c7c 4344 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4345 struct kvm_cpuid_entry2 *e;
4346
ad312c7c 4347 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4348 if (is_matching_cpuid_entry(e, function, index)) {
4349 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4350 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4351 best = e;
4352 break;
4353 }
4354 /*
4355 * Both basic or both extended?
4356 */
4357 if (((e->function ^ function) & 0x80000000) == 0)
4358 if (!best || e->function > best->function)
4359 best = e;
4360 }
d8017474
AG		 4361 return best;
4362}
0e851880 4363EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4364
82725b20
DE		 4365int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4366{
4367 struct kvm_cpuid_entry2 *best;
4368
f7a71197
AK		 4369 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4370 if (!best || best->eax < 0x80000008)
4371 goto not_found;
82725b20
DE		 4372 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4373 if (best)
4374 return best->eax & 0xff;
f7a71197 4375not_found:
82725b20
DE		 4376 return 36;
4377}
4378
d8017474
AG		 4379void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4380{
4381 u32 function, index;
4382 struct kvm_cpuid_entry2 *best;
4383
4384 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4385 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4386 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4387 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4388 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4389 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4390 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4391 if (best) {
5fdbf976
MT		 4392 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4393 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4394 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4395 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4396 }
8776e519 4397 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4398 trace_kvm_cpuid(function,
4399 kvm_register_read(vcpu, VCPU_REGS_RAX),
4400 kvm_register_read(vcpu, VCPU_REGS_RBX),
4401 kvm_register_read(vcpu, VCPU_REGS_RCX),
4402 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4403}
4404EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4405
b6c7a5dc
HB		 4406/*
4407 * Check if userspace requested an interrupt window, and that the
4408 * interrupt window is open.
4409 *
4410 * No need to exit to userspace if we already have an interrupt queued.
4411 */
851ba692 4412static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4413{
8061823a 4414 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4415 vcpu->run->request_interrupt_window &&
5df56646 4416 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4417}
4418
851ba692 4419static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4420{
851ba692
AK		 4421 struct kvm_run *kvm_run = vcpu->run;
4422
91586a3b 4423 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4424 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4425 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4426 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4427 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4428 else
b6c7a5dc 4429 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4430 kvm_arch_interrupt_allowed(vcpu) &&
4431 !kvm_cpu_has_interrupt(vcpu) &&
4432 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4433}
4434
b93463aa
AK		 4435static void vapic_enter(struct kvm_vcpu *vcpu)
4436{
4437 struct kvm_lapic *apic = vcpu->arch.apic;
4438 struct page *page;
4439
4440 if (!apic || !apic->vapic_addr)
4441 return;
4442
4443 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4444
4445 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4446}
4447
4448static void vapic_exit(struct kvm_vcpu *vcpu)
4449{
4450 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4451 int idx;
b93463aa
AK		 4452
4453 if (!apic || !apic->vapic_addr)
4454 return;
4455
f656ce01 4456 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4457 kvm_release_page_dirty(apic->vapic_page);
4458 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4459 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4460}
4461
95ba8273
GN		 4462static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4463{
4464 int max_irr, tpr;
4465
4466 if (!kvm_x86_ops->update_cr8_intercept)
4467 return;
4468
88c808fd
AK		 4469 if (!vcpu->arch.apic)
4470 return;
4471
8db3baa2
GN		 4472 if (!vcpu->arch.apic->vapic_addr)
4473 max_irr = kvm_lapic_find_highest_irr(vcpu);
4474 else
4475 max_irr = -1;
95ba8273
GN		 4476
4477 if (max_irr != -1)
4478 max_irr >>= 4;
4479
4480 tpr = kvm_lapic_get_cr8(vcpu);
4481
4482 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4483}
4484
851ba692 4485static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4486{
4487 /* try to reinject previous events if any */
b59bb7bd 4488 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4489 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4490 vcpu->arch.exception.has_error_code,
4491 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4492 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4493 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4494 vcpu->arch.exception.error_code,
4495 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4496 return;
4497 }
4498
95ba8273
GN		 4499 if (vcpu->arch.nmi_injected) {
4500 kvm_x86_ops->set_nmi(vcpu);
4501 return;
4502 }
4503
4504 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4505 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4506 return;
4507 }
4508
4509 /* try to inject new event if pending */
4510 if (vcpu->arch.nmi_pending) {
4511 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4512 vcpu->arch.nmi_pending = false;
4513 vcpu->arch.nmi_injected = true;
4514 kvm_x86_ops->set_nmi(vcpu);
4515 }
4516 } else if (kvm_cpu_has_interrupt(vcpu)) {
4517 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4518 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4519 false);
4520 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4521 }
4522 }
4523}
4524
851ba692 4525static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4526{
4527 int r;
6a8b1d13 4528 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4529 vcpu->run->request_interrupt_window;
b6c7a5dc 4530
2e53d63a
MT		 4531 if (vcpu->requests)
4532 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4533 kvm_mmu_unload(vcpu);
4534
b6c7a5dc
HB		 4535 r = kvm_mmu_reload(vcpu);
4536 if (unlikely(r))
4537 goto out;
4538
2f52d58c
AK		 4539 if (vcpu->requests) {
4540 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4541 __kvm_migrate_timers(vcpu);
c8076604
GH		 4542 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4543 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4544 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4545 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4546 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4547 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4548 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4549 &vcpu->requests)) {
851ba692 4550 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4551 r = 0;
4552 goto out;
4553 }
71c4dfaf 4554 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4555 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4556 r = 0;
4557 goto out;
4558 }
02daab21
AK		 4559 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4560 vcpu->fpu_active = 0;
4561 kvm_x86_ops->fpu_deactivate(vcpu);
4562 }
2f52d58c 4563 }
b93463aa 4564
b6c7a5dc
HB		 4565 preempt_disable();
4566
4567 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4568 if (vcpu->fpu_active)
4569 kvm_load_guest_fpu(vcpu);
b6c7a5dc 4570
d94e1dc9
AK		 4571 atomic_set(&vcpu->guest_mode, 1);
4572 smp_wmb();
b6c7a5dc 4573
d94e1dc9 4574 local_irq_disable();
32f88400 4575
d94e1dc9
AK		 4576 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
4577 || need_resched() || signal_pending(current)) {
4578 atomic_set(&vcpu->guest_mode, 0);
4579 smp_wmb();
6c142801
AK		 4580 local_irq_enable();
4581 preempt_enable();
4582 r = 1;
4583 goto out;
4584 }
4585
851ba692 4586 inject_pending_event(vcpu);
b6c7a5dc 4587
6a8b1d13
GN		 4588 /* enable NMI/IRQ window open exits if needed */
4589 if (vcpu->arch.nmi_pending)
4590 kvm_x86_ops->enable_nmi_window(vcpu);
4591 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4592 kvm_x86_ops->enable_irq_window(vcpu);
4593
95ba8273 4594 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4595 update_cr8_intercept(vcpu);
4596 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4597 }
b93463aa 4598
f656ce01 4599 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4600
b6c7a5dc
HB		 4601 kvm_guest_enter();
4602
42dbaa5a 4603 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4604 set_debugreg(0, 7);
4605 set_debugreg(vcpu->arch.eff_db[0], 0);
4606 set_debugreg(vcpu->arch.eff_db[1], 1);
4607 set_debugreg(vcpu->arch.eff_db[2], 2);
4608 set_debugreg(vcpu->arch.eff_db[3], 3);
4609 }
b6c7a5dc 4610
229456fc 4611 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4612 kvm_x86_ops->run(vcpu);
b6c7a5dc 4613
24f1e32c
FW		 4614 /*
4615 * If the guest has used debug registers, at least dr7
4616 * will be disabled while returning to the host.
4617 * If we don't have active breakpoints in the host, we don't
4618 * care about the messed up debug address registers. But if
4619 * we have some of them active, restore the old state.
4620 */
59d8eb53 4621 if (hw_breakpoint_active())
24f1e32c 4622 hw_breakpoint_restore();
42dbaa5a 4623
d94e1dc9
AK		 4624 atomic_set(&vcpu->guest_mode, 0);
4625 smp_wmb();
b6c7a5dc
HB		 4626 local_irq_enable();
4627
4628 ++vcpu->stat.exits;
4629
4630 /*
4631 * We must have an instruction between local_irq_enable() and
4632 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4633 * the interrupt shadow. The stat.exits increment will do nicely.
4634 * But we need to prevent reordering, hence this barrier():
4635 */
4636 barrier();
4637
4638 kvm_guest_exit();
4639
4640 preempt_enable();
4641
f656ce01 4642 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4643
b6c7a5dc
HB		 4644 /*
4645 * Profile KVM exit RIPs:
4646 */
4647 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4648 unsigned long rip = kvm_rip_read(vcpu);
4649 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4650 }
4651
298101da 4652
b93463aa
AK		 4653 kvm_lapic_sync_from_vapic(vcpu);
4654
851ba692 4655 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4656out:
4657 return r;
4658}
b6c7a5dc 4659
09cec754 4660
851ba692 4661static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4662{
4663 int r;
f656ce01 4664 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4665
4666 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4667 pr_debug("vcpu %d received sipi with vector # %x\n",
4668 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4669 kvm_lapic_reset(vcpu);
5f179287 4670 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4671 if (r)
4672 return r;
4673 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4674 }
4675
f656ce01 4676 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4677 vapic_enter(vcpu);
4678
4679 r = 1;
4680 while (r > 0) {
af2152f5 4681 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4682 r = vcpu_enter_guest(vcpu);
d7690175 4683 else {
f656ce01 4684 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4685 kvm_vcpu_block(vcpu);
f656ce01 4686 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4687 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4688 {
4689 switch(vcpu->arch.mp_state) {
4690 case KVM_MP_STATE_HALTED:
d7690175 4691 vcpu->arch.mp_state =
09cec754
GN		 4692 KVM_MP_STATE_RUNNABLE;
4693 case KVM_MP_STATE_RUNNABLE:
4694 break;
4695 case KVM_MP_STATE_SIPI_RECEIVED:
4696 default:
4697 r = -EINTR;
4698 break;
4699 }
4700 }
d7690175
MT		 4701 }
4702
09cec754
GN		 4703 if (r <= 0)
4704 break;
4705
4706 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4707 if (kvm_cpu_has_pending_timer(vcpu))
4708 kvm_inject_pending_timer_irqs(vcpu);
4709
851ba692 4710 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4711 r = -EINTR;
851ba692 4712 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4713 ++vcpu->stat.request_irq_exits;
4714 }
4715 if (signal_pending(current)) {
4716 r = -EINTR;
851ba692 4717 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4718 ++vcpu->stat.signal_exits;
4719 }
4720 if (need_resched()) {
f656ce01 4721 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4722 kvm_resched(vcpu);
f656ce01 4723 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4724 }
b6c7a5dc
HB		 4725 }
4726
f656ce01 4727 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 4728
b93463aa
AK		 4729 vapic_exit(vcpu);
4730
b6c7a5dc
HB		 4731 return r;
4732}
4733
4734int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4735{
4736 int r;
4737 sigset_t sigsaved;
4738
ac9f6dc0
AK		 4739 if (vcpu->sigset_active)
4740 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4741
a4535290 4742 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4743 kvm_vcpu_block(vcpu);
d7690175 4744 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4745 r = -EAGAIN;
4746 goto out;
b6c7a5dc
HB		 4747 }
4748
b6c7a5dc
HB		 4749 /* re-sync apic's tpr */
4750 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4751 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4752
92bf9748
GN		 4753 if (vcpu->arch.pio.count || vcpu->mmio_needed ||
4754 vcpu->arch.emulate_ctxt.restart) {
4755 if (vcpu->mmio_needed) {
4756 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4757 vcpu->mmio_read_completed = 1;
4758 vcpu->mmio_needed = 0;
b6c7a5dc 4759 }
f656ce01 4760 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 4761 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 4762 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 4763 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 4764 r = 0;
4765 goto out;
4766 }
4767 }
5fdbf976
MT		 4768 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4769 kvm_register_write(vcpu, VCPU_REGS_RAX,
4770 kvm_run->hypercall.ret);
b6c7a5dc 4771
851ba692 4772 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4773
4774out:
f1d86e46 4775 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 4776 if (vcpu->sigset_active)
4777 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4778
b6c7a5dc
HB		 4779 return r;
4780}
4781
4782int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4783{
5fdbf976
MT		 4784 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4785 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4786 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4787 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4788 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4789 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4790 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4791 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4792#ifdef CONFIG_X86_64
5fdbf976
MT		 4793 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4794 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4795 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4796 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4797 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4798 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4799 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4800 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4801#endif
4802
5fdbf976 4803 regs->rip = kvm_rip_read(vcpu);
91586a3b 4804 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 4805
b6c7a5dc
HB		 4806 return 0;
4807}
4808
4809int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4810{
5fdbf976
MT		 4811 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4812 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4813 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4814 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4815 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4816 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4817 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4818 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4819#ifdef CONFIG_X86_64
5fdbf976
MT		 4820 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4821 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4822 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4823 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4824 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4825 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4826 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4827 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4828#endif
4829
5fdbf976 4830 kvm_rip_write(vcpu, regs->rip);
91586a3b 4831 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4832
b4f14abd
JK		 4833 vcpu->arch.exception.pending = false;
4834
b6c7a5dc
HB		 4835 return 0;
4836}
4837
b6c7a5dc
HB		 4838void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4839{
4840 struct kvm_segment cs;
4841
3e6e0aab 4842 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4843 *db = cs.db;
4844 *l = cs.l;
4845}
4846EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4847
4848int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4849 struct kvm_sregs *sregs)
4850{
89a27f4d 4851 struct desc_ptr dt;
b6c7a5dc 4852
3e6e0aab
GT		 4853 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4854 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4855 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4856 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4857 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4858 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4859
3e6e0aab
GT		 4860 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4861 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4862
4863 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4864 sregs->idt.limit = dt.size;
4865 sregs->idt.base = dt.address;
b6c7a5dc 4866 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4867 sregs->gdt.limit = dt.size;
4868 sregs->gdt.base = dt.address;
b6c7a5dc 4869
4d4ec087 4870 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4871 sregs->cr2 = vcpu->arch.cr2;
4872 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4873 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4874 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4875 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4876 sregs->apic_base = kvm_get_apic_base(vcpu);
4877
923c61bb 4878 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4879
36752c9b 4880 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4881 set_bit(vcpu->arch.interrupt.nr,
4882 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4883
b6c7a5dc
HB		 4884 return 0;
4885}
4886
62d9f0db
MT		 4887int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4888 struct kvm_mp_state *mp_state)
4889{
62d9f0db 4890 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 4891 return 0;
4892}
4893
4894int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4895 struct kvm_mp_state *mp_state)
4896{
62d9f0db 4897 vcpu->arch.mp_state = mp_state->mp_state;
62d9f0db
MT		 4898 return 0;
4899}
4900
e269fb21
JK		 4901int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
4902 bool has_error_code, u32 error_code)
b6c7a5dc 4903{
4d2179e1 4904 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
ceffb459
GN		 4905 int cs_db, cs_l, ret;
4906 cache_all_regs(vcpu);
37817f29 4907
ceffb459 4908 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
e01c2426 4909
ceffb459
GN		 4910 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4911 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4912 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4913 vcpu->arch.emulate_ctxt.mode =
4914 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4915 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4916 ? X86EMUL_MODE_VM86 : cs_l
4917 ? X86EMUL_MODE_PROT64 : cs_db
4918 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4d2179e1
GN		 4919 memset(c, 0, sizeof(struct decode_cache));
4920 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
c697518a 4921
ceffb459 4922 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
e269fb21
JK		 4923 tss_selector, reason, has_error_code,
4924 error_code);
c697518a 4925
c697518a 4926 if (ret)
19d04437 4927 return EMULATE_FAIL;
37817f29 4928
4d2179e1 4929 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 4930 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437
GN		 4931 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4932 return EMULATE_DONE;
37817f29
IE		 4933}
4934EXPORT_SYMBOL_GPL(kvm_task_switch);
4935
b6c7a5dc
HB		 4936int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4937 struct kvm_sregs *sregs)
4938{
4939 int mmu_reset_needed = 0;
923c61bb 4940 int pending_vec, max_bits;
89a27f4d 4941 struct desc_ptr dt;
b6c7a5dc 4942
89a27f4d
GN		 4943 dt.size = sregs->idt.limit;
4944 dt.address = sregs->idt.base;
b6c7a5dc 4945 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 4946 dt.size = sregs->gdt.limit;
4947 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 4948 kvm_x86_ops->set_gdt(vcpu, &dt);
4949
ad312c7c
ZX		 4950 vcpu->arch.cr2 = sregs->cr2;
4951 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4952 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4953
2d3ad1f4 4954 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4955
f6801dff 4956 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 4957 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4958 kvm_set_apic_base(vcpu, sregs->apic_base);
4959
4d4ec087 4960 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 4961 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4962 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4963
fc78f519 4964 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 4965 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 4966 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 4967 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 4968 mmu_reset_needed = 1;
4969 }
b6c7a5dc
HB		 4970
4971 if (mmu_reset_needed)
4972 kvm_mmu_reset_context(vcpu);
4973
923c61bb
GN		 4974 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4975 pending_vec = find_first_bit(
4976 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4977 if (pending_vec < max_bits) {
66fd3f7f 4978 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4979 pr_debug("Set back pending irq %d\n", pending_vec);
4980 if (irqchip_in_kernel(vcpu->kvm))
4981 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4982 }
4983
3e6e0aab
GT		 4984 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4985 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4986 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4987 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4988 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4989 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4990
3e6e0aab
GT		 4991 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4992 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4993
5f0269f5
ME		 4994 update_cr8_intercept(vcpu);
4995
9c3e4aab 4996 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4997 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 4998 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 4999 !is_protmode(vcpu))
9c3e4aab
MT		 5000 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5001
b6c7a5dc
HB		 5002 return 0;
5003}
5004
d0bfb940
JK		 5005int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5006 struct kvm_guest_debug *dbg)
b6c7a5dc 5007{
355be0b9 5008 unsigned long rflags;
ae675ef0 5009 int i, r;
b6c7a5dc 5010
4f926bf2
JK		 5011 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5012 r = -EBUSY;
5013 if (vcpu->arch.exception.pending)
2122ff5e 5014 goto out;
4f926bf2
JK		 5015 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5016 kvm_queue_exception(vcpu, DB_VECTOR);
5017 else
5018 kvm_queue_exception(vcpu, BP_VECTOR);
5019 }
5020
91586a3b
JK		 5021 /*
5022 * Read rflags as long as potentially injected trace flags are still
5023 * filtered out.
5024 */
5025 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5026
5027 vcpu->guest_debug = dbg->control;
5028 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5029 vcpu->guest_debug = 0;
5030
5031 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5032 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5033 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5034 vcpu->arch.switch_db_regs =
5035 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5036 } else {
5037 for (i = 0; i < KVM_NR_DB_REGS; i++)
5038 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5039 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5040 }
5041
f92653ee
JK		 5042 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5043 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5044 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5045
91586a3b
JK		 5046 /*
5047 * Trigger an rflags update that will inject or remove the trace
5048 * flags.
5049 */
5050 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5051
355be0b9 5052 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5053
4f926bf2 5054 r = 0;
d0bfb940 5055
2122ff5e 5056out:
b6c7a5dc
HB		 5057
5058 return r;
5059}
5060
8b006791
ZX		 5061/*
5062 * Translate a guest virtual address to a guest physical address.
5063 */
5064int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5065 struct kvm_translation *tr)
5066{
5067 unsigned long vaddr = tr->linear_address;
5068 gpa_t gpa;
f656ce01 5069 int idx;
8b006791 5070
f656ce01 5071 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5072 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5073 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5074 tr->physical_address = gpa;
5075 tr->valid = gpa != UNMAPPED_GVA;
5076 tr->writeable = 1;
5077 tr->usermode = 0;
8b006791
ZX		 5078
5079 return 0;
5080}
5081
d0752060
HB		 5082int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5083{
98918833
SY		 5084 struct i387_fxsave_struct *fxsave =
5085 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5086
d0752060
HB		 5087 memcpy(fpu->fpr, fxsave->st_space, 128);
5088 fpu->fcw = fxsave->cwd;
5089 fpu->fsw = fxsave->swd;
5090 fpu->ftwx = fxsave->twd;
5091 fpu->last_opcode = fxsave->fop;
5092 fpu->last_ip = fxsave->rip;
5093 fpu->last_dp = fxsave->rdp;
5094 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5095
d0752060
HB		 5096 return 0;
5097}
5098
5099int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5100{
98918833
SY		 5101 struct i387_fxsave_struct *fxsave =
5102 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5103
d0752060
HB		 5104 memcpy(fxsave->st_space, fpu->fpr, 128);
5105 fxsave->cwd = fpu->fcw;
5106 fxsave->swd = fpu->fsw;
5107 fxsave->twd = fpu->ftwx;
5108 fxsave->fop = fpu->last_opcode;
5109 fxsave->rip = fpu->last_ip;
5110 fxsave->rdp = fpu->last_dp;
5111 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5112
d0752060
HB		 5113 return 0;
5114}
5115
5116void fx_init(struct kvm_vcpu *vcpu)
5117{
98918833
SY		 5118 fpu_alloc(&vcpu->arch.guest_fpu);
5119 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5120
ad312c7c 5121 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060
HB		 5122}
5123EXPORT_SYMBOL_GPL(fx_init);
5124
98918833
SY		 5125static void fx_free(struct kvm_vcpu *vcpu)
5126{
5127 fpu_free(&vcpu->arch.guest_fpu);
5128}
5129
d0752060
HB		 5130void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5131{
2608d7a1 5132 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5133 return;
5134
5135 vcpu->guest_fpu_loaded = 1;
7cf30855 5136 unlazy_fpu(current);
98918833 5137 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5138 trace_kvm_fpu(1);
d0752060 5139}
d0752060
HB		 5140
5141void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5142{
5143 if (!vcpu->guest_fpu_loaded)
5144 return;
5145
5146 vcpu->guest_fpu_loaded = 0;
98918833 5147 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5148 ++vcpu->stat.fpu_reload;
02daab21 5149 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5150 trace_kvm_fpu(0);
d0752060 5151}
e9b11c17
ZX		 5152
5153void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5154{
7f1ea208
JR		 5155 if (vcpu->arch.time_page) {
5156 kvm_release_page_dirty(vcpu->arch.time_page);
5157 vcpu->arch.time_page = NULL;
5158 }
5159
98918833 5160 fx_free(vcpu);
e9b11c17
ZX		 5161 kvm_x86_ops->vcpu_free(vcpu);
5162}
5163
5164struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5165 unsigned int id)
5166{
26e5215f
AK		 5167 return kvm_x86_ops->vcpu_create(kvm, id);
5168}
e9b11c17 5169
26e5215f
AK		 5170int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5171{
5172 int r;
e9b11c17 5173
0bed3b56 5174 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5175 vcpu_load(vcpu);
5176 r = kvm_arch_vcpu_reset(vcpu);
5177 if (r == 0)
5178 r = kvm_mmu_setup(vcpu);
5179 vcpu_put(vcpu);
5180 if (r < 0)
5181 goto free_vcpu;
5182
26e5215f 5183 return 0;
e9b11c17
ZX		 5184free_vcpu:
5185 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5186 return r;
e9b11c17
ZX		 5187}
5188
d40ccc62 5189void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5190{
5191 vcpu_load(vcpu);
5192 kvm_mmu_unload(vcpu);
5193 vcpu_put(vcpu);
5194
98918833 5195 fx_free(vcpu);
e9b11c17
ZX		 5196 kvm_x86_ops->vcpu_free(vcpu);
5197}
5198
5199int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5200{
448fa4a9
JK		 5201 vcpu->arch.nmi_pending = false;
5202 vcpu->arch.nmi_injected = false;
5203
42dbaa5a
JK		 5204 vcpu->arch.switch_db_regs = 0;
5205 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5206 vcpu->arch.dr6 = DR6_FIXED_1;
5207 vcpu->arch.dr7 = DR7_FIXED_1;
5208
e9b11c17
ZX		 5209 return kvm_x86_ops->vcpu_reset(vcpu);
5210}
5211
10474ae8 5212int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5213{
0cca7907
ZA		 5214 /*
5215 * Since this may be called from a hotplug notifcation,
5216 * we can't get the CPU frequency directly.
5217 */
5218 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5219 int cpu = raw_smp_processor_id();
5220 per_cpu(cpu_tsc_khz, cpu) = 0;
5221 }
18863bdd
AK		 5222
5223 kvm_shared_msr_cpu_online();
5224
10474ae8 5225 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5226}
5227
5228void kvm_arch_hardware_disable(void *garbage)
5229{
5230 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5231 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5232}
5233
5234int kvm_arch_hardware_setup(void)
5235{
5236 return kvm_x86_ops->hardware_setup();
5237}
5238
5239void kvm_arch_hardware_unsetup(void)
5240{
5241 kvm_x86_ops->hardware_unsetup();
5242}
5243
5244void kvm_arch_check_processor_compat(void *rtn)
5245{
5246 kvm_x86_ops->check_processor_compatibility(rtn);
5247}
5248
5249int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5250{
5251 struct page *page;
5252 struct kvm *kvm;
5253 int r;
5254
5255 BUG_ON(vcpu->kvm == NULL);
5256 kvm = vcpu->kvm;
5257
ad312c7c 5258 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5259 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5260 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5261 else
a4535290 5262 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5263
5264 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5265 if (!page) {
5266 r = -ENOMEM;
5267 goto fail;
5268 }
ad312c7c 5269 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5270
5271 r = kvm_mmu_create(vcpu);
5272 if (r < 0)
5273 goto fail_free_pio_data;
5274
5275 if (irqchip_in_kernel(kvm)) {
5276 r = kvm_create_lapic(vcpu);
5277 if (r < 0)
5278 goto fail_mmu_destroy;
5279 }
5280
890ca9ae
HY		 5281 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5282 GFP_KERNEL);
5283 if (!vcpu->arch.mce_banks) {
5284 r = -ENOMEM;
443c39bc 5285 goto fail_free_lapic;
890ca9ae
HY		 5286 }
5287 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5288
e9b11c17 5289 return 0;
443c39bc
WY		 5290fail_free_lapic:
5291 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5292fail_mmu_destroy:
5293 kvm_mmu_destroy(vcpu);
5294fail_free_pio_data:
ad312c7c 5295 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5296fail:
5297 return r;
5298}
5299
5300void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5301{
f656ce01
MT		 5302 int idx;
5303
36cb93fd 5304 kfree(vcpu->arch.mce_banks);
e9b11c17 5305 kvm_free_lapic(vcpu);
f656ce01 5306 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5307 kvm_mmu_destroy(vcpu);
f656ce01 5308 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5309 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5310}
d19a9cd2
ZX		 5311
5312struct kvm *kvm_arch_create_vm(void)
5313{
5314 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5315
5316 if (!kvm)
5317 return ERR_PTR(-ENOMEM);
5318
fef9cce0
MT		 5319 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5320 if (!kvm->arch.aliases) {
5321 kfree(kvm);
5322 return ERR_PTR(-ENOMEM);
5323 }
5324
f05e70ac 5325 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5326 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5327
5550af4d
SY		 5328 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5329 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5330
53f658b3
MT		 5331 rdtscll(kvm->arch.vm_init_tsc);
5332
d19a9cd2
ZX		 5333 return kvm;
5334}
5335
5336static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5337{
5338 vcpu_load(vcpu);
5339 kvm_mmu_unload(vcpu);
5340 vcpu_put(vcpu);
5341}
5342
5343static void kvm_free_vcpus(struct kvm *kvm)
5344{
5345 unsigned int i;
988a2cae 5346 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5347
5348 /*
5349 * Unpin any mmu pages first.
5350 */
988a2cae
GN		 5351 kvm_for_each_vcpu(i, vcpu, kvm)
5352 kvm_unload_vcpu_mmu(vcpu);
5353 kvm_for_each_vcpu(i, vcpu, kvm)
5354 kvm_arch_vcpu_free(vcpu);
5355
5356 mutex_lock(&kvm->lock);
5357 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5358 kvm->vcpus[i] = NULL;
d19a9cd2 5359
988a2cae
GN		 5360 atomic_set(&kvm->online_vcpus, 0);
5361 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5362}
5363
ad8ba2cd
SY		 5364void kvm_arch_sync_events(struct kvm *kvm)
5365{
ba4cef31 5366 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5367}
5368
d19a9cd2
ZX		 5369void kvm_arch_destroy_vm(struct kvm *kvm)
5370{
6eb55818 5371 kvm_iommu_unmap_guest(kvm);
7837699f 5372 kvm_free_pit(kvm);
d7deeeb0
ZX		 5373 kfree(kvm->arch.vpic);
5374 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5375 kvm_free_vcpus(kvm);
5376 kvm_free_physmem(kvm);
3d45830c
AK		 5377 if (kvm->arch.apic_access_page)
5378 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5379 if (kvm->arch.ept_identity_pagetable)
5380 put_page(kvm->arch.ept_identity_pagetable);
64749204 5381 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5382 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5383 kfree(kvm);
5384}
0de10343 5385
f7784b8e
MT		 5386int kvm_arch_prepare_memory_region(struct kvm *kvm,
5387 struct kvm_memory_slot *memslot,
0de10343 5388 struct kvm_memory_slot old,
f7784b8e 5389 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5390 int user_alloc)
5391{
f7784b8e 5392 int npages = memslot->npages;
0de10343
ZX		 5393
5394 /*To keep backward compatibility with older userspace,
5395 *x86 needs to hanlde !user_alloc case.
5396 */
5397 if (!user_alloc) {
5398 if (npages && !old.rmap) {
604b38ac
AA		 5399 unsigned long userspace_addr;
5400
72dc67a6 5401 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5402 userspace_addr = do_mmap(NULL, 0,
5403 npages * PAGE_SIZE,
5404 PROT_READ | PROT_WRITE,
acee3c04 5405 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5406 0);
72dc67a6 5407 up_write(&current->mm->mmap_sem);
0de10343 5408
604b38ac
AA		 5409 if (IS_ERR((void *)userspace_addr))
5410 return PTR_ERR((void *)userspace_addr);
5411
604b38ac 5412 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5413 }
5414 }
5415
f7784b8e
MT		 5416
5417 return 0;
5418}
5419
5420void kvm_arch_commit_memory_region(struct kvm *kvm,
5421 struct kvm_userspace_memory_region *mem,
5422 struct kvm_memory_slot old,
5423 int user_alloc)
5424{
5425
5426 int npages = mem->memory_size >> PAGE_SHIFT;
5427
5428 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5429 int ret;
5430
5431 down_write(&current->mm->mmap_sem);
5432 ret = do_munmap(current->mm, old.userspace_addr,
5433 old.npages * PAGE_SIZE);
5434 up_write(&current->mm->mmap_sem);
5435 if (ret < 0)
5436 printk(KERN_WARNING
5437 "kvm_vm_ioctl_set_memory_region: "
5438 "failed to munmap memory\n");
5439 }
5440
7c8a83b7 5441 spin_lock(&kvm->mmu_lock);
f05e70ac 5442 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5443 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5444 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5445 }
5446
5447 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5448 spin_unlock(&kvm->mmu_lock);
0de10343 5449}
1d737c8a 5450
34d4cb8f
MT		 5451void kvm_arch_flush_shadow(struct kvm *kvm)
5452{
5453 kvm_mmu_zap_all(kvm);
8986ecc0 5454 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5455}
5456
1d737c8a
ZX		 5457int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5458{
a4535290 5459 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5460 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5461 || vcpu->arch.nmi_pending ||
5462 (kvm_arch_interrupt_allowed(vcpu) &&
5463 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5464}
5736199a 5465
5736199a
ZX		 5466void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5467{
32f88400
MT		 5468 int me;
5469 int cpu = vcpu->cpu;
5736199a
ZX		 5470
5471 if (waitqueue_active(&vcpu->wq)) {
5472 wake_up_interruptible(&vcpu->wq);
5473 ++vcpu->stat.halt_wakeup;
5474 }
32f88400
MT		 5475
5476 me = get_cpu();
5477 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 5478 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 5479 smp_send_reschedule(cpu);
e9571ed5 5480 put_cpu();
5736199a 5481}
78646121
GN		 5482
5483int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5484{
5485 return kvm_x86_ops->interrupt_allowed(vcpu);
5486}
229456fc 5487
f92653ee
JK		 5488bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5489{
5490 unsigned long current_rip = kvm_rip_read(vcpu) +
5491 get_segment_base(vcpu, VCPU_SREG_CS);
5492
5493 return current_rip == linear_rip;
5494}
5495EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5496
94fe45da
JK		 5497unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5498{
5499 unsigned long rflags;
5500
5501 rflags = kvm_x86_ops->get_rflags(vcpu);
5502 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5503 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5504 return rflags;
5505}
5506EXPORT_SYMBOL_GPL(kvm_get_rflags);
5507
5508void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5509{
5510 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5511 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5512 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5513 kvm_x86_ops->set_rflags(vcpu, rflags);
5514}
5515EXPORT_SYMBOL_GPL(kvm_set_rflags);
5516
229456fc
MT		 5517EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5518EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5519EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5520EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5521EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5522EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5523EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5524EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5525EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5526EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5527EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5528EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux 6.x block layer and io_uring tree(s)