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KVM: Replace reads of vcpu->arch.cr3 by an accessor
[linux-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
a03490ed
CO		 63#define CR0_RESERVED_BITS \
64 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
65 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
66 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
67#define CR4_RESERVED_BITS \
68 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
69 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
70 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 71 | X86_CR4_OSXSAVE \
a03490ed
CO		 72 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
73
74#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 75
76#define KVM_MAX_MCE_BANKS 32
5854dbca 77#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 78
50a37eb4
JR		 79/* EFER defaults:
80 * - enable syscall per default because its emulated by KVM
81 * - enable LME and LMA per default on 64 bit KVM
82 */
83#ifdef CONFIG_X86_64
84static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
85#else
86static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 93static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
94 struct kvm_cpuid_entry2 __user *entries);
95
97896d04 96struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
ed85c068
AP		 99int ignore_msrs = 0;
100module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
101
18863bdd
AK		 102#define KVM_NR_SHARED_MSRS 16
103
104struct kvm_shared_msrs_global {
105 int nr;
2bf78fa7 106 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 107};
108
109struct kvm_shared_msrs {
110 struct user_return_notifier urn;
111 bool registered;
2bf78fa7
SY		 112 struct kvm_shared_msr_values {
113 u64 host;
114 u64 curr;
115 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 116};
117
118static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
119static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
120
417bc304 121struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 122 { "pf_fixed", VCPU_STAT(pf_fixed) },
123 { "pf_guest", VCPU_STAT(pf_guest) },
124 { "tlb_flush", VCPU_STAT(tlb_flush) },
125 { "invlpg", VCPU_STAT(invlpg) },
126 { "exits", VCPU_STAT(exits) },
127 { "io_exits", VCPU_STAT(io_exits) },
128 { "mmio_exits", VCPU_STAT(mmio_exits) },
129 { "signal_exits", VCPU_STAT(signal_exits) },
130 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 131 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 132 { "halt_exits", VCPU_STAT(halt_exits) },
133 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 134 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 135 { "request_irq", VCPU_STAT(request_irq_exits) },
136 { "irq_exits", VCPU_STAT(irq_exits) },
137 { "host_state_reload", VCPU_STAT(host_state_reload) },
138 { "efer_reload", VCPU_STAT(efer_reload) },
139 { "fpu_reload", VCPU_STAT(fpu_reload) },
140 { "insn_emulation", VCPU_STAT(insn_emulation) },
141 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 142 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 143 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 144 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
145 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
146 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
147 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
148 { "mmu_flooded", VM_STAT(mmu_flooded) },
149 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 150 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 151 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 152 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 153 { "largepages", VM_STAT(lpages) },
417bc304
HB		 154 { NULL }
155};
156
2acf923e
DC		 157u64 __read_mostly host_xcr0;
158
af585b92
GN		 159static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
160{
161 int i;
162 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
163 vcpu->arch.apf.gfns[i] = ~0;
164}
165
18863bdd
AK		 166static void kvm_on_user_return(struct user_return_notifier *urn)
167{
168 unsigned slot;
18863bdd
AK		 169 struct kvm_shared_msrs *locals
170 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 171 struct kvm_shared_msr_values *values;
18863bdd
AK		 172
173 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 174 values = &locals->values[slot];
175 if (values->host != values->curr) {
176 wrmsrl(shared_msrs_global.msrs[slot], values->host);
177 values->curr = values->host;
18863bdd
AK		 178 }
179 }
180 locals->registered = false;
181 user_return_notifier_unregister(urn);
182}
183
2bf78fa7 184static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 185{
2bf78fa7 186 struct kvm_shared_msrs *smsr;
18863bdd
AK		 187 u64 value;
188
2bf78fa7
SY		 189 smsr = &__get_cpu_var(shared_msrs);
190 /* only read, and nobody should modify it at this time,
191 * so don't need lock */
192 if (slot >= shared_msrs_global.nr) {
193 printk(KERN_ERR "kvm: invalid MSR slot!");
194 return;
195 }
196 rdmsrl_safe(msr, &value);
197 smsr->values[slot].host = value;
198 smsr->values[slot].curr = value;
199}
200
201void kvm_define_shared_msr(unsigned slot, u32 msr)
202{
18863bdd
AK		 203 if (slot >= shared_msrs_global.nr)
204 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 205 shared_msrs_global.msrs[slot] = msr;
206 /* we need ensured the shared_msr_global have been updated */
207 smp_wmb();
18863bdd
AK		 208}
209EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
210
211static void kvm_shared_msr_cpu_online(void)
212{
213 unsigned i;
18863bdd
AK		 214
215 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 216 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 217}
218
d5696725 219void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
2bf78fa7 223 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 224 return;
2bf78fa7
SY		 225 smsr->values[slot].curr = value;
226 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 227 if (!smsr->registered) {
228 smsr->urn.on_user_return = kvm_on_user_return;
229 user_return_notifier_register(&smsr->urn);
230 smsr->registered = true;
231 }
232}
233EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
234
3548bab5
AK		 235static void drop_user_return_notifiers(void *ignore)
236{
237 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
238
239 if (smsr->registered)
240 kvm_on_user_return(&smsr->urn);
241}
242
6866b83e
CO		 243u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
244{
245 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e 247 else
ad312c7c 248 return vcpu->arch.apic_base;
6866b83e
CO		 249}
250EXPORT_SYMBOL_GPL(kvm_get_apic_base);
251
252void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
253{
254 /* TODO: reserve bits check */
255 if (irqchip_in_kernel(vcpu->kvm))
256 kvm_lapic_set_base(vcpu, data);
257 else
ad312c7c 258 vcpu->arch.apic_base = data;
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_set_apic_base);
261
3fd28fce
ED		 262#define EXCPT_BENIGN 0
263#define EXCPT_CONTRIBUTORY 1
264#define EXCPT_PF 2
265
266static int exception_class(int vector)
267{
268 switch (vector) {
269 case PF_VECTOR:
270 return EXCPT_PF;
271 case DE_VECTOR:
272 case TS_VECTOR:
273 case NP_VECTOR:
274 case SS_VECTOR:
275 case GP_VECTOR:
276 return EXCPT_CONTRIBUTORY;
277 default:
278 break;
279 }
280 return EXCPT_BENIGN;
281}
282
283static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 284 unsigned nr, bool has_error, u32 error_code,
285 bool reinject)
3fd28fce
ED		 286{
287 u32 prev_nr;
288 int class1, class2;
289
3842d135
AK		 290 kvm_make_request(KVM_REQ_EVENT, vcpu);
291
3fd28fce
ED		 292 if (!vcpu->arch.exception.pending) {
293 queue:
294 vcpu->arch.exception.pending = true;
295 vcpu->arch.exception.has_error_code = has_error;
296 vcpu->arch.exception.nr = nr;
297 vcpu->arch.exception.error_code = error_code;
3f0fd292 298 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 299 return;
300 }
301
302 /* to check exception */
303 prev_nr = vcpu->arch.exception.nr;
304 if (prev_nr == DF_VECTOR) {
305 /* triple fault -> shutdown */
a8eeb04a 306 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 307 return;
308 }
309 class1 = exception_class(prev_nr);
310 class2 = exception_class(nr);
311 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
312 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
313 /* generate double fault per SDM Table 5-5 */
314 vcpu->arch.exception.pending = true;
315 vcpu->arch.exception.has_error_code = true;
316 vcpu->arch.exception.nr = DF_VECTOR;
317 vcpu->arch.exception.error_code = 0;
318 } else
319 /* replace previous exception with a new one in a hope
320 that instruction re-execution will regenerate lost
321 exception */
322 goto queue;
323}
324
298101da
AK		 325void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
326{
ce7ddec4 327 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 328}
329EXPORT_SYMBOL_GPL(kvm_queue_exception);
330
ce7ddec4
JR		 331void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
333 kvm_multiple_exception(vcpu, nr, false, 0, true);
334}
335EXPORT_SYMBOL_GPL(kvm_requeue_exception);
336
db8fcefa
AP		 337void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
338{
339 if (err)
340 kvm_inject_gp(vcpu, 0);
341 else
342 kvm_x86_ops->skip_emulated_instruction(vcpu);
343}
344EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
345
6389ee94 346void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 347{
348 ++vcpu->stat.pf_guest;
6389ee94
AK		 349 vcpu->arch.cr2 = fault->address;
350 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee
AK		 351}
352
6389ee94 353void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 354{
6389ee94
AK		 355 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
356 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 357 else
6389ee94 358 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 359}
360
3419ffc8
SY		 361void kvm_inject_nmi(struct kvm_vcpu *vcpu)
362{
3842d135 363 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419ffc8
SY		 364 vcpu->arch.nmi_pending = 1;
365}
366EXPORT_SYMBOL_GPL(kvm_inject_nmi);
367
298101da
AK		 368void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
369{
ce7ddec4 370 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 371}
372EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
373
ce7ddec4
JR		 374void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
375{
376 kvm_multiple_exception(vcpu, nr, true, error_code, true);
377}
378EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
379
0a79b009
AK		 380/*
381 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
382 * a #GP and return false.
383 */
384bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 385{
0a79b009
AK		 386 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
387 return true;
388 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
389 return false;
298101da 390}
0a79b009 391EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 392
ec92fe44
JR		 393/*
394 * This function will be used to read from the physical memory of the currently
395 * running guest. The difference to kvm_read_guest_page is that this function
396 * can read from guest physical or from the guest's guest physical memory.
397 */
398int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
399 gfn_t ngfn, void *data, int offset, int len,
400 u32 access)
401{
402 gfn_t real_gfn;
403 gpa_t ngpa;
404
405 ngpa = gfn_to_gpa(ngfn);
406 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
407 if (real_gfn == UNMAPPED_GVA)
408 return -EFAULT;
409
410 real_gfn = gpa_to_gfn(real_gfn);
411
412 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
413}
414EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
415
3d06b8bf
JR		 416int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
417 void *data, int offset, int len, u32 access)
418{
419 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
420 data, offset, len, access);
421}
422
a03490ed
CO		 423/*
424 * Load the pae pdptrs. Return true is they are all valid.
425 */
ff03a073 426int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 427{
428 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
429 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
430 int i;
431 int ret;
ff03a073 432 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 433
ff03a073
JR		 434 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
435 offset * sizeof(u64), sizeof(pdpte),
436 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 437 if (ret < 0) {
438 ret = 0;
439 goto out;
440 }
441 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 442 if (is_present_gpte(pdpte[i]) &&
20c466b5 443 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 444 ret = 0;
445 goto out;
446 }
447 }
448 ret = 1;
449
ff03a073 450 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 451 __set_bit(VCPU_EXREG_PDPTR,
452 (unsigned long *)&vcpu->arch.regs_avail);
453 __set_bit(VCPU_EXREG_PDPTR,
454 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 455out:
a03490ed
CO		 456
457 return ret;
458}
cc4b6871 459EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 460
d835dfec
AK		 461static bool pdptrs_changed(struct kvm_vcpu *vcpu)
462{
ff03a073 463 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 464 bool changed = true;
3d06b8bf
JR		 465 int offset;
466 gfn_t gfn;
d835dfec
AK		 467 int r;
468
469 if (is_long_mode(vcpu) || !is_pae(vcpu))
470 return false;
471
6de4f3ad
AK		 472 if (!test_bit(VCPU_EXREG_PDPTR,
473 (unsigned long *)&vcpu->arch.regs_avail))
474 return true;
475
9f8fe504
AK		 476 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
477 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 478 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
479 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 480 if (r < 0)
481 goto out;
ff03a073 482 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 483out:
d835dfec
AK		 484
485 return changed;
486}
487
49a9b07e 488int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 489{
aad82703
SY		 490 unsigned long old_cr0 = kvm_read_cr0(vcpu);
491 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
492 X86_CR0_CD | X86_CR0_NW;
493
f9a48e6a
AK		 494 cr0 |= X86_CR0_ET;
495
ab344828 496#ifdef CONFIG_X86_64
0f12244f
GN		 497 if (cr0 & 0xffffffff00000000UL)
498 return 1;
ab344828
GN		 499#endif
500
501 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 502
0f12244f
GN		 503 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
504 return 1;
a03490ed 505
0f12244f
GN		 506 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
507 return 1;
a03490ed
CO		 508
509 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
510#ifdef CONFIG_X86_64
f6801dff 511 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 512 int cs_db, cs_l;
513
0f12244f
GN		 514 if (!is_pae(vcpu))
515 return 1;
a03490ed 516 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 517 if (cs_l)
518 return 1;
a03490ed
CO		 519 } else
520#endif
ff03a073 521 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 522 kvm_read_cr3(vcpu)))
0f12244f 523 return 1;
a03490ed
CO		 524 }
525
526 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 527
e5f3f027
XG		 528 if ((cr0 ^ old_cr0) & X86_CR0_PG)
529 kvm_clear_async_pf_completion_queue(vcpu);
530
aad82703
SY		 531 if ((cr0 ^ old_cr0) & update_bits)
532 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 533 return 0;
534}
2d3ad1f4 535EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 536
2d3ad1f4 537void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 538{
49a9b07e 539 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 540}
2d3ad1f4 541EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 542
2acf923e
DC		 543int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
544{
545 u64 xcr0;
546
547 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
548 if (index != XCR_XFEATURE_ENABLED_MASK)
549 return 1;
550 xcr0 = xcr;
551 if (kvm_x86_ops->get_cpl(vcpu) != 0)
552 return 1;
553 if (!(xcr0 & XSTATE_FP))
554 return 1;
555 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
556 return 1;
557 if (xcr0 & ~host_xcr0)
558 return 1;
559 vcpu->arch.xcr0 = xcr0;
560 vcpu->guest_xcr0_loaded = 0;
561 return 0;
562}
563
564int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
565{
566 if (__kvm_set_xcr(vcpu, index, xcr)) {
567 kvm_inject_gp(vcpu, 0);
568 return 1;
569 }
570 return 0;
571}
572EXPORT_SYMBOL_GPL(kvm_set_xcr);
573
574static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
575{
576 struct kvm_cpuid_entry2 *best;
577
578 best = kvm_find_cpuid_entry(vcpu, 1, 0);
579 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
580}
581
582static void update_cpuid(struct kvm_vcpu *vcpu)
583{
584 struct kvm_cpuid_entry2 *best;
585
586 best = kvm_find_cpuid_entry(vcpu, 1, 0);
587 if (!best)
588 return;
589
590 /* Update OSXSAVE bit */
591 if (cpu_has_xsave && best->function == 0x1) {
592 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
593 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
594 best->ecx |= bit(X86_FEATURE_OSXSAVE);
595 }
596}
597
a83b29c6 598int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 599{
fc78f519 600 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 601 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
602
0f12244f
GN		 603 if (cr4 & CR4_RESERVED_BITS)
604 return 1;
a03490ed 605
2acf923e
DC		 606 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
607 return 1;
608
a03490ed 609 if (is_long_mode(vcpu)) {
0f12244f
GN		 610 if (!(cr4 & X86_CR4_PAE))
611 return 1;
a2edf57f
AK		 612 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
613 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 614 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
615 kvm_read_cr3(vcpu)))
0f12244f
GN		 616 return 1;
617
618 if (cr4 & X86_CR4_VMXE)
619 return 1;
a03490ed 620
a03490ed 621 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 622
aad82703
SY		 623 if ((cr4 ^ old_cr4) & pdptr_bits)
624 kvm_mmu_reset_context(vcpu);
0f12244f 625
2acf923e
DC		 626 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
627 update_cpuid(vcpu);
628
0f12244f
GN		 629 return 0;
630}
2d3ad1f4 631EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 632
2390218b 633int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 634{
9f8fe504 635 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 636 kvm_mmu_sync_roots(vcpu);
d835dfec 637 kvm_mmu_flush_tlb(vcpu);
0f12244f 638 return 0;
d835dfec
AK		 639 }
640
a03490ed 641 if (is_long_mode(vcpu)) {
0f12244f
GN		 642 if (cr3 & CR3_L_MODE_RESERVED_BITS)
643 return 1;
a03490ed
CO		 644 } else {
645 if (is_pae(vcpu)) {
0f12244f
GN		 646 if (cr3 & CR3_PAE_RESERVED_BITS)
647 return 1;
ff03a073
JR		 648 if (is_paging(vcpu) &&
649 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 650 return 1;
a03490ed
CO		 651 }
652 /*
653 * We don't check reserved bits in nonpae mode, because
654 * this isn't enforced, and VMware depends on this.
655 */
656 }
657
a03490ed
CO		 658 /*
659 * Does the new cr3 value map to physical memory? (Note, we
660 * catch an invalid cr3 even in real-mode, because it would
661 * cause trouble later on when we turn on paging anyway.)
662 *
663 * A real CPU would silently accept an invalid cr3 and would
664 * attempt to use it - with largely undefined (and often hard
665 * to debug) behavior on the guest side.
666 */
667 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 668 return 1;
669 vcpu->arch.cr3 = cr3;
670 vcpu->arch.mmu.new_cr3(vcpu);
671 return 0;
672}
2d3ad1f4 673EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 674
eea1cff9 675int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 676{
0f12244f
GN		 677 if (cr8 & CR8_RESERVED_BITS)
678 return 1;
a03490ed
CO		 679 if (irqchip_in_kernel(vcpu->kvm))
680 kvm_lapic_set_tpr(vcpu, cr8);
681 else
ad312c7c 682 vcpu->arch.cr8 = cr8;
0f12244f
GN		 683 return 0;
684}
2d3ad1f4 685EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 686
2d3ad1f4 687unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 688{
689 if (irqchip_in_kernel(vcpu->kvm))
690 return kvm_lapic_get_cr8(vcpu);
691 else
ad312c7c 692 return vcpu->arch.cr8;
a03490ed 693}
2d3ad1f4 694EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 695
338dbc97 696static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 697{
698 switch (dr) {
699 case 0 ... 3:
700 vcpu->arch.db[dr] = val;
701 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
702 vcpu->arch.eff_db[dr] = val;
703 break;
704 case 4:
338dbc97
GN		 705 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
706 return 1; /* #UD */
020df079
GN		 707 /* fall through */
708 case 6:
338dbc97
GN		 709 if (val & 0xffffffff00000000ULL)
710 return -1; /* #GP */
020df079
GN		 711 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
712 break;
713 case 5:
338dbc97
GN		 714 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
715 return 1; /* #UD */
020df079
GN		 716 /* fall through */
717 default: /* 7 */
338dbc97
GN		 718 if (val & 0xffffffff00000000ULL)
719 return -1; /* #GP */
020df079
GN		 720 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
721 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
722 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
723 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
724 }
725 break;
726 }
727
728 return 0;
729}
338dbc97
GN		 730
731int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
732{
733 int res;
734
735 res = __kvm_set_dr(vcpu, dr, val);
736 if (res > 0)
737 kvm_queue_exception(vcpu, UD_VECTOR);
738 else if (res < 0)
739 kvm_inject_gp(vcpu, 0);
740
741 return res;
742}
020df079
GN		 743EXPORT_SYMBOL_GPL(kvm_set_dr);
744
338dbc97 745static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 746{
747 switch (dr) {
748 case 0 ... 3:
749 *val = vcpu->arch.db[dr];
750 break;
751 case 4:
338dbc97 752 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 753 return 1;
020df079
GN		 754 /* fall through */
755 case 6:
756 *val = vcpu->arch.dr6;
757 break;
758 case 5:
338dbc97 759 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 760 return 1;
020df079
GN		 761 /* fall through */
762 default: /* 7 */
763 *val = vcpu->arch.dr7;
764 break;
765 }
766
767 return 0;
768}
338dbc97
GN		 769
770int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
771{
772 if (_kvm_get_dr(vcpu, dr, val)) {
773 kvm_queue_exception(vcpu, UD_VECTOR);
774 return 1;
775 }
776 return 0;
777}
020df079
GN		 778EXPORT_SYMBOL_GPL(kvm_get_dr);
779
043405e1
CO		 780/*
781 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
782 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
783 *
784 * This list is modified at module load time to reflect the
e3267cbb
GC		 785 * capabilities of the host cpu. This capabilities test skips MSRs that are
786 * kvm-specific. Those are put in the beginning of the list.
043405e1 787 */
e3267cbb 788
344d9588 789#define KVM_SAVE_MSRS_BEGIN 8
043405e1 790static u32 msrs_to_save[] = {
e3267cbb 791 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 792 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 793 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 794 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 795 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 796 MSR_STAR,
043405e1
CO		 797#ifdef CONFIG_X86_64
798 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
799#endif
e90aa41e 800 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 801};
802
803static unsigned num_msrs_to_save;
804
805static u32 emulated_msrs[] = {
806 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 807 MSR_IA32_MCG_STATUS,
808 MSR_IA32_MCG_CTL,
043405e1
CO		 809};
810
b69e8cae 811static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 812{
aad82703
SY		 813 u64 old_efer = vcpu->arch.efer;
814
b69e8cae
RJ		 815 if (efer & efer_reserved_bits)
816 return 1;
15c4a640
CO		 817
818 if (is_paging(vcpu)
b69e8cae
RJ		 819 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
820 return 1;
15c4a640 821
1b2fd70c
AG		 822 if (efer & EFER_FFXSR) {
823 struct kvm_cpuid_entry2 *feat;
824
825 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 826 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
827 return 1;
1b2fd70c
AG		 828 }
829
d8017474
AG		 830 if (efer & EFER_SVME) {
831 struct kvm_cpuid_entry2 *feat;
832
833 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 834 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
835 return 1;
d8017474
AG		 836 }
837
15c4a640 838 efer &= ~EFER_LMA;
f6801dff 839 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 840
a3d204e2
SY		 841 kvm_x86_ops->set_efer(vcpu, efer);
842
9645bb56 843 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 844
aad82703
SY		 845 /* Update reserved bits */
846 if ((efer ^ old_efer) & EFER_NX)
847 kvm_mmu_reset_context(vcpu);
848
b69e8cae 849 return 0;
15c4a640
CO		 850}
851
f2b4b7dd
JR		 852void kvm_enable_efer_bits(u64 mask)
853{
854 efer_reserved_bits &= ~mask;
855}
856EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
857
858
15c4a640
CO		 859/*
860 * Writes msr value into into the appropriate "register".
861 * Returns 0 on success, non-0 otherwise.
862 * Assumes vcpu_load() was already called.
863 */
864int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
865{
866 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
867}
868
313a3dc7
CO		 869/*
870 * Adapt set_msr() to msr_io()'s calling convention
871 */
872static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
873{
874 return kvm_set_msr(vcpu, index, *data);
875}
876
18068523
GOC		 877static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
878{
9ed3c444
AK		 879 int version;
880 int r;
50d0a0f9 881 struct pvclock_wall_clock wc;
923de3cf 882 struct timespec boot;
18068523
GOC		 883
884 if (!wall_clock)
885 return;
886
9ed3c444
AK		 887 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
888 if (r)
889 return;
890
891 if (version & 1)
892 ++version; /* first time write, random junk */
893
894 ++version;
18068523 895
18068523
GOC		 896 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
897
50d0a0f9
GH		 898 /*
899 * The guest calculates current wall clock time by adding
34c238a1 900 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 901 * wall clock specified here. guest system time equals host
902 * system time for us, thus we must fill in host boot time here.
903 */
923de3cf 904 getboottime(&boot);
50d0a0f9
GH		 905
906 wc.sec = boot.tv_sec;
907 wc.nsec = boot.tv_nsec;
908 wc.version = version;
18068523
GOC		 909
910 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
911
912 version++;
913 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 914}
915
50d0a0f9
GH		 916static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
917{
918 uint32_t quotient, remainder;
919
920 /* Don't try to replace with do_div(), this one calculates
921 * "(dividend << 32) / divisor" */
922 __asm__ ( "divl %4"
923 : "=a" (quotient), "=d" (remainder)
924 : "0" (0), "1" (dividend), "r" (divisor) );
925 return quotient;
926}
927
5f4e3f88
ZA		 928static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
929 s8 *pshift, u32 *pmultiplier)
50d0a0f9 930{
5f4e3f88 931 uint64_t scaled64;
50d0a0f9
GH		 932 int32_t shift = 0;
933 uint64_t tps64;
934 uint32_t tps32;
935
5f4e3f88
ZA		 936 tps64 = base_khz * 1000LL;
937 scaled64 = scaled_khz * 1000LL;
50933623 938 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 939 tps64 >>= 1;
940 shift--;
941 }
942
943 tps32 = (uint32_t)tps64;
50933623
JK		 944 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
945 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 946 scaled64 >>= 1;
947 else
948 tps32 <<= 1;
50d0a0f9
GH		 949 shift++;
950 }
951
5f4e3f88
ZA		 952 *pshift = shift;
953 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 954
5f4e3f88
ZA		 955 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
956 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 957}
958
759379dd
ZA		 959static inline u64 get_kernel_ns(void)
960{
961 struct timespec ts;
962
963 WARN_ON(preemptible());
964 ktime_get_ts(&ts);
965 monotonic_to_bootbased(&ts);
966 return timespec_to_ns(&ts);
50d0a0f9
GH		 967}
968
c8076604 969static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 970unsigned long max_tsc_khz;
c8076604 971
8cfdc000
ZA		 972static inline int kvm_tsc_changes_freq(void)
973{
974 int cpu = get_cpu();
975 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
976 cpufreq_quick_get(cpu) != 0;
977 put_cpu();
978 return ret;
979}
980
759379dd
ZA		 981static inline u64 nsec_to_cycles(u64 nsec)
982{
217fc9cf
AK		 983 u64 ret;
984
759379dd
ZA		 985 WARN_ON(preemptible());
986 if (kvm_tsc_changes_freq())
987 printk_once(KERN_WARNING
988 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 989 ret = nsec * __get_cpu_var(cpu_tsc_khz);
990 do_div(ret, USEC_PER_SEC);
991 return ret;
759379dd
ZA		 992}
993
c285545f
ZA		 994static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz)
995{
996 /* Compute a scale to convert nanoseconds in TSC cycles */
997 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
998 &kvm->arch.virtual_tsc_shift,
999 &kvm->arch.virtual_tsc_mult);
1000 kvm->arch.virtual_tsc_khz = this_tsc_khz;
1001}
1002
1003static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1004{
1005 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1006 vcpu->kvm->arch.virtual_tsc_mult,
1007 vcpu->kvm->arch.virtual_tsc_shift);
1008 tsc += vcpu->arch.last_tsc_write;
1009 return tsc;
1010}
1011
99e3e30a
ZA		 1012void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1013{
1014 struct kvm *kvm = vcpu->kvm;
f38e098f 1015 u64 offset, ns, elapsed;
99e3e30a 1016 unsigned long flags;
46543ba4 1017 s64 sdiff;
99e3e30a
ZA		 1018
1019 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1020 offset = data - native_read_tsc();
759379dd 1021 ns = get_kernel_ns();
f38e098f 1022 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1023 sdiff = data - kvm->arch.last_tsc_write;
1024 if (sdiff < 0)
1025 sdiff = -sdiff;
f38e098f
ZA		 1026
1027 /*
46543ba4 1028 * Special case: close write to TSC within 5 seconds of
f38e098f 1029 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1030 * The 5 seconds is to accomodate host load / swapping as
1031 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1032 *
1033 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1034 * or make a best guest using elapsed value.
f38e098f 1035 */
46543ba4
ZA		 1036 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1037 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1038 if (!check_tsc_unstable()) {
1039 offset = kvm->arch.last_tsc_offset;
1040 pr_debug("kvm: matched tsc offset for %llu\n", data);
1041 } else {
759379dd
ZA		 1042 u64 delta = nsec_to_cycles(elapsed);
1043 offset += delta;
1044 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1045 }
1046 ns = kvm->arch.last_tsc_nsec;
1047 }
1048 kvm->arch.last_tsc_nsec = ns;
1049 kvm->arch.last_tsc_write = data;
1050 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1051 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1052 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1053
1054 /* Reset of TSC must disable overshoot protection below */
1055 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1056 vcpu->arch.last_tsc_write = data;
1057 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1058}
1059EXPORT_SYMBOL_GPL(kvm_write_tsc);
1060
34c238a1 1061static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1062{
18068523
GOC		 1063 unsigned long flags;
1064 struct kvm_vcpu_arch *vcpu = &v->arch;
1065 void *shared_kaddr;
463656c0 1066 unsigned long this_tsc_khz;
1d5f066e
ZA		 1067 s64 kernel_ns, max_kernel_ns;
1068 u64 tsc_timestamp;
18068523 1069
18068523
GOC		 1070 /* Keep irq disabled to prevent changes to the clock */
1071 local_irq_save(flags);
1d5f066e 1072 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1073 kernel_ns = get_kernel_ns();
8cfdc000 1074 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523 1075
8cfdc000 1076 if (unlikely(this_tsc_khz == 0)) {
c285545f 1077 local_irq_restore(flags);
34c238a1 1078 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1079 return 1;
1080 }
18068523 1081
c285545f
ZA		 1082 /*
1083 * We may have to catch up the TSC to match elapsed wall clock
1084 * time for two reasons, even if kvmclock is used.
1085 * 1) CPU could have been running below the maximum TSC rate
1086 * 2) Broken TSC compensation resets the base at each VCPU
1087 * entry to avoid unknown leaps of TSC even when running
1088 * again on the same CPU. This may cause apparent elapsed
1089 * time to disappear, and the guest to stand still or run
1090 * very slowly.
1091 */
1092 if (vcpu->tsc_catchup) {
1093 u64 tsc = compute_guest_tsc(v, kernel_ns);
1094 if (tsc > tsc_timestamp) {
1095 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1096 tsc_timestamp = tsc;
1097 }
50d0a0f9
GH		 1098 }
1099
18068523
GOC		 1100 local_irq_restore(flags);
1101
c285545f
ZA		 1102 if (!vcpu->time_page)
1103 return 0;
18068523 1104
1d5f066e
ZA		 1105 /*
1106 * Time as measured by the TSC may go backwards when resetting the base
1107 * tsc_timestamp. The reason for this is that the TSC resolution is
1108 * higher than the resolution of the other clock scales. Thus, many
1109 * possible measurments of the TSC correspond to one measurement of any
1110 * other clock, and so a spread of values is possible. This is not a
1111 * problem for the computation of the nanosecond clock; with TSC rates
1112 * around 1GHZ, there can only be a few cycles which correspond to one
1113 * nanosecond value, and any path through this code will inevitably
1114 * take longer than that. However, with the kernel_ns value itself,
1115 * the precision may be much lower, down to HZ granularity. If the
1116 * first sampling of TSC against kernel_ns ends in the low part of the
1117 * range, and the second in the high end of the range, we can get:
1118 *
1119 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1120 *
1121 * As the sampling errors potentially range in the thousands of cycles,
1122 * it is possible such a time value has already been observed by the
1123 * guest. To protect against this, we must compute the system time as
1124 * observed by the guest and ensure the new system time is greater.
1125 */
1126 max_kernel_ns = 0;
1127 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1128 max_kernel_ns = vcpu->last_guest_tsc -
1129 vcpu->hv_clock.tsc_timestamp;
1130 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1131 vcpu->hv_clock.tsc_to_system_mul,
1132 vcpu->hv_clock.tsc_shift);
1133 max_kernel_ns += vcpu->last_kernel_ns;
1134 }
afbcf7ab 1135
e48672fa 1136 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1137 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1138 &vcpu->hv_clock.tsc_shift,
1139 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1140 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1141 }
1142
1d5f066e
ZA		 1143 if (max_kernel_ns > kernel_ns)
1144 kernel_ns = max_kernel_ns;
1145
8cfdc000 1146 /* With all the info we got, fill in the values */
1d5f066e 1147 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1148 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1149 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1150 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1151 vcpu->hv_clock.flags = 0;
1152
18068523
GOC		 1153 /*
1154 * The interface expects us to write an even number signaling that the
1155 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1156 * state, we just increase by 2 at the end.
18068523 1157 */
50d0a0f9 1158 vcpu->hv_clock.version += 2;
18068523
GOC		 1159
1160 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1161
1162 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1163 sizeof(vcpu->hv_clock));
18068523
GOC		 1164
1165 kunmap_atomic(shared_kaddr, KM_USER0);
1166
1167 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1168 return 0;
c8076604
GH		 1169}
1170
9ba075a6
AK		 1171static bool msr_mtrr_valid(unsigned msr)
1172{
1173 switch (msr) {
1174 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1175 case MSR_MTRRfix64K_00000:
1176 case MSR_MTRRfix16K_80000:
1177 case MSR_MTRRfix16K_A0000:
1178 case MSR_MTRRfix4K_C0000:
1179 case MSR_MTRRfix4K_C8000:
1180 case MSR_MTRRfix4K_D0000:
1181 case MSR_MTRRfix4K_D8000:
1182 case MSR_MTRRfix4K_E0000:
1183 case MSR_MTRRfix4K_E8000:
1184 case MSR_MTRRfix4K_F0000:
1185 case MSR_MTRRfix4K_F8000:
1186 case MSR_MTRRdefType:
1187 case MSR_IA32_CR_PAT:
1188 return true;
1189 case 0x2f8:
1190 return true;
1191 }
1192 return false;
1193}
1194
d6289b93
MT		 1195static bool valid_pat_type(unsigned t)
1196{
1197 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1198}
1199
1200static bool valid_mtrr_type(unsigned t)
1201{
1202 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1203}
1204
1205static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1206{
1207 int i;
1208
1209 if (!msr_mtrr_valid(msr))
1210 return false;
1211
1212 if (msr == MSR_IA32_CR_PAT) {
1213 for (i = 0; i < 8; i++)
1214 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1215 return false;
1216 return true;
1217 } else if (msr == MSR_MTRRdefType) {
1218 if (data & ~0xcff)
1219 return false;
1220 return valid_mtrr_type(data & 0xff);
1221 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1222 for (i = 0; i < 8 ; i++)
1223 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1224 return false;
1225 return true;
1226 }
1227
1228 /* variable MTRRs */
1229 return valid_mtrr_type(data & 0xff);
1230}
1231
9ba075a6
AK		 1232static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1233{
0bed3b56
SY		 1234 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1235
d6289b93 1236 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1237 return 1;
1238
0bed3b56
SY		 1239 if (msr == MSR_MTRRdefType) {
1240 vcpu->arch.mtrr_state.def_type = data;
1241 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1242 } else if (msr == MSR_MTRRfix64K_00000)
1243 p[0] = data;
1244 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1245 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1246 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1247 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1248 else if (msr == MSR_IA32_CR_PAT)
1249 vcpu->arch.pat = data;
1250 else { /* Variable MTRRs */
1251 int idx, is_mtrr_mask;
1252 u64 *pt;
1253
1254 idx = (msr - 0x200) / 2;
1255 is_mtrr_mask = msr - 0x200 - 2 * idx;
1256 if (!is_mtrr_mask)
1257 pt =
1258 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1259 else
1260 pt =
1261 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1262 *pt = data;
1263 }
1264
1265 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1266 return 0;
1267}
15c4a640 1268
890ca9ae 1269static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1270{
890ca9ae
HY		 1271 u64 mcg_cap = vcpu->arch.mcg_cap;
1272 unsigned bank_num = mcg_cap & 0xff;
1273
15c4a640 1274 switch (msr) {
15c4a640 1275 case MSR_IA32_MCG_STATUS:
890ca9ae 1276 vcpu->arch.mcg_status = data;
15c4a640 1277 break;
c7ac679c 1278 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1279 if (!(mcg_cap & MCG_CTL_P))
1280 return 1;
1281 if (data != 0 && data != ~(u64)0)
1282 return -1;
1283 vcpu->arch.mcg_ctl = data;
1284 break;
1285 default:
1286 if (msr >= MSR_IA32_MC0_CTL &&
1287 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1288 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1289 /* only 0 or all 1s can be written to IA32_MCi_CTL
1290 * some Linux kernels though clear bit 10 in bank 4 to
1291 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1292 * this to avoid an uncatched #GP in the guest
1293 */
890ca9ae 1294 if ((offset & 0x3) == 0 &&
114be429 1295 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1296 return -1;
1297 vcpu->arch.mce_banks[offset] = data;
1298 break;
1299 }
1300 return 1;
1301 }
1302 return 0;
1303}
1304
ffde22ac
ES		 1305static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1306{
1307 struct kvm *kvm = vcpu->kvm;
1308 int lm = is_long_mode(vcpu);
1309 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1310 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1311 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1312 : kvm->arch.xen_hvm_config.blob_size_32;
1313 u32 page_num = data & ~PAGE_MASK;
1314 u64 page_addr = data & PAGE_MASK;
1315 u8 *page;
1316 int r;
1317
1318 r = -E2BIG;
1319 if (page_num >= blob_size)
1320 goto out;
1321 r = -ENOMEM;
1322 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1323 if (!page)
1324 goto out;
1325 r = -EFAULT;
1326 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1327 goto out_free;
1328 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1329 goto out_free;
1330 r = 0;
1331out_free:
1332 kfree(page);
1333out:
1334 return r;
1335}
1336
55cd8e5a
GN		 1337static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1338{
1339 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1340}
1341
1342static bool kvm_hv_msr_partition_wide(u32 msr)
1343{
1344 bool r = false;
1345 switch (msr) {
1346 case HV_X64_MSR_GUEST_OS_ID:
1347 case HV_X64_MSR_HYPERCALL:
1348 r = true;
1349 break;
1350 }
1351
1352 return r;
1353}
1354
1355static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1356{
1357 struct kvm *kvm = vcpu->kvm;
1358
1359 switch (msr) {
1360 case HV_X64_MSR_GUEST_OS_ID:
1361 kvm->arch.hv_guest_os_id = data;
1362 /* setting guest os id to zero disables hypercall page */
1363 if (!kvm->arch.hv_guest_os_id)
1364 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1365 break;
1366 case HV_X64_MSR_HYPERCALL: {
1367 u64 gfn;
1368 unsigned long addr;
1369 u8 instructions[4];
1370
1371 /* if guest os id is not set hypercall should remain disabled */
1372 if (!kvm->arch.hv_guest_os_id)
1373 break;
1374 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1375 kvm->arch.hv_hypercall = data;
1376 break;
1377 }
1378 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1379 addr = gfn_to_hva(kvm, gfn);
1380 if (kvm_is_error_hva(addr))
1381 return 1;
1382 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1383 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1384 if (copy_to_user((void __user *)addr, instructions, 4))
1385 return 1;
1386 kvm->arch.hv_hypercall = data;
1387 break;
1388 }
1389 default:
1390 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1391 "data 0x%llx\n", msr, data);
1392 return 1;
1393 }
1394 return 0;
1395}
1396
1397static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1398{
10388a07
GN		 1399 switch (msr) {
1400 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1401 unsigned long addr;
55cd8e5a 1402
10388a07
GN		 1403 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1404 vcpu->arch.hv_vapic = data;
1405 break;
1406 }
1407 addr = gfn_to_hva(vcpu->kvm, data >>
1408 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1409 if (kvm_is_error_hva(addr))
1410 return 1;
1411 if (clear_user((void __user *)addr, PAGE_SIZE))
1412 return 1;
1413 vcpu->arch.hv_vapic = data;
1414 break;
1415 }
1416 case HV_X64_MSR_EOI:
1417 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1418 case HV_X64_MSR_ICR:
1419 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1420 case HV_X64_MSR_TPR:
1421 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1422 default:
1423 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1424 "data 0x%llx\n", msr, data);
1425 return 1;
1426 }
1427
1428 return 0;
55cd8e5a
GN		 1429}
1430
344d9588
GN		 1431static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1432{
1433 gpa_t gpa = data & ~0x3f;
1434
6adba527
GN		 1435 /* Bits 2:5 are resrved, Should be zero */
1436 if (data & 0x3c)
344d9588
GN		 1437 return 1;
1438
1439 vcpu->arch.apf.msr_val = data;
1440
1441 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1442 kvm_clear_async_pf_completion_queue(vcpu);
1443 kvm_async_pf_hash_reset(vcpu);
1444 return 0;
1445 }
1446
1447 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1448 return 1;
1449
6adba527 1450 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1451 kvm_async_pf_wakeup_all(vcpu);
1452 return 0;
1453}
1454
15c4a640
CO		 1455int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1456{
1457 switch (msr) {
15c4a640 1458 case MSR_EFER:
b69e8cae 1459 return set_efer(vcpu, data);
8f1589d9
AP		 1460 case MSR_K7_HWCR:
1461 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1462 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1463 if (data != 0) {
1464 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1465 data);
1466 return 1;
1467 }
15c4a640 1468 break;
f7c6d140
AP		 1469 case MSR_FAM10H_MMIO_CONF_BASE:
1470 if (data != 0) {
1471 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1472 "0x%llx\n", data);
1473 return 1;
1474 }
15c4a640 1475 break;
c323c0e5 1476 case MSR_AMD64_NB_CFG:
c7ac679c 1477 break;
b5e2fec0
AG		 1478 case MSR_IA32_DEBUGCTLMSR:
1479 if (!data) {
1480 /* We support the non-activated case already */
1481 break;
1482 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1483 /* Values other than LBR and BTF are vendor-specific,
1484 thus reserved and should throw a #GP */
1485 return 1;
1486 }
1487 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1488 __func__, data);
1489 break;
15c4a640
CO		 1490 case MSR_IA32_UCODE_REV:
1491 case MSR_IA32_UCODE_WRITE:
61a6bd67 1492 case MSR_VM_HSAVE_PA:
6098ca93 1493 case MSR_AMD64_PATCH_LOADER:
15c4a640 1494 break;
9ba075a6
AK		 1495 case 0x200 ... 0x2ff:
1496 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1497 case MSR_IA32_APICBASE:
1498 kvm_set_apic_base(vcpu, data);
1499 break;
0105d1a5
GN		 1500 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1501 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1502 case MSR_IA32_MISC_ENABLE:
ad312c7c 1503 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1504 break;
11c6bffa 1505 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1506 case MSR_KVM_WALL_CLOCK:
1507 vcpu->kvm->arch.wall_clock = data;
1508 kvm_write_wall_clock(vcpu->kvm, data);
1509 break;
11c6bffa 1510 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1511 case MSR_KVM_SYSTEM_TIME: {
1512 if (vcpu->arch.time_page) {
1513 kvm_release_page_dirty(vcpu->arch.time_page);
1514 vcpu->arch.time_page = NULL;
1515 }
1516
1517 vcpu->arch.time = data;
c285545f 1518 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1519
1520 /* we verify if the enable bit is set... */
1521 if (!(data & 1))
1522 break;
1523
1524 /* ...but clean it before doing the actual write */
1525 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1526
18068523
GOC		 1527 vcpu->arch.time_page =
1528 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1529
1530 if (is_error_page(vcpu->arch.time_page)) {
1531 kvm_release_page_clean(vcpu->arch.time_page);
1532 vcpu->arch.time_page = NULL;
1533 }
18068523
GOC		 1534 break;
1535 }
344d9588
GN		 1536 case MSR_KVM_ASYNC_PF_EN:
1537 if (kvm_pv_enable_async_pf(vcpu, data))
1538 return 1;
1539 break;
890ca9ae
HY		 1540 case MSR_IA32_MCG_CTL:
1541 case MSR_IA32_MCG_STATUS:
1542 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1543 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1544
1545 /* Performance counters are not protected by a CPUID bit,
1546 * so we should check all of them in the generic path for the sake of
1547 * cross vendor migration.
1548 * Writing a zero into the event select MSRs disables them,
1549 * which we perfectly emulate ;-). Any other value should be at least
1550 * reported, some guests depend on them.
1551 */
1552 case MSR_P6_EVNTSEL0:
1553 case MSR_P6_EVNTSEL1:
1554 case MSR_K7_EVNTSEL0:
1555 case MSR_K7_EVNTSEL1:
1556 case MSR_K7_EVNTSEL2:
1557 case MSR_K7_EVNTSEL3:
1558 if (data != 0)
1559 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1560 "0x%x data 0x%llx\n", msr, data);
1561 break;
1562 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1563 * so we ignore writes to make it happy.
1564 */
1565 case MSR_P6_PERFCTR0:
1566 case MSR_P6_PERFCTR1:
1567 case MSR_K7_PERFCTR0:
1568 case MSR_K7_PERFCTR1:
1569 case MSR_K7_PERFCTR2:
1570 case MSR_K7_PERFCTR3:
1571 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1572 "0x%x data 0x%llx\n", msr, data);
1573 break;
84e0cefa
JS		 1574 case MSR_K7_CLK_CTL:
1575 /*
1576 * Ignore all writes to this no longer documented MSR.
1577 * Writes are only relevant for old K7 processors,
1578 * all pre-dating SVM, but a recommended workaround from
1579 * AMD for these chips. It is possible to speicify the
1580 * affected processor models on the command line, hence
1581 * the need to ignore the workaround.
1582 */
1583 break;
55cd8e5a
GN		 1584 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1585 if (kvm_hv_msr_partition_wide(msr)) {
1586 int r;
1587 mutex_lock(&vcpu->kvm->lock);
1588 r = set_msr_hyperv_pw(vcpu, msr, data);
1589 mutex_unlock(&vcpu->kvm->lock);
1590 return r;
1591 } else
1592 return set_msr_hyperv(vcpu, msr, data);
1593 break;
15c4a640 1594 default:
ffde22ac
ES		 1595 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1596 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1597 if (!ignore_msrs) {
1598 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1599 msr, data);
1600 return 1;
1601 } else {
1602 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1603 msr, data);
1604 break;
1605 }
15c4a640
CO		 1606 }
1607 return 0;
1608}
1609EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1610
1611
1612/*
1613 * Reads an msr value (of 'msr_index') into 'pdata'.
1614 * Returns 0 on success, non-0 otherwise.
1615 * Assumes vcpu_load() was already called.
1616 */
1617int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1618{
1619 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1620}
1621
9ba075a6
AK		 1622static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1623{
0bed3b56
SY		 1624 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1625
9ba075a6
AK		 1626 if (!msr_mtrr_valid(msr))
1627 return 1;
1628
0bed3b56
SY		 1629 if (msr == MSR_MTRRdefType)
1630 *pdata = vcpu->arch.mtrr_state.def_type +
1631 (vcpu->arch.mtrr_state.enabled << 10);
1632 else if (msr == MSR_MTRRfix64K_00000)
1633 *pdata = p[0];
1634 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1635 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1636 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1637 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1638 else if (msr == MSR_IA32_CR_PAT)
1639 *pdata = vcpu->arch.pat;
1640 else { /* Variable MTRRs */
1641 int idx, is_mtrr_mask;
1642 u64 *pt;
1643
1644 idx = (msr - 0x200) / 2;
1645 is_mtrr_mask = msr - 0x200 - 2 * idx;
1646 if (!is_mtrr_mask)
1647 pt =
1648 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1649 else
1650 pt =
1651 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1652 *pdata = *pt;
1653 }
1654
9ba075a6
AK		 1655 return 0;
1656}
1657
890ca9ae 1658static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1659{
1660 u64 data;
890ca9ae
HY		 1661 u64 mcg_cap = vcpu->arch.mcg_cap;
1662 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1663
1664 switch (msr) {
15c4a640
CO		 1665 case MSR_IA32_P5_MC_ADDR:
1666 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1667 data = 0;
1668 break;
15c4a640 1669 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1670 data = vcpu->arch.mcg_cap;
1671 break;
c7ac679c 1672 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1673 if (!(mcg_cap & MCG_CTL_P))
1674 return 1;
1675 data = vcpu->arch.mcg_ctl;
1676 break;
1677 case MSR_IA32_MCG_STATUS:
1678 data = vcpu->arch.mcg_status;
1679 break;
1680 default:
1681 if (msr >= MSR_IA32_MC0_CTL &&
1682 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1683 u32 offset = msr - MSR_IA32_MC0_CTL;
1684 data = vcpu->arch.mce_banks[offset];
1685 break;
1686 }
1687 return 1;
1688 }
1689 *pdata = data;
1690 return 0;
1691}
1692
55cd8e5a
GN		 1693static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1694{
1695 u64 data = 0;
1696 struct kvm *kvm = vcpu->kvm;
1697
1698 switch (msr) {
1699 case HV_X64_MSR_GUEST_OS_ID:
1700 data = kvm->arch.hv_guest_os_id;
1701 break;
1702 case HV_X64_MSR_HYPERCALL:
1703 data = kvm->arch.hv_hypercall;
1704 break;
1705 default:
1706 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1707 return 1;
1708 }
1709
1710 *pdata = data;
1711 return 0;
1712}
1713
1714static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1715{
1716 u64 data = 0;
1717
1718 switch (msr) {
1719 case HV_X64_MSR_VP_INDEX: {
1720 int r;
1721 struct kvm_vcpu *v;
1722 kvm_for_each_vcpu(r, v, vcpu->kvm)
1723 if (v == vcpu)
1724 data = r;
1725 break;
1726 }
10388a07
GN		 1727 case HV_X64_MSR_EOI:
1728 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1729 case HV_X64_MSR_ICR:
1730 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1731 case HV_X64_MSR_TPR:
1732 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1733 default:
1734 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1735 return 1;
1736 }
1737 *pdata = data;
1738 return 0;
1739}
1740
890ca9ae
HY		 1741int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1742{
1743 u64 data;
1744
1745 switch (msr) {
890ca9ae 1746 case MSR_IA32_PLATFORM_ID:
15c4a640 1747 case MSR_IA32_UCODE_REV:
15c4a640 1748 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1749 case MSR_IA32_DEBUGCTLMSR:
1750 case MSR_IA32_LASTBRANCHFROMIP:
1751 case MSR_IA32_LASTBRANCHTOIP:
1752 case MSR_IA32_LASTINTFROMIP:
1753 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1754 case MSR_K8_SYSCFG:
1755 case MSR_K7_HWCR:
61a6bd67 1756 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1757 case MSR_P6_PERFCTR0:
1758 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1759 case MSR_P6_EVNTSEL0:
1760 case MSR_P6_EVNTSEL1:
9e699624 1761 case MSR_K7_EVNTSEL0:
1f3ee616 1762 case MSR_K7_PERFCTR0:
1fdbd48c 1763 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1764 case MSR_AMD64_NB_CFG:
f7c6d140 1765 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1766 data = 0;
1767 break;
9ba075a6
AK		 1768 case MSR_MTRRcap:
1769 data = 0x500 | KVM_NR_VAR_MTRR;
1770 break;
1771 case 0x200 ... 0x2ff:
1772 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1773 case 0xcd: /* fsb frequency */
1774 data = 3;
1775 break;
7b914098
JS		 1776 /*
1777 * MSR_EBC_FREQUENCY_ID
1778 * Conservative value valid for even the basic CPU models.
1779 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1780 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1781 * and 266MHz for model 3, or 4. Set Core Clock
1782 * Frequency to System Bus Frequency Ratio to 1 (bits
1783 * 31:24) even though these are only valid for CPU
1784 * models > 2, however guests may end up dividing or
1785 * multiplying by zero otherwise.
1786 */
1787 case MSR_EBC_FREQUENCY_ID:
1788 data = 1 << 24;
1789 break;
15c4a640
CO		 1790 case MSR_IA32_APICBASE:
1791 data = kvm_get_apic_base(vcpu);
1792 break;
0105d1a5
GN		 1793 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1794 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1795 break;
15c4a640 1796 case MSR_IA32_MISC_ENABLE:
ad312c7c 1797 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1798 break;
847f0ad8
AG		 1799 case MSR_IA32_PERF_STATUS:
1800 /* TSC increment by tick */
1801 data = 1000ULL;
1802 /* CPU multiplier */
1803 data |= (((uint64_t)4ULL) << 40);
1804 break;
15c4a640 1805 case MSR_EFER:
f6801dff 1806 data = vcpu->arch.efer;
15c4a640 1807 break;
18068523 1808 case MSR_KVM_WALL_CLOCK:
11c6bffa 1809 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1810 data = vcpu->kvm->arch.wall_clock;
1811 break;
1812 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1813 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1814 data = vcpu->arch.time;
1815 break;
344d9588
GN		 1816 case MSR_KVM_ASYNC_PF_EN:
1817 data = vcpu->arch.apf.msr_val;
1818 break;
890ca9ae
HY		 1819 case MSR_IA32_P5_MC_ADDR:
1820 case MSR_IA32_P5_MC_TYPE:
1821 case MSR_IA32_MCG_CAP:
1822 case MSR_IA32_MCG_CTL:
1823 case MSR_IA32_MCG_STATUS:
1824 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1825 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1826 case MSR_K7_CLK_CTL:
1827 /*
1828 * Provide expected ramp-up count for K7. All other
1829 * are set to zero, indicating minimum divisors for
1830 * every field.
1831 *
1832 * This prevents guest kernels on AMD host with CPU
1833 * type 6, model 8 and higher from exploding due to
1834 * the rdmsr failing.
1835 */
1836 data = 0x20000000;
1837 break;
55cd8e5a
GN		 1838 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1839 if (kvm_hv_msr_partition_wide(msr)) {
1840 int r;
1841 mutex_lock(&vcpu->kvm->lock);
1842 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1843 mutex_unlock(&vcpu->kvm->lock);
1844 return r;
1845 } else
1846 return get_msr_hyperv(vcpu, msr, pdata);
1847 break;
15c4a640 1848 default:
ed85c068
AP		 1849 if (!ignore_msrs) {
1850 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1851 return 1;
1852 } else {
1853 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1854 data = 0;
1855 }
1856 break;
15c4a640
CO		 1857 }
1858 *pdata = data;
1859 return 0;
1860}
1861EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1862
313a3dc7
CO		 1863/*
1864 * Read or write a bunch of msrs. All parameters are kernel addresses.
1865 *
1866 * @return number of msrs set successfully.
1867 */
1868static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1869 struct kvm_msr_entry *entries,
1870 int (*do_msr)(struct kvm_vcpu *vcpu,
1871 unsigned index, u64 *data))
1872{
f656ce01 1873 int i, idx;
313a3dc7 1874
f656ce01 1875 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1876 for (i = 0; i < msrs->nmsrs; ++i)
1877 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1878 break;
f656ce01 1879 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1880
313a3dc7
CO		 1881 return i;
1882}
1883
1884/*
1885 * Read or write a bunch of msrs. Parameters are user addresses.
1886 *
1887 * @return number of msrs set successfully.
1888 */
1889static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1890 int (*do_msr)(struct kvm_vcpu *vcpu,
1891 unsigned index, u64 *data),
1892 int writeback)
1893{
1894 struct kvm_msrs msrs;
1895 struct kvm_msr_entry *entries;
1896 int r, n;
1897 unsigned size;
1898
1899 r = -EFAULT;
1900 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1901 goto out;
1902
1903 r = -E2BIG;
1904 if (msrs.nmsrs >= MAX_IO_MSRS)
1905 goto out;
1906
1907 r = -ENOMEM;
1908 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1909 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1910 if (!entries)
1911 goto out;
1912
1913 r = -EFAULT;
1914 if (copy_from_user(entries, user_msrs->entries, size))
1915 goto out_free;
1916
1917 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1918 if (r < 0)
1919 goto out_free;
1920
1921 r = -EFAULT;
1922 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1923 goto out_free;
1924
1925 r = n;
1926
1927out_free:
7a73c028 1928 kfree(entries);
313a3dc7
CO		 1929out:
1930 return r;
1931}
1932
018d00d2
ZX		 1933int kvm_dev_ioctl_check_extension(long ext)
1934{
1935 int r;
1936
1937 switch (ext) {
1938 case KVM_CAP_IRQCHIP:
1939 case KVM_CAP_HLT:
1940 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1941 case KVM_CAP_SET_TSS_ADDR:
07716717 1942 case KVM_CAP_EXT_CPUID:
c8076604 1943 case KVM_CAP_CLOCKSOURCE:
7837699f 1944 case KVM_CAP_PIT:
a28e4f5a 1945 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1946 case KVM_CAP_MP_STATE:
ed848624 1947 case KVM_CAP_SYNC_MMU:
a355c85c 1948 case KVM_CAP_USER_NMI:
52d939a0 1949 case KVM_CAP_REINJECT_CONTROL:
4925663a 1950 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1951 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1952 case KVM_CAP_IRQFD:
d34e6b17 1953 case KVM_CAP_IOEVENTFD:
c5ff41ce 1954 case KVM_CAP_PIT2:
e9f42757 1955 case KVM_CAP_PIT_STATE2:
b927a3ce 1956 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1957 case KVM_CAP_XEN_HVM:
afbcf7ab 1958 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1959 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1960 case KVM_CAP_HYPERV:
10388a07 1961 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1962 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1963 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1964 case KVM_CAP_DEBUGREGS:
d2be1651 1965 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1966 case KVM_CAP_XSAVE:
344d9588 1967 case KVM_CAP_ASYNC_PF:
018d00d2
ZX		 1968 r = 1;
1969 break;
542472b5
LV		 1970 case KVM_CAP_COALESCED_MMIO:
1971 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1972 break;
774ead3a
AK		 1973 case KVM_CAP_VAPIC:
1974 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1975 break;
f725230a
AK		 1976 case KVM_CAP_NR_VCPUS:
1977 r = KVM_MAX_VCPUS;
1978 break;
a988b910
AK		 1979 case KVM_CAP_NR_MEMSLOTS:
1980 r = KVM_MEMORY_SLOTS;
1981 break;
a68a6a72
MT		 1982 case KVM_CAP_PV_MMU: /* obsolete */
1983 r = 0;
2f333bcb 1984 break;
62c476c7 1985 case KVM_CAP_IOMMU:
19de40a8 1986 r = iommu_found();
62c476c7 1987 break;
890ca9ae
HY		 1988 case KVM_CAP_MCE:
1989 r = KVM_MAX_MCE_BANKS;
1990 break;
2d5b5a66
SY		 1991 case KVM_CAP_XCRS:
1992 r = cpu_has_xsave;
1993 break;
018d00d2
ZX		 1994 default:
1995 r = 0;
1996 break;
1997 }
1998 return r;
1999
2000}
2001
043405e1
CO		 2002long kvm_arch_dev_ioctl(struct file *filp,
2003 unsigned int ioctl, unsigned long arg)
2004{
2005 void __user *argp = (void __user *)arg;
2006 long r;
2007
2008 switch (ioctl) {
2009 case KVM_GET_MSR_INDEX_LIST: {
2010 struct kvm_msr_list __user *user_msr_list = argp;
2011 struct kvm_msr_list msr_list;
2012 unsigned n;
2013
2014 r = -EFAULT;
2015 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2016 goto out;
2017 n = msr_list.nmsrs;
2018 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2019 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2020 goto out;
2021 r = -E2BIG;
e125e7b6 2022 if (n < msr_list.nmsrs)
043405e1
CO		 2023 goto out;
2024 r = -EFAULT;
2025 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2026 num_msrs_to_save * sizeof(u32)))
2027 goto out;
e125e7b6 2028 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2029 &emulated_msrs,
2030 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2031 goto out;
2032 r = 0;
2033 break;
2034 }
674eea0f
AK		 2035 case KVM_GET_SUPPORTED_CPUID: {
2036 struct kvm_cpuid2 __user *cpuid_arg = argp;
2037 struct kvm_cpuid2 cpuid;
2038
2039 r = -EFAULT;
2040 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2041 goto out;
2042 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2043 cpuid_arg->entries);
674eea0f
AK		 2044 if (r)
2045 goto out;
2046
2047 r = -EFAULT;
2048 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2049 goto out;
2050 r = 0;
2051 break;
2052 }
890ca9ae
HY		 2053 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2054 u64 mce_cap;
2055
2056 mce_cap = KVM_MCE_CAP_SUPPORTED;
2057 r = -EFAULT;
2058 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2059 goto out;
2060 r = 0;
2061 break;
2062 }
043405e1
CO		 2063 default:
2064 r = -EINVAL;
2065 }
2066out:
2067 return r;
2068}
2069
f5f48ee1
SY		 2070static void wbinvd_ipi(void *garbage)
2071{
2072 wbinvd();
2073}
2074
2075static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2076{
2077 return vcpu->kvm->arch.iommu_domain &&
2078 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2079}
2080
313a3dc7
CO		 2081void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2082{
f5f48ee1
SY		 2083 /* Address WBINVD may be executed by guest */
2084 if (need_emulate_wbinvd(vcpu)) {
2085 if (kvm_x86_ops->has_wbinvd_exit())
2086 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2087 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2088 smp_call_function_single(vcpu->cpu,
2089 wbinvd_ipi, NULL, 1);
2090 }
2091
313a3dc7 2092 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2093 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2094 /* Make sure TSC doesn't go backwards */
2095 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2096 native_read_tsc() - vcpu->arch.last_host_tsc;
2097 if (tsc_delta < 0)
2098 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2099 if (check_tsc_unstable()) {
e48672fa 2100 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f
ZA		 2101 vcpu->arch.tsc_catchup = 1;
2102 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2103 }
2104 if (vcpu->cpu != cpu)
2105 kvm_migrate_timers(vcpu);
e48672fa 2106 vcpu->cpu = cpu;
6b7d7e76 2107 }
313a3dc7
CO		 2108}
2109
2110void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2111{
02daab21 2112 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2113 kvm_put_guest_fpu(vcpu);
e48672fa 2114 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2115}
2116
07716717 2117static int is_efer_nx(void)
313a3dc7 2118{
e286e86e 2119 unsigned long long efer = 0;
313a3dc7 2120
e286e86e 2121 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2122 return efer & EFER_NX;
2123}
2124
2125static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2126{
2127 int i;
2128 struct kvm_cpuid_entry2 *e, *entry;
2129
313a3dc7 2130 entry = NULL;
ad312c7c
ZX		 2131 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2132 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2133 if (e->function == 0x80000001) {
2134 entry = e;
2135 break;
2136 }
2137 }
07716717 2138 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2139 entry->edx &= ~(1 << 20);
2140 printk(KERN_INFO "kvm: guest NX capability removed\n");
2141 }
2142}
2143
07716717 2144/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2145static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2146 struct kvm_cpuid *cpuid,
2147 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2148{
2149 int r, i;
2150 struct kvm_cpuid_entry *cpuid_entries;
2151
2152 r = -E2BIG;
2153 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2154 goto out;
2155 r = -ENOMEM;
2156 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2157 if (!cpuid_entries)
2158 goto out;
2159 r = -EFAULT;
2160 if (copy_from_user(cpuid_entries, entries,
2161 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2162 goto out_free;
2163 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2164 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2165 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2166 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2167 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2168 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2169 vcpu->arch.cpuid_entries[i].index = 0;
2170 vcpu->arch.cpuid_entries[i].flags = 0;
2171 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2172 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2173 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2174 }
2175 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2176 cpuid_fix_nx_cap(vcpu);
2177 r = 0;
fc61b800 2178 kvm_apic_set_version(vcpu);
0e851880 2179 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2180 update_cpuid(vcpu);
07716717
DK		 2181
2182out_free:
2183 vfree(cpuid_entries);
2184out:
2185 return r;
2186}
2187
2188static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2189 struct kvm_cpuid2 *cpuid,
2190 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2191{
2192 int r;
2193
2194 r = -E2BIG;
2195 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2196 goto out;
2197 r = -EFAULT;
ad312c7c 2198 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2199 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2200 goto out;
ad312c7c 2201 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2202 kvm_apic_set_version(vcpu);
0e851880 2203 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2204 update_cpuid(vcpu);
313a3dc7
CO		 2205 return 0;
2206
2207out:
2208 return r;
2209}
2210
07716717 2211static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2212 struct kvm_cpuid2 *cpuid,
2213 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2214{
2215 int r;
2216
2217 r = -E2BIG;
ad312c7c 2218 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2219 goto out;
2220 r = -EFAULT;
ad312c7c 2221 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2222 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2223 goto out;
2224 return 0;
2225
2226out:
ad312c7c 2227 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2228 return r;
2229}
2230
945ee35e
AK		 2231static void cpuid_mask(u32 *word, int wordnum)
2232{
2233 *word &= boot_cpu_data.x86_capability[wordnum];
2234}
2235
07716717 2236static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2237 u32 index)
07716717
DK		 2238{
2239 entry->function = function;
2240 entry->index = index;
2241 cpuid_count(entry->function, entry->index,
19355475 2242 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2243 entry->flags = 0;
2244}
2245
7faa4ee1
AK		 2246#define F(x) bit(X86_FEATURE_##x)
2247
07716717
DK		 2248static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2249 u32 index, int *nent, int maxnent)
2250{
7faa4ee1 2251 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2252#ifdef CONFIG_X86_64
17cc3935
SY		 2253 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2254 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2255 unsigned f_lm = F(LM);
2256#else
17cc3935 2257 unsigned f_gbpages = 0;
7faa4ee1 2258 unsigned f_lm = 0;
07716717 2259#endif
4e47c7a6 2260 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2261
2262 /* cpuid 1.edx */
2263 const u32 kvm_supported_word0_x86_features =
2264 F(FPU) | F(VME) | F(DE) | F(PSE) |
2265 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2266 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2267 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2268 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2269 0 /* Reserved, DS, ACPI */ | F(MMX) |
2270 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2271 0 /* HTT, TM, Reserved, PBE */;
2272 /* cpuid 0x80000001.edx */
2273 const u32 kvm_supported_word1_x86_features =
2274 F(FPU) | F(VME) | F(DE) | F(PSE) |
2275 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2276 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2277 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2278 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2279 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2280 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2281 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2282 /* cpuid 1.ecx */
2283 const u32 kvm_supported_word4_x86_features =
6c3f6041 2284 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2285 0 /* DS-CPL, VMX, SMX, EST */ |
2286 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2287 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2288 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2289 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2290 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2291 F(F16C);
7faa4ee1 2292 /* cpuid 0x80000001.ecx */
07716717 2293 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2294 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2295 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2296 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2297 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2298
19355475 2299 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2300 get_cpu();
2301 do_cpuid_1_ent(entry, function, index);
2302 ++*nent;
2303
2304 switch (function) {
2305 case 0:
2acf923e 2306 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2307 break;
2308 case 1:
2309 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2310 cpuid_mask(&entry->edx, 0);
7faa4ee1 2311 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2312 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2313 /* we support x2apic emulation even if host does not support
2314 * it since we emulate x2apic in software */
2315 entry->ecx |= F(X2APIC);
07716717
DK		 2316 break;
2317 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2318 * may return different values. This forces us to get_cpu() before
2319 * issuing the first command, and also to emulate this annoying behavior
2320 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2321 case 2: {
2322 int t, times = entry->eax & 0xff;
2323
2324 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2325 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2326 for (t = 1; t < times && *nent < maxnent; ++t) {
2327 do_cpuid_1_ent(&entry[t], function, 0);
2328 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2329 ++*nent;
2330 }
2331 break;
2332 }
2333 /* function 4 and 0xb have additional index. */
2334 case 4: {
14af3f3c 2335 int i, cache_type;
07716717
DK		 2336
2337 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2338 /* read more entries until cache_type is zero */
14af3f3c
HH		 2339 for (i = 1; *nent < maxnent; ++i) {
2340 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2341 if (!cache_type)
2342 break;
14af3f3c
HH		 2343 do_cpuid_1_ent(&entry[i], function, i);
2344 entry[i].flags |=
07716717
DK		 2345 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2346 ++*nent;
2347 }
2348 break;
2349 }
2350 case 0xb: {
14af3f3c 2351 int i, level_type;
07716717
DK		 2352
2353 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2354 /* read more entries until level_type is zero */
14af3f3c 2355 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2356 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2357 if (!level_type)
2358 break;
14af3f3c
HH		 2359 do_cpuid_1_ent(&entry[i], function, i);
2360 entry[i].flags |=
07716717
DK		 2361 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2362 ++*nent;
2363 }
2364 break;
2365 }
2acf923e
DC		 2366 case 0xd: {
2367 int i;
2368
2369 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2370 for (i = 1; *nent < maxnent; ++i) {
2371 if (entry[i - 1].eax == 0 && i != 2)
2372 break;
2373 do_cpuid_1_ent(&entry[i], function, i);
2374 entry[i].flags |=
2375 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2376 ++*nent;
2377 }
2378 break;
2379 }
84478c82
GC		 2380 case KVM_CPUID_SIGNATURE: {
2381 char signature[12] = "KVMKVMKVM\0\0";
2382 u32 *sigptr = (u32 *)signature;
2383 entry->eax = 0;
2384 entry->ebx = sigptr[0];
2385 entry->ecx = sigptr[1];
2386 entry->edx = sigptr[2];
2387 break;
2388 }
2389 case KVM_CPUID_FEATURES:
2390 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2391 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2392 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2393 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2394 entry->ebx = 0;
2395 entry->ecx = 0;
2396 entry->edx = 0;
2397 break;
07716717
DK		 2398 case 0x80000000:
2399 entry->eax = min(entry->eax, 0x8000001a);
2400 break;
2401 case 0x80000001:
2402 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2403 cpuid_mask(&entry->edx, 1);
07716717 2404 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2405 cpuid_mask(&entry->ecx, 6);
07716717
DK		 2406 break;
2407 }
d4330ef2
JR		 2408
2409 kvm_x86_ops->set_supported_cpuid(function, entry);
2410
07716717
DK		 2411 put_cpu();
2412}
2413
7faa4ee1
AK		 2414#undef F
2415
674eea0f 2416static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2417 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2418{
2419 struct kvm_cpuid_entry2 *cpuid_entries;
2420 int limit, nent = 0, r = -E2BIG;
2421 u32 func;
2422
2423 if (cpuid->nent < 1)
2424 goto out;
6a544355
AK		 2425 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2426 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2427 r = -ENOMEM;
2428 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2429 if (!cpuid_entries)
2430 goto out;
2431
2432 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2433 limit = cpuid_entries[0].eax;
2434 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2435 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2436 &nent, cpuid->nent);
07716717
DK		 2437 r = -E2BIG;
2438 if (nent >= cpuid->nent)
2439 goto out_free;
2440
2441 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2442 limit = cpuid_entries[nent - 1].eax;
2443 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2444 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2445 &nent, cpuid->nent);
84478c82
GC		 2446
2447
2448
2449 r = -E2BIG;
2450 if (nent >= cpuid->nent)
2451 goto out_free;
2452
2453 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2454 cpuid->nent);
2455
2456 r = -E2BIG;
2457 if (nent >= cpuid->nent)
2458 goto out_free;
2459
2460 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2461 cpuid->nent);
2462
cb007648
MM		 2463 r = -E2BIG;
2464 if (nent >= cpuid->nent)
2465 goto out_free;
2466
07716717
DK		 2467 r = -EFAULT;
2468 if (copy_to_user(entries, cpuid_entries,
19355475 2469 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2470 goto out_free;
2471 cpuid->nent = nent;
2472 r = 0;
2473
2474out_free:
2475 vfree(cpuid_entries);
2476out:
2477 return r;
2478}
2479
313a3dc7
CO		 2480static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2481 struct kvm_lapic_state *s)
2482{
ad312c7c 2483 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2484
2485 return 0;
2486}
2487
2488static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2489 struct kvm_lapic_state *s)
2490{
ad312c7c 2491 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2492 kvm_apic_post_state_restore(vcpu);
cb142eb7 2493 update_cr8_intercept(vcpu);
313a3dc7
CO		 2494
2495 return 0;
2496}
2497
f77bc6a4
ZX		 2498static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2499 struct kvm_interrupt *irq)
2500{
2501 if (irq->irq < 0 || irq->irq >= 256)
2502 return -EINVAL;
2503 if (irqchip_in_kernel(vcpu->kvm))
2504 return -ENXIO;
f77bc6a4 2505
66fd3f7f 2506 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2507 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2508
f77bc6a4
ZX		 2509 return 0;
2510}
2511
c4abb7c9
JK		 2512static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2513{
c4abb7c9 2514 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2515
2516 return 0;
2517}
2518
b209749f
AK		 2519static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2520 struct kvm_tpr_access_ctl *tac)
2521{
2522 if (tac->flags)
2523 return -EINVAL;
2524 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2525 return 0;
2526}
2527
890ca9ae
HY		 2528static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2529 u64 mcg_cap)
2530{
2531 int r;
2532 unsigned bank_num = mcg_cap & 0xff, bank;
2533
2534 r = -EINVAL;
a9e38c3e 2535 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2536 goto out;
2537 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2538 goto out;
2539 r = 0;
2540 vcpu->arch.mcg_cap = mcg_cap;
2541 /* Init IA32_MCG_CTL to all 1s */
2542 if (mcg_cap & MCG_CTL_P)
2543 vcpu->arch.mcg_ctl = ~(u64)0;
2544 /* Init IA32_MCi_CTL to all 1s */
2545 for (bank = 0; bank < bank_num; bank++)
2546 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2547out:
2548 return r;
2549}
2550
2551static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2552 struct kvm_x86_mce *mce)
2553{
2554 u64 mcg_cap = vcpu->arch.mcg_cap;
2555 unsigned bank_num = mcg_cap & 0xff;
2556 u64 *banks = vcpu->arch.mce_banks;
2557
2558 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2559 return -EINVAL;
2560 /*
2561 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2562 * reporting is disabled
2563 */
2564 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2565 vcpu->arch.mcg_ctl != ~(u64)0)
2566 return 0;
2567 banks += 4 * mce->bank;
2568 /*
2569 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2570 * reporting is disabled for the bank
2571 */
2572 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2573 return 0;
2574 if (mce->status & MCI_STATUS_UC) {
2575 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2576 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2577 printk(KERN_DEBUG "kvm: set_mce: "
2578 "injects mce exception while "
2579 "previous one is in progress!\n");
a8eeb04a 2580 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2581 return 0;
2582 }
2583 if (banks[1] & MCI_STATUS_VAL)
2584 mce->status |= MCI_STATUS_OVER;
2585 banks[2] = mce->addr;
2586 banks[3] = mce->misc;
2587 vcpu->arch.mcg_status = mce->mcg_status;
2588 banks[1] = mce->status;
2589 kvm_queue_exception(vcpu, MC_VECTOR);
2590 } else if (!(banks[1] & MCI_STATUS_VAL)
2591 || !(banks[1] & MCI_STATUS_UC)) {
2592 if (banks[1] & MCI_STATUS_VAL)
2593 mce->status |= MCI_STATUS_OVER;
2594 banks[2] = mce->addr;
2595 banks[3] = mce->misc;
2596 banks[1] = mce->status;
2597 } else
2598 banks[1] |= MCI_STATUS_OVER;
2599 return 0;
2600}
2601
3cfc3092
JK		 2602static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2603 struct kvm_vcpu_events *events)
2604{
03b82a30
JK		 2605 events->exception.injected =
2606 vcpu->arch.exception.pending &&
2607 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2608 events->exception.nr = vcpu->arch.exception.nr;
2609 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2610 events->exception.pad = 0;
3cfc3092
JK		 2611 events->exception.error_code = vcpu->arch.exception.error_code;
2612
03b82a30
JK		 2613 events->interrupt.injected =
2614 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2615 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2616 events->interrupt.soft = 0;
48005f64
JK		 2617 events->interrupt.shadow =
2618 kvm_x86_ops->get_interrupt_shadow(vcpu,
2619 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2620
2621 events->nmi.injected = vcpu->arch.nmi_injected;
2622 events->nmi.pending = vcpu->arch.nmi_pending;
2623 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2624 events->nmi.pad = 0;
3cfc3092
JK		 2625
2626 events->sipi_vector = vcpu->arch.sipi_vector;
2627
dab4b911 2628 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2629 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2630 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2631 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2632}
2633
2634static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2635 struct kvm_vcpu_events *events)
2636{
dab4b911 2637 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2638 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2639 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2640 return -EINVAL;
2641
3cfc3092
JK		 2642 vcpu->arch.exception.pending = events->exception.injected;
2643 vcpu->arch.exception.nr = events->exception.nr;
2644 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2645 vcpu->arch.exception.error_code = events->exception.error_code;
2646
2647 vcpu->arch.interrupt.pending = events->interrupt.injected;
2648 vcpu->arch.interrupt.nr = events->interrupt.nr;
2649 vcpu->arch.interrupt.soft = events->interrupt.soft;
2650 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2651 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2652 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2653 kvm_x86_ops->set_interrupt_shadow(vcpu,
2654 events->interrupt.shadow);
3cfc3092
JK		 2655
2656 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2657 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2658 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2659 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2660
dab4b911
JK		 2661 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2662 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2663
3842d135
AK		 2664 kvm_make_request(KVM_REQ_EVENT, vcpu);
2665
3cfc3092
JK		 2666 return 0;
2667}
2668
a1efbe77
JK		 2669static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2670 struct kvm_debugregs *dbgregs)
2671{
a1efbe77
JK		 2672 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2673 dbgregs->dr6 = vcpu->arch.dr6;
2674 dbgregs->dr7 = vcpu->arch.dr7;
2675 dbgregs->flags = 0;
97e69aa6 2676 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2677}
2678
2679static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2680 struct kvm_debugregs *dbgregs)
2681{
2682 if (dbgregs->flags)
2683 return -EINVAL;
2684
a1efbe77
JK		 2685 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2686 vcpu->arch.dr6 = dbgregs->dr6;
2687 vcpu->arch.dr7 = dbgregs->dr7;
2688
a1efbe77
JK		 2689 return 0;
2690}
2691
2d5b5a66
SY		 2692static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2693 struct kvm_xsave *guest_xsave)
2694{
2695 if (cpu_has_xsave)
2696 memcpy(guest_xsave->region,
2697 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2698 xstate_size);
2d5b5a66
SY		 2699 else {
2700 memcpy(guest_xsave->region,
2701 &vcpu->arch.guest_fpu.state->fxsave,
2702 sizeof(struct i387_fxsave_struct));
2703 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2704 XSTATE_FPSSE;
2705 }
2706}
2707
2708static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2709 struct kvm_xsave *guest_xsave)
2710{
2711 u64 xstate_bv =
2712 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2713
2714 if (cpu_has_xsave)
2715 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2716 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2717 else {
2718 if (xstate_bv & ~XSTATE_FPSSE)
2719 return -EINVAL;
2720 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2721 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2722 }
2723 return 0;
2724}
2725
2726static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2727 struct kvm_xcrs *guest_xcrs)
2728{
2729 if (!cpu_has_xsave) {
2730 guest_xcrs->nr_xcrs = 0;
2731 return;
2732 }
2733
2734 guest_xcrs->nr_xcrs = 1;
2735 guest_xcrs->flags = 0;
2736 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2737 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2738}
2739
2740static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2741 struct kvm_xcrs *guest_xcrs)
2742{
2743 int i, r = 0;
2744
2745 if (!cpu_has_xsave)
2746 return -EINVAL;
2747
2748 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2749 return -EINVAL;
2750
2751 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2752 /* Only support XCR0 currently */
2753 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2754 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2755 guest_xcrs->xcrs[0].value);
2756 break;
2757 }
2758 if (r)
2759 r = -EINVAL;
2760 return r;
2761}
2762
313a3dc7
CO		 2763long kvm_arch_vcpu_ioctl(struct file *filp,
2764 unsigned int ioctl, unsigned long arg)
2765{
2766 struct kvm_vcpu *vcpu = filp->private_data;
2767 void __user *argp = (void __user *)arg;
2768 int r;
d1ac91d8
AK		 2769 union {
2770 struct kvm_lapic_state *lapic;
2771 struct kvm_xsave *xsave;
2772 struct kvm_xcrs *xcrs;
2773 void *buffer;
2774 } u;
2775
2776 u.buffer = NULL;
313a3dc7
CO		 2777 switch (ioctl) {
2778 case KVM_GET_LAPIC: {
2204ae3c
MT		 2779 r = -EINVAL;
2780 if (!vcpu->arch.apic)
2781 goto out;
d1ac91d8 2782 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2783
b772ff36 2784 r = -ENOMEM;
d1ac91d8 2785 if (!u.lapic)
b772ff36 2786 goto out;
d1ac91d8 2787 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2788 if (r)
2789 goto out;
2790 r = -EFAULT;
d1ac91d8 2791 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2792 goto out;
2793 r = 0;
2794 break;
2795 }
2796 case KVM_SET_LAPIC: {
2204ae3c
MT		 2797 r = -EINVAL;
2798 if (!vcpu->arch.apic)
2799 goto out;
d1ac91d8 2800 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2801 r = -ENOMEM;
d1ac91d8 2802 if (!u.lapic)
b772ff36 2803 goto out;
313a3dc7 2804 r = -EFAULT;
d1ac91d8 2805 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2806 goto out;
d1ac91d8 2807 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2808 if (r)
2809 goto out;
2810 r = 0;
2811 break;
2812 }
f77bc6a4
ZX		 2813 case KVM_INTERRUPT: {
2814 struct kvm_interrupt irq;
2815
2816 r = -EFAULT;
2817 if (copy_from_user(&irq, argp, sizeof irq))
2818 goto out;
2819 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2820 if (r)
2821 goto out;
2822 r = 0;
2823 break;
2824 }
c4abb7c9
JK		 2825 case KVM_NMI: {
2826 r = kvm_vcpu_ioctl_nmi(vcpu);
2827 if (r)
2828 goto out;
2829 r = 0;
2830 break;
2831 }
313a3dc7
CO		 2832 case KVM_SET_CPUID: {
2833 struct kvm_cpuid __user *cpuid_arg = argp;
2834 struct kvm_cpuid cpuid;
2835
2836 r = -EFAULT;
2837 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2838 goto out;
2839 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2840 if (r)
2841 goto out;
2842 break;
2843 }
07716717
DK		 2844 case KVM_SET_CPUID2: {
2845 struct kvm_cpuid2 __user *cpuid_arg = argp;
2846 struct kvm_cpuid2 cpuid;
2847
2848 r = -EFAULT;
2849 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2850 goto out;
2851 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2852 cpuid_arg->entries);
07716717
DK		 2853 if (r)
2854 goto out;
2855 break;
2856 }
2857 case KVM_GET_CPUID2: {
2858 struct kvm_cpuid2 __user *cpuid_arg = argp;
2859 struct kvm_cpuid2 cpuid;
2860
2861 r = -EFAULT;
2862 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2863 goto out;
2864 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2865 cpuid_arg->entries);
07716717
DK		 2866 if (r)
2867 goto out;
2868 r = -EFAULT;
2869 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2870 goto out;
2871 r = 0;
2872 break;
2873 }
313a3dc7
CO		 2874 case KVM_GET_MSRS:
2875 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2876 break;
2877 case KVM_SET_MSRS:
2878 r = msr_io(vcpu, argp, do_set_msr, 0);
2879 break;
b209749f
AK		 2880 case KVM_TPR_ACCESS_REPORTING: {
2881 struct kvm_tpr_access_ctl tac;
2882
2883 r = -EFAULT;
2884 if (copy_from_user(&tac, argp, sizeof tac))
2885 goto out;
2886 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2887 if (r)
2888 goto out;
2889 r = -EFAULT;
2890 if (copy_to_user(argp, &tac, sizeof tac))
2891 goto out;
2892 r = 0;
2893 break;
2894 };
b93463aa
AK		 2895 case KVM_SET_VAPIC_ADDR: {
2896 struct kvm_vapic_addr va;
2897
2898 r = -EINVAL;
2899 if (!irqchip_in_kernel(vcpu->kvm))
2900 goto out;
2901 r = -EFAULT;
2902 if (copy_from_user(&va, argp, sizeof va))
2903 goto out;
2904 r = 0;
2905 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2906 break;
2907 }
890ca9ae
HY		 2908 case KVM_X86_SETUP_MCE: {
2909 u64 mcg_cap;
2910
2911 r = -EFAULT;
2912 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2913 goto out;
2914 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2915 break;
2916 }
2917 case KVM_X86_SET_MCE: {
2918 struct kvm_x86_mce mce;
2919
2920 r = -EFAULT;
2921 if (copy_from_user(&mce, argp, sizeof mce))
2922 goto out;
2923 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2924 break;
2925 }
3cfc3092
JK		 2926 case KVM_GET_VCPU_EVENTS: {
2927 struct kvm_vcpu_events events;
2928
2929 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2930
2931 r = -EFAULT;
2932 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2933 break;
2934 r = 0;
2935 break;
2936 }
2937 case KVM_SET_VCPU_EVENTS: {
2938 struct kvm_vcpu_events events;
2939
2940 r = -EFAULT;
2941 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2942 break;
2943
2944 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2945 break;
2946 }
a1efbe77
JK		 2947 case KVM_GET_DEBUGREGS: {
2948 struct kvm_debugregs dbgregs;
2949
2950 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2951
2952 r = -EFAULT;
2953 if (copy_to_user(argp, &dbgregs,
2954 sizeof(struct kvm_debugregs)))
2955 break;
2956 r = 0;
2957 break;
2958 }
2959 case KVM_SET_DEBUGREGS: {
2960 struct kvm_debugregs dbgregs;
2961
2962 r = -EFAULT;
2963 if (copy_from_user(&dbgregs, argp,
2964 sizeof(struct kvm_debugregs)))
2965 break;
2966
2967 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2968 break;
2969 }
2d5b5a66 2970 case KVM_GET_XSAVE: {
d1ac91d8 2971 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2972 r = -ENOMEM;
d1ac91d8 2973 if (!u.xsave)
2d5b5a66
SY		 2974 break;
2975
d1ac91d8 2976 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2977
2978 r = -EFAULT;
d1ac91d8 2979 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2980 break;
2981 r = 0;
2982 break;
2983 }
2984 case KVM_SET_XSAVE: {
d1ac91d8 2985 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2986 r = -ENOMEM;
d1ac91d8 2987 if (!u.xsave)
2d5b5a66
SY		 2988 break;
2989
2990 r = -EFAULT;
d1ac91d8 2991 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2992 break;
2993
d1ac91d8 2994 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2995 break;
2996 }
2997 case KVM_GET_XCRS: {
d1ac91d8 2998 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2999 r = -ENOMEM;
d1ac91d8 3000 if (!u.xcrs)
2d5b5a66
SY		 3001 break;
3002
d1ac91d8 3003 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3004
3005 r = -EFAULT;
d1ac91d8 3006 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3007 sizeof(struct kvm_xcrs)))
3008 break;
3009 r = 0;
3010 break;
3011 }
3012 case KVM_SET_XCRS: {
d1ac91d8 3013 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3014 r = -ENOMEM;
d1ac91d8 3015 if (!u.xcrs)
2d5b5a66
SY		 3016 break;
3017
3018 r = -EFAULT;
d1ac91d8 3019 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3020 sizeof(struct kvm_xcrs)))
3021 break;
3022
d1ac91d8 3023 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3024 break;
3025 }
313a3dc7
CO		 3026 default:
3027 r = -EINVAL;
3028 }
3029out:
d1ac91d8 3030 kfree(u.buffer);
313a3dc7
CO		 3031 return r;
3032}
3033
1fe779f8
CO		 3034static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3035{
3036 int ret;
3037
3038 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3039 return -1;
3040 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3041 return ret;
3042}
3043
b927a3ce
SY		 3044static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3045 u64 ident_addr)
3046{
3047 kvm->arch.ept_identity_map_addr = ident_addr;
3048 return 0;
3049}
3050
1fe779f8
CO		 3051static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3052 u32 kvm_nr_mmu_pages)
3053{
3054 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3055 return -EINVAL;
3056
79fac95e 3057 mutex_lock(&kvm->slots_lock);
7c8a83b7 3058 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3059
3060 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3061 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3062
7c8a83b7 3063 spin_unlock(&kvm->mmu_lock);
79fac95e 3064 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3065 return 0;
3066}
3067
3068static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3069{
39de71ec 3070 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3071}
3072
1fe779f8
CO		 3073static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3074{
3075 int r;
3076
3077 r = 0;
3078 switch (chip->chip_id) {
3079 case KVM_IRQCHIP_PIC_MASTER:
3080 memcpy(&chip->chip.pic,
3081 &pic_irqchip(kvm)->pics[0],
3082 sizeof(struct kvm_pic_state));
3083 break;
3084 case KVM_IRQCHIP_PIC_SLAVE:
3085 memcpy(&chip->chip.pic,
3086 &pic_irqchip(kvm)->pics[1],
3087 sizeof(struct kvm_pic_state));
3088 break;
3089 case KVM_IRQCHIP_IOAPIC:
eba0226b 3090 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3091 break;
3092 default:
3093 r = -EINVAL;
3094 break;
3095 }
3096 return r;
3097}
3098
3099static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3100{
3101 int r;
3102
3103 r = 0;
3104 switch (chip->chip_id) {
3105 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3106 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3107 memcpy(&pic_irqchip(kvm)->pics[0],
3108 &chip->chip.pic,
3109 sizeof(struct kvm_pic_state));
f4f51050 3110 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3111 break;
3112 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3113 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3114 memcpy(&pic_irqchip(kvm)->pics[1],
3115 &chip->chip.pic,
3116 sizeof(struct kvm_pic_state));
f4f51050 3117 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3118 break;
3119 case KVM_IRQCHIP_IOAPIC:
eba0226b 3120 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3121 break;
3122 default:
3123 r = -EINVAL;
3124 break;
3125 }
3126 kvm_pic_update_irq(pic_irqchip(kvm));
3127 return r;
3128}
3129
e0f63cb9
SY		 3130static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3131{
3132 int r = 0;
3133
894a9c55 3134 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3135 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3136 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3137 return r;
3138}
3139
3140static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3141{
3142 int r = 0;
3143
894a9c55 3144 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3145 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3146 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3147 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3148 return r;
3149}
3150
3151static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3152{
3153 int r = 0;
3154
3155 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3156 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3157 sizeof(ps->channels));
3158 ps->flags = kvm->arch.vpit->pit_state.flags;
3159 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3160 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3161 return r;
3162}
3163
3164static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3165{
3166 int r = 0, start = 0;
3167 u32 prev_legacy, cur_legacy;
3168 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3169 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3170 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3171 if (!prev_legacy && cur_legacy)
3172 start = 1;
3173 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3174 sizeof(kvm->arch.vpit->pit_state.channels));
3175 kvm->arch.vpit->pit_state.flags = ps->flags;
3176 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3177 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3178 return r;
3179}
3180
52d939a0
MT		 3181static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3182 struct kvm_reinject_control *control)
3183{
3184 if (!kvm->arch.vpit)
3185 return -ENXIO;
894a9c55 3186 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3187 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3188 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3189 return 0;
3190}
3191
5bb064dc
ZX		 3192/*
3193 * Get (and clear) the dirty memory log for a memory slot.
3194 */
3195int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3196 struct kvm_dirty_log *log)
3197{
87bf6e7d 3198 int r, i;
5bb064dc 3199 struct kvm_memory_slot *memslot;
87bf6e7d 3200 unsigned long n;
b050b015 3201 unsigned long is_dirty = 0;
5bb064dc 3202
79fac95e 3203 mutex_lock(&kvm->slots_lock);
5bb064dc 3204
b050b015
MT		 3205 r = -EINVAL;
3206 if (log->slot >= KVM_MEMORY_SLOTS)
3207 goto out;
3208
3209 memslot = &kvm->memslots->memslots[log->slot];
3210 r = -ENOENT;
3211 if (!memslot->dirty_bitmap)
3212 goto out;
3213
87bf6e7d 3214 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3215
b050b015
MT		 3216 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3217 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3218
3219 /* If nothing is dirty, don't bother messing with page tables. */
3220 if (is_dirty) {
b050b015 3221 struct kvm_memslots *slots, *old_slots;
914ebccd 3222 unsigned long *dirty_bitmap;
b050b015 3223
515a0127
TY		 3224 dirty_bitmap = memslot->dirty_bitmap_head;
3225 if (memslot->dirty_bitmap == dirty_bitmap)
3226 dirty_bitmap += n / sizeof(long);
914ebccd 3227 memset(dirty_bitmap, 0, n);
b050b015 3228
914ebccd
TY		 3229 r = -ENOMEM;
3230 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3231 if (!slots)
914ebccd 3232 goto out;
b050b015
MT		 3233 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3234 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3235 slots->generation++;
b050b015
MT		 3236
3237 old_slots = kvm->memslots;
3238 rcu_assign_pointer(kvm->memslots, slots);
3239 synchronize_srcu_expedited(&kvm->srcu);
3240 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3241 kfree(old_slots);
914ebccd 3242
edde99ce
MT		 3243 spin_lock(&kvm->mmu_lock);
3244 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3245 spin_unlock(&kvm->mmu_lock);
3246
914ebccd 3247 r = -EFAULT;
515a0127 3248 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3249 goto out;
914ebccd
TY		 3250 } else {
3251 r = -EFAULT;
3252 if (clear_user(log->dirty_bitmap, n))
3253 goto out;
5bb064dc 3254 }
b050b015 3255
5bb064dc
ZX		 3256 r = 0;
3257out:
79fac95e 3258 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3259 return r;
3260}
3261
1fe779f8
CO		 3262long kvm_arch_vm_ioctl(struct file *filp,
3263 unsigned int ioctl, unsigned long arg)
3264{
3265 struct kvm *kvm = filp->private_data;
3266 void __user *argp = (void __user *)arg;
367e1319 3267 int r = -ENOTTY;
f0d66275
DH		 3268 /*
3269 * This union makes it completely explicit to gcc-3.x
3270 * that these two variables' stack usage should be
3271 * combined, not added together.
3272 */
3273 union {
3274 struct kvm_pit_state ps;
e9f42757 3275 struct kvm_pit_state2 ps2;
c5ff41ce 3276 struct kvm_pit_config pit_config;
f0d66275 3277 } u;
1fe779f8
CO		 3278
3279 switch (ioctl) {
3280 case KVM_SET_TSS_ADDR:
3281 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3282 if (r < 0)
3283 goto out;
3284 break;
b927a3ce
SY		 3285 case KVM_SET_IDENTITY_MAP_ADDR: {
3286 u64 ident_addr;
3287
3288 r = -EFAULT;
3289 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3290 goto out;
3291 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3292 if (r < 0)
3293 goto out;
3294 break;
3295 }
1fe779f8
CO		 3296 case KVM_SET_NR_MMU_PAGES:
3297 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3298 if (r)
3299 goto out;
3300 break;
3301 case KVM_GET_NR_MMU_PAGES:
3302 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3303 break;
3ddea128
MT		 3304 case KVM_CREATE_IRQCHIP: {
3305 struct kvm_pic *vpic;
3306
3307 mutex_lock(&kvm->lock);
3308 r = -EEXIST;
3309 if (kvm->arch.vpic)
3310 goto create_irqchip_unlock;
1fe779f8 3311 r = -ENOMEM;
3ddea128
MT		 3312 vpic = kvm_create_pic(kvm);
3313 if (vpic) {
1fe779f8
CO		 3314 r = kvm_ioapic_init(kvm);
3315 if (r) {
175504cd 3316 mutex_lock(&kvm->slots_lock);
72bb2fcd
WY		 3317 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3318 &vpic->dev);
175504cd 3319 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3320 kfree(vpic);
3321 goto create_irqchip_unlock;
1fe779f8
CO		 3322 }
3323 } else
3ddea128
MT		 3324 goto create_irqchip_unlock;
3325 smp_wmb();
3326 kvm->arch.vpic = vpic;
3327 smp_wmb();
399ec807
AK		 3328 r = kvm_setup_default_irq_routing(kvm);
3329 if (r) {
175504cd 3330 mutex_lock(&kvm->slots_lock);
3ddea128 3331 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3332 kvm_ioapic_destroy(kvm);
3333 kvm_destroy_pic(kvm);
3ddea128 3334 mutex_unlock(&kvm->irq_lock);
175504cd 3335 mutex_unlock(&kvm->slots_lock);
399ec807 3336 }
3ddea128
MT		 3337 create_irqchip_unlock:
3338 mutex_unlock(&kvm->lock);
1fe779f8 3339 break;
3ddea128 3340 }
7837699f 3341 case KVM_CREATE_PIT:
c5ff41ce
JK		 3342 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3343 goto create_pit;
3344 case KVM_CREATE_PIT2:
3345 r = -EFAULT;
3346 if (copy_from_user(&u.pit_config, argp,
3347 sizeof(struct kvm_pit_config)))
3348 goto out;
3349 create_pit:
79fac95e 3350 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3351 r = -EEXIST;
3352 if (kvm->arch.vpit)
3353 goto create_pit_unlock;
7837699f 3354 r = -ENOMEM;
c5ff41ce 3355 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3356 if (kvm->arch.vpit)
3357 r = 0;
269e05e4 3358 create_pit_unlock:
79fac95e 3359 mutex_unlock(&kvm->slots_lock);
7837699f 3360 break;
4925663a 3361 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3362 case KVM_IRQ_LINE: {
3363 struct kvm_irq_level irq_event;
3364
3365 r = -EFAULT;
3366 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3367 goto out;
160d2f6c 3368 r = -ENXIO;
1fe779f8 3369 if (irqchip_in_kernel(kvm)) {
4925663a 3370 __s32 status;
4925663a
GN		 3371 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3372 irq_event.irq, irq_event.level);
4925663a 3373 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3374 r = -EFAULT;
4925663a
GN		 3375 irq_event.status = status;
3376 if (copy_to_user(argp, &irq_event,
3377 sizeof irq_event))
3378 goto out;
3379 }
1fe779f8
CO		 3380 r = 0;
3381 }
3382 break;
3383 }
3384 case KVM_GET_IRQCHIP: {
3385 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3386 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3387
f0d66275
DH		 3388 r = -ENOMEM;
3389 if (!chip)
1fe779f8 3390 goto out;
f0d66275
DH		 3391 r = -EFAULT;
3392 if (copy_from_user(chip, argp, sizeof *chip))
3393 goto get_irqchip_out;
1fe779f8
CO		 3394 r = -ENXIO;
3395 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3396 goto get_irqchip_out;
3397 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3398 if (r)
f0d66275 3399 goto get_irqchip_out;
1fe779f8 3400 r = -EFAULT;
f0d66275
DH		 3401 if (copy_to_user(argp, chip, sizeof *chip))
3402 goto get_irqchip_out;
1fe779f8 3403 r = 0;
f0d66275
DH		 3404 get_irqchip_out:
3405 kfree(chip);
3406 if (r)
3407 goto out;
1fe779f8
CO		 3408 break;
3409 }
3410 case KVM_SET_IRQCHIP: {
3411 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3412 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3413
f0d66275
DH		 3414 r = -ENOMEM;
3415 if (!chip)
1fe779f8 3416 goto out;
f0d66275
DH		 3417 r = -EFAULT;
3418 if (copy_from_user(chip, argp, sizeof *chip))
3419 goto set_irqchip_out;
1fe779f8
CO		 3420 r = -ENXIO;
3421 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3422 goto set_irqchip_out;
3423 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3424 if (r)
f0d66275 3425 goto set_irqchip_out;
1fe779f8 3426 r = 0;
f0d66275
DH		 3427 set_irqchip_out:
3428 kfree(chip);
3429 if (r)
3430 goto out;
1fe779f8
CO		 3431 break;
3432 }
e0f63cb9 3433 case KVM_GET_PIT: {
e0f63cb9 3434 r = -EFAULT;
f0d66275 3435 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3436 goto out;
3437 r = -ENXIO;
3438 if (!kvm->arch.vpit)
3439 goto out;
f0d66275 3440 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3441 if (r)
3442 goto out;
3443 r = -EFAULT;
f0d66275 3444 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3445 goto out;
3446 r = 0;
3447 break;
3448 }
3449 case KVM_SET_PIT: {
e0f63cb9 3450 r = -EFAULT;
f0d66275 3451 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3452 goto out;
3453 r = -ENXIO;
3454 if (!kvm->arch.vpit)
3455 goto out;
f0d66275 3456 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3457 if (r)
3458 goto out;
3459 r = 0;
3460 break;
3461 }
e9f42757
BK		 3462 case KVM_GET_PIT2: {
3463 r = -ENXIO;
3464 if (!kvm->arch.vpit)
3465 goto out;
3466 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3467 if (r)
3468 goto out;
3469 r = -EFAULT;
3470 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3471 goto out;
3472 r = 0;
3473 break;
3474 }
3475 case KVM_SET_PIT2: {
3476 r = -EFAULT;
3477 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3478 goto out;
3479 r = -ENXIO;
3480 if (!kvm->arch.vpit)
3481 goto out;
3482 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3483 if (r)
3484 goto out;
3485 r = 0;
3486 break;
3487 }
52d939a0
MT		 3488 case KVM_REINJECT_CONTROL: {
3489 struct kvm_reinject_control control;
3490 r = -EFAULT;
3491 if (copy_from_user(&control, argp, sizeof(control)))
3492 goto out;
3493 r = kvm_vm_ioctl_reinject(kvm, &control);
3494 if (r)
3495 goto out;
3496 r = 0;
3497 break;
3498 }
ffde22ac
ES		 3499 case KVM_XEN_HVM_CONFIG: {
3500 r = -EFAULT;
3501 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3502 sizeof(struct kvm_xen_hvm_config)))
3503 goto out;
3504 r = -EINVAL;
3505 if (kvm->arch.xen_hvm_config.flags)
3506 goto out;
3507 r = 0;
3508 break;
3509 }
afbcf7ab 3510 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3511 struct kvm_clock_data user_ns;
3512 u64 now_ns;
3513 s64 delta;
3514
3515 r = -EFAULT;
3516 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3517 goto out;
3518
3519 r = -EINVAL;
3520 if (user_ns.flags)
3521 goto out;
3522
3523 r = 0;
395c6b0a 3524 local_irq_disable();
759379dd 3525 now_ns = get_kernel_ns();
afbcf7ab 3526 delta = user_ns.clock - now_ns;
395c6b0a 3527 local_irq_enable();
afbcf7ab
GC		 3528 kvm->arch.kvmclock_offset = delta;
3529 break;
3530 }
3531 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3532 struct kvm_clock_data user_ns;
3533 u64 now_ns;
3534
395c6b0a 3535 local_irq_disable();
759379dd 3536 now_ns = get_kernel_ns();
afbcf7ab 3537 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3538 local_irq_enable();
afbcf7ab 3539 user_ns.flags = 0;
97e69aa6 3540 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3541
3542 r = -EFAULT;
3543 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3544 goto out;
3545 r = 0;
3546 break;
3547 }
3548
1fe779f8
CO		 3549 default:
3550 ;
3551 }
3552out:
3553 return r;
3554}
3555
a16b043c 3556static void kvm_init_msr_list(void)
043405e1
CO		 3557{
3558 u32 dummy[2];
3559 unsigned i, j;
3560
e3267cbb
GC		 3561 /* skip the first msrs in the list. KVM-specific */
3562 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3563 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3564 continue;
3565 if (j < i)
3566 msrs_to_save[j] = msrs_to_save[i];
3567 j++;
3568 }
3569 num_msrs_to_save = j;
3570}
3571
bda9020e
MT		 3572static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3573 const void *v)
bbd9b64e 3574{
bda9020e
MT		 3575 if (vcpu->arch.apic &&
3576 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3577 return 0;
bbd9b64e 3578
e93f8a0f 3579 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3580}
3581
bda9020e 3582static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3583{
bda9020e
MT		 3584 if (vcpu->arch.apic &&
3585 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3586 return 0;
bbd9b64e 3587
e93f8a0f 3588 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3589}
3590
2dafc6c2
GN		 3591static void kvm_set_segment(struct kvm_vcpu *vcpu,
3592 struct kvm_segment *var, int seg)
3593{
3594 kvm_x86_ops->set_segment(vcpu, var, seg);
3595}
3596
3597void kvm_get_segment(struct kvm_vcpu *vcpu,
3598 struct kvm_segment *var, int seg)
3599{
3600 kvm_x86_ops->get_segment(vcpu, var, seg);
3601}
3602
c30a358d
JR		 3603static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3604{
3605 return gpa;
3606}
3607
02f59dc9
JR		 3608static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3609{
3610 gpa_t t_gpa;
ab9ae313 3611 struct x86_exception exception;
02f59dc9
JR		 3612
3613 BUG_ON(!mmu_is_nested(vcpu));
3614
3615 /* NPT walks are always user-walks */
3616 access |= PFERR_USER_MASK;
ab9ae313 3617 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3618
3619 return t_gpa;
3620}
3621
ab9ae313
AK		 3622gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3623 struct x86_exception *exception)
1871c602
GN		 3624{
3625 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3626 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3627}
3628
ab9ae313
AK		 3629 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3630 struct x86_exception *exception)
1871c602
GN		 3631{
3632 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3633 access |= PFERR_FETCH_MASK;
ab9ae313 3634 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3635}
3636
ab9ae313
AK		 3637gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3638 struct x86_exception *exception)
1871c602
GN		 3639{
3640 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3641 access |= PFERR_WRITE_MASK;
ab9ae313 3642 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3643}
3644
3645/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3646gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3647 struct x86_exception *exception)
bcc55cba 3648{
ab9ae313 3649 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
bcc55cba
AK		 3650}
3651
1871c602
GN		 3652static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3653 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3654 struct x86_exception *exception)
bbd9b64e
CO		 3655{
3656 void *data = val;
10589a46 3657 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3658
3659 while (bytes) {
14dfe855 3660 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3661 exception);
bbd9b64e 3662 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3663 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3664 int ret;
3665
bcc55cba 3666 if (gpa == UNMAPPED_GVA)
ab9ae313 3667 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3668 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3669 if (ret < 0) {
c3cd7ffa 3670 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3671 goto out;
3672 }
bbd9b64e 3673
77c2002e
IE		 3674 bytes -= toread;
3675 data += toread;
3676 addr += toread;
bbd9b64e 3677 }
10589a46 3678out:
10589a46 3679 return r;
bbd9b64e 3680}
77c2002e 3681
1871c602
GN		 3682/* used for instruction fetching */
3683static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3684 struct kvm_vcpu *vcpu,
3685 struct x86_exception *exception)
1871c602
GN		 3686{
3687 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3688 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3689 access | PFERR_FETCH_MASK,
3690 exception);
1871c602
GN		 3691}
3692
3693static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3694 struct kvm_vcpu *vcpu,
3695 struct x86_exception *exception)
1871c602
GN		 3696{
3697 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3698 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3699 exception);
1871c602
GN		 3700}
3701
3702static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3703 struct kvm_vcpu *vcpu,
3704 struct x86_exception *exception)
1871c602 3705{
bcc55cba 3706 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3707}
3708
7972995b 3709static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3710 unsigned int bytes,
7972995b 3711 struct kvm_vcpu *vcpu,
bcc55cba 3712 struct x86_exception *exception)
77c2002e
IE		 3713{
3714 void *data = val;
3715 int r = X86EMUL_CONTINUE;
3716
3717 while (bytes) {
14dfe855
JR		 3718 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3719 PFERR_WRITE_MASK,
ab9ae313 3720 exception);
77c2002e
IE		 3721 unsigned offset = addr & (PAGE_SIZE-1);
3722 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3723 int ret;
3724
bcc55cba 3725 if (gpa == UNMAPPED_GVA)
ab9ae313 3726 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3727 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3728 if (ret < 0) {
c3cd7ffa 3729 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3730 goto out;
3731 }
3732
3733 bytes -= towrite;
3734 data += towrite;
3735 addr += towrite;
3736 }
3737out:
3738 return r;
3739}
3740
bbd9b64e
CO		 3741static int emulator_read_emulated(unsigned long addr,
3742 void *val,
3743 unsigned int bytes,
bcc55cba 3744 struct x86_exception *exception,
bbd9b64e
CO		 3745 struct kvm_vcpu *vcpu)
3746{
bbd9b64e
CO		 3747 gpa_t gpa;
3748
3749 if (vcpu->mmio_read_completed) {
3750 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3751 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3752 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3753 vcpu->mmio_read_completed = 0;
3754 return X86EMUL_CONTINUE;
3755 }
3756
ab9ae313 3757 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception);
1871c602 3758
8fe681e9 3759 if (gpa == UNMAPPED_GVA)
ab9ae313 3760 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3761
3762 /* For APIC access vmexit */
3763 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3764 goto mmio;
3765
bcc55cba
AK		 3766 if (kvm_read_guest_virt(addr, val, bytes, vcpu, exception)
3767 == X86EMUL_CONTINUE)
bbd9b64e 3768 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3769
3770mmio:
3771 /*
3772 * Is this MMIO handled locally?
3773 */
aec51dc4
AK		 3774 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3775 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3776 return X86EMUL_CONTINUE;
3777 }
aec51dc4
AK		 3778
3779 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3780
3781 vcpu->mmio_needed = 1;
411c35b7
GN		 3782 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3783 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3784 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3785 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3786
c3cd7ffa 3787 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3788}
3789
3200f405 3790int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3791 const void *val, int bytes)
bbd9b64e
CO		 3792{
3793 int ret;
3794
3795 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3796 if (ret < 0)
bbd9b64e 3797 return 0;
ad218f85 3798 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3799 return 1;
3800}
3801
3802static int emulator_write_emulated_onepage(unsigned long addr,
3803 const void *val,
3804 unsigned int bytes,
bcc55cba 3805 struct x86_exception *exception,
bbd9b64e
CO		 3806 struct kvm_vcpu *vcpu)
3807{
10589a46
MT		 3808 gpa_t gpa;
3809
ab9ae313 3810 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception);
bbd9b64e 3811
8fe681e9 3812 if (gpa == UNMAPPED_GVA)
ab9ae313 3813 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3814
3815 /* For APIC access vmexit */
3816 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3817 goto mmio;
3818
3819 if (emulator_write_phys(vcpu, gpa, val, bytes))
3820 return X86EMUL_CONTINUE;
3821
3822mmio:
aec51dc4 3823 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3824 /*
3825 * Is this MMIO handled locally?
3826 */
bda9020e 3827 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3828 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3829
3830 vcpu->mmio_needed = 1;
411c35b7
GN		 3831 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3832 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3833 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3834 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3835 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3836
3837 return X86EMUL_CONTINUE;
3838}
3839
3840int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3841 const void *val,
3842 unsigned int bytes,
bcc55cba 3843 struct x86_exception *exception,
8f6abd06 3844 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3845{
3846 /* Crossing a page boundary? */
3847 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3848 int rc, now;
3849
3850 now = -addr & ~PAGE_MASK;
bcc55cba 3851 rc = emulator_write_emulated_onepage(addr, val, now, exception,
8fe681e9 3852 vcpu);
bbd9b64e
CO		 3853 if (rc != X86EMUL_CONTINUE)
3854 return rc;
3855 addr += now;
3856 val += now;
3857 bytes -= now;
3858 }
bcc55cba 3859 return emulator_write_emulated_onepage(addr, val, bytes, exception,
8fe681e9 3860 vcpu);
bbd9b64e 3861}
bbd9b64e 3862
daea3e73
AK		 3863#define CMPXCHG_TYPE(t, ptr, old, new) \
3864 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3865
3866#ifdef CONFIG_X86_64
3867# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3868#else
3869# define CMPXCHG64(ptr, old, new) \
9749a6c0 3870 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3871#endif
3872
bbd9b64e
CO		 3873static int emulator_cmpxchg_emulated(unsigned long addr,
3874 const void *old,
3875 const void *new,
3876 unsigned int bytes,
bcc55cba 3877 struct x86_exception *exception,
bbd9b64e
CO		 3878 struct kvm_vcpu *vcpu)
3879{
daea3e73
AK		 3880 gpa_t gpa;
3881 struct page *page;
3882 char *kaddr;
3883 bool exchanged;
2bacc55c 3884
daea3e73
AK		 3885 /* guests cmpxchg8b have to be emulated atomically */
3886 if (bytes > 8 || (bytes & (bytes - 1)))
3887 goto emul_write;
10589a46 3888
daea3e73 3889 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3890
daea3e73
AK		 3891 if (gpa == UNMAPPED_GVA ||
3892 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3893 goto emul_write;
2bacc55c 3894
daea3e73
AK		 3895 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3896 goto emul_write;
72dc67a6 3897
daea3e73 3898 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3899 if (is_error_page(page)) {
3900 kvm_release_page_clean(page);
3901 goto emul_write;
3902 }
72dc67a6 3903
daea3e73
AK		 3904 kaddr = kmap_atomic(page, KM_USER0);
3905 kaddr += offset_in_page(gpa);
3906 switch (bytes) {
3907 case 1:
3908 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3909 break;
3910 case 2:
3911 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3912 break;
3913 case 4:
3914 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3915 break;
3916 case 8:
3917 exchanged = CMPXCHG64(kaddr, old, new);
3918 break;
3919 default:
3920 BUG();
2bacc55c 3921 }
daea3e73
AK		 3922 kunmap_atomic(kaddr, KM_USER0);
3923 kvm_release_page_dirty(page);
3924
3925 if (!exchanged)
3926 return X86EMUL_CMPXCHG_FAILED;
3927
8f6abd06
GN		 3928 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3929
3930 return X86EMUL_CONTINUE;
4a5f48f6 3931
3200f405 3932emul_write:
daea3e73 3933 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3934
bcc55cba 3935 return emulator_write_emulated(addr, new, bytes, exception, vcpu);
bbd9b64e
CO		 3936}
3937
cf8f70bf
GN		 3938static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3939{
3940 /* TODO: String I/O for in kernel device */
3941 int r;
3942
3943 if (vcpu->arch.pio.in)
3944 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3945 vcpu->arch.pio.size, pd);
3946 else
3947 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3948 vcpu->arch.pio.port, vcpu->arch.pio.size,
3949 pd);
3950 return r;
3951}
3952
3953
3954static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3955 unsigned int count, struct kvm_vcpu *vcpu)
3956{
7972995b 3957 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3958 goto data_avail;
3959
61cfab2e 3960 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 3961
3962 vcpu->arch.pio.port = port;
3963 vcpu->arch.pio.in = 1;
7972995b 3964 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3965 vcpu->arch.pio.size = size;
3966
3967 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3968 data_avail:
3969 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3970 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3971 return 1;
3972 }
3973
3974 vcpu->run->exit_reason = KVM_EXIT_IO;
3975 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3976 vcpu->run->io.size = size;
3977 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3978 vcpu->run->io.count = count;
3979 vcpu->run->io.port = port;
3980
3981 return 0;
3982}
3983
3984static int emulator_pio_out_emulated(int size, unsigned short port,
3985 const void *val, unsigned int count,
3986 struct kvm_vcpu *vcpu)
3987{
61cfab2e 3988 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 3989
3990 vcpu->arch.pio.port = port;
3991 vcpu->arch.pio.in = 0;
7972995b 3992 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3993 vcpu->arch.pio.size = size;
3994
3995 memcpy(vcpu->arch.pio_data, val, size * count);
3996
3997 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3998 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3999 return 1;
4000 }
4001
4002 vcpu->run->exit_reason = KVM_EXIT_IO;
4003 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4004 vcpu->run->io.size = size;
4005 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4006 vcpu->run->io.count = count;
4007 vcpu->run->io.port = port;
4008
4009 return 0;
4010}
4011
bbd9b64e
CO		 4012static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4013{
4014 return kvm_x86_ops->get_segment_base(vcpu, seg);
4015}
4016
4017int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
4018{
a7052897 4019 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 4020 return X86EMUL_CONTINUE;
4021}
4022
f5f48ee1
SY		 4023int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4024{
4025 if (!need_emulate_wbinvd(vcpu))
4026 return X86EMUL_CONTINUE;
4027
4028 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4029 int cpu = get_cpu();
4030
4031 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4032 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4033 wbinvd_ipi, NULL, 1);
2eec7343 4034 put_cpu();
f5f48ee1 4035 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4036 } else
4037 wbinvd();
f5f48ee1
SY		 4038 return X86EMUL_CONTINUE;
4039}
4040EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4041
bbd9b64e
CO		 4042int emulate_clts(struct kvm_vcpu *vcpu)
4043{
4d4ec087 4044 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 4045 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 4046 return X86EMUL_CONTINUE;
4047}
4048
35aa5375 4049int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 4050{
338dbc97 4051 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 4052}
4053
35aa5375 4054int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 4055{
338dbc97
GN		 4056
4057 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 4058}
4059
52a46617 4060static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4061{
52a46617 4062 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4063}
4064
52a46617 4065static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 4066{
52a46617
GN		 4067 unsigned long value;
4068
4069 switch (cr) {
4070 case 0:
4071 value = kvm_read_cr0(vcpu);
4072 break;
4073 case 2:
4074 value = vcpu->arch.cr2;
4075 break;
4076 case 3:
9f8fe504 4077 value = kvm_read_cr3(vcpu);
52a46617
GN		 4078 break;
4079 case 4:
4080 value = kvm_read_cr4(vcpu);
4081 break;
4082 case 8:
4083 value = kvm_get_cr8(vcpu);
4084 break;
4085 default:
4086 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4087 return 0;
4088 }
4089
4090 return value;
4091}
4092
0f12244f 4093static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 4094{
0f12244f
GN		 4095 int res = 0;
4096
52a46617
GN		 4097 switch (cr) {
4098 case 0:
49a9b07e 4099 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4100 break;
4101 case 2:
4102 vcpu->arch.cr2 = val;
4103 break;
4104 case 3:
2390218b 4105 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4106 break;
4107 case 4:
a83b29c6 4108 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4109 break;
4110 case 8:
eea1cff9 4111 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4112 break;
4113 default:
4114 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4115 res = -1;
52a46617 4116 }
0f12244f
GN		 4117
4118 return res;
52a46617
GN		 4119}
4120
9c537244
GN		 4121static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4122{
4123 return kvm_x86_ops->get_cpl(vcpu);
4124}
4125
2dafc6c2
GN		 4126static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4127{
4128 kvm_x86_ops->get_gdt(vcpu, dt);
4129}
4130
160ce1f1
MG		 4131static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4132{
4133 kvm_x86_ops->get_idt(vcpu, dt);
4134}
4135
5951c442
GN		 4136static unsigned long emulator_get_cached_segment_base(int seg,
4137 struct kvm_vcpu *vcpu)
4138{
4139 return get_segment_base(vcpu, seg);
4140}
4141
2dafc6c2
GN		 4142static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4143 struct kvm_vcpu *vcpu)
4144{
4145 struct kvm_segment var;
4146
4147 kvm_get_segment(vcpu, &var, seg);
4148
4149 if (var.unusable)
4150 return false;
4151
4152 if (var.g)
4153 var.limit >>= 12;
4154 set_desc_limit(desc, var.limit);
4155 set_desc_base(desc, (unsigned long)var.base);
4156 desc->type = var.type;
4157 desc->s = var.s;
4158 desc->dpl = var.dpl;
4159 desc->p = var.present;
4160 desc->avl = var.avl;
4161 desc->l = var.l;
4162 desc->d = var.db;
4163 desc->g = var.g;
4164
4165 return true;
4166}
4167
4168static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4169 struct kvm_vcpu *vcpu)
4170{
4171 struct kvm_segment var;
4172
4173 /* needed to preserve selector */
4174 kvm_get_segment(vcpu, &var, seg);
4175
4176 var.base = get_desc_base(desc);
4177 var.limit = get_desc_limit(desc);
4178 if (desc->g)
4179 var.limit = (var.limit << 12) | 0xfff;
4180 var.type = desc->type;
4181 var.present = desc->p;
4182 var.dpl = desc->dpl;
4183 var.db = desc->d;
4184 var.s = desc->s;
4185 var.l = desc->l;
4186 var.g = desc->g;
4187 var.avl = desc->avl;
4188 var.present = desc->p;
4189 var.unusable = !var.present;
4190 var.padding = 0;
4191
4192 kvm_set_segment(vcpu, &var, seg);
4193 return;
4194}
4195
4196static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4197{
4198 struct kvm_segment kvm_seg;
4199
4200 kvm_get_segment(vcpu, &kvm_seg, seg);
4201 return kvm_seg.selector;
4202}
4203
4204static void emulator_set_segment_selector(u16 sel, int seg,
4205 struct kvm_vcpu *vcpu)
4206{
4207 struct kvm_segment kvm_seg;
4208
4209 kvm_get_segment(vcpu, &kvm_seg, seg);
4210 kvm_seg.selector = sel;
4211 kvm_set_segment(vcpu, &kvm_seg, seg);
4212}
4213
14af3f3c 4214static struct x86_emulate_ops emulate_ops = {
1871c602 4215 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4216 .write_std = kvm_write_guest_virt_system,
1871c602 4217 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4218 .read_emulated = emulator_read_emulated,
4219 .write_emulated = emulator_write_emulated,
4220 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4221 .pio_in_emulated = emulator_pio_in_emulated,
4222 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4223 .get_cached_descriptor = emulator_get_cached_descriptor,
4224 .set_cached_descriptor = emulator_set_cached_descriptor,
4225 .get_segment_selector = emulator_get_segment_selector,
4226 .set_segment_selector = emulator_set_segment_selector,
5951c442 4227 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4228 .get_gdt = emulator_get_gdt,
160ce1f1 4229 .get_idt = emulator_get_idt,
52a46617
GN		 4230 .get_cr = emulator_get_cr,
4231 .set_cr = emulator_set_cr,
9c537244 4232 .cpl = emulator_get_cpl,
35aa5375
GN		 4233 .get_dr = emulator_get_dr,
4234 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4235 .set_msr = kvm_set_msr,
4236 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4237};
4238
5fdbf976
MT		 4239static void cache_all_regs(struct kvm_vcpu *vcpu)
4240{
4241 kvm_register_read(vcpu, VCPU_REGS_RAX);
4242 kvm_register_read(vcpu, VCPU_REGS_RSP);
4243 kvm_register_read(vcpu, VCPU_REGS_RIP);
4244 vcpu->arch.regs_dirty = ~0;
4245}
4246
95cb2295
GN		 4247static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4248{
4249 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4250 /*
4251 * an sti; sti; sequence only disable interrupts for the first
4252 * instruction. So, if the last instruction, be it emulated or
4253 * not, left the system with the INT_STI flag enabled, it
4254 * means that the last instruction is an sti. We should not
4255 * leave the flag on in this case. The same goes for mov ss
4256 */
4257 if (!(int_shadow & mask))
4258 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4259}
4260
54b8486f
GN		 4261static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4262{
4263 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4264 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4265 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4266 else if (ctxt->exception.error_code_valid)
4267 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4268 ctxt->exception.error_code);
54b8486f 4269 else
da9cb575 4270 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4271}
4272
8ec4722d
MG		 4273static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4274{
4275 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4276 int cs_db, cs_l;
4277
4278 cache_all_regs(vcpu);
4279
4280 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4281
4282 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4283 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4284 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4285 vcpu->arch.emulate_ctxt.mode =
4286 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4287 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4288 ? X86EMUL_MODE_VM86 : cs_l
4289 ? X86EMUL_MODE_PROT64 : cs_db
4290 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4291 memset(c, 0, sizeof(struct decode_cache));
4292 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4293}
4294
63995653
MG		 4295int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4296{
4297 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4298 int ret;
4299
4300 init_emulate_ctxt(vcpu);
4301
4302 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4303 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4304 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4305 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4306
4307 if (ret != X86EMUL_CONTINUE)
4308 return EMULATE_FAIL;
4309
4310 vcpu->arch.emulate_ctxt.eip = c->eip;
4311 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4312 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4313 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4314
4315 if (irq == NMI_VECTOR)
4316 vcpu->arch.nmi_pending = false;
4317 else
4318 vcpu->arch.interrupt.pending = false;
4319
4320 return EMULATE_DONE;
4321}
4322EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4323
6d77dbfc
GN		 4324static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4325{
fc3a9157
JR		 4326 int r = EMULATE_DONE;
4327
6d77dbfc
GN		 4328 ++vcpu->stat.insn_emulation_fail;
4329 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4330 if (!is_guest_mode(vcpu)) {
4331 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4332 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4333 vcpu->run->internal.ndata = 0;
4334 r = EMULATE_FAIL;
4335 }
6d77dbfc 4336 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4337
4338 return r;
6d77dbfc
GN		 4339}
4340
a6f177ef
GN		 4341static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4342{
4343 gpa_t gpa;
4344
68be0803
GN		 4345 if (tdp_enabled)
4346 return false;
4347
a6f177ef
GN		 4348 /*
4349 * if emulation was due to access to shadowed page table
4350 * and it failed try to unshadow page and re-entetr the
4351 * guest to let CPU execute the instruction.
4352 */
4353 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4354 return true;
4355
4356 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4357
4358 if (gpa == UNMAPPED_GVA)
4359 return true; /* let cpu generate fault */
4360
4361 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4362 return true;
4363
4364 return false;
4365}
4366
51d8b661
AP		 4367int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4368 unsigned long cr2,
dc25e89e
AP		 4369 int emulation_type,
4370 void *insn,
4371 int insn_len)
bbd9b64e 4372{
95cb2295 4373 int r;
4d2179e1 4374 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4375
26eef70c 4376 kvm_clear_exception_queue(vcpu);
ad312c7c 4377 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4378 /*
56e82318 4379 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4380 * instead of direct ->regs accesses, can save hundred cycles
4381 * on Intel for instructions that don't read/change RSP, for
4382 * for example.
4383 */
4384 cache_all_regs(vcpu);
bbd9b64e 4385
571008da 4386 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4387 init_emulate_ctxt(vcpu);
95cb2295 4388 vcpu->arch.emulate_ctxt.interruptibility = 0;
da9cb575 4389 vcpu->arch.emulate_ctxt.have_exception = false;
4fc40f07 4390 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4391
dc25e89e 4392 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, insn, insn_len);
d47f00a6
JR		 4393 if (r == X86EMUL_PROPAGATE_FAULT)
4394 goto done;
bbd9b64e 4395
e46479f8 4396 trace_kvm_emulate_insn_start(vcpu);
571008da 4397
0cb5762e
AP		 4398 /* Only allow emulation of specific instructions on #UD
4399 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4400 if (emulation_type & EMULTYPE_TRAP_UD) {
4401 if (!c->twobyte)
4402 return EMULATE_FAIL;
4403 switch (c->b) {
4404 case 0x01: /* VMMCALL */
4405 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4406 return EMULATE_FAIL;
4407 break;
4408 case 0x34: /* sysenter */
4409 case 0x35: /* sysexit */
4410 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4411 return EMULATE_FAIL;
4412 break;
4413 case 0x05: /* syscall */
4414 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4415 return EMULATE_FAIL;
4416 break;
4417 default:
4418 return EMULATE_FAIL;
4419 }
4420
4421 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4422 return EMULATE_FAIL;
4423 }
571008da 4424
f2b5756b 4425 ++vcpu->stat.insn_emulation;
bbd9b64e 4426 if (r) {
a6f177ef 4427 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4428 return EMULATE_DONE;
6d77dbfc
GN		 4429 if (emulation_type & EMULTYPE_SKIP)
4430 return EMULATE_FAIL;
4431 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4432 }
4433 }
4434
ba8afb6b
GN		 4435 if (emulation_type & EMULTYPE_SKIP) {
4436 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4437 return EMULATE_DONE;
4438 }
4439
4d2179e1
GN		 4440 /* this is needed for vmware backdor interface to work since it
4441 changes registers values during IO operation */
4442 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4443
5cd21917 4444restart:
9aabc88f 4445 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4446
d2ddd1c4 4447 if (r == EMULATION_FAILED) {
a6f177ef 4448 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4449 return EMULATE_DONE;
4450
6d77dbfc 4451 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4452 }
4453
d47f00a6 4454done:
da9cb575 4455 if (vcpu->arch.emulate_ctxt.have_exception) {
54b8486f 4456 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4457 r = EMULATE_DONE;
4458 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4459 if (!vcpu->arch.pio.in)
4460 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4461 r = EMULATE_DO_MMIO;
4462 } else if (vcpu->mmio_needed) {
3457e419
GN		 4463 if (vcpu->mmio_is_write)
4464 vcpu->mmio_needed = 0;
e85d28f8 4465 r = EMULATE_DO_MMIO;
d2ddd1c4 4466 } else if (r == EMULATION_RESTART)
5cd21917 4467 goto restart;
d2ddd1c4
GN		 4468 else
4469 r = EMULATE_DONE;
f850e2e6 4470
e85d28f8
GN		 4471 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4472 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4473 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4474 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4475 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4476
4477 return r;
de7d789a 4478}
51d8b661 4479EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4480
cf8f70bf 4481int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4482{
cf8f70bf
GN		 4483 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4484 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4485 /* do not return to emulator after return from userspace */
7972995b 4486 vcpu->arch.pio.count = 0;
de7d789a
CO		 4487 return ret;
4488}
cf8f70bf 4489EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4490
8cfdc000
ZA		 4491static void tsc_bad(void *info)
4492{
4493 __get_cpu_var(cpu_tsc_khz) = 0;
4494}
4495
4496static void tsc_khz_changed(void *data)
c8076604 4497{
8cfdc000
ZA		 4498 struct cpufreq_freqs *freq = data;
4499 unsigned long khz = 0;
4500
4501 if (data)
4502 khz = freq->new;
4503 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4504 khz = cpufreq_quick_get(raw_smp_processor_id());
4505 if (!khz)
4506 khz = tsc_khz;
4507 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4508}
4509
c8076604
GH		 4510static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4511 void *data)
4512{
4513 struct cpufreq_freqs *freq = data;
4514 struct kvm *kvm;
4515 struct kvm_vcpu *vcpu;
4516 int i, send_ipi = 0;
4517
8cfdc000
ZA		 4518 /*
4519 * We allow guests to temporarily run on slowing clocks,
4520 * provided we notify them after, or to run on accelerating
4521 * clocks, provided we notify them before. Thus time never
4522 * goes backwards.
4523 *
4524 * However, we have a problem. We can't atomically update
4525 * the frequency of a given CPU from this function; it is
4526 * merely a notifier, which can be called from any CPU.
4527 * Changing the TSC frequency at arbitrary points in time
4528 * requires a recomputation of local variables related to
4529 * the TSC for each VCPU. We must flag these local variables
4530 * to be updated and be sure the update takes place with the
4531 * new frequency before any guests proceed.
4532 *
4533 * Unfortunately, the combination of hotplug CPU and frequency
4534 * change creates an intractable locking scenario; the order
4535 * of when these callouts happen is undefined with respect to
4536 * CPU hotplug, and they can race with each other. As such,
4537 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4538 * undefined; you can actually have a CPU frequency change take
4539 * place in between the computation of X and the setting of the
4540 * variable. To protect against this problem, all updates of
4541 * the per_cpu tsc_khz variable are done in an interrupt
4542 * protected IPI, and all callers wishing to update the value
4543 * must wait for a synchronous IPI to complete (which is trivial
4544 * if the caller is on the CPU already). This establishes the
4545 * necessary total order on variable updates.
4546 *
4547 * Note that because a guest time update may take place
4548 * anytime after the setting of the VCPU's request bit, the
4549 * correct TSC value must be set before the request. However,
4550 * to ensure the update actually makes it to any guest which
4551 * starts running in hardware virtualization between the set
4552 * and the acquisition of the spinlock, we must also ping the
4553 * CPU after setting the request bit.
4554 *
4555 */
4556
c8076604
GH		 4557 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4558 return 0;
4559 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4560 return 0;
8cfdc000
ZA		 4561
4562 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4563
4564 spin_lock(&kvm_lock);
4565 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4566 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4567 if (vcpu->cpu != freq->cpu)
4568 continue;
c285545f 4569 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4570 if (vcpu->cpu != smp_processor_id())
8cfdc000 4571 send_ipi = 1;
c8076604
GH		 4572 }
4573 }
4574 spin_unlock(&kvm_lock);
4575
4576 if (freq->old < freq->new && send_ipi) {
4577 /*
4578 * We upscale the frequency. Must make the guest
4579 * doesn't see old kvmclock values while running with
4580 * the new frequency, otherwise we risk the guest sees
4581 * time go backwards.
4582 *
4583 * In case we update the frequency for another cpu
4584 * (which might be in guest context) send an interrupt
4585 * to kick the cpu out of guest context. Next time
4586 * guest context is entered kvmclock will be updated,
4587 * so the guest will not see stale values.
4588 */
8cfdc000 4589 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4590 }
4591 return 0;
4592}
4593
4594static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4595 .notifier_call = kvmclock_cpufreq_notifier
4596};
4597
4598static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4599 unsigned long action, void *hcpu)
4600{
4601 unsigned int cpu = (unsigned long)hcpu;
4602
4603 switch (action) {
4604 case CPU_ONLINE:
4605 case CPU_DOWN_FAILED:
4606 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4607 break;
4608 case CPU_DOWN_PREPARE:
4609 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4610 break;
4611 }
4612 return NOTIFY_OK;
4613}
4614
4615static struct notifier_block kvmclock_cpu_notifier_block = {
4616 .notifier_call = kvmclock_cpu_notifier,
4617 .priority = -INT_MAX
c8076604
GH		 4618};
4619
b820cc0c
ZA		 4620static void kvm_timer_init(void)
4621{
4622 int cpu;
4623
c285545f 4624 max_tsc_khz = tsc_khz;
8cfdc000 4625 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4626 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4627#ifdef CONFIG_CPU_FREQ
4628 struct cpufreq_policy policy;
4629 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4630 cpu = get_cpu();
4631 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4632 if (policy.cpuinfo.max_freq)
4633 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4634 put_cpu();
c285545f 4635#endif
b820cc0c
ZA		 4636 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4637 CPUFREQ_TRANSITION_NOTIFIER);
4638 }
c285545f 4639 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4640 for_each_online_cpu(cpu)
4641 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4642}
4643
ff9d07a0
ZY		 4644static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4645
4646static int kvm_is_in_guest(void)
4647{
4648 return percpu_read(current_vcpu) != NULL;
4649}
4650
4651static int kvm_is_user_mode(void)
4652{
4653 int user_mode = 3;
dcf46b94 4654
ff9d07a0
ZY		 4655 if (percpu_read(current_vcpu))
4656 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4657
ff9d07a0
ZY		 4658 return user_mode != 0;
4659}
4660
4661static unsigned long kvm_get_guest_ip(void)
4662{
4663 unsigned long ip = 0;
dcf46b94 4664
ff9d07a0
ZY		 4665 if (percpu_read(current_vcpu))
4666 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4667
ff9d07a0
ZY		 4668 return ip;
4669}
4670
4671static struct perf_guest_info_callbacks kvm_guest_cbs = {
4672 .is_in_guest = kvm_is_in_guest,
4673 .is_user_mode = kvm_is_user_mode,
4674 .get_guest_ip = kvm_get_guest_ip,
4675};
4676
4677void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4678{
4679 percpu_write(current_vcpu, vcpu);
4680}
4681EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4682
4683void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4684{
4685 percpu_write(current_vcpu, NULL);
4686}
4687EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4688
f8c16bba 4689int kvm_arch_init(void *opaque)
043405e1 4690{
b820cc0c 4691 int r;
f8c16bba
ZX		 4692 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4693
f8c16bba
ZX		 4694 if (kvm_x86_ops) {
4695 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4696 r = -EEXIST;
4697 goto out;
f8c16bba
ZX		 4698 }
4699
4700 if (!ops->cpu_has_kvm_support()) {
4701 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4702 r = -EOPNOTSUPP;
4703 goto out;
f8c16bba
ZX		 4704 }
4705 if (ops->disabled_by_bios()) {
4706 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4707 r = -EOPNOTSUPP;
4708 goto out;
f8c16bba
ZX		 4709 }
4710
97db56ce
AK		 4711 r = kvm_mmu_module_init();
4712 if (r)
4713 goto out;
4714
4715 kvm_init_msr_list();
4716
f8c16bba 4717 kvm_x86_ops = ops;
56c6d28a 4718 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4719 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4720 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4721
b820cc0c 4722 kvm_timer_init();
c8076604 4723
ff9d07a0
ZY		 4724 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4725
2acf923e
DC		 4726 if (cpu_has_xsave)
4727 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4728
f8c16bba 4729 return 0;
56c6d28a
ZX		 4730
4731out:
56c6d28a 4732 return r;
043405e1 4733}
8776e519 4734
f8c16bba
ZX		 4735void kvm_arch_exit(void)
4736{
ff9d07a0
ZY		 4737 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4738
888d256e
JK		 4739 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4740 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4741 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4742 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4743 kvm_x86_ops = NULL;
56c6d28a
ZX		 4744 kvm_mmu_module_exit();
4745}
f8c16bba 4746
8776e519
HB		 4747int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4748{
4749 ++vcpu->stat.halt_exits;
4750 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4751 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4752 return 1;
4753 } else {
4754 vcpu->run->exit_reason = KVM_EXIT_HLT;
4755 return 0;
4756 }
4757}
4758EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4759
2f333bcb
MT		 4760static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4761 unsigned long a1)
4762{
4763 if (is_long_mode(vcpu))
4764 return a0;
4765 else
4766 return a0 | ((gpa_t)a1 << 32);
4767}
4768
55cd8e5a
GN		 4769int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4770{
4771 u64 param, ingpa, outgpa, ret;
4772 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4773 bool fast, longmode;
4774 int cs_db, cs_l;
4775
4776 /*
4777 * hypercall generates UD from non zero cpl and real mode
4778 * per HYPER-V spec
4779 */
3eeb3288 4780 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4781 kvm_queue_exception(vcpu, UD_VECTOR);
4782 return 0;
4783 }
4784
4785 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4786 longmode = is_long_mode(vcpu) && cs_l == 1;
4787
4788 if (!longmode) {
ccd46936
GN		 4789 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4790 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4791 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4792 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4793 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4794 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4795 }
4796#ifdef CONFIG_X86_64
4797 else {
4798 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4799 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4800 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4801 }
4802#endif
4803
4804 code = param & 0xffff;
4805 fast = (param >> 16) & 0x1;
4806 rep_cnt = (param >> 32) & 0xfff;
4807 rep_idx = (param >> 48) & 0xfff;
4808
4809 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4810
c25bc163
GN		 4811 switch (code) {
4812 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4813 kvm_vcpu_on_spin(vcpu);
4814 break;
4815 default:
4816 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4817 break;
4818 }
55cd8e5a
GN		 4819
4820 ret = res | (((u64)rep_done & 0xfff) << 32);
4821 if (longmode) {
4822 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4823 } else {
4824 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4825 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4826 }
4827
4828 return 1;
4829}
4830
8776e519
HB		 4831int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4832{
4833 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4834 int r = 1;
8776e519 4835
55cd8e5a
GN		 4836 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4837 return kvm_hv_hypercall(vcpu);
4838
5fdbf976
MT		 4839 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4840 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4841 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4842 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4843 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4844
229456fc 4845 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4846
8776e519
HB		 4847 if (!is_long_mode(vcpu)) {
4848 nr &= 0xFFFFFFFF;
4849 a0 &= 0xFFFFFFFF;
4850 a1 &= 0xFFFFFFFF;
4851 a2 &= 0xFFFFFFFF;
4852 a3 &= 0xFFFFFFFF;
4853 }
4854
07708c4a
JK		 4855 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4856 ret = -KVM_EPERM;
4857 goto out;
4858 }
4859
8776e519 4860 switch (nr) {
b93463aa
AK		 4861 case KVM_HC_VAPIC_POLL_IRQ:
4862 ret = 0;
4863 break;
2f333bcb
MT		 4864 case KVM_HC_MMU_OP:
4865 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4866 break;
8776e519
HB		 4867 default:
4868 ret = -KVM_ENOSYS;
4869 break;
4870 }
07708c4a 4871out:
5fdbf976 4872 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4873 ++vcpu->stat.hypercalls;
2f333bcb 4874 return r;
8776e519
HB		 4875}
4876EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4877
4878int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4879{
4880 char instruction[3];
5fdbf976 4881 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4882
8776e519
HB		 4883 /*
4884 * Blow out the MMU to ensure that no other VCPU has an active mapping
4885 * to ensure that the updated hypercall appears atomically across all
4886 * VCPUs.
4887 */
4888 kvm_mmu_zap_all(vcpu->kvm);
4889
8776e519 4890 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4891
8fe681e9 4892 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4893}
4894
8776e519
HB		 4895void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4896{
89a27f4d 4897 struct desc_ptr dt = { limit, base };
8776e519
HB		 4898
4899 kvm_x86_ops->set_gdt(vcpu, &dt);
4900}
4901
4902void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4903{
89a27f4d 4904 struct desc_ptr dt = { limit, base };
8776e519
HB		 4905
4906 kvm_x86_ops->set_idt(vcpu, &dt);
4907}
4908
07716717
DK		 4909static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4910{
ad312c7c
ZX		 4911 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4912 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4913
4914 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4915 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4916 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4917 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4918 if (ej->function == e->function) {
4919 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4920 return j;
4921 }
4922 }
4923 return 0; /* silence gcc, even though control never reaches here */
4924}
4925
4926/* find an entry with matching function, matching index (if needed), and that
4927 * should be read next (if it's stateful) */
4928static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4929 u32 function, u32 index)
4930{
4931 if (e->function != function)
4932 return 0;
4933 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4934 return 0;
4935 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4936 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4937 return 0;
4938 return 1;
4939}
4940
d8017474
AG		 4941struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4942 u32 function, u32 index)
8776e519
HB		 4943{
4944 int i;
d8017474 4945 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4946
ad312c7c 4947 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4948 struct kvm_cpuid_entry2 *e;
4949
ad312c7c 4950 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4951 if (is_matching_cpuid_entry(e, function, index)) {
4952 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4953 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4954 best = e;
4955 break;
4956 }
4957 /*
4958 * Both basic or both extended?
4959 */
4960 if (((e->function ^ function) & 0x80000000) == 0)
4961 if (!best || e->function > best->function)
4962 best = e;
4963 }
d8017474
AG		 4964 return best;
4965}
0e851880 4966EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4967
82725b20
DE		 4968int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4969{
4970 struct kvm_cpuid_entry2 *best;
4971
f7a71197
AK		 4972 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4973 if (!best || best->eax < 0x80000008)
4974 goto not_found;
82725b20
DE		 4975 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4976 if (best)
4977 return best->eax & 0xff;
f7a71197 4978not_found:
82725b20
DE		 4979 return 36;
4980}
4981
d8017474
AG		 4982void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4983{
4984 u32 function, index;
4985 struct kvm_cpuid_entry2 *best;
4986
4987 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4988 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4989 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4990 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4991 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4992 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4993 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4994 if (best) {
5fdbf976
MT		 4995 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4996 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4997 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4998 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4999 }
8776e519 5000 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5001 trace_kvm_cpuid(function,
5002 kvm_register_read(vcpu, VCPU_REGS_RAX),
5003 kvm_register_read(vcpu, VCPU_REGS_RBX),
5004 kvm_register_read(vcpu, VCPU_REGS_RCX),
5005 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5006}
5007EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5008
b6c7a5dc
HB		 5009/*
5010 * Check if userspace requested an interrupt window, and that the
5011 * interrupt window is open.
5012 *
5013 * No need to exit to userspace if we already have an interrupt queued.
5014 */
851ba692 5015static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5016{
8061823a 5017 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5018 vcpu->run->request_interrupt_window &&
5df56646 5019 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5020}
5021
851ba692 5022static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5023{
851ba692
AK		 5024 struct kvm_run *kvm_run = vcpu->run;
5025
91586a3b 5026 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5027 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5028 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5029 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5030 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5031 else
b6c7a5dc 5032 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5033 kvm_arch_interrupt_allowed(vcpu) &&
5034 !kvm_cpu_has_interrupt(vcpu) &&
5035 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5036}
5037
b93463aa
AK		 5038static void vapic_enter(struct kvm_vcpu *vcpu)
5039{
5040 struct kvm_lapic *apic = vcpu->arch.apic;
5041 struct page *page;
5042
5043 if (!apic || !apic->vapic_addr)
5044 return;
5045
5046 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5047
5048 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5049}
5050
5051static void vapic_exit(struct kvm_vcpu *vcpu)
5052{
5053 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5054 int idx;
b93463aa
AK		 5055
5056 if (!apic || !apic->vapic_addr)
5057 return;
5058
f656ce01 5059 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5060 kvm_release_page_dirty(apic->vapic_page);
5061 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5062 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5063}
5064
95ba8273
GN		 5065static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5066{
5067 int max_irr, tpr;
5068
5069 if (!kvm_x86_ops->update_cr8_intercept)
5070 return;
5071
88c808fd
AK		 5072 if (!vcpu->arch.apic)
5073 return;
5074
8db3baa2
GN		 5075 if (!vcpu->arch.apic->vapic_addr)
5076 max_irr = kvm_lapic_find_highest_irr(vcpu);
5077 else
5078 max_irr = -1;
95ba8273
GN		 5079
5080 if (max_irr != -1)
5081 max_irr >>= 4;
5082
5083 tpr = kvm_lapic_get_cr8(vcpu);
5084
5085 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5086}
5087
851ba692 5088static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5089{
5090 /* try to reinject previous events if any */
b59bb7bd 5091 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5092 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5093 vcpu->arch.exception.has_error_code,
5094 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5095 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5096 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5097 vcpu->arch.exception.error_code,
5098 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5099 return;
5100 }
5101
95ba8273
GN		 5102 if (vcpu->arch.nmi_injected) {
5103 kvm_x86_ops->set_nmi(vcpu);
5104 return;
5105 }
5106
5107 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5108 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5109 return;
5110 }
5111
5112 /* try to inject new event if pending */
5113 if (vcpu->arch.nmi_pending) {
5114 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5115 vcpu->arch.nmi_pending = false;
5116 vcpu->arch.nmi_injected = true;
5117 kvm_x86_ops->set_nmi(vcpu);
5118 }
5119 } else if (kvm_cpu_has_interrupt(vcpu)) {
5120 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5121 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5122 false);
5123 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5124 }
5125 }
5126}
5127
2acf923e
DC		 5128static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5129{
5130 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5131 !vcpu->guest_xcr0_loaded) {
5132 /* kvm_set_xcr() also depends on this */
5133 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5134 vcpu->guest_xcr0_loaded = 1;
5135 }
5136}
5137
5138static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5139{
5140 if (vcpu->guest_xcr0_loaded) {
5141 if (vcpu->arch.xcr0 != host_xcr0)
5142 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5143 vcpu->guest_xcr0_loaded = 0;
5144 }
5145}
5146
851ba692 5147static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5148{
5149 int r;
6a8b1d13 5150 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5151 vcpu->run->request_interrupt_window;
b6c7a5dc 5152
3e007509 5153 if (vcpu->requests) {
a8eeb04a 5154 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5155 kvm_mmu_unload(vcpu);
a8eeb04a 5156 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5157 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5158 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5159 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5160 if (unlikely(r))
5161 goto out;
5162 }
a8eeb04a 5163 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5164 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5165 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5166 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5167 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5168 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5169 r = 0;
5170 goto out;
5171 }
a8eeb04a 5172 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5173 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5174 r = 0;
5175 goto out;
5176 }
a8eeb04a 5177 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5178 vcpu->fpu_active = 0;
5179 kvm_x86_ops->fpu_deactivate(vcpu);
5180 }
af585b92
GN		 5181 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5182 /* Page is swapped out. Do synthetic halt */
5183 vcpu->arch.apf.halted = true;
5184 r = 1;
5185 goto out;
5186 }
2f52d58c 5187 }
b93463aa 5188
3e007509
AK		 5189 r = kvm_mmu_reload(vcpu);
5190 if (unlikely(r))
5191 goto out;
5192
b463a6f7
AK		 5193 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5194 inject_pending_event(vcpu);
5195
5196 /* enable NMI/IRQ window open exits if needed */
5197 if (vcpu->arch.nmi_pending)
5198 kvm_x86_ops->enable_nmi_window(vcpu);
5199 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5200 kvm_x86_ops->enable_irq_window(vcpu);
5201
5202 if (kvm_lapic_enabled(vcpu)) {
5203 update_cr8_intercept(vcpu);
5204 kvm_lapic_sync_to_vapic(vcpu);
5205 }
5206 }
5207
b6c7a5dc
HB		 5208 preempt_disable();
5209
5210 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5211 if (vcpu->fpu_active)
5212 kvm_load_guest_fpu(vcpu);
2acf923e 5213 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5214
d94e1dc9
AK		 5215 atomic_set(&vcpu->guest_mode, 1);
5216 smp_wmb();
b6c7a5dc 5217
d94e1dc9 5218 local_irq_disable();
32f88400 5219
d94e1dc9
AK		 5220 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5221 || need_resched() || signal_pending(current)) {
5222 atomic_set(&vcpu->guest_mode, 0);
5223 smp_wmb();
6c142801
AK		 5224 local_irq_enable();
5225 preempt_enable();
b463a6f7 5226 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5227 r = 1;
5228 goto out;
5229 }
5230
f656ce01 5231 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5232
b6c7a5dc
HB		 5233 kvm_guest_enter();
5234
42dbaa5a 5235 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5236 set_debugreg(0, 7);
5237 set_debugreg(vcpu->arch.eff_db[0], 0);
5238 set_debugreg(vcpu->arch.eff_db[1], 1);
5239 set_debugreg(vcpu->arch.eff_db[2], 2);
5240 set_debugreg(vcpu->arch.eff_db[3], 3);
5241 }
b6c7a5dc 5242
229456fc 5243 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5244 kvm_x86_ops->run(vcpu);
b6c7a5dc 5245
24f1e32c
FW		 5246 /*
5247 * If the guest has used debug registers, at least dr7
5248 * will be disabled while returning to the host.
5249 * If we don't have active breakpoints in the host, we don't
5250 * care about the messed up debug address registers. But if
5251 * we have some of them active, restore the old state.
5252 */
59d8eb53 5253 if (hw_breakpoint_active())
24f1e32c 5254 hw_breakpoint_restore();
42dbaa5a 5255
1d5f066e
ZA		 5256 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5257
d94e1dc9
AK		 5258 atomic_set(&vcpu->guest_mode, 0);
5259 smp_wmb();
b6c7a5dc
HB		 5260 local_irq_enable();
5261
5262 ++vcpu->stat.exits;
5263
5264 /*
5265 * We must have an instruction between local_irq_enable() and
5266 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5267 * the interrupt shadow. The stat.exits increment will do nicely.
5268 * But we need to prevent reordering, hence this barrier():
5269 */
5270 barrier();
5271
5272 kvm_guest_exit();
5273
5274 preempt_enable();
5275
f656ce01 5276 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5277
b6c7a5dc
HB		 5278 /*
5279 * Profile KVM exit RIPs:
5280 */
5281 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5282 unsigned long rip = kvm_rip_read(vcpu);
5283 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5284 }
5285
298101da 5286
b93463aa
AK		 5287 kvm_lapic_sync_from_vapic(vcpu);
5288
851ba692 5289 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5290out:
5291 return r;
5292}
b6c7a5dc 5293
09cec754 5294
851ba692 5295static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5296{
5297 int r;
f656ce01 5298 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5299
5300 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5301 pr_debug("vcpu %d received sipi with vector # %x\n",
5302 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5303 kvm_lapic_reset(vcpu);
5f179287 5304 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5305 if (r)
5306 return r;
5307 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5308 }
5309
f656ce01 5310 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5311 vapic_enter(vcpu);
5312
5313 r = 1;
5314 while (r > 0) {
af585b92
GN		 5315 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5316 !vcpu->arch.apf.halted)
851ba692 5317 r = vcpu_enter_guest(vcpu);
d7690175 5318 else {
f656ce01 5319 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5320 kvm_vcpu_block(vcpu);
f656ce01 5321 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5322 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5323 {
5324 switch(vcpu->arch.mp_state) {
5325 case KVM_MP_STATE_HALTED:
d7690175 5326 vcpu->arch.mp_state =
09cec754
GN		 5327 KVM_MP_STATE_RUNNABLE;
5328 case KVM_MP_STATE_RUNNABLE:
af585b92 5329 vcpu->arch.apf.halted = false;
09cec754
GN		 5330 break;
5331 case KVM_MP_STATE_SIPI_RECEIVED:
5332 default:
5333 r = -EINTR;
5334 break;
5335 }
5336 }
d7690175
MT		 5337 }
5338
09cec754
GN		 5339 if (r <= 0)
5340 break;
5341
5342 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5343 if (kvm_cpu_has_pending_timer(vcpu))
5344 kvm_inject_pending_timer_irqs(vcpu);
5345
851ba692 5346 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5347 r = -EINTR;
851ba692 5348 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5349 ++vcpu->stat.request_irq_exits;
5350 }
af585b92
GN		 5351
5352 kvm_check_async_pf_completion(vcpu);
5353
09cec754
GN		 5354 if (signal_pending(current)) {
5355 r = -EINTR;
851ba692 5356 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5357 ++vcpu->stat.signal_exits;
5358 }
5359 if (need_resched()) {
f656ce01 5360 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5361 kvm_resched(vcpu);
f656ce01 5362 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5363 }
b6c7a5dc
HB		 5364 }
5365
f656ce01 5366 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5367
b93463aa
AK		 5368 vapic_exit(vcpu);
5369
b6c7a5dc
HB		 5370 return r;
5371}
5372
5373int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5374{
5375 int r;
5376 sigset_t sigsaved;
5377
ac9f6dc0
AK		 5378 if (vcpu->sigset_active)
5379 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5380
a4535290 5381 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5382 kvm_vcpu_block(vcpu);
d7690175 5383 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5384 r = -EAGAIN;
5385 goto out;
b6c7a5dc
HB		 5386 }
5387
b6c7a5dc 5388 /* re-sync apic's tpr */
eea1cff9
AP		 5389 if (!irqchip_in_kernel(vcpu->kvm)) {
5390 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5391 r = -EINVAL;
5392 goto out;
5393 }
5394 }
b6c7a5dc 5395
d2ddd1c4 5396 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5397 if (vcpu->mmio_needed) {
5398 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5399 vcpu->mmio_read_completed = 1;
5400 vcpu->mmio_needed = 0;
b6c7a5dc 5401 }
f656ce01 5402 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
51d8b661 5403 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
f656ce01 5404 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5405 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5406 r = 0;
5407 goto out;
5408 }
5409 }
5fdbf976
MT		 5410 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5411 kvm_register_write(vcpu, VCPU_REGS_RAX,
5412 kvm_run->hypercall.ret);
b6c7a5dc 5413
851ba692 5414 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5415
5416out:
f1d86e46 5417 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5418 if (vcpu->sigset_active)
5419 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5420
b6c7a5dc
HB		 5421 return r;
5422}
5423
5424int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5425{
5fdbf976
MT		 5426 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5427 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5428 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5429 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5430 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5431 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5432 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5433 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5434#ifdef CONFIG_X86_64
5fdbf976
MT		 5435 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5436 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5437 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5438 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5439 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5440 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5441 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5442 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5443#endif
5444
5fdbf976 5445 regs->rip = kvm_rip_read(vcpu);
91586a3b 5446 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5447
b6c7a5dc
HB		 5448 return 0;
5449}
5450
5451int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5452{
5fdbf976
MT		 5453 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5454 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5455 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5456 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5457 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5458 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5459 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5460 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5461#ifdef CONFIG_X86_64
5fdbf976
MT		 5462 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5463 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5464 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5465 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5466 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5467 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5468 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5469 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5470#endif
5471
5fdbf976 5472 kvm_rip_write(vcpu, regs->rip);
91586a3b 5473 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5474
b4f14abd
JK		 5475 vcpu->arch.exception.pending = false;
5476
3842d135
AK		 5477 kvm_make_request(KVM_REQ_EVENT, vcpu);
5478
b6c7a5dc
HB		 5479 return 0;
5480}
5481
b6c7a5dc
HB		 5482void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5483{
5484 struct kvm_segment cs;
5485
3e6e0aab 5486 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5487 *db = cs.db;
5488 *l = cs.l;
5489}
5490EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5491
5492int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5493 struct kvm_sregs *sregs)
5494{
89a27f4d 5495 struct desc_ptr dt;
b6c7a5dc 5496
3e6e0aab
GT		 5497 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5498 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5499 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5500 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5501 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5502 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5503
3e6e0aab
GT		 5504 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5505 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5506
5507 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5508 sregs->idt.limit = dt.size;
5509 sregs->idt.base = dt.address;
b6c7a5dc 5510 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5511 sregs->gdt.limit = dt.size;
5512 sregs->gdt.base = dt.address;
b6c7a5dc 5513
4d4ec087 5514 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5515 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5516 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5517 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5518 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5519 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5520 sregs->apic_base = kvm_get_apic_base(vcpu);
5521
923c61bb 5522 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5523
36752c9b 5524 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5525 set_bit(vcpu->arch.interrupt.nr,
5526 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5527
b6c7a5dc
HB		 5528 return 0;
5529}
5530
62d9f0db
MT		 5531int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5532 struct kvm_mp_state *mp_state)
5533{
62d9f0db 5534 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5535 return 0;
5536}
5537
5538int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5539 struct kvm_mp_state *mp_state)
5540{
62d9f0db 5541 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5542 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5543 return 0;
5544}
5545
e269fb21
JK		 5546int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5547 bool has_error_code, u32 error_code)
b6c7a5dc 5548{
4d2179e1 5549 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5550 int ret;
e01c2426 5551
8ec4722d 5552 init_emulate_ctxt(vcpu);
c697518a 5553
9aabc88f 5554 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5555 tss_selector, reason, has_error_code,
5556 error_code);
c697518a 5557
c697518a 5558 if (ret)
19d04437 5559 return EMULATE_FAIL;
37817f29 5560
4d2179e1 5561 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5562 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437 5563 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5564 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5565 return EMULATE_DONE;
37817f29
IE		 5566}
5567EXPORT_SYMBOL_GPL(kvm_task_switch);
5568
b6c7a5dc
HB		 5569int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5570 struct kvm_sregs *sregs)
5571{
5572 int mmu_reset_needed = 0;
923c61bb 5573 int pending_vec, max_bits;
89a27f4d 5574 struct desc_ptr dt;
b6c7a5dc 5575
89a27f4d
GN		 5576 dt.size = sregs->idt.limit;
5577 dt.address = sregs->idt.base;
b6c7a5dc 5578 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5579 dt.size = sregs->gdt.limit;
5580 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5581 kvm_x86_ops->set_gdt(vcpu, &dt);
5582
ad312c7c 5583 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5584 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5585 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5586
2d3ad1f4 5587 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5588
f6801dff 5589 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5590 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5591 kvm_set_apic_base(vcpu, sregs->apic_base);
5592
4d4ec087 5593 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5594 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5595 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5596
fc78f519 5597 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5598 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5599 if (sregs->cr4 & X86_CR4_OSXSAVE)
5600 update_cpuid(vcpu);
7c93be44 5601 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5602 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5603 mmu_reset_needed = 1;
5604 }
b6c7a5dc
HB		 5605
5606 if (mmu_reset_needed)
5607 kvm_mmu_reset_context(vcpu);
5608
923c61bb
GN		 5609 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5610 pending_vec = find_first_bit(
5611 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5612 if (pending_vec < max_bits) {
66fd3f7f 5613 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5614 pr_debug("Set back pending irq %d\n", pending_vec);
5615 if (irqchip_in_kernel(vcpu->kvm))
5616 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5617 }
5618
3e6e0aab
GT		 5619 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5620 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5621 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5622 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5623 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5624 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5625
3e6e0aab
GT		 5626 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5627 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5628
5f0269f5
ME		 5629 update_cr8_intercept(vcpu);
5630
9c3e4aab 5631 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5632 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5633 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5634 !is_protmode(vcpu))
9c3e4aab
MT		 5635 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5636
3842d135
AK		 5637 kvm_make_request(KVM_REQ_EVENT, vcpu);
5638
b6c7a5dc
HB		 5639 return 0;
5640}
5641
d0bfb940
JK		 5642int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5643 struct kvm_guest_debug *dbg)
b6c7a5dc 5644{
355be0b9 5645 unsigned long rflags;
ae675ef0 5646 int i, r;
b6c7a5dc 5647
4f926bf2
JK		 5648 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5649 r = -EBUSY;
5650 if (vcpu->arch.exception.pending)
2122ff5e 5651 goto out;
4f926bf2
JK		 5652 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5653 kvm_queue_exception(vcpu, DB_VECTOR);
5654 else
5655 kvm_queue_exception(vcpu, BP_VECTOR);
5656 }
5657
91586a3b
JK		 5658 /*
5659 * Read rflags as long as potentially injected trace flags are still
5660 * filtered out.
5661 */
5662 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5663
5664 vcpu->guest_debug = dbg->control;
5665 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5666 vcpu->guest_debug = 0;
5667
5668 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5669 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5670 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5671 vcpu->arch.switch_db_regs =
5672 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5673 } else {
5674 for (i = 0; i < KVM_NR_DB_REGS; i++)
5675 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5676 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5677 }
5678
f92653ee
JK		 5679 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5680 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5681 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5682
91586a3b
JK		 5683 /*
5684 * Trigger an rflags update that will inject or remove the trace
5685 * flags.
5686 */
5687 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5688
355be0b9 5689 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5690
4f926bf2 5691 r = 0;
d0bfb940 5692
2122ff5e 5693out:
b6c7a5dc
HB		 5694
5695 return r;
5696}
5697
8b006791
ZX		 5698/*
5699 * Translate a guest virtual address to a guest physical address.
5700 */
5701int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5702 struct kvm_translation *tr)
5703{
5704 unsigned long vaddr = tr->linear_address;
5705 gpa_t gpa;
f656ce01 5706 int idx;
8b006791 5707
f656ce01 5708 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5709 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5710 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5711 tr->physical_address = gpa;
5712 tr->valid = gpa != UNMAPPED_GVA;
5713 tr->writeable = 1;
5714 tr->usermode = 0;
8b006791
ZX		 5715
5716 return 0;
5717}
5718
d0752060
HB		 5719int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5720{
98918833
SY		 5721 struct i387_fxsave_struct *fxsave =
5722 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5723
d0752060
HB		 5724 memcpy(fpu->fpr, fxsave->st_space, 128);
5725 fpu->fcw = fxsave->cwd;
5726 fpu->fsw = fxsave->swd;
5727 fpu->ftwx = fxsave->twd;
5728 fpu->last_opcode = fxsave->fop;
5729 fpu->last_ip = fxsave->rip;
5730 fpu->last_dp = fxsave->rdp;
5731 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5732
d0752060
HB		 5733 return 0;
5734}
5735
5736int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5737{
98918833
SY		 5738 struct i387_fxsave_struct *fxsave =
5739 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5740
d0752060
HB		 5741 memcpy(fxsave->st_space, fpu->fpr, 128);
5742 fxsave->cwd = fpu->fcw;
5743 fxsave->swd = fpu->fsw;
5744 fxsave->twd = fpu->ftwx;
5745 fxsave->fop = fpu->last_opcode;
5746 fxsave->rip = fpu->last_ip;
5747 fxsave->rdp = fpu->last_dp;
5748 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5749
d0752060
HB		 5750 return 0;
5751}
5752
10ab25cd 5753int fx_init(struct kvm_vcpu *vcpu)
d0752060 5754{
10ab25cd
JK		 5755 int err;
5756
5757 err = fpu_alloc(&vcpu->arch.guest_fpu);
5758 if (err)
5759 return err;
5760
98918833 5761 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5762
2acf923e
DC		 5763 /*
5764 * Ensure guest xcr0 is valid for loading
5765 */
5766 vcpu->arch.xcr0 = XSTATE_FP;
5767
ad312c7c 5768 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5769
5770 return 0;
d0752060
HB		 5771}
5772EXPORT_SYMBOL_GPL(fx_init);
5773
98918833
SY		 5774static void fx_free(struct kvm_vcpu *vcpu)
5775{
5776 fpu_free(&vcpu->arch.guest_fpu);
5777}
5778
d0752060
HB		 5779void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5780{
2608d7a1 5781 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5782 return;
5783
2acf923e
DC		 5784 /*
5785 * Restore all possible states in the guest,
5786 * and assume host would use all available bits.
5787 * Guest xcr0 would be loaded later.
5788 */
5789 kvm_put_guest_xcr0(vcpu);
d0752060 5790 vcpu->guest_fpu_loaded = 1;
7cf30855 5791 unlazy_fpu(current);
98918833 5792 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5793 trace_kvm_fpu(1);
d0752060 5794}
d0752060
HB		 5795
5796void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5797{
2acf923e
DC		 5798 kvm_put_guest_xcr0(vcpu);
5799
d0752060
HB		 5800 if (!vcpu->guest_fpu_loaded)
5801 return;
5802
5803 vcpu->guest_fpu_loaded = 0;
98918833 5804 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5805 ++vcpu->stat.fpu_reload;
a8eeb04a 5806 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5807 trace_kvm_fpu(0);
d0752060 5808}
e9b11c17
ZX		 5809
5810void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5811{
7f1ea208
JR		 5812 if (vcpu->arch.time_page) {
5813 kvm_release_page_dirty(vcpu->arch.time_page);
5814 vcpu->arch.time_page = NULL;
5815 }
5816
f5f48ee1 5817 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5818 fx_free(vcpu);
e9b11c17
ZX		 5819 kvm_x86_ops->vcpu_free(vcpu);
5820}
5821
5822struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5823 unsigned int id)
5824{
6755bae8
ZA		 5825 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5826 printk_once(KERN_WARNING
5827 "kvm: SMP vm created on host with unstable TSC; "
5828 "guest TSC will not be reliable\n");
26e5215f
AK		 5829 return kvm_x86_ops->vcpu_create(kvm, id);
5830}
e9b11c17 5831
26e5215f
AK		 5832int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5833{
5834 int r;
e9b11c17 5835
0bed3b56 5836 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5837 vcpu_load(vcpu);
5838 r = kvm_arch_vcpu_reset(vcpu);
5839 if (r == 0)
5840 r = kvm_mmu_setup(vcpu);
5841 vcpu_put(vcpu);
5842 if (r < 0)
5843 goto free_vcpu;
5844
26e5215f 5845 return 0;
e9b11c17
ZX		 5846free_vcpu:
5847 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5848 return r;
e9b11c17
ZX		 5849}
5850
d40ccc62 5851void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5852{
344d9588
GN		 5853 vcpu->arch.apf.msr_val = 0;
5854
e9b11c17
ZX		 5855 vcpu_load(vcpu);
5856 kvm_mmu_unload(vcpu);
5857 vcpu_put(vcpu);
5858
98918833 5859 fx_free(vcpu);
e9b11c17
ZX		 5860 kvm_x86_ops->vcpu_free(vcpu);
5861}
5862
5863int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5864{
448fa4a9
JK		 5865 vcpu->arch.nmi_pending = false;
5866 vcpu->arch.nmi_injected = false;
5867
42dbaa5a
JK		 5868 vcpu->arch.switch_db_regs = 0;
5869 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5870 vcpu->arch.dr6 = DR6_FIXED_1;
5871 vcpu->arch.dr7 = DR7_FIXED_1;
5872
3842d135 5873 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5874 vcpu->arch.apf.msr_val = 0;
3842d135 5875
af585b92
GN		 5876 kvm_clear_async_pf_completion_queue(vcpu);
5877 kvm_async_pf_hash_reset(vcpu);
5878 vcpu->arch.apf.halted = false;
5879
e9b11c17
ZX		 5880 return kvm_x86_ops->vcpu_reset(vcpu);
5881}
5882
10474ae8 5883int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5884{
ca84d1a2
ZA		 5885 struct kvm *kvm;
5886 struct kvm_vcpu *vcpu;
5887 int i;
18863bdd
AK		 5888
5889 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5890 list_for_each_entry(kvm, &vm_list, vm_list)
5891 kvm_for_each_vcpu(i, vcpu, kvm)
5892 if (vcpu->cpu == smp_processor_id())
c285545f 5893 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5894 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5895}
5896
5897void kvm_arch_hardware_disable(void *garbage)
5898{
5899 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5900 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5901}
5902
5903int kvm_arch_hardware_setup(void)
5904{
5905 return kvm_x86_ops->hardware_setup();
5906}
5907
5908void kvm_arch_hardware_unsetup(void)
5909{
5910 kvm_x86_ops->hardware_unsetup();
5911}
5912
5913void kvm_arch_check_processor_compat(void *rtn)
5914{
5915 kvm_x86_ops->check_processor_compatibility(rtn);
5916}
5917
5918int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5919{
5920 struct page *page;
5921 struct kvm *kvm;
5922 int r;
5923
5924 BUG_ON(vcpu->kvm == NULL);
5925 kvm = vcpu->kvm;
5926
9aabc88f 5927 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5928 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5929 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5930 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5931 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5932 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5933 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5934 else
a4535290 5935 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5936
5937 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5938 if (!page) {
5939 r = -ENOMEM;
5940 goto fail;
5941 }
ad312c7c 5942 vcpu->arch.pio_data = page_address(page);
e9b11c17 5943
c285545f
ZA		 5944 if (!kvm->arch.virtual_tsc_khz)
5945 kvm_arch_set_tsc_khz(kvm, max_tsc_khz);
5946
e9b11c17
ZX		 5947 r = kvm_mmu_create(vcpu);
5948 if (r < 0)
5949 goto fail_free_pio_data;
5950
5951 if (irqchip_in_kernel(kvm)) {
5952 r = kvm_create_lapic(vcpu);
5953 if (r < 0)
5954 goto fail_mmu_destroy;
5955 }
5956
890ca9ae
HY		 5957 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5958 GFP_KERNEL);
5959 if (!vcpu->arch.mce_banks) {
5960 r = -ENOMEM;
443c39bc 5961 goto fail_free_lapic;
890ca9ae
HY		 5962 }
5963 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5964
f5f48ee1
SY		 5965 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5966 goto fail_free_mce_banks;
5967
af585b92
GN		 5968 kvm_async_pf_hash_reset(vcpu);
5969
e9b11c17 5970 return 0;
f5f48ee1
SY		 5971fail_free_mce_banks:
5972 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5973fail_free_lapic:
5974 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5975fail_mmu_destroy:
5976 kvm_mmu_destroy(vcpu);
5977fail_free_pio_data:
ad312c7c 5978 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5979fail:
5980 return r;
5981}
5982
5983void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5984{
f656ce01
MT		 5985 int idx;
5986
36cb93fd 5987 kfree(vcpu->arch.mce_banks);
e9b11c17 5988 kvm_free_lapic(vcpu);
f656ce01 5989 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5990 kvm_mmu_destroy(vcpu);
f656ce01 5991 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5992 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5993}
d19a9cd2 5994
d89f5eff 5995int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 5996{
f05e70ac 5997 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5998 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5999
5550af4d
SY		 6000 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6001 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6002
99e3e30a 6003 spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6004
d89f5eff 6005 return 0;
d19a9cd2
ZX		 6006}
6007
6008static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6009{
6010 vcpu_load(vcpu);
6011 kvm_mmu_unload(vcpu);
6012 vcpu_put(vcpu);
6013}
6014
6015static void kvm_free_vcpus(struct kvm *kvm)
6016{
6017 unsigned int i;
988a2cae 6018 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6019
6020 /*
6021 * Unpin any mmu pages first.
6022 */
af585b92
GN		 6023 kvm_for_each_vcpu(i, vcpu, kvm) {
6024 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6025 kvm_unload_vcpu_mmu(vcpu);
af585b92 6026 }
988a2cae
GN		 6027 kvm_for_each_vcpu(i, vcpu, kvm)
6028 kvm_arch_vcpu_free(vcpu);
6029
6030 mutex_lock(&kvm->lock);
6031 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6032 kvm->vcpus[i] = NULL;
d19a9cd2 6033
988a2cae
GN		 6034 atomic_set(&kvm->online_vcpus, 0);
6035 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6036}
6037
ad8ba2cd
SY		 6038void kvm_arch_sync_events(struct kvm *kvm)
6039{
ba4cef31 6040 kvm_free_all_assigned_devices(kvm);
aea924f6 6041 kvm_free_pit(kvm);
ad8ba2cd
SY		 6042}
6043
d19a9cd2
ZX		 6044void kvm_arch_destroy_vm(struct kvm *kvm)
6045{
6eb55818 6046 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6047 kfree(kvm->arch.vpic);
6048 kfree(kvm->arch.vioapic);
d19a9cd2 6049 kvm_free_vcpus(kvm);
3d45830c
AK		 6050 if (kvm->arch.apic_access_page)
6051 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6052 if (kvm->arch.ept_identity_pagetable)
6053 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6054}
0de10343 6055
f7784b8e
MT		 6056int kvm_arch_prepare_memory_region(struct kvm *kvm,
6057 struct kvm_memory_slot *memslot,
0de10343 6058 struct kvm_memory_slot old,
f7784b8e 6059 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6060 int user_alloc)
6061{
f7784b8e 6062 int npages = memslot->npages;
7ac77099
AK		 6063 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6064
6065 /* Prevent internal slot pages from being moved by fork()/COW. */
6066 if (memslot->id >= KVM_MEMORY_SLOTS)
6067 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6068
6069 /*To keep backward compatibility with older userspace,
6070 *x86 needs to hanlde !user_alloc case.
6071 */
6072 if (!user_alloc) {
6073 if (npages && !old.rmap) {
604b38ac
AA		 6074 unsigned long userspace_addr;
6075
72dc67a6 6076 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6077 userspace_addr = do_mmap(NULL, 0,
6078 npages * PAGE_SIZE,
6079 PROT_READ | PROT_WRITE,
7ac77099 6080 map_flags,
604b38ac 6081 0);
72dc67a6 6082 up_write(&current->mm->mmap_sem);
0de10343 6083
604b38ac
AA		 6084 if (IS_ERR((void *)userspace_addr))
6085 return PTR_ERR((void *)userspace_addr);
6086
604b38ac 6087 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6088 }
6089 }
6090
f7784b8e
MT		 6091
6092 return 0;
6093}
6094
6095void kvm_arch_commit_memory_region(struct kvm *kvm,
6096 struct kvm_userspace_memory_region *mem,
6097 struct kvm_memory_slot old,
6098 int user_alloc)
6099{
6100
6101 int npages = mem->memory_size >> PAGE_SHIFT;
6102
6103 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6104 int ret;
6105
6106 down_write(&current->mm->mmap_sem);
6107 ret = do_munmap(current->mm, old.userspace_addr,
6108 old.npages * PAGE_SIZE);
6109 up_write(&current->mm->mmap_sem);
6110 if (ret < 0)
6111 printk(KERN_WARNING
6112 "kvm_vm_ioctl_set_memory_region: "
6113 "failed to munmap memory\n");
6114 }
6115
7c8a83b7 6116 spin_lock(&kvm->mmu_lock);
f05e70ac 6117 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 6118 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6119 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6120 }
6121
6122 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6123 spin_unlock(&kvm->mmu_lock);
0de10343 6124}
1d737c8a 6125
34d4cb8f
MT		 6126void kvm_arch_flush_shadow(struct kvm *kvm)
6127{
6128 kvm_mmu_zap_all(kvm);
8986ecc0 6129 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6130}
6131
1d737c8a
ZX		 6132int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6133{
af585b92
GN		 6134 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6135 !vcpu->arch.apf.halted)
6136 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6137 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6138 || vcpu->arch.nmi_pending ||
6139 (kvm_arch_interrupt_allowed(vcpu) &&
6140 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6141}
5736199a 6142
5736199a
ZX		 6143void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6144{
32f88400
MT		 6145 int me;
6146 int cpu = vcpu->cpu;
5736199a
ZX		 6147
6148 if (waitqueue_active(&vcpu->wq)) {
6149 wake_up_interruptible(&vcpu->wq);
6150 ++vcpu->stat.halt_wakeup;
6151 }
32f88400
MT		 6152
6153 me = get_cpu();
6154 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 6155 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 6156 smp_send_reschedule(cpu);
e9571ed5 6157 put_cpu();
5736199a 6158}
78646121
GN		 6159
6160int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6161{
6162 return kvm_x86_ops->interrupt_allowed(vcpu);
6163}
229456fc 6164
f92653ee
JK		 6165bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6166{
6167 unsigned long current_rip = kvm_rip_read(vcpu) +
6168 get_segment_base(vcpu, VCPU_SREG_CS);
6169
6170 return current_rip == linear_rip;
6171}
6172EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6173
94fe45da
JK		 6174unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6175{
6176 unsigned long rflags;
6177
6178 rflags = kvm_x86_ops->get_rflags(vcpu);
6179 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6180 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6181 return rflags;
6182}
6183EXPORT_SYMBOL_GPL(kvm_get_rflags);
6184
6185void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6186{
6187 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6188 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6189 rflags |= X86_EFLAGS_TF;
94fe45da 6190 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6191 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6192}
6193EXPORT_SYMBOL_GPL(kvm_set_rflags);
6194
56028d08
GN		 6195void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6196{
6197 int r;
6198
fb67e14f 6199 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6200 is_error_page(work->page))
56028d08
GN		 6201 return;
6202
6203 r = kvm_mmu_reload(vcpu);
6204 if (unlikely(r))
6205 return;
6206
fb67e14f
XG		 6207 if (!vcpu->arch.mmu.direct_map &&
6208 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6209 return;
6210
56028d08
GN		 6211 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6212}
6213
af585b92
GN		 6214static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6215{
6216 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6217}
6218
6219static inline u32 kvm_async_pf_next_probe(u32 key)
6220{
6221 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6222}
6223
6224static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6225{
6226 u32 key = kvm_async_pf_hash_fn(gfn);
6227
6228 while (vcpu->arch.apf.gfns[key] != ~0)
6229 key = kvm_async_pf_next_probe(key);
6230
6231 vcpu->arch.apf.gfns[key] = gfn;
6232}
6233
6234static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6235{
6236 int i;
6237 u32 key = kvm_async_pf_hash_fn(gfn);
6238
6239 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6240 (vcpu->arch.apf.gfns[key] != gfn &&
6241 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6242 key = kvm_async_pf_next_probe(key);
6243
6244 return key;
6245}
6246
6247bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6248{
6249 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6250}
6251
6252static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6253{
6254 u32 i, j, k;
6255
6256 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6257 while (true) {
6258 vcpu->arch.apf.gfns[i] = ~0;
6259 do {
6260 j = kvm_async_pf_next_probe(j);
6261 if (vcpu->arch.apf.gfns[j] == ~0)
6262 return;
6263 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6264 /*
6265 * k lies cyclically in ]i,j]
6266 * | i.k.j |
6267 * |....j i.k.| or |.k..j i...|
6268 */
6269 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6270 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6271 i = j;
6272 }
6273}
6274
7c90705b
GN		 6275static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6276{
6277
6278 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6279 sizeof(val));
6280}
6281
af585b92
GN		 6282void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6283 struct kvm_async_pf *work)
6284{
6389ee94
AK		 6285 struct x86_exception fault;
6286
7c90705b 6287 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6288 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6289
6290 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6291 (vcpu->arch.apf.send_user_only &&
6292 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6293 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6294 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6295 fault.vector = PF_VECTOR;
6296 fault.error_code_valid = true;
6297 fault.error_code = 0;
6298 fault.nested_page_fault = false;
6299 fault.address = work->arch.token;
6300 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6301 }
af585b92
GN		 6302}
6303
6304void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6305 struct kvm_async_pf *work)
6306{
6389ee94
AK		 6307 struct x86_exception fault;
6308
7c90705b
GN		 6309 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6310 if (is_error_page(work->page))
6311 work->arch.token = ~0; /* broadcast wakeup */
6312 else
6313 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6314
6315 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6316 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6317 fault.vector = PF_VECTOR;
6318 fault.error_code_valid = true;
6319 fault.error_code = 0;
6320 fault.nested_page_fault = false;
6321 fault.address = work->arch.token;
6322 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6323 }
e6d53e3b 6324 vcpu->arch.apf.halted = false;
7c90705b
GN		 6325}
6326
6327bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6328{
6329 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6330 return true;
6331 else
6332 return !kvm_event_needs_reinjection(vcpu) &&
6333 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6334}
6335
229456fc
MT		 6336EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6337EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6338EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6339EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6340EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6341EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6342EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6343EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6344EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6345EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6346EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6347EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux 6.x block layer and io_uring tree(s)