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KVM: x86: SVM: Intercept #GP to support access to VMware backdoor ports
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
9ed96e87
MT		 117unsigned int min_timer_period_us = 500;
118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
141
52004014
FW		 142static bool __read_mostly vector_hashing = true;
143module_param(vector_hashing, bool, S_IRUGO);
144
c4ae60e4
LA		 145bool __read_mostly enable_vmware_backdoor = false;
146module_param(enable_vmware_backdoor, bool, S_IRUGO);
147EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
148
18863bdd
AK		 149#define KVM_NR_SHARED_MSRS 16
150
151struct kvm_shared_msrs_global {
152 int nr;
2bf78fa7 153 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 154};
155
156struct kvm_shared_msrs {
157 struct user_return_notifier urn;
158 bool registered;
2bf78fa7
SY		 159 struct kvm_shared_msr_values {
160 u64 host;
161 u64 curr;
162 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 163};
164
165static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 166static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 167
417bc304 168struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 169 { "pf_fixed", VCPU_STAT(pf_fixed) },
170 { "pf_guest", VCPU_STAT(pf_guest) },
171 { "tlb_flush", VCPU_STAT(tlb_flush) },
172 { "invlpg", VCPU_STAT(invlpg) },
173 { "exits", VCPU_STAT(exits) },
174 { "io_exits", VCPU_STAT(io_exits) },
175 { "mmio_exits", VCPU_STAT(mmio_exits) },
176 { "signal_exits", VCPU_STAT(signal_exits) },
177 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 178 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 179 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 180 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 181 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 182 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 183 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 184 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 185 { "request_irq", VCPU_STAT(request_irq_exits) },
186 { "irq_exits", VCPU_STAT(irq_exits) },
187 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 188 { "fpu_reload", VCPU_STAT(fpu_reload) },
189 { "insn_emulation", VCPU_STAT(insn_emulation) },
190 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 191 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 192 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 193 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 194 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
195 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
196 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
197 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
198 { "mmu_flooded", VM_STAT(mmu_flooded) },
199 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 200 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 201 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 202 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 203 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 204 { "max_mmu_page_hash_collisions",
205 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 206 { NULL }
207};
208
2acf923e
DC		 209u64 __read_mostly host_xcr0;
210
b6785def 211static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 212
af585b92
GN		 213static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
214{
215 int i;
216 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
217 vcpu->arch.apf.gfns[i] = ~0;
218}
219
18863bdd
AK		 220static void kvm_on_user_return(struct user_return_notifier *urn)
221{
222 unsigned slot;
18863bdd
AK		 223 struct kvm_shared_msrs *locals
224 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 225 struct kvm_shared_msr_values *values;
1650b4eb
IA		 226 unsigned long flags;
227
228 /*
229 * Disabling irqs at this point since the following code could be
230 * interrupted and executed through kvm_arch_hardware_disable()
231 */
232 local_irq_save(flags);
233 if (locals->registered) {
234 locals->registered = false;
235 user_return_notifier_unregister(urn);
236 }
237 local_irq_restore(flags);
18863bdd 238 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 239 values = &locals->values[slot];
240 if (values->host != values->curr) {
241 wrmsrl(shared_msrs_global.msrs[slot], values->host);
242 values->curr = values->host;
18863bdd
AK		 243 }
244 }
18863bdd
AK		 245}
246
2bf78fa7 247static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 248{
18863bdd 249 u64 value;
013f6a5d
MT		 250 unsigned int cpu = smp_processor_id();
251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 252
2bf78fa7
SY		 253 /* only read, and nobody should modify it at this time,
254 * so don't need lock */
255 if (slot >= shared_msrs_global.nr) {
256 printk(KERN_ERR "kvm: invalid MSR slot!");
257 return;
258 }
259 rdmsrl_safe(msr, &value);
260 smsr->values[slot].host = value;
261 smsr->values[slot].curr = value;
262}
263
264void kvm_define_shared_msr(unsigned slot, u32 msr)
265{
0123be42 266 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 267 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 268 if (slot >= shared_msrs_global.nr)
269 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 270}
271EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
272
273static void kvm_shared_msr_cpu_online(void)
274{
275 unsigned i;
18863bdd
AK		 276
277 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 278 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 279}
280
8b3c3104 281int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 282{
013f6a5d
MT		 283 unsigned int cpu = smp_processor_id();
284 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 285 int err;
18863bdd 286
2bf78fa7 287 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 288 return 0;
2bf78fa7 289 smsr->values[slot].curr = value;
8b3c3104
AH		 290 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
291 if (err)
292 return 1;
293
18863bdd
AK		 294 if (!smsr->registered) {
295 smsr->urn.on_user_return = kvm_on_user_return;
296 user_return_notifier_register(&smsr->urn);
297 smsr->registered = true;
298 }
8b3c3104 299 return 0;
18863bdd
AK		 300}
301EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
302
13a34e06 303static void drop_user_return_notifiers(void)
3548bab5 304{
013f6a5d
MT		 305 unsigned int cpu = smp_processor_id();
306 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 307
308 if (smsr->registered)
309 kvm_on_user_return(&smsr->urn);
310}
311
6866b83e
CO		 312u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
313{
8a5a87d9 314 return vcpu->arch.apic_base;
6866b83e
CO		 315}
316EXPORT_SYMBOL_GPL(kvm_get_apic_base);
317
58cb628d
JK		 318int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
319{
320 u64 old_state = vcpu->arch.apic_base &
321 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
322 u64 new_state = msr_info->data &
323 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 324 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
325 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 326
d3802286
JM		 327 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
328 return 1;
58cb628d 329 if (!msr_info->host_initiated &&
d3802286 330 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 331 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
332 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
333 old_state == 0)))
334 return 1;
335
336 kvm_lapic_set_base(vcpu, msr_info->data);
337 return 0;
6866b83e
CO		 338}
339EXPORT_SYMBOL_GPL(kvm_set_apic_base);
340
2605fc21 341asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 342{
343 /* Fault while not rebooting. We want the trace. */
344 BUG();
345}
346EXPORT_SYMBOL_GPL(kvm_spurious_fault);
347
3fd28fce
ED		 348#define EXCPT_BENIGN 0
349#define EXCPT_CONTRIBUTORY 1
350#define EXCPT_PF 2
351
352static int exception_class(int vector)
353{
354 switch (vector) {
355 case PF_VECTOR:
356 return EXCPT_PF;
357 case DE_VECTOR:
358 case TS_VECTOR:
359 case NP_VECTOR:
360 case SS_VECTOR:
361 case GP_VECTOR:
362 return EXCPT_CONTRIBUTORY;
363 default:
364 break;
365 }
366 return EXCPT_BENIGN;
367}
368
d6e8c854
NA		 369#define EXCPT_FAULT 0
370#define EXCPT_TRAP 1
371#define EXCPT_ABORT 2
372#define EXCPT_INTERRUPT 3
373
374static int exception_type(int vector)
375{
376 unsigned int mask;
377
378 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
379 return EXCPT_INTERRUPT;
380
381 mask = 1 << vector;
382
383 /* #DB is trap, as instruction watchpoints are handled elsewhere */
384 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
385 return EXCPT_TRAP;
386
387 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
388 return EXCPT_ABORT;
389
390 /* Reserved exceptions will result in fault */
391 return EXCPT_FAULT;
392}
393
3fd28fce 394static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 395 unsigned nr, bool has_error, u32 error_code,
396 bool reinject)
3fd28fce
ED		 397{
398 u32 prev_nr;
399 int class1, class2;
400
3842d135
AK		 401 kvm_make_request(KVM_REQ_EVENT, vcpu);
402
664f8e26 403 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 404 queue:
3ffb2468
NA		 405 if (has_error && !is_protmode(vcpu))
406 has_error = false;
664f8e26
WL		 407 if (reinject) {
408 /*
409 * On vmentry, vcpu->arch.exception.pending is only
410 * true if an event injection was blocked by
411 * nested_run_pending. In that case, however,
412 * vcpu_enter_guest requests an immediate exit,
413 * and the guest shouldn't proceed far enough to
414 * need reinjection.
415 */
416 WARN_ON_ONCE(vcpu->arch.exception.pending);
417 vcpu->arch.exception.injected = true;
418 } else {
419 vcpu->arch.exception.pending = true;
420 vcpu->arch.exception.injected = false;
421 }
3fd28fce
ED		 422 vcpu->arch.exception.has_error_code = has_error;
423 vcpu->arch.exception.nr = nr;
424 vcpu->arch.exception.error_code = error_code;
425 return;
426 }
427
428 /* to check exception */
429 prev_nr = vcpu->arch.exception.nr;
430 if (prev_nr == DF_VECTOR) {
431 /* triple fault -> shutdown */
a8eeb04a 432 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 433 return;
434 }
435 class1 = exception_class(prev_nr);
436 class2 = exception_class(nr);
437 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
438 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 439 /*
440 * Generate double fault per SDM Table 5-5. Set
441 * exception.pending = true so that the double fault
442 * can trigger a nested vmexit.
443 */
3fd28fce 444 vcpu->arch.exception.pending = true;
664f8e26 445 vcpu->arch.exception.injected = false;
3fd28fce
ED		 446 vcpu->arch.exception.has_error_code = true;
447 vcpu->arch.exception.nr = DF_VECTOR;
448 vcpu->arch.exception.error_code = 0;
449 } else
450 /* replace previous exception with a new one in a hope
451 that instruction re-execution will regenerate lost
452 exception */
453 goto queue;
454}
455
298101da
AK		 456void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
457{
ce7ddec4 458 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 459}
460EXPORT_SYMBOL_GPL(kvm_queue_exception);
461
ce7ddec4
JR		 462void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
463{
464 kvm_multiple_exception(vcpu, nr, false, 0, true);
465}
466EXPORT_SYMBOL_GPL(kvm_requeue_exception);
467
6affcbed 468int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 469{
db8fcefa
AP		 470 if (err)
471 kvm_inject_gp(vcpu, 0);
472 else
6affcbed
KH		 473 return kvm_skip_emulated_instruction(vcpu);
474
475 return 1;
db8fcefa
AP		 476}
477EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 478
6389ee94 479void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 480{
481 ++vcpu->stat.pf_guest;
adfe20fb
WL		 482 vcpu->arch.exception.nested_apf =
483 is_guest_mode(vcpu) && fault->async_page_fault;
484 if (vcpu->arch.exception.nested_apf)
485 vcpu->arch.apf.nested_apf_token = fault->address;
486 else
487 vcpu->arch.cr2 = fault->address;
6389ee94 488 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 489}
27d6c865 490EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 491
ef54bcfe 492static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 493{
6389ee94
AK		 494 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
495 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 496 else
6389ee94 497 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 498
499 return fault->nested_page_fault;
d4f8cf66
JR		 500}
501
3419ffc8
SY		 502void kvm_inject_nmi(struct kvm_vcpu *vcpu)
503{
7460fb4a
AK		 504 atomic_inc(&vcpu->arch.nmi_queued);
505 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 506}
507EXPORT_SYMBOL_GPL(kvm_inject_nmi);
508
298101da
AK		 509void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
510{
ce7ddec4 511 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 512}
513EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
514
ce7ddec4
JR		 515void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
516{
517 kvm_multiple_exception(vcpu, nr, true, error_code, true);
518}
519EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
520
0a79b009
AK		 521/*
522 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
523 * a #GP and return false.
524 */
525bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 526{
0a79b009
AK		 527 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
528 return true;
529 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
530 return false;
298101da 531}
0a79b009 532EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 533
16f8a6f9
NA		 534bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
535{
536 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
537 return true;
538
539 kvm_queue_exception(vcpu, UD_VECTOR);
540 return false;
541}
542EXPORT_SYMBOL_GPL(kvm_require_dr);
543
ec92fe44
JR		 544/*
545 * This function will be used to read from the physical memory of the currently
54bf36aa 546 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 547 * can read from guest physical or from the guest's guest physical memory.
548 */
549int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
550 gfn_t ngfn, void *data, int offset, int len,
551 u32 access)
552{
54987b7a 553 struct x86_exception exception;
ec92fe44
JR		 554 gfn_t real_gfn;
555 gpa_t ngpa;
556
557 ngpa = gfn_to_gpa(ngfn);
54987b7a 558 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 559 if (real_gfn == UNMAPPED_GVA)
560 return -EFAULT;
561
562 real_gfn = gpa_to_gfn(real_gfn);
563
54bf36aa 564 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 565}
566EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
567
69b0049a 568static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 569 void *data, int offset, int len, u32 access)
570{
571 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
572 data, offset, len, access);
573}
574
a03490ed
CO		 575/*
576 * Load the pae pdptrs. Return true is they are all valid.
577 */
ff03a073 578int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 579{
580 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
581 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
582 int i;
583 int ret;
ff03a073 584 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 585
ff03a073
JR		 586 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
587 offset * sizeof(u64), sizeof(pdpte),
588 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 589 if (ret < 0) {
590 ret = 0;
591 goto out;
592 }
593 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 594 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 595 (pdpte[i] &
596 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 597 ret = 0;
598 goto out;
599 }
600 }
601 ret = 1;
602
ff03a073 603 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 604 __set_bit(VCPU_EXREG_PDPTR,
605 (unsigned long *)&vcpu->arch.regs_avail);
606 __set_bit(VCPU_EXREG_PDPTR,
607 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 608out:
a03490ed
CO		 609
610 return ret;
611}
cc4b6871 612EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 613
9ed38ffa 614bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 615{
ff03a073 616 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 617 bool changed = true;
3d06b8bf
JR		 618 int offset;
619 gfn_t gfn;
d835dfec
AK		 620 int r;
621
622 if (is_long_mode(vcpu) || !is_pae(vcpu))
623 return false;
624
6de4f3ad
AK		 625 if (!test_bit(VCPU_EXREG_PDPTR,
626 (unsigned long *)&vcpu->arch.regs_avail))
627 return true;
628
a512177e
PB		 629 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
630 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 631 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
632 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 633 if (r < 0)
634 goto out;
ff03a073 635 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 636out:
d835dfec
AK		 637
638 return changed;
639}
9ed38ffa 640EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 641
49a9b07e 642int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 643{
aad82703 644 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 645 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 646
f9a48e6a
AK		 647 cr0 |= X86_CR0_ET;
648
ab344828 649#ifdef CONFIG_X86_64
0f12244f
GN		 650 if (cr0 & 0xffffffff00000000UL)
651 return 1;
ab344828
GN		 652#endif
653
654 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 655
0f12244f
GN		 656 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
657 return 1;
a03490ed 658
0f12244f
GN		 659 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
660 return 1;
a03490ed
CO		 661
662 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
663#ifdef CONFIG_X86_64
f6801dff 664 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 665 int cs_db, cs_l;
666
0f12244f
GN		 667 if (!is_pae(vcpu))
668 return 1;
a03490ed 669 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 670 if (cs_l)
671 return 1;
a03490ed
CO		 672 } else
673#endif
ff03a073 674 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 675 kvm_read_cr3(vcpu)))
0f12244f 676 return 1;
a03490ed
CO		 677 }
678
ad756a16
MJ		 679 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
680 return 1;
681
a03490ed 682 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 683
d170c419 684 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 685 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 686 kvm_async_pf_hash_reset(vcpu);
687 }
e5f3f027 688
aad82703
SY		 689 if ((cr0 ^ old_cr0) & update_bits)
690 kvm_mmu_reset_context(vcpu);
b18d5431 691
879ae188
LE		 692 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
693 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
694 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 695 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
696
0f12244f
GN		 697 return 0;
698}
2d3ad1f4 699EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 700
2d3ad1f4 701void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 702{
49a9b07e 703 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 704}
2d3ad1f4 705EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 706
42bdf991
MT		 707static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
708{
709 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
710 !vcpu->guest_xcr0_loaded) {
711 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 712 if (vcpu->arch.xcr0 != host_xcr0)
713 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 714 vcpu->guest_xcr0_loaded = 1;
715 }
716}
717
718static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
719{
720 if (vcpu->guest_xcr0_loaded) {
721 if (vcpu->arch.xcr0 != host_xcr0)
722 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
723 vcpu->guest_xcr0_loaded = 0;
724 }
725}
726
69b0049a 727static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 728{
56c103ec
LJ		 729 u64 xcr0 = xcr;
730 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 731 u64 valid_bits;
2acf923e
DC		 732
733 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
734 if (index != XCR_XFEATURE_ENABLED_MASK)
735 return 1;
d91cab78 736 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 737 return 1;
d91cab78 738 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 739 return 1;
46c34cb0
PB		 740
741 /*
742 * Do not allow the guest to set bits that we do not support
743 * saving. However, xcr0 bit 0 is always set, even if the
744 * emulated CPU does not support XSAVE (see fx_init).
745 */
d91cab78 746 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 747 if (xcr0 & ~valid_bits)
2acf923e 748 return 1;
46c34cb0 749
d91cab78
DH		 750 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
751 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 752 return 1;
753
d91cab78
DH		 754 if (xcr0 & XFEATURE_MASK_AVX512) {
755 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 756 return 1;
d91cab78 757 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 758 return 1;
759 }
2acf923e 760 vcpu->arch.xcr0 = xcr0;
56c103ec 761
d91cab78 762 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 763 kvm_update_cpuid(vcpu);
2acf923e
DC		 764 return 0;
765}
766
767int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
768{
764bcbc5
Z		 769 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
770 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 771 kvm_inject_gp(vcpu, 0);
772 return 1;
773 }
774 return 0;
775}
776EXPORT_SYMBOL_GPL(kvm_set_xcr);
777
a83b29c6 778int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 779{
fc78f519 780 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 781 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 782 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 783
0f12244f
GN		 784 if (cr4 & CR4_RESERVED_BITS)
785 return 1;
a03490ed 786
d6321d49 787 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 788 return 1;
789
d6321d49 790 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 791 return 1;
792
d6321d49 793 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 794 return 1;
795
d6321d49 796 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 797 return 1;
798
d6321d49 799 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 800 return 1;
801
fd8cb433 802 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 803 return 1;
804
ae3e61e1
PB		 805 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
806 return 1;
807
a03490ed 808 if (is_long_mode(vcpu)) {
0f12244f
GN		 809 if (!(cr4 & X86_CR4_PAE))
810 return 1;
a2edf57f
AK		 811 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
812 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 813 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
814 kvm_read_cr3(vcpu)))
0f12244f
GN		 815 return 1;
816
ad756a16 817 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 818 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 819 return 1;
820
821 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
822 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
823 return 1;
824 }
825
5e1746d6 826 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 827 return 1;
a03490ed 828
ad756a16
MJ		 829 if (((cr4 ^ old_cr4) & pdptr_bits) ||
830 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 831 kvm_mmu_reset_context(vcpu);
0f12244f 832
b9baba86 833 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 834 kvm_update_cpuid(vcpu);
2acf923e 835
0f12244f
GN		 836 return 0;
837}
2d3ad1f4 838EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 839
2390218b 840int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 841{
ac146235 842#ifdef CONFIG_X86_64
9d88fca7 843 cr3 &= ~CR3_PCID_INVD;
ac146235 844#endif
9d88fca7 845
9f8fe504 846 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 847 kvm_mmu_sync_roots(vcpu);
77c3913b 848 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 849 return 0;
d835dfec
AK		 850 }
851
d1cd3ce9
YZ		 852 if (is_long_mode(vcpu) &&
853 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
854 return 1;
855 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 856 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 857 return 1;
a03490ed 858
0f12244f 859 vcpu->arch.cr3 = cr3;
aff48baa 860 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 861 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 862 return 0;
863}
2d3ad1f4 864EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 865
eea1cff9 866int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 867{
0f12244f
GN		 868 if (cr8 & CR8_RESERVED_BITS)
869 return 1;
35754c98 870 if (lapic_in_kernel(vcpu))
a03490ed
CO		 871 kvm_lapic_set_tpr(vcpu, cr8);
872 else
ad312c7c 873 vcpu->arch.cr8 = cr8;
0f12244f
GN		 874 return 0;
875}
2d3ad1f4 876EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 877
2d3ad1f4 878unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 879{
35754c98 880 if (lapic_in_kernel(vcpu))
a03490ed
CO		 881 return kvm_lapic_get_cr8(vcpu);
882 else
ad312c7c 883 return vcpu->arch.cr8;
a03490ed 884}
2d3ad1f4 885EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 886
ae561ede
NA		 887static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
888{
889 int i;
890
891 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
892 for (i = 0; i < KVM_NR_DB_REGS; i++)
893 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
894 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
895 }
896}
897
73aaf249
JK		 898static void kvm_update_dr6(struct kvm_vcpu *vcpu)
899{
900 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
901 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
902}
903
c8639010
JK		 904static void kvm_update_dr7(struct kvm_vcpu *vcpu)
905{
906 unsigned long dr7;
907
908 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
909 dr7 = vcpu->arch.guest_debug_dr7;
910 else
911 dr7 = vcpu->arch.dr7;
912 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 913 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
914 if (dr7 & DR7_BP_EN_MASK)
915 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 916}
917
6f43ed01
NA		 918static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
919{
920 u64 fixed = DR6_FIXED_1;
921
d6321d49 922 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 923 fixed |= DR6_RTM;
924 return fixed;
925}
926
338dbc97 927static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 928{
929 switch (dr) {
930 case 0 ... 3:
931 vcpu->arch.db[dr] = val;
932 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
933 vcpu->arch.eff_db[dr] = val;
934 break;
935 case 4:
020df079
GN		 936 /* fall through */
937 case 6:
338dbc97
GN		 938 if (val & 0xffffffff00000000ULL)
939 return -1; /* #GP */
6f43ed01 940 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 941 kvm_update_dr6(vcpu);
020df079
GN		 942 break;
943 case 5:
020df079
GN		 944 /* fall through */
945 default: /* 7 */
338dbc97
GN		 946 if (val & 0xffffffff00000000ULL)
947 return -1; /* #GP */
020df079 948 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 949 kvm_update_dr7(vcpu);
020df079
GN		 950 break;
951 }
952
953 return 0;
954}
338dbc97
GN		 955
956int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
957{
16f8a6f9 958 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 959 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 960 return 1;
961 }
962 return 0;
338dbc97 963}
020df079
GN		 964EXPORT_SYMBOL_GPL(kvm_set_dr);
965
16f8a6f9 966int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 967{
968 switch (dr) {
969 case 0 ... 3:
970 *val = vcpu->arch.db[dr];
971 break;
972 case 4:
020df079
GN		 973 /* fall through */
974 case 6:
73aaf249
JK		 975 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
976 *val = vcpu->arch.dr6;
977 else
978 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 979 break;
980 case 5:
020df079
GN		 981 /* fall through */
982 default: /* 7 */
983 *val = vcpu->arch.dr7;
984 break;
985 }
338dbc97
GN		 986 return 0;
987}
020df079
GN		 988EXPORT_SYMBOL_GPL(kvm_get_dr);
989
022cd0e8
AK		 990bool kvm_rdpmc(struct kvm_vcpu *vcpu)
991{
992 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
993 u64 data;
994 int err;
995
c6702c9d 996 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 997 if (err)
998 return err;
999 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1000 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1001 return err;
1002}
1003EXPORT_SYMBOL_GPL(kvm_rdpmc);
1004
043405e1
CO		 1005/*
1006 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1007 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1008 *
1009 * This list is modified at module load time to reflect the
e3267cbb 1010 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1011 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1012 * may depend on host virtualization features rather than host cpu features.
043405e1 1013 */
e3267cbb 1014
043405e1
CO		 1015static u32 msrs_to_save[] = {
1016 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1017 MSR_STAR,
043405e1
CO		 1018#ifdef CONFIG_X86_64
1019 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1020#endif
b3897a49 1021 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1022 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1023 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1024};
1025
1026static unsigned num_msrs_to_save;
1027
62ef68bb
PB		 1028static u32 emulated_msrs[] = {
1029 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1030 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1031 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1032 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1033 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1034 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1035 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1036 HV_X64_MSR_RESET,
11c4b1ca 1037 HV_X64_MSR_VP_INDEX,
9eec50b8 1038 HV_X64_MSR_VP_RUNTIME,
5c919412 1039 HV_X64_MSR_SCONTROL,
1f4b34f8 1040 HV_X64_MSR_STIMER0_CONFIG,
a2e164e7
VK		 1041 HV_X64_MSR_APIC_ASSIST_PAGE,
1042 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1043 HV_X64_MSR_TSC_EMULATION_STATUS,
1044
1045 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1046 MSR_KVM_PV_EOI_EN,
1047
ba904635 1048 MSR_IA32_TSC_ADJUST,
a3e06bbe 1049 MSR_IA32_TSCDEADLINE,
043405e1 1050 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1051 MSR_IA32_MCG_STATUS,
1052 MSR_IA32_MCG_CTL,
c45dcc71 1053 MSR_IA32_MCG_EXT_CTL,
64d60670 1054 MSR_IA32_SMBASE,
52797bf9 1055 MSR_SMI_COUNT,
db2336a8
KH		 1056 MSR_PLATFORM_INFO,
1057 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1058};
1059
62ef68bb
PB		 1060static unsigned num_emulated_msrs;
1061
801e459a
TL		 1062/*
1063 * List of msr numbers which are used to expose MSR-based features that
1064 * can be used by a hypervisor to validate requested CPU features.
1065 */
1066static u32 msr_based_features[] = {
1389309c
PB		 1067 MSR_IA32_VMX_BASIC,
1068 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1069 MSR_IA32_VMX_PINBASED_CTLS,
1070 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1071 MSR_IA32_VMX_PROCBASED_CTLS,
1072 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1073 MSR_IA32_VMX_EXIT_CTLS,
1074 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1075 MSR_IA32_VMX_ENTRY_CTLS,
1076 MSR_IA32_VMX_MISC,
1077 MSR_IA32_VMX_CR0_FIXED0,
1078 MSR_IA32_VMX_CR0_FIXED1,
1079 MSR_IA32_VMX_CR4_FIXED0,
1080 MSR_IA32_VMX_CR4_FIXED1,
1081 MSR_IA32_VMX_VMCS_ENUM,
1082 MSR_IA32_VMX_PROCBASED_CTLS2,
1083 MSR_IA32_VMX_EPT_VPID_CAP,
1084 MSR_IA32_VMX_VMFUNC,
1085
d1d93fa9 1086 MSR_F10H_DECFG,
518e7b94 1087 MSR_IA32_UCODE_REV,
801e459a
TL		 1088};
1089
1090static unsigned int num_msr_based_features;
1091
66421c1e
WL		 1092static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1093{
1094 switch (msr->index) {
518e7b94
WL		 1095 case MSR_IA32_UCODE_REV:
1096 rdmsrl(msr->index, msr->data);
1097 break;
66421c1e
WL		 1098 default:
1099 if (kvm_x86_ops->get_msr_feature(msr))
1100 return 1;
1101 }
1102 return 0;
1103}
1104
801e459a
TL		 1105static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1106{
1107 struct kvm_msr_entry msr;
66421c1e 1108 int r;
801e459a
TL		 1109
1110 msr.index = index;
66421c1e
WL		 1111 r = kvm_get_msr_feature(&msr);
1112 if (r)
1113 return r;
801e459a
TL		 1114
1115 *data = msr.data;
1116
1117 return 0;
1118}
1119
384bb783 1120bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1121{
b69e8cae 1122 if (efer & efer_reserved_bits)
384bb783 1123 return false;
15c4a640 1124
1b4d56b8 1125 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1126 return false;
1b2fd70c 1127
1b4d56b8 1128 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1129 return false;
d8017474 1130
384bb783
JK		 1131 return true;
1132}
1133EXPORT_SYMBOL_GPL(kvm_valid_efer);
1134
1135static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1136{
1137 u64 old_efer = vcpu->arch.efer;
1138
1139 if (!kvm_valid_efer(vcpu, efer))
1140 return 1;
1141
1142 if (is_paging(vcpu)
1143 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1144 return 1;
1145
15c4a640 1146 efer &= ~EFER_LMA;
f6801dff 1147 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1148
a3d204e2
SY		 1149 kvm_x86_ops->set_efer(vcpu, efer);
1150
aad82703
SY		 1151 /* Update reserved bits */
1152 if ((efer ^ old_efer) & EFER_NX)
1153 kvm_mmu_reset_context(vcpu);
1154
b69e8cae 1155 return 0;
15c4a640
CO		 1156}
1157
f2b4b7dd
JR		 1158void kvm_enable_efer_bits(u64 mask)
1159{
1160 efer_reserved_bits &= ~mask;
1161}
1162EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1163
15c4a640
CO		 1164/*
1165 * Writes msr value into into the appropriate "register".
1166 * Returns 0 on success, non-0 otherwise.
1167 * Assumes vcpu_load() was already called.
1168 */
8fe8ab46 1169int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1170{
854e8bb1
NA		 1171 switch (msr->index) {
1172 case MSR_FS_BASE:
1173 case MSR_GS_BASE:
1174 case MSR_KERNEL_GS_BASE:
1175 case MSR_CSTAR:
1176 case MSR_LSTAR:
fd8cb433 1177 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1178 return 1;
1179 break;
1180 case MSR_IA32_SYSENTER_EIP:
1181 case MSR_IA32_SYSENTER_ESP:
1182 /*
1183 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1184 * non-canonical address is written on Intel but not on
1185 * AMD (which ignores the top 32-bits, because it does
1186 * not implement 64-bit SYSENTER).
1187 *
1188 * 64-bit code should hence be able to write a non-canonical
1189 * value on AMD. Making the address canonical ensures that
1190 * vmentry does not fail on Intel after writing a non-canonical
1191 * value, and that something deterministic happens if the guest
1192 * invokes 64-bit SYSENTER.
1193 */
fd8cb433 1194 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1195 }
8fe8ab46 1196 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1197}
854e8bb1 1198EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1199
313a3dc7
CO		 1200/*
1201 * Adapt set_msr() to msr_io()'s calling convention
1202 */
609e36d3
PB		 1203static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1204{
1205 struct msr_data msr;
1206 int r;
1207
1208 msr.index = index;
1209 msr.host_initiated = true;
1210 r = kvm_get_msr(vcpu, &msr);
1211 if (r)
1212 return r;
1213
1214 *data = msr.data;
1215 return 0;
1216}
1217
313a3dc7
CO		 1218static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1219{
8fe8ab46
WA		 1220 struct msr_data msr;
1221
1222 msr.data = *data;
1223 msr.index = index;
1224 msr.host_initiated = true;
1225 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1226}
1227
16e8d74d
MT		 1228#ifdef CONFIG_X86_64
1229struct pvclock_gtod_data {
1230 seqcount_t seq;
1231
1232 struct { /* extract of a clocksource struct */
1233 int vclock_mode;
a5a1d1c2
TG		 1234 u64 cycle_last;
1235 u64 mask;
16e8d74d
MT		 1236 u32 mult;
1237 u32 shift;
1238 } clock;
1239
cbcf2dd3
TG		 1240 u64 boot_ns;
1241 u64 nsec_base;
55dd00a7 1242 u64 wall_time_sec;
16e8d74d
MT		 1243};
1244
1245static struct pvclock_gtod_data pvclock_gtod_data;
1246
1247static void update_pvclock_gtod(struct timekeeper *tk)
1248{
1249 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1250 u64 boot_ns;
1251
876e7881 1252 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1253
1254 write_seqcount_begin(&vdata->seq);
1255
1256 /* copy pvclock gtod data */
876e7881
PZ		 1257 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1258 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1259 vdata->clock.mask = tk->tkr_mono.mask;
1260 vdata->clock.mult = tk->tkr_mono.mult;
1261 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1262
cbcf2dd3 1263 vdata->boot_ns = boot_ns;
876e7881 1264 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1265
55dd00a7
MT		 1266 vdata->wall_time_sec = tk->xtime_sec;
1267
16e8d74d
MT		 1268 write_seqcount_end(&vdata->seq);
1269}
1270#endif
1271
bab5bb39
NK		 1272void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1273{
1274 /*
1275 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1276 * vcpu_enter_guest. This function is only called from
1277 * the physical CPU that is running vcpu.
1278 */
1279 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1280}
16e8d74d 1281
18068523
GOC		 1282static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1283{
9ed3c444
AK		 1284 int version;
1285 int r;
50d0a0f9 1286 struct pvclock_wall_clock wc;
87aeb54f 1287 struct timespec64 boot;
18068523
GOC		 1288
1289 if (!wall_clock)
1290 return;
1291
9ed3c444
AK		 1292 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1293 if (r)
1294 return;
1295
1296 if (version & 1)
1297 ++version; /* first time write, random junk */
1298
1299 ++version;
18068523 1300
1dab1345
NK		 1301 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1302 return;
18068523 1303
50d0a0f9
GH		 1304 /*
1305 * The guest calculates current wall clock time by adding
34c238a1 1306 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1307 * wall clock specified here. guest system time equals host
1308 * system time for us, thus we must fill in host boot time here.
1309 */
87aeb54f 1310 getboottime64(&boot);
50d0a0f9 1311
4b648665 1312 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1313 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1314 boot = timespec64_sub(boot, ts);
4b648665 1315 }
87aeb54f 1316 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1317 wc.nsec = boot.tv_nsec;
1318 wc.version = version;
18068523
GOC		 1319
1320 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1321
1322 version++;
1323 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1324}
1325
50d0a0f9
GH		 1326static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1327{
b51012de
PB		 1328 do_shl32_div32(dividend, divisor);
1329 return dividend;
50d0a0f9
GH		 1330}
1331
3ae13faa 1332static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1333 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1334{
5f4e3f88 1335 uint64_t scaled64;
50d0a0f9
GH		 1336 int32_t shift = 0;
1337 uint64_t tps64;
1338 uint32_t tps32;
1339
3ae13faa
PB		 1340 tps64 = base_hz;
1341 scaled64 = scaled_hz;
50933623 1342 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1343 tps64 >>= 1;
1344 shift--;
1345 }
1346
1347 tps32 = (uint32_t)tps64;
50933623
JK		 1348 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1349 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1350 scaled64 >>= 1;
1351 else
1352 tps32 <<= 1;
50d0a0f9
GH		 1353 shift++;
1354 }
1355
5f4e3f88
ZA		 1356 *pshift = shift;
1357 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1358
3ae13faa
PB		 1359 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1360 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1361}
1362
d828199e 1363#ifdef CONFIG_X86_64
16e8d74d 1364static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1365#endif
16e8d74d 1366
c8076604 1367static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1368static unsigned long max_tsc_khz;
c8076604 1369
cc578287 1370static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1371{
cc578287
ZA		 1372 u64 v = (u64)khz * (1000000 + ppm);
1373 do_div(v, 1000000);
1374 return v;
1e993611
JR		 1375}
1376
381d585c
HZ		 1377static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1378{
1379 u64 ratio;
1380
1381 /* Guest TSC same frequency as host TSC? */
1382 if (!scale) {
1383 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1384 return 0;
1385 }
1386
1387 /* TSC scaling supported? */
1388 if (!kvm_has_tsc_control) {
1389 if (user_tsc_khz > tsc_khz) {
1390 vcpu->arch.tsc_catchup = 1;
1391 vcpu->arch.tsc_always_catchup = 1;
1392 return 0;
1393 } else {
1394 WARN(1, "user requested TSC rate below hardware speed\n");
1395 return -1;
1396 }
1397 }
1398
1399 /* TSC scaling required - calculate ratio */
1400 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1401 user_tsc_khz, tsc_khz);
1402
1403 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1404 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1405 user_tsc_khz);
1406 return -1;
1407 }
1408
1409 vcpu->arch.tsc_scaling_ratio = ratio;
1410 return 0;
1411}
1412
4941b8cb 1413static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1414{
cc578287
ZA		 1415 u32 thresh_lo, thresh_hi;
1416 int use_scaling = 0;
217fc9cf 1417
03ba32ca 1418 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1419 if (user_tsc_khz == 0) {
ad721883
HZ		 1420 /* set tsc_scaling_ratio to a safe value */
1421 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1422 return -1;
ad721883 1423 }
03ba32ca 1424
c285545f 1425 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1426 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1427 &vcpu->arch.virtual_tsc_shift,
1428 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1429 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1430
1431 /*
1432 * Compute the variation in TSC rate which is acceptable
1433 * within the range of tolerance and decide if the
1434 * rate being applied is within that bounds of the hardware
1435 * rate. If so, no scaling or compensation need be done.
1436 */
1437 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1438 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1439 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1440 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1441 use_scaling = 1;
1442 }
4941b8cb 1443 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1444}
1445
1446static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1447{
e26101b1 1448 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1449 vcpu->arch.virtual_tsc_mult,
1450 vcpu->arch.virtual_tsc_shift);
e26101b1 1451 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1452 return tsc;
1453}
1454
b0c39dc6
VK		 1455static inline int gtod_is_based_on_tsc(int mode)
1456{
1457 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1458}
1459
69b0049a 1460static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1461{
1462#ifdef CONFIG_X86_64
1463 bool vcpus_matched;
b48aa97e
MT		 1464 struct kvm_arch *ka = &vcpu->kvm->arch;
1465 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1466
1467 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1468 atomic_read(&vcpu->kvm->online_vcpus));
1469
7f187922
MT		 1470 /*
1471 * Once the masterclock is enabled, always perform request in
1472 * order to update it.
1473 *
1474 * In order to enable masterclock, the host clocksource must be TSC
1475 * and the vcpus need to have matched TSCs. When that happens,
1476 * perform request to enable masterclock.
1477 */
1478 if (ka->use_master_clock ||
b0c39dc6 1479 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1480 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1481
1482 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1483 atomic_read(&vcpu->kvm->online_vcpus),
1484 ka->use_master_clock, gtod->clock.vclock_mode);
1485#endif
1486}
1487
ba904635
WA		 1488static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1489{
3e3f5026 1490 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1491 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1492}
1493
35181e86
HZ		 1494/*
1495 * Multiply tsc by a fixed point number represented by ratio.
1496 *
1497 * The most significant 64-N bits (mult) of ratio represent the
1498 * integral part of the fixed point number; the remaining N bits
1499 * (frac) represent the fractional part, ie. ratio represents a fixed
1500 * point number (mult + frac * 2^(-N)).
1501 *
1502 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1503 */
1504static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1505{
1506 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1507}
1508
1509u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1510{
1511 u64 _tsc = tsc;
1512 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1513
1514 if (ratio != kvm_default_tsc_scaling_ratio)
1515 _tsc = __scale_tsc(ratio, tsc);
1516
1517 return _tsc;
1518}
1519EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1520
07c1419a
HZ		 1521static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1522{
1523 u64 tsc;
1524
1525 tsc = kvm_scale_tsc(vcpu, rdtsc());
1526
1527 return target_tsc - tsc;
1528}
1529
4ba76538
HZ		 1530u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1531{
ea26e4ec 1532 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1533}
1534EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1535
a545ab6a
LC		 1536static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1537{
1538 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1539 vcpu->arch.tsc_offset = offset;
1540}
1541
b0c39dc6
VK		 1542static inline bool kvm_check_tsc_unstable(void)
1543{
1544#ifdef CONFIG_X86_64
1545 /*
1546 * TSC is marked unstable when we're running on Hyper-V,
1547 * 'TSC page' clocksource is good.
1548 */
1549 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1550 return false;
1551#endif
1552 return check_tsc_unstable();
1553}
1554
8fe8ab46 1555void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1556{
1557 struct kvm *kvm = vcpu->kvm;
f38e098f 1558 u64 offset, ns, elapsed;
99e3e30a 1559 unsigned long flags;
b48aa97e 1560 bool matched;
0d3da0d2 1561 bool already_matched;
8fe8ab46 1562 u64 data = msr->data;
c5e8ec8e 1563 bool synchronizing = false;
99e3e30a 1564
038f8c11 1565 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1566 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1567 ns = ktime_get_boot_ns();
f38e098f 1568 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1569
03ba32ca 1570 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1571 if (data == 0 && msr->host_initiated) {
1572 /*
1573 * detection of vcpu initialization -- need to sync
1574 * with other vCPUs. This particularly helps to keep
1575 * kvm_clock stable after CPU hotplug
1576 */
1577 synchronizing = true;
1578 } else {
1579 u64 tsc_exp = kvm->arch.last_tsc_write +
1580 nsec_to_cycles(vcpu, elapsed);
1581 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1582 /*
1583 * Special case: TSC write with a small delta (1 second)
1584 * of virtual cycle time against real time is
1585 * interpreted as an attempt to synchronize the CPU.
1586 */
1587 synchronizing = data < tsc_exp + tsc_hz &&
1588 data + tsc_hz > tsc_exp;
1589 }
c5e8ec8e 1590 }
f38e098f
ZA		 1591
1592 /*
5d3cb0f6
ZA		 1593 * For a reliable TSC, we can match TSC offsets, and for an unstable
1594 * TSC, we add elapsed time in this computation. We could let the
1595 * compensation code attempt to catch up if we fall behind, but
1596 * it's better to try to match offsets from the beginning.
1597 */
c5e8ec8e 1598 if (synchronizing &&
5d3cb0f6 1599 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1600 if (!kvm_check_tsc_unstable()) {
e26101b1 1601 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1602 pr_debug("kvm: matched tsc offset for %llu\n", data);
1603 } else {
857e4099 1604 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1605 data += delta;
07c1419a 1606 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1607 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1608 }
b48aa97e 1609 matched = true;
0d3da0d2 1610 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1611 } else {
1612 /*
1613 * We split periods of matched TSC writes into generations.
1614 * For each generation, we track the original measured
1615 * nanosecond time, offset, and write, so if TSCs are in
1616 * sync, we can match exact offset, and if not, we can match
4a969980 1617 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1618 *
1619 * These values are tracked in kvm->arch.cur_xxx variables.
1620 */
1621 kvm->arch.cur_tsc_generation++;
1622 kvm->arch.cur_tsc_nsec = ns;
1623 kvm->arch.cur_tsc_write = data;
1624 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1625 matched = false;
0d3da0d2 1626 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1627 kvm->arch.cur_tsc_generation, data);
f38e098f 1628 }
e26101b1
ZA		 1629
1630 /*
1631 * We also track th most recent recorded KHZ, write and time to
1632 * allow the matching interval to be extended at each write.
1633 */
f38e098f
ZA		 1634 kvm->arch.last_tsc_nsec = ns;
1635 kvm->arch.last_tsc_write = data;
5d3cb0f6 1636 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1637
b183aa58 1638 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1639
1640 /* Keep track of which generation this VCPU has synchronized to */
1641 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1642 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1643 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1644
d6321d49 1645 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1646 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1647
a545ab6a 1648 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1649 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1650
1651 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1652 if (!matched) {
b48aa97e 1653 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1654 } else if (!already_matched) {
1655 kvm->arch.nr_vcpus_matched_tsc++;
1656 }
b48aa97e
MT		 1657
1658 kvm_track_tsc_matching(vcpu);
1659 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1660}
e26101b1 1661
99e3e30a
ZA		 1662EXPORT_SYMBOL_GPL(kvm_write_tsc);
1663
58ea6767
HZ		 1664static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1665 s64 adjustment)
1666{
ea26e4ec 1667 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1668}
1669
1670static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1671{
1672 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1673 WARN_ON(adjustment < 0);
1674 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1675 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1676}
1677
d828199e
MT		 1678#ifdef CONFIG_X86_64
1679
a5a1d1c2 1680static u64 read_tsc(void)
d828199e 1681{
a5a1d1c2 1682 u64 ret = (u64)rdtsc_ordered();
03b9730b 1683 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1684
1685 if (likely(ret >= last))
1686 return ret;
1687
1688 /*
1689 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1690 * predictable (it's just a function of time and the likely is
d828199e
MT		 1691 * very likely) and there's a data dependence, so force GCC
1692 * to generate a branch instead. I don't barrier() because
1693 * we don't actually need a barrier, and if this function
1694 * ever gets inlined it will generate worse code.
1695 */
1696 asm volatile ("");
1697 return last;
1698}
1699
b0c39dc6 1700static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1701{
1702 long v;
1703 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1704 u64 tsc_pg_val;
1705
1706 switch (gtod->clock.vclock_mode) {
1707 case VCLOCK_HVCLOCK:
1708 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1709 tsc_timestamp);
1710 if (tsc_pg_val != U64_MAX) {
1711 /* TSC page valid */
1712 *mode = VCLOCK_HVCLOCK;
1713 v = (tsc_pg_val - gtod->clock.cycle_last) &
1714 gtod->clock.mask;
1715 } else {
1716 /* TSC page invalid */
1717 *mode = VCLOCK_NONE;
1718 }
1719 break;
1720 case VCLOCK_TSC:
1721 *mode = VCLOCK_TSC;
1722 *tsc_timestamp = read_tsc();
1723 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1724 gtod->clock.mask;
1725 break;
1726 default:
1727 *mode = VCLOCK_NONE;
1728 }
d828199e 1729
b0c39dc6
VK		 1730 if (*mode == VCLOCK_NONE)
1731 *tsc_timestamp = v = 0;
d828199e 1732
d828199e
MT		 1733 return v * gtod->clock.mult;
1734}
1735
b0c39dc6 1736static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1737{
cbcf2dd3 1738 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1739 unsigned long seq;
d828199e 1740 int mode;
cbcf2dd3 1741 u64 ns;
d828199e 1742
d828199e
MT		 1743 do {
1744 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1745 ns = gtod->nsec_base;
b0c39dc6 1746 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1747 ns >>= gtod->clock.shift;
cbcf2dd3 1748 ns += gtod->boot_ns;
d828199e 1749 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1750 *t = ns;
d828199e
MT		 1751
1752 return mode;
1753}
1754
b0c39dc6 1755static int do_realtime(struct timespec *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1756{
1757 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1758 unsigned long seq;
1759 int mode;
1760 u64 ns;
1761
1762 do {
1763 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1764 ts->tv_sec = gtod->wall_time_sec;
1765 ns = gtod->nsec_base;
b0c39dc6 1766 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1767 ns >>= gtod->clock.shift;
1768 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1769
1770 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1771 ts->tv_nsec = ns;
1772
1773 return mode;
1774}
1775
b0c39dc6
VK		 1776/* returns true if host is using TSC based clocksource */
1777static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1778{
d828199e 1779 /* checked again under seqlock below */
b0c39dc6 1780 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1781 return false;
1782
b0c39dc6
VK		 1783 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1784 tsc_timestamp));
d828199e 1785}
55dd00a7 1786
b0c39dc6 1787/* returns true if host is using TSC based clocksource */
55dd00a7 1788static bool kvm_get_walltime_and_clockread(struct timespec *ts,
b0c39dc6 1789 u64 *tsc_timestamp)
55dd00a7
MT		 1790{
1791 /* checked again under seqlock below */
b0c39dc6 1792 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1793 return false;
1794
b0c39dc6 1795 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1796}
d828199e
MT		 1797#endif
1798
1799/*
1800 *
b48aa97e
MT		 1801 * Assuming a stable TSC across physical CPUS, and a stable TSC
1802 * across virtual CPUs, the following condition is possible.
1803 * Each numbered line represents an event visible to both
d828199e
MT		 1804 * CPUs at the next numbered event.
1805 *
1806 * "timespecX" represents host monotonic time. "tscX" represents
1807 * RDTSC value.
1808 *
1809 * VCPU0 on CPU0 | VCPU1 on CPU1
1810 *
1811 * 1. read timespec0,tsc0
1812 * 2. | timespec1 = timespec0 + N
1813 * | tsc1 = tsc0 + M
1814 * 3. transition to guest | transition to guest
1815 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1816 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1817 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1818 *
1819 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1820 *
1821 * - ret0 < ret1
1822 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1823 * ...
1824 * - 0 < N - M => M < N
1825 *
1826 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1827 * always the case (the difference between two distinct xtime instances
1828 * might be smaller then the difference between corresponding TSC reads,
1829 * when updating guest vcpus pvclock areas).
1830 *
1831 * To avoid that problem, do not allow visibility of distinct
1832 * system_timestamp/tsc_timestamp values simultaneously: use a master
1833 * copy of host monotonic time values. Update that master copy
1834 * in lockstep.
1835 *
b48aa97e 1836 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1837 *
1838 */
1839
1840static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1841{
1842#ifdef CONFIG_X86_64
1843 struct kvm_arch *ka = &kvm->arch;
1844 int vclock_mode;
b48aa97e
MT		 1845 bool host_tsc_clocksource, vcpus_matched;
1846
1847 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1848 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1849
1850 /*
1851 * If the host uses TSC clock, then passthrough TSC as stable
1852 * to the guest.
1853 */
b48aa97e 1854 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1855 &ka->master_kernel_ns,
1856 &ka->master_cycle_now);
1857
16a96021 1858 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1859 && !ka->backwards_tsc_observed
54750f2c 1860 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1861
d828199e
MT		 1862 if (ka->use_master_clock)
1863 atomic_set(&kvm_guest_has_master_clock, 1);
1864
1865 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1866 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1867 vcpus_matched);
d828199e
MT		 1868#endif
1869}
1870
2860c4b1
PB		 1871void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1872{
1873 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1874}
1875
2e762ff7
MT		 1876static void kvm_gen_update_masterclock(struct kvm *kvm)
1877{
1878#ifdef CONFIG_X86_64
1879 int i;
1880 struct kvm_vcpu *vcpu;
1881 struct kvm_arch *ka = &kvm->arch;
1882
1883 spin_lock(&ka->pvclock_gtod_sync_lock);
1884 kvm_make_mclock_inprogress_request(kvm);
1885 /* no guest entries from this point */
1886 pvclock_update_vm_gtod_copy(kvm);
1887
1888 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1889 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1890
1891 /* guest entries allowed */
1892 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1893 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1894
1895 spin_unlock(&ka->pvclock_gtod_sync_lock);
1896#endif
1897}
1898
e891a32e 1899u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1900{
108b249c 1901 struct kvm_arch *ka = &kvm->arch;
8b953440 1902 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1903 u64 ret;
108b249c 1904
8b953440
PB		 1905 spin_lock(&ka->pvclock_gtod_sync_lock);
1906 if (!ka->use_master_clock) {
1907 spin_unlock(&ka->pvclock_gtod_sync_lock);
1908 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1909 }
1910
8b953440
PB		 1911 hv_clock.tsc_timestamp = ka->master_cycle_now;
1912 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1913 spin_unlock(&ka->pvclock_gtod_sync_lock);
1914
e2c2206a
WL		 1915 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1916 get_cpu();
1917
e70b57a6
WL		 1918 if (__this_cpu_read(cpu_tsc_khz)) {
1919 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1920 &hv_clock.tsc_shift,
1921 &hv_clock.tsc_to_system_mul);
1922 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1923 } else
1924 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1925
1926 put_cpu();
1927
1928 return ret;
108b249c
PB		 1929}
1930
0d6dd2ff
PB		 1931static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1932{
1933 struct kvm_vcpu_arch *vcpu = &v->arch;
1934 struct pvclock_vcpu_time_info guest_hv_clock;
1935
4e335d9e 1936 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1937 &guest_hv_clock, sizeof(guest_hv_clock))))
1938 return;
1939
1940 /* This VCPU is paused, but it's legal for a guest to read another
1941 * VCPU's kvmclock, so we really have to follow the specification where
1942 * it says that version is odd if data is being modified, and even after
1943 * it is consistent.
1944 *
1945 * Version field updates must be kept separate. This is because
1946 * kvm_write_guest_cached might use a "rep movs" instruction, and
1947 * writes within a string instruction are weakly ordered. So there
1948 * are three writes overall.
1949 *
1950 * As a small optimization, only write the version field in the first
1951 * and third write. The vcpu->pv_time cache is still valid, because the
1952 * version field is the first in the struct.
1953 */
1954 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1955
51c4b8bb
LA		 1956 if (guest_hv_clock.version & 1)
1957 ++guest_hv_clock.version; /* first time write, random junk */
1958
0d6dd2ff 1959 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1960 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1961 &vcpu->hv_clock,
1962 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1963
1964 smp_wmb();
1965
1966 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1967 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1968
1969 if (vcpu->pvclock_set_guest_stopped_request) {
1970 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1971 vcpu->pvclock_set_guest_stopped_request = false;
1972 }
1973
1974 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1975
4e335d9e
PB		 1976 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1977 &vcpu->hv_clock,
1978 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1979
1980 smp_wmb();
1981
1982 vcpu->hv_clock.version++;
4e335d9e
PB		 1983 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1984 &vcpu->hv_clock,
1985 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1986}
1987
34c238a1 1988static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1989{
78db6a50 1990 unsigned long flags, tgt_tsc_khz;
18068523 1991 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1992 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1993 s64 kernel_ns;
d828199e 1994 u64 tsc_timestamp, host_tsc;
51d59c6b 1995 u8 pvclock_flags;
d828199e
MT		 1996 bool use_master_clock;
1997
1998 kernel_ns = 0;
1999 host_tsc = 0;
18068523 2000
d828199e
MT		 2001 /*
2002 * If the host uses TSC clock, then passthrough TSC as stable
2003 * to the guest.
2004 */
2005 spin_lock(&ka->pvclock_gtod_sync_lock);
2006 use_master_clock = ka->use_master_clock;
2007 if (use_master_clock) {
2008 host_tsc = ka->master_cycle_now;
2009 kernel_ns = ka->master_kernel_ns;
2010 }
2011 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2012
2013 /* Keep irq disabled to prevent changes to the clock */
2014 local_irq_save(flags);
78db6a50
PB		 2015 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2016 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2017 local_irq_restore(flags);
2018 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2019 return 1;
2020 }
d828199e 2021 if (!use_master_clock) {
4ea1636b 2022 host_tsc = rdtsc();
108b249c 2023 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2024 }
2025
4ba76538 2026 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2027
c285545f
ZA		 2028 /*
2029 * We may have to catch up the TSC to match elapsed wall clock
2030 * time for two reasons, even if kvmclock is used.
2031 * 1) CPU could have been running below the maximum TSC rate
2032 * 2) Broken TSC compensation resets the base at each VCPU
2033 * entry to avoid unknown leaps of TSC even when running
2034 * again on the same CPU. This may cause apparent elapsed
2035 * time to disappear, and the guest to stand still or run
2036 * very slowly.
2037 */
2038 if (vcpu->tsc_catchup) {
2039 u64 tsc = compute_guest_tsc(v, kernel_ns);
2040 if (tsc > tsc_timestamp) {
f1e2b260 2041 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2042 tsc_timestamp = tsc;
2043 }
50d0a0f9
GH		 2044 }
2045
18068523
GOC		 2046 local_irq_restore(flags);
2047
0d6dd2ff 2048 /* With all the info we got, fill in the values */
18068523 2049
78db6a50
PB		 2050 if (kvm_has_tsc_control)
2051 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2052
2053 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2054 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2055 &vcpu->hv_clock.tsc_shift,
2056 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2057 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2058 }
2059
1d5f066e 2060 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2061 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2062 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2063
d828199e 2064 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2065 pvclock_flags = 0;
d828199e
MT		 2066 if (use_master_clock)
2067 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2068
78c0337a
MT		 2069 vcpu->hv_clock.flags = pvclock_flags;
2070
095cf55d
PB		 2071 if (vcpu->pv_time_enabled)
2072 kvm_setup_pvclock_page(v);
2073 if (v == kvm_get_vcpu(v->kvm, 0))
2074 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2075 return 0;
c8076604
GH		 2076}
2077
0061d53d
MT		 2078/*
2079 * kvmclock updates which are isolated to a given vcpu, such as
2080 * vcpu->cpu migration, should not allow system_timestamp from
2081 * the rest of the vcpus to remain static. Otherwise ntp frequency
2082 * correction applies to one vcpu's system_timestamp but not
2083 * the others.
2084 *
2085 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2086 * We need to rate-limit these requests though, as they can
2087 * considerably slow guests that have a large number of vcpus.
2088 * The time for a remote vcpu to update its kvmclock is bound
2089 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2090 */
2091
7e44e449
AJ		 2092#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2093
2094static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2095{
2096 int i;
7e44e449
AJ		 2097 struct delayed_work *dwork = to_delayed_work(work);
2098 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2099 kvmclock_update_work);
2100 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2101 struct kvm_vcpu *vcpu;
2102
2103 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2104 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2105 kvm_vcpu_kick(vcpu);
2106 }
2107}
2108
7e44e449
AJ		 2109static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2110{
2111 struct kvm *kvm = v->kvm;
2112
105b21bb 2113 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2114 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2115 KVMCLOCK_UPDATE_DELAY);
2116}
2117
332967a3
AJ		 2118#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2119
2120static void kvmclock_sync_fn(struct work_struct *work)
2121{
2122 struct delayed_work *dwork = to_delayed_work(work);
2123 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2124 kvmclock_sync_work);
2125 struct kvm *kvm = container_of(ka, struct kvm, arch);
2126
630994b3
MT		 2127 if (!kvmclock_periodic_sync)
2128 return;
2129
332967a3
AJ		 2130 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2131 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2132 KVMCLOCK_SYNC_PERIOD);
2133}
2134
9ffd986c 2135static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2136{
890ca9ae
HY		 2137 u64 mcg_cap = vcpu->arch.mcg_cap;
2138 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2139 u32 msr = msr_info->index;
2140 u64 data = msr_info->data;
890ca9ae 2141
15c4a640 2142 switch (msr) {
15c4a640 2143 case MSR_IA32_MCG_STATUS:
890ca9ae 2144 vcpu->arch.mcg_status = data;
15c4a640 2145 break;
c7ac679c 2146 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2147 if (!(mcg_cap & MCG_CTL_P))
2148 return 1;
2149 if (data != 0 && data != ~(u64)0)
2150 return -1;
2151 vcpu->arch.mcg_ctl = data;
2152 break;
2153 default:
2154 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2155 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2156 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2157 /* only 0 or all 1s can be written to IA32_MCi_CTL
2158 * some Linux kernels though clear bit 10 in bank 4 to
2159 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2160 * this to avoid an uncatched #GP in the guest
2161 */
890ca9ae 2162 if ((offset & 0x3) == 0 &&
114be429 2163 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2164 return -1;
9ffd986c
WL		 2165 if (!msr_info->host_initiated &&
2166 (offset & 0x3) == 1 && data != 0)
2167 return -1;
890ca9ae
HY		 2168 vcpu->arch.mce_banks[offset] = data;
2169 break;
2170 }
2171 return 1;
2172 }
2173 return 0;
2174}
2175
ffde22ac
ES		 2176static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2177{
2178 struct kvm *kvm = vcpu->kvm;
2179 int lm = is_long_mode(vcpu);
2180 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2181 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2182 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2183 : kvm->arch.xen_hvm_config.blob_size_32;
2184 u32 page_num = data & ~PAGE_MASK;
2185 u64 page_addr = data & PAGE_MASK;
2186 u8 *page;
2187 int r;
2188
2189 r = -E2BIG;
2190 if (page_num >= blob_size)
2191 goto out;
2192 r = -ENOMEM;
ff5c2c03
SL		 2193 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2194 if (IS_ERR(page)) {
2195 r = PTR_ERR(page);
ffde22ac 2196 goto out;
ff5c2c03 2197 }
54bf36aa 2198 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2199 goto out_free;
2200 r = 0;
2201out_free:
2202 kfree(page);
2203out:
2204 return r;
2205}
2206
344d9588
GN		 2207static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2208{
2209 gpa_t gpa = data & ~0x3f;
2210
52a5c155
WL		 2211 /* Bits 3:5 are reserved, Should be zero */
2212 if (data & 0x38)
344d9588
GN		 2213 return 1;
2214
2215 vcpu->arch.apf.msr_val = data;
2216
2217 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2218 kvm_clear_async_pf_completion_queue(vcpu);
2219 kvm_async_pf_hash_reset(vcpu);
2220 return 0;
2221 }
2222
4e335d9e 2223 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2224 sizeof(u32)))
344d9588
GN		 2225 return 1;
2226
6adba527 2227 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2228 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2229 kvm_async_pf_wakeup_all(vcpu);
2230 return 0;
2231}
2232
12f9a48f
GC		 2233static void kvmclock_reset(struct kvm_vcpu *vcpu)
2234{
0b79459b 2235 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2236}
2237
f38a7b75
WL		 2238static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2239{
2240 ++vcpu->stat.tlb_flush;
2241 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2242}
2243
c9aaa895
GC		 2244static void record_steal_time(struct kvm_vcpu *vcpu)
2245{
2246 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2247 return;
2248
4e335d9e 2249 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2250 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2251 return;
2252
f38a7b75
WL		 2253 /*
2254 * Doing a TLB flush here, on the guest's behalf, can avoid
2255 * expensive IPIs.
2256 */
2257 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2258 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2259
35f3fae1
WL		 2260 if (vcpu->arch.st.steal.version & 1)
2261 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2262
2263 vcpu->arch.st.steal.version += 1;
2264
4e335d9e 2265 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2266 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2267
2268 smp_wmb();
2269
c54cdf14
LC		 2270 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2271 vcpu->arch.st.last_steal;
2272 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2273
4e335d9e 2274 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2275 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2276
2277 smp_wmb();
2278
2279 vcpu->arch.st.steal.version += 1;
c9aaa895 2280
4e335d9e 2281 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2282 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2283}
2284
8fe8ab46 2285int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2286{
5753785f 2287 bool pr = false;
8fe8ab46
WA		 2288 u32 msr = msr_info->index;
2289 u64 data = msr_info->data;
5753785f 2290
15c4a640 2291 switch (msr) {
2e32b719 2292 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2293 case MSR_IA32_UCODE_WRITE:
2294 case MSR_VM_HSAVE_PA:
2295 case MSR_AMD64_PATCH_LOADER:
2296 case MSR_AMD64_BU_CFG2:
405a353a 2297 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2298 break;
2299
518e7b94
WL		 2300 case MSR_IA32_UCODE_REV:
2301 if (msr_info->host_initiated)
2302 vcpu->arch.microcode_version = data;
2303 break;
15c4a640 2304 case MSR_EFER:
b69e8cae 2305 return set_efer(vcpu, data);
8f1589d9
AP		 2306 case MSR_K7_HWCR:
2307 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2308 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2309 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2310 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2311 if (data != 0) {
a737f256
CD		 2312 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2313 data);
8f1589d9
AP		 2314 return 1;
2315 }
15c4a640 2316 break;
f7c6d140
AP		 2317 case MSR_FAM10H_MMIO_CONF_BASE:
2318 if (data != 0) {
a737f256
CD		 2319 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2320 "0x%llx\n", data);
f7c6d140
AP		 2321 return 1;
2322 }
15c4a640 2323 break;
b5e2fec0
AG		 2324 case MSR_IA32_DEBUGCTLMSR:
2325 if (!data) {
2326 /* We support the non-activated case already */
2327 break;
2328 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2329 /* Values other than LBR and BTF are vendor-specific,
2330 thus reserved and should throw a #GP */
2331 return 1;
2332 }
a737f256
CD		 2333 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2334 __func__, data);
b5e2fec0 2335 break;
9ba075a6 2336 case 0x200 ... 0x2ff:
ff53604b 2337 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2338 case MSR_IA32_APICBASE:
58cb628d 2339 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2340 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2341 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2342 case MSR_IA32_TSCDEADLINE:
2343 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2344 break;
ba904635 2345 case MSR_IA32_TSC_ADJUST:
d6321d49 2346 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2347 if (!msr_info->host_initiated) {
d913b904 2348 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2349 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2350 }
2351 vcpu->arch.ia32_tsc_adjust_msr = data;
2352 }
2353 break;
15c4a640 2354 case MSR_IA32_MISC_ENABLE:
ad312c7c 2355 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2356 break;
64d60670
PB		 2357 case MSR_IA32_SMBASE:
2358 if (!msr_info->host_initiated)
2359 return 1;
2360 vcpu->arch.smbase = data;
2361 break;
52797bf9
LA		 2362 case MSR_SMI_COUNT:
2363 if (!msr_info->host_initiated)
2364 return 1;
2365 vcpu->arch.smi_count = data;
2366 break;
11c6bffa 2367 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2368 case MSR_KVM_WALL_CLOCK:
2369 vcpu->kvm->arch.wall_clock = data;
2370 kvm_write_wall_clock(vcpu->kvm, data);
2371 break;
11c6bffa 2372 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2373 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2374 struct kvm_arch *ka = &vcpu->kvm->arch;
2375
12f9a48f 2376 kvmclock_reset(vcpu);
18068523 2377
54750f2c
MT		 2378 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2379 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2380
2381 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2382 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2383
2384 ka->boot_vcpu_runs_old_kvmclock = tmp;
2385 }
2386
18068523 2387 vcpu->arch.time = data;
0061d53d 2388 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2389
2390 /* we verify if the enable bit is set... */
2391 if (!(data & 1))
2392 break;
2393
4e335d9e 2394 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2395 &vcpu->arch.pv_time, data & ~1ULL,
2396 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2397 vcpu->arch.pv_time_enabled = false;
2398 else
2399 vcpu->arch.pv_time_enabled = true;
32cad84f 2400
18068523
GOC		 2401 break;
2402 }
344d9588
GN		 2403 case MSR_KVM_ASYNC_PF_EN:
2404 if (kvm_pv_enable_async_pf(vcpu, data))
2405 return 1;
2406 break;
c9aaa895
GC		 2407 case MSR_KVM_STEAL_TIME:
2408
2409 if (unlikely(!sched_info_on()))
2410 return 1;
2411
2412 if (data & KVM_STEAL_RESERVED_MASK)
2413 return 1;
2414
4e335d9e 2415 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2416 data & KVM_STEAL_VALID_BITS,
2417 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2418 return 1;
2419
2420 vcpu->arch.st.msr_val = data;
2421
2422 if (!(data & KVM_MSR_ENABLED))
2423 break;
2424
c9aaa895
GC		 2425 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2426
2427 break;
ae7a2a3f
MT		 2428 case MSR_KVM_PV_EOI_EN:
2429 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2430 return 1;
2431 break;
c9aaa895 2432
890ca9ae
HY		 2433 case MSR_IA32_MCG_CTL:
2434 case MSR_IA32_MCG_STATUS:
81760dcc 2435 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2436 return set_msr_mce(vcpu, msr_info);
71db6023 2437
6912ac32
WH		 2438 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2439 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2440 pr = true; /* fall through */
2441 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2442 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2443 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2444 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2445
2446 if (pr || data != 0)
a737f256
CD		 2447 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2448 "0x%x data 0x%llx\n", msr, data);
5753785f 2449 break;
84e0cefa
JS		 2450 case MSR_K7_CLK_CTL:
2451 /*
2452 * Ignore all writes to this no longer documented MSR.
2453 * Writes are only relevant for old K7 processors,
2454 * all pre-dating SVM, but a recommended workaround from
4a969980 2455 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2456 * affected processor models on the command line, hence
2457 * the need to ignore the workaround.
2458 */
2459 break;
55cd8e5a 2460 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2461 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2462 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2463 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2464 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2465 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2466 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2467 return kvm_hv_set_msr_common(vcpu, msr, data,
2468 msr_info->host_initiated);
91c9c3ed 2469 case MSR_IA32_BBL_CR_CTL3:
2470 /* Drop writes to this legacy MSR -- see rdmsr
2471 * counterpart for further detail.
2472 */
fab0aa3b
EM		 2473 if (report_ignored_msrs)
2474 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2475 msr, data);
91c9c3ed 2476 break;
2b036c6b 2477 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2478 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2479 return 1;
2480 vcpu->arch.osvw.length = data;
2481 break;
2482 case MSR_AMD64_OSVW_STATUS:
d6321d49 2483 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2484 return 1;
2485 vcpu->arch.osvw.status = data;
2486 break;
db2336a8
KH		 2487 case MSR_PLATFORM_INFO:
2488 if (!msr_info->host_initiated ||
2489 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2490 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2491 cpuid_fault_enabled(vcpu)))
2492 return 1;
2493 vcpu->arch.msr_platform_info = data;
2494 break;
2495 case MSR_MISC_FEATURES_ENABLES:
2496 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2497 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2498 !supports_cpuid_fault(vcpu)))
2499 return 1;
2500 vcpu->arch.msr_misc_features_enables = data;
2501 break;
15c4a640 2502 default:
ffde22ac
ES		 2503 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2504 return xen_hvm_config(vcpu, data);
c6702c9d 2505 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2506 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2507 if (!ignore_msrs) {
ae0f5499 2508 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2509 msr, data);
ed85c068
AP		 2510 return 1;
2511 } else {
fab0aa3b
EM		 2512 if (report_ignored_msrs)
2513 vcpu_unimpl(vcpu,
2514 "ignored wrmsr: 0x%x data 0x%llx\n",
2515 msr, data);
ed85c068
AP		 2516 break;
2517 }
15c4a640
CO		 2518 }
2519 return 0;
2520}
2521EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2522
2523
2524/*
2525 * Reads an msr value (of 'msr_index') into 'pdata'.
2526 * Returns 0 on success, non-0 otherwise.
2527 * Assumes vcpu_load() was already called.
2528 */
609e36d3 2529int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2530{
609e36d3 2531 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2532}
ff651cb6 2533EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2534
890ca9ae 2535static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2536{
2537 u64 data;
890ca9ae
HY		 2538 u64 mcg_cap = vcpu->arch.mcg_cap;
2539 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2540
2541 switch (msr) {
15c4a640
CO		 2542 case MSR_IA32_P5_MC_ADDR:
2543 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2544 data = 0;
2545 break;
15c4a640 2546 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2547 data = vcpu->arch.mcg_cap;
2548 break;
c7ac679c 2549 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2550 if (!(mcg_cap & MCG_CTL_P))
2551 return 1;
2552 data = vcpu->arch.mcg_ctl;
2553 break;
2554 case MSR_IA32_MCG_STATUS:
2555 data = vcpu->arch.mcg_status;
2556 break;
2557 default:
2558 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2559 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2560 u32 offset = msr - MSR_IA32_MC0_CTL;
2561 data = vcpu->arch.mce_banks[offset];
2562 break;
2563 }
2564 return 1;
2565 }
2566 *pdata = data;
2567 return 0;
2568}
2569
609e36d3 2570int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2571{
609e36d3 2572 switch (msr_info->index) {
890ca9ae 2573 case MSR_IA32_PLATFORM_ID:
15c4a640 2574 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2575 case MSR_IA32_DEBUGCTLMSR:
2576 case MSR_IA32_LASTBRANCHFROMIP:
2577 case MSR_IA32_LASTBRANCHTOIP:
2578 case MSR_IA32_LASTINTFROMIP:
2579 case MSR_IA32_LASTINTTOIP:
60af2ecd 2580 case MSR_K8_SYSCFG:
3afb1121
PB		 2581 case MSR_K8_TSEG_ADDR:
2582 case MSR_K8_TSEG_MASK:
60af2ecd 2583 case MSR_K7_HWCR:
61a6bd67 2584 case MSR_VM_HSAVE_PA:
1fdbd48c 2585 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2586 case MSR_AMD64_NB_CFG:
f7c6d140 2587 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2588 case MSR_AMD64_BU_CFG2:
0c2df2a1 2589 case MSR_IA32_PERF_CTL:
405a353a 2590 case MSR_AMD64_DC_CFG:
609e36d3 2591 msr_info->data = 0;
15c4a640 2592 break;
c51eb52b 2593 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2594 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2595 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2596 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2597 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2598 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2599 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2600 msr_info->data = 0;
5753785f 2601 break;
742bc670 2602 case MSR_IA32_UCODE_REV:
518e7b94 2603 msr_info->data = vcpu->arch.microcode_version;
742bc670 2604 break;
9ba075a6 2605 case MSR_MTRRcap:
9ba075a6 2606 case 0x200 ... 0x2ff:
ff53604b 2607 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2608 case 0xcd: /* fsb frequency */
609e36d3 2609 msr_info->data = 3;
15c4a640 2610 break;
7b914098
JS		 2611 /*
2612 * MSR_EBC_FREQUENCY_ID
2613 * Conservative value valid for even the basic CPU models.
2614 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2615 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2616 * and 266MHz for model 3, or 4. Set Core Clock
2617 * Frequency to System Bus Frequency Ratio to 1 (bits
2618 * 31:24) even though these are only valid for CPU
2619 * models > 2, however guests may end up dividing or
2620 * multiplying by zero otherwise.
2621 */
2622 case MSR_EBC_FREQUENCY_ID:
609e36d3 2623 msr_info->data = 1 << 24;
7b914098 2624 break;
15c4a640 2625 case MSR_IA32_APICBASE:
609e36d3 2626 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2627 break;
0105d1a5 2628 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2629 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2630 break;
a3e06bbe 2631 case MSR_IA32_TSCDEADLINE:
609e36d3 2632 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2633 break;
ba904635 2634 case MSR_IA32_TSC_ADJUST:
609e36d3 2635 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2636 break;
15c4a640 2637 case MSR_IA32_MISC_ENABLE:
609e36d3 2638 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2639 break;
64d60670
PB		 2640 case MSR_IA32_SMBASE:
2641 if (!msr_info->host_initiated)
2642 return 1;
2643 msr_info->data = vcpu->arch.smbase;
15c4a640 2644 break;
52797bf9
LA		 2645 case MSR_SMI_COUNT:
2646 msr_info->data = vcpu->arch.smi_count;
2647 break;
847f0ad8
AG		 2648 case MSR_IA32_PERF_STATUS:
2649 /* TSC increment by tick */
609e36d3 2650 msr_info->data = 1000ULL;
847f0ad8 2651 /* CPU multiplier */
b0996ae4 2652 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2653 break;
15c4a640 2654 case MSR_EFER:
609e36d3 2655 msr_info->data = vcpu->arch.efer;
15c4a640 2656 break;
18068523 2657 case MSR_KVM_WALL_CLOCK:
11c6bffa 2658 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2659 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2660 break;
2661 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2662 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2663 msr_info->data = vcpu->arch.time;
18068523 2664 break;
344d9588 2665 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2666 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2667 break;
c9aaa895 2668 case MSR_KVM_STEAL_TIME:
609e36d3 2669 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2670 break;
1d92128f 2671 case MSR_KVM_PV_EOI_EN:
609e36d3 2672 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2673 break;
890ca9ae
HY		 2674 case MSR_IA32_P5_MC_ADDR:
2675 case MSR_IA32_P5_MC_TYPE:
2676 case MSR_IA32_MCG_CAP:
2677 case MSR_IA32_MCG_CTL:
2678 case MSR_IA32_MCG_STATUS:
81760dcc 2679 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2680 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2681 case MSR_K7_CLK_CTL:
2682 /*
2683 * Provide expected ramp-up count for K7. All other
2684 * are set to zero, indicating minimum divisors for
2685 * every field.
2686 *
2687 * This prevents guest kernels on AMD host with CPU
2688 * type 6, model 8 and higher from exploding due to
2689 * the rdmsr failing.
2690 */
609e36d3 2691 msr_info->data = 0x20000000;
84e0cefa 2692 break;
55cd8e5a 2693 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2694 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2695 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2696 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2697 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2698 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2699 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887
AS		 2700 return kvm_hv_get_msr_common(vcpu,
2701 msr_info->index, &msr_info->data);
55cd8e5a 2702 break;
91c9c3ed 2703 case MSR_IA32_BBL_CR_CTL3:
2704 /* This legacy MSR exists but isn't fully documented in current
2705 * silicon. It is however accessed by winxp in very narrow
2706 * scenarios where it sets bit #19, itself documented as
2707 * a "reserved" bit. Best effort attempt to source coherent
2708 * read data here should the balance of the register be
2709 * interpreted by the guest:
2710 *
2711 * L2 cache control register 3: 64GB range, 256KB size,
2712 * enabled, latency 0x1, configured
2713 */
609e36d3 2714 msr_info->data = 0xbe702111;
91c9c3ed 2715 break;
2b036c6b 2716 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2717 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2718 return 1;
609e36d3 2719 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2720 break;
2721 case MSR_AMD64_OSVW_STATUS:
d6321d49 2722 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2723 return 1;
609e36d3 2724 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2725 break;
db2336a8
KH		 2726 case MSR_PLATFORM_INFO:
2727 msr_info->data = vcpu->arch.msr_platform_info;
2728 break;
2729 case MSR_MISC_FEATURES_ENABLES:
2730 msr_info->data = vcpu->arch.msr_misc_features_enables;
2731 break;
15c4a640 2732 default:
c6702c9d 2733 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2734 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2735 if (!ignore_msrs) {
ae0f5499
BD		 2736 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2737 msr_info->index);
ed85c068
AP		 2738 return 1;
2739 } else {
fab0aa3b
EM		 2740 if (report_ignored_msrs)
2741 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2742 msr_info->index);
609e36d3 2743 msr_info->data = 0;
ed85c068
AP		 2744 }
2745 break;
15c4a640 2746 }
15c4a640
CO		 2747 return 0;
2748}
2749EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2750
313a3dc7
CO		 2751/*
2752 * Read or write a bunch of msrs. All parameters are kernel addresses.
2753 *
2754 * @return number of msrs set successfully.
2755 */
2756static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2757 struct kvm_msr_entry *entries,
2758 int (*do_msr)(struct kvm_vcpu *vcpu,
2759 unsigned index, u64 *data))
2760{
801e459a 2761 int i;
313a3dc7 2762
313a3dc7
CO		 2763 for (i = 0; i < msrs->nmsrs; ++i)
2764 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2765 break;
2766
313a3dc7
CO		 2767 return i;
2768}
2769
2770/*
2771 * Read or write a bunch of msrs. Parameters are user addresses.
2772 *
2773 * @return number of msrs set successfully.
2774 */
2775static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2776 int (*do_msr)(struct kvm_vcpu *vcpu,
2777 unsigned index, u64 *data),
2778 int writeback)
2779{
2780 struct kvm_msrs msrs;
2781 struct kvm_msr_entry *entries;
2782 int r, n;
2783 unsigned size;
2784
2785 r = -EFAULT;
2786 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2787 goto out;
2788
2789 r = -E2BIG;
2790 if (msrs.nmsrs >= MAX_IO_MSRS)
2791 goto out;
2792
313a3dc7 2793 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2794 entries = memdup_user(user_msrs->entries, size);
2795 if (IS_ERR(entries)) {
2796 r = PTR_ERR(entries);
313a3dc7 2797 goto out;
ff5c2c03 2798 }
313a3dc7
CO		 2799
2800 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2801 if (r < 0)
2802 goto out_free;
2803
2804 r = -EFAULT;
2805 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2806 goto out_free;
2807
2808 r = n;
2809
2810out_free:
7a73c028 2811 kfree(entries);
313a3dc7
CO		 2812out:
2813 return r;
2814}
2815
784aa3d7 2816int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2817{
2818 int r;
2819
2820 switch (ext) {
2821 case KVM_CAP_IRQCHIP:
2822 case KVM_CAP_HLT:
2823 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2824 case KVM_CAP_SET_TSS_ADDR:
07716717 2825 case KVM_CAP_EXT_CPUID:
9c15bb1d 2826 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2827 case KVM_CAP_CLOCKSOURCE:
7837699f 2828 case KVM_CAP_PIT:
a28e4f5a 2829 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2830 case KVM_CAP_MP_STATE:
ed848624 2831 case KVM_CAP_SYNC_MMU:
a355c85c 2832 case KVM_CAP_USER_NMI:
52d939a0 2833 case KVM_CAP_REINJECT_CONTROL:
4925663a 2834 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2835 case KVM_CAP_IOEVENTFD:
f848a5a8 2836 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2837 case KVM_CAP_PIT2:
e9f42757 2838 case KVM_CAP_PIT_STATE2:
b927a3ce 2839 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2840 case KVM_CAP_XEN_HVM:
3cfc3092 2841 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2842 case KVM_CAP_HYPERV:
10388a07 2843 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2844 case KVM_CAP_HYPERV_SPIN:
5c919412 2845 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2846 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2847 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2848 case KVM_CAP_HYPERV_EVENTFD:
ab9f4ecb 2849 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2850 case KVM_CAP_DEBUGREGS:
d2be1651 2851 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2852 case KVM_CAP_XSAVE:
344d9588 2853 case KVM_CAP_ASYNC_PF:
92a1f12d 2854 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2855 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2856 case KVM_CAP_READONLY_MEM:
5f66b620 2857 case KVM_CAP_HYPERV_TIME:
100943c5 2858 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2859 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2860 case KVM_CAP_ENABLE_CAP_VM:
2861 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2862 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2863 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2864 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2865 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2866 r = 1;
2867 break;
01643c51
KH		 2868 case KVM_CAP_SYNC_REGS:
2869 r = KVM_SYNC_X86_VALID_FIELDS;
2870 break;
e3fd9a93
PB		 2871 case KVM_CAP_ADJUST_CLOCK:
2872 r = KVM_CLOCK_TSC_STABLE;
2873 break;
668fffa3
MT		 2874 case KVM_CAP_X86_GUEST_MWAIT:
2875 r = kvm_mwait_in_guest();
2876 break;
6d396b55
PB		 2877 case KVM_CAP_X86_SMM:
2878 /* SMBASE is usually relocated above 1M on modern chipsets,
2879 * and SMM handlers might indeed rely on 4G segment limits,
2880 * so do not report SMM to be available if real mode is
2881 * emulated via vm86 mode. Still, do not go to great lengths
2882 * to avoid userspace's usage of the feature, because it is a
2883 * fringe case that is not enabled except via specific settings
2884 * of the module parameters.
2885 */
2886 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2887 break;
774ead3a
AK		 2888 case KVM_CAP_VAPIC:
2889 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2890 break;
f725230a 2891 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2892 r = KVM_SOFT_MAX_VCPUS;
2893 break;
2894 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2895 r = KVM_MAX_VCPUS;
2896 break;
a988b910 2897 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2898 r = KVM_USER_MEM_SLOTS;
a988b910 2899 break;
a68a6a72
MT		 2900 case KVM_CAP_PV_MMU: /* obsolete */
2901 r = 0;
2f333bcb 2902 break;
890ca9ae
HY		 2903 case KVM_CAP_MCE:
2904 r = KVM_MAX_MCE_BANKS;
2905 break;
2d5b5a66 2906 case KVM_CAP_XCRS:
d366bf7e 2907 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2908 break;
92a1f12d
JR		 2909 case KVM_CAP_TSC_CONTROL:
2910 r = kvm_has_tsc_control;
2911 break;
37131313
RK		 2912 case KVM_CAP_X2APIC_API:
2913 r = KVM_X2APIC_API_VALID_FLAGS;
2914 break;
018d00d2
ZX		 2915 default:
2916 r = 0;
2917 break;
2918 }
2919 return r;
2920
2921}
2922
043405e1
CO		 2923long kvm_arch_dev_ioctl(struct file *filp,
2924 unsigned int ioctl, unsigned long arg)
2925{
2926 void __user *argp = (void __user *)arg;
2927 long r;
2928
2929 switch (ioctl) {
2930 case KVM_GET_MSR_INDEX_LIST: {
2931 struct kvm_msr_list __user *user_msr_list = argp;
2932 struct kvm_msr_list msr_list;
2933 unsigned n;
2934
2935 r = -EFAULT;
2936 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2937 goto out;
2938 n = msr_list.nmsrs;
62ef68bb 2939 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2940 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2941 goto out;
2942 r = -E2BIG;
e125e7b6 2943 if (n < msr_list.nmsrs)
043405e1
CO		 2944 goto out;
2945 r = -EFAULT;
2946 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2947 num_msrs_to_save * sizeof(u32)))
2948 goto out;
e125e7b6 2949 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2950 &emulated_msrs,
62ef68bb 2951 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2952 goto out;
2953 r = 0;
2954 break;
2955 }
9c15bb1d
BP		 2956 case KVM_GET_SUPPORTED_CPUID:
2957 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2958 struct kvm_cpuid2 __user *cpuid_arg = argp;
2959 struct kvm_cpuid2 cpuid;
2960
2961 r = -EFAULT;
2962 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2963 goto out;
9c15bb1d
BP		 2964
2965 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2966 ioctl);
674eea0f
AK		 2967 if (r)
2968 goto out;
2969
2970 r = -EFAULT;
2971 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2972 goto out;
2973 r = 0;
2974 break;
2975 }
890ca9ae 2976 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2977 r = -EFAULT;
c45dcc71
AR		 2978 if (copy_to_user(argp, &kvm_mce_cap_supported,
2979 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2980 goto out;
2981 r = 0;
2982 break;
801e459a
TL		 2983 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
2984 struct kvm_msr_list __user *user_msr_list = argp;
2985 struct kvm_msr_list msr_list;
2986 unsigned int n;
2987
2988 r = -EFAULT;
2989 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
2990 goto out;
2991 n = msr_list.nmsrs;
2992 msr_list.nmsrs = num_msr_based_features;
2993 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
2994 goto out;
2995 r = -E2BIG;
2996 if (n < msr_list.nmsrs)
2997 goto out;
2998 r = -EFAULT;
2999 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3000 num_msr_based_features * sizeof(u32)))
3001 goto out;
3002 r = 0;
3003 break;
3004 }
3005 case KVM_GET_MSRS:
3006 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3007 break;
890ca9ae 3008 }
043405e1
CO		 3009 default:
3010 r = -EINVAL;
3011 }
3012out:
3013 return r;
3014}
3015
f5f48ee1
SY		 3016static void wbinvd_ipi(void *garbage)
3017{
3018 wbinvd();
3019}
3020
3021static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3022{
e0f0bbc5 3023 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3024}
3025
313a3dc7
CO		 3026void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3027{
f5f48ee1
SY		 3028 /* Address WBINVD may be executed by guest */
3029 if (need_emulate_wbinvd(vcpu)) {
3030 if (kvm_x86_ops->has_wbinvd_exit())
3031 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3032 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3033 smp_call_function_single(vcpu->cpu,
3034 wbinvd_ipi, NULL, 1);
3035 }
3036
313a3dc7 3037 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3038
0dd6a6ed
ZA		 3039 /* Apply any externally detected TSC adjustments (due to suspend) */
3040 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3041 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3042 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3043 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3044 }
8f6055cb 3045
b0c39dc6 3046 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3047 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3048 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3049 if (tsc_delta < 0)
3050 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3051
b0c39dc6 3052 if (kvm_check_tsc_unstable()) {
07c1419a 3053 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3054 vcpu->arch.last_guest_tsc);
a545ab6a 3055 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3056 vcpu->arch.tsc_catchup = 1;
c285545f 3057 }
a749e247
PB		 3058
3059 if (kvm_lapic_hv_timer_in_use(vcpu))
3060 kvm_lapic_restart_hv_timer(vcpu);
3061
d98d07ca
MT		 3062 /*
3063 * On a host with synchronized TSC, there is no need to update
3064 * kvmclock on vcpu->cpu migration
3065 */
3066 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3067 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3068 if (vcpu->cpu != cpu)
1bd2009e 3069 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3070 vcpu->cpu = cpu;
6b7d7e76 3071 }
c9aaa895 3072
c9aaa895 3073 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3074}
3075
0b9f6c46
PX		 3076static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3077{
3078 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3079 return;
3080
fa55eedd 3081 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3082
4e335d9e 3083 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3084 &vcpu->arch.st.steal.preempted,
3085 offsetof(struct kvm_steal_time, preempted),
3086 sizeof(vcpu->arch.st.steal.preempted));
3087}
3088
313a3dc7
CO		 3089void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3090{
cc0d907c 3091 int idx;
de63ad4c
LM		 3092
3093 if (vcpu->preempted)
3094 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3095
931f261b
AA		 3096 /*
3097 * Disable page faults because we're in atomic context here.
3098 * kvm_write_guest_offset_cached() would call might_fault()
3099 * that relies on pagefault_disable() to tell if there's a
3100 * bug. NOTE: the write to guest memory may not go through if
3101 * during postcopy live migration or if there's heavy guest
3102 * paging.
3103 */
3104 pagefault_disable();
cc0d907c
AA		 3105 /*
3106 * kvm_memslots() will be called by
3107 * kvm_write_guest_offset_cached() so take the srcu lock.
3108 */
3109 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3110 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3111 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3112 pagefault_enable();
02daab21 3113 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3114 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3115 /*
3116 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3117 * on every vmexit, but if not, we might have a stale dr6 from the
3118 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3119 */
3120 set_debugreg(0, 6);
313a3dc7
CO		 3121}
3122
313a3dc7
CO		 3123static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3124 struct kvm_lapic_state *s)
3125{
fa59cc00 3126 if (vcpu->arch.apicv_active)
d62caabb
AS		 3127 kvm_x86_ops->sync_pir_to_irr(vcpu);
3128
a92e2543 3129 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3130}
3131
3132static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3133 struct kvm_lapic_state *s)
3134{
a92e2543
RK		 3135 int r;
3136
3137 r = kvm_apic_set_state(vcpu, s);
3138 if (r)
3139 return r;
cb142eb7 3140 update_cr8_intercept(vcpu);
313a3dc7
CO		 3141
3142 return 0;
3143}
3144
127a457a
MG		 3145static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3146{
3147 return (!lapic_in_kernel(vcpu) ||
3148 kvm_apic_accept_pic_intr(vcpu));
3149}
3150
782d422b
MG		 3151/*
3152 * if userspace requested an interrupt window, check that the
3153 * interrupt window is open.
3154 *
3155 * No need to exit to userspace if we already have an interrupt queued.
3156 */
3157static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3158{
3159 return kvm_arch_interrupt_allowed(vcpu) &&
3160 !kvm_cpu_has_interrupt(vcpu) &&
3161 !kvm_event_needs_reinjection(vcpu) &&
3162 kvm_cpu_accept_dm_intr(vcpu);
3163}
3164
f77bc6a4
ZX		 3165static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3166 struct kvm_interrupt *irq)
3167{
02cdb50f 3168 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3169 return -EINVAL;
1c1a9ce9
SR		 3170
3171 if (!irqchip_in_kernel(vcpu->kvm)) {
3172 kvm_queue_interrupt(vcpu, irq->irq, false);
3173 kvm_make_request(KVM_REQ_EVENT, vcpu);
3174 return 0;
3175 }
3176
3177 /*
3178 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3179 * fail for in-kernel 8259.
3180 */
3181 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3182 return -ENXIO;
f77bc6a4 3183
1c1a9ce9
SR		 3184 if (vcpu->arch.pending_external_vector != -1)
3185 return -EEXIST;
f77bc6a4 3186
1c1a9ce9 3187 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3188 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3189 return 0;
3190}
3191
c4abb7c9
JK		 3192static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3193{
c4abb7c9 3194 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3195
3196 return 0;
3197}
3198
f077825a
PB		 3199static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3200{
64d60670
PB		 3201 kvm_make_request(KVM_REQ_SMI, vcpu);
3202
f077825a
PB		 3203 return 0;
3204}
3205
b209749f
AK		 3206static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3207 struct kvm_tpr_access_ctl *tac)
3208{
3209 if (tac->flags)
3210 return -EINVAL;
3211 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3212 return 0;
3213}
3214
890ca9ae
HY		 3215static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3216 u64 mcg_cap)
3217{
3218 int r;
3219 unsigned bank_num = mcg_cap & 0xff, bank;
3220
3221 r = -EINVAL;
a9e38c3e 3222 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3223 goto out;
c45dcc71 3224 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3225 goto out;
3226 r = 0;
3227 vcpu->arch.mcg_cap = mcg_cap;
3228 /* Init IA32_MCG_CTL to all 1s */
3229 if (mcg_cap & MCG_CTL_P)
3230 vcpu->arch.mcg_ctl = ~(u64)0;
3231 /* Init IA32_MCi_CTL to all 1s */
3232 for (bank = 0; bank < bank_num; bank++)
3233 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3234
3235 if (kvm_x86_ops->setup_mce)
3236 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3237out:
3238 return r;
3239}
3240
3241static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3242 struct kvm_x86_mce *mce)
3243{
3244 u64 mcg_cap = vcpu->arch.mcg_cap;
3245 unsigned bank_num = mcg_cap & 0xff;
3246 u64 *banks = vcpu->arch.mce_banks;
3247
3248 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3249 return -EINVAL;
3250 /*
3251 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3252 * reporting is disabled
3253 */
3254 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3255 vcpu->arch.mcg_ctl != ~(u64)0)
3256 return 0;
3257 banks += 4 * mce->bank;
3258 /*
3259 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3260 * reporting is disabled for the bank
3261 */
3262 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3263 return 0;
3264 if (mce->status & MCI_STATUS_UC) {
3265 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3266 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3267 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3268 return 0;
3269 }
3270 if (banks[1] & MCI_STATUS_VAL)
3271 mce->status |= MCI_STATUS_OVER;
3272 banks[2] = mce->addr;
3273 banks[3] = mce->misc;
3274 vcpu->arch.mcg_status = mce->mcg_status;
3275 banks[1] = mce->status;
3276 kvm_queue_exception(vcpu, MC_VECTOR);
3277 } else if (!(banks[1] & MCI_STATUS_VAL)
3278 || !(banks[1] & MCI_STATUS_UC)) {
3279 if (banks[1] & MCI_STATUS_VAL)
3280 mce->status |= MCI_STATUS_OVER;
3281 banks[2] = mce->addr;
3282 banks[3] = mce->misc;
3283 banks[1] = mce->status;
3284 } else
3285 banks[1] |= MCI_STATUS_OVER;
3286 return 0;
3287}
3288
3cfc3092
JK		 3289static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3290 struct kvm_vcpu_events *events)
3291{
7460fb4a 3292 process_nmi(vcpu);
664f8e26
WL		 3293 /*
3294 * FIXME: pass injected and pending separately. This is only
3295 * needed for nested virtualization, whose state cannot be
3296 * migrated yet. For now we can combine them.
3297 */
03b82a30 3298 events->exception.injected =
664f8e26
WL		 3299 (vcpu->arch.exception.pending ||
3300 vcpu->arch.exception.injected) &&
03b82a30 3301 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3302 events->exception.nr = vcpu->arch.exception.nr;
3303 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3304 events->exception.pad = 0;
3cfc3092
JK		 3305 events->exception.error_code = vcpu->arch.exception.error_code;
3306
03b82a30
JK		 3307 events->interrupt.injected =
3308 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3309 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3310 events->interrupt.soft = 0;
37ccdcbe 3311 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3312
3313 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3314 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3315 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3316 events->nmi.pad = 0;
3cfc3092 3317
66450a21 3318 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3319
f077825a
PB		 3320 events->smi.smm = is_smm(vcpu);
3321 events->smi.pending = vcpu->arch.smi_pending;
3322 events->smi.smm_inside_nmi =
3323 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3324 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3325
dab4b911 3326 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3327 | KVM_VCPUEVENT_VALID_SHADOW
3328 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3329 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3330}
3331
6ef4e07e
XG		 3332static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3333
3cfc3092
JK		 3334static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3335 struct kvm_vcpu_events *events)
3336{
dab4b911 3337 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3338 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3339 | KVM_VCPUEVENT_VALID_SHADOW
3340 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3341 return -EINVAL;
3342
78e546c8 3343 if (events->exception.injected &&
28d06353
JM		 3344 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3345 is_guest_mode(vcpu)))
78e546c8
PB		 3346 return -EINVAL;
3347
28bf2888
DH		 3348 /* INITs are latched while in SMM */
3349 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3350 (events->smi.smm || events->smi.pending) &&
3351 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3352 return -EINVAL;
3353
7460fb4a 3354 process_nmi(vcpu);
664f8e26 3355 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3356 vcpu->arch.exception.pending = events->exception.injected;
3357 vcpu->arch.exception.nr = events->exception.nr;
3358 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3359 vcpu->arch.exception.error_code = events->exception.error_code;
3360
3361 vcpu->arch.interrupt.pending = events->interrupt.injected;
3362 vcpu->arch.interrupt.nr = events->interrupt.nr;
3363 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3364 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3365 kvm_x86_ops->set_interrupt_shadow(vcpu,
3366 events->interrupt.shadow);
3cfc3092
JK		 3367
3368 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3369 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3370 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3371 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3372
66450a21 3373 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3374 lapic_in_kernel(vcpu))
66450a21 3375 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3376
f077825a 3377 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3378 u32 hflags = vcpu->arch.hflags;
f077825a 3379 if (events->smi.smm)
6ef4e07e 3380 hflags |= HF_SMM_MASK;
f077825a 3381 else
6ef4e07e
XG		 3382 hflags &= ~HF_SMM_MASK;
3383 kvm_set_hflags(vcpu, hflags);
3384
f077825a 3385 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3386
3387 if (events->smi.smm) {
3388 if (events->smi.smm_inside_nmi)
3389 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3390 else
f4ef1910
WL		 3391 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3392 if (lapic_in_kernel(vcpu)) {
3393 if (events->smi.latched_init)
3394 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3395 else
3396 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3397 }
f077825a
PB		 3398 }
3399 }
3400
3842d135
AK		 3401 kvm_make_request(KVM_REQ_EVENT, vcpu);
3402
3cfc3092
JK		 3403 return 0;
3404}
3405
a1efbe77
JK		 3406static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3407 struct kvm_debugregs *dbgregs)
3408{
73aaf249
JK		 3409 unsigned long val;
3410
a1efbe77 3411 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3412 kvm_get_dr(vcpu, 6, &val);
73aaf249 3413 dbgregs->dr6 = val;
a1efbe77
JK		 3414 dbgregs->dr7 = vcpu->arch.dr7;
3415 dbgregs->flags = 0;
97e69aa6 3416 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3417}
3418
3419static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3420 struct kvm_debugregs *dbgregs)
3421{
3422 if (dbgregs->flags)
3423 return -EINVAL;
3424
d14bdb55
PB		 3425 if (dbgregs->dr6 & ~0xffffffffull)
3426 return -EINVAL;
3427 if (dbgregs->dr7 & ~0xffffffffull)
3428 return -EINVAL;
3429
a1efbe77 3430 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3431 kvm_update_dr0123(vcpu);
a1efbe77 3432 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3433 kvm_update_dr6(vcpu);
a1efbe77 3434 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3435 kvm_update_dr7(vcpu);
a1efbe77 3436
a1efbe77
JK		 3437 return 0;
3438}
3439
df1daba7
PB		 3440#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3441
3442static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3443{
c47ada30 3444 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3445 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3446 u64 valid;
3447
3448 /*
3449 * Copy legacy XSAVE area, to avoid complications with CPUID
3450 * leaves 0 and 1 in the loop below.
3451 */
3452 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3453
3454 /* Set XSTATE_BV */
00c87e9a 3455 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3456 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3457
3458 /*
3459 * Copy each region from the possibly compacted offset to the
3460 * non-compacted offset.
3461 */
d91cab78 3462 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3463 while (valid) {
3464 u64 feature = valid & -valid;
3465 int index = fls64(feature) - 1;
3466 void *src = get_xsave_addr(xsave, feature);
3467
3468 if (src) {
3469 u32 size, offset, ecx, edx;
3470 cpuid_count(XSTATE_CPUID, index,
3471 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3472 if (feature == XFEATURE_MASK_PKRU)
3473 memcpy(dest + offset, &vcpu->arch.pkru,
3474 sizeof(vcpu->arch.pkru));
3475 else
3476 memcpy(dest + offset, src, size);
3477
df1daba7
PB		 3478 }
3479
3480 valid -= feature;
3481 }
3482}
3483
3484static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3485{
c47ada30 3486 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3487 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3488 u64 valid;
3489
3490 /*
3491 * Copy legacy XSAVE area, to avoid complications with CPUID
3492 * leaves 0 and 1 in the loop below.
3493 */
3494 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3495
3496 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3497 xsave->header.xfeatures = xstate_bv;
782511b0 3498 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3499 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3500
3501 /*
3502 * Copy each region from the non-compacted offset to the
3503 * possibly compacted offset.
3504 */
d91cab78 3505 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3506 while (valid) {
3507 u64 feature = valid & -valid;
3508 int index = fls64(feature) - 1;
3509 void *dest = get_xsave_addr(xsave, feature);
3510
3511 if (dest) {
3512 u32 size, offset, ecx, edx;
3513 cpuid_count(XSTATE_CPUID, index,
3514 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3515 if (feature == XFEATURE_MASK_PKRU)
3516 memcpy(&vcpu->arch.pkru, src + offset,
3517 sizeof(vcpu->arch.pkru));
3518 else
3519 memcpy(dest, src + offset, size);
ee4100da 3520 }
df1daba7
PB		 3521
3522 valid -= feature;
3523 }
3524}
3525
2d5b5a66
SY		 3526static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3527 struct kvm_xsave *guest_xsave)
3528{
d366bf7e 3529 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3530 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3531 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3532 } else {
2d5b5a66 3533 memcpy(guest_xsave->region,
7366ed77 3534 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3535 sizeof(struct fxregs_state));
2d5b5a66 3536 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3537 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3538 }
3539}
3540
a575813b
WL		 3541#define XSAVE_MXCSR_OFFSET 24
3542
2d5b5a66
SY		 3543static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3544 struct kvm_xsave *guest_xsave)
3545{
3546 u64 xstate_bv =
3547 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3548 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3549
d366bf7e 3550 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3551 /*
3552 * Here we allow setting states that are not present in
3553 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3554 * with old userspace.
3555 */
a575813b
WL		 3556 if (xstate_bv & ~kvm_supported_xcr0() ||
3557 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3558 return -EINVAL;
df1daba7 3559 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3560 } else {
a575813b
WL		 3561 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3562 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3563 return -EINVAL;
7366ed77 3564 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3565 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3566 }
3567 return 0;
3568}
3569
3570static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3571 struct kvm_xcrs *guest_xcrs)
3572{
d366bf7e 3573 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3574 guest_xcrs->nr_xcrs = 0;
3575 return;
3576 }
3577
3578 guest_xcrs->nr_xcrs = 1;
3579 guest_xcrs->flags = 0;
3580 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3581 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3582}
3583
3584static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3585 struct kvm_xcrs *guest_xcrs)
3586{
3587 int i, r = 0;
3588
d366bf7e 3589 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3590 return -EINVAL;
3591
3592 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3593 return -EINVAL;
3594
3595 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3596 /* Only support XCR0 currently */
c67a04cb 3597 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3598 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3599 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3600 break;
3601 }
3602 if (r)
3603 r = -EINVAL;
3604 return r;
3605}
3606
1c0b28c2
EM		 3607/*
3608 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3609 * stopped by the hypervisor. This function will be called from the host only.
3610 * EINVAL is returned when the host attempts to set the flag for a guest that
3611 * does not support pv clocks.
3612 */
3613static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3614{
0b79459b 3615 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3616 return -EINVAL;
51d59c6b 3617 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3618 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3619 return 0;
3620}
3621
5c919412
AS		 3622static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3623 struct kvm_enable_cap *cap)
3624{
3625 if (cap->flags)
3626 return -EINVAL;
3627
3628 switch (cap->cap) {
efc479e6
RK		 3629 case KVM_CAP_HYPERV_SYNIC2:
3630 if (cap->args[0])
3631 return -EINVAL;
5c919412 3632 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3633 if (!irqchip_in_kernel(vcpu->kvm))
3634 return -EINVAL;
efc479e6
RK		 3635 return kvm_hv_activate_synic(vcpu, cap->cap ==
3636 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3637 default:
3638 return -EINVAL;
3639 }
3640}
3641
313a3dc7
CO		 3642long kvm_arch_vcpu_ioctl(struct file *filp,
3643 unsigned int ioctl, unsigned long arg)
3644{
3645 struct kvm_vcpu *vcpu = filp->private_data;
3646 void __user *argp = (void __user *)arg;
3647 int r;
d1ac91d8
AK		 3648 union {
3649 struct kvm_lapic_state *lapic;
3650 struct kvm_xsave *xsave;
3651 struct kvm_xcrs *xcrs;
3652 void *buffer;
3653 } u;
3654
9b062471
CD		 3655 vcpu_load(vcpu);
3656
d1ac91d8 3657 u.buffer = NULL;
313a3dc7
CO		 3658 switch (ioctl) {
3659 case KVM_GET_LAPIC: {
2204ae3c 3660 r = -EINVAL;
bce87cce 3661 if (!lapic_in_kernel(vcpu))
2204ae3c 3662 goto out;
d1ac91d8 3663 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3664
b772ff36 3665 r = -ENOMEM;
d1ac91d8 3666 if (!u.lapic)
b772ff36 3667 goto out;
d1ac91d8 3668 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3669 if (r)
3670 goto out;
3671 r = -EFAULT;
d1ac91d8 3672 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3673 goto out;
3674 r = 0;
3675 break;
3676 }
3677 case KVM_SET_LAPIC: {
2204ae3c 3678 r = -EINVAL;
bce87cce 3679 if (!lapic_in_kernel(vcpu))
2204ae3c 3680 goto out;
ff5c2c03 3681 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3682 if (IS_ERR(u.lapic)) {
3683 r = PTR_ERR(u.lapic);
3684 goto out_nofree;
3685 }
ff5c2c03 3686
d1ac91d8 3687 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3688 break;
3689 }
f77bc6a4
ZX		 3690 case KVM_INTERRUPT: {
3691 struct kvm_interrupt irq;
3692
3693 r = -EFAULT;
3694 if (copy_from_user(&irq, argp, sizeof irq))
3695 goto out;
3696 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3697 break;
3698 }
c4abb7c9
JK		 3699 case KVM_NMI: {
3700 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3701 break;
3702 }
f077825a
PB		 3703 case KVM_SMI: {
3704 r = kvm_vcpu_ioctl_smi(vcpu);
3705 break;
3706 }
313a3dc7
CO		 3707 case KVM_SET_CPUID: {
3708 struct kvm_cpuid __user *cpuid_arg = argp;
3709 struct kvm_cpuid cpuid;
3710
3711 r = -EFAULT;
3712 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3713 goto out;
3714 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3715 break;
3716 }
07716717
DK		 3717 case KVM_SET_CPUID2: {
3718 struct kvm_cpuid2 __user *cpuid_arg = argp;
3719 struct kvm_cpuid2 cpuid;
3720
3721 r = -EFAULT;
3722 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3723 goto out;
3724 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3725 cpuid_arg->entries);
07716717
DK		 3726 break;
3727 }
3728 case KVM_GET_CPUID2: {
3729 struct kvm_cpuid2 __user *cpuid_arg = argp;
3730 struct kvm_cpuid2 cpuid;
3731
3732 r = -EFAULT;
3733 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3734 goto out;
3735 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3736 cpuid_arg->entries);
07716717
DK		 3737 if (r)
3738 goto out;
3739 r = -EFAULT;
3740 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3741 goto out;
3742 r = 0;
3743 break;
3744 }
801e459a
TL		 3745 case KVM_GET_MSRS: {
3746 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3747 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3748 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3749 break;
801e459a
TL		 3750 }
3751 case KVM_SET_MSRS: {
3752 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3753 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3754 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3755 break;
801e459a 3756 }
b209749f
AK		 3757 case KVM_TPR_ACCESS_REPORTING: {
3758 struct kvm_tpr_access_ctl tac;
3759
3760 r = -EFAULT;
3761 if (copy_from_user(&tac, argp, sizeof tac))
3762 goto out;
3763 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3764 if (r)
3765 goto out;
3766 r = -EFAULT;
3767 if (copy_to_user(argp, &tac, sizeof tac))
3768 goto out;
3769 r = 0;
3770 break;
3771 };
b93463aa
AK		 3772 case KVM_SET_VAPIC_ADDR: {
3773 struct kvm_vapic_addr va;
7301d6ab 3774 int idx;
b93463aa
AK		 3775
3776 r = -EINVAL;
35754c98 3777 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3778 goto out;
3779 r = -EFAULT;
3780 if (copy_from_user(&va, argp, sizeof va))
3781 goto out;
7301d6ab 3782 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3783 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3784 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3785 break;
3786 }
890ca9ae
HY		 3787 case KVM_X86_SETUP_MCE: {
3788 u64 mcg_cap;
3789
3790 r = -EFAULT;
3791 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3792 goto out;
3793 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3794 break;
3795 }
3796 case KVM_X86_SET_MCE: {
3797 struct kvm_x86_mce mce;
3798
3799 r = -EFAULT;
3800 if (copy_from_user(&mce, argp, sizeof mce))
3801 goto out;
3802 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3803 break;
3804 }
3cfc3092
JK		 3805 case KVM_GET_VCPU_EVENTS: {
3806 struct kvm_vcpu_events events;
3807
3808 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3809
3810 r = -EFAULT;
3811 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3812 break;
3813 r = 0;
3814 break;
3815 }
3816 case KVM_SET_VCPU_EVENTS: {
3817 struct kvm_vcpu_events events;
3818
3819 r = -EFAULT;
3820 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3821 break;
3822
3823 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3824 break;
3825 }
a1efbe77
JK		 3826 case KVM_GET_DEBUGREGS: {
3827 struct kvm_debugregs dbgregs;
3828
3829 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3830
3831 r = -EFAULT;
3832 if (copy_to_user(argp, &dbgregs,
3833 sizeof(struct kvm_debugregs)))
3834 break;
3835 r = 0;
3836 break;
3837 }
3838 case KVM_SET_DEBUGREGS: {
3839 struct kvm_debugregs dbgregs;
3840
3841 r = -EFAULT;
3842 if (copy_from_user(&dbgregs, argp,
3843 sizeof(struct kvm_debugregs)))
3844 break;
3845
3846 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3847 break;
3848 }
2d5b5a66 3849 case KVM_GET_XSAVE: {
d1ac91d8 3850 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3851 r = -ENOMEM;
d1ac91d8 3852 if (!u.xsave)
2d5b5a66
SY		 3853 break;
3854
d1ac91d8 3855 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3856
3857 r = -EFAULT;
d1ac91d8 3858 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3859 break;
3860 r = 0;
3861 break;
3862 }
3863 case KVM_SET_XSAVE: {
ff5c2c03 3864 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3865 if (IS_ERR(u.xsave)) {
3866 r = PTR_ERR(u.xsave);
3867 goto out_nofree;
3868 }
2d5b5a66 3869
d1ac91d8 3870 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3871 break;
3872 }
3873 case KVM_GET_XCRS: {
d1ac91d8 3874 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3875 r = -ENOMEM;
d1ac91d8 3876 if (!u.xcrs)
2d5b5a66
SY		 3877 break;
3878
d1ac91d8 3879 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3880
3881 r = -EFAULT;
d1ac91d8 3882 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3883 sizeof(struct kvm_xcrs)))
3884 break;
3885 r = 0;
3886 break;
3887 }
3888 case KVM_SET_XCRS: {
ff5c2c03 3889 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3890 if (IS_ERR(u.xcrs)) {
3891 r = PTR_ERR(u.xcrs);
3892 goto out_nofree;
3893 }
2d5b5a66 3894
d1ac91d8 3895 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3896 break;
3897 }
92a1f12d
JR		 3898 case KVM_SET_TSC_KHZ: {
3899 u32 user_tsc_khz;
3900
3901 r = -EINVAL;
92a1f12d
JR		 3902 user_tsc_khz = (u32)arg;
3903
3904 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3905 goto out;
3906
cc578287
ZA		 3907 if (user_tsc_khz == 0)
3908 user_tsc_khz = tsc_khz;
3909
381d585c
HZ		 3910 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3911 r = 0;
92a1f12d 3912
92a1f12d
JR		 3913 goto out;
3914 }
3915 case KVM_GET_TSC_KHZ: {
cc578287 3916 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3917 goto out;
3918 }
1c0b28c2
EM		 3919 case KVM_KVMCLOCK_CTRL: {
3920 r = kvm_set_guest_paused(vcpu);
3921 goto out;
3922 }
5c919412
AS		 3923 case KVM_ENABLE_CAP: {
3924 struct kvm_enable_cap cap;
3925
3926 r = -EFAULT;
3927 if (copy_from_user(&cap, argp, sizeof(cap)))
3928 goto out;
3929 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3930 break;
3931 }
313a3dc7
CO		 3932 default:
3933 r = -EINVAL;
3934 }
3935out:
d1ac91d8 3936 kfree(u.buffer);
9b062471
CD		 3937out_nofree:
3938 vcpu_put(vcpu);
313a3dc7
CO		 3939 return r;
3940}
3941
5b1c1493
CO		 3942int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3943{
3944 return VM_FAULT_SIGBUS;
3945}
3946
1fe779f8
CO		 3947static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3948{
3949 int ret;
3950
3951 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3952 return -EINVAL;
1fe779f8
CO		 3953 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3954 return ret;
3955}
3956
b927a3ce
SY		 3957static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3958 u64 ident_addr)
3959{
3960 kvm->arch.ept_identity_map_addr = ident_addr;
3961 return 0;
3962}
3963
1fe779f8
CO		 3964static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3965 u32 kvm_nr_mmu_pages)
3966{
3967 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3968 return -EINVAL;
3969
79fac95e 3970 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3971
3972 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3973 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3974
79fac95e 3975 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3976 return 0;
3977}
3978
3979static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3980{
39de71ec 3981 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3982}
3983
1fe779f8
CO		 3984static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3985{
90bca052 3986 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3987 int r;
3988
3989 r = 0;
3990 switch (chip->chip_id) {
3991 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3992 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3993 sizeof(struct kvm_pic_state));
3994 break;
3995 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3996 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3997 sizeof(struct kvm_pic_state));
3998 break;
3999 case KVM_IRQCHIP_IOAPIC:
33392b49 4000 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4001 break;
4002 default:
4003 r = -EINVAL;
4004 break;
4005 }
4006 return r;
4007}
4008
4009static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4010{
90bca052 4011 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4012 int r;
4013
4014 r = 0;
4015 switch (chip->chip_id) {
4016 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4017 spin_lock(&pic->lock);
4018 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4019 sizeof(struct kvm_pic_state));
90bca052 4020 spin_unlock(&pic->lock);
1fe779f8
CO		 4021 break;
4022 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4023 spin_lock(&pic->lock);
4024 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4025 sizeof(struct kvm_pic_state));
90bca052 4026 spin_unlock(&pic->lock);
1fe779f8
CO		 4027 break;
4028 case KVM_IRQCHIP_IOAPIC:
33392b49 4029 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4030 break;
4031 default:
4032 r = -EINVAL;
4033 break;
4034 }
90bca052 4035 kvm_pic_update_irq(pic);
1fe779f8
CO		 4036 return r;
4037}
4038
e0f63cb9
SY		 4039static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4040{
34f3941c
RK		 4041 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4042
4043 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4044
4045 mutex_lock(&kps->lock);
4046 memcpy(ps, &kps->channels, sizeof(*ps));
4047 mutex_unlock(&kps->lock);
2da29bcc 4048 return 0;
e0f63cb9
SY		 4049}
4050
4051static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4052{
0185604c 4053 int i;
09edea72
RK		 4054 struct kvm_pit *pit = kvm->arch.vpit;
4055
4056 mutex_lock(&pit->pit_state.lock);
34f3941c 4057 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4058 for (i = 0; i < 3; i++)
09edea72
RK		 4059 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4060 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4061 return 0;
e9f42757
BK		 4062}
4063
4064static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4065{
e9f42757
BK		 4066 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4067 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4068 sizeof(ps->channels));
4069 ps->flags = kvm->arch.vpit->pit_state.flags;
4070 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4071 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4072 return 0;
e9f42757
BK		 4073}
4074
4075static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4076{
2da29bcc 4077 int start = 0;
0185604c 4078 int i;
e9f42757 4079 u32 prev_legacy, cur_legacy;
09edea72
RK		 4080 struct kvm_pit *pit = kvm->arch.vpit;
4081
4082 mutex_lock(&pit->pit_state.lock);
4083 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4084 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4085 if (!prev_legacy && cur_legacy)
4086 start = 1;
09edea72
RK		 4087 memcpy(&pit->pit_state.channels, &ps->channels,
4088 sizeof(pit->pit_state.channels));
4089 pit->pit_state.flags = ps->flags;
0185604c 4090 for (i = 0; i < 3; i++)
09edea72 4091 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4092 start && i == 0);
09edea72 4093 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4094 return 0;
e0f63cb9
SY		 4095}
4096
52d939a0
MT		 4097static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4098 struct kvm_reinject_control *control)
4099{
71474e2f
RK		 4100 struct kvm_pit *pit = kvm->arch.vpit;
4101
4102 if (!pit)
52d939a0 4103 return -ENXIO;
b39c90b6 4104
71474e2f
RK		 4105 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4106 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4107 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4108 */
4109 mutex_lock(&pit->pit_state.lock);
4110 kvm_pit_set_reinject(pit, control->pit_reinject);
4111 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4112
52d939a0
MT		 4113 return 0;
4114}
4115
95d4c16c 4116/**
60c34612
TY		 4117 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4118 * @kvm: kvm instance
4119 * @log: slot id and address to which we copy the log
95d4c16c 4120 *
e108ff2f
PB		 4121 * Steps 1-4 below provide general overview of dirty page logging. See
4122 * kvm_get_dirty_log_protect() function description for additional details.
4123 *
4124 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4125 * always flush the TLB (step 4) even if previous step failed and the dirty
4126 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4127 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4128 * writes will be marked dirty for next log read.
95d4c16c 4129 *
60c34612
TY		 4130 * 1. Take a snapshot of the bit and clear it if needed.
4131 * 2. Write protect the corresponding page.
e108ff2f
PB		 4132 * 3. Copy the snapshot to the userspace.
4133 * 4. Flush TLB's if needed.
5bb064dc 4134 */
60c34612 4135int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4136{
60c34612 4137 bool is_dirty = false;
e108ff2f 4138 int r;
5bb064dc 4139
79fac95e 4140 mutex_lock(&kvm->slots_lock);
5bb064dc 4141
88178fd4
KH		 4142 /*
4143 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4144 */
4145 if (kvm_x86_ops->flush_log_dirty)
4146 kvm_x86_ops->flush_log_dirty(kvm);
4147
e108ff2f 4148 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4149
4150 /*
4151 * All the TLBs can be flushed out of mmu lock, see the comments in
4152 * kvm_mmu_slot_remove_write_access().
4153 */
e108ff2f 4154 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4155 if (is_dirty)
4156 kvm_flush_remote_tlbs(kvm);
4157
79fac95e 4158 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4159 return r;
4160}
4161
aa2fbe6d
YZ		 4162int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4163 bool line_status)
23d43cf9
CD		 4164{
4165 if (!irqchip_in_kernel(kvm))
4166 return -ENXIO;
4167
4168 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4169 irq_event->irq, irq_event->level,
4170 line_status);
23d43cf9
CD		 4171 return 0;
4172}
4173
90de4a18
NA		 4174static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4175 struct kvm_enable_cap *cap)
4176{
4177 int r;
4178
4179 if (cap->flags)
4180 return -EINVAL;
4181
4182 switch (cap->cap) {
4183 case KVM_CAP_DISABLE_QUIRKS:
4184 kvm->arch.disabled_quirks = cap->args[0];
4185 r = 0;
4186 break;
49df6397
SR		 4187 case KVM_CAP_SPLIT_IRQCHIP: {
4188 mutex_lock(&kvm->lock);
b053b2ae
SR		 4189 r = -EINVAL;
4190 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4191 goto split_irqchip_unlock;
49df6397
SR		 4192 r = -EEXIST;
4193 if (irqchip_in_kernel(kvm))
4194 goto split_irqchip_unlock;
557abc40 4195 if (kvm->created_vcpus)
49df6397
SR		 4196 goto split_irqchip_unlock;
4197 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4198 if (r)
49df6397
SR		 4199 goto split_irqchip_unlock;
4200 /* Pairs with irqchip_in_kernel. */
4201 smp_wmb();
49776faf 4202 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4203 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4204 r = 0;
4205split_irqchip_unlock:
4206 mutex_unlock(&kvm->lock);
4207 break;
4208 }
37131313
RK		 4209 case KVM_CAP_X2APIC_API:
4210 r = -EINVAL;
4211 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4212 break;
4213
4214 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4215 kvm->arch.x2apic_format = true;
c519265f
RK		 4216 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4217 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4218
4219 r = 0;
4220 break;
90de4a18
NA		 4221 default:
4222 r = -EINVAL;
4223 break;
4224 }
4225 return r;
4226}
4227
1fe779f8
CO		 4228long kvm_arch_vm_ioctl(struct file *filp,
4229 unsigned int ioctl, unsigned long arg)
4230{
4231 struct kvm *kvm = filp->private_data;
4232 void __user *argp = (void __user *)arg;
367e1319 4233 int r = -ENOTTY;
f0d66275
DH		 4234 /*
4235 * This union makes it completely explicit to gcc-3.x
4236 * that these two variables' stack usage should be
4237 * combined, not added together.
4238 */
4239 union {
4240 struct kvm_pit_state ps;
e9f42757 4241 struct kvm_pit_state2 ps2;
c5ff41ce 4242 struct kvm_pit_config pit_config;
f0d66275 4243 } u;
1fe779f8
CO		 4244
4245 switch (ioctl) {
4246 case KVM_SET_TSS_ADDR:
4247 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4248 break;
b927a3ce
SY		 4249 case KVM_SET_IDENTITY_MAP_ADDR: {
4250 u64 ident_addr;
4251
1af1ac91
DH		 4252 mutex_lock(&kvm->lock);
4253 r = -EINVAL;
4254 if (kvm->created_vcpus)
4255 goto set_identity_unlock;
b927a3ce
SY		 4256 r = -EFAULT;
4257 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4258 goto set_identity_unlock;
b927a3ce 4259 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4260set_identity_unlock:
4261 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4262 break;
4263 }
1fe779f8
CO		 4264 case KVM_SET_NR_MMU_PAGES:
4265 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4266 break;
4267 case KVM_GET_NR_MMU_PAGES:
4268 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4269 break;
3ddea128 4270 case KVM_CREATE_IRQCHIP: {
3ddea128 4271 mutex_lock(&kvm->lock);
09941366 4272
3ddea128 4273 r = -EEXIST;
35e6eaa3 4274 if (irqchip_in_kernel(kvm))
3ddea128 4275 goto create_irqchip_unlock;
09941366 4276
3e515705 4277 r = -EINVAL;
557abc40 4278 if (kvm->created_vcpus)
3e515705 4279 goto create_irqchip_unlock;
09941366
RK		 4280
4281 r = kvm_pic_init(kvm);
4282 if (r)
3ddea128 4283 goto create_irqchip_unlock;
09941366
RK		 4284
4285 r = kvm_ioapic_init(kvm);
4286 if (r) {
09941366 4287 kvm_pic_destroy(kvm);
3ddea128 4288 goto create_irqchip_unlock;
09941366
RK		 4289 }
4290
399ec807
AK		 4291 r = kvm_setup_default_irq_routing(kvm);
4292 if (r) {
72bb2fcd 4293 kvm_ioapic_destroy(kvm);
09941366 4294 kvm_pic_destroy(kvm);
71ba994c 4295 goto create_irqchip_unlock;
399ec807 4296 }
49776faf 4297 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4298 smp_wmb();
49776faf 4299 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4300 create_irqchip_unlock:
4301 mutex_unlock(&kvm->lock);
1fe779f8 4302 break;
3ddea128 4303 }
7837699f 4304 case KVM_CREATE_PIT:
c5ff41ce
JK		 4305 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4306 goto create_pit;
4307 case KVM_CREATE_PIT2:
4308 r = -EFAULT;
4309 if (copy_from_user(&u.pit_config, argp,
4310 sizeof(struct kvm_pit_config)))
4311 goto out;
4312 create_pit:
250715a6 4313 mutex_lock(&kvm->lock);
269e05e4
AK		 4314 r = -EEXIST;
4315 if (kvm->arch.vpit)
4316 goto create_pit_unlock;
7837699f 4317 r = -ENOMEM;
c5ff41ce 4318 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4319 if (kvm->arch.vpit)
4320 r = 0;
269e05e4 4321 create_pit_unlock:
250715a6 4322 mutex_unlock(&kvm->lock);
7837699f 4323 break;
1fe779f8
CO		 4324 case KVM_GET_IRQCHIP: {
4325 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4326 struct kvm_irqchip *chip;
1fe779f8 4327
ff5c2c03
SL		 4328 chip = memdup_user(argp, sizeof(*chip));
4329 if (IS_ERR(chip)) {
4330 r = PTR_ERR(chip);
1fe779f8 4331 goto out;
ff5c2c03
SL		 4332 }
4333
1fe779f8 4334 r = -ENXIO;
826da321 4335 if (!irqchip_kernel(kvm))
f0d66275
DH		 4336 goto get_irqchip_out;
4337 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4338 if (r)
f0d66275 4339 goto get_irqchip_out;
1fe779f8 4340 r = -EFAULT;
f0d66275
DH		 4341 if (copy_to_user(argp, chip, sizeof *chip))
4342 goto get_irqchip_out;
1fe779f8 4343 r = 0;
f0d66275
DH		 4344 get_irqchip_out:
4345 kfree(chip);
1fe779f8
CO		 4346 break;
4347 }
4348 case KVM_SET_IRQCHIP: {
4349 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4350 struct kvm_irqchip *chip;
1fe779f8 4351
ff5c2c03
SL		 4352 chip = memdup_user(argp, sizeof(*chip));
4353 if (IS_ERR(chip)) {
4354 r = PTR_ERR(chip);
1fe779f8 4355 goto out;
ff5c2c03
SL		 4356 }
4357
1fe779f8 4358 r = -ENXIO;
826da321 4359 if (!irqchip_kernel(kvm))
f0d66275
DH		 4360 goto set_irqchip_out;
4361 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4362 if (r)
f0d66275 4363 goto set_irqchip_out;
1fe779f8 4364 r = 0;
f0d66275
DH		 4365 set_irqchip_out:
4366 kfree(chip);
1fe779f8
CO		 4367 break;
4368 }
e0f63cb9 4369 case KVM_GET_PIT: {
e0f63cb9 4370 r = -EFAULT;
f0d66275 4371 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4372 goto out;
4373 r = -ENXIO;
4374 if (!kvm->arch.vpit)
4375 goto out;
f0d66275 4376 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4377 if (r)
4378 goto out;
4379 r = -EFAULT;
f0d66275 4380 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4381 goto out;
4382 r = 0;
4383 break;
4384 }
4385 case KVM_SET_PIT: {
e0f63cb9 4386 r = -EFAULT;
f0d66275 4387 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4388 goto out;
4389 r = -ENXIO;
4390 if (!kvm->arch.vpit)
4391 goto out;
f0d66275 4392 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4393 break;
4394 }
e9f42757
BK		 4395 case KVM_GET_PIT2: {
4396 r = -ENXIO;
4397 if (!kvm->arch.vpit)
4398 goto out;
4399 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4400 if (r)
4401 goto out;
4402 r = -EFAULT;
4403 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4404 goto out;
4405 r = 0;
4406 break;
4407 }
4408 case KVM_SET_PIT2: {
4409 r = -EFAULT;
4410 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4411 goto out;
4412 r = -ENXIO;
4413 if (!kvm->arch.vpit)
4414 goto out;
4415 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4416 break;
4417 }
52d939a0
MT		 4418 case KVM_REINJECT_CONTROL: {
4419 struct kvm_reinject_control control;
4420 r = -EFAULT;
4421 if (copy_from_user(&control, argp, sizeof(control)))
4422 goto out;
4423 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4424 break;
4425 }
d71ba788
PB		 4426 case KVM_SET_BOOT_CPU_ID:
4427 r = 0;
4428 mutex_lock(&kvm->lock);
557abc40 4429 if (kvm->created_vcpus)
d71ba788
PB		 4430 r = -EBUSY;
4431 else
4432 kvm->arch.bsp_vcpu_id = arg;
4433 mutex_unlock(&kvm->lock);
4434 break;
ffde22ac 4435 case KVM_XEN_HVM_CONFIG: {
51776043 4436 struct kvm_xen_hvm_config xhc;
ffde22ac 4437 r = -EFAULT;
51776043 4438 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4439 goto out;
4440 r = -EINVAL;
51776043 4441 if (xhc.flags)
ffde22ac 4442 goto out;
51776043 4443 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4444 r = 0;
4445 break;
4446 }
afbcf7ab 4447 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4448 struct kvm_clock_data user_ns;
4449 u64 now_ns;
afbcf7ab
GC		 4450
4451 r = -EFAULT;
4452 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4453 goto out;
4454
4455 r = -EINVAL;
4456 if (user_ns.flags)
4457 goto out;
4458
4459 r = 0;
0bc48bea
RK		 4460 /*
4461 * TODO: userspace has to take care of races with VCPU_RUN, so
4462 * kvm_gen_update_masterclock() can be cut down to locked
4463 * pvclock_update_vm_gtod_copy().
4464 */
4465 kvm_gen_update_masterclock(kvm);
e891a32e 4466 now_ns = get_kvmclock_ns(kvm);
108b249c 4467 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4468 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4469 break;
4470 }
4471 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4472 struct kvm_clock_data user_ns;
4473 u64 now_ns;
4474
e891a32e 4475 now_ns = get_kvmclock_ns(kvm);
108b249c 4476 user_ns.clock = now_ns;
e3fd9a93 4477 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4478 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4479
4480 r = -EFAULT;
4481 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4482 goto out;
4483 r = 0;
4484 break;
4485 }
90de4a18
NA		 4486 case KVM_ENABLE_CAP: {
4487 struct kvm_enable_cap cap;
afbcf7ab 4488
90de4a18
NA		 4489 r = -EFAULT;
4490 if (copy_from_user(&cap, argp, sizeof(cap)))
4491 goto out;
4492 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4493 break;
4494 }
5acc5c06
BS		 4495 case KVM_MEMORY_ENCRYPT_OP: {
4496 r = -ENOTTY;
4497 if (kvm_x86_ops->mem_enc_op)
4498 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4499 break;
4500 }
69eaedee
BS		 4501 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4502 struct kvm_enc_region region;
4503
4504 r = -EFAULT;
4505 if (copy_from_user(&region, argp, sizeof(region)))
4506 goto out;
4507
4508 r = -ENOTTY;
4509 if (kvm_x86_ops->mem_enc_reg_region)
4510 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4511 break;
4512 }
4513 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4514 struct kvm_enc_region region;
4515
4516 r = -EFAULT;
4517 if (copy_from_user(&region, argp, sizeof(region)))
4518 goto out;
4519
4520 r = -ENOTTY;
4521 if (kvm_x86_ops->mem_enc_unreg_region)
4522 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4523 break;
4524 }
faeb7833
RK		 4525 case KVM_HYPERV_EVENTFD: {
4526 struct kvm_hyperv_eventfd hvevfd;
4527
4528 r = -EFAULT;
4529 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4530 goto out;
4531 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4532 break;
4533 }
1fe779f8 4534 default:
ad6260da 4535 r = -ENOTTY;
1fe779f8
CO		 4536 }
4537out:
4538 return r;
4539}
4540
a16b043c 4541static void kvm_init_msr_list(void)
043405e1
CO		 4542{
4543 u32 dummy[2];
4544 unsigned i, j;
4545
62ef68bb 4546 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4547 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4548 continue;
93c4adc7
PB		 4549
4550 /*
4551 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4552 * to the guests in some cases.
93c4adc7
PB		 4553 */
4554 switch (msrs_to_save[i]) {
4555 case MSR_IA32_BNDCFGS:
4556 if (!kvm_x86_ops->mpx_supported())
4557 continue;
4558 break;
9dbe6cf9
PB		 4559 case MSR_TSC_AUX:
4560 if (!kvm_x86_ops->rdtscp_supported())
4561 continue;
4562 break;
93c4adc7
PB		 4563 default:
4564 break;
4565 }
4566
043405e1
CO		 4567 if (j < i)
4568 msrs_to_save[j] = msrs_to_save[i];
4569 j++;
4570 }
4571 num_msrs_to_save = j;
62ef68bb
PB		 4572
4573 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4574 switch (emulated_msrs[i]) {
6d396b55
PB		 4575 case MSR_IA32_SMBASE:
4576 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4577 continue;
4578 break;
62ef68bb
PB		 4579 default:
4580 break;
4581 }
4582
4583 if (j < i)
4584 emulated_msrs[j] = emulated_msrs[i];
4585 j++;
4586 }
4587 num_emulated_msrs = j;
801e459a
TL		 4588
4589 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4590 struct kvm_msr_entry msr;
4591
4592 msr.index = msr_based_features[i];
66421c1e 4593 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4594 continue;
4595
4596 if (j < i)
4597 msr_based_features[j] = msr_based_features[i];
4598 j++;
4599 }
4600 num_msr_based_features = j;
043405e1
CO		 4601}
4602
bda9020e
MT		 4603static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4604 const void *v)
bbd9b64e 4605{
70252a10
AK		 4606 int handled = 0;
4607 int n;
4608
4609 do {
4610 n = min(len, 8);
bce87cce 4611 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4612 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4613 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4614 break;
4615 handled += n;
4616 addr += n;
4617 len -= n;
4618 v += n;
4619 } while (len);
bbd9b64e 4620
70252a10 4621 return handled;
bbd9b64e
CO		 4622}
4623
bda9020e 4624static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4625{
70252a10
AK		 4626 int handled = 0;
4627 int n;
4628
4629 do {
4630 n = min(len, 8);
bce87cce 4631 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4632 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4633 addr, n, v))
4634 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4635 break;
e39d200f 4636 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4637 handled += n;
4638 addr += n;
4639 len -= n;
4640 v += n;
4641 } while (len);
bbd9b64e 4642
70252a10 4643 return handled;
bbd9b64e
CO		 4644}
4645
2dafc6c2
GN		 4646static void kvm_set_segment(struct kvm_vcpu *vcpu,
4647 struct kvm_segment *var, int seg)
4648{
4649 kvm_x86_ops->set_segment(vcpu, var, seg);
4650}
4651
4652void kvm_get_segment(struct kvm_vcpu *vcpu,
4653 struct kvm_segment *var, int seg)
4654{
4655 kvm_x86_ops->get_segment(vcpu, var, seg);
4656}
4657
54987b7a
PB		 4658gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4659 struct x86_exception *exception)
02f59dc9
JR		 4660{
4661 gpa_t t_gpa;
02f59dc9
JR		 4662
4663 BUG_ON(!mmu_is_nested(vcpu));
4664
4665 /* NPT walks are always user-walks */
4666 access |= PFERR_USER_MASK;
54987b7a 4667 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4668
4669 return t_gpa;
4670}
4671
ab9ae313
AK		 4672gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4673 struct x86_exception *exception)
1871c602
GN		 4674{
4675 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4676 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4677}
4678
ab9ae313
AK		 4679 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4680 struct x86_exception *exception)
1871c602
GN		 4681{
4682 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4683 access |= PFERR_FETCH_MASK;
ab9ae313 4684 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4685}
4686
ab9ae313
AK		 4687gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4688 struct x86_exception *exception)
1871c602
GN		 4689{
4690 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4691 access |= PFERR_WRITE_MASK;
ab9ae313 4692 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4693}
4694
4695/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4696gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4697 struct x86_exception *exception)
1871c602 4698{
ab9ae313 4699 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4700}
4701
4702static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4703 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4704 struct x86_exception *exception)
bbd9b64e
CO		 4705{
4706 void *data = val;
10589a46 4707 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4708
4709 while (bytes) {
14dfe855 4710 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4711 exception);
bbd9b64e 4712 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4713 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4714 int ret;
4715
bcc55cba 4716 if (gpa == UNMAPPED_GVA)
ab9ae313 4717 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4718 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4719 offset, toread);
10589a46 4720 if (ret < 0) {
c3cd7ffa 4721 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4722 goto out;
4723 }
bbd9b64e 4724
77c2002e
IE		 4725 bytes -= toread;
4726 data += toread;
4727 addr += toread;
bbd9b64e 4728 }
10589a46 4729out:
10589a46 4730 return r;
bbd9b64e 4731}
77c2002e 4732
1871c602 4733/* used for instruction fetching */
0f65dd70
AK		 4734static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4735 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4736 struct x86_exception *exception)
1871c602 4737{
0f65dd70 4738 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4739 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4740 unsigned offset;
4741 int ret;
0f65dd70 4742
44583cba
PB		 4743 /* Inline kvm_read_guest_virt_helper for speed. */
4744 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4745 exception);
4746 if (unlikely(gpa == UNMAPPED_GVA))
4747 return X86EMUL_PROPAGATE_FAULT;
4748
4749 offset = addr & (PAGE_SIZE-1);
4750 if (WARN_ON(offset + bytes > PAGE_SIZE))
4751 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4752 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4753 offset, bytes);
44583cba
PB		 4754 if (unlikely(ret < 0))
4755 return X86EMUL_IO_NEEDED;
4756
4757 return X86EMUL_CONTINUE;
1871c602
GN		 4758}
4759
064aea77 4760int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4761 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4762 struct x86_exception *exception)
1871c602 4763{
0f65dd70 4764 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4765 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4766
1871c602 4767 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4768 exception);
1871c602 4769}
064aea77 4770EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4771
0f65dd70
AK		 4772static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4773 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4774 struct x86_exception *exception)
1871c602 4775{
0f65dd70 4776 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4777 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4778}
4779
7a036a6f
RK		 4780static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4781 unsigned long addr, void *val, unsigned int bytes)
4782{
4783 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4784 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4785
4786 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4787}
4788
6a4d7550 4789int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4790 gva_t addr, void *val,
2dafc6c2 4791 unsigned int bytes,
bcc55cba 4792 struct x86_exception *exception)
77c2002e 4793{
0f65dd70 4794 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4795 void *data = val;
4796 int r = X86EMUL_CONTINUE;
4797
4798 while (bytes) {
14dfe855
JR		 4799 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4800 PFERR_WRITE_MASK,
ab9ae313 4801 exception);
77c2002e
IE		 4802 unsigned offset = addr & (PAGE_SIZE-1);
4803 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4804 int ret;
4805
bcc55cba 4806 if (gpa == UNMAPPED_GVA)
ab9ae313 4807 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4808 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4809 if (ret < 0) {
c3cd7ffa 4810 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4811 goto out;
4812 }
4813
4814 bytes -= towrite;
4815 data += towrite;
4816 addr += towrite;
4817 }
4818out:
4819 return r;
4820}
6a4d7550 4821EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4822
0f89b207
TL		 4823static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4824 gpa_t gpa, bool write)
4825{
4826 /* For APIC access vmexit */
4827 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4828 return 1;
4829
4830 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4831 trace_vcpu_match_mmio(gva, gpa, write, true);
4832 return 1;
4833 }
4834
4835 return 0;
4836}
4837
af7cc7d1
XG		 4838static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4839 gpa_t *gpa, struct x86_exception *exception,
4840 bool write)
4841{
97d64b78
AK		 4842 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4843 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4844
be94f6b7
HH		 4845 /*
4846 * currently PKRU is only applied to ept enabled guest so
4847 * there is no pkey in EPT page table for L1 guest or EPT
4848 * shadow page table for L2 guest.
4849 */
97d64b78 4850 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4851 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4852 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4853 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4854 (gva & (PAGE_SIZE - 1));
4f022648 4855 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4856 return 1;
4857 }
4858
af7cc7d1
XG		 4859 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4860
4861 if (*gpa == UNMAPPED_GVA)
4862 return -1;
4863
0f89b207 4864 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4865}
4866
3200f405 4867int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4868 const void *val, int bytes)
bbd9b64e
CO		 4869{
4870 int ret;
4871
54bf36aa 4872 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4873 if (ret < 0)
bbd9b64e 4874 return 0;
0eb05bf2 4875 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4876 return 1;
4877}
4878
77d197b2
XG		 4879struct read_write_emulator_ops {
4880 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4881 int bytes);
4882 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4883 void *val, int bytes);
4884 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4885 int bytes, void *val);
4886 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4887 void *val, int bytes);
4888 bool write;
4889};
4890
4891static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4892{
4893 if (vcpu->mmio_read_completed) {
77d197b2 4894 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4895 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4896 vcpu->mmio_read_completed = 0;
4897 return 1;
4898 }
4899
4900 return 0;
4901}
4902
4903static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4904 void *val, int bytes)
4905{
54bf36aa 4906 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4907}
4908
4909static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4910 void *val, int bytes)
4911{
4912 return emulator_write_phys(vcpu, gpa, val, bytes);
4913}
4914
4915static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4916{
e39d200f 4917 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4918 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4919}
4920
4921static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4922 void *val, int bytes)
4923{
e39d200f 4924 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4925 return X86EMUL_IO_NEEDED;
4926}
4927
4928static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4929 void *val, int bytes)
4930{
f78146b0
AK		 4931 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4932
87da7e66 4933 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4934 return X86EMUL_CONTINUE;
4935}
4936
0fbe9b0b 4937static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4938 .read_write_prepare = read_prepare,
4939 .read_write_emulate = read_emulate,
4940 .read_write_mmio = vcpu_mmio_read,
4941 .read_write_exit_mmio = read_exit_mmio,
4942};
4943
0fbe9b0b 4944static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4945 .read_write_emulate = write_emulate,
4946 .read_write_mmio = write_mmio,
4947 .read_write_exit_mmio = write_exit_mmio,
4948 .write = true,
4949};
4950
22388a3c
XG		 4951static int emulator_read_write_onepage(unsigned long addr, void *val,
4952 unsigned int bytes,
4953 struct x86_exception *exception,
4954 struct kvm_vcpu *vcpu,
0fbe9b0b 4955 const struct read_write_emulator_ops *ops)
bbd9b64e 4956{
af7cc7d1
XG		 4957 gpa_t gpa;
4958 int handled, ret;
22388a3c 4959 bool write = ops->write;
f78146b0 4960 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4961 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4962
4963 /*
4964 * If the exit was due to a NPF we may already have a GPA.
4965 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4966 * Note, this cannot be used on string operations since string
4967 * operation using rep will only have the initial GPA from the NPF
4968 * occurred.
4969 */
4970 if (vcpu->arch.gpa_available &&
4971 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4972 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4973 gpa = vcpu->arch.gpa_val;
4974 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4975 } else {
4976 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4977 if (ret < 0)
4978 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4979 }
10589a46 4980
618232e2 4981 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4982 return X86EMUL_CONTINUE;
4983
bbd9b64e
CO		 4984 /*
4985 * Is this MMIO handled locally?
4986 */
22388a3c 4987 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4988 if (handled == bytes)
bbd9b64e 4989 return X86EMUL_CONTINUE;
bbd9b64e 4990
70252a10
AK		 4991 gpa += handled;
4992 bytes -= handled;
4993 val += handled;
4994
87da7e66
XG		 4995 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4996 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4997 frag->gpa = gpa;
4998 frag->data = val;
4999 frag->len = bytes;
f78146b0 5000 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5001}
5002
52eb5a6d
XL		 5003static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5004 unsigned long addr,
22388a3c
XG		 5005 void *val, unsigned int bytes,
5006 struct x86_exception *exception,
0fbe9b0b 5007 const struct read_write_emulator_ops *ops)
bbd9b64e 5008{
0f65dd70 5009 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5010 gpa_t gpa;
5011 int rc;
5012
5013 if (ops->read_write_prepare &&
5014 ops->read_write_prepare(vcpu, val, bytes))
5015 return X86EMUL_CONTINUE;
5016
5017 vcpu->mmio_nr_fragments = 0;
0f65dd70 5018
bbd9b64e
CO		 5019 /* Crossing a page boundary? */
5020 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5021 int now;
bbd9b64e
CO		 5022
5023 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5024 rc = emulator_read_write_onepage(addr, val, now, exception,
5025 vcpu, ops);
5026
bbd9b64e
CO		 5027 if (rc != X86EMUL_CONTINUE)
5028 return rc;
5029 addr += now;
bac15531
NA		 5030 if (ctxt->mode != X86EMUL_MODE_PROT64)
5031 addr = (u32)addr;
bbd9b64e
CO		 5032 val += now;
5033 bytes -= now;
5034 }
22388a3c 5035
f78146b0
AK		 5036 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5037 vcpu, ops);
5038 if (rc != X86EMUL_CONTINUE)
5039 return rc;
5040
5041 if (!vcpu->mmio_nr_fragments)
5042 return rc;
5043
5044 gpa = vcpu->mmio_fragments[0].gpa;
5045
5046 vcpu->mmio_needed = 1;
5047 vcpu->mmio_cur_fragment = 0;
5048
87da7e66 5049 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5050 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5051 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5052 vcpu->run->mmio.phys_addr = gpa;
5053
5054 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5055}
5056
5057static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5058 unsigned long addr,
5059 void *val,
5060 unsigned int bytes,
5061 struct x86_exception *exception)
5062{
5063 return emulator_read_write(ctxt, addr, val, bytes,
5064 exception, &read_emultor);
5065}
5066
52eb5a6d 5067static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5068 unsigned long addr,
5069 const void *val,
5070 unsigned int bytes,
5071 struct x86_exception *exception)
5072{
5073 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5074 exception, &write_emultor);
bbd9b64e 5075}
bbd9b64e 5076
daea3e73
AK		 5077#define CMPXCHG_TYPE(t, ptr, old, new) \
5078 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5079
5080#ifdef CONFIG_X86_64
5081# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5082#else
5083# define CMPXCHG64(ptr, old, new) \
9749a6c0 5084 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5085#endif
5086
0f65dd70
AK		 5087static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5088 unsigned long addr,
bbd9b64e
CO		 5089 const void *old,
5090 const void *new,
5091 unsigned int bytes,
0f65dd70 5092 struct x86_exception *exception)
bbd9b64e 5093{
0f65dd70 5094 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5095 gpa_t gpa;
5096 struct page *page;
5097 char *kaddr;
5098 bool exchanged;
2bacc55c 5099
daea3e73
AK		 5100 /* guests cmpxchg8b have to be emulated atomically */
5101 if (bytes > 8 || (bytes & (bytes - 1)))
5102 goto emul_write;
10589a46 5103
daea3e73 5104 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5105
daea3e73
AK		 5106 if (gpa == UNMAPPED_GVA ||
5107 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5108 goto emul_write;
2bacc55c 5109
daea3e73
AK		 5110 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5111 goto emul_write;
72dc67a6 5112
54bf36aa 5113 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5114 if (is_error_page(page))
c19b8bd6 5115 goto emul_write;
72dc67a6 5116
8fd75e12 5117 kaddr = kmap_atomic(page);
daea3e73
AK		 5118 kaddr += offset_in_page(gpa);
5119 switch (bytes) {
5120 case 1:
5121 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5122 break;
5123 case 2:
5124 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5125 break;
5126 case 4:
5127 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5128 break;
5129 case 8:
5130 exchanged = CMPXCHG64(kaddr, old, new);
5131 break;
5132 default:
5133 BUG();
2bacc55c 5134 }
8fd75e12 5135 kunmap_atomic(kaddr);
daea3e73
AK		 5136 kvm_release_page_dirty(page);
5137
5138 if (!exchanged)
5139 return X86EMUL_CMPXCHG_FAILED;
5140
54bf36aa 5141 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5142 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5143
5144 return X86EMUL_CONTINUE;
4a5f48f6 5145
3200f405 5146emul_write:
daea3e73 5147 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5148
0f65dd70 5149 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5150}
5151
cf8f70bf
GN		 5152static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5153{
cbfc6c91 5154 int r = 0, i;
cf8f70bf 5155
cbfc6c91
WL		 5156 for (i = 0; i < vcpu->arch.pio.count; i++) {
5157 if (vcpu->arch.pio.in)
5158 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5159 vcpu->arch.pio.size, pd);
5160 else
5161 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5162 vcpu->arch.pio.port, vcpu->arch.pio.size,
5163 pd);
5164 if (r)
5165 break;
5166 pd += vcpu->arch.pio.size;
5167 }
cf8f70bf
GN		 5168 return r;
5169}
5170
6f6fbe98
XG		 5171static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5172 unsigned short port, void *val,
5173 unsigned int count, bool in)
cf8f70bf 5174{
cf8f70bf 5175 vcpu->arch.pio.port = port;
6f6fbe98 5176 vcpu->arch.pio.in = in;
7972995b 5177 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5178 vcpu->arch.pio.size = size;
5179
5180 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5181 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5182 return 1;
5183 }
5184
5185 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5186 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5187 vcpu->run->io.size = size;
5188 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5189 vcpu->run->io.count = count;
5190 vcpu->run->io.port = port;
5191
5192 return 0;
5193}
5194
6f6fbe98
XG		 5195static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5196 int size, unsigned short port, void *val,
5197 unsigned int count)
cf8f70bf 5198{
ca1d4a9e 5199 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5200 int ret;
ca1d4a9e 5201
6f6fbe98
XG		 5202 if (vcpu->arch.pio.count)
5203 goto data_avail;
cf8f70bf 5204
cbfc6c91
WL		 5205 memset(vcpu->arch.pio_data, 0, size * count);
5206
6f6fbe98
XG		 5207 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5208 if (ret) {
5209data_avail:
5210 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5211 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5212 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5213 return 1;
5214 }
5215
cf8f70bf
GN		 5216 return 0;
5217}
5218
6f6fbe98
XG		 5219static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5220 int size, unsigned short port,
5221 const void *val, unsigned int count)
5222{
5223 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5224
5225 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5226 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5227 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5228}
5229
bbd9b64e
CO		 5230static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5231{
5232 return kvm_x86_ops->get_segment_base(vcpu, seg);
5233}
5234
3cb16fe7 5235static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5236{
3cb16fe7 5237 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5238}
5239
ae6a2375 5240static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5241{
5242 if (!need_emulate_wbinvd(vcpu))
5243 return X86EMUL_CONTINUE;
5244
5245 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5246 int cpu = get_cpu();
5247
5248 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5249 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5250 wbinvd_ipi, NULL, 1);
2eec7343 5251 put_cpu();
f5f48ee1 5252 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5253 } else
5254 wbinvd();
f5f48ee1
SY		 5255 return X86EMUL_CONTINUE;
5256}
5cb56059
JS		 5257
5258int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5259{
6affcbed
KH		 5260 kvm_emulate_wbinvd_noskip(vcpu);
5261 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5262}
f5f48ee1
SY		 5263EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5264
5cb56059
JS		 5265
5266
bcaf5cc5
AK		 5267static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5268{
5cb56059 5269 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5270}
5271
52eb5a6d
XL		 5272static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5273 unsigned long *dest)
bbd9b64e 5274{
16f8a6f9 5275 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5276}
5277
52eb5a6d
XL		 5278static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5279 unsigned long value)
bbd9b64e 5280{
338dbc97 5281
717746e3 5282 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5283}
5284
52a46617 5285static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5286{
52a46617 5287 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5288}
5289
717746e3 5290static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5291{
717746e3 5292 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5293 unsigned long value;
5294
5295 switch (cr) {
5296 case 0:
5297 value = kvm_read_cr0(vcpu);
5298 break;
5299 case 2:
5300 value = vcpu->arch.cr2;
5301 break;
5302 case 3:
9f8fe504 5303 value = kvm_read_cr3(vcpu);
52a46617
GN		 5304 break;
5305 case 4:
5306 value = kvm_read_cr4(vcpu);
5307 break;
5308 case 8:
5309 value = kvm_get_cr8(vcpu);
5310 break;
5311 default:
a737f256 5312 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5313 return 0;
5314 }
5315
5316 return value;
5317}
5318
717746e3 5319static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5320{
717746e3 5321 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5322 int res = 0;
5323
52a46617
GN		 5324 switch (cr) {
5325 case 0:
49a9b07e 5326 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5327 break;
5328 case 2:
5329 vcpu->arch.cr2 = val;
5330 break;
5331 case 3:
2390218b 5332 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5333 break;
5334 case 4:
a83b29c6 5335 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5336 break;
5337 case 8:
eea1cff9 5338 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5339 break;
5340 default:
a737f256 5341 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5342 res = -1;
52a46617 5343 }
0f12244f
GN		 5344
5345 return res;
52a46617
GN		 5346}
5347
717746e3 5348static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5349{
717746e3 5350 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5351}
5352
4bff1e86 5353static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5354{
4bff1e86 5355 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5356}
5357
4bff1e86 5358static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5359{
4bff1e86 5360 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5361}
5362
1ac9d0cf
AK		 5363static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5364{
5365 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5366}
5367
5368static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5369{
5370 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5371}
5372
4bff1e86
AK		 5373static unsigned long emulator_get_cached_segment_base(
5374 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5375{
4bff1e86 5376 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5377}
5378
1aa36616
AK		 5379static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5380 struct desc_struct *desc, u32 *base3,
5381 int seg)
2dafc6c2
GN		 5382{
5383 struct kvm_segment var;
5384
4bff1e86 5385 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5386 *selector = var.selector;
2dafc6c2 5387
378a8b09
GN		 5388 if (var.unusable) {
5389 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5390 if (base3)
5391 *base3 = 0;
2dafc6c2 5392 return false;
378a8b09 5393 }
2dafc6c2
GN		 5394
5395 if (var.g)
5396 var.limit >>= 12;
5397 set_desc_limit(desc, var.limit);
5398 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5399#ifdef CONFIG_X86_64
5400 if (base3)
5401 *base3 = var.base >> 32;
5402#endif
2dafc6c2
GN		 5403 desc->type = var.type;
5404 desc->s = var.s;
5405 desc->dpl = var.dpl;
5406 desc->p = var.present;
5407 desc->avl = var.avl;
5408 desc->l = var.l;
5409 desc->d = var.db;
5410 desc->g = var.g;
5411
5412 return true;
5413}
5414
1aa36616
AK		 5415static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5416 struct desc_struct *desc, u32 base3,
5417 int seg)
2dafc6c2 5418{
4bff1e86 5419 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5420 struct kvm_segment var;
5421
1aa36616 5422 var.selector = selector;
2dafc6c2 5423 var.base = get_desc_base(desc);
5601d05b
GN		 5424#ifdef CONFIG_X86_64
5425 var.base |= ((u64)base3) << 32;
5426#endif
2dafc6c2
GN		 5427 var.limit = get_desc_limit(desc);
5428 if (desc->g)
5429 var.limit = (var.limit << 12) | 0xfff;
5430 var.type = desc->type;
2dafc6c2
GN		 5431 var.dpl = desc->dpl;
5432 var.db = desc->d;
5433 var.s = desc->s;
5434 var.l = desc->l;
5435 var.g = desc->g;
5436 var.avl = desc->avl;
5437 var.present = desc->p;
5438 var.unusable = !var.present;
5439 var.padding = 0;
5440
5441 kvm_set_segment(vcpu, &var, seg);
5442 return;
5443}
5444
717746e3
AK		 5445static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5446 u32 msr_index, u64 *pdata)
5447{
609e36d3
PB		 5448 struct msr_data msr;
5449 int r;
5450
5451 msr.index = msr_index;
5452 msr.host_initiated = false;
5453 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5454 if (r)
5455 return r;
5456
5457 *pdata = msr.data;
5458 return 0;
717746e3
AK		 5459}
5460
5461static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5462 u32 msr_index, u64 data)
5463{
8fe8ab46
WA		 5464 struct msr_data msr;
5465
5466 msr.data = data;
5467 msr.index = msr_index;
5468 msr.host_initiated = false;
5469 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5470}
5471
64d60670
PB		 5472static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5473{
5474 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5475
5476 return vcpu->arch.smbase;
5477}
5478
5479static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5480{
5481 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5482
5483 vcpu->arch.smbase = smbase;
5484}
5485
67f4d428
NA		 5486static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5487 u32 pmc)
5488{
c6702c9d 5489 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5490}
5491
222d21aa
AK		 5492static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5493 u32 pmc, u64 *pdata)
5494{
c6702c9d 5495 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5496}
5497
6c3287f7
AK		 5498static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5499{
5500 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5501}
5502
2953538e 5503static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5504 struct x86_instruction_info *info,
c4f035c6
AK		 5505 enum x86_intercept_stage stage)
5506{
2953538e 5507 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5508}
5509
e911eb3b
YZ		 5510static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5511 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5512{
e911eb3b 5513 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5514}
5515
dd856efa
AK		 5516static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5517{
5518 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5519}
5520
5521static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5522{
5523 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5524}
5525
801806d9
NA		 5526static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5527{
5528 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5529}
5530
6ed071f0
LP		 5531static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5532{
5533 return emul_to_vcpu(ctxt)->arch.hflags;
5534}
5535
5536static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5537{
5538 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5539}
5540
0234bf88
LP		 5541static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5542{
5543 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5544}
5545
0225fb50 5546static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5547 .read_gpr = emulator_read_gpr,
5548 .write_gpr = emulator_write_gpr,
1871c602 5549 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5550 .write_std = kvm_write_guest_virt_system,
7a036a6f 5551 .read_phys = kvm_read_guest_phys_system,
1871c602 5552 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5553 .read_emulated = emulator_read_emulated,
5554 .write_emulated = emulator_write_emulated,
5555 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5556 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5557 .pio_in_emulated = emulator_pio_in_emulated,
5558 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5559 .get_segment = emulator_get_segment,
5560 .set_segment = emulator_set_segment,
5951c442 5561 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5562 .get_gdt = emulator_get_gdt,
160ce1f1 5563 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5564 .set_gdt = emulator_set_gdt,
5565 .set_idt = emulator_set_idt,
52a46617
GN		 5566 .get_cr = emulator_get_cr,
5567 .set_cr = emulator_set_cr,
9c537244 5568 .cpl = emulator_get_cpl,
35aa5375
GN		 5569 .get_dr = emulator_get_dr,
5570 .set_dr = emulator_set_dr,
64d60670
PB		 5571 .get_smbase = emulator_get_smbase,
5572 .set_smbase = emulator_set_smbase,
717746e3
AK		 5573 .set_msr = emulator_set_msr,
5574 .get_msr = emulator_get_msr,
67f4d428 5575 .check_pmc = emulator_check_pmc,
222d21aa 5576 .read_pmc = emulator_read_pmc,
6c3287f7 5577 .halt = emulator_halt,
bcaf5cc5 5578 .wbinvd = emulator_wbinvd,
d6aa1000 5579 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5580 .intercept = emulator_intercept,
bdb42f5a 5581 .get_cpuid = emulator_get_cpuid,
801806d9 5582 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5583 .get_hflags = emulator_get_hflags,
5584 .set_hflags = emulator_set_hflags,
0234bf88 5585 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5586};
5587
95cb2295
GN		 5588static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5589{
37ccdcbe 5590 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5591 /*
5592 * an sti; sti; sequence only disable interrupts for the first
5593 * instruction. So, if the last instruction, be it emulated or
5594 * not, left the system with the INT_STI flag enabled, it
5595 * means that the last instruction is an sti. We should not
5596 * leave the flag on in this case. The same goes for mov ss
5597 */
37ccdcbe
PB		 5598 if (int_shadow & mask)
5599 mask = 0;
6addfc42 5600 if (unlikely(int_shadow || mask)) {
95cb2295 5601 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5602 if (!mask)
5603 kvm_make_request(KVM_REQ_EVENT, vcpu);
5604 }
95cb2295
GN		 5605}
5606
ef54bcfe 5607static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5608{
5609 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5610 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5611 return kvm_propagate_fault(vcpu, &ctxt->exception);
5612
5613 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5614 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5615 ctxt->exception.error_code);
54b8486f 5616 else
da9cb575 5617 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5618 return false;
54b8486f
GN		 5619}
5620
8ec4722d
MG		 5621static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5622{
adf52235 5623 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5624 int cs_db, cs_l;
5625
8ec4722d
MG		 5626 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5627
adf52235 5628 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5629 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5630
adf52235
TY		 5631 ctxt->eip = kvm_rip_read(vcpu);
5632 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5633 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5634 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5635 cs_db ? X86EMUL_MODE_PROT32 :
5636 X86EMUL_MODE_PROT16;
a584539b 5637 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5638 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5639 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5640
dd856efa 5641 init_decode_cache(ctxt);
7ae441ea 5642 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5643}
5644
71f9833b 5645int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5646{
9d74191a 5647 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5648 int ret;
5649
5650 init_emulate_ctxt(vcpu);
5651
9dac77fa
AK		 5652 ctxt->op_bytes = 2;
5653 ctxt->ad_bytes = 2;
5654 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5655 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5656
5657 if (ret != X86EMUL_CONTINUE)
5658 return EMULATE_FAIL;
5659
9dac77fa 5660 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5661 kvm_rip_write(vcpu, ctxt->eip);
5662 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5663
5664 if (irq == NMI_VECTOR)
7460fb4a 5665 vcpu->arch.nmi_pending = 0;
63995653
MG		 5666 else
5667 vcpu->arch.interrupt.pending = false;
5668
5669 return EMULATE_DONE;
5670}
5671EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5672
e2366171 5673static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5674{
fc3a9157
JR		 5675 int r = EMULATE_DONE;
5676
6d77dbfc
GN		 5677 ++vcpu->stat.insn_emulation_fail;
5678 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5679
5680 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5681 return EMULATE_FAIL;
5682
a2b9e6c1 5683 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5684 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5685 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5686 vcpu->run->internal.ndata = 0;
1f4dcb3b 5687 r = EMULATE_USER_EXIT;
fc3a9157 5688 }
e2366171 5689
6d77dbfc 5690 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5691
5692 return r;
6d77dbfc
GN		 5693}
5694
93c05d3e 5695static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5696 bool write_fault_to_shadow_pgtable,
5697 int emulation_type)
a6f177ef 5698{
95b3cf69 5699 gpa_t gpa = cr2;
ba049e93 5700 kvm_pfn_t pfn;
a6f177ef 5701
991eebf9
GN		 5702 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5703 return false;
5704
95b3cf69
XG		 5705 if (!vcpu->arch.mmu.direct_map) {
5706 /*
5707 * Write permission should be allowed since only
5708 * write access need to be emulated.
5709 */
5710 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5711
95b3cf69
XG		 5712 /*
5713 * If the mapping is invalid in guest, let cpu retry
5714 * it to generate fault.
5715 */
5716 if (gpa == UNMAPPED_GVA)
5717 return true;
5718 }
a6f177ef 5719
8e3d9d06
XG		 5720 /*
5721 * Do not retry the unhandleable instruction if it faults on the
5722 * readonly host memory, otherwise it will goto a infinite loop:
5723 * retry instruction -> write #PF -> emulation fail -> retry
5724 * instruction -> ...
5725 */
5726 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5727
5728 /*
5729 * If the instruction failed on the error pfn, it can not be fixed,
5730 * report the error to userspace.
5731 */
5732 if (is_error_noslot_pfn(pfn))
5733 return false;
5734
5735 kvm_release_pfn_clean(pfn);
5736
5737 /* The instructions are well-emulated on direct mmu. */
5738 if (vcpu->arch.mmu.direct_map) {
5739 unsigned int indirect_shadow_pages;
5740
5741 spin_lock(&vcpu->kvm->mmu_lock);
5742 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5743 spin_unlock(&vcpu->kvm->mmu_lock);
5744
5745 if (indirect_shadow_pages)
5746 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5747
a6f177ef 5748 return true;
8e3d9d06 5749 }
a6f177ef 5750
95b3cf69
XG		 5751 /*
5752 * if emulation was due to access to shadowed page table
5753 * and it failed try to unshadow page and re-enter the
5754 * guest to let CPU execute the instruction.
5755 */
5756 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5757
5758 /*
5759 * If the access faults on its page table, it can not
5760 * be fixed by unprotecting shadow page and it should
5761 * be reported to userspace.
5762 */
5763 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5764}
5765
1cb3f3ae
XG		 5766static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5767 unsigned long cr2, int emulation_type)
5768{
5769 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5770 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5771
5772 last_retry_eip = vcpu->arch.last_retry_eip;
5773 last_retry_addr = vcpu->arch.last_retry_addr;
5774
5775 /*
5776 * If the emulation is caused by #PF and it is non-page_table
5777 * writing instruction, it means the VM-EXIT is caused by shadow
5778 * page protected, we can zap the shadow page and retry this
5779 * instruction directly.
5780 *
5781 * Note: if the guest uses a non-page-table modifying instruction
5782 * on the PDE that points to the instruction, then we will unmap
5783 * the instruction and go to an infinite loop. So, we cache the
5784 * last retried eip and the last fault address, if we meet the eip
5785 * and the address again, we can break out of the potential infinite
5786 * loop.
5787 */
5788 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5789
5790 if (!(emulation_type & EMULTYPE_RETRY))
5791 return false;
5792
5793 if (x86_page_table_writing_insn(ctxt))
5794 return false;
5795
5796 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5797 return false;
5798
5799 vcpu->arch.last_retry_eip = ctxt->eip;
5800 vcpu->arch.last_retry_addr = cr2;
5801
5802 if (!vcpu->arch.mmu.direct_map)
5803 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5804
22368028 5805 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5806
5807 return true;
5808}
5809
716d51ab
GN		 5810static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5811static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5812
64d60670 5813static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5814{
64d60670 5815 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5816 /* This is a good place to trace that we are exiting SMM. */
5817 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5818
c43203ca
PB		 5819 /* Process a latched INIT or SMI, if any. */
5820 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5821 }
699023e2
PB		 5822
5823 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5824}
5825
5826static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5827{
5828 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5829
a584539b 5830 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5831
5832 if (changed & HF_SMM_MASK)
5833 kvm_smm_changed(vcpu);
a584539b
PB		 5834}
5835
4a1e10d5
PB		 5836static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5837 unsigned long *db)
5838{
5839 u32 dr6 = 0;
5840 int i;
5841 u32 enable, rwlen;
5842
5843 enable = dr7;
5844 rwlen = dr7 >> 16;
5845 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5846 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5847 dr6 |= (1 << i);
5848 return dr6;
5849}
5850
c8401dda 5851static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5852{
5853 struct kvm_run *kvm_run = vcpu->run;
5854
c8401dda
PB		 5855 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5856 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5857 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5858 kvm_run->debug.arch.exception = DB_VECTOR;
5859 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5860 *r = EMULATE_USER_EXIT;
5861 } else {
5862 /*
5863 * "Certain debug exceptions may clear bit 0-3. The
5864 * remaining contents of the DR6 register are never
5865 * cleared by the processor".
5866 */
5867 vcpu->arch.dr6 &= ~15;
5868 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5869 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5870 }
5871}
5872
6affcbed
KH		 5873int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5874{
5875 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5876 int r = EMULATE_DONE;
5877
5878 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5879
5880 /*
5881 * rflags is the old, "raw" value of the flags. The new value has
5882 * not been saved yet.
5883 *
5884 * This is correct even for TF set by the guest, because "the
5885 * processor will not generate this exception after the instruction
5886 * that sets the TF flag".
5887 */
5888 if (unlikely(rflags & X86_EFLAGS_TF))
5889 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5890 return r == EMULATE_DONE;
5891}
5892EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5893
4a1e10d5
PB		 5894static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5895{
4a1e10d5
PB		 5896 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5897 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5898 struct kvm_run *kvm_run = vcpu->run;
5899 unsigned long eip = kvm_get_linear_rip(vcpu);
5900 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5901 vcpu->arch.guest_debug_dr7,
5902 vcpu->arch.eff_db);
5903
5904 if (dr6 != 0) {
6f43ed01 5905 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5906 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5907 kvm_run->debug.arch.exception = DB_VECTOR;
5908 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5909 *r = EMULATE_USER_EXIT;
5910 return true;
5911 }
5912 }
5913
4161a569
NA		 5914 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5915 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5916 unsigned long eip = kvm_get_linear_rip(vcpu);
5917 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5918 vcpu->arch.dr7,
5919 vcpu->arch.db);
5920
5921 if (dr6 != 0) {
5922 vcpu->arch.dr6 &= ~15;
6f43ed01 5923 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5924 kvm_queue_exception(vcpu, DB_VECTOR);
5925 *r = EMULATE_DONE;
5926 return true;
5927 }
5928 }
5929
5930 return false;
5931}
5932
04789b66
LA		 5933static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
5934{
5935 if (ctxt->opcode_len != 1)
5936 return false;
5937
5938 switch (ctxt->b) {
5939 case 0xe4: /* IN */
5940 case 0xe5:
5941 case 0xec:
5942 case 0xed:
5943 case 0xe6: /* OUT */
5944 case 0xe7:
5945 case 0xee:
5946 case 0xef:
5947 case 0x6c: /* INS */
5948 case 0x6d:
5949 case 0x6e: /* OUTS */
5950 case 0x6f:
5951 return true;
5952 }
5953
5954 return false;
5955}
5956
51d8b661
AP		 5957int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5958 unsigned long cr2,
dc25e89e
AP		 5959 int emulation_type,
5960 void *insn,
5961 int insn_len)
bbd9b64e 5962{
95cb2295 5963 int r;
9d74191a 5964 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5965 bool writeback = true;
93c05d3e 5966 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5967
93c05d3e
XG		 5968 /*
5969 * Clear write_fault_to_shadow_pgtable here to ensure it is
5970 * never reused.
5971 */
5972 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5973 kvm_clear_exception_queue(vcpu);
8d7d8102 5974
571008da 5975 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5976 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5977
5978 /*
5979 * We will reenter on the same instruction since
5980 * we do not set complete_userspace_io. This does not
5981 * handle watchpoints yet, those would be handled in
5982 * the emulate_ops.
5983 */
d391f120
VK		 5984 if (!(emulation_type & EMULTYPE_SKIP) &&
5985 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 5986 return r;
5987
9d74191a
TY		 5988 ctxt->interruptibility = 0;
5989 ctxt->have_exception = false;
e0ad0b47 5990 ctxt->exception.vector = -1;
9d74191a 5991 ctxt->perm_ok = false;
bbd9b64e 5992
b51e974f 5993 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5994
9d74191a 5995 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5996
e46479f8 5997 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5998 ++vcpu->stat.insn_emulation;
1d2887e2 5999 if (r != EMULATION_OK) {
4005996e
AK		 6000 if (emulation_type & EMULTYPE_TRAP_UD)
6001 return EMULATE_FAIL;
991eebf9
GN		 6002 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6003 emulation_type))
bbd9b64e 6004 return EMULATE_DONE;
6ea6e843
PB		 6005 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6006 return EMULATE_DONE;
6d77dbfc
GN		 6007 if (emulation_type & EMULTYPE_SKIP)
6008 return EMULATE_FAIL;
e2366171 6009 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6010 }
6011 }
6012
04789b66
LA		 6013 if ((emulation_type & EMULTYPE_VMWARE) &&
6014 !is_vmware_backdoor_opcode(ctxt))
6015 return EMULATE_FAIL;
6016
ba8afb6b 6017 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6018 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6019 if (ctxt->eflags & X86_EFLAGS_RF)
6020 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6021 return EMULATE_DONE;
6022 }
6023
1cb3f3ae
XG		 6024 if (retry_instruction(ctxt, cr2, emulation_type))
6025 return EMULATE_DONE;
6026
7ae441ea 6027 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6028 changes registers values during IO operation */
7ae441ea
GN		 6029 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6030 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6031 emulator_invalidate_register_cache(ctxt);
7ae441ea 6032 }
4d2179e1 6033
5cd21917 6034restart:
0f89b207
TL		 6035 /* Save the faulting GPA (cr2) in the address field */
6036 ctxt->exception.address = cr2;
6037
9d74191a 6038 r = x86_emulate_insn(ctxt);
bbd9b64e 6039
775fde86
JR		 6040 if (r == EMULATION_INTERCEPTED)
6041 return EMULATE_DONE;
6042
d2ddd1c4 6043 if (r == EMULATION_FAILED) {
991eebf9
GN		 6044 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6045 emulation_type))
c3cd7ffa
GN		 6046 return EMULATE_DONE;
6047
e2366171 6048 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6049 }
6050
9d74191a 6051 if (ctxt->have_exception) {
d2ddd1c4 6052 r = EMULATE_DONE;
ef54bcfe
PB		 6053 if (inject_emulated_exception(vcpu))
6054 return r;
d2ddd1c4 6055 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6056 if (!vcpu->arch.pio.in) {
6057 /* FIXME: return into emulator if single-stepping. */
3457e419 6058 vcpu->arch.pio.count = 0;
0912c977 6059 } else {
7ae441ea 6060 writeback = false;
716d51ab
GN		 6061 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6062 }
ac0a48c3 6063 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6064 } else if (vcpu->mmio_needed) {
6065 if (!vcpu->mmio_is_write)
6066 writeback = false;
ac0a48c3 6067 r = EMULATE_USER_EXIT;
716d51ab 6068 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6069 } else if (r == EMULATION_RESTART)
5cd21917 6070 goto restart;
d2ddd1c4
GN		 6071 else
6072 r = EMULATE_DONE;
f850e2e6 6073
7ae441ea 6074 if (writeback) {
6addfc42 6075 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6076 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6077 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6078 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6079 if (r == EMULATE_DONE &&
6080 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6081 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6082 if (!ctxt->have_exception ||
6083 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6084 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6085
6086 /*
6087 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6088 * do nothing, and it will be requested again as soon as
6089 * the shadow expires. But we still need to check here,
6090 * because POPF has no interrupt shadow.
6091 */
6092 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6093 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6094 } else
6095 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6096
6097 return r;
de7d789a 6098}
51d8b661 6099EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6100
dca7f128
SC		 6101static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6102 unsigned short port)
de7d789a 6103{
cf8f70bf 6104 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6105 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6106 size, port, &val, 1);
cf8f70bf 6107 /* do not return to emulator after return from userspace */
7972995b 6108 vcpu->arch.pio.count = 0;
de7d789a
CO		 6109 return ret;
6110}
de7d789a 6111
8370c3d0
TL		 6112static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6113{
6114 unsigned long val;
6115
6116 /* We should only ever be called with arch.pio.count equal to 1 */
6117 BUG_ON(vcpu->arch.pio.count != 1);
6118
6119 /* For size less than 4 we merge, else we zero extend */
6120 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6121 : 0;
6122
6123 /*
6124 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6125 * the copy and tracing
6126 */
6127 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6128 vcpu->arch.pio.port, &val, 1);
6129 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6130
6131 return 1;
6132}
6133
dca7f128
SC		 6134static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6135 unsigned short port)
8370c3d0
TL		 6136{
6137 unsigned long val;
6138 int ret;
6139
6140 /* For size less than 4 we merge, else we zero extend */
6141 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6142
6143 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6144 &val, 1);
6145 if (ret) {
6146 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6147 return ret;
6148 }
6149
6150 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6151
6152 return 0;
6153}
dca7f128
SC		 6154
6155int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6156{
6157 int ret = kvm_skip_emulated_instruction(vcpu);
6158
6159 /*
6160 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6161 * KVM_EXIT_DEBUG here.
6162 */
6163 if (in)
6164 return kvm_fast_pio_in(vcpu, size, port) && ret;
6165 else
6166 return kvm_fast_pio_out(vcpu, size, port) && ret;
6167}
6168EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6169
251a5fd6 6170static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6171{
0a3aee0d 6172 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6173 return 0;
8cfdc000
ZA		 6174}
6175
6176static void tsc_khz_changed(void *data)
c8076604 6177{
8cfdc000
ZA		 6178 struct cpufreq_freqs *freq = data;
6179 unsigned long khz = 0;
6180
6181 if (data)
6182 khz = freq->new;
6183 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6184 khz = cpufreq_quick_get(raw_smp_processor_id());
6185 if (!khz)
6186 khz = tsc_khz;
0a3aee0d 6187 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6188}
6189
5fa4ec9c 6190#ifdef CONFIG_X86_64
0092e434
VK		 6191static void kvm_hyperv_tsc_notifier(void)
6192{
0092e434
VK		 6193 struct kvm *kvm;
6194 struct kvm_vcpu *vcpu;
6195 int cpu;
6196
6197 spin_lock(&kvm_lock);
6198 list_for_each_entry(kvm, &vm_list, vm_list)
6199 kvm_make_mclock_inprogress_request(kvm);
6200
6201 hyperv_stop_tsc_emulation();
6202
6203 /* TSC frequency always matches when on Hyper-V */
6204 for_each_present_cpu(cpu)
6205 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6206 kvm_max_guest_tsc_khz = tsc_khz;
6207
6208 list_for_each_entry(kvm, &vm_list, vm_list) {
6209 struct kvm_arch *ka = &kvm->arch;
6210
6211 spin_lock(&ka->pvclock_gtod_sync_lock);
6212
6213 pvclock_update_vm_gtod_copy(kvm);
6214
6215 kvm_for_each_vcpu(cpu, vcpu, kvm)
6216 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6217
6218 kvm_for_each_vcpu(cpu, vcpu, kvm)
6219 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6220
6221 spin_unlock(&ka->pvclock_gtod_sync_lock);
6222 }
6223 spin_unlock(&kvm_lock);
0092e434 6224}
5fa4ec9c 6225#endif
0092e434 6226
c8076604
GH		 6227static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6228 void *data)
6229{
6230 struct cpufreq_freqs *freq = data;
6231 struct kvm *kvm;
6232 struct kvm_vcpu *vcpu;
6233 int i, send_ipi = 0;
6234
8cfdc000
ZA		 6235 /*
6236 * We allow guests to temporarily run on slowing clocks,
6237 * provided we notify them after, or to run on accelerating
6238 * clocks, provided we notify them before. Thus time never
6239 * goes backwards.
6240 *
6241 * However, we have a problem. We can't atomically update
6242 * the frequency of a given CPU from this function; it is
6243 * merely a notifier, which can be called from any CPU.
6244 * Changing the TSC frequency at arbitrary points in time
6245 * requires a recomputation of local variables related to
6246 * the TSC for each VCPU. We must flag these local variables
6247 * to be updated and be sure the update takes place with the
6248 * new frequency before any guests proceed.
6249 *
6250 * Unfortunately, the combination of hotplug CPU and frequency
6251 * change creates an intractable locking scenario; the order
6252 * of when these callouts happen is undefined with respect to
6253 * CPU hotplug, and they can race with each other. As such,
6254 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6255 * undefined; you can actually have a CPU frequency change take
6256 * place in between the computation of X and the setting of the
6257 * variable. To protect against this problem, all updates of
6258 * the per_cpu tsc_khz variable are done in an interrupt
6259 * protected IPI, and all callers wishing to update the value
6260 * must wait for a synchronous IPI to complete (which is trivial
6261 * if the caller is on the CPU already). This establishes the
6262 * necessary total order on variable updates.
6263 *
6264 * Note that because a guest time update may take place
6265 * anytime after the setting of the VCPU's request bit, the
6266 * correct TSC value must be set before the request. However,
6267 * to ensure the update actually makes it to any guest which
6268 * starts running in hardware virtualization between the set
6269 * and the acquisition of the spinlock, we must also ping the
6270 * CPU after setting the request bit.
6271 *
6272 */
6273
c8076604
GH		 6274 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6275 return 0;
6276 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6277 return 0;
8cfdc000
ZA		 6278
6279 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6280
2f303b74 6281 spin_lock(&kvm_lock);
c8076604 6282 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6283 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6284 if (vcpu->cpu != freq->cpu)
6285 continue;
c285545f 6286 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6287 if (vcpu->cpu != smp_processor_id())
8cfdc000 6288 send_ipi = 1;
c8076604
GH		 6289 }
6290 }
2f303b74 6291 spin_unlock(&kvm_lock);
c8076604
GH		 6292
6293 if (freq->old < freq->new && send_ipi) {
6294 /*
6295 * We upscale the frequency. Must make the guest
6296 * doesn't see old kvmclock values while running with
6297 * the new frequency, otherwise we risk the guest sees
6298 * time go backwards.
6299 *
6300 * In case we update the frequency for another cpu
6301 * (which might be in guest context) send an interrupt
6302 * to kick the cpu out of guest context. Next time
6303 * guest context is entered kvmclock will be updated,
6304 * so the guest will not see stale values.
6305 */
8cfdc000 6306 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6307 }
6308 return 0;
6309}
6310
6311static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6312 .notifier_call = kvmclock_cpufreq_notifier
6313};
6314
251a5fd6 6315static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6316{
251a5fd6
SAS		 6317 tsc_khz_changed(NULL);
6318 return 0;
8cfdc000
ZA		 6319}
6320
b820cc0c
ZA		 6321static void kvm_timer_init(void)
6322{
c285545f 6323 max_tsc_khz = tsc_khz;
460dd42e 6324
b820cc0c 6325 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6326#ifdef CONFIG_CPU_FREQ
6327 struct cpufreq_policy policy;
758f588d
BP		 6328 int cpu;
6329
c285545f 6330 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6331 cpu = get_cpu();
6332 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6333 if (policy.cpuinfo.max_freq)
6334 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6335 put_cpu();
c285545f 6336#endif
b820cc0c
ZA		 6337 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6338 CPUFREQ_TRANSITION_NOTIFIER);
6339 }
c285545f 6340 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6341
73c1b41e 6342 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6343 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6344}
6345
ff9d07a0
ZY		 6346static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6347
f5132b01 6348int kvm_is_in_guest(void)
ff9d07a0 6349{
086c9855 6350 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6351}
6352
6353static int kvm_is_user_mode(void)
6354{
6355 int user_mode = 3;
dcf46b94 6356
086c9855
AS		 6357 if (__this_cpu_read(current_vcpu))
6358 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6359
ff9d07a0
ZY		 6360 return user_mode != 0;
6361}
6362
6363static unsigned long kvm_get_guest_ip(void)
6364{
6365 unsigned long ip = 0;
dcf46b94 6366
086c9855
AS		 6367 if (__this_cpu_read(current_vcpu))
6368 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6369
ff9d07a0
ZY		 6370 return ip;
6371}
6372
6373static struct perf_guest_info_callbacks kvm_guest_cbs = {
6374 .is_in_guest = kvm_is_in_guest,
6375 .is_user_mode = kvm_is_user_mode,
6376 .get_guest_ip = kvm_get_guest_ip,
6377};
6378
6379void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6380{
086c9855 6381 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6382}
6383EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6384
6385void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6386{
086c9855 6387 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6388}
6389EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6390
ce88decf
XG		 6391static void kvm_set_mmio_spte_mask(void)
6392{
6393 u64 mask;
6394 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6395
6396 /*
6397 * Set the reserved bits and the present bit of an paging-structure
6398 * entry to generate page fault with PFER.RSV = 1.
6399 */
885032b9 6400 /* Mask the reserved physical address bits. */
d1431483 6401 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6402
885032b9 6403 /* Set the present bit. */
ce88decf
XG		 6404 mask |= 1ull;
6405
6406#ifdef CONFIG_X86_64
6407 /*
6408 * If reserved bit is not supported, clear the present bit to disable
6409 * mmio page fault.
6410 */
6411 if (maxphyaddr == 52)
6412 mask &= ~1ull;
6413#endif
6414
dcdca5fe 6415 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6416}
6417
16e8d74d
MT		 6418#ifdef CONFIG_X86_64
6419static void pvclock_gtod_update_fn(struct work_struct *work)
6420{
d828199e
MT		 6421 struct kvm *kvm;
6422
6423 struct kvm_vcpu *vcpu;
6424 int i;
6425
2f303b74 6426 spin_lock(&kvm_lock);
d828199e
MT		 6427 list_for_each_entry(kvm, &vm_list, vm_list)
6428 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6429 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6430 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6431 spin_unlock(&kvm_lock);
16e8d74d
MT		 6432}
6433
6434static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6435
6436/*
6437 * Notification about pvclock gtod data update.
6438 */
6439static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6440 void *priv)
6441{
6442 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6443 struct timekeeper *tk = priv;
6444
6445 update_pvclock_gtod(tk);
6446
6447 /* disable master clock if host does not trust, or does not
b0c39dc6 6448 * use, TSC based clocksource.
16e8d74d 6449 */
b0c39dc6 6450 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6451 atomic_read(&kvm_guest_has_master_clock) != 0)
6452 queue_work(system_long_wq, &pvclock_gtod_work);
6453
6454 return 0;
6455}
6456
6457static struct notifier_block pvclock_gtod_notifier = {
6458 .notifier_call = pvclock_gtod_notify,
6459};
6460#endif
6461
f8c16bba 6462int kvm_arch_init(void *opaque)
043405e1 6463{
b820cc0c 6464 int r;
6b61edf7 6465 struct kvm_x86_ops *ops = opaque;
f8c16bba 6466
f8c16bba
ZX		 6467 if (kvm_x86_ops) {
6468 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6469 r = -EEXIST;
6470 goto out;
f8c16bba
ZX		 6471 }
6472
6473 if (!ops->cpu_has_kvm_support()) {
6474 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6475 r = -EOPNOTSUPP;
6476 goto out;
f8c16bba
ZX		 6477 }
6478 if (ops->disabled_by_bios()) {
6479 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6480 r = -EOPNOTSUPP;
6481 goto out;
f8c16bba
ZX		 6482 }
6483
013f6a5d
MT		 6484 r = -ENOMEM;
6485 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6486 if (!shared_msrs) {
6487 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6488 goto out;
6489 }
6490
97db56ce
AK		 6491 r = kvm_mmu_module_init();
6492 if (r)
013f6a5d 6493 goto out_free_percpu;
97db56ce 6494
ce88decf 6495 kvm_set_mmio_spte_mask();
97db56ce 6496
f8c16bba 6497 kvm_x86_ops = ops;
920c8377 6498
7b52345e 6499 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6500 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6501 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6502 kvm_timer_init();
c8076604 6503
ff9d07a0
ZY		 6504 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6505
d366bf7e 6506 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6507 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6508
c5cc421b 6509 kvm_lapic_init();
16e8d74d
MT		 6510#ifdef CONFIG_X86_64
6511 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6512
5fa4ec9c 6513 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6514 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6515#endif
6516
f8c16bba 6517 return 0;
56c6d28a 6518
013f6a5d
MT		 6519out_free_percpu:
6520 free_percpu(shared_msrs);
56c6d28a 6521out:
56c6d28a 6522 return r;
043405e1 6523}
8776e519 6524
f8c16bba
ZX		 6525void kvm_arch_exit(void)
6526{
0092e434 6527#ifdef CONFIG_X86_64
5fa4ec9c 6528 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6529 clear_hv_tscchange_cb();
6530#endif
cef84c30 6531 kvm_lapic_exit();
ff9d07a0
ZY		 6532 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6533
888d256e
JK		 6534 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6535 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6536 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6537 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6538#ifdef CONFIG_X86_64
6539 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6540#endif
f8c16bba 6541 kvm_x86_ops = NULL;
56c6d28a 6542 kvm_mmu_module_exit();
013f6a5d 6543 free_percpu(shared_msrs);
56c6d28a 6544}
f8c16bba 6545
5cb56059 6546int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6547{
6548 ++vcpu->stat.halt_exits;
35754c98 6549 if (lapic_in_kernel(vcpu)) {
a4535290 6550 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6551 return 1;
6552 } else {
6553 vcpu->run->exit_reason = KVM_EXIT_HLT;
6554 return 0;
6555 }
6556}
5cb56059
JS		 6557EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6558
6559int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6560{
6affcbed
KH		 6561 int ret = kvm_skip_emulated_instruction(vcpu);
6562 /*
6563 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6564 * KVM_EXIT_DEBUG here.
6565 */
6566 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6567}
8776e519
HB		 6568EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6569
8ef81a9a 6570#ifdef CONFIG_X86_64
55dd00a7
MT		 6571static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6572 unsigned long clock_type)
6573{
6574 struct kvm_clock_pairing clock_pairing;
6575 struct timespec ts;
80fbd89c 6576 u64 cycle;
55dd00a7
MT		 6577 int ret;
6578
6579 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6580 return -KVM_EOPNOTSUPP;
6581
6582 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6583 return -KVM_EOPNOTSUPP;
6584
6585 clock_pairing.sec = ts.tv_sec;
6586 clock_pairing.nsec = ts.tv_nsec;
6587 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6588 clock_pairing.flags = 0;
6589
6590 ret = 0;
6591 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6592 sizeof(struct kvm_clock_pairing)))
6593 ret = -KVM_EFAULT;
6594
6595 return ret;
6596}
8ef81a9a 6597#endif
55dd00a7 6598
6aef266c
SV		 6599/*
6600 * kvm_pv_kick_cpu_op: Kick a vcpu.
6601 *
6602 * @apicid - apicid of vcpu to be kicked.
6603 */
6604static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6605{
24d2166b 6606 struct kvm_lapic_irq lapic_irq;
6aef266c 6607
24d2166b
R		 6608 lapic_irq.shorthand = 0;
6609 lapic_irq.dest_mode = 0;
ebd28fcb 6610 lapic_irq.level = 0;
24d2166b 6611 lapic_irq.dest_id = apicid;
93bbf0b8 6612 lapic_irq.msi_redir_hint = false;
6aef266c 6613
24d2166b 6614 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6615 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6616}
6617
d62caabb
AS		 6618void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6619{
6620 vcpu->arch.apicv_active = false;
6621 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6622}
6623
8776e519
HB		 6624int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6625{
6626 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6627 int op_64_bit, r;
8776e519 6628
6affcbed 6629 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6630
55cd8e5a
GN		 6631 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6632 return kvm_hv_hypercall(vcpu);
6633
5fdbf976
MT		 6634 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6635 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6636 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6637 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6638 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6639
229456fc 6640 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6641
a449c7aa
NA		 6642 op_64_bit = is_64_bit_mode(vcpu);
6643 if (!op_64_bit) {
8776e519
HB		 6644 nr &= 0xFFFFFFFF;
6645 a0 &= 0xFFFFFFFF;
6646 a1 &= 0xFFFFFFFF;
6647 a2 &= 0xFFFFFFFF;
6648 a3 &= 0xFFFFFFFF;
6649 }
6650
07708c4a
JK		 6651 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6652 ret = -KVM_EPERM;
6653 goto out;
6654 }
6655
8776e519 6656 switch (nr) {
b93463aa
AK		 6657 case KVM_HC_VAPIC_POLL_IRQ:
6658 ret = 0;
6659 break;
6aef266c
SV		 6660 case KVM_HC_KICK_CPU:
6661 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6662 ret = 0;
6663 break;
8ef81a9a 6664#ifdef CONFIG_X86_64
55dd00a7
MT		 6665 case KVM_HC_CLOCK_PAIRING:
6666 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6667 break;
8ef81a9a 6668#endif
8776e519
HB		 6669 default:
6670 ret = -KVM_ENOSYS;
6671 break;
6672 }
07708c4a 6673out:
a449c7aa
NA		 6674 if (!op_64_bit)
6675 ret = (u32)ret;
5fdbf976 6676 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6677 ++vcpu->stat.hypercalls;
2f333bcb 6678 return r;
8776e519
HB		 6679}
6680EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6681
b6785def 6682static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6683{
d6aa1000 6684 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6685 char instruction[3];
5fdbf976 6686 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6687
8776e519 6688 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6689
ce2e852e
DV		 6690 return emulator_write_emulated(ctxt, rip, instruction, 3,
6691 &ctxt->exception);
8776e519
HB		 6692}
6693
851ba692 6694static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6695{
782d422b
MG		 6696 return vcpu->run->request_interrupt_window &&
6697 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6698}
6699
851ba692 6700static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6701{
851ba692
AK		 6702 struct kvm_run *kvm_run = vcpu->run;
6703
91586a3b 6704 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6705 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6706 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6707 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6708 kvm_run->ready_for_interrupt_injection =
6709 pic_in_kernel(vcpu->kvm) ||
782d422b 6710 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6711}
6712
95ba8273
GN		 6713static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6714{
6715 int max_irr, tpr;
6716
6717 if (!kvm_x86_ops->update_cr8_intercept)
6718 return;
6719
bce87cce 6720 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6721 return;
6722
d62caabb
AS		 6723 if (vcpu->arch.apicv_active)
6724 return;
6725
8db3baa2
GN		 6726 if (!vcpu->arch.apic->vapic_addr)
6727 max_irr = kvm_lapic_find_highest_irr(vcpu);
6728 else
6729 max_irr = -1;
95ba8273
GN		 6730
6731 if (max_irr != -1)
6732 max_irr >>= 4;
6733
6734 tpr = kvm_lapic_get_cr8(vcpu);
6735
6736 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6737}
6738
b6b8a145 6739static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6740{
b6b8a145
JK		 6741 int r;
6742
95ba8273 6743 /* try to reinject previous events if any */
664f8e26
WL		 6744 if (vcpu->arch.exception.injected) {
6745 kvm_x86_ops->queue_exception(vcpu);
6746 return 0;
6747 }
6748
6749 /*
6750 * Exceptions must be injected immediately, or the exception
6751 * frame will have the address of the NMI or interrupt handler.
6752 */
6753 if (!vcpu->arch.exception.pending) {
6754 if (vcpu->arch.nmi_injected) {
6755 kvm_x86_ops->set_nmi(vcpu);
6756 return 0;
6757 }
6758
6759 if (vcpu->arch.interrupt.pending) {
6760 kvm_x86_ops->set_irq(vcpu);
6761 return 0;
6762 }
6763 }
6764
6765 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6766 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6767 if (r != 0)
6768 return r;
6769 }
6770
6771 /* try to inject new event if pending */
b59bb7bd 6772 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6773 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6774 vcpu->arch.exception.has_error_code,
6775 vcpu->arch.exception.error_code);
d6e8c854 6776
664f8e26
WL		 6777 vcpu->arch.exception.pending = false;
6778 vcpu->arch.exception.injected = true;
6779
d6e8c854
NA		 6780 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6781 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6782 X86_EFLAGS_RF);
6783
6bdf0662
NA		 6784 if (vcpu->arch.exception.nr == DB_VECTOR &&
6785 (vcpu->arch.dr7 & DR7_GD)) {
6786 vcpu->arch.dr7 &= ~DR7_GD;
6787 kvm_update_dr7(vcpu);
6788 }
6789
cfcd20e5 6790 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6791 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6792 vcpu->arch.smi_pending = false;
52797bf9 6793 ++vcpu->arch.smi_count;
ee2cd4b7 6794 enter_smm(vcpu);
c43203ca 6795 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6796 --vcpu->arch.nmi_pending;
6797 vcpu->arch.nmi_injected = true;
6798 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6799 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6800 /*
6801 * Because interrupts can be injected asynchronously, we are
6802 * calling check_nested_events again here to avoid a race condition.
6803 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6804 * proposal and current concerns. Perhaps we should be setting
6805 * KVM_REQ_EVENT only on certain events and not unconditionally?
6806 */
6807 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6808 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6809 if (r != 0)
6810 return r;
6811 }
95ba8273 6812 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6813 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6814 false);
6815 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6816 }
6817 }
ee2cd4b7 6818
b6b8a145 6819 return 0;
95ba8273
GN		 6820}
6821
7460fb4a
AK		 6822static void process_nmi(struct kvm_vcpu *vcpu)
6823{
6824 unsigned limit = 2;
6825
6826 /*
6827 * x86 is limited to one NMI running, and one NMI pending after it.
6828 * If an NMI is already in progress, limit further NMIs to just one.
6829 * Otherwise, allow two (and we'll inject the first one immediately).
6830 */
6831 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6832 limit = 1;
6833
6834 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6835 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6836 kvm_make_request(KVM_REQ_EVENT, vcpu);
6837}
6838
ee2cd4b7 6839static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6840{
6841 u32 flags = 0;
6842 flags |= seg->g << 23;
6843 flags |= seg->db << 22;
6844 flags |= seg->l << 21;
6845 flags |= seg->avl << 20;
6846 flags |= seg->present << 15;
6847 flags |= seg->dpl << 13;
6848 flags |= seg->s << 12;
6849 flags |= seg->type << 8;
6850 return flags;
6851}
6852
ee2cd4b7 6853static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6854{
6855 struct kvm_segment seg;
6856 int offset;
6857
6858 kvm_get_segment(vcpu, &seg, n);
6859 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6860
6861 if (n < 3)
6862 offset = 0x7f84 + n * 12;
6863 else
6864 offset = 0x7f2c + (n - 3) * 12;
6865
6866 put_smstate(u32, buf, offset + 8, seg.base);
6867 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6868 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6869}
6870
efbb288a 6871#ifdef CONFIG_X86_64
ee2cd4b7 6872static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6873{
6874 struct kvm_segment seg;
6875 int offset;
6876 u16 flags;
6877
6878 kvm_get_segment(vcpu, &seg, n);
6879 offset = 0x7e00 + n * 16;
6880
ee2cd4b7 6881 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6882 put_smstate(u16, buf, offset, seg.selector);
6883 put_smstate(u16, buf, offset + 2, flags);
6884 put_smstate(u32, buf, offset + 4, seg.limit);
6885 put_smstate(u64, buf, offset + 8, seg.base);
6886}
efbb288a 6887#endif
660a5d51 6888
ee2cd4b7 6889static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6890{
6891 struct desc_ptr dt;
6892 struct kvm_segment seg;
6893 unsigned long val;
6894 int i;
6895
6896 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6897 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6898 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6899 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6900
6901 for (i = 0; i < 8; i++)
6902 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6903
6904 kvm_get_dr(vcpu, 6, &val);
6905 put_smstate(u32, buf, 0x7fcc, (u32)val);
6906 kvm_get_dr(vcpu, 7, &val);
6907 put_smstate(u32, buf, 0x7fc8, (u32)val);
6908
6909 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6910 put_smstate(u32, buf, 0x7fc4, seg.selector);
6911 put_smstate(u32, buf, 0x7f64, seg.base);
6912 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6913 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6914
6915 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6916 put_smstate(u32, buf, 0x7fc0, seg.selector);
6917 put_smstate(u32, buf, 0x7f80, seg.base);
6918 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6919 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6920
6921 kvm_x86_ops->get_gdt(vcpu, &dt);
6922 put_smstate(u32, buf, 0x7f74, dt.address);
6923 put_smstate(u32, buf, 0x7f70, dt.size);
6924
6925 kvm_x86_ops->get_idt(vcpu, &dt);
6926 put_smstate(u32, buf, 0x7f58, dt.address);
6927 put_smstate(u32, buf, 0x7f54, dt.size);
6928
6929 for (i = 0; i < 6; i++)
ee2cd4b7 6930 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6931
6932 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6933
6934 /* revision id */
6935 put_smstate(u32, buf, 0x7efc, 0x00020000);
6936 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6937}
6938
ee2cd4b7 6939static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6940{
6941#ifdef CONFIG_X86_64
6942 struct desc_ptr dt;
6943 struct kvm_segment seg;
6944 unsigned long val;
6945 int i;
6946
6947 for (i = 0; i < 16; i++)
6948 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6949
6950 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6951 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6952
6953 kvm_get_dr(vcpu, 6, &val);
6954 put_smstate(u64, buf, 0x7f68, val);
6955 kvm_get_dr(vcpu, 7, &val);
6956 put_smstate(u64, buf, 0x7f60, val);
6957
6958 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6959 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6960 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6961
6962 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6963
6964 /* revision id */
6965 put_smstate(u32, buf, 0x7efc, 0x00020064);
6966
6967 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6968
6969 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6970 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6971 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6972 put_smstate(u32, buf, 0x7e94, seg.limit);
6973 put_smstate(u64, buf, 0x7e98, seg.base);
6974
6975 kvm_x86_ops->get_idt(vcpu, &dt);
6976 put_smstate(u32, buf, 0x7e84, dt.size);
6977 put_smstate(u64, buf, 0x7e88, dt.address);
6978
6979 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6980 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6981 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6982 put_smstate(u32, buf, 0x7e74, seg.limit);
6983 put_smstate(u64, buf, 0x7e78, seg.base);
6984
6985 kvm_x86_ops->get_gdt(vcpu, &dt);
6986 put_smstate(u32, buf, 0x7e64, dt.size);
6987 put_smstate(u64, buf, 0x7e68, dt.address);
6988
6989 for (i = 0; i < 6; i++)
ee2cd4b7 6990 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6991#else
6992 WARN_ON_ONCE(1);
6993#endif
6994}
6995
ee2cd4b7 6996static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6997{
660a5d51 6998 struct kvm_segment cs, ds;
18c3626e 6999 struct desc_ptr dt;
660a5d51
PB		 7000 char buf[512];
7001 u32 cr0;
7002
660a5d51 7003 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7004 memset(buf, 0, 512);
d6321d49 7005 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7006 enter_smm_save_state_64(vcpu, buf);
660a5d51 7007 else
ee2cd4b7 7008 enter_smm_save_state_32(vcpu, buf);
660a5d51 7009
0234bf88
LP		 7010 /*
7011 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7012 * vCPU state (e.g. leave guest mode) after we've saved the state into
7013 * the SMM state-save area.
7014 */
7015 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7016
7017 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7018 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7019
7020 if (kvm_x86_ops->get_nmi_mask(vcpu))
7021 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7022 else
7023 kvm_x86_ops->set_nmi_mask(vcpu, true);
7024
7025 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7026 kvm_rip_write(vcpu, 0x8000);
7027
7028 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7029 kvm_x86_ops->set_cr0(vcpu, cr0);
7030 vcpu->arch.cr0 = cr0;
7031
7032 kvm_x86_ops->set_cr4(vcpu, 0);
7033
18c3626e
PB		 7034 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7035 dt.address = dt.size = 0;
7036 kvm_x86_ops->set_idt(vcpu, &dt);
7037
660a5d51
PB		 7038 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7039
7040 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7041 cs.base = vcpu->arch.smbase;
7042
7043 ds.selector = 0;
7044 ds.base = 0;
7045
7046 cs.limit = ds.limit = 0xffffffff;
7047 cs.type = ds.type = 0x3;
7048 cs.dpl = ds.dpl = 0;
7049 cs.db = ds.db = 0;
7050 cs.s = ds.s = 1;
7051 cs.l = ds.l = 0;
7052 cs.g = ds.g = 1;
7053 cs.avl = ds.avl = 0;
7054 cs.present = ds.present = 1;
7055 cs.unusable = ds.unusable = 0;
7056 cs.padding = ds.padding = 0;
7057
7058 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7059 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7060 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7061 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7062 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7063 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7064
d6321d49 7065 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7066 kvm_x86_ops->set_efer(vcpu, 0);
7067
7068 kvm_update_cpuid(vcpu);
7069 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7070}
7071
ee2cd4b7 7072static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7073{
7074 vcpu->arch.smi_pending = true;
7075 kvm_make_request(KVM_REQ_EVENT, vcpu);
7076}
7077
2860c4b1
PB		 7078void kvm_make_scan_ioapic_request(struct kvm *kvm)
7079{
7080 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7081}
7082
3d81bc7e 7083static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7084{
5c919412
AS		 7085 u64 eoi_exit_bitmap[4];
7086
3d81bc7e
YZ		 7087 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7088 return;
c7c9c56c 7089
6308630b 7090 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7091
b053b2ae 7092 if (irqchip_split(vcpu->kvm))
6308630b 7093 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7094 else {
fa59cc00 7095 if (vcpu->arch.apicv_active)
d62caabb 7096 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7097 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7098 }
5c919412
AS		 7099 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7100 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7101 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7102}
7103
b1394e74
RK		 7104void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7105 unsigned long start, unsigned long end)
7106{
7107 unsigned long apic_address;
7108
7109 /*
7110 * The physical address of apic access page is stored in the VMCS.
7111 * Update it when it becomes invalid.
7112 */
7113 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7114 if (start <= apic_address && apic_address < end)
7115 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7116}
7117
4256f43f
TC		 7118void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7119{
c24ae0dc
TC		 7120 struct page *page = NULL;
7121
35754c98 7122 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7123 return;
7124
4256f43f
TC		 7125 if (!kvm_x86_ops->set_apic_access_page_addr)
7126 return;
7127
c24ae0dc 7128 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7129 if (is_error_page(page))
7130 return;
c24ae0dc
TC		 7131 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7132
7133 /*
7134 * Do not pin apic access page in memory, the MMU notifier
7135 * will call us again if it is migrated or swapped out.
7136 */
7137 put_page(page);
4256f43f
TC		 7138}
7139EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7140
9357d939 7141/*
362c698f 7142 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7143 * exiting to the userspace. Otherwise, the value will be returned to the
7144 * userspace.
7145 */
851ba692 7146static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7147{
7148 int r;
62a193ed
MG		 7149 bool req_int_win =
7150 dm_request_for_irq_injection(vcpu) &&
7151 kvm_cpu_accept_dm_intr(vcpu);
7152
730dca42 7153 bool req_immediate_exit = false;
b6c7a5dc 7154
2fa6e1e1 7155 if (kvm_request_pending(vcpu)) {
a8eeb04a 7156 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7157 kvm_mmu_unload(vcpu);
a8eeb04a 7158 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7159 __kvm_migrate_timers(vcpu);
d828199e
MT		 7160 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7161 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7162 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7163 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7164 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7165 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7166 if (unlikely(r))
7167 goto out;
7168 }
a8eeb04a 7169 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7170 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7171 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7172 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7173 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7174 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7175 r = 0;
7176 goto out;
7177 }
a8eeb04a 7178 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7179 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7180 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7181 r = 0;
7182 goto out;
7183 }
af585b92
GN		 7184 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7185 /* Page is swapped out. Do synthetic halt */
7186 vcpu->arch.apf.halted = true;
7187 r = 1;
7188 goto out;
7189 }
c9aaa895
GC		 7190 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7191 record_steal_time(vcpu);
64d60670
PB		 7192 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7193 process_smi(vcpu);
7460fb4a
AK		 7194 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7195 process_nmi(vcpu);
f5132b01 7196 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7197 kvm_pmu_handle_event(vcpu);
f5132b01 7198 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7199 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7200 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7201 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7202 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7203 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7204 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7205 vcpu->run->eoi.vector =
7206 vcpu->arch.pending_ioapic_eoi;
7207 r = 0;
7208 goto out;
7209 }
7210 }
3d81bc7e
YZ		 7211 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7212 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 7213 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7214 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7215 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7216 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7217 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7218 r = 0;
7219 goto out;
7220 }
e516cebb
AS		 7221 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7222 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7223 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7224 r = 0;
7225 goto out;
7226 }
db397571
AS		 7227 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7228 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7229 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7230 r = 0;
7231 goto out;
7232 }
f3b138c5
AS		 7233
7234 /*
7235 * KVM_REQ_HV_STIMER has to be processed after
7236 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7237 * depend on the guest clock being up-to-date
7238 */
1f4b34f8
AS		 7239 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7240 kvm_hv_process_stimers(vcpu);
2f52d58c 7241 }
b93463aa 7242
b463a6f7 7243 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7244 ++vcpu->stat.req_event;
66450a21
JK		 7245 kvm_apic_accept_events(vcpu);
7246 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7247 r = 1;
7248 goto out;
7249 }
7250
b6b8a145
JK		 7251 if (inject_pending_event(vcpu, req_int_win) != 0)
7252 req_immediate_exit = true;
321c5658 7253 else {
cc3d967f 7254 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7255 *
cc3d967f
LP		 7256 * SMIs have three cases:
7257 * 1) They can be nested, and then there is nothing to
7258 * do here because RSM will cause a vmexit anyway.
7259 * 2) There is an ISA-specific reason why SMI cannot be
7260 * injected, and the moment when this changes can be
7261 * intercepted.
7262 * 3) Or the SMI can be pending because
7263 * inject_pending_event has completed the injection
7264 * of an IRQ or NMI from the previous vmexit, and
7265 * then we request an immediate exit to inject the
7266 * SMI.
c43203ca
PB		 7267 */
7268 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7269 if (!kvm_x86_ops->enable_smi_window(vcpu))
7270 req_immediate_exit = true;
321c5658
YS		 7271 if (vcpu->arch.nmi_pending)
7272 kvm_x86_ops->enable_nmi_window(vcpu);
7273 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7274 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7275 WARN_ON(vcpu->arch.exception.pending);
321c5658 7276 }
b463a6f7
AK		 7277
7278 if (kvm_lapic_enabled(vcpu)) {
7279 update_cr8_intercept(vcpu);
7280 kvm_lapic_sync_to_vapic(vcpu);
7281 }
7282 }
7283
d8368af8
AK		 7284 r = kvm_mmu_reload(vcpu);
7285 if (unlikely(r)) {
d905c069 7286 goto cancel_injection;
d8368af8
AK		 7287 }
7288
b6c7a5dc
HB		 7289 preempt_disable();
7290
7291 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7292
7293 /*
7294 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7295 * IPI are then delayed after guest entry, which ensures that they
7296 * result in virtual interrupt delivery.
7297 */
7298 local_irq_disable();
6b7e2d09
XG		 7299 vcpu->mode = IN_GUEST_MODE;
7300
01b71917
MT		 7301 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7302
0f127d12 7303 /*
b95234c8 7304 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7305 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7306 *
7307 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7308 * pairs with the memory barrier implicit in pi_test_and_set_on
7309 * (see vmx_deliver_posted_interrupt).
7310 *
7311 * 3) This also orders the write to mode from any reads to the page
7312 * tables done while the VCPU is running. Please see the comment
7313 * in kvm_flush_remote_tlbs.
6b7e2d09 7314 */
01b71917 7315 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7316
b95234c8
PB		 7317 /*
7318 * This handles the case where a posted interrupt was
7319 * notified with kvm_vcpu_kick.
7320 */
fa59cc00
LA		 7321 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7322 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7323
2fa6e1e1 7324 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7325 || need_resched() || signal_pending(current)) {
6b7e2d09 7326 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7327 smp_wmb();
6c142801
AK		 7328 local_irq_enable();
7329 preempt_enable();
01b71917 7330 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7331 r = 1;
d905c069 7332 goto cancel_injection;
6c142801
AK		 7333 }
7334
fc5b7f3b
DM		 7335 kvm_load_guest_xcr0(vcpu);
7336
c43203ca
PB		 7337 if (req_immediate_exit) {
7338 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7339 smp_send_reschedule(vcpu->cpu);
c43203ca 7340 }
d6185f20 7341
8b89fe1f 7342 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7343 if (lapic_timer_advance_ns)
7344 wait_lapic_expire(vcpu);
6edaa530 7345 guest_enter_irqoff();
b6c7a5dc 7346
42dbaa5a 7347 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7348 set_debugreg(0, 7);
7349 set_debugreg(vcpu->arch.eff_db[0], 0);
7350 set_debugreg(vcpu->arch.eff_db[1], 1);
7351 set_debugreg(vcpu->arch.eff_db[2], 2);
7352 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7353 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7354 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7355 }
b6c7a5dc 7356
851ba692 7357 kvm_x86_ops->run(vcpu);
b6c7a5dc 7358
c77fb5fe
PB		 7359 /*
7360 * Do this here before restoring debug registers on the host. And
7361 * since we do this before handling the vmexit, a DR access vmexit
7362 * can (a) read the correct value of the debug registers, (b) set
7363 * KVM_DEBUGREG_WONT_EXIT again.
7364 */
7365 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7366 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7367 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7368 kvm_update_dr0123(vcpu);
7369 kvm_update_dr6(vcpu);
7370 kvm_update_dr7(vcpu);
7371 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7372 }
7373
24f1e32c
FW		 7374 /*
7375 * If the guest has used debug registers, at least dr7
7376 * will be disabled while returning to the host.
7377 * If we don't have active breakpoints in the host, we don't
7378 * care about the messed up debug address registers. But if
7379 * we have some of them active, restore the old state.
7380 */
59d8eb53 7381 if (hw_breakpoint_active())
24f1e32c 7382 hw_breakpoint_restore();
42dbaa5a 7383
4ba76538 7384 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7385
6b7e2d09 7386 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7387 smp_wmb();
a547c6db 7388
fc5b7f3b
DM		 7389 kvm_put_guest_xcr0(vcpu);
7390
a547c6db 7391 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7392
7393 ++vcpu->stat.exits;
7394
f2485b3e 7395 guest_exit_irqoff();
b6c7a5dc 7396
f2485b3e 7397 local_irq_enable();
b6c7a5dc
HB		 7398 preempt_enable();
7399
f656ce01 7400 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7401
b6c7a5dc
HB		 7402 /*
7403 * Profile KVM exit RIPs:
7404 */
7405 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7406 unsigned long rip = kvm_rip_read(vcpu);
7407 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7408 }
7409
cc578287
ZA		 7410 if (unlikely(vcpu->arch.tsc_always_catchup))
7411 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7412
5cfb1d5a
MT		 7413 if (vcpu->arch.apic_attention)
7414 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7415
618232e2 7416 vcpu->arch.gpa_available = false;
851ba692 7417 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7418 return r;
7419
7420cancel_injection:
7421 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7422 if (unlikely(vcpu->arch.apic_attention))
7423 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7424out:
7425 return r;
7426}
b6c7a5dc 7427
362c698f
PB		 7428static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7429{
bf9f6ac8
FW		 7430 if (!kvm_arch_vcpu_runnable(vcpu) &&
7431 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7432 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7433 kvm_vcpu_block(vcpu);
7434 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7435
7436 if (kvm_x86_ops->post_block)
7437 kvm_x86_ops->post_block(vcpu);
7438
9c8fd1ba
PB		 7439 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7440 return 1;
7441 }
362c698f
PB		 7442
7443 kvm_apic_accept_events(vcpu);
7444 switch(vcpu->arch.mp_state) {
7445 case KVM_MP_STATE_HALTED:
7446 vcpu->arch.pv.pv_unhalted = false;
7447 vcpu->arch.mp_state =
7448 KVM_MP_STATE_RUNNABLE;
7449 case KVM_MP_STATE_RUNNABLE:
7450 vcpu->arch.apf.halted = false;
7451 break;
7452 case KVM_MP_STATE_INIT_RECEIVED:
7453 break;
7454 default:
7455 return -EINTR;
7456 break;
7457 }
7458 return 1;
7459}
09cec754 7460
5d9bc648
PB		 7461static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7462{
0ad3bed6
PB		 7463 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7464 kvm_x86_ops->check_nested_events(vcpu, false);
7465
5d9bc648
PB		 7466 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7467 !vcpu->arch.apf.halted);
7468}
7469
362c698f 7470static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7471{
7472 int r;
f656ce01 7473 struct kvm *kvm = vcpu->kvm;
d7690175 7474
f656ce01 7475 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7476
362c698f 7477 for (;;) {
58f800d5 7478 if (kvm_vcpu_running(vcpu)) {
851ba692 7479 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7480 } else {
362c698f 7481 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7482 }
7483
09cec754
GN		 7484 if (r <= 0)
7485 break;
7486
72875d8a 7487 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7488 if (kvm_cpu_has_pending_timer(vcpu))
7489 kvm_inject_pending_timer_irqs(vcpu);
7490
782d422b
MG		 7491 if (dm_request_for_irq_injection(vcpu) &&
7492 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7493 r = 0;
7494 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7495 ++vcpu->stat.request_irq_exits;
362c698f 7496 break;
09cec754 7497 }
af585b92
GN		 7498
7499 kvm_check_async_pf_completion(vcpu);
7500
09cec754
GN		 7501 if (signal_pending(current)) {
7502 r = -EINTR;
851ba692 7503 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7504 ++vcpu->stat.signal_exits;
362c698f 7505 break;
09cec754
GN		 7506 }
7507 if (need_resched()) {
f656ce01 7508 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7509 cond_resched();
f656ce01 7510 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7511 }
b6c7a5dc
HB		 7512 }
7513
f656ce01 7514 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7515
7516 return r;
7517}
7518
716d51ab
GN		 7519static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7520{
7521 int r;
7522 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7523 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7524 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7525 if (r != EMULATE_DONE)
7526 return 0;
7527 return 1;
7528}
7529
7530static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7531{
7532 BUG_ON(!vcpu->arch.pio.count);
7533
7534 return complete_emulated_io(vcpu);
7535}
7536
f78146b0
AK		 7537/*
7538 * Implements the following, as a state machine:
7539 *
7540 * read:
7541 * for each fragment
87da7e66
XG		 7542 * for each mmio piece in the fragment
7543 * write gpa, len
7544 * exit
7545 * copy data
f78146b0
AK		 7546 * execute insn
7547 *
7548 * write:
7549 * for each fragment
87da7e66
XG		 7550 * for each mmio piece in the fragment
7551 * write gpa, len
7552 * copy data
7553 * exit
f78146b0 7554 */
716d51ab 7555static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7556{
7557 struct kvm_run *run = vcpu->run;
f78146b0 7558 struct kvm_mmio_fragment *frag;
87da7e66 7559 unsigned len;
5287f194 7560
716d51ab 7561 BUG_ON(!vcpu->mmio_needed);
5287f194 7562
716d51ab 7563 /* Complete previous fragment */
87da7e66
XG		 7564 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7565 len = min(8u, frag->len);
716d51ab 7566 if (!vcpu->mmio_is_write)
87da7e66
XG		 7567 memcpy(frag->data, run->mmio.data, len);
7568
7569 if (frag->len <= 8) {
7570 /* Switch to the next fragment. */
7571 frag++;
7572 vcpu->mmio_cur_fragment++;
7573 } else {
7574 /* Go forward to the next mmio piece. */
7575 frag->data += len;
7576 frag->gpa += len;
7577 frag->len -= len;
7578 }
7579
a08d3b3b 7580 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7581 vcpu->mmio_needed = 0;
0912c977
PB		 7582
7583 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7584 if (vcpu->mmio_is_write)
716d51ab
GN		 7585 return 1;
7586 vcpu->mmio_read_completed = 1;
7587 return complete_emulated_io(vcpu);
7588 }
87da7e66 7589
716d51ab
GN		 7590 run->exit_reason = KVM_EXIT_MMIO;
7591 run->mmio.phys_addr = frag->gpa;
7592 if (vcpu->mmio_is_write)
87da7e66
XG		 7593 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7594 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7595 run->mmio.is_write = vcpu->mmio_is_write;
7596 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7597 return 0;
5287f194
AK		 7598}
7599
b6c7a5dc
HB		 7600int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7601{
7602 int r;
b6c7a5dc 7603
accb757d 7604 vcpu_load(vcpu);
20b7035c 7605 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7606 kvm_load_guest_fpu(vcpu);
7607
a4535290 7608 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7609 if (kvm_run->immediate_exit) {
7610 r = -EINTR;
7611 goto out;
7612 }
b6c7a5dc 7613 kvm_vcpu_block(vcpu);
66450a21 7614 kvm_apic_accept_events(vcpu);
72875d8a 7615 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7616 r = -EAGAIN;
a0595000
JS		 7617 if (signal_pending(current)) {
7618 r = -EINTR;
7619 vcpu->run->exit_reason = KVM_EXIT_INTR;
7620 ++vcpu->stat.signal_exits;
7621 }
ac9f6dc0 7622 goto out;
b6c7a5dc
HB		 7623 }
7624
01643c51
KH		 7625 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7626 r = -EINVAL;
7627 goto out;
7628 }
7629
7630 if (vcpu->run->kvm_dirty_regs) {
7631 r = sync_regs(vcpu);
7632 if (r != 0)
7633 goto out;
7634 }
7635
b6c7a5dc 7636 /* re-sync apic's tpr */
35754c98 7637 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7638 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7639 r = -EINVAL;
7640 goto out;
7641 }
7642 }
b6c7a5dc 7643
716d51ab
GN		 7644 if (unlikely(vcpu->arch.complete_userspace_io)) {
7645 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7646 vcpu->arch.complete_userspace_io = NULL;
7647 r = cui(vcpu);
7648 if (r <= 0)
5663d8f9 7649 goto out;
716d51ab
GN		 7650 } else
7651 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7652
460df4c1
PB		 7653 if (kvm_run->immediate_exit)
7654 r = -EINTR;
7655 else
7656 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7657
7658out:
5663d8f9 7659 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7660 if (vcpu->run->kvm_valid_regs)
7661 store_regs(vcpu);
f1d86e46 7662 post_kvm_run_save(vcpu);
20b7035c 7663 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7664
accb757d 7665 vcpu_put(vcpu);
b6c7a5dc
HB		 7666 return r;
7667}
7668
01643c51 7669static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7670{
7ae441ea
GN		 7671 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7672 /*
7673 * We are here if userspace calls get_regs() in the middle of
7674 * instruction emulation. Registers state needs to be copied
4a969980 7675 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7676 * that usually, but some bad designed PV devices (vmware
7677 * backdoor interface) need this to work
7678 */
dd856efa 7679 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7680 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7681 }
5fdbf976
MT		 7682 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7683 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7684 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7685 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7686 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7687 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7688 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7689 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7690#ifdef CONFIG_X86_64
5fdbf976
MT		 7691 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7692 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7693 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7694 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7695 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7696 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7697 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7698 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7699#endif
7700
5fdbf976 7701 regs->rip = kvm_rip_read(vcpu);
91586a3b 7702 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7703}
b6c7a5dc 7704
01643c51
KH		 7705int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7706{
7707 vcpu_load(vcpu);
7708 __get_regs(vcpu, regs);
1fc9b76b 7709 vcpu_put(vcpu);
b6c7a5dc
HB		 7710 return 0;
7711}
7712
01643c51 7713static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7714{
7ae441ea
GN		 7715 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7716 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7717
5fdbf976
MT		 7718 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7719 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7720 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7721 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7722 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7723 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7724 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7725 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7726#ifdef CONFIG_X86_64
5fdbf976
MT		 7727 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7728 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7729 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7730 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7731 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7732 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7733 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7734 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7735#endif
7736
5fdbf976 7737 kvm_rip_write(vcpu, regs->rip);
d73235d1 7738 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7739
b4f14abd
JK		 7740 vcpu->arch.exception.pending = false;
7741
3842d135 7742 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7743}
3842d135 7744
01643c51
KH		 7745int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7746{
7747 vcpu_load(vcpu);
7748 __set_regs(vcpu, regs);
875656fe 7749 vcpu_put(vcpu);
b6c7a5dc
HB		 7750 return 0;
7751}
7752
b6c7a5dc
HB		 7753void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7754{
7755 struct kvm_segment cs;
7756
3e6e0aab 7757 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7758 *db = cs.db;
7759 *l = cs.l;
7760}
7761EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7762
01643c51 7763static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7764{
89a27f4d 7765 struct desc_ptr dt;
b6c7a5dc 7766
3e6e0aab
GT		 7767 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7768 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7769 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7770 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7771 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7772 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7773
3e6e0aab
GT		 7774 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7775 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7776
7777 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7778 sregs->idt.limit = dt.size;
7779 sregs->idt.base = dt.address;
b6c7a5dc 7780 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7781 sregs->gdt.limit = dt.size;
7782 sregs->gdt.base = dt.address;
b6c7a5dc 7783
4d4ec087 7784 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7785 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7786 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7787 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7788 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7789 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7790 sregs->apic_base = kvm_get_apic_base(vcpu);
7791
923c61bb 7792 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7793
36752c9b 7794 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7795 set_bit(vcpu->arch.interrupt.nr,
7796 (unsigned long *)sregs->interrupt_bitmap);
01643c51 7797}
16d7a191 7798
01643c51
KH		 7799int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7800 struct kvm_sregs *sregs)
7801{
7802 vcpu_load(vcpu);
7803 __get_sregs(vcpu, sregs);
bcdec41c 7804 vcpu_put(vcpu);
b6c7a5dc
HB		 7805 return 0;
7806}
7807
62d9f0db
MT		 7808int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7809 struct kvm_mp_state *mp_state)
7810{
fd232561
CD		 7811 vcpu_load(vcpu);
7812
66450a21 7813 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7814 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7815 vcpu->arch.pv.pv_unhalted)
7816 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7817 else
7818 mp_state->mp_state = vcpu->arch.mp_state;
7819
fd232561 7820 vcpu_put(vcpu);
62d9f0db
MT		 7821 return 0;
7822}
7823
7824int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7825 struct kvm_mp_state *mp_state)
7826{
e83dff5e
CD		 7827 int ret = -EINVAL;
7828
7829 vcpu_load(vcpu);
7830
bce87cce 7831 if (!lapic_in_kernel(vcpu) &&
66450a21 7832 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7833 goto out;
66450a21 7834
28bf2888
DH		 7835 /* INITs are latched while in SMM */
7836 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7837 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7838 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7839 goto out;
28bf2888 7840
66450a21
JK		 7841 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7842 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7843 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7844 } else
7845 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7846 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7847
7848 ret = 0;
7849out:
7850 vcpu_put(vcpu);
7851 return ret;
62d9f0db
MT		 7852}
7853
7f3d35fd
KW		 7854int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7855 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7856{
9d74191a 7857 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7858 int ret;
e01c2426 7859
8ec4722d 7860 init_emulate_ctxt(vcpu);
c697518a 7861
7f3d35fd 7862 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7863 has_error_code, error_code);
c697518a 7864
c697518a 7865 if (ret)
19d04437 7866 return EMULATE_FAIL;
37817f29 7867
9d74191a
TY		 7868 kvm_rip_write(vcpu, ctxt->eip);
7869 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7870 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7871 return EMULATE_DONE;
37817f29
IE		 7872}
7873EXPORT_SYMBOL_GPL(kvm_task_switch);
7874
f2981033
LT		 7875int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7876{
37b95951 7877 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7878 /*
7879 * When EFER.LME and CR0.PG are set, the processor is in
7880 * 64-bit mode (though maybe in a 32-bit code segment).
7881 * CR4.PAE and EFER.LMA must be set.
7882 */
37b95951 7883 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7884 || !(sregs->efer & EFER_LMA))
7885 return -EINVAL;
7886 } else {
7887 /*
7888 * Not in 64-bit mode: EFER.LMA is clear and the code
7889 * segment cannot be 64-bit.
7890 */
7891 if (sregs->efer & EFER_LMA || sregs->cs.l)
7892 return -EINVAL;
7893 }
7894
7895 return 0;
7896}
7897
01643c51 7898static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7899{
58cb628d 7900 struct msr_data apic_base_msr;
b6c7a5dc 7901 int mmu_reset_needed = 0;
63f42e02 7902 int pending_vec, max_bits, idx;
89a27f4d 7903 struct desc_ptr dt;
b4ef9d4e
CD		 7904 int ret = -EINVAL;
7905
d6321d49
RK		 7906 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7907 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7908 goto out;
6d1068b3 7909
f2981033 7910 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 7911 goto out;
f2981033 7912
d3802286
JM		 7913 apic_base_msr.data = sregs->apic_base;
7914 apic_base_msr.host_initiated = true;
7915 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 7916 goto out;
6d1068b3 7917
89a27f4d
GN		 7918 dt.size = sregs->idt.limit;
7919 dt.address = sregs->idt.base;
b6c7a5dc 7920 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7921 dt.size = sregs->gdt.limit;
7922 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7923 kvm_x86_ops->set_gdt(vcpu, &dt);
7924
ad312c7c 7925 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7926 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7927 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7928 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7929
2d3ad1f4 7930 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7931
f6801dff 7932 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7933 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7934
4d4ec087 7935 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7936 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7937 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7938
fc78f519 7939 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7940 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7941 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7942 kvm_update_cpuid(vcpu);
63f42e02
XG		 7943
7944 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7945 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7946 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7947 mmu_reset_needed = 1;
7948 }
63f42e02 7949 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7950
7951 if (mmu_reset_needed)
7952 kvm_mmu_reset_context(vcpu);
7953
a50abc3b 7954 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7955 pending_vec = find_first_bit(
7956 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7957 if (pending_vec < max_bits) {
66fd3f7f 7958 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7959 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7960 }
7961
3e6e0aab
GT		 7962 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7963 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7964 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7965 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7966 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7967 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7968
3e6e0aab
GT		 7969 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7970 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7971
5f0269f5
ME		 7972 update_cr8_intercept(vcpu);
7973
9c3e4aab 7974 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7975 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7976 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7977 !is_protmode(vcpu))
9c3e4aab
MT		 7978 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7979
3842d135
AK		 7980 kvm_make_request(KVM_REQ_EVENT, vcpu);
7981
b4ef9d4e
CD		 7982 ret = 0;
7983out:
01643c51
KH		 7984 return ret;
7985}
7986
7987int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7988 struct kvm_sregs *sregs)
7989{
7990 int ret;
7991
7992 vcpu_load(vcpu);
7993 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 7994 vcpu_put(vcpu);
7995 return ret;
b6c7a5dc
HB		 7996}
7997
d0bfb940
JK		 7998int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7999 struct kvm_guest_debug *dbg)
b6c7a5dc 8000{
355be0b9 8001 unsigned long rflags;
ae675ef0 8002 int i, r;
b6c7a5dc 8003
66b56562
CD		 8004 vcpu_load(vcpu);
8005
4f926bf2
JK		 8006 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8007 r = -EBUSY;
8008 if (vcpu->arch.exception.pending)
2122ff5e 8009 goto out;
4f926bf2
JK		 8010 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8011 kvm_queue_exception(vcpu, DB_VECTOR);
8012 else
8013 kvm_queue_exception(vcpu, BP_VECTOR);
8014 }
8015
91586a3b
JK		 8016 /*
8017 * Read rflags as long as potentially injected trace flags are still
8018 * filtered out.
8019 */
8020 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8021
8022 vcpu->guest_debug = dbg->control;
8023 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8024 vcpu->guest_debug = 0;
8025
8026 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8027 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8028 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8029 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8030 } else {
8031 for (i = 0; i < KVM_NR_DB_REGS; i++)
8032 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8033 }
c8639010 8034 kvm_update_dr7(vcpu);
ae675ef0 8035
f92653ee
JK		 8036 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8037 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8038 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8039
91586a3b
JK		 8040 /*
8041 * Trigger an rflags update that will inject or remove the trace
8042 * flags.
8043 */
8044 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8045
a96036b8 8046 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8047
4f926bf2 8048 r = 0;
d0bfb940 8049
2122ff5e 8050out:
66b56562 8051 vcpu_put(vcpu);
b6c7a5dc
HB		 8052 return r;
8053}
8054
8b006791
ZX		 8055/*
8056 * Translate a guest virtual address to a guest physical address.
8057 */
8058int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8059 struct kvm_translation *tr)
8060{
8061 unsigned long vaddr = tr->linear_address;
8062 gpa_t gpa;
f656ce01 8063 int idx;
8b006791 8064
1da5b61d
CD		 8065 vcpu_load(vcpu);
8066
f656ce01 8067 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8068 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8069 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8070 tr->physical_address = gpa;
8071 tr->valid = gpa != UNMAPPED_GVA;
8072 tr->writeable = 1;
8073 tr->usermode = 0;
8b006791 8074
1da5b61d 8075 vcpu_put(vcpu);
8b006791
ZX		 8076 return 0;
8077}
8078
d0752060
HB		 8079int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8080{
1393123e 8081 struct fxregs_state *fxsave;
d0752060 8082
1393123e 8083 vcpu_load(vcpu);
d0752060 8084
1393123e 8085 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8086 memcpy(fpu->fpr, fxsave->st_space, 128);
8087 fpu->fcw = fxsave->cwd;
8088 fpu->fsw = fxsave->swd;
8089 fpu->ftwx = fxsave->twd;
8090 fpu->last_opcode = fxsave->fop;
8091 fpu->last_ip = fxsave->rip;
8092 fpu->last_dp = fxsave->rdp;
8093 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8094
1393123e 8095 vcpu_put(vcpu);
d0752060
HB		 8096 return 0;
8097}
8098
8099int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8100{
6a96bc7f
CD		 8101 struct fxregs_state *fxsave;
8102
8103 vcpu_load(vcpu);
8104
8105 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8106
d0752060
HB		 8107 memcpy(fxsave->st_space, fpu->fpr, 128);
8108 fxsave->cwd = fpu->fcw;
8109 fxsave->swd = fpu->fsw;
8110 fxsave->twd = fpu->ftwx;
8111 fxsave->fop = fpu->last_opcode;
8112 fxsave->rip = fpu->last_ip;
8113 fxsave->rdp = fpu->last_dp;
8114 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8115
6a96bc7f 8116 vcpu_put(vcpu);
d0752060
HB		 8117 return 0;
8118}
8119
01643c51
KH		 8120static void store_regs(struct kvm_vcpu *vcpu)
8121{
8122 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8123
8124 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8125 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8126
8127 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8128 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8129
8130 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8131 kvm_vcpu_ioctl_x86_get_vcpu_events(
8132 vcpu, &vcpu->run->s.regs.events);
8133}
8134
8135static int sync_regs(struct kvm_vcpu *vcpu)
8136{
8137 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8138 return -EINVAL;
8139
8140 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8141 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8142 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8143 }
8144 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8145 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8146 return -EINVAL;
8147 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8148 }
8149 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8150 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8151 vcpu, &vcpu->run->s.regs.events))
8152 return -EINVAL;
8153 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8154 }
8155
8156 return 0;
8157}
8158
0ee6a517 8159static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8160{
bf935b0b 8161 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8162 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8163 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8164 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8165
2acf923e
DC		 8166 /*
8167 * Ensure guest xcr0 is valid for loading
8168 */
d91cab78 8169 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8170
ad312c7c 8171 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8172}
d0752060 8173
f775b13e 8174/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8175void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8176{
f775b13e
RR		 8177 preempt_disable();
8178 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8179 /* PKRU is separately restored in kvm_x86_ops->run. */
8180 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8181 ~XFEATURE_MASK_PKRU);
f775b13e 8182 preempt_enable();
0c04851c 8183 trace_kvm_fpu(1);
d0752060 8184}
d0752060 8185
f775b13e 8186/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8187void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8188{
f775b13e 8189 preempt_disable();
4f836347 8190 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8191 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8192 preempt_enable();
f096ed85 8193 ++vcpu->stat.fpu_reload;
0c04851c 8194 trace_kvm_fpu(0);
d0752060 8195}
e9b11c17
ZX		 8196
8197void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8198{
bd768e14
IY		 8199 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8200
12f9a48f 8201 kvmclock_reset(vcpu);
7f1ea208 8202
e9b11c17 8203 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8204 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8205}
8206
8207struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8208 unsigned int id)
8209{
c447e76b
LL		 8210 struct kvm_vcpu *vcpu;
8211
b0c39dc6 8212 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8213 printk_once(KERN_WARNING
8214 "kvm: SMP vm created on host with unstable TSC; "
8215 "guest TSC will not be reliable\n");
c447e76b
LL		 8216
8217 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8218
c447e76b 8219 return vcpu;
26e5215f 8220}
e9b11c17 8221
26e5215f
AK		 8222int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8223{
19efffa2 8224 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8225 vcpu_load(vcpu);
d28bc9dd 8226 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8227 kvm_mmu_setup(vcpu);
e9b11c17 8228 vcpu_put(vcpu);
ec7660cc 8229 return 0;
e9b11c17
ZX		 8230}
8231
31928aa5 8232void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8233{
8fe8ab46 8234 struct msr_data msr;
332967a3 8235 struct kvm *kvm = vcpu->kvm;
42897d86 8236
d3457c87
RK		 8237 kvm_hv_vcpu_postcreate(vcpu);
8238
ec7660cc 8239 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8240 return;
ec7660cc 8241 vcpu_load(vcpu);
8fe8ab46
WA		 8242 msr.data = 0x0;
8243 msr.index = MSR_IA32_TSC;
8244 msr.host_initiated = true;
8245 kvm_write_tsc(vcpu, &msr);
42897d86 8246 vcpu_put(vcpu);
ec7660cc 8247 mutex_unlock(&vcpu->mutex);
42897d86 8248
630994b3
MT		 8249 if (!kvmclock_periodic_sync)
8250 return;
8251
332967a3
AJ		 8252 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8253 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8254}
8255
d40ccc62 8256void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8257{
344d9588
GN		 8258 vcpu->arch.apf.msr_val = 0;
8259
ec7660cc 8260 vcpu_load(vcpu);
e9b11c17
ZX		 8261 kvm_mmu_unload(vcpu);
8262 vcpu_put(vcpu);
8263
8264 kvm_x86_ops->vcpu_free(vcpu);
8265}
8266
d28bc9dd 8267void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8268{
b7e31be3
RK		 8269 kvm_lapic_reset(vcpu, init_event);
8270
e69fab5d
PB		 8271 vcpu->arch.hflags = 0;
8272
c43203ca 8273 vcpu->arch.smi_pending = 0;
52797bf9 8274 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8275 atomic_set(&vcpu->arch.nmi_queued, 0);
8276 vcpu->arch.nmi_pending = 0;
448fa4a9 8277 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8278 kvm_clear_interrupt_queue(vcpu);
8279 kvm_clear_exception_queue(vcpu);
664f8e26 8280 vcpu->arch.exception.pending = false;
448fa4a9 8281
42dbaa5a 8282 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8283 kvm_update_dr0123(vcpu);
6f43ed01 8284 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8285 kvm_update_dr6(vcpu);
42dbaa5a 8286 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8287 kvm_update_dr7(vcpu);
42dbaa5a 8288
1119022c
NA		 8289 vcpu->arch.cr2 = 0;
8290
3842d135 8291 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8292 vcpu->arch.apf.msr_val = 0;
c9aaa895 8293 vcpu->arch.st.msr_val = 0;
3842d135 8294
12f9a48f
GC		 8295 kvmclock_reset(vcpu);
8296
af585b92
GN		 8297 kvm_clear_async_pf_completion_queue(vcpu);
8298 kvm_async_pf_hash_reset(vcpu);
8299 vcpu->arch.apf.halted = false;
3842d135 8300
a554d207
WL		 8301 if (kvm_mpx_supported()) {
8302 void *mpx_state_buffer;
8303
8304 /*
8305 * To avoid have the INIT path from kvm_apic_has_events() that be
8306 * called with loaded FPU and does not let userspace fix the state.
8307 */
f775b13e
RR		 8308 if (init_event)
8309 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8310 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8311 XFEATURE_MASK_BNDREGS);
8312 if (mpx_state_buffer)
8313 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8314 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8315 XFEATURE_MASK_BNDCSR);
8316 if (mpx_state_buffer)
8317 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8318 if (init_event)
8319 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8320 }
8321
64d60670 8322 if (!init_event) {
d28bc9dd 8323 kvm_pmu_reset(vcpu);
64d60670 8324 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8325
8326 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8327 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8328
8329 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8330 }
f5132b01 8331
66f7b72e
JS		 8332 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8333 vcpu->arch.regs_avail = ~0;
8334 vcpu->arch.regs_dirty = ~0;
8335
a554d207
WL		 8336 vcpu->arch.ia32_xss = 0;
8337
d28bc9dd 8338 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8339}
8340
2b4a273b 8341void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8342{
8343 struct kvm_segment cs;
8344
8345 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8346 cs.selector = vector << 8;
8347 cs.base = vector << 12;
8348 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8349 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8350}
8351
13a34e06 8352int kvm_arch_hardware_enable(void)
e9b11c17 8353{
ca84d1a2
ZA		 8354 struct kvm *kvm;
8355 struct kvm_vcpu *vcpu;
8356 int i;
0dd6a6ed
ZA		 8357 int ret;
8358 u64 local_tsc;
8359 u64 max_tsc = 0;
8360 bool stable, backwards_tsc = false;
18863bdd
AK		 8361
8362 kvm_shared_msr_cpu_online();
13a34e06 8363 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8364 if (ret != 0)
8365 return ret;
8366
4ea1636b 8367 local_tsc = rdtsc();
b0c39dc6 8368 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8369 list_for_each_entry(kvm, &vm_list, vm_list) {
8370 kvm_for_each_vcpu(i, vcpu, kvm) {
8371 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8372 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8373 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8374 backwards_tsc = true;
8375 if (vcpu->arch.last_host_tsc > max_tsc)
8376 max_tsc = vcpu->arch.last_host_tsc;
8377 }
8378 }
8379 }
8380
8381 /*
8382 * Sometimes, even reliable TSCs go backwards. This happens on
8383 * platforms that reset TSC during suspend or hibernate actions, but
8384 * maintain synchronization. We must compensate. Fortunately, we can
8385 * detect that condition here, which happens early in CPU bringup,
8386 * before any KVM threads can be running. Unfortunately, we can't
8387 * bring the TSCs fully up to date with real time, as we aren't yet far
8388 * enough into CPU bringup that we know how much real time has actually
108b249c 8389 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8390 * variables that haven't been updated yet.
8391 *
8392 * So we simply find the maximum observed TSC above, then record the
8393 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8394 * the adjustment will be applied. Note that we accumulate
8395 * adjustments, in case multiple suspend cycles happen before some VCPU
8396 * gets a chance to run again. In the event that no KVM threads get a
8397 * chance to run, we will miss the entire elapsed period, as we'll have
8398 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8399 * loose cycle time. This isn't too big a deal, since the loss will be
8400 * uniform across all VCPUs (not to mention the scenario is extremely
8401 * unlikely). It is possible that a second hibernate recovery happens
8402 * much faster than a first, causing the observed TSC here to be
8403 * smaller; this would require additional padding adjustment, which is
8404 * why we set last_host_tsc to the local tsc observed here.
8405 *
8406 * N.B. - this code below runs only on platforms with reliable TSC,
8407 * as that is the only way backwards_tsc is set above. Also note
8408 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8409 * have the same delta_cyc adjustment applied if backwards_tsc
8410 * is detected. Note further, this adjustment is only done once,
8411 * as we reset last_host_tsc on all VCPUs to stop this from being
8412 * called multiple times (one for each physical CPU bringup).
8413 *
4a969980 8414 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8415 * will be compensated by the logic in vcpu_load, which sets the TSC to
8416 * catchup mode. This will catchup all VCPUs to real time, but cannot
8417 * guarantee that they stay in perfect synchronization.
8418 */
8419 if (backwards_tsc) {
8420 u64 delta_cyc = max_tsc - local_tsc;
8421 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8422 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8423 kvm_for_each_vcpu(i, vcpu, kvm) {
8424 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8425 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8426 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8427 }
8428
8429 /*
8430 * We have to disable TSC offset matching.. if you were
8431 * booting a VM while issuing an S4 host suspend....
8432 * you may have some problem. Solving this issue is
8433 * left as an exercise to the reader.
8434 */
8435 kvm->arch.last_tsc_nsec = 0;
8436 kvm->arch.last_tsc_write = 0;
8437 }
8438
8439 }
8440 return 0;
e9b11c17
ZX		 8441}
8442
13a34e06 8443void kvm_arch_hardware_disable(void)
e9b11c17 8444{
13a34e06
RK		 8445 kvm_x86_ops->hardware_disable();
8446 drop_user_return_notifiers();
e9b11c17
ZX		 8447}
8448
8449int kvm_arch_hardware_setup(void)
8450{
9e9c3fe4
NA		 8451 int r;
8452
8453 r = kvm_x86_ops->hardware_setup();
8454 if (r != 0)
8455 return r;
8456
35181e86
HZ		 8457 if (kvm_has_tsc_control) {
8458 /*
8459 * Make sure the user can only configure tsc_khz values that
8460 * fit into a signed integer.
8461 * A min value is not calculated needed because it will always
8462 * be 1 on all machines.
8463 */
8464 u64 max = min(0x7fffffffULL,
8465 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8466 kvm_max_guest_tsc_khz = max;
8467
ad721883 8468 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8469 }
ad721883 8470
9e9c3fe4
NA		 8471 kvm_init_msr_list();
8472 return 0;
e9b11c17
ZX		 8473}
8474
8475void kvm_arch_hardware_unsetup(void)
8476{
8477 kvm_x86_ops->hardware_unsetup();
8478}
8479
8480void kvm_arch_check_processor_compat(void *rtn)
8481{
8482 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8483}
8484
8485bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8486{
8487 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8488}
8489EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8490
8491bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8492{
8493 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8494}
8495
54e9818f 8496struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8497EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8498
e9b11c17
ZX		 8499int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8500{
8501 struct page *page;
e9b11c17
ZX		 8502 int r;
8503
b2a05fef 8504 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8505 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8506 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8507 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8508 else
a4535290 8509 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8510
8511 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8512 if (!page) {
8513 r = -ENOMEM;
8514 goto fail;
8515 }
ad312c7c 8516 vcpu->arch.pio_data = page_address(page);
e9b11c17 8517
cc578287 8518 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8519
e9b11c17
ZX		 8520 r = kvm_mmu_create(vcpu);
8521 if (r < 0)
8522 goto fail_free_pio_data;
8523
26de7988 8524 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8525 r = kvm_create_lapic(vcpu);
8526 if (r < 0)
8527 goto fail_mmu_destroy;
54e9818f
GN		 8528 } else
8529 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8530
890ca9ae
HY		 8531 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8532 GFP_KERNEL);
8533 if (!vcpu->arch.mce_banks) {
8534 r = -ENOMEM;
443c39bc 8535 goto fail_free_lapic;
890ca9ae
HY		 8536 }
8537 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8538
f1797359
WY		 8539 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8540 r = -ENOMEM;
f5f48ee1 8541 goto fail_free_mce_banks;
f1797359 8542 }
f5f48ee1 8543
0ee6a517 8544 fx_init(vcpu);
66f7b72e 8545
4344ee98 8546 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8547
5a4f55cd
EK		 8548 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8549
74545705
RK		 8550 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8551
af585b92 8552 kvm_async_pf_hash_reset(vcpu);
f5132b01 8553 kvm_pmu_init(vcpu);
af585b92 8554
1c1a9ce9 8555 vcpu->arch.pending_external_vector = -1;
de63ad4c 8556 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8557
5c919412
AS		 8558 kvm_hv_vcpu_init(vcpu);
8559
e9b11c17 8560 return 0;
0ee6a517 8561
f5f48ee1
SY		 8562fail_free_mce_banks:
8563 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8564fail_free_lapic:
8565 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8566fail_mmu_destroy:
8567 kvm_mmu_destroy(vcpu);
8568fail_free_pio_data:
ad312c7c 8569 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8570fail:
8571 return r;
8572}
8573
8574void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8575{
f656ce01
MT		 8576 int idx;
8577
1f4b34f8 8578 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8579 kvm_pmu_destroy(vcpu);
36cb93fd 8580 kfree(vcpu->arch.mce_banks);
e9b11c17 8581 kvm_free_lapic(vcpu);
f656ce01 8582 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8583 kvm_mmu_destroy(vcpu);
f656ce01 8584 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8585 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8586 if (!lapic_in_kernel(vcpu))
54e9818f 8587 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8588}
d19a9cd2 8589
e790d9ef
RK		 8590void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8591{
ae97a3b8 8592 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8593}
8594
e08b9637 8595int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8596{
e08b9637
CO		 8597 if (type)
8598 return -EINVAL;
8599
6ef768fa 8600 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8601 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8602 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8603 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8604 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8605
5550af4d
SY		 8606 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8607 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8608 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8609 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8610 &kvm->arch.irq_sources_bitmap);
5550af4d 8611
038f8c11 8612 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8613 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8614 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8615
108b249c 8616 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8617 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8618
7e44e449 8619 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8620 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8621
cbc0236a 8622 kvm_hv_init_vm(kvm);
0eb05bf2 8623 kvm_page_track_init(kvm);
13d268ca 8624 kvm_mmu_init_vm(kvm);
0eb05bf2 8625
03543133
SS		 8626 if (kvm_x86_ops->vm_init)
8627 return kvm_x86_ops->vm_init(kvm);
8628
d89f5eff 8629 return 0;
d19a9cd2
ZX		 8630}
8631
8632static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8633{
ec7660cc 8634 vcpu_load(vcpu);
d19a9cd2
ZX		 8635 kvm_mmu_unload(vcpu);
8636 vcpu_put(vcpu);
8637}
8638
8639static void kvm_free_vcpus(struct kvm *kvm)
8640{
8641 unsigned int i;
988a2cae 8642 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8643
8644 /*
8645 * Unpin any mmu pages first.
8646 */
af585b92
GN		 8647 kvm_for_each_vcpu(i, vcpu, kvm) {
8648 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8649 kvm_unload_vcpu_mmu(vcpu);
af585b92 8650 }
988a2cae
GN		 8651 kvm_for_each_vcpu(i, vcpu, kvm)
8652 kvm_arch_vcpu_free(vcpu);
8653
8654 mutex_lock(&kvm->lock);
8655 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8656 kvm->vcpus[i] = NULL;
d19a9cd2 8657
988a2cae
GN		 8658 atomic_set(&kvm->online_vcpus, 0);
8659 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8660}
8661
ad8ba2cd
SY		 8662void kvm_arch_sync_events(struct kvm *kvm)
8663{
332967a3 8664 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8665 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8666 kvm_free_pit(kvm);
ad8ba2cd
SY		 8667}
8668
1d8007bd 8669int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8670{
8671 int i, r;
25188b99 8672 unsigned long hva;
f0d648bd
PB		 8673 struct kvm_memslots *slots = kvm_memslots(kvm);
8674 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8675
8676 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8677 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8678 return -EINVAL;
9da0e4d5 8679
f0d648bd
PB		 8680 slot = id_to_memslot(slots, id);
8681 if (size) {
b21629da 8682 if (slot->npages)
f0d648bd
PB		 8683 return -EEXIST;
8684
8685 /*
8686 * MAP_SHARED to prevent internal slot pages from being moved
8687 * by fork()/COW.
8688 */
8689 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8690 MAP_SHARED | MAP_ANONYMOUS, 0);
8691 if (IS_ERR((void *)hva))
8692 return PTR_ERR((void *)hva);
8693 } else {
8694 if (!slot->npages)
8695 return 0;
8696
8697 hva = 0;
8698 }
8699
8700 old = *slot;
9da0e4d5 8701 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8702 struct kvm_userspace_memory_region m;
9da0e4d5 8703
1d8007bd
PB		 8704 m.slot = id | (i << 16);
8705 m.flags = 0;
8706 m.guest_phys_addr = gpa;
f0d648bd 8707 m.userspace_addr = hva;
1d8007bd 8708 m.memory_size = size;
9da0e4d5
PB		 8709 r = __kvm_set_memory_region(kvm, &m);
8710 if (r < 0)
8711 return r;
8712 }
8713
103c763c
EB		 8714 if (!size)
8715 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8716
9da0e4d5
PB		 8717 return 0;
8718}
8719EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8720
1d8007bd 8721int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8722{
8723 int r;
8724
8725 mutex_lock(&kvm->slots_lock);
1d8007bd 8726 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8727 mutex_unlock(&kvm->slots_lock);
8728
8729 return r;
8730}
8731EXPORT_SYMBOL_GPL(x86_set_memory_region);
8732
d19a9cd2
ZX		 8733void kvm_arch_destroy_vm(struct kvm *kvm)
8734{
27469d29
AH		 8735 if (current->mm == kvm->mm) {
8736 /*
8737 * Free memory regions allocated on behalf of userspace,
8738 * unless the the memory map has changed due to process exit
8739 * or fd copying.
8740 */
1d8007bd
PB		 8741 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8742 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8743 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8744 }
03543133
SS		 8745 if (kvm_x86_ops->vm_destroy)
8746 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8747 kvm_pic_destroy(kvm);
8748 kvm_ioapic_destroy(kvm);
d19a9cd2 8749 kvm_free_vcpus(kvm);
af1bae54 8750 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8751 kvm_mmu_uninit_vm(kvm);
2beb6dad 8752 kvm_page_track_cleanup(kvm);
cbc0236a 8753 kvm_hv_destroy_vm(kvm);
d19a9cd2 8754}
0de10343 8755
5587027c 8756void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8757 struct kvm_memory_slot *dont)
8758{
8759 int i;
8760
d89cc617
TY		 8761 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8762 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8763 kvfree(free->arch.rmap[i]);
d89cc617 8764 free->arch.rmap[i] = NULL;
77d11309 8765 }
d89cc617
TY		 8766 if (i == 0)
8767 continue;
8768
8769 if (!dont || free->arch.lpage_info[i - 1] !=
8770 dont->arch.lpage_info[i - 1]) {
548ef284 8771 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8772 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8773 }
8774 }
21ebbeda
XG		 8775
8776 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8777}
8778
5587027c
AK		 8779int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8780 unsigned long npages)
db3fe4eb
TY		 8781{
8782 int i;
8783
d89cc617 8784 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8785 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8786 unsigned long ugfn;
8787 int lpages;
d89cc617 8788 int level = i + 1;
db3fe4eb
TY		 8789
8790 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8791 slot->base_gfn, level) + 1;
8792
d89cc617 8793 slot->arch.rmap[i] =
a7c3e901 8794 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8795 if (!slot->arch.rmap[i])
77d11309 8796 goto out_free;
d89cc617
TY		 8797 if (i == 0)
8798 continue;
77d11309 8799
a7c3e901 8800 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8801 if (!linfo)
db3fe4eb
TY		 8802 goto out_free;
8803
92f94f1e
XG		 8804 slot->arch.lpage_info[i - 1] = linfo;
8805
db3fe4eb 8806 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8807 linfo[0].disallow_lpage = 1;
db3fe4eb 8808 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8809 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8810 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8811 /*
8812 * If the gfn and userspace address are not aligned wrt each
8813 * other, or if explicitly asked to, disable large page
8814 * support for this slot
8815 */
8816 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8817 !kvm_largepages_enabled()) {
8818 unsigned long j;
8819
8820 for (j = 0; j < lpages; ++j)
92f94f1e 8821 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8822 }
8823 }
8824
21ebbeda
XG		 8825 if (kvm_page_track_create_memslot(slot, npages))
8826 goto out_free;
8827
db3fe4eb
TY		 8828 return 0;
8829
8830out_free:
d89cc617 8831 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8832 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8833 slot->arch.rmap[i] = NULL;
8834 if (i == 0)
8835 continue;
8836
548ef284 8837 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8838 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8839 }
8840 return -ENOMEM;
8841}
8842
15f46015 8843void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8844{
e6dff7d1
TY		 8845 /*
8846 * memslots->generation has been incremented.
8847 * mmio generation may have reached its maximum value.
8848 */
54bf36aa 8849 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8850}
8851
f7784b8e
MT		 8852int kvm_arch_prepare_memory_region(struct kvm *kvm,
8853 struct kvm_memory_slot *memslot,
09170a49 8854 const struct kvm_userspace_memory_region *mem,
7b6195a9 8855 enum kvm_mr_change change)
0de10343 8856{
f7784b8e
MT		 8857 return 0;
8858}
8859
88178fd4
KH		 8860static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8861 struct kvm_memory_slot *new)
8862{
8863 /* Still write protect RO slot */
8864 if (new->flags & KVM_MEM_READONLY) {
8865 kvm_mmu_slot_remove_write_access(kvm, new);
8866 return;
8867 }
8868
8869 /*
8870 * Call kvm_x86_ops dirty logging hooks when they are valid.
8871 *
8872 * kvm_x86_ops->slot_disable_log_dirty is called when:
8873 *
8874 * - KVM_MR_CREATE with dirty logging is disabled
8875 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8876 *
8877 * The reason is, in case of PML, we need to set D-bit for any slots
8878 * with dirty logging disabled in order to eliminate unnecessary GPA
8879 * logging in PML buffer (and potential PML buffer full VMEXT). This
8880 * guarantees leaving PML enabled during guest's lifetime won't have
8881 * any additonal overhead from PML when guest is running with dirty
8882 * logging disabled for memory slots.
8883 *
8884 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8885 * to dirty logging mode.
8886 *
8887 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8888 *
8889 * In case of write protect:
8890 *
8891 * Write protect all pages for dirty logging.
8892 *
8893 * All the sptes including the large sptes which point to this
8894 * slot are set to readonly. We can not create any new large
8895 * spte on this slot until the end of the logging.
8896 *
8897 * See the comments in fast_page_fault().
8898 */
8899 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8900 if (kvm_x86_ops->slot_enable_log_dirty)
8901 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8902 else
8903 kvm_mmu_slot_remove_write_access(kvm, new);
8904 } else {
8905 if (kvm_x86_ops->slot_disable_log_dirty)
8906 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8907 }
8908}
8909
f7784b8e 8910void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8911 const struct kvm_userspace_memory_region *mem,
8482644a 8912 const struct kvm_memory_slot *old,
f36f3f28 8913 const struct kvm_memory_slot *new,
8482644a 8914 enum kvm_mr_change change)
f7784b8e 8915{
8482644a 8916 int nr_mmu_pages = 0;
f7784b8e 8917
48c0e4e9
XG		 8918 if (!kvm->arch.n_requested_mmu_pages)
8919 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8920
48c0e4e9 8921 if (nr_mmu_pages)
0de10343 8922 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8923
3ea3b7fa
WL		 8924 /*
8925 * Dirty logging tracks sptes in 4k granularity, meaning that large
8926 * sptes have to be split. If live migration is successful, the guest
8927 * in the source machine will be destroyed and large sptes will be
8928 * created in the destination. However, if the guest continues to run
8929 * in the source machine (for example if live migration fails), small
8930 * sptes will remain around and cause bad performance.
8931 *
8932 * Scan sptes if dirty logging has been stopped, dropping those
8933 * which can be collapsed into a single large-page spte. Later
8934 * page faults will create the large-page sptes.
8935 */
8936 if ((change != KVM_MR_DELETE) &&
8937 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8938 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8939 kvm_mmu_zap_collapsible_sptes(kvm, new);
8940
c972f3b1 8941 /*
88178fd4 8942 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8943 *
88178fd4
KH		 8944 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8945 * been zapped so no dirty logging staff is needed for old slot. For
8946 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8947 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8948 *
8949 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8950 */
88178fd4 8951 if (change != KVM_MR_DELETE)
f36f3f28 8952 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8953}
1d737c8a 8954
2df72e9b 8955void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8956{
6ca18b69 8957 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8958}
8959
2df72e9b
MT		 8960void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8961 struct kvm_memory_slot *slot)
8962{
ae7cd873 8963 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8964}
8965
5d9bc648
PB		 8966static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8967{
8968 if (!list_empty_careful(&vcpu->async_pf.done))
8969 return true;
8970
8971 if (kvm_apic_has_events(vcpu))
8972 return true;
8973
8974 if (vcpu->arch.pv.pv_unhalted)
8975 return true;
8976
a5f01f8e
WL		 8977 if (vcpu->arch.exception.pending)
8978 return true;
8979
47a66eed
Z		 8980 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8981 (vcpu->arch.nmi_pending &&
8982 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8983 return true;
8984
47a66eed
Z		 8985 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8986 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8987 return true;
8988
5d9bc648
PB		 8989 if (kvm_arch_interrupt_allowed(vcpu) &&
8990 kvm_cpu_has_interrupt(vcpu))
8991 return true;
8992
1f4b34f8
AS		 8993 if (kvm_hv_has_stimer_pending(vcpu))
8994 return true;
8995
5d9bc648
PB		 8996 return false;
8997}
8998
1d737c8a
ZX		 8999int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9000{
5d9bc648 9001 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9002}
5736199a 9003
199b5763
LM		 9004bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9005{
de63ad4c 9006 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9007}
9008
b6d33834 9009int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9010{
b6d33834 9011 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9012}
78646121
GN		 9013
9014int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9015{
9016 return kvm_x86_ops->interrupt_allowed(vcpu);
9017}
229456fc 9018
82b32774 9019unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9020{
82b32774
NA		 9021 if (is_64_bit_mode(vcpu))
9022 return kvm_rip_read(vcpu);
9023 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9024 kvm_rip_read(vcpu));
9025}
9026EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9027
82b32774
NA		 9028bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9029{
9030 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9031}
9032EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9033
94fe45da
JK		 9034unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9035{
9036 unsigned long rflags;
9037
9038 rflags = kvm_x86_ops->get_rflags(vcpu);
9039 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9040 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9041 return rflags;
9042}
9043EXPORT_SYMBOL_GPL(kvm_get_rflags);
9044
6addfc42 9045static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9046{
9047 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9048 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9049 rflags |= X86_EFLAGS_TF;
94fe45da 9050 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9051}
9052
9053void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9054{
9055 __kvm_set_rflags(vcpu, rflags);
3842d135 9056 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9057}
9058EXPORT_SYMBOL_GPL(kvm_set_rflags);
9059
56028d08
GN		 9060void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9061{
9062 int r;
9063
fb67e14f 9064 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 9065 work->wakeup_all)
56028d08
GN		 9066 return;
9067
9068 r = kvm_mmu_reload(vcpu);
9069 if (unlikely(r))
9070 return;
9071
fb67e14f
XG		 9072 if (!vcpu->arch.mmu.direct_map &&
9073 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9074 return;
9075
56028d08
GN		 9076 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9077}
9078
af585b92
GN		 9079static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9080{
9081 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9082}
9083
9084static inline u32 kvm_async_pf_next_probe(u32 key)
9085{
9086 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9087}
9088
9089static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9090{
9091 u32 key = kvm_async_pf_hash_fn(gfn);
9092
9093 while (vcpu->arch.apf.gfns[key] != ~0)
9094 key = kvm_async_pf_next_probe(key);
9095
9096 vcpu->arch.apf.gfns[key] = gfn;
9097}
9098
9099static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9100{
9101 int i;
9102 u32 key = kvm_async_pf_hash_fn(gfn);
9103
9104 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9105 (vcpu->arch.apf.gfns[key] != gfn &&
9106 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9107 key = kvm_async_pf_next_probe(key);
9108
9109 return key;
9110}
9111
9112bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9113{
9114 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9115}
9116
9117static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9118{
9119 u32 i, j, k;
9120
9121 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9122 while (true) {
9123 vcpu->arch.apf.gfns[i] = ~0;
9124 do {
9125 j = kvm_async_pf_next_probe(j);
9126 if (vcpu->arch.apf.gfns[j] == ~0)
9127 return;
9128 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9129 /*
9130 * k lies cyclically in ]i,j]
9131 * | i.k.j |
9132 * |....j i.k.| or |.k..j i...|
9133 */
9134 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9135 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9136 i = j;
9137 }
9138}
9139
7c90705b
GN		 9140static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9141{
4e335d9e
PB		 9142
9143 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9144 sizeof(val));
7c90705b
GN		 9145}
9146
9a6e7c39
WL		 9147static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9148{
9149
9150 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9151 sizeof(u32));
9152}
9153
af585b92
GN		 9154void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9155 struct kvm_async_pf *work)
9156{
6389ee94
AK		 9157 struct x86_exception fault;
9158
7c90705b 9159 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9160 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9161
9162 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9163 (vcpu->arch.apf.send_user_only &&
9164 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9165 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9166 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9167 fault.vector = PF_VECTOR;
9168 fault.error_code_valid = true;
9169 fault.error_code = 0;
9170 fault.nested_page_fault = false;
9171 fault.address = work->arch.token;
adfe20fb 9172 fault.async_page_fault = true;
6389ee94 9173 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9174 }
af585b92
GN		 9175}
9176
9177void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9178 struct kvm_async_pf *work)
9179{
6389ee94 9180 struct x86_exception fault;
9a6e7c39 9181 u32 val;
6389ee94 9182
f2e10669 9183 if (work->wakeup_all)
7c90705b
GN		 9184 work->arch.token = ~0; /* broadcast wakeup */
9185 else
9186 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9187 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9188
9a6e7c39
WL		 9189 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9190 !apf_get_user(vcpu, &val)) {
9191 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9192 vcpu->arch.exception.pending &&
9193 vcpu->arch.exception.nr == PF_VECTOR &&
9194 !apf_put_user(vcpu, 0)) {
9195 vcpu->arch.exception.injected = false;
9196 vcpu->arch.exception.pending = false;
9197 vcpu->arch.exception.nr = 0;
9198 vcpu->arch.exception.has_error_code = false;
9199 vcpu->arch.exception.error_code = 0;
9200 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9201 fault.vector = PF_VECTOR;
9202 fault.error_code_valid = true;
9203 fault.error_code = 0;
9204 fault.nested_page_fault = false;
9205 fault.address = work->arch.token;
9206 fault.async_page_fault = true;
9207 kvm_inject_page_fault(vcpu, &fault);
9208 }
7c90705b 9209 }
e6d53e3b 9210 vcpu->arch.apf.halted = false;
a4fa1635 9211 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9212}
9213
9214bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9215{
9216 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9217 return true;
9218 else
9bc1f09f 9219 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9220}
9221
5544eb9b
PB		 9222void kvm_arch_start_assignment(struct kvm *kvm)
9223{
9224 atomic_inc(&kvm->arch.assigned_device_count);
9225}
9226EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9227
9228void kvm_arch_end_assignment(struct kvm *kvm)
9229{
9230 atomic_dec(&kvm->arch.assigned_device_count);
9231}
9232EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9233
9234bool kvm_arch_has_assigned_device(struct kvm *kvm)
9235{
9236 return atomic_read(&kvm->arch.assigned_device_count);
9237}
9238EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9239
e0f0bbc5
AW		 9240void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9241{
9242 atomic_inc(&kvm->arch.noncoherent_dma_count);
9243}
9244EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9245
9246void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9247{
9248 atomic_dec(&kvm->arch.noncoherent_dma_count);
9249}
9250EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9251
9252bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9253{
9254 return atomic_read(&kvm->arch.noncoherent_dma_count);
9255}
9256EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9257
14717e20
AW		 9258bool kvm_arch_has_irq_bypass(void)
9259{
9260 return kvm_x86_ops->update_pi_irte != NULL;
9261}
9262
87276880
FW		 9263int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9264 struct irq_bypass_producer *prod)
9265{
9266 struct kvm_kernel_irqfd *irqfd =
9267 container_of(cons, struct kvm_kernel_irqfd, consumer);
9268
14717e20 9269 irqfd->producer = prod;
87276880 9270
14717e20
AW		 9271 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9272 prod->irq, irqfd->gsi, 1);
87276880
FW		 9273}
9274
9275void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9276 struct irq_bypass_producer *prod)
9277{
9278 int ret;
9279 struct kvm_kernel_irqfd *irqfd =
9280 container_of(cons, struct kvm_kernel_irqfd, consumer);
9281
87276880
FW		 9282 WARN_ON(irqfd->producer != prod);
9283 irqfd->producer = NULL;
9284
9285 /*
9286 * When producer of consumer is unregistered, we change back to
9287 * remapped mode, so we can re-use the current implementation
bb3541f1 9288 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9289 * int this case doesn't want to receive the interrupts.
9290 */
9291 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9292 if (ret)
9293 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9294 " fails: %d\n", irqfd->consumer.token, ret);
9295}
9296
9297int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9298 uint32_t guest_irq, bool set)
9299{
9300 if (!kvm_x86_ops->update_pi_irte)
9301 return -EINVAL;
9302
9303 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9304}
9305
52004014
FW		 9306bool kvm_vector_hashing_enabled(void)
9307{
9308 return vector_hashing;
9309}
9310EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9311
229456fc 9312EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9313EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9314EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9315EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9316EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9317EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9318EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9319EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9320EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9321EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9322EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9323EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9324EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9325EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9326EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9327EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9328EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9329EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9330EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)