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KVM: x86: svm: remove unneeded nested_enable_evmcs() hook
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
043405e1
CO		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
9611c187 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 17 */
18
edf88417 19#include <linux/kvm_host.h>
313a3dc7 20#include "irq.h"
1d737c8a 21#include "mmu.h"
7837699f 22#include "i8254.h"
37817f29 23#include "tss.h"
5fdbf976 24#include "kvm_cache_regs.h"
26eef70c 25#include "x86.h"
00b27a3e 26#include "cpuid.h"
474a5bb9 27#include "pmu.h"
e83d5887 28#include "hyperv.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
1767e931
PG		 35#include <linux/export.h>
36#include <linux/moduleparam.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
87276880
FW		 51#include <linux/kvm_irqfd.h>
52#include <linux/irqbypass.h>
3905f9ad 53#include <linux/sched/stat.h>
0c5f81da 54#include <linux/sched/isolation.h>
d0ec49d4 55#include <linux/mem_encrypt.h>
3905f9ad 56
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
b0c39dc6 68#include <asm/mshyperv.h>
0092e434 69#include <asm/hypervisor.h>
bf8c55d8 70#include <asm/intel_pt.h>
dd2cb348 71#include <clocksource/hyperv_timer.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
c3941d9e
SC		 138/*
139 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
140 * adaptive tuning starting from default advancment of 1000ns. '0' disables
141 * advancement entirely. Any other value is used as-is and disables adaptive
142 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
143 */
144static int __read_mostly lapic_timer_advance_ns = -1;
0e6edceb 145module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
d0659d94 146
52004014
FW		 147static bool __read_mostly vector_hashing = true;
148module_param(vector_hashing, bool, S_IRUGO);
149
c4ae60e4
LA		 150bool __read_mostly enable_vmware_backdoor = false;
151module_param(enable_vmware_backdoor, bool, S_IRUGO);
152EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
153
6c86eedc
WL		 154static bool __read_mostly force_emulation_prefix = false;
155module_param(force_emulation_prefix, bool, S_IRUGO);
156
0c5f81da
WL		 157int __read_mostly pi_inject_timer = -1;
158module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
159
18863bdd
AK		 160#define KVM_NR_SHARED_MSRS 16
161
162struct kvm_shared_msrs_global {
163 int nr;
2bf78fa7 164 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 165};
166
167struct kvm_shared_msrs {
168 struct user_return_notifier urn;
169 bool registered;
2bf78fa7
SY		 170 struct kvm_shared_msr_values {
171 u64 host;
172 u64 curr;
173 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 174};
175
176static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 177static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 178
417bc304 179struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 180 { "pf_fixed", VCPU_STAT(pf_fixed) },
181 { "pf_guest", VCPU_STAT(pf_guest) },
182 { "tlb_flush", VCPU_STAT(tlb_flush) },
183 { "invlpg", VCPU_STAT(invlpg) },
184 { "exits", VCPU_STAT(exits) },
185 { "io_exits", VCPU_STAT(io_exits) },
186 { "mmio_exits", VCPU_STAT(mmio_exits) },
187 { "signal_exits", VCPU_STAT(signal_exits) },
188 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 189 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 190 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 191 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 192 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 193 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 194 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 195 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 196 { "request_irq", VCPU_STAT(request_irq_exits) },
197 { "irq_exits", VCPU_STAT(irq_exits) },
198 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 199 { "fpu_reload", VCPU_STAT(fpu_reload) },
200 { "insn_emulation", VCPU_STAT(insn_emulation) },
201 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 202 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 203 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 204 { "req_event", VCPU_STAT(req_event) },
c595ceee 205 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 206 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
207 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
208 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
209 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
210 { "mmu_flooded", VM_STAT(mmu_flooded) },
211 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 212 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 213 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 214 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 215 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 216 { "max_mmu_page_hash_collisions",
217 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 218 { NULL }
219};
220
2acf923e
DC		 221u64 __read_mostly host_xcr0;
222
b666a4b6
MO		 223struct kmem_cache *x86_fpu_cache;
224EXPORT_SYMBOL_GPL(x86_fpu_cache);
225
b6785def 226static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 227
af585b92
GN		 228static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
229{
230 int i;
231 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
232 vcpu->arch.apf.gfns[i] = ~0;
233}
234
18863bdd
AK		 235static void kvm_on_user_return(struct user_return_notifier *urn)
236{
237 unsigned slot;
18863bdd
AK		 238 struct kvm_shared_msrs *locals
239 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 240 struct kvm_shared_msr_values *values;
1650b4eb
IA		 241 unsigned long flags;
242
243 /*
244 * Disabling irqs at this point since the following code could be
245 * interrupted and executed through kvm_arch_hardware_disable()
246 */
247 local_irq_save(flags);
248 if (locals->registered) {
249 locals->registered = false;
250 user_return_notifier_unregister(urn);
251 }
252 local_irq_restore(flags);
18863bdd 253 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 254 values = &locals->values[slot];
255 if (values->host != values->curr) {
256 wrmsrl(shared_msrs_global.msrs[slot], values->host);
257 values->curr = values->host;
18863bdd
AK		 258 }
259 }
18863bdd
AK		 260}
261
2bf78fa7 262static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 263{
18863bdd 264 u64 value;
013f6a5d
MT		 265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 267
2bf78fa7
SY		 268 /* only read, and nobody should modify it at this time,
269 * so don't need lock */
270 if (slot >= shared_msrs_global.nr) {
271 printk(KERN_ERR "kvm: invalid MSR slot!");
272 return;
273 }
274 rdmsrl_safe(msr, &value);
275 smsr->values[slot].host = value;
276 smsr->values[slot].curr = value;
277}
278
279void kvm_define_shared_msr(unsigned slot, u32 msr)
280{
0123be42 281 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 282 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 283 if (slot >= shared_msrs_global.nr)
284 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 285}
286EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
287
288static void kvm_shared_msr_cpu_online(void)
289{
290 unsigned i;
18863bdd
AK		 291
292 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 293 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 294}
295
8b3c3104 296int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 297{
013f6a5d
MT		 298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 300 int err;
18863bdd 301
2bf78fa7 302 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 303 return 0;
2bf78fa7 304 smsr->values[slot].curr = value;
8b3c3104
AH		 305 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
306 if (err)
307 return 1;
308
18863bdd
AK		 309 if (!smsr->registered) {
310 smsr->urn.on_user_return = kvm_on_user_return;
311 user_return_notifier_register(&smsr->urn);
312 smsr->registered = true;
313 }
8b3c3104 314 return 0;
18863bdd
AK		 315}
316EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
317
13a34e06 318static void drop_user_return_notifiers(void)
3548bab5 319{
013f6a5d
MT		 320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 322
323 if (smsr->registered)
324 kvm_on_user_return(&smsr->urn);
325}
326
6866b83e
CO		 327u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
328{
8a5a87d9 329 return vcpu->arch.apic_base;
6866b83e
CO		 330}
331EXPORT_SYMBOL_GPL(kvm_get_apic_base);
332
58871649
JM		 333enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
334{
335 return kvm_apic_mode(kvm_get_apic_base(vcpu));
336}
337EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
338
58cb628d
JK		 339int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
340{
58871649
JM		 341 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
342 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 343 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
344 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 345
58871649 346 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 347 return 1;
58871649
JM		 348 if (!msr_info->host_initiated) {
349 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
350 return 1;
351 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
352 return 1;
353 }
58cb628d
JK		 354
355 kvm_lapic_set_base(vcpu, msr_info->data);
356 return 0;
6866b83e
CO		 357}
358EXPORT_SYMBOL_GPL(kvm_set_apic_base);
359
2605fc21 360asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 361{
362 /* Fault while not rebooting. We want the trace. */
363 BUG();
364}
365EXPORT_SYMBOL_GPL(kvm_spurious_fault);
366
3fd28fce
ED		 367#define EXCPT_BENIGN 0
368#define EXCPT_CONTRIBUTORY 1
369#define EXCPT_PF 2
370
371static int exception_class(int vector)
372{
373 switch (vector) {
374 case PF_VECTOR:
375 return EXCPT_PF;
376 case DE_VECTOR:
377 case TS_VECTOR:
378 case NP_VECTOR:
379 case SS_VECTOR:
380 case GP_VECTOR:
381 return EXCPT_CONTRIBUTORY;
382 default:
383 break;
384 }
385 return EXCPT_BENIGN;
386}
387
d6e8c854
NA		 388#define EXCPT_FAULT 0
389#define EXCPT_TRAP 1
390#define EXCPT_ABORT 2
391#define EXCPT_INTERRUPT 3
392
393static int exception_type(int vector)
394{
395 unsigned int mask;
396
397 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
398 return EXCPT_INTERRUPT;
399
400 mask = 1 << vector;
401
402 /* #DB is trap, as instruction watchpoints are handled elsewhere */
403 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
404 return EXCPT_TRAP;
405
406 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
407 return EXCPT_ABORT;
408
409 /* Reserved exceptions will result in fault */
410 return EXCPT_FAULT;
411}
412
da998b46
JM		 413void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
414{
415 unsigned nr = vcpu->arch.exception.nr;
416 bool has_payload = vcpu->arch.exception.has_payload;
417 unsigned long payload = vcpu->arch.exception.payload;
418
419 if (!has_payload)
420 return;
421
422 switch (nr) {
f10c729f
JM		 423 case DB_VECTOR:
424 /*
425 * "Certain debug exceptions may clear bit 0-3. The
426 * remaining contents of the DR6 register are never
427 * cleared by the processor".
428 */
429 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
430 /*
431 * DR6.RTM is set by all #DB exceptions that don't clear it.
432 */
433 vcpu->arch.dr6 |= DR6_RTM;
434 vcpu->arch.dr6 |= payload;
435 /*
436 * Bit 16 should be set in the payload whenever the #DB
437 * exception should clear DR6.RTM. This makes the payload
438 * compatible with the pending debug exceptions under VMX.
439 * Though not currently documented in the SDM, this also
440 * makes the payload compatible with the exit qualification
441 * for #DB exceptions under VMX.
442 */
443 vcpu->arch.dr6 ^= payload & DR6_RTM;
444 break;
da998b46
JM		 445 case PF_VECTOR:
446 vcpu->arch.cr2 = payload;
447 break;
448 }
449
450 vcpu->arch.exception.has_payload = false;
451 vcpu->arch.exception.payload = 0;
452}
453EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
454
3fd28fce 455static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 456 unsigned nr, bool has_error, u32 error_code,
91e86d22 457 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 458{
459 u32 prev_nr;
460 int class1, class2;
461
3842d135
AK		 462 kvm_make_request(KVM_REQ_EVENT, vcpu);
463
664f8e26 464 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 465 queue:
3ffb2468
NA		 466 if (has_error && !is_protmode(vcpu))
467 has_error = false;
664f8e26
WL		 468 if (reinject) {
469 /*
470 * On vmentry, vcpu->arch.exception.pending is only
471 * true if an event injection was blocked by
472 * nested_run_pending. In that case, however,
473 * vcpu_enter_guest requests an immediate exit,
474 * and the guest shouldn't proceed far enough to
475 * need reinjection.
476 */
477 WARN_ON_ONCE(vcpu->arch.exception.pending);
478 vcpu->arch.exception.injected = true;
91e86d22
JM		 479 if (WARN_ON_ONCE(has_payload)) {
480 /*
481 * A reinjected event has already
482 * delivered its payload.
483 */
484 has_payload = false;
485 payload = 0;
486 }
664f8e26
WL		 487 } else {
488 vcpu->arch.exception.pending = true;
489 vcpu->arch.exception.injected = false;
490 }
3fd28fce
ED		 491 vcpu->arch.exception.has_error_code = has_error;
492 vcpu->arch.exception.nr = nr;
493 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 494 vcpu->arch.exception.has_payload = has_payload;
495 vcpu->arch.exception.payload = payload;
da998b46
JM		 496 /*
497 * In guest mode, payload delivery should be deferred,
498 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 499 * CR2 is modified (or intercept #DB before DR6 is
500 * modified under nVMX). However, for ABI
501 * compatibility with KVM_GET_VCPU_EVENTS and
502 * KVM_SET_VCPU_EVENTS, we can't delay payload
503 * delivery unless userspace has enabled this
504 * functionality via the per-VM capability,
505 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 506 */
507 if (!vcpu->kvm->arch.exception_payload_enabled ||
508 !is_guest_mode(vcpu))
509 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 510 return;
511 }
512
513 /* to check exception */
514 prev_nr = vcpu->arch.exception.nr;
515 if (prev_nr == DF_VECTOR) {
516 /* triple fault -> shutdown */
a8eeb04a 517 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 518 return;
519 }
520 class1 = exception_class(prev_nr);
521 class2 = exception_class(nr);
522 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
523 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 524 /*
525 * Generate double fault per SDM Table 5-5. Set
526 * exception.pending = true so that the double fault
527 * can trigger a nested vmexit.
528 */
3fd28fce 529 vcpu->arch.exception.pending = true;
664f8e26 530 vcpu->arch.exception.injected = false;
3fd28fce
ED		 531 vcpu->arch.exception.has_error_code = true;
532 vcpu->arch.exception.nr = DF_VECTOR;
533 vcpu->arch.exception.error_code = 0;
c851436a
JM		 534 vcpu->arch.exception.has_payload = false;
535 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 536 } else
537 /* replace previous exception with a new one in a hope
538 that instruction re-execution will regenerate lost
539 exception */
540 goto queue;
541}
542
298101da
AK		 543void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
544{
91e86d22 545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 546}
547EXPORT_SYMBOL_GPL(kvm_queue_exception);
548
ce7ddec4
JR		 549void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
550{
91e86d22 551 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 552}
553EXPORT_SYMBOL_GPL(kvm_requeue_exception);
554
f10c729f
JM		 555static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
556 unsigned long payload)
557{
558 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
559}
560
da998b46
JM		 561static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
562 u32 error_code, unsigned long payload)
563{
564 kvm_multiple_exception(vcpu, nr, true, error_code,
565 true, payload, false);
566}
567
6affcbed 568int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 569{
db8fcefa
AP		 570 if (err)
571 kvm_inject_gp(vcpu, 0);
572 else
6affcbed
KH		 573 return kvm_skip_emulated_instruction(vcpu);
574
575 return 1;
db8fcefa
AP		 576}
577EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 578
6389ee94 579void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 580{
581 ++vcpu->stat.pf_guest;
adfe20fb
WL		 582 vcpu->arch.exception.nested_apf =
583 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 584 if (vcpu->arch.exception.nested_apf) {
adfe20fb 585 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 586 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
587 } else {
588 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
589 fault->address);
590 }
c3c91fee 591}
27d6c865 592EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 593
ef54bcfe 594static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 595{
6389ee94
AK		 596 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
597 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 598 else
44dd3ffa 599 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 600
601 return fault->nested_page_fault;
d4f8cf66
JR		 602}
603
3419ffc8
SY		 604void kvm_inject_nmi(struct kvm_vcpu *vcpu)
605{
7460fb4a
AK		 606 atomic_inc(&vcpu->arch.nmi_queued);
607 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 608}
609EXPORT_SYMBOL_GPL(kvm_inject_nmi);
610
298101da
AK		 611void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
612{
91e86d22 613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 614}
615EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
616
ce7ddec4
JR		 617void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
618{
91e86d22 619 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 620}
621EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
622
0a79b009
AK		 623/*
624 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
625 * a #GP and return false.
626 */
627bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 628{
0a79b009
AK		 629 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
630 return true;
631 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
632 return false;
298101da 633}
0a79b009 634EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 635
16f8a6f9
NA		 636bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
637{
638 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
639 return true;
640
641 kvm_queue_exception(vcpu, UD_VECTOR);
642 return false;
643}
644EXPORT_SYMBOL_GPL(kvm_require_dr);
645
ec92fe44
JR		 646/*
647 * This function will be used to read from the physical memory of the currently
54bf36aa 648 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 649 * can read from guest physical or from the guest's guest physical memory.
650 */
651int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
652 gfn_t ngfn, void *data, int offset, int len,
653 u32 access)
654{
54987b7a 655 struct x86_exception exception;
ec92fe44
JR		 656 gfn_t real_gfn;
657 gpa_t ngpa;
658
659 ngpa = gfn_to_gpa(ngfn);
54987b7a 660 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 661 if (real_gfn == UNMAPPED_GVA)
662 return -EFAULT;
663
664 real_gfn = gpa_to_gfn(real_gfn);
665
54bf36aa 666 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 667}
668EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
669
69b0049a 670static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 671 void *data, int offset, int len, u32 access)
672{
673 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
674 data, offset, len, access);
675}
676
16cfacc8
SC		 677static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
678{
679 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
680 rsvd_bits(1, 2);
681}
682
a03490ed 683/*
16cfacc8 684 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
a03490ed 685 */
ff03a073 686int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 687{
688 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
689 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
690 int i;
691 int ret;
ff03a073 692 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 693
ff03a073
JR		 694 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
695 offset * sizeof(u64), sizeof(pdpte),
696 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 697 if (ret < 0) {
698 ret = 0;
699 goto out;
700 }
701 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 702 if ((pdpte[i] & PT_PRESENT_MASK) &&
16cfacc8 703 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
a03490ed
CO		 704 ret = 0;
705 goto out;
706 }
707 }
708 ret = 1;
709
ff03a073 710 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 711 __set_bit(VCPU_EXREG_PDPTR,
712 (unsigned long *)&vcpu->arch.regs_avail);
713 __set_bit(VCPU_EXREG_PDPTR,
714 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 715out:
a03490ed
CO		 716
717 return ret;
718}
cc4b6871 719EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 720
9ed38ffa 721bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 722{
ff03a073 723 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 724 bool changed = true;
3d06b8bf
JR		 725 int offset;
726 gfn_t gfn;
d835dfec
AK		 727 int r;
728
bf03d4f9 729 if (!is_pae_paging(vcpu))
d835dfec
AK		 730 return false;
731
6de4f3ad
AK		 732 if (!test_bit(VCPU_EXREG_PDPTR,
733 (unsigned long *)&vcpu->arch.regs_avail))
734 return true;
735
a512177e
PB		 736 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
737 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 738 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
739 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 740 if (r < 0)
741 goto out;
ff03a073 742 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 743out:
d835dfec
AK		 744
745 return changed;
746}
9ed38ffa 747EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 748
49a9b07e 749int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 750{
aad82703 751 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 752 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 753
f9a48e6a
AK		 754 cr0 |= X86_CR0_ET;
755
ab344828 756#ifdef CONFIG_X86_64
0f12244f
GN		 757 if (cr0 & 0xffffffff00000000UL)
758 return 1;
ab344828
GN		 759#endif
760
761 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 762
0f12244f
GN		 763 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
764 return 1;
a03490ed 765
0f12244f
GN		 766 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
767 return 1;
a03490ed
CO		 768
769 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
770#ifdef CONFIG_X86_64
f6801dff 771 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 772 int cs_db, cs_l;
773
0f12244f
GN		 774 if (!is_pae(vcpu))
775 return 1;
a03490ed 776 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 777 if (cs_l)
778 return 1;
a03490ed
CO		 779 } else
780#endif
ff03a073 781 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 782 kvm_read_cr3(vcpu)))
0f12244f 783 return 1;
a03490ed
CO		 784 }
785
ad756a16
MJ		 786 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
787 return 1;
788
a03490ed 789 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 790
d170c419 791 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 792 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 793 kvm_async_pf_hash_reset(vcpu);
794 }
e5f3f027 795
aad82703
SY		 796 if ((cr0 ^ old_cr0) & update_bits)
797 kvm_mmu_reset_context(vcpu);
b18d5431 798
879ae188
LE		 799 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
800 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
801 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 802 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
803
0f12244f
GN		 804 return 0;
805}
2d3ad1f4 806EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 807
2d3ad1f4 808void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 809{
49a9b07e 810 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 811}
2d3ad1f4 812EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 813
1811d979 814void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 815{
816 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
817 !vcpu->guest_xcr0_loaded) {
818 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 819 if (vcpu->arch.xcr0 != host_xcr0)
820 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 821 vcpu->guest_xcr0_loaded = 1;
822 }
823}
1811d979 824EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
42bdf991 825
1811d979 826void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 827{
828 if (vcpu->guest_xcr0_loaded) {
829 if (vcpu->arch.xcr0 != host_xcr0)
830 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
831 vcpu->guest_xcr0_loaded = 0;
832 }
833}
1811d979 834EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
42bdf991 835
69b0049a 836static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 837{
56c103ec
LJ		 838 u64 xcr0 = xcr;
839 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 840 u64 valid_bits;
2acf923e
DC		 841
842 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
843 if (index != XCR_XFEATURE_ENABLED_MASK)
844 return 1;
d91cab78 845 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 846 return 1;
d91cab78 847 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 848 return 1;
46c34cb0
PB		 849
850 /*
851 * Do not allow the guest to set bits that we do not support
852 * saving. However, xcr0 bit 0 is always set, even if the
853 * emulated CPU does not support XSAVE (see fx_init).
854 */
d91cab78 855 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 856 if (xcr0 & ~valid_bits)
2acf923e 857 return 1;
46c34cb0 858
d91cab78
DH		 859 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
860 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 861 return 1;
862
d91cab78
DH		 863 if (xcr0 & XFEATURE_MASK_AVX512) {
864 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 865 return 1;
d91cab78 866 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 867 return 1;
868 }
2acf923e 869 vcpu->arch.xcr0 = xcr0;
56c103ec 870
d91cab78 871 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 872 kvm_update_cpuid(vcpu);
2acf923e
DC		 873 return 0;
874}
875
876int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
877{
764bcbc5
Z		 878 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
879 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 880 kvm_inject_gp(vcpu, 0);
881 return 1;
882 }
883 return 0;
884}
885EXPORT_SYMBOL_GPL(kvm_set_xcr);
886
a83b29c6 887int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 888{
fc78f519 889 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 890 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 891 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 892
0f12244f
GN		 893 if (cr4 & CR4_RESERVED_BITS)
894 return 1;
a03490ed 895
d6321d49 896 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 897 return 1;
898
d6321d49 899 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 900 return 1;
901
d6321d49 902 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 903 return 1;
904
d6321d49 905 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 906 return 1;
907
d6321d49 908 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 909 return 1;
910
fd8cb433 911 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 912 return 1;
913
ae3e61e1
PB		 914 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
915 return 1;
916
a03490ed 917 if (is_long_mode(vcpu)) {
0f12244f
GN		 918 if (!(cr4 & X86_CR4_PAE))
919 return 1;
a2edf57f
AK		 920 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
921 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 922 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
923 kvm_read_cr3(vcpu)))
0f12244f
GN		 924 return 1;
925
ad756a16 926 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 927 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 928 return 1;
929
930 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
931 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
932 return 1;
933 }
934
5e1746d6 935 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 936 return 1;
a03490ed 937
ad756a16
MJ		 938 if (((cr4 ^ old_cr4) & pdptr_bits) ||
939 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 940 kvm_mmu_reset_context(vcpu);
0f12244f 941
b9baba86 942 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 943 kvm_update_cpuid(vcpu);
2acf923e 944
0f12244f
GN		 945 return 0;
946}
2d3ad1f4 947EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 948
2390218b 949int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 950{
ade61e28 951 bool skip_tlb_flush = false;
ac146235 952#ifdef CONFIG_X86_64
c19986fe
JS		 953 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
954
ade61e28 955 if (pcid_enabled) {
208320ba
JS		 956 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
957 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 958 }
ac146235 959#endif
9d88fca7 960
9f8fe504 961 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 962 if (!skip_tlb_flush) {
963 kvm_mmu_sync_roots(vcpu);
ade61e28 964 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 965 }
0f12244f 966 return 0;
d835dfec
AK		 967 }
968
d1cd3ce9 969 if (is_long_mode(vcpu) &&
a780a3ea 970 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9 971 return 1;
bf03d4f9
PB		 972 else if (is_pae_paging(vcpu) &&
973 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 974 return 1;
a03490ed 975
ade61e28 976 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 977 vcpu->arch.cr3 = cr3;
aff48baa 978 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 979
0f12244f
GN		 980 return 0;
981}
2d3ad1f4 982EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 983
eea1cff9 984int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 985{
0f12244f
GN		 986 if (cr8 & CR8_RESERVED_BITS)
987 return 1;
35754c98 988 if (lapic_in_kernel(vcpu))
a03490ed
CO		 989 kvm_lapic_set_tpr(vcpu, cr8);
990 else
ad312c7c 991 vcpu->arch.cr8 = cr8;
0f12244f
GN		 992 return 0;
993}
2d3ad1f4 994EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 995
2d3ad1f4 996unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 997{
35754c98 998 if (lapic_in_kernel(vcpu))
a03490ed
CO		 999 return kvm_lapic_get_cr8(vcpu);
1000 else
ad312c7c 1001 return vcpu->arch.cr8;
a03490ed 1002}
2d3ad1f4 1003EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 1004
ae561ede
NA		 1005static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1006{
1007 int i;
1008
1009 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1010 for (i = 0; i < KVM_NR_DB_REGS; i++)
1011 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1012 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1013 }
1014}
1015
73aaf249
JK		 1016static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1017{
1018 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1019 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1020}
1021
c8639010
JK		 1022static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1023{
1024 unsigned long dr7;
1025
1026 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1027 dr7 = vcpu->arch.guest_debug_dr7;
1028 else
1029 dr7 = vcpu->arch.dr7;
1030 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1031 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1032 if (dr7 & DR7_BP_EN_MASK)
1033 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1034}
1035
6f43ed01
NA		 1036static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1037{
1038 u64 fixed = DR6_FIXED_1;
1039
d6321d49 1040 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1041 fixed |= DR6_RTM;
1042 return fixed;
1043}
1044
338dbc97 1045static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1046{
1047 switch (dr) {
1048 case 0 ... 3:
1049 vcpu->arch.db[dr] = val;
1050 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1051 vcpu->arch.eff_db[dr] = val;
1052 break;
1053 case 4:
020df079
GN		 1054 /* fall through */
1055 case 6:
338dbc97
GN		 1056 if (val & 0xffffffff00000000ULL)
1057 return -1; /* #GP */
6f43ed01 1058 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1059 kvm_update_dr6(vcpu);
020df079
GN		 1060 break;
1061 case 5:
020df079
GN		 1062 /* fall through */
1063 default: /* 7 */
338dbc97
GN		 1064 if (val & 0xffffffff00000000ULL)
1065 return -1; /* #GP */
020df079 1066 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1067 kvm_update_dr7(vcpu);
020df079
GN		 1068 break;
1069 }
1070
1071 return 0;
1072}
338dbc97
GN		 1073
1074int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1075{
16f8a6f9 1076 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1077 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1078 return 1;
1079 }
1080 return 0;
338dbc97 1081}
020df079
GN		 1082EXPORT_SYMBOL_GPL(kvm_set_dr);
1083
16f8a6f9 1084int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1085{
1086 switch (dr) {
1087 case 0 ... 3:
1088 *val = vcpu->arch.db[dr];
1089 break;
1090 case 4:
020df079
GN		 1091 /* fall through */
1092 case 6:
73aaf249
JK		 1093 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1094 *val = vcpu->arch.dr6;
1095 else
1096 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1097 break;
1098 case 5:
020df079
GN		 1099 /* fall through */
1100 default: /* 7 */
1101 *val = vcpu->arch.dr7;
1102 break;
1103 }
338dbc97
GN		 1104 return 0;
1105}
020df079
GN		 1106EXPORT_SYMBOL_GPL(kvm_get_dr);
1107
022cd0e8
AK		 1108bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1109{
de3cd117 1110 u32 ecx = kvm_rcx_read(vcpu);
022cd0e8
AK		 1111 u64 data;
1112 int err;
1113
c6702c9d 1114 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1115 if (err)
1116 return err;
de3cd117
SC		 1117 kvm_rax_write(vcpu, (u32)data);
1118 kvm_rdx_write(vcpu, data >> 32);
022cd0e8
AK		 1119 return err;
1120}
1121EXPORT_SYMBOL_GPL(kvm_rdpmc);
1122
043405e1
CO		 1123/*
1124 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1125 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1126 *
1127 * This list is modified at module load time to reflect the
e3267cbb 1128 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1129 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1130 * may depend on host virtualization features rather than host cpu features.
043405e1 1131 */
e3267cbb 1132
043405e1
CO		 1133static u32 msrs_to_save[] = {
1134 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1135 MSR_STAR,
043405e1
CO		 1136#ifdef CONFIG_X86_64
1137 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1138#endif
b3897a49 1139 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1140 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
2bdb76c0 1141 MSR_IA32_SPEC_CTRL,
bf8c55d8
CP		 1142 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1143 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1144 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1145 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1146 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1147 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
e2ada66e
JM		 1148 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1149 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1150 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1151 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1152 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1153 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1154 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1155 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1156 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1157 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1158 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1159 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1160 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1161 MSR_ARCH_PERFMON_PERFCTR0 + 18, MSR_ARCH_PERFMON_PERFCTR0 + 19,
1162 MSR_ARCH_PERFMON_PERFCTR0 + 20, MSR_ARCH_PERFMON_PERFCTR0 + 21,
1163 MSR_ARCH_PERFMON_PERFCTR0 + 22, MSR_ARCH_PERFMON_PERFCTR0 + 23,
1164 MSR_ARCH_PERFMON_PERFCTR0 + 24, MSR_ARCH_PERFMON_PERFCTR0 + 25,
1165 MSR_ARCH_PERFMON_PERFCTR0 + 26, MSR_ARCH_PERFMON_PERFCTR0 + 27,
1166 MSR_ARCH_PERFMON_PERFCTR0 + 28, MSR_ARCH_PERFMON_PERFCTR0 + 29,
1167 MSR_ARCH_PERFMON_PERFCTR0 + 30, MSR_ARCH_PERFMON_PERFCTR0 + 31,
1168 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1169 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1170 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1171 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1172 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1173 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1174 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1175 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1176 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1177 MSR_ARCH_PERFMON_EVENTSEL0 + 18, MSR_ARCH_PERFMON_EVENTSEL0 + 19,
1178 MSR_ARCH_PERFMON_EVENTSEL0 + 20, MSR_ARCH_PERFMON_EVENTSEL0 + 21,
1179 MSR_ARCH_PERFMON_EVENTSEL0 + 22, MSR_ARCH_PERFMON_EVENTSEL0 + 23,
1180 MSR_ARCH_PERFMON_EVENTSEL0 + 24, MSR_ARCH_PERFMON_EVENTSEL0 + 25,
1181 MSR_ARCH_PERFMON_EVENTSEL0 + 26, MSR_ARCH_PERFMON_EVENTSEL0 + 27,
1182 MSR_ARCH_PERFMON_EVENTSEL0 + 28, MSR_ARCH_PERFMON_EVENTSEL0 + 29,
1183 MSR_ARCH_PERFMON_EVENTSEL0 + 30, MSR_ARCH_PERFMON_EVENTSEL0 + 31,
043405e1
CO		 1184};
1185
1186static unsigned num_msrs_to_save;
1187
62ef68bb
PB		 1188static u32 emulated_msrs[] = {
1189 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1190 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1191 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1192 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1193 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1194 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1195 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1196 HV_X64_MSR_RESET,
11c4b1ca 1197 HV_X64_MSR_VP_INDEX,
9eec50b8 1198 HV_X64_MSR_VP_RUNTIME,
5c919412 1199 HV_X64_MSR_SCONTROL,
1f4b34f8 1200 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1201 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1202 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1203 HV_X64_MSR_TSC_EMULATION_STATUS,
1204
1205 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1206 MSR_KVM_PV_EOI_EN,
1207
ba904635 1208 MSR_IA32_TSC_ADJUST,
a3e06bbe 1209 MSR_IA32_TSCDEADLINE,
2bdb76c0 1210 MSR_IA32_ARCH_CAPABILITIES,
043405e1 1211 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1212 MSR_IA32_MCG_STATUS,
1213 MSR_IA32_MCG_CTL,
c45dcc71 1214 MSR_IA32_MCG_EXT_CTL,
64d60670 1215 MSR_IA32_SMBASE,
52797bf9 1216 MSR_SMI_COUNT,
db2336a8
KH		 1217 MSR_PLATFORM_INFO,
1218 MSR_MISC_FEATURES_ENABLES,
bc226f07 1219 MSR_AMD64_VIRT_SPEC_CTRL,
6c6a2ab9 1220 MSR_IA32_POWER_CTL,
191c8137 1221
95c5c7c7
PB		 1222 /*
1223 * The following list leaves out MSRs whose values are determined
1224 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1225 * We always support the "true" VMX control MSRs, even if the host
1226 * processor does not, so I am putting these registers here rather
1227 * than in msrs_to_save.
1228 */
1229 MSR_IA32_VMX_BASIC,
1230 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1231 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1232 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1233 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1234 MSR_IA32_VMX_MISC,
1235 MSR_IA32_VMX_CR0_FIXED0,
1236 MSR_IA32_VMX_CR4_FIXED0,
1237 MSR_IA32_VMX_VMCS_ENUM,
1238 MSR_IA32_VMX_PROCBASED_CTLS2,
1239 MSR_IA32_VMX_EPT_VPID_CAP,
1240 MSR_IA32_VMX_VMFUNC,
1241
191c8137 1242 MSR_K7_HWCR,
2d5ba19b 1243 MSR_KVM_POLL_CONTROL,
043405e1
CO		 1244};
1245
62ef68bb
PB		 1246static unsigned num_emulated_msrs;
1247
801e459a
TL		 1248/*
1249 * List of msr numbers which are used to expose MSR-based features that
1250 * can be used by a hypervisor to validate requested CPU features.
1251 */
1252static u32 msr_based_features[] = {
1389309c
PB		 1253 MSR_IA32_VMX_BASIC,
1254 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1255 MSR_IA32_VMX_PINBASED_CTLS,
1256 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1257 MSR_IA32_VMX_PROCBASED_CTLS,
1258 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1259 MSR_IA32_VMX_EXIT_CTLS,
1260 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1261 MSR_IA32_VMX_ENTRY_CTLS,
1262 MSR_IA32_VMX_MISC,
1263 MSR_IA32_VMX_CR0_FIXED0,
1264 MSR_IA32_VMX_CR0_FIXED1,
1265 MSR_IA32_VMX_CR4_FIXED0,
1266 MSR_IA32_VMX_CR4_FIXED1,
1267 MSR_IA32_VMX_VMCS_ENUM,
1268 MSR_IA32_VMX_PROCBASED_CTLS2,
1269 MSR_IA32_VMX_EPT_VPID_CAP,
1270 MSR_IA32_VMX_VMFUNC,
1271
d1d93fa9 1272 MSR_F10H_DECFG,
518e7b94 1273 MSR_IA32_UCODE_REV,
cd283252 1274 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1275};
1276
1277static unsigned int num_msr_based_features;
1278
4d22c17c 1279static u64 kvm_get_arch_capabilities(void)
5b76a3cf 1280{
4d22c17c 1281 u64 data = 0;
5b76a3cf 1282
4d22c17c
XL		 1283 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1284 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
5b76a3cf
PB		 1285
1286 /*
1287 * If we're doing cache flushes (either "always" or "cond")
1288 * we will do one whenever the guest does a vmlaunch/vmresume.
1289 * If an outer hypervisor is doing the cache flush for us
1290 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1291 * capability to the guest too, and if EPT is disabled we're not
1292 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1293 * require a nested hypervisor to do a flush of its own.
1294 */
1295 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1296 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1297
0c54914d
PB		 1298 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1299 data |= ARCH_CAP_RDCL_NO;
1300 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1301 data |= ARCH_CAP_SSB_NO;
1302 if (!boot_cpu_has_bug(X86_BUG_MDS))
1303 data |= ARCH_CAP_MDS_NO;
1304
5b76a3cf
PB		 1305 return data;
1306}
5b76a3cf 1307
66421c1e
WL		 1308static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1309{
1310 switch (msr->index) {
cd283252 1311 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1312 msr->data = kvm_get_arch_capabilities();
1313 break;
1314 case MSR_IA32_UCODE_REV:
cd283252 1315 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1316 break;
66421c1e
WL		 1317 default:
1318 if (kvm_x86_ops->get_msr_feature(msr))
1319 return 1;
1320 }
1321 return 0;
1322}
1323
801e459a
TL		 1324static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1325{
1326 struct kvm_msr_entry msr;
66421c1e 1327 int r;
801e459a
TL		 1328
1329 msr.index = index;
66421c1e
WL		 1330 r = kvm_get_msr_feature(&msr);
1331 if (r)
1332 return r;
801e459a
TL		 1333
1334 *data = msr.data;
1335
1336 return 0;
1337}
1338
11988499 1339static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1340{
1b4d56b8 1341 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
11988499 1342 return false;
1b2fd70c 1343
1b4d56b8 1344 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
11988499 1345 return false;
d8017474 1346
0a629563
SC		 1347 if (efer & (EFER_LME | EFER_LMA) &&
1348 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1349 return false;
1350
1351 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1352 return false;
d8017474 1353
384bb783 1354 return true;
11988499
SC		 1355
1356}
1357bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1358{
1359 if (efer & efer_reserved_bits)
1360 return false;
1361
1362 return __kvm_valid_efer(vcpu, efer);
384bb783
JK		 1363}
1364EXPORT_SYMBOL_GPL(kvm_valid_efer);
1365
11988499 1366static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
384bb783
JK		 1367{
1368 u64 old_efer = vcpu->arch.efer;
11988499 1369 u64 efer = msr_info->data;
384bb783 1370
11988499 1371 if (efer & efer_reserved_bits)
66f61c92 1372 return 1;
384bb783 1373
11988499
SC		 1374 if (!msr_info->host_initiated) {
1375 if (!__kvm_valid_efer(vcpu, efer))
1376 return 1;
1377
1378 if (is_paging(vcpu) &&
1379 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1380 return 1;
1381 }
384bb783 1382
15c4a640 1383 efer &= ~EFER_LMA;
f6801dff 1384 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1385
a3d204e2
SY		 1386 kvm_x86_ops->set_efer(vcpu, efer);
1387
aad82703
SY		 1388 /* Update reserved bits */
1389 if ((efer ^ old_efer) & EFER_NX)
1390 kvm_mmu_reset_context(vcpu);
1391
b69e8cae 1392 return 0;
15c4a640
CO		 1393}
1394
f2b4b7dd
JR		 1395void kvm_enable_efer_bits(u64 mask)
1396{
1397 efer_reserved_bits &= ~mask;
1398}
1399EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1400
15c4a640 1401/*
f20935d8
SC		 1402 * Write @data into the MSR specified by @index. Select MSR specific fault
1403 * checks are bypassed if @host_initiated is %true.
15c4a640
CO		 1404 * Returns 0 on success, non-0 otherwise.
1405 * Assumes vcpu_load() was already called.
1406 */
f20935d8
SC		 1407static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1408 bool host_initiated)
15c4a640 1409{
f20935d8
SC		 1410 struct msr_data msr;
1411
1412 switch (index) {
854e8bb1
NA		 1413 case MSR_FS_BASE:
1414 case MSR_GS_BASE:
1415 case MSR_KERNEL_GS_BASE:
1416 case MSR_CSTAR:
1417 case MSR_LSTAR:
f20935d8 1418 if (is_noncanonical_address(data, vcpu))
854e8bb1
NA		 1419 return 1;
1420 break;
1421 case MSR_IA32_SYSENTER_EIP:
1422 case MSR_IA32_SYSENTER_ESP:
1423 /*
1424 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1425 * non-canonical address is written on Intel but not on
1426 * AMD (which ignores the top 32-bits, because it does
1427 * not implement 64-bit SYSENTER).
1428 *
1429 * 64-bit code should hence be able to write a non-canonical
1430 * value on AMD. Making the address canonical ensures that
1431 * vmentry does not fail on Intel after writing a non-canonical
1432 * value, and that something deterministic happens if the guest
1433 * invokes 64-bit SYSENTER.
1434 */
f20935d8 1435 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1436 }
f20935d8
SC		 1437
1438 msr.data = data;
1439 msr.index = index;
1440 msr.host_initiated = host_initiated;
1441
1442 return kvm_x86_ops->set_msr(vcpu, &msr);
15c4a640
CO		 1443}
1444
313a3dc7 1445/*
f20935d8
SC		 1446 * Read the MSR specified by @index into @data. Select MSR specific fault
1447 * checks are bypassed if @host_initiated is %true.
1448 * Returns 0 on success, non-0 otherwise.
1449 * Assumes vcpu_load() was already called.
313a3dc7 1450 */
f20935d8
SC		 1451static int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1452 bool host_initiated)
609e36d3
PB		 1453{
1454 struct msr_data msr;
f20935d8 1455 int ret;
609e36d3
PB		 1456
1457 msr.index = index;
f20935d8 1458 msr.host_initiated = host_initiated;
609e36d3 1459
f20935d8
SC		 1460 ret = kvm_x86_ops->get_msr(vcpu, &msr);
1461 if (!ret)
1462 *data = msr.data;
1463 return ret;
609e36d3
PB		 1464}
1465
f20935d8 1466int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
313a3dc7 1467{
f20935d8
SC		 1468 return __kvm_get_msr(vcpu, index, data, false);
1469}
1470EXPORT_SYMBOL_GPL(kvm_get_msr);
8fe8ab46 1471
f20935d8
SC		 1472int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1473{
1474 return __kvm_set_msr(vcpu, index, data, false);
1475}
1476EXPORT_SYMBOL_GPL(kvm_set_msr);
1477
1edce0a9
SC		 1478int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1479{
1480 u32 ecx = kvm_rcx_read(vcpu);
1481 u64 data;
1482
1483 if (kvm_get_msr(vcpu, ecx, &data)) {
1484 trace_kvm_msr_read_ex(ecx);
1485 kvm_inject_gp(vcpu, 0);
1486 return 1;
1487 }
1488
1489 trace_kvm_msr_read(ecx, data);
1490
1491 kvm_rax_write(vcpu, data & -1u);
1492 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1493 return kvm_skip_emulated_instruction(vcpu);
1494}
1495EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1496
1497int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1498{
1499 u32 ecx = kvm_rcx_read(vcpu);
1500 u64 data = kvm_read_edx_eax(vcpu);
1501
1502 if (kvm_set_msr(vcpu, ecx, data)) {
1503 trace_kvm_msr_write_ex(ecx, data);
1504 kvm_inject_gp(vcpu, 0);
1505 return 1;
1506 }
1507
1508 trace_kvm_msr_write(ecx, data);
1509 return kvm_skip_emulated_instruction(vcpu);
1510}
1511EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1512
f20935d8
SC		 1513/*
1514 * Adapt set_msr() to msr_io()'s calling convention
1515 */
1516static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1517{
1518 return __kvm_get_msr(vcpu, index, data, true);
1519}
1520
1521static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1522{
1523 return __kvm_set_msr(vcpu, index, *data, true);
313a3dc7
CO		 1524}
1525
16e8d74d
MT		 1526#ifdef CONFIG_X86_64
1527struct pvclock_gtod_data {
1528 seqcount_t seq;
1529
1530 struct { /* extract of a clocksource struct */
1531 int vclock_mode;
a5a1d1c2
TG		 1532 u64 cycle_last;
1533 u64 mask;
16e8d74d
MT		 1534 u32 mult;
1535 u32 shift;
1536 } clock;
1537
cbcf2dd3
TG		 1538 u64 boot_ns;
1539 u64 nsec_base;
55dd00a7 1540 u64 wall_time_sec;
16e8d74d
MT		 1541};
1542
1543static struct pvclock_gtod_data pvclock_gtod_data;
1544
1545static void update_pvclock_gtod(struct timekeeper *tk)
1546{
1547 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1548 u64 boot_ns;
1549
876e7881 1550 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1551
1552 write_seqcount_begin(&vdata->seq);
1553
1554 /* copy pvclock gtod data */
876e7881
PZ		 1555 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1556 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1557 vdata->clock.mask = tk->tkr_mono.mask;
1558 vdata->clock.mult = tk->tkr_mono.mult;
1559 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1560
cbcf2dd3 1561 vdata->boot_ns = boot_ns;
876e7881 1562 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1563
55dd00a7
MT		 1564 vdata->wall_time_sec = tk->xtime_sec;
1565
16e8d74d
MT		 1566 write_seqcount_end(&vdata->seq);
1567}
1568#endif
1569
bab5bb39
NK		 1570void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1571{
bab5bb39 1572 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
4d151bf3 1573 kvm_vcpu_kick(vcpu);
bab5bb39 1574}
16e8d74d 1575
18068523
GOC		 1576static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1577{
9ed3c444
AK		 1578 int version;
1579 int r;
50d0a0f9 1580 struct pvclock_wall_clock wc;
87aeb54f 1581 struct timespec64 boot;
18068523
GOC		 1582
1583 if (!wall_clock)
1584 return;
1585
9ed3c444
AK		 1586 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1587 if (r)
1588 return;
1589
1590 if (version & 1)
1591 ++version; /* first time write, random junk */
1592
1593 ++version;
18068523 1594
1dab1345
NK		 1595 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1596 return;
18068523 1597
50d0a0f9
GH		 1598 /*
1599 * The guest calculates current wall clock time by adding
34c238a1 1600 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1601 * wall clock specified here. guest system time equals host
1602 * system time for us, thus we must fill in host boot time here.
1603 */
87aeb54f 1604 getboottime64(&boot);
50d0a0f9 1605
4b648665 1606 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1607 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1608 boot = timespec64_sub(boot, ts);
4b648665 1609 }
87aeb54f 1610 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1611 wc.nsec = boot.tv_nsec;
1612 wc.version = version;
18068523
GOC		 1613
1614 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1615
1616 version++;
1617 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1618}
1619
50d0a0f9
GH		 1620static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1621{
b51012de
PB		 1622 do_shl32_div32(dividend, divisor);
1623 return dividend;
50d0a0f9
GH		 1624}
1625
3ae13faa 1626static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1627 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1628{
5f4e3f88 1629 uint64_t scaled64;
50d0a0f9
GH		 1630 int32_t shift = 0;
1631 uint64_t tps64;
1632 uint32_t tps32;
1633
3ae13faa
PB		 1634 tps64 = base_hz;
1635 scaled64 = scaled_hz;
50933623 1636 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1637 tps64 >>= 1;
1638 shift--;
1639 }
1640
1641 tps32 = (uint32_t)tps64;
50933623
JK		 1642 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1643 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1644 scaled64 >>= 1;
1645 else
1646 tps32 <<= 1;
50d0a0f9
GH		 1647 shift++;
1648 }
1649
5f4e3f88
ZA		 1650 *pshift = shift;
1651 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9
GH		 1652}
1653
d828199e 1654#ifdef CONFIG_X86_64
16e8d74d 1655static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1656#endif
16e8d74d 1657
c8076604 1658static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1659static unsigned long max_tsc_khz;
c8076604 1660
cc578287 1661static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1662{
cc578287
ZA		 1663 u64 v = (u64)khz * (1000000 + ppm);
1664 do_div(v, 1000000);
1665 return v;
1e993611
JR		 1666}
1667
381d585c
HZ		 1668static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1669{
1670 u64 ratio;
1671
1672 /* Guest TSC same frequency as host TSC? */
1673 if (!scale) {
1674 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1675 return 0;
1676 }
1677
1678 /* TSC scaling supported? */
1679 if (!kvm_has_tsc_control) {
1680 if (user_tsc_khz > tsc_khz) {
1681 vcpu->arch.tsc_catchup = 1;
1682 vcpu->arch.tsc_always_catchup = 1;
1683 return 0;
1684 } else {
3f16a5c3 1685 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
381d585c
HZ		 1686 return -1;
1687 }
1688 }
1689
1690 /* TSC scaling required - calculate ratio */
1691 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1692 user_tsc_khz, tsc_khz);
1693
1694 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
3f16a5c3
PB		 1695 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1696 user_tsc_khz);
381d585c
HZ		 1697 return -1;
1698 }
1699
1700 vcpu->arch.tsc_scaling_ratio = ratio;
1701 return 0;
1702}
1703
4941b8cb 1704static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1705{
cc578287
ZA		 1706 u32 thresh_lo, thresh_hi;
1707 int use_scaling = 0;
217fc9cf 1708
03ba32ca 1709 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1710 if (user_tsc_khz == 0) {
ad721883
HZ		 1711 /* set tsc_scaling_ratio to a safe value */
1712 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1713 return -1;
ad721883 1714 }
03ba32ca 1715
c285545f 1716 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1717 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1718 &vcpu->arch.virtual_tsc_shift,
1719 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1720 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1721
1722 /*
1723 * Compute the variation in TSC rate which is acceptable
1724 * within the range of tolerance and decide if the
1725 * rate being applied is within that bounds of the hardware
1726 * rate. If so, no scaling or compensation need be done.
1727 */
1728 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1729 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1730 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1731 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1732 use_scaling = 1;
1733 }
4941b8cb 1734 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1735}
1736
1737static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1738{
e26101b1 1739 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1740 vcpu->arch.virtual_tsc_mult,
1741 vcpu->arch.virtual_tsc_shift);
e26101b1 1742 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1743 return tsc;
1744}
1745
b0c39dc6
VK		 1746static inline int gtod_is_based_on_tsc(int mode)
1747{
1748 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1749}
1750
69b0049a 1751static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1752{
1753#ifdef CONFIG_X86_64
1754 bool vcpus_matched;
b48aa97e
MT		 1755 struct kvm_arch *ka = &vcpu->kvm->arch;
1756 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1757
1758 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1759 atomic_read(&vcpu->kvm->online_vcpus));
1760
7f187922
MT		 1761 /*
1762 * Once the masterclock is enabled, always perform request in
1763 * order to update it.
1764 *
1765 * In order to enable masterclock, the host clocksource must be TSC
1766 * and the vcpus need to have matched TSCs. When that happens,
1767 * perform request to enable masterclock.
1768 */
1769 if (ka->use_master_clock ||
b0c39dc6 1770 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1771 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1772
1773 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1774 atomic_read(&vcpu->kvm->online_vcpus),
1775 ka->use_master_clock, gtod->clock.vclock_mode);
1776#endif
1777}
1778
ba904635
WA		 1779static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1780{
e79f245d 1781 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1782 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1783}
1784
35181e86
HZ		 1785/*
1786 * Multiply tsc by a fixed point number represented by ratio.
1787 *
1788 * The most significant 64-N bits (mult) of ratio represent the
1789 * integral part of the fixed point number; the remaining N bits
1790 * (frac) represent the fractional part, ie. ratio represents a fixed
1791 * point number (mult + frac * 2^(-N)).
1792 *
1793 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1794 */
1795static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1796{
1797 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1798}
1799
1800u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1801{
1802 u64 _tsc = tsc;
1803 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1804
1805 if (ratio != kvm_default_tsc_scaling_ratio)
1806 _tsc = __scale_tsc(ratio, tsc);
1807
1808 return _tsc;
1809}
1810EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1811
07c1419a
HZ		 1812static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1813{
1814 u64 tsc;
1815
1816 tsc = kvm_scale_tsc(vcpu, rdtsc());
1817
1818 return target_tsc - tsc;
1819}
1820
4ba76538
HZ		 1821u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1822{
e79f245d
KA		 1823 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1824
1825 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1826}
1827EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1828
a545ab6a
LC		 1829static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1830{
326e7425 1831 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1832}
1833
b0c39dc6
VK		 1834static inline bool kvm_check_tsc_unstable(void)
1835{
1836#ifdef CONFIG_X86_64
1837 /*
1838 * TSC is marked unstable when we're running on Hyper-V,
1839 * 'TSC page' clocksource is good.
1840 */
1841 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1842 return false;
1843#endif
1844 return check_tsc_unstable();
1845}
1846
8fe8ab46 1847void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1848{
1849 struct kvm *kvm = vcpu->kvm;
f38e098f 1850 u64 offset, ns, elapsed;
99e3e30a 1851 unsigned long flags;
b48aa97e 1852 bool matched;
0d3da0d2 1853 bool already_matched;
8fe8ab46 1854 u64 data = msr->data;
c5e8ec8e 1855 bool synchronizing = false;
99e3e30a 1856
038f8c11 1857 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1858 offset = kvm_compute_tsc_offset(vcpu, data);
9285ec4c 1859 ns = ktime_get_boottime_ns();
f38e098f 1860 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1861
03ba32ca 1862 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1863 if (data == 0 && msr->host_initiated) {
1864 /*
1865 * detection of vcpu initialization -- need to sync
1866 * with other vCPUs. This particularly helps to keep
1867 * kvm_clock stable after CPU hotplug
1868 */
1869 synchronizing = true;
1870 } else {
1871 u64 tsc_exp = kvm->arch.last_tsc_write +
1872 nsec_to_cycles(vcpu, elapsed);
1873 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1874 /*
1875 * Special case: TSC write with a small delta (1 second)
1876 * of virtual cycle time against real time is
1877 * interpreted as an attempt to synchronize the CPU.
1878 */
1879 synchronizing = data < tsc_exp + tsc_hz &&
1880 data + tsc_hz > tsc_exp;
1881 }
c5e8ec8e 1882 }
f38e098f
ZA		 1883
1884 /*
5d3cb0f6
ZA		 1885 * For a reliable TSC, we can match TSC offsets, and for an unstable
1886 * TSC, we add elapsed time in this computation. We could let the
1887 * compensation code attempt to catch up if we fall behind, but
1888 * it's better to try to match offsets from the beginning.
1889 */
c5e8ec8e 1890 if (synchronizing &&
5d3cb0f6 1891 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1892 if (!kvm_check_tsc_unstable()) {
e26101b1 1893 offset = kvm->arch.cur_tsc_offset;
f38e098f 1894 } else {
857e4099 1895 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1896 data += delta;
07c1419a 1897 offset = kvm_compute_tsc_offset(vcpu, data);
f38e098f 1898 }
b48aa97e 1899 matched = true;
0d3da0d2 1900 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1901 } else {
1902 /*
1903 * We split periods of matched TSC writes into generations.
1904 * For each generation, we track the original measured
1905 * nanosecond time, offset, and write, so if TSCs are in
1906 * sync, we can match exact offset, and if not, we can match
4a969980 1907 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1908 *
1909 * These values are tracked in kvm->arch.cur_xxx variables.
1910 */
1911 kvm->arch.cur_tsc_generation++;
1912 kvm->arch.cur_tsc_nsec = ns;
1913 kvm->arch.cur_tsc_write = data;
1914 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1915 matched = false;
f38e098f 1916 }
e26101b1
ZA		 1917
1918 /*
1919 * We also track th most recent recorded KHZ, write and time to
1920 * allow the matching interval to be extended at each write.
1921 */
f38e098f
ZA		 1922 kvm->arch.last_tsc_nsec = ns;
1923 kvm->arch.last_tsc_write = data;
5d3cb0f6 1924 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1925
b183aa58 1926 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1927
1928 /* Keep track of which generation this VCPU has synchronized to */
1929 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1930 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1931 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1932
d6321d49 1933 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1934 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1935
a545ab6a 1936 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1937 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1938
1939 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1940 if (!matched) {
b48aa97e 1941 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1942 } else if (!already_matched) {
1943 kvm->arch.nr_vcpus_matched_tsc++;
1944 }
b48aa97e
MT		 1945
1946 kvm_track_tsc_matching(vcpu);
1947 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1948}
e26101b1 1949
99e3e30a
ZA		 1950EXPORT_SYMBOL_GPL(kvm_write_tsc);
1951
58ea6767
HZ		 1952static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1953 s64 adjustment)
1954{
326e7425
LS		 1955 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1956 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 1957}
1958
1959static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1960{
1961 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1962 WARN_ON(adjustment < 0);
1963 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1964 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1965}
1966
d828199e
MT		 1967#ifdef CONFIG_X86_64
1968
a5a1d1c2 1969static u64 read_tsc(void)
d828199e 1970{
a5a1d1c2 1971 u64 ret = (u64)rdtsc_ordered();
03b9730b 1972 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1973
1974 if (likely(ret >= last))
1975 return ret;
1976
1977 /*
1978 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1979 * predictable (it's just a function of time and the likely is
d828199e
MT		 1980 * very likely) and there's a data dependence, so force GCC
1981 * to generate a branch instead. I don't barrier() because
1982 * we don't actually need a barrier, and if this function
1983 * ever gets inlined it will generate worse code.
1984 */
1985 asm volatile ("");
1986 return last;
1987}
1988
b0c39dc6 1989static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1990{
1991 long v;
1992 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1993 u64 tsc_pg_val;
1994
1995 switch (gtod->clock.vclock_mode) {
1996 case VCLOCK_HVCLOCK:
1997 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1998 tsc_timestamp);
1999 if (tsc_pg_val != U64_MAX) {
2000 /* TSC page valid */
2001 *mode = VCLOCK_HVCLOCK;
2002 v = (tsc_pg_val - gtod->clock.cycle_last) &
2003 gtod->clock.mask;
2004 } else {
2005 /* TSC page invalid */
2006 *mode = VCLOCK_NONE;
2007 }
2008 break;
2009 case VCLOCK_TSC:
2010 *mode = VCLOCK_TSC;
2011 *tsc_timestamp = read_tsc();
2012 v = (*tsc_timestamp - gtod->clock.cycle_last) &
2013 gtod->clock.mask;
2014 break;
2015 default:
2016 *mode = VCLOCK_NONE;
2017 }
d828199e 2018
b0c39dc6
VK		 2019 if (*mode == VCLOCK_NONE)
2020 *tsc_timestamp = v = 0;
d828199e 2021
d828199e
MT		 2022 return v * gtod->clock.mult;
2023}
2024
b0c39dc6 2025static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 2026{
cbcf2dd3 2027 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 2028 unsigned long seq;
d828199e 2029 int mode;
cbcf2dd3 2030 u64 ns;
d828199e 2031
d828199e
MT		 2032 do {
2033 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 2034 ns = gtod->nsec_base;
b0c39dc6 2035 ns += vgettsc(tsc_timestamp, &mode);
d828199e 2036 ns >>= gtod->clock.shift;
cbcf2dd3 2037 ns += gtod->boot_ns;
d828199e 2038 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 2039 *t = ns;
d828199e
MT		 2040
2041 return mode;
2042}
2043
899a31f5 2044static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 2045{
2046 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2047 unsigned long seq;
2048 int mode;
2049 u64 ns;
2050
2051 do {
2052 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 2053 ts->tv_sec = gtod->wall_time_sec;
2054 ns = gtod->nsec_base;
b0c39dc6 2055 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 2056 ns >>= gtod->clock.shift;
2057 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2058
2059 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2060 ts->tv_nsec = ns;
2061
2062 return mode;
2063}
2064
b0c39dc6
VK		 2065/* returns true if host is using TSC based clocksource */
2066static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 2067{
d828199e 2068 /* checked again under seqlock below */
b0c39dc6 2069 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 2070 return false;
2071
b0c39dc6
VK		 2072 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
2073 tsc_timestamp));
d828199e 2074}
55dd00a7 2075
b0c39dc6 2076/* returns true if host is using TSC based clocksource */
899a31f5 2077static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 2078 u64 *tsc_timestamp)
55dd00a7
MT		 2079{
2080 /* checked again under seqlock below */
b0c39dc6 2081 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 2082 return false;
2083
b0c39dc6 2084 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 2085}
d828199e
MT		 2086#endif
2087
2088/*
2089 *
b48aa97e
MT		 2090 * Assuming a stable TSC across physical CPUS, and a stable TSC
2091 * across virtual CPUs, the following condition is possible.
2092 * Each numbered line represents an event visible to both
d828199e
MT		 2093 * CPUs at the next numbered event.
2094 *
2095 * "timespecX" represents host monotonic time. "tscX" represents
2096 * RDTSC value.
2097 *
2098 * VCPU0 on CPU0 | VCPU1 on CPU1
2099 *
2100 * 1. read timespec0,tsc0
2101 * 2. | timespec1 = timespec0 + N
2102 * | tsc1 = tsc0 + M
2103 * 3. transition to guest | transition to guest
2104 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2105 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2106 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2107 *
2108 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2109 *
2110 * - ret0 < ret1
2111 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2112 * ...
2113 * - 0 < N - M => M < N
2114 *
2115 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2116 * always the case (the difference between two distinct xtime instances
2117 * might be smaller then the difference between corresponding TSC reads,
2118 * when updating guest vcpus pvclock areas).
2119 *
2120 * To avoid that problem, do not allow visibility of distinct
2121 * system_timestamp/tsc_timestamp values simultaneously: use a master
2122 * copy of host monotonic time values. Update that master copy
2123 * in lockstep.
2124 *
b48aa97e 2125 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 2126 *
2127 */
2128
2129static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2130{
2131#ifdef CONFIG_X86_64
2132 struct kvm_arch *ka = &kvm->arch;
2133 int vclock_mode;
b48aa97e
MT		 2134 bool host_tsc_clocksource, vcpus_matched;
2135
2136 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2137 atomic_read(&kvm->online_vcpus));
d828199e
MT		 2138
2139 /*
2140 * If the host uses TSC clock, then passthrough TSC as stable
2141 * to the guest.
2142 */
b48aa97e 2143 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 2144 &ka->master_kernel_ns,
2145 &ka->master_cycle_now);
2146
16a96021 2147 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 2148 && !ka->backwards_tsc_observed
54750f2c 2149 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 2150
d828199e
MT		 2151 if (ka->use_master_clock)
2152 atomic_set(&kvm_guest_has_master_clock, 1);
2153
2154 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 2155 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2156 vcpus_matched);
d828199e
MT		 2157#endif
2158}
2159
2860c4b1
PB		 2160void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2161{
2162 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2163}
2164
2e762ff7
MT		 2165static void kvm_gen_update_masterclock(struct kvm *kvm)
2166{
2167#ifdef CONFIG_X86_64
2168 int i;
2169 struct kvm_vcpu *vcpu;
2170 struct kvm_arch *ka = &kvm->arch;
2171
2172 spin_lock(&ka->pvclock_gtod_sync_lock);
2173 kvm_make_mclock_inprogress_request(kvm);
2174 /* no guest entries from this point */
2175 pvclock_update_vm_gtod_copy(kvm);
2176
2177 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2178 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2179
2180 /* guest entries allowed */
2181 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2182 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2183
2184 spin_unlock(&ka->pvclock_gtod_sync_lock);
2185#endif
2186}
2187
e891a32e 2188u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2189{
108b249c 2190 struct kvm_arch *ka = &kvm->arch;
8b953440 2191 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2192 u64 ret;
108b249c 2193
8b953440
PB		 2194 spin_lock(&ka->pvclock_gtod_sync_lock);
2195 if (!ka->use_master_clock) {
2196 spin_unlock(&ka->pvclock_gtod_sync_lock);
9285ec4c 2197 return ktime_get_boottime_ns() + ka->kvmclock_offset;
108b249c
PB		 2198 }
2199
8b953440
PB		 2200 hv_clock.tsc_timestamp = ka->master_cycle_now;
2201 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2202 spin_unlock(&ka->pvclock_gtod_sync_lock);
2203
e2c2206a
WL		 2204 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2205 get_cpu();
2206
e70b57a6
WL		 2207 if (__this_cpu_read(cpu_tsc_khz)) {
2208 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2209 &hv_clock.tsc_shift,
2210 &hv_clock.tsc_to_system_mul);
2211 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2212 } else
9285ec4c 2213 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2214
2215 put_cpu();
2216
2217 return ret;
108b249c
PB		 2218}
2219
0d6dd2ff
PB		 2220static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2221{
2222 struct kvm_vcpu_arch *vcpu = &v->arch;
2223 struct pvclock_vcpu_time_info guest_hv_clock;
2224
4e335d9e 2225 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2226 &guest_hv_clock, sizeof(guest_hv_clock))))
2227 return;
2228
2229 /* This VCPU is paused, but it's legal for a guest to read another
2230 * VCPU's kvmclock, so we really have to follow the specification where
2231 * it says that version is odd if data is being modified, and even after
2232 * it is consistent.
2233 *
2234 * Version field updates must be kept separate. This is because
2235 * kvm_write_guest_cached might use a "rep movs" instruction, and
2236 * writes within a string instruction are weakly ordered. So there
2237 * are three writes overall.
2238 *
2239 * As a small optimization, only write the version field in the first
2240 * and third write. The vcpu->pv_time cache is still valid, because the
2241 * version field is the first in the struct.
2242 */
2243 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2244
51c4b8bb
LA		 2245 if (guest_hv_clock.version & 1)
2246 ++guest_hv_clock.version; /* first time write, random junk */
2247
0d6dd2ff 2248 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2249 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2250 &vcpu->hv_clock,
2251 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2252
2253 smp_wmb();
2254
2255 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2256 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2257
2258 if (vcpu->pvclock_set_guest_stopped_request) {
2259 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2260 vcpu->pvclock_set_guest_stopped_request = false;
2261 }
2262
2263 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2264
4e335d9e
PB		 2265 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2266 &vcpu->hv_clock,
2267 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2268
2269 smp_wmb();
2270
2271 vcpu->hv_clock.version++;
4e335d9e
PB		 2272 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2273 &vcpu->hv_clock,
2274 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2275}
2276
34c238a1 2277static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2278{
78db6a50 2279 unsigned long flags, tgt_tsc_khz;
18068523 2280 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2281 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2282 s64 kernel_ns;
d828199e 2283 u64 tsc_timestamp, host_tsc;
51d59c6b 2284 u8 pvclock_flags;
d828199e
MT		 2285 bool use_master_clock;
2286
2287 kernel_ns = 0;
2288 host_tsc = 0;
18068523 2289
d828199e
MT		 2290 /*
2291 * If the host uses TSC clock, then passthrough TSC as stable
2292 * to the guest.
2293 */
2294 spin_lock(&ka->pvclock_gtod_sync_lock);
2295 use_master_clock = ka->use_master_clock;
2296 if (use_master_clock) {
2297 host_tsc = ka->master_cycle_now;
2298 kernel_ns = ka->master_kernel_ns;
2299 }
2300 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2301
2302 /* Keep irq disabled to prevent changes to the clock */
2303 local_irq_save(flags);
78db6a50
PB		 2304 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2305 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2306 local_irq_restore(flags);
2307 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2308 return 1;
2309 }
d828199e 2310 if (!use_master_clock) {
4ea1636b 2311 host_tsc = rdtsc();
9285ec4c 2312 kernel_ns = ktime_get_boottime_ns();
d828199e
MT		 2313 }
2314
4ba76538 2315 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2316
c285545f
ZA		 2317 /*
2318 * We may have to catch up the TSC to match elapsed wall clock
2319 * time for two reasons, even if kvmclock is used.
2320 * 1) CPU could have been running below the maximum TSC rate
2321 * 2) Broken TSC compensation resets the base at each VCPU
2322 * entry to avoid unknown leaps of TSC even when running
2323 * again on the same CPU. This may cause apparent elapsed
2324 * time to disappear, and the guest to stand still or run
2325 * very slowly.
2326 */
2327 if (vcpu->tsc_catchup) {
2328 u64 tsc = compute_guest_tsc(v, kernel_ns);
2329 if (tsc > tsc_timestamp) {
f1e2b260 2330 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2331 tsc_timestamp = tsc;
2332 }
50d0a0f9
GH		 2333 }
2334
18068523
GOC		 2335 local_irq_restore(flags);
2336
0d6dd2ff 2337 /* With all the info we got, fill in the values */
18068523 2338
78db6a50
PB		 2339 if (kvm_has_tsc_control)
2340 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2341
2342 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2343 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2344 &vcpu->hv_clock.tsc_shift,
2345 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2346 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2347 }
2348
1d5f066e 2349 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2350 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2351 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2352
d828199e 2353 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2354 pvclock_flags = 0;
d828199e
MT		 2355 if (use_master_clock)
2356 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2357
78c0337a
MT		 2358 vcpu->hv_clock.flags = pvclock_flags;
2359
095cf55d
PB		 2360 if (vcpu->pv_time_enabled)
2361 kvm_setup_pvclock_page(v);
2362 if (v == kvm_get_vcpu(v->kvm, 0))
2363 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2364 return 0;
c8076604
GH		 2365}
2366
0061d53d
MT		 2367/*
2368 * kvmclock updates which are isolated to a given vcpu, such as
2369 * vcpu->cpu migration, should not allow system_timestamp from
2370 * the rest of the vcpus to remain static. Otherwise ntp frequency
2371 * correction applies to one vcpu's system_timestamp but not
2372 * the others.
2373 *
2374 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2375 * We need to rate-limit these requests though, as they can
2376 * considerably slow guests that have a large number of vcpus.
2377 * The time for a remote vcpu to update its kvmclock is bound
2378 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2379 */
2380
7e44e449
AJ		 2381#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2382
2383static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2384{
2385 int i;
7e44e449
AJ		 2386 struct delayed_work *dwork = to_delayed_work(work);
2387 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2388 kvmclock_update_work);
2389 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2390 struct kvm_vcpu *vcpu;
2391
2392 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2393 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2394 kvm_vcpu_kick(vcpu);
2395 }
2396}
2397
7e44e449
AJ		 2398static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2399{
2400 struct kvm *kvm = v->kvm;
2401
105b21bb 2402 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2403 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2404 KVMCLOCK_UPDATE_DELAY);
2405}
2406
332967a3
AJ		 2407#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2408
2409static void kvmclock_sync_fn(struct work_struct *work)
2410{
2411 struct delayed_work *dwork = to_delayed_work(work);
2412 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2413 kvmclock_sync_work);
2414 struct kvm *kvm = container_of(ka, struct kvm, arch);
2415
630994b3
MT		 2416 if (!kvmclock_periodic_sync)
2417 return;
2418
332967a3
AJ		 2419 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2420 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2421 KVMCLOCK_SYNC_PERIOD);
2422}
2423
191c8137
BP		 2424/*
2425 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2426 */
2427static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2428{
2429 /* McStatusWrEn enabled? */
2430 if (guest_cpuid_is_amd(vcpu))
2431 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2432
2433 return false;
2434}
2435
9ffd986c 2436static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2437{
890ca9ae
HY		 2438 u64 mcg_cap = vcpu->arch.mcg_cap;
2439 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2440 u32 msr = msr_info->index;
2441 u64 data = msr_info->data;
890ca9ae 2442
15c4a640 2443 switch (msr) {
15c4a640 2444 case MSR_IA32_MCG_STATUS:
890ca9ae 2445 vcpu->arch.mcg_status = data;
15c4a640 2446 break;
c7ac679c 2447 case MSR_IA32_MCG_CTL:
44883f01
PB		 2448 if (!(mcg_cap & MCG_CTL_P) &&
2449 (data || !msr_info->host_initiated))
890ca9ae
HY		 2450 return 1;
2451 if (data != 0 && data != ~(u64)0)
44883f01 2452 return 1;
890ca9ae
HY		 2453 vcpu->arch.mcg_ctl = data;
2454 break;
2455 default:
2456 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2457 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2458 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2459 /* only 0 or all 1s can be written to IA32_MCi_CTL
2460 * some Linux kernels though clear bit 10 in bank 4 to
2461 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2462 * this to avoid an uncatched #GP in the guest
2463 */
890ca9ae 2464 if ((offset & 0x3) == 0 &&
114be429 2465 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2466 return -1;
191c8137
BP		 2467
2468 /* MCi_STATUS */
9ffd986c 2469 if (!msr_info->host_initiated &&
191c8137
BP		 2470 (offset & 0x3) == 1 && data != 0) {
2471 if (!can_set_mci_status(vcpu))
2472 return -1;
2473 }
2474
890ca9ae
HY		 2475 vcpu->arch.mce_banks[offset] = data;
2476 break;
2477 }
2478 return 1;
2479 }
2480 return 0;
2481}
2482
ffde22ac
ES		 2483static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2484{
2485 struct kvm *kvm = vcpu->kvm;
2486 int lm = is_long_mode(vcpu);
2487 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2488 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2489 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2490 : kvm->arch.xen_hvm_config.blob_size_32;
2491 u32 page_num = data & ~PAGE_MASK;
2492 u64 page_addr = data & PAGE_MASK;
2493 u8 *page;
2494 int r;
2495
2496 r = -E2BIG;
2497 if (page_num >= blob_size)
2498 goto out;
2499 r = -ENOMEM;
ff5c2c03
SL		 2500 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2501 if (IS_ERR(page)) {
2502 r = PTR_ERR(page);
ffde22ac 2503 goto out;
ff5c2c03 2504 }
54bf36aa 2505 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2506 goto out_free;
2507 r = 0;
2508out_free:
2509 kfree(page);
2510out:
2511 return r;
2512}
2513
344d9588
GN		 2514static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2515{
2516 gpa_t gpa = data & ~0x3f;
2517
52a5c155
WL		 2518 /* Bits 3:5 are reserved, Should be zero */
2519 if (data & 0x38)
344d9588
GN		 2520 return 1;
2521
2522 vcpu->arch.apf.msr_val = data;
2523
2524 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2525 kvm_clear_async_pf_completion_queue(vcpu);
2526 kvm_async_pf_hash_reset(vcpu);
2527 return 0;
2528 }
2529
4e335d9e 2530 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2531 sizeof(u32)))
344d9588
GN		 2532 return 1;
2533
6adba527 2534 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2535 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2536 kvm_async_pf_wakeup_all(vcpu);
2537 return 0;
2538}
2539
12f9a48f
GC		 2540static void kvmclock_reset(struct kvm_vcpu *vcpu)
2541{
0b79459b 2542 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2543}
2544
f38a7b75
WL		 2545static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2546{
2547 ++vcpu->stat.tlb_flush;
2548 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2549}
2550
c9aaa895
GC		 2551static void record_steal_time(struct kvm_vcpu *vcpu)
2552{
2553 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2554 return;
2555
4e335d9e 2556 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2557 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2558 return;
2559
f38a7b75
WL		 2560 /*
2561 * Doing a TLB flush here, on the guest's behalf, can avoid
2562 * expensive IPIs.
2563 */
b382f44e
WL		 2564 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2565 vcpu->arch.st.steal.preempted & KVM_VCPU_FLUSH_TLB);
f38a7b75
WL		 2566 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2567 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2568
35f3fae1
WL		 2569 if (vcpu->arch.st.steal.version & 1)
2570 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2571
2572 vcpu->arch.st.steal.version += 1;
2573
4e335d9e 2574 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2575 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2576
2577 smp_wmb();
2578
c54cdf14
LC		 2579 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2580 vcpu->arch.st.last_steal;
2581 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2582
4e335d9e 2583 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2584 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2585
2586 smp_wmb();
2587
2588 vcpu->arch.st.steal.version += 1;
c9aaa895 2589
4e335d9e 2590 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2591 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2592}
2593
8fe8ab46 2594int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2595{
5753785f 2596 bool pr = false;
8fe8ab46
WA		 2597 u32 msr = msr_info->index;
2598 u64 data = msr_info->data;
5753785f 2599
15c4a640 2600 switch (msr) {
2e32b719 2601 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2602 case MSR_IA32_UCODE_WRITE:
2603 case MSR_VM_HSAVE_PA:
2604 case MSR_AMD64_PATCH_LOADER:
2605 case MSR_AMD64_BU_CFG2:
405a353a 2606 case MSR_AMD64_DC_CFG:
0e1b869f 2607 case MSR_F15H_EX_CFG:
2e32b719
BP		 2608 break;
2609
518e7b94
WL		 2610 case MSR_IA32_UCODE_REV:
2611 if (msr_info->host_initiated)
2612 vcpu->arch.microcode_version = data;
2613 break;
0cf9135b
SC		 2614 case MSR_IA32_ARCH_CAPABILITIES:
2615 if (!msr_info->host_initiated)
2616 return 1;
2617 vcpu->arch.arch_capabilities = data;
2618 break;
15c4a640 2619 case MSR_EFER:
11988499 2620 return set_efer(vcpu, msr_info);
8f1589d9
AP		 2621 case MSR_K7_HWCR:
2622 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2623 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2624 data &= ~(u64)0x8; /* ignore TLB cache disable */
191c8137
BP		 2625
2626 /* Handle McStatusWrEn */
2627 if (data == BIT_ULL(18)) {
2628 vcpu->arch.msr_hwcr = data;
2629 } else if (data != 0) {
a737f256
CD		 2630 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2631 data);
8f1589d9
AP		 2632 return 1;
2633 }
15c4a640 2634 break;
f7c6d140
AP		 2635 case MSR_FAM10H_MMIO_CONF_BASE:
2636 if (data != 0) {
a737f256
CD		 2637 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2638 "0x%llx\n", data);
f7c6d140
AP		 2639 return 1;
2640 }
15c4a640 2641 break;
b5e2fec0
AG		 2642 case MSR_IA32_DEBUGCTLMSR:
2643 if (!data) {
2644 /* We support the non-activated case already */
2645 break;
2646 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2647 /* Values other than LBR and BTF are vendor-specific,
2648 thus reserved and should throw a #GP */
2649 return 1;
2650 }
a737f256
CD		 2651 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2652 __func__, data);
b5e2fec0 2653 break;
9ba075a6 2654 case 0x200 ... 0x2ff:
ff53604b 2655 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2656 case MSR_IA32_APICBASE:
58cb628d 2657 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2658 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2659 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2660 case MSR_IA32_TSCDEADLINE:
2661 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2662 break;
ba904635 2663 case MSR_IA32_TSC_ADJUST:
d6321d49 2664 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2665 if (!msr_info->host_initiated) {
d913b904 2666 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2667 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2668 }
2669 vcpu->arch.ia32_tsc_adjust_msr = data;
2670 }
2671 break;
15c4a640 2672 case MSR_IA32_MISC_ENABLE:
511a8556
WL		 2673 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2674 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2675 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2676 return 1;
2677 vcpu->arch.ia32_misc_enable_msr = data;
2678 kvm_update_cpuid(vcpu);
2679 } else {
2680 vcpu->arch.ia32_misc_enable_msr = data;
2681 }
15c4a640 2682 break;
64d60670
PB		 2683 case MSR_IA32_SMBASE:
2684 if (!msr_info->host_initiated)
2685 return 1;
2686 vcpu->arch.smbase = data;
2687 break;
73f624f4
PB		 2688 case MSR_IA32_POWER_CTL:
2689 vcpu->arch.msr_ia32_power_ctl = data;
2690 break;
dd259935
PB		 2691 case MSR_IA32_TSC:
2692 kvm_write_tsc(vcpu, msr_info);
2693 break;
52797bf9
LA		 2694 case MSR_SMI_COUNT:
2695 if (!msr_info->host_initiated)
2696 return 1;
2697 vcpu->arch.smi_count = data;
2698 break;
11c6bffa 2699 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2700 case MSR_KVM_WALL_CLOCK:
2701 vcpu->kvm->arch.wall_clock = data;
2702 kvm_write_wall_clock(vcpu->kvm, data);
2703 break;
11c6bffa 2704 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2705 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2706 struct kvm_arch *ka = &vcpu->kvm->arch;
2707
12f9a48f 2708 kvmclock_reset(vcpu);
18068523 2709
54750f2c
MT		 2710 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2711 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2712
2713 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2714 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2715
2716 ka->boot_vcpu_runs_old_kvmclock = tmp;
2717 }
2718
18068523 2719 vcpu->arch.time = data;
0061d53d 2720 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2721
2722 /* we verify if the enable bit is set... */
2723 if (!(data & 1))
2724 break;
2725
4e335d9e 2726 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2727 &vcpu->arch.pv_time, data & ~1ULL,
2728 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2729 vcpu->arch.pv_time_enabled = false;
2730 else
2731 vcpu->arch.pv_time_enabled = true;
32cad84f 2732
18068523
GOC		 2733 break;
2734 }
344d9588
GN		 2735 case MSR_KVM_ASYNC_PF_EN:
2736 if (kvm_pv_enable_async_pf(vcpu, data))
2737 return 1;
2738 break;
c9aaa895
GC		 2739 case MSR_KVM_STEAL_TIME:
2740
2741 if (unlikely(!sched_info_on()))
2742 return 1;
2743
2744 if (data & KVM_STEAL_RESERVED_MASK)
2745 return 1;
2746
4e335d9e 2747 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2748 data & KVM_STEAL_VALID_BITS,
2749 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2750 return 1;
2751
2752 vcpu->arch.st.msr_val = data;
2753
2754 if (!(data & KVM_MSR_ENABLED))
2755 break;
2756
c9aaa895
GC		 2757 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2758
2759 break;
ae7a2a3f 2760 case MSR_KVM_PV_EOI_EN:
72bbf935 2761 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2762 return 1;
2763 break;
c9aaa895 2764
2d5ba19b
MT		 2765 case MSR_KVM_POLL_CONTROL:
2766 /* only enable bit supported */
2767 if (data & (-1ULL << 1))
2768 return 1;
2769
2770 vcpu->arch.msr_kvm_poll_control = data;
2771 break;
2772
890ca9ae
HY		 2773 case MSR_IA32_MCG_CTL:
2774 case MSR_IA32_MCG_STATUS:
81760dcc 2775 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2776 return set_msr_mce(vcpu, msr_info);
71db6023 2777
6912ac32
WH		 2778 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2779 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2780 pr = true; /* fall through */
2781 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2782 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2783 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2784 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2785
2786 if (pr || data != 0)
a737f256
CD		 2787 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2788 "0x%x data 0x%llx\n", msr, data);
5753785f 2789 break;
84e0cefa
JS		 2790 case MSR_K7_CLK_CTL:
2791 /*
2792 * Ignore all writes to this no longer documented MSR.
2793 * Writes are only relevant for old K7 processors,
2794 * all pre-dating SVM, but a recommended workaround from
4a969980 2795 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2796 * affected processor models on the command line, hence
2797 * the need to ignore the workaround.
2798 */
2799 break;
55cd8e5a 2800 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2801 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2802 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2803 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2804 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2805 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2806 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2807 return kvm_hv_set_msr_common(vcpu, msr, data,
2808 msr_info->host_initiated);
91c9c3ed 2809 case MSR_IA32_BBL_CR_CTL3:
2810 /* Drop writes to this legacy MSR -- see rdmsr
2811 * counterpart for further detail.
2812 */
fab0aa3b
EM		 2813 if (report_ignored_msrs)
2814 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2815 msr, data);
91c9c3ed 2816 break;
2b036c6b 2817 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2818 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2819 return 1;
2820 vcpu->arch.osvw.length = data;
2821 break;
2822 case MSR_AMD64_OSVW_STATUS:
d6321d49 2823 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2824 return 1;
2825 vcpu->arch.osvw.status = data;
2826 break;
db2336a8
KH		 2827 case MSR_PLATFORM_INFO:
2828 if (!msr_info->host_initiated ||
db2336a8
KH		 2829 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2830 cpuid_fault_enabled(vcpu)))
2831 return 1;
2832 vcpu->arch.msr_platform_info = data;
2833 break;
2834 case MSR_MISC_FEATURES_ENABLES:
2835 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2836 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2837 !supports_cpuid_fault(vcpu)))
2838 return 1;
2839 vcpu->arch.msr_misc_features_enables = data;
2840 break;
15c4a640 2841 default:
ffde22ac
ES		 2842 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2843 return xen_hvm_config(vcpu, data);
c6702c9d 2844 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2845 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2846 if (!ignore_msrs) {
ae0f5499 2847 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2848 msr, data);
ed85c068
AP		 2849 return 1;
2850 } else {
fab0aa3b
EM		 2851 if (report_ignored_msrs)
2852 vcpu_unimpl(vcpu,
2853 "ignored wrmsr: 0x%x data 0x%llx\n",
2854 msr, data);
ed85c068
AP		 2855 break;
2856 }
15c4a640
CO		 2857 }
2858 return 0;
2859}
2860EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2861
44883f01 2862static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2863{
2864 u64 data;
890ca9ae
HY		 2865 u64 mcg_cap = vcpu->arch.mcg_cap;
2866 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2867
2868 switch (msr) {
15c4a640
CO		 2869 case MSR_IA32_P5_MC_ADDR:
2870 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2871 data = 0;
2872 break;
15c4a640 2873 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2874 data = vcpu->arch.mcg_cap;
2875 break;
c7ac679c 2876 case MSR_IA32_MCG_CTL:
44883f01 2877 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2878 return 1;
2879 data = vcpu->arch.mcg_ctl;
2880 break;
2881 case MSR_IA32_MCG_STATUS:
2882 data = vcpu->arch.mcg_status;
2883 break;
2884 default:
2885 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2886 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2887 u32 offset = msr - MSR_IA32_MC0_CTL;
2888 data = vcpu->arch.mce_banks[offset];
2889 break;
2890 }
2891 return 1;
2892 }
2893 *pdata = data;
2894 return 0;
2895}
2896
609e36d3 2897int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2898{
609e36d3 2899 switch (msr_info->index) {
890ca9ae 2900 case MSR_IA32_PLATFORM_ID:
15c4a640 2901 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2902 case MSR_IA32_DEBUGCTLMSR:
2903 case MSR_IA32_LASTBRANCHFROMIP:
2904 case MSR_IA32_LASTBRANCHTOIP:
2905 case MSR_IA32_LASTINTFROMIP:
2906 case MSR_IA32_LASTINTTOIP:
60af2ecd 2907 case MSR_K8_SYSCFG:
3afb1121
PB		 2908 case MSR_K8_TSEG_ADDR:
2909 case MSR_K8_TSEG_MASK:
61a6bd67 2910 case MSR_VM_HSAVE_PA:
1fdbd48c 2911 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2912 case MSR_AMD64_NB_CFG:
f7c6d140 2913 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2914 case MSR_AMD64_BU_CFG2:
0c2df2a1 2915 case MSR_IA32_PERF_CTL:
405a353a 2916 case MSR_AMD64_DC_CFG:
0e1b869f 2917 case MSR_F15H_EX_CFG:
609e36d3 2918 msr_info->data = 0;
15c4a640 2919 break;
c51eb52b 2920 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2921 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2922 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2923 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2924 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2925 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2926 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2927 msr_info->data = 0;
5753785f 2928 break;
742bc670 2929 case MSR_IA32_UCODE_REV:
518e7b94 2930 msr_info->data = vcpu->arch.microcode_version;
742bc670 2931 break;
0cf9135b
SC		 2932 case MSR_IA32_ARCH_CAPABILITIES:
2933 if (!msr_info->host_initiated &&
2934 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2935 return 1;
2936 msr_info->data = vcpu->arch.arch_capabilities;
2937 break;
73f624f4
PB		 2938 case MSR_IA32_POWER_CTL:
2939 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2940 break;
dd259935
PB		 2941 case MSR_IA32_TSC:
2942 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2943 break;
9ba075a6 2944 case MSR_MTRRcap:
9ba075a6 2945 case 0x200 ... 0x2ff:
ff53604b 2946 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2947 case 0xcd: /* fsb frequency */
609e36d3 2948 msr_info->data = 3;
15c4a640 2949 break;
7b914098
JS		 2950 /*
2951 * MSR_EBC_FREQUENCY_ID
2952 * Conservative value valid for even the basic CPU models.
2953 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2954 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2955 * and 266MHz for model 3, or 4. Set Core Clock
2956 * Frequency to System Bus Frequency Ratio to 1 (bits
2957 * 31:24) even though these are only valid for CPU
2958 * models > 2, however guests may end up dividing or
2959 * multiplying by zero otherwise.
2960 */
2961 case MSR_EBC_FREQUENCY_ID:
609e36d3 2962 msr_info->data = 1 << 24;
7b914098 2963 break;
15c4a640 2964 case MSR_IA32_APICBASE:
609e36d3 2965 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2966 break;
0105d1a5 2967 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2968 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2969 break;
a3e06bbe 2970 case MSR_IA32_TSCDEADLINE:
609e36d3 2971 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2972 break;
ba904635 2973 case MSR_IA32_TSC_ADJUST:
609e36d3 2974 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2975 break;
15c4a640 2976 case MSR_IA32_MISC_ENABLE:
609e36d3 2977 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2978 break;
64d60670
PB		 2979 case MSR_IA32_SMBASE:
2980 if (!msr_info->host_initiated)
2981 return 1;
2982 msr_info->data = vcpu->arch.smbase;
15c4a640 2983 break;
52797bf9
LA		 2984 case MSR_SMI_COUNT:
2985 msr_info->data = vcpu->arch.smi_count;
2986 break;
847f0ad8
AG		 2987 case MSR_IA32_PERF_STATUS:
2988 /* TSC increment by tick */
609e36d3 2989 msr_info->data = 1000ULL;
847f0ad8 2990 /* CPU multiplier */
b0996ae4 2991 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2992 break;
15c4a640 2993 case MSR_EFER:
609e36d3 2994 msr_info->data = vcpu->arch.efer;
15c4a640 2995 break;
18068523 2996 case MSR_KVM_WALL_CLOCK:
11c6bffa 2997 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2998 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2999 break;
3000 case MSR_KVM_SYSTEM_TIME:
11c6bffa 3001 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 3002 msr_info->data = vcpu->arch.time;
18068523 3003 break;
344d9588 3004 case MSR_KVM_ASYNC_PF_EN:
609e36d3 3005 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 3006 break;
c9aaa895 3007 case MSR_KVM_STEAL_TIME:
609e36d3 3008 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 3009 break;
1d92128f 3010 case MSR_KVM_PV_EOI_EN:
609e36d3 3011 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 3012 break;
2d5ba19b
MT		 3013 case MSR_KVM_POLL_CONTROL:
3014 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3015 break;
890ca9ae
HY		 3016 case MSR_IA32_P5_MC_ADDR:
3017 case MSR_IA32_P5_MC_TYPE:
3018 case MSR_IA32_MCG_CAP:
3019 case MSR_IA32_MCG_CTL:
3020 case MSR_IA32_MCG_STATUS:
81760dcc 3021 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 3022 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3023 msr_info->host_initiated);
84e0cefa
JS		 3024 case MSR_K7_CLK_CTL:
3025 /*
3026 * Provide expected ramp-up count for K7. All other
3027 * are set to zero, indicating minimum divisors for
3028 * every field.
3029 *
3030 * This prevents guest kernels on AMD host with CPU
3031 * type 6, model 8 and higher from exploding due to
3032 * the rdmsr failing.
3033 */
609e36d3 3034 msr_info->data = 0x20000000;
84e0cefa 3035 break;
55cd8e5a 3036 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 3037 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3038 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 3039 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 3040 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3041 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3042 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 3043 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 3044 msr_info->index, &msr_info->data,
3045 msr_info->host_initiated);
55cd8e5a 3046 break;
91c9c3ed 3047 case MSR_IA32_BBL_CR_CTL3:
3048 /* This legacy MSR exists but isn't fully documented in current
3049 * silicon. It is however accessed by winxp in very narrow
3050 * scenarios where it sets bit #19, itself documented as
3051 * a "reserved" bit. Best effort attempt to source coherent
3052 * read data here should the balance of the register be
3053 * interpreted by the guest:
3054 *
3055 * L2 cache control register 3: 64GB range, 256KB size,
3056 * enabled, latency 0x1, configured
3057 */
609e36d3 3058 msr_info->data = 0xbe702111;
91c9c3ed 3059 break;
2b036c6b 3060 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 3061 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 3062 return 1;
609e36d3 3063 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 3064 break;
3065 case MSR_AMD64_OSVW_STATUS:
d6321d49 3066 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 3067 return 1;
609e36d3 3068 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 3069 break;
db2336a8 3070 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 3071 if (!msr_info->host_initiated &&
3072 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3073 return 1;
db2336a8
KH		 3074 msr_info->data = vcpu->arch.msr_platform_info;
3075 break;
3076 case MSR_MISC_FEATURES_ENABLES:
3077 msr_info->data = vcpu->arch.msr_misc_features_enables;
3078 break;
191c8137
BP		 3079 case MSR_K7_HWCR:
3080 msr_info->data = vcpu->arch.msr_hwcr;
3081 break;
15c4a640 3082 default:
c6702c9d 3083 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 3084 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 3085 if (!ignore_msrs) {
ae0f5499
BD		 3086 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3087 msr_info->index);
ed85c068
AP		 3088 return 1;
3089 } else {
fab0aa3b
EM		 3090 if (report_ignored_msrs)
3091 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3092 msr_info->index);
609e36d3 3093 msr_info->data = 0;
ed85c068
AP		 3094 }
3095 break;
15c4a640 3096 }
15c4a640
CO		 3097 return 0;
3098}
3099EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3100
313a3dc7
CO		 3101/*
3102 * Read or write a bunch of msrs. All parameters are kernel addresses.
3103 *
3104 * @return number of msrs set successfully.
3105 */
3106static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3107 struct kvm_msr_entry *entries,
3108 int (*do_msr)(struct kvm_vcpu *vcpu,
3109 unsigned index, u64 *data))
3110{
801e459a 3111 int i;
313a3dc7 3112
313a3dc7
CO		 3113 for (i = 0; i < msrs->nmsrs; ++i)
3114 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3115 break;
3116
313a3dc7
CO		 3117 return i;
3118}
3119
3120/*
3121 * Read or write a bunch of msrs. Parameters are user addresses.
3122 *
3123 * @return number of msrs set successfully.
3124 */
3125static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3126 int (*do_msr)(struct kvm_vcpu *vcpu,
3127 unsigned index, u64 *data),
3128 int writeback)
3129{
3130 struct kvm_msrs msrs;
3131 struct kvm_msr_entry *entries;
3132 int r, n;
3133 unsigned size;
3134
3135 r = -EFAULT;
0e96f31e 3136 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 3137 goto out;
3138
3139 r = -E2BIG;
3140 if (msrs.nmsrs >= MAX_IO_MSRS)
3141 goto out;
3142
313a3dc7 3143 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 3144 entries = memdup_user(user_msrs->entries, size);
3145 if (IS_ERR(entries)) {
3146 r = PTR_ERR(entries);
313a3dc7 3147 goto out;
ff5c2c03 3148 }
313a3dc7
CO		 3149
3150 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3151 if (r < 0)
3152 goto out_free;
3153
3154 r = -EFAULT;
3155 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3156 goto out_free;
3157
3158 r = n;
3159
3160out_free:
7a73c028 3161 kfree(entries);
313a3dc7
CO		 3162out:
3163 return r;
3164}
3165
4d5422ce
WL		 3166static inline bool kvm_can_mwait_in_guest(void)
3167{
3168 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 3169 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3170 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 3171}
3172
784aa3d7 3173int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 3174{
4d5422ce 3175 int r = 0;
018d00d2
ZX		 3176
3177 switch (ext) {
3178 case KVM_CAP_IRQCHIP:
3179 case KVM_CAP_HLT:
3180 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 3181 case KVM_CAP_SET_TSS_ADDR:
07716717 3182 case KVM_CAP_EXT_CPUID:
9c15bb1d 3183 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 3184 case KVM_CAP_CLOCKSOURCE:
7837699f 3185 case KVM_CAP_PIT:
a28e4f5a 3186 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 3187 case KVM_CAP_MP_STATE:
ed848624 3188 case KVM_CAP_SYNC_MMU:
a355c85c 3189 case KVM_CAP_USER_NMI:
52d939a0 3190 case KVM_CAP_REINJECT_CONTROL:
4925663a 3191 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 3192 case KVM_CAP_IOEVENTFD:
f848a5a8 3193 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 3194 case KVM_CAP_PIT2:
e9f42757 3195 case KVM_CAP_PIT_STATE2:
b927a3ce 3196 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 3197 case KVM_CAP_XEN_HVM:
3cfc3092 3198 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 3199 case KVM_CAP_HYPERV:
10388a07 3200 case KVM_CAP_HYPERV_VAPIC:
c25bc163 3201 case KVM_CAP_HYPERV_SPIN:
5c919412 3202 case KVM_CAP_HYPERV_SYNIC:
efc479e6 3203 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 3204 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 3205 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3206 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3207 case KVM_CAP_HYPERV_SEND_IPI:
57b119da 3208 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
2bc39970 3209 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3210 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3211 case KVM_CAP_DEBUGREGS:
d2be1651 3212 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3213 case KVM_CAP_XSAVE:
344d9588 3214 case KVM_CAP_ASYNC_PF:
92a1f12d 3215 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3216 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3217 case KVM_CAP_READONLY_MEM:
5f66b620 3218 case KVM_CAP_HYPERV_TIME:
100943c5 3219 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3220 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3221 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3222 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3223 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3224 case KVM_CAP_IMMEDIATE_EXIT:
66bb8a06 3225 case KVM_CAP_PMU_EVENT_FILTER:
801e459a 3226 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3227 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3228 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3229 r = 1;
3230 break;
01643c51
KH		 3231 case KVM_CAP_SYNC_REGS:
3232 r = KVM_SYNC_X86_VALID_FIELDS;
3233 break;
e3fd9a93
PB		 3234 case KVM_CAP_ADJUST_CLOCK:
3235 r = KVM_CLOCK_TSC_STABLE;
3236 break;
4d5422ce 3237 case KVM_CAP_X86_DISABLE_EXITS:
b5170063
WL		 3238 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3239 KVM_X86_DISABLE_EXITS_CSTATE;
4d5422ce
WL		 3240 if(kvm_can_mwait_in_guest())
3241 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3242 break;
6d396b55
PB		 3243 case KVM_CAP_X86_SMM:
3244 /* SMBASE is usually relocated above 1M on modern chipsets,
3245 * and SMM handlers might indeed rely on 4G segment limits,
3246 * so do not report SMM to be available if real mode is
3247 * emulated via vm86 mode. Still, do not go to great lengths
3248 * to avoid userspace's usage of the feature, because it is a
3249 * fringe case that is not enabled except via specific settings
3250 * of the module parameters.
3251 */
bc226f07 3252 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3253 break;
774ead3a
AK		 3254 case KVM_CAP_VAPIC:
3255 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3256 break;
f725230a 3257 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3258 r = KVM_SOFT_MAX_VCPUS;
3259 break;
3260 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3261 r = KVM_MAX_VCPUS;
3262 break;
a86cb413
TH		 3263 case KVM_CAP_MAX_VCPU_ID:
3264 r = KVM_MAX_VCPU_ID;
3265 break;
a68a6a72
MT		 3266 case KVM_CAP_PV_MMU: /* obsolete */
3267 r = 0;
2f333bcb 3268 break;
890ca9ae
HY		 3269 case KVM_CAP_MCE:
3270 r = KVM_MAX_MCE_BANKS;
3271 break;
2d5b5a66 3272 case KVM_CAP_XCRS:
d366bf7e 3273 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3274 break;
92a1f12d
JR		 3275 case KVM_CAP_TSC_CONTROL:
3276 r = kvm_has_tsc_control;
3277 break;
37131313
RK		 3278 case KVM_CAP_X2APIC_API:
3279 r = KVM_X2APIC_API_VALID_FLAGS;
3280 break;
8fcc4b59
JM		 3281 case KVM_CAP_NESTED_STATE:
3282 r = kvm_x86_ops->get_nested_state ?
be43c440 3283 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
8fcc4b59 3284 break;
344c6c80
TL		 3285 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
3286 r = kvm_x86_ops->enable_direct_tlbflush ? 1 : 0;
3287 break;
018d00d2 3288 default:
018d00d2
ZX		 3289 break;
3290 }
3291 return r;
3292
3293}
3294
043405e1
CO		 3295long kvm_arch_dev_ioctl(struct file *filp,
3296 unsigned int ioctl, unsigned long arg)
3297{
3298 void __user *argp = (void __user *)arg;
3299 long r;
3300
3301 switch (ioctl) {
3302 case KVM_GET_MSR_INDEX_LIST: {
3303 struct kvm_msr_list __user *user_msr_list = argp;
3304 struct kvm_msr_list msr_list;
3305 unsigned n;
3306
3307 r = -EFAULT;
0e96f31e 3308 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3309 goto out;
3310 n = msr_list.nmsrs;
62ef68bb 3311 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3312 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3313 goto out;
3314 r = -E2BIG;
e125e7b6 3315 if (n < msr_list.nmsrs)
043405e1
CO		 3316 goto out;
3317 r = -EFAULT;
3318 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3319 num_msrs_to_save * sizeof(u32)))
3320 goto out;
e125e7b6 3321 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3322 &emulated_msrs,
62ef68bb 3323 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3324 goto out;
3325 r = 0;
3326 break;
3327 }
9c15bb1d
BP		 3328 case KVM_GET_SUPPORTED_CPUID:
3329 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3330 struct kvm_cpuid2 __user *cpuid_arg = argp;
3331 struct kvm_cpuid2 cpuid;
3332
3333 r = -EFAULT;
0e96f31e 3334 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3335 goto out;
9c15bb1d
BP		 3336
3337 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3338 ioctl);
674eea0f
AK		 3339 if (r)
3340 goto out;
3341
3342 r = -EFAULT;
0e96f31e 3343 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3344 goto out;
3345 r = 0;
3346 break;
3347 }
890ca9ae 3348 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3349 r = -EFAULT;
c45dcc71
AR		 3350 if (copy_to_user(argp, &kvm_mce_cap_supported,
3351 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3352 goto out;
3353 r = 0;
3354 break;
801e459a
TL		 3355 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3356 struct kvm_msr_list __user *user_msr_list = argp;
3357 struct kvm_msr_list msr_list;
3358 unsigned int n;
3359
3360 r = -EFAULT;
3361 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3362 goto out;
3363 n = msr_list.nmsrs;
3364 msr_list.nmsrs = num_msr_based_features;
3365 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3366 goto out;
3367 r = -E2BIG;
3368 if (n < msr_list.nmsrs)
3369 goto out;
3370 r = -EFAULT;
3371 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3372 num_msr_based_features * sizeof(u32)))
3373 goto out;
3374 r = 0;
3375 break;
3376 }
3377 case KVM_GET_MSRS:
3378 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3379 break;
890ca9ae 3380 }
043405e1
CO		 3381 default:
3382 r = -EINVAL;
3383 }
3384out:
3385 return r;
3386}
3387
f5f48ee1
SY		 3388static void wbinvd_ipi(void *garbage)
3389{
3390 wbinvd();
3391}
3392
3393static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3394{
e0f0bbc5 3395 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3396}
3397
313a3dc7
CO		 3398void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3399{
f5f48ee1
SY		 3400 /* Address WBINVD may be executed by guest */
3401 if (need_emulate_wbinvd(vcpu)) {
3402 if (kvm_x86_ops->has_wbinvd_exit())
3403 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3404 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3405 smp_call_function_single(vcpu->cpu,
3406 wbinvd_ipi, NULL, 1);
3407 }
3408
313a3dc7 3409 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3410
e7517324
WL		 3411 fpregs_assert_state_consistent();
3412 if (test_thread_flag(TIF_NEED_FPU_LOAD))
3413 switch_fpu_return();
3414
0dd6a6ed
ZA		 3415 /* Apply any externally detected TSC adjustments (due to suspend) */
3416 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3417 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3418 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3419 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3420 }
8f6055cb 3421
b0c39dc6 3422 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3423 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3424 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3425 if (tsc_delta < 0)
3426 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3427
b0c39dc6 3428 if (kvm_check_tsc_unstable()) {
07c1419a 3429 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3430 vcpu->arch.last_guest_tsc);
a545ab6a 3431 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3432 vcpu->arch.tsc_catchup = 1;
c285545f 3433 }
a749e247
PB		 3434
3435 if (kvm_lapic_hv_timer_in_use(vcpu))
3436 kvm_lapic_restart_hv_timer(vcpu);
3437
d98d07ca
MT		 3438 /*
3439 * On a host with synchronized TSC, there is no need to update
3440 * kvmclock on vcpu->cpu migration
3441 */
3442 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3443 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3444 if (vcpu->cpu != cpu)
1bd2009e 3445 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3446 vcpu->cpu = cpu;
6b7d7e76 3447 }
c9aaa895 3448
c9aaa895 3449 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3450}
3451
0b9f6c46
PX		 3452static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3453{
3454 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3455 return;
3456
fa55eedd 3457 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3458
4e335d9e 3459 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3460 &vcpu->arch.st.steal.preempted,
3461 offsetof(struct kvm_steal_time, preempted),
3462 sizeof(vcpu->arch.st.steal.preempted));
3463}
3464
313a3dc7
CO		 3465void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3466{
cc0d907c 3467 int idx;
de63ad4c
LM		 3468
3469 if (vcpu->preempted)
3470 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3471
931f261b
AA		 3472 /*
3473 * Disable page faults because we're in atomic context here.
3474 * kvm_write_guest_offset_cached() would call might_fault()
3475 * that relies on pagefault_disable() to tell if there's a
3476 * bug. NOTE: the write to guest memory may not go through if
3477 * during postcopy live migration or if there's heavy guest
3478 * paging.
3479 */
3480 pagefault_disable();
cc0d907c
AA		 3481 /*
3482 * kvm_memslots() will be called by
3483 * kvm_write_guest_offset_cached() so take the srcu lock.
3484 */
3485 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3486 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3487 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3488 pagefault_enable();
02daab21 3489 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3490 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3491 /*
f9dcf08e
RK		 3492 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3493 * on every vmexit, but if not, we might have a stale dr6 from the
3494 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3495 */
f9dcf08e 3496 set_debugreg(0, 6);
313a3dc7
CO		 3497}
3498
313a3dc7
CO		 3499static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3500 struct kvm_lapic_state *s)
3501{
fa59cc00 3502 if (vcpu->arch.apicv_active)
d62caabb
AS		 3503 kvm_x86_ops->sync_pir_to_irr(vcpu);
3504
a92e2543 3505 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3506}
3507
3508static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3509 struct kvm_lapic_state *s)
3510{
a92e2543
RK		 3511 int r;
3512
3513 r = kvm_apic_set_state(vcpu, s);
3514 if (r)
3515 return r;
cb142eb7 3516 update_cr8_intercept(vcpu);
313a3dc7
CO		 3517
3518 return 0;
3519}
3520
127a457a
MG		 3521static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3522{
3523 return (!lapic_in_kernel(vcpu) ||
3524 kvm_apic_accept_pic_intr(vcpu));
3525}
3526
782d422b
MG		 3527/*
3528 * if userspace requested an interrupt window, check that the
3529 * interrupt window is open.
3530 *
3531 * No need to exit to userspace if we already have an interrupt queued.
3532 */
3533static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3534{
3535 return kvm_arch_interrupt_allowed(vcpu) &&
3536 !kvm_cpu_has_interrupt(vcpu) &&
3537 !kvm_event_needs_reinjection(vcpu) &&
3538 kvm_cpu_accept_dm_intr(vcpu);
3539}
3540
f77bc6a4
ZX		 3541static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3542 struct kvm_interrupt *irq)
3543{
02cdb50f 3544 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3545 return -EINVAL;
1c1a9ce9
SR		 3546
3547 if (!irqchip_in_kernel(vcpu->kvm)) {
3548 kvm_queue_interrupt(vcpu, irq->irq, false);
3549 kvm_make_request(KVM_REQ_EVENT, vcpu);
3550 return 0;
3551 }
3552
3553 /*
3554 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3555 * fail for in-kernel 8259.
3556 */
3557 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3558 return -ENXIO;
f77bc6a4 3559
1c1a9ce9
SR		 3560 if (vcpu->arch.pending_external_vector != -1)
3561 return -EEXIST;
f77bc6a4 3562
1c1a9ce9 3563 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3564 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3565 return 0;
3566}
3567
c4abb7c9
JK		 3568static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3569{
c4abb7c9 3570 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3571
3572 return 0;
3573}
3574
f077825a
PB		 3575static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3576{
64d60670
PB		 3577 kvm_make_request(KVM_REQ_SMI, vcpu);
3578
f077825a
PB		 3579 return 0;
3580}
3581
b209749f
AK		 3582static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3583 struct kvm_tpr_access_ctl *tac)
3584{
3585 if (tac->flags)
3586 return -EINVAL;
3587 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3588 return 0;
3589}
3590
890ca9ae
HY		 3591static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3592 u64 mcg_cap)
3593{
3594 int r;
3595 unsigned bank_num = mcg_cap & 0xff, bank;
3596
3597 r = -EINVAL;
a9e38c3e 3598 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3599 goto out;
c45dcc71 3600 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3601 goto out;
3602 r = 0;
3603 vcpu->arch.mcg_cap = mcg_cap;
3604 /* Init IA32_MCG_CTL to all 1s */
3605 if (mcg_cap & MCG_CTL_P)
3606 vcpu->arch.mcg_ctl = ~(u64)0;
3607 /* Init IA32_MCi_CTL to all 1s */
3608 for (bank = 0; bank < bank_num; bank++)
3609 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71 3610
92735b1b 3611 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3612out:
3613 return r;
3614}
3615
3616static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3617 struct kvm_x86_mce *mce)
3618{
3619 u64 mcg_cap = vcpu->arch.mcg_cap;
3620 unsigned bank_num = mcg_cap & 0xff;
3621 u64 *banks = vcpu->arch.mce_banks;
3622
3623 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3624 return -EINVAL;
3625 /*
3626 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3627 * reporting is disabled
3628 */
3629 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3630 vcpu->arch.mcg_ctl != ~(u64)0)
3631 return 0;
3632 banks += 4 * mce->bank;
3633 /*
3634 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3635 * reporting is disabled for the bank
3636 */
3637 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3638 return 0;
3639 if (mce->status & MCI_STATUS_UC) {
3640 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3641 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3642 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3643 return 0;
3644 }
3645 if (banks[1] & MCI_STATUS_VAL)
3646 mce->status |= MCI_STATUS_OVER;
3647 banks[2] = mce->addr;
3648 banks[3] = mce->misc;
3649 vcpu->arch.mcg_status = mce->mcg_status;
3650 banks[1] = mce->status;
3651 kvm_queue_exception(vcpu, MC_VECTOR);
3652 } else if (!(banks[1] & MCI_STATUS_VAL)
3653 || !(banks[1] & MCI_STATUS_UC)) {
3654 if (banks[1] & MCI_STATUS_VAL)
3655 mce->status |= MCI_STATUS_OVER;
3656 banks[2] = mce->addr;
3657 banks[3] = mce->misc;
3658 banks[1] = mce->status;
3659 } else
3660 banks[1] |= MCI_STATUS_OVER;
3661 return 0;
3662}
3663
3cfc3092
JK		 3664static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3665 struct kvm_vcpu_events *events)
3666{
7460fb4a 3667 process_nmi(vcpu);
59073aaf 3668
664f8e26 3669 /*
59073aaf
JM		 3670 * The API doesn't provide the instruction length for software
3671 * exceptions, so don't report them. As long as the guest RIP
3672 * isn't advanced, we should expect to encounter the exception
3673 * again.
664f8e26 3674 */
59073aaf
JM		 3675 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3676 events->exception.injected = 0;
3677 events->exception.pending = 0;
3678 } else {
3679 events->exception.injected = vcpu->arch.exception.injected;
3680 events->exception.pending = vcpu->arch.exception.pending;
3681 /*
3682 * For ABI compatibility, deliberately conflate
3683 * pending and injected exceptions when
3684 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3685 */
3686 if (!vcpu->kvm->arch.exception_payload_enabled)
3687 events->exception.injected |=
3688 vcpu->arch.exception.pending;
3689 }
3cfc3092
JK		 3690 events->exception.nr = vcpu->arch.exception.nr;
3691 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3692 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3693 events->exception_has_payload = vcpu->arch.exception.has_payload;
3694 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3695
03b82a30 3696 events->interrupt.injected =
04140b41 3697 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3698 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3699 events->interrupt.soft = 0;
37ccdcbe 3700 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3701
3702 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3703 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3704 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3705 events->nmi.pad = 0;
3cfc3092 3706
66450a21 3707 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3708
f077825a
PB		 3709 events->smi.smm = is_smm(vcpu);
3710 events->smi.pending = vcpu->arch.smi_pending;
3711 events->smi.smm_inside_nmi =
3712 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3713 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3714
dab4b911 3715 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3716 | KVM_VCPUEVENT_VALID_SHADOW
3717 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3718 if (vcpu->kvm->arch.exception_payload_enabled)
3719 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3720
97e69aa6 3721 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3722}
3723
c5833c7a 3724static void kvm_smm_changed(struct kvm_vcpu *vcpu);
6ef4e07e 3725
3cfc3092
JK		 3726static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3727 struct kvm_vcpu_events *events)
3728{
dab4b911 3729 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3730 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3731 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3732 | KVM_VCPUEVENT_VALID_SMM
3733 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3734 return -EINVAL;
3735
59073aaf
JM		 3736 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3737 if (!vcpu->kvm->arch.exception_payload_enabled)
3738 return -EINVAL;
3739 if (events->exception.pending)
3740 events->exception.injected = 0;
3741 else
3742 events->exception_has_payload = 0;
3743 } else {
3744 events->exception.pending = 0;
3745 events->exception_has_payload = 0;
3746 }
3747
3748 if ((events->exception.injected || events->exception.pending) &&
3749 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3750 return -EINVAL;
3751
28bf2888
DH		 3752 /* INITs are latched while in SMM */
3753 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3754 (events->smi.smm || events->smi.pending) &&
3755 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3756 return -EINVAL;
3757
7460fb4a 3758 process_nmi(vcpu);
59073aaf
JM		 3759 vcpu->arch.exception.injected = events->exception.injected;
3760 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3761 vcpu->arch.exception.nr = events->exception.nr;
3762 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3763 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3764 vcpu->arch.exception.has_payload = events->exception_has_payload;
3765 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3766
04140b41 3767 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3768 vcpu->arch.interrupt.nr = events->interrupt.nr;
3769 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3770 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3771 kvm_x86_ops->set_interrupt_shadow(vcpu,
3772 events->interrupt.shadow);
3cfc3092
JK		 3773
3774 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3775 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3776 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3777 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3778
66450a21 3779 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3780 lapic_in_kernel(vcpu))
66450a21 3781 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3782
f077825a 3783 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
c5833c7a
SC		 3784 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3785 if (events->smi.smm)
3786 vcpu->arch.hflags |= HF_SMM_MASK;
3787 else
3788 vcpu->arch.hflags &= ~HF_SMM_MASK;
3789 kvm_smm_changed(vcpu);
3790 }
6ef4e07e 3791
f077825a 3792 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3793
3794 if (events->smi.smm) {
3795 if (events->smi.smm_inside_nmi)
3796 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3797 else
f4ef1910
WL		 3798 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3799 if (lapic_in_kernel(vcpu)) {
3800 if (events->smi.latched_init)
3801 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3802 else
3803 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3804 }
f077825a
PB		 3805 }
3806 }
3807
3842d135
AK		 3808 kvm_make_request(KVM_REQ_EVENT, vcpu);
3809
3cfc3092
JK		 3810 return 0;
3811}
3812
a1efbe77
JK		 3813static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3814 struct kvm_debugregs *dbgregs)
3815{
73aaf249
JK		 3816 unsigned long val;
3817
a1efbe77 3818 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3819 kvm_get_dr(vcpu, 6, &val);
73aaf249 3820 dbgregs->dr6 = val;
a1efbe77
JK		 3821 dbgregs->dr7 = vcpu->arch.dr7;
3822 dbgregs->flags = 0;
97e69aa6 3823 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3824}
3825
3826static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3827 struct kvm_debugregs *dbgregs)
3828{
3829 if (dbgregs->flags)
3830 return -EINVAL;
3831
d14bdb55
PB		 3832 if (dbgregs->dr6 & ~0xffffffffull)
3833 return -EINVAL;
3834 if (dbgregs->dr7 & ~0xffffffffull)
3835 return -EINVAL;
3836
a1efbe77 3837 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3838 kvm_update_dr0123(vcpu);
a1efbe77 3839 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3840 kvm_update_dr6(vcpu);
a1efbe77 3841 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3842 kvm_update_dr7(vcpu);
a1efbe77 3843
a1efbe77
JK		 3844 return 0;
3845}
3846
df1daba7
PB		 3847#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3848
3849static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3850{
b666a4b6 3851 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3852 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3853 u64 valid;
3854
3855 /*
3856 * Copy legacy XSAVE area, to avoid complications with CPUID
3857 * leaves 0 and 1 in the loop below.
3858 */
3859 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3860
3861 /* Set XSTATE_BV */
00c87e9a 3862 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3863 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3864
3865 /*
3866 * Copy each region from the possibly compacted offset to the
3867 * non-compacted offset.
3868 */
d91cab78 3869 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3870 while (valid) {
abd16d68
SAS		 3871 u64 xfeature_mask = valid & -valid;
3872 int xfeature_nr = fls64(xfeature_mask) - 1;
3873 void *src = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3874
3875 if (src) {
3876 u32 size, offset, ecx, edx;
abd16d68 3877 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3878 &size, &offset, &ecx, &edx);
abd16d68 3879 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3880 memcpy(dest + offset, &vcpu->arch.pkru,
3881 sizeof(vcpu->arch.pkru));
3882 else
3883 memcpy(dest + offset, src, size);
3884
df1daba7
PB		 3885 }
3886
abd16d68 3887 valid -= xfeature_mask;
df1daba7
PB		 3888 }
3889}
3890
3891static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3892{
b666a4b6 3893 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 3894 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3895 u64 valid;
3896
3897 /*
3898 * Copy legacy XSAVE area, to avoid complications with CPUID
3899 * leaves 0 and 1 in the loop below.
3900 */
3901 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3902
3903 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3904 xsave->header.xfeatures = xstate_bv;
782511b0 3905 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3906 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3907
3908 /*
3909 * Copy each region from the non-compacted offset to the
3910 * possibly compacted offset.
3911 */
d91cab78 3912 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3913 while (valid) {
abd16d68
SAS		 3914 u64 xfeature_mask = valid & -valid;
3915 int xfeature_nr = fls64(xfeature_mask) - 1;
3916 void *dest = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3917
3918 if (dest) {
3919 u32 size, offset, ecx, edx;
abd16d68 3920 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3921 &size, &offset, &ecx, &edx);
abd16d68 3922 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3923 memcpy(&vcpu->arch.pkru, src + offset,
3924 sizeof(vcpu->arch.pkru));
3925 else
3926 memcpy(dest, src + offset, size);
ee4100da 3927 }
df1daba7 3928
abd16d68 3929 valid -= xfeature_mask;
df1daba7
PB		 3930 }
3931}
3932
2d5b5a66
SY		 3933static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3934 struct kvm_xsave *guest_xsave)
3935{
d366bf7e 3936 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3937 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3938 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3939 } else {
2d5b5a66 3940 memcpy(guest_xsave->region,
b666a4b6 3941 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3942 sizeof(struct fxregs_state));
2d5b5a66 3943 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3944 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3945 }
3946}
3947
a575813b
WL		 3948#define XSAVE_MXCSR_OFFSET 24
3949
2d5b5a66
SY		 3950static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3951 struct kvm_xsave *guest_xsave)
3952{
3953 u64 xstate_bv =
3954 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3955 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3956
d366bf7e 3957 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3958 /*
3959 * Here we allow setting states that are not present in
3960 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3961 * with old userspace.
3962 */
a575813b
WL		 3963 if (xstate_bv & ~kvm_supported_xcr0() ||
3964 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3965 return -EINVAL;
df1daba7 3966 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3967 } else {
a575813b
WL		 3968 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3969 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3970 return -EINVAL;
b666a4b6 3971 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3972 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3973 }
3974 return 0;
3975}
3976
3977static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3978 struct kvm_xcrs *guest_xcrs)
3979{
d366bf7e 3980 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3981 guest_xcrs->nr_xcrs = 0;
3982 return;
3983 }
3984
3985 guest_xcrs->nr_xcrs = 1;
3986 guest_xcrs->flags = 0;
3987 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3988 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3989}
3990
3991static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3992 struct kvm_xcrs *guest_xcrs)
3993{
3994 int i, r = 0;
3995
d366bf7e 3996 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3997 return -EINVAL;
3998
3999 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4000 return -EINVAL;
4001
4002 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4003 /* Only support XCR0 currently */
c67a04cb 4004 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 4005 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 4006 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 4007 break;
4008 }
4009 if (r)
4010 r = -EINVAL;
4011 return r;
4012}
4013
1c0b28c2
EM		 4014/*
4015 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4016 * stopped by the hypervisor. This function will be called from the host only.
4017 * EINVAL is returned when the host attempts to set the flag for a guest that
4018 * does not support pv clocks.
4019 */
4020static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4021{
0b79459b 4022 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 4023 return -EINVAL;
51d59c6b 4024 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 4025 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4026 return 0;
4027}
4028
5c919412
AS		 4029static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4030 struct kvm_enable_cap *cap)
4031{
57b119da
VK		 4032 int r;
4033 uint16_t vmcs_version;
4034 void __user *user_ptr;
4035
5c919412
AS		 4036 if (cap->flags)
4037 return -EINVAL;
4038
4039 switch (cap->cap) {
efc479e6
RK		 4040 case KVM_CAP_HYPERV_SYNIC2:
4041 if (cap->args[0])
4042 return -EINVAL;
b2869f28
GS		 4043 /* fall through */
4044
5c919412 4045 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 4046 if (!irqchip_in_kernel(vcpu->kvm))
4047 return -EINVAL;
efc479e6
RK		 4048 return kvm_hv_activate_synic(vcpu, cap->cap ==
4049 KVM_CAP_HYPERV_SYNIC2);
57b119da 4050 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 4051 if (!kvm_x86_ops->nested_enable_evmcs)
4052 return -ENOTTY;
57b119da
VK		 4053 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4054 if (!r) {
4055 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4056 if (copy_to_user(user_ptr, &vmcs_version,
4057 sizeof(vmcs_version)))
4058 r = -EFAULT;
4059 }
4060 return r;
344c6c80
TL		 4061 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4062 if (!kvm_x86_ops->enable_direct_tlbflush)
4063 return -ENOTTY;
4064
4065 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
57b119da 4066
5c919412
AS		 4067 default:
4068 return -EINVAL;
4069 }
4070}
4071
313a3dc7
CO		 4072long kvm_arch_vcpu_ioctl(struct file *filp,
4073 unsigned int ioctl, unsigned long arg)
4074{
4075 struct kvm_vcpu *vcpu = filp->private_data;
4076 void __user *argp = (void __user *)arg;
4077 int r;
d1ac91d8
AK		 4078 union {
4079 struct kvm_lapic_state *lapic;
4080 struct kvm_xsave *xsave;
4081 struct kvm_xcrs *xcrs;
4082 void *buffer;
4083 } u;
4084
9b062471
CD		 4085 vcpu_load(vcpu);
4086
d1ac91d8 4087 u.buffer = NULL;
313a3dc7
CO		 4088 switch (ioctl) {
4089 case KVM_GET_LAPIC: {
2204ae3c 4090 r = -EINVAL;
bce87cce 4091 if (!lapic_in_kernel(vcpu))
2204ae3c 4092 goto out;
254272ce
BG		 4093 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4094 GFP_KERNEL_ACCOUNT);
313a3dc7 4095
b772ff36 4096 r = -ENOMEM;
d1ac91d8 4097 if (!u.lapic)
b772ff36 4098 goto out;
d1ac91d8 4099 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 4100 if (r)
4101 goto out;
4102 r = -EFAULT;
d1ac91d8 4103 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 4104 goto out;
4105 r = 0;
4106 break;
4107 }
4108 case KVM_SET_LAPIC: {
2204ae3c 4109 r = -EINVAL;
bce87cce 4110 if (!lapic_in_kernel(vcpu))
2204ae3c 4111 goto out;
ff5c2c03 4112 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 4113 if (IS_ERR(u.lapic)) {
4114 r = PTR_ERR(u.lapic);
4115 goto out_nofree;
4116 }
ff5c2c03 4117
d1ac91d8 4118 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 4119 break;
4120 }
f77bc6a4
ZX		 4121 case KVM_INTERRUPT: {
4122 struct kvm_interrupt irq;
4123
4124 r = -EFAULT;
0e96f31e 4125 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 4126 goto out;
4127 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 4128 break;
4129 }
c4abb7c9
JK		 4130 case KVM_NMI: {
4131 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 4132 break;
4133 }
f077825a
PB		 4134 case KVM_SMI: {
4135 r = kvm_vcpu_ioctl_smi(vcpu);
4136 break;
4137 }
313a3dc7
CO		 4138 case KVM_SET_CPUID: {
4139 struct kvm_cpuid __user *cpuid_arg = argp;
4140 struct kvm_cpuid cpuid;
4141
4142 r = -EFAULT;
0e96f31e 4143 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 4144 goto out;
4145 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 4146 break;
4147 }
07716717
DK		 4148 case KVM_SET_CPUID2: {
4149 struct kvm_cpuid2 __user *cpuid_arg = argp;
4150 struct kvm_cpuid2 cpuid;
4151
4152 r = -EFAULT;
0e96f31e 4153 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4154 goto out;
4155 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 4156 cpuid_arg->entries);
07716717
DK		 4157 break;
4158 }
4159 case KVM_GET_CPUID2: {
4160 struct kvm_cpuid2 __user *cpuid_arg = argp;
4161 struct kvm_cpuid2 cpuid;
4162
4163 r = -EFAULT;
0e96f31e 4164 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4165 goto out;
4166 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 4167 cpuid_arg->entries);
07716717
DK		 4168 if (r)
4169 goto out;
4170 r = -EFAULT;
0e96f31e 4171 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 4172 goto out;
4173 r = 0;
4174 break;
4175 }
801e459a
TL		 4176 case KVM_GET_MSRS: {
4177 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 4178 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 4179 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4180 break;
801e459a
TL		 4181 }
4182 case KVM_SET_MSRS: {
4183 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 4184 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 4185 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4186 break;
801e459a 4187 }
b209749f
AK		 4188 case KVM_TPR_ACCESS_REPORTING: {
4189 struct kvm_tpr_access_ctl tac;
4190
4191 r = -EFAULT;
0e96f31e 4192 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 4193 goto out;
4194 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4195 if (r)
4196 goto out;
4197 r = -EFAULT;
0e96f31e 4198 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 4199 goto out;
4200 r = 0;
4201 break;
4202 };
b93463aa
AK		 4203 case KVM_SET_VAPIC_ADDR: {
4204 struct kvm_vapic_addr va;
7301d6ab 4205 int idx;
b93463aa
AK		 4206
4207 r = -EINVAL;
35754c98 4208 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 4209 goto out;
4210 r = -EFAULT;
0e96f31e 4211 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 4212 goto out;
7301d6ab 4213 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 4214 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 4215 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4216 break;
4217 }
890ca9ae
HY		 4218 case KVM_X86_SETUP_MCE: {
4219 u64 mcg_cap;
4220
4221 r = -EFAULT;
0e96f31e 4222 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4223 goto out;
4224 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4225 break;
4226 }
4227 case KVM_X86_SET_MCE: {
4228 struct kvm_x86_mce mce;
4229
4230 r = -EFAULT;
0e96f31e 4231 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4232 goto out;
4233 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4234 break;
4235 }
3cfc3092
JK		 4236 case KVM_GET_VCPU_EVENTS: {
4237 struct kvm_vcpu_events events;
4238
4239 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4240
4241 r = -EFAULT;
4242 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4243 break;
4244 r = 0;
4245 break;
4246 }
4247 case KVM_SET_VCPU_EVENTS: {
4248 struct kvm_vcpu_events events;
4249
4250 r = -EFAULT;
4251 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4252 break;
4253
4254 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4255 break;
4256 }
a1efbe77
JK		 4257 case KVM_GET_DEBUGREGS: {
4258 struct kvm_debugregs dbgregs;
4259
4260 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4261
4262 r = -EFAULT;
4263 if (copy_to_user(argp, &dbgregs,
4264 sizeof(struct kvm_debugregs)))
4265 break;
4266 r = 0;
4267 break;
4268 }
4269 case KVM_SET_DEBUGREGS: {
4270 struct kvm_debugregs dbgregs;
4271
4272 r = -EFAULT;
4273 if (copy_from_user(&dbgregs, argp,
4274 sizeof(struct kvm_debugregs)))
4275 break;
4276
4277 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4278 break;
4279 }
2d5b5a66 4280 case KVM_GET_XSAVE: {
254272ce 4281 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
2d5b5a66 4282 r = -ENOMEM;
d1ac91d8 4283 if (!u.xsave)
2d5b5a66
SY		 4284 break;
4285
d1ac91d8 4286 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4287
4288 r = -EFAULT;
d1ac91d8 4289 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4290 break;
4291 r = 0;
4292 break;
4293 }
4294 case KVM_SET_XSAVE: {
ff5c2c03 4295 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4296 if (IS_ERR(u.xsave)) {
4297 r = PTR_ERR(u.xsave);
4298 goto out_nofree;
4299 }
2d5b5a66 4300
d1ac91d8 4301 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4302 break;
4303 }
4304 case KVM_GET_XCRS: {
254272ce 4305 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
2d5b5a66 4306 r = -ENOMEM;
d1ac91d8 4307 if (!u.xcrs)
2d5b5a66
SY		 4308 break;
4309
d1ac91d8 4310 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4311
4312 r = -EFAULT;
d1ac91d8 4313 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4314 sizeof(struct kvm_xcrs)))
4315 break;
4316 r = 0;
4317 break;
4318 }
4319 case KVM_SET_XCRS: {
ff5c2c03 4320 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4321 if (IS_ERR(u.xcrs)) {
4322 r = PTR_ERR(u.xcrs);
4323 goto out_nofree;
4324 }
2d5b5a66 4325
d1ac91d8 4326 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4327 break;
4328 }
92a1f12d
JR		 4329 case KVM_SET_TSC_KHZ: {
4330 u32 user_tsc_khz;
4331
4332 r = -EINVAL;
92a1f12d
JR		 4333 user_tsc_khz = (u32)arg;
4334
4335 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4336 goto out;
4337
cc578287
ZA		 4338 if (user_tsc_khz == 0)
4339 user_tsc_khz = tsc_khz;
4340
381d585c
HZ		 4341 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4342 r = 0;
92a1f12d 4343
92a1f12d
JR		 4344 goto out;
4345 }
4346 case KVM_GET_TSC_KHZ: {
cc578287 4347 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4348 goto out;
4349 }
1c0b28c2
EM		 4350 case KVM_KVMCLOCK_CTRL: {
4351 r = kvm_set_guest_paused(vcpu);
4352 goto out;
4353 }
5c919412
AS		 4354 case KVM_ENABLE_CAP: {
4355 struct kvm_enable_cap cap;
4356
4357 r = -EFAULT;
4358 if (copy_from_user(&cap, argp, sizeof(cap)))
4359 goto out;
4360 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4361 break;
4362 }
8fcc4b59
JM		 4363 case KVM_GET_NESTED_STATE: {
4364 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4365 u32 user_data_size;
4366
4367 r = -EINVAL;
4368 if (!kvm_x86_ops->get_nested_state)
4369 break;
4370
4371 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4372 r = -EFAULT;
8fcc4b59 4373 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4374 break;
8fcc4b59
JM		 4375
4376 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4377 user_data_size);
4378 if (r < 0)
26b471c7 4379 break;
8fcc4b59
JM		 4380
4381 if (r > user_data_size) {
4382 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4383 r = -EFAULT;
4384 else
4385 r = -E2BIG;
4386 break;
8fcc4b59 4387 }
26b471c7 4388
8fcc4b59
JM		 4389 r = 0;
4390 break;
4391 }
4392 case KVM_SET_NESTED_STATE: {
4393 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4394 struct kvm_nested_state kvm_state;
4395
4396 r = -EINVAL;
4397 if (!kvm_x86_ops->set_nested_state)
4398 break;
4399
26b471c7 4400 r = -EFAULT;
8fcc4b59 4401 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4402 break;
8fcc4b59 4403
26b471c7 4404 r = -EINVAL;
8fcc4b59 4405 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4406 break;
8fcc4b59
JM		 4407
4408 if (kvm_state.flags &
8cab6507
VK		 4409 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4410 | KVM_STATE_NESTED_EVMCS))
26b471c7 4411 break;
8fcc4b59
JM		 4412
4413 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4414 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4415 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4416 break;
8fcc4b59
JM		 4417
4418 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4419 break;
4420 }
2bc39970
VK		 4421 case KVM_GET_SUPPORTED_HV_CPUID: {
4422 struct kvm_cpuid2 __user *cpuid_arg = argp;
4423 struct kvm_cpuid2 cpuid;
4424
4425 r = -EFAULT;
4426 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4427 goto out;
4428
4429 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4430 cpuid_arg->entries);
4431 if (r)
4432 goto out;
4433
4434 r = -EFAULT;
4435 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4436 goto out;
4437 r = 0;
4438 break;
4439 }
313a3dc7
CO		 4440 default:
4441 r = -EINVAL;
4442 }
4443out:
d1ac91d8 4444 kfree(u.buffer);
9b062471
CD		 4445out_nofree:
4446 vcpu_put(vcpu);
313a3dc7
CO		 4447 return r;
4448}
4449
1499fa80 4450vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4451{
4452 return VM_FAULT_SIGBUS;
4453}
4454
1fe779f8
CO		 4455static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4456{
4457 int ret;
4458
4459 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4460 return -EINVAL;
1fe779f8
CO		 4461 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4462 return ret;
4463}
4464
b927a3ce
SY		 4465static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4466 u64 ident_addr)
4467{
2ac52ab8 4468 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4469}
4470
1fe779f8 4471static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
bc8a3d89 4472 unsigned long kvm_nr_mmu_pages)
1fe779f8
CO		 4473{
4474 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4475 return -EINVAL;
4476
79fac95e 4477 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4478
4479 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4480 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4481
79fac95e 4482 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4483 return 0;
4484}
4485
bc8a3d89 4486static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1fe779f8 4487{
39de71ec 4488 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4489}
4490
1fe779f8
CO		 4491static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4492{
90bca052 4493 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4494 int r;
4495
4496 r = 0;
4497 switch (chip->chip_id) {
4498 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4499 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4500 sizeof(struct kvm_pic_state));
4501 break;
4502 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4503 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4504 sizeof(struct kvm_pic_state));
4505 break;
4506 case KVM_IRQCHIP_IOAPIC:
33392b49 4507 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4508 break;
4509 default:
4510 r = -EINVAL;
4511 break;
4512 }
4513 return r;
4514}
4515
4516static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4517{
90bca052 4518 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4519 int r;
4520
4521 r = 0;
4522 switch (chip->chip_id) {
4523 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4524 spin_lock(&pic->lock);
4525 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4526 sizeof(struct kvm_pic_state));
90bca052 4527 spin_unlock(&pic->lock);
1fe779f8
CO		 4528 break;
4529 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4530 spin_lock(&pic->lock);
4531 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4532 sizeof(struct kvm_pic_state));
90bca052 4533 spin_unlock(&pic->lock);
1fe779f8
CO		 4534 break;
4535 case KVM_IRQCHIP_IOAPIC:
33392b49 4536 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4537 break;
4538 default:
4539 r = -EINVAL;
4540 break;
4541 }
90bca052 4542 kvm_pic_update_irq(pic);
1fe779f8
CO		 4543 return r;
4544}
4545
e0f63cb9
SY		 4546static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4547{
34f3941c
RK		 4548 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4549
4550 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4551
4552 mutex_lock(&kps->lock);
4553 memcpy(ps, &kps->channels, sizeof(*ps));
4554 mutex_unlock(&kps->lock);
2da29bcc 4555 return 0;
e0f63cb9
SY		 4556}
4557
4558static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4559{
0185604c 4560 int i;
09edea72
RK		 4561 struct kvm_pit *pit = kvm->arch.vpit;
4562
4563 mutex_lock(&pit->pit_state.lock);
34f3941c 4564 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4565 for (i = 0; i < 3; i++)
09edea72
RK		 4566 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4567 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4568 return 0;
e9f42757
BK		 4569}
4570
4571static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4572{
e9f42757
BK		 4573 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4574 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4575 sizeof(ps->channels));
4576 ps->flags = kvm->arch.vpit->pit_state.flags;
4577 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4578 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4579 return 0;
e9f42757
BK		 4580}
4581
4582static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4583{
2da29bcc 4584 int start = 0;
0185604c 4585 int i;
e9f42757 4586 u32 prev_legacy, cur_legacy;
09edea72
RK		 4587 struct kvm_pit *pit = kvm->arch.vpit;
4588
4589 mutex_lock(&pit->pit_state.lock);
4590 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4591 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4592 if (!prev_legacy && cur_legacy)
4593 start = 1;
09edea72
RK		 4594 memcpy(&pit->pit_state.channels, &ps->channels,
4595 sizeof(pit->pit_state.channels));
4596 pit->pit_state.flags = ps->flags;
0185604c 4597 for (i = 0; i < 3; i++)
09edea72 4598 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4599 start && i == 0);
09edea72 4600 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4601 return 0;
e0f63cb9
SY		 4602}
4603
52d939a0
MT		 4604static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4605 struct kvm_reinject_control *control)
4606{
71474e2f
RK		 4607 struct kvm_pit *pit = kvm->arch.vpit;
4608
4609 if (!pit)
52d939a0 4610 return -ENXIO;
b39c90b6 4611
71474e2f
RK		 4612 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4613 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4614 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4615 */
4616 mutex_lock(&pit->pit_state.lock);
4617 kvm_pit_set_reinject(pit, control->pit_reinject);
4618 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4619
52d939a0
MT		 4620 return 0;
4621}
4622
95d4c16c 4623/**
60c34612
TY		 4624 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4625 * @kvm: kvm instance
4626 * @log: slot id and address to which we copy the log
95d4c16c 4627 *
e108ff2f
PB		 4628 * Steps 1-4 below provide general overview of dirty page logging. See
4629 * kvm_get_dirty_log_protect() function description for additional details.
4630 *
4631 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4632 * always flush the TLB (step 4) even if previous step failed and the dirty
4633 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4634 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4635 * writes will be marked dirty for next log read.
95d4c16c 4636 *
60c34612
TY		 4637 * 1. Take a snapshot of the bit and clear it if needed.
4638 * 2. Write protect the corresponding page.
e108ff2f
PB		 4639 * 3. Copy the snapshot to the userspace.
4640 * 4. Flush TLB's if needed.
5bb064dc 4641 */
60c34612 4642int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4643{
8fe65a82 4644 bool flush = false;
e108ff2f 4645 int r;
5bb064dc 4646
79fac95e 4647 mutex_lock(&kvm->slots_lock);
5bb064dc 4648
88178fd4
KH		 4649 /*
4650 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4651 */
4652 if (kvm_x86_ops->flush_log_dirty)
4653 kvm_x86_ops->flush_log_dirty(kvm);
4654
8fe65a82 4655 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4656
4657 /*
4658 * All the TLBs can be flushed out of mmu lock, see the comments in
4659 * kvm_mmu_slot_remove_write_access().
4660 */
e108ff2f 4661 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4662 if (flush)
2a31b9db
PB		 4663 kvm_flush_remote_tlbs(kvm);
4664
4665 mutex_unlock(&kvm->slots_lock);
4666 return r;
4667}
4668
4669int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4670{
4671 bool flush = false;
4672 int r;
4673
4674 mutex_lock(&kvm->slots_lock);
4675
4676 /*
4677 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4678 */
4679 if (kvm_x86_ops->flush_log_dirty)
4680 kvm_x86_ops->flush_log_dirty(kvm);
4681
4682 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4683
4684 /*
4685 * All the TLBs can be flushed out of mmu lock, see the comments in
4686 * kvm_mmu_slot_remove_write_access().
4687 */
4688 lockdep_assert_held(&kvm->slots_lock);
4689 if (flush)
198c74f4
XG		 4690 kvm_flush_remote_tlbs(kvm);
4691
79fac95e 4692 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4693 return r;
4694}
4695
aa2fbe6d
YZ		 4696int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4697 bool line_status)
23d43cf9
CD		 4698{
4699 if (!irqchip_in_kernel(kvm))
4700 return -ENXIO;
4701
4702 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4703 irq_event->irq, irq_event->level,
4704 line_status);
23d43cf9
CD		 4705 return 0;
4706}
4707
e5d83c74
PB		 4708int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4709 struct kvm_enable_cap *cap)
90de4a18
NA		 4710{
4711 int r;
4712
4713 if (cap->flags)
4714 return -EINVAL;
4715
4716 switch (cap->cap) {
4717 case KVM_CAP_DISABLE_QUIRKS:
4718 kvm->arch.disabled_quirks = cap->args[0];
4719 r = 0;
4720 break;
49df6397
SR		 4721 case KVM_CAP_SPLIT_IRQCHIP: {
4722 mutex_lock(&kvm->lock);
b053b2ae
SR		 4723 r = -EINVAL;
4724 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4725 goto split_irqchip_unlock;
49df6397
SR		 4726 r = -EEXIST;
4727 if (irqchip_in_kernel(kvm))
4728 goto split_irqchip_unlock;
557abc40 4729 if (kvm->created_vcpus)
49df6397
SR		 4730 goto split_irqchip_unlock;
4731 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4732 if (r)
49df6397
SR		 4733 goto split_irqchip_unlock;
4734 /* Pairs with irqchip_in_kernel. */
4735 smp_wmb();
49776faf 4736 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4737 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4738 r = 0;
4739split_irqchip_unlock:
4740 mutex_unlock(&kvm->lock);
4741 break;
4742 }
37131313
RK		 4743 case KVM_CAP_X2APIC_API:
4744 r = -EINVAL;
4745 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4746 break;
4747
4748 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4749 kvm->arch.x2apic_format = true;
c519265f
RK		 4750 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4751 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4752
4753 r = 0;
4754 break;
4d5422ce
WL		 4755 case KVM_CAP_X86_DISABLE_EXITS:
4756 r = -EINVAL;
4757 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4758 break;
4759
4760 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4761 kvm_can_mwait_in_guest())
4762 kvm->arch.mwait_in_guest = true;
766d3571 4763 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4764 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4765 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4766 kvm->arch.pause_in_guest = true;
b5170063
WL		 4767 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4768 kvm->arch.cstate_in_guest = true;
4d5422ce
WL		 4769 r = 0;
4770 break;
6fbbde9a
DS		 4771 case KVM_CAP_MSR_PLATFORM_INFO:
4772 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4773 r = 0;
c4f55198
JM		 4774 break;
4775 case KVM_CAP_EXCEPTION_PAYLOAD:
4776 kvm->arch.exception_payload_enabled = cap->args[0];
4777 r = 0;
6fbbde9a 4778 break;
90de4a18
NA		 4779 default:
4780 r = -EINVAL;
4781 break;
4782 }
4783 return r;
4784}
4785
1fe779f8
CO		 4786long kvm_arch_vm_ioctl(struct file *filp,
4787 unsigned int ioctl, unsigned long arg)
4788{
4789 struct kvm *kvm = filp->private_data;
4790 void __user *argp = (void __user *)arg;
367e1319 4791 int r = -ENOTTY;
f0d66275
DH		 4792 /*
4793 * This union makes it completely explicit to gcc-3.x
4794 * that these two variables' stack usage should be
4795 * combined, not added together.
4796 */
4797 union {
4798 struct kvm_pit_state ps;
e9f42757 4799 struct kvm_pit_state2 ps2;
c5ff41ce 4800 struct kvm_pit_config pit_config;
f0d66275 4801 } u;
1fe779f8
CO		 4802
4803 switch (ioctl) {
4804 case KVM_SET_TSS_ADDR:
4805 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4806 break;
b927a3ce
SY		 4807 case KVM_SET_IDENTITY_MAP_ADDR: {
4808 u64 ident_addr;
4809
1af1ac91
DH		 4810 mutex_lock(&kvm->lock);
4811 r = -EINVAL;
4812 if (kvm->created_vcpus)
4813 goto set_identity_unlock;
b927a3ce 4814 r = -EFAULT;
0e96f31e 4815 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4816 goto set_identity_unlock;
b927a3ce 4817 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4818set_identity_unlock:
4819 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4820 break;
4821 }
1fe779f8
CO		 4822 case KVM_SET_NR_MMU_PAGES:
4823 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4824 break;
4825 case KVM_GET_NR_MMU_PAGES:
4826 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4827 break;
3ddea128 4828 case KVM_CREATE_IRQCHIP: {
3ddea128 4829 mutex_lock(&kvm->lock);
09941366 4830
3ddea128 4831 r = -EEXIST;
35e6eaa3 4832 if (irqchip_in_kernel(kvm))
3ddea128 4833 goto create_irqchip_unlock;
09941366 4834
3e515705 4835 r = -EINVAL;
557abc40 4836 if (kvm->created_vcpus)
3e515705 4837 goto create_irqchip_unlock;
09941366
RK		 4838
4839 r = kvm_pic_init(kvm);
4840 if (r)
3ddea128 4841 goto create_irqchip_unlock;
09941366
RK		 4842
4843 r = kvm_ioapic_init(kvm);
4844 if (r) {
09941366 4845 kvm_pic_destroy(kvm);
3ddea128 4846 goto create_irqchip_unlock;
09941366
RK		 4847 }
4848
399ec807
AK		 4849 r = kvm_setup_default_irq_routing(kvm);
4850 if (r) {
72bb2fcd 4851 kvm_ioapic_destroy(kvm);
09941366 4852 kvm_pic_destroy(kvm);
71ba994c 4853 goto create_irqchip_unlock;
399ec807 4854 }
49776faf 4855 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4856 smp_wmb();
49776faf 4857 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4858 create_irqchip_unlock:
4859 mutex_unlock(&kvm->lock);
1fe779f8 4860 break;
3ddea128 4861 }
7837699f 4862 case KVM_CREATE_PIT:
c5ff41ce
JK		 4863 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4864 goto create_pit;
4865 case KVM_CREATE_PIT2:
4866 r = -EFAULT;
4867 if (copy_from_user(&u.pit_config, argp,
4868 sizeof(struct kvm_pit_config)))
4869 goto out;
4870 create_pit:
250715a6 4871 mutex_lock(&kvm->lock);
269e05e4
AK		 4872 r = -EEXIST;
4873 if (kvm->arch.vpit)
4874 goto create_pit_unlock;
7837699f 4875 r = -ENOMEM;
c5ff41ce 4876 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4877 if (kvm->arch.vpit)
4878 r = 0;
269e05e4 4879 create_pit_unlock:
250715a6 4880 mutex_unlock(&kvm->lock);
7837699f 4881 break;
1fe779f8
CO		 4882 case KVM_GET_IRQCHIP: {
4883 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4884 struct kvm_irqchip *chip;
1fe779f8 4885
ff5c2c03
SL		 4886 chip = memdup_user(argp, sizeof(*chip));
4887 if (IS_ERR(chip)) {
4888 r = PTR_ERR(chip);
1fe779f8 4889 goto out;
ff5c2c03
SL		 4890 }
4891
1fe779f8 4892 r = -ENXIO;
826da321 4893 if (!irqchip_kernel(kvm))
f0d66275
DH		 4894 goto get_irqchip_out;
4895 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4896 if (r)
f0d66275 4897 goto get_irqchip_out;
1fe779f8 4898 r = -EFAULT;
0e96f31e 4899 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 4900 goto get_irqchip_out;
1fe779f8 4901 r = 0;
f0d66275
DH		 4902 get_irqchip_out:
4903 kfree(chip);
1fe779f8
CO		 4904 break;
4905 }
4906 case KVM_SET_IRQCHIP: {
4907 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4908 struct kvm_irqchip *chip;
1fe779f8 4909
ff5c2c03
SL		 4910 chip = memdup_user(argp, sizeof(*chip));
4911 if (IS_ERR(chip)) {
4912 r = PTR_ERR(chip);
1fe779f8 4913 goto out;
ff5c2c03
SL		 4914 }
4915
1fe779f8 4916 r = -ENXIO;
826da321 4917 if (!irqchip_kernel(kvm))
f0d66275
DH		 4918 goto set_irqchip_out;
4919 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4920 if (r)
f0d66275 4921 goto set_irqchip_out;
1fe779f8 4922 r = 0;
f0d66275
DH		 4923 set_irqchip_out:
4924 kfree(chip);
1fe779f8
CO		 4925 break;
4926 }
e0f63cb9 4927 case KVM_GET_PIT: {
e0f63cb9 4928 r = -EFAULT;
f0d66275 4929 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4930 goto out;
4931 r = -ENXIO;
4932 if (!kvm->arch.vpit)
4933 goto out;
f0d66275 4934 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4935 if (r)
4936 goto out;
4937 r = -EFAULT;
f0d66275 4938 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4939 goto out;
4940 r = 0;
4941 break;
4942 }
4943 case KVM_SET_PIT: {
e0f63cb9 4944 r = -EFAULT;
0e96f31e 4945 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 4946 goto out;
4947 r = -ENXIO;
4948 if (!kvm->arch.vpit)
4949 goto out;
f0d66275 4950 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4951 break;
4952 }
e9f42757
BK		 4953 case KVM_GET_PIT2: {
4954 r = -ENXIO;
4955 if (!kvm->arch.vpit)
4956 goto out;
4957 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4958 if (r)
4959 goto out;
4960 r = -EFAULT;
4961 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4962 goto out;
4963 r = 0;
4964 break;
4965 }
4966 case KVM_SET_PIT2: {
4967 r = -EFAULT;
4968 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4969 goto out;
4970 r = -ENXIO;
4971 if (!kvm->arch.vpit)
4972 goto out;
4973 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4974 break;
4975 }
52d939a0
MT		 4976 case KVM_REINJECT_CONTROL: {
4977 struct kvm_reinject_control control;
4978 r = -EFAULT;
4979 if (copy_from_user(&control, argp, sizeof(control)))
4980 goto out;
4981 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4982 break;
4983 }
d71ba788
PB		 4984 case KVM_SET_BOOT_CPU_ID:
4985 r = 0;
4986 mutex_lock(&kvm->lock);
557abc40 4987 if (kvm->created_vcpus)
d71ba788
PB		 4988 r = -EBUSY;
4989 else
4990 kvm->arch.bsp_vcpu_id = arg;
4991 mutex_unlock(&kvm->lock);
4992 break;
ffde22ac 4993 case KVM_XEN_HVM_CONFIG: {
51776043 4994 struct kvm_xen_hvm_config xhc;
ffde22ac 4995 r = -EFAULT;
51776043 4996 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4997 goto out;
4998 r = -EINVAL;
51776043 4999 if (xhc.flags)
ffde22ac 5000 goto out;
51776043 5001 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 5002 r = 0;
5003 break;
5004 }
afbcf7ab 5005 case KVM_SET_CLOCK: {
afbcf7ab
GC		 5006 struct kvm_clock_data user_ns;
5007 u64 now_ns;
afbcf7ab
GC		 5008
5009 r = -EFAULT;
5010 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5011 goto out;
5012
5013 r = -EINVAL;
5014 if (user_ns.flags)
5015 goto out;
5016
5017 r = 0;
0bc48bea
RK		 5018 /*
5019 * TODO: userspace has to take care of races with VCPU_RUN, so
5020 * kvm_gen_update_masterclock() can be cut down to locked
5021 * pvclock_update_vm_gtod_copy().
5022 */
5023 kvm_gen_update_masterclock(kvm);
e891a32e 5024 now_ns = get_kvmclock_ns(kvm);
108b249c 5025 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 5026 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 5027 break;
5028 }
5029 case KVM_GET_CLOCK: {
afbcf7ab
GC		 5030 struct kvm_clock_data user_ns;
5031 u64 now_ns;
5032
e891a32e 5033 now_ns = get_kvmclock_ns(kvm);
108b249c 5034 user_ns.clock = now_ns;
e3fd9a93 5035 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 5036 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 5037
5038 r = -EFAULT;
5039 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5040 goto out;
5041 r = 0;
5042 break;
5043 }
5acc5c06
BS		 5044 case KVM_MEMORY_ENCRYPT_OP: {
5045 r = -ENOTTY;
5046 if (kvm_x86_ops->mem_enc_op)
5047 r = kvm_x86_ops->mem_enc_op(kvm, argp);
5048 break;
5049 }
69eaedee
BS		 5050 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5051 struct kvm_enc_region region;
5052
5053 r = -EFAULT;
5054 if (copy_from_user(&region, argp, sizeof(region)))
5055 goto out;
5056
5057 r = -ENOTTY;
5058 if (kvm_x86_ops->mem_enc_reg_region)
5059 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
5060 break;
5061 }
5062 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5063 struct kvm_enc_region region;
5064
5065 r = -EFAULT;
5066 if (copy_from_user(&region, argp, sizeof(region)))
5067 goto out;
5068
5069 r = -ENOTTY;
5070 if (kvm_x86_ops->mem_enc_unreg_region)
5071 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
5072 break;
5073 }
faeb7833
RK		 5074 case KVM_HYPERV_EVENTFD: {
5075 struct kvm_hyperv_eventfd hvevfd;
5076
5077 r = -EFAULT;
5078 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5079 goto out;
5080 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5081 break;
5082 }
66bb8a06
EH		 5083 case KVM_SET_PMU_EVENT_FILTER:
5084 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5085 break;
1fe779f8 5086 default:
ad6260da 5087 r = -ENOTTY;
1fe779f8
CO		 5088 }
5089out:
5090 return r;
5091}
5092
a16b043c 5093static void kvm_init_msr_list(void)
043405e1
CO		 5094{
5095 u32 dummy[2];
5096 unsigned i, j;
5097
e2ada66e
JM		 5098 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5099 "Please update the fixed PMCs in msrs_to_save[]");
5100 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_GENERIC != 32,
5101 "Please update the generic perfctr/eventsel MSRs in msrs_to_save[]");
5102
62ef68bb 5103 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 5104 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
5105 continue;
93c4adc7
PB		 5106
5107 /*
5108 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 5109 * to the guests in some cases.
93c4adc7
PB		 5110 */
5111 switch (msrs_to_save[i]) {
5112 case MSR_IA32_BNDCFGS:
503234b3 5113 if (!kvm_mpx_supported())
93c4adc7
PB		 5114 continue;
5115 break;
9dbe6cf9
PB		 5116 case MSR_TSC_AUX:
5117 if (!kvm_x86_ops->rdtscp_supported())
5118 continue;
5119 break;
bf8c55d8
CP		 5120 case MSR_IA32_RTIT_CTL:
5121 case MSR_IA32_RTIT_STATUS:
5122 if (!kvm_x86_ops->pt_supported())
5123 continue;
5124 break;
5125 case MSR_IA32_RTIT_CR3_MATCH:
5126 if (!kvm_x86_ops->pt_supported() ||
5127 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5128 continue;
5129 break;
5130 case MSR_IA32_RTIT_OUTPUT_BASE:
5131 case MSR_IA32_RTIT_OUTPUT_MASK:
5132 if (!kvm_x86_ops->pt_supported() ||
5133 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5134 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5135 continue;
5136 break;
5137 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5138 if (!kvm_x86_ops->pt_supported() ||
5139 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5140 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5141 continue;
5142 break;
5143 }
93c4adc7
PB		 5144 default:
5145 break;
5146 }
5147
043405e1
CO		 5148 if (j < i)
5149 msrs_to_save[j] = msrs_to_save[i];
5150 j++;
5151 }
5152 num_msrs_to_save = j;
62ef68bb
PB		 5153
5154 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 5155 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5156 continue;
62ef68bb
PB		 5157
5158 if (j < i)
5159 emulated_msrs[j] = emulated_msrs[i];
5160 j++;
5161 }
5162 num_emulated_msrs = j;
801e459a
TL		 5163
5164 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5165 struct kvm_msr_entry msr;
5166
5167 msr.index = msr_based_features[i];
66421c1e 5168 if (kvm_get_msr_feature(&msr))
801e459a
TL		 5169 continue;
5170
5171 if (j < i)
5172 msr_based_features[j] = msr_based_features[i];
5173 j++;
5174 }
5175 num_msr_based_features = j;
043405e1
CO		 5176}
5177
bda9020e
MT		 5178static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5179 const void *v)
bbd9b64e 5180{
70252a10
AK		 5181 int handled = 0;
5182 int n;
5183
5184 do {
5185 n = min(len, 8);
bce87cce 5186 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5187 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5188 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 5189 break;
5190 handled += n;
5191 addr += n;
5192 len -= n;
5193 v += n;
5194 } while (len);
bbd9b64e 5195
70252a10 5196 return handled;
bbd9b64e
CO		 5197}
5198
bda9020e 5199static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 5200{
70252a10
AK		 5201 int handled = 0;
5202 int n;
5203
5204 do {
5205 n = min(len, 8);
bce87cce 5206 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5207 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5208 addr, n, v))
5209 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 5210 break;
e39d200f 5211 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 5212 handled += n;
5213 addr += n;
5214 len -= n;
5215 v += n;
5216 } while (len);
bbd9b64e 5217
70252a10 5218 return handled;
bbd9b64e
CO		 5219}
5220
2dafc6c2
GN		 5221static void kvm_set_segment(struct kvm_vcpu *vcpu,
5222 struct kvm_segment *var, int seg)
5223{
5224 kvm_x86_ops->set_segment(vcpu, var, seg);
5225}
5226
5227void kvm_get_segment(struct kvm_vcpu *vcpu,
5228 struct kvm_segment *var, int seg)
5229{
5230 kvm_x86_ops->get_segment(vcpu, var, seg);
5231}
5232
54987b7a
PB		 5233gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5234 struct x86_exception *exception)
02f59dc9
JR		 5235{
5236 gpa_t t_gpa;
02f59dc9
JR		 5237
5238 BUG_ON(!mmu_is_nested(vcpu));
5239
5240 /* NPT walks are always user-walks */
5241 access |= PFERR_USER_MASK;
44dd3ffa 5242 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 5243
5244 return t_gpa;
5245}
5246
ab9ae313
AK		 5247gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5248 struct x86_exception *exception)
1871c602
GN		 5249{
5250 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 5251 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5252}
5253
ab9ae313
AK		 5254 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5255 struct x86_exception *exception)
1871c602
GN		 5256{
5257 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5258 access |= PFERR_FETCH_MASK;
ab9ae313 5259 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5260}
5261
ab9ae313
AK		 5262gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5263 struct x86_exception *exception)
1871c602
GN		 5264{
5265 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5266 access |= PFERR_WRITE_MASK;
ab9ae313 5267 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5268}
5269
5270/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5271gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5272 struct x86_exception *exception)
1871c602 5273{
ab9ae313 5274 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5275}
5276
5277static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5278 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5279 struct x86_exception *exception)
bbd9b64e
CO		 5280{
5281 void *data = val;
10589a46 5282 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5283
5284 while (bytes) {
14dfe855 5285 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5286 exception);
bbd9b64e 5287 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5288 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5289 int ret;
5290
bcc55cba 5291 if (gpa == UNMAPPED_GVA)
ab9ae313 5292 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5293 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5294 offset, toread);
10589a46 5295 if (ret < 0) {
c3cd7ffa 5296 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5297 goto out;
5298 }
bbd9b64e 5299
77c2002e
IE		 5300 bytes -= toread;
5301 data += toread;
5302 addr += toread;
bbd9b64e 5303 }
10589a46 5304out:
10589a46 5305 return r;
bbd9b64e 5306}
77c2002e 5307
1871c602 5308/* used for instruction fetching */
0f65dd70
AK		 5309static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5310 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5311 struct x86_exception *exception)
1871c602 5312{
0f65dd70 5313 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5314 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5315 unsigned offset;
5316 int ret;
0f65dd70 5317
44583cba
PB		 5318 /* Inline kvm_read_guest_virt_helper for speed. */
5319 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5320 exception);
5321 if (unlikely(gpa == UNMAPPED_GVA))
5322 return X86EMUL_PROPAGATE_FAULT;
5323
5324 offset = addr & (PAGE_SIZE-1);
5325 if (WARN_ON(offset + bytes > PAGE_SIZE))
5326 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5327 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5328 offset, bytes);
44583cba
PB		 5329 if (unlikely(ret < 0))
5330 return X86EMUL_IO_NEEDED;
5331
5332 return X86EMUL_CONTINUE;
1871c602
GN		 5333}
5334
ce14e868 5335int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5336 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5337 struct x86_exception *exception)
1871c602
GN		 5338{
5339 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5340
353c0956
PB		 5341 /*
5342 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5343 * is returned, but our callers are not ready for that and they blindly
5344 * call kvm_inject_page_fault. Ensure that they at least do not leak
5345 * uninitialized kernel stack memory into cr2 and error code.
5346 */
5347 memset(exception, 0, sizeof(*exception));
1871c602 5348 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5349 exception);
1871c602 5350}
064aea77 5351EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5352
ce14e868
PB		 5353static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5354 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5355 struct x86_exception *exception, bool system)
1871c602 5356{
0f65dd70 5357 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5358 u32 access = 0;
5359
5360 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5361 access |= PFERR_USER_MASK;
5362
5363 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5364}
5365
7a036a6f
RK		 5366static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5367 unsigned long addr, void *val, unsigned int bytes)
5368{
5369 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5370 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5371
5372 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5373}
5374
ce14e868
PB		 5375static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5376 struct kvm_vcpu *vcpu, u32 access,
5377 struct x86_exception *exception)
77c2002e
IE		 5378{
5379 void *data = val;
5380 int r = X86EMUL_CONTINUE;
5381
5382 while (bytes) {
14dfe855 5383 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5384 access,
ab9ae313 5385 exception);
77c2002e
IE		 5386 unsigned offset = addr & (PAGE_SIZE-1);
5387 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5388 int ret;
5389
bcc55cba 5390 if (gpa == UNMAPPED_GVA)
ab9ae313 5391 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5392 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5393 if (ret < 0) {
c3cd7ffa 5394 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5395 goto out;
5396 }
5397
5398 bytes -= towrite;
5399 data += towrite;
5400 addr += towrite;
5401 }
5402out:
5403 return r;
5404}
ce14e868
PB		 5405
5406static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5407 unsigned int bytes, struct x86_exception *exception,
5408 bool system)
ce14e868
PB		 5409{
5410 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5411 u32 access = PFERR_WRITE_MASK;
5412
5413 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5414 access |= PFERR_USER_MASK;
ce14e868
PB		 5415
5416 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5417 access, exception);
ce14e868
PB		 5418}
5419
5420int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5421 unsigned int bytes, struct x86_exception *exception)
5422{
c595ceee
PB		 5423 /* kvm_write_guest_virt_system can pull in tons of pages. */
5424 vcpu->arch.l1tf_flush_l1d = true;
5425
541ab2ae
FH		 5426 /*
5427 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5428 * is returned, but our callers are not ready for that and they blindly
5429 * call kvm_inject_page_fault. Ensure that they at least do not leak
5430 * uninitialized kernel stack memory into cr2 and error code.
5431 */
5432 memset(exception, 0, sizeof(*exception));
ce14e868
PB		 5433 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5434 PFERR_WRITE_MASK, exception);
5435}
6a4d7550 5436EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5437
082d06ed
WL		 5438int handle_ud(struct kvm_vcpu *vcpu)
5439{
6c86eedc 5440 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 5441 enum emulation_result er;
6c86eedc
WL		 5442 char sig[5]; /* ud2; .ascii "kvm" */
5443 struct x86_exception e;
5444
5445 if (force_emulation_prefix &&
3c9fa24c
PB		 5446 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5447 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5448 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5449 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
5450 emul_type = 0;
5451 }
082d06ed 5452
0ce97a2b 5453 er = kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5454 if (er == EMULATE_USER_EXIT)
5455 return 0;
5456 if (er != EMULATE_DONE)
5457 kvm_queue_exception(vcpu, UD_VECTOR);
5458 return 1;
5459}
5460EXPORT_SYMBOL_GPL(handle_ud);
5461
0f89b207
TL		 5462static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5463 gpa_t gpa, bool write)
5464{
5465 /* For APIC access vmexit */
5466 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5467 return 1;
5468
5469 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5470 trace_vcpu_match_mmio(gva, gpa, write, true);
5471 return 1;
5472 }
5473
5474 return 0;
5475}
5476
af7cc7d1
XG		 5477static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5478 gpa_t *gpa, struct x86_exception *exception,
5479 bool write)
5480{
97d64b78
AK		 5481 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5482 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5483
be94f6b7
HH		 5484 /*
5485 * currently PKRU is only applied to ept enabled guest so
5486 * there is no pkey in EPT page table for L1 guest or EPT
5487 * shadow page table for L2 guest.
5488 */
97d64b78 5489 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5490 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
871bd034 5491 vcpu->arch.mmio_access, 0, access)) {
bebb106a
XG		 5492 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5493 (gva & (PAGE_SIZE - 1));
4f022648 5494 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5495 return 1;
5496 }
5497
af7cc7d1
XG		 5498 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5499
5500 if (*gpa == UNMAPPED_GVA)
5501 return -1;
5502
0f89b207 5503 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5504}
5505
3200f405 5506int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5507 const void *val, int bytes)
bbd9b64e
CO		 5508{
5509 int ret;
5510
54bf36aa 5511 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5512 if (ret < 0)
bbd9b64e 5513 return 0;
0eb05bf2 5514 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5515 return 1;
5516}
5517
77d197b2
XG		 5518struct read_write_emulator_ops {
5519 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5520 int bytes);
5521 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5522 void *val, int bytes);
5523 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5524 int bytes, void *val);
5525 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5526 void *val, int bytes);
5527 bool write;
5528};
5529
5530static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5531{
5532 if (vcpu->mmio_read_completed) {
77d197b2 5533 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5534 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5535 vcpu->mmio_read_completed = 0;
5536 return 1;
5537 }
5538
5539 return 0;
5540}
5541
5542static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5543 void *val, int bytes)
5544{
54bf36aa 5545 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5546}
5547
5548static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5549 void *val, int bytes)
5550{
5551 return emulator_write_phys(vcpu, gpa, val, bytes);
5552}
5553
5554static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5555{
e39d200f 5556 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5557 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5558}
5559
5560static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5561 void *val, int bytes)
5562{
e39d200f 5563 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5564 return X86EMUL_IO_NEEDED;
5565}
5566
5567static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5568 void *val, int bytes)
5569{
f78146b0
AK		 5570 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5571
87da7e66 5572 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5573 return X86EMUL_CONTINUE;
5574}
5575
0fbe9b0b 5576static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5577 .read_write_prepare = read_prepare,
5578 .read_write_emulate = read_emulate,
5579 .read_write_mmio = vcpu_mmio_read,
5580 .read_write_exit_mmio = read_exit_mmio,
5581};
5582
0fbe9b0b 5583static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5584 .read_write_emulate = write_emulate,
5585 .read_write_mmio = write_mmio,
5586 .read_write_exit_mmio = write_exit_mmio,
5587 .write = true,
5588};
5589
22388a3c
XG		 5590static int emulator_read_write_onepage(unsigned long addr, void *val,
5591 unsigned int bytes,
5592 struct x86_exception *exception,
5593 struct kvm_vcpu *vcpu,
0fbe9b0b 5594 const struct read_write_emulator_ops *ops)
bbd9b64e 5595{
af7cc7d1
XG		 5596 gpa_t gpa;
5597 int handled, ret;
22388a3c 5598 bool write = ops->write;
f78146b0 5599 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5600 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5601
5602 /*
5603 * If the exit was due to a NPF we may already have a GPA.
5604 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5605 * Note, this cannot be used on string operations since string
5606 * operation using rep will only have the initial GPA from the NPF
5607 * occurred.
5608 */
5609 if (vcpu->arch.gpa_available &&
5610 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5611 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5612 gpa = vcpu->arch.gpa_val;
5613 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5614 } else {
5615 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5616 if (ret < 0)
5617 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5618 }
10589a46 5619
618232e2 5620 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5621 return X86EMUL_CONTINUE;
5622
bbd9b64e
CO		 5623 /*
5624 * Is this MMIO handled locally?
5625 */
22388a3c 5626 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5627 if (handled == bytes)
bbd9b64e 5628 return X86EMUL_CONTINUE;
bbd9b64e 5629
70252a10
AK		 5630 gpa += handled;
5631 bytes -= handled;
5632 val += handled;
5633
87da7e66
XG		 5634 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5635 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5636 frag->gpa = gpa;
5637 frag->data = val;
5638 frag->len = bytes;
f78146b0 5639 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5640}
5641
52eb5a6d
XL		 5642static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5643 unsigned long addr,
22388a3c
XG		 5644 void *val, unsigned int bytes,
5645 struct x86_exception *exception,
0fbe9b0b 5646 const struct read_write_emulator_ops *ops)
bbd9b64e 5647{
0f65dd70 5648 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5649 gpa_t gpa;
5650 int rc;
5651
5652 if (ops->read_write_prepare &&
5653 ops->read_write_prepare(vcpu, val, bytes))
5654 return X86EMUL_CONTINUE;
5655
5656 vcpu->mmio_nr_fragments = 0;
0f65dd70 5657
bbd9b64e
CO		 5658 /* Crossing a page boundary? */
5659 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5660 int now;
bbd9b64e
CO		 5661
5662 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5663 rc = emulator_read_write_onepage(addr, val, now, exception,
5664 vcpu, ops);
5665
bbd9b64e
CO		 5666 if (rc != X86EMUL_CONTINUE)
5667 return rc;
5668 addr += now;
bac15531
NA		 5669 if (ctxt->mode != X86EMUL_MODE_PROT64)
5670 addr = (u32)addr;
bbd9b64e
CO		 5671 val += now;
5672 bytes -= now;
5673 }
22388a3c 5674
f78146b0
AK		 5675 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5676 vcpu, ops);
5677 if (rc != X86EMUL_CONTINUE)
5678 return rc;
5679
5680 if (!vcpu->mmio_nr_fragments)
5681 return rc;
5682
5683 gpa = vcpu->mmio_fragments[0].gpa;
5684
5685 vcpu->mmio_needed = 1;
5686 vcpu->mmio_cur_fragment = 0;
5687
87da7e66 5688 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5689 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5690 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5691 vcpu->run->mmio.phys_addr = gpa;
5692
5693 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5694}
5695
5696static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5697 unsigned long addr,
5698 void *val,
5699 unsigned int bytes,
5700 struct x86_exception *exception)
5701{
5702 return emulator_read_write(ctxt, addr, val, bytes,
5703 exception, &read_emultor);
5704}
5705
52eb5a6d 5706static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5707 unsigned long addr,
5708 const void *val,
5709 unsigned int bytes,
5710 struct x86_exception *exception)
5711{
5712 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5713 exception, &write_emultor);
bbd9b64e 5714}
bbd9b64e 5715
daea3e73
AK		 5716#define CMPXCHG_TYPE(t, ptr, old, new) \
5717 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5718
5719#ifdef CONFIG_X86_64
5720# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5721#else
5722# define CMPXCHG64(ptr, old, new) \
9749a6c0 5723 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5724#endif
5725
0f65dd70
AK		 5726static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5727 unsigned long addr,
bbd9b64e
CO		 5728 const void *old,
5729 const void *new,
5730 unsigned int bytes,
0f65dd70 5731 struct x86_exception *exception)
bbd9b64e 5732{
42e35f80 5733 struct kvm_host_map map;
0f65dd70 5734 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73 5735 gpa_t gpa;
daea3e73
AK		 5736 char *kaddr;
5737 bool exchanged;
2bacc55c 5738
daea3e73
AK		 5739 /* guests cmpxchg8b have to be emulated atomically */
5740 if (bytes > 8 || (bytes & (bytes - 1)))
5741 goto emul_write;
10589a46 5742
daea3e73 5743 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5744
daea3e73
AK		 5745 if (gpa == UNMAPPED_GVA ||
5746 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5747 goto emul_write;
2bacc55c 5748
daea3e73
AK		 5749 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5750 goto emul_write;
72dc67a6 5751
42e35f80 5752 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
c19b8bd6 5753 goto emul_write;
72dc67a6 5754
42e35f80
KA		 5755 kaddr = map.hva + offset_in_page(gpa);
5756
daea3e73
AK		 5757 switch (bytes) {
5758 case 1:
5759 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5760 break;
5761 case 2:
5762 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5763 break;
5764 case 4:
5765 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5766 break;
5767 case 8:
5768 exchanged = CMPXCHG64(kaddr, old, new);
5769 break;
5770 default:
5771 BUG();
2bacc55c 5772 }
42e35f80
KA		 5773
5774 kvm_vcpu_unmap(vcpu, &map, true);
daea3e73
AK		 5775
5776 if (!exchanged)
5777 return X86EMUL_CMPXCHG_FAILED;
5778
0eb05bf2 5779 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5780
5781 return X86EMUL_CONTINUE;
4a5f48f6 5782
3200f405 5783emul_write:
daea3e73 5784 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5785
0f65dd70 5786 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5787}
5788
cf8f70bf
GN		 5789static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5790{
cbfc6c91 5791 int r = 0, i;
cf8f70bf 5792
cbfc6c91
WL		 5793 for (i = 0; i < vcpu->arch.pio.count; i++) {
5794 if (vcpu->arch.pio.in)
5795 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5796 vcpu->arch.pio.size, pd);
5797 else
5798 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5799 vcpu->arch.pio.port, vcpu->arch.pio.size,
5800 pd);
5801 if (r)
5802 break;
5803 pd += vcpu->arch.pio.size;
5804 }
cf8f70bf
GN		 5805 return r;
5806}
5807
6f6fbe98
XG		 5808static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5809 unsigned short port, void *val,
5810 unsigned int count, bool in)
cf8f70bf 5811{
cf8f70bf 5812 vcpu->arch.pio.port = port;
6f6fbe98 5813 vcpu->arch.pio.in = in;
7972995b 5814 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5815 vcpu->arch.pio.size = size;
5816
5817 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5818 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5819 return 1;
5820 }
5821
5822 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5823 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5824 vcpu->run->io.size = size;
5825 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5826 vcpu->run->io.count = count;
5827 vcpu->run->io.port = port;
5828
5829 return 0;
5830}
5831
6f6fbe98
XG		 5832static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5833 int size, unsigned short port, void *val,
5834 unsigned int count)
cf8f70bf 5835{
ca1d4a9e 5836 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5837 int ret;
ca1d4a9e 5838
6f6fbe98
XG		 5839 if (vcpu->arch.pio.count)
5840 goto data_avail;
cf8f70bf 5841
cbfc6c91
WL		 5842 memset(vcpu->arch.pio_data, 0, size * count);
5843
6f6fbe98
XG		 5844 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5845 if (ret) {
5846data_avail:
5847 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5848 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5849 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5850 return 1;
5851 }
5852
cf8f70bf
GN		 5853 return 0;
5854}
5855
6f6fbe98
XG		 5856static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5857 int size, unsigned short port,
5858 const void *val, unsigned int count)
5859{
5860 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5861
5862 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5863 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5864 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5865}
5866
bbd9b64e
CO		 5867static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5868{
5869 return kvm_x86_ops->get_segment_base(vcpu, seg);
5870}
5871
3cb16fe7 5872static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5873{
3cb16fe7 5874 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5875}
5876
ae6a2375 5877static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5878{
5879 if (!need_emulate_wbinvd(vcpu))
5880 return X86EMUL_CONTINUE;
5881
5882 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5883 int cpu = get_cpu();
5884
5885 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5886 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5887 wbinvd_ipi, NULL, 1);
2eec7343 5888 put_cpu();
f5f48ee1 5889 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5890 } else
5891 wbinvd();
f5f48ee1
SY		 5892 return X86EMUL_CONTINUE;
5893}
5cb56059
JS		 5894
5895int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5896{
6affcbed
KH		 5897 kvm_emulate_wbinvd_noskip(vcpu);
5898 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5899}
f5f48ee1
SY		 5900EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5901
5cb56059
JS		 5902
5903
bcaf5cc5
AK		 5904static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5905{
5cb56059 5906 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5907}
5908
52eb5a6d
XL		 5909static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5910 unsigned long *dest)
bbd9b64e 5911{
16f8a6f9 5912 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5913}
5914
52eb5a6d
XL		 5915static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5916 unsigned long value)
bbd9b64e 5917{
338dbc97 5918
717746e3 5919 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5920}
5921
52a46617 5922static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5923{
52a46617 5924 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5925}
5926
717746e3 5927static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5928{
717746e3 5929 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5930 unsigned long value;
5931
5932 switch (cr) {
5933 case 0:
5934 value = kvm_read_cr0(vcpu);
5935 break;
5936 case 2:
5937 value = vcpu->arch.cr2;
5938 break;
5939 case 3:
9f8fe504 5940 value = kvm_read_cr3(vcpu);
52a46617
GN		 5941 break;
5942 case 4:
5943 value = kvm_read_cr4(vcpu);
5944 break;
5945 case 8:
5946 value = kvm_get_cr8(vcpu);
5947 break;
5948 default:
a737f256 5949 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5950 return 0;
5951 }
5952
5953 return value;
5954}
5955
717746e3 5956static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5957{
717746e3 5958 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5959 int res = 0;
5960
52a46617
GN		 5961 switch (cr) {
5962 case 0:
49a9b07e 5963 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5964 break;
5965 case 2:
5966 vcpu->arch.cr2 = val;
5967 break;
5968 case 3:
2390218b 5969 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5970 break;
5971 case 4:
a83b29c6 5972 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5973 break;
5974 case 8:
eea1cff9 5975 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5976 break;
5977 default:
a737f256 5978 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5979 res = -1;
52a46617 5980 }
0f12244f
GN		 5981
5982 return res;
52a46617
GN		 5983}
5984
717746e3 5985static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5986{
717746e3 5987 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5988}
5989
4bff1e86 5990static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5991{
4bff1e86 5992 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5993}
5994
4bff1e86 5995static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5996{
4bff1e86 5997 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5998}
5999
1ac9d0cf
AK		 6000static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6001{
6002 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
6003}
6004
6005static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6006{
6007 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6008}
6009
4bff1e86
AK		 6010static unsigned long emulator_get_cached_segment_base(
6011 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 6012{
4bff1e86 6013 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 6014}
6015
1aa36616
AK		 6016static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6017 struct desc_struct *desc, u32 *base3,
6018 int seg)
2dafc6c2
GN		 6019{
6020 struct kvm_segment var;
6021
4bff1e86 6022 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 6023 *selector = var.selector;
2dafc6c2 6024
378a8b09
GN		 6025 if (var.unusable) {
6026 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 6027 if (base3)
6028 *base3 = 0;
2dafc6c2 6029 return false;
378a8b09 6030 }
2dafc6c2
GN		 6031
6032 if (var.g)
6033 var.limit >>= 12;
6034 set_desc_limit(desc, var.limit);
6035 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 6036#ifdef CONFIG_X86_64
6037 if (base3)
6038 *base3 = var.base >> 32;
6039#endif
2dafc6c2
GN		 6040 desc->type = var.type;
6041 desc->s = var.s;
6042 desc->dpl = var.dpl;
6043 desc->p = var.present;
6044 desc->avl = var.avl;
6045 desc->l = var.l;
6046 desc->d = var.db;
6047 desc->g = var.g;
6048
6049 return true;
6050}
6051
1aa36616
AK		 6052static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6053 struct desc_struct *desc, u32 base3,
6054 int seg)
2dafc6c2 6055{
4bff1e86 6056 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 6057 struct kvm_segment var;
6058
1aa36616 6059 var.selector = selector;
2dafc6c2 6060 var.base = get_desc_base(desc);
5601d05b
GN		 6061#ifdef CONFIG_X86_64
6062 var.base |= ((u64)base3) << 32;
6063#endif
2dafc6c2
GN		 6064 var.limit = get_desc_limit(desc);
6065 if (desc->g)
6066 var.limit = (var.limit << 12) | 0xfff;
6067 var.type = desc->type;
2dafc6c2
GN		 6068 var.dpl = desc->dpl;
6069 var.db = desc->d;
6070 var.s = desc->s;
6071 var.l = desc->l;
6072 var.g = desc->g;
6073 var.avl = desc->avl;
6074 var.present = desc->p;
6075 var.unusable = !var.present;
6076 var.padding = 0;
6077
6078 kvm_set_segment(vcpu, &var, seg);
6079 return;
6080}
6081
717746e3
AK		 6082static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6083 u32 msr_index, u64 *pdata)
6084{
f20935d8 6085 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
717746e3
AK		 6086}
6087
6088static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6089 u32 msr_index, u64 data)
6090{
f20935d8 6091 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
717746e3
AK		 6092}
6093
64d60670
PB		 6094static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6095{
6096 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6097
6098 return vcpu->arch.smbase;
6099}
6100
6101static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6102{
6103 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6104
6105 vcpu->arch.smbase = smbase;
6106}
6107
67f4d428
NA		 6108static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6109 u32 pmc)
6110{
c6702c9d 6111 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 6112}
6113
222d21aa
AK		 6114static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6115 u32 pmc, u64 *pdata)
6116{
c6702c9d 6117 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 6118}
6119
6c3287f7
AK		 6120static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6121{
6122 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6123}
6124
2953538e 6125static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 6126 struct x86_instruction_info *info,
c4f035c6
AK		 6127 enum x86_intercept_stage stage)
6128{
2953538e 6129 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 6130}
6131
e911eb3b
YZ		 6132static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6133 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 6134{
e911eb3b 6135 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 6136}
6137
dd856efa
AK		 6138static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6139{
6140 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6141}
6142
6143static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6144{
6145 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6146}
6147
801806d9
NA		 6148static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6149{
6150 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6151}
6152
6ed071f0
LP		 6153static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6154{
6155 return emul_to_vcpu(ctxt)->arch.hflags;
6156}
6157
6158static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6159{
c5833c7a 6160 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6ed071f0
LP		 6161}
6162
ed19321f
SC		 6163static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6164 const char *smstate)
0234bf88 6165{
ed19321f 6166 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
0234bf88
LP		 6167}
6168
c5833c7a
SC		 6169static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6170{
6171 kvm_smm_changed(emul_to_vcpu(ctxt));
6172}
6173
02d4160f
VK		 6174static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6175{
6176 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6177}
6178
0225fb50 6179static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 6180 .read_gpr = emulator_read_gpr,
6181 .write_gpr = emulator_write_gpr,
ce14e868
PB		 6182 .read_std = emulator_read_std,
6183 .write_std = emulator_write_std,
7a036a6f 6184 .read_phys = kvm_read_guest_phys_system,
1871c602 6185 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 6186 .read_emulated = emulator_read_emulated,
6187 .write_emulated = emulator_write_emulated,
6188 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 6189 .invlpg = emulator_invlpg,
cf8f70bf
GN		 6190 .pio_in_emulated = emulator_pio_in_emulated,
6191 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 6192 .get_segment = emulator_get_segment,
6193 .set_segment = emulator_set_segment,
5951c442 6194 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 6195 .get_gdt = emulator_get_gdt,
160ce1f1 6196 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 6197 .set_gdt = emulator_set_gdt,
6198 .set_idt = emulator_set_idt,
52a46617
GN		 6199 .get_cr = emulator_get_cr,
6200 .set_cr = emulator_set_cr,
9c537244 6201 .cpl = emulator_get_cpl,
35aa5375
GN		 6202 .get_dr = emulator_get_dr,
6203 .set_dr = emulator_set_dr,
64d60670
PB		 6204 .get_smbase = emulator_get_smbase,
6205 .set_smbase = emulator_set_smbase,
717746e3
AK		 6206 .set_msr = emulator_set_msr,
6207 .get_msr = emulator_get_msr,
67f4d428 6208 .check_pmc = emulator_check_pmc,
222d21aa 6209 .read_pmc = emulator_read_pmc,
6c3287f7 6210 .halt = emulator_halt,
bcaf5cc5 6211 .wbinvd = emulator_wbinvd,
d6aa1000 6212 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 6213 .intercept = emulator_intercept,
bdb42f5a 6214 .get_cpuid = emulator_get_cpuid,
801806d9 6215 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 6216 .get_hflags = emulator_get_hflags,
6217 .set_hflags = emulator_set_hflags,
0234bf88 6218 .pre_leave_smm = emulator_pre_leave_smm,
c5833c7a 6219 .post_leave_smm = emulator_post_leave_smm,
02d4160f 6220 .set_xcr = emulator_set_xcr,
bbd9b64e
CO		 6221};
6222
95cb2295
GN		 6223static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6224{
37ccdcbe 6225 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 6226 /*
6227 * an sti; sti; sequence only disable interrupts for the first
6228 * instruction. So, if the last instruction, be it emulated or
6229 * not, left the system with the INT_STI flag enabled, it
6230 * means that the last instruction is an sti. We should not
6231 * leave the flag on in this case. The same goes for mov ss
6232 */
37ccdcbe
PB		 6233 if (int_shadow & mask)
6234 mask = 0;
6addfc42 6235 if (unlikely(int_shadow || mask)) {
95cb2295 6236 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 6237 if (!mask)
6238 kvm_make_request(KVM_REQ_EVENT, vcpu);
6239 }
95cb2295
GN		 6240}
6241
ef54bcfe 6242static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 6243{
6244 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 6245 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 6246 return kvm_propagate_fault(vcpu, &ctxt->exception);
6247
6248 if (ctxt->exception.error_code_valid)
da9cb575
AK		 6249 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6250 ctxt->exception.error_code);
54b8486f 6251 else
da9cb575 6252 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 6253 return false;
54b8486f
GN		 6254}
6255
8ec4722d
MG		 6256static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6257{
adf52235 6258 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 6259 int cs_db, cs_l;
6260
8ec4722d
MG		 6261 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6262
adf52235 6263 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 6264 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6265
adf52235
TY		 6266 ctxt->eip = kvm_rip_read(vcpu);
6267 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6268 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6269 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6270 cs_db ? X86EMUL_MODE_PROT32 :
6271 X86EMUL_MODE_PROT16;
a584539b 6272 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6273 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6274 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6275
dd856efa 6276 init_decode_cache(ctxt);
7ae441ea 6277 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6278}
6279
71f9833b 6280int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6281{
9d74191a 6282 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6283 int ret;
6284
6285 init_emulate_ctxt(vcpu);
6286
9dac77fa
AK		 6287 ctxt->op_bytes = 2;
6288 ctxt->ad_bytes = 2;
6289 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6290 ret = emulate_int_real(ctxt, irq);
63995653
MG		 6291
6292 if (ret != X86EMUL_CONTINUE)
6293 return EMULATE_FAIL;
6294
9dac77fa 6295 ctxt->eip = ctxt->_eip;
9d74191a
TY		 6296 kvm_rip_write(vcpu, ctxt->eip);
6297 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 6298
63995653
MG		 6299 return EMULATE_DONE;
6300}
6301EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6302
e2366171 6303static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6304{
fc3a9157
JR		 6305 int r = EMULATE_DONE;
6306
6d77dbfc
GN		 6307 ++vcpu->stat.insn_emulation_fail;
6308 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 6309
6310 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
6311 return EMULATE_FAIL;
6312
a2b9e6c1 6313 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6314 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6315 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6316 vcpu->run->internal.ndata = 0;
1f4dcb3b 6317 r = EMULATE_USER_EXIT;
fc3a9157 6318 }
e2366171 6319
6d77dbfc 6320 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 6321
6322 return r;
6d77dbfc
GN		 6323}
6324
93c05d3e 6325static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6326 bool write_fault_to_shadow_pgtable,
6327 int emulation_type)
a6f177ef 6328{
95b3cf69 6329 gpa_t gpa = cr2;
ba049e93 6330 kvm_pfn_t pfn;
a6f177ef 6331
384bf221 6332 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6333 return false;
6334
6c3dfeb6
SC		 6335 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6336 return false;
6337
44dd3ffa 6338 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6339 /*
6340 * Write permission should be allowed since only
6341 * write access need to be emulated.
6342 */
6343 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6344
95b3cf69
XG		 6345 /*
6346 * If the mapping is invalid in guest, let cpu retry
6347 * it to generate fault.
6348 */
6349 if (gpa == UNMAPPED_GVA)
6350 return true;
6351 }
a6f177ef 6352
8e3d9d06
XG		 6353 /*
6354 * Do not retry the unhandleable instruction if it faults on the
6355 * readonly host memory, otherwise it will goto a infinite loop:
6356 * retry instruction -> write #PF -> emulation fail -> retry
6357 * instruction -> ...
6358 */
6359 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6360
6361 /*
6362 * If the instruction failed on the error pfn, it can not be fixed,
6363 * report the error to userspace.
6364 */
6365 if (is_error_noslot_pfn(pfn))
6366 return false;
6367
6368 kvm_release_pfn_clean(pfn);
6369
6370 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6371 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6372 unsigned int indirect_shadow_pages;
6373
6374 spin_lock(&vcpu->kvm->mmu_lock);
6375 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6376 spin_unlock(&vcpu->kvm->mmu_lock);
6377
6378 if (indirect_shadow_pages)
6379 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6380
a6f177ef 6381 return true;
8e3d9d06 6382 }
a6f177ef 6383
95b3cf69
XG		 6384 /*
6385 * if emulation was due to access to shadowed page table
6386 * and it failed try to unshadow page and re-enter the
6387 * guest to let CPU execute the instruction.
6388 */
6389 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6390
6391 /*
6392 * If the access faults on its page table, it can not
6393 * be fixed by unprotecting shadow page and it should
6394 * be reported to userspace.
6395 */
6396 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6397}
6398
1cb3f3ae
XG		 6399static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6400 unsigned long cr2, int emulation_type)
6401{
6402 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6403 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6404
6405 last_retry_eip = vcpu->arch.last_retry_eip;
6406 last_retry_addr = vcpu->arch.last_retry_addr;
6407
6408 /*
6409 * If the emulation is caused by #PF and it is non-page_table
6410 * writing instruction, it means the VM-EXIT is caused by shadow
6411 * page protected, we can zap the shadow page and retry this
6412 * instruction directly.
6413 *
6414 * Note: if the guest uses a non-page-table modifying instruction
6415 * on the PDE that points to the instruction, then we will unmap
6416 * the instruction and go to an infinite loop. So, we cache the
6417 * last retried eip and the last fault address, if we meet the eip
6418 * and the address again, we can break out of the potential infinite
6419 * loop.
6420 */
6421 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6422
384bf221 6423 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6424 return false;
6425
6c3dfeb6
SC		 6426 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6427 return false;
6428
1cb3f3ae
XG		 6429 if (x86_page_table_writing_insn(ctxt))
6430 return false;
6431
6432 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6433 return false;
6434
6435 vcpu->arch.last_retry_eip = ctxt->eip;
6436 vcpu->arch.last_retry_addr = cr2;
6437
44dd3ffa 6438 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6439 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6440
22368028 6441 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6442
6443 return true;
6444}
6445
716d51ab
GN		 6446static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6447static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6448
64d60670 6449static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6450{
64d60670 6451 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6452 /* This is a good place to trace that we are exiting SMM. */
6453 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6454
c43203ca
PB		 6455 /* Process a latched INIT or SMI, if any. */
6456 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6457 }
699023e2
PB		 6458
6459 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6460}
6461
4a1e10d5
PB		 6462static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6463 unsigned long *db)
6464{
6465 u32 dr6 = 0;
6466 int i;
6467 u32 enable, rwlen;
6468
6469 enable = dr7;
6470 rwlen = dr7 >> 16;
6471 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6472 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6473 dr6 |= (1 << i);
6474 return dr6;
6475}
6476
c8401dda 6477static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6478{
6479 struct kvm_run *kvm_run = vcpu->run;
6480
c8401dda
PB		 6481 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6482 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6483 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6484 kvm_run->debug.arch.exception = DB_VECTOR;
6485 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6486 *r = EMULATE_USER_EXIT;
6487 } else {
f10c729f 6488 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
663f4c61
PB		 6489 }
6490}
6491
6affcbed
KH		 6492int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6493{
6494 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
f8ea7c60 6495 int r;
6affcbed 6496
f8ea7c60
VK		 6497 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
6498 if (unlikely(r != EMULATE_DONE))
6499 return 0;
c8401dda
PB		 6500
6501 /*
6502 * rflags is the old, "raw" value of the flags. The new value has
6503 * not been saved yet.
6504 *
6505 * This is correct even for TF set by the guest, because "the
6506 * processor will not generate this exception after the instruction
6507 * that sets the TF flag".
6508 */
6509 if (unlikely(rflags & X86_EFLAGS_TF))
6510 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6511 return r == EMULATE_DONE;
6512}
6513EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6514
4a1e10d5
PB		 6515static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6516{
4a1e10d5
PB		 6517 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6518 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6519 struct kvm_run *kvm_run = vcpu->run;
6520 unsigned long eip = kvm_get_linear_rip(vcpu);
6521 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6522 vcpu->arch.guest_debug_dr7,
6523 vcpu->arch.eff_db);
6524
6525 if (dr6 != 0) {
6f43ed01 6526 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6527 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6528 kvm_run->debug.arch.exception = DB_VECTOR;
6529 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6530 *r = EMULATE_USER_EXIT;
6531 return true;
6532 }
6533 }
6534
4161a569
NA		 6535 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6536 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6537 unsigned long eip = kvm_get_linear_rip(vcpu);
6538 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6539 vcpu->arch.dr7,
6540 vcpu->arch.db);
6541
6542 if (dr6 != 0) {
1fc5d194 6543 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 6544 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6545 kvm_queue_exception(vcpu, DB_VECTOR);
6546 *r = EMULATE_DONE;
6547 return true;
6548 }
6549 }
6550
6551 return false;
6552}
6553
04789b66
LA		 6554static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6555{
2d7921c4
AM		 6556 switch (ctxt->opcode_len) {
6557 case 1:
6558 switch (ctxt->b) {
6559 case 0xe4: /* IN */
6560 case 0xe5:
6561 case 0xec:
6562 case 0xed:
6563 case 0xe6: /* OUT */
6564 case 0xe7:
6565 case 0xee:
6566 case 0xef:
6567 case 0x6c: /* INS */
6568 case 0x6d:
6569 case 0x6e: /* OUTS */
6570 case 0x6f:
6571 return true;
6572 }
6573 break;
6574 case 2:
6575 switch (ctxt->b) {
6576 case 0x33: /* RDPMC */
6577 return true;
6578 }
6579 break;
04789b66
LA		 6580 }
6581
6582 return false;
6583}
6584
51d8b661
AP		 6585int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6586 unsigned long cr2,
dc25e89e
AP		 6587 int emulation_type,
6588 void *insn,
6589 int insn_len)
bbd9b64e 6590{
95cb2295 6591 int r;
9d74191a 6592 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6593 bool writeback = true;
93c05d3e 6594 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6595
c595ceee
PB		 6596 vcpu->arch.l1tf_flush_l1d = true;
6597
93c05d3e
XG		 6598 /*
6599 * Clear write_fault_to_shadow_pgtable here to ensure it is
6600 * never reused.
6601 */
6602 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6603 kvm_clear_exception_queue(vcpu);
8d7d8102 6604
571008da 6605 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6606 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6607
6608 /*
6609 * We will reenter on the same instruction since
6610 * we do not set complete_userspace_io. This does not
6611 * handle watchpoints yet, those would be handled in
6612 * the emulate_ops.
6613 */
d391f120
VK		 6614 if (!(emulation_type & EMULTYPE_SKIP) &&
6615 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6616 return r;
6617
9d74191a
TY		 6618 ctxt->interruptibility = 0;
6619 ctxt->have_exception = false;
e0ad0b47 6620 ctxt->exception.vector = -1;
9d74191a 6621 ctxt->perm_ok = false;
bbd9b64e 6622
b51e974f 6623 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6624
9d74191a 6625 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6626
e46479f8 6627 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6628 ++vcpu->stat.insn_emulation;
1d2887e2 6629 if (r != EMULATION_OK) {
4005996e
AK		 6630 if (emulation_type & EMULTYPE_TRAP_UD)
6631 return EMULATE_FAIL;
991eebf9
GN		 6632 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6633 emulation_type))
bbd9b64e 6634 return EMULATE_DONE;
8530a79c 6635 if (ctxt->have_exception) {
c8848cee
JD		 6636 /*
6637 * #UD should result in just EMULATION_FAILED, and trap-like
6638 * exception should not be encountered during decode.
6639 */
6640 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6641 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8530a79c 6642 inject_emulated_exception(vcpu);
6ea6e843 6643 return EMULATE_DONE;
8530a79c 6644 }
6d77dbfc
GN		 6645 if (emulation_type & EMULTYPE_SKIP)
6646 return EMULATE_FAIL;
e2366171 6647 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6648 }
6649 }
6650
04789b66
LA		 6651 if ((emulation_type & EMULTYPE_VMWARE) &&
6652 !is_vmware_backdoor_opcode(ctxt))
6653 return EMULATE_FAIL;
6654
ba8afb6b 6655 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6656 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6657 if (ctxt->eflags & X86_EFLAGS_RF)
6658 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
97413d29 6659 kvm_x86_ops->set_interrupt_shadow(vcpu, 0);
ba8afb6b
GN		 6660 return EMULATE_DONE;
6661 }
6662
1cb3f3ae
XG		 6663 if (retry_instruction(ctxt, cr2, emulation_type))
6664 return EMULATE_DONE;
6665
7ae441ea 6666 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6667 changes registers values during IO operation */
7ae441ea
GN		 6668 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6669 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6670 emulator_invalidate_register_cache(ctxt);
7ae441ea 6671 }
4d2179e1 6672
5cd21917 6673restart:
0f89b207
TL		 6674 /* Save the faulting GPA (cr2) in the address field */
6675 ctxt->exception.address = cr2;
6676
9d74191a 6677 r = x86_emulate_insn(ctxt);
bbd9b64e 6678
775fde86
JR		 6679 if (r == EMULATION_INTERCEPTED)
6680 return EMULATE_DONE;
6681
d2ddd1c4 6682 if (r == EMULATION_FAILED) {
991eebf9
GN		 6683 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6684 emulation_type))
c3cd7ffa
GN		 6685 return EMULATE_DONE;
6686
e2366171 6687 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6688 }
6689
9d74191a 6690 if (ctxt->have_exception) {
d2ddd1c4 6691 r = EMULATE_DONE;
ef54bcfe
PB		 6692 if (inject_emulated_exception(vcpu))
6693 return r;
d2ddd1c4 6694 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6695 if (!vcpu->arch.pio.in) {
6696 /* FIXME: return into emulator if single-stepping. */
3457e419 6697 vcpu->arch.pio.count = 0;
0912c977 6698 } else {
7ae441ea 6699 writeback = false;
716d51ab
GN		 6700 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6701 }
ac0a48c3 6702 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6703 } else if (vcpu->mmio_needed) {
6704 if (!vcpu->mmio_is_write)
6705 writeback = false;
ac0a48c3 6706 r = EMULATE_USER_EXIT;
716d51ab 6707 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6708 } else if (r == EMULATION_RESTART)
5cd21917 6709 goto restart;
d2ddd1c4
GN		 6710 else
6711 r = EMULATE_DONE;
f850e2e6 6712
7ae441ea 6713 if (writeback) {
6addfc42 6714 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6715 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6716 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
38827dbd 6717 if (!ctxt->have_exception ||
75ee23b3
SC		 6718 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6719 kvm_rip_write(vcpu, ctxt->eip);
6720 if (r == EMULATE_DONE && ctxt->tf)
6721 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd 6722 __kvm_set_rflags(vcpu, ctxt->eflags);
75ee23b3 6723 }
6addfc42
PB		 6724
6725 /*
6726 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6727 * do nothing, and it will be requested again as soon as
6728 * the shadow expires. But we still need to check here,
6729 * because POPF has no interrupt shadow.
6730 */
6731 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6732 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6733 } else
6734 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6735
6736 return r;
de7d789a 6737}
c60658d1
SC		 6738
6739int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6740{
6741 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6742}
6743EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6744
6745int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6746 void *insn, int insn_len)
6747{
6748 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6749}
6750EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6751
8764ed55
SC		 6752static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6753{
6754 vcpu->arch.pio.count = 0;
6755 return 1;
6756}
6757
45def77e
SC		 6758static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6759{
6760 vcpu->arch.pio.count = 0;
6761
6762 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6763 return 1;
6764
6765 return kvm_skip_emulated_instruction(vcpu);
6766}
6767
dca7f128
SC		 6768static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6769 unsigned short port)
de7d789a 6770{
de3cd117 6771 unsigned long val = kvm_rax_read(vcpu);
ca1d4a9e
AK		 6772 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6773 size, port, &val, 1);
8764ed55
SC		 6774 if (ret)
6775 return ret;
45def77e 6776
8764ed55
SC		 6777 /*
6778 * Workaround userspace that relies on old KVM behavior of %rip being
6779 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6780 */
6781 if (port == 0x7e &&
6782 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6783 vcpu->arch.complete_userspace_io =
6784 complete_fast_pio_out_port_0x7e;
6785 kvm_skip_emulated_instruction(vcpu);
6786 } else {
45def77e
SC		 6787 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6788 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6789 }
8764ed55 6790 return 0;
de7d789a 6791}
de7d789a 6792
8370c3d0
TL		 6793static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6794{
6795 unsigned long val;
6796
6797 /* We should only ever be called with arch.pio.count equal to 1 */
6798 BUG_ON(vcpu->arch.pio.count != 1);
6799
45def77e
SC		 6800 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6801 vcpu->arch.pio.count = 0;
6802 return 1;
6803 }
6804
8370c3d0 6805 /* For size less than 4 we merge, else we zero extend */
de3cd117 6806 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6807
6808 /*
6809 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6810 * the copy and tracing
6811 */
6812 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6813 vcpu->arch.pio.port, &val, 1);
de3cd117 6814 kvm_rax_write(vcpu, val);
8370c3d0 6815
45def77e 6816 return kvm_skip_emulated_instruction(vcpu);
8370c3d0
TL		 6817}
6818
dca7f128
SC		 6819static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6820 unsigned short port)
8370c3d0
TL		 6821{
6822 unsigned long val;
6823 int ret;
6824
6825 /* For size less than 4 we merge, else we zero extend */
de3cd117 6826 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6827
6828 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6829 &val, 1);
6830 if (ret) {
de3cd117 6831 kvm_rax_write(vcpu, val);
8370c3d0
TL		 6832 return ret;
6833 }
6834
45def77e 6835 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8370c3d0
TL		 6836 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6837
6838 return 0;
6839}
dca7f128
SC		 6840
6841int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6842{
45def77e 6843 int ret;
dca7f128 6844
dca7f128 6845 if (in)
45def77e 6846 ret = kvm_fast_pio_in(vcpu, size, port);
dca7f128 6847 else
45def77e
SC		 6848 ret = kvm_fast_pio_out(vcpu, size, port);
6849 return ret && kvm_skip_emulated_instruction(vcpu);
dca7f128
SC		 6850}
6851EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6852
251a5fd6 6853static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6854{
0a3aee0d 6855 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6856 return 0;
8cfdc000
ZA		 6857}
6858
6859static void tsc_khz_changed(void *data)
c8076604 6860{
8cfdc000
ZA		 6861 struct cpufreq_freqs *freq = data;
6862 unsigned long khz = 0;
6863
6864 if (data)
6865 khz = freq->new;
6866 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6867 khz = cpufreq_quick_get(raw_smp_processor_id());
6868 if (!khz)
6869 khz = tsc_khz;
0a3aee0d 6870 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6871}
6872
5fa4ec9c 6873#ifdef CONFIG_X86_64
0092e434
VK		 6874static void kvm_hyperv_tsc_notifier(void)
6875{
0092e434
VK		 6876 struct kvm *kvm;
6877 struct kvm_vcpu *vcpu;
6878 int cpu;
6879
0d9ce162 6880 mutex_lock(&kvm_lock);
0092e434
VK		 6881 list_for_each_entry(kvm, &vm_list, vm_list)
6882 kvm_make_mclock_inprogress_request(kvm);
6883
6884 hyperv_stop_tsc_emulation();
6885
6886 /* TSC frequency always matches when on Hyper-V */
6887 for_each_present_cpu(cpu)
6888 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6889 kvm_max_guest_tsc_khz = tsc_khz;
6890
6891 list_for_each_entry(kvm, &vm_list, vm_list) {
6892 struct kvm_arch *ka = &kvm->arch;
6893
6894 spin_lock(&ka->pvclock_gtod_sync_lock);
6895
6896 pvclock_update_vm_gtod_copy(kvm);
6897
6898 kvm_for_each_vcpu(cpu, vcpu, kvm)
6899 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6900
6901 kvm_for_each_vcpu(cpu, vcpu, kvm)
6902 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6903
6904 spin_unlock(&ka->pvclock_gtod_sync_lock);
6905 }
0d9ce162 6906 mutex_unlock(&kvm_lock);
0092e434 6907}
5fa4ec9c 6908#endif
0092e434 6909
df24014a 6910static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
c8076604 6911{
c8076604
GH		 6912 struct kvm *kvm;
6913 struct kvm_vcpu *vcpu;
6914 int i, send_ipi = 0;
6915
8cfdc000
ZA		 6916 /*
6917 * We allow guests to temporarily run on slowing clocks,
6918 * provided we notify them after, or to run on accelerating
6919 * clocks, provided we notify them before. Thus time never
6920 * goes backwards.
6921 *
6922 * However, we have a problem. We can't atomically update
6923 * the frequency of a given CPU from this function; it is
6924 * merely a notifier, which can be called from any CPU.
6925 * Changing the TSC frequency at arbitrary points in time
6926 * requires a recomputation of local variables related to
6927 * the TSC for each VCPU. We must flag these local variables
6928 * to be updated and be sure the update takes place with the
6929 * new frequency before any guests proceed.
6930 *
6931 * Unfortunately, the combination of hotplug CPU and frequency
6932 * change creates an intractable locking scenario; the order
6933 * of when these callouts happen is undefined with respect to
6934 * CPU hotplug, and they can race with each other. As such,
6935 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6936 * undefined; you can actually have a CPU frequency change take
6937 * place in between the computation of X and the setting of the
6938 * variable. To protect against this problem, all updates of
6939 * the per_cpu tsc_khz variable are done in an interrupt
6940 * protected IPI, and all callers wishing to update the value
6941 * must wait for a synchronous IPI to complete (which is trivial
6942 * if the caller is on the CPU already). This establishes the
6943 * necessary total order on variable updates.
6944 *
6945 * Note that because a guest time update may take place
6946 * anytime after the setting of the VCPU's request bit, the
6947 * correct TSC value must be set before the request. However,
6948 * to ensure the update actually makes it to any guest which
6949 * starts running in hardware virtualization between the set
6950 * and the acquisition of the spinlock, we must also ping the
6951 * CPU after setting the request bit.
6952 *
6953 */
6954
df24014a 6955 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6956
0d9ce162 6957 mutex_lock(&kvm_lock);
c8076604 6958 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6959 kvm_for_each_vcpu(i, vcpu, kvm) {
df24014a 6960 if (vcpu->cpu != cpu)
c8076604 6961 continue;
c285545f 6962 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0d9ce162 6963 if (vcpu->cpu != raw_smp_processor_id())
8cfdc000 6964 send_ipi = 1;
c8076604
GH		 6965 }
6966 }
0d9ce162 6967 mutex_unlock(&kvm_lock);
c8076604
GH		 6968
6969 if (freq->old < freq->new && send_ipi) {
6970 /*
6971 * We upscale the frequency. Must make the guest
6972 * doesn't see old kvmclock values while running with
6973 * the new frequency, otherwise we risk the guest sees
6974 * time go backwards.
6975 *
6976 * In case we update the frequency for another cpu
6977 * (which might be in guest context) send an interrupt
6978 * to kick the cpu out of guest context. Next time
6979 * guest context is entered kvmclock will be updated,
6980 * so the guest will not see stale values.
6981 */
df24014a 6982 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6983 }
df24014a
VK		 6984}
6985
6986static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6987 void *data)
6988{
6989 struct cpufreq_freqs *freq = data;
6990 int cpu;
6991
6992 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6993 return 0;
6994 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6995 return 0;
6996
6997 for_each_cpu(cpu, freq->policy->cpus)
6998 __kvmclock_cpufreq_notifier(freq, cpu);
6999
c8076604
GH		 7000 return 0;
7001}
7002
7003static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 7004 .notifier_call = kvmclock_cpufreq_notifier
7005};
7006
251a5fd6 7007static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 7008{
251a5fd6
SAS		 7009 tsc_khz_changed(NULL);
7010 return 0;
8cfdc000
ZA		 7011}
7012
b820cc0c
ZA		 7013static void kvm_timer_init(void)
7014{
c285545f 7015 max_tsc_khz = tsc_khz;
460dd42e 7016
b820cc0c 7017 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 7018#ifdef CONFIG_CPU_FREQ
7019 struct cpufreq_policy policy;
758f588d
BP		 7020 int cpu;
7021
c285545f 7022 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 7023 cpu = get_cpu();
7024 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 7025 if (policy.cpuinfo.max_freq)
7026 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 7027 put_cpu();
c285545f 7028#endif
b820cc0c
ZA		 7029 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7030 CPUFREQ_TRANSITION_NOTIFIER);
7031 }
460dd42e 7032
73c1b41e 7033 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 7034 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 7035}
7036
dd60d217
AK		 7037DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7038EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 7039
f5132b01 7040int kvm_is_in_guest(void)
ff9d07a0 7041{
086c9855 7042 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 7043}
7044
7045static int kvm_is_user_mode(void)
7046{
7047 int user_mode = 3;
dcf46b94 7048
086c9855
AS		 7049 if (__this_cpu_read(current_vcpu))
7050 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 7051
ff9d07a0
ZY		 7052 return user_mode != 0;
7053}
7054
7055static unsigned long kvm_get_guest_ip(void)
7056{
7057 unsigned long ip = 0;
dcf46b94 7058
086c9855
AS		 7059 if (__this_cpu_read(current_vcpu))
7060 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 7061
ff9d07a0
ZY		 7062 return ip;
7063}
7064
8479e04e
LK		 7065static void kvm_handle_intel_pt_intr(void)
7066{
7067 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7068
7069 kvm_make_request(KVM_REQ_PMI, vcpu);
7070 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7071 (unsigned long *)&vcpu->arch.pmu.global_status);
7072}
7073
ff9d07a0
ZY		 7074static struct perf_guest_info_callbacks kvm_guest_cbs = {
7075 .is_in_guest = kvm_is_in_guest,
7076 .is_user_mode = kvm_is_user_mode,
7077 .get_guest_ip = kvm_get_guest_ip,
8479e04e 7078 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
ff9d07a0
ZY		 7079};
7080
16e8d74d
MT		 7081#ifdef CONFIG_X86_64
7082static void pvclock_gtod_update_fn(struct work_struct *work)
7083{
d828199e
MT		 7084 struct kvm *kvm;
7085
7086 struct kvm_vcpu *vcpu;
7087 int i;
7088
0d9ce162 7089 mutex_lock(&kvm_lock);
d828199e
MT		 7090 list_for_each_entry(kvm, &vm_list, vm_list)
7091 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 7092 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 7093 atomic_set(&kvm_guest_has_master_clock, 0);
0d9ce162 7094 mutex_unlock(&kvm_lock);
16e8d74d
MT		 7095}
7096
7097static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7098
7099/*
7100 * Notification about pvclock gtod data update.
7101 */
7102static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7103 void *priv)
7104{
7105 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7106 struct timekeeper *tk = priv;
7107
7108 update_pvclock_gtod(tk);
7109
7110 /* disable master clock if host does not trust, or does not
b0c39dc6 7111 * use, TSC based clocksource.
16e8d74d 7112 */
b0c39dc6 7113 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 7114 atomic_read(&kvm_guest_has_master_clock) != 0)
7115 queue_work(system_long_wq, &pvclock_gtod_work);
7116
7117 return 0;
7118}
7119
7120static struct notifier_block pvclock_gtod_notifier = {
7121 .notifier_call = pvclock_gtod_notify,
7122};
7123#endif
7124
f8c16bba 7125int kvm_arch_init(void *opaque)
043405e1 7126{
b820cc0c 7127 int r;
6b61edf7 7128 struct kvm_x86_ops *ops = opaque;
f8c16bba 7129
f8c16bba
ZX		 7130 if (kvm_x86_ops) {
7131 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 7132 r = -EEXIST;
7133 goto out;
f8c16bba
ZX		 7134 }
7135
7136 if (!ops->cpu_has_kvm_support()) {
7137 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 7138 r = -EOPNOTSUPP;
7139 goto out;
f8c16bba
ZX		 7140 }
7141 if (ops->disabled_by_bios()) {
7142 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 7143 r = -EOPNOTSUPP;
7144 goto out;
f8c16bba
ZX		 7145 }
7146
b666a4b6
MO		 7147 /*
7148 * KVM explicitly assumes that the guest has an FPU and
7149 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7150 * vCPU's FPU state as a fxregs_state struct.
7151 */
7152 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7153 printk(KERN_ERR "kvm: inadequate fpu\n");
7154 r = -EOPNOTSUPP;
7155 goto out;
7156 }
7157
013f6a5d 7158 r = -ENOMEM;
ed8e4812 7159 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 7160 __alignof__(struct fpu), SLAB_ACCOUNT,
7161 NULL);
7162 if (!x86_fpu_cache) {
7163 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7164 goto out;
7165 }
7166
013f6a5d
MT		 7167 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7168 if (!shared_msrs) {
7169 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 7170 goto out_free_x86_fpu_cache;
013f6a5d
MT		 7171 }
7172
97db56ce
AK		 7173 r = kvm_mmu_module_init();
7174 if (r)
013f6a5d 7175 goto out_free_percpu;
97db56ce 7176
f8c16bba 7177 kvm_x86_ops = ops;
920c8377 7178
7b52345e 7179 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 7180 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 7181 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 7182 kvm_timer_init();
c8076604 7183
ff9d07a0
ZY		 7184 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7185
d366bf7e 7186 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 7187 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7188
c5cc421b 7189 kvm_lapic_init();
0c5f81da
WL		 7190 if (pi_inject_timer == -1)
7191 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
16e8d74d
MT		 7192#ifdef CONFIG_X86_64
7193 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 7194
5fa4ec9c 7195 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 7196 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 7197#endif
7198
f8c16bba 7199 return 0;
56c6d28a 7200
013f6a5d
MT		 7201out_free_percpu:
7202 free_percpu(shared_msrs);
b666a4b6
MO		 7203out_free_x86_fpu_cache:
7204 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7205out:
56c6d28a 7206 return r;
043405e1 7207}
8776e519 7208
f8c16bba
ZX		 7209void kvm_arch_exit(void)
7210{
0092e434 7211#ifdef CONFIG_X86_64
5fa4ec9c 7212 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 7213 clear_hv_tscchange_cb();
7214#endif
cef84c30 7215 kvm_lapic_exit();
ff9d07a0
ZY		 7216 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7217
888d256e
JK		 7218 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7219 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7220 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 7221 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 7222#ifdef CONFIG_X86_64
7223 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7224#endif
f8c16bba 7225 kvm_x86_ops = NULL;
56c6d28a 7226 kvm_mmu_module_exit();
013f6a5d 7227 free_percpu(shared_msrs);
b666a4b6 7228 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7229}
f8c16bba 7230
5cb56059 7231int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 7232{
7233 ++vcpu->stat.halt_exits;
35754c98 7234 if (lapic_in_kernel(vcpu)) {
a4535290 7235 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 7236 return 1;
7237 } else {
7238 vcpu->run->exit_reason = KVM_EXIT_HLT;
7239 return 0;
7240 }
7241}
5cb56059
JS		 7242EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7243
7244int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7245{
6affcbed
KH		 7246 int ret = kvm_skip_emulated_instruction(vcpu);
7247 /*
7248 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7249 * KVM_EXIT_DEBUG here.
7250 */
7251 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 7252}
8776e519
HB		 7253EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7254
8ef81a9a 7255#ifdef CONFIG_X86_64
55dd00a7
MT		 7256static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7257 unsigned long clock_type)
7258{
7259 struct kvm_clock_pairing clock_pairing;
899a31f5 7260 struct timespec64 ts;
80fbd89c 7261 u64 cycle;
55dd00a7
MT		 7262 int ret;
7263
7264 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7265 return -KVM_EOPNOTSUPP;
7266
7267 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7268 return -KVM_EOPNOTSUPP;
7269
7270 clock_pairing.sec = ts.tv_sec;
7271 clock_pairing.nsec = ts.tv_nsec;
7272 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7273 clock_pairing.flags = 0;
bcbfbd8e 7274 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 7275
7276 ret = 0;
7277 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7278 sizeof(struct kvm_clock_pairing)))
7279 ret = -KVM_EFAULT;
7280
7281 return ret;
7282}
8ef81a9a 7283#endif
55dd00a7 7284
6aef266c
SV		 7285/*
7286 * kvm_pv_kick_cpu_op: Kick a vcpu.
7287 *
7288 * @apicid - apicid of vcpu to be kicked.
7289 */
7290static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7291{
24d2166b 7292 struct kvm_lapic_irq lapic_irq;
6aef266c 7293
24d2166b
R		 7294 lapic_irq.shorthand = 0;
7295 lapic_irq.dest_mode = 0;
ebd28fcb 7296 lapic_irq.level = 0;
24d2166b 7297 lapic_irq.dest_id = apicid;
93bbf0b8 7298 lapic_irq.msi_redir_hint = false;
6aef266c 7299
24d2166b 7300 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7301 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7302}
7303
d62caabb
AS		 7304void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7305{
f7589cca
PB		 7306 if (!lapic_in_kernel(vcpu)) {
7307 WARN_ON_ONCE(vcpu->arch.apicv_active);
7308 return;
7309 }
7310 if (!vcpu->arch.apicv_active)
7311 return;
7312
d62caabb
AS		 7313 vcpu->arch.apicv_active = false;
7314 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7315}
7316
71506297
WL		 7317static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7318{
7319 struct kvm_vcpu *target = NULL;
7320 struct kvm_apic_map *map;
7321
7322 rcu_read_lock();
7323 map = rcu_dereference(kvm->arch.apic_map);
7324
7325 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7326 target = map->phys_map[dest_id]->vcpu;
7327
7328 rcu_read_unlock();
7329
266e85a5 7330 if (target && READ_ONCE(target->ready))
71506297
WL		 7331 kvm_vcpu_yield_to(target);
7332}
7333
8776e519
HB		 7334int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7335{
7336 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7337 int op_64_bit;
8776e519 7338
696ca779
RK		 7339 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7340 return kvm_hv_hypercall(vcpu);
55cd8e5a 7341
de3cd117
SC		 7342 nr = kvm_rax_read(vcpu);
7343 a0 = kvm_rbx_read(vcpu);
7344 a1 = kvm_rcx_read(vcpu);
7345 a2 = kvm_rdx_read(vcpu);
7346 a3 = kvm_rsi_read(vcpu);
8776e519 7347
229456fc 7348 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7349
a449c7aa
NA		 7350 op_64_bit = is_64_bit_mode(vcpu);
7351 if (!op_64_bit) {
8776e519
HB		 7352 nr &= 0xFFFFFFFF;
7353 a0 &= 0xFFFFFFFF;
7354 a1 &= 0xFFFFFFFF;
7355 a2 &= 0xFFFFFFFF;
7356 a3 &= 0xFFFFFFFF;
7357 }
7358
07708c4a
JK		 7359 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7360 ret = -KVM_EPERM;
696ca779 7361 goto out;
07708c4a
JK		 7362 }
7363
8776e519 7364 switch (nr) {
b93463aa
AK		 7365 case KVM_HC_VAPIC_POLL_IRQ:
7366 ret = 0;
7367 break;
6aef266c
SV		 7368 case KVM_HC_KICK_CPU:
7369 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
266e85a5 7370 kvm_sched_yield(vcpu->kvm, a1);
6aef266c
SV		 7371 ret = 0;
7372 break;
8ef81a9a 7373#ifdef CONFIG_X86_64
55dd00a7
MT		 7374 case KVM_HC_CLOCK_PAIRING:
7375 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7376 break;
1ed199a4 7377#endif
4180bf1b
WL		 7378 case KVM_HC_SEND_IPI:
7379 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7380 break;
71506297
WL		 7381 case KVM_HC_SCHED_YIELD:
7382 kvm_sched_yield(vcpu->kvm, a0);
7383 ret = 0;
7384 break;
8776e519
HB		 7385 default:
7386 ret = -KVM_ENOSYS;
7387 break;
7388 }
696ca779 7389out:
a449c7aa
NA		 7390 if (!op_64_bit)
7391 ret = (u32)ret;
de3cd117 7392 kvm_rax_write(vcpu, ret);
6356ee0c 7393
f11c3a8d 7394 ++vcpu->stat.hypercalls;
6356ee0c 7395 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7396}
7397EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7398
b6785def 7399static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7400{
d6aa1000 7401 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7402 char instruction[3];
5fdbf976 7403 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7404
8776e519 7405 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7406
ce2e852e
DV		 7407 return emulator_write_emulated(ctxt, rip, instruction, 3,
7408 &ctxt->exception);
8776e519
HB		 7409}
7410
851ba692 7411static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7412{
782d422b
MG		 7413 return vcpu->run->request_interrupt_window &&
7414 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7415}
7416
851ba692 7417static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7418{
851ba692
AK		 7419 struct kvm_run *kvm_run = vcpu->run;
7420
91586a3b 7421 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7422 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7423 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7424 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7425 kvm_run->ready_for_interrupt_injection =
7426 pic_in_kernel(vcpu->kvm) ||
782d422b 7427 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7428}
7429
95ba8273
GN		 7430static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7431{
7432 int max_irr, tpr;
7433
7434 if (!kvm_x86_ops->update_cr8_intercept)
7435 return;
7436
bce87cce 7437 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7438 return;
7439
d62caabb
AS		 7440 if (vcpu->arch.apicv_active)
7441 return;
7442
8db3baa2
GN		 7443 if (!vcpu->arch.apic->vapic_addr)
7444 max_irr = kvm_lapic_find_highest_irr(vcpu);
7445 else
7446 max_irr = -1;
95ba8273
GN		 7447
7448 if (max_irr != -1)
7449 max_irr >>= 4;
7450
7451 tpr = kvm_lapic_get_cr8(vcpu);
7452
7453 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7454}
7455
b6b8a145 7456static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7457{
b6b8a145
JK		 7458 int r;
7459
95ba8273 7460 /* try to reinject previous events if any */
664f8e26 7461
1a680e35
LA		 7462 if (vcpu->arch.exception.injected)
7463 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7464 /*
a042c26f
LA		 7465 * Do not inject an NMI or interrupt if there is a pending
7466 * exception. Exceptions and interrupts are recognized at
7467 * instruction boundaries, i.e. the start of an instruction.
7468 * Trap-like exceptions, e.g. #DB, have higher priority than
7469 * NMIs and interrupts, i.e. traps are recognized before an
7470 * NMI/interrupt that's pending on the same instruction.
7471 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7472 * priority, but are only generated (pended) during instruction
7473 * execution, i.e. a pending fault-like exception means the
7474 * fault occurred on the *previous* instruction and must be
7475 * serviced prior to recognizing any new events in order to
7476 * fully complete the previous instruction.
664f8e26 7477 */
1a680e35
LA		 7478 else if (!vcpu->arch.exception.pending) {
7479 if (vcpu->arch.nmi_injected)
664f8e26 7480 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7481 else if (vcpu->arch.interrupt.injected)
664f8e26 7482 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7483 }
7484
1a680e35
LA		 7485 /*
7486 * Call check_nested_events() even if we reinjected a previous event
7487 * in order for caller to determine if it should require immediate-exit
7488 * from L2 to L1 due to pending L1 events which require exit
7489 * from L2 to L1.
7490 */
664f8e26
WL		 7491 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7492 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7493 if (r != 0)
7494 return r;
7495 }
7496
7497 /* try to inject new event if pending */
b59bb7bd 7498 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7499 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7500 vcpu->arch.exception.has_error_code,
7501 vcpu->arch.exception.error_code);
d6e8c854 7502
1a680e35 7503 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7504 vcpu->arch.exception.pending = false;
7505 vcpu->arch.exception.injected = true;
7506
d6e8c854
NA		 7507 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7508 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7509 X86_EFLAGS_RF);
7510
f10c729f
JM		 7511 if (vcpu->arch.exception.nr == DB_VECTOR) {
7512 /*
7513 * This code assumes that nSVM doesn't use
7514 * check_nested_events(). If it does, the
7515 * DR6/DR7 changes should happen before L1
7516 * gets a #VMEXIT for an intercepted #DB in
7517 * L2. (Under VMX, on the other hand, the
7518 * DR6/DR7 changes should not happen in the
7519 * event of a VM-exit to L1 for an intercepted
7520 * #DB in L2.)
7521 */
7522 kvm_deliver_exception_payload(vcpu);
7523 if (vcpu->arch.dr7 & DR7_GD) {
7524 vcpu->arch.dr7 &= ~DR7_GD;
7525 kvm_update_dr7(vcpu);
7526 }
6bdf0662
NA		 7527 }
7528
cfcd20e5 7529 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7530 }
7531
7532 /* Don't consider new event if we re-injected an event */
7533 if (kvm_event_needs_reinjection(vcpu))
7534 return 0;
7535
7536 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7537 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7538 vcpu->arch.smi_pending = false;
52797bf9 7539 ++vcpu->arch.smi_count;
ee2cd4b7 7540 enter_smm(vcpu);
c43203ca 7541 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7542 --vcpu->arch.nmi_pending;
7543 vcpu->arch.nmi_injected = true;
7544 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7545 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7546 /*
7547 * Because interrupts can be injected asynchronously, we are
7548 * calling check_nested_events again here to avoid a race condition.
7549 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7550 * proposal and current concerns. Perhaps we should be setting
7551 * KVM_REQ_EVENT only on certain events and not unconditionally?
7552 */
7553 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7554 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7555 if (r != 0)
7556 return r;
7557 }
95ba8273 7558 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7559 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7560 false);
7561 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7562 }
7563 }
ee2cd4b7 7564
b6b8a145 7565 return 0;
95ba8273
GN		 7566}
7567
7460fb4a
AK		 7568static void process_nmi(struct kvm_vcpu *vcpu)
7569{
7570 unsigned limit = 2;
7571
7572 /*
7573 * x86 is limited to one NMI running, and one NMI pending after it.
7574 * If an NMI is already in progress, limit further NMIs to just one.
7575 * Otherwise, allow two (and we'll inject the first one immediately).
7576 */
7577 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7578 limit = 1;
7579
7580 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7581 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7582 kvm_make_request(KVM_REQ_EVENT, vcpu);
7583}
7584
ee2cd4b7 7585static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7586{
7587 u32 flags = 0;
7588 flags |= seg->g << 23;
7589 flags |= seg->db << 22;
7590 flags |= seg->l << 21;
7591 flags |= seg->avl << 20;
7592 flags |= seg->present << 15;
7593 flags |= seg->dpl << 13;
7594 flags |= seg->s << 12;
7595 flags |= seg->type << 8;
7596 return flags;
7597}
7598
ee2cd4b7 7599static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7600{
7601 struct kvm_segment seg;
7602 int offset;
7603
7604 kvm_get_segment(vcpu, &seg, n);
7605 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7606
7607 if (n < 3)
7608 offset = 0x7f84 + n * 12;
7609 else
7610 offset = 0x7f2c + (n - 3) * 12;
7611
7612 put_smstate(u32, buf, offset + 8, seg.base);
7613 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7614 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7615}
7616
efbb288a 7617#ifdef CONFIG_X86_64
ee2cd4b7 7618static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7619{
7620 struct kvm_segment seg;
7621 int offset;
7622 u16 flags;
7623
7624 kvm_get_segment(vcpu, &seg, n);
7625 offset = 0x7e00 + n * 16;
7626
ee2cd4b7 7627 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7628 put_smstate(u16, buf, offset, seg.selector);
7629 put_smstate(u16, buf, offset + 2, flags);
7630 put_smstate(u32, buf, offset + 4, seg.limit);
7631 put_smstate(u64, buf, offset + 8, seg.base);
7632}
efbb288a 7633#endif
660a5d51 7634
ee2cd4b7 7635static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7636{
7637 struct desc_ptr dt;
7638 struct kvm_segment seg;
7639 unsigned long val;
7640 int i;
7641
7642 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7643 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7644 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7645 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7646
7647 for (i = 0; i < 8; i++)
7648 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7649
7650 kvm_get_dr(vcpu, 6, &val);
7651 put_smstate(u32, buf, 0x7fcc, (u32)val);
7652 kvm_get_dr(vcpu, 7, &val);
7653 put_smstate(u32, buf, 0x7fc8, (u32)val);
7654
7655 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7656 put_smstate(u32, buf, 0x7fc4, seg.selector);
7657 put_smstate(u32, buf, 0x7f64, seg.base);
7658 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7659 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7660
7661 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7662 put_smstate(u32, buf, 0x7fc0, seg.selector);
7663 put_smstate(u32, buf, 0x7f80, seg.base);
7664 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7665 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7666
7667 kvm_x86_ops->get_gdt(vcpu, &dt);
7668 put_smstate(u32, buf, 0x7f74, dt.address);
7669 put_smstate(u32, buf, 0x7f70, dt.size);
7670
7671 kvm_x86_ops->get_idt(vcpu, &dt);
7672 put_smstate(u32, buf, 0x7f58, dt.address);
7673 put_smstate(u32, buf, 0x7f54, dt.size);
7674
7675 for (i = 0; i < 6; i++)
ee2cd4b7 7676 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7677
7678 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7679
7680 /* revision id */
7681 put_smstate(u32, buf, 0x7efc, 0x00020000);
7682 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7683}
7684
b68f3cc7 7685#ifdef CONFIG_X86_64
ee2cd4b7 7686static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51 7687{
660a5d51
PB		 7688 struct desc_ptr dt;
7689 struct kvm_segment seg;
7690 unsigned long val;
7691 int i;
7692
7693 for (i = 0; i < 16; i++)
7694 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7695
7696 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7697 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7698
7699 kvm_get_dr(vcpu, 6, &val);
7700 put_smstate(u64, buf, 0x7f68, val);
7701 kvm_get_dr(vcpu, 7, &val);
7702 put_smstate(u64, buf, 0x7f60, val);
7703
7704 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7705 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7706 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7707
7708 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7709
7710 /* revision id */
7711 put_smstate(u32, buf, 0x7efc, 0x00020064);
7712
7713 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7714
7715 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7716 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7717 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7718 put_smstate(u32, buf, 0x7e94, seg.limit);
7719 put_smstate(u64, buf, 0x7e98, seg.base);
7720
7721 kvm_x86_ops->get_idt(vcpu, &dt);
7722 put_smstate(u32, buf, 0x7e84, dt.size);
7723 put_smstate(u64, buf, 0x7e88, dt.address);
7724
7725 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7726 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7727 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7728 put_smstate(u32, buf, 0x7e74, seg.limit);
7729 put_smstate(u64, buf, 0x7e78, seg.base);
7730
7731 kvm_x86_ops->get_gdt(vcpu, &dt);
7732 put_smstate(u32, buf, 0x7e64, dt.size);
7733 put_smstate(u64, buf, 0x7e68, dt.address);
7734
7735 for (i = 0; i < 6; i++)
ee2cd4b7 7736 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51 7737}
b68f3cc7 7738#endif
660a5d51 7739
ee2cd4b7 7740static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7741{
660a5d51 7742 struct kvm_segment cs, ds;
18c3626e 7743 struct desc_ptr dt;
660a5d51
PB		 7744 char buf[512];
7745 u32 cr0;
7746
660a5d51 7747 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7748 memset(buf, 0, 512);
b68f3cc7 7749#ifdef CONFIG_X86_64
d6321d49 7750 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7751 enter_smm_save_state_64(vcpu, buf);
660a5d51 7752 else
b68f3cc7 7753#endif
ee2cd4b7 7754 enter_smm_save_state_32(vcpu, buf);
660a5d51 7755
0234bf88
LP		 7756 /*
7757 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7758 * vCPU state (e.g. leave guest mode) after we've saved the state into
7759 * the SMM state-save area.
7760 */
7761 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7762
7763 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7764 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7765
7766 if (kvm_x86_ops->get_nmi_mask(vcpu))
7767 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7768 else
7769 kvm_x86_ops->set_nmi_mask(vcpu, true);
7770
7771 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7772 kvm_rip_write(vcpu, 0x8000);
7773
7774 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7775 kvm_x86_ops->set_cr0(vcpu, cr0);
7776 vcpu->arch.cr0 = cr0;
7777
7778 kvm_x86_ops->set_cr4(vcpu, 0);
7779
18c3626e
PB		 7780 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7781 dt.address = dt.size = 0;
7782 kvm_x86_ops->set_idt(vcpu, &dt);
7783
660a5d51
PB		 7784 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7785
7786 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7787 cs.base = vcpu->arch.smbase;
7788
7789 ds.selector = 0;
7790 ds.base = 0;
7791
7792 cs.limit = ds.limit = 0xffffffff;
7793 cs.type = ds.type = 0x3;
7794 cs.dpl = ds.dpl = 0;
7795 cs.db = ds.db = 0;
7796 cs.s = ds.s = 1;
7797 cs.l = ds.l = 0;
7798 cs.g = ds.g = 1;
7799 cs.avl = ds.avl = 0;
7800 cs.present = ds.present = 1;
7801 cs.unusable = ds.unusable = 0;
7802 cs.padding = ds.padding = 0;
7803
7804 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7805 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7806 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7807 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7808 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7809 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7810
b68f3cc7 7811#ifdef CONFIG_X86_64
d6321d49 7812 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51 7813 kvm_x86_ops->set_efer(vcpu, 0);
b68f3cc7 7814#endif
660a5d51
PB		 7815
7816 kvm_update_cpuid(vcpu);
7817 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7818}
7819
ee2cd4b7 7820static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7821{
7822 vcpu->arch.smi_pending = true;
7823 kvm_make_request(KVM_REQ_EVENT, vcpu);
7824}
7825
2860c4b1
PB		 7826void kvm_make_scan_ioapic_request(struct kvm *kvm)
7827{
7828 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7829}
7830
3d81bc7e 7831static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7832{
dcbd3e49 7833 if (!kvm_apic_present(vcpu))
3d81bc7e 7834 return;
c7c9c56c 7835
6308630b 7836 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7837
b053b2ae 7838 if (irqchip_split(vcpu->kvm))
6308630b 7839 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7840 else {
fa59cc00 7841 if (vcpu->arch.apicv_active)
d62caabb 7842 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 7843 if (ioapic_in_kernel(vcpu->kvm))
7844 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7845 }
e40ff1d6
LA		 7846
7847 if (is_guest_mode(vcpu))
7848 vcpu->arch.load_eoi_exitmap_pending = true;
7849 else
7850 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7851}
7852
7853static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7854{
7855 u64 eoi_exit_bitmap[4];
7856
7857 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7858 return;
7859
5c919412
AS		 7860 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7861 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7862 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7863}
7864
93065ac7
MH		 7865int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7866 unsigned long start, unsigned long end,
7867 bool blockable)
b1394e74
RK		 7868{
7869 unsigned long apic_address;
7870
7871 /*
7872 * The physical address of apic access page is stored in the VMCS.
7873 * Update it when it becomes invalid.
7874 */
7875 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7876 if (start <= apic_address && apic_address < end)
7877 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7878
7879 return 0;
b1394e74
RK		 7880}
7881
4256f43f
TC		 7882void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7883{
c24ae0dc
TC		 7884 struct page *page = NULL;
7885
35754c98 7886 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7887 return;
7888
4256f43f
TC		 7889 if (!kvm_x86_ops->set_apic_access_page_addr)
7890 return;
7891
c24ae0dc 7892 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7893 if (is_error_page(page))
7894 return;
c24ae0dc
TC		 7895 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7896
7897 /*
7898 * Do not pin apic access page in memory, the MMU notifier
7899 * will call us again if it is migrated or swapped out.
7900 */
7901 put_page(page);
4256f43f
TC		 7902}
7903EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7904
d264ee0c
SC		 7905void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7906{
7907 smp_send_reschedule(vcpu->cpu);
7908}
7909EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7910
9357d939 7911/*
362c698f 7912 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7913 * exiting to the userspace. Otherwise, the value will be returned to the
7914 * userspace.
7915 */
851ba692 7916static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7917{
7918 int r;
62a193ed
MG		 7919 bool req_int_win =
7920 dm_request_for_irq_injection(vcpu) &&
7921 kvm_cpu_accept_dm_intr(vcpu);
7922
730dca42 7923 bool req_immediate_exit = false;
b6c7a5dc 7924
2fa6e1e1 7925 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7926 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7927 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7928 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7929 kvm_mmu_unload(vcpu);
a8eeb04a 7930 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7931 __kvm_migrate_timers(vcpu);
d828199e
MT		 7932 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7933 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7934 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7935 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7936 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7937 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7938 if (unlikely(r))
7939 goto out;
7940 }
a8eeb04a 7941 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7942 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7943 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7944 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7945 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7946 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7947 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7948 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7949 r = 0;
7950 goto out;
7951 }
a8eeb04a 7952 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7953 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7954 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7955 r = 0;
7956 goto out;
7957 }
af585b92
GN		 7958 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7959 /* Page is swapped out. Do synthetic halt */
7960 vcpu->arch.apf.halted = true;
7961 r = 1;
7962 goto out;
7963 }
c9aaa895
GC		 7964 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7965 record_steal_time(vcpu);
64d60670
PB		 7966 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7967 process_smi(vcpu);
7460fb4a
AK		 7968 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7969 process_nmi(vcpu);
f5132b01 7970 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7971 kvm_pmu_handle_event(vcpu);
f5132b01 7972 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7973 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7974 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7975 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7976 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7977 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7978 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7979 vcpu->run->eoi.vector =
7980 vcpu->arch.pending_ioapic_eoi;
7981 r = 0;
7982 goto out;
7983 }
7984 }
3d81bc7e
YZ		 7985 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7986 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7987 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7988 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7989 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7990 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7991 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7992 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7993 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7994 r = 0;
7995 goto out;
7996 }
e516cebb
AS		 7997 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7998 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7999 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8000 r = 0;
8001 goto out;
8002 }
db397571
AS		 8003 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8004 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8005 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8006 r = 0;
8007 goto out;
8008 }
f3b138c5
AS		 8009
8010 /*
8011 * KVM_REQ_HV_STIMER has to be processed after
8012 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8013 * depend on the guest clock being up-to-date
8014 */
1f4b34f8
AS		 8015 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8016 kvm_hv_process_stimers(vcpu);
2f52d58c 8017 }
b93463aa 8018
b463a6f7 8019 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 8020 ++vcpu->stat.req_event;
66450a21
JK		 8021 kvm_apic_accept_events(vcpu);
8022 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8023 r = 1;
8024 goto out;
8025 }
8026
b6b8a145
JK		 8027 if (inject_pending_event(vcpu, req_int_win) != 0)
8028 req_immediate_exit = true;
321c5658 8029 else {
cc3d967f 8030 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 8031 *
cc3d967f
LP		 8032 * SMIs have three cases:
8033 * 1) They can be nested, and then there is nothing to
8034 * do here because RSM will cause a vmexit anyway.
8035 * 2) There is an ISA-specific reason why SMI cannot be
8036 * injected, and the moment when this changes can be
8037 * intercepted.
8038 * 3) Or the SMI can be pending because
8039 * inject_pending_event has completed the injection
8040 * of an IRQ or NMI from the previous vmexit, and
8041 * then we request an immediate exit to inject the
8042 * SMI.
c43203ca
PB		 8043 */
8044 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 8045 if (!kvm_x86_ops->enable_smi_window(vcpu))
8046 req_immediate_exit = true;
321c5658
YS		 8047 if (vcpu->arch.nmi_pending)
8048 kvm_x86_ops->enable_nmi_window(vcpu);
8049 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8050 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 8051 WARN_ON(vcpu->arch.exception.pending);
321c5658 8052 }
b463a6f7
AK		 8053
8054 if (kvm_lapic_enabled(vcpu)) {
8055 update_cr8_intercept(vcpu);
8056 kvm_lapic_sync_to_vapic(vcpu);
8057 }
8058 }
8059
d8368af8
AK		 8060 r = kvm_mmu_reload(vcpu);
8061 if (unlikely(r)) {
d905c069 8062 goto cancel_injection;
d8368af8
AK		 8063 }
8064
b6c7a5dc
HB		 8065 preempt_disable();
8066
8067 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 8068
8069 /*
8070 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8071 * IPI are then delayed after guest entry, which ensures that they
8072 * result in virtual interrupt delivery.
8073 */
8074 local_irq_disable();
6b7e2d09
XG		 8075 vcpu->mode = IN_GUEST_MODE;
8076
01b71917
MT		 8077 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8078
0f127d12 8079 /*
b95234c8 8080 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 8081 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8 8082 *
81b01667 8083 * 2) For APICv, we should set ->mode before checking PID.ON. This
b95234c8
PB		 8084 * pairs with the memory barrier implicit in pi_test_and_set_on
8085 * (see vmx_deliver_posted_interrupt).
8086 *
8087 * 3) This also orders the write to mode from any reads to the page
8088 * tables done while the VCPU is running. Please see the comment
8089 * in kvm_flush_remote_tlbs.
6b7e2d09 8090 */
01b71917 8091 smp_mb__after_srcu_read_unlock();
b6c7a5dc 8092
b95234c8
PB		 8093 /*
8094 * This handles the case where a posted interrupt was
8095 * notified with kvm_vcpu_kick.
8096 */
fa59cc00
LA		 8097 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8098 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 8099
2fa6e1e1 8100 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 8101 || need_resched() || signal_pending(current)) {
6b7e2d09 8102 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8103 smp_wmb();
6c142801
AK		 8104 local_irq_enable();
8105 preempt_enable();
01b71917 8106 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 8107 r = 1;
d905c069 8108 goto cancel_injection;
6c142801
AK		 8109 }
8110
c43203ca
PB		 8111 if (req_immediate_exit) {
8112 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 8113 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 8114 }
d6185f20 8115
8b89fe1f 8116 trace_kvm_entry(vcpu->vcpu_id);
6edaa530 8117 guest_enter_irqoff();
b6c7a5dc 8118
e7517324
WL		 8119 /* The preempt notifier should have taken care of the FPU already. */
8120 WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD));
5f409e20 8121
42dbaa5a 8122 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 8123 set_debugreg(0, 7);
8124 set_debugreg(vcpu->arch.eff_db[0], 0);
8125 set_debugreg(vcpu->arch.eff_db[1], 1);
8126 set_debugreg(vcpu->arch.eff_db[2], 2);
8127 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 8128 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 8129 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 8130 }
b6c7a5dc 8131
851ba692 8132 kvm_x86_ops->run(vcpu);
b6c7a5dc 8133
c77fb5fe
PB		 8134 /*
8135 * Do this here before restoring debug registers on the host. And
8136 * since we do this before handling the vmexit, a DR access vmexit
8137 * can (a) read the correct value of the debug registers, (b) set
8138 * KVM_DEBUGREG_WONT_EXIT again.
8139 */
8140 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 8141 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8142 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 8143 kvm_update_dr0123(vcpu);
8144 kvm_update_dr6(vcpu);
8145 kvm_update_dr7(vcpu);
8146 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 8147 }
8148
24f1e32c
FW		 8149 /*
8150 * If the guest has used debug registers, at least dr7
8151 * will be disabled while returning to the host.
8152 * If we don't have active breakpoints in the host, we don't
8153 * care about the messed up debug address registers. But if
8154 * we have some of them active, restore the old state.
8155 */
59d8eb53 8156 if (hw_breakpoint_active())
24f1e32c 8157 hw_breakpoint_restore();
42dbaa5a 8158
4ba76538 8159 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 8160
6b7e2d09 8161 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8162 smp_wmb();
a547c6db 8163
95b5a48c 8164 kvm_x86_ops->handle_exit_irqoff(vcpu);
b6c7a5dc 8165
d7a08882
SC		 8166 /*
8167 * Consume any pending interrupts, including the possible source of
8168 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8169 * An instruction is required after local_irq_enable() to fully unblock
8170 * interrupts on processors that implement an interrupt shadow, the
8171 * stat.exits increment will do nicely.
8172 */
8173 kvm_before_interrupt(vcpu);
8174 local_irq_enable();
b6c7a5dc 8175 ++vcpu->stat.exits;
d7a08882
SC		 8176 local_irq_disable();
8177 kvm_after_interrupt(vcpu);
b6c7a5dc 8178
f2485b3e 8179 guest_exit_irqoff();
ec0671d5
WL		 8180 if (lapic_in_kernel(vcpu)) {
8181 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8182 if (delta != S64_MIN) {
8183 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8184 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8185 }
8186 }
b6c7a5dc 8187
f2485b3e 8188 local_irq_enable();
b6c7a5dc
HB		 8189 preempt_enable();
8190
f656ce01 8191 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 8192
b6c7a5dc
HB		 8193 /*
8194 * Profile KVM exit RIPs:
8195 */
8196 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 8197 unsigned long rip = kvm_rip_read(vcpu);
8198 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 8199 }
8200
cc578287
ZA		 8201 if (unlikely(vcpu->arch.tsc_always_catchup))
8202 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 8203
5cfb1d5a
MT		 8204 if (vcpu->arch.apic_attention)
8205 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 8206
618232e2 8207 vcpu->arch.gpa_available = false;
851ba692 8208 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 8209 return r;
8210
8211cancel_injection:
8212 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 8213 if (unlikely(vcpu->arch.apic_attention))
8214 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 8215out:
8216 return r;
8217}
b6c7a5dc 8218
362c698f
PB		 8219static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8220{
bf9f6ac8
FW		 8221 if (!kvm_arch_vcpu_runnable(vcpu) &&
8222 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 8223 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8224 kvm_vcpu_block(vcpu);
8225 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 8226
8227 if (kvm_x86_ops->post_block)
8228 kvm_x86_ops->post_block(vcpu);
8229
9c8fd1ba
PB		 8230 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8231 return 1;
8232 }
362c698f
PB		 8233
8234 kvm_apic_accept_events(vcpu);
8235 switch(vcpu->arch.mp_state) {
8236 case KVM_MP_STATE_HALTED:
8237 vcpu->arch.pv.pv_unhalted = false;
8238 vcpu->arch.mp_state =
8239 KVM_MP_STATE_RUNNABLE;
b2869f28 8240 /* fall through */
362c698f
PB		 8241 case KVM_MP_STATE_RUNNABLE:
8242 vcpu->arch.apf.halted = false;
8243 break;
8244 case KVM_MP_STATE_INIT_RECEIVED:
8245 break;
8246 default:
8247 return -EINTR;
8248 break;
8249 }
8250 return 1;
8251}
09cec754 8252
5d9bc648
PB		 8253static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8254{
0ad3bed6
PB		 8255 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8256 kvm_x86_ops->check_nested_events(vcpu, false);
8257
5d9bc648
PB		 8258 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8259 !vcpu->arch.apf.halted);
8260}
8261
362c698f 8262static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 8263{
8264 int r;
f656ce01 8265 struct kvm *kvm = vcpu->kvm;
d7690175 8266
f656ce01 8267 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 8268 vcpu->arch.l1tf_flush_l1d = true;
d7690175 8269
362c698f 8270 for (;;) {
58f800d5 8271 if (kvm_vcpu_running(vcpu)) {
851ba692 8272 r = vcpu_enter_guest(vcpu);
bf9f6ac8 8273 } else {
362c698f 8274 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 8275 }
8276
09cec754
GN		 8277 if (r <= 0)
8278 break;
8279
72875d8a 8280 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 8281 if (kvm_cpu_has_pending_timer(vcpu))
8282 kvm_inject_pending_timer_irqs(vcpu);
8283
782d422b
MG		 8284 if (dm_request_for_irq_injection(vcpu) &&
8285 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 8286 r = 0;
8287 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 8288 ++vcpu->stat.request_irq_exits;
362c698f 8289 break;
09cec754 8290 }
af585b92
GN		 8291
8292 kvm_check_async_pf_completion(vcpu);
8293
09cec754
GN		 8294 if (signal_pending(current)) {
8295 r = -EINTR;
851ba692 8296 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 8297 ++vcpu->stat.signal_exits;
362c698f 8298 break;
09cec754
GN		 8299 }
8300 if (need_resched()) {
f656ce01 8301 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 8302 cond_resched();
f656ce01 8303 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 8304 }
b6c7a5dc
HB		 8305 }
8306
f656ce01 8307 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 8308
8309 return r;
8310}
8311
716d51ab
GN		 8312static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8313{
8314 int r;
8315 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 8316 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab
GN		 8317 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8318 if (r != EMULATE_DONE)
8319 return 0;
8320 return 1;
8321}
8322
8323static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8324{
8325 BUG_ON(!vcpu->arch.pio.count);
8326
8327 return complete_emulated_io(vcpu);
8328}
8329
f78146b0
AK		 8330/*
8331 * Implements the following, as a state machine:
8332 *
8333 * read:
8334 * for each fragment
87da7e66
XG		 8335 * for each mmio piece in the fragment
8336 * write gpa, len
8337 * exit
8338 * copy data
f78146b0
AK		 8339 * execute insn
8340 *
8341 * write:
8342 * for each fragment
87da7e66
XG		 8343 * for each mmio piece in the fragment
8344 * write gpa, len
8345 * copy data
8346 * exit
f78146b0 8347 */
716d51ab 8348static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8349{
8350 struct kvm_run *run = vcpu->run;
f78146b0 8351 struct kvm_mmio_fragment *frag;
87da7e66 8352 unsigned len;
5287f194 8353
716d51ab 8354 BUG_ON(!vcpu->mmio_needed);
5287f194 8355
716d51ab 8356 /* Complete previous fragment */
87da7e66
XG		 8357 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8358 len = min(8u, frag->len);
716d51ab 8359 if (!vcpu->mmio_is_write)
87da7e66
XG		 8360 memcpy(frag->data, run->mmio.data, len);
8361
8362 if (frag->len <= 8) {
8363 /* Switch to the next fragment. */
8364 frag++;
8365 vcpu->mmio_cur_fragment++;
8366 } else {
8367 /* Go forward to the next mmio piece. */
8368 frag->data += len;
8369 frag->gpa += len;
8370 frag->len -= len;
8371 }
8372
a08d3b3b 8373 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8374 vcpu->mmio_needed = 0;
0912c977
PB		 8375
8376 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8377 if (vcpu->mmio_is_write)
716d51ab
GN		 8378 return 1;
8379 vcpu->mmio_read_completed = 1;
8380 return complete_emulated_io(vcpu);
8381 }
87da7e66 8382
716d51ab
GN		 8383 run->exit_reason = KVM_EXIT_MMIO;
8384 run->mmio.phys_addr = frag->gpa;
8385 if (vcpu->mmio_is_write)
87da7e66
XG		 8386 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8387 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8388 run->mmio.is_write = vcpu->mmio_is_write;
8389 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8390 return 0;
5287f194
AK		 8391}
8392
822f312d
SAS		 8393/* Swap (qemu) user FPU context for the guest FPU context. */
8394static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8395{
5f409e20
RR		 8396 fpregs_lock();
8397
d9a710e5 8398 copy_fpregs_to_fpstate(vcpu->arch.user_fpu);
822f312d 8399 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8400 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d 8401 ~XFEATURE_MASK_PKRU);
5f409e20
RR		 8402
8403 fpregs_mark_activate();
8404 fpregs_unlock();
8405
822f312d
SAS		 8406 trace_kvm_fpu(1);
8407}
8408
8409/* When vcpu_run ends, restore user space FPU context. */
8410static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8411{
5f409e20
RR		 8412 fpregs_lock();
8413
b666a4b6 8414 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
d9a710e5 8415 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
5f409e20
RR		 8416
8417 fpregs_mark_activate();
8418 fpregs_unlock();
8419
822f312d
SAS		 8420 ++vcpu->stat.fpu_reload;
8421 trace_kvm_fpu(0);
8422}
8423
b6c7a5dc
HB		 8424int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8425{
8426 int r;
b6c7a5dc 8427
accb757d 8428 vcpu_load(vcpu);
20b7035c 8429 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8430 kvm_load_guest_fpu(vcpu);
8431
a4535290 8432 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8433 if (kvm_run->immediate_exit) {
8434 r = -EINTR;
8435 goto out;
8436 }
b6c7a5dc 8437 kvm_vcpu_block(vcpu);
66450a21 8438 kvm_apic_accept_events(vcpu);
72875d8a 8439 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8440 r = -EAGAIN;
a0595000
JS		 8441 if (signal_pending(current)) {
8442 r = -EINTR;
8443 vcpu->run->exit_reason = KVM_EXIT_INTR;
8444 ++vcpu->stat.signal_exits;
8445 }
ac9f6dc0 8446 goto out;
b6c7a5dc
HB		 8447 }
8448
01643c51
KH		 8449 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8450 r = -EINVAL;
8451 goto out;
8452 }
8453
8454 if (vcpu->run->kvm_dirty_regs) {
8455 r = sync_regs(vcpu);
8456 if (r != 0)
8457 goto out;
8458 }
8459
b6c7a5dc 8460 /* re-sync apic's tpr */
35754c98 8461 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8462 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8463 r = -EINVAL;
8464 goto out;
8465 }
8466 }
b6c7a5dc 8467
716d51ab
GN		 8468 if (unlikely(vcpu->arch.complete_userspace_io)) {
8469 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8470 vcpu->arch.complete_userspace_io = NULL;
8471 r = cui(vcpu);
8472 if (r <= 0)
5663d8f9 8473 goto out;
716d51ab
GN		 8474 } else
8475 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8476
460df4c1
PB		 8477 if (kvm_run->immediate_exit)
8478 r = -EINTR;
8479 else
8480 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8481
8482out:
5663d8f9 8483 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8484 if (vcpu->run->kvm_valid_regs)
8485 store_regs(vcpu);
f1d86e46 8486 post_kvm_run_save(vcpu);
20b7035c 8487 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8488
accb757d 8489 vcpu_put(vcpu);
b6c7a5dc
HB		 8490 return r;
8491}
8492
01643c51 8493static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8494{
7ae441ea
GN		 8495 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8496 /*
8497 * We are here if userspace calls get_regs() in the middle of
8498 * instruction emulation. Registers state needs to be copied
4a969980 8499 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8500 * that usually, but some bad designed PV devices (vmware
8501 * backdoor interface) need this to work
8502 */
dd856efa 8503 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8504 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8505 }
de3cd117
SC		 8506 regs->rax = kvm_rax_read(vcpu);
8507 regs->rbx = kvm_rbx_read(vcpu);
8508 regs->rcx = kvm_rcx_read(vcpu);
8509 regs->rdx = kvm_rdx_read(vcpu);
8510 regs->rsi = kvm_rsi_read(vcpu);
8511 regs->rdi = kvm_rdi_read(vcpu);
e9c16c78 8512 regs->rsp = kvm_rsp_read(vcpu);
de3cd117 8513 regs->rbp = kvm_rbp_read(vcpu);
b6c7a5dc 8514#ifdef CONFIG_X86_64
de3cd117
SC		 8515 regs->r8 = kvm_r8_read(vcpu);
8516 regs->r9 = kvm_r9_read(vcpu);
8517 regs->r10 = kvm_r10_read(vcpu);
8518 regs->r11 = kvm_r11_read(vcpu);
8519 regs->r12 = kvm_r12_read(vcpu);
8520 regs->r13 = kvm_r13_read(vcpu);
8521 regs->r14 = kvm_r14_read(vcpu);
8522 regs->r15 = kvm_r15_read(vcpu);
b6c7a5dc
HB		 8523#endif
8524
5fdbf976 8525 regs->rip = kvm_rip_read(vcpu);
91586a3b 8526 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8527}
b6c7a5dc 8528
01643c51
KH		 8529int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8530{
8531 vcpu_load(vcpu);
8532 __get_regs(vcpu, regs);
1fc9b76b 8533 vcpu_put(vcpu);
b6c7a5dc
HB		 8534 return 0;
8535}
8536
01643c51 8537static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8538{
7ae441ea
GN		 8539 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8540 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8541
de3cd117
SC		 8542 kvm_rax_write(vcpu, regs->rax);
8543 kvm_rbx_write(vcpu, regs->rbx);
8544 kvm_rcx_write(vcpu, regs->rcx);
8545 kvm_rdx_write(vcpu, regs->rdx);
8546 kvm_rsi_write(vcpu, regs->rsi);
8547 kvm_rdi_write(vcpu, regs->rdi);
e9c16c78 8548 kvm_rsp_write(vcpu, regs->rsp);
de3cd117 8549 kvm_rbp_write(vcpu, regs->rbp);
b6c7a5dc 8550#ifdef CONFIG_X86_64
de3cd117
SC		 8551 kvm_r8_write(vcpu, regs->r8);
8552 kvm_r9_write(vcpu, regs->r9);
8553 kvm_r10_write(vcpu, regs->r10);
8554 kvm_r11_write(vcpu, regs->r11);
8555 kvm_r12_write(vcpu, regs->r12);
8556 kvm_r13_write(vcpu, regs->r13);
8557 kvm_r14_write(vcpu, regs->r14);
8558 kvm_r15_write(vcpu, regs->r15);
b6c7a5dc
HB		 8559#endif
8560
5fdbf976 8561 kvm_rip_write(vcpu, regs->rip);
d73235d1 8562 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8563
b4f14abd
JK		 8564 vcpu->arch.exception.pending = false;
8565
3842d135 8566 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8567}
3842d135 8568
01643c51
KH		 8569int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8570{
8571 vcpu_load(vcpu);
8572 __set_regs(vcpu, regs);
875656fe 8573 vcpu_put(vcpu);
b6c7a5dc
HB		 8574 return 0;
8575}
8576
b6c7a5dc
HB		 8577void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8578{
8579 struct kvm_segment cs;
8580
3e6e0aab 8581 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8582 *db = cs.db;
8583 *l = cs.l;
8584}
8585EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8586
01643c51 8587static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8588{
89a27f4d 8589 struct desc_ptr dt;
b6c7a5dc 8590
3e6e0aab
GT		 8591 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8592 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8593 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8594 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8595 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8596 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8597
3e6e0aab
GT		 8598 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8599 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8600
8601 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8602 sregs->idt.limit = dt.size;
8603 sregs->idt.base = dt.address;
b6c7a5dc 8604 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8605 sregs->gdt.limit = dt.size;
8606 sregs->gdt.base = dt.address;
b6c7a5dc 8607
4d4ec087 8608 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8609 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8610 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8611 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8612 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8613 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8614 sregs->apic_base = kvm_get_apic_base(vcpu);
8615
0e96f31e 8616 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8617
04140b41 8618 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8619 set_bit(vcpu->arch.interrupt.nr,
8620 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8621}
16d7a191 8622
01643c51
KH		 8623int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8624 struct kvm_sregs *sregs)
8625{
8626 vcpu_load(vcpu);
8627 __get_sregs(vcpu, sregs);
bcdec41c 8628 vcpu_put(vcpu);
b6c7a5dc
HB		 8629 return 0;
8630}
8631
62d9f0db
MT		 8632int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8633 struct kvm_mp_state *mp_state)
8634{
fd232561
CD		 8635 vcpu_load(vcpu);
8636
66450a21 8637 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8638 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8639 vcpu->arch.pv.pv_unhalted)
8640 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8641 else
8642 mp_state->mp_state = vcpu->arch.mp_state;
8643
fd232561 8644 vcpu_put(vcpu);
62d9f0db
MT		 8645 return 0;
8646}
8647
8648int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8649 struct kvm_mp_state *mp_state)
8650{
e83dff5e
CD		 8651 int ret = -EINVAL;
8652
8653 vcpu_load(vcpu);
8654
bce87cce 8655 if (!lapic_in_kernel(vcpu) &&
66450a21 8656 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8657 goto out;
66450a21 8658
28bf2888
DH		 8659 /* INITs are latched while in SMM */
8660 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8661 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8662 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8663 goto out;
28bf2888 8664
66450a21
JK		 8665 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8666 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8667 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8668 } else
8669 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8670 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8671
8672 ret = 0;
8673out:
8674 vcpu_put(vcpu);
8675 return ret;
62d9f0db
MT		 8676}
8677
7f3d35fd
KW		 8678int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8679 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8680{
9d74191a 8681 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8682 int ret;
e01c2426 8683
8ec4722d 8684 init_emulate_ctxt(vcpu);
c697518a 8685
7f3d35fd 8686 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8687 has_error_code, error_code);
c697518a 8688
c697518a 8689 if (ret)
19d04437 8690 return EMULATE_FAIL;
37817f29 8691
9d74191a
TY		 8692 kvm_rip_write(vcpu, ctxt->eip);
8693 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8694 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8695 return EMULATE_DONE;
37817f29
IE		 8696}
8697EXPORT_SYMBOL_GPL(kvm_task_switch);
8698
3140c156 8699static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8700{
74fec5b9
TL		 8701 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8702 (sregs->cr4 & X86_CR4_OSXSAVE))
8703 return -EINVAL;
8704
37b95951 8705 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8706 /*
8707 * When EFER.LME and CR0.PG are set, the processor is in
8708 * 64-bit mode (though maybe in a 32-bit code segment).
8709 * CR4.PAE and EFER.LMA must be set.
8710 */
37b95951 8711 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8712 || !(sregs->efer & EFER_LMA))
8713 return -EINVAL;
8714 } else {
8715 /*
8716 * Not in 64-bit mode: EFER.LMA is clear and the code
8717 * segment cannot be 64-bit.
8718 */
8719 if (sregs->efer & EFER_LMA || sregs->cs.l)
8720 return -EINVAL;
8721 }
8722
8723 return 0;
8724}
8725
01643c51 8726static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8727{
58cb628d 8728 struct msr_data apic_base_msr;
b6c7a5dc 8729 int mmu_reset_needed = 0;
c4d21882 8730 int cpuid_update_needed = 0;
63f42e02 8731 int pending_vec, max_bits, idx;
89a27f4d 8732 struct desc_ptr dt;
b4ef9d4e
CD		 8733 int ret = -EINVAL;
8734
f2981033 8735 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8736 goto out;
f2981033 8737
d3802286
JM		 8738 apic_base_msr.data = sregs->apic_base;
8739 apic_base_msr.host_initiated = true;
8740 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8741 goto out;
6d1068b3 8742
89a27f4d
GN		 8743 dt.size = sregs->idt.limit;
8744 dt.address = sregs->idt.base;
b6c7a5dc 8745 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8746 dt.size = sregs->gdt.limit;
8747 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8748 kvm_x86_ops->set_gdt(vcpu, &dt);
8749
ad312c7c 8750 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8751 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8752 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8753 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8754
2d3ad1f4 8755 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8756
f6801dff 8757 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8758 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8759
4d4ec087 8760 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8761 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8762 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8763
fc78f519 8764 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8765 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8766 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8767 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8768 if (cpuid_update_needed)
00b27a3e 8769 kvm_update_cpuid(vcpu);
63f42e02
XG		 8770
8771 idx = srcu_read_lock(&vcpu->kvm->srcu);
bf03d4f9 8772 if (is_pae_paging(vcpu)) {
9f8fe504 8773 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8774 mmu_reset_needed = 1;
8775 }
63f42e02 8776 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8777
8778 if (mmu_reset_needed)
8779 kvm_mmu_reset_context(vcpu);
8780
a50abc3b 8781 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8782 pending_vec = find_first_bit(
8783 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8784 if (pending_vec < max_bits) {
66fd3f7f 8785 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8786 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8787 }
8788
3e6e0aab
GT		 8789 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8790 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8791 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8792 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8793 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8794 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8795
3e6e0aab
GT		 8796 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8797 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8798
5f0269f5
ME		 8799 update_cr8_intercept(vcpu);
8800
9c3e4aab 8801 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8802 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8803 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8804 !is_protmode(vcpu))
9c3e4aab
MT		 8805 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8806
3842d135
AK		 8807 kvm_make_request(KVM_REQ_EVENT, vcpu);
8808
b4ef9d4e
CD		 8809 ret = 0;
8810out:
01643c51
KH		 8811 return ret;
8812}
8813
8814int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8815 struct kvm_sregs *sregs)
8816{
8817 int ret;
8818
8819 vcpu_load(vcpu);
8820 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8821 vcpu_put(vcpu);
8822 return ret;
b6c7a5dc
HB		 8823}
8824
d0bfb940
JK		 8825int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8826 struct kvm_guest_debug *dbg)
b6c7a5dc 8827{
355be0b9 8828 unsigned long rflags;
ae675ef0 8829 int i, r;
b6c7a5dc 8830
66b56562
CD		 8831 vcpu_load(vcpu);
8832
4f926bf2
JK		 8833 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8834 r = -EBUSY;
8835 if (vcpu->arch.exception.pending)
2122ff5e 8836 goto out;
4f926bf2
JK		 8837 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8838 kvm_queue_exception(vcpu, DB_VECTOR);
8839 else
8840 kvm_queue_exception(vcpu, BP_VECTOR);
8841 }
8842
91586a3b
JK		 8843 /*
8844 * Read rflags as long as potentially injected trace flags are still
8845 * filtered out.
8846 */
8847 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8848
8849 vcpu->guest_debug = dbg->control;
8850 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8851 vcpu->guest_debug = 0;
8852
8853 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8854 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8855 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8856 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8857 } else {
8858 for (i = 0; i < KVM_NR_DB_REGS; i++)
8859 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8860 }
c8639010 8861 kvm_update_dr7(vcpu);
ae675ef0 8862
f92653ee
JK		 8863 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8864 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8865 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8866
91586a3b
JK		 8867 /*
8868 * Trigger an rflags update that will inject or remove the trace
8869 * flags.
8870 */
8871 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8872
a96036b8 8873 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8874
4f926bf2 8875 r = 0;
d0bfb940 8876
2122ff5e 8877out:
66b56562 8878 vcpu_put(vcpu);
b6c7a5dc
HB		 8879 return r;
8880}
8881
8b006791
ZX		 8882/*
8883 * Translate a guest virtual address to a guest physical address.
8884 */
8885int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8886 struct kvm_translation *tr)
8887{
8888 unsigned long vaddr = tr->linear_address;
8889 gpa_t gpa;
f656ce01 8890 int idx;
8b006791 8891
1da5b61d
CD		 8892 vcpu_load(vcpu);
8893
f656ce01 8894 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8895 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8896 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8897 tr->physical_address = gpa;
8898 tr->valid = gpa != UNMAPPED_GVA;
8899 tr->writeable = 1;
8900 tr->usermode = 0;
8b006791 8901
1da5b61d 8902 vcpu_put(vcpu);
8b006791
ZX		 8903 return 0;
8904}
8905
d0752060
HB		 8906int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8907{
1393123e 8908 struct fxregs_state *fxsave;
d0752060 8909
1393123e 8910 vcpu_load(vcpu);
d0752060 8911
b666a4b6 8912 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 8913 memcpy(fpu->fpr, fxsave->st_space, 128);
8914 fpu->fcw = fxsave->cwd;
8915 fpu->fsw = fxsave->swd;
8916 fpu->ftwx = fxsave->twd;
8917 fpu->last_opcode = fxsave->fop;
8918 fpu->last_ip = fxsave->rip;
8919 fpu->last_dp = fxsave->rdp;
0e96f31e 8920 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 8921
1393123e 8922 vcpu_put(vcpu);
d0752060
HB		 8923 return 0;
8924}
8925
8926int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8927{
6a96bc7f
CD		 8928 struct fxregs_state *fxsave;
8929
8930 vcpu_load(vcpu);
8931
b666a4b6 8932 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 8933
d0752060
HB		 8934 memcpy(fxsave->st_space, fpu->fpr, 128);
8935 fxsave->cwd = fpu->fcw;
8936 fxsave->swd = fpu->fsw;
8937 fxsave->twd = fpu->ftwx;
8938 fxsave->fop = fpu->last_opcode;
8939 fxsave->rip = fpu->last_ip;
8940 fxsave->rdp = fpu->last_dp;
0e96f31e 8941 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 8942
6a96bc7f 8943 vcpu_put(vcpu);
d0752060
HB		 8944 return 0;
8945}
8946
01643c51
KH		 8947static void store_regs(struct kvm_vcpu *vcpu)
8948{
8949 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8950
8951 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8952 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8953
8954 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8955 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8956
8957 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8958 kvm_vcpu_ioctl_x86_get_vcpu_events(
8959 vcpu, &vcpu->run->s.regs.events);
8960}
8961
8962static int sync_regs(struct kvm_vcpu *vcpu)
8963{
8964 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8965 return -EINVAL;
8966
8967 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8968 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8969 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8970 }
8971 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8972 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8973 return -EINVAL;
8974 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8975 }
8976 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8977 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8978 vcpu, &vcpu->run->s.regs.events))
8979 return -EINVAL;
8980 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8981 }
8982
8983 return 0;
8984}
8985
0ee6a517 8986static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8987{
b666a4b6 8988 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 8989 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 8990 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 8991 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8992
2acf923e
DC		 8993 /*
8994 * Ensure guest xcr0 is valid for loading
8995 */
d91cab78 8996 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8997
ad312c7c 8998 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8999}
d0752060 9000
e9b11c17
ZX		 9001void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
9002{
bd768e14
IY		 9003 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
9004
12f9a48f 9005 kvmclock_reset(vcpu);
7f1ea208 9006
e9b11c17 9007 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 9008 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 9009}
9010
9011struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
9012 unsigned int id)
9013{
c447e76b
LL		 9014 struct kvm_vcpu *vcpu;
9015
b0c39dc6 9016 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 9017 printk_once(KERN_WARNING
9018 "kvm: SMP vm created on host with unstable TSC; "
9019 "guest TSC will not be reliable\n");
c447e76b
LL		 9020
9021 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
9022
c447e76b 9023 return vcpu;
26e5215f 9024}
e9b11c17 9025
26e5215f
AK		 9026int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
9027{
0cf9135b 9028 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
e53d88af 9029 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 9030 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 9031 vcpu_load(vcpu);
d28bc9dd 9032 kvm_vcpu_reset(vcpu, false);
e1732991 9033 kvm_init_mmu(vcpu, false);
e9b11c17 9034 vcpu_put(vcpu);
ec7660cc 9035 return 0;
e9b11c17
ZX		 9036}
9037
31928aa5 9038void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 9039{
8fe8ab46 9040 struct msr_data msr;
332967a3 9041 struct kvm *kvm = vcpu->kvm;
42897d86 9042
d3457c87
RK		 9043 kvm_hv_vcpu_postcreate(vcpu);
9044
ec7660cc 9045 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 9046 return;
ec7660cc 9047 vcpu_load(vcpu);
8fe8ab46
WA		 9048 msr.data = 0x0;
9049 msr.index = MSR_IA32_TSC;
9050 msr.host_initiated = true;
9051 kvm_write_tsc(vcpu, &msr);
42897d86 9052 vcpu_put(vcpu);
2d5ba19b
MT		 9053
9054 /* poll control enabled by default */
9055 vcpu->arch.msr_kvm_poll_control = 1;
9056
ec7660cc 9057 mutex_unlock(&vcpu->mutex);
42897d86 9058
630994b3
MT		 9059 if (!kvmclock_periodic_sync)
9060 return;
9061
332967a3
AJ		 9062 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9063 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 9064}
9065
d40ccc62 9066void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 9067{
344d9588
GN		 9068 vcpu->arch.apf.msr_val = 0;
9069
ec7660cc 9070 vcpu_load(vcpu);
e9b11c17
ZX		 9071 kvm_mmu_unload(vcpu);
9072 vcpu_put(vcpu);
9073
9074 kvm_x86_ops->vcpu_free(vcpu);
9075}
9076
d28bc9dd 9077void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 9078{
b7e31be3
RK		 9079 kvm_lapic_reset(vcpu, init_event);
9080
e69fab5d
PB		 9081 vcpu->arch.hflags = 0;
9082
c43203ca 9083 vcpu->arch.smi_pending = 0;
52797bf9 9084 vcpu->arch.smi_count = 0;
7460fb4a
AK		 9085 atomic_set(&vcpu->arch.nmi_queued, 0);
9086 vcpu->arch.nmi_pending = 0;
448fa4a9 9087 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 9088 kvm_clear_interrupt_queue(vcpu);
9089 kvm_clear_exception_queue(vcpu);
664f8e26 9090 vcpu->arch.exception.pending = false;
448fa4a9 9091
42dbaa5a 9092 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 9093 kvm_update_dr0123(vcpu);
6f43ed01 9094 vcpu->arch.dr6 = DR6_INIT;
73aaf249 9095 kvm_update_dr6(vcpu);
42dbaa5a 9096 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 9097 kvm_update_dr7(vcpu);
42dbaa5a 9098
1119022c
NA		 9099 vcpu->arch.cr2 = 0;
9100
3842d135 9101 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 9102 vcpu->arch.apf.msr_val = 0;
c9aaa895 9103 vcpu->arch.st.msr_val = 0;
3842d135 9104
12f9a48f
GC		 9105 kvmclock_reset(vcpu);
9106
af585b92
GN		 9107 kvm_clear_async_pf_completion_queue(vcpu);
9108 kvm_async_pf_hash_reset(vcpu);
9109 vcpu->arch.apf.halted = false;
3842d135 9110
a554d207
WL		 9111 if (kvm_mpx_supported()) {
9112 void *mpx_state_buffer;
9113
9114 /*
9115 * To avoid have the INIT path from kvm_apic_has_events() that be
9116 * called with loaded FPU and does not let userspace fix the state.
9117 */
f775b13e
RR		 9118 if (init_event)
9119 kvm_put_guest_fpu(vcpu);
b666a4b6 9120 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9121 XFEATURE_BNDREGS);
a554d207
WL		 9122 if (mpx_state_buffer)
9123 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 9124 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9125 XFEATURE_BNDCSR);
a554d207
WL		 9126 if (mpx_state_buffer)
9127 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 9128 if (init_event)
9129 kvm_load_guest_fpu(vcpu);
a554d207
WL		 9130 }
9131
64d60670 9132 if (!init_event) {
d28bc9dd 9133 kvm_pmu_reset(vcpu);
64d60670 9134 vcpu->arch.smbase = 0x30000;
db2336a8 9135
db2336a8 9136 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 9137
9138 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 9139 }
f5132b01 9140
66f7b72e
JS		 9141 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9142 vcpu->arch.regs_avail = ~0;
9143 vcpu->arch.regs_dirty = ~0;
9144
a554d207
WL		 9145 vcpu->arch.ia32_xss = 0;
9146
d28bc9dd 9147 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 9148}
9149
2b4a273b 9150void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 9151{
9152 struct kvm_segment cs;
9153
9154 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9155 cs.selector = vector << 8;
9156 cs.base = vector << 12;
9157 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9158 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 9159}
9160
13a34e06 9161int kvm_arch_hardware_enable(void)
e9b11c17 9162{
ca84d1a2
ZA		 9163 struct kvm *kvm;
9164 struct kvm_vcpu *vcpu;
9165 int i;
0dd6a6ed
ZA		 9166 int ret;
9167 u64 local_tsc;
9168 u64 max_tsc = 0;
9169 bool stable, backwards_tsc = false;
18863bdd
AK		 9170
9171 kvm_shared_msr_cpu_online();
13a34e06 9172 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 9173 if (ret != 0)
9174 return ret;
9175
4ea1636b 9176 local_tsc = rdtsc();
b0c39dc6 9177 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 9178 list_for_each_entry(kvm, &vm_list, vm_list) {
9179 kvm_for_each_vcpu(i, vcpu, kvm) {
9180 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 9181 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9182 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9183 backwards_tsc = true;
9184 if (vcpu->arch.last_host_tsc > max_tsc)
9185 max_tsc = vcpu->arch.last_host_tsc;
9186 }
9187 }
9188 }
9189
9190 /*
9191 * Sometimes, even reliable TSCs go backwards. This happens on
9192 * platforms that reset TSC during suspend or hibernate actions, but
9193 * maintain synchronization. We must compensate. Fortunately, we can
9194 * detect that condition here, which happens early in CPU bringup,
9195 * before any KVM threads can be running. Unfortunately, we can't
9196 * bring the TSCs fully up to date with real time, as we aren't yet far
9197 * enough into CPU bringup that we know how much real time has actually
9285ec4c 9198 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
0dd6a6ed
ZA		 9199 * variables that haven't been updated yet.
9200 *
9201 * So we simply find the maximum observed TSC above, then record the
9202 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9203 * the adjustment will be applied. Note that we accumulate
9204 * adjustments, in case multiple suspend cycles happen before some VCPU
9205 * gets a chance to run again. In the event that no KVM threads get a
9206 * chance to run, we will miss the entire elapsed period, as we'll have
9207 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9208 * loose cycle time. This isn't too big a deal, since the loss will be
9209 * uniform across all VCPUs (not to mention the scenario is extremely
9210 * unlikely). It is possible that a second hibernate recovery happens
9211 * much faster than a first, causing the observed TSC here to be
9212 * smaller; this would require additional padding adjustment, which is
9213 * why we set last_host_tsc to the local tsc observed here.
9214 *
9215 * N.B. - this code below runs only on platforms with reliable TSC,
9216 * as that is the only way backwards_tsc is set above. Also note
9217 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9218 * have the same delta_cyc adjustment applied if backwards_tsc
9219 * is detected. Note further, this adjustment is only done once,
9220 * as we reset last_host_tsc on all VCPUs to stop this from being
9221 * called multiple times (one for each physical CPU bringup).
9222 *
4a969980 9223 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 9224 * will be compensated by the logic in vcpu_load, which sets the TSC to
9225 * catchup mode. This will catchup all VCPUs to real time, but cannot
9226 * guarantee that they stay in perfect synchronization.
9227 */
9228 if (backwards_tsc) {
9229 u64 delta_cyc = max_tsc - local_tsc;
9230 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 9231 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 9232 kvm_for_each_vcpu(i, vcpu, kvm) {
9233 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9234 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 9235 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9236 }
9237
9238 /*
9239 * We have to disable TSC offset matching.. if you were
9240 * booting a VM while issuing an S4 host suspend....
9241 * you may have some problem. Solving this issue is
9242 * left as an exercise to the reader.
9243 */
9244 kvm->arch.last_tsc_nsec = 0;
9245 kvm->arch.last_tsc_write = 0;
9246 }
9247
9248 }
9249 return 0;
e9b11c17
ZX		 9250}
9251
13a34e06 9252void kvm_arch_hardware_disable(void)
e9b11c17 9253{
13a34e06
RK		 9254 kvm_x86_ops->hardware_disable();
9255 drop_user_return_notifiers();
e9b11c17
ZX		 9256}
9257
9258int kvm_arch_hardware_setup(void)
9259{
9e9c3fe4
NA		 9260 int r;
9261
9262 r = kvm_x86_ops->hardware_setup();
9263 if (r != 0)
9264 return r;
9265
35181e86
HZ		 9266 if (kvm_has_tsc_control) {
9267 /*
9268 * Make sure the user can only configure tsc_khz values that
9269 * fit into a signed integer.
273ba457 9270 * A min value is not calculated because it will always
35181e86
HZ		 9271 * be 1 on all machines.
9272 */
9273 u64 max = min(0x7fffffffULL,
9274 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9275 kvm_max_guest_tsc_khz = max;
9276
ad721883 9277 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 9278 }
ad721883 9279
9e9c3fe4
NA		 9280 kvm_init_msr_list();
9281 return 0;
e9b11c17
ZX		 9282}
9283
9284void kvm_arch_hardware_unsetup(void)
9285{
9286 kvm_x86_ops->hardware_unsetup();
9287}
9288
f257d6dc 9289int kvm_arch_check_processor_compat(void)
e9b11c17 9290{
f257d6dc 9291 return kvm_x86_ops->check_processor_compatibility();
d71ba788
PB		 9292}
9293
9294bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9295{
9296 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9297}
9298EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9299
9300bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9301{
9302 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 9303}
9304
54e9818f 9305struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 9306EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 9307
e9b11c17
ZX		 9308int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9309{
9310 struct page *page;
e9b11c17
ZX		 9311 int r;
9312
9aabc88f 9313 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 9314 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 9315 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 9316 else
a4535290 9317 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 9318
9319 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9320 if (!page) {
9321 r = -ENOMEM;
9322 goto fail;
9323 }
ad312c7c 9324 vcpu->arch.pio_data = page_address(page);
e9b11c17 9325
cc578287 9326 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 9327
e9b11c17
ZX		 9328 r = kvm_mmu_create(vcpu);
9329 if (r < 0)
9330 goto fail_free_pio_data;
9331
26de7988 9332 if (irqchip_in_kernel(vcpu->kvm)) {
f7589cca 9333 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
39497d76 9334 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
e9b11c17
ZX		 9335 if (r < 0)
9336 goto fail_mmu_destroy;
54e9818f
GN		 9337 } else
9338 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 9339
890ca9ae 9340 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
254272ce 9341 GFP_KERNEL_ACCOUNT);
890ca9ae
HY		 9342 if (!vcpu->arch.mce_banks) {
9343 r = -ENOMEM;
443c39bc 9344 goto fail_free_lapic;
890ca9ae
HY		 9345 }
9346 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9347
254272ce
BG		 9348 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9349 GFP_KERNEL_ACCOUNT)) {
f1797359 9350 r = -ENOMEM;
f5f48ee1 9351 goto fail_free_mce_banks;
f1797359 9352 }
f5f48ee1 9353
0ee6a517 9354 fx_init(vcpu);
66f7b72e 9355
4344ee98 9356 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 9357
5a4f55cd
EK		 9358 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9359
74545705
RK		 9360 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9361
af585b92 9362 kvm_async_pf_hash_reset(vcpu);
f5132b01 9363 kvm_pmu_init(vcpu);
af585b92 9364
1c1a9ce9 9365 vcpu->arch.pending_external_vector = -1;
de63ad4c 9366 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 9367
5c919412
AS		 9368 kvm_hv_vcpu_init(vcpu);
9369
e9b11c17 9370 return 0;
0ee6a517 9371
f5f48ee1
SY		 9372fail_free_mce_banks:
9373 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 9374fail_free_lapic:
9375 kvm_free_lapic(vcpu);
e9b11c17
ZX		 9376fail_mmu_destroy:
9377 kvm_mmu_destroy(vcpu);
9378fail_free_pio_data:
ad312c7c 9379 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 9380fail:
9381 return r;
9382}
9383
9384void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9385{
f656ce01
MT		 9386 int idx;
9387
1f4b34f8 9388 kvm_hv_vcpu_uninit(vcpu);
f5132b01 9389 kvm_pmu_destroy(vcpu);
36cb93fd 9390 kfree(vcpu->arch.mce_banks);
e9b11c17 9391 kvm_free_lapic(vcpu);
f656ce01 9392 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 9393 kvm_mmu_destroy(vcpu);
f656ce01 9394 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 9395 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 9396 if (!lapic_in_kernel(vcpu))
54e9818f 9397 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 9398}
d19a9cd2 9399
e790d9ef
RK		 9400void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9401{
c595ceee 9402 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 9403 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9404}
9405
e08b9637 9406int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9407{
e08b9637
CO		 9408 if (type)
9409 return -EINVAL;
9410
6ef768fa 9411 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9412 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 9413 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9414 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9415
5550af4d
SY		 9416 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9417 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9418 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9419 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9420 &kvm->arch.irq_sources_bitmap);
5550af4d 9421
038f8c11 9422 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9423 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9424 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9425
9285ec4c 9426 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
d828199e 9427 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9428
6fbbde9a
DS		 9429 kvm->arch.guest_can_read_msr_platform_info = true;
9430
7e44e449 9431 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9432 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9433
cbc0236a 9434 kvm_hv_init_vm(kvm);
0eb05bf2 9435 kvm_page_track_init(kvm);
13d268ca 9436 kvm_mmu_init_vm(kvm);
0eb05bf2 9437
92735b1b 9438 return kvm_x86_ops->vm_init(kvm);
d19a9cd2
ZX		 9439}
9440
9441static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9442{
ec7660cc 9443 vcpu_load(vcpu);
d19a9cd2
ZX		 9444 kvm_mmu_unload(vcpu);
9445 vcpu_put(vcpu);
9446}
9447
9448static void kvm_free_vcpus(struct kvm *kvm)
9449{
9450 unsigned int i;
988a2cae 9451 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9452
9453 /*
9454 * Unpin any mmu pages first.
9455 */
af585b92
GN		 9456 kvm_for_each_vcpu(i, vcpu, kvm) {
9457 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9458 kvm_unload_vcpu_mmu(vcpu);
af585b92 9459 }
988a2cae
GN		 9460 kvm_for_each_vcpu(i, vcpu, kvm)
9461 kvm_arch_vcpu_free(vcpu);
9462
9463 mutex_lock(&kvm->lock);
9464 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9465 kvm->vcpus[i] = NULL;
d19a9cd2 9466
988a2cae
GN		 9467 atomic_set(&kvm->online_vcpus, 0);
9468 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9469}
9470
ad8ba2cd
SY		 9471void kvm_arch_sync_events(struct kvm *kvm)
9472{
332967a3 9473 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9474 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9475 kvm_free_pit(kvm);
ad8ba2cd
SY		 9476}
9477
1d8007bd 9478int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9479{
9480 int i, r;
25188b99 9481 unsigned long hva;
f0d648bd
PB		 9482 struct kvm_memslots *slots = kvm_memslots(kvm);
9483 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9484
9485 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9486 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9487 return -EINVAL;
9da0e4d5 9488
f0d648bd
PB		 9489 slot = id_to_memslot(slots, id);
9490 if (size) {
b21629da 9491 if (slot->npages)
f0d648bd
PB		 9492 return -EEXIST;
9493
9494 /*
9495 * MAP_SHARED to prevent internal slot pages from being moved
9496 * by fork()/COW.
9497 */
9498 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9499 MAP_SHARED | MAP_ANONYMOUS, 0);
9500 if (IS_ERR((void *)hva))
9501 return PTR_ERR((void *)hva);
9502 } else {
9503 if (!slot->npages)
9504 return 0;
9505
9506 hva = 0;
9507 }
9508
9509 old = *slot;
9da0e4d5 9510 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9511 struct kvm_userspace_memory_region m;
9da0e4d5 9512
1d8007bd
PB		 9513 m.slot = id | (i << 16);
9514 m.flags = 0;
9515 m.guest_phys_addr = gpa;
f0d648bd 9516 m.userspace_addr = hva;
1d8007bd 9517 m.memory_size = size;
9da0e4d5
PB		 9518 r = __kvm_set_memory_region(kvm, &m);
9519 if (r < 0)
9520 return r;
9521 }
9522
103c763c
EB		 9523 if (!size)
9524 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9525
9da0e4d5
PB		 9526 return 0;
9527}
9528EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9529
1d8007bd 9530int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9531{
9532 int r;
9533
9534 mutex_lock(&kvm->slots_lock);
1d8007bd 9535 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9536 mutex_unlock(&kvm->slots_lock);
9537
9538 return r;
9539}
9540EXPORT_SYMBOL_GPL(x86_set_memory_region);
9541
d19a9cd2
ZX		 9542void kvm_arch_destroy_vm(struct kvm *kvm)
9543{
27469d29
AH		 9544 if (current->mm == kvm->mm) {
9545 /*
9546 * Free memory regions allocated on behalf of userspace,
9547 * unless the the memory map has changed due to process exit
9548 * or fd copying.
9549 */
1d8007bd
PB		 9550 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9551 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9552 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9553 }
03543133
SS		 9554 if (kvm_x86_ops->vm_destroy)
9555 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9556 kvm_pic_destroy(kvm);
9557 kvm_ioapic_destroy(kvm);
d19a9cd2 9558 kvm_free_vcpus(kvm);
af1bae54 9559 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
66bb8a06 9560 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
13d268ca 9561 kvm_mmu_uninit_vm(kvm);
2beb6dad 9562 kvm_page_track_cleanup(kvm);
cbc0236a 9563 kvm_hv_destroy_vm(kvm);
d19a9cd2 9564}
0de10343 9565
5587027c 9566void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9567 struct kvm_memory_slot *dont)
9568{
9569 int i;
9570
d89cc617
TY		 9571 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9572 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9573 kvfree(free->arch.rmap[i]);
d89cc617 9574 free->arch.rmap[i] = NULL;
77d11309 9575 }
d89cc617
TY		 9576 if (i == 0)
9577 continue;
9578
9579 if (!dont || free->arch.lpage_info[i - 1] !=
9580 dont->arch.lpage_info[i - 1]) {
548ef284 9581 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9582 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9583 }
9584 }
21ebbeda
XG		 9585
9586 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9587}
9588
5587027c
AK		 9589int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9590 unsigned long npages)
db3fe4eb
TY		 9591{
9592 int i;
9593
d89cc617 9594 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9595 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9596 unsigned long ugfn;
9597 int lpages;
d89cc617 9598 int level = i + 1;
db3fe4eb
TY		 9599
9600 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9601 slot->base_gfn, level) + 1;
9602
d89cc617 9603 slot->arch.rmap[i] =
778e1cdd 9604 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
254272ce 9605 GFP_KERNEL_ACCOUNT);
d89cc617 9606 if (!slot->arch.rmap[i])
77d11309 9607 goto out_free;
d89cc617
TY		 9608 if (i == 0)
9609 continue;
77d11309 9610
254272ce 9611 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
92f94f1e 9612 if (!linfo)
db3fe4eb
TY		 9613 goto out_free;
9614
92f94f1e
XG		 9615 slot->arch.lpage_info[i - 1] = linfo;
9616
db3fe4eb 9617 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9618 linfo[0].disallow_lpage = 1;
db3fe4eb 9619 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9620 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9621 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9622 /*
9623 * If the gfn and userspace address are not aligned wrt each
9624 * other, or if explicitly asked to, disable large page
9625 * support for this slot
9626 */
9627 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9628 !kvm_largepages_enabled()) {
9629 unsigned long j;
9630
9631 for (j = 0; j < lpages; ++j)
92f94f1e 9632 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9633 }
9634 }
9635
21ebbeda
XG		 9636 if (kvm_page_track_create_memslot(slot, npages))
9637 goto out_free;
9638
db3fe4eb
TY		 9639 return 0;
9640
9641out_free:
d89cc617 9642 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9643 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9644 slot->arch.rmap[i] = NULL;
9645 if (i == 0)
9646 continue;
9647
548ef284 9648 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9649 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9650 }
9651 return -ENOMEM;
9652}
9653
15248258 9654void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
e59dbe09 9655{
e6dff7d1
TY		 9656 /*
9657 * memslots->generation has been incremented.
9658 * mmio generation may have reached its maximum value.
9659 */
15248258 9660 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
e59dbe09
TY		 9661}
9662
f7784b8e
MT		 9663int kvm_arch_prepare_memory_region(struct kvm *kvm,
9664 struct kvm_memory_slot *memslot,
09170a49 9665 const struct kvm_userspace_memory_region *mem,
7b6195a9 9666 enum kvm_mr_change change)
0de10343 9667{
f7784b8e
MT		 9668 return 0;
9669}
9670
88178fd4
KH		 9671static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9672 struct kvm_memory_slot *new)
9673{
9674 /* Still write protect RO slot */
9675 if (new->flags & KVM_MEM_READONLY) {
9676 kvm_mmu_slot_remove_write_access(kvm, new);
9677 return;
9678 }
9679
9680 /*
9681 * Call kvm_x86_ops dirty logging hooks when they are valid.
9682 *
9683 * kvm_x86_ops->slot_disable_log_dirty is called when:
9684 *
9685 * - KVM_MR_CREATE with dirty logging is disabled
9686 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9687 *
9688 * The reason is, in case of PML, we need to set D-bit for any slots
9689 * with dirty logging disabled in order to eliminate unnecessary GPA
9690 * logging in PML buffer (and potential PML buffer full VMEXT). This
9691 * guarantees leaving PML enabled during guest's lifetime won't have
bdd303cb 9692 * any additional overhead from PML when guest is running with dirty
88178fd4
KH		 9693 * logging disabled for memory slots.
9694 *
9695 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9696 * to dirty logging mode.
9697 *
9698 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9699 *
9700 * In case of write protect:
9701 *
9702 * Write protect all pages for dirty logging.
9703 *
9704 * All the sptes including the large sptes which point to this
9705 * slot are set to readonly. We can not create any new large
9706 * spte on this slot until the end of the logging.
9707 *
9708 * See the comments in fast_page_fault().
9709 */
9710 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9711 if (kvm_x86_ops->slot_enable_log_dirty)
9712 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9713 else
9714 kvm_mmu_slot_remove_write_access(kvm, new);
9715 } else {
9716 if (kvm_x86_ops->slot_disable_log_dirty)
9717 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9718 }
9719}
9720
f7784b8e 9721void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9722 const struct kvm_userspace_memory_region *mem,
8482644a 9723 const struct kvm_memory_slot *old,
f36f3f28 9724 const struct kvm_memory_slot *new,
8482644a 9725 enum kvm_mr_change change)
f7784b8e 9726{
48c0e4e9 9727 if (!kvm->arch.n_requested_mmu_pages)
4d66623c
WY		 9728 kvm_mmu_change_mmu_pages(kvm,
9729 kvm_mmu_calculate_default_mmu_pages(kvm));
1c91cad4 9730
3ea3b7fa
WL		 9731 /*
9732 * Dirty logging tracks sptes in 4k granularity, meaning that large
9733 * sptes have to be split. If live migration is successful, the guest
9734 * in the source machine will be destroyed and large sptes will be
9735 * created in the destination. However, if the guest continues to run
9736 * in the source machine (for example if live migration fails), small
9737 * sptes will remain around and cause bad performance.
9738 *
9739 * Scan sptes if dirty logging has been stopped, dropping those
9740 * which can be collapsed into a single large-page spte. Later
9741 * page faults will create the large-page sptes.
9742 */
9743 if ((change != KVM_MR_DELETE) &&
9744 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9745 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9746 kvm_mmu_zap_collapsible_sptes(kvm, new);
9747
c972f3b1 9748 /*
88178fd4 9749 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9750 *
88178fd4
KH		 9751 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9752 * been zapped so no dirty logging staff is needed for old slot. For
9753 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9754 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9755 *
9756 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9757 */
88178fd4 9758 if (change != KVM_MR_DELETE)
f36f3f28 9759 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9760}
1d737c8a 9761
2df72e9b 9762void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9763{
7390de1e 9764 kvm_mmu_zap_all(kvm);
34d4cb8f
MT		 9765}
9766
2df72e9b
MT		 9767void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9768 struct kvm_memory_slot *slot)
9769{
ae7cd873 9770 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9771}
9772
e6c67d8c
LA		 9773static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9774{
9775 return (is_guest_mode(vcpu) &&
9776 kvm_x86_ops->guest_apic_has_interrupt &&
9777 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9778}
9779
5d9bc648
PB		 9780static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9781{
9782 if (!list_empty_careful(&vcpu->async_pf.done))
9783 return true;
9784
9785 if (kvm_apic_has_events(vcpu))
9786 return true;
9787
9788 if (vcpu->arch.pv.pv_unhalted)
9789 return true;
9790
a5f01f8e
WL		 9791 if (vcpu->arch.exception.pending)
9792 return true;
9793
47a66eed
Z		 9794 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9795 (vcpu->arch.nmi_pending &&
9796 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9797 return true;
9798
47a66eed
Z		 9799 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9800 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9801 return true;
9802
5d9bc648 9803 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9804 (kvm_cpu_has_interrupt(vcpu) ||
9805 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9806 return true;
9807
1f4b34f8
AS		 9808 if (kvm_hv_has_stimer_pending(vcpu))
9809 return true;
9810
5d9bc648
PB		 9811 return false;
9812}
9813
1d737c8a
ZX		 9814int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9815{
5d9bc648 9816 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9817}
5736199a 9818
17e433b5
WL		 9819bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
9820{
9821 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
9822 return true;
9823
9824 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9825 kvm_test_request(KVM_REQ_SMI, vcpu) ||
9826 kvm_test_request(KVM_REQ_EVENT, vcpu))
9827 return true;
9828
9829 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
9830 return true;
9831
9832 return false;
9833}
9834
199b5763
LM		 9835bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9836{
de63ad4c 9837 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9838}
9839
b6d33834 9840int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9841{
b6d33834 9842 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9843}
78646121
GN		 9844
9845int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9846{
9847 return kvm_x86_ops->interrupt_allowed(vcpu);
9848}
229456fc 9849
82b32774 9850unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9851{
82b32774
NA		 9852 if (is_64_bit_mode(vcpu))
9853 return kvm_rip_read(vcpu);
9854 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9855 kvm_rip_read(vcpu));
9856}
9857EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9858
82b32774
NA		 9859bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9860{
9861 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9862}
9863EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9864
94fe45da
JK		 9865unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9866{
9867 unsigned long rflags;
9868
9869 rflags = kvm_x86_ops->get_rflags(vcpu);
9870 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9871 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9872 return rflags;
9873}
9874EXPORT_SYMBOL_GPL(kvm_get_rflags);
9875
6addfc42 9876static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9877{
9878 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9879 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9880 rflags |= X86_EFLAGS_TF;
94fe45da 9881 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9882}
9883
9884void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9885{
9886 __kvm_set_rflags(vcpu, rflags);
3842d135 9887 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9888}
9889EXPORT_SYMBOL_GPL(kvm_set_rflags);
9890
56028d08
GN		 9891void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9892{
9893 int r;
9894
44dd3ffa 9895 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9896 work->wakeup_all)
56028d08
GN		 9897 return;
9898
9899 r = kvm_mmu_reload(vcpu);
9900 if (unlikely(r))
9901 return;
9902
44dd3ffa
VK		 9903 if (!vcpu->arch.mmu->direct_map &&
9904 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9905 return;
9906
44dd3ffa 9907 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9908}
9909
af585b92
GN		 9910static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9911{
9912 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9913}
9914
9915static inline u32 kvm_async_pf_next_probe(u32 key)
9916{
9917 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9918}
9919
9920static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9921{
9922 u32 key = kvm_async_pf_hash_fn(gfn);
9923
9924 while (vcpu->arch.apf.gfns[key] != ~0)
9925 key = kvm_async_pf_next_probe(key);
9926
9927 vcpu->arch.apf.gfns[key] = gfn;
9928}
9929
9930static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9931{
9932 int i;
9933 u32 key = kvm_async_pf_hash_fn(gfn);
9934
9935 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9936 (vcpu->arch.apf.gfns[key] != gfn &&
9937 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9938 key = kvm_async_pf_next_probe(key);
9939
9940 return key;
9941}
9942
9943bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9944{
9945 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9946}
9947
9948static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9949{
9950 u32 i, j, k;
9951
9952 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9953 while (true) {
9954 vcpu->arch.apf.gfns[i] = ~0;
9955 do {
9956 j = kvm_async_pf_next_probe(j);
9957 if (vcpu->arch.apf.gfns[j] == ~0)
9958 return;
9959 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9960 /*
9961 * k lies cyclically in ]i,j]
9962 * | i.k.j |
9963 * |....j i.k.| or |.k..j i...|
9964 */
9965 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9966 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9967 i = j;
9968 }
9969}
9970
7c90705b
GN		 9971static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9972{
4e335d9e
PB		 9973
9974 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9975 sizeof(val));
7c90705b
GN		 9976}
9977
9a6e7c39
WL		 9978static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9979{
9980
9981 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9982 sizeof(u32));
9983}
9984
1dfdb45e
PB		 9985static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
9986{
9987 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
9988 return false;
9989
9990 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
9991 (vcpu->arch.apf.send_user_only &&
9992 kvm_x86_ops->get_cpl(vcpu) == 0))
9993 return false;
9994
9995 return true;
9996}
9997
9998bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
9999{
10000 if (unlikely(!lapic_in_kernel(vcpu) ||
10001 kvm_event_needs_reinjection(vcpu) ||
10002 vcpu->arch.exception.pending))
10003 return false;
10004
10005 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10006 return false;
10007
10008 /*
10009 * If interrupts are off we cannot even use an artificial
10010 * halt state.
10011 */
10012 return kvm_x86_ops->interrupt_allowed(vcpu);
10013}
10014
af585b92
GN		 10015void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10016 struct kvm_async_pf *work)
10017{
6389ee94
AK		 10018 struct x86_exception fault;
10019
7c90705b 10020 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 10021 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b 10022
1dfdb45e
PB		 10023 if (kvm_can_deliver_async_pf(vcpu) &&
10024 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 10025 fault.vector = PF_VECTOR;
10026 fault.error_code_valid = true;
10027 fault.error_code = 0;
10028 fault.nested_page_fault = false;
10029 fault.address = work->arch.token;
adfe20fb 10030 fault.async_page_fault = true;
6389ee94 10031 kvm_inject_page_fault(vcpu, &fault);
1dfdb45e
PB		 10032 } else {
10033 /*
10034 * It is not possible to deliver a paravirtualized asynchronous
10035 * page fault, but putting the guest in an artificial halt state
10036 * can be beneficial nevertheless: if an interrupt arrives, we
10037 * can deliver it timely and perhaps the guest will schedule
10038 * another process. When the instruction that triggered a page
10039 * fault is retried, hopefully the page will be ready in the host.
10040 */
10041 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7c90705b 10042 }
af585b92
GN		 10043}
10044
10045void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10046 struct kvm_async_pf *work)
10047{
6389ee94 10048 struct x86_exception fault;
9a6e7c39 10049 u32 val;
6389ee94 10050
f2e10669 10051 if (work->wakeup_all)
7c90705b
GN		 10052 work->arch.token = ~0; /* broadcast wakeup */
10053 else
10054 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 10055 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 10056
9a6e7c39
WL		 10057 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10058 !apf_get_user(vcpu, &val)) {
10059 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10060 vcpu->arch.exception.pending &&
10061 vcpu->arch.exception.nr == PF_VECTOR &&
10062 !apf_put_user(vcpu, 0)) {
10063 vcpu->arch.exception.injected = false;
10064 vcpu->arch.exception.pending = false;
10065 vcpu->arch.exception.nr = 0;
10066 vcpu->arch.exception.has_error_code = false;
10067 vcpu->arch.exception.error_code = 0;
c851436a
JM		 10068 vcpu->arch.exception.has_payload = false;
10069 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 10070 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10071 fault.vector = PF_VECTOR;
10072 fault.error_code_valid = true;
10073 fault.error_code = 0;
10074 fault.nested_page_fault = false;
10075 fault.address = work->arch.token;
10076 fault.async_page_fault = true;
10077 kvm_inject_page_fault(vcpu, &fault);
10078 }
7c90705b 10079 }
e6d53e3b 10080 vcpu->arch.apf.halted = false;
a4fa1635 10081 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 10082}
10083
10084bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10085{
10086 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10087 return true;
10088 else
9bc1f09f 10089 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 10090}
10091
5544eb9b
PB		 10092void kvm_arch_start_assignment(struct kvm *kvm)
10093{
10094 atomic_inc(&kvm->arch.assigned_device_count);
10095}
10096EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10097
10098void kvm_arch_end_assignment(struct kvm *kvm)
10099{
10100 atomic_dec(&kvm->arch.assigned_device_count);
10101}
10102EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10103
10104bool kvm_arch_has_assigned_device(struct kvm *kvm)
10105{
10106 return atomic_read(&kvm->arch.assigned_device_count);
10107}
10108EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10109
e0f0bbc5
AW		 10110void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10111{
10112 atomic_inc(&kvm->arch.noncoherent_dma_count);
10113}
10114EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10115
10116void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10117{
10118 atomic_dec(&kvm->arch.noncoherent_dma_count);
10119}
10120EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10121
10122bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10123{
10124 return atomic_read(&kvm->arch.noncoherent_dma_count);
10125}
10126EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10127
14717e20
AW		 10128bool kvm_arch_has_irq_bypass(void)
10129{
92735b1b 10130 return true;
14717e20
AW		 10131}
10132
87276880
FW		 10133int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10134 struct irq_bypass_producer *prod)
10135{
10136 struct kvm_kernel_irqfd *irqfd =
10137 container_of(cons, struct kvm_kernel_irqfd, consumer);
10138
14717e20 10139 irqfd->producer = prod;
87276880 10140
14717e20
AW		 10141 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10142 prod->irq, irqfd->gsi, 1);
87276880
FW		 10143}
10144
10145void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10146 struct irq_bypass_producer *prod)
10147{
10148 int ret;
10149 struct kvm_kernel_irqfd *irqfd =
10150 container_of(cons, struct kvm_kernel_irqfd, consumer);
10151
87276880
FW		 10152 WARN_ON(irqfd->producer != prod);
10153 irqfd->producer = NULL;
10154
10155 /*
10156 * When producer of consumer is unregistered, we change back to
10157 * remapped mode, so we can re-use the current implementation
bb3541f1 10158 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 10159 * int this case doesn't want to receive the interrupts.
10160 */
10161 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10162 if (ret)
10163 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10164 " fails: %d\n", irqfd->consumer.token, ret);
10165}
10166
10167int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10168 uint32_t guest_irq, bool set)
10169{
87276880
FW		 10170 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10171}
10172
52004014
FW		 10173bool kvm_vector_hashing_enabled(void)
10174{
10175 return vector_hashing;
10176}
10177EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10178
2d5ba19b
MT		 10179bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10180{
10181 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10182}
10183EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10184
10185
229456fc 10186EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 10187EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 10188EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10189EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10190EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10191EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 10192EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 10193EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 10194EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 10195EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
5497b955 10196EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
ec1ff790 10197EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 10198EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 10199EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 10200EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
4f75bcc3 10201EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
843e4330 10202EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 10203EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 10204EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10205EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)