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KVM: selftests: fix ucall on x86
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
043405e1
CO		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
9611c187 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 17 */
18
edf88417 19#include <linux/kvm_host.h>
313a3dc7 20#include "irq.h"
1d737c8a 21#include "mmu.h"
7837699f 22#include "i8254.h"
37817f29 23#include "tss.h"
5fdbf976 24#include "kvm_cache_regs.h"
26eef70c 25#include "x86.h"
00b27a3e 26#include "cpuid.h"
474a5bb9 27#include "pmu.h"
e83d5887 28#include "hyperv.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
1767e931
PG		 35#include <linux/export.h>
36#include <linux/moduleparam.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
87276880
FW		 51#include <linux/kvm_irqfd.h>
52#include <linux/irqbypass.h>
3905f9ad 53#include <linux/sched/stat.h>
0c5f81da 54#include <linux/sched/isolation.h>
d0ec49d4 55#include <linux/mem_encrypt.h>
3905f9ad 56
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
b0c39dc6 68#include <asm/mshyperv.h>
0092e434 69#include <asm/hypervisor.h>
bf8c55d8 70#include <asm/intel_pt.h>
dd2cb348 71#include <clocksource/hyperv_timer.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
c3941d9e
SC		 138/*
139 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
140 * adaptive tuning starting from default advancment of 1000ns. '0' disables
141 * advancement entirely. Any other value is used as-is and disables adaptive
142 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
143 */
144static int __read_mostly lapic_timer_advance_ns = -1;
0e6edceb 145module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
d0659d94 146
52004014
FW		 147static bool __read_mostly vector_hashing = true;
148module_param(vector_hashing, bool, S_IRUGO);
149
c4ae60e4
LA		 150bool __read_mostly enable_vmware_backdoor = false;
151module_param(enable_vmware_backdoor, bool, S_IRUGO);
152EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
153
6c86eedc
WL		 154static bool __read_mostly force_emulation_prefix = false;
155module_param(force_emulation_prefix, bool, S_IRUGO);
156
0c5f81da
WL		 157int __read_mostly pi_inject_timer = -1;
158module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
159
18863bdd
AK		 160#define KVM_NR_SHARED_MSRS 16
161
162struct kvm_shared_msrs_global {
163 int nr;
2bf78fa7 164 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 165};
166
167struct kvm_shared_msrs {
168 struct user_return_notifier urn;
169 bool registered;
2bf78fa7
SY		 170 struct kvm_shared_msr_values {
171 u64 host;
172 u64 curr;
173 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 174};
175
176static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 177static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 178
417bc304 179struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 180 { "pf_fixed", VCPU_STAT(pf_fixed) },
181 { "pf_guest", VCPU_STAT(pf_guest) },
182 { "tlb_flush", VCPU_STAT(tlb_flush) },
183 { "invlpg", VCPU_STAT(invlpg) },
184 { "exits", VCPU_STAT(exits) },
185 { "io_exits", VCPU_STAT(io_exits) },
186 { "mmio_exits", VCPU_STAT(mmio_exits) },
187 { "signal_exits", VCPU_STAT(signal_exits) },
188 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 189 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 190 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 191 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 192 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 193 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 194 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 195 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 196 { "request_irq", VCPU_STAT(request_irq_exits) },
197 { "irq_exits", VCPU_STAT(irq_exits) },
198 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 199 { "fpu_reload", VCPU_STAT(fpu_reload) },
200 { "insn_emulation", VCPU_STAT(insn_emulation) },
201 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 202 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 203 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 204 { "req_event", VCPU_STAT(req_event) },
c595ceee 205 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 206 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
207 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
208 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
209 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
210 { "mmu_flooded", VM_STAT(mmu_flooded) },
211 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 212 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 213 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 214 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 215 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 216 { "max_mmu_page_hash_collisions",
217 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 218 { NULL }
219};
220
2acf923e
DC		 221u64 __read_mostly host_xcr0;
222
b666a4b6
MO		 223struct kmem_cache *x86_fpu_cache;
224EXPORT_SYMBOL_GPL(x86_fpu_cache);
225
b6785def 226static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 227
af585b92
GN		 228static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
229{
230 int i;
231 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
232 vcpu->arch.apf.gfns[i] = ~0;
233}
234
18863bdd
AK		 235static void kvm_on_user_return(struct user_return_notifier *urn)
236{
237 unsigned slot;
18863bdd
AK		 238 struct kvm_shared_msrs *locals
239 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 240 struct kvm_shared_msr_values *values;
1650b4eb
IA		 241 unsigned long flags;
242
243 /*
244 * Disabling irqs at this point since the following code could be
245 * interrupted and executed through kvm_arch_hardware_disable()
246 */
247 local_irq_save(flags);
248 if (locals->registered) {
249 locals->registered = false;
250 user_return_notifier_unregister(urn);
251 }
252 local_irq_restore(flags);
18863bdd 253 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 254 values = &locals->values[slot];
255 if (values->host != values->curr) {
256 wrmsrl(shared_msrs_global.msrs[slot], values->host);
257 values->curr = values->host;
18863bdd
AK		 258 }
259 }
18863bdd
AK		 260}
261
2bf78fa7 262static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 263{
18863bdd 264 u64 value;
013f6a5d
MT		 265 unsigned int cpu = smp_processor_id();
266 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 267
2bf78fa7
SY		 268 /* only read, and nobody should modify it at this time,
269 * so don't need lock */
270 if (slot >= shared_msrs_global.nr) {
271 printk(KERN_ERR "kvm: invalid MSR slot!");
272 return;
273 }
274 rdmsrl_safe(msr, &value);
275 smsr->values[slot].host = value;
276 smsr->values[slot].curr = value;
277}
278
279void kvm_define_shared_msr(unsigned slot, u32 msr)
280{
0123be42 281 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 282 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 283 if (slot >= shared_msrs_global.nr)
284 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 285}
286EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
287
288static void kvm_shared_msr_cpu_online(void)
289{
290 unsigned i;
18863bdd
AK		 291
292 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 293 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 294}
295
8b3c3104 296int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 297{
013f6a5d
MT		 298 unsigned int cpu = smp_processor_id();
299 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 300 int err;
18863bdd 301
2bf78fa7 302 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 303 return 0;
2bf78fa7 304 smsr->values[slot].curr = value;
8b3c3104
AH		 305 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
306 if (err)
307 return 1;
308
18863bdd
AK		 309 if (!smsr->registered) {
310 smsr->urn.on_user_return = kvm_on_user_return;
311 user_return_notifier_register(&smsr->urn);
312 smsr->registered = true;
313 }
8b3c3104 314 return 0;
18863bdd
AK		 315}
316EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
317
13a34e06 318static void drop_user_return_notifiers(void)
3548bab5 319{
013f6a5d
MT		 320 unsigned int cpu = smp_processor_id();
321 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 322
323 if (smsr->registered)
324 kvm_on_user_return(&smsr->urn);
325}
326
6866b83e
CO		 327u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
328{
8a5a87d9 329 return vcpu->arch.apic_base;
6866b83e
CO		 330}
331EXPORT_SYMBOL_GPL(kvm_get_apic_base);
332
58871649
JM		 333enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
334{
335 return kvm_apic_mode(kvm_get_apic_base(vcpu));
336}
337EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
338
58cb628d
JK		 339int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
340{
58871649
JM		 341 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
342 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 343 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
344 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 345
58871649 346 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 347 return 1;
58871649
JM		 348 if (!msr_info->host_initiated) {
349 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
350 return 1;
351 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
352 return 1;
353 }
58cb628d
JK		 354
355 kvm_lapic_set_base(vcpu, msr_info->data);
356 return 0;
6866b83e
CO		 357}
358EXPORT_SYMBOL_GPL(kvm_set_apic_base);
359
2605fc21 360asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 361{
362 /* Fault while not rebooting. We want the trace. */
363 BUG();
364}
365EXPORT_SYMBOL_GPL(kvm_spurious_fault);
366
3fd28fce
ED		 367#define EXCPT_BENIGN 0
368#define EXCPT_CONTRIBUTORY 1
369#define EXCPT_PF 2
370
371static int exception_class(int vector)
372{
373 switch (vector) {
374 case PF_VECTOR:
375 return EXCPT_PF;
376 case DE_VECTOR:
377 case TS_VECTOR:
378 case NP_VECTOR:
379 case SS_VECTOR:
380 case GP_VECTOR:
381 return EXCPT_CONTRIBUTORY;
382 default:
383 break;
384 }
385 return EXCPT_BENIGN;
386}
387
d6e8c854
NA		 388#define EXCPT_FAULT 0
389#define EXCPT_TRAP 1
390#define EXCPT_ABORT 2
391#define EXCPT_INTERRUPT 3
392
393static int exception_type(int vector)
394{
395 unsigned int mask;
396
397 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
398 return EXCPT_INTERRUPT;
399
400 mask = 1 << vector;
401
402 /* #DB is trap, as instruction watchpoints are handled elsewhere */
403 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
404 return EXCPT_TRAP;
405
406 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
407 return EXCPT_ABORT;
408
409 /* Reserved exceptions will result in fault */
410 return EXCPT_FAULT;
411}
412
da998b46
JM		 413void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
414{
415 unsigned nr = vcpu->arch.exception.nr;
416 bool has_payload = vcpu->arch.exception.has_payload;
417 unsigned long payload = vcpu->arch.exception.payload;
418
419 if (!has_payload)
420 return;
421
422 switch (nr) {
f10c729f
JM		 423 case DB_VECTOR:
424 /*
425 * "Certain debug exceptions may clear bit 0-3. The
426 * remaining contents of the DR6 register are never
427 * cleared by the processor".
428 */
429 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
430 /*
431 * DR6.RTM is set by all #DB exceptions that don't clear it.
432 */
433 vcpu->arch.dr6 |= DR6_RTM;
434 vcpu->arch.dr6 |= payload;
435 /*
436 * Bit 16 should be set in the payload whenever the #DB
437 * exception should clear DR6.RTM. This makes the payload
438 * compatible with the pending debug exceptions under VMX.
439 * Though not currently documented in the SDM, this also
440 * makes the payload compatible with the exit qualification
441 * for #DB exceptions under VMX.
442 */
443 vcpu->arch.dr6 ^= payload & DR6_RTM;
444 break;
da998b46
JM		 445 case PF_VECTOR:
446 vcpu->arch.cr2 = payload;
447 break;
448 }
449
450 vcpu->arch.exception.has_payload = false;
451 vcpu->arch.exception.payload = 0;
452}
453EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
454
3fd28fce 455static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 456 unsigned nr, bool has_error, u32 error_code,
91e86d22 457 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 458{
459 u32 prev_nr;
460 int class1, class2;
461
3842d135
AK		 462 kvm_make_request(KVM_REQ_EVENT, vcpu);
463
664f8e26 464 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 465 queue:
3ffb2468
NA		 466 if (has_error && !is_protmode(vcpu))
467 has_error = false;
664f8e26
WL		 468 if (reinject) {
469 /*
470 * On vmentry, vcpu->arch.exception.pending is only
471 * true if an event injection was blocked by
472 * nested_run_pending. In that case, however,
473 * vcpu_enter_guest requests an immediate exit,
474 * and the guest shouldn't proceed far enough to
475 * need reinjection.
476 */
477 WARN_ON_ONCE(vcpu->arch.exception.pending);
478 vcpu->arch.exception.injected = true;
91e86d22
JM		 479 if (WARN_ON_ONCE(has_payload)) {
480 /*
481 * A reinjected event has already
482 * delivered its payload.
483 */
484 has_payload = false;
485 payload = 0;
486 }
664f8e26
WL		 487 } else {
488 vcpu->arch.exception.pending = true;
489 vcpu->arch.exception.injected = false;
490 }
3fd28fce
ED		 491 vcpu->arch.exception.has_error_code = has_error;
492 vcpu->arch.exception.nr = nr;
493 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 494 vcpu->arch.exception.has_payload = has_payload;
495 vcpu->arch.exception.payload = payload;
da998b46
JM		 496 /*
497 * In guest mode, payload delivery should be deferred,
498 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 499 * CR2 is modified (or intercept #DB before DR6 is
500 * modified under nVMX). However, for ABI
501 * compatibility with KVM_GET_VCPU_EVENTS and
502 * KVM_SET_VCPU_EVENTS, we can't delay payload
503 * delivery unless userspace has enabled this
504 * functionality via the per-VM capability,
505 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 506 */
507 if (!vcpu->kvm->arch.exception_payload_enabled ||
508 !is_guest_mode(vcpu))
509 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 510 return;
511 }
512
513 /* to check exception */
514 prev_nr = vcpu->arch.exception.nr;
515 if (prev_nr == DF_VECTOR) {
516 /* triple fault -> shutdown */
a8eeb04a 517 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 518 return;
519 }
520 class1 = exception_class(prev_nr);
521 class2 = exception_class(nr);
522 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
523 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 524 /*
525 * Generate double fault per SDM Table 5-5. Set
526 * exception.pending = true so that the double fault
527 * can trigger a nested vmexit.
528 */
3fd28fce 529 vcpu->arch.exception.pending = true;
664f8e26 530 vcpu->arch.exception.injected = false;
3fd28fce
ED		 531 vcpu->arch.exception.has_error_code = true;
532 vcpu->arch.exception.nr = DF_VECTOR;
533 vcpu->arch.exception.error_code = 0;
c851436a
JM		 534 vcpu->arch.exception.has_payload = false;
535 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 536 } else
537 /* replace previous exception with a new one in a hope
538 that instruction re-execution will regenerate lost
539 exception */
540 goto queue;
541}
542
298101da
AK		 543void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
544{
91e86d22 545 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 546}
547EXPORT_SYMBOL_GPL(kvm_queue_exception);
548
ce7ddec4
JR		 549void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
550{
91e86d22 551 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 552}
553EXPORT_SYMBOL_GPL(kvm_requeue_exception);
554
f10c729f
JM		 555static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
556 unsigned long payload)
557{
558 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
559}
560
da998b46
JM		 561static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
562 u32 error_code, unsigned long payload)
563{
564 kvm_multiple_exception(vcpu, nr, true, error_code,
565 true, payload, false);
566}
567
6affcbed 568int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 569{
db8fcefa
AP		 570 if (err)
571 kvm_inject_gp(vcpu, 0);
572 else
6affcbed
KH		 573 return kvm_skip_emulated_instruction(vcpu);
574
575 return 1;
db8fcefa
AP		 576}
577EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 578
6389ee94 579void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 580{
581 ++vcpu->stat.pf_guest;
adfe20fb
WL		 582 vcpu->arch.exception.nested_apf =
583 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 584 if (vcpu->arch.exception.nested_apf) {
adfe20fb 585 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 586 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
587 } else {
588 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
589 fault->address);
590 }
c3c91fee 591}
27d6c865 592EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 593
ef54bcfe 594static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 595{
6389ee94
AK		 596 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
597 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 598 else
44dd3ffa 599 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 600
601 return fault->nested_page_fault;
d4f8cf66
JR		 602}
603
3419ffc8
SY		 604void kvm_inject_nmi(struct kvm_vcpu *vcpu)
605{
7460fb4a
AK		 606 atomic_inc(&vcpu->arch.nmi_queued);
607 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 608}
609EXPORT_SYMBOL_GPL(kvm_inject_nmi);
610
298101da
AK		 611void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
612{
91e86d22 613 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 614}
615EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
616
ce7ddec4
JR		 617void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
618{
91e86d22 619 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 620}
621EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
622
0a79b009
AK		 623/*
624 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
625 * a #GP and return false.
626 */
627bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 628{
0a79b009
AK		 629 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
630 return true;
631 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
632 return false;
298101da 633}
0a79b009 634EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 635
16f8a6f9
NA		 636bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
637{
638 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
639 return true;
640
641 kvm_queue_exception(vcpu, UD_VECTOR);
642 return false;
643}
644EXPORT_SYMBOL_GPL(kvm_require_dr);
645
ec92fe44
JR		 646/*
647 * This function will be used to read from the physical memory of the currently
54bf36aa 648 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 649 * can read from guest physical or from the guest's guest physical memory.
650 */
651int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
652 gfn_t ngfn, void *data, int offset, int len,
653 u32 access)
654{
54987b7a 655 struct x86_exception exception;
ec92fe44
JR		 656 gfn_t real_gfn;
657 gpa_t ngpa;
658
659 ngpa = gfn_to_gpa(ngfn);
54987b7a 660 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 661 if (real_gfn == UNMAPPED_GVA)
662 return -EFAULT;
663
664 real_gfn = gpa_to_gfn(real_gfn);
665
54bf36aa 666 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 667}
668EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
669
69b0049a 670static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 671 void *data, int offset, int len, u32 access)
672{
673 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
674 data, offset, len, access);
675}
676
16cfacc8
SC		 677static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
678{
679 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
680 rsvd_bits(1, 2);
681}
682
a03490ed 683/*
16cfacc8 684 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
a03490ed 685 */
ff03a073 686int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 687{
688 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
689 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
690 int i;
691 int ret;
ff03a073 692 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 693
ff03a073
JR		 694 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
695 offset * sizeof(u64), sizeof(pdpte),
696 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 697 if (ret < 0) {
698 ret = 0;
699 goto out;
700 }
701 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 702 if ((pdpte[i] & PT_PRESENT_MASK) &&
16cfacc8 703 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
a03490ed
CO		 704 ret = 0;
705 goto out;
706 }
707 }
708 ret = 1;
709
ff03a073 710 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 711 __set_bit(VCPU_EXREG_PDPTR,
712 (unsigned long *)&vcpu->arch.regs_avail);
713 __set_bit(VCPU_EXREG_PDPTR,
714 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 715out:
a03490ed
CO		 716
717 return ret;
718}
cc4b6871 719EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 720
9ed38ffa 721bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 722{
ff03a073 723 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 724 bool changed = true;
3d06b8bf
JR		 725 int offset;
726 gfn_t gfn;
d835dfec
AK		 727 int r;
728
bf03d4f9 729 if (!is_pae_paging(vcpu))
d835dfec
AK		 730 return false;
731
6de4f3ad
AK		 732 if (!test_bit(VCPU_EXREG_PDPTR,
733 (unsigned long *)&vcpu->arch.regs_avail))
734 return true;
735
a512177e
PB		 736 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
737 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 738 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
739 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 740 if (r < 0)
741 goto out;
ff03a073 742 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 743out:
d835dfec
AK		 744
745 return changed;
746}
9ed38ffa 747EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 748
49a9b07e 749int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 750{
aad82703 751 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 752 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 753
f9a48e6a
AK		 754 cr0 |= X86_CR0_ET;
755
ab344828 756#ifdef CONFIG_X86_64
0f12244f
GN		 757 if (cr0 & 0xffffffff00000000UL)
758 return 1;
ab344828
GN		 759#endif
760
761 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 762
0f12244f
GN		 763 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
764 return 1;
a03490ed 765
0f12244f
GN		 766 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
767 return 1;
a03490ed
CO		 768
769 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
770#ifdef CONFIG_X86_64
f6801dff 771 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 772 int cs_db, cs_l;
773
0f12244f
GN		 774 if (!is_pae(vcpu))
775 return 1;
a03490ed 776 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 777 if (cs_l)
778 return 1;
a03490ed
CO		 779 } else
780#endif
ff03a073 781 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 782 kvm_read_cr3(vcpu)))
0f12244f 783 return 1;
a03490ed
CO		 784 }
785
ad756a16
MJ		 786 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
787 return 1;
788
a03490ed 789 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 790
d170c419 791 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 792 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 793 kvm_async_pf_hash_reset(vcpu);
794 }
e5f3f027 795
aad82703
SY		 796 if ((cr0 ^ old_cr0) & update_bits)
797 kvm_mmu_reset_context(vcpu);
b18d5431 798
879ae188
LE		 799 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
800 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
801 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 802 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
803
0f12244f
GN		 804 return 0;
805}
2d3ad1f4 806EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 807
2d3ad1f4 808void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 809{
49a9b07e 810 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 811}
2d3ad1f4 812EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 813
1811d979 814void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 815{
816 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
817 !vcpu->guest_xcr0_loaded) {
818 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 819 if (vcpu->arch.xcr0 != host_xcr0)
820 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 821 vcpu->guest_xcr0_loaded = 1;
822 }
823}
1811d979 824EXPORT_SYMBOL_GPL(kvm_load_guest_xcr0);
42bdf991 825
1811d979 826void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
42bdf991
MT		 827{
828 if (vcpu->guest_xcr0_loaded) {
829 if (vcpu->arch.xcr0 != host_xcr0)
830 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
831 vcpu->guest_xcr0_loaded = 0;
832 }
833}
1811d979 834EXPORT_SYMBOL_GPL(kvm_put_guest_xcr0);
42bdf991 835
69b0049a 836static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 837{
56c103ec
LJ		 838 u64 xcr0 = xcr;
839 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 840 u64 valid_bits;
2acf923e
DC		 841
842 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
843 if (index != XCR_XFEATURE_ENABLED_MASK)
844 return 1;
d91cab78 845 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 846 return 1;
d91cab78 847 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 848 return 1;
46c34cb0
PB		 849
850 /*
851 * Do not allow the guest to set bits that we do not support
852 * saving. However, xcr0 bit 0 is always set, even if the
853 * emulated CPU does not support XSAVE (see fx_init).
854 */
d91cab78 855 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 856 if (xcr0 & ~valid_bits)
2acf923e 857 return 1;
46c34cb0 858
d91cab78
DH		 859 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
860 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 861 return 1;
862
d91cab78
DH		 863 if (xcr0 & XFEATURE_MASK_AVX512) {
864 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 865 return 1;
d91cab78 866 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 867 return 1;
868 }
2acf923e 869 vcpu->arch.xcr0 = xcr0;
56c103ec 870
d91cab78 871 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 872 kvm_update_cpuid(vcpu);
2acf923e
DC		 873 return 0;
874}
875
876int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
877{
764bcbc5
Z		 878 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
879 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 880 kvm_inject_gp(vcpu, 0);
881 return 1;
882 }
883 return 0;
884}
885EXPORT_SYMBOL_GPL(kvm_set_xcr);
886
a83b29c6 887int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 888{
fc78f519 889 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 890 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 891 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 892
0f12244f
GN		 893 if (cr4 & CR4_RESERVED_BITS)
894 return 1;
a03490ed 895
d6321d49 896 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 897 return 1;
898
d6321d49 899 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 900 return 1;
901
d6321d49 902 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 903 return 1;
904
d6321d49 905 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 906 return 1;
907
d6321d49 908 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 909 return 1;
910
fd8cb433 911 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 912 return 1;
913
ae3e61e1
PB		 914 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
915 return 1;
916
a03490ed 917 if (is_long_mode(vcpu)) {
0f12244f
GN		 918 if (!(cr4 & X86_CR4_PAE))
919 return 1;
a2edf57f
AK		 920 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
921 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 922 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
923 kvm_read_cr3(vcpu)))
0f12244f
GN		 924 return 1;
925
ad756a16 926 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 927 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 928 return 1;
929
930 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
931 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
932 return 1;
933 }
934
5e1746d6 935 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 936 return 1;
a03490ed 937
ad756a16
MJ		 938 if (((cr4 ^ old_cr4) & pdptr_bits) ||
939 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 940 kvm_mmu_reset_context(vcpu);
0f12244f 941
b9baba86 942 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 943 kvm_update_cpuid(vcpu);
2acf923e 944
0f12244f
GN		 945 return 0;
946}
2d3ad1f4 947EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 948
2390218b 949int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 950{
ade61e28 951 bool skip_tlb_flush = false;
ac146235 952#ifdef CONFIG_X86_64
c19986fe
JS		 953 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
954
ade61e28 955 if (pcid_enabled) {
208320ba
JS		 956 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
957 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 958 }
ac146235 959#endif
9d88fca7 960
9f8fe504 961 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 962 if (!skip_tlb_flush) {
963 kvm_mmu_sync_roots(vcpu);
ade61e28 964 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 965 }
0f12244f 966 return 0;
d835dfec
AK		 967 }
968
d1cd3ce9 969 if (is_long_mode(vcpu) &&
a780a3ea 970 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9 971 return 1;
bf03d4f9
PB		 972 else if (is_pae_paging(vcpu) &&
973 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 974 return 1;
a03490ed 975
ade61e28 976 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 977 vcpu->arch.cr3 = cr3;
aff48baa 978 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 979
0f12244f
GN		 980 return 0;
981}
2d3ad1f4 982EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 983
eea1cff9 984int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 985{
0f12244f
GN		 986 if (cr8 & CR8_RESERVED_BITS)
987 return 1;
35754c98 988 if (lapic_in_kernel(vcpu))
a03490ed
CO		 989 kvm_lapic_set_tpr(vcpu, cr8);
990 else
ad312c7c 991 vcpu->arch.cr8 = cr8;
0f12244f
GN		 992 return 0;
993}
2d3ad1f4 994EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 995
2d3ad1f4 996unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 997{
35754c98 998 if (lapic_in_kernel(vcpu))
a03490ed
CO		 999 return kvm_lapic_get_cr8(vcpu);
1000 else
ad312c7c 1001 return vcpu->arch.cr8;
a03490ed 1002}
2d3ad1f4 1003EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 1004
ae561ede
NA		 1005static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1006{
1007 int i;
1008
1009 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1010 for (i = 0; i < KVM_NR_DB_REGS; i++)
1011 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1012 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1013 }
1014}
1015
73aaf249
JK		 1016static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1017{
1018 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1019 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1020}
1021
c8639010
JK		 1022static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1023{
1024 unsigned long dr7;
1025
1026 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1027 dr7 = vcpu->arch.guest_debug_dr7;
1028 else
1029 dr7 = vcpu->arch.dr7;
1030 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1031 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1032 if (dr7 & DR7_BP_EN_MASK)
1033 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1034}
1035
6f43ed01
NA		 1036static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1037{
1038 u64 fixed = DR6_FIXED_1;
1039
d6321d49 1040 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1041 fixed |= DR6_RTM;
1042 return fixed;
1043}
1044
338dbc97 1045static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 1046{
1047 switch (dr) {
1048 case 0 ... 3:
1049 vcpu->arch.db[dr] = val;
1050 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1051 vcpu->arch.eff_db[dr] = val;
1052 break;
1053 case 4:
020df079
GN		 1054 /* fall through */
1055 case 6:
338dbc97
GN		 1056 if (val & 0xffffffff00000000ULL)
1057 return -1; /* #GP */
6f43ed01 1058 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1059 kvm_update_dr6(vcpu);
020df079
GN		 1060 break;
1061 case 5:
020df079
GN		 1062 /* fall through */
1063 default: /* 7 */
338dbc97
GN		 1064 if (val & 0xffffffff00000000ULL)
1065 return -1; /* #GP */
020df079 1066 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1067 kvm_update_dr7(vcpu);
020df079
GN		 1068 break;
1069 }
1070
1071 return 0;
1072}
338dbc97
GN		 1073
1074int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1075{
16f8a6f9 1076 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1077 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1078 return 1;
1079 }
1080 return 0;
338dbc97 1081}
020df079
GN		 1082EXPORT_SYMBOL_GPL(kvm_set_dr);
1083
16f8a6f9 1084int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 1085{
1086 switch (dr) {
1087 case 0 ... 3:
1088 *val = vcpu->arch.db[dr];
1089 break;
1090 case 4:
020df079
GN		 1091 /* fall through */
1092 case 6:
73aaf249
JK		 1093 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1094 *val = vcpu->arch.dr6;
1095 else
1096 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1097 break;
1098 case 5:
020df079
GN		 1099 /* fall through */
1100 default: /* 7 */
1101 *val = vcpu->arch.dr7;
1102 break;
1103 }
338dbc97
GN		 1104 return 0;
1105}
020df079
GN		 1106EXPORT_SYMBOL_GPL(kvm_get_dr);
1107
022cd0e8
AK		 1108bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1109{
de3cd117 1110 u32 ecx = kvm_rcx_read(vcpu);
022cd0e8
AK		 1111 u64 data;
1112 int err;
1113
c6702c9d 1114 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1115 if (err)
1116 return err;
de3cd117
SC		 1117 kvm_rax_write(vcpu, (u32)data);
1118 kvm_rdx_write(vcpu, data >> 32);
022cd0e8
AK		 1119 return err;
1120}
1121EXPORT_SYMBOL_GPL(kvm_rdpmc);
1122
043405e1
CO		 1123/*
1124 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1125 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1126 *
1127 * This list is modified at module load time to reflect the
e3267cbb 1128 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1129 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1130 * may depend on host virtualization features rather than host cpu features.
043405e1 1131 */
e3267cbb 1132
043405e1
CO		 1133static u32 msrs_to_save[] = {
1134 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1135 MSR_STAR,
043405e1
CO		 1136#ifdef CONFIG_X86_64
1137 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1138#endif
b3897a49 1139 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1140 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
2bdb76c0 1141 MSR_IA32_SPEC_CTRL,
bf8c55d8
CP		 1142 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1143 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1144 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1145 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1146 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1147 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
6e3ba4ab
TX		 1148 MSR_IA32_UMWAIT_CONTROL,
1149
e2ada66e
JM		 1150 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1151 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1152 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1153 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1154 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1155 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1156 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1157 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1158 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1159 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1160 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1161 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1162 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
1163 MSR_ARCH_PERFMON_PERFCTR0 + 18, MSR_ARCH_PERFMON_PERFCTR0 + 19,
1164 MSR_ARCH_PERFMON_PERFCTR0 + 20, MSR_ARCH_PERFMON_PERFCTR0 + 21,
1165 MSR_ARCH_PERFMON_PERFCTR0 + 22, MSR_ARCH_PERFMON_PERFCTR0 + 23,
1166 MSR_ARCH_PERFMON_PERFCTR0 + 24, MSR_ARCH_PERFMON_PERFCTR0 + 25,
1167 MSR_ARCH_PERFMON_PERFCTR0 + 26, MSR_ARCH_PERFMON_PERFCTR0 + 27,
1168 MSR_ARCH_PERFMON_PERFCTR0 + 28, MSR_ARCH_PERFMON_PERFCTR0 + 29,
1169 MSR_ARCH_PERFMON_PERFCTR0 + 30, MSR_ARCH_PERFMON_PERFCTR0 + 31,
1170 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1171 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1172 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1173 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1174 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1175 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1176 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1177 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1178 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
1179 MSR_ARCH_PERFMON_EVENTSEL0 + 18, MSR_ARCH_PERFMON_EVENTSEL0 + 19,
1180 MSR_ARCH_PERFMON_EVENTSEL0 + 20, MSR_ARCH_PERFMON_EVENTSEL0 + 21,
1181 MSR_ARCH_PERFMON_EVENTSEL0 + 22, MSR_ARCH_PERFMON_EVENTSEL0 + 23,
1182 MSR_ARCH_PERFMON_EVENTSEL0 + 24, MSR_ARCH_PERFMON_EVENTSEL0 + 25,
1183 MSR_ARCH_PERFMON_EVENTSEL0 + 26, MSR_ARCH_PERFMON_EVENTSEL0 + 27,
1184 MSR_ARCH_PERFMON_EVENTSEL0 + 28, MSR_ARCH_PERFMON_EVENTSEL0 + 29,
1185 MSR_ARCH_PERFMON_EVENTSEL0 + 30, MSR_ARCH_PERFMON_EVENTSEL0 + 31,
043405e1
CO		 1186};
1187
1188static unsigned num_msrs_to_save;
1189
62ef68bb
PB		 1190static u32 emulated_msrs[] = {
1191 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1192 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1193 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1194 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1195 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1196 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1197 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1198 HV_X64_MSR_RESET,
11c4b1ca 1199 HV_X64_MSR_VP_INDEX,
9eec50b8 1200 HV_X64_MSR_VP_RUNTIME,
5c919412 1201 HV_X64_MSR_SCONTROL,
1f4b34f8 1202 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1203 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1204 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1205 HV_X64_MSR_TSC_EMULATION_STATUS,
1206
1207 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1208 MSR_KVM_PV_EOI_EN,
1209
ba904635 1210 MSR_IA32_TSC_ADJUST,
a3e06bbe 1211 MSR_IA32_TSCDEADLINE,
2bdb76c0 1212 MSR_IA32_ARCH_CAPABILITIES,
043405e1 1213 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1214 MSR_IA32_MCG_STATUS,
1215 MSR_IA32_MCG_CTL,
c45dcc71 1216 MSR_IA32_MCG_EXT_CTL,
64d60670 1217 MSR_IA32_SMBASE,
52797bf9 1218 MSR_SMI_COUNT,
db2336a8
KH		 1219 MSR_PLATFORM_INFO,
1220 MSR_MISC_FEATURES_ENABLES,
bc226f07 1221 MSR_AMD64_VIRT_SPEC_CTRL,
6c6a2ab9 1222 MSR_IA32_POWER_CTL,
191c8137 1223
95c5c7c7
PB		 1224 /*
1225 * The following list leaves out MSRs whose values are determined
1226 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1227 * We always support the "true" VMX control MSRs, even if the host
1228 * processor does not, so I am putting these registers here rather
1229 * than in msrs_to_save.
1230 */
1231 MSR_IA32_VMX_BASIC,
1232 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1233 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1234 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1235 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1236 MSR_IA32_VMX_MISC,
1237 MSR_IA32_VMX_CR0_FIXED0,
1238 MSR_IA32_VMX_CR4_FIXED0,
1239 MSR_IA32_VMX_VMCS_ENUM,
1240 MSR_IA32_VMX_PROCBASED_CTLS2,
1241 MSR_IA32_VMX_EPT_VPID_CAP,
1242 MSR_IA32_VMX_VMFUNC,
1243
191c8137 1244 MSR_K7_HWCR,
2d5ba19b 1245 MSR_KVM_POLL_CONTROL,
043405e1
CO		 1246};
1247
62ef68bb
PB		 1248static unsigned num_emulated_msrs;
1249
801e459a
TL		 1250/*
1251 * List of msr numbers which are used to expose MSR-based features that
1252 * can be used by a hypervisor to validate requested CPU features.
1253 */
1254static u32 msr_based_features[] = {
1389309c
PB		 1255 MSR_IA32_VMX_BASIC,
1256 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1257 MSR_IA32_VMX_PINBASED_CTLS,
1258 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1259 MSR_IA32_VMX_PROCBASED_CTLS,
1260 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1261 MSR_IA32_VMX_EXIT_CTLS,
1262 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1263 MSR_IA32_VMX_ENTRY_CTLS,
1264 MSR_IA32_VMX_MISC,
1265 MSR_IA32_VMX_CR0_FIXED0,
1266 MSR_IA32_VMX_CR0_FIXED1,
1267 MSR_IA32_VMX_CR4_FIXED0,
1268 MSR_IA32_VMX_CR4_FIXED1,
1269 MSR_IA32_VMX_VMCS_ENUM,
1270 MSR_IA32_VMX_PROCBASED_CTLS2,
1271 MSR_IA32_VMX_EPT_VPID_CAP,
1272 MSR_IA32_VMX_VMFUNC,
1273
d1d93fa9 1274 MSR_F10H_DECFG,
518e7b94 1275 MSR_IA32_UCODE_REV,
cd283252 1276 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1277};
1278
1279static unsigned int num_msr_based_features;
1280
4d22c17c 1281static u64 kvm_get_arch_capabilities(void)
5b76a3cf 1282{
4d22c17c 1283 u64 data = 0;
5b76a3cf 1284
4d22c17c
XL		 1285 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1286 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
5b76a3cf
PB		 1287
1288 /*
1289 * If we're doing cache flushes (either "always" or "cond")
1290 * we will do one whenever the guest does a vmlaunch/vmresume.
1291 * If an outer hypervisor is doing the cache flush for us
1292 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1293 * capability to the guest too, and if EPT is disabled we're not
1294 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1295 * require a nested hypervisor to do a flush of its own.
1296 */
1297 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1298 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1299
0c54914d
PB		 1300 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1301 data |= ARCH_CAP_RDCL_NO;
1302 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1303 data |= ARCH_CAP_SSB_NO;
1304 if (!boot_cpu_has_bug(X86_BUG_MDS))
1305 data |= ARCH_CAP_MDS_NO;
1306
5b76a3cf
PB		 1307 return data;
1308}
5b76a3cf 1309
66421c1e
WL		 1310static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1311{
1312 switch (msr->index) {
cd283252 1313 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1314 msr->data = kvm_get_arch_capabilities();
1315 break;
1316 case MSR_IA32_UCODE_REV:
cd283252 1317 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1318 break;
66421c1e
WL		 1319 default:
1320 if (kvm_x86_ops->get_msr_feature(msr))
1321 return 1;
1322 }
1323 return 0;
1324}
1325
801e459a
TL		 1326static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1327{
1328 struct kvm_msr_entry msr;
66421c1e 1329 int r;
801e459a
TL		 1330
1331 msr.index = index;
66421c1e
WL		 1332 r = kvm_get_msr_feature(&msr);
1333 if (r)
1334 return r;
801e459a
TL		 1335
1336 *data = msr.data;
1337
1338 return 0;
1339}
1340
11988499 1341static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1342{
1b4d56b8 1343 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
11988499 1344 return false;
1b2fd70c 1345
1b4d56b8 1346 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
11988499 1347 return false;
d8017474 1348
0a629563
SC		 1349 if (efer & (EFER_LME | EFER_LMA) &&
1350 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1351 return false;
1352
1353 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1354 return false;
d8017474 1355
384bb783 1356 return true;
11988499
SC		 1357
1358}
1359bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1360{
1361 if (efer & efer_reserved_bits)
1362 return false;
1363
1364 return __kvm_valid_efer(vcpu, efer);
384bb783
JK		 1365}
1366EXPORT_SYMBOL_GPL(kvm_valid_efer);
1367
11988499 1368static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
384bb783
JK		 1369{
1370 u64 old_efer = vcpu->arch.efer;
11988499 1371 u64 efer = msr_info->data;
384bb783 1372
11988499 1373 if (efer & efer_reserved_bits)
66f61c92 1374 return 1;
384bb783 1375
11988499
SC		 1376 if (!msr_info->host_initiated) {
1377 if (!__kvm_valid_efer(vcpu, efer))
1378 return 1;
1379
1380 if (is_paging(vcpu) &&
1381 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1382 return 1;
1383 }
384bb783 1384
15c4a640 1385 efer &= ~EFER_LMA;
f6801dff 1386 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1387
a3d204e2
SY		 1388 kvm_x86_ops->set_efer(vcpu, efer);
1389
aad82703
SY		 1390 /* Update reserved bits */
1391 if ((efer ^ old_efer) & EFER_NX)
1392 kvm_mmu_reset_context(vcpu);
1393
b69e8cae 1394 return 0;
15c4a640
CO		 1395}
1396
f2b4b7dd
JR		 1397void kvm_enable_efer_bits(u64 mask)
1398{
1399 efer_reserved_bits &= ~mask;
1400}
1401EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1402
15c4a640 1403/*
f20935d8
SC		 1404 * Write @data into the MSR specified by @index. Select MSR specific fault
1405 * checks are bypassed if @host_initiated is %true.
15c4a640
CO		 1406 * Returns 0 on success, non-0 otherwise.
1407 * Assumes vcpu_load() was already called.
1408 */
f20935d8
SC		 1409static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1410 bool host_initiated)
15c4a640 1411{
f20935d8
SC		 1412 struct msr_data msr;
1413
1414 switch (index) {
854e8bb1
NA		 1415 case MSR_FS_BASE:
1416 case MSR_GS_BASE:
1417 case MSR_KERNEL_GS_BASE:
1418 case MSR_CSTAR:
1419 case MSR_LSTAR:
f20935d8 1420 if (is_noncanonical_address(data, vcpu))
854e8bb1
NA		 1421 return 1;
1422 break;
1423 case MSR_IA32_SYSENTER_EIP:
1424 case MSR_IA32_SYSENTER_ESP:
1425 /*
1426 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1427 * non-canonical address is written on Intel but not on
1428 * AMD (which ignores the top 32-bits, because it does
1429 * not implement 64-bit SYSENTER).
1430 *
1431 * 64-bit code should hence be able to write a non-canonical
1432 * value on AMD. Making the address canonical ensures that
1433 * vmentry does not fail on Intel after writing a non-canonical
1434 * value, and that something deterministic happens if the guest
1435 * invokes 64-bit SYSENTER.
1436 */
f20935d8 1437 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1438 }
f20935d8
SC		 1439
1440 msr.data = data;
1441 msr.index = index;
1442 msr.host_initiated = host_initiated;
1443
1444 return kvm_x86_ops->set_msr(vcpu, &msr);
15c4a640
CO		 1445}
1446
313a3dc7 1447/*
f20935d8
SC		 1448 * Read the MSR specified by @index into @data. Select MSR specific fault
1449 * checks are bypassed if @host_initiated is %true.
1450 * Returns 0 on success, non-0 otherwise.
1451 * Assumes vcpu_load() was already called.
313a3dc7 1452 */
f20935d8
SC		 1453static int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1454 bool host_initiated)
609e36d3
PB		 1455{
1456 struct msr_data msr;
f20935d8 1457 int ret;
609e36d3
PB		 1458
1459 msr.index = index;
f20935d8 1460 msr.host_initiated = host_initiated;
609e36d3 1461
f20935d8
SC		 1462 ret = kvm_x86_ops->get_msr(vcpu, &msr);
1463 if (!ret)
1464 *data = msr.data;
1465 return ret;
609e36d3
PB		 1466}
1467
f20935d8 1468int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
313a3dc7 1469{
f20935d8
SC		 1470 return __kvm_get_msr(vcpu, index, data, false);
1471}
1472EXPORT_SYMBOL_GPL(kvm_get_msr);
8fe8ab46 1473
f20935d8
SC		 1474int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1475{
1476 return __kvm_set_msr(vcpu, index, data, false);
1477}
1478EXPORT_SYMBOL_GPL(kvm_set_msr);
1479
1edce0a9
SC		 1480int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1481{
1482 u32 ecx = kvm_rcx_read(vcpu);
1483 u64 data;
1484
1485 if (kvm_get_msr(vcpu, ecx, &data)) {
1486 trace_kvm_msr_read_ex(ecx);
1487 kvm_inject_gp(vcpu, 0);
1488 return 1;
1489 }
1490
1491 trace_kvm_msr_read(ecx, data);
1492
1493 kvm_rax_write(vcpu, data & -1u);
1494 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1495 return kvm_skip_emulated_instruction(vcpu);
1496}
1497EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1498
1499int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1500{
1501 u32 ecx = kvm_rcx_read(vcpu);
1502 u64 data = kvm_read_edx_eax(vcpu);
1503
1504 if (kvm_set_msr(vcpu, ecx, data)) {
1505 trace_kvm_msr_write_ex(ecx, data);
1506 kvm_inject_gp(vcpu, 0);
1507 return 1;
1508 }
1509
1510 trace_kvm_msr_write(ecx, data);
1511 return kvm_skip_emulated_instruction(vcpu);
1512}
1513EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1514
f20935d8
SC		 1515/*
1516 * Adapt set_msr() to msr_io()'s calling convention
1517 */
1518static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1519{
1520 return __kvm_get_msr(vcpu, index, data, true);
1521}
1522
1523static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1524{
1525 return __kvm_set_msr(vcpu, index, *data, true);
313a3dc7
CO		 1526}
1527
16e8d74d
MT		 1528#ifdef CONFIG_X86_64
1529struct pvclock_gtod_data {
1530 seqcount_t seq;
1531
1532 struct { /* extract of a clocksource struct */
1533 int vclock_mode;
a5a1d1c2
TG		 1534 u64 cycle_last;
1535 u64 mask;
16e8d74d
MT		 1536 u32 mult;
1537 u32 shift;
1538 } clock;
1539
cbcf2dd3
TG		 1540 u64 boot_ns;
1541 u64 nsec_base;
55dd00a7 1542 u64 wall_time_sec;
16e8d74d
MT		 1543};
1544
1545static struct pvclock_gtod_data pvclock_gtod_data;
1546
1547static void update_pvclock_gtod(struct timekeeper *tk)
1548{
1549 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1550 u64 boot_ns;
1551
876e7881 1552 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1553
1554 write_seqcount_begin(&vdata->seq);
1555
1556 /* copy pvclock gtod data */
876e7881
PZ		 1557 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1558 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1559 vdata->clock.mask = tk->tkr_mono.mask;
1560 vdata->clock.mult = tk->tkr_mono.mult;
1561 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1562
cbcf2dd3 1563 vdata->boot_ns = boot_ns;
876e7881 1564 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1565
55dd00a7
MT		 1566 vdata->wall_time_sec = tk->xtime_sec;
1567
16e8d74d
MT		 1568 write_seqcount_end(&vdata->seq);
1569}
1570#endif
1571
bab5bb39
NK		 1572void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1573{
bab5bb39 1574 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
4d151bf3 1575 kvm_vcpu_kick(vcpu);
bab5bb39 1576}
16e8d74d 1577
18068523
GOC		 1578static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1579{
9ed3c444
AK		 1580 int version;
1581 int r;
50d0a0f9 1582 struct pvclock_wall_clock wc;
87aeb54f 1583 struct timespec64 boot;
18068523
GOC		 1584
1585 if (!wall_clock)
1586 return;
1587
9ed3c444
AK		 1588 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1589 if (r)
1590 return;
1591
1592 if (version & 1)
1593 ++version; /* first time write, random junk */
1594
1595 ++version;
18068523 1596
1dab1345
NK		 1597 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1598 return;
18068523 1599
50d0a0f9
GH		 1600 /*
1601 * The guest calculates current wall clock time by adding
34c238a1 1602 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1603 * wall clock specified here. guest system time equals host
1604 * system time for us, thus we must fill in host boot time here.
1605 */
87aeb54f 1606 getboottime64(&boot);
50d0a0f9 1607
4b648665 1608 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1609 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1610 boot = timespec64_sub(boot, ts);
4b648665 1611 }
87aeb54f 1612 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1613 wc.nsec = boot.tv_nsec;
1614 wc.version = version;
18068523
GOC		 1615
1616 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1617
1618 version++;
1619 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1620}
1621
50d0a0f9
GH		 1622static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1623{
b51012de
PB		 1624 do_shl32_div32(dividend, divisor);
1625 return dividend;
50d0a0f9
GH		 1626}
1627
3ae13faa 1628static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1629 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1630{
5f4e3f88 1631 uint64_t scaled64;
50d0a0f9
GH		 1632 int32_t shift = 0;
1633 uint64_t tps64;
1634 uint32_t tps32;
1635
3ae13faa
PB		 1636 tps64 = base_hz;
1637 scaled64 = scaled_hz;
50933623 1638 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1639 tps64 >>= 1;
1640 shift--;
1641 }
1642
1643 tps32 = (uint32_t)tps64;
50933623
JK		 1644 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1645 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1646 scaled64 >>= 1;
1647 else
1648 tps32 <<= 1;
50d0a0f9
GH		 1649 shift++;
1650 }
1651
5f4e3f88
ZA		 1652 *pshift = shift;
1653 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9
GH		 1654}
1655
d828199e 1656#ifdef CONFIG_X86_64
16e8d74d 1657static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1658#endif
16e8d74d 1659
c8076604 1660static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1661static unsigned long max_tsc_khz;
c8076604 1662
cc578287 1663static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1664{
cc578287
ZA		 1665 u64 v = (u64)khz * (1000000 + ppm);
1666 do_div(v, 1000000);
1667 return v;
1e993611
JR		 1668}
1669
381d585c
HZ		 1670static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1671{
1672 u64 ratio;
1673
1674 /* Guest TSC same frequency as host TSC? */
1675 if (!scale) {
1676 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1677 return 0;
1678 }
1679
1680 /* TSC scaling supported? */
1681 if (!kvm_has_tsc_control) {
1682 if (user_tsc_khz > tsc_khz) {
1683 vcpu->arch.tsc_catchup = 1;
1684 vcpu->arch.tsc_always_catchup = 1;
1685 return 0;
1686 } else {
3f16a5c3 1687 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
381d585c
HZ		 1688 return -1;
1689 }
1690 }
1691
1692 /* TSC scaling required - calculate ratio */
1693 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1694 user_tsc_khz, tsc_khz);
1695
1696 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
3f16a5c3
PB		 1697 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1698 user_tsc_khz);
381d585c
HZ		 1699 return -1;
1700 }
1701
1702 vcpu->arch.tsc_scaling_ratio = ratio;
1703 return 0;
1704}
1705
4941b8cb 1706static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1707{
cc578287
ZA		 1708 u32 thresh_lo, thresh_hi;
1709 int use_scaling = 0;
217fc9cf 1710
03ba32ca 1711 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1712 if (user_tsc_khz == 0) {
ad721883
HZ		 1713 /* set tsc_scaling_ratio to a safe value */
1714 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1715 return -1;
ad721883 1716 }
03ba32ca 1717
c285545f 1718 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1719 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1720 &vcpu->arch.virtual_tsc_shift,
1721 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1722 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1723
1724 /*
1725 * Compute the variation in TSC rate which is acceptable
1726 * within the range of tolerance and decide if the
1727 * rate being applied is within that bounds of the hardware
1728 * rate. If so, no scaling or compensation need be done.
1729 */
1730 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1731 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1732 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1733 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1734 use_scaling = 1;
1735 }
4941b8cb 1736 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1737}
1738
1739static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1740{
e26101b1 1741 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1742 vcpu->arch.virtual_tsc_mult,
1743 vcpu->arch.virtual_tsc_shift);
e26101b1 1744 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1745 return tsc;
1746}
1747
b0c39dc6
VK		 1748static inline int gtod_is_based_on_tsc(int mode)
1749{
1750 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1751}
1752
69b0049a 1753static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1754{
1755#ifdef CONFIG_X86_64
1756 bool vcpus_matched;
b48aa97e
MT		 1757 struct kvm_arch *ka = &vcpu->kvm->arch;
1758 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1759
1760 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1761 atomic_read(&vcpu->kvm->online_vcpus));
1762
7f187922
MT		 1763 /*
1764 * Once the masterclock is enabled, always perform request in
1765 * order to update it.
1766 *
1767 * In order to enable masterclock, the host clocksource must be TSC
1768 * and the vcpus need to have matched TSCs. When that happens,
1769 * perform request to enable masterclock.
1770 */
1771 if (ka->use_master_clock ||
b0c39dc6 1772 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1773 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1774
1775 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1776 atomic_read(&vcpu->kvm->online_vcpus),
1777 ka->use_master_clock, gtod->clock.vclock_mode);
1778#endif
1779}
1780
ba904635
WA		 1781static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1782{
e79f245d 1783 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1784 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1785}
1786
35181e86
HZ		 1787/*
1788 * Multiply tsc by a fixed point number represented by ratio.
1789 *
1790 * The most significant 64-N bits (mult) of ratio represent the
1791 * integral part of the fixed point number; the remaining N bits
1792 * (frac) represent the fractional part, ie. ratio represents a fixed
1793 * point number (mult + frac * 2^(-N)).
1794 *
1795 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1796 */
1797static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1798{
1799 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1800}
1801
1802u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1803{
1804 u64 _tsc = tsc;
1805 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1806
1807 if (ratio != kvm_default_tsc_scaling_ratio)
1808 _tsc = __scale_tsc(ratio, tsc);
1809
1810 return _tsc;
1811}
1812EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1813
07c1419a
HZ		 1814static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1815{
1816 u64 tsc;
1817
1818 tsc = kvm_scale_tsc(vcpu, rdtsc());
1819
1820 return target_tsc - tsc;
1821}
1822
4ba76538
HZ		 1823u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1824{
e79f245d
KA		 1825 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1826
1827 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1828}
1829EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1830
a545ab6a
LC		 1831static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1832{
326e7425 1833 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1834}
1835
b0c39dc6
VK		 1836static inline bool kvm_check_tsc_unstable(void)
1837{
1838#ifdef CONFIG_X86_64
1839 /*
1840 * TSC is marked unstable when we're running on Hyper-V,
1841 * 'TSC page' clocksource is good.
1842 */
1843 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1844 return false;
1845#endif
1846 return check_tsc_unstable();
1847}
1848
8fe8ab46 1849void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1850{
1851 struct kvm *kvm = vcpu->kvm;
f38e098f 1852 u64 offset, ns, elapsed;
99e3e30a 1853 unsigned long flags;
b48aa97e 1854 bool matched;
0d3da0d2 1855 bool already_matched;
8fe8ab46 1856 u64 data = msr->data;
c5e8ec8e 1857 bool synchronizing = false;
99e3e30a 1858
038f8c11 1859 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1860 offset = kvm_compute_tsc_offset(vcpu, data);
9285ec4c 1861 ns = ktime_get_boottime_ns();
f38e098f 1862 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1863
03ba32ca 1864 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1865 if (data == 0 && msr->host_initiated) {
1866 /*
1867 * detection of vcpu initialization -- need to sync
1868 * with other vCPUs. This particularly helps to keep
1869 * kvm_clock stable after CPU hotplug
1870 */
1871 synchronizing = true;
1872 } else {
1873 u64 tsc_exp = kvm->arch.last_tsc_write +
1874 nsec_to_cycles(vcpu, elapsed);
1875 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1876 /*
1877 * Special case: TSC write with a small delta (1 second)
1878 * of virtual cycle time against real time is
1879 * interpreted as an attempt to synchronize the CPU.
1880 */
1881 synchronizing = data < tsc_exp + tsc_hz &&
1882 data + tsc_hz > tsc_exp;
1883 }
c5e8ec8e 1884 }
f38e098f
ZA		 1885
1886 /*
5d3cb0f6
ZA		 1887 * For a reliable TSC, we can match TSC offsets, and for an unstable
1888 * TSC, we add elapsed time in this computation. We could let the
1889 * compensation code attempt to catch up if we fall behind, but
1890 * it's better to try to match offsets from the beginning.
1891 */
c5e8ec8e 1892 if (synchronizing &&
5d3cb0f6 1893 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1894 if (!kvm_check_tsc_unstable()) {
e26101b1 1895 offset = kvm->arch.cur_tsc_offset;
f38e098f 1896 } else {
857e4099 1897 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1898 data += delta;
07c1419a 1899 offset = kvm_compute_tsc_offset(vcpu, data);
f38e098f 1900 }
b48aa97e 1901 matched = true;
0d3da0d2 1902 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1903 } else {
1904 /*
1905 * We split periods of matched TSC writes into generations.
1906 * For each generation, we track the original measured
1907 * nanosecond time, offset, and write, so if TSCs are in
1908 * sync, we can match exact offset, and if not, we can match
4a969980 1909 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1910 *
1911 * These values are tracked in kvm->arch.cur_xxx variables.
1912 */
1913 kvm->arch.cur_tsc_generation++;
1914 kvm->arch.cur_tsc_nsec = ns;
1915 kvm->arch.cur_tsc_write = data;
1916 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1917 matched = false;
f38e098f 1918 }
e26101b1
ZA		 1919
1920 /*
1921 * We also track th most recent recorded KHZ, write and time to
1922 * allow the matching interval to be extended at each write.
1923 */
f38e098f
ZA		 1924 kvm->arch.last_tsc_nsec = ns;
1925 kvm->arch.last_tsc_write = data;
5d3cb0f6 1926 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1927
b183aa58 1928 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1929
1930 /* Keep track of which generation this VCPU has synchronized to */
1931 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1932 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1933 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1934
d6321d49 1935 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1936 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1937
a545ab6a 1938 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1939 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1940
1941 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1942 if (!matched) {
b48aa97e 1943 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1944 } else if (!already_matched) {
1945 kvm->arch.nr_vcpus_matched_tsc++;
1946 }
b48aa97e
MT		 1947
1948 kvm_track_tsc_matching(vcpu);
1949 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1950}
e26101b1 1951
99e3e30a
ZA		 1952EXPORT_SYMBOL_GPL(kvm_write_tsc);
1953
58ea6767
HZ		 1954static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1955 s64 adjustment)
1956{
326e7425
LS		 1957 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1958 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 1959}
1960
1961static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1962{
1963 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1964 WARN_ON(adjustment < 0);
1965 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1966 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1967}
1968
d828199e
MT		 1969#ifdef CONFIG_X86_64
1970
a5a1d1c2 1971static u64 read_tsc(void)
d828199e 1972{
a5a1d1c2 1973 u64 ret = (u64)rdtsc_ordered();
03b9730b 1974 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1975
1976 if (likely(ret >= last))
1977 return ret;
1978
1979 /*
1980 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1981 * predictable (it's just a function of time and the likely is
d828199e
MT		 1982 * very likely) and there's a data dependence, so force GCC
1983 * to generate a branch instead. I don't barrier() because
1984 * we don't actually need a barrier, and if this function
1985 * ever gets inlined it will generate worse code.
1986 */
1987 asm volatile ("");
1988 return last;
1989}
1990
b0c39dc6 1991static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1992{
1993 long v;
1994 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1995 u64 tsc_pg_val;
1996
1997 switch (gtod->clock.vclock_mode) {
1998 case VCLOCK_HVCLOCK:
1999 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2000 tsc_timestamp);
2001 if (tsc_pg_val != U64_MAX) {
2002 /* TSC page valid */
2003 *mode = VCLOCK_HVCLOCK;
2004 v = (tsc_pg_val - gtod->clock.cycle_last) &
2005 gtod->clock.mask;
2006 } else {
2007 /* TSC page invalid */
2008 *mode = VCLOCK_NONE;
2009 }
2010 break;
2011 case VCLOCK_TSC:
2012 *mode = VCLOCK_TSC;
2013 *tsc_timestamp = read_tsc();
2014 v = (*tsc_timestamp - gtod->clock.cycle_last) &
2015 gtod->clock.mask;
2016 break;
2017 default:
2018 *mode = VCLOCK_NONE;
2019 }
d828199e 2020
b0c39dc6
VK		 2021 if (*mode == VCLOCK_NONE)
2022 *tsc_timestamp = v = 0;
d828199e 2023
d828199e
MT		 2024 return v * gtod->clock.mult;
2025}
2026
b0c39dc6 2027static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 2028{
cbcf2dd3 2029 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 2030 unsigned long seq;
d828199e 2031 int mode;
cbcf2dd3 2032 u64 ns;
d828199e 2033
d828199e
MT		 2034 do {
2035 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 2036 ns = gtod->nsec_base;
b0c39dc6 2037 ns += vgettsc(tsc_timestamp, &mode);
d828199e 2038 ns >>= gtod->clock.shift;
cbcf2dd3 2039 ns += gtod->boot_ns;
d828199e 2040 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 2041 *t = ns;
d828199e
MT		 2042
2043 return mode;
2044}
2045
899a31f5 2046static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 2047{
2048 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2049 unsigned long seq;
2050 int mode;
2051 u64 ns;
2052
2053 do {
2054 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 2055 ts->tv_sec = gtod->wall_time_sec;
2056 ns = gtod->nsec_base;
b0c39dc6 2057 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 2058 ns >>= gtod->clock.shift;
2059 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2060
2061 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2062 ts->tv_nsec = ns;
2063
2064 return mode;
2065}
2066
b0c39dc6
VK		 2067/* returns true if host is using TSC based clocksource */
2068static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 2069{
d828199e 2070 /* checked again under seqlock below */
b0c39dc6 2071 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 2072 return false;
2073
b0c39dc6
VK		 2074 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
2075 tsc_timestamp));
d828199e 2076}
55dd00a7 2077
b0c39dc6 2078/* returns true if host is using TSC based clocksource */
899a31f5 2079static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 2080 u64 *tsc_timestamp)
55dd00a7
MT		 2081{
2082 /* checked again under seqlock below */
b0c39dc6 2083 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 2084 return false;
2085
b0c39dc6 2086 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 2087}
d828199e
MT		 2088#endif
2089
2090/*
2091 *
b48aa97e
MT		 2092 * Assuming a stable TSC across physical CPUS, and a stable TSC
2093 * across virtual CPUs, the following condition is possible.
2094 * Each numbered line represents an event visible to both
d828199e
MT		 2095 * CPUs at the next numbered event.
2096 *
2097 * "timespecX" represents host monotonic time. "tscX" represents
2098 * RDTSC value.
2099 *
2100 * VCPU0 on CPU0 | VCPU1 on CPU1
2101 *
2102 * 1. read timespec0,tsc0
2103 * 2. | timespec1 = timespec0 + N
2104 * | tsc1 = tsc0 + M
2105 * 3. transition to guest | transition to guest
2106 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2107 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2108 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2109 *
2110 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2111 *
2112 * - ret0 < ret1
2113 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2114 * ...
2115 * - 0 < N - M => M < N
2116 *
2117 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2118 * always the case (the difference between two distinct xtime instances
2119 * might be smaller then the difference between corresponding TSC reads,
2120 * when updating guest vcpus pvclock areas).
2121 *
2122 * To avoid that problem, do not allow visibility of distinct
2123 * system_timestamp/tsc_timestamp values simultaneously: use a master
2124 * copy of host monotonic time values. Update that master copy
2125 * in lockstep.
2126 *
b48aa97e 2127 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 2128 *
2129 */
2130
2131static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2132{
2133#ifdef CONFIG_X86_64
2134 struct kvm_arch *ka = &kvm->arch;
2135 int vclock_mode;
b48aa97e
MT		 2136 bool host_tsc_clocksource, vcpus_matched;
2137
2138 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2139 atomic_read(&kvm->online_vcpus));
d828199e
MT		 2140
2141 /*
2142 * If the host uses TSC clock, then passthrough TSC as stable
2143 * to the guest.
2144 */
b48aa97e 2145 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 2146 &ka->master_kernel_ns,
2147 &ka->master_cycle_now);
2148
16a96021 2149 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 2150 && !ka->backwards_tsc_observed
54750f2c 2151 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 2152
d828199e
MT		 2153 if (ka->use_master_clock)
2154 atomic_set(&kvm_guest_has_master_clock, 1);
2155
2156 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 2157 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2158 vcpus_matched);
d828199e
MT		 2159#endif
2160}
2161
2860c4b1
PB		 2162void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2163{
2164 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2165}
2166
2e762ff7
MT		 2167static void kvm_gen_update_masterclock(struct kvm *kvm)
2168{
2169#ifdef CONFIG_X86_64
2170 int i;
2171 struct kvm_vcpu *vcpu;
2172 struct kvm_arch *ka = &kvm->arch;
2173
2174 spin_lock(&ka->pvclock_gtod_sync_lock);
2175 kvm_make_mclock_inprogress_request(kvm);
2176 /* no guest entries from this point */
2177 pvclock_update_vm_gtod_copy(kvm);
2178
2179 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2180 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2181
2182 /* guest entries allowed */
2183 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2184 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2185
2186 spin_unlock(&ka->pvclock_gtod_sync_lock);
2187#endif
2188}
2189
e891a32e 2190u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2191{
108b249c 2192 struct kvm_arch *ka = &kvm->arch;
8b953440 2193 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2194 u64 ret;
108b249c 2195
8b953440
PB		 2196 spin_lock(&ka->pvclock_gtod_sync_lock);
2197 if (!ka->use_master_clock) {
2198 spin_unlock(&ka->pvclock_gtod_sync_lock);
9285ec4c 2199 return ktime_get_boottime_ns() + ka->kvmclock_offset;
108b249c
PB		 2200 }
2201
8b953440
PB		 2202 hv_clock.tsc_timestamp = ka->master_cycle_now;
2203 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2204 spin_unlock(&ka->pvclock_gtod_sync_lock);
2205
e2c2206a
WL		 2206 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2207 get_cpu();
2208
e70b57a6
WL		 2209 if (__this_cpu_read(cpu_tsc_khz)) {
2210 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2211 &hv_clock.tsc_shift,
2212 &hv_clock.tsc_to_system_mul);
2213 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2214 } else
9285ec4c 2215 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2216
2217 put_cpu();
2218
2219 return ret;
108b249c
PB		 2220}
2221
0d6dd2ff
PB		 2222static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2223{
2224 struct kvm_vcpu_arch *vcpu = &v->arch;
2225 struct pvclock_vcpu_time_info guest_hv_clock;
2226
4e335d9e 2227 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2228 &guest_hv_clock, sizeof(guest_hv_clock))))
2229 return;
2230
2231 /* This VCPU is paused, but it's legal for a guest to read another
2232 * VCPU's kvmclock, so we really have to follow the specification where
2233 * it says that version is odd if data is being modified, and even after
2234 * it is consistent.
2235 *
2236 * Version field updates must be kept separate. This is because
2237 * kvm_write_guest_cached might use a "rep movs" instruction, and
2238 * writes within a string instruction are weakly ordered. So there
2239 * are three writes overall.
2240 *
2241 * As a small optimization, only write the version field in the first
2242 * and third write. The vcpu->pv_time cache is still valid, because the
2243 * version field is the first in the struct.
2244 */
2245 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2246
51c4b8bb
LA		 2247 if (guest_hv_clock.version & 1)
2248 ++guest_hv_clock.version; /* first time write, random junk */
2249
0d6dd2ff 2250 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2251 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2252 &vcpu->hv_clock,
2253 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2254
2255 smp_wmb();
2256
2257 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2258 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2259
2260 if (vcpu->pvclock_set_guest_stopped_request) {
2261 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2262 vcpu->pvclock_set_guest_stopped_request = false;
2263 }
2264
2265 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2266
4e335d9e
PB		 2267 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2268 &vcpu->hv_clock,
2269 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2270
2271 smp_wmb();
2272
2273 vcpu->hv_clock.version++;
4e335d9e
PB		 2274 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2275 &vcpu->hv_clock,
2276 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2277}
2278
34c238a1 2279static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2280{
78db6a50 2281 unsigned long flags, tgt_tsc_khz;
18068523 2282 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2283 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2284 s64 kernel_ns;
d828199e 2285 u64 tsc_timestamp, host_tsc;
51d59c6b 2286 u8 pvclock_flags;
d828199e
MT		 2287 bool use_master_clock;
2288
2289 kernel_ns = 0;
2290 host_tsc = 0;
18068523 2291
d828199e
MT		 2292 /*
2293 * If the host uses TSC clock, then passthrough TSC as stable
2294 * to the guest.
2295 */
2296 spin_lock(&ka->pvclock_gtod_sync_lock);
2297 use_master_clock = ka->use_master_clock;
2298 if (use_master_clock) {
2299 host_tsc = ka->master_cycle_now;
2300 kernel_ns = ka->master_kernel_ns;
2301 }
2302 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2303
2304 /* Keep irq disabled to prevent changes to the clock */
2305 local_irq_save(flags);
78db6a50
PB		 2306 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2307 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2308 local_irq_restore(flags);
2309 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2310 return 1;
2311 }
d828199e 2312 if (!use_master_clock) {
4ea1636b 2313 host_tsc = rdtsc();
9285ec4c 2314 kernel_ns = ktime_get_boottime_ns();
d828199e
MT		 2315 }
2316
4ba76538 2317 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2318
c285545f
ZA		 2319 /*
2320 * We may have to catch up the TSC to match elapsed wall clock
2321 * time for two reasons, even if kvmclock is used.
2322 * 1) CPU could have been running below the maximum TSC rate
2323 * 2) Broken TSC compensation resets the base at each VCPU
2324 * entry to avoid unknown leaps of TSC even when running
2325 * again on the same CPU. This may cause apparent elapsed
2326 * time to disappear, and the guest to stand still or run
2327 * very slowly.
2328 */
2329 if (vcpu->tsc_catchup) {
2330 u64 tsc = compute_guest_tsc(v, kernel_ns);
2331 if (tsc > tsc_timestamp) {
f1e2b260 2332 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2333 tsc_timestamp = tsc;
2334 }
50d0a0f9
GH		 2335 }
2336
18068523
GOC		 2337 local_irq_restore(flags);
2338
0d6dd2ff 2339 /* With all the info we got, fill in the values */
18068523 2340
78db6a50
PB		 2341 if (kvm_has_tsc_control)
2342 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2343
2344 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2345 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2346 &vcpu->hv_clock.tsc_shift,
2347 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2348 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2349 }
2350
1d5f066e 2351 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2352 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2353 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2354
d828199e 2355 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2356 pvclock_flags = 0;
d828199e
MT		 2357 if (use_master_clock)
2358 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2359
78c0337a
MT		 2360 vcpu->hv_clock.flags = pvclock_flags;
2361
095cf55d
PB		 2362 if (vcpu->pv_time_enabled)
2363 kvm_setup_pvclock_page(v);
2364 if (v == kvm_get_vcpu(v->kvm, 0))
2365 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2366 return 0;
c8076604
GH		 2367}
2368
0061d53d
MT		 2369/*
2370 * kvmclock updates which are isolated to a given vcpu, such as
2371 * vcpu->cpu migration, should not allow system_timestamp from
2372 * the rest of the vcpus to remain static. Otherwise ntp frequency
2373 * correction applies to one vcpu's system_timestamp but not
2374 * the others.
2375 *
2376 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2377 * We need to rate-limit these requests though, as they can
2378 * considerably slow guests that have a large number of vcpus.
2379 * The time for a remote vcpu to update its kvmclock is bound
2380 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2381 */
2382
7e44e449
AJ		 2383#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2384
2385static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2386{
2387 int i;
7e44e449
AJ		 2388 struct delayed_work *dwork = to_delayed_work(work);
2389 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2390 kvmclock_update_work);
2391 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2392 struct kvm_vcpu *vcpu;
2393
2394 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2395 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2396 kvm_vcpu_kick(vcpu);
2397 }
2398}
2399
7e44e449
AJ		 2400static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2401{
2402 struct kvm *kvm = v->kvm;
2403
105b21bb 2404 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2405 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2406 KVMCLOCK_UPDATE_DELAY);
2407}
2408
332967a3
AJ		 2409#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2410
2411static void kvmclock_sync_fn(struct work_struct *work)
2412{
2413 struct delayed_work *dwork = to_delayed_work(work);
2414 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2415 kvmclock_sync_work);
2416 struct kvm *kvm = container_of(ka, struct kvm, arch);
2417
630994b3
MT		 2418 if (!kvmclock_periodic_sync)
2419 return;
2420
332967a3
AJ		 2421 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2422 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2423 KVMCLOCK_SYNC_PERIOD);
2424}
2425
191c8137
BP		 2426/*
2427 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2428 */
2429static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2430{
2431 /* McStatusWrEn enabled? */
2432 if (guest_cpuid_is_amd(vcpu))
2433 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2434
2435 return false;
2436}
2437
9ffd986c 2438static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2439{
890ca9ae
HY		 2440 u64 mcg_cap = vcpu->arch.mcg_cap;
2441 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2442 u32 msr = msr_info->index;
2443 u64 data = msr_info->data;
890ca9ae 2444
15c4a640 2445 switch (msr) {
15c4a640 2446 case MSR_IA32_MCG_STATUS:
890ca9ae 2447 vcpu->arch.mcg_status = data;
15c4a640 2448 break;
c7ac679c 2449 case MSR_IA32_MCG_CTL:
44883f01
PB		 2450 if (!(mcg_cap & MCG_CTL_P) &&
2451 (data || !msr_info->host_initiated))
890ca9ae
HY		 2452 return 1;
2453 if (data != 0 && data != ~(u64)0)
44883f01 2454 return 1;
890ca9ae
HY		 2455 vcpu->arch.mcg_ctl = data;
2456 break;
2457 default:
2458 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2459 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2460 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2461 /* only 0 or all 1s can be written to IA32_MCi_CTL
2462 * some Linux kernels though clear bit 10 in bank 4 to
2463 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2464 * this to avoid an uncatched #GP in the guest
2465 */
890ca9ae 2466 if ((offset & 0x3) == 0 &&
114be429 2467 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2468 return -1;
191c8137
BP		 2469
2470 /* MCi_STATUS */
9ffd986c 2471 if (!msr_info->host_initiated &&
191c8137
BP		 2472 (offset & 0x3) == 1 && data != 0) {
2473 if (!can_set_mci_status(vcpu))
2474 return -1;
2475 }
2476
890ca9ae
HY		 2477 vcpu->arch.mce_banks[offset] = data;
2478 break;
2479 }
2480 return 1;
2481 }
2482 return 0;
2483}
2484
ffde22ac
ES		 2485static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2486{
2487 struct kvm *kvm = vcpu->kvm;
2488 int lm = is_long_mode(vcpu);
2489 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2490 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2491 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2492 : kvm->arch.xen_hvm_config.blob_size_32;
2493 u32 page_num = data & ~PAGE_MASK;
2494 u64 page_addr = data & PAGE_MASK;
2495 u8 *page;
2496 int r;
2497
2498 r = -E2BIG;
2499 if (page_num >= blob_size)
2500 goto out;
2501 r = -ENOMEM;
ff5c2c03
SL		 2502 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2503 if (IS_ERR(page)) {
2504 r = PTR_ERR(page);
ffde22ac 2505 goto out;
ff5c2c03 2506 }
54bf36aa 2507 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2508 goto out_free;
2509 r = 0;
2510out_free:
2511 kfree(page);
2512out:
2513 return r;
2514}
2515
344d9588
GN		 2516static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2517{
2518 gpa_t gpa = data & ~0x3f;
2519
52a5c155
WL		 2520 /* Bits 3:5 are reserved, Should be zero */
2521 if (data & 0x38)
344d9588
GN		 2522 return 1;
2523
2524 vcpu->arch.apf.msr_val = data;
2525
2526 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2527 kvm_clear_async_pf_completion_queue(vcpu);
2528 kvm_async_pf_hash_reset(vcpu);
2529 return 0;
2530 }
2531
4e335d9e 2532 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2533 sizeof(u32)))
344d9588
GN		 2534 return 1;
2535
6adba527 2536 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2537 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2538 kvm_async_pf_wakeup_all(vcpu);
2539 return 0;
2540}
2541
12f9a48f
GC		 2542static void kvmclock_reset(struct kvm_vcpu *vcpu)
2543{
0b79459b 2544 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2545}
2546
f38a7b75
WL		 2547static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2548{
2549 ++vcpu->stat.tlb_flush;
2550 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2551}
2552
c9aaa895
GC		 2553static void record_steal_time(struct kvm_vcpu *vcpu)
2554{
2555 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2556 return;
2557
4e335d9e 2558 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2559 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2560 return;
2561
f38a7b75
WL		 2562 /*
2563 * Doing a TLB flush here, on the guest's behalf, can avoid
2564 * expensive IPIs.
2565 */
b382f44e
WL		 2566 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
2567 vcpu->arch.st.steal.preempted & KVM_VCPU_FLUSH_TLB);
f38a7b75
WL		 2568 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2569 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2570
35f3fae1
WL		 2571 if (vcpu->arch.st.steal.version & 1)
2572 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2573
2574 vcpu->arch.st.steal.version += 1;
2575
4e335d9e 2576 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2577 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2578
2579 smp_wmb();
2580
c54cdf14
LC		 2581 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2582 vcpu->arch.st.last_steal;
2583 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2584
4e335d9e 2585 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2586 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2587
2588 smp_wmb();
2589
2590 vcpu->arch.st.steal.version += 1;
c9aaa895 2591
4e335d9e 2592 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2593 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2594}
2595
8fe8ab46 2596int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2597{
5753785f 2598 bool pr = false;
8fe8ab46
WA		 2599 u32 msr = msr_info->index;
2600 u64 data = msr_info->data;
5753785f 2601
15c4a640 2602 switch (msr) {
2e32b719 2603 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2604 case MSR_IA32_UCODE_WRITE:
2605 case MSR_VM_HSAVE_PA:
2606 case MSR_AMD64_PATCH_LOADER:
2607 case MSR_AMD64_BU_CFG2:
405a353a 2608 case MSR_AMD64_DC_CFG:
0e1b869f 2609 case MSR_F15H_EX_CFG:
2e32b719
BP		 2610 break;
2611
518e7b94
WL		 2612 case MSR_IA32_UCODE_REV:
2613 if (msr_info->host_initiated)
2614 vcpu->arch.microcode_version = data;
2615 break;
0cf9135b
SC		 2616 case MSR_IA32_ARCH_CAPABILITIES:
2617 if (!msr_info->host_initiated)
2618 return 1;
2619 vcpu->arch.arch_capabilities = data;
2620 break;
15c4a640 2621 case MSR_EFER:
11988499 2622 return set_efer(vcpu, msr_info);
8f1589d9
AP		 2623 case MSR_K7_HWCR:
2624 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2625 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2626 data &= ~(u64)0x8; /* ignore TLB cache disable */
191c8137
BP		 2627
2628 /* Handle McStatusWrEn */
2629 if (data == BIT_ULL(18)) {
2630 vcpu->arch.msr_hwcr = data;
2631 } else if (data != 0) {
a737f256
CD		 2632 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2633 data);
8f1589d9
AP		 2634 return 1;
2635 }
15c4a640 2636 break;
f7c6d140
AP		 2637 case MSR_FAM10H_MMIO_CONF_BASE:
2638 if (data != 0) {
a737f256
CD		 2639 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2640 "0x%llx\n", data);
f7c6d140
AP		 2641 return 1;
2642 }
15c4a640 2643 break;
b5e2fec0
AG		 2644 case MSR_IA32_DEBUGCTLMSR:
2645 if (!data) {
2646 /* We support the non-activated case already */
2647 break;
2648 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2649 /* Values other than LBR and BTF are vendor-specific,
2650 thus reserved and should throw a #GP */
2651 return 1;
2652 }
a737f256
CD		 2653 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2654 __func__, data);
b5e2fec0 2655 break;
9ba075a6 2656 case 0x200 ... 0x2ff:
ff53604b 2657 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2658 case MSR_IA32_APICBASE:
58cb628d 2659 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2660 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2661 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2662 case MSR_IA32_TSCDEADLINE:
2663 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2664 break;
ba904635 2665 case MSR_IA32_TSC_ADJUST:
d6321d49 2666 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2667 if (!msr_info->host_initiated) {
d913b904 2668 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2669 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2670 }
2671 vcpu->arch.ia32_tsc_adjust_msr = data;
2672 }
2673 break;
15c4a640 2674 case MSR_IA32_MISC_ENABLE:
511a8556
WL		 2675 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2676 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2677 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2678 return 1;
2679 vcpu->arch.ia32_misc_enable_msr = data;
2680 kvm_update_cpuid(vcpu);
2681 } else {
2682 vcpu->arch.ia32_misc_enable_msr = data;
2683 }
15c4a640 2684 break;
64d60670
PB		 2685 case MSR_IA32_SMBASE:
2686 if (!msr_info->host_initiated)
2687 return 1;
2688 vcpu->arch.smbase = data;
2689 break;
73f624f4
PB		 2690 case MSR_IA32_POWER_CTL:
2691 vcpu->arch.msr_ia32_power_ctl = data;
2692 break;
dd259935
PB		 2693 case MSR_IA32_TSC:
2694 kvm_write_tsc(vcpu, msr_info);
2695 break;
52797bf9
LA		 2696 case MSR_SMI_COUNT:
2697 if (!msr_info->host_initiated)
2698 return 1;
2699 vcpu->arch.smi_count = data;
2700 break;
11c6bffa 2701 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2702 case MSR_KVM_WALL_CLOCK:
2703 vcpu->kvm->arch.wall_clock = data;
2704 kvm_write_wall_clock(vcpu->kvm, data);
2705 break;
11c6bffa 2706 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2707 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2708 struct kvm_arch *ka = &vcpu->kvm->arch;
2709
12f9a48f 2710 kvmclock_reset(vcpu);
18068523 2711
54750f2c
MT		 2712 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2713 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2714
2715 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2716 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2717
2718 ka->boot_vcpu_runs_old_kvmclock = tmp;
2719 }
2720
18068523 2721 vcpu->arch.time = data;
0061d53d 2722 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2723
2724 /* we verify if the enable bit is set... */
2725 if (!(data & 1))
2726 break;
2727
4e335d9e 2728 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2729 &vcpu->arch.pv_time, data & ~1ULL,
2730 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2731 vcpu->arch.pv_time_enabled = false;
2732 else
2733 vcpu->arch.pv_time_enabled = true;
32cad84f 2734
18068523
GOC		 2735 break;
2736 }
344d9588
GN		 2737 case MSR_KVM_ASYNC_PF_EN:
2738 if (kvm_pv_enable_async_pf(vcpu, data))
2739 return 1;
2740 break;
c9aaa895
GC		 2741 case MSR_KVM_STEAL_TIME:
2742
2743 if (unlikely(!sched_info_on()))
2744 return 1;
2745
2746 if (data & KVM_STEAL_RESERVED_MASK)
2747 return 1;
2748
4e335d9e 2749 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2750 data & KVM_STEAL_VALID_BITS,
2751 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2752 return 1;
2753
2754 vcpu->arch.st.msr_val = data;
2755
2756 if (!(data & KVM_MSR_ENABLED))
2757 break;
2758
c9aaa895
GC		 2759 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2760
2761 break;
ae7a2a3f 2762 case MSR_KVM_PV_EOI_EN:
72bbf935 2763 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2764 return 1;
2765 break;
c9aaa895 2766
2d5ba19b
MT		 2767 case MSR_KVM_POLL_CONTROL:
2768 /* only enable bit supported */
2769 if (data & (-1ULL << 1))
2770 return 1;
2771
2772 vcpu->arch.msr_kvm_poll_control = data;
2773 break;
2774
890ca9ae
HY		 2775 case MSR_IA32_MCG_CTL:
2776 case MSR_IA32_MCG_STATUS:
81760dcc 2777 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2778 return set_msr_mce(vcpu, msr_info);
71db6023 2779
6912ac32
WH		 2780 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2781 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2782 pr = true; /* fall through */
2783 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2784 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2785 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2786 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2787
2788 if (pr || data != 0)
a737f256
CD		 2789 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2790 "0x%x data 0x%llx\n", msr, data);
5753785f 2791 break;
84e0cefa
JS		 2792 case MSR_K7_CLK_CTL:
2793 /*
2794 * Ignore all writes to this no longer documented MSR.
2795 * Writes are only relevant for old K7 processors,
2796 * all pre-dating SVM, but a recommended workaround from
4a969980 2797 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2798 * affected processor models on the command line, hence
2799 * the need to ignore the workaround.
2800 */
2801 break;
55cd8e5a 2802 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2803 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2804 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2805 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2806 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2807 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2808 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2809 return kvm_hv_set_msr_common(vcpu, msr, data,
2810 msr_info->host_initiated);
91c9c3ed 2811 case MSR_IA32_BBL_CR_CTL3:
2812 /* Drop writes to this legacy MSR -- see rdmsr
2813 * counterpart for further detail.
2814 */
fab0aa3b
EM		 2815 if (report_ignored_msrs)
2816 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2817 msr, data);
91c9c3ed 2818 break;
2b036c6b 2819 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2820 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2821 return 1;
2822 vcpu->arch.osvw.length = data;
2823 break;
2824 case MSR_AMD64_OSVW_STATUS:
d6321d49 2825 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2826 return 1;
2827 vcpu->arch.osvw.status = data;
2828 break;
db2336a8
KH		 2829 case MSR_PLATFORM_INFO:
2830 if (!msr_info->host_initiated ||
db2336a8
KH		 2831 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2832 cpuid_fault_enabled(vcpu)))
2833 return 1;
2834 vcpu->arch.msr_platform_info = data;
2835 break;
2836 case MSR_MISC_FEATURES_ENABLES:
2837 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2838 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2839 !supports_cpuid_fault(vcpu)))
2840 return 1;
2841 vcpu->arch.msr_misc_features_enables = data;
2842 break;
15c4a640 2843 default:
ffde22ac
ES		 2844 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2845 return xen_hvm_config(vcpu, data);
c6702c9d 2846 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2847 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2848 if (!ignore_msrs) {
ae0f5499 2849 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2850 msr, data);
ed85c068
AP		 2851 return 1;
2852 } else {
fab0aa3b
EM		 2853 if (report_ignored_msrs)
2854 vcpu_unimpl(vcpu,
2855 "ignored wrmsr: 0x%x data 0x%llx\n",
2856 msr, data);
ed85c068
AP		 2857 break;
2858 }
15c4a640
CO		 2859 }
2860 return 0;
2861}
2862EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2863
44883f01 2864static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2865{
2866 u64 data;
890ca9ae
HY		 2867 u64 mcg_cap = vcpu->arch.mcg_cap;
2868 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2869
2870 switch (msr) {
15c4a640
CO		 2871 case MSR_IA32_P5_MC_ADDR:
2872 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2873 data = 0;
2874 break;
15c4a640 2875 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2876 data = vcpu->arch.mcg_cap;
2877 break;
c7ac679c 2878 case MSR_IA32_MCG_CTL:
44883f01 2879 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2880 return 1;
2881 data = vcpu->arch.mcg_ctl;
2882 break;
2883 case MSR_IA32_MCG_STATUS:
2884 data = vcpu->arch.mcg_status;
2885 break;
2886 default:
2887 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2888 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2889 u32 offset = msr - MSR_IA32_MC0_CTL;
2890 data = vcpu->arch.mce_banks[offset];
2891 break;
2892 }
2893 return 1;
2894 }
2895 *pdata = data;
2896 return 0;
2897}
2898
609e36d3 2899int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2900{
609e36d3 2901 switch (msr_info->index) {
890ca9ae 2902 case MSR_IA32_PLATFORM_ID:
15c4a640 2903 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2904 case MSR_IA32_DEBUGCTLMSR:
2905 case MSR_IA32_LASTBRANCHFROMIP:
2906 case MSR_IA32_LASTBRANCHTOIP:
2907 case MSR_IA32_LASTINTFROMIP:
2908 case MSR_IA32_LASTINTTOIP:
60af2ecd 2909 case MSR_K8_SYSCFG:
3afb1121
PB		 2910 case MSR_K8_TSEG_ADDR:
2911 case MSR_K8_TSEG_MASK:
61a6bd67 2912 case MSR_VM_HSAVE_PA:
1fdbd48c 2913 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2914 case MSR_AMD64_NB_CFG:
f7c6d140 2915 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2916 case MSR_AMD64_BU_CFG2:
0c2df2a1 2917 case MSR_IA32_PERF_CTL:
405a353a 2918 case MSR_AMD64_DC_CFG:
0e1b869f 2919 case MSR_F15H_EX_CFG:
609e36d3 2920 msr_info->data = 0;
15c4a640 2921 break;
c51eb52b 2922 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2923 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2924 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2925 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2926 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2927 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2928 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2929 msr_info->data = 0;
5753785f 2930 break;
742bc670 2931 case MSR_IA32_UCODE_REV:
518e7b94 2932 msr_info->data = vcpu->arch.microcode_version;
742bc670 2933 break;
0cf9135b
SC		 2934 case MSR_IA32_ARCH_CAPABILITIES:
2935 if (!msr_info->host_initiated &&
2936 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
2937 return 1;
2938 msr_info->data = vcpu->arch.arch_capabilities;
2939 break;
73f624f4
PB		 2940 case MSR_IA32_POWER_CTL:
2941 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
2942 break;
dd259935
PB		 2943 case MSR_IA32_TSC:
2944 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2945 break;
9ba075a6 2946 case MSR_MTRRcap:
9ba075a6 2947 case 0x200 ... 0x2ff:
ff53604b 2948 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2949 case 0xcd: /* fsb frequency */
609e36d3 2950 msr_info->data = 3;
15c4a640 2951 break;
7b914098
JS		 2952 /*
2953 * MSR_EBC_FREQUENCY_ID
2954 * Conservative value valid for even the basic CPU models.
2955 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2956 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2957 * and 266MHz for model 3, or 4. Set Core Clock
2958 * Frequency to System Bus Frequency Ratio to 1 (bits
2959 * 31:24) even though these are only valid for CPU
2960 * models > 2, however guests may end up dividing or
2961 * multiplying by zero otherwise.
2962 */
2963 case MSR_EBC_FREQUENCY_ID:
609e36d3 2964 msr_info->data = 1 << 24;
7b914098 2965 break;
15c4a640 2966 case MSR_IA32_APICBASE:
609e36d3 2967 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2968 break;
0105d1a5 2969 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2970 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2971 break;
a3e06bbe 2972 case MSR_IA32_TSCDEADLINE:
609e36d3 2973 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2974 break;
ba904635 2975 case MSR_IA32_TSC_ADJUST:
609e36d3 2976 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2977 break;
15c4a640 2978 case MSR_IA32_MISC_ENABLE:
609e36d3 2979 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2980 break;
64d60670
PB		 2981 case MSR_IA32_SMBASE:
2982 if (!msr_info->host_initiated)
2983 return 1;
2984 msr_info->data = vcpu->arch.smbase;
15c4a640 2985 break;
52797bf9
LA		 2986 case MSR_SMI_COUNT:
2987 msr_info->data = vcpu->arch.smi_count;
2988 break;
847f0ad8
AG		 2989 case MSR_IA32_PERF_STATUS:
2990 /* TSC increment by tick */
609e36d3 2991 msr_info->data = 1000ULL;
847f0ad8 2992 /* CPU multiplier */
b0996ae4 2993 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2994 break;
15c4a640 2995 case MSR_EFER:
609e36d3 2996 msr_info->data = vcpu->arch.efer;
15c4a640 2997 break;
18068523 2998 case MSR_KVM_WALL_CLOCK:
11c6bffa 2999 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 3000 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 3001 break;
3002 case MSR_KVM_SYSTEM_TIME:
11c6bffa 3003 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 3004 msr_info->data = vcpu->arch.time;
18068523 3005 break;
344d9588 3006 case MSR_KVM_ASYNC_PF_EN:
609e36d3 3007 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 3008 break;
c9aaa895 3009 case MSR_KVM_STEAL_TIME:
609e36d3 3010 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 3011 break;
1d92128f 3012 case MSR_KVM_PV_EOI_EN:
609e36d3 3013 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 3014 break;
2d5ba19b
MT		 3015 case MSR_KVM_POLL_CONTROL:
3016 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3017 break;
890ca9ae
HY		 3018 case MSR_IA32_P5_MC_ADDR:
3019 case MSR_IA32_P5_MC_TYPE:
3020 case MSR_IA32_MCG_CAP:
3021 case MSR_IA32_MCG_CTL:
3022 case MSR_IA32_MCG_STATUS:
81760dcc 3023 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 3024 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3025 msr_info->host_initiated);
84e0cefa
JS		 3026 case MSR_K7_CLK_CTL:
3027 /*
3028 * Provide expected ramp-up count for K7. All other
3029 * are set to zero, indicating minimum divisors for
3030 * every field.
3031 *
3032 * This prevents guest kernels on AMD host with CPU
3033 * type 6, model 8 and higher from exploding due to
3034 * the rdmsr failing.
3035 */
609e36d3 3036 msr_info->data = 0x20000000;
84e0cefa 3037 break;
55cd8e5a 3038 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 3039 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3040 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 3041 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 3042 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3043 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3044 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 3045 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 3046 msr_info->index, &msr_info->data,
3047 msr_info->host_initiated);
55cd8e5a 3048 break;
91c9c3ed 3049 case MSR_IA32_BBL_CR_CTL3:
3050 /* This legacy MSR exists but isn't fully documented in current
3051 * silicon. It is however accessed by winxp in very narrow
3052 * scenarios where it sets bit #19, itself documented as
3053 * a "reserved" bit. Best effort attempt to source coherent
3054 * read data here should the balance of the register be
3055 * interpreted by the guest:
3056 *
3057 * L2 cache control register 3: 64GB range, 256KB size,
3058 * enabled, latency 0x1, configured
3059 */
609e36d3 3060 msr_info->data = 0xbe702111;
91c9c3ed 3061 break;
2b036c6b 3062 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 3063 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 3064 return 1;
609e36d3 3065 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 3066 break;
3067 case MSR_AMD64_OSVW_STATUS:
d6321d49 3068 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 3069 return 1;
609e36d3 3070 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 3071 break;
db2336a8 3072 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 3073 if (!msr_info->host_initiated &&
3074 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3075 return 1;
db2336a8
KH		 3076 msr_info->data = vcpu->arch.msr_platform_info;
3077 break;
3078 case MSR_MISC_FEATURES_ENABLES:
3079 msr_info->data = vcpu->arch.msr_misc_features_enables;
3080 break;
191c8137
BP		 3081 case MSR_K7_HWCR:
3082 msr_info->data = vcpu->arch.msr_hwcr;
3083 break;
15c4a640 3084 default:
c6702c9d 3085 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 3086 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 3087 if (!ignore_msrs) {
ae0f5499
BD		 3088 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3089 msr_info->index);
ed85c068
AP		 3090 return 1;
3091 } else {
fab0aa3b
EM		 3092 if (report_ignored_msrs)
3093 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3094 msr_info->index);
609e36d3 3095 msr_info->data = 0;
ed85c068
AP		 3096 }
3097 break;
15c4a640 3098 }
15c4a640
CO		 3099 return 0;
3100}
3101EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3102
313a3dc7
CO		 3103/*
3104 * Read or write a bunch of msrs. All parameters are kernel addresses.
3105 *
3106 * @return number of msrs set successfully.
3107 */
3108static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3109 struct kvm_msr_entry *entries,
3110 int (*do_msr)(struct kvm_vcpu *vcpu,
3111 unsigned index, u64 *data))
3112{
801e459a 3113 int i;
313a3dc7 3114
313a3dc7
CO		 3115 for (i = 0; i < msrs->nmsrs; ++i)
3116 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3117 break;
3118
313a3dc7
CO		 3119 return i;
3120}
3121
3122/*
3123 * Read or write a bunch of msrs. Parameters are user addresses.
3124 *
3125 * @return number of msrs set successfully.
3126 */
3127static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3128 int (*do_msr)(struct kvm_vcpu *vcpu,
3129 unsigned index, u64 *data),
3130 int writeback)
3131{
3132 struct kvm_msrs msrs;
3133 struct kvm_msr_entry *entries;
3134 int r, n;
3135 unsigned size;
3136
3137 r = -EFAULT;
0e96f31e 3138 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 3139 goto out;
3140
3141 r = -E2BIG;
3142 if (msrs.nmsrs >= MAX_IO_MSRS)
3143 goto out;
3144
313a3dc7 3145 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 3146 entries = memdup_user(user_msrs->entries, size);
3147 if (IS_ERR(entries)) {
3148 r = PTR_ERR(entries);
313a3dc7 3149 goto out;
ff5c2c03 3150 }
313a3dc7
CO		 3151
3152 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3153 if (r < 0)
3154 goto out_free;
3155
3156 r = -EFAULT;
3157 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3158 goto out_free;
3159
3160 r = n;
3161
3162out_free:
7a73c028 3163 kfree(entries);
313a3dc7
CO		 3164out:
3165 return r;
3166}
3167
4d5422ce
WL		 3168static inline bool kvm_can_mwait_in_guest(void)
3169{
3170 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 3171 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3172 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 3173}
3174
784aa3d7 3175int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 3176{
4d5422ce 3177 int r = 0;
018d00d2
ZX		 3178
3179 switch (ext) {
3180 case KVM_CAP_IRQCHIP:
3181 case KVM_CAP_HLT:
3182 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 3183 case KVM_CAP_SET_TSS_ADDR:
07716717 3184 case KVM_CAP_EXT_CPUID:
9c15bb1d 3185 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 3186 case KVM_CAP_CLOCKSOURCE:
7837699f 3187 case KVM_CAP_PIT:
a28e4f5a 3188 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 3189 case KVM_CAP_MP_STATE:
ed848624 3190 case KVM_CAP_SYNC_MMU:
a355c85c 3191 case KVM_CAP_USER_NMI:
52d939a0 3192 case KVM_CAP_REINJECT_CONTROL:
4925663a 3193 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 3194 case KVM_CAP_IOEVENTFD:
f848a5a8 3195 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 3196 case KVM_CAP_PIT2:
e9f42757 3197 case KVM_CAP_PIT_STATE2:
b927a3ce 3198 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 3199 case KVM_CAP_XEN_HVM:
3cfc3092 3200 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 3201 case KVM_CAP_HYPERV:
10388a07 3202 case KVM_CAP_HYPERV_VAPIC:
c25bc163 3203 case KVM_CAP_HYPERV_SPIN:
5c919412 3204 case KVM_CAP_HYPERV_SYNIC:
efc479e6 3205 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 3206 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 3207 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3208 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3209 case KVM_CAP_HYPERV_SEND_IPI:
2bc39970 3210 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3211 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3212 case KVM_CAP_DEBUGREGS:
d2be1651 3213 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3214 case KVM_CAP_XSAVE:
344d9588 3215 case KVM_CAP_ASYNC_PF:
92a1f12d 3216 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3217 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3218 case KVM_CAP_READONLY_MEM:
5f66b620 3219 case KVM_CAP_HYPERV_TIME:
100943c5 3220 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3221 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3222 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3223 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3224 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3225 case KVM_CAP_IMMEDIATE_EXIT:
66bb8a06 3226 case KVM_CAP_PMU_EVENT_FILTER:
801e459a 3227 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3228 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3229 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3230 r = 1;
3231 break;
01643c51
KH		 3232 case KVM_CAP_SYNC_REGS:
3233 r = KVM_SYNC_X86_VALID_FIELDS;
3234 break;
e3fd9a93
PB		 3235 case KVM_CAP_ADJUST_CLOCK:
3236 r = KVM_CLOCK_TSC_STABLE;
3237 break;
4d5422ce 3238 case KVM_CAP_X86_DISABLE_EXITS:
b5170063
WL		 3239 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3240 KVM_X86_DISABLE_EXITS_CSTATE;
4d5422ce
WL		 3241 if(kvm_can_mwait_in_guest())
3242 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3243 break;
6d396b55
PB		 3244 case KVM_CAP_X86_SMM:
3245 /* SMBASE is usually relocated above 1M on modern chipsets,
3246 * and SMM handlers might indeed rely on 4G segment limits,
3247 * so do not report SMM to be available if real mode is
3248 * emulated via vm86 mode. Still, do not go to great lengths
3249 * to avoid userspace's usage of the feature, because it is a
3250 * fringe case that is not enabled except via specific settings
3251 * of the module parameters.
3252 */
bc226f07 3253 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3254 break;
774ead3a
AK		 3255 case KVM_CAP_VAPIC:
3256 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3257 break;
f725230a 3258 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3259 r = KVM_SOFT_MAX_VCPUS;
3260 break;
3261 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3262 r = KVM_MAX_VCPUS;
3263 break;
a86cb413
TH		 3264 case KVM_CAP_MAX_VCPU_ID:
3265 r = KVM_MAX_VCPU_ID;
3266 break;
a68a6a72
MT		 3267 case KVM_CAP_PV_MMU: /* obsolete */
3268 r = 0;
2f333bcb 3269 break;
890ca9ae
HY		 3270 case KVM_CAP_MCE:
3271 r = KVM_MAX_MCE_BANKS;
3272 break;
2d5b5a66 3273 case KVM_CAP_XCRS:
d366bf7e 3274 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3275 break;
92a1f12d
JR		 3276 case KVM_CAP_TSC_CONTROL:
3277 r = kvm_has_tsc_control;
3278 break;
37131313
RK		 3279 case KVM_CAP_X2APIC_API:
3280 r = KVM_X2APIC_API_VALID_FLAGS;
3281 break;
8fcc4b59
JM		 3282 case KVM_CAP_NESTED_STATE:
3283 r = kvm_x86_ops->get_nested_state ?
be43c440 3284 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
8fcc4b59 3285 break;
344c6c80 3286 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5a0165f6
VK		 3287 r = kvm_x86_ops->enable_direct_tlbflush != NULL;
3288 break;
3289 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3290 r = kvm_x86_ops->nested_enable_evmcs != NULL;
344c6c80 3291 break;
018d00d2 3292 default:
018d00d2
ZX		 3293 break;
3294 }
3295 return r;
3296
3297}
3298
043405e1
CO		 3299long kvm_arch_dev_ioctl(struct file *filp,
3300 unsigned int ioctl, unsigned long arg)
3301{
3302 void __user *argp = (void __user *)arg;
3303 long r;
3304
3305 switch (ioctl) {
3306 case KVM_GET_MSR_INDEX_LIST: {
3307 struct kvm_msr_list __user *user_msr_list = argp;
3308 struct kvm_msr_list msr_list;
3309 unsigned n;
3310
3311 r = -EFAULT;
0e96f31e 3312 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3313 goto out;
3314 n = msr_list.nmsrs;
62ef68bb 3315 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3316 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3317 goto out;
3318 r = -E2BIG;
e125e7b6 3319 if (n < msr_list.nmsrs)
043405e1
CO		 3320 goto out;
3321 r = -EFAULT;
3322 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3323 num_msrs_to_save * sizeof(u32)))
3324 goto out;
e125e7b6 3325 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3326 &emulated_msrs,
62ef68bb 3327 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3328 goto out;
3329 r = 0;
3330 break;
3331 }
9c15bb1d
BP		 3332 case KVM_GET_SUPPORTED_CPUID:
3333 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3334 struct kvm_cpuid2 __user *cpuid_arg = argp;
3335 struct kvm_cpuid2 cpuid;
3336
3337 r = -EFAULT;
0e96f31e 3338 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3339 goto out;
9c15bb1d
BP		 3340
3341 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3342 ioctl);
674eea0f
AK		 3343 if (r)
3344 goto out;
3345
3346 r = -EFAULT;
0e96f31e 3347 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3348 goto out;
3349 r = 0;
3350 break;
3351 }
890ca9ae 3352 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3353 r = -EFAULT;
c45dcc71
AR		 3354 if (copy_to_user(argp, &kvm_mce_cap_supported,
3355 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3356 goto out;
3357 r = 0;
3358 break;
801e459a
TL		 3359 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3360 struct kvm_msr_list __user *user_msr_list = argp;
3361 struct kvm_msr_list msr_list;
3362 unsigned int n;
3363
3364 r = -EFAULT;
3365 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3366 goto out;
3367 n = msr_list.nmsrs;
3368 msr_list.nmsrs = num_msr_based_features;
3369 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3370 goto out;
3371 r = -E2BIG;
3372 if (n < msr_list.nmsrs)
3373 goto out;
3374 r = -EFAULT;
3375 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3376 num_msr_based_features * sizeof(u32)))
3377 goto out;
3378 r = 0;
3379 break;
3380 }
3381 case KVM_GET_MSRS:
3382 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3383 break;
890ca9ae 3384 }
043405e1
CO		 3385 default:
3386 r = -EINVAL;
3387 }
3388out:
3389 return r;
3390}
3391
f5f48ee1
SY		 3392static void wbinvd_ipi(void *garbage)
3393{
3394 wbinvd();
3395}
3396
3397static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3398{
e0f0bbc5 3399 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3400}
3401
313a3dc7
CO		 3402void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3403{
f5f48ee1
SY		 3404 /* Address WBINVD may be executed by guest */
3405 if (need_emulate_wbinvd(vcpu)) {
3406 if (kvm_x86_ops->has_wbinvd_exit())
3407 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3408 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3409 smp_call_function_single(vcpu->cpu,
3410 wbinvd_ipi, NULL, 1);
3411 }
3412
313a3dc7 3413 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3414
e7517324
WL		 3415 fpregs_assert_state_consistent();
3416 if (test_thread_flag(TIF_NEED_FPU_LOAD))
3417 switch_fpu_return();
3418
0dd6a6ed
ZA		 3419 /* Apply any externally detected TSC adjustments (due to suspend) */
3420 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3421 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3422 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3423 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3424 }
8f6055cb 3425
b0c39dc6 3426 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3427 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3428 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3429 if (tsc_delta < 0)
3430 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3431
b0c39dc6 3432 if (kvm_check_tsc_unstable()) {
07c1419a 3433 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3434 vcpu->arch.last_guest_tsc);
a545ab6a 3435 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3436 vcpu->arch.tsc_catchup = 1;
c285545f 3437 }
a749e247
PB		 3438
3439 if (kvm_lapic_hv_timer_in_use(vcpu))
3440 kvm_lapic_restart_hv_timer(vcpu);
3441
d98d07ca
MT		 3442 /*
3443 * On a host with synchronized TSC, there is no need to update
3444 * kvmclock on vcpu->cpu migration
3445 */
3446 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3447 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3448 if (vcpu->cpu != cpu)
1bd2009e 3449 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3450 vcpu->cpu = cpu;
6b7d7e76 3451 }
c9aaa895 3452
c9aaa895 3453 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3454}
3455
0b9f6c46
PX		 3456static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3457{
3458 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3459 return;
3460
fa55eedd 3461 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3462
4e335d9e 3463 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3464 &vcpu->arch.st.steal.preempted,
3465 offsetof(struct kvm_steal_time, preempted),
3466 sizeof(vcpu->arch.st.steal.preempted));
3467}
3468
313a3dc7
CO		 3469void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3470{
cc0d907c 3471 int idx;
de63ad4c
LM		 3472
3473 if (vcpu->preempted)
3474 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3475
931f261b
AA		 3476 /*
3477 * Disable page faults because we're in atomic context here.
3478 * kvm_write_guest_offset_cached() would call might_fault()
3479 * that relies on pagefault_disable() to tell if there's a
3480 * bug. NOTE: the write to guest memory may not go through if
3481 * during postcopy live migration or if there's heavy guest
3482 * paging.
3483 */
3484 pagefault_disable();
cc0d907c
AA		 3485 /*
3486 * kvm_memslots() will be called by
3487 * kvm_write_guest_offset_cached() so take the srcu lock.
3488 */
3489 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3490 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3491 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3492 pagefault_enable();
02daab21 3493 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3494 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3495 /*
f9dcf08e
RK		 3496 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3497 * on every vmexit, but if not, we might have a stale dr6 from the
3498 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3499 */
f9dcf08e 3500 set_debugreg(0, 6);
313a3dc7
CO		 3501}
3502
313a3dc7
CO		 3503static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3504 struct kvm_lapic_state *s)
3505{
fa59cc00 3506 if (vcpu->arch.apicv_active)
d62caabb
AS		 3507 kvm_x86_ops->sync_pir_to_irr(vcpu);
3508
a92e2543 3509 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3510}
3511
3512static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3513 struct kvm_lapic_state *s)
3514{
a92e2543
RK		 3515 int r;
3516
3517 r = kvm_apic_set_state(vcpu, s);
3518 if (r)
3519 return r;
cb142eb7 3520 update_cr8_intercept(vcpu);
313a3dc7
CO		 3521
3522 return 0;
3523}
3524
127a457a
MG		 3525static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3526{
3527 return (!lapic_in_kernel(vcpu) ||
3528 kvm_apic_accept_pic_intr(vcpu));
3529}
3530
782d422b
MG		 3531/*
3532 * if userspace requested an interrupt window, check that the
3533 * interrupt window is open.
3534 *
3535 * No need to exit to userspace if we already have an interrupt queued.
3536 */
3537static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3538{
3539 return kvm_arch_interrupt_allowed(vcpu) &&
3540 !kvm_cpu_has_interrupt(vcpu) &&
3541 !kvm_event_needs_reinjection(vcpu) &&
3542 kvm_cpu_accept_dm_intr(vcpu);
3543}
3544
f77bc6a4
ZX		 3545static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3546 struct kvm_interrupt *irq)
3547{
02cdb50f 3548 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3549 return -EINVAL;
1c1a9ce9
SR		 3550
3551 if (!irqchip_in_kernel(vcpu->kvm)) {
3552 kvm_queue_interrupt(vcpu, irq->irq, false);
3553 kvm_make_request(KVM_REQ_EVENT, vcpu);
3554 return 0;
3555 }
3556
3557 /*
3558 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3559 * fail for in-kernel 8259.
3560 */
3561 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3562 return -ENXIO;
f77bc6a4 3563
1c1a9ce9
SR		 3564 if (vcpu->arch.pending_external_vector != -1)
3565 return -EEXIST;
f77bc6a4 3566
1c1a9ce9 3567 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3568 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3569 return 0;
3570}
3571
c4abb7c9
JK		 3572static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3573{
c4abb7c9 3574 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3575
3576 return 0;
3577}
3578
f077825a
PB		 3579static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3580{
64d60670
PB		 3581 kvm_make_request(KVM_REQ_SMI, vcpu);
3582
f077825a
PB		 3583 return 0;
3584}
3585
b209749f
AK		 3586static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3587 struct kvm_tpr_access_ctl *tac)
3588{
3589 if (tac->flags)
3590 return -EINVAL;
3591 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3592 return 0;
3593}
3594
890ca9ae
HY		 3595static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3596 u64 mcg_cap)
3597{
3598 int r;
3599 unsigned bank_num = mcg_cap & 0xff, bank;
3600
3601 r = -EINVAL;
a9e38c3e 3602 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3603 goto out;
c45dcc71 3604 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3605 goto out;
3606 r = 0;
3607 vcpu->arch.mcg_cap = mcg_cap;
3608 /* Init IA32_MCG_CTL to all 1s */
3609 if (mcg_cap & MCG_CTL_P)
3610 vcpu->arch.mcg_ctl = ~(u64)0;
3611 /* Init IA32_MCi_CTL to all 1s */
3612 for (bank = 0; bank < bank_num; bank++)
3613 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71 3614
92735b1b 3615 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3616out:
3617 return r;
3618}
3619
3620static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3621 struct kvm_x86_mce *mce)
3622{
3623 u64 mcg_cap = vcpu->arch.mcg_cap;
3624 unsigned bank_num = mcg_cap & 0xff;
3625 u64 *banks = vcpu->arch.mce_banks;
3626
3627 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3628 return -EINVAL;
3629 /*
3630 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3631 * reporting is disabled
3632 */
3633 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3634 vcpu->arch.mcg_ctl != ~(u64)0)
3635 return 0;
3636 banks += 4 * mce->bank;
3637 /*
3638 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3639 * reporting is disabled for the bank
3640 */
3641 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3642 return 0;
3643 if (mce->status & MCI_STATUS_UC) {
3644 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3645 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3646 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3647 return 0;
3648 }
3649 if (banks[1] & MCI_STATUS_VAL)
3650 mce->status |= MCI_STATUS_OVER;
3651 banks[2] = mce->addr;
3652 banks[3] = mce->misc;
3653 vcpu->arch.mcg_status = mce->mcg_status;
3654 banks[1] = mce->status;
3655 kvm_queue_exception(vcpu, MC_VECTOR);
3656 } else if (!(banks[1] & MCI_STATUS_VAL)
3657 || !(banks[1] & MCI_STATUS_UC)) {
3658 if (banks[1] & MCI_STATUS_VAL)
3659 mce->status |= MCI_STATUS_OVER;
3660 banks[2] = mce->addr;
3661 banks[3] = mce->misc;
3662 banks[1] = mce->status;
3663 } else
3664 banks[1] |= MCI_STATUS_OVER;
3665 return 0;
3666}
3667
3cfc3092
JK		 3668static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3669 struct kvm_vcpu_events *events)
3670{
7460fb4a 3671 process_nmi(vcpu);
59073aaf 3672
664f8e26 3673 /*
59073aaf
JM		 3674 * The API doesn't provide the instruction length for software
3675 * exceptions, so don't report them. As long as the guest RIP
3676 * isn't advanced, we should expect to encounter the exception
3677 * again.
664f8e26 3678 */
59073aaf
JM		 3679 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3680 events->exception.injected = 0;
3681 events->exception.pending = 0;
3682 } else {
3683 events->exception.injected = vcpu->arch.exception.injected;
3684 events->exception.pending = vcpu->arch.exception.pending;
3685 /*
3686 * For ABI compatibility, deliberately conflate
3687 * pending and injected exceptions when
3688 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3689 */
3690 if (!vcpu->kvm->arch.exception_payload_enabled)
3691 events->exception.injected |=
3692 vcpu->arch.exception.pending;
3693 }
3cfc3092
JK		 3694 events->exception.nr = vcpu->arch.exception.nr;
3695 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3696 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3697 events->exception_has_payload = vcpu->arch.exception.has_payload;
3698 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3699
03b82a30 3700 events->interrupt.injected =
04140b41 3701 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3702 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3703 events->interrupt.soft = 0;
37ccdcbe 3704 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3705
3706 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3707 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3708 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3709 events->nmi.pad = 0;
3cfc3092 3710
66450a21 3711 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3712
f077825a
PB		 3713 events->smi.smm = is_smm(vcpu);
3714 events->smi.pending = vcpu->arch.smi_pending;
3715 events->smi.smm_inside_nmi =
3716 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3717 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3718
dab4b911 3719 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3720 | KVM_VCPUEVENT_VALID_SHADOW
3721 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3722 if (vcpu->kvm->arch.exception_payload_enabled)
3723 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3724
97e69aa6 3725 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3726}
3727
c5833c7a 3728static void kvm_smm_changed(struct kvm_vcpu *vcpu);
6ef4e07e 3729
3cfc3092
JK		 3730static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3731 struct kvm_vcpu_events *events)
3732{
dab4b911 3733 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3734 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3735 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3736 | KVM_VCPUEVENT_VALID_SMM
3737 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3738 return -EINVAL;
3739
59073aaf
JM		 3740 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3741 if (!vcpu->kvm->arch.exception_payload_enabled)
3742 return -EINVAL;
3743 if (events->exception.pending)
3744 events->exception.injected = 0;
3745 else
3746 events->exception_has_payload = 0;
3747 } else {
3748 events->exception.pending = 0;
3749 events->exception_has_payload = 0;
3750 }
3751
3752 if ((events->exception.injected || events->exception.pending) &&
3753 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3754 return -EINVAL;
3755
28bf2888
DH		 3756 /* INITs are latched while in SMM */
3757 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3758 (events->smi.smm || events->smi.pending) &&
3759 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3760 return -EINVAL;
3761
7460fb4a 3762 process_nmi(vcpu);
59073aaf
JM		 3763 vcpu->arch.exception.injected = events->exception.injected;
3764 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3765 vcpu->arch.exception.nr = events->exception.nr;
3766 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3767 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3768 vcpu->arch.exception.has_payload = events->exception_has_payload;
3769 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3770
04140b41 3771 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3772 vcpu->arch.interrupt.nr = events->interrupt.nr;
3773 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3774 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3775 kvm_x86_ops->set_interrupt_shadow(vcpu,
3776 events->interrupt.shadow);
3cfc3092
JK		 3777
3778 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3779 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3780 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3781 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3782
66450a21 3783 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3784 lapic_in_kernel(vcpu))
66450a21 3785 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3786
f077825a 3787 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
c5833c7a
SC		 3788 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3789 if (events->smi.smm)
3790 vcpu->arch.hflags |= HF_SMM_MASK;
3791 else
3792 vcpu->arch.hflags &= ~HF_SMM_MASK;
3793 kvm_smm_changed(vcpu);
3794 }
6ef4e07e 3795
f077825a 3796 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3797
3798 if (events->smi.smm) {
3799 if (events->smi.smm_inside_nmi)
3800 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3801 else
f4ef1910
WL		 3802 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3803 if (lapic_in_kernel(vcpu)) {
3804 if (events->smi.latched_init)
3805 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3806 else
3807 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3808 }
f077825a
PB		 3809 }
3810 }
3811
3842d135
AK		 3812 kvm_make_request(KVM_REQ_EVENT, vcpu);
3813
3cfc3092
JK		 3814 return 0;
3815}
3816
a1efbe77
JK		 3817static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3818 struct kvm_debugregs *dbgregs)
3819{
73aaf249
JK		 3820 unsigned long val;
3821
a1efbe77 3822 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3823 kvm_get_dr(vcpu, 6, &val);
73aaf249 3824 dbgregs->dr6 = val;
a1efbe77
JK		 3825 dbgregs->dr7 = vcpu->arch.dr7;
3826 dbgregs->flags = 0;
97e69aa6 3827 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3828}
3829
3830static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3831 struct kvm_debugregs *dbgregs)
3832{
3833 if (dbgregs->flags)
3834 return -EINVAL;
3835
d14bdb55
PB		 3836 if (dbgregs->dr6 & ~0xffffffffull)
3837 return -EINVAL;
3838 if (dbgregs->dr7 & ~0xffffffffull)
3839 return -EINVAL;
3840
a1efbe77 3841 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3842 kvm_update_dr0123(vcpu);
a1efbe77 3843 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3844 kvm_update_dr6(vcpu);
a1efbe77 3845 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3846 kvm_update_dr7(vcpu);
a1efbe77 3847
a1efbe77
JK		 3848 return 0;
3849}
3850
df1daba7
PB		 3851#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3852
3853static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3854{
b666a4b6 3855 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3856 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3857 u64 valid;
3858
3859 /*
3860 * Copy legacy XSAVE area, to avoid complications with CPUID
3861 * leaves 0 and 1 in the loop below.
3862 */
3863 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3864
3865 /* Set XSTATE_BV */
00c87e9a 3866 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3867 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3868
3869 /*
3870 * Copy each region from the possibly compacted offset to the
3871 * non-compacted offset.
3872 */
d91cab78 3873 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3874 while (valid) {
abd16d68
SAS		 3875 u64 xfeature_mask = valid & -valid;
3876 int xfeature_nr = fls64(xfeature_mask) - 1;
3877 void *src = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3878
3879 if (src) {
3880 u32 size, offset, ecx, edx;
abd16d68 3881 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3882 &size, &offset, &ecx, &edx);
abd16d68 3883 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3884 memcpy(dest + offset, &vcpu->arch.pkru,
3885 sizeof(vcpu->arch.pkru));
3886 else
3887 memcpy(dest + offset, src, size);
3888
df1daba7
PB		 3889 }
3890
abd16d68 3891 valid -= xfeature_mask;
df1daba7
PB		 3892 }
3893}
3894
3895static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3896{
b666a4b6 3897 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 3898 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3899 u64 valid;
3900
3901 /*
3902 * Copy legacy XSAVE area, to avoid complications with CPUID
3903 * leaves 0 and 1 in the loop below.
3904 */
3905 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3906
3907 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3908 xsave->header.xfeatures = xstate_bv;
782511b0 3909 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3910 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3911
3912 /*
3913 * Copy each region from the non-compacted offset to the
3914 * possibly compacted offset.
3915 */
d91cab78 3916 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3917 while (valid) {
abd16d68
SAS		 3918 u64 xfeature_mask = valid & -valid;
3919 int xfeature_nr = fls64(xfeature_mask) - 1;
3920 void *dest = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3921
3922 if (dest) {
3923 u32 size, offset, ecx, edx;
abd16d68 3924 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 3925 &size, &offset, &ecx, &edx);
abd16d68 3926 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 3927 memcpy(&vcpu->arch.pkru, src + offset,
3928 sizeof(vcpu->arch.pkru));
3929 else
3930 memcpy(dest, src + offset, size);
ee4100da 3931 }
df1daba7 3932
abd16d68 3933 valid -= xfeature_mask;
df1daba7
PB		 3934 }
3935}
3936
2d5b5a66
SY		 3937static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3938 struct kvm_xsave *guest_xsave)
3939{
d366bf7e 3940 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3941 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3942 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3943 } else {
2d5b5a66 3944 memcpy(guest_xsave->region,
b666a4b6 3945 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3946 sizeof(struct fxregs_state));
2d5b5a66 3947 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3948 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3949 }
3950}
3951
a575813b
WL		 3952#define XSAVE_MXCSR_OFFSET 24
3953
2d5b5a66
SY		 3954static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3955 struct kvm_xsave *guest_xsave)
3956{
3957 u64 xstate_bv =
3958 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3959 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3960
d366bf7e 3961 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3962 /*
3963 * Here we allow setting states that are not present in
3964 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3965 * with old userspace.
3966 */
a575813b
WL		 3967 if (xstate_bv & ~kvm_supported_xcr0() ||
3968 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3969 return -EINVAL;
df1daba7 3970 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3971 } else {
a575813b
WL		 3972 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3973 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3974 return -EINVAL;
b666a4b6 3975 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 3976 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3977 }
3978 return 0;
3979}
3980
3981static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3982 struct kvm_xcrs *guest_xcrs)
3983{
d366bf7e 3984 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3985 guest_xcrs->nr_xcrs = 0;
3986 return;
3987 }
3988
3989 guest_xcrs->nr_xcrs = 1;
3990 guest_xcrs->flags = 0;
3991 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3992 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3993}
3994
3995static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3996 struct kvm_xcrs *guest_xcrs)
3997{
3998 int i, r = 0;
3999
d366bf7e 4000 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 4001 return -EINVAL;
4002
4003 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4004 return -EINVAL;
4005
4006 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4007 /* Only support XCR0 currently */
c67a04cb 4008 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 4009 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 4010 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 4011 break;
4012 }
4013 if (r)
4014 r = -EINVAL;
4015 return r;
4016}
4017
1c0b28c2
EM		 4018/*
4019 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4020 * stopped by the hypervisor. This function will be called from the host only.
4021 * EINVAL is returned when the host attempts to set the flag for a guest that
4022 * does not support pv clocks.
4023 */
4024static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4025{
0b79459b 4026 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 4027 return -EINVAL;
51d59c6b 4028 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 4029 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4030 return 0;
4031}
4032
5c919412
AS		 4033static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4034 struct kvm_enable_cap *cap)
4035{
57b119da
VK		 4036 int r;
4037 uint16_t vmcs_version;
4038 void __user *user_ptr;
4039
5c919412
AS		 4040 if (cap->flags)
4041 return -EINVAL;
4042
4043 switch (cap->cap) {
efc479e6
RK		 4044 case KVM_CAP_HYPERV_SYNIC2:
4045 if (cap->args[0])
4046 return -EINVAL;
b2869f28
GS		 4047 /* fall through */
4048
5c919412 4049 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 4050 if (!irqchip_in_kernel(vcpu->kvm))
4051 return -EINVAL;
efc479e6
RK		 4052 return kvm_hv_activate_synic(vcpu, cap->cap ==
4053 KVM_CAP_HYPERV_SYNIC2);
57b119da 4054 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 4055 if (!kvm_x86_ops->nested_enable_evmcs)
4056 return -ENOTTY;
57b119da
VK		 4057 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4058 if (!r) {
4059 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4060 if (copy_to_user(user_ptr, &vmcs_version,
4061 sizeof(vmcs_version)))
4062 r = -EFAULT;
4063 }
4064 return r;
344c6c80
TL		 4065 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4066 if (!kvm_x86_ops->enable_direct_tlbflush)
4067 return -ENOTTY;
4068
4069 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
57b119da 4070
5c919412
AS		 4071 default:
4072 return -EINVAL;
4073 }
4074}
4075
313a3dc7
CO		 4076long kvm_arch_vcpu_ioctl(struct file *filp,
4077 unsigned int ioctl, unsigned long arg)
4078{
4079 struct kvm_vcpu *vcpu = filp->private_data;
4080 void __user *argp = (void __user *)arg;
4081 int r;
d1ac91d8
AK		 4082 union {
4083 struct kvm_lapic_state *lapic;
4084 struct kvm_xsave *xsave;
4085 struct kvm_xcrs *xcrs;
4086 void *buffer;
4087 } u;
4088
9b062471
CD		 4089 vcpu_load(vcpu);
4090
d1ac91d8 4091 u.buffer = NULL;
313a3dc7
CO		 4092 switch (ioctl) {
4093 case KVM_GET_LAPIC: {
2204ae3c 4094 r = -EINVAL;
bce87cce 4095 if (!lapic_in_kernel(vcpu))
2204ae3c 4096 goto out;
254272ce
BG		 4097 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4098 GFP_KERNEL_ACCOUNT);
313a3dc7 4099
b772ff36 4100 r = -ENOMEM;
d1ac91d8 4101 if (!u.lapic)
b772ff36 4102 goto out;
d1ac91d8 4103 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 4104 if (r)
4105 goto out;
4106 r = -EFAULT;
d1ac91d8 4107 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 4108 goto out;
4109 r = 0;
4110 break;
4111 }
4112 case KVM_SET_LAPIC: {
2204ae3c 4113 r = -EINVAL;
bce87cce 4114 if (!lapic_in_kernel(vcpu))
2204ae3c 4115 goto out;
ff5c2c03 4116 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 4117 if (IS_ERR(u.lapic)) {
4118 r = PTR_ERR(u.lapic);
4119 goto out_nofree;
4120 }
ff5c2c03 4121
d1ac91d8 4122 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 4123 break;
4124 }
f77bc6a4
ZX		 4125 case KVM_INTERRUPT: {
4126 struct kvm_interrupt irq;
4127
4128 r = -EFAULT;
0e96f31e 4129 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 4130 goto out;
4131 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 4132 break;
4133 }
c4abb7c9
JK		 4134 case KVM_NMI: {
4135 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 4136 break;
4137 }
f077825a
PB		 4138 case KVM_SMI: {
4139 r = kvm_vcpu_ioctl_smi(vcpu);
4140 break;
4141 }
313a3dc7
CO		 4142 case KVM_SET_CPUID: {
4143 struct kvm_cpuid __user *cpuid_arg = argp;
4144 struct kvm_cpuid cpuid;
4145
4146 r = -EFAULT;
0e96f31e 4147 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 4148 goto out;
4149 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 4150 break;
4151 }
07716717
DK		 4152 case KVM_SET_CPUID2: {
4153 struct kvm_cpuid2 __user *cpuid_arg = argp;
4154 struct kvm_cpuid2 cpuid;
4155
4156 r = -EFAULT;
0e96f31e 4157 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4158 goto out;
4159 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 4160 cpuid_arg->entries);
07716717
DK		 4161 break;
4162 }
4163 case KVM_GET_CPUID2: {
4164 struct kvm_cpuid2 __user *cpuid_arg = argp;
4165 struct kvm_cpuid2 cpuid;
4166
4167 r = -EFAULT;
0e96f31e 4168 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4169 goto out;
4170 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 4171 cpuid_arg->entries);
07716717
DK		 4172 if (r)
4173 goto out;
4174 r = -EFAULT;
0e96f31e 4175 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 4176 goto out;
4177 r = 0;
4178 break;
4179 }
801e459a
TL		 4180 case KVM_GET_MSRS: {
4181 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 4182 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 4183 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4184 break;
801e459a
TL		 4185 }
4186 case KVM_SET_MSRS: {
4187 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 4188 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 4189 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4190 break;
801e459a 4191 }
b209749f
AK		 4192 case KVM_TPR_ACCESS_REPORTING: {
4193 struct kvm_tpr_access_ctl tac;
4194
4195 r = -EFAULT;
0e96f31e 4196 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 4197 goto out;
4198 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4199 if (r)
4200 goto out;
4201 r = -EFAULT;
0e96f31e 4202 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 4203 goto out;
4204 r = 0;
4205 break;
4206 };
b93463aa
AK		 4207 case KVM_SET_VAPIC_ADDR: {
4208 struct kvm_vapic_addr va;
7301d6ab 4209 int idx;
b93463aa
AK		 4210
4211 r = -EINVAL;
35754c98 4212 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 4213 goto out;
4214 r = -EFAULT;
0e96f31e 4215 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 4216 goto out;
7301d6ab 4217 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 4218 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 4219 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4220 break;
4221 }
890ca9ae
HY		 4222 case KVM_X86_SETUP_MCE: {
4223 u64 mcg_cap;
4224
4225 r = -EFAULT;
0e96f31e 4226 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4227 goto out;
4228 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4229 break;
4230 }
4231 case KVM_X86_SET_MCE: {
4232 struct kvm_x86_mce mce;
4233
4234 r = -EFAULT;
0e96f31e 4235 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4236 goto out;
4237 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4238 break;
4239 }
3cfc3092
JK		 4240 case KVM_GET_VCPU_EVENTS: {
4241 struct kvm_vcpu_events events;
4242
4243 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4244
4245 r = -EFAULT;
4246 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4247 break;
4248 r = 0;
4249 break;
4250 }
4251 case KVM_SET_VCPU_EVENTS: {
4252 struct kvm_vcpu_events events;
4253
4254 r = -EFAULT;
4255 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4256 break;
4257
4258 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4259 break;
4260 }
a1efbe77
JK		 4261 case KVM_GET_DEBUGREGS: {
4262 struct kvm_debugregs dbgregs;
4263
4264 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4265
4266 r = -EFAULT;
4267 if (copy_to_user(argp, &dbgregs,
4268 sizeof(struct kvm_debugregs)))
4269 break;
4270 r = 0;
4271 break;
4272 }
4273 case KVM_SET_DEBUGREGS: {
4274 struct kvm_debugregs dbgregs;
4275
4276 r = -EFAULT;
4277 if (copy_from_user(&dbgregs, argp,
4278 sizeof(struct kvm_debugregs)))
4279 break;
4280
4281 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4282 break;
4283 }
2d5b5a66 4284 case KVM_GET_XSAVE: {
254272ce 4285 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
2d5b5a66 4286 r = -ENOMEM;
d1ac91d8 4287 if (!u.xsave)
2d5b5a66
SY		 4288 break;
4289
d1ac91d8 4290 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4291
4292 r = -EFAULT;
d1ac91d8 4293 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4294 break;
4295 r = 0;
4296 break;
4297 }
4298 case KVM_SET_XSAVE: {
ff5c2c03 4299 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4300 if (IS_ERR(u.xsave)) {
4301 r = PTR_ERR(u.xsave);
4302 goto out_nofree;
4303 }
2d5b5a66 4304
d1ac91d8 4305 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4306 break;
4307 }
4308 case KVM_GET_XCRS: {
254272ce 4309 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
2d5b5a66 4310 r = -ENOMEM;
d1ac91d8 4311 if (!u.xcrs)
2d5b5a66
SY		 4312 break;
4313
d1ac91d8 4314 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4315
4316 r = -EFAULT;
d1ac91d8 4317 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4318 sizeof(struct kvm_xcrs)))
4319 break;
4320 r = 0;
4321 break;
4322 }
4323 case KVM_SET_XCRS: {
ff5c2c03 4324 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4325 if (IS_ERR(u.xcrs)) {
4326 r = PTR_ERR(u.xcrs);
4327 goto out_nofree;
4328 }
2d5b5a66 4329
d1ac91d8 4330 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4331 break;
4332 }
92a1f12d
JR		 4333 case KVM_SET_TSC_KHZ: {
4334 u32 user_tsc_khz;
4335
4336 r = -EINVAL;
92a1f12d
JR		 4337 user_tsc_khz = (u32)arg;
4338
4339 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4340 goto out;
4341
cc578287
ZA		 4342 if (user_tsc_khz == 0)
4343 user_tsc_khz = tsc_khz;
4344
381d585c
HZ		 4345 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4346 r = 0;
92a1f12d 4347
92a1f12d
JR		 4348 goto out;
4349 }
4350 case KVM_GET_TSC_KHZ: {
cc578287 4351 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4352 goto out;
4353 }
1c0b28c2
EM		 4354 case KVM_KVMCLOCK_CTRL: {
4355 r = kvm_set_guest_paused(vcpu);
4356 goto out;
4357 }
5c919412
AS		 4358 case KVM_ENABLE_CAP: {
4359 struct kvm_enable_cap cap;
4360
4361 r = -EFAULT;
4362 if (copy_from_user(&cap, argp, sizeof(cap)))
4363 goto out;
4364 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4365 break;
4366 }
8fcc4b59
JM		 4367 case KVM_GET_NESTED_STATE: {
4368 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4369 u32 user_data_size;
4370
4371 r = -EINVAL;
4372 if (!kvm_x86_ops->get_nested_state)
4373 break;
4374
4375 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4376 r = -EFAULT;
8fcc4b59 4377 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4378 break;
8fcc4b59
JM		 4379
4380 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4381 user_data_size);
4382 if (r < 0)
26b471c7 4383 break;
8fcc4b59
JM		 4384
4385 if (r > user_data_size) {
4386 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4387 r = -EFAULT;
4388 else
4389 r = -E2BIG;
4390 break;
8fcc4b59 4391 }
26b471c7 4392
8fcc4b59
JM		 4393 r = 0;
4394 break;
4395 }
4396 case KVM_SET_NESTED_STATE: {
4397 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4398 struct kvm_nested_state kvm_state;
4399
4400 r = -EINVAL;
4401 if (!kvm_x86_ops->set_nested_state)
4402 break;
4403
26b471c7 4404 r = -EFAULT;
8fcc4b59 4405 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4406 break;
8fcc4b59 4407
26b471c7 4408 r = -EINVAL;
8fcc4b59 4409 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4410 break;
8fcc4b59
JM		 4411
4412 if (kvm_state.flags &
8cab6507
VK		 4413 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4414 | KVM_STATE_NESTED_EVMCS))
26b471c7 4415 break;
8fcc4b59
JM		 4416
4417 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4418 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4419 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4420 break;
8fcc4b59
JM		 4421
4422 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4423 break;
4424 }
2bc39970
VK		 4425 case KVM_GET_SUPPORTED_HV_CPUID: {
4426 struct kvm_cpuid2 __user *cpuid_arg = argp;
4427 struct kvm_cpuid2 cpuid;
4428
4429 r = -EFAULT;
4430 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4431 goto out;
4432
4433 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4434 cpuid_arg->entries);
4435 if (r)
4436 goto out;
4437
4438 r = -EFAULT;
4439 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4440 goto out;
4441 r = 0;
4442 break;
4443 }
313a3dc7
CO		 4444 default:
4445 r = -EINVAL;
4446 }
4447out:
d1ac91d8 4448 kfree(u.buffer);
9b062471
CD		 4449out_nofree:
4450 vcpu_put(vcpu);
313a3dc7
CO		 4451 return r;
4452}
4453
1499fa80 4454vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4455{
4456 return VM_FAULT_SIGBUS;
4457}
4458
1fe779f8
CO		 4459static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4460{
4461 int ret;
4462
4463 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4464 return -EINVAL;
1fe779f8
CO		 4465 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4466 return ret;
4467}
4468
b927a3ce
SY		 4469static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4470 u64 ident_addr)
4471{
2ac52ab8 4472 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4473}
4474
1fe779f8 4475static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
bc8a3d89 4476 unsigned long kvm_nr_mmu_pages)
1fe779f8
CO		 4477{
4478 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4479 return -EINVAL;
4480
79fac95e 4481 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4482
4483 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4484 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4485
79fac95e 4486 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4487 return 0;
4488}
4489
bc8a3d89 4490static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1fe779f8 4491{
39de71ec 4492 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4493}
4494
1fe779f8
CO		 4495static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4496{
90bca052 4497 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4498 int r;
4499
4500 r = 0;
4501 switch (chip->chip_id) {
4502 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4503 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4504 sizeof(struct kvm_pic_state));
4505 break;
4506 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4507 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4508 sizeof(struct kvm_pic_state));
4509 break;
4510 case KVM_IRQCHIP_IOAPIC:
33392b49 4511 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4512 break;
4513 default:
4514 r = -EINVAL;
4515 break;
4516 }
4517 return r;
4518}
4519
4520static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4521{
90bca052 4522 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4523 int r;
4524
4525 r = 0;
4526 switch (chip->chip_id) {
4527 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4528 spin_lock(&pic->lock);
4529 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4530 sizeof(struct kvm_pic_state));
90bca052 4531 spin_unlock(&pic->lock);
1fe779f8
CO		 4532 break;
4533 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4534 spin_lock(&pic->lock);
4535 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4536 sizeof(struct kvm_pic_state));
90bca052 4537 spin_unlock(&pic->lock);
1fe779f8
CO		 4538 break;
4539 case KVM_IRQCHIP_IOAPIC:
33392b49 4540 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4541 break;
4542 default:
4543 r = -EINVAL;
4544 break;
4545 }
90bca052 4546 kvm_pic_update_irq(pic);
1fe779f8
CO		 4547 return r;
4548}
4549
e0f63cb9
SY		 4550static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4551{
34f3941c
RK		 4552 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4553
4554 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4555
4556 mutex_lock(&kps->lock);
4557 memcpy(ps, &kps->channels, sizeof(*ps));
4558 mutex_unlock(&kps->lock);
2da29bcc 4559 return 0;
e0f63cb9
SY		 4560}
4561
4562static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4563{
0185604c 4564 int i;
09edea72
RK		 4565 struct kvm_pit *pit = kvm->arch.vpit;
4566
4567 mutex_lock(&pit->pit_state.lock);
34f3941c 4568 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4569 for (i = 0; i < 3; i++)
09edea72
RK		 4570 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4571 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4572 return 0;
e9f42757
BK		 4573}
4574
4575static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4576{
e9f42757
BK		 4577 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4578 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4579 sizeof(ps->channels));
4580 ps->flags = kvm->arch.vpit->pit_state.flags;
4581 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4582 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4583 return 0;
e9f42757
BK		 4584}
4585
4586static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4587{
2da29bcc 4588 int start = 0;
0185604c 4589 int i;
e9f42757 4590 u32 prev_legacy, cur_legacy;
09edea72
RK		 4591 struct kvm_pit *pit = kvm->arch.vpit;
4592
4593 mutex_lock(&pit->pit_state.lock);
4594 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4595 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4596 if (!prev_legacy && cur_legacy)
4597 start = 1;
09edea72
RK		 4598 memcpy(&pit->pit_state.channels, &ps->channels,
4599 sizeof(pit->pit_state.channels));
4600 pit->pit_state.flags = ps->flags;
0185604c 4601 for (i = 0; i < 3; i++)
09edea72 4602 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4603 start && i == 0);
09edea72 4604 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4605 return 0;
e0f63cb9
SY		 4606}
4607
52d939a0
MT		 4608static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4609 struct kvm_reinject_control *control)
4610{
71474e2f
RK		 4611 struct kvm_pit *pit = kvm->arch.vpit;
4612
4613 if (!pit)
52d939a0 4614 return -ENXIO;
b39c90b6 4615
71474e2f
RK		 4616 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4617 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4618 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4619 */
4620 mutex_lock(&pit->pit_state.lock);
4621 kvm_pit_set_reinject(pit, control->pit_reinject);
4622 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4623
52d939a0
MT		 4624 return 0;
4625}
4626
95d4c16c 4627/**
60c34612
TY		 4628 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4629 * @kvm: kvm instance
4630 * @log: slot id and address to which we copy the log
95d4c16c 4631 *
e108ff2f
PB		 4632 * Steps 1-4 below provide general overview of dirty page logging. See
4633 * kvm_get_dirty_log_protect() function description for additional details.
4634 *
4635 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4636 * always flush the TLB (step 4) even if previous step failed and the dirty
4637 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4638 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4639 * writes will be marked dirty for next log read.
95d4c16c 4640 *
60c34612
TY		 4641 * 1. Take a snapshot of the bit and clear it if needed.
4642 * 2. Write protect the corresponding page.
e108ff2f
PB		 4643 * 3. Copy the snapshot to the userspace.
4644 * 4. Flush TLB's if needed.
5bb064dc 4645 */
60c34612 4646int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4647{
8fe65a82 4648 bool flush = false;
e108ff2f 4649 int r;
5bb064dc 4650
79fac95e 4651 mutex_lock(&kvm->slots_lock);
5bb064dc 4652
88178fd4
KH		 4653 /*
4654 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4655 */
4656 if (kvm_x86_ops->flush_log_dirty)
4657 kvm_x86_ops->flush_log_dirty(kvm);
4658
8fe65a82 4659 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4660
4661 /*
4662 * All the TLBs can be flushed out of mmu lock, see the comments in
4663 * kvm_mmu_slot_remove_write_access().
4664 */
e108ff2f 4665 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4666 if (flush)
2a31b9db
PB		 4667 kvm_flush_remote_tlbs(kvm);
4668
4669 mutex_unlock(&kvm->slots_lock);
4670 return r;
4671}
4672
4673int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4674{
4675 bool flush = false;
4676 int r;
4677
4678 mutex_lock(&kvm->slots_lock);
4679
4680 /*
4681 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4682 */
4683 if (kvm_x86_ops->flush_log_dirty)
4684 kvm_x86_ops->flush_log_dirty(kvm);
4685
4686 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4687
4688 /*
4689 * All the TLBs can be flushed out of mmu lock, see the comments in
4690 * kvm_mmu_slot_remove_write_access().
4691 */
4692 lockdep_assert_held(&kvm->slots_lock);
4693 if (flush)
198c74f4
XG		 4694 kvm_flush_remote_tlbs(kvm);
4695
79fac95e 4696 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4697 return r;
4698}
4699
aa2fbe6d
YZ		 4700int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4701 bool line_status)
23d43cf9
CD		 4702{
4703 if (!irqchip_in_kernel(kvm))
4704 return -ENXIO;
4705
4706 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4707 irq_event->irq, irq_event->level,
4708 line_status);
23d43cf9
CD		 4709 return 0;
4710}
4711
e5d83c74
PB		 4712int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4713 struct kvm_enable_cap *cap)
90de4a18
NA		 4714{
4715 int r;
4716
4717 if (cap->flags)
4718 return -EINVAL;
4719
4720 switch (cap->cap) {
4721 case KVM_CAP_DISABLE_QUIRKS:
4722 kvm->arch.disabled_quirks = cap->args[0];
4723 r = 0;
4724 break;
49df6397
SR		 4725 case KVM_CAP_SPLIT_IRQCHIP: {
4726 mutex_lock(&kvm->lock);
b053b2ae
SR		 4727 r = -EINVAL;
4728 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4729 goto split_irqchip_unlock;
49df6397
SR		 4730 r = -EEXIST;
4731 if (irqchip_in_kernel(kvm))
4732 goto split_irqchip_unlock;
557abc40 4733 if (kvm->created_vcpus)
49df6397
SR		 4734 goto split_irqchip_unlock;
4735 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4736 if (r)
49df6397
SR		 4737 goto split_irqchip_unlock;
4738 /* Pairs with irqchip_in_kernel. */
4739 smp_wmb();
49776faf 4740 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4741 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4742 r = 0;
4743split_irqchip_unlock:
4744 mutex_unlock(&kvm->lock);
4745 break;
4746 }
37131313
RK		 4747 case KVM_CAP_X2APIC_API:
4748 r = -EINVAL;
4749 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4750 break;
4751
4752 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4753 kvm->arch.x2apic_format = true;
c519265f
RK		 4754 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4755 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4756
4757 r = 0;
4758 break;
4d5422ce
WL		 4759 case KVM_CAP_X86_DISABLE_EXITS:
4760 r = -EINVAL;
4761 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4762 break;
4763
4764 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4765 kvm_can_mwait_in_guest())
4766 kvm->arch.mwait_in_guest = true;
766d3571 4767 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4768 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4769 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4770 kvm->arch.pause_in_guest = true;
b5170063
WL		 4771 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4772 kvm->arch.cstate_in_guest = true;
4d5422ce
WL		 4773 r = 0;
4774 break;
6fbbde9a
DS		 4775 case KVM_CAP_MSR_PLATFORM_INFO:
4776 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4777 r = 0;
c4f55198
JM		 4778 break;
4779 case KVM_CAP_EXCEPTION_PAYLOAD:
4780 kvm->arch.exception_payload_enabled = cap->args[0];
4781 r = 0;
6fbbde9a 4782 break;
90de4a18
NA		 4783 default:
4784 r = -EINVAL;
4785 break;
4786 }
4787 return r;
4788}
4789
1fe779f8
CO		 4790long kvm_arch_vm_ioctl(struct file *filp,
4791 unsigned int ioctl, unsigned long arg)
4792{
4793 struct kvm *kvm = filp->private_data;
4794 void __user *argp = (void __user *)arg;
367e1319 4795 int r = -ENOTTY;
f0d66275
DH		 4796 /*
4797 * This union makes it completely explicit to gcc-3.x
4798 * that these two variables' stack usage should be
4799 * combined, not added together.
4800 */
4801 union {
4802 struct kvm_pit_state ps;
e9f42757 4803 struct kvm_pit_state2 ps2;
c5ff41ce 4804 struct kvm_pit_config pit_config;
f0d66275 4805 } u;
1fe779f8
CO		 4806
4807 switch (ioctl) {
4808 case KVM_SET_TSS_ADDR:
4809 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4810 break;
b927a3ce
SY		 4811 case KVM_SET_IDENTITY_MAP_ADDR: {
4812 u64 ident_addr;
4813
1af1ac91
DH		 4814 mutex_lock(&kvm->lock);
4815 r = -EINVAL;
4816 if (kvm->created_vcpus)
4817 goto set_identity_unlock;
b927a3ce 4818 r = -EFAULT;
0e96f31e 4819 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4820 goto set_identity_unlock;
b927a3ce 4821 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4822set_identity_unlock:
4823 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4824 break;
4825 }
1fe779f8
CO		 4826 case KVM_SET_NR_MMU_PAGES:
4827 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4828 break;
4829 case KVM_GET_NR_MMU_PAGES:
4830 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4831 break;
3ddea128 4832 case KVM_CREATE_IRQCHIP: {
3ddea128 4833 mutex_lock(&kvm->lock);
09941366 4834
3ddea128 4835 r = -EEXIST;
35e6eaa3 4836 if (irqchip_in_kernel(kvm))
3ddea128 4837 goto create_irqchip_unlock;
09941366 4838
3e515705 4839 r = -EINVAL;
557abc40 4840 if (kvm->created_vcpus)
3e515705 4841 goto create_irqchip_unlock;
09941366
RK		 4842
4843 r = kvm_pic_init(kvm);
4844 if (r)
3ddea128 4845 goto create_irqchip_unlock;
09941366
RK		 4846
4847 r = kvm_ioapic_init(kvm);
4848 if (r) {
09941366 4849 kvm_pic_destroy(kvm);
3ddea128 4850 goto create_irqchip_unlock;
09941366
RK		 4851 }
4852
399ec807
AK		 4853 r = kvm_setup_default_irq_routing(kvm);
4854 if (r) {
72bb2fcd 4855 kvm_ioapic_destroy(kvm);
09941366 4856 kvm_pic_destroy(kvm);
71ba994c 4857 goto create_irqchip_unlock;
399ec807 4858 }
49776faf 4859 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4860 smp_wmb();
49776faf 4861 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4862 create_irqchip_unlock:
4863 mutex_unlock(&kvm->lock);
1fe779f8 4864 break;
3ddea128 4865 }
7837699f 4866 case KVM_CREATE_PIT:
c5ff41ce
JK		 4867 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4868 goto create_pit;
4869 case KVM_CREATE_PIT2:
4870 r = -EFAULT;
4871 if (copy_from_user(&u.pit_config, argp,
4872 sizeof(struct kvm_pit_config)))
4873 goto out;
4874 create_pit:
250715a6 4875 mutex_lock(&kvm->lock);
269e05e4
AK		 4876 r = -EEXIST;
4877 if (kvm->arch.vpit)
4878 goto create_pit_unlock;
7837699f 4879 r = -ENOMEM;
c5ff41ce 4880 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4881 if (kvm->arch.vpit)
4882 r = 0;
269e05e4 4883 create_pit_unlock:
250715a6 4884 mutex_unlock(&kvm->lock);
7837699f 4885 break;
1fe779f8
CO		 4886 case KVM_GET_IRQCHIP: {
4887 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4888 struct kvm_irqchip *chip;
1fe779f8 4889
ff5c2c03
SL		 4890 chip = memdup_user(argp, sizeof(*chip));
4891 if (IS_ERR(chip)) {
4892 r = PTR_ERR(chip);
1fe779f8 4893 goto out;
ff5c2c03
SL		 4894 }
4895
1fe779f8 4896 r = -ENXIO;
826da321 4897 if (!irqchip_kernel(kvm))
f0d66275
DH		 4898 goto get_irqchip_out;
4899 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4900 if (r)
f0d66275 4901 goto get_irqchip_out;
1fe779f8 4902 r = -EFAULT;
0e96f31e 4903 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 4904 goto get_irqchip_out;
1fe779f8 4905 r = 0;
f0d66275
DH		 4906 get_irqchip_out:
4907 kfree(chip);
1fe779f8
CO		 4908 break;
4909 }
4910 case KVM_SET_IRQCHIP: {
4911 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4912 struct kvm_irqchip *chip;
1fe779f8 4913
ff5c2c03
SL		 4914 chip = memdup_user(argp, sizeof(*chip));
4915 if (IS_ERR(chip)) {
4916 r = PTR_ERR(chip);
1fe779f8 4917 goto out;
ff5c2c03
SL		 4918 }
4919
1fe779f8 4920 r = -ENXIO;
826da321 4921 if (!irqchip_kernel(kvm))
f0d66275
DH		 4922 goto set_irqchip_out;
4923 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4924 if (r)
f0d66275 4925 goto set_irqchip_out;
1fe779f8 4926 r = 0;
f0d66275
DH		 4927 set_irqchip_out:
4928 kfree(chip);
1fe779f8
CO		 4929 break;
4930 }
e0f63cb9 4931 case KVM_GET_PIT: {
e0f63cb9 4932 r = -EFAULT;
f0d66275 4933 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4934 goto out;
4935 r = -ENXIO;
4936 if (!kvm->arch.vpit)
4937 goto out;
f0d66275 4938 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4939 if (r)
4940 goto out;
4941 r = -EFAULT;
f0d66275 4942 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4943 goto out;
4944 r = 0;
4945 break;
4946 }
4947 case KVM_SET_PIT: {
e0f63cb9 4948 r = -EFAULT;
0e96f31e 4949 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 4950 goto out;
4951 r = -ENXIO;
4952 if (!kvm->arch.vpit)
4953 goto out;
f0d66275 4954 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4955 break;
4956 }
e9f42757
BK		 4957 case KVM_GET_PIT2: {
4958 r = -ENXIO;
4959 if (!kvm->arch.vpit)
4960 goto out;
4961 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4962 if (r)
4963 goto out;
4964 r = -EFAULT;
4965 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4966 goto out;
4967 r = 0;
4968 break;
4969 }
4970 case KVM_SET_PIT2: {
4971 r = -EFAULT;
4972 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4973 goto out;
4974 r = -ENXIO;
4975 if (!kvm->arch.vpit)
4976 goto out;
4977 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4978 break;
4979 }
52d939a0
MT		 4980 case KVM_REINJECT_CONTROL: {
4981 struct kvm_reinject_control control;
4982 r = -EFAULT;
4983 if (copy_from_user(&control, argp, sizeof(control)))
4984 goto out;
4985 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4986 break;
4987 }
d71ba788
PB		 4988 case KVM_SET_BOOT_CPU_ID:
4989 r = 0;
4990 mutex_lock(&kvm->lock);
557abc40 4991 if (kvm->created_vcpus)
d71ba788
PB		 4992 r = -EBUSY;
4993 else
4994 kvm->arch.bsp_vcpu_id = arg;
4995 mutex_unlock(&kvm->lock);
4996 break;
ffde22ac 4997 case KVM_XEN_HVM_CONFIG: {
51776043 4998 struct kvm_xen_hvm_config xhc;
ffde22ac 4999 r = -EFAULT;
51776043 5000 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 5001 goto out;
5002 r = -EINVAL;
51776043 5003 if (xhc.flags)
ffde22ac 5004 goto out;
51776043 5005 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 5006 r = 0;
5007 break;
5008 }
afbcf7ab 5009 case KVM_SET_CLOCK: {
afbcf7ab
GC		 5010 struct kvm_clock_data user_ns;
5011 u64 now_ns;
afbcf7ab
GC		 5012
5013 r = -EFAULT;
5014 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5015 goto out;
5016
5017 r = -EINVAL;
5018 if (user_ns.flags)
5019 goto out;
5020
5021 r = 0;
0bc48bea
RK		 5022 /*
5023 * TODO: userspace has to take care of races with VCPU_RUN, so
5024 * kvm_gen_update_masterclock() can be cut down to locked
5025 * pvclock_update_vm_gtod_copy().
5026 */
5027 kvm_gen_update_masterclock(kvm);
e891a32e 5028 now_ns = get_kvmclock_ns(kvm);
108b249c 5029 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 5030 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 5031 break;
5032 }
5033 case KVM_GET_CLOCK: {
afbcf7ab
GC		 5034 struct kvm_clock_data user_ns;
5035 u64 now_ns;
5036
e891a32e 5037 now_ns = get_kvmclock_ns(kvm);
108b249c 5038 user_ns.clock = now_ns;
e3fd9a93 5039 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 5040 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 5041
5042 r = -EFAULT;
5043 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5044 goto out;
5045 r = 0;
5046 break;
5047 }
5acc5c06
BS		 5048 case KVM_MEMORY_ENCRYPT_OP: {
5049 r = -ENOTTY;
5050 if (kvm_x86_ops->mem_enc_op)
5051 r = kvm_x86_ops->mem_enc_op(kvm, argp);
5052 break;
5053 }
69eaedee
BS		 5054 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5055 struct kvm_enc_region region;
5056
5057 r = -EFAULT;
5058 if (copy_from_user(&region, argp, sizeof(region)))
5059 goto out;
5060
5061 r = -ENOTTY;
5062 if (kvm_x86_ops->mem_enc_reg_region)
5063 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
5064 break;
5065 }
5066 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5067 struct kvm_enc_region region;
5068
5069 r = -EFAULT;
5070 if (copy_from_user(&region, argp, sizeof(region)))
5071 goto out;
5072
5073 r = -ENOTTY;
5074 if (kvm_x86_ops->mem_enc_unreg_region)
5075 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
5076 break;
5077 }
faeb7833
RK		 5078 case KVM_HYPERV_EVENTFD: {
5079 struct kvm_hyperv_eventfd hvevfd;
5080
5081 r = -EFAULT;
5082 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5083 goto out;
5084 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5085 break;
5086 }
66bb8a06
EH		 5087 case KVM_SET_PMU_EVENT_FILTER:
5088 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5089 break;
1fe779f8 5090 default:
ad6260da 5091 r = -ENOTTY;
1fe779f8
CO		 5092 }
5093out:
5094 return r;
5095}
5096
a16b043c 5097static void kvm_init_msr_list(void)
043405e1
CO		 5098{
5099 u32 dummy[2];
5100 unsigned i, j;
5101
e2ada66e
JM		 5102 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
5103 "Please update the fixed PMCs in msrs_to_save[]");
5104 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_GENERIC != 32,
5105 "Please update the generic perfctr/eventsel MSRs in msrs_to_save[]");
5106
62ef68bb 5107 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 5108 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
5109 continue;
93c4adc7
PB		 5110
5111 /*
5112 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 5113 * to the guests in some cases.
93c4adc7
PB		 5114 */
5115 switch (msrs_to_save[i]) {
5116 case MSR_IA32_BNDCFGS:
503234b3 5117 if (!kvm_mpx_supported())
93c4adc7
PB		 5118 continue;
5119 break;
9dbe6cf9
PB		 5120 case MSR_TSC_AUX:
5121 if (!kvm_x86_ops->rdtscp_supported())
5122 continue;
5123 break;
bf8c55d8
CP		 5124 case MSR_IA32_RTIT_CTL:
5125 case MSR_IA32_RTIT_STATUS:
5126 if (!kvm_x86_ops->pt_supported())
5127 continue;
5128 break;
5129 case MSR_IA32_RTIT_CR3_MATCH:
5130 if (!kvm_x86_ops->pt_supported() ||
5131 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5132 continue;
5133 break;
5134 case MSR_IA32_RTIT_OUTPUT_BASE:
5135 case MSR_IA32_RTIT_OUTPUT_MASK:
5136 if (!kvm_x86_ops->pt_supported() ||
5137 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5138 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5139 continue;
5140 break;
5141 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5142 if (!kvm_x86_ops->pt_supported() ||
5143 msrs_to_save[i] - MSR_IA32_RTIT_ADDR0_A >=
5144 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5145 continue;
5146 break;
5147 }
93c4adc7
PB		 5148 default:
5149 break;
5150 }
5151
043405e1
CO		 5152 if (j < i)
5153 msrs_to_save[j] = msrs_to_save[i];
5154 j++;
5155 }
5156 num_msrs_to_save = j;
62ef68bb
PB		 5157
5158 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 5159 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
5160 continue;
62ef68bb
PB		 5161
5162 if (j < i)
5163 emulated_msrs[j] = emulated_msrs[i];
5164 j++;
5165 }
5166 num_emulated_msrs = j;
801e459a
TL		 5167
5168 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
5169 struct kvm_msr_entry msr;
5170
5171 msr.index = msr_based_features[i];
66421c1e 5172 if (kvm_get_msr_feature(&msr))
801e459a
TL		 5173 continue;
5174
5175 if (j < i)
5176 msr_based_features[j] = msr_based_features[i];
5177 j++;
5178 }
5179 num_msr_based_features = j;
043405e1
CO		 5180}
5181
bda9020e
MT		 5182static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5183 const void *v)
bbd9b64e 5184{
70252a10
AK		 5185 int handled = 0;
5186 int n;
5187
5188 do {
5189 n = min(len, 8);
bce87cce 5190 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5191 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5192 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 5193 break;
5194 handled += n;
5195 addr += n;
5196 len -= n;
5197 v += n;
5198 } while (len);
bbd9b64e 5199
70252a10 5200 return handled;
bbd9b64e
CO		 5201}
5202
bda9020e 5203static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 5204{
70252a10
AK		 5205 int handled = 0;
5206 int n;
5207
5208 do {
5209 n = min(len, 8);
bce87cce 5210 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5211 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5212 addr, n, v))
5213 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 5214 break;
e39d200f 5215 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 5216 handled += n;
5217 addr += n;
5218 len -= n;
5219 v += n;
5220 } while (len);
bbd9b64e 5221
70252a10 5222 return handled;
bbd9b64e
CO		 5223}
5224
2dafc6c2
GN		 5225static void kvm_set_segment(struct kvm_vcpu *vcpu,
5226 struct kvm_segment *var, int seg)
5227{
5228 kvm_x86_ops->set_segment(vcpu, var, seg);
5229}
5230
5231void kvm_get_segment(struct kvm_vcpu *vcpu,
5232 struct kvm_segment *var, int seg)
5233{
5234 kvm_x86_ops->get_segment(vcpu, var, seg);
5235}
5236
54987b7a
PB		 5237gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5238 struct x86_exception *exception)
02f59dc9
JR		 5239{
5240 gpa_t t_gpa;
02f59dc9
JR		 5241
5242 BUG_ON(!mmu_is_nested(vcpu));
5243
5244 /* NPT walks are always user-walks */
5245 access |= PFERR_USER_MASK;
44dd3ffa 5246 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 5247
5248 return t_gpa;
5249}
5250
ab9ae313
AK		 5251gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5252 struct x86_exception *exception)
1871c602
GN		 5253{
5254 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 5255 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5256}
5257
ab9ae313
AK		 5258 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5259 struct x86_exception *exception)
1871c602
GN		 5260{
5261 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5262 access |= PFERR_FETCH_MASK;
ab9ae313 5263 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5264}
5265
ab9ae313
AK		 5266gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5267 struct x86_exception *exception)
1871c602
GN		 5268{
5269 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5270 access |= PFERR_WRITE_MASK;
ab9ae313 5271 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5272}
5273
5274/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5275gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5276 struct x86_exception *exception)
1871c602 5277{
ab9ae313 5278 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5279}
5280
5281static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5282 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5283 struct x86_exception *exception)
bbd9b64e
CO		 5284{
5285 void *data = val;
10589a46 5286 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5287
5288 while (bytes) {
14dfe855 5289 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5290 exception);
bbd9b64e 5291 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5292 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5293 int ret;
5294
bcc55cba 5295 if (gpa == UNMAPPED_GVA)
ab9ae313 5296 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5297 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5298 offset, toread);
10589a46 5299 if (ret < 0) {
c3cd7ffa 5300 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5301 goto out;
5302 }
bbd9b64e 5303
77c2002e
IE		 5304 bytes -= toread;
5305 data += toread;
5306 addr += toread;
bbd9b64e 5307 }
10589a46 5308out:
10589a46 5309 return r;
bbd9b64e 5310}
77c2002e 5311
1871c602 5312/* used for instruction fetching */
0f65dd70
AK		 5313static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5314 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5315 struct x86_exception *exception)
1871c602 5316{
0f65dd70 5317 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5318 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5319 unsigned offset;
5320 int ret;
0f65dd70 5321
44583cba
PB		 5322 /* Inline kvm_read_guest_virt_helper for speed. */
5323 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5324 exception);
5325 if (unlikely(gpa == UNMAPPED_GVA))
5326 return X86EMUL_PROPAGATE_FAULT;
5327
5328 offset = addr & (PAGE_SIZE-1);
5329 if (WARN_ON(offset + bytes > PAGE_SIZE))
5330 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5331 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5332 offset, bytes);
44583cba
PB		 5333 if (unlikely(ret < 0))
5334 return X86EMUL_IO_NEEDED;
5335
5336 return X86EMUL_CONTINUE;
1871c602
GN		 5337}
5338
ce14e868 5339int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5340 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5341 struct x86_exception *exception)
1871c602
GN		 5342{
5343 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5344
353c0956
PB		 5345 /*
5346 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5347 * is returned, but our callers are not ready for that and they blindly
5348 * call kvm_inject_page_fault. Ensure that they at least do not leak
5349 * uninitialized kernel stack memory into cr2 and error code.
5350 */
5351 memset(exception, 0, sizeof(*exception));
1871c602 5352 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5353 exception);
1871c602 5354}
064aea77 5355EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5356
ce14e868
PB		 5357static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5358 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5359 struct x86_exception *exception, bool system)
1871c602 5360{
0f65dd70 5361 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5362 u32 access = 0;
5363
5364 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5365 access |= PFERR_USER_MASK;
5366
5367 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5368}
5369
7a036a6f
RK		 5370static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5371 unsigned long addr, void *val, unsigned int bytes)
5372{
5373 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5374 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5375
5376 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5377}
5378
ce14e868
PB		 5379static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5380 struct kvm_vcpu *vcpu, u32 access,
5381 struct x86_exception *exception)
77c2002e
IE		 5382{
5383 void *data = val;
5384 int r = X86EMUL_CONTINUE;
5385
5386 while (bytes) {
14dfe855 5387 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5388 access,
ab9ae313 5389 exception);
77c2002e
IE		 5390 unsigned offset = addr & (PAGE_SIZE-1);
5391 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5392 int ret;
5393
bcc55cba 5394 if (gpa == UNMAPPED_GVA)
ab9ae313 5395 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5396 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5397 if (ret < 0) {
c3cd7ffa 5398 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5399 goto out;
5400 }
5401
5402 bytes -= towrite;
5403 data += towrite;
5404 addr += towrite;
5405 }
5406out:
5407 return r;
5408}
ce14e868
PB		 5409
5410static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5411 unsigned int bytes, struct x86_exception *exception,
5412 bool system)
ce14e868
PB		 5413{
5414 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5415 u32 access = PFERR_WRITE_MASK;
5416
5417 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5418 access |= PFERR_USER_MASK;
ce14e868
PB		 5419
5420 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5421 access, exception);
ce14e868
PB		 5422}
5423
5424int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5425 unsigned int bytes, struct x86_exception *exception)
5426{
c595ceee
PB		 5427 /* kvm_write_guest_virt_system can pull in tons of pages. */
5428 vcpu->arch.l1tf_flush_l1d = true;
5429
541ab2ae
FH		 5430 /*
5431 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5432 * is returned, but our callers are not ready for that and they blindly
5433 * call kvm_inject_page_fault. Ensure that they at least do not leak
5434 * uninitialized kernel stack memory into cr2 and error code.
5435 */
5436 memset(exception, 0, sizeof(*exception));
ce14e868
PB		 5437 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5438 PFERR_WRITE_MASK, exception);
5439}
6a4d7550 5440EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5441
082d06ed
WL		 5442int handle_ud(struct kvm_vcpu *vcpu)
5443{
6c86eedc 5444 int emul_type = EMULTYPE_TRAP_UD;
6c86eedc
WL		 5445 char sig[5]; /* ud2; .ascii "kvm" */
5446 struct x86_exception e;
5447
5448 if (force_emulation_prefix &&
3c9fa24c
PB		 5449 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5450 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 5451 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
5452 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
b4000606 5453 emul_type = EMULTYPE_TRAP_UD_FORCED;
6c86eedc 5454 }
082d06ed 5455
60fc3d02 5456 return kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5457}
5458EXPORT_SYMBOL_GPL(handle_ud);
5459
0f89b207
TL		 5460static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5461 gpa_t gpa, bool write)
5462{
5463 /* For APIC access vmexit */
5464 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5465 return 1;
5466
5467 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5468 trace_vcpu_match_mmio(gva, gpa, write, true);
5469 return 1;
5470 }
5471
5472 return 0;
5473}
5474
af7cc7d1
XG		 5475static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5476 gpa_t *gpa, struct x86_exception *exception,
5477 bool write)
5478{
97d64b78
AK		 5479 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5480 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5481
be94f6b7
HH		 5482 /*
5483 * currently PKRU is only applied to ept enabled guest so
5484 * there is no pkey in EPT page table for L1 guest or EPT
5485 * shadow page table for L2 guest.
5486 */
97d64b78 5487 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5488 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
871bd034 5489 vcpu->arch.mmio_access, 0, access)) {
bebb106a
XG		 5490 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5491 (gva & (PAGE_SIZE - 1));
4f022648 5492 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5493 return 1;
5494 }
5495
af7cc7d1
XG		 5496 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5497
5498 if (*gpa == UNMAPPED_GVA)
5499 return -1;
5500
0f89b207 5501 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5502}
5503
3200f405 5504int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5505 const void *val, int bytes)
bbd9b64e
CO		 5506{
5507 int ret;
5508
54bf36aa 5509 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5510 if (ret < 0)
bbd9b64e 5511 return 0;
0eb05bf2 5512 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5513 return 1;
5514}
5515
77d197b2
XG		 5516struct read_write_emulator_ops {
5517 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5518 int bytes);
5519 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5520 void *val, int bytes);
5521 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5522 int bytes, void *val);
5523 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5524 void *val, int bytes);
5525 bool write;
5526};
5527
5528static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5529{
5530 if (vcpu->mmio_read_completed) {
77d197b2 5531 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5532 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5533 vcpu->mmio_read_completed = 0;
5534 return 1;
5535 }
5536
5537 return 0;
5538}
5539
5540static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5541 void *val, int bytes)
5542{
54bf36aa 5543 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5544}
5545
5546static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5547 void *val, int bytes)
5548{
5549 return emulator_write_phys(vcpu, gpa, val, bytes);
5550}
5551
5552static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5553{
e39d200f 5554 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5555 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5556}
5557
5558static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5559 void *val, int bytes)
5560{
e39d200f 5561 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5562 return X86EMUL_IO_NEEDED;
5563}
5564
5565static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5566 void *val, int bytes)
5567{
f78146b0
AK		 5568 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5569
87da7e66 5570 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5571 return X86EMUL_CONTINUE;
5572}
5573
0fbe9b0b 5574static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5575 .read_write_prepare = read_prepare,
5576 .read_write_emulate = read_emulate,
5577 .read_write_mmio = vcpu_mmio_read,
5578 .read_write_exit_mmio = read_exit_mmio,
5579};
5580
0fbe9b0b 5581static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5582 .read_write_emulate = write_emulate,
5583 .read_write_mmio = write_mmio,
5584 .read_write_exit_mmio = write_exit_mmio,
5585 .write = true,
5586};
5587
22388a3c
XG		 5588static int emulator_read_write_onepage(unsigned long addr, void *val,
5589 unsigned int bytes,
5590 struct x86_exception *exception,
5591 struct kvm_vcpu *vcpu,
0fbe9b0b 5592 const struct read_write_emulator_ops *ops)
bbd9b64e 5593{
af7cc7d1
XG		 5594 gpa_t gpa;
5595 int handled, ret;
22388a3c 5596 bool write = ops->write;
f78146b0 5597 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5598 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5599
5600 /*
5601 * If the exit was due to a NPF we may already have a GPA.
5602 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5603 * Note, this cannot be used on string operations since string
5604 * operation using rep will only have the initial GPA from the NPF
5605 * occurred.
5606 */
5607 if (vcpu->arch.gpa_available &&
5608 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5609 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5610 gpa = vcpu->arch.gpa_val;
5611 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5612 } else {
5613 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5614 if (ret < 0)
5615 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5616 }
10589a46 5617
618232e2 5618 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5619 return X86EMUL_CONTINUE;
5620
bbd9b64e
CO		 5621 /*
5622 * Is this MMIO handled locally?
5623 */
22388a3c 5624 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5625 if (handled == bytes)
bbd9b64e 5626 return X86EMUL_CONTINUE;
bbd9b64e 5627
70252a10
AK		 5628 gpa += handled;
5629 bytes -= handled;
5630 val += handled;
5631
87da7e66
XG		 5632 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5633 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5634 frag->gpa = gpa;
5635 frag->data = val;
5636 frag->len = bytes;
f78146b0 5637 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5638}
5639
52eb5a6d
XL		 5640static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5641 unsigned long addr,
22388a3c
XG		 5642 void *val, unsigned int bytes,
5643 struct x86_exception *exception,
0fbe9b0b 5644 const struct read_write_emulator_ops *ops)
bbd9b64e 5645{
0f65dd70 5646 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5647 gpa_t gpa;
5648 int rc;
5649
5650 if (ops->read_write_prepare &&
5651 ops->read_write_prepare(vcpu, val, bytes))
5652 return X86EMUL_CONTINUE;
5653
5654 vcpu->mmio_nr_fragments = 0;
0f65dd70 5655
bbd9b64e
CO		 5656 /* Crossing a page boundary? */
5657 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5658 int now;
bbd9b64e
CO		 5659
5660 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5661 rc = emulator_read_write_onepage(addr, val, now, exception,
5662 vcpu, ops);
5663
bbd9b64e
CO		 5664 if (rc != X86EMUL_CONTINUE)
5665 return rc;
5666 addr += now;
bac15531
NA		 5667 if (ctxt->mode != X86EMUL_MODE_PROT64)
5668 addr = (u32)addr;
bbd9b64e
CO		 5669 val += now;
5670 bytes -= now;
5671 }
22388a3c 5672
f78146b0
AK		 5673 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5674 vcpu, ops);
5675 if (rc != X86EMUL_CONTINUE)
5676 return rc;
5677
5678 if (!vcpu->mmio_nr_fragments)
5679 return rc;
5680
5681 gpa = vcpu->mmio_fragments[0].gpa;
5682
5683 vcpu->mmio_needed = 1;
5684 vcpu->mmio_cur_fragment = 0;
5685
87da7e66 5686 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5687 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5688 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5689 vcpu->run->mmio.phys_addr = gpa;
5690
5691 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5692}
5693
5694static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5695 unsigned long addr,
5696 void *val,
5697 unsigned int bytes,
5698 struct x86_exception *exception)
5699{
5700 return emulator_read_write(ctxt, addr, val, bytes,
5701 exception, &read_emultor);
5702}
5703
52eb5a6d 5704static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5705 unsigned long addr,
5706 const void *val,
5707 unsigned int bytes,
5708 struct x86_exception *exception)
5709{
5710 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5711 exception, &write_emultor);
bbd9b64e 5712}
bbd9b64e 5713
daea3e73
AK		 5714#define CMPXCHG_TYPE(t, ptr, old, new) \
5715 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5716
5717#ifdef CONFIG_X86_64
5718# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5719#else
5720# define CMPXCHG64(ptr, old, new) \
9749a6c0 5721 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5722#endif
5723
0f65dd70
AK		 5724static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5725 unsigned long addr,
bbd9b64e
CO		 5726 const void *old,
5727 const void *new,
5728 unsigned int bytes,
0f65dd70 5729 struct x86_exception *exception)
bbd9b64e 5730{
42e35f80 5731 struct kvm_host_map map;
0f65dd70 5732 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73 5733 gpa_t gpa;
daea3e73
AK		 5734 char *kaddr;
5735 bool exchanged;
2bacc55c 5736
daea3e73
AK		 5737 /* guests cmpxchg8b have to be emulated atomically */
5738 if (bytes > 8 || (bytes & (bytes - 1)))
5739 goto emul_write;
10589a46 5740
daea3e73 5741 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5742
daea3e73
AK		 5743 if (gpa == UNMAPPED_GVA ||
5744 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5745 goto emul_write;
2bacc55c 5746
daea3e73
AK		 5747 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5748 goto emul_write;
72dc67a6 5749
42e35f80 5750 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
c19b8bd6 5751 goto emul_write;
72dc67a6 5752
42e35f80
KA		 5753 kaddr = map.hva + offset_in_page(gpa);
5754
daea3e73
AK		 5755 switch (bytes) {
5756 case 1:
5757 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5758 break;
5759 case 2:
5760 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5761 break;
5762 case 4:
5763 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5764 break;
5765 case 8:
5766 exchanged = CMPXCHG64(kaddr, old, new);
5767 break;
5768 default:
5769 BUG();
2bacc55c 5770 }
42e35f80
KA		 5771
5772 kvm_vcpu_unmap(vcpu, &map, true);
daea3e73
AK		 5773
5774 if (!exchanged)
5775 return X86EMUL_CMPXCHG_FAILED;
5776
0eb05bf2 5777 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5778
5779 return X86EMUL_CONTINUE;
4a5f48f6 5780
3200f405 5781emul_write:
daea3e73 5782 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5783
0f65dd70 5784 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5785}
5786
cf8f70bf
GN		 5787static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5788{
cbfc6c91 5789 int r = 0, i;
cf8f70bf 5790
cbfc6c91
WL		 5791 for (i = 0; i < vcpu->arch.pio.count; i++) {
5792 if (vcpu->arch.pio.in)
5793 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5794 vcpu->arch.pio.size, pd);
5795 else
5796 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5797 vcpu->arch.pio.port, vcpu->arch.pio.size,
5798 pd);
5799 if (r)
5800 break;
5801 pd += vcpu->arch.pio.size;
5802 }
cf8f70bf
GN		 5803 return r;
5804}
5805
6f6fbe98
XG		 5806static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5807 unsigned short port, void *val,
5808 unsigned int count, bool in)
cf8f70bf 5809{
cf8f70bf 5810 vcpu->arch.pio.port = port;
6f6fbe98 5811 vcpu->arch.pio.in = in;
7972995b 5812 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5813 vcpu->arch.pio.size = size;
5814
5815 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5816 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5817 return 1;
5818 }
5819
5820 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5821 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5822 vcpu->run->io.size = size;
5823 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5824 vcpu->run->io.count = count;
5825 vcpu->run->io.port = port;
5826
5827 return 0;
5828}
5829
6f6fbe98
XG		 5830static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5831 int size, unsigned short port, void *val,
5832 unsigned int count)
cf8f70bf 5833{
ca1d4a9e 5834 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5835 int ret;
ca1d4a9e 5836
6f6fbe98
XG		 5837 if (vcpu->arch.pio.count)
5838 goto data_avail;
cf8f70bf 5839
cbfc6c91
WL		 5840 memset(vcpu->arch.pio_data, 0, size * count);
5841
6f6fbe98
XG		 5842 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5843 if (ret) {
5844data_avail:
5845 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5846 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5847 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5848 return 1;
5849 }
5850
cf8f70bf
GN		 5851 return 0;
5852}
5853
6f6fbe98
XG		 5854static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5855 int size, unsigned short port,
5856 const void *val, unsigned int count)
5857{
5858 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5859
5860 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5861 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5862 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5863}
5864
bbd9b64e
CO		 5865static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5866{
5867 return kvm_x86_ops->get_segment_base(vcpu, seg);
5868}
5869
3cb16fe7 5870static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5871{
3cb16fe7 5872 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5873}
5874
ae6a2375 5875static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5876{
5877 if (!need_emulate_wbinvd(vcpu))
5878 return X86EMUL_CONTINUE;
5879
5880 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5881 int cpu = get_cpu();
5882
5883 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5884 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5885 wbinvd_ipi, NULL, 1);
2eec7343 5886 put_cpu();
f5f48ee1 5887 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5888 } else
5889 wbinvd();
f5f48ee1
SY		 5890 return X86EMUL_CONTINUE;
5891}
5cb56059
JS		 5892
5893int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5894{
6affcbed
KH		 5895 kvm_emulate_wbinvd_noskip(vcpu);
5896 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5897}
f5f48ee1
SY		 5898EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5899
5cb56059
JS		 5900
5901
bcaf5cc5
AK		 5902static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5903{
5cb56059 5904 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5905}
5906
52eb5a6d
XL		 5907static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5908 unsigned long *dest)
bbd9b64e 5909{
16f8a6f9 5910 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5911}
5912
52eb5a6d
XL		 5913static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5914 unsigned long value)
bbd9b64e 5915{
338dbc97 5916
717746e3 5917 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5918}
5919
52a46617 5920static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5921{
52a46617 5922 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5923}
5924
717746e3 5925static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5926{
717746e3 5927 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5928 unsigned long value;
5929
5930 switch (cr) {
5931 case 0:
5932 value = kvm_read_cr0(vcpu);
5933 break;
5934 case 2:
5935 value = vcpu->arch.cr2;
5936 break;
5937 case 3:
9f8fe504 5938 value = kvm_read_cr3(vcpu);
52a46617
GN		 5939 break;
5940 case 4:
5941 value = kvm_read_cr4(vcpu);
5942 break;
5943 case 8:
5944 value = kvm_get_cr8(vcpu);
5945 break;
5946 default:
a737f256 5947 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5948 return 0;
5949 }
5950
5951 return value;
5952}
5953
717746e3 5954static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5955{
717746e3 5956 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5957 int res = 0;
5958
52a46617
GN		 5959 switch (cr) {
5960 case 0:
49a9b07e 5961 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5962 break;
5963 case 2:
5964 vcpu->arch.cr2 = val;
5965 break;
5966 case 3:
2390218b 5967 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5968 break;
5969 case 4:
a83b29c6 5970 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5971 break;
5972 case 8:
eea1cff9 5973 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5974 break;
5975 default:
a737f256 5976 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5977 res = -1;
52a46617 5978 }
0f12244f
GN		 5979
5980 return res;
52a46617
GN		 5981}
5982
717746e3 5983static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5984{
717746e3 5985 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5986}
5987
4bff1e86 5988static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5989{
4bff1e86 5990 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5991}
5992
4bff1e86 5993static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5994{
4bff1e86 5995 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5996}
5997
1ac9d0cf
AK		 5998static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5999{
6000 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
6001}
6002
6003static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6004{
6005 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6006}
6007
4bff1e86
AK		 6008static unsigned long emulator_get_cached_segment_base(
6009 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 6010{
4bff1e86 6011 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 6012}
6013
1aa36616
AK		 6014static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6015 struct desc_struct *desc, u32 *base3,
6016 int seg)
2dafc6c2
GN		 6017{
6018 struct kvm_segment var;
6019
4bff1e86 6020 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 6021 *selector = var.selector;
2dafc6c2 6022
378a8b09
GN		 6023 if (var.unusable) {
6024 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 6025 if (base3)
6026 *base3 = 0;
2dafc6c2 6027 return false;
378a8b09 6028 }
2dafc6c2
GN		 6029
6030 if (var.g)
6031 var.limit >>= 12;
6032 set_desc_limit(desc, var.limit);
6033 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 6034#ifdef CONFIG_X86_64
6035 if (base3)
6036 *base3 = var.base >> 32;
6037#endif
2dafc6c2
GN		 6038 desc->type = var.type;
6039 desc->s = var.s;
6040 desc->dpl = var.dpl;
6041 desc->p = var.present;
6042 desc->avl = var.avl;
6043 desc->l = var.l;
6044 desc->d = var.db;
6045 desc->g = var.g;
6046
6047 return true;
6048}
6049
1aa36616
AK		 6050static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6051 struct desc_struct *desc, u32 base3,
6052 int seg)
2dafc6c2 6053{
4bff1e86 6054 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 6055 struct kvm_segment var;
6056
1aa36616 6057 var.selector = selector;
2dafc6c2 6058 var.base = get_desc_base(desc);
5601d05b
GN		 6059#ifdef CONFIG_X86_64
6060 var.base |= ((u64)base3) << 32;
6061#endif
2dafc6c2
GN		 6062 var.limit = get_desc_limit(desc);
6063 if (desc->g)
6064 var.limit = (var.limit << 12) | 0xfff;
6065 var.type = desc->type;
2dafc6c2
GN		 6066 var.dpl = desc->dpl;
6067 var.db = desc->d;
6068 var.s = desc->s;
6069 var.l = desc->l;
6070 var.g = desc->g;
6071 var.avl = desc->avl;
6072 var.present = desc->p;
6073 var.unusable = !var.present;
6074 var.padding = 0;
6075
6076 kvm_set_segment(vcpu, &var, seg);
6077 return;
6078}
6079
717746e3
AK		 6080static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6081 u32 msr_index, u64 *pdata)
6082{
f20935d8 6083 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
717746e3
AK		 6084}
6085
6086static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6087 u32 msr_index, u64 data)
6088{
f20935d8 6089 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
717746e3
AK		 6090}
6091
64d60670
PB		 6092static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6093{
6094 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6095
6096 return vcpu->arch.smbase;
6097}
6098
6099static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6100{
6101 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6102
6103 vcpu->arch.smbase = smbase;
6104}
6105
67f4d428
NA		 6106static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6107 u32 pmc)
6108{
c6702c9d 6109 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 6110}
6111
222d21aa
AK		 6112static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6113 u32 pmc, u64 *pdata)
6114{
c6702c9d 6115 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 6116}
6117
6c3287f7
AK		 6118static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6119{
6120 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6121}
6122
2953538e 6123static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 6124 struct x86_instruction_info *info,
c4f035c6
AK		 6125 enum x86_intercept_stage stage)
6126{
2953538e 6127 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 6128}
6129
e911eb3b
YZ		 6130static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6131 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 6132{
e911eb3b 6133 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 6134}
6135
dd856efa
AK		 6136static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6137{
6138 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6139}
6140
6141static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6142{
6143 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6144}
6145
801806d9
NA		 6146static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6147{
6148 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6149}
6150
6ed071f0
LP		 6151static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6152{
6153 return emul_to_vcpu(ctxt)->arch.hflags;
6154}
6155
6156static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6157{
c5833c7a 6158 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6ed071f0
LP		 6159}
6160
ed19321f
SC		 6161static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6162 const char *smstate)
0234bf88 6163{
ed19321f 6164 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
0234bf88
LP		 6165}
6166
c5833c7a
SC		 6167static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6168{
6169 kvm_smm_changed(emul_to_vcpu(ctxt));
6170}
6171
02d4160f
VK		 6172static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6173{
6174 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6175}
6176
0225fb50 6177static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 6178 .read_gpr = emulator_read_gpr,
6179 .write_gpr = emulator_write_gpr,
ce14e868
PB		 6180 .read_std = emulator_read_std,
6181 .write_std = emulator_write_std,
7a036a6f 6182 .read_phys = kvm_read_guest_phys_system,
1871c602 6183 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 6184 .read_emulated = emulator_read_emulated,
6185 .write_emulated = emulator_write_emulated,
6186 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 6187 .invlpg = emulator_invlpg,
cf8f70bf
GN		 6188 .pio_in_emulated = emulator_pio_in_emulated,
6189 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 6190 .get_segment = emulator_get_segment,
6191 .set_segment = emulator_set_segment,
5951c442 6192 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 6193 .get_gdt = emulator_get_gdt,
160ce1f1 6194 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 6195 .set_gdt = emulator_set_gdt,
6196 .set_idt = emulator_set_idt,
52a46617
GN		 6197 .get_cr = emulator_get_cr,
6198 .set_cr = emulator_set_cr,
9c537244 6199 .cpl = emulator_get_cpl,
35aa5375
GN		 6200 .get_dr = emulator_get_dr,
6201 .set_dr = emulator_set_dr,
64d60670
PB		 6202 .get_smbase = emulator_get_smbase,
6203 .set_smbase = emulator_set_smbase,
717746e3
AK		 6204 .set_msr = emulator_set_msr,
6205 .get_msr = emulator_get_msr,
67f4d428 6206 .check_pmc = emulator_check_pmc,
222d21aa 6207 .read_pmc = emulator_read_pmc,
6c3287f7 6208 .halt = emulator_halt,
bcaf5cc5 6209 .wbinvd = emulator_wbinvd,
d6aa1000 6210 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 6211 .intercept = emulator_intercept,
bdb42f5a 6212 .get_cpuid = emulator_get_cpuid,
801806d9 6213 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 6214 .get_hflags = emulator_get_hflags,
6215 .set_hflags = emulator_set_hflags,
0234bf88 6216 .pre_leave_smm = emulator_pre_leave_smm,
c5833c7a 6217 .post_leave_smm = emulator_post_leave_smm,
02d4160f 6218 .set_xcr = emulator_set_xcr,
bbd9b64e
CO		 6219};
6220
95cb2295
GN		 6221static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6222{
37ccdcbe 6223 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 6224 /*
6225 * an sti; sti; sequence only disable interrupts for the first
6226 * instruction. So, if the last instruction, be it emulated or
6227 * not, left the system with the INT_STI flag enabled, it
6228 * means that the last instruction is an sti. We should not
6229 * leave the flag on in this case. The same goes for mov ss
6230 */
37ccdcbe
PB		 6231 if (int_shadow & mask)
6232 mask = 0;
6addfc42 6233 if (unlikely(int_shadow || mask)) {
95cb2295 6234 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 6235 if (!mask)
6236 kvm_make_request(KVM_REQ_EVENT, vcpu);
6237 }
95cb2295
GN		 6238}
6239
ef54bcfe 6240static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 6241{
6242 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 6243 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 6244 return kvm_propagate_fault(vcpu, &ctxt->exception);
6245
6246 if (ctxt->exception.error_code_valid)
da9cb575
AK		 6247 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6248 ctxt->exception.error_code);
54b8486f 6249 else
da9cb575 6250 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 6251 return false;
54b8486f
GN		 6252}
6253
8ec4722d
MG		 6254static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6255{
adf52235 6256 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 6257 int cs_db, cs_l;
6258
8ec4722d
MG		 6259 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6260
adf52235 6261 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 6262 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6263
adf52235
TY		 6264 ctxt->eip = kvm_rip_read(vcpu);
6265 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6266 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6267 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6268 cs_db ? X86EMUL_MODE_PROT32 :
6269 X86EMUL_MODE_PROT16;
a584539b 6270 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6271 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6272 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6273
dd856efa 6274 init_decode_cache(ctxt);
7ae441ea 6275 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6276}
6277
9497e1f2 6278void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6279{
9d74191a 6280 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6281 int ret;
6282
6283 init_emulate_ctxt(vcpu);
6284
9dac77fa
AK		 6285 ctxt->op_bytes = 2;
6286 ctxt->ad_bytes = 2;
6287 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6288 ret = emulate_int_real(ctxt, irq);
63995653 6289
9497e1f2
SC		 6290 if (ret != X86EMUL_CONTINUE) {
6291 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6292 } else {
6293 ctxt->eip = ctxt->_eip;
6294 kvm_rip_write(vcpu, ctxt->eip);
6295 kvm_set_rflags(vcpu, ctxt->eflags);
6296 }
63995653
MG		 6297}
6298EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6299
e2366171 6300static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6301{
6d77dbfc
GN		 6302 ++vcpu->stat.insn_emulation_fail;
6303 trace_kvm_emulate_insn_failed(vcpu);
e2366171 6304
42cbf068
SC		 6305 if (emulation_type & EMULTYPE_VMWARE_GP) {
6306 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
60fc3d02 6307 return 1;
42cbf068 6308 }
e2366171 6309
738fece4
SC		 6310 if (emulation_type & EMULTYPE_SKIP) {
6311 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6312 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6313 vcpu->run->internal.ndata = 0;
60fc3d02 6314 return 0;
738fece4
SC		 6315 }
6316
22da61c9
SC		 6317 kvm_queue_exception(vcpu, UD_VECTOR);
6318
a2b9e6c1 6319 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6320 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6321 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6322 vcpu->run->internal.ndata = 0;
60fc3d02 6323 return 0;
fc3a9157 6324 }
e2366171 6325
60fc3d02 6326 return 1;
6d77dbfc
GN		 6327}
6328
93c05d3e 6329static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 6330 bool write_fault_to_shadow_pgtable,
6331 int emulation_type)
a6f177ef 6332{
95b3cf69 6333 gpa_t gpa = cr2;
ba049e93 6334 kvm_pfn_t pfn;
a6f177ef 6335
384bf221 6336 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6337 return false;
6338
6c3dfeb6
SC		 6339 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6340 return false;
6341
44dd3ffa 6342 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6343 /*
6344 * Write permission should be allowed since only
6345 * write access need to be emulated.
6346 */
6347 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 6348
95b3cf69
XG		 6349 /*
6350 * If the mapping is invalid in guest, let cpu retry
6351 * it to generate fault.
6352 */
6353 if (gpa == UNMAPPED_GVA)
6354 return true;
6355 }
a6f177ef 6356
8e3d9d06
XG		 6357 /*
6358 * Do not retry the unhandleable instruction if it faults on the
6359 * readonly host memory, otherwise it will goto a infinite loop:
6360 * retry instruction -> write #PF -> emulation fail -> retry
6361 * instruction -> ...
6362 */
6363 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6364
6365 /*
6366 * If the instruction failed on the error pfn, it can not be fixed,
6367 * report the error to userspace.
6368 */
6369 if (is_error_noslot_pfn(pfn))
6370 return false;
6371
6372 kvm_release_pfn_clean(pfn);
6373
6374 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6375 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6376 unsigned int indirect_shadow_pages;
6377
6378 spin_lock(&vcpu->kvm->mmu_lock);
6379 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6380 spin_unlock(&vcpu->kvm->mmu_lock);
6381
6382 if (indirect_shadow_pages)
6383 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6384
a6f177ef 6385 return true;
8e3d9d06 6386 }
a6f177ef 6387
95b3cf69
XG		 6388 /*
6389 * if emulation was due to access to shadowed page table
6390 * and it failed try to unshadow page and re-enter the
6391 * guest to let CPU execute the instruction.
6392 */
6393 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6394
6395 /*
6396 * If the access faults on its page table, it can not
6397 * be fixed by unprotecting shadow page and it should
6398 * be reported to userspace.
6399 */
6400 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6401}
6402
1cb3f3ae
XG		 6403static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
6404 unsigned long cr2, int emulation_type)
6405{
6406 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6407 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
6408
6409 last_retry_eip = vcpu->arch.last_retry_eip;
6410 last_retry_addr = vcpu->arch.last_retry_addr;
6411
6412 /*
6413 * If the emulation is caused by #PF and it is non-page_table
6414 * writing instruction, it means the VM-EXIT is caused by shadow
6415 * page protected, we can zap the shadow page and retry this
6416 * instruction directly.
6417 *
6418 * Note: if the guest uses a non-page-table modifying instruction
6419 * on the PDE that points to the instruction, then we will unmap
6420 * the instruction and go to an infinite loop. So, we cache the
6421 * last retried eip and the last fault address, if we meet the eip
6422 * and the address again, we can break out of the potential infinite
6423 * loop.
6424 */
6425 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6426
384bf221 6427 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6428 return false;
6429
6c3dfeb6
SC		 6430 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6431 return false;
6432
1cb3f3ae
XG		 6433 if (x86_page_table_writing_insn(ctxt))
6434 return false;
6435
6436 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
6437 return false;
6438
6439 vcpu->arch.last_retry_eip = ctxt->eip;
6440 vcpu->arch.last_retry_addr = cr2;
6441
44dd3ffa 6442 if (!vcpu->arch.mmu->direct_map)
1cb3f3ae
XG		 6443 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
6444
22368028 6445 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6446
6447 return true;
6448}
6449
716d51ab
GN		 6450static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6451static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6452
64d60670 6453static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6454{
64d60670 6455 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6456 /* This is a good place to trace that we are exiting SMM. */
6457 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6458
c43203ca
PB		 6459 /* Process a latched INIT or SMI, if any. */
6460 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6461 }
699023e2
PB		 6462
6463 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6464}
6465
4a1e10d5
PB		 6466static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6467 unsigned long *db)
6468{
6469 u32 dr6 = 0;
6470 int i;
6471 u32 enable, rwlen;
6472
6473 enable = dr7;
6474 rwlen = dr7 >> 16;
6475 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6476 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6477 dr6 |= (1 << i);
6478 return dr6;
6479}
6480
120c2c4f 6481static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
663f4c61
PB		 6482{
6483 struct kvm_run *kvm_run = vcpu->run;
6484
c8401dda
PB		 6485 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6486 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6487 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6488 kvm_run->debug.arch.exception = DB_VECTOR;
6489 kvm_run->exit_reason = KVM_EXIT_DEBUG;
60fc3d02 6490 return 0;
663f4c61 6491 }
120c2c4f 6492 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
60fc3d02 6493 return 1;
663f4c61
PB		 6494}
6495
6affcbed
KH		 6496int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6497{
6498 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
f8ea7c60 6499 int r;
6affcbed 6500
f8ea7c60 6501 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
60fc3d02 6502 if (unlikely(!r))
f8ea7c60 6503 return 0;
c8401dda
PB		 6504
6505 /*
6506 * rflags is the old, "raw" value of the flags. The new value has
6507 * not been saved yet.
6508 *
6509 * This is correct even for TF set by the guest, because "the
6510 * processor will not generate this exception after the instruction
6511 * that sets the TF flag".
6512 */
6513 if (unlikely(rflags & X86_EFLAGS_TF))
120c2c4f 6514 r = kvm_vcpu_do_singlestep(vcpu);
60fc3d02 6515 return r;
6affcbed
KH		 6516}
6517EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6518
4a1e10d5
PB		 6519static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6520{
4a1e10d5
PB		 6521 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6522 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6523 struct kvm_run *kvm_run = vcpu->run;
6524 unsigned long eip = kvm_get_linear_rip(vcpu);
6525 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6526 vcpu->arch.guest_debug_dr7,
6527 vcpu->arch.eff_db);
6528
6529 if (dr6 != 0) {
6f43ed01 6530 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6531 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6532 kvm_run->debug.arch.exception = DB_VECTOR;
6533 kvm_run->exit_reason = KVM_EXIT_DEBUG;
60fc3d02 6534 *r = 0;
4a1e10d5
PB		 6535 return true;
6536 }
6537 }
6538
4161a569
NA		 6539 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6540 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6541 unsigned long eip = kvm_get_linear_rip(vcpu);
6542 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6543 vcpu->arch.dr7,
6544 vcpu->arch.db);
6545
6546 if (dr6 != 0) {
1fc5d194 6547 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 6548 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5 6549 kvm_queue_exception(vcpu, DB_VECTOR);
60fc3d02 6550 *r = 1;
4a1e10d5
PB		 6551 return true;
6552 }
6553 }
6554
6555 return false;
6556}
6557
04789b66
LA		 6558static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6559{
2d7921c4
AM		 6560 switch (ctxt->opcode_len) {
6561 case 1:
6562 switch (ctxt->b) {
6563 case 0xe4: /* IN */
6564 case 0xe5:
6565 case 0xec:
6566 case 0xed:
6567 case 0xe6: /* OUT */
6568 case 0xe7:
6569 case 0xee:
6570 case 0xef:
6571 case 0x6c: /* INS */
6572 case 0x6d:
6573 case 0x6e: /* OUTS */
6574 case 0x6f:
6575 return true;
6576 }
6577 break;
6578 case 2:
6579 switch (ctxt->b) {
6580 case 0x33: /* RDPMC */
6581 return true;
6582 }
6583 break;
04789b66
LA		 6584 }
6585
6586 return false;
6587}
6588
51d8b661
AP		 6589int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6590 unsigned long cr2,
dc25e89e
AP		 6591 int emulation_type,
6592 void *insn,
6593 int insn_len)
bbd9b64e 6594{
95cb2295 6595 int r;
9d74191a 6596 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6597 bool writeback = true;
93c05d3e 6598 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6599
c595ceee
PB		 6600 vcpu->arch.l1tf_flush_l1d = true;
6601
93c05d3e
XG		 6602 /*
6603 * Clear write_fault_to_shadow_pgtable here to ensure it is
6604 * never reused.
6605 */
6606 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6607 kvm_clear_exception_queue(vcpu);
8d7d8102 6608
571008da 6609 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6610 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6611
6612 /*
6613 * We will reenter on the same instruction since
6614 * we do not set complete_userspace_io. This does not
6615 * handle watchpoints yet, those would be handled in
6616 * the emulate_ops.
6617 */
d391f120
VK		 6618 if (!(emulation_type & EMULTYPE_SKIP) &&
6619 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6620 return r;
6621
9d74191a
TY		 6622 ctxt->interruptibility = 0;
6623 ctxt->have_exception = false;
e0ad0b47 6624 ctxt->exception.vector = -1;
9d74191a 6625 ctxt->perm_ok = false;
bbd9b64e 6626
b51e974f 6627 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6628
9d74191a 6629 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6630
e46479f8 6631 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6632 ++vcpu->stat.insn_emulation;
1d2887e2 6633 if (r != EMULATION_OK) {
b4000606 6634 if ((emulation_type & EMULTYPE_TRAP_UD) ||
c83fad65
SC		 6635 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6636 kvm_queue_exception(vcpu, UD_VECTOR);
60fc3d02 6637 return 1;
c83fad65 6638 }
991eebf9
GN		 6639 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6640 emulation_type))
60fc3d02 6641 return 1;
8530a79c 6642 if (ctxt->have_exception) {
c8848cee
JD		 6643 /*
6644 * #UD should result in just EMULATION_FAILED, and trap-like
6645 * exception should not be encountered during decode.
6646 */
6647 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6648 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8530a79c 6649 inject_emulated_exception(vcpu);
60fc3d02 6650 return 1;
8530a79c 6651 }
e2366171 6652 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6653 }
6654 }
6655
42cbf068
SC		 6656 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6657 !is_vmware_backdoor_opcode(ctxt)) {
6658 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
60fc3d02 6659 return 1;
42cbf068 6660 }
04789b66 6661
1957aa63
SC		 6662 /*
6663 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6664 * for kvm_skip_emulated_instruction(). The caller is responsible for
6665 * updating interruptibility state and injecting single-step #DBs.
6666 */
ba8afb6b 6667 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6668 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6669 if (ctxt->eflags & X86_EFLAGS_RF)
6670 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
60fc3d02 6671 return 1;
ba8afb6b
GN		 6672 }
6673
1cb3f3ae 6674 if (retry_instruction(ctxt, cr2, emulation_type))
60fc3d02 6675 return 1;
1cb3f3ae 6676
7ae441ea 6677 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6678 changes registers values during IO operation */
7ae441ea
GN		 6679 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6680 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6681 emulator_invalidate_register_cache(ctxt);
7ae441ea 6682 }
4d2179e1 6683
5cd21917 6684restart:
0f89b207
TL		 6685 /* Save the faulting GPA (cr2) in the address field */
6686 ctxt->exception.address = cr2;
6687
9d74191a 6688 r = x86_emulate_insn(ctxt);
bbd9b64e 6689
775fde86 6690 if (r == EMULATION_INTERCEPTED)
60fc3d02 6691 return 1;
775fde86 6692
d2ddd1c4 6693 if (r == EMULATION_FAILED) {
991eebf9
GN		 6694 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6695 emulation_type))
60fc3d02 6696 return 1;
c3cd7ffa 6697
e2366171 6698 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6699 }
6700
9d74191a 6701 if (ctxt->have_exception) {
60fc3d02 6702 r = 1;
ef54bcfe
PB		 6703 if (inject_emulated_exception(vcpu))
6704 return r;
d2ddd1c4 6705 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6706 if (!vcpu->arch.pio.in) {
6707 /* FIXME: return into emulator if single-stepping. */
3457e419 6708 vcpu->arch.pio.count = 0;
0912c977 6709 } else {
7ae441ea 6710 writeback = false;
716d51ab
GN		 6711 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6712 }
60fc3d02 6713 r = 0;
7ae441ea 6714 } else if (vcpu->mmio_needed) {
bc8a0aaf
SC		 6715 ++vcpu->stat.mmio_exits;
6716
7ae441ea
GN		 6717 if (!vcpu->mmio_is_write)
6718 writeback = false;
60fc3d02 6719 r = 0;
716d51ab 6720 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6721 } else if (r == EMULATION_RESTART)
5cd21917 6722 goto restart;
d2ddd1c4 6723 else
60fc3d02 6724 r = 1;
f850e2e6 6725
7ae441ea 6726 if (writeback) {
6addfc42 6727 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6728 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6729 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
38827dbd 6730 if (!ctxt->have_exception ||
75ee23b3
SC		 6731 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6732 kvm_rip_write(vcpu, ctxt->eip);
60fc3d02 6733 if (r && ctxt->tf)
120c2c4f 6734 r = kvm_vcpu_do_singlestep(vcpu);
38827dbd 6735 __kvm_set_rflags(vcpu, ctxt->eflags);
75ee23b3 6736 }
6addfc42
PB		 6737
6738 /*
6739 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6740 * do nothing, and it will be requested again as soon as
6741 * the shadow expires. But we still need to check here,
6742 * because POPF has no interrupt shadow.
6743 */
6744 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6745 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6746 } else
6747 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6748
6749 return r;
de7d789a 6750}
c60658d1
SC		 6751
6752int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6753{
6754 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6755}
6756EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6757
6758int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6759 void *insn, int insn_len)
6760{
6761 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6762}
6763EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6764
8764ed55
SC		 6765static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6766{
6767 vcpu->arch.pio.count = 0;
6768 return 1;
6769}
6770
45def77e
SC		 6771static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6772{
6773 vcpu->arch.pio.count = 0;
6774
6775 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6776 return 1;
6777
6778 return kvm_skip_emulated_instruction(vcpu);
6779}
6780
dca7f128
SC		 6781static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6782 unsigned short port)
de7d789a 6783{
de3cd117 6784 unsigned long val = kvm_rax_read(vcpu);
ca1d4a9e
AK		 6785 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6786 size, port, &val, 1);
8764ed55
SC		 6787 if (ret)
6788 return ret;
45def77e 6789
8764ed55
SC		 6790 /*
6791 * Workaround userspace that relies on old KVM behavior of %rip being
6792 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6793 */
6794 if (port == 0x7e &&
6795 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6796 vcpu->arch.complete_userspace_io =
6797 complete_fast_pio_out_port_0x7e;
6798 kvm_skip_emulated_instruction(vcpu);
6799 } else {
45def77e
SC		 6800 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6801 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6802 }
8764ed55 6803 return 0;
de7d789a 6804}
de7d789a 6805
8370c3d0
TL		 6806static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6807{
6808 unsigned long val;
6809
6810 /* We should only ever be called with arch.pio.count equal to 1 */
6811 BUG_ON(vcpu->arch.pio.count != 1);
6812
45def77e
SC		 6813 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6814 vcpu->arch.pio.count = 0;
6815 return 1;
6816 }
6817
8370c3d0 6818 /* For size less than 4 we merge, else we zero extend */
de3cd117 6819 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6820
6821 /*
6822 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6823 * the copy and tracing
6824 */
6825 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6826 vcpu->arch.pio.port, &val, 1);
de3cd117 6827 kvm_rax_write(vcpu, val);
8370c3d0 6828
45def77e 6829 return kvm_skip_emulated_instruction(vcpu);
8370c3d0
TL		 6830}
6831
dca7f128
SC		 6832static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6833 unsigned short port)
8370c3d0
TL		 6834{
6835 unsigned long val;
6836 int ret;
6837
6838 /* For size less than 4 we merge, else we zero extend */
de3cd117 6839 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6840
6841 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6842 &val, 1);
6843 if (ret) {
de3cd117 6844 kvm_rax_write(vcpu, val);
8370c3d0
TL		 6845 return ret;
6846 }
6847
45def77e 6848 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8370c3d0
TL		 6849 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6850
6851 return 0;
6852}
dca7f128
SC		 6853
6854int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6855{
45def77e 6856 int ret;
dca7f128 6857
dca7f128 6858 if (in)
45def77e 6859 ret = kvm_fast_pio_in(vcpu, size, port);
dca7f128 6860 else
45def77e
SC		 6861 ret = kvm_fast_pio_out(vcpu, size, port);
6862 return ret && kvm_skip_emulated_instruction(vcpu);
dca7f128
SC		 6863}
6864EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6865
251a5fd6 6866static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6867{
0a3aee0d 6868 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6869 return 0;
8cfdc000
ZA		 6870}
6871
6872static void tsc_khz_changed(void *data)
c8076604 6873{
8cfdc000
ZA		 6874 struct cpufreq_freqs *freq = data;
6875 unsigned long khz = 0;
6876
6877 if (data)
6878 khz = freq->new;
6879 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6880 khz = cpufreq_quick_get(raw_smp_processor_id());
6881 if (!khz)
6882 khz = tsc_khz;
0a3aee0d 6883 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6884}
6885
5fa4ec9c 6886#ifdef CONFIG_X86_64
0092e434
VK		 6887static void kvm_hyperv_tsc_notifier(void)
6888{
0092e434
VK		 6889 struct kvm *kvm;
6890 struct kvm_vcpu *vcpu;
6891 int cpu;
6892
0d9ce162 6893 mutex_lock(&kvm_lock);
0092e434
VK		 6894 list_for_each_entry(kvm, &vm_list, vm_list)
6895 kvm_make_mclock_inprogress_request(kvm);
6896
6897 hyperv_stop_tsc_emulation();
6898
6899 /* TSC frequency always matches when on Hyper-V */
6900 for_each_present_cpu(cpu)
6901 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6902 kvm_max_guest_tsc_khz = tsc_khz;
6903
6904 list_for_each_entry(kvm, &vm_list, vm_list) {
6905 struct kvm_arch *ka = &kvm->arch;
6906
6907 spin_lock(&ka->pvclock_gtod_sync_lock);
6908
6909 pvclock_update_vm_gtod_copy(kvm);
6910
6911 kvm_for_each_vcpu(cpu, vcpu, kvm)
6912 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6913
6914 kvm_for_each_vcpu(cpu, vcpu, kvm)
6915 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6916
6917 spin_unlock(&ka->pvclock_gtod_sync_lock);
6918 }
0d9ce162 6919 mutex_unlock(&kvm_lock);
0092e434 6920}
5fa4ec9c 6921#endif
0092e434 6922
df24014a 6923static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
c8076604 6924{
c8076604
GH		 6925 struct kvm *kvm;
6926 struct kvm_vcpu *vcpu;
6927 int i, send_ipi = 0;
6928
8cfdc000
ZA		 6929 /*
6930 * We allow guests to temporarily run on slowing clocks,
6931 * provided we notify them after, or to run on accelerating
6932 * clocks, provided we notify them before. Thus time never
6933 * goes backwards.
6934 *
6935 * However, we have a problem. We can't atomically update
6936 * the frequency of a given CPU from this function; it is
6937 * merely a notifier, which can be called from any CPU.
6938 * Changing the TSC frequency at arbitrary points in time
6939 * requires a recomputation of local variables related to
6940 * the TSC for each VCPU. We must flag these local variables
6941 * to be updated and be sure the update takes place with the
6942 * new frequency before any guests proceed.
6943 *
6944 * Unfortunately, the combination of hotplug CPU and frequency
6945 * change creates an intractable locking scenario; the order
6946 * of when these callouts happen is undefined with respect to
6947 * CPU hotplug, and they can race with each other. As such,
6948 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6949 * undefined; you can actually have a CPU frequency change take
6950 * place in between the computation of X and the setting of the
6951 * variable. To protect against this problem, all updates of
6952 * the per_cpu tsc_khz variable are done in an interrupt
6953 * protected IPI, and all callers wishing to update the value
6954 * must wait for a synchronous IPI to complete (which is trivial
6955 * if the caller is on the CPU already). This establishes the
6956 * necessary total order on variable updates.
6957 *
6958 * Note that because a guest time update may take place
6959 * anytime after the setting of the VCPU's request bit, the
6960 * correct TSC value must be set before the request. However,
6961 * to ensure the update actually makes it to any guest which
6962 * starts running in hardware virtualization between the set
6963 * and the acquisition of the spinlock, we must also ping the
6964 * CPU after setting the request bit.
6965 *
6966 */
6967
df24014a 6968 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6969
0d9ce162 6970 mutex_lock(&kvm_lock);
c8076604 6971 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6972 kvm_for_each_vcpu(i, vcpu, kvm) {
df24014a 6973 if (vcpu->cpu != cpu)
c8076604 6974 continue;
c285545f 6975 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0d9ce162 6976 if (vcpu->cpu != raw_smp_processor_id())
8cfdc000 6977 send_ipi = 1;
c8076604
GH		 6978 }
6979 }
0d9ce162 6980 mutex_unlock(&kvm_lock);
c8076604
GH		 6981
6982 if (freq->old < freq->new && send_ipi) {
6983 /*
6984 * We upscale the frequency. Must make the guest
6985 * doesn't see old kvmclock values while running with
6986 * the new frequency, otherwise we risk the guest sees
6987 * time go backwards.
6988 *
6989 * In case we update the frequency for another cpu
6990 * (which might be in guest context) send an interrupt
6991 * to kick the cpu out of guest context. Next time
6992 * guest context is entered kvmclock will be updated,
6993 * so the guest will not see stale values.
6994 */
df24014a 6995 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 6996 }
df24014a
VK		 6997}
6998
6999static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7000 void *data)
7001{
7002 struct cpufreq_freqs *freq = data;
7003 int cpu;
7004
7005 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7006 return 0;
7007 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7008 return 0;
7009
7010 for_each_cpu(cpu, freq->policy->cpus)
7011 __kvmclock_cpufreq_notifier(freq, cpu);
7012
c8076604
GH		 7013 return 0;
7014}
7015
7016static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 7017 .notifier_call = kvmclock_cpufreq_notifier
7018};
7019
251a5fd6 7020static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 7021{
251a5fd6
SAS		 7022 tsc_khz_changed(NULL);
7023 return 0;
8cfdc000
ZA		 7024}
7025
b820cc0c
ZA		 7026static void kvm_timer_init(void)
7027{
c285545f 7028 max_tsc_khz = tsc_khz;
460dd42e 7029
b820cc0c 7030 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 7031#ifdef CONFIG_CPU_FREQ
7032 struct cpufreq_policy policy;
758f588d
BP		 7033 int cpu;
7034
c285545f 7035 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 7036 cpu = get_cpu();
7037 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 7038 if (policy.cpuinfo.max_freq)
7039 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 7040 put_cpu();
c285545f 7041#endif
b820cc0c
ZA		 7042 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7043 CPUFREQ_TRANSITION_NOTIFIER);
7044 }
460dd42e 7045
73c1b41e 7046 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 7047 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 7048}
7049
dd60d217
AK		 7050DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7051EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 7052
f5132b01 7053int kvm_is_in_guest(void)
ff9d07a0 7054{
086c9855 7055 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 7056}
7057
7058static int kvm_is_user_mode(void)
7059{
7060 int user_mode = 3;
dcf46b94 7061
086c9855
AS		 7062 if (__this_cpu_read(current_vcpu))
7063 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 7064
ff9d07a0
ZY		 7065 return user_mode != 0;
7066}
7067
7068static unsigned long kvm_get_guest_ip(void)
7069{
7070 unsigned long ip = 0;
dcf46b94 7071
086c9855
AS		 7072 if (__this_cpu_read(current_vcpu))
7073 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 7074
ff9d07a0
ZY		 7075 return ip;
7076}
7077
8479e04e
LK		 7078static void kvm_handle_intel_pt_intr(void)
7079{
7080 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7081
7082 kvm_make_request(KVM_REQ_PMI, vcpu);
7083 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7084 (unsigned long *)&vcpu->arch.pmu.global_status);
7085}
7086
ff9d07a0
ZY		 7087static struct perf_guest_info_callbacks kvm_guest_cbs = {
7088 .is_in_guest = kvm_is_in_guest,
7089 .is_user_mode = kvm_is_user_mode,
7090 .get_guest_ip = kvm_get_guest_ip,
8479e04e 7091 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
ff9d07a0
ZY		 7092};
7093
16e8d74d
MT		 7094#ifdef CONFIG_X86_64
7095static void pvclock_gtod_update_fn(struct work_struct *work)
7096{
d828199e
MT		 7097 struct kvm *kvm;
7098
7099 struct kvm_vcpu *vcpu;
7100 int i;
7101
0d9ce162 7102 mutex_lock(&kvm_lock);
d828199e
MT		 7103 list_for_each_entry(kvm, &vm_list, vm_list)
7104 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 7105 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 7106 atomic_set(&kvm_guest_has_master_clock, 0);
0d9ce162 7107 mutex_unlock(&kvm_lock);
16e8d74d
MT		 7108}
7109
7110static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7111
7112/*
7113 * Notification about pvclock gtod data update.
7114 */
7115static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7116 void *priv)
7117{
7118 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7119 struct timekeeper *tk = priv;
7120
7121 update_pvclock_gtod(tk);
7122
7123 /* disable master clock if host does not trust, or does not
b0c39dc6 7124 * use, TSC based clocksource.
16e8d74d 7125 */
b0c39dc6 7126 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 7127 atomic_read(&kvm_guest_has_master_clock) != 0)
7128 queue_work(system_long_wq, &pvclock_gtod_work);
7129
7130 return 0;
7131}
7132
7133static struct notifier_block pvclock_gtod_notifier = {
7134 .notifier_call = pvclock_gtod_notify,
7135};
7136#endif
7137
f8c16bba 7138int kvm_arch_init(void *opaque)
043405e1 7139{
b820cc0c 7140 int r;
6b61edf7 7141 struct kvm_x86_ops *ops = opaque;
f8c16bba 7142
f8c16bba
ZX		 7143 if (kvm_x86_ops) {
7144 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 7145 r = -EEXIST;
7146 goto out;
f8c16bba
ZX		 7147 }
7148
7149 if (!ops->cpu_has_kvm_support()) {
7150 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 7151 r = -EOPNOTSUPP;
7152 goto out;
f8c16bba
ZX		 7153 }
7154 if (ops->disabled_by_bios()) {
7155 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 7156 r = -EOPNOTSUPP;
7157 goto out;
f8c16bba
ZX		 7158 }
7159
b666a4b6
MO		 7160 /*
7161 * KVM explicitly assumes that the guest has an FPU and
7162 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7163 * vCPU's FPU state as a fxregs_state struct.
7164 */
7165 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7166 printk(KERN_ERR "kvm: inadequate fpu\n");
7167 r = -EOPNOTSUPP;
7168 goto out;
7169 }
7170
013f6a5d 7171 r = -ENOMEM;
ed8e4812 7172 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 7173 __alignof__(struct fpu), SLAB_ACCOUNT,
7174 NULL);
7175 if (!x86_fpu_cache) {
7176 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7177 goto out;
7178 }
7179
013f6a5d
MT		 7180 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7181 if (!shared_msrs) {
7182 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 7183 goto out_free_x86_fpu_cache;
013f6a5d
MT		 7184 }
7185
97db56ce
AK		 7186 r = kvm_mmu_module_init();
7187 if (r)
013f6a5d 7188 goto out_free_percpu;
97db56ce 7189
f8c16bba 7190 kvm_x86_ops = ops;
920c8377 7191
7b52345e 7192 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 7193 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 7194 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 7195 kvm_timer_init();
c8076604 7196
ff9d07a0
ZY		 7197 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7198
d366bf7e 7199 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 7200 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7201
c5cc421b 7202 kvm_lapic_init();
0c5f81da
WL		 7203 if (pi_inject_timer == -1)
7204 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
16e8d74d
MT		 7205#ifdef CONFIG_X86_64
7206 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 7207
5fa4ec9c 7208 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 7209 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 7210#endif
7211
f8c16bba 7212 return 0;
56c6d28a 7213
013f6a5d
MT		 7214out_free_percpu:
7215 free_percpu(shared_msrs);
b666a4b6
MO		 7216out_free_x86_fpu_cache:
7217 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7218out:
56c6d28a 7219 return r;
043405e1 7220}
8776e519 7221
f8c16bba
ZX		 7222void kvm_arch_exit(void)
7223{
0092e434 7224#ifdef CONFIG_X86_64
5fa4ec9c 7225 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 7226 clear_hv_tscchange_cb();
7227#endif
cef84c30 7228 kvm_lapic_exit();
ff9d07a0
ZY		 7229 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7230
888d256e
JK		 7231 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7232 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7233 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 7234 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 7235#ifdef CONFIG_X86_64
7236 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7237#endif
f8c16bba 7238 kvm_x86_ops = NULL;
56c6d28a 7239 kvm_mmu_module_exit();
013f6a5d 7240 free_percpu(shared_msrs);
b666a4b6 7241 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7242}
f8c16bba 7243
5cb56059 7244int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 7245{
7246 ++vcpu->stat.halt_exits;
35754c98 7247 if (lapic_in_kernel(vcpu)) {
a4535290 7248 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 7249 return 1;
7250 } else {
7251 vcpu->run->exit_reason = KVM_EXIT_HLT;
7252 return 0;
7253 }
7254}
5cb56059
JS		 7255EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7256
7257int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7258{
6affcbed
KH		 7259 int ret = kvm_skip_emulated_instruction(vcpu);
7260 /*
7261 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7262 * KVM_EXIT_DEBUG here.
7263 */
7264 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 7265}
8776e519
HB		 7266EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7267
8ef81a9a 7268#ifdef CONFIG_X86_64
55dd00a7
MT		 7269static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7270 unsigned long clock_type)
7271{
7272 struct kvm_clock_pairing clock_pairing;
899a31f5 7273 struct timespec64 ts;
80fbd89c 7274 u64 cycle;
55dd00a7
MT		 7275 int ret;
7276
7277 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7278 return -KVM_EOPNOTSUPP;
7279
7280 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7281 return -KVM_EOPNOTSUPP;
7282
7283 clock_pairing.sec = ts.tv_sec;
7284 clock_pairing.nsec = ts.tv_nsec;
7285 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7286 clock_pairing.flags = 0;
bcbfbd8e 7287 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 7288
7289 ret = 0;
7290 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7291 sizeof(struct kvm_clock_pairing)))
7292 ret = -KVM_EFAULT;
7293
7294 return ret;
7295}
8ef81a9a 7296#endif
55dd00a7 7297
6aef266c
SV		 7298/*
7299 * kvm_pv_kick_cpu_op: Kick a vcpu.
7300 *
7301 * @apicid - apicid of vcpu to be kicked.
7302 */
7303static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7304{
24d2166b 7305 struct kvm_lapic_irq lapic_irq;
6aef266c 7306
24d2166b
R		 7307 lapic_irq.shorthand = 0;
7308 lapic_irq.dest_mode = 0;
ebd28fcb 7309 lapic_irq.level = 0;
24d2166b 7310 lapic_irq.dest_id = apicid;
93bbf0b8 7311 lapic_irq.msi_redir_hint = false;
6aef266c 7312
24d2166b 7313 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7314 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7315}
7316
d62caabb
AS		 7317void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7318{
f7589cca
PB		 7319 if (!lapic_in_kernel(vcpu)) {
7320 WARN_ON_ONCE(vcpu->arch.apicv_active);
7321 return;
7322 }
7323 if (!vcpu->arch.apicv_active)
7324 return;
7325
d62caabb
AS		 7326 vcpu->arch.apicv_active = false;
7327 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7328}
7329
71506297
WL		 7330static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7331{
7332 struct kvm_vcpu *target = NULL;
7333 struct kvm_apic_map *map;
7334
7335 rcu_read_lock();
7336 map = rcu_dereference(kvm->arch.apic_map);
7337
7338 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7339 target = map->phys_map[dest_id]->vcpu;
7340
7341 rcu_read_unlock();
7342
266e85a5 7343 if (target && READ_ONCE(target->ready))
71506297
WL		 7344 kvm_vcpu_yield_to(target);
7345}
7346
8776e519
HB		 7347int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7348{
7349 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7350 int op_64_bit;
8776e519 7351
696ca779
RK		 7352 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7353 return kvm_hv_hypercall(vcpu);
55cd8e5a 7354
de3cd117
SC		 7355 nr = kvm_rax_read(vcpu);
7356 a0 = kvm_rbx_read(vcpu);
7357 a1 = kvm_rcx_read(vcpu);
7358 a2 = kvm_rdx_read(vcpu);
7359 a3 = kvm_rsi_read(vcpu);
8776e519 7360
229456fc 7361 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7362
a449c7aa
NA		 7363 op_64_bit = is_64_bit_mode(vcpu);
7364 if (!op_64_bit) {
8776e519
HB		 7365 nr &= 0xFFFFFFFF;
7366 a0 &= 0xFFFFFFFF;
7367 a1 &= 0xFFFFFFFF;
7368 a2 &= 0xFFFFFFFF;
7369 a3 &= 0xFFFFFFFF;
7370 }
7371
07708c4a
JK		 7372 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7373 ret = -KVM_EPERM;
696ca779 7374 goto out;
07708c4a
JK		 7375 }
7376
8776e519 7377 switch (nr) {
b93463aa
AK		 7378 case KVM_HC_VAPIC_POLL_IRQ:
7379 ret = 0;
7380 break;
6aef266c
SV		 7381 case KVM_HC_KICK_CPU:
7382 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
266e85a5 7383 kvm_sched_yield(vcpu->kvm, a1);
6aef266c
SV		 7384 ret = 0;
7385 break;
8ef81a9a 7386#ifdef CONFIG_X86_64
55dd00a7
MT		 7387 case KVM_HC_CLOCK_PAIRING:
7388 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7389 break;
1ed199a4 7390#endif
4180bf1b
WL		 7391 case KVM_HC_SEND_IPI:
7392 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7393 break;
71506297
WL		 7394 case KVM_HC_SCHED_YIELD:
7395 kvm_sched_yield(vcpu->kvm, a0);
7396 ret = 0;
7397 break;
8776e519
HB		 7398 default:
7399 ret = -KVM_ENOSYS;
7400 break;
7401 }
696ca779 7402out:
a449c7aa
NA		 7403 if (!op_64_bit)
7404 ret = (u32)ret;
de3cd117 7405 kvm_rax_write(vcpu, ret);
6356ee0c 7406
f11c3a8d 7407 ++vcpu->stat.hypercalls;
6356ee0c 7408 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7409}
7410EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7411
b6785def 7412static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7413{
d6aa1000 7414 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7415 char instruction[3];
5fdbf976 7416 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7417
8776e519 7418 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7419
ce2e852e
DV		 7420 return emulator_write_emulated(ctxt, rip, instruction, 3,
7421 &ctxt->exception);
8776e519
HB		 7422}
7423
851ba692 7424static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7425{
782d422b
MG		 7426 return vcpu->run->request_interrupt_window &&
7427 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7428}
7429
851ba692 7430static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7431{
851ba692
AK		 7432 struct kvm_run *kvm_run = vcpu->run;
7433
91586a3b 7434 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7435 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7436 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7437 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7438 kvm_run->ready_for_interrupt_injection =
7439 pic_in_kernel(vcpu->kvm) ||
782d422b 7440 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7441}
7442
95ba8273
GN		 7443static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7444{
7445 int max_irr, tpr;
7446
7447 if (!kvm_x86_ops->update_cr8_intercept)
7448 return;
7449
bce87cce 7450 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7451 return;
7452
d62caabb
AS		 7453 if (vcpu->arch.apicv_active)
7454 return;
7455
8db3baa2
GN		 7456 if (!vcpu->arch.apic->vapic_addr)
7457 max_irr = kvm_lapic_find_highest_irr(vcpu);
7458 else
7459 max_irr = -1;
95ba8273
GN		 7460
7461 if (max_irr != -1)
7462 max_irr >>= 4;
7463
7464 tpr = kvm_lapic_get_cr8(vcpu);
7465
7466 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7467}
7468
b6b8a145 7469static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7470{
b6b8a145
JK		 7471 int r;
7472
95ba8273 7473 /* try to reinject previous events if any */
664f8e26 7474
1a680e35
LA		 7475 if (vcpu->arch.exception.injected)
7476 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7477 /*
a042c26f
LA		 7478 * Do not inject an NMI or interrupt if there is a pending
7479 * exception. Exceptions and interrupts are recognized at
7480 * instruction boundaries, i.e. the start of an instruction.
7481 * Trap-like exceptions, e.g. #DB, have higher priority than
7482 * NMIs and interrupts, i.e. traps are recognized before an
7483 * NMI/interrupt that's pending on the same instruction.
7484 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7485 * priority, but are only generated (pended) during instruction
7486 * execution, i.e. a pending fault-like exception means the
7487 * fault occurred on the *previous* instruction and must be
7488 * serviced prior to recognizing any new events in order to
7489 * fully complete the previous instruction.
664f8e26 7490 */
1a680e35
LA		 7491 else if (!vcpu->arch.exception.pending) {
7492 if (vcpu->arch.nmi_injected)
664f8e26 7493 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7494 else if (vcpu->arch.interrupt.injected)
664f8e26 7495 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7496 }
7497
1a680e35
LA		 7498 /*
7499 * Call check_nested_events() even if we reinjected a previous event
7500 * in order for caller to determine if it should require immediate-exit
7501 * from L2 to L1 due to pending L1 events which require exit
7502 * from L2 to L1.
7503 */
664f8e26
WL		 7504 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7505 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7506 if (r != 0)
7507 return r;
7508 }
7509
7510 /* try to inject new event if pending */
b59bb7bd 7511 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7512 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7513 vcpu->arch.exception.has_error_code,
7514 vcpu->arch.exception.error_code);
d6e8c854 7515
1a680e35 7516 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7517 vcpu->arch.exception.pending = false;
7518 vcpu->arch.exception.injected = true;
7519
d6e8c854
NA		 7520 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7521 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7522 X86_EFLAGS_RF);
7523
f10c729f
JM		 7524 if (vcpu->arch.exception.nr == DB_VECTOR) {
7525 /*
7526 * This code assumes that nSVM doesn't use
7527 * check_nested_events(). If it does, the
7528 * DR6/DR7 changes should happen before L1
7529 * gets a #VMEXIT for an intercepted #DB in
7530 * L2. (Under VMX, on the other hand, the
7531 * DR6/DR7 changes should not happen in the
7532 * event of a VM-exit to L1 for an intercepted
7533 * #DB in L2.)
7534 */
7535 kvm_deliver_exception_payload(vcpu);
7536 if (vcpu->arch.dr7 & DR7_GD) {
7537 vcpu->arch.dr7 &= ~DR7_GD;
7538 kvm_update_dr7(vcpu);
7539 }
6bdf0662
NA		 7540 }
7541
cfcd20e5 7542 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7543 }
7544
7545 /* Don't consider new event if we re-injected an event */
7546 if (kvm_event_needs_reinjection(vcpu))
7547 return 0;
7548
7549 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7550 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7551 vcpu->arch.smi_pending = false;
52797bf9 7552 ++vcpu->arch.smi_count;
ee2cd4b7 7553 enter_smm(vcpu);
c43203ca 7554 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7555 --vcpu->arch.nmi_pending;
7556 vcpu->arch.nmi_injected = true;
7557 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7558 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7559 /*
7560 * Because interrupts can be injected asynchronously, we are
7561 * calling check_nested_events again here to avoid a race condition.
7562 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7563 * proposal and current concerns. Perhaps we should be setting
7564 * KVM_REQ_EVENT only on certain events and not unconditionally?
7565 */
7566 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7567 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7568 if (r != 0)
7569 return r;
7570 }
95ba8273 7571 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7572 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7573 false);
7574 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7575 }
7576 }
ee2cd4b7 7577
b6b8a145 7578 return 0;
95ba8273
GN		 7579}
7580
7460fb4a
AK		 7581static void process_nmi(struct kvm_vcpu *vcpu)
7582{
7583 unsigned limit = 2;
7584
7585 /*
7586 * x86 is limited to one NMI running, and one NMI pending after it.
7587 * If an NMI is already in progress, limit further NMIs to just one.
7588 * Otherwise, allow two (and we'll inject the first one immediately).
7589 */
7590 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7591 limit = 1;
7592
7593 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7594 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7595 kvm_make_request(KVM_REQ_EVENT, vcpu);
7596}
7597
ee2cd4b7 7598static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7599{
7600 u32 flags = 0;
7601 flags |= seg->g << 23;
7602 flags |= seg->db << 22;
7603 flags |= seg->l << 21;
7604 flags |= seg->avl << 20;
7605 flags |= seg->present << 15;
7606 flags |= seg->dpl << 13;
7607 flags |= seg->s << 12;
7608 flags |= seg->type << 8;
7609 return flags;
7610}
7611
ee2cd4b7 7612static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7613{
7614 struct kvm_segment seg;
7615 int offset;
7616
7617 kvm_get_segment(vcpu, &seg, n);
7618 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7619
7620 if (n < 3)
7621 offset = 0x7f84 + n * 12;
7622 else
7623 offset = 0x7f2c + (n - 3) * 12;
7624
7625 put_smstate(u32, buf, offset + 8, seg.base);
7626 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7627 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7628}
7629
efbb288a 7630#ifdef CONFIG_X86_64
ee2cd4b7 7631static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7632{
7633 struct kvm_segment seg;
7634 int offset;
7635 u16 flags;
7636
7637 kvm_get_segment(vcpu, &seg, n);
7638 offset = 0x7e00 + n * 16;
7639
ee2cd4b7 7640 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7641 put_smstate(u16, buf, offset, seg.selector);
7642 put_smstate(u16, buf, offset + 2, flags);
7643 put_smstate(u32, buf, offset + 4, seg.limit);
7644 put_smstate(u64, buf, offset + 8, seg.base);
7645}
efbb288a 7646#endif
660a5d51 7647
ee2cd4b7 7648static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7649{
7650 struct desc_ptr dt;
7651 struct kvm_segment seg;
7652 unsigned long val;
7653 int i;
7654
7655 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7656 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7657 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7658 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7659
7660 for (i = 0; i < 8; i++)
7661 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7662
7663 kvm_get_dr(vcpu, 6, &val);
7664 put_smstate(u32, buf, 0x7fcc, (u32)val);
7665 kvm_get_dr(vcpu, 7, &val);
7666 put_smstate(u32, buf, 0x7fc8, (u32)val);
7667
7668 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7669 put_smstate(u32, buf, 0x7fc4, seg.selector);
7670 put_smstate(u32, buf, 0x7f64, seg.base);
7671 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7672 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7673
7674 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7675 put_smstate(u32, buf, 0x7fc0, seg.selector);
7676 put_smstate(u32, buf, 0x7f80, seg.base);
7677 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7678 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7679
7680 kvm_x86_ops->get_gdt(vcpu, &dt);
7681 put_smstate(u32, buf, 0x7f74, dt.address);
7682 put_smstate(u32, buf, 0x7f70, dt.size);
7683
7684 kvm_x86_ops->get_idt(vcpu, &dt);
7685 put_smstate(u32, buf, 0x7f58, dt.address);
7686 put_smstate(u32, buf, 0x7f54, dt.size);
7687
7688 for (i = 0; i < 6; i++)
ee2cd4b7 7689 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7690
7691 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7692
7693 /* revision id */
7694 put_smstate(u32, buf, 0x7efc, 0x00020000);
7695 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7696}
7697
b68f3cc7 7698#ifdef CONFIG_X86_64
ee2cd4b7 7699static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51 7700{
660a5d51
PB		 7701 struct desc_ptr dt;
7702 struct kvm_segment seg;
7703 unsigned long val;
7704 int i;
7705
7706 for (i = 0; i < 16; i++)
7707 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7708
7709 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7710 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7711
7712 kvm_get_dr(vcpu, 6, &val);
7713 put_smstate(u64, buf, 0x7f68, val);
7714 kvm_get_dr(vcpu, 7, &val);
7715 put_smstate(u64, buf, 0x7f60, val);
7716
7717 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7718 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7719 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7720
7721 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7722
7723 /* revision id */
7724 put_smstate(u32, buf, 0x7efc, 0x00020064);
7725
7726 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7727
7728 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7729 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7730 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7731 put_smstate(u32, buf, 0x7e94, seg.limit);
7732 put_smstate(u64, buf, 0x7e98, seg.base);
7733
7734 kvm_x86_ops->get_idt(vcpu, &dt);
7735 put_smstate(u32, buf, 0x7e84, dt.size);
7736 put_smstate(u64, buf, 0x7e88, dt.address);
7737
7738 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7739 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7740 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7741 put_smstate(u32, buf, 0x7e74, seg.limit);
7742 put_smstate(u64, buf, 0x7e78, seg.base);
7743
7744 kvm_x86_ops->get_gdt(vcpu, &dt);
7745 put_smstate(u32, buf, 0x7e64, dt.size);
7746 put_smstate(u64, buf, 0x7e68, dt.address);
7747
7748 for (i = 0; i < 6; i++)
ee2cd4b7 7749 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51 7750}
b68f3cc7 7751#endif
660a5d51 7752
ee2cd4b7 7753static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7754{
660a5d51 7755 struct kvm_segment cs, ds;
18c3626e 7756 struct desc_ptr dt;
660a5d51
PB		 7757 char buf[512];
7758 u32 cr0;
7759
660a5d51 7760 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7761 memset(buf, 0, 512);
b68f3cc7 7762#ifdef CONFIG_X86_64
d6321d49 7763 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7764 enter_smm_save_state_64(vcpu, buf);
660a5d51 7765 else
b68f3cc7 7766#endif
ee2cd4b7 7767 enter_smm_save_state_32(vcpu, buf);
660a5d51 7768
0234bf88
LP		 7769 /*
7770 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7771 * vCPU state (e.g. leave guest mode) after we've saved the state into
7772 * the SMM state-save area.
7773 */
7774 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7775
7776 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7777 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7778
7779 if (kvm_x86_ops->get_nmi_mask(vcpu))
7780 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7781 else
7782 kvm_x86_ops->set_nmi_mask(vcpu, true);
7783
7784 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7785 kvm_rip_write(vcpu, 0x8000);
7786
7787 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7788 kvm_x86_ops->set_cr0(vcpu, cr0);
7789 vcpu->arch.cr0 = cr0;
7790
7791 kvm_x86_ops->set_cr4(vcpu, 0);
7792
18c3626e
PB		 7793 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7794 dt.address = dt.size = 0;
7795 kvm_x86_ops->set_idt(vcpu, &dt);
7796
660a5d51
PB		 7797 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7798
7799 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7800 cs.base = vcpu->arch.smbase;
7801
7802 ds.selector = 0;
7803 ds.base = 0;
7804
7805 cs.limit = ds.limit = 0xffffffff;
7806 cs.type = ds.type = 0x3;
7807 cs.dpl = ds.dpl = 0;
7808 cs.db = ds.db = 0;
7809 cs.s = ds.s = 1;
7810 cs.l = ds.l = 0;
7811 cs.g = ds.g = 1;
7812 cs.avl = ds.avl = 0;
7813 cs.present = ds.present = 1;
7814 cs.unusable = ds.unusable = 0;
7815 cs.padding = ds.padding = 0;
7816
7817 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7818 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7819 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7820 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7821 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7822 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7823
b68f3cc7 7824#ifdef CONFIG_X86_64
d6321d49 7825 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51 7826 kvm_x86_ops->set_efer(vcpu, 0);
b68f3cc7 7827#endif
660a5d51
PB		 7828
7829 kvm_update_cpuid(vcpu);
7830 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7831}
7832
ee2cd4b7 7833static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7834{
7835 vcpu->arch.smi_pending = true;
7836 kvm_make_request(KVM_REQ_EVENT, vcpu);
7837}
7838
2860c4b1
PB		 7839void kvm_make_scan_ioapic_request(struct kvm *kvm)
7840{
7841 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7842}
7843
3d81bc7e 7844static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7845{
dcbd3e49 7846 if (!kvm_apic_present(vcpu))
3d81bc7e 7847 return;
c7c9c56c 7848
6308630b 7849 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7850
b053b2ae 7851 if (irqchip_split(vcpu->kvm))
6308630b 7852 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7853 else {
fa59cc00 7854 if (vcpu->arch.apicv_active)
d62caabb 7855 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 7856 if (ioapic_in_kernel(vcpu->kvm))
7857 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7858 }
e40ff1d6
LA		 7859
7860 if (is_guest_mode(vcpu))
7861 vcpu->arch.load_eoi_exitmap_pending = true;
7862 else
7863 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7864}
7865
7866static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7867{
7868 u64 eoi_exit_bitmap[4];
7869
7870 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7871 return;
7872
5c919412
AS		 7873 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7874 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7875 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7876}
7877
93065ac7
MH		 7878int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7879 unsigned long start, unsigned long end,
7880 bool blockable)
b1394e74
RK		 7881{
7882 unsigned long apic_address;
7883
7884 /*
7885 * The physical address of apic access page is stored in the VMCS.
7886 * Update it when it becomes invalid.
7887 */
7888 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7889 if (start <= apic_address && apic_address < end)
7890 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7891
7892 return 0;
b1394e74
RK		 7893}
7894
4256f43f
TC		 7895void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7896{
c24ae0dc
TC		 7897 struct page *page = NULL;
7898
35754c98 7899 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7900 return;
7901
4256f43f
TC		 7902 if (!kvm_x86_ops->set_apic_access_page_addr)
7903 return;
7904
c24ae0dc 7905 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7906 if (is_error_page(page))
7907 return;
c24ae0dc
TC		 7908 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7909
7910 /*
7911 * Do not pin apic access page in memory, the MMU notifier
7912 * will call us again if it is migrated or swapped out.
7913 */
7914 put_page(page);
4256f43f
TC		 7915}
7916EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7917
d264ee0c
SC		 7918void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
7919{
7920 smp_send_reschedule(vcpu->cpu);
7921}
7922EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
7923
9357d939 7924/*
362c698f 7925 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7926 * exiting to the userspace. Otherwise, the value will be returned to the
7927 * userspace.
7928 */
851ba692 7929static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7930{
7931 int r;
62a193ed
MG		 7932 bool req_int_win =
7933 dm_request_for_irq_injection(vcpu) &&
7934 kvm_cpu_accept_dm_intr(vcpu);
7935
730dca42 7936 bool req_immediate_exit = false;
b6c7a5dc 7937
2fa6e1e1 7938 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7939 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7940 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7941 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7942 kvm_mmu_unload(vcpu);
a8eeb04a 7943 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7944 __kvm_migrate_timers(vcpu);
d828199e
MT		 7945 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7946 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7947 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7948 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7949 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7950 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7951 if (unlikely(r))
7952 goto out;
7953 }
a8eeb04a 7954 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7955 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7956 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7957 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7958 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7959 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7960 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7961 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7962 r = 0;
7963 goto out;
7964 }
a8eeb04a 7965 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7966 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7967 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7968 r = 0;
7969 goto out;
7970 }
af585b92
GN		 7971 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7972 /* Page is swapped out. Do synthetic halt */
7973 vcpu->arch.apf.halted = true;
7974 r = 1;
7975 goto out;
7976 }
c9aaa895
GC		 7977 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7978 record_steal_time(vcpu);
64d60670
PB		 7979 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7980 process_smi(vcpu);
7460fb4a
AK		 7981 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7982 process_nmi(vcpu);
f5132b01 7983 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7984 kvm_pmu_handle_event(vcpu);
f5132b01 7985 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7986 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7987 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7988 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7989 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7990 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7991 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7992 vcpu->run->eoi.vector =
7993 vcpu->arch.pending_ioapic_eoi;
7994 r = 0;
7995 goto out;
7996 }
7997 }
3d81bc7e
YZ		 7998 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7999 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 8000 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8001 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 8002 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8003 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 8004 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8005 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8006 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8007 r = 0;
8008 goto out;
8009 }
e516cebb
AS		 8010 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8011 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8012 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8013 r = 0;
8014 goto out;
8015 }
db397571
AS		 8016 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8017 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8018 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8019 r = 0;
8020 goto out;
8021 }
f3b138c5
AS		 8022
8023 /*
8024 * KVM_REQ_HV_STIMER has to be processed after
8025 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8026 * depend on the guest clock being up-to-date
8027 */
1f4b34f8
AS		 8028 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8029 kvm_hv_process_stimers(vcpu);
2f52d58c 8030 }
b93463aa 8031
b463a6f7 8032 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 8033 ++vcpu->stat.req_event;
66450a21
JK		 8034 kvm_apic_accept_events(vcpu);
8035 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8036 r = 1;
8037 goto out;
8038 }
8039
b6b8a145
JK		 8040 if (inject_pending_event(vcpu, req_int_win) != 0)
8041 req_immediate_exit = true;
321c5658 8042 else {
cc3d967f 8043 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 8044 *
cc3d967f
LP		 8045 * SMIs have three cases:
8046 * 1) They can be nested, and then there is nothing to
8047 * do here because RSM will cause a vmexit anyway.
8048 * 2) There is an ISA-specific reason why SMI cannot be
8049 * injected, and the moment when this changes can be
8050 * intercepted.
8051 * 3) Or the SMI can be pending because
8052 * inject_pending_event has completed the injection
8053 * of an IRQ or NMI from the previous vmexit, and
8054 * then we request an immediate exit to inject the
8055 * SMI.
c43203ca
PB		 8056 */
8057 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 8058 if (!kvm_x86_ops->enable_smi_window(vcpu))
8059 req_immediate_exit = true;
321c5658
YS		 8060 if (vcpu->arch.nmi_pending)
8061 kvm_x86_ops->enable_nmi_window(vcpu);
8062 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8063 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 8064 WARN_ON(vcpu->arch.exception.pending);
321c5658 8065 }
b463a6f7
AK		 8066
8067 if (kvm_lapic_enabled(vcpu)) {
8068 update_cr8_intercept(vcpu);
8069 kvm_lapic_sync_to_vapic(vcpu);
8070 }
8071 }
8072
d8368af8
AK		 8073 r = kvm_mmu_reload(vcpu);
8074 if (unlikely(r)) {
d905c069 8075 goto cancel_injection;
d8368af8
AK		 8076 }
8077
b6c7a5dc
HB		 8078 preempt_disable();
8079
8080 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 8081
8082 /*
8083 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8084 * IPI are then delayed after guest entry, which ensures that they
8085 * result in virtual interrupt delivery.
8086 */
8087 local_irq_disable();
6b7e2d09
XG		 8088 vcpu->mode = IN_GUEST_MODE;
8089
01b71917
MT		 8090 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8091
0f127d12 8092 /*
b95234c8 8093 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 8094 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8 8095 *
81b01667 8096 * 2) For APICv, we should set ->mode before checking PID.ON. This
b95234c8
PB		 8097 * pairs with the memory barrier implicit in pi_test_and_set_on
8098 * (see vmx_deliver_posted_interrupt).
8099 *
8100 * 3) This also orders the write to mode from any reads to the page
8101 * tables done while the VCPU is running. Please see the comment
8102 * in kvm_flush_remote_tlbs.
6b7e2d09 8103 */
01b71917 8104 smp_mb__after_srcu_read_unlock();
b6c7a5dc 8105
b95234c8
PB		 8106 /*
8107 * This handles the case where a posted interrupt was
8108 * notified with kvm_vcpu_kick.
8109 */
fa59cc00
LA		 8110 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8111 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 8112
2fa6e1e1 8113 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 8114 || need_resched() || signal_pending(current)) {
6b7e2d09 8115 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8116 smp_wmb();
6c142801
AK		 8117 local_irq_enable();
8118 preempt_enable();
01b71917 8119 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 8120 r = 1;
d905c069 8121 goto cancel_injection;
6c142801
AK		 8122 }
8123
c43203ca
PB		 8124 if (req_immediate_exit) {
8125 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 8126 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 8127 }
d6185f20 8128
8b89fe1f 8129 trace_kvm_entry(vcpu->vcpu_id);
6edaa530 8130 guest_enter_irqoff();
b6c7a5dc 8131
e7517324
WL		 8132 /* The preempt notifier should have taken care of the FPU already. */
8133 WARN_ON_ONCE(test_thread_flag(TIF_NEED_FPU_LOAD));
5f409e20 8134
42dbaa5a 8135 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 8136 set_debugreg(0, 7);
8137 set_debugreg(vcpu->arch.eff_db[0], 0);
8138 set_debugreg(vcpu->arch.eff_db[1], 1);
8139 set_debugreg(vcpu->arch.eff_db[2], 2);
8140 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 8141 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 8142 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 8143 }
b6c7a5dc 8144
851ba692 8145 kvm_x86_ops->run(vcpu);
b6c7a5dc 8146
c77fb5fe
PB		 8147 /*
8148 * Do this here before restoring debug registers on the host. And
8149 * since we do this before handling the vmexit, a DR access vmexit
8150 * can (a) read the correct value of the debug registers, (b) set
8151 * KVM_DEBUGREG_WONT_EXIT again.
8152 */
8153 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 8154 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8155 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 8156 kvm_update_dr0123(vcpu);
8157 kvm_update_dr6(vcpu);
8158 kvm_update_dr7(vcpu);
8159 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 8160 }
8161
24f1e32c
FW		 8162 /*
8163 * If the guest has used debug registers, at least dr7
8164 * will be disabled while returning to the host.
8165 * If we don't have active breakpoints in the host, we don't
8166 * care about the messed up debug address registers. But if
8167 * we have some of them active, restore the old state.
8168 */
59d8eb53 8169 if (hw_breakpoint_active())
24f1e32c 8170 hw_breakpoint_restore();
42dbaa5a 8171
4ba76538 8172 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 8173
6b7e2d09 8174 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8175 smp_wmb();
a547c6db 8176
95b5a48c 8177 kvm_x86_ops->handle_exit_irqoff(vcpu);
b6c7a5dc 8178
d7a08882
SC		 8179 /*
8180 * Consume any pending interrupts, including the possible source of
8181 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8182 * An instruction is required after local_irq_enable() to fully unblock
8183 * interrupts on processors that implement an interrupt shadow, the
8184 * stat.exits increment will do nicely.
8185 */
8186 kvm_before_interrupt(vcpu);
8187 local_irq_enable();
b6c7a5dc 8188 ++vcpu->stat.exits;
d7a08882
SC		 8189 local_irq_disable();
8190 kvm_after_interrupt(vcpu);
b6c7a5dc 8191
f2485b3e 8192 guest_exit_irqoff();
ec0671d5
WL		 8193 if (lapic_in_kernel(vcpu)) {
8194 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8195 if (delta != S64_MIN) {
8196 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8197 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8198 }
8199 }
b6c7a5dc 8200
f2485b3e 8201 local_irq_enable();
b6c7a5dc
HB		 8202 preempt_enable();
8203
f656ce01 8204 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 8205
b6c7a5dc
HB		 8206 /*
8207 * Profile KVM exit RIPs:
8208 */
8209 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 8210 unsigned long rip = kvm_rip_read(vcpu);
8211 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 8212 }
8213
cc578287
ZA		 8214 if (unlikely(vcpu->arch.tsc_always_catchup))
8215 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 8216
5cfb1d5a
MT		 8217 if (vcpu->arch.apic_attention)
8218 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 8219
618232e2 8220 vcpu->arch.gpa_available = false;
851ba692 8221 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 8222 return r;
8223
8224cancel_injection:
8225 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 8226 if (unlikely(vcpu->arch.apic_attention))
8227 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 8228out:
8229 return r;
8230}
b6c7a5dc 8231
362c698f
PB		 8232static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8233{
bf9f6ac8
FW		 8234 if (!kvm_arch_vcpu_runnable(vcpu) &&
8235 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 8236 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8237 kvm_vcpu_block(vcpu);
8238 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 8239
8240 if (kvm_x86_ops->post_block)
8241 kvm_x86_ops->post_block(vcpu);
8242
9c8fd1ba
PB		 8243 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8244 return 1;
8245 }
362c698f
PB		 8246
8247 kvm_apic_accept_events(vcpu);
8248 switch(vcpu->arch.mp_state) {
8249 case KVM_MP_STATE_HALTED:
8250 vcpu->arch.pv.pv_unhalted = false;
8251 vcpu->arch.mp_state =
8252 KVM_MP_STATE_RUNNABLE;
b2869f28 8253 /* fall through */
362c698f
PB		 8254 case KVM_MP_STATE_RUNNABLE:
8255 vcpu->arch.apf.halted = false;
8256 break;
8257 case KVM_MP_STATE_INIT_RECEIVED:
8258 break;
8259 default:
8260 return -EINTR;
8261 break;
8262 }
8263 return 1;
8264}
09cec754 8265
5d9bc648
PB		 8266static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8267{
0ad3bed6
PB		 8268 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8269 kvm_x86_ops->check_nested_events(vcpu, false);
8270
5d9bc648
PB		 8271 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8272 !vcpu->arch.apf.halted);
8273}
8274
362c698f 8275static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 8276{
8277 int r;
f656ce01 8278 struct kvm *kvm = vcpu->kvm;
d7690175 8279
f656ce01 8280 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 8281 vcpu->arch.l1tf_flush_l1d = true;
d7690175 8282
362c698f 8283 for (;;) {
58f800d5 8284 if (kvm_vcpu_running(vcpu)) {
851ba692 8285 r = vcpu_enter_guest(vcpu);
bf9f6ac8 8286 } else {
362c698f 8287 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 8288 }
8289
09cec754
GN		 8290 if (r <= 0)
8291 break;
8292
72875d8a 8293 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 8294 if (kvm_cpu_has_pending_timer(vcpu))
8295 kvm_inject_pending_timer_irqs(vcpu);
8296
782d422b
MG		 8297 if (dm_request_for_irq_injection(vcpu) &&
8298 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 8299 r = 0;
8300 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 8301 ++vcpu->stat.request_irq_exits;
362c698f 8302 break;
09cec754 8303 }
af585b92
GN		 8304
8305 kvm_check_async_pf_completion(vcpu);
8306
09cec754
GN		 8307 if (signal_pending(current)) {
8308 r = -EINTR;
851ba692 8309 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 8310 ++vcpu->stat.signal_exits;
362c698f 8311 break;
09cec754
GN		 8312 }
8313 if (need_resched()) {
f656ce01 8314 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 8315 cond_resched();
f656ce01 8316 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 8317 }
b6c7a5dc
HB		 8318 }
8319
f656ce01 8320 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 8321
8322 return r;
8323}
8324
716d51ab
GN		 8325static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8326{
8327 int r;
60fc3d02 8328
716d51ab 8329 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 8330 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab 8331 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
60fc3d02 8332 return r;
716d51ab
GN		 8333}
8334
8335static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8336{
8337 BUG_ON(!vcpu->arch.pio.count);
8338
8339 return complete_emulated_io(vcpu);
8340}
8341
f78146b0
AK		 8342/*
8343 * Implements the following, as a state machine:
8344 *
8345 * read:
8346 * for each fragment
87da7e66
XG		 8347 * for each mmio piece in the fragment
8348 * write gpa, len
8349 * exit
8350 * copy data
f78146b0
AK		 8351 * execute insn
8352 *
8353 * write:
8354 * for each fragment
87da7e66
XG		 8355 * for each mmio piece in the fragment
8356 * write gpa, len
8357 * copy data
8358 * exit
f78146b0 8359 */
716d51ab 8360static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8361{
8362 struct kvm_run *run = vcpu->run;
f78146b0 8363 struct kvm_mmio_fragment *frag;
87da7e66 8364 unsigned len;
5287f194 8365
716d51ab 8366 BUG_ON(!vcpu->mmio_needed);
5287f194 8367
716d51ab 8368 /* Complete previous fragment */
87da7e66
XG		 8369 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8370 len = min(8u, frag->len);
716d51ab 8371 if (!vcpu->mmio_is_write)
87da7e66
XG		 8372 memcpy(frag->data, run->mmio.data, len);
8373
8374 if (frag->len <= 8) {
8375 /* Switch to the next fragment. */
8376 frag++;
8377 vcpu->mmio_cur_fragment++;
8378 } else {
8379 /* Go forward to the next mmio piece. */
8380 frag->data += len;
8381 frag->gpa += len;
8382 frag->len -= len;
8383 }
8384
a08d3b3b 8385 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8386 vcpu->mmio_needed = 0;
0912c977
PB		 8387
8388 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8389 if (vcpu->mmio_is_write)
716d51ab
GN		 8390 return 1;
8391 vcpu->mmio_read_completed = 1;
8392 return complete_emulated_io(vcpu);
8393 }
87da7e66 8394
716d51ab
GN		 8395 run->exit_reason = KVM_EXIT_MMIO;
8396 run->mmio.phys_addr = frag->gpa;
8397 if (vcpu->mmio_is_write)
87da7e66
XG		 8398 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8399 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8400 run->mmio.is_write = vcpu->mmio_is_write;
8401 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8402 return 0;
5287f194
AK		 8403}
8404
822f312d
SAS		 8405/* Swap (qemu) user FPU context for the guest FPU context. */
8406static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8407{
5f409e20
RR		 8408 fpregs_lock();
8409
d9a710e5 8410 copy_fpregs_to_fpstate(vcpu->arch.user_fpu);
822f312d 8411 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8412 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d 8413 ~XFEATURE_MASK_PKRU);
5f409e20
RR		 8414
8415 fpregs_mark_activate();
8416 fpregs_unlock();
8417
822f312d
SAS		 8418 trace_kvm_fpu(1);
8419}
8420
8421/* When vcpu_run ends, restore user space FPU context. */
8422static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8423{
5f409e20
RR		 8424 fpregs_lock();
8425
b666a4b6 8426 copy_fpregs_to_fpstate(vcpu->arch.guest_fpu);
d9a710e5 8427 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
5f409e20
RR		 8428
8429 fpregs_mark_activate();
8430 fpregs_unlock();
8431
822f312d
SAS		 8432 ++vcpu->stat.fpu_reload;
8433 trace_kvm_fpu(0);
8434}
8435
b6c7a5dc
HB		 8436int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8437{
8438 int r;
b6c7a5dc 8439
accb757d 8440 vcpu_load(vcpu);
20b7035c 8441 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8442 kvm_load_guest_fpu(vcpu);
8443
a4535290 8444 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8445 if (kvm_run->immediate_exit) {
8446 r = -EINTR;
8447 goto out;
8448 }
b6c7a5dc 8449 kvm_vcpu_block(vcpu);
66450a21 8450 kvm_apic_accept_events(vcpu);
72875d8a 8451 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8452 r = -EAGAIN;
a0595000
JS		 8453 if (signal_pending(current)) {
8454 r = -EINTR;
8455 vcpu->run->exit_reason = KVM_EXIT_INTR;
8456 ++vcpu->stat.signal_exits;
8457 }
ac9f6dc0 8458 goto out;
b6c7a5dc
HB		 8459 }
8460
01643c51
KH		 8461 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8462 r = -EINVAL;
8463 goto out;
8464 }
8465
8466 if (vcpu->run->kvm_dirty_regs) {
8467 r = sync_regs(vcpu);
8468 if (r != 0)
8469 goto out;
8470 }
8471
b6c7a5dc 8472 /* re-sync apic's tpr */
35754c98 8473 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8474 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8475 r = -EINVAL;
8476 goto out;
8477 }
8478 }
b6c7a5dc 8479
716d51ab
GN		 8480 if (unlikely(vcpu->arch.complete_userspace_io)) {
8481 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8482 vcpu->arch.complete_userspace_io = NULL;
8483 r = cui(vcpu);
8484 if (r <= 0)
5663d8f9 8485 goto out;
716d51ab
GN		 8486 } else
8487 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8488
460df4c1
PB		 8489 if (kvm_run->immediate_exit)
8490 r = -EINTR;
8491 else
8492 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8493
8494out:
5663d8f9 8495 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8496 if (vcpu->run->kvm_valid_regs)
8497 store_regs(vcpu);
f1d86e46 8498 post_kvm_run_save(vcpu);
20b7035c 8499 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8500
accb757d 8501 vcpu_put(vcpu);
b6c7a5dc
HB		 8502 return r;
8503}
8504
01643c51 8505static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8506{
7ae441ea
GN		 8507 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8508 /*
8509 * We are here if userspace calls get_regs() in the middle of
8510 * instruction emulation. Registers state needs to be copied
4a969980 8511 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8512 * that usually, but some bad designed PV devices (vmware
8513 * backdoor interface) need this to work
8514 */
dd856efa 8515 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8516 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8517 }
de3cd117
SC		 8518 regs->rax = kvm_rax_read(vcpu);
8519 regs->rbx = kvm_rbx_read(vcpu);
8520 regs->rcx = kvm_rcx_read(vcpu);
8521 regs->rdx = kvm_rdx_read(vcpu);
8522 regs->rsi = kvm_rsi_read(vcpu);
8523 regs->rdi = kvm_rdi_read(vcpu);
e9c16c78 8524 regs->rsp = kvm_rsp_read(vcpu);
de3cd117 8525 regs->rbp = kvm_rbp_read(vcpu);
b6c7a5dc 8526#ifdef CONFIG_X86_64
de3cd117
SC		 8527 regs->r8 = kvm_r8_read(vcpu);
8528 regs->r9 = kvm_r9_read(vcpu);
8529 regs->r10 = kvm_r10_read(vcpu);
8530 regs->r11 = kvm_r11_read(vcpu);
8531 regs->r12 = kvm_r12_read(vcpu);
8532 regs->r13 = kvm_r13_read(vcpu);
8533 regs->r14 = kvm_r14_read(vcpu);
8534 regs->r15 = kvm_r15_read(vcpu);
b6c7a5dc
HB		 8535#endif
8536
5fdbf976 8537 regs->rip = kvm_rip_read(vcpu);
91586a3b 8538 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8539}
b6c7a5dc 8540
01643c51
KH		 8541int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8542{
8543 vcpu_load(vcpu);
8544 __get_regs(vcpu, regs);
1fc9b76b 8545 vcpu_put(vcpu);
b6c7a5dc
HB		 8546 return 0;
8547}
8548
01643c51 8549static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8550{
7ae441ea
GN		 8551 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8552 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8553
de3cd117
SC		 8554 kvm_rax_write(vcpu, regs->rax);
8555 kvm_rbx_write(vcpu, regs->rbx);
8556 kvm_rcx_write(vcpu, regs->rcx);
8557 kvm_rdx_write(vcpu, regs->rdx);
8558 kvm_rsi_write(vcpu, regs->rsi);
8559 kvm_rdi_write(vcpu, regs->rdi);
e9c16c78 8560 kvm_rsp_write(vcpu, regs->rsp);
de3cd117 8561 kvm_rbp_write(vcpu, regs->rbp);
b6c7a5dc 8562#ifdef CONFIG_X86_64
de3cd117
SC		 8563 kvm_r8_write(vcpu, regs->r8);
8564 kvm_r9_write(vcpu, regs->r9);
8565 kvm_r10_write(vcpu, regs->r10);
8566 kvm_r11_write(vcpu, regs->r11);
8567 kvm_r12_write(vcpu, regs->r12);
8568 kvm_r13_write(vcpu, regs->r13);
8569 kvm_r14_write(vcpu, regs->r14);
8570 kvm_r15_write(vcpu, regs->r15);
b6c7a5dc
HB		 8571#endif
8572
5fdbf976 8573 kvm_rip_write(vcpu, regs->rip);
d73235d1 8574 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8575
b4f14abd
JK		 8576 vcpu->arch.exception.pending = false;
8577
3842d135 8578 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8579}
3842d135 8580
01643c51
KH		 8581int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8582{
8583 vcpu_load(vcpu);
8584 __set_regs(vcpu, regs);
875656fe 8585 vcpu_put(vcpu);
b6c7a5dc
HB		 8586 return 0;
8587}
8588
b6c7a5dc
HB		 8589void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8590{
8591 struct kvm_segment cs;
8592
3e6e0aab 8593 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8594 *db = cs.db;
8595 *l = cs.l;
8596}
8597EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8598
01643c51 8599static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8600{
89a27f4d 8601 struct desc_ptr dt;
b6c7a5dc 8602
3e6e0aab
GT		 8603 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8604 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8605 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8606 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8607 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8608 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8609
3e6e0aab
GT		 8610 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8611 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8612
8613 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8614 sregs->idt.limit = dt.size;
8615 sregs->idt.base = dt.address;
b6c7a5dc 8616 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8617 sregs->gdt.limit = dt.size;
8618 sregs->gdt.base = dt.address;
b6c7a5dc 8619
4d4ec087 8620 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8621 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8622 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8623 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8624 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8625 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8626 sregs->apic_base = kvm_get_apic_base(vcpu);
8627
0e96f31e 8628 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8629
04140b41 8630 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8631 set_bit(vcpu->arch.interrupt.nr,
8632 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8633}
16d7a191 8634
01643c51
KH		 8635int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8636 struct kvm_sregs *sregs)
8637{
8638 vcpu_load(vcpu);
8639 __get_sregs(vcpu, sregs);
bcdec41c 8640 vcpu_put(vcpu);
b6c7a5dc
HB		 8641 return 0;
8642}
8643
62d9f0db
MT		 8644int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8645 struct kvm_mp_state *mp_state)
8646{
fd232561
CD		 8647 vcpu_load(vcpu);
8648
66450a21 8649 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8650 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8651 vcpu->arch.pv.pv_unhalted)
8652 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8653 else
8654 mp_state->mp_state = vcpu->arch.mp_state;
8655
fd232561 8656 vcpu_put(vcpu);
62d9f0db
MT		 8657 return 0;
8658}
8659
8660int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8661 struct kvm_mp_state *mp_state)
8662{
e83dff5e
CD		 8663 int ret = -EINVAL;
8664
8665 vcpu_load(vcpu);
8666
bce87cce 8667 if (!lapic_in_kernel(vcpu) &&
66450a21 8668 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8669 goto out;
66450a21 8670
28bf2888
DH		 8671 /* INITs are latched while in SMM */
8672 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8673 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8674 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8675 goto out;
28bf2888 8676
66450a21
JK		 8677 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8678 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8679 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8680 } else
8681 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8682 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8683
8684 ret = 0;
8685out:
8686 vcpu_put(vcpu);
8687 return ret;
62d9f0db
MT		 8688}
8689
7f3d35fd
KW		 8690int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8691 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8692{
9d74191a 8693 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8694 int ret;
e01c2426 8695
8ec4722d 8696 init_emulate_ctxt(vcpu);
c697518a 8697
7f3d35fd 8698 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8699 has_error_code, error_code);
1051778f
SC		 8700 if (ret) {
8701 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8702 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8703 vcpu->run->internal.ndata = 0;
60fc3d02 8704 return 0;
1051778f 8705 }
37817f29 8706
9d74191a
TY		 8707 kvm_rip_write(vcpu, ctxt->eip);
8708 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8709 kvm_make_request(KVM_REQ_EVENT, vcpu);
60fc3d02 8710 return 1;
37817f29
IE		 8711}
8712EXPORT_SYMBOL_GPL(kvm_task_switch);
8713
3140c156 8714static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8715{
74fec5b9
TL		 8716 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8717 (sregs->cr4 & X86_CR4_OSXSAVE))
8718 return -EINVAL;
8719
37b95951 8720 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8721 /*
8722 * When EFER.LME and CR0.PG are set, the processor is in
8723 * 64-bit mode (though maybe in a 32-bit code segment).
8724 * CR4.PAE and EFER.LMA must be set.
8725 */
37b95951 8726 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8727 || !(sregs->efer & EFER_LMA))
8728 return -EINVAL;
8729 } else {
8730 /*
8731 * Not in 64-bit mode: EFER.LMA is clear and the code
8732 * segment cannot be 64-bit.
8733 */
8734 if (sregs->efer & EFER_LMA || sregs->cs.l)
8735 return -EINVAL;
8736 }
8737
8738 return 0;
8739}
8740
01643c51 8741static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8742{
58cb628d 8743 struct msr_data apic_base_msr;
b6c7a5dc 8744 int mmu_reset_needed = 0;
c4d21882 8745 int cpuid_update_needed = 0;
63f42e02 8746 int pending_vec, max_bits, idx;
89a27f4d 8747 struct desc_ptr dt;
b4ef9d4e
CD		 8748 int ret = -EINVAL;
8749
f2981033 8750 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8751 goto out;
f2981033 8752
d3802286
JM		 8753 apic_base_msr.data = sregs->apic_base;
8754 apic_base_msr.host_initiated = true;
8755 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8756 goto out;
6d1068b3 8757
89a27f4d
GN		 8758 dt.size = sregs->idt.limit;
8759 dt.address = sregs->idt.base;
b6c7a5dc 8760 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8761 dt.size = sregs->gdt.limit;
8762 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8763 kvm_x86_ops->set_gdt(vcpu, &dt);
8764
ad312c7c 8765 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8766 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8767 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8768 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8769
2d3ad1f4 8770 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8771
f6801dff 8772 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8773 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8774
4d4ec087 8775 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8776 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8777 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8778
fc78f519 8779 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8780 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8781 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8782 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8783 if (cpuid_update_needed)
00b27a3e 8784 kvm_update_cpuid(vcpu);
63f42e02
XG		 8785
8786 idx = srcu_read_lock(&vcpu->kvm->srcu);
bf03d4f9 8787 if (is_pae_paging(vcpu)) {
9f8fe504 8788 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8789 mmu_reset_needed = 1;
8790 }
63f42e02 8791 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8792
8793 if (mmu_reset_needed)
8794 kvm_mmu_reset_context(vcpu);
8795
a50abc3b 8796 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8797 pending_vec = find_first_bit(
8798 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8799 if (pending_vec < max_bits) {
66fd3f7f 8800 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8801 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8802 }
8803
3e6e0aab
GT		 8804 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8805 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8806 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8807 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8808 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8809 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8810
3e6e0aab
GT		 8811 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8812 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8813
5f0269f5
ME		 8814 update_cr8_intercept(vcpu);
8815
9c3e4aab 8816 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8817 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8818 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8819 !is_protmode(vcpu))
9c3e4aab
MT		 8820 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8821
3842d135
AK		 8822 kvm_make_request(KVM_REQ_EVENT, vcpu);
8823
b4ef9d4e
CD		 8824 ret = 0;
8825out:
01643c51
KH		 8826 return ret;
8827}
8828
8829int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8830 struct kvm_sregs *sregs)
8831{
8832 int ret;
8833
8834 vcpu_load(vcpu);
8835 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8836 vcpu_put(vcpu);
8837 return ret;
b6c7a5dc
HB		 8838}
8839
d0bfb940
JK		 8840int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8841 struct kvm_guest_debug *dbg)
b6c7a5dc 8842{
355be0b9 8843 unsigned long rflags;
ae675ef0 8844 int i, r;
b6c7a5dc 8845
66b56562
CD		 8846 vcpu_load(vcpu);
8847
4f926bf2
JK		 8848 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8849 r = -EBUSY;
8850 if (vcpu->arch.exception.pending)
2122ff5e 8851 goto out;
4f926bf2
JK		 8852 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8853 kvm_queue_exception(vcpu, DB_VECTOR);
8854 else
8855 kvm_queue_exception(vcpu, BP_VECTOR);
8856 }
8857
91586a3b
JK		 8858 /*
8859 * Read rflags as long as potentially injected trace flags are still
8860 * filtered out.
8861 */
8862 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8863
8864 vcpu->guest_debug = dbg->control;
8865 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8866 vcpu->guest_debug = 0;
8867
8868 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8869 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8870 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8871 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8872 } else {
8873 for (i = 0; i < KVM_NR_DB_REGS; i++)
8874 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8875 }
c8639010 8876 kvm_update_dr7(vcpu);
ae675ef0 8877
f92653ee
JK		 8878 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8879 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8880 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8881
91586a3b
JK		 8882 /*
8883 * Trigger an rflags update that will inject or remove the trace
8884 * flags.
8885 */
8886 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8887
a96036b8 8888 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8889
4f926bf2 8890 r = 0;
d0bfb940 8891
2122ff5e 8892out:
66b56562 8893 vcpu_put(vcpu);
b6c7a5dc
HB		 8894 return r;
8895}
8896
8b006791
ZX		 8897/*
8898 * Translate a guest virtual address to a guest physical address.
8899 */
8900int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8901 struct kvm_translation *tr)
8902{
8903 unsigned long vaddr = tr->linear_address;
8904 gpa_t gpa;
f656ce01 8905 int idx;
8b006791 8906
1da5b61d
CD		 8907 vcpu_load(vcpu);
8908
f656ce01 8909 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8910 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8911 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8912 tr->physical_address = gpa;
8913 tr->valid = gpa != UNMAPPED_GVA;
8914 tr->writeable = 1;
8915 tr->usermode = 0;
8b006791 8916
1da5b61d 8917 vcpu_put(vcpu);
8b006791
ZX		 8918 return 0;
8919}
8920
d0752060
HB		 8921int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8922{
1393123e 8923 struct fxregs_state *fxsave;
d0752060 8924
1393123e 8925 vcpu_load(vcpu);
d0752060 8926
b666a4b6 8927 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 8928 memcpy(fpu->fpr, fxsave->st_space, 128);
8929 fpu->fcw = fxsave->cwd;
8930 fpu->fsw = fxsave->swd;
8931 fpu->ftwx = fxsave->twd;
8932 fpu->last_opcode = fxsave->fop;
8933 fpu->last_ip = fxsave->rip;
8934 fpu->last_dp = fxsave->rdp;
0e96f31e 8935 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 8936
1393123e 8937 vcpu_put(vcpu);
d0752060
HB		 8938 return 0;
8939}
8940
8941int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8942{
6a96bc7f
CD		 8943 struct fxregs_state *fxsave;
8944
8945 vcpu_load(vcpu);
8946
b666a4b6 8947 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 8948
d0752060
HB		 8949 memcpy(fxsave->st_space, fpu->fpr, 128);
8950 fxsave->cwd = fpu->fcw;
8951 fxsave->swd = fpu->fsw;
8952 fxsave->twd = fpu->ftwx;
8953 fxsave->fop = fpu->last_opcode;
8954 fxsave->rip = fpu->last_ip;
8955 fxsave->rdp = fpu->last_dp;
0e96f31e 8956 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 8957
6a96bc7f 8958 vcpu_put(vcpu);
d0752060
HB		 8959 return 0;
8960}
8961
01643c51
KH		 8962static void store_regs(struct kvm_vcpu *vcpu)
8963{
8964 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8965
8966 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8967 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8968
8969 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8970 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8971
8972 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8973 kvm_vcpu_ioctl_x86_get_vcpu_events(
8974 vcpu, &vcpu->run->s.regs.events);
8975}
8976
8977static int sync_regs(struct kvm_vcpu *vcpu)
8978{
8979 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8980 return -EINVAL;
8981
8982 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8983 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8984 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8985 }
8986 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8987 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8988 return -EINVAL;
8989 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8990 }
8991 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8992 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8993 vcpu, &vcpu->run->s.regs.events))
8994 return -EINVAL;
8995 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8996 }
8997
8998 return 0;
8999}
9000
0ee6a517 9001static void fx_init(struct kvm_vcpu *vcpu)
d0752060 9002{
b666a4b6 9003 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 9004 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 9005 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 9006 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 9007
2acf923e
DC		 9008 /*
9009 * Ensure guest xcr0 is valid for loading
9010 */
d91cab78 9011 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 9012
ad312c7c 9013 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 9014}
d0752060 9015
e9b11c17
ZX		 9016void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
9017{
bd768e14
IY		 9018 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
9019
12f9a48f 9020 kvmclock_reset(vcpu);
7f1ea208 9021
e9b11c17 9022 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 9023 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 9024}
9025
9026struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
9027 unsigned int id)
9028{
c447e76b
LL		 9029 struct kvm_vcpu *vcpu;
9030
b0c39dc6 9031 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 9032 printk_once(KERN_WARNING
9033 "kvm: SMP vm created on host with unstable TSC; "
9034 "guest TSC will not be reliable\n");
c447e76b
LL		 9035
9036 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
9037
c447e76b 9038 return vcpu;
26e5215f 9039}
e9b11c17 9040
26e5215f
AK		 9041int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
9042{
0cf9135b 9043 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
e53d88af 9044 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 9045 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 9046 vcpu_load(vcpu);
d28bc9dd 9047 kvm_vcpu_reset(vcpu, false);
e1732991 9048 kvm_init_mmu(vcpu, false);
e9b11c17 9049 vcpu_put(vcpu);
ec7660cc 9050 return 0;
e9b11c17
ZX		 9051}
9052
31928aa5 9053void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 9054{
8fe8ab46 9055 struct msr_data msr;
332967a3 9056 struct kvm *kvm = vcpu->kvm;
42897d86 9057
d3457c87
RK		 9058 kvm_hv_vcpu_postcreate(vcpu);
9059
ec7660cc 9060 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 9061 return;
ec7660cc 9062 vcpu_load(vcpu);
8fe8ab46
WA		 9063 msr.data = 0x0;
9064 msr.index = MSR_IA32_TSC;
9065 msr.host_initiated = true;
9066 kvm_write_tsc(vcpu, &msr);
42897d86 9067 vcpu_put(vcpu);
2d5ba19b
MT		 9068
9069 /* poll control enabled by default */
9070 vcpu->arch.msr_kvm_poll_control = 1;
9071
ec7660cc 9072 mutex_unlock(&vcpu->mutex);
42897d86 9073
630994b3
MT		 9074 if (!kvmclock_periodic_sync)
9075 return;
9076
332967a3
AJ		 9077 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9078 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 9079}
9080
d40ccc62 9081void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 9082{
344d9588
GN		 9083 vcpu->arch.apf.msr_val = 0;
9084
ec7660cc 9085 vcpu_load(vcpu);
e9b11c17
ZX		 9086 kvm_mmu_unload(vcpu);
9087 vcpu_put(vcpu);
9088
9089 kvm_x86_ops->vcpu_free(vcpu);
9090}
9091
d28bc9dd 9092void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 9093{
b7e31be3
RK		 9094 kvm_lapic_reset(vcpu, init_event);
9095
e69fab5d
PB		 9096 vcpu->arch.hflags = 0;
9097
c43203ca 9098 vcpu->arch.smi_pending = 0;
52797bf9 9099 vcpu->arch.smi_count = 0;
7460fb4a
AK		 9100 atomic_set(&vcpu->arch.nmi_queued, 0);
9101 vcpu->arch.nmi_pending = 0;
448fa4a9 9102 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 9103 kvm_clear_interrupt_queue(vcpu);
9104 kvm_clear_exception_queue(vcpu);
664f8e26 9105 vcpu->arch.exception.pending = false;
448fa4a9 9106
42dbaa5a 9107 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 9108 kvm_update_dr0123(vcpu);
6f43ed01 9109 vcpu->arch.dr6 = DR6_INIT;
73aaf249 9110 kvm_update_dr6(vcpu);
42dbaa5a 9111 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 9112 kvm_update_dr7(vcpu);
42dbaa5a 9113
1119022c
NA		 9114 vcpu->arch.cr2 = 0;
9115
3842d135 9116 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 9117 vcpu->arch.apf.msr_val = 0;
c9aaa895 9118 vcpu->arch.st.msr_val = 0;
3842d135 9119
12f9a48f
GC		 9120 kvmclock_reset(vcpu);
9121
af585b92
GN		 9122 kvm_clear_async_pf_completion_queue(vcpu);
9123 kvm_async_pf_hash_reset(vcpu);
9124 vcpu->arch.apf.halted = false;
3842d135 9125
a554d207
WL		 9126 if (kvm_mpx_supported()) {
9127 void *mpx_state_buffer;
9128
9129 /*
9130 * To avoid have the INIT path from kvm_apic_has_events() that be
9131 * called with loaded FPU and does not let userspace fix the state.
9132 */
f775b13e
RR		 9133 if (init_event)
9134 kvm_put_guest_fpu(vcpu);
b666a4b6 9135 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9136 XFEATURE_BNDREGS);
a554d207
WL		 9137 if (mpx_state_buffer)
9138 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 9139 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9140 XFEATURE_BNDCSR);
a554d207
WL		 9141 if (mpx_state_buffer)
9142 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 9143 if (init_event)
9144 kvm_load_guest_fpu(vcpu);
a554d207
WL		 9145 }
9146
64d60670 9147 if (!init_event) {
d28bc9dd 9148 kvm_pmu_reset(vcpu);
64d60670 9149 vcpu->arch.smbase = 0x30000;
db2336a8 9150
db2336a8 9151 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 9152
9153 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 9154 }
f5132b01 9155
66f7b72e
JS		 9156 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9157 vcpu->arch.regs_avail = ~0;
9158 vcpu->arch.regs_dirty = ~0;
9159
a554d207
WL		 9160 vcpu->arch.ia32_xss = 0;
9161
d28bc9dd 9162 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 9163}
9164
2b4a273b 9165void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 9166{
9167 struct kvm_segment cs;
9168
9169 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9170 cs.selector = vector << 8;
9171 cs.base = vector << 12;
9172 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9173 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 9174}
9175
13a34e06 9176int kvm_arch_hardware_enable(void)
e9b11c17 9177{
ca84d1a2
ZA		 9178 struct kvm *kvm;
9179 struct kvm_vcpu *vcpu;
9180 int i;
0dd6a6ed
ZA		 9181 int ret;
9182 u64 local_tsc;
9183 u64 max_tsc = 0;
9184 bool stable, backwards_tsc = false;
18863bdd
AK		 9185
9186 kvm_shared_msr_cpu_online();
13a34e06 9187 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 9188 if (ret != 0)
9189 return ret;
9190
4ea1636b 9191 local_tsc = rdtsc();
b0c39dc6 9192 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 9193 list_for_each_entry(kvm, &vm_list, vm_list) {
9194 kvm_for_each_vcpu(i, vcpu, kvm) {
9195 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 9196 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9197 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9198 backwards_tsc = true;
9199 if (vcpu->arch.last_host_tsc > max_tsc)
9200 max_tsc = vcpu->arch.last_host_tsc;
9201 }
9202 }
9203 }
9204
9205 /*
9206 * Sometimes, even reliable TSCs go backwards. This happens on
9207 * platforms that reset TSC during suspend or hibernate actions, but
9208 * maintain synchronization. We must compensate. Fortunately, we can
9209 * detect that condition here, which happens early in CPU bringup,
9210 * before any KVM threads can be running. Unfortunately, we can't
9211 * bring the TSCs fully up to date with real time, as we aren't yet far
9212 * enough into CPU bringup that we know how much real time has actually
9285ec4c 9213 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
0dd6a6ed
ZA		 9214 * variables that haven't been updated yet.
9215 *
9216 * So we simply find the maximum observed TSC above, then record the
9217 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9218 * the adjustment will be applied. Note that we accumulate
9219 * adjustments, in case multiple suspend cycles happen before some VCPU
9220 * gets a chance to run again. In the event that no KVM threads get a
9221 * chance to run, we will miss the entire elapsed period, as we'll have
9222 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9223 * loose cycle time. This isn't too big a deal, since the loss will be
9224 * uniform across all VCPUs (not to mention the scenario is extremely
9225 * unlikely). It is possible that a second hibernate recovery happens
9226 * much faster than a first, causing the observed TSC here to be
9227 * smaller; this would require additional padding adjustment, which is
9228 * why we set last_host_tsc to the local tsc observed here.
9229 *
9230 * N.B. - this code below runs only on platforms with reliable TSC,
9231 * as that is the only way backwards_tsc is set above. Also note
9232 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9233 * have the same delta_cyc adjustment applied if backwards_tsc
9234 * is detected. Note further, this adjustment is only done once,
9235 * as we reset last_host_tsc on all VCPUs to stop this from being
9236 * called multiple times (one for each physical CPU bringup).
9237 *
4a969980 9238 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 9239 * will be compensated by the logic in vcpu_load, which sets the TSC to
9240 * catchup mode. This will catchup all VCPUs to real time, but cannot
9241 * guarantee that they stay in perfect synchronization.
9242 */
9243 if (backwards_tsc) {
9244 u64 delta_cyc = max_tsc - local_tsc;
9245 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 9246 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 9247 kvm_for_each_vcpu(i, vcpu, kvm) {
9248 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9249 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 9250 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9251 }
9252
9253 /*
9254 * We have to disable TSC offset matching.. if you were
9255 * booting a VM while issuing an S4 host suspend....
9256 * you may have some problem. Solving this issue is
9257 * left as an exercise to the reader.
9258 */
9259 kvm->arch.last_tsc_nsec = 0;
9260 kvm->arch.last_tsc_write = 0;
9261 }
9262
9263 }
9264 return 0;
e9b11c17
ZX		 9265}
9266
13a34e06 9267void kvm_arch_hardware_disable(void)
e9b11c17 9268{
13a34e06
RK		 9269 kvm_x86_ops->hardware_disable();
9270 drop_user_return_notifiers();
e9b11c17
ZX		 9271}
9272
9273int kvm_arch_hardware_setup(void)
9274{
9e9c3fe4
NA		 9275 int r;
9276
9277 r = kvm_x86_ops->hardware_setup();
9278 if (r != 0)
9279 return r;
9280
35181e86
HZ		 9281 if (kvm_has_tsc_control) {
9282 /*
9283 * Make sure the user can only configure tsc_khz values that
9284 * fit into a signed integer.
273ba457 9285 * A min value is not calculated because it will always
35181e86
HZ		 9286 * be 1 on all machines.
9287 */
9288 u64 max = min(0x7fffffffULL,
9289 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9290 kvm_max_guest_tsc_khz = max;
9291
ad721883 9292 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 9293 }
ad721883 9294
9e9c3fe4
NA		 9295 kvm_init_msr_list();
9296 return 0;
e9b11c17
ZX		 9297}
9298
9299void kvm_arch_hardware_unsetup(void)
9300{
9301 kvm_x86_ops->hardware_unsetup();
9302}
9303
f257d6dc 9304int kvm_arch_check_processor_compat(void)
e9b11c17 9305{
f257d6dc 9306 return kvm_x86_ops->check_processor_compatibility();
d71ba788
PB		 9307}
9308
9309bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9310{
9311 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9312}
9313EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9314
9315bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9316{
9317 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 9318}
9319
54e9818f 9320struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 9321EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 9322
e9b11c17
ZX		 9323int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
9324{
9325 struct page *page;
e9b11c17
ZX		 9326 int r;
9327
9aabc88f 9328 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 9329 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 9330 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 9331 else
a4535290 9332 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 9333
9334 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9335 if (!page) {
9336 r = -ENOMEM;
9337 goto fail;
9338 }
ad312c7c 9339 vcpu->arch.pio_data = page_address(page);
e9b11c17 9340
cc578287 9341 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 9342
e9b11c17
ZX		 9343 r = kvm_mmu_create(vcpu);
9344 if (r < 0)
9345 goto fail_free_pio_data;
9346
26de7988 9347 if (irqchip_in_kernel(vcpu->kvm)) {
f7589cca 9348 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
39497d76 9349 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
e9b11c17
ZX		 9350 if (r < 0)
9351 goto fail_mmu_destroy;
54e9818f
GN		 9352 } else
9353 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 9354
890ca9ae 9355 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
254272ce 9356 GFP_KERNEL_ACCOUNT);
890ca9ae
HY		 9357 if (!vcpu->arch.mce_banks) {
9358 r = -ENOMEM;
443c39bc 9359 goto fail_free_lapic;
890ca9ae
HY		 9360 }
9361 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9362
254272ce
BG		 9363 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9364 GFP_KERNEL_ACCOUNT)) {
f1797359 9365 r = -ENOMEM;
f5f48ee1 9366 goto fail_free_mce_banks;
f1797359 9367 }
f5f48ee1 9368
0ee6a517 9369 fx_init(vcpu);
66f7b72e 9370
4344ee98 9371 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 9372
5a4f55cd
EK		 9373 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9374
74545705
RK		 9375 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9376
af585b92 9377 kvm_async_pf_hash_reset(vcpu);
f5132b01 9378 kvm_pmu_init(vcpu);
af585b92 9379
1c1a9ce9 9380 vcpu->arch.pending_external_vector = -1;
de63ad4c 9381 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 9382
5c919412
AS		 9383 kvm_hv_vcpu_init(vcpu);
9384
e9b11c17 9385 return 0;
0ee6a517 9386
f5f48ee1
SY		 9387fail_free_mce_banks:
9388 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 9389fail_free_lapic:
9390 kvm_free_lapic(vcpu);
e9b11c17
ZX		 9391fail_mmu_destroy:
9392 kvm_mmu_destroy(vcpu);
9393fail_free_pio_data:
ad312c7c 9394 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 9395fail:
9396 return r;
9397}
9398
9399void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
9400{
f656ce01
MT		 9401 int idx;
9402
1f4b34f8 9403 kvm_hv_vcpu_uninit(vcpu);
f5132b01 9404 kvm_pmu_destroy(vcpu);
36cb93fd 9405 kfree(vcpu->arch.mce_banks);
e9b11c17 9406 kvm_free_lapic(vcpu);
f656ce01 9407 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 9408 kvm_mmu_destroy(vcpu);
f656ce01 9409 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 9410 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 9411 if (!lapic_in_kernel(vcpu))
54e9818f 9412 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 9413}
d19a9cd2 9414
e790d9ef
RK		 9415void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9416{
c595ceee 9417 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 9418 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9419}
9420
e08b9637 9421int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9422{
e08b9637
CO		 9423 if (type)
9424 return -EINVAL;
9425
6ef768fa 9426 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9427 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
10605204 9428 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 9429 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9430 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9431
5550af4d
SY		 9432 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9433 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9434 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9435 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9436 &kvm->arch.irq_sources_bitmap);
5550af4d 9437
038f8c11 9438 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9439 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9440 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9441
9285ec4c 9442 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
d828199e 9443 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9444
6fbbde9a
DS		 9445 kvm->arch.guest_can_read_msr_platform_info = true;
9446
7e44e449 9447 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9448 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9449
cbc0236a 9450 kvm_hv_init_vm(kvm);
0eb05bf2 9451 kvm_page_track_init(kvm);
13d268ca 9452 kvm_mmu_init_vm(kvm);
0eb05bf2 9453
92735b1b 9454 return kvm_x86_ops->vm_init(kvm);
d19a9cd2
ZX		 9455}
9456
9457static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9458{
ec7660cc 9459 vcpu_load(vcpu);
d19a9cd2
ZX		 9460 kvm_mmu_unload(vcpu);
9461 vcpu_put(vcpu);
9462}
9463
9464static void kvm_free_vcpus(struct kvm *kvm)
9465{
9466 unsigned int i;
988a2cae 9467 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9468
9469 /*
9470 * Unpin any mmu pages first.
9471 */
af585b92
GN		 9472 kvm_for_each_vcpu(i, vcpu, kvm) {
9473 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9474 kvm_unload_vcpu_mmu(vcpu);
af585b92 9475 }
988a2cae
GN		 9476 kvm_for_each_vcpu(i, vcpu, kvm)
9477 kvm_arch_vcpu_free(vcpu);
9478
9479 mutex_lock(&kvm->lock);
9480 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9481 kvm->vcpus[i] = NULL;
d19a9cd2 9482
988a2cae
GN		 9483 atomic_set(&kvm->online_vcpus, 0);
9484 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9485}
9486
ad8ba2cd
SY		 9487void kvm_arch_sync_events(struct kvm *kvm)
9488{
332967a3 9489 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9490 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9491 kvm_free_pit(kvm);
ad8ba2cd
SY		 9492}
9493
1d8007bd 9494int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9495{
9496 int i, r;
25188b99 9497 unsigned long hva;
f0d648bd
PB		 9498 struct kvm_memslots *slots = kvm_memslots(kvm);
9499 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9500
9501 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9502 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9503 return -EINVAL;
9da0e4d5 9504
f0d648bd
PB		 9505 slot = id_to_memslot(slots, id);
9506 if (size) {
b21629da 9507 if (slot->npages)
f0d648bd
PB		 9508 return -EEXIST;
9509
9510 /*
9511 * MAP_SHARED to prevent internal slot pages from being moved
9512 * by fork()/COW.
9513 */
9514 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9515 MAP_SHARED | MAP_ANONYMOUS, 0);
9516 if (IS_ERR((void *)hva))
9517 return PTR_ERR((void *)hva);
9518 } else {
9519 if (!slot->npages)
9520 return 0;
9521
9522 hva = 0;
9523 }
9524
9525 old = *slot;
9da0e4d5 9526 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9527 struct kvm_userspace_memory_region m;
9da0e4d5 9528
1d8007bd
PB		 9529 m.slot = id | (i << 16);
9530 m.flags = 0;
9531 m.guest_phys_addr = gpa;
f0d648bd 9532 m.userspace_addr = hva;
1d8007bd 9533 m.memory_size = size;
9da0e4d5
PB		 9534 r = __kvm_set_memory_region(kvm, &m);
9535 if (r < 0)
9536 return r;
9537 }
9538
103c763c
EB		 9539 if (!size)
9540 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9541
9da0e4d5
PB		 9542 return 0;
9543}
9544EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9545
1d8007bd 9546int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9547{
9548 int r;
9549
9550 mutex_lock(&kvm->slots_lock);
1d8007bd 9551 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 9552 mutex_unlock(&kvm->slots_lock);
9553
9554 return r;
9555}
9556EXPORT_SYMBOL_GPL(x86_set_memory_region);
9557
d19a9cd2
ZX		 9558void kvm_arch_destroy_vm(struct kvm *kvm)
9559{
27469d29
AH		 9560 if (current->mm == kvm->mm) {
9561 /*
9562 * Free memory regions allocated on behalf of userspace,
9563 * unless the the memory map has changed due to process exit
9564 * or fd copying.
9565 */
1d8007bd
PB		 9566 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
9567 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
9568 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 9569 }
03543133
SS		 9570 if (kvm_x86_ops->vm_destroy)
9571 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9572 kvm_pic_destroy(kvm);
9573 kvm_ioapic_destroy(kvm);
d19a9cd2 9574 kvm_free_vcpus(kvm);
af1bae54 9575 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
66bb8a06 9576 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
13d268ca 9577 kvm_mmu_uninit_vm(kvm);
2beb6dad 9578 kvm_page_track_cleanup(kvm);
cbc0236a 9579 kvm_hv_destroy_vm(kvm);
d19a9cd2 9580}
0de10343 9581
5587027c 9582void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9583 struct kvm_memory_slot *dont)
9584{
9585 int i;
9586
d89cc617
TY		 9587 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9588 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9589 kvfree(free->arch.rmap[i]);
d89cc617 9590 free->arch.rmap[i] = NULL;
77d11309 9591 }
d89cc617
TY		 9592 if (i == 0)
9593 continue;
9594
9595 if (!dont || free->arch.lpage_info[i - 1] !=
9596 dont->arch.lpage_info[i - 1]) {
548ef284 9597 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9598 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9599 }
9600 }
21ebbeda
XG		 9601
9602 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9603}
9604
5587027c
AK		 9605int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9606 unsigned long npages)
db3fe4eb
TY		 9607{
9608 int i;
9609
d89cc617 9610 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9611 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9612 unsigned long ugfn;
9613 int lpages;
d89cc617 9614 int level = i + 1;
db3fe4eb
TY		 9615
9616 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9617 slot->base_gfn, level) + 1;
9618
d89cc617 9619 slot->arch.rmap[i] =
778e1cdd 9620 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
254272ce 9621 GFP_KERNEL_ACCOUNT);
d89cc617 9622 if (!slot->arch.rmap[i])
77d11309 9623 goto out_free;
d89cc617
TY		 9624 if (i == 0)
9625 continue;
77d11309 9626
254272ce 9627 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
92f94f1e 9628 if (!linfo)
db3fe4eb
TY		 9629 goto out_free;
9630
92f94f1e
XG		 9631 slot->arch.lpage_info[i - 1] = linfo;
9632
db3fe4eb 9633 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9634 linfo[0].disallow_lpage = 1;
db3fe4eb 9635 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9636 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9637 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9638 /*
9639 * If the gfn and userspace address are not aligned wrt each
9640 * other, or if explicitly asked to, disable large page
9641 * support for this slot
9642 */
9643 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9644 !kvm_largepages_enabled()) {
9645 unsigned long j;
9646
9647 for (j = 0; j < lpages; ++j)
92f94f1e 9648 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9649 }
9650 }
9651
21ebbeda
XG		 9652 if (kvm_page_track_create_memslot(slot, npages))
9653 goto out_free;
9654
db3fe4eb
TY		 9655 return 0;
9656
9657out_free:
d89cc617 9658 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9659 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9660 slot->arch.rmap[i] = NULL;
9661 if (i == 0)
9662 continue;
9663
548ef284 9664 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9665 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9666 }
9667 return -ENOMEM;
9668}
9669
15248258 9670void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
e59dbe09 9671{
e6dff7d1
TY		 9672 /*
9673 * memslots->generation has been incremented.
9674 * mmio generation may have reached its maximum value.
9675 */
15248258 9676 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
e59dbe09
TY		 9677}
9678
f7784b8e
MT		 9679int kvm_arch_prepare_memory_region(struct kvm *kvm,
9680 struct kvm_memory_slot *memslot,
09170a49 9681 const struct kvm_userspace_memory_region *mem,
7b6195a9 9682 enum kvm_mr_change change)
0de10343 9683{
f7784b8e
MT		 9684 return 0;
9685}
9686
88178fd4
KH		 9687static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9688 struct kvm_memory_slot *new)
9689{
9690 /* Still write protect RO slot */
9691 if (new->flags & KVM_MEM_READONLY) {
9692 kvm_mmu_slot_remove_write_access(kvm, new);
9693 return;
9694 }
9695
9696 /*
9697 * Call kvm_x86_ops dirty logging hooks when they are valid.
9698 *
9699 * kvm_x86_ops->slot_disable_log_dirty is called when:
9700 *
9701 * - KVM_MR_CREATE with dirty logging is disabled
9702 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9703 *
9704 * The reason is, in case of PML, we need to set D-bit for any slots
9705 * with dirty logging disabled in order to eliminate unnecessary GPA
9706 * logging in PML buffer (and potential PML buffer full VMEXT). This
9707 * guarantees leaving PML enabled during guest's lifetime won't have
bdd303cb 9708 * any additional overhead from PML when guest is running with dirty
88178fd4
KH		 9709 * logging disabled for memory slots.
9710 *
9711 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9712 * to dirty logging mode.
9713 *
9714 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9715 *
9716 * In case of write protect:
9717 *
9718 * Write protect all pages for dirty logging.
9719 *
9720 * All the sptes including the large sptes which point to this
9721 * slot are set to readonly. We can not create any new large
9722 * spte on this slot until the end of the logging.
9723 *
9724 * See the comments in fast_page_fault().
9725 */
9726 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9727 if (kvm_x86_ops->slot_enable_log_dirty)
9728 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9729 else
9730 kvm_mmu_slot_remove_write_access(kvm, new);
9731 } else {
9732 if (kvm_x86_ops->slot_disable_log_dirty)
9733 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9734 }
9735}
9736
f7784b8e 9737void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9738 const struct kvm_userspace_memory_region *mem,
8482644a 9739 const struct kvm_memory_slot *old,
f36f3f28 9740 const struct kvm_memory_slot *new,
8482644a 9741 enum kvm_mr_change change)
f7784b8e 9742{
48c0e4e9 9743 if (!kvm->arch.n_requested_mmu_pages)
4d66623c
WY		 9744 kvm_mmu_change_mmu_pages(kvm,
9745 kvm_mmu_calculate_default_mmu_pages(kvm));
1c91cad4 9746
3ea3b7fa
WL		 9747 /*
9748 * Dirty logging tracks sptes in 4k granularity, meaning that large
9749 * sptes have to be split. If live migration is successful, the guest
9750 * in the source machine will be destroyed and large sptes will be
9751 * created in the destination. However, if the guest continues to run
9752 * in the source machine (for example if live migration fails), small
9753 * sptes will remain around and cause bad performance.
9754 *
9755 * Scan sptes if dirty logging has been stopped, dropping those
9756 * which can be collapsed into a single large-page spte. Later
9757 * page faults will create the large-page sptes.
319109a2
SC		 9758 *
9759 * There is no need to do this in any of the following cases:
9760 * CREATE: No dirty mappings will already exist.
9761 * MOVE/DELETE: The old mappings will already have been cleaned up by
9762 * kvm_arch_flush_shadow_memslot()
3ea3b7fa 9763 */
319109a2 9764 if (change == KVM_MR_FLAGS_ONLY &&
3ea3b7fa
WL		 9765 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9766 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9767 kvm_mmu_zap_collapsible_sptes(kvm, new);
9768
c972f3b1 9769 /*
88178fd4 9770 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9771 *
88178fd4
KH		 9772 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9773 * been zapped so no dirty logging staff is needed for old slot. For
9774 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9775 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9776 *
9777 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9778 */
88178fd4 9779 if (change != KVM_MR_DELETE)
f36f3f28 9780 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9781}
1d737c8a 9782
2df72e9b 9783void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9784{
7390de1e 9785 kvm_mmu_zap_all(kvm);
34d4cb8f
MT		 9786}
9787
2df72e9b
MT		 9788void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9789 struct kvm_memory_slot *slot)
9790{
ae7cd873 9791 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9792}
9793
e6c67d8c
LA		 9794static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
9795{
9796 return (is_guest_mode(vcpu) &&
9797 kvm_x86_ops->guest_apic_has_interrupt &&
9798 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
9799}
9800
5d9bc648
PB		 9801static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9802{
9803 if (!list_empty_careful(&vcpu->async_pf.done))
9804 return true;
9805
9806 if (kvm_apic_has_events(vcpu))
9807 return true;
9808
9809 if (vcpu->arch.pv.pv_unhalted)
9810 return true;
9811
a5f01f8e
WL		 9812 if (vcpu->arch.exception.pending)
9813 return true;
9814
47a66eed
Z		 9815 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9816 (vcpu->arch.nmi_pending &&
9817 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9818 return true;
9819
47a66eed
Z		 9820 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9821 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9822 return true;
9823
5d9bc648 9824 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 9825 (kvm_cpu_has_interrupt(vcpu) ||
9826 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 9827 return true;
9828
1f4b34f8
AS		 9829 if (kvm_hv_has_stimer_pending(vcpu))
9830 return true;
9831
5d9bc648
PB		 9832 return false;
9833}
9834
1d737c8a
ZX		 9835int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9836{
5d9bc648 9837 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9838}
5736199a 9839
17e433b5
WL		 9840bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
9841{
9842 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
9843 return true;
9844
9845 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9846 kvm_test_request(KVM_REQ_SMI, vcpu) ||
9847 kvm_test_request(KVM_REQ_EVENT, vcpu))
9848 return true;
9849
9850 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
9851 return true;
9852
9853 return false;
9854}
9855
199b5763
LM		 9856bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9857{
de63ad4c 9858 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9859}
9860
b6d33834 9861int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9862{
b6d33834 9863 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9864}
78646121
GN		 9865
9866int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9867{
9868 return kvm_x86_ops->interrupt_allowed(vcpu);
9869}
229456fc 9870
82b32774 9871unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9872{
82b32774
NA		 9873 if (is_64_bit_mode(vcpu))
9874 return kvm_rip_read(vcpu);
9875 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9876 kvm_rip_read(vcpu));
9877}
9878EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9879
82b32774
NA		 9880bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9881{
9882 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9883}
9884EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9885
94fe45da
JK		 9886unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9887{
9888 unsigned long rflags;
9889
9890 rflags = kvm_x86_ops->get_rflags(vcpu);
9891 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9892 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9893 return rflags;
9894}
9895EXPORT_SYMBOL_GPL(kvm_get_rflags);
9896
6addfc42 9897static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9898{
9899 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9900 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9901 rflags |= X86_EFLAGS_TF;
94fe45da 9902 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9903}
9904
9905void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9906{
9907 __kvm_set_rflags(vcpu, rflags);
3842d135 9908 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9909}
9910EXPORT_SYMBOL_GPL(kvm_set_rflags);
9911
56028d08
GN		 9912void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9913{
9914 int r;
9915
44dd3ffa 9916 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 9917 work->wakeup_all)
56028d08
GN		 9918 return;
9919
9920 r = kvm_mmu_reload(vcpu);
9921 if (unlikely(r))
9922 return;
9923
44dd3ffa
VK		 9924 if (!vcpu->arch.mmu->direct_map &&
9925 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 9926 return;
9927
44dd3ffa 9928 vcpu->arch.mmu->page_fault(vcpu, work->gva, 0, true);
56028d08
GN		 9929}
9930
af585b92
GN		 9931static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9932{
9933 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9934}
9935
9936static inline u32 kvm_async_pf_next_probe(u32 key)
9937{
9938 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9939}
9940
9941static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9942{
9943 u32 key = kvm_async_pf_hash_fn(gfn);
9944
9945 while (vcpu->arch.apf.gfns[key] != ~0)
9946 key = kvm_async_pf_next_probe(key);
9947
9948 vcpu->arch.apf.gfns[key] = gfn;
9949}
9950
9951static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9952{
9953 int i;
9954 u32 key = kvm_async_pf_hash_fn(gfn);
9955
9956 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9957 (vcpu->arch.apf.gfns[key] != gfn &&
9958 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9959 key = kvm_async_pf_next_probe(key);
9960
9961 return key;
9962}
9963
9964bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9965{
9966 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9967}
9968
9969static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9970{
9971 u32 i, j, k;
9972
9973 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9974 while (true) {
9975 vcpu->arch.apf.gfns[i] = ~0;
9976 do {
9977 j = kvm_async_pf_next_probe(j);
9978 if (vcpu->arch.apf.gfns[j] == ~0)
9979 return;
9980 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9981 /*
9982 * k lies cyclically in ]i,j]
9983 * | i.k.j |
9984 * |....j i.k.| or |.k..j i...|
9985 */
9986 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9987 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9988 i = j;
9989 }
9990}
9991
7c90705b
GN		 9992static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9993{
4e335d9e
PB		 9994
9995 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9996 sizeof(val));
7c90705b
GN		 9997}
9998
9a6e7c39
WL		 9999static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10000{
10001
10002 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10003 sizeof(u32));
10004}
10005
1dfdb45e
PB		 10006static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10007{
10008 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10009 return false;
10010
10011 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10012 (vcpu->arch.apf.send_user_only &&
10013 kvm_x86_ops->get_cpl(vcpu) == 0))
10014 return false;
10015
10016 return true;
10017}
10018
10019bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10020{
10021 if (unlikely(!lapic_in_kernel(vcpu) ||
10022 kvm_event_needs_reinjection(vcpu) ||
10023 vcpu->arch.exception.pending))
10024 return false;
10025
10026 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10027 return false;
10028
10029 /*
10030 * If interrupts are off we cannot even use an artificial
10031 * halt state.
10032 */
10033 return kvm_x86_ops->interrupt_allowed(vcpu);
10034}
10035
af585b92
GN		 10036void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10037 struct kvm_async_pf *work)
10038{
6389ee94
AK		 10039 struct x86_exception fault;
10040
7c90705b 10041 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 10042 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b 10043
1dfdb45e
PB		 10044 if (kvm_can_deliver_async_pf(vcpu) &&
10045 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 10046 fault.vector = PF_VECTOR;
10047 fault.error_code_valid = true;
10048 fault.error_code = 0;
10049 fault.nested_page_fault = false;
10050 fault.address = work->arch.token;
adfe20fb 10051 fault.async_page_fault = true;
6389ee94 10052 kvm_inject_page_fault(vcpu, &fault);
1dfdb45e
PB		 10053 } else {
10054 /*
10055 * It is not possible to deliver a paravirtualized asynchronous
10056 * page fault, but putting the guest in an artificial halt state
10057 * can be beneficial nevertheless: if an interrupt arrives, we
10058 * can deliver it timely and perhaps the guest will schedule
10059 * another process. When the instruction that triggered a page
10060 * fault is retried, hopefully the page will be ready in the host.
10061 */
10062 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7c90705b 10063 }
af585b92
GN		 10064}
10065
10066void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10067 struct kvm_async_pf *work)
10068{
6389ee94 10069 struct x86_exception fault;
9a6e7c39 10070 u32 val;
6389ee94 10071
f2e10669 10072 if (work->wakeup_all)
7c90705b
GN		 10073 work->arch.token = ~0; /* broadcast wakeup */
10074 else
10075 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 10076 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 10077
9a6e7c39
WL		 10078 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10079 !apf_get_user(vcpu, &val)) {
10080 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10081 vcpu->arch.exception.pending &&
10082 vcpu->arch.exception.nr == PF_VECTOR &&
10083 !apf_put_user(vcpu, 0)) {
10084 vcpu->arch.exception.injected = false;
10085 vcpu->arch.exception.pending = false;
10086 vcpu->arch.exception.nr = 0;
10087 vcpu->arch.exception.has_error_code = false;
10088 vcpu->arch.exception.error_code = 0;
c851436a
JM		 10089 vcpu->arch.exception.has_payload = false;
10090 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 10091 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10092 fault.vector = PF_VECTOR;
10093 fault.error_code_valid = true;
10094 fault.error_code = 0;
10095 fault.nested_page_fault = false;
10096 fault.address = work->arch.token;
10097 fault.async_page_fault = true;
10098 kvm_inject_page_fault(vcpu, &fault);
10099 }
7c90705b 10100 }
e6d53e3b 10101 vcpu->arch.apf.halted = false;
a4fa1635 10102 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 10103}
10104
10105bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10106{
10107 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10108 return true;
10109 else
9bc1f09f 10110 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 10111}
10112
5544eb9b
PB		 10113void kvm_arch_start_assignment(struct kvm *kvm)
10114{
10115 atomic_inc(&kvm->arch.assigned_device_count);
10116}
10117EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10118
10119void kvm_arch_end_assignment(struct kvm *kvm)
10120{
10121 atomic_dec(&kvm->arch.assigned_device_count);
10122}
10123EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10124
10125bool kvm_arch_has_assigned_device(struct kvm *kvm)
10126{
10127 return atomic_read(&kvm->arch.assigned_device_count);
10128}
10129EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10130
e0f0bbc5
AW		 10131void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10132{
10133 atomic_inc(&kvm->arch.noncoherent_dma_count);
10134}
10135EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10136
10137void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10138{
10139 atomic_dec(&kvm->arch.noncoherent_dma_count);
10140}
10141EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10142
10143bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10144{
10145 return atomic_read(&kvm->arch.noncoherent_dma_count);
10146}
10147EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10148
14717e20
AW		 10149bool kvm_arch_has_irq_bypass(void)
10150{
92735b1b 10151 return true;
14717e20
AW		 10152}
10153
87276880
FW		 10154int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10155 struct irq_bypass_producer *prod)
10156{
10157 struct kvm_kernel_irqfd *irqfd =
10158 container_of(cons, struct kvm_kernel_irqfd, consumer);
10159
14717e20 10160 irqfd->producer = prod;
87276880 10161
14717e20
AW		 10162 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10163 prod->irq, irqfd->gsi, 1);
87276880
FW		 10164}
10165
10166void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10167 struct irq_bypass_producer *prod)
10168{
10169 int ret;
10170 struct kvm_kernel_irqfd *irqfd =
10171 container_of(cons, struct kvm_kernel_irqfd, consumer);
10172
87276880
FW		 10173 WARN_ON(irqfd->producer != prod);
10174 irqfd->producer = NULL;
10175
10176 /*
10177 * When producer of consumer is unregistered, we change back to
10178 * remapped mode, so we can re-use the current implementation
bb3541f1 10179 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 10180 * int this case doesn't want to receive the interrupts.
10181 */
10182 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10183 if (ret)
10184 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10185 " fails: %d\n", irqfd->consumer.token, ret);
10186}
10187
10188int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10189 uint32_t guest_irq, bool set)
10190{
87276880
FW		 10191 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10192}
10193
52004014
FW		 10194bool kvm_vector_hashing_enabled(void)
10195{
10196 return vector_hashing;
10197}
10198EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
10199
2d5ba19b
MT		 10200bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10201{
10202 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10203}
10204EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10205
10206
229456fc 10207EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 10208EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 10209EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10210EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10211EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10212EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 10213EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 10214EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 10215EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 10216EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
5497b955 10217EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
ec1ff790 10218EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 10219EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 10220EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 10221EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
4f75bcc3 10222EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
843e4330 10223EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 10224EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 10225EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10226EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)