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KVM: ignore AMDs HWCR register access to set the FFDIS bit
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
229456fc
MT		 40#define CREATE_TRACE_POINTS
41#include "trace.h"
043405e1
CO		 42
43#include <asm/uaccess.h>
d825ed0a 44#include <asm/msr.h>
a5f61300 45#include <asm/desc.h>
0bed3b56 46#include <asm/mtrr.h>
890ca9ae 47#include <asm/mce.h>
043405e1 48
313a3dc7 49#define MAX_IO_MSRS 256
a03490ed
CO		 50#define CR0_RESERVED_BITS \
51 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
52 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
53 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
54#define CR4_RESERVED_BITS \
55 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
56 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
57 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
58 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
59
60#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 61
62#define KVM_MAX_MCE_BANKS 32
63#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
64
50a37eb4
JR		 65/* EFER defaults:
66 * - enable syscall per default because its emulated by KVM
67 * - enable LME and LMA per default on 64 bit KVM
68 */
69#ifdef CONFIG_X86_64
70static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
71#else
72static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
73#endif
313a3dc7 74
ba1389b7
AK		 75#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
76#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 77
674eea0f
AK		 78static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
79 struct kvm_cpuid_entry2 __user *entries);
d8017474
AG		 80struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
81 u32 function, u32 index);
674eea0f 82
97896d04 83struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 84EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 85
417bc304 86struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 87 { "pf_fixed", VCPU_STAT(pf_fixed) },
88 { "pf_guest", VCPU_STAT(pf_guest) },
89 { "tlb_flush", VCPU_STAT(tlb_flush) },
90 { "invlpg", VCPU_STAT(invlpg) },
91 { "exits", VCPU_STAT(exits) },
92 { "io_exits", VCPU_STAT(io_exits) },
93 { "mmio_exits", VCPU_STAT(mmio_exits) },
94 { "signal_exits", VCPU_STAT(signal_exits) },
95 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 96 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 97 { "halt_exits", VCPU_STAT(halt_exits) },
98 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 99 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 100 { "request_irq", VCPU_STAT(request_irq_exits) },
101 { "irq_exits", VCPU_STAT(irq_exits) },
102 { "host_state_reload", VCPU_STAT(host_state_reload) },
103 { "efer_reload", VCPU_STAT(efer_reload) },
104 { "fpu_reload", VCPU_STAT(fpu_reload) },
105 { "insn_emulation", VCPU_STAT(insn_emulation) },
106 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 107 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 108 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 109 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
110 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
111 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
112 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
113 { "mmu_flooded", VM_STAT(mmu_flooded) },
114 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 115 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 116 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 117 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 118 { "largepages", VM_STAT(lpages) },
417bc304
HB		 119 { NULL }
120};
121
5fb76f9b
CO		 122unsigned long segment_base(u16 selector)
123{
124 struct descriptor_table gdt;
a5f61300 125 struct desc_struct *d;
5fb76f9b
CO		 126 unsigned long table_base;
127 unsigned long v;
128
129 if (selector == 0)
130 return 0;
131
132 asm("sgdt %0" : "=m"(gdt));
133 table_base = gdt.base;
134
135 if (selector & 4) { /* from ldt */
136 u16 ldt_selector;
137
138 asm("sldt %0" : "=g"(ldt_selector));
139 table_base = segment_base(ldt_selector);
140 }
a5f61300
AK		 141 d = (struct desc_struct *)(table_base + (selector & ~7));
142 v = d->base0 | ((unsigned long)d->base1 << 16) |
143 ((unsigned long)d->base2 << 24);
5fb76f9b 144#ifdef CONFIG_X86_64
a5f61300
AK		 145 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
146 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 147#endif
148 return v;
149}
150EXPORT_SYMBOL_GPL(segment_base);
151
6866b83e
CO		 152u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
153{
154 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 155 return vcpu->arch.apic_base;
6866b83e 156 else
ad312c7c 157 return vcpu->arch.apic_base;
6866b83e
CO		 158}
159EXPORT_SYMBOL_GPL(kvm_get_apic_base);
160
161void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
162{
163 /* TODO: reserve bits check */
164 if (irqchip_in_kernel(vcpu->kvm))
165 kvm_lapic_set_base(vcpu, data);
166 else
ad312c7c 167 vcpu->arch.apic_base = data;
6866b83e
CO		 168}
169EXPORT_SYMBOL_GPL(kvm_set_apic_base);
170
298101da
AK		 171void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
172{
ad312c7c
ZX		 173 WARN_ON(vcpu->arch.exception.pending);
174 vcpu->arch.exception.pending = true;
175 vcpu->arch.exception.has_error_code = false;
176 vcpu->arch.exception.nr = nr;
298101da
AK		 177}
178EXPORT_SYMBOL_GPL(kvm_queue_exception);
179
c3c91fee
AK		 180void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
181 u32 error_code)
182{
183 ++vcpu->stat.pf_guest;
d8017474 184
71c4dfaf 185 if (vcpu->arch.exception.pending) {
6edf14d8
GN		 186 switch(vcpu->arch.exception.nr) {
187 case DF_VECTOR:
71c4dfaf
JR		 188 /* triple fault -> shutdown */
189 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
6edf14d8
GN		 190 return;
191 case PF_VECTOR:
192 vcpu->arch.exception.nr = DF_VECTOR;
193 vcpu->arch.exception.error_code = 0;
194 return;
195 default:
196 /* replace previous exception with a new one in a hope
197 that instruction re-execution will regenerate lost
198 exception */
199 vcpu->arch.exception.pending = false;
200 break;
71c4dfaf 201 }
c3c91fee 202 }
ad312c7c 203 vcpu->arch.cr2 = addr;
c3c91fee
AK		 204 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
205}
206
3419ffc8
SY		 207void kvm_inject_nmi(struct kvm_vcpu *vcpu)
208{
209 vcpu->arch.nmi_pending = 1;
210}
211EXPORT_SYMBOL_GPL(kvm_inject_nmi);
212
298101da
AK		 213void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
214{
ad312c7c
ZX		 215 WARN_ON(vcpu->arch.exception.pending);
216 vcpu->arch.exception.pending = true;
217 vcpu->arch.exception.has_error_code = true;
218 vcpu->arch.exception.nr = nr;
219 vcpu->arch.exception.error_code = error_code;
298101da
AK		 220}
221EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
222
223static void __queue_exception(struct kvm_vcpu *vcpu)
224{
ad312c7c
ZX		 225 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
226 vcpu->arch.exception.has_error_code,
227 vcpu->arch.exception.error_code);
298101da
AK		 228}
229
a03490ed
CO		 230/*
231 * Load the pae pdptrs. Return true is they are all valid.
232 */
233int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
234{
235 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
236 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
237 int i;
238 int ret;
ad312c7c 239 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 240
a03490ed
CO		 241 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
242 offset * sizeof(u64), sizeof(pdpte));
243 if (ret < 0) {
244 ret = 0;
245 goto out;
246 }
247 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 248 if (is_present_gpte(pdpte[i]) &&
20c466b5 249 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 250 ret = 0;
251 goto out;
252 }
253 }
254 ret = 1;
255
ad312c7c 256 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 257 __set_bit(VCPU_EXREG_PDPTR,
258 (unsigned long *)&vcpu->arch.regs_avail);
259 __set_bit(VCPU_EXREG_PDPTR,
260 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 261out:
a03490ed
CO		 262
263 return ret;
264}
cc4b6871 265EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 266
d835dfec
AK		 267static bool pdptrs_changed(struct kvm_vcpu *vcpu)
268{
ad312c7c 269 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 270 bool changed = true;
271 int r;
272
273 if (is_long_mode(vcpu) || !is_pae(vcpu))
274 return false;
275
6de4f3ad
AK		 276 if (!test_bit(VCPU_EXREG_PDPTR,
277 (unsigned long *)&vcpu->arch.regs_avail))
278 return true;
279
ad312c7c 280 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 281 if (r < 0)
282 goto out;
ad312c7c 283 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 284out:
d835dfec
AK		 285
286 return changed;
287}
288
2d3ad1f4 289void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 290{
291 if (cr0 & CR0_RESERVED_BITS) {
292 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 293 cr0, vcpu->arch.cr0);
c1a5d4f9 294 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 295 return;
296 }
297
298 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
299 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 300 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 301 return;
302 }
303
304 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
305 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
306 "and a clear PE flag\n");
c1a5d4f9 307 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 308 return;
309 }
310
311 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
312#ifdef CONFIG_X86_64
ad312c7c 313 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 314 int cs_db, cs_l;
315
316 if (!is_pae(vcpu)) {
317 printk(KERN_DEBUG "set_cr0: #GP, start paging "
318 "in long mode while PAE is disabled\n");
c1a5d4f9 319 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 320 return;
321 }
322 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
323 if (cs_l) {
324 printk(KERN_DEBUG "set_cr0: #GP, start paging "
325 "in long mode while CS.L == 1\n");
c1a5d4f9 326 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 327 return;
328
329 }
330 } else
331#endif
ad312c7c 332 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 333 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
334 "reserved bits\n");
c1a5d4f9 335 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 336 return;
337 }
338
339 }
340
341 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 342 vcpu->arch.cr0 = cr0;
a03490ed 343
a03490ed 344 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 345 return;
346}
2d3ad1f4 347EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 348
2d3ad1f4 349void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 350{
2d3ad1f4 351 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 352}
2d3ad1f4 353EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 354
2d3ad1f4 355void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 356{
a2edf57f
AK		 357 unsigned long old_cr4 = vcpu->arch.cr4;
358 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
359
a03490ed
CO		 360 if (cr4 & CR4_RESERVED_BITS) {
361 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 362 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 363 return;
364 }
365
366 if (is_long_mode(vcpu)) {
367 if (!(cr4 & X86_CR4_PAE)) {
368 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
369 "in long mode\n");
c1a5d4f9 370 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 371 return;
372 }
a2edf57f
AK		 373 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
374 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 375 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 376 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 377 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 378 return;
379 }
380
381 if (cr4 & X86_CR4_VMXE) {
382 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 383 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 384 return;
385 }
386 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 387 vcpu->arch.cr4 = cr4;
5a41accd 388 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 389 kvm_mmu_reset_context(vcpu);
a03490ed 390}
2d3ad1f4 391EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 392
2d3ad1f4 393void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 394{
ad312c7c 395 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 396 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 397 kvm_mmu_flush_tlb(vcpu);
398 return;
399 }
400
a03490ed
CO		 401 if (is_long_mode(vcpu)) {
402 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
403 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 404 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 405 return;
406 }
407 } else {
408 if (is_pae(vcpu)) {
409 if (cr3 & CR3_PAE_RESERVED_BITS) {
410 printk(KERN_DEBUG
411 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 412 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 413 return;
414 }
415 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
416 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
417 "reserved bits\n");
c1a5d4f9 418 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 419 return;
420 }
421 }
422 /*
423 * We don't check reserved bits in nonpae mode, because
424 * this isn't enforced, and VMware depends on this.
425 */
426 }
427
a03490ed
CO		 428 /*
429 * Does the new cr3 value map to physical memory? (Note, we
430 * catch an invalid cr3 even in real-mode, because it would
431 * cause trouble later on when we turn on paging anyway.)
432 *
433 * A real CPU would silently accept an invalid cr3 and would
434 * attempt to use it - with largely undefined (and often hard
435 * to debug) behavior on the guest side.
436 */
437 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 438 kvm_inject_gp(vcpu, 0);
a03490ed 439 else {
ad312c7c
ZX		 440 vcpu->arch.cr3 = cr3;
441 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 442 }
a03490ed 443}
2d3ad1f4 444EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 445
2d3ad1f4 446void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 447{
448 if (cr8 & CR8_RESERVED_BITS) {
449 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 450 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 451 return;
452 }
453 if (irqchip_in_kernel(vcpu->kvm))
454 kvm_lapic_set_tpr(vcpu, cr8);
455 else
ad312c7c 456 vcpu->arch.cr8 = cr8;
a03490ed 457}
2d3ad1f4 458EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 459
2d3ad1f4 460unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 461{
462 if (irqchip_in_kernel(vcpu->kvm))
463 return kvm_lapic_get_cr8(vcpu);
464 else
ad312c7c 465 return vcpu->arch.cr8;
a03490ed 466}
2d3ad1f4 467EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 468
d8017474
AG		 469static inline u32 bit(int bitno)
470{
471 return 1 << (bitno & 31);
472}
473
043405e1
CO		 474/*
475 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
476 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
477 *
478 * This list is modified at module load time to reflect the
479 * capabilities of the host cpu.
480 */
481static u32 msrs_to_save[] = {
482 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
483 MSR_K6_STAR,
484#ifdef CONFIG_X86_64
485 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
486#endif
af24a4e4 487 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 488 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 489};
490
491static unsigned num_msrs_to_save;
492
493static u32 emulated_msrs[] = {
494 MSR_IA32_MISC_ENABLE,
495};
496
15c4a640
CO		 497static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
498{
f2b4b7dd 499 if (efer & efer_reserved_bits) {
15c4a640
CO		 500 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
501 efer);
c1a5d4f9 502 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 503 return;
504 }
505
506 if (is_paging(vcpu)
ad312c7c 507 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 508 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 509 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 510 return;
511 }
512
1b2fd70c
AG		 513 if (efer & EFER_FFXSR) {
514 struct kvm_cpuid_entry2 *feat;
515
516 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
517 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
518 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
519 kvm_inject_gp(vcpu, 0);
520 return;
521 }
522 }
523
d8017474
AG		 524 if (efer & EFER_SVME) {
525 struct kvm_cpuid_entry2 *feat;
526
527 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
528 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
529 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
530 kvm_inject_gp(vcpu, 0);
531 return;
532 }
533 }
534
15c4a640
CO		 535 kvm_x86_ops->set_efer(vcpu, efer);
536
537 efer &= ~EFER_LMA;
ad312c7c 538 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 539
ad312c7c 540 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 541
542 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
543 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 544}
545
f2b4b7dd
JR		 546void kvm_enable_efer_bits(u64 mask)
547{
548 efer_reserved_bits &= ~mask;
549}
550EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
551
552
15c4a640
CO		 553/*
554 * Writes msr value into into the appropriate "register".
555 * Returns 0 on success, non-0 otherwise.
556 * Assumes vcpu_load() was already called.
557 */
558int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
559{
560 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
561}
562
313a3dc7
CO		 563/*
564 * Adapt set_msr() to msr_io()'s calling convention
565 */
566static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
567{
568 return kvm_set_msr(vcpu, index, *data);
569}
570
18068523
GOC		 571static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
572{
573 static int version;
50d0a0f9
GH		 574 struct pvclock_wall_clock wc;
575 struct timespec now, sys, boot;
18068523
GOC		 576
577 if (!wall_clock)
578 return;
579
580 version++;
581
18068523
GOC		 582 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
583
50d0a0f9
GH		 584 /*
585 * The guest calculates current wall clock time by adding
586 * system time (updated by kvm_write_guest_time below) to the
587 * wall clock specified here. guest system time equals host
588 * system time for us, thus we must fill in host boot time here.
589 */
590 now = current_kernel_time();
591 ktime_get_ts(&sys);
592 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
593
594 wc.sec = boot.tv_sec;
595 wc.nsec = boot.tv_nsec;
596 wc.version = version;
18068523
GOC		 597
598 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
599
600 version++;
601 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 602}
603
50d0a0f9
GH		 604static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
605{
606 uint32_t quotient, remainder;
607
608 /* Don't try to replace with do_div(), this one calculates
609 * "(dividend << 32) / divisor" */
610 __asm__ ( "divl %4"
611 : "=a" (quotient), "=d" (remainder)
612 : "0" (0), "1" (dividend), "r" (divisor) );
613 return quotient;
614}
615
616static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
617{
618 uint64_t nsecs = 1000000000LL;
619 int32_t shift = 0;
620 uint64_t tps64;
621 uint32_t tps32;
622
623 tps64 = tsc_khz * 1000LL;
624 while (tps64 > nsecs*2) {
625 tps64 >>= 1;
626 shift--;
627 }
628
629 tps32 = (uint32_t)tps64;
630 while (tps32 <= (uint32_t)nsecs) {
631 tps32 <<= 1;
632 shift++;
633 }
634
635 hv_clock->tsc_shift = shift;
636 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
637
638 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 639 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 640 hv_clock->tsc_to_system_mul);
641}
642
c8076604
GH		 643static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
644
18068523
GOC		 645static void kvm_write_guest_time(struct kvm_vcpu *v)
646{
647 struct timespec ts;
648 unsigned long flags;
649 struct kvm_vcpu_arch *vcpu = &v->arch;
650 void *shared_kaddr;
463656c0 651 unsigned long this_tsc_khz;
18068523
GOC		 652
653 if ((!vcpu->time_page))
654 return;
655
463656c0
AK		 656 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
657 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
658 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
659 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 660 }
463656c0 661 put_cpu_var(cpu_tsc_khz);
50d0a0f9 662
18068523
GOC		 663 /* Keep irq disabled to prevent changes to the clock */
664 local_irq_save(flags);
af24a4e4 665 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 666 ktime_get_ts(&ts);
667 local_irq_restore(flags);
668
669 /* With all the info we got, fill in the values */
670
671 vcpu->hv_clock.system_time = ts.tv_nsec +
672 (NSEC_PER_SEC * (u64)ts.tv_sec);
673 /*
674 * The interface expects us to write an even number signaling that the
675 * update is finished. Since the guest won't see the intermediate
50d0a0f9 676 * state, we just increase by 2 at the end.
18068523 677 */
50d0a0f9 678 vcpu->hv_clock.version += 2;
18068523
GOC		 679
680 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
681
682 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 683 sizeof(vcpu->hv_clock));
18068523
GOC		 684
685 kunmap_atomic(shared_kaddr, KM_USER0);
686
687 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
688}
689
c8076604
GH		 690static int kvm_request_guest_time_update(struct kvm_vcpu *v)
691{
692 struct kvm_vcpu_arch *vcpu = &v->arch;
693
694 if (!vcpu->time_page)
695 return 0;
696 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
697 return 1;
698}
699
9ba075a6
AK		 700static bool msr_mtrr_valid(unsigned msr)
701{
702 switch (msr) {
703 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
704 case MSR_MTRRfix64K_00000:
705 case MSR_MTRRfix16K_80000:
706 case MSR_MTRRfix16K_A0000:
707 case MSR_MTRRfix4K_C0000:
708 case MSR_MTRRfix4K_C8000:
709 case MSR_MTRRfix4K_D0000:
710 case MSR_MTRRfix4K_D8000:
711 case MSR_MTRRfix4K_E0000:
712 case MSR_MTRRfix4K_E8000:
713 case MSR_MTRRfix4K_F0000:
714 case MSR_MTRRfix4K_F8000:
715 case MSR_MTRRdefType:
716 case MSR_IA32_CR_PAT:
717 return true;
718 case 0x2f8:
719 return true;
720 }
721 return false;
722}
723
d6289b93
MT		 724static bool valid_pat_type(unsigned t)
725{
726 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
727}
728
729static bool valid_mtrr_type(unsigned t)
730{
731 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
732}
733
734static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
735{
736 int i;
737
738 if (!msr_mtrr_valid(msr))
739 return false;
740
741 if (msr == MSR_IA32_CR_PAT) {
742 for (i = 0; i < 8; i++)
743 if (!valid_pat_type((data >> (i * 8)) & 0xff))
744 return false;
745 return true;
746 } else if (msr == MSR_MTRRdefType) {
747 if (data & ~0xcff)
748 return false;
749 return valid_mtrr_type(data & 0xff);
750 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
751 for (i = 0; i < 8 ; i++)
752 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
753 return false;
754 return true;
755 }
756
757 /* variable MTRRs */
758 return valid_mtrr_type(data & 0xff);
759}
760
9ba075a6
AK		 761static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
762{
0bed3b56
SY		 763 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
764
d6289b93 765 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 766 return 1;
767
0bed3b56
SY		 768 if (msr == MSR_MTRRdefType) {
769 vcpu->arch.mtrr_state.def_type = data;
770 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
771 } else if (msr == MSR_MTRRfix64K_00000)
772 p[0] = data;
773 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
774 p[1 + msr - MSR_MTRRfix16K_80000] = data;
775 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
776 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
777 else if (msr == MSR_IA32_CR_PAT)
778 vcpu->arch.pat = data;
779 else { /* Variable MTRRs */
780 int idx, is_mtrr_mask;
781 u64 *pt;
782
783 idx = (msr - 0x200) / 2;
784 is_mtrr_mask = msr - 0x200 - 2 * idx;
785 if (!is_mtrr_mask)
786 pt =
787 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
788 else
789 pt =
790 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
791 *pt = data;
792 }
793
794 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 795 return 0;
796}
15c4a640 797
890ca9ae 798static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 799{
890ca9ae
HY		 800 u64 mcg_cap = vcpu->arch.mcg_cap;
801 unsigned bank_num = mcg_cap & 0xff;
802
15c4a640 803 switch (msr) {
15c4a640 804 case MSR_IA32_MCG_STATUS:
890ca9ae 805 vcpu->arch.mcg_status = data;
15c4a640 806 break;
c7ac679c 807 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 808 if (!(mcg_cap & MCG_CTL_P))
809 return 1;
810 if (data != 0 && data != ~(u64)0)
811 return -1;
812 vcpu->arch.mcg_ctl = data;
813 break;
814 default:
815 if (msr >= MSR_IA32_MC0_CTL &&
816 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
817 u32 offset = msr - MSR_IA32_MC0_CTL;
818 /* only 0 or all 1s can be written to IA32_MCi_CTL */
819 if ((offset & 0x3) == 0 &&
820 data != 0 && data != ~(u64)0)
821 return -1;
822 vcpu->arch.mce_banks[offset] = data;
823 break;
824 }
825 return 1;
826 }
827 return 0;
828}
829
830int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
831{
832 switch (msr) {
833 case MSR_EFER:
834 set_efer(vcpu, data);
c7ac679c 835 break;
8f1589d9
AP		 836 case MSR_K7_HWCR:
837 data &= ~(u64)0x40; /* ignore flush filter disable */
838 if (data != 0) {
839 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
840 data);
841 return 1;
842 }
843 break;
b5e2fec0
AG		 844 case MSR_IA32_DEBUGCTLMSR:
845 if (!data) {
846 /* We support the non-activated case already */
847 break;
848 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
849 /* Values other than LBR and BTF are vendor-specific,
850 thus reserved and should throw a #GP */
851 return 1;
852 }
853 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
854 __func__, data);
855 break;
15c4a640
CO		 856 case MSR_IA32_UCODE_REV:
857 case MSR_IA32_UCODE_WRITE:
61a6bd67 858 case MSR_VM_HSAVE_PA:
15c4a640 859 break;
9ba075a6
AK		 860 case 0x200 ... 0x2ff:
861 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 862 case MSR_IA32_APICBASE:
863 kvm_set_apic_base(vcpu, data);
864 break;
865 case MSR_IA32_MISC_ENABLE:
ad312c7c 866 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 867 break;
18068523
GOC		 868 case MSR_KVM_WALL_CLOCK:
869 vcpu->kvm->arch.wall_clock = data;
870 kvm_write_wall_clock(vcpu->kvm, data);
871 break;
872 case MSR_KVM_SYSTEM_TIME: {
873 if (vcpu->arch.time_page) {
874 kvm_release_page_dirty(vcpu->arch.time_page);
875 vcpu->arch.time_page = NULL;
876 }
877
878 vcpu->arch.time = data;
879
880 /* we verify if the enable bit is set... */
881 if (!(data & 1))
882 break;
883
884 /* ...but clean it before doing the actual write */
885 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
886
18068523
GOC		 887 vcpu->arch.time_page =
888 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 889
890 if (is_error_page(vcpu->arch.time_page)) {
891 kvm_release_page_clean(vcpu->arch.time_page);
892 vcpu->arch.time_page = NULL;
893 }
894
c8076604 895 kvm_request_guest_time_update(vcpu);
18068523
GOC		 896 break;
897 }
890ca9ae
HY		 898 case MSR_IA32_MCG_CTL:
899 case MSR_IA32_MCG_STATUS:
900 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
901 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 902
903 /* Performance counters are not protected by a CPUID bit,
904 * so we should check all of them in the generic path for the sake of
905 * cross vendor migration.
906 * Writing a zero into the event select MSRs disables them,
907 * which we perfectly emulate ;-). Any other value should be at least
908 * reported, some guests depend on them.
909 */
910 case MSR_P6_EVNTSEL0:
911 case MSR_P6_EVNTSEL1:
912 case MSR_K7_EVNTSEL0:
913 case MSR_K7_EVNTSEL1:
914 case MSR_K7_EVNTSEL2:
915 case MSR_K7_EVNTSEL3:
916 if (data != 0)
917 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
918 "0x%x data 0x%llx\n", msr, data);
919 break;
920 /* at least RHEL 4 unconditionally writes to the perfctr registers,
921 * so we ignore writes to make it happy.
922 */
923 case MSR_P6_PERFCTR0:
924 case MSR_P6_PERFCTR1:
925 case MSR_K7_PERFCTR0:
926 case MSR_K7_PERFCTR1:
927 case MSR_K7_PERFCTR2:
928 case MSR_K7_PERFCTR3:
929 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
930 "0x%x data 0x%llx\n", msr, data);
931 break;
15c4a640 932 default:
565f1fbd 933 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 934 return 1;
935 }
936 return 0;
937}
938EXPORT_SYMBOL_GPL(kvm_set_msr_common);
939
940
941/*
942 * Reads an msr value (of 'msr_index') into 'pdata'.
943 * Returns 0 on success, non-0 otherwise.
944 * Assumes vcpu_load() was already called.
945 */
946int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
947{
948 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
949}
950
9ba075a6
AK		 951static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
952{
0bed3b56
SY		 953 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
954
9ba075a6
AK		 955 if (!msr_mtrr_valid(msr))
956 return 1;
957
0bed3b56
SY		 958 if (msr == MSR_MTRRdefType)
959 *pdata = vcpu->arch.mtrr_state.def_type +
960 (vcpu->arch.mtrr_state.enabled << 10);
961 else if (msr == MSR_MTRRfix64K_00000)
962 *pdata = p[0];
963 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
964 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
965 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
966 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
967 else if (msr == MSR_IA32_CR_PAT)
968 *pdata = vcpu->arch.pat;
969 else { /* Variable MTRRs */
970 int idx, is_mtrr_mask;
971 u64 *pt;
972
973 idx = (msr - 0x200) / 2;
974 is_mtrr_mask = msr - 0x200 - 2 * idx;
975 if (!is_mtrr_mask)
976 pt =
977 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
978 else
979 pt =
980 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
981 *pdata = *pt;
982 }
983
9ba075a6
AK		 984 return 0;
985}
986
890ca9ae 987static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 988{
989 u64 data;
890ca9ae
HY		 990 u64 mcg_cap = vcpu->arch.mcg_cap;
991 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 992
993 switch (msr) {
15c4a640
CO		 994 case MSR_IA32_P5_MC_ADDR:
995 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 996 data = 0;
997 break;
15c4a640 998 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 999 data = vcpu->arch.mcg_cap;
1000 break;
c7ac679c 1001 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1002 if (!(mcg_cap & MCG_CTL_P))
1003 return 1;
1004 data = vcpu->arch.mcg_ctl;
1005 break;
1006 case MSR_IA32_MCG_STATUS:
1007 data = vcpu->arch.mcg_status;
1008 break;
1009 default:
1010 if (msr >= MSR_IA32_MC0_CTL &&
1011 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1012 u32 offset = msr - MSR_IA32_MC0_CTL;
1013 data = vcpu->arch.mce_banks[offset];
1014 break;
1015 }
1016 return 1;
1017 }
1018 *pdata = data;
1019 return 0;
1020}
1021
1022int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1023{
1024 u64 data;
1025
1026 switch (msr) {
890ca9ae 1027 case MSR_IA32_PLATFORM_ID:
15c4a640 1028 case MSR_IA32_UCODE_REV:
15c4a640 1029 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1030 case MSR_IA32_DEBUGCTLMSR:
1031 case MSR_IA32_LASTBRANCHFROMIP:
1032 case MSR_IA32_LASTBRANCHTOIP:
1033 case MSR_IA32_LASTINTFROMIP:
1034 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1035 case MSR_K8_SYSCFG:
1036 case MSR_K7_HWCR:
61a6bd67 1037 case MSR_VM_HSAVE_PA:
7fe29e0f
AS		 1038 case MSR_P6_EVNTSEL0:
1039 case MSR_P6_EVNTSEL1:
9e699624 1040 case MSR_K7_EVNTSEL0:
15c4a640
CO		 1041 data = 0;
1042 break;
9ba075a6
AK		 1043 case MSR_MTRRcap:
1044 data = 0x500 | KVM_NR_VAR_MTRR;
1045 break;
1046 case 0x200 ... 0x2ff:
1047 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1048 case 0xcd: /* fsb frequency */
1049 data = 3;
1050 break;
1051 case MSR_IA32_APICBASE:
1052 data = kvm_get_apic_base(vcpu);
1053 break;
1054 case MSR_IA32_MISC_ENABLE:
ad312c7c 1055 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1056 break;
847f0ad8
AG		 1057 case MSR_IA32_PERF_STATUS:
1058 /* TSC increment by tick */
1059 data = 1000ULL;
1060 /* CPU multiplier */
1061 data |= (((uint64_t)4ULL) << 40);
1062 break;
15c4a640 1063 case MSR_EFER:
ad312c7c 1064 data = vcpu->arch.shadow_efer;
15c4a640 1065 break;
18068523
GOC		 1066 case MSR_KVM_WALL_CLOCK:
1067 data = vcpu->kvm->arch.wall_clock;
1068 break;
1069 case MSR_KVM_SYSTEM_TIME:
1070 data = vcpu->arch.time;
1071 break;
890ca9ae
HY		 1072 case MSR_IA32_P5_MC_ADDR:
1073 case MSR_IA32_P5_MC_TYPE:
1074 case MSR_IA32_MCG_CAP:
1075 case MSR_IA32_MCG_CTL:
1076 case MSR_IA32_MCG_STATUS:
1077 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1078 return get_msr_mce(vcpu, msr, pdata);
15c4a640
CO		 1079 default:
1080 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1081 return 1;
1082 }
1083 *pdata = data;
1084 return 0;
1085}
1086EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1087
313a3dc7
CO		 1088/*
1089 * Read or write a bunch of msrs. All parameters are kernel addresses.
1090 *
1091 * @return number of msrs set successfully.
1092 */
1093static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1094 struct kvm_msr_entry *entries,
1095 int (*do_msr)(struct kvm_vcpu *vcpu,
1096 unsigned index, u64 *data))
1097{
1098 int i;
1099
1100 vcpu_load(vcpu);
1101
3200f405 1102 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1103 for (i = 0; i < msrs->nmsrs; ++i)
1104 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1105 break;
3200f405 1106 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1107
1108 vcpu_put(vcpu);
1109
1110 return i;
1111}
1112
1113/*
1114 * Read or write a bunch of msrs. Parameters are user addresses.
1115 *
1116 * @return number of msrs set successfully.
1117 */
1118static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1119 int (*do_msr)(struct kvm_vcpu *vcpu,
1120 unsigned index, u64 *data),
1121 int writeback)
1122{
1123 struct kvm_msrs msrs;
1124 struct kvm_msr_entry *entries;
1125 int r, n;
1126 unsigned size;
1127
1128 r = -EFAULT;
1129 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1130 goto out;
1131
1132 r = -E2BIG;
1133 if (msrs.nmsrs >= MAX_IO_MSRS)
1134 goto out;
1135
1136 r = -ENOMEM;
1137 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1138 entries = vmalloc(size);
1139 if (!entries)
1140 goto out;
1141
1142 r = -EFAULT;
1143 if (copy_from_user(entries, user_msrs->entries, size))
1144 goto out_free;
1145
1146 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1147 if (r < 0)
1148 goto out_free;
1149
1150 r = -EFAULT;
1151 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1152 goto out_free;
1153
1154 r = n;
1155
1156out_free:
1157 vfree(entries);
1158out:
1159 return r;
1160}
1161
018d00d2
ZX		 1162int kvm_dev_ioctl_check_extension(long ext)
1163{
1164 int r;
1165
1166 switch (ext) {
1167 case KVM_CAP_IRQCHIP:
1168 case KVM_CAP_HLT:
1169 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1170 case KVM_CAP_SET_TSS_ADDR:
07716717 1171 case KVM_CAP_EXT_CPUID:
c8076604 1172 case KVM_CAP_CLOCKSOURCE:
7837699f 1173 case KVM_CAP_PIT:
a28e4f5a 1174 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1175 case KVM_CAP_MP_STATE:
ed848624 1176 case KVM_CAP_SYNC_MMU:
52d939a0 1177 case KVM_CAP_REINJECT_CONTROL:
4925663a 1178 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1179 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1180 case KVM_CAP_IRQFD:
c5ff41ce 1181 case KVM_CAP_PIT2:
018d00d2
ZX		 1182 r = 1;
1183 break;
542472b5
LV		 1184 case KVM_CAP_COALESCED_MMIO:
1185 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1186 break;
774ead3a
AK		 1187 case KVM_CAP_VAPIC:
1188 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1189 break;
f725230a
AK		 1190 case KVM_CAP_NR_VCPUS:
1191 r = KVM_MAX_VCPUS;
1192 break;
a988b910
AK		 1193 case KVM_CAP_NR_MEMSLOTS:
1194 r = KVM_MEMORY_SLOTS;
1195 break;
2f333bcb
MT		 1196 case KVM_CAP_PV_MMU:
1197 r = !tdp_enabled;
1198 break;
62c476c7 1199 case KVM_CAP_IOMMU:
19de40a8 1200 r = iommu_found();
62c476c7 1201 break;
890ca9ae
HY		 1202 case KVM_CAP_MCE:
1203 r = KVM_MAX_MCE_BANKS;
1204 break;
018d00d2
ZX		 1205 default:
1206 r = 0;
1207 break;
1208 }
1209 return r;
1210
1211}
1212
043405e1
CO		 1213long kvm_arch_dev_ioctl(struct file *filp,
1214 unsigned int ioctl, unsigned long arg)
1215{
1216 void __user *argp = (void __user *)arg;
1217 long r;
1218
1219 switch (ioctl) {
1220 case KVM_GET_MSR_INDEX_LIST: {
1221 struct kvm_msr_list __user *user_msr_list = argp;
1222 struct kvm_msr_list msr_list;
1223 unsigned n;
1224
1225 r = -EFAULT;
1226 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1227 goto out;
1228 n = msr_list.nmsrs;
1229 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1230 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1231 goto out;
1232 r = -E2BIG;
e125e7b6 1233 if (n < msr_list.nmsrs)
043405e1
CO		 1234 goto out;
1235 r = -EFAULT;
1236 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1237 num_msrs_to_save * sizeof(u32)))
1238 goto out;
e125e7b6 1239 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1240 &emulated_msrs,
1241 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1242 goto out;
1243 r = 0;
1244 break;
1245 }
674eea0f
AK		 1246 case KVM_GET_SUPPORTED_CPUID: {
1247 struct kvm_cpuid2 __user *cpuid_arg = argp;
1248 struct kvm_cpuid2 cpuid;
1249
1250 r = -EFAULT;
1251 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1252 goto out;
1253 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1254 cpuid_arg->entries);
674eea0f
AK		 1255 if (r)
1256 goto out;
1257
1258 r = -EFAULT;
1259 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1260 goto out;
1261 r = 0;
1262 break;
1263 }
890ca9ae
HY		 1264 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1265 u64 mce_cap;
1266
1267 mce_cap = KVM_MCE_CAP_SUPPORTED;
1268 r = -EFAULT;
1269 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1270 goto out;
1271 r = 0;
1272 break;
1273 }
043405e1
CO		 1274 default:
1275 r = -EINVAL;
1276 }
1277out:
1278 return r;
1279}
1280
313a3dc7
CO		 1281void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1282{
1283 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1284 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1285}
1286
1287void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1288{
1289 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1290 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1291}
1292
07716717 1293static int is_efer_nx(void)
313a3dc7 1294{
e286e86e 1295 unsigned long long efer = 0;
313a3dc7 1296
e286e86e 1297 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1298 return efer & EFER_NX;
1299}
1300
1301static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1302{
1303 int i;
1304 struct kvm_cpuid_entry2 *e, *entry;
1305
313a3dc7 1306 entry = NULL;
ad312c7c
ZX		 1307 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1308 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1309 if (e->function == 0x80000001) {
1310 entry = e;
1311 break;
1312 }
1313 }
07716717 1314 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1315 entry->edx &= ~(1 << 20);
1316 printk(KERN_INFO "kvm: guest NX capability removed\n");
1317 }
1318}
1319
07716717 1320/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1321static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1322 struct kvm_cpuid *cpuid,
1323 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1324{
1325 int r, i;
1326 struct kvm_cpuid_entry *cpuid_entries;
1327
1328 r = -E2BIG;
1329 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1330 goto out;
1331 r = -ENOMEM;
1332 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1333 if (!cpuid_entries)
1334 goto out;
1335 r = -EFAULT;
1336 if (copy_from_user(cpuid_entries, entries,
1337 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1338 goto out_free;
1339 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1340 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1341 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1342 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1343 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1344 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1345 vcpu->arch.cpuid_entries[i].index = 0;
1346 vcpu->arch.cpuid_entries[i].flags = 0;
1347 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1348 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1349 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1350 }
1351 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1352 cpuid_fix_nx_cap(vcpu);
1353 r = 0;
1354
1355out_free:
1356 vfree(cpuid_entries);
1357out:
1358 return r;
1359}
1360
1361static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1362 struct kvm_cpuid2 *cpuid,
1363 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1364{
1365 int r;
1366
1367 r = -E2BIG;
1368 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1369 goto out;
1370 r = -EFAULT;
ad312c7c 1371 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1372 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1373 goto out;
ad312c7c 1374 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1375 return 0;
1376
1377out:
1378 return r;
1379}
1380
07716717 1381static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1382 struct kvm_cpuid2 *cpuid,
1383 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1384{
1385 int r;
1386
1387 r = -E2BIG;
ad312c7c 1388 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1389 goto out;
1390 r = -EFAULT;
ad312c7c 1391 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1392 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1393 goto out;
1394 return 0;
1395
1396out:
ad312c7c 1397 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1398 return r;
1399}
1400
07716717 1401static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1402 u32 index)
07716717
DK		 1403{
1404 entry->function = function;
1405 entry->index = index;
1406 cpuid_count(entry->function, entry->index,
19355475 1407 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1408 entry->flags = 0;
1409}
1410
7faa4ee1
AK		 1411#define F(x) bit(X86_FEATURE_##x)
1412
07716717
DK		 1413static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1414 u32 index, int *nent, int maxnent)
1415{
7faa4ee1 1416 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1417#ifdef CONFIG_X86_64
7faa4ee1
AK		 1418 unsigned f_lm = F(LM);
1419#else
1420 unsigned f_lm = 0;
07716717 1421#endif
7faa4ee1
AK		 1422
1423 /* cpuid 1.edx */
1424 const u32 kvm_supported_word0_x86_features =
1425 F(FPU) | F(VME) | F(DE) | F(PSE) |
1426 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1427 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1428 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1429 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1430 0 /* Reserved, DS, ACPI */ | F(MMX) |
1431 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1432 0 /* HTT, TM, Reserved, PBE */;
1433 /* cpuid 0x80000001.edx */
1434 const u32 kvm_supported_word1_x86_features =
1435 F(FPU) | F(VME) | F(DE) | F(PSE) |
1436 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1437 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1438 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1439 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1440 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1441 F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
1442 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1443 /* cpuid 1.ecx */
1444 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1445 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1446 0 /* DS-CPL, VMX, SMX, EST */ |
1447 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1448 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1449 0 /* Reserved, DCA */ | F(XMM4_1) |
1450 F(XMM4_2) | 0 /* x2APIC */ | F(MOVBE) | F(POPCNT) |
1451 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1452 /* cpuid 0x80000001.ecx */
07716717 1453 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1454 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1455 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1456 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1457 0 /* SKINIT */ | 0 /* WDT */;
07716717 1458
19355475 1459 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1460 get_cpu();
1461 do_cpuid_1_ent(entry, function, index);
1462 ++*nent;
1463
1464 switch (function) {
1465 case 0:
1466 entry->eax = min(entry->eax, (u32)0xb);
1467 break;
1468 case 1:
1469 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1470 entry->ecx &= kvm_supported_word4_x86_features;
07716717
DK		 1471 break;
1472 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1473 * may return different values. This forces us to get_cpu() before
1474 * issuing the first command, and also to emulate this annoying behavior
1475 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1476 case 2: {
1477 int t, times = entry->eax & 0xff;
1478
1479 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1480 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1481 for (t = 1; t < times && *nent < maxnent; ++t) {
1482 do_cpuid_1_ent(&entry[t], function, 0);
1483 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1484 ++*nent;
1485 }
1486 break;
1487 }
1488 /* function 4 and 0xb have additional index. */
1489 case 4: {
14af3f3c 1490 int i, cache_type;
07716717
DK		 1491
1492 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1493 /* read more entries until cache_type is zero */
14af3f3c
HH		 1494 for (i = 1; *nent < maxnent; ++i) {
1495 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1496 if (!cache_type)
1497 break;
14af3f3c
HH		 1498 do_cpuid_1_ent(&entry[i], function, i);
1499 entry[i].flags |=
07716717
DK		 1500 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1501 ++*nent;
1502 }
1503 break;
1504 }
1505 case 0xb: {
14af3f3c 1506 int i, level_type;
07716717
DK		 1507
1508 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1509 /* read more entries until level_type is zero */
14af3f3c 1510 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1511 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1512 if (!level_type)
1513 break;
14af3f3c
HH		 1514 do_cpuid_1_ent(&entry[i], function, i);
1515 entry[i].flags |=
07716717
DK		 1516 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1517 ++*nent;
1518 }
1519 break;
1520 }
1521 case 0x80000000:
1522 entry->eax = min(entry->eax, 0x8000001a);
1523 break;
1524 case 0x80000001:
1525 entry->edx &= kvm_supported_word1_x86_features;
1526 entry->ecx &= kvm_supported_word6_x86_features;
1527 break;
1528 }
1529 put_cpu();
1530}
1531
7faa4ee1
AK		 1532#undef F
1533
674eea0f 1534static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1535 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1536{
1537 struct kvm_cpuid_entry2 *cpuid_entries;
1538 int limit, nent = 0, r = -E2BIG;
1539 u32 func;
1540
1541 if (cpuid->nent < 1)
1542 goto out;
1543 r = -ENOMEM;
1544 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1545 if (!cpuid_entries)
1546 goto out;
1547
1548 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1549 limit = cpuid_entries[0].eax;
1550 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1551 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1552 &nent, cpuid->nent);
07716717
DK		 1553 r = -E2BIG;
1554 if (nent >= cpuid->nent)
1555 goto out_free;
1556
1557 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1558 limit = cpuid_entries[nent - 1].eax;
1559 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1560 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1561 &nent, cpuid->nent);
cb007648
MM		 1562 r = -E2BIG;
1563 if (nent >= cpuid->nent)
1564 goto out_free;
1565
07716717
DK		 1566 r = -EFAULT;
1567 if (copy_to_user(entries, cpuid_entries,
19355475 1568 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1569 goto out_free;
1570 cpuid->nent = nent;
1571 r = 0;
1572
1573out_free:
1574 vfree(cpuid_entries);
1575out:
1576 return r;
1577}
1578
313a3dc7
CO		 1579static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1580 struct kvm_lapic_state *s)
1581{
1582 vcpu_load(vcpu);
ad312c7c 1583 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1584 vcpu_put(vcpu);
1585
1586 return 0;
1587}
1588
1589static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1590 struct kvm_lapic_state *s)
1591{
1592 vcpu_load(vcpu);
ad312c7c 1593 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1594 kvm_apic_post_state_restore(vcpu);
1595 vcpu_put(vcpu);
1596
1597 return 0;
1598}
1599
f77bc6a4
ZX		 1600static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1601 struct kvm_interrupt *irq)
1602{
1603 if (irq->irq < 0 || irq->irq >= 256)
1604 return -EINVAL;
1605 if (irqchip_in_kernel(vcpu->kvm))
1606 return -ENXIO;
1607 vcpu_load(vcpu);
1608
66fd3f7f 1609 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1610
1611 vcpu_put(vcpu);
1612
1613 return 0;
1614}
1615
c4abb7c9
JK		 1616static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1617{
1618 vcpu_load(vcpu);
1619 kvm_inject_nmi(vcpu);
1620 vcpu_put(vcpu);
1621
1622 return 0;
1623}
1624
b209749f
AK		 1625static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1626 struct kvm_tpr_access_ctl *tac)
1627{
1628 if (tac->flags)
1629 return -EINVAL;
1630 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1631 return 0;
1632}
1633
890ca9ae
HY		 1634static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1635 u64 mcg_cap)
1636{
1637 int r;
1638 unsigned bank_num = mcg_cap & 0xff, bank;
1639
1640 r = -EINVAL;
1641 if (!bank_num)
1642 goto out;
1643 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1644 goto out;
1645 r = 0;
1646 vcpu->arch.mcg_cap = mcg_cap;
1647 /* Init IA32_MCG_CTL to all 1s */
1648 if (mcg_cap & MCG_CTL_P)
1649 vcpu->arch.mcg_ctl = ~(u64)0;
1650 /* Init IA32_MCi_CTL to all 1s */
1651 for (bank = 0; bank < bank_num; bank++)
1652 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1653out:
1654 return r;
1655}
1656
1657static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1658 struct kvm_x86_mce *mce)
1659{
1660 u64 mcg_cap = vcpu->arch.mcg_cap;
1661 unsigned bank_num = mcg_cap & 0xff;
1662 u64 *banks = vcpu->arch.mce_banks;
1663
1664 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1665 return -EINVAL;
1666 /*
1667 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1668 * reporting is disabled
1669 */
1670 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1671 vcpu->arch.mcg_ctl != ~(u64)0)
1672 return 0;
1673 banks += 4 * mce->bank;
1674 /*
1675 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1676 * reporting is disabled for the bank
1677 */
1678 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1679 return 0;
1680 if (mce->status & MCI_STATUS_UC) {
1681 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1682 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1683 printk(KERN_DEBUG "kvm: set_mce: "
1684 "injects mce exception while "
1685 "previous one is in progress!\n");
1686 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1687 return 0;
1688 }
1689 if (banks[1] & MCI_STATUS_VAL)
1690 mce->status |= MCI_STATUS_OVER;
1691 banks[2] = mce->addr;
1692 banks[3] = mce->misc;
1693 vcpu->arch.mcg_status = mce->mcg_status;
1694 banks[1] = mce->status;
1695 kvm_queue_exception(vcpu, MC_VECTOR);
1696 } else if (!(banks[1] & MCI_STATUS_VAL)
1697 || !(banks[1] & MCI_STATUS_UC)) {
1698 if (banks[1] & MCI_STATUS_VAL)
1699 mce->status |= MCI_STATUS_OVER;
1700 banks[2] = mce->addr;
1701 banks[3] = mce->misc;
1702 banks[1] = mce->status;
1703 } else
1704 banks[1] |= MCI_STATUS_OVER;
1705 return 0;
1706}
1707
313a3dc7
CO		 1708long kvm_arch_vcpu_ioctl(struct file *filp,
1709 unsigned int ioctl, unsigned long arg)
1710{
1711 struct kvm_vcpu *vcpu = filp->private_data;
1712 void __user *argp = (void __user *)arg;
1713 int r;
b772ff36 1714 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1715
1716 switch (ioctl) {
1717 case KVM_GET_LAPIC: {
b772ff36 1718 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1719
b772ff36
DH		 1720 r = -ENOMEM;
1721 if (!lapic)
1722 goto out;
1723 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1724 if (r)
1725 goto out;
1726 r = -EFAULT;
b772ff36 1727 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1728 goto out;
1729 r = 0;
1730 break;
1731 }
1732 case KVM_SET_LAPIC: {
b772ff36
DH		 1733 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1734 r = -ENOMEM;
1735 if (!lapic)
1736 goto out;
313a3dc7 1737 r = -EFAULT;
b772ff36 1738 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1739 goto out;
b772ff36 1740 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1741 if (r)
1742 goto out;
1743 r = 0;
1744 break;
1745 }
f77bc6a4
ZX		 1746 case KVM_INTERRUPT: {
1747 struct kvm_interrupt irq;
1748
1749 r = -EFAULT;
1750 if (copy_from_user(&irq, argp, sizeof irq))
1751 goto out;
1752 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1753 if (r)
1754 goto out;
1755 r = 0;
1756 break;
1757 }
c4abb7c9
JK		 1758 case KVM_NMI: {
1759 r = kvm_vcpu_ioctl_nmi(vcpu);
1760 if (r)
1761 goto out;
1762 r = 0;
1763 break;
1764 }
313a3dc7
CO		 1765 case KVM_SET_CPUID: {
1766 struct kvm_cpuid __user *cpuid_arg = argp;
1767 struct kvm_cpuid cpuid;
1768
1769 r = -EFAULT;
1770 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1771 goto out;
1772 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1773 if (r)
1774 goto out;
1775 break;
1776 }
07716717
DK		 1777 case KVM_SET_CPUID2: {
1778 struct kvm_cpuid2 __user *cpuid_arg = argp;
1779 struct kvm_cpuid2 cpuid;
1780
1781 r = -EFAULT;
1782 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1783 goto out;
1784 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1785 cpuid_arg->entries);
07716717
DK		 1786 if (r)
1787 goto out;
1788 break;
1789 }
1790 case KVM_GET_CPUID2: {
1791 struct kvm_cpuid2 __user *cpuid_arg = argp;
1792 struct kvm_cpuid2 cpuid;
1793
1794 r = -EFAULT;
1795 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1796 goto out;
1797 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1798 cpuid_arg->entries);
07716717
DK		 1799 if (r)
1800 goto out;
1801 r = -EFAULT;
1802 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1803 goto out;
1804 r = 0;
1805 break;
1806 }
313a3dc7
CO		 1807 case KVM_GET_MSRS:
1808 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1809 break;
1810 case KVM_SET_MSRS:
1811 r = msr_io(vcpu, argp, do_set_msr, 0);
1812 break;
b209749f
AK		 1813 case KVM_TPR_ACCESS_REPORTING: {
1814 struct kvm_tpr_access_ctl tac;
1815
1816 r = -EFAULT;
1817 if (copy_from_user(&tac, argp, sizeof tac))
1818 goto out;
1819 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1820 if (r)
1821 goto out;
1822 r = -EFAULT;
1823 if (copy_to_user(argp, &tac, sizeof tac))
1824 goto out;
1825 r = 0;
1826 break;
1827 };
b93463aa
AK		 1828 case KVM_SET_VAPIC_ADDR: {
1829 struct kvm_vapic_addr va;
1830
1831 r = -EINVAL;
1832 if (!irqchip_in_kernel(vcpu->kvm))
1833 goto out;
1834 r = -EFAULT;
1835 if (copy_from_user(&va, argp, sizeof va))
1836 goto out;
1837 r = 0;
1838 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1839 break;
1840 }
890ca9ae
HY		 1841 case KVM_X86_SETUP_MCE: {
1842 u64 mcg_cap;
1843
1844 r = -EFAULT;
1845 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1846 goto out;
1847 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1848 break;
1849 }
1850 case KVM_X86_SET_MCE: {
1851 struct kvm_x86_mce mce;
1852
1853 r = -EFAULT;
1854 if (copy_from_user(&mce, argp, sizeof mce))
1855 goto out;
1856 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1857 break;
1858 }
313a3dc7
CO		 1859 default:
1860 r = -EINVAL;
1861 }
1862out:
7a6ce84c 1863 kfree(lapic);
313a3dc7
CO		 1864 return r;
1865}
1866
1fe779f8
CO		 1867static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1868{
1869 int ret;
1870
1871 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1872 return -1;
1873 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1874 return ret;
1875}
1876
1877static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1878 u32 kvm_nr_mmu_pages)
1879{
1880 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1881 return -EINVAL;
1882
72dc67a6 1883 down_write(&kvm->slots_lock);
7c8a83b7 1884 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1885
1886 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1887 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1888
7c8a83b7 1889 spin_unlock(&kvm->mmu_lock);
72dc67a6 1890 up_write(&kvm->slots_lock);
1fe779f8
CO		 1891 return 0;
1892}
1893
1894static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1895{
f05e70ac 1896 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1897}
1898
e9f85cde
ZX		 1899gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1900{
1901 int i;
1902 struct kvm_mem_alias *alias;
1903
d69fb81f
ZX		 1904 for (i = 0; i < kvm->arch.naliases; ++i) {
1905 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1906 if (gfn >= alias->base_gfn
1907 && gfn < alias->base_gfn + alias->npages)
1908 return alias->target_gfn + gfn - alias->base_gfn;
1909 }
1910 return gfn;
1911}
1912
1fe779f8
CO		 1913/*
1914 * Set a new alias region. Aliases map a portion of physical memory into
1915 * another portion. This is useful for memory windows, for example the PC
1916 * VGA region.
1917 */
1918static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1919 struct kvm_memory_alias *alias)
1920{
1921 int r, n;
1922 struct kvm_mem_alias *p;
1923
1924 r = -EINVAL;
1925 /* General sanity checks */
1926 if (alias->memory_size & (PAGE_SIZE - 1))
1927 goto out;
1928 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1929 goto out;
1930 if (alias->slot >= KVM_ALIAS_SLOTS)
1931 goto out;
1932 if (alias->guest_phys_addr + alias->memory_size
1933 < alias->guest_phys_addr)
1934 goto out;
1935 if (alias->target_phys_addr + alias->memory_size
1936 < alias->target_phys_addr)
1937 goto out;
1938
72dc67a6 1939 down_write(&kvm->slots_lock);
a1708ce8 1940 spin_lock(&kvm->mmu_lock);
1fe779f8 1941
d69fb81f 1942 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1943 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1944 p->npages = alias->memory_size >> PAGE_SHIFT;
1945 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1946
1947 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1948 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1949 break;
d69fb81f 1950 kvm->arch.naliases = n;
1fe779f8 1951
a1708ce8 1952 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1953 kvm_mmu_zap_all(kvm);
1954
72dc67a6 1955 up_write(&kvm->slots_lock);
1fe779f8
CO		 1956
1957 return 0;
1958
1959out:
1960 return r;
1961}
1962
1963static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1964{
1965 int r;
1966
1967 r = 0;
1968 switch (chip->chip_id) {
1969 case KVM_IRQCHIP_PIC_MASTER:
1970 memcpy(&chip->chip.pic,
1971 &pic_irqchip(kvm)->pics[0],
1972 sizeof(struct kvm_pic_state));
1973 break;
1974 case KVM_IRQCHIP_PIC_SLAVE:
1975 memcpy(&chip->chip.pic,
1976 &pic_irqchip(kvm)->pics[1],
1977 sizeof(struct kvm_pic_state));
1978 break;
1979 case KVM_IRQCHIP_IOAPIC:
1980 memcpy(&chip->chip.ioapic,
1981 ioapic_irqchip(kvm),
1982 sizeof(struct kvm_ioapic_state));
1983 break;
1984 default:
1985 r = -EINVAL;
1986 break;
1987 }
1988 return r;
1989}
1990
1991static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1992{
1993 int r;
1994
1995 r = 0;
1996 switch (chip->chip_id) {
1997 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 1998 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 1999 memcpy(&pic_irqchip(kvm)->pics[0],
2000 &chip->chip.pic,
2001 sizeof(struct kvm_pic_state));
894a9c55 2002 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2003 break;
2004 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2005 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2006 memcpy(&pic_irqchip(kvm)->pics[1],
2007 &chip->chip.pic,
2008 sizeof(struct kvm_pic_state));
894a9c55 2009 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2010 break;
2011 case KVM_IRQCHIP_IOAPIC:
894a9c55 2012 mutex_lock(&kvm->irq_lock);
1fe779f8
CO		 2013 memcpy(ioapic_irqchip(kvm),
2014 &chip->chip.ioapic,
2015 sizeof(struct kvm_ioapic_state));
894a9c55 2016 mutex_unlock(&kvm->irq_lock);
1fe779f8
CO		 2017 break;
2018 default:
2019 r = -EINVAL;
2020 break;
2021 }
2022 kvm_pic_update_irq(pic_irqchip(kvm));
2023 return r;
2024}
2025
e0f63cb9
SY		 2026static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2027{
2028 int r = 0;
2029
894a9c55 2030 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2031 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2032 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2033 return r;
2034}
2035
2036static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2037{
2038 int r = 0;
2039
894a9c55 2040 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2041 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2042 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
894a9c55 2043 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2044 return r;
2045}
2046
52d939a0
MT		 2047static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2048 struct kvm_reinject_control *control)
2049{
2050 if (!kvm->arch.vpit)
2051 return -ENXIO;
894a9c55 2052 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2053 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2054 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2055 return 0;
2056}
2057
5bb064dc
ZX		 2058/*
2059 * Get (and clear) the dirty memory log for a memory slot.
2060 */
2061int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2062 struct kvm_dirty_log *log)
2063{
2064 int r;
2065 int n;
2066 struct kvm_memory_slot *memslot;
2067 int is_dirty = 0;
2068
72dc67a6 2069 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2070
2071 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2072 if (r)
2073 goto out;
2074
2075 /* If nothing is dirty, don't bother messing with page tables. */
2076 if (is_dirty) {
7c8a83b7 2077 spin_lock(&kvm->mmu_lock);
5bb064dc 2078 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2079 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2080 kvm_flush_remote_tlbs(kvm);
2081 memslot = &kvm->memslots[log->slot];
2082 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2083 memset(memslot->dirty_bitmap, 0, n);
2084 }
2085 r = 0;
2086out:
72dc67a6 2087 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2088 return r;
2089}
2090
1fe779f8
CO		 2091long kvm_arch_vm_ioctl(struct file *filp,
2092 unsigned int ioctl, unsigned long arg)
2093{
2094 struct kvm *kvm = filp->private_data;
2095 void __user *argp = (void __user *)arg;
2096 int r = -EINVAL;
f0d66275
DH		 2097 /*
2098 * This union makes it completely explicit to gcc-3.x
2099 * that these two variables' stack usage should be
2100 * combined, not added together.
2101 */
2102 union {
2103 struct kvm_pit_state ps;
2104 struct kvm_memory_alias alias;
c5ff41ce 2105 struct kvm_pit_config pit_config;
f0d66275 2106 } u;
1fe779f8
CO		 2107
2108 switch (ioctl) {
2109 case KVM_SET_TSS_ADDR:
2110 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2111 if (r < 0)
2112 goto out;
2113 break;
2114 case KVM_SET_MEMORY_REGION: {
2115 struct kvm_memory_region kvm_mem;
2116 struct kvm_userspace_memory_region kvm_userspace_mem;
2117
2118 r = -EFAULT;
2119 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2120 goto out;
2121 kvm_userspace_mem.slot = kvm_mem.slot;
2122 kvm_userspace_mem.flags = kvm_mem.flags;
2123 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2124 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2125 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2126 if (r)
2127 goto out;
2128 break;
2129 }
2130 case KVM_SET_NR_MMU_PAGES:
2131 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2132 if (r)
2133 goto out;
2134 break;
2135 case KVM_GET_NR_MMU_PAGES:
2136 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2137 break;
f0d66275 2138 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2139 r = -EFAULT;
f0d66275 2140 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2141 goto out;
f0d66275 2142 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2143 if (r)
2144 goto out;
2145 break;
1fe779f8
CO		 2146 case KVM_CREATE_IRQCHIP:
2147 r = -ENOMEM;
d7deeeb0
ZX		 2148 kvm->arch.vpic = kvm_create_pic(kvm);
2149 if (kvm->arch.vpic) {
1fe779f8
CO		 2150 r = kvm_ioapic_init(kvm);
2151 if (r) {
d7deeeb0
ZX		 2152 kfree(kvm->arch.vpic);
2153 kvm->arch.vpic = NULL;
1fe779f8
CO		 2154 goto out;
2155 }
2156 } else
2157 goto out;
399ec807
AK		 2158 r = kvm_setup_default_irq_routing(kvm);
2159 if (r) {
2160 kfree(kvm->arch.vpic);
2161 kfree(kvm->arch.vioapic);
2162 goto out;
2163 }
1fe779f8 2164 break;
7837699f 2165 case KVM_CREATE_PIT:
c5ff41ce
JK		 2166 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2167 goto create_pit;
2168 case KVM_CREATE_PIT2:
2169 r = -EFAULT;
2170 if (copy_from_user(&u.pit_config, argp,
2171 sizeof(struct kvm_pit_config)))
2172 goto out;
2173 create_pit:
269e05e4
AK		 2174 mutex_lock(&kvm->lock);
2175 r = -EEXIST;
2176 if (kvm->arch.vpit)
2177 goto create_pit_unlock;
7837699f 2178 r = -ENOMEM;
c5ff41ce 2179 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2180 if (kvm->arch.vpit)
2181 r = 0;
269e05e4
AK		 2182 create_pit_unlock:
2183 mutex_unlock(&kvm->lock);
7837699f 2184 break;
4925663a 2185 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2186 case KVM_IRQ_LINE: {
2187 struct kvm_irq_level irq_event;
2188
2189 r = -EFAULT;
2190 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2191 goto out;
2192 if (irqchip_in_kernel(kvm)) {
4925663a 2193 __s32 status;
fa40a821 2194 mutex_lock(&kvm->irq_lock);
4925663a
GN		 2195 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2196 irq_event.irq, irq_event.level);
fa40a821 2197 mutex_unlock(&kvm->irq_lock);
4925663a
GN		 2198 if (ioctl == KVM_IRQ_LINE_STATUS) {
2199 irq_event.status = status;
2200 if (copy_to_user(argp, &irq_event,
2201 sizeof irq_event))
2202 goto out;
2203 }
1fe779f8
CO		 2204 r = 0;
2205 }
2206 break;
2207 }
2208 case KVM_GET_IRQCHIP: {
2209 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2210 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2211
f0d66275
DH		 2212 r = -ENOMEM;
2213 if (!chip)
1fe779f8 2214 goto out;
f0d66275
DH		 2215 r = -EFAULT;
2216 if (copy_from_user(chip, argp, sizeof *chip))
2217 goto get_irqchip_out;
1fe779f8
CO		 2218 r = -ENXIO;
2219 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2220 goto get_irqchip_out;
2221 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2222 if (r)
f0d66275 2223 goto get_irqchip_out;
1fe779f8 2224 r = -EFAULT;
f0d66275
DH		 2225 if (copy_to_user(argp, chip, sizeof *chip))
2226 goto get_irqchip_out;
1fe779f8 2227 r = 0;
f0d66275
DH		 2228 get_irqchip_out:
2229 kfree(chip);
2230 if (r)
2231 goto out;
1fe779f8
CO		 2232 break;
2233 }
2234 case KVM_SET_IRQCHIP: {
2235 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2236 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2237
f0d66275
DH		 2238 r = -ENOMEM;
2239 if (!chip)
1fe779f8 2240 goto out;
f0d66275
DH		 2241 r = -EFAULT;
2242 if (copy_from_user(chip, argp, sizeof *chip))
2243 goto set_irqchip_out;
1fe779f8
CO		 2244 r = -ENXIO;
2245 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2246 goto set_irqchip_out;
2247 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2248 if (r)
f0d66275 2249 goto set_irqchip_out;
1fe779f8 2250 r = 0;
f0d66275
DH		 2251 set_irqchip_out:
2252 kfree(chip);
2253 if (r)
2254 goto out;
1fe779f8
CO		 2255 break;
2256 }
e0f63cb9 2257 case KVM_GET_PIT: {
e0f63cb9 2258 r = -EFAULT;
f0d66275 2259 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2260 goto out;
2261 r = -ENXIO;
2262 if (!kvm->arch.vpit)
2263 goto out;
f0d66275 2264 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2265 if (r)
2266 goto out;
2267 r = -EFAULT;
f0d66275 2268 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2269 goto out;
2270 r = 0;
2271 break;
2272 }
2273 case KVM_SET_PIT: {
e0f63cb9 2274 r = -EFAULT;
f0d66275 2275 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2276 goto out;
2277 r = -ENXIO;
2278 if (!kvm->arch.vpit)
2279 goto out;
f0d66275 2280 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2281 if (r)
2282 goto out;
2283 r = 0;
2284 break;
2285 }
52d939a0
MT		 2286 case KVM_REINJECT_CONTROL: {
2287 struct kvm_reinject_control control;
2288 r = -EFAULT;
2289 if (copy_from_user(&control, argp, sizeof(control)))
2290 goto out;
2291 r = kvm_vm_ioctl_reinject(kvm, &control);
2292 if (r)
2293 goto out;
2294 r = 0;
2295 break;
2296 }
1fe779f8
CO		 2297 default:
2298 ;
2299 }
2300out:
2301 return r;
2302}
2303
a16b043c 2304static void kvm_init_msr_list(void)
043405e1
CO		 2305{
2306 u32 dummy[2];
2307 unsigned i, j;
2308
2309 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2310 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2311 continue;
2312 if (j < i)
2313 msrs_to_save[j] = msrs_to_save[i];
2314 j++;
2315 }
2316 num_msrs_to_save = j;
2317}
2318
bbd9b64e
CO		 2319/*
2320 * Only apic need an MMIO device hook, so shortcut now..
2321 */
2322static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2323 gpa_t addr, int len,
2324 int is_write)
bbd9b64e
CO		 2325{
2326 struct kvm_io_device *dev;
2327
ad312c7c
ZX		 2328 if (vcpu->arch.apic) {
2329 dev = &vcpu->arch.apic->dev;
d76685c4 2330 if (kvm_iodevice_in_range(dev, addr, len, is_write))
bbd9b64e
CO		 2331 return dev;
2332 }
2333 return NULL;
2334}
2335
2336
2337static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2338 gpa_t addr, int len,
2339 int is_write)
bbd9b64e
CO		 2340{
2341 struct kvm_io_device *dev;
2342
92760499 2343 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 2344 if (dev == NULL)
92760499
LV		 2345 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
2346 is_write);
bbd9b64e
CO		 2347 return dev;
2348}
2349
cded19f3
HE		 2350static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2351 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2352{
2353 void *data = val;
10589a46 2354 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2355
2356 while (bytes) {
ad312c7c 2357 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2358 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2359 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2360 int ret;
2361
10589a46
MT		 2362 if (gpa == UNMAPPED_GVA) {
2363 r = X86EMUL_PROPAGATE_FAULT;
2364 goto out;
2365 }
77c2002e 2366 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2367 if (ret < 0) {
2368 r = X86EMUL_UNHANDLEABLE;
2369 goto out;
2370 }
bbd9b64e 2371
77c2002e
IE		 2372 bytes -= toread;
2373 data += toread;
2374 addr += toread;
bbd9b64e 2375 }
10589a46 2376out:
10589a46 2377 return r;
bbd9b64e 2378}
77c2002e 2379
cded19f3
HE		 2380static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2381 struct kvm_vcpu *vcpu)
77c2002e
IE		 2382{
2383 void *data = val;
2384 int r = X86EMUL_CONTINUE;
2385
2386 while (bytes) {
2387 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2388 unsigned offset = addr & (PAGE_SIZE-1);
2389 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2390 int ret;
2391
2392 if (gpa == UNMAPPED_GVA) {
2393 r = X86EMUL_PROPAGATE_FAULT;
2394 goto out;
2395 }
2396 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2397 if (ret < 0) {
2398 r = X86EMUL_UNHANDLEABLE;
2399 goto out;
2400 }
2401
2402 bytes -= towrite;
2403 data += towrite;
2404 addr += towrite;
2405 }
2406out:
2407 return r;
2408}
2409
bbd9b64e 2410
bbd9b64e
CO		 2411static int emulator_read_emulated(unsigned long addr,
2412 void *val,
2413 unsigned int bytes,
2414 struct kvm_vcpu *vcpu)
2415{
2416 struct kvm_io_device *mmio_dev;
2417 gpa_t gpa;
2418
2419 if (vcpu->mmio_read_completed) {
2420 memcpy(val, vcpu->mmio_data, bytes);
2421 vcpu->mmio_read_completed = 0;
2422 return X86EMUL_CONTINUE;
2423 }
2424
ad312c7c 2425 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2426
2427 /* For APIC access vmexit */
2428 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2429 goto mmio;
2430
77c2002e
IE		 2431 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2432 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2433 return X86EMUL_CONTINUE;
2434 if (gpa == UNMAPPED_GVA)
2435 return X86EMUL_PROPAGATE_FAULT;
2436
2437mmio:
2438 /*
2439 * Is this MMIO handled locally?
2440 */
10589a46 2441 mutex_lock(&vcpu->kvm->lock);
92760499 2442 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
fa40a821 2443 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2444 if (mmio_dev) {
2445 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
2446 return X86EMUL_CONTINUE;
2447 }
2448
2449 vcpu->mmio_needed = 1;
2450 vcpu->mmio_phys_addr = gpa;
2451 vcpu->mmio_size = bytes;
2452 vcpu->mmio_is_write = 0;
2453
2454 return X86EMUL_UNHANDLEABLE;
2455}
2456
3200f405 2457int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2458 const void *val, int bytes)
bbd9b64e
CO		 2459{
2460 int ret;
2461
2462 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2463 if (ret < 0)
bbd9b64e 2464 return 0;
ad218f85 2465 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2466 return 1;
2467}
2468
2469static int emulator_write_emulated_onepage(unsigned long addr,
2470 const void *val,
2471 unsigned int bytes,
2472 struct kvm_vcpu *vcpu)
2473{
2474 struct kvm_io_device *mmio_dev;
10589a46
MT		 2475 gpa_t gpa;
2476
10589a46 2477 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2478
2479 if (gpa == UNMAPPED_GVA) {
c3c91fee 2480 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2481 return X86EMUL_PROPAGATE_FAULT;
2482 }
2483
2484 /* For APIC access vmexit */
2485 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2486 goto mmio;
2487
2488 if (emulator_write_phys(vcpu, gpa, val, bytes))
2489 return X86EMUL_CONTINUE;
2490
2491mmio:
2492 /*
2493 * Is this MMIO handled locally?
2494 */
10589a46 2495 mutex_lock(&vcpu->kvm->lock);
92760499 2496 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
fa40a821 2497 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2498 if (mmio_dev) {
2499 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
2500 return X86EMUL_CONTINUE;
2501 }
2502
2503 vcpu->mmio_needed = 1;
2504 vcpu->mmio_phys_addr = gpa;
2505 vcpu->mmio_size = bytes;
2506 vcpu->mmio_is_write = 1;
2507 memcpy(vcpu->mmio_data, val, bytes);
2508
2509 return X86EMUL_CONTINUE;
2510}
2511
2512int emulator_write_emulated(unsigned long addr,
2513 const void *val,
2514 unsigned int bytes,
2515 struct kvm_vcpu *vcpu)
2516{
2517 /* Crossing a page boundary? */
2518 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2519 int rc, now;
2520
2521 now = -addr & ~PAGE_MASK;
2522 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2523 if (rc != X86EMUL_CONTINUE)
2524 return rc;
2525 addr += now;
2526 val += now;
2527 bytes -= now;
2528 }
2529 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2530}
2531EXPORT_SYMBOL_GPL(emulator_write_emulated);
2532
2533static int emulator_cmpxchg_emulated(unsigned long addr,
2534 const void *old,
2535 const void *new,
2536 unsigned int bytes,
2537 struct kvm_vcpu *vcpu)
2538{
2539 static int reported;
2540
2541 if (!reported) {
2542 reported = 1;
2543 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2544 }
2bacc55c
MT		 2545#ifndef CONFIG_X86_64
2546 /* guests cmpxchg8b have to be emulated atomically */
2547 if (bytes == 8) {
10589a46 2548 gpa_t gpa;
2bacc55c 2549 struct page *page;
c0b49b0d 2550 char *kaddr;
2bacc55c
MT		 2551 u64 val;
2552
10589a46
MT		 2553 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2554
2bacc55c
MT		 2555 if (gpa == UNMAPPED_GVA ||
2556 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2557 goto emul_write;
2558
2559 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2560 goto emul_write;
2561
2562 val = *(u64 *)new;
72dc67a6 2563
2bacc55c 2564 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2565
c0b49b0d
AM		 2566 kaddr = kmap_atomic(page, KM_USER0);
2567 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2568 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2569 kvm_release_page_dirty(page);
2570 }
3200f405 2571emul_write:
2bacc55c
MT		 2572#endif
2573
bbd9b64e
CO		 2574 return emulator_write_emulated(addr, new, bytes, vcpu);
2575}
2576
2577static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2578{
2579 return kvm_x86_ops->get_segment_base(vcpu, seg);
2580}
2581
2582int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2583{
a7052897 2584 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2585 return X86EMUL_CONTINUE;
2586}
2587
2588int emulate_clts(struct kvm_vcpu *vcpu)
2589{
ad312c7c 2590 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2591 return X86EMUL_CONTINUE;
2592}
2593
2594int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2595{
2596 struct kvm_vcpu *vcpu = ctxt->vcpu;
2597
2598 switch (dr) {
2599 case 0 ... 3:
2600 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2601 return X86EMUL_CONTINUE;
2602 default:
b8688d51 2603 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2604 return X86EMUL_UNHANDLEABLE;
2605 }
2606}
2607
2608int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2609{
2610 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2611 int exception;
2612
2613 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2614 if (exception) {
2615 /* FIXME: better handling */
2616 return X86EMUL_UNHANDLEABLE;
2617 }
2618 return X86EMUL_CONTINUE;
2619}
2620
2621void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2622{
bbd9b64e 2623 u8 opcodes[4];
5fdbf976 2624 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2625 unsigned long rip_linear;
2626
f76c710d 2627 if (!printk_ratelimit())
bbd9b64e
CO		 2628 return;
2629
25be4608
GC		 2630 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2631
77c2002e 2632 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2633
2634 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2635 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2636}
2637EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2638
14af3f3c 2639static struct x86_emulate_ops emulate_ops = {
77c2002e 2640 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2641 .read_emulated = emulator_read_emulated,
2642 .write_emulated = emulator_write_emulated,
2643 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2644};
2645
5fdbf976
MT		 2646static void cache_all_regs(struct kvm_vcpu *vcpu)
2647{
2648 kvm_register_read(vcpu, VCPU_REGS_RAX);
2649 kvm_register_read(vcpu, VCPU_REGS_RSP);
2650 kvm_register_read(vcpu, VCPU_REGS_RIP);
2651 vcpu->arch.regs_dirty = ~0;
2652}
2653
bbd9b64e
CO		 2654int emulate_instruction(struct kvm_vcpu *vcpu,
2655 struct kvm_run *run,
2656 unsigned long cr2,
2657 u16 error_code,
571008da 2658 int emulation_type)
bbd9b64e 2659{
310b5d30 2660 int r, shadow_mask;
571008da 2661 struct decode_cache *c;
bbd9b64e 2662
26eef70c 2663 kvm_clear_exception_queue(vcpu);
ad312c7c 2664 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2665 /*
2666 * TODO: fix x86_emulate.c to use guest_read/write_register
2667 * instead of direct ->regs accesses, can save hundred cycles
2668 * on Intel for instructions that don't read/change RSP, for
2669 * for example.
2670 */
2671 cache_all_regs(vcpu);
bbd9b64e
CO		 2672
2673 vcpu->mmio_is_write = 0;
ad312c7c 2674 vcpu->arch.pio.string = 0;
bbd9b64e 2675
571008da 2676 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2677 int cs_db, cs_l;
2678 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2679
ad312c7c
ZX		 2680 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2681 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2682 vcpu->arch.emulate_ctxt.mode =
2683 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2684 ? X86EMUL_MODE_REAL : cs_l
2685 ? X86EMUL_MODE_PROT64 : cs_db
2686 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2687
ad312c7c 2688 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 2689
0cb5762e
AP		 2690 /* Only allow emulation of specific instructions on #UD
2691 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 2692 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 2693 if (emulation_type & EMULTYPE_TRAP_UD) {
2694 if (!c->twobyte)
2695 return EMULATE_FAIL;
2696 switch (c->b) {
2697 case 0x01: /* VMMCALL */
2698 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2699 return EMULATE_FAIL;
2700 break;
2701 case 0x34: /* sysenter */
2702 case 0x35: /* sysexit */
2703 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2704 return EMULATE_FAIL;
2705 break;
2706 case 0x05: /* syscall */
2707 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2708 return EMULATE_FAIL;
2709 break;
2710 default:
2711 return EMULATE_FAIL;
2712 }
2713
2714 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2715 return EMULATE_FAIL;
2716 }
571008da 2717
f2b5756b 2718 ++vcpu->stat.insn_emulation;
bbd9b64e 2719 if (r) {
f2b5756b 2720 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2721 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2722 return EMULATE_DONE;
2723 return EMULATE_FAIL;
2724 }
2725 }
2726
ba8afb6b
GN		 2727 if (emulation_type & EMULTYPE_SKIP) {
2728 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2729 return EMULATE_DONE;
2730 }
2731
ad312c7c 2732 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2733 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2734
2735 if (r == 0)
2736 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2737
ad312c7c 2738 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2739 return EMULATE_DO_MMIO;
2740
2741 if ((r || vcpu->mmio_is_write) && run) {
2742 run->exit_reason = KVM_EXIT_MMIO;
2743 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2744 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2745 run->mmio.len = vcpu->mmio_size;
2746 run->mmio.is_write = vcpu->mmio_is_write;
2747 }
2748
2749 if (r) {
2750 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2751 return EMULATE_DONE;
2752 if (!vcpu->mmio_needed) {
2753 kvm_report_emulation_failure(vcpu, "mmio");
2754 return EMULATE_FAIL;
2755 }
2756 return EMULATE_DO_MMIO;
2757 }
2758
ad312c7c 2759 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2760
2761 if (vcpu->mmio_is_write) {
2762 vcpu->mmio_needed = 0;
2763 return EMULATE_DO_MMIO;
2764 }
2765
2766 return EMULATE_DONE;
2767}
2768EXPORT_SYMBOL_GPL(emulate_instruction);
2769
de7d789a
CO		 2770static int pio_copy_data(struct kvm_vcpu *vcpu)
2771{
ad312c7c 2772 void *p = vcpu->arch.pio_data;
0f346074 2773 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2774 unsigned bytes;
0f346074 2775 int ret;
de7d789a 2776
ad312c7c
ZX		 2777 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2778 if (vcpu->arch.pio.in)
0f346074 2779 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2780 else
0f346074
IE		 2781 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2782 return ret;
de7d789a
CO		 2783}
2784
2785int complete_pio(struct kvm_vcpu *vcpu)
2786{
ad312c7c 2787 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2788 long delta;
2789 int r;
5fdbf976 2790 unsigned long val;
de7d789a
CO		 2791
2792 if (!io->string) {
5fdbf976
MT		 2793 if (io->in) {
2794 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2795 memcpy(&val, vcpu->arch.pio_data, io->size);
2796 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2797 }
de7d789a
CO		 2798 } else {
2799 if (io->in) {
2800 r = pio_copy_data(vcpu);
5fdbf976 2801 if (r)
de7d789a 2802 return r;
de7d789a
CO		 2803 }
2804
2805 delta = 1;
2806 if (io->rep) {
2807 delta *= io->cur_count;
2808 /*
2809 * The size of the register should really depend on
2810 * current address size.
2811 */
5fdbf976
MT		 2812 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2813 val -= delta;
2814 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2815 }
2816 if (io->down)
2817 delta = -delta;
2818 delta *= io->size;
5fdbf976
MT		 2819 if (io->in) {
2820 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2821 val += delta;
2822 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2823 } else {
2824 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2825 val += delta;
2826 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2827 }
de7d789a
CO		 2828 }
2829
de7d789a
CO		 2830 io->count -= io->cur_count;
2831 io->cur_count = 0;
2832
2833 return 0;
2834}
2835
2836static void kernel_pio(struct kvm_io_device *pio_dev,
2837 struct kvm_vcpu *vcpu,
2838 void *pd)
2839{
2840 /* TODO: String I/O for in kernel device */
2841
ad312c7c
ZX		 2842 if (vcpu->arch.pio.in)
2843 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2844 vcpu->arch.pio.size,
de7d789a
CO		 2845 pd);
2846 else
ad312c7c
ZX		 2847 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2848 vcpu->arch.pio.size,
de7d789a 2849 pd);
de7d789a
CO		 2850}
2851
2852static void pio_string_write(struct kvm_io_device *pio_dev,
2853 struct kvm_vcpu *vcpu)
2854{
ad312c7c
ZX		 2855 struct kvm_pio_request *io = &vcpu->arch.pio;
2856 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2857 int i;
2858
de7d789a
CO		 2859 for (i = 0; i < io->cur_count; i++) {
2860 kvm_iodevice_write(pio_dev, io->port,
2861 io->size,
2862 pd);
2863 pd += io->size;
2864 }
de7d789a
CO		 2865}
2866
2867static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2868 gpa_t addr, int len,
2869 int is_write)
de7d789a 2870{
92760499 2871 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2872}
2873
2874int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2875 int size, unsigned port)
2876{
2877 struct kvm_io_device *pio_dev;
5fdbf976 2878 unsigned long val;
de7d789a
CO		 2879
2880 vcpu->run->exit_reason = KVM_EXIT_IO;
2881 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2882 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2883 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2884 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2885 vcpu->run->io.port = vcpu->arch.pio.port = port;
2886 vcpu->arch.pio.in = in;
2887 vcpu->arch.pio.string = 0;
2888 vcpu->arch.pio.down = 0;
ad312c7c 2889 vcpu->arch.pio.rep = 0;
de7d789a 2890
229456fc
MT		 2891 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2892 size, 1);
2714d1d3 2893
5fdbf976
MT		 2894 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2895 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2896
fa40a821 2897 mutex_lock(&vcpu->kvm->lock);
92760499 2898 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
fa40a821 2899 mutex_unlock(&vcpu->kvm->lock);
de7d789a 2900 if (pio_dev) {
ad312c7c 2901 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2902 complete_pio(vcpu);
2903 return 1;
2904 }
2905 return 0;
2906}
2907EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2908
2909int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2910 int size, unsigned long count, int down,
2911 gva_t address, int rep, unsigned port)
2912{
2913 unsigned now, in_page;
0f346074 2914 int ret = 0;
de7d789a
CO		 2915 struct kvm_io_device *pio_dev;
2916
2917 vcpu->run->exit_reason = KVM_EXIT_IO;
2918 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2919 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2920 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2921 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2922 vcpu->run->io.port = vcpu->arch.pio.port = port;
2923 vcpu->arch.pio.in = in;
2924 vcpu->arch.pio.string = 1;
2925 vcpu->arch.pio.down = down;
ad312c7c 2926 vcpu->arch.pio.rep = rep;
de7d789a 2927
229456fc
MT		 2928 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2929 size, count);
2714d1d3 2930
de7d789a
CO		 2931 if (!count) {
2932 kvm_x86_ops->skip_emulated_instruction(vcpu);
2933 return 1;
2934 }
2935
2936 if (!down)
2937 in_page = PAGE_SIZE - offset_in_page(address);
2938 else
2939 in_page = offset_in_page(address) + size;
2940 now = min(count, (unsigned long)in_page / size);
0f346074 2941 if (!now)
de7d789a 2942 now = 1;
de7d789a
CO		 2943 if (down) {
2944 /*
2945 * String I/O in reverse. Yuck. Kill the guest, fix later.
2946 */
2947 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2948 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2949 return 1;
2950 }
2951 vcpu->run->io.count = now;
ad312c7c 2952 vcpu->arch.pio.cur_count = now;
de7d789a 2953
ad312c7c 2954 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2955 kvm_x86_ops->skip_emulated_instruction(vcpu);
2956
0f346074 2957 vcpu->arch.pio.guest_gva = address;
de7d789a 2958
fa40a821 2959 mutex_lock(&vcpu->kvm->lock);
92760499
LV		 2960 pio_dev = vcpu_find_pio_dev(vcpu, port,
2961 vcpu->arch.pio.cur_count,
2962 !vcpu->arch.pio.in);
fa40a821
MT		 2963 mutex_unlock(&vcpu->kvm->lock);
2964
ad312c7c 2965 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2966 /* string PIO write */
2967 ret = pio_copy_data(vcpu);
0f346074
IE		 2968 if (ret == X86EMUL_PROPAGATE_FAULT) {
2969 kvm_inject_gp(vcpu, 0);
2970 return 1;
2971 }
2972 if (ret == 0 && pio_dev) {
de7d789a
CO		 2973 pio_string_write(pio_dev, vcpu);
2974 complete_pio(vcpu);
ad312c7c 2975 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2976 ret = 1;
2977 }
2978 } else if (pio_dev)
2979 pr_unimpl(vcpu, "no string pio read support yet, "
2980 "port %x size %d count %ld\n",
2981 port, size, count);
2982
2983 return ret;
2984}
2985EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2986
c8076604
GH		 2987static void bounce_off(void *info)
2988{
2989 /* nothing */
2990}
2991
2992static unsigned int ref_freq;
2993static unsigned long tsc_khz_ref;
2994
2995static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
2996 void *data)
2997{
2998 struct cpufreq_freqs *freq = data;
2999 struct kvm *kvm;
3000 struct kvm_vcpu *vcpu;
3001 int i, send_ipi = 0;
3002
3003 if (!ref_freq)
3004 ref_freq = freq->old;
3005
3006 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3007 return 0;
3008 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3009 return 0;
3010 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
3011
3012 spin_lock(&kvm_lock);
3013 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3014 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3015 if (vcpu->cpu != freq->cpu)
3016 continue;
3017 if (!kvm_request_guest_time_update(vcpu))
3018 continue;
3019 if (vcpu->cpu != smp_processor_id())
3020 send_ipi++;
3021 }
3022 }
3023 spin_unlock(&kvm_lock);
3024
3025 if (freq->old < freq->new && send_ipi) {
3026 /*
3027 * We upscale the frequency. Must make the guest
3028 * doesn't see old kvmclock values while running with
3029 * the new frequency, otherwise we risk the guest sees
3030 * time go backwards.
3031 *
3032 * In case we update the frequency for another cpu
3033 * (which might be in guest context) send an interrupt
3034 * to kick the cpu out of guest context. Next time
3035 * guest context is entered kvmclock will be updated,
3036 * so the guest will not see stale values.
3037 */
3038 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3039 }
3040 return 0;
3041}
3042
3043static struct notifier_block kvmclock_cpufreq_notifier_block = {
3044 .notifier_call = kvmclock_cpufreq_notifier
3045};
3046
f8c16bba 3047int kvm_arch_init(void *opaque)
043405e1 3048{
c8076604 3049 int r, cpu;
f8c16bba
ZX		 3050 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3051
f8c16bba
ZX		 3052 if (kvm_x86_ops) {
3053 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3054 r = -EEXIST;
3055 goto out;
f8c16bba
ZX		 3056 }
3057
3058 if (!ops->cpu_has_kvm_support()) {
3059 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3060 r = -EOPNOTSUPP;
3061 goto out;
f8c16bba
ZX		 3062 }
3063 if (ops->disabled_by_bios()) {
3064 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3065 r = -EOPNOTSUPP;
3066 goto out;
f8c16bba
ZX		 3067 }
3068
97db56ce
AK		 3069 r = kvm_mmu_module_init();
3070 if (r)
3071 goto out;
3072
3073 kvm_init_msr_list();
3074
f8c16bba 3075 kvm_x86_ops = ops;
56c6d28a 3076 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3077 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3078 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3079 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604
GH		 3080
3081 for_each_possible_cpu(cpu)
3082 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3083 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3084 tsc_khz_ref = tsc_khz;
3085 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3086 CPUFREQ_TRANSITION_NOTIFIER);
3087 }
3088
f8c16bba 3089 return 0;
56c6d28a
ZX		 3090
3091out:
56c6d28a 3092 return r;
043405e1 3093}
8776e519 3094
f8c16bba
ZX		 3095void kvm_arch_exit(void)
3096{
888d256e
JK		 3097 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3098 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3099 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3100 kvm_x86_ops = NULL;
56c6d28a
ZX		 3101 kvm_mmu_module_exit();
3102}
f8c16bba 3103
8776e519
HB		 3104int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3105{
3106 ++vcpu->stat.halt_exits;
3107 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3108 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3109 return 1;
3110 } else {
3111 vcpu->run->exit_reason = KVM_EXIT_HLT;
3112 return 0;
3113 }
3114}
3115EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3116
2f333bcb
MT		 3117static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3118 unsigned long a1)
3119{
3120 if (is_long_mode(vcpu))
3121 return a0;
3122 else
3123 return a0 | ((gpa_t)a1 << 32);
3124}
3125
8776e519
HB		 3126int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3127{
3128 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3129 int r = 1;
8776e519 3130
5fdbf976
MT		 3131 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3132 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3133 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3134 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3135 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3136
229456fc 3137 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3138
8776e519
HB		 3139 if (!is_long_mode(vcpu)) {
3140 nr &= 0xFFFFFFFF;
3141 a0 &= 0xFFFFFFFF;
3142 a1 &= 0xFFFFFFFF;
3143 a2 &= 0xFFFFFFFF;
3144 a3 &= 0xFFFFFFFF;
3145 }
3146
3147 switch (nr) {
b93463aa
AK		 3148 case KVM_HC_VAPIC_POLL_IRQ:
3149 ret = 0;
3150 break;
2f333bcb
MT		 3151 case KVM_HC_MMU_OP:
3152 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3153 break;
8776e519
HB		 3154 default:
3155 ret = -KVM_ENOSYS;
3156 break;
3157 }
5fdbf976 3158 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3159 ++vcpu->stat.hypercalls;
2f333bcb 3160 return r;
8776e519
HB		 3161}
3162EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3163
3164int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3165{
3166 char instruction[3];
3167 int ret = 0;
5fdbf976 3168 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3169
8776e519
HB		 3170
3171 /*
3172 * Blow out the MMU to ensure that no other VCPU has an active mapping
3173 * to ensure that the updated hypercall appears atomically across all
3174 * VCPUs.
3175 */
3176 kvm_mmu_zap_all(vcpu->kvm);
3177
8776e519 3178 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3179 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3180 != X86EMUL_CONTINUE)
3181 ret = -EFAULT;
3182
8776e519
HB		 3183 return ret;
3184}
3185
3186static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3187{
3188 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3189}
3190
3191void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3192{
3193 struct descriptor_table dt = { limit, base };
3194
3195 kvm_x86_ops->set_gdt(vcpu, &dt);
3196}
3197
3198void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3199{
3200 struct descriptor_table dt = { limit, base };
3201
3202 kvm_x86_ops->set_idt(vcpu, &dt);
3203}
3204
3205void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3206 unsigned long *rflags)
3207{
2d3ad1f4 3208 kvm_lmsw(vcpu, msw);
8776e519
HB		 3209 *rflags = kvm_x86_ops->get_rflags(vcpu);
3210}
3211
3212unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3213{
54e445ca
JR		 3214 unsigned long value;
3215
8776e519
HB		 3216 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3217 switch (cr) {
3218 case 0:
54e445ca
JR		 3219 value = vcpu->arch.cr0;
3220 break;
8776e519 3221 case 2:
54e445ca
JR		 3222 value = vcpu->arch.cr2;
3223 break;
8776e519 3224 case 3:
54e445ca
JR		 3225 value = vcpu->arch.cr3;
3226 break;
8776e519 3227 case 4:
54e445ca
JR		 3228 value = vcpu->arch.cr4;
3229 break;
152ff9be 3230 case 8:
54e445ca
JR		 3231 value = kvm_get_cr8(vcpu);
3232 break;
8776e519 3233 default:
b8688d51 3234 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3235 return 0;
3236 }
54e445ca
JR		 3237
3238 return value;
8776e519
HB		 3239}
3240
3241void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3242 unsigned long *rflags)
3243{
3244 switch (cr) {
3245 case 0:
2d3ad1f4 3246 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 3247 *rflags = kvm_x86_ops->get_rflags(vcpu);
3248 break;
3249 case 2:
ad312c7c 3250 vcpu->arch.cr2 = val;
8776e519
HB		 3251 break;
3252 case 3:
2d3ad1f4 3253 kvm_set_cr3(vcpu, val);
8776e519
HB		 3254 break;
3255 case 4:
2d3ad1f4 3256 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3257 break;
152ff9be 3258 case 8:
2d3ad1f4 3259 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3260 break;
8776e519 3261 default:
b8688d51 3262 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3263 }
3264}
3265
07716717
DK		 3266static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3267{
ad312c7c
ZX		 3268 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3269 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3270
3271 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3272 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3273 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3274 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3275 if (ej->function == e->function) {
3276 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3277 return j;
3278 }
3279 }
3280 return 0; /* silence gcc, even though control never reaches here */
3281}
3282
3283/* find an entry with matching function, matching index (if needed), and that
3284 * should be read next (if it's stateful) */
3285static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3286 u32 function, u32 index)
3287{
3288 if (e->function != function)
3289 return 0;
3290 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3291 return 0;
3292 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3293 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3294 return 0;
3295 return 1;
3296}
3297
d8017474
AG		 3298struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3299 u32 function, u32 index)
8776e519
HB		 3300{
3301 int i;
d8017474 3302 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3303
ad312c7c 3304 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3305 struct kvm_cpuid_entry2 *e;
3306
ad312c7c 3307 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3308 if (is_matching_cpuid_entry(e, function, index)) {
3309 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3310 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3311 best = e;
3312 break;
3313 }
3314 /*
3315 * Both basic or both extended?
3316 */
3317 if (((e->function ^ function) & 0x80000000) == 0)
3318 if (!best || e->function > best->function)
3319 best = e;
3320 }
d8017474
AG		 3321 return best;
3322}
3323
82725b20
DE		 3324int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3325{
3326 struct kvm_cpuid_entry2 *best;
3327
3328 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3329 if (best)
3330 return best->eax & 0xff;
3331 return 36;
3332}
3333
d8017474
AG		 3334void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3335{
3336 u32 function, index;
3337 struct kvm_cpuid_entry2 *best;
3338
3339 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3340 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3341 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3342 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3343 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3344 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3345 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3346 if (best) {
5fdbf976
MT		 3347 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3348 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3349 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3350 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3351 }
8776e519 3352 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3353 trace_kvm_cpuid(function,
3354 kvm_register_read(vcpu, VCPU_REGS_RAX),
3355 kvm_register_read(vcpu, VCPU_REGS_RBX),
3356 kvm_register_read(vcpu, VCPU_REGS_RCX),
3357 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3358}
3359EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3360
b6c7a5dc
HB		 3361/*
3362 * Check if userspace requested an interrupt window, and that the
3363 * interrupt window is open.
3364 *
3365 * No need to exit to userspace if we already have an interrupt queued.
3366 */
3367static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3368 struct kvm_run *kvm_run)
3369{
8061823a 3370 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
b6c7a5dc 3371 kvm_run->request_interrupt_window &&
5df56646 3372 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3373}
3374
3375static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3376 struct kvm_run *kvm_run)
3377{
3378 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3379 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3380 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3381 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3382 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3383 else
b6c7a5dc 3384 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3385 kvm_arch_interrupt_allowed(vcpu) &&
3386 !kvm_cpu_has_interrupt(vcpu) &&
3387 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3388}
3389
b93463aa
AK		 3390static void vapic_enter(struct kvm_vcpu *vcpu)
3391{
3392 struct kvm_lapic *apic = vcpu->arch.apic;
3393 struct page *page;
3394
3395 if (!apic || !apic->vapic_addr)
3396 return;
3397
3398 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3399
3400 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3401}
3402
3403static void vapic_exit(struct kvm_vcpu *vcpu)
3404{
3405 struct kvm_lapic *apic = vcpu->arch.apic;
3406
3407 if (!apic || !apic->vapic_addr)
3408 return;
3409
f8b78fa3 3410 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3411 kvm_release_page_dirty(apic->vapic_page);
3412 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3413 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3414}
3415
95ba8273
GN		 3416static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3417{
3418 int max_irr, tpr;
3419
3420 if (!kvm_x86_ops->update_cr8_intercept)
3421 return;
3422
8db3baa2
GN		 3423 if (!vcpu->arch.apic->vapic_addr)
3424 max_irr = kvm_lapic_find_highest_irr(vcpu);
3425 else
3426 max_irr = -1;
95ba8273
GN		 3427
3428 if (max_irr != -1)
3429 max_irr >>= 4;
3430
3431 tpr = kvm_lapic_get_cr8(vcpu);
3432
3433 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3434}
3435
6a8b1d13 3436static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
95ba8273
GN		 3437{
3438 /* try to reinject previous events if any */
3439 if (vcpu->arch.nmi_injected) {
3440 kvm_x86_ops->set_nmi(vcpu);
3441 return;
3442 }
3443
3444 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3445 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3446 return;
3447 }
3448
3449 /* try to inject new event if pending */
3450 if (vcpu->arch.nmi_pending) {
3451 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3452 vcpu->arch.nmi_pending = false;
3453 vcpu->arch.nmi_injected = true;
3454 kvm_x86_ops->set_nmi(vcpu);
3455 }
3456 } else if (kvm_cpu_has_interrupt(vcpu)) {
3457 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3458 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3459 false);
3460 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3461 }
3462 }
3463}
3464
d7690175 3465static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3466{
3467 int r;
6a8b1d13
GN		 3468 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3469 kvm_run->request_interrupt_window;
b6c7a5dc 3470
2e53d63a
MT		 3471 if (vcpu->requests)
3472 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3473 kvm_mmu_unload(vcpu);
3474
b6c7a5dc
HB		 3475 r = kvm_mmu_reload(vcpu);
3476 if (unlikely(r))
3477 goto out;
3478
2f52d58c
AK		 3479 if (vcpu->requests) {
3480 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3481 __kvm_migrate_timers(vcpu);
c8076604
GH		 3482 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3483 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3484 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3485 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3486 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3487 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3488 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3489 &vcpu->requests)) {
3490 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3491 r = 0;
3492 goto out;
3493 }
71c4dfaf
JR		 3494 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3495 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3496 r = 0;
3497 goto out;
3498 }
2f52d58c 3499 }
b93463aa 3500
b6c7a5dc
HB		 3501 preempt_disable();
3502
3503 kvm_x86_ops->prepare_guest_switch(vcpu);
3504 kvm_load_guest_fpu(vcpu);
3505
3506 local_irq_disable();
3507
32f88400
MT		 3508 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3509 smp_mb__after_clear_bit();
3510
d7690175 3511 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3512 local_irq_enable();
3513 preempt_enable();
3514 r = 1;
3515 goto out;
3516 }
3517
ad312c7c 3518 if (vcpu->arch.exception.pending)
298101da 3519 __queue_exception(vcpu);
eb9774f0 3520 else
95ba8273 3521 inject_pending_irq(vcpu, kvm_run);
b6c7a5dc 3522
6a8b1d13
GN		 3523 /* enable NMI/IRQ window open exits if needed */
3524 if (vcpu->arch.nmi_pending)
3525 kvm_x86_ops->enable_nmi_window(vcpu);
3526 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3527 kvm_x86_ops->enable_irq_window(vcpu);
3528
95ba8273 3529 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3530 update_cr8_intercept(vcpu);
3531 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3532 }
b93463aa 3533
3200f405
MT		 3534 up_read(&vcpu->kvm->slots_lock);
3535
b6c7a5dc
HB		 3536 kvm_guest_enter();
3537
42dbaa5a
JK		 3538 get_debugreg(vcpu->arch.host_dr6, 6);
3539 get_debugreg(vcpu->arch.host_dr7, 7);
3540 if (unlikely(vcpu->arch.switch_db_regs)) {
3541 get_debugreg(vcpu->arch.host_db[0], 0);
3542 get_debugreg(vcpu->arch.host_db[1], 1);
3543 get_debugreg(vcpu->arch.host_db[2], 2);
3544 get_debugreg(vcpu->arch.host_db[3], 3);
3545
3546 set_debugreg(0, 7);
3547 set_debugreg(vcpu->arch.eff_db[0], 0);
3548 set_debugreg(vcpu->arch.eff_db[1], 1);
3549 set_debugreg(vcpu->arch.eff_db[2], 2);
3550 set_debugreg(vcpu->arch.eff_db[3], 3);
3551 }
b6c7a5dc 3552
229456fc 3553 trace_kvm_entry(vcpu->vcpu_id);
b6c7a5dc
HB		 3554 kvm_x86_ops->run(vcpu, kvm_run);
3555
42dbaa5a
JK		 3556 if (unlikely(vcpu->arch.switch_db_regs)) {
3557 set_debugreg(0, 7);
3558 set_debugreg(vcpu->arch.host_db[0], 0);
3559 set_debugreg(vcpu->arch.host_db[1], 1);
3560 set_debugreg(vcpu->arch.host_db[2], 2);
3561 set_debugreg(vcpu->arch.host_db[3], 3);
3562 }
3563 set_debugreg(vcpu->arch.host_dr6, 6);
3564 set_debugreg(vcpu->arch.host_dr7, 7);
3565
32f88400 3566 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3567 local_irq_enable();
3568
3569 ++vcpu->stat.exits;
3570
3571 /*
3572 * We must have an instruction between local_irq_enable() and
3573 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3574 * the interrupt shadow. The stat.exits increment will do nicely.
3575 * But we need to prevent reordering, hence this barrier():
3576 */
3577 barrier();
3578
3579 kvm_guest_exit();
3580
3581 preempt_enable();
3582
3200f405
MT		 3583 down_read(&vcpu->kvm->slots_lock);
3584
b6c7a5dc
HB		 3585 /*
3586 * Profile KVM exit RIPs:
3587 */
3588 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3589 unsigned long rip = kvm_rip_read(vcpu);
3590 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3591 }
3592
298101da 3593
b93463aa
AK		 3594 kvm_lapic_sync_from_vapic(vcpu);
3595
b6c7a5dc 3596 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3597out:
3598 return r;
3599}
b6c7a5dc 3600
09cec754 3601
d7690175
MT		 3602static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3603{
3604 int r;
3605
3606 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3607 pr_debug("vcpu %d received sipi with vector # %x\n",
3608 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3609 kvm_lapic_reset(vcpu);
5f179287 3610 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3611 if (r)
3612 return r;
3613 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3614 }
3615
d7690175
MT		 3616 down_read(&vcpu->kvm->slots_lock);
3617 vapic_enter(vcpu);
3618
3619 r = 1;
3620 while (r > 0) {
af2152f5 3621 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3622 r = vcpu_enter_guest(vcpu, kvm_run);
3623 else {
3624 up_read(&vcpu->kvm->slots_lock);
3625 kvm_vcpu_block(vcpu);
3626 down_read(&vcpu->kvm->slots_lock);
3627 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3628 {
3629 switch(vcpu->arch.mp_state) {
3630 case KVM_MP_STATE_HALTED:
d7690175 3631 vcpu->arch.mp_state =
09cec754
GN		 3632 KVM_MP_STATE_RUNNABLE;
3633 case KVM_MP_STATE_RUNNABLE:
3634 break;
3635 case KVM_MP_STATE_SIPI_RECEIVED:
3636 default:
3637 r = -EINTR;
3638 break;
3639 }
3640 }
d7690175
MT		 3641 }
3642
09cec754
GN		 3643 if (r <= 0)
3644 break;
3645
3646 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3647 if (kvm_cpu_has_pending_timer(vcpu))
3648 kvm_inject_pending_timer_irqs(vcpu);
3649
3650 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3651 r = -EINTR;
3652 kvm_run->exit_reason = KVM_EXIT_INTR;
3653 ++vcpu->stat.request_irq_exits;
3654 }
3655 if (signal_pending(current)) {
3656 r = -EINTR;
3657 kvm_run->exit_reason = KVM_EXIT_INTR;
3658 ++vcpu->stat.signal_exits;
3659 }
3660 if (need_resched()) {
3661 up_read(&vcpu->kvm->slots_lock);
3662 kvm_resched(vcpu);
3663 down_read(&vcpu->kvm->slots_lock);
d7690175 3664 }
b6c7a5dc
HB		 3665 }
3666
d7690175 3667 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3668 post_kvm_run_save(vcpu, kvm_run);
3669
b93463aa
AK		 3670 vapic_exit(vcpu);
3671
b6c7a5dc
HB		 3672 return r;
3673}
3674
3675int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3676{
3677 int r;
3678 sigset_t sigsaved;
3679
3680 vcpu_load(vcpu);
3681
ac9f6dc0
AK		 3682 if (vcpu->sigset_active)
3683 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3684
a4535290 3685 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3686 kvm_vcpu_block(vcpu);
d7690175 3687 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3688 r = -EAGAIN;
3689 goto out;
b6c7a5dc
HB		 3690 }
3691
b6c7a5dc
HB		 3692 /* re-sync apic's tpr */
3693 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3694 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3695
ad312c7c 3696 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3697 r = complete_pio(vcpu);
3698 if (r)
3699 goto out;
3700 }
3701#if CONFIG_HAS_IOMEM
3702 if (vcpu->mmio_needed) {
3703 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3704 vcpu->mmio_read_completed = 1;
3705 vcpu->mmio_needed = 0;
3200f405
MT		 3706
3707 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3708 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3709 vcpu->arch.mmio_fault_cr2, 0,
3710 EMULTYPE_NO_DECODE);
3200f405 3711 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3712 if (r == EMULATE_DO_MMIO) {
3713 /*
3714 * Read-modify-write. Back to userspace.
3715 */
3716 r = 0;
3717 goto out;
3718 }
3719 }
3720#endif
5fdbf976
MT		 3721 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3722 kvm_register_write(vcpu, VCPU_REGS_RAX,
3723 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3724
3725 r = __vcpu_run(vcpu, kvm_run);
3726
3727out:
3728 if (vcpu->sigset_active)
3729 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3730
3731 vcpu_put(vcpu);
3732 return r;
3733}
3734
3735int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3736{
3737 vcpu_load(vcpu);
3738
5fdbf976
MT		 3739 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3740 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3741 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3742 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3743 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3744 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3745 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3746 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3747#ifdef CONFIG_X86_64
5fdbf976
MT		 3748 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3749 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3750 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3751 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3752 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3753 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3754 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3755 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3756#endif
3757
5fdbf976 3758 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3759 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3760
3761 /*
3762 * Don't leak debug flags in case they were set for guest debugging
3763 */
d0bfb940 3764 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3765 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3766
3767 vcpu_put(vcpu);
3768
3769 return 0;
3770}
3771
3772int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3773{
3774 vcpu_load(vcpu);
3775
5fdbf976
MT		 3776 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3777 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3778 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3779 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3780 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3781 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3782 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3783 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3784#ifdef CONFIG_X86_64
5fdbf976
MT		 3785 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3786 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3787 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3788 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3789 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3790 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3791 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3792 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3793
b6c7a5dc
HB		 3794#endif
3795
5fdbf976 3796 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3797 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3798
b6c7a5dc 3799
b4f14abd
JK		 3800 vcpu->arch.exception.pending = false;
3801
b6c7a5dc
HB		 3802 vcpu_put(vcpu);
3803
3804 return 0;
3805}
3806
3e6e0aab
GT		 3807void kvm_get_segment(struct kvm_vcpu *vcpu,
3808 struct kvm_segment *var, int seg)
b6c7a5dc 3809{
14af3f3c 3810 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3811}
3812
3813void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3814{
3815 struct kvm_segment cs;
3816
3e6e0aab 3817 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3818 *db = cs.db;
3819 *l = cs.l;
3820}
3821EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3822
3823int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3824 struct kvm_sregs *sregs)
3825{
3826 struct descriptor_table dt;
b6c7a5dc
HB		 3827
3828 vcpu_load(vcpu);
3829
3e6e0aab
GT		 3830 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3831 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3832 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3833 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3834 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3835 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3836
3e6e0aab
GT		 3837 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3838 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3839
3840 kvm_x86_ops->get_idt(vcpu, &dt);
3841 sregs->idt.limit = dt.limit;
3842 sregs->idt.base = dt.base;
3843 kvm_x86_ops->get_gdt(vcpu, &dt);
3844 sregs->gdt.limit = dt.limit;
3845 sregs->gdt.base = dt.base;
3846
3847 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3848 sregs->cr0 = vcpu->arch.cr0;
3849 sregs->cr2 = vcpu->arch.cr2;
3850 sregs->cr3 = vcpu->arch.cr3;
3851 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3852 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3853 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3854 sregs->apic_base = kvm_get_apic_base(vcpu);
3855
923c61bb 3856 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3857
36752c9b 3858 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3859 set_bit(vcpu->arch.interrupt.nr,
3860 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3861
b6c7a5dc
HB		 3862 vcpu_put(vcpu);
3863
3864 return 0;
3865}
3866
62d9f0db
MT		 3867int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3868 struct kvm_mp_state *mp_state)
3869{
3870 vcpu_load(vcpu);
3871 mp_state->mp_state = vcpu->arch.mp_state;
3872 vcpu_put(vcpu);
3873 return 0;
3874}
3875
3876int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3877 struct kvm_mp_state *mp_state)
3878{
3879 vcpu_load(vcpu);
3880 vcpu->arch.mp_state = mp_state->mp_state;
3881 vcpu_put(vcpu);
3882 return 0;
3883}
3884
3e6e0aab 3885static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3886 struct kvm_segment *var, int seg)
3887{
14af3f3c 3888 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3889}
3890
37817f29
IE		 3891static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3892 struct kvm_segment *kvm_desct)
3893{
3894 kvm_desct->base = seg_desc->base0;
3895 kvm_desct->base |= seg_desc->base1 << 16;
3896 kvm_desct->base |= seg_desc->base2 << 24;
3897 kvm_desct->limit = seg_desc->limit0;
3898 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3899 if (seg_desc->g) {
3900 kvm_desct->limit <<= 12;
3901 kvm_desct->limit |= 0xfff;
3902 }
37817f29
IE		 3903 kvm_desct->selector = selector;
3904 kvm_desct->type = seg_desc->type;
3905 kvm_desct->present = seg_desc->p;
3906 kvm_desct->dpl = seg_desc->dpl;
3907 kvm_desct->db = seg_desc->d;
3908 kvm_desct->s = seg_desc->s;
3909 kvm_desct->l = seg_desc->l;
3910 kvm_desct->g = seg_desc->g;
3911 kvm_desct->avl = seg_desc->avl;
3912 if (!selector)
3913 kvm_desct->unusable = 1;
3914 else
3915 kvm_desct->unusable = 0;
3916 kvm_desct->padding = 0;
3917}
3918
b8222ad2
AS		 3919static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3920 u16 selector,
3921 struct descriptor_table *dtable)
37817f29
IE		 3922{
3923 if (selector & 1 << 2) {
3924 struct kvm_segment kvm_seg;
3925
3e6e0aab 3926 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3927
3928 if (kvm_seg.unusable)
3929 dtable->limit = 0;
3930 else
3931 dtable->limit = kvm_seg.limit;
3932 dtable->base = kvm_seg.base;
3933 }
3934 else
3935 kvm_x86_ops->get_gdt(vcpu, dtable);
3936}
3937
3938/* allowed just for 8 bytes segments */
3939static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3940 struct desc_struct *seg_desc)
3941{
98899aa0 3942 gpa_t gpa;
37817f29
IE		 3943 struct descriptor_table dtable;
3944 u16 index = selector >> 3;
3945
b8222ad2 3946 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3947
3948 if (dtable.limit < index * 8 + 7) {
3949 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3950 return 1;
3951 }
98899aa0
MT		 3952 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3953 gpa += index * 8;
3954 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3955}
3956
3957/* allowed just for 8 bytes segments */
3958static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3959 struct desc_struct *seg_desc)
3960{
98899aa0 3961 gpa_t gpa;
37817f29
IE		 3962 struct descriptor_table dtable;
3963 u16 index = selector >> 3;
3964
b8222ad2 3965 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3966
3967 if (dtable.limit < index * 8 + 7)
3968 return 1;
98899aa0
MT		 3969 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3970 gpa += index * 8;
3971 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3972}
3973
3974static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3975 struct desc_struct *seg_desc)
3976{
3977 u32 base_addr;
3978
3979 base_addr = seg_desc->base0;
3980 base_addr |= (seg_desc->base1 << 16);
3981 base_addr |= (seg_desc->base2 << 24);
3982
98899aa0 3983 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3984}
3985
37817f29
IE		 3986static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3987{
3988 struct kvm_segment kvm_seg;
3989
3e6e0aab 3990 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3991 return kvm_seg.selector;
3992}
3993
3994static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3995 u16 selector,
3996 struct kvm_segment *kvm_seg)
3997{
3998 struct desc_struct seg_desc;
3999
4000 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
4001 return 1;
4002 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
4003 return 0;
4004}
4005
2259e3a7 4006static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4007{
4008 struct kvm_segment segvar = {
4009 .base = selector << 4,
4010 .limit = 0xffff,
4011 .selector = selector,
4012 .type = 3,
4013 .present = 1,
4014 .dpl = 3,
4015 .db = 0,
4016 .s = 1,
4017 .l = 0,
4018 .g = 0,
4019 .avl = 0,
4020 .unusable = 0,
4021 };
4022 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4023 return 0;
4024}
4025
3e6e0aab
GT		 4026int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4027 int type_bits, int seg)
37817f29
IE		 4028{
4029 struct kvm_segment kvm_seg;
4030
f4bbd9aa
AK		 4031 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4032 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4033 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4034 return 1;
4035 kvm_seg.type |= type_bits;
4036
4037 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4038 seg != VCPU_SREG_LDTR)
4039 if (!kvm_seg.s)
4040 kvm_seg.unusable = 1;
4041
3e6e0aab 4042 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4043 return 0;
4044}
4045
4046static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4047 struct tss_segment_32 *tss)
4048{
4049 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4050 tss->eip = kvm_rip_read(vcpu);
37817f29 4051 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4052 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4053 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4054 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4055 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4056 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4057 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4058 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4059 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4060 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4061 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4062 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4063 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4064 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4065 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4066 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4067}
4068
4069static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4070 struct tss_segment_32 *tss)
4071{
4072 kvm_set_cr3(vcpu, tss->cr3);
4073
5fdbf976 4074 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 4075 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4076
5fdbf976
MT		 4077 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4078 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4079 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4080 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4081 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4082 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4083 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4084 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4085
3e6e0aab 4086 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4087 return 1;
4088
3e6e0aab 4089 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4090 return 1;
4091
3e6e0aab 4092 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4093 return 1;
4094
3e6e0aab 4095 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4096 return 1;
4097
3e6e0aab 4098 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4099 return 1;
4100
3e6e0aab 4101 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4102 return 1;
4103
3e6e0aab 4104 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4105 return 1;
4106 return 0;
4107}
4108
4109static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4110 struct tss_segment_16 *tss)
4111{
5fdbf976 4112 tss->ip = kvm_rip_read(vcpu);
37817f29 4113 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4114 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4115 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4116 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4117 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4118 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4119 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4120 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4121 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4122
4123 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4124 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4125 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4126 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4127 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4128 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4129}
4130
4131static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4132 struct tss_segment_16 *tss)
4133{
5fdbf976 4134 kvm_rip_write(vcpu, tss->ip);
37817f29 4135 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4136 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4137 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4138 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4139 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4140 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4141 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4142 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4143 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4144
3e6e0aab 4145 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4146 return 1;
4147
3e6e0aab 4148 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4149 return 1;
4150
3e6e0aab 4151 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4152 return 1;
4153
3e6e0aab 4154 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4155 return 1;
4156
3e6e0aab 4157 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4158 return 1;
4159 return 0;
4160}
4161
8b2cf73c 4162static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4163 u16 old_tss_sel, u32 old_tss_base,
4164 struct desc_struct *nseg_desc)
37817f29
IE		 4165{
4166 struct tss_segment_16 tss_segment_16;
4167 int ret = 0;
4168
34198bf8
MT		 4169 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4170 sizeof tss_segment_16))
37817f29
IE		 4171 goto out;
4172
4173 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4174
34198bf8
MT		 4175 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4176 sizeof tss_segment_16))
37817f29 4177 goto out;
34198bf8
MT		 4178
4179 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4180 &tss_segment_16, sizeof tss_segment_16))
4181 goto out;
4182
b237ac37
GN		 4183 if (old_tss_sel != 0xffff) {
4184 tss_segment_16.prev_task_link = old_tss_sel;
4185
4186 if (kvm_write_guest(vcpu->kvm,
4187 get_tss_base_addr(vcpu, nseg_desc),
4188 &tss_segment_16.prev_task_link,
4189 sizeof tss_segment_16.prev_task_link))
4190 goto out;
4191 }
4192
37817f29
IE		 4193 if (load_state_from_tss16(vcpu, &tss_segment_16))
4194 goto out;
4195
4196 ret = 1;
4197out:
4198 return ret;
4199}
4200
8b2cf73c 4201static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4202 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4203 struct desc_struct *nseg_desc)
4204{
4205 struct tss_segment_32 tss_segment_32;
4206 int ret = 0;
4207
34198bf8
MT		 4208 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4209 sizeof tss_segment_32))
37817f29
IE		 4210 goto out;
4211
4212 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4213
34198bf8
MT		 4214 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4215 sizeof tss_segment_32))
4216 goto out;
4217
4218 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4219 &tss_segment_32, sizeof tss_segment_32))
37817f29 4220 goto out;
34198bf8 4221
b237ac37
GN		 4222 if (old_tss_sel != 0xffff) {
4223 tss_segment_32.prev_task_link = old_tss_sel;
4224
4225 if (kvm_write_guest(vcpu->kvm,
4226 get_tss_base_addr(vcpu, nseg_desc),
4227 &tss_segment_32.prev_task_link,
4228 sizeof tss_segment_32.prev_task_link))
4229 goto out;
4230 }
4231
37817f29
IE		 4232 if (load_state_from_tss32(vcpu, &tss_segment_32))
4233 goto out;
4234
4235 ret = 1;
4236out:
4237 return ret;
4238}
4239
4240int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4241{
4242 struct kvm_segment tr_seg;
4243 struct desc_struct cseg_desc;
4244 struct desc_struct nseg_desc;
4245 int ret = 0;
34198bf8
MT		 4246 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4247 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4248
34198bf8 4249 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4250
34198bf8
MT		 4251 /* FIXME: Handle errors. Failure to read either TSS or their
4252 * descriptors should generate a pagefault.
4253 */
37817f29
IE		 4254 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4255 goto out;
4256
34198bf8 4257 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4258 goto out;
4259
37817f29
IE		 4260 if (reason != TASK_SWITCH_IRET) {
4261 int cpl;
4262
4263 cpl = kvm_x86_ops->get_cpl(vcpu);
4264 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4265 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4266 return 1;
4267 }
4268 }
4269
4270 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
4271 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4272 return 1;
4273 }
4274
4275 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4276 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4277 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4278 }
4279
4280 if (reason == TASK_SWITCH_IRET) {
4281 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4282 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4283 }
4284
64a7ec06
GN		 4285 /* set back link to prev task only if NT bit is set in eflags
4286 note that old_tss_sel is not used afetr this point */
4287 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4288 old_tss_sel = 0xffff;
37817f29 4289
b237ac37
GN		 4290 /* set back link to prev task only if NT bit is set in eflags
4291 note that old_tss_sel is not used afetr this point */
4292 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4293 old_tss_sel = 0xffff;
4294
37817f29 4295 if (nseg_desc.type & 8)
b237ac37
GN		 4296 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4297 old_tss_base, &nseg_desc);
37817f29 4298 else
b237ac37
GN		 4299 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4300 old_tss_base, &nseg_desc);
37817f29
IE		 4301
4302 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4303 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4304 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4305 }
4306
4307 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4308 nseg_desc.type |= (1 << 1);
37817f29
IE		 4309 save_guest_segment_descriptor(vcpu, tss_selector,
4310 &nseg_desc);
4311 }
4312
4313 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4314 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4315 tr_seg.type = 11;
3e6e0aab 4316 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4317out:
37817f29
IE		 4318 return ret;
4319}
4320EXPORT_SYMBOL_GPL(kvm_task_switch);
4321
b6c7a5dc
HB		 4322int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4323 struct kvm_sregs *sregs)
4324{
4325 int mmu_reset_needed = 0;
923c61bb 4326 int pending_vec, max_bits;
b6c7a5dc
HB		 4327 struct descriptor_table dt;
4328
4329 vcpu_load(vcpu);
4330
4331 dt.limit = sregs->idt.limit;
4332 dt.base = sregs->idt.base;
4333 kvm_x86_ops->set_idt(vcpu, &dt);
4334 dt.limit = sregs->gdt.limit;
4335 dt.base = sregs->gdt.base;
4336 kvm_x86_ops->set_gdt(vcpu, &dt);
4337
ad312c7c
ZX		 4338 vcpu->arch.cr2 = sregs->cr2;
4339 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
59839dff
MT		 4340
4341 down_read(&vcpu->kvm->slots_lock);
4342 if (gfn_to_memslot(vcpu->kvm, sregs->cr3 >> PAGE_SHIFT))
4343 vcpu->arch.cr3 = sregs->cr3;
4344 else
4345 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
4346 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc 4347
2d3ad1f4 4348 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4349
ad312c7c 4350 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4351 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4352 kvm_set_apic_base(vcpu, sregs->apic_base);
4353
4354 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4355
ad312c7c 4356 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4357 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4358 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4359
ad312c7c 4360 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4361 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4362 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4363 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4364
4365 if (mmu_reset_needed)
4366 kvm_mmu_reset_context(vcpu);
4367
923c61bb
GN		 4368 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4369 pending_vec = find_first_bit(
4370 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4371 if (pending_vec < max_bits) {
66fd3f7f 4372 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4373 pr_debug("Set back pending irq %d\n", pending_vec);
4374 if (irqchip_in_kernel(vcpu->kvm))
4375 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4376 }
4377
3e6e0aab
GT		 4378 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4379 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4380 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4381 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4382 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4383 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4384
3e6e0aab
GT		 4385 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4386 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4387
9c3e4aab 4388 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4389 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4390 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4391 !(vcpu->arch.cr0 & X86_CR0_PE))
4392 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4393
b6c7a5dc
HB		 4394 vcpu_put(vcpu);
4395
4396 return 0;
4397}
4398
d0bfb940
JK		 4399int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4400 struct kvm_guest_debug *dbg)
b6c7a5dc 4401{
ae675ef0 4402 int i, r;
b6c7a5dc
HB		 4403
4404 vcpu_load(vcpu);
4405
ae675ef0
JK		 4406 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4407 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4408 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4409 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4410 vcpu->arch.switch_db_regs =
4411 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4412 } else {
4413 for (i = 0; i < KVM_NR_DB_REGS; i++)
4414 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4415 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4416 }
4417
b6c7a5dc
HB		 4418 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4419
d0bfb940
JK		 4420 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4421 kvm_queue_exception(vcpu, DB_VECTOR);
4422 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4423 kvm_queue_exception(vcpu, BP_VECTOR);
4424
b6c7a5dc
HB		 4425 vcpu_put(vcpu);
4426
4427 return r;
4428}
4429
d0752060
HB		 4430/*
4431 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4432 * we have asm/x86/processor.h
4433 */
4434struct fxsave {
4435 u16 cwd;
4436 u16 swd;
4437 u16 twd;
4438 u16 fop;
4439 u64 rip;
4440 u64 rdp;
4441 u32 mxcsr;
4442 u32 mxcsr_mask;
4443 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4444#ifdef CONFIG_X86_64
4445 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4446#else
4447 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4448#endif
4449};
4450
8b006791
ZX		 4451/*
4452 * Translate a guest virtual address to a guest physical address.
4453 */
4454int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4455 struct kvm_translation *tr)
4456{
4457 unsigned long vaddr = tr->linear_address;
4458 gpa_t gpa;
4459
4460 vcpu_load(vcpu);
72dc67a6 4461 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4462 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4463 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4464 tr->physical_address = gpa;
4465 tr->valid = gpa != UNMAPPED_GVA;
4466 tr->writeable = 1;
4467 tr->usermode = 0;
8b006791
ZX		 4468 vcpu_put(vcpu);
4469
4470 return 0;
4471}
4472
d0752060
HB		 4473int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4474{
ad312c7c 4475 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4476
4477 vcpu_load(vcpu);
4478
4479 memcpy(fpu->fpr, fxsave->st_space, 128);
4480 fpu->fcw = fxsave->cwd;
4481 fpu->fsw = fxsave->swd;
4482 fpu->ftwx = fxsave->twd;
4483 fpu->last_opcode = fxsave->fop;
4484 fpu->last_ip = fxsave->rip;
4485 fpu->last_dp = fxsave->rdp;
4486 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4487
4488 vcpu_put(vcpu);
4489
4490 return 0;
4491}
4492
4493int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4494{
ad312c7c 4495 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4496
4497 vcpu_load(vcpu);
4498
4499 memcpy(fxsave->st_space, fpu->fpr, 128);
4500 fxsave->cwd = fpu->fcw;
4501 fxsave->swd = fpu->fsw;
4502 fxsave->twd = fpu->ftwx;
4503 fxsave->fop = fpu->last_opcode;
4504 fxsave->rip = fpu->last_ip;
4505 fxsave->rdp = fpu->last_dp;
4506 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4507
4508 vcpu_put(vcpu);
4509
4510 return 0;
4511}
4512
4513void fx_init(struct kvm_vcpu *vcpu)
4514{
4515 unsigned after_mxcsr_mask;
4516
bc1a34f1
AA		 4517 /*
4518 * Touch the fpu the first time in non atomic context as if
4519 * this is the first fpu instruction the exception handler
4520 * will fire before the instruction returns and it'll have to
4521 * allocate ram with GFP_KERNEL.
4522 */
4523 if (!used_math())
d6e88aec 4524 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4525
d0752060
HB		 4526 /* Initialize guest FPU by resetting ours and saving into guest's */
4527 preempt_disable();
d6e88aec
AK		 4528 kvm_fx_save(&vcpu->arch.host_fx_image);
4529 kvm_fx_finit();
4530 kvm_fx_save(&vcpu->arch.guest_fx_image);
4531 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4532 preempt_enable();
4533
ad312c7c 4534 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4535 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4536 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4537 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4538 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4539}
4540EXPORT_SYMBOL_GPL(fx_init);
4541
4542void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4543{
4544 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4545 return;
4546
4547 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4548 kvm_fx_save(&vcpu->arch.host_fx_image);
4549 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4550}
4551EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4552
4553void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4554{
4555 if (!vcpu->guest_fpu_loaded)
4556 return;
4557
4558 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4559 kvm_fx_save(&vcpu->arch.guest_fx_image);
4560 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4561 ++vcpu->stat.fpu_reload;
d0752060
HB		 4562}
4563EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4564
4565void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4566{
7f1ea208
JR		 4567 if (vcpu->arch.time_page) {
4568 kvm_release_page_dirty(vcpu->arch.time_page);
4569 vcpu->arch.time_page = NULL;
4570 }
4571
e9b11c17
ZX		 4572 kvm_x86_ops->vcpu_free(vcpu);
4573}
4574
4575struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4576 unsigned int id)
4577{
26e5215f
AK		 4578 return kvm_x86_ops->vcpu_create(kvm, id);
4579}
e9b11c17 4580
26e5215f
AK		 4581int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4582{
4583 int r;
e9b11c17
ZX		 4584
4585 /* We do fxsave: this must be aligned. */
ad312c7c 4586 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4587
0bed3b56 4588 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4589 vcpu_load(vcpu);
4590 r = kvm_arch_vcpu_reset(vcpu);
4591 if (r == 0)
4592 r = kvm_mmu_setup(vcpu);
4593 vcpu_put(vcpu);
4594 if (r < 0)
4595 goto free_vcpu;
4596
26e5215f 4597 return 0;
e9b11c17
ZX		 4598free_vcpu:
4599 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4600 return r;
e9b11c17
ZX		 4601}
4602
d40ccc62 4603void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4604{
4605 vcpu_load(vcpu);
4606 kvm_mmu_unload(vcpu);
4607 vcpu_put(vcpu);
4608
4609 kvm_x86_ops->vcpu_free(vcpu);
4610}
4611
4612int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4613{
448fa4a9
JK		 4614 vcpu->arch.nmi_pending = false;
4615 vcpu->arch.nmi_injected = false;
4616
42dbaa5a
JK		 4617 vcpu->arch.switch_db_regs = 0;
4618 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4619 vcpu->arch.dr6 = DR6_FIXED_1;
4620 vcpu->arch.dr7 = DR7_FIXED_1;
4621
e9b11c17
ZX		 4622 return kvm_x86_ops->vcpu_reset(vcpu);
4623}
4624
4625void kvm_arch_hardware_enable(void *garbage)
4626{
4627 kvm_x86_ops->hardware_enable(garbage);
4628}
4629
4630void kvm_arch_hardware_disable(void *garbage)
4631{
4632 kvm_x86_ops->hardware_disable(garbage);
4633}
4634
4635int kvm_arch_hardware_setup(void)
4636{
4637 return kvm_x86_ops->hardware_setup();
4638}
4639
4640void kvm_arch_hardware_unsetup(void)
4641{
4642 kvm_x86_ops->hardware_unsetup();
4643}
4644
4645void kvm_arch_check_processor_compat(void *rtn)
4646{
4647 kvm_x86_ops->check_processor_compatibility(rtn);
4648}
4649
4650int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4651{
4652 struct page *page;
4653 struct kvm *kvm;
4654 int r;
4655
4656 BUG_ON(vcpu->kvm == NULL);
4657 kvm = vcpu->kvm;
4658
ad312c7c 4659 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 4660 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 4661 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4662 else
a4535290 4663 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4664
4665 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4666 if (!page) {
4667 r = -ENOMEM;
4668 goto fail;
4669 }
ad312c7c 4670 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4671
4672 r = kvm_mmu_create(vcpu);
4673 if (r < 0)
4674 goto fail_free_pio_data;
4675
4676 if (irqchip_in_kernel(kvm)) {
4677 r = kvm_create_lapic(vcpu);
4678 if (r < 0)
4679 goto fail_mmu_destroy;
4680 }
4681
890ca9ae
HY		 4682 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4683 GFP_KERNEL);
4684 if (!vcpu->arch.mce_banks) {
4685 r = -ENOMEM;
4686 goto fail_mmu_destroy;
4687 }
4688 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4689
e9b11c17
ZX		 4690 return 0;
4691
4692fail_mmu_destroy:
4693 kvm_mmu_destroy(vcpu);
4694fail_free_pio_data:
ad312c7c 4695 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4696fail:
4697 return r;
4698}
4699
4700void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4701{
4702 kvm_free_lapic(vcpu);
3200f405 4703 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4704 kvm_mmu_destroy(vcpu);
3200f405 4705 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4706 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4707}
d19a9cd2
ZX		 4708
4709struct kvm *kvm_arch_create_vm(void)
4710{
4711 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4712
4713 if (!kvm)
4714 return ERR_PTR(-ENOMEM);
4715
f05e70ac 4716 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4717 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4718
5550af4d
SY		 4719 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4720 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4721
53f658b3
MT		 4722 rdtscll(kvm->arch.vm_init_tsc);
4723
d19a9cd2
ZX		 4724 return kvm;
4725}
4726
4727static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4728{
4729 vcpu_load(vcpu);
4730 kvm_mmu_unload(vcpu);
4731 vcpu_put(vcpu);
4732}
4733
4734static void kvm_free_vcpus(struct kvm *kvm)
4735{
4736 unsigned int i;
988a2cae 4737 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 4738
4739 /*
4740 * Unpin any mmu pages first.
4741 */
988a2cae
GN		 4742 kvm_for_each_vcpu(i, vcpu, kvm)
4743 kvm_unload_vcpu_mmu(vcpu);
4744 kvm_for_each_vcpu(i, vcpu, kvm)
4745 kvm_arch_vcpu_free(vcpu);
4746
4747 mutex_lock(&kvm->lock);
4748 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4749 kvm->vcpus[i] = NULL;
d19a9cd2 4750
988a2cae
GN		 4751 atomic_set(&kvm->online_vcpus, 0);
4752 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 4753}
4754
ad8ba2cd
SY		 4755void kvm_arch_sync_events(struct kvm *kvm)
4756{
ba4cef31 4757 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4758}
4759
d19a9cd2
ZX		 4760void kvm_arch_destroy_vm(struct kvm *kvm)
4761{
6eb55818 4762 kvm_iommu_unmap_guest(kvm);
7837699f 4763 kvm_free_pit(kvm);
d7deeeb0
ZX		 4764 kfree(kvm->arch.vpic);
4765 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4766 kvm_free_vcpus(kvm);
4767 kvm_free_physmem(kvm);
3d45830c
AK		 4768 if (kvm->arch.apic_access_page)
4769 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4770 if (kvm->arch.ept_identity_pagetable)
4771 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4772 kfree(kvm);
4773}
0de10343
ZX		 4774
4775int kvm_arch_set_memory_region(struct kvm *kvm,
4776 struct kvm_userspace_memory_region *mem,
4777 struct kvm_memory_slot old,
4778 int user_alloc)
4779{
4780 int npages = mem->memory_size >> PAGE_SHIFT;
4781 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4782
4783 /*To keep backward compatibility with older userspace,
4784 *x86 needs to hanlde !user_alloc case.
4785 */
4786 if (!user_alloc) {
4787 if (npages && !old.rmap) {
604b38ac
AA		 4788 unsigned long userspace_addr;
4789
72dc67a6 4790 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4791 userspace_addr = do_mmap(NULL, 0,
4792 npages * PAGE_SIZE,
4793 PROT_READ | PROT_WRITE,
acee3c04 4794 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4795 0);
72dc67a6 4796 up_write(&current->mm->mmap_sem);
0de10343 4797
604b38ac
AA		 4798 if (IS_ERR((void *)userspace_addr))
4799 return PTR_ERR((void *)userspace_addr);
4800
4801 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4802 spin_lock(&kvm->mmu_lock);
4803 memslot->userspace_addr = userspace_addr;
4804 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4805 } else {
4806 if (!old.user_alloc && old.rmap) {
4807 int ret;
4808
72dc67a6 4809 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4810 ret = do_munmap(current->mm, old.userspace_addr,
4811 old.npages * PAGE_SIZE);
72dc67a6 4812 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4813 if (ret < 0)
4814 printk(KERN_WARNING
4815 "kvm_vm_ioctl_set_memory_region: "
4816 "failed to munmap memory\n");
4817 }
4818 }
4819 }
4820
7c8a83b7 4821 spin_lock(&kvm->mmu_lock);
f05e70ac 4822 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4823 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4824 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4825 }
4826
4827 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4828 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4829 kvm_flush_remote_tlbs(kvm);
4830
4831 return 0;
4832}
1d737c8a 4833
34d4cb8f
MT		 4834void kvm_arch_flush_shadow(struct kvm *kvm)
4835{
4836 kvm_mmu_zap_all(kvm);
8986ecc0 4837 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4838}
4839
1d737c8a
ZX		 4840int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4841{
a4535290 4842 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4843 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4844 || vcpu->arch.nmi_pending;
1d737c8a 4845}
5736199a 4846
5736199a
ZX		 4847void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4848{
32f88400
MT		 4849 int me;
4850 int cpu = vcpu->cpu;
5736199a
ZX		 4851
4852 if (waitqueue_active(&vcpu->wq)) {
4853 wake_up_interruptible(&vcpu->wq);
4854 ++vcpu->stat.halt_wakeup;
4855 }
32f88400
MT		 4856
4857 me = get_cpu();
4858 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4859 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4860 smp_send_reschedule(cpu);
e9571ed5 4861 put_cpu();
5736199a 4862}
78646121
GN		 4863
4864int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4865{
4866 return kvm_x86_ops->interrupt_allowed(vcpu);
4867}
229456fc
MT		 4868
4869EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4870EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4871EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4872EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4873EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
Linux 6.x block layer and io_uring tree(s)