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x86/speculation: Use ARCH_CAPABILITIES to skip L1D flush on vmentry
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 141EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 142
52004014
FW		 143static bool __read_mostly vector_hashing = true;
144module_param(vector_hashing, bool, S_IRUGO);
145
c4ae60e4
LA		 146bool __read_mostly enable_vmware_backdoor = false;
147module_param(enable_vmware_backdoor, bool, S_IRUGO);
148EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
149
6c86eedc
WL		 150static bool __read_mostly force_emulation_prefix = false;
151module_param(force_emulation_prefix, bool, S_IRUGO);
152
18863bdd
AK		 153#define KVM_NR_SHARED_MSRS 16
154
155struct kvm_shared_msrs_global {
156 int nr;
2bf78fa7 157 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 158};
159
160struct kvm_shared_msrs {
161 struct user_return_notifier urn;
162 bool registered;
2bf78fa7
SY		 163 struct kvm_shared_msr_values {
164 u64 host;
165 u64 curr;
166 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 167};
168
169static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 170static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 171
417bc304 172struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 173 { "pf_fixed", VCPU_STAT(pf_fixed) },
174 { "pf_guest", VCPU_STAT(pf_guest) },
175 { "tlb_flush", VCPU_STAT(tlb_flush) },
176 { "invlpg", VCPU_STAT(invlpg) },
177 { "exits", VCPU_STAT(exits) },
178 { "io_exits", VCPU_STAT(io_exits) },
179 { "mmio_exits", VCPU_STAT(mmio_exits) },
180 { "signal_exits", VCPU_STAT(signal_exits) },
181 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 182 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 183 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 184 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 185 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 186 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 187 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 188 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 189 { "request_irq", VCPU_STAT(request_irq_exits) },
190 { "irq_exits", VCPU_STAT(irq_exits) },
191 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 192 { "fpu_reload", VCPU_STAT(fpu_reload) },
193 { "insn_emulation", VCPU_STAT(insn_emulation) },
194 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 195 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 196 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 197 { "req_event", VCPU_STAT(req_event) },
c595ceee 198 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 199 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
200 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
201 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
202 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
203 { "mmu_flooded", VM_STAT(mmu_flooded) },
204 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 205 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 206 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 207 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 208 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 209 { "max_mmu_page_hash_collisions",
210 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 211 { NULL }
212};
213
2acf923e
DC		 214u64 __read_mostly host_xcr0;
215
b6785def 216static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 217
af585b92
GN		 218static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
219{
220 int i;
221 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
222 vcpu->arch.apf.gfns[i] = ~0;
223}
224
18863bdd
AK		 225static void kvm_on_user_return(struct user_return_notifier *urn)
226{
227 unsigned slot;
18863bdd
AK		 228 struct kvm_shared_msrs *locals
229 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 230 struct kvm_shared_msr_values *values;
1650b4eb
IA		 231 unsigned long flags;
232
233 /*
234 * Disabling irqs at this point since the following code could be
235 * interrupted and executed through kvm_arch_hardware_disable()
236 */
237 local_irq_save(flags);
238 if (locals->registered) {
239 locals->registered = false;
240 user_return_notifier_unregister(urn);
241 }
242 local_irq_restore(flags);
18863bdd 243 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 244 values = &locals->values[slot];
245 if (values->host != values->curr) {
246 wrmsrl(shared_msrs_global.msrs[slot], values->host);
247 values->curr = values->host;
18863bdd
AK		 248 }
249 }
18863bdd
AK		 250}
251
2bf78fa7 252static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 253{
18863bdd 254 u64 value;
013f6a5d
MT		 255 unsigned int cpu = smp_processor_id();
256 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 257
2bf78fa7
SY		 258 /* only read, and nobody should modify it at this time,
259 * so don't need lock */
260 if (slot >= shared_msrs_global.nr) {
261 printk(KERN_ERR "kvm: invalid MSR slot!");
262 return;
263 }
264 rdmsrl_safe(msr, &value);
265 smsr->values[slot].host = value;
266 smsr->values[slot].curr = value;
267}
268
269void kvm_define_shared_msr(unsigned slot, u32 msr)
270{
0123be42 271 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 272 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 273 if (slot >= shared_msrs_global.nr)
274 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 275}
276EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
277
278static void kvm_shared_msr_cpu_online(void)
279{
280 unsigned i;
18863bdd
AK		 281
282 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 283 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 284}
285
8b3c3104 286int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 287{
013f6a5d
MT		 288 unsigned int cpu = smp_processor_id();
289 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 290 int err;
18863bdd 291
2bf78fa7 292 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 293 return 0;
2bf78fa7 294 smsr->values[slot].curr = value;
8b3c3104
AH		 295 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
296 if (err)
297 return 1;
298
18863bdd
AK		 299 if (!smsr->registered) {
300 smsr->urn.on_user_return = kvm_on_user_return;
301 user_return_notifier_register(&smsr->urn);
302 smsr->registered = true;
303 }
8b3c3104 304 return 0;
18863bdd
AK		 305}
306EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
307
13a34e06 308static void drop_user_return_notifiers(void)
3548bab5 309{
013f6a5d
MT		 310 unsigned int cpu = smp_processor_id();
311 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 312
313 if (smsr->registered)
314 kvm_on_user_return(&smsr->urn);
315}
316
6866b83e
CO		 317u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
318{
8a5a87d9 319 return vcpu->arch.apic_base;
6866b83e
CO		 320}
321EXPORT_SYMBOL_GPL(kvm_get_apic_base);
322
58871649
JM		 323enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
324{
325 return kvm_apic_mode(kvm_get_apic_base(vcpu));
326}
327EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
328
58cb628d
JK		 329int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
330{
58871649
JM		 331 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
332 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 333 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
334 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 335
58871649 336 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 337 return 1;
58871649
JM		 338 if (!msr_info->host_initiated) {
339 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
340 return 1;
341 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
342 return 1;
343 }
58cb628d
JK		 344
345 kvm_lapic_set_base(vcpu, msr_info->data);
346 return 0;
6866b83e
CO		 347}
348EXPORT_SYMBOL_GPL(kvm_set_apic_base);
349
2605fc21 350asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 351{
352 /* Fault while not rebooting. We want the trace. */
353 BUG();
354}
355EXPORT_SYMBOL_GPL(kvm_spurious_fault);
356
3fd28fce
ED		 357#define EXCPT_BENIGN 0
358#define EXCPT_CONTRIBUTORY 1
359#define EXCPT_PF 2
360
361static int exception_class(int vector)
362{
363 switch (vector) {
364 case PF_VECTOR:
365 return EXCPT_PF;
366 case DE_VECTOR:
367 case TS_VECTOR:
368 case NP_VECTOR:
369 case SS_VECTOR:
370 case GP_VECTOR:
371 return EXCPT_CONTRIBUTORY;
372 default:
373 break;
374 }
375 return EXCPT_BENIGN;
376}
377
d6e8c854
NA		 378#define EXCPT_FAULT 0
379#define EXCPT_TRAP 1
380#define EXCPT_ABORT 2
381#define EXCPT_INTERRUPT 3
382
383static int exception_type(int vector)
384{
385 unsigned int mask;
386
387 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
388 return EXCPT_INTERRUPT;
389
390 mask = 1 << vector;
391
392 /* #DB is trap, as instruction watchpoints are handled elsewhere */
393 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
394 return EXCPT_TRAP;
395
396 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
397 return EXCPT_ABORT;
398
399 /* Reserved exceptions will result in fault */
400 return EXCPT_FAULT;
401}
402
3fd28fce 403static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 404 unsigned nr, bool has_error, u32 error_code,
405 bool reinject)
3fd28fce
ED		 406{
407 u32 prev_nr;
408 int class1, class2;
409
3842d135
AK		 410 kvm_make_request(KVM_REQ_EVENT, vcpu);
411
664f8e26 412 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 413 queue:
3ffb2468
NA		 414 if (has_error && !is_protmode(vcpu))
415 has_error = false;
664f8e26
WL		 416 if (reinject) {
417 /*
418 * On vmentry, vcpu->arch.exception.pending is only
419 * true if an event injection was blocked by
420 * nested_run_pending. In that case, however,
421 * vcpu_enter_guest requests an immediate exit,
422 * and the guest shouldn't proceed far enough to
423 * need reinjection.
424 */
425 WARN_ON_ONCE(vcpu->arch.exception.pending);
426 vcpu->arch.exception.injected = true;
427 } else {
428 vcpu->arch.exception.pending = true;
429 vcpu->arch.exception.injected = false;
430 }
3fd28fce
ED		 431 vcpu->arch.exception.has_error_code = has_error;
432 vcpu->arch.exception.nr = nr;
433 vcpu->arch.exception.error_code = error_code;
434 return;
435 }
436
437 /* to check exception */
438 prev_nr = vcpu->arch.exception.nr;
439 if (prev_nr == DF_VECTOR) {
440 /* triple fault -> shutdown */
a8eeb04a 441 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 442 return;
443 }
444 class1 = exception_class(prev_nr);
445 class2 = exception_class(nr);
446 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
447 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 448 /*
449 * Generate double fault per SDM Table 5-5. Set
450 * exception.pending = true so that the double fault
451 * can trigger a nested vmexit.
452 */
3fd28fce 453 vcpu->arch.exception.pending = true;
664f8e26 454 vcpu->arch.exception.injected = false;
3fd28fce
ED		 455 vcpu->arch.exception.has_error_code = true;
456 vcpu->arch.exception.nr = DF_VECTOR;
457 vcpu->arch.exception.error_code = 0;
458 } else
459 /* replace previous exception with a new one in a hope
460 that instruction re-execution will regenerate lost
461 exception */
462 goto queue;
463}
464
298101da
AK		 465void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
466{
ce7ddec4 467 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 468}
469EXPORT_SYMBOL_GPL(kvm_queue_exception);
470
ce7ddec4
JR		 471void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
472{
473 kvm_multiple_exception(vcpu, nr, false, 0, true);
474}
475EXPORT_SYMBOL_GPL(kvm_requeue_exception);
476
6affcbed 477int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 478{
db8fcefa
AP		 479 if (err)
480 kvm_inject_gp(vcpu, 0);
481 else
6affcbed
KH		 482 return kvm_skip_emulated_instruction(vcpu);
483
484 return 1;
db8fcefa
AP		 485}
486EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 487
6389ee94 488void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 489{
490 ++vcpu->stat.pf_guest;
adfe20fb
WL		 491 vcpu->arch.exception.nested_apf =
492 is_guest_mode(vcpu) && fault->async_page_fault;
493 if (vcpu->arch.exception.nested_apf)
494 vcpu->arch.apf.nested_apf_token = fault->address;
495 else
496 vcpu->arch.cr2 = fault->address;
6389ee94 497 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 498}
27d6c865 499EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 500
ef54bcfe 501static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 502{
6389ee94
AK		 503 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
504 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 505 else
6389ee94 506 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 507
508 return fault->nested_page_fault;
d4f8cf66
JR		 509}
510
3419ffc8
SY		 511void kvm_inject_nmi(struct kvm_vcpu *vcpu)
512{
7460fb4a
AK		 513 atomic_inc(&vcpu->arch.nmi_queued);
514 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 515}
516EXPORT_SYMBOL_GPL(kvm_inject_nmi);
517
298101da
AK		 518void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
519{
ce7ddec4 520 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 521}
522EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
523
ce7ddec4
JR		 524void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
525{
526 kvm_multiple_exception(vcpu, nr, true, error_code, true);
527}
528EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
529
0a79b009
AK		 530/*
531 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
532 * a #GP and return false.
533 */
534bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 535{
0a79b009
AK		 536 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
537 return true;
538 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
539 return false;
298101da 540}
0a79b009 541EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 542
16f8a6f9
NA		 543bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
544{
545 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
546 return true;
547
548 kvm_queue_exception(vcpu, UD_VECTOR);
549 return false;
550}
551EXPORT_SYMBOL_GPL(kvm_require_dr);
552
ec92fe44
JR		 553/*
554 * This function will be used to read from the physical memory of the currently
54bf36aa 555 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 556 * can read from guest physical or from the guest's guest physical memory.
557 */
558int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
559 gfn_t ngfn, void *data, int offset, int len,
560 u32 access)
561{
54987b7a 562 struct x86_exception exception;
ec92fe44
JR		 563 gfn_t real_gfn;
564 gpa_t ngpa;
565
566 ngpa = gfn_to_gpa(ngfn);
54987b7a 567 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 568 if (real_gfn == UNMAPPED_GVA)
569 return -EFAULT;
570
571 real_gfn = gpa_to_gfn(real_gfn);
572
54bf36aa 573 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 574}
575EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
576
69b0049a 577static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 578 void *data, int offset, int len, u32 access)
579{
580 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
581 data, offset, len, access);
582}
583
a03490ed
CO		 584/*
585 * Load the pae pdptrs. Return true is they are all valid.
586 */
ff03a073 587int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 588{
589 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
590 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
591 int i;
592 int ret;
ff03a073 593 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 594
ff03a073
JR		 595 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
596 offset * sizeof(u64), sizeof(pdpte),
597 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 598 if (ret < 0) {
599 ret = 0;
600 goto out;
601 }
602 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 603 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 604 (pdpte[i] &
605 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 606 ret = 0;
607 goto out;
608 }
609 }
610 ret = 1;
611
ff03a073 612 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 613 __set_bit(VCPU_EXREG_PDPTR,
614 (unsigned long *)&vcpu->arch.regs_avail);
615 __set_bit(VCPU_EXREG_PDPTR,
616 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 617out:
a03490ed
CO		 618
619 return ret;
620}
cc4b6871 621EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 622
9ed38ffa 623bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 624{
ff03a073 625 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 626 bool changed = true;
3d06b8bf
JR		 627 int offset;
628 gfn_t gfn;
d835dfec
AK		 629 int r;
630
631 if (is_long_mode(vcpu) || !is_pae(vcpu))
632 return false;
633
6de4f3ad
AK		 634 if (!test_bit(VCPU_EXREG_PDPTR,
635 (unsigned long *)&vcpu->arch.regs_avail))
636 return true;
637
a512177e
PB		 638 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
639 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 640 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
641 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 642 if (r < 0)
643 goto out;
ff03a073 644 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 645out:
d835dfec
AK		 646
647 return changed;
648}
9ed38ffa 649EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 650
49a9b07e 651int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 652{
aad82703 653 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 654 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 655
f9a48e6a
AK		 656 cr0 |= X86_CR0_ET;
657
ab344828 658#ifdef CONFIG_X86_64
0f12244f
GN		 659 if (cr0 & 0xffffffff00000000UL)
660 return 1;
ab344828
GN		 661#endif
662
663 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 664
0f12244f
GN		 665 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
666 return 1;
a03490ed 667
0f12244f
GN		 668 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
669 return 1;
a03490ed
CO		 670
671 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
672#ifdef CONFIG_X86_64
f6801dff 673 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 674 int cs_db, cs_l;
675
0f12244f
GN		 676 if (!is_pae(vcpu))
677 return 1;
a03490ed 678 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 679 if (cs_l)
680 return 1;
a03490ed
CO		 681 } else
682#endif
ff03a073 683 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 684 kvm_read_cr3(vcpu)))
0f12244f 685 return 1;
a03490ed
CO		 686 }
687
ad756a16
MJ		 688 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
689 return 1;
690
a03490ed 691 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 692
d170c419 693 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 694 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 695 kvm_async_pf_hash_reset(vcpu);
696 }
e5f3f027 697
aad82703
SY		 698 if ((cr0 ^ old_cr0) & update_bits)
699 kvm_mmu_reset_context(vcpu);
b18d5431 700
879ae188
LE		 701 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
702 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
703 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 704 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
705
0f12244f
GN		 706 return 0;
707}
2d3ad1f4 708EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 709
2d3ad1f4 710void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 711{
49a9b07e 712 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 713}
2d3ad1f4 714EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 715
42bdf991
MT		 716static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
717{
718 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
719 !vcpu->guest_xcr0_loaded) {
720 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 721 if (vcpu->arch.xcr0 != host_xcr0)
722 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 723 vcpu->guest_xcr0_loaded = 1;
724 }
725}
726
727static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
728{
729 if (vcpu->guest_xcr0_loaded) {
730 if (vcpu->arch.xcr0 != host_xcr0)
731 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
732 vcpu->guest_xcr0_loaded = 0;
733 }
734}
735
69b0049a 736static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 737{
56c103ec
LJ		 738 u64 xcr0 = xcr;
739 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 740 u64 valid_bits;
2acf923e
DC		 741
742 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
743 if (index != XCR_XFEATURE_ENABLED_MASK)
744 return 1;
d91cab78 745 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 746 return 1;
d91cab78 747 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 748 return 1;
46c34cb0
PB		 749
750 /*
751 * Do not allow the guest to set bits that we do not support
752 * saving. However, xcr0 bit 0 is always set, even if the
753 * emulated CPU does not support XSAVE (see fx_init).
754 */
d91cab78 755 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 756 if (xcr0 & ~valid_bits)
2acf923e 757 return 1;
46c34cb0 758
d91cab78
DH		 759 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
760 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 761 return 1;
762
d91cab78
DH		 763 if (xcr0 & XFEATURE_MASK_AVX512) {
764 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 765 return 1;
d91cab78 766 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 767 return 1;
768 }
2acf923e 769 vcpu->arch.xcr0 = xcr0;
56c103ec 770
d91cab78 771 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 772 kvm_update_cpuid(vcpu);
2acf923e
DC		 773 return 0;
774}
775
776int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
777{
764bcbc5
Z		 778 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
779 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 780 kvm_inject_gp(vcpu, 0);
781 return 1;
782 }
783 return 0;
784}
785EXPORT_SYMBOL_GPL(kvm_set_xcr);
786
a83b29c6 787int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 788{
fc78f519 789 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 790 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 791 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 792
0f12244f
GN		 793 if (cr4 & CR4_RESERVED_BITS)
794 return 1;
a03490ed 795
d6321d49 796 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 797 return 1;
798
d6321d49 799 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 800 return 1;
801
d6321d49 802 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 803 return 1;
804
d6321d49 805 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 806 return 1;
807
d6321d49 808 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 809 return 1;
810
fd8cb433 811 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 812 return 1;
813
ae3e61e1
PB		 814 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
815 return 1;
816
a03490ed 817 if (is_long_mode(vcpu)) {
0f12244f
GN		 818 if (!(cr4 & X86_CR4_PAE))
819 return 1;
a2edf57f
AK		 820 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
821 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 822 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
823 kvm_read_cr3(vcpu)))
0f12244f
GN		 824 return 1;
825
ad756a16 826 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 827 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 828 return 1;
829
830 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
831 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
832 return 1;
833 }
834
5e1746d6 835 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 836 return 1;
a03490ed 837
ad756a16
MJ		 838 if (((cr4 ^ old_cr4) & pdptr_bits) ||
839 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 840 kvm_mmu_reset_context(vcpu);
0f12244f 841
b9baba86 842 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 843 kvm_update_cpuid(vcpu);
2acf923e 844
0f12244f
GN		 845 return 0;
846}
2d3ad1f4 847EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 848
2390218b 849int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 850{
ac146235 851#ifdef CONFIG_X86_64
c19986fe
JS		 852 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
853
854 if (pcid_enabled)
855 cr3 &= ~CR3_PCID_INVD;
ac146235 856#endif
9d88fca7 857
9f8fe504 858 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 859 kvm_mmu_sync_roots(vcpu);
77c3913b 860 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 861 return 0;
d835dfec
AK		 862 }
863
d1cd3ce9 864 if (is_long_mode(vcpu) &&
a780a3ea 865 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 866 return 1;
867 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 868 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 869 return 1;
a03490ed 870
0f12244f 871 vcpu->arch.cr3 = cr3;
aff48baa 872 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 873 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 874 return 0;
875}
2d3ad1f4 876EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 877
eea1cff9 878int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 879{
0f12244f
GN		 880 if (cr8 & CR8_RESERVED_BITS)
881 return 1;
35754c98 882 if (lapic_in_kernel(vcpu))
a03490ed
CO		 883 kvm_lapic_set_tpr(vcpu, cr8);
884 else
ad312c7c 885 vcpu->arch.cr8 = cr8;
0f12244f
GN		 886 return 0;
887}
2d3ad1f4 888EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 889
2d3ad1f4 890unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 891{
35754c98 892 if (lapic_in_kernel(vcpu))
a03490ed
CO		 893 return kvm_lapic_get_cr8(vcpu);
894 else
ad312c7c 895 return vcpu->arch.cr8;
a03490ed 896}
2d3ad1f4 897EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 898
ae561ede
NA		 899static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
900{
901 int i;
902
903 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
904 for (i = 0; i < KVM_NR_DB_REGS; i++)
905 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
906 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
907 }
908}
909
73aaf249
JK		 910static void kvm_update_dr6(struct kvm_vcpu *vcpu)
911{
912 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
913 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
914}
915
c8639010
JK		 916static void kvm_update_dr7(struct kvm_vcpu *vcpu)
917{
918 unsigned long dr7;
919
920 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
921 dr7 = vcpu->arch.guest_debug_dr7;
922 else
923 dr7 = vcpu->arch.dr7;
924 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 925 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
926 if (dr7 & DR7_BP_EN_MASK)
927 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 928}
929
6f43ed01
NA		 930static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
931{
932 u64 fixed = DR6_FIXED_1;
933
d6321d49 934 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 935 fixed |= DR6_RTM;
936 return fixed;
937}
938
338dbc97 939static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 940{
941 switch (dr) {
942 case 0 ... 3:
943 vcpu->arch.db[dr] = val;
944 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
945 vcpu->arch.eff_db[dr] = val;
946 break;
947 case 4:
020df079
GN		 948 /* fall through */
949 case 6:
338dbc97
GN		 950 if (val & 0xffffffff00000000ULL)
951 return -1; /* #GP */
6f43ed01 952 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 953 kvm_update_dr6(vcpu);
020df079
GN		 954 break;
955 case 5:
020df079
GN		 956 /* fall through */
957 default: /* 7 */
338dbc97
GN		 958 if (val & 0xffffffff00000000ULL)
959 return -1; /* #GP */
020df079 960 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 961 kvm_update_dr7(vcpu);
020df079
GN		 962 break;
963 }
964
965 return 0;
966}
338dbc97
GN		 967
968int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
969{
16f8a6f9 970 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 971 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 972 return 1;
973 }
974 return 0;
338dbc97 975}
020df079
GN		 976EXPORT_SYMBOL_GPL(kvm_set_dr);
977
16f8a6f9 978int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 979{
980 switch (dr) {
981 case 0 ... 3:
982 *val = vcpu->arch.db[dr];
983 break;
984 case 4:
020df079
GN		 985 /* fall through */
986 case 6:
73aaf249
JK		 987 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
988 *val = vcpu->arch.dr6;
989 else
990 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 991 break;
992 case 5:
020df079
GN		 993 /* fall through */
994 default: /* 7 */
995 *val = vcpu->arch.dr7;
996 break;
997 }
338dbc97
GN		 998 return 0;
999}
020df079
GN		 1000EXPORT_SYMBOL_GPL(kvm_get_dr);
1001
022cd0e8
AK		 1002bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1003{
1004 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1005 u64 data;
1006 int err;
1007
c6702c9d 1008 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1009 if (err)
1010 return err;
1011 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1012 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1013 return err;
1014}
1015EXPORT_SYMBOL_GPL(kvm_rdpmc);
1016
043405e1
CO		 1017/*
1018 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1019 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1020 *
1021 * This list is modified at module load time to reflect the
e3267cbb 1022 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1023 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1024 * may depend on host virtualization features rather than host cpu features.
043405e1 1025 */
e3267cbb 1026
043405e1
CO		 1027static u32 msrs_to_save[] = {
1028 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1029 MSR_STAR,
043405e1
CO		 1030#ifdef CONFIG_X86_64
1031 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1032#endif
b3897a49 1033 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1034 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1035 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1036};
1037
1038static unsigned num_msrs_to_save;
1039
62ef68bb
PB		 1040static u32 emulated_msrs[] = {
1041 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1042 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1043 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1044 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1045 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1046 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1047 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1048 HV_X64_MSR_RESET,
11c4b1ca 1049 HV_X64_MSR_VP_INDEX,
9eec50b8 1050 HV_X64_MSR_VP_RUNTIME,
5c919412 1051 HV_X64_MSR_SCONTROL,
1f4b34f8 1052 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1053 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1054 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1055 HV_X64_MSR_TSC_EMULATION_STATUS,
1056
1057 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1058 MSR_KVM_PV_EOI_EN,
1059
ba904635 1060 MSR_IA32_TSC_ADJUST,
a3e06bbe 1061 MSR_IA32_TSCDEADLINE,
043405e1 1062 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1063 MSR_IA32_MCG_STATUS,
1064 MSR_IA32_MCG_CTL,
c45dcc71 1065 MSR_IA32_MCG_EXT_CTL,
64d60670 1066 MSR_IA32_SMBASE,
52797bf9 1067 MSR_SMI_COUNT,
db2336a8
KH		 1068 MSR_PLATFORM_INFO,
1069 MSR_MISC_FEATURES_ENABLES,
bc226f07 1070 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1071};
1072
62ef68bb
PB		 1073static unsigned num_emulated_msrs;
1074
801e459a
TL		 1075/*
1076 * List of msr numbers which are used to expose MSR-based features that
1077 * can be used by a hypervisor to validate requested CPU features.
1078 */
1079static u32 msr_based_features[] = {
1389309c
PB		 1080 MSR_IA32_VMX_BASIC,
1081 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1082 MSR_IA32_VMX_PINBASED_CTLS,
1083 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1084 MSR_IA32_VMX_PROCBASED_CTLS,
1085 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1086 MSR_IA32_VMX_EXIT_CTLS,
1087 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1088 MSR_IA32_VMX_ENTRY_CTLS,
1089 MSR_IA32_VMX_MISC,
1090 MSR_IA32_VMX_CR0_FIXED0,
1091 MSR_IA32_VMX_CR0_FIXED1,
1092 MSR_IA32_VMX_CR4_FIXED0,
1093 MSR_IA32_VMX_CR4_FIXED1,
1094 MSR_IA32_VMX_VMCS_ENUM,
1095 MSR_IA32_VMX_PROCBASED_CTLS2,
1096 MSR_IA32_VMX_EPT_VPID_CAP,
1097 MSR_IA32_VMX_VMFUNC,
1098
d1d93fa9 1099 MSR_F10H_DECFG,
518e7b94 1100 MSR_IA32_UCODE_REV,
cd283252 1101 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1102};
1103
1104static unsigned int num_msr_based_features;
1105
66421c1e
WL		 1106static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1107{
1108 switch (msr->index) {
518e7b94 1109 case MSR_IA32_UCODE_REV:
cd283252
PB		 1110 case MSR_IA32_ARCH_CAPABILITIES:
1111 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1112 break;
66421c1e
WL		 1113 default:
1114 if (kvm_x86_ops->get_msr_feature(msr))
1115 return 1;
1116 }
1117 return 0;
1118}
1119
801e459a
TL		 1120static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1121{
1122 struct kvm_msr_entry msr;
66421c1e 1123 int r;
801e459a
TL		 1124
1125 msr.index = index;
66421c1e
WL		 1126 r = kvm_get_msr_feature(&msr);
1127 if (r)
1128 return r;
801e459a
TL		 1129
1130 *data = msr.data;
1131
1132 return 0;
1133}
1134
384bb783 1135bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1136{
b69e8cae 1137 if (efer & efer_reserved_bits)
384bb783 1138 return false;
15c4a640 1139
1b4d56b8 1140 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1141 return false;
1b2fd70c 1142
1b4d56b8 1143 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1144 return false;
d8017474 1145
384bb783
JK		 1146 return true;
1147}
1148EXPORT_SYMBOL_GPL(kvm_valid_efer);
1149
1150static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1151{
1152 u64 old_efer = vcpu->arch.efer;
1153
1154 if (!kvm_valid_efer(vcpu, efer))
1155 return 1;
1156
1157 if (is_paging(vcpu)
1158 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1159 return 1;
1160
15c4a640 1161 efer &= ~EFER_LMA;
f6801dff 1162 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1163
a3d204e2
SY		 1164 kvm_x86_ops->set_efer(vcpu, efer);
1165
aad82703
SY		 1166 /* Update reserved bits */
1167 if ((efer ^ old_efer) & EFER_NX)
1168 kvm_mmu_reset_context(vcpu);
1169
b69e8cae 1170 return 0;
15c4a640
CO		 1171}
1172
f2b4b7dd
JR		 1173void kvm_enable_efer_bits(u64 mask)
1174{
1175 efer_reserved_bits &= ~mask;
1176}
1177EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1178
15c4a640
CO		 1179/*
1180 * Writes msr value into into the appropriate "register".
1181 * Returns 0 on success, non-0 otherwise.
1182 * Assumes vcpu_load() was already called.
1183 */
8fe8ab46 1184int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1185{
854e8bb1
NA		 1186 switch (msr->index) {
1187 case MSR_FS_BASE:
1188 case MSR_GS_BASE:
1189 case MSR_KERNEL_GS_BASE:
1190 case MSR_CSTAR:
1191 case MSR_LSTAR:
fd8cb433 1192 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1193 return 1;
1194 break;
1195 case MSR_IA32_SYSENTER_EIP:
1196 case MSR_IA32_SYSENTER_ESP:
1197 /*
1198 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1199 * non-canonical address is written on Intel but not on
1200 * AMD (which ignores the top 32-bits, because it does
1201 * not implement 64-bit SYSENTER).
1202 *
1203 * 64-bit code should hence be able to write a non-canonical
1204 * value on AMD. Making the address canonical ensures that
1205 * vmentry does not fail on Intel after writing a non-canonical
1206 * value, and that something deterministic happens if the guest
1207 * invokes 64-bit SYSENTER.
1208 */
fd8cb433 1209 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1210 }
8fe8ab46 1211 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1212}
854e8bb1 1213EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1214
313a3dc7
CO		 1215/*
1216 * Adapt set_msr() to msr_io()'s calling convention
1217 */
609e36d3
PB		 1218static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1219{
1220 struct msr_data msr;
1221 int r;
1222
1223 msr.index = index;
1224 msr.host_initiated = true;
1225 r = kvm_get_msr(vcpu, &msr);
1226 if (r)
1227 return r;
1228
1229 *data = msr.data;
1230 return 0;
1231}
1232
313a3dc7
CO		 1233static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1234{
8fe8ab46
WA		 1235 struct msr_data msr;
1236
1237 msr.data = *data;
1238 msr.index = index;
1239 msr.host_initiated = true;
1240 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1241}
1242
16e8d74d
MT		 1243#ifdef CONFIG_X86_64
1244struct pvclock_gtod_data {
1245 seqcount_t seq;
1246
1247 struct { /* extract of a clocksource struct */
1248 int vclock_mode;
a5a1d1c2
TG		 1249 u64 cycle_last;
1250 u64 mask;
16e8d74d
MT		 1251 u32 mult;
1252 u32 shift;
1253 } clock;
1254
cbcf2dd3
TG		 1255 u64 boot_ns;
1256 u64 nsec_base;
55dd00a7 1257 u64 wall_time_sec;
16e8d74d
MT		 1258};
1259
1260static struct pvclock_gtod_data pvclock_gtod_data;
1261
1262static void update_pvclock_gtod(struct timekeeper *tk)
1263{
1264 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1265 u64 boot_ns;
1266
876e7881 1267 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1268
1269 write_seqcount_begin(&vdata->seq);
1270
1271 /* copy pvclock gtod data */
876e7881
PZ		 1272 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1273 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1274 vdata->clock.mask = tk->tkr_mono.mask;
1275 vdata->clock.mult = tk->tkr_mono.mult;
1276 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1277
cbcf2dd3 1278 vdata->boot_ns = boot_ns;
876e7881 1279 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1280
55dd00a7
MT		 1281 vdata->wall_time_sec = tk->xtime_sec;
1282
16e8d74d
MT		 1283 write_seqcount_end(&vdata->seq);
1284}
1285#endif
1286
bab5bb39
NK		 1287void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1288{
1289 /*
1290 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1291 * vcpu_enter_guest. This function is only called from
1292 * the physical CPU that is running vcpu.
1293 */
1294 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1295}
16e8d74d 1296
18068523
GOC		 1297static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1298{
9ed3c444
AK		 1299 int version;
1300 int r;
50d0a0f9 1301 struct pvclock_wall_clock wc;
87aeb54f 1302 struct timespec64 boot;
18068523
GOC		 1303
1304 if (!wall_clock)
1305 return;
1306
9ed3c444
AK		 1307 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1308 if (r)
1309 return;
1310
1311 if (version & 1)
1312 ++version; /* first time write, random junk */
1313
1314 ++version;
18068523 1315
1dab1345
NK		 1316 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1317 return;
18068523 1318
50d0a0f9
GH		 1319 /*
1320 * The guest calculates current wall clock time by adding
34c238a1 1321 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1322 * wall clock specified here. guest system time equals host
1323 * system time for us, thus we must fill in host boot time here.
1324 */
87aeb54f 1325 getboottime64(&boot);
50d0a0f9 1326
4b648665 1327 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1328 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1329 boot = timespec64_sub(boot, ts);
4b648665 1330 }
87aeb54f 1331 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1332 wc.nsec = boot.tv_nsec;
1333 wc.version = version;
18068523
GOC		 1334
1335 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1336
1337 version++;
1338 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1339}
1340
50d0a0f9
GH		 1341static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1342{
b51012de
PB		 1343 do_shl32_div32(dividend, divisor);
1344 return dividend;
50d0a0f9
GH		 1345}
1346
3ae13faa 1347static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1348 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1349{
5f4e3f88 1350 uint64_t scaled64;
50d0a0f9
GH		 1351 int32_t shift = 0;
1352 uint64_t tps64;
1353 uint32_t tps32;
1354
3ae13faa
PB		 1355 tps64 = base_hz;
1356 scaled64 = scaled_hz;
50933623 1357 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1358 tps64 >>= 1;
1359 shift--;
1360 }
1361
1362 tps32 = (uint32_t)tps64;
50933623
JK		 1363 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1364 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1365 scaled64 >>= 1;
1366 else
1367 tps32 <<= 1;
50d0a0f9
GH		 1368 shift++;
1369 }
1370
5f4e3f88
ZA		 1371 *pshift = shift;
1372 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1373
3ae13faa
PB		 1374 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1375 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1376}
1377
d828199e 1378#ifdef CONFIG_X86_64
16e8d74d 1379static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1380#endif
16e8d74d 1381
c8076604 1382static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1383static unsigned long max_tsc_khz;
c8076604 1384
cc578287 1385static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1386{
cc578287
ZA		 1387 u64 v = (u64)khz * (1000000 + ppm);
1388 do_div(v, 1000000);
1389 return v;
1e993611
JR		 1390}
1391
381d585c
HZ		 1392static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1393{
1394 u64 ratio;
1395
1396 /* Guest TSC same frequency as host TSC? */
1397 if (!scale) {
1398 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1399 return 0;
1400 }
1401
1402 /* TSC scaling supported? */
1403 if (!kvm_has_tsc_control) {
1404 if (user_tsc_khz > tsc_khz) {
1405 vcpu->arch.tsc_catchup = 1;
1406 vcpu->arch.tsc_always_catchup = 1;
1407 return 0;
1408 } else {
1409 WARN(1, "user requested TSC rate below hardware speed\n");
1410 return -1;
1411 }
1412 }
1413
1414 /* TSC scaling required - calculate ratio */
1415 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1416 user_tsc_khz, tsc_khz);
1417
1418 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1419 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1420 user_tsc_khz);
1421 return -1;
1422 }
1423
1424 vcpu->arch.tsc_scaling_ratio = ratio;
1425 return 0;
1426}
1427
4941b8cb 1428static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1429{
cc578287
ZA		 1430 u32 thresh_lo, thresh_hi;
1431 int use_scaling = 0;
217fc9cf 1432
03ba32ca 1433 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1434 if (user_tsc_khz == 0) {
ad721883
HZ		 1435 /* set tsc_scaling_ratio to a safe value */
1436 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1437 return -1;
ad721883 1438 }
03ba32ca 1439
c285545f 1440 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1441 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1442 &vcpu->arch.virtual_tsc_shift,
1443 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1444 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1445
1446 /*
1447 * Compute the variation in TSC rate which is acceptable
1448 * within the range of tolerance and decide if the
1449 * rate being applied is within that bounds of the hardware
1450 * rate. If so, no scaling or compensation need be done.
1451 */
1452 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1453 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1454 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1455 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1456 use_scaling = 1;
1457 }
4941b8cb 1458 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1459}
1460
1461static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1462{
e26101b1 1463 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1464 vcpu->arch.virtual_tsc_mult,
1465 vcpu->arch.virtual_tsc_shift);
e26101b1 1466 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1467 return tsc;
1468}
1469
b0c39dc6
VK		 1470static inline int gtod_is_based_on_tsc(int mode)
1471{
1472 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1473}
1474
69b0049a 1475static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1476{
1477#ifdef CONFIG_X86_64
1478 bool vcpus_matched;
b48aa97e
MT		 1479 struct kvm_arch *ka = &vcpu->kvm->arch;
1480 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1481
1482 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1483 atomic_read(&vcpu->kvm->online_vcpus));
1484
7f187922
MT		 1485 /*
1486 * Once the masterclock is enabled, always perform request in
1487 * order to update it.
1488 *
1489 * In order to enable masterclock, the host clocksource must be TSC
1490 * and the vcpus need to have matched TSCs. When that happens,
1491 * perform request to enable masterclock.
1492 */
1493 if (ka->use_master_clock ||
b0c39dc6 1494 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1495 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1496
1497 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1498 atomic_read(&vcpu->kvm->online_vcpus),
1499 ka->use_master_clock, gtod->clock.vclock_mode);
1500#endif
1501}
1502
ba904635
WA		 1503static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1504{
e79f245d 1505 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1506 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1507}
1508
35181e86
HZ		 1509/*
1510 * Multiply tsc by a fixed point number represented by ratio.
1511 *
1512 * The most significant 64-N bits (mult) of ratio represent the
1513 * integral part of the fixed point number; the remaining N bits
1514 * (frac) represent the fractional part, ie. ratio represents a fixed
1515 * point number (mult + frac * 2^(-N)).
1516 *
1517 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1518 */
1519static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1520{
1521 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1522}
1523
1524u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1525{
1526 u64 _tsc = tsc;
1527 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1528
1529 if (ratio != kvm_default_tsc_scaling_ratio)
1530 _tsc = __scale_tsc(ratio, tsc);
1531
1532 return _tsc;
1533}
1534EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1535
07c1419a
HZ		 1536static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1537{
1538 u64 tsc;
1539
1540 tsc = kvm_scale_tsc(vcpu, rdtsc());
1541
1542 return target_tsc - tsc;
1543}
1544
4ba76538
HZ		 1545u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1546{
e79f245d
KA		 1547 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1548
1549 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1550}
1551EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1552
a545ab6a
LC		 1553static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1554{
1555 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1556 vcpu->arch.tsc_offset = offset;
1557}
1558
b0c39dc6
VK		 1559static inline bool kvm_check_tsc_unstable(void)
1560{
1561#ifdef CONFIG_X86_64
1562 /*
1563 * TSC is marked unstable when we're running on Hyper-V,
1564 * 'TSC page' clocksource is good.
1565 */
1566 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1567 return false;
1568#endif
1569 return check_tsc_unstable();
1570}
1571
8fe8ab46 1572void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1573{
1574 struct kvm *kvm = vcpu->kvm;
f38e098f 1575 u64 offset, ns, elapsed;
99e3e30a 1576 unsigned long flags;
b48aa97e 1577 bool matched;
0d3da0d2 1578 bool already_matched;
8fe8ab46 1579 u64 data = msr->data;
c5e8ec8e 1580 bool synchronizing = false;
99e3e30a 1581
038f8c11 1582 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1583 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1584 ns = ktime_get_boot_ns();
f38e098f 1585 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1586
03ba32ca 1587 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1588 if (data == 0 && msr->host_initiated) {
1589 /*
1590 * detection of vcpu initialization -- need to sync
1591 * with other vCPUs. This particularly helps to keep
1592 * kvm_clock stable after CPU hotplug
1593 */
1594 synchronizing = true;
1595 } else {
1596 u64 tsc_exp = kvm->arch.last_tsc_write +
1597 nsec_to_cycles(vcpu, elapsed);
1598 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1599 /*
1600 * Special case: TSC write with a small delta (1 second)
1601 * of virtual cycle time against real time is
1602 * interpreted as an attempt to synchronize the CPU.
1603 */
1604 synchronizing = data < tsc_exp + tsc_hz &&
1605 data + tsc_hz > tsc_exp;
1606 }
c5e8ec8e 1607 }
f38e098f
ZA		 1608
1609 /*
5d3cb0f6
ZA		 1610 * For a reliable TSC, we can match TSC offsets, and for an unstable
1611 * TSC, we add elapsed time in this computation. We could let the
1612 * compensation code attempt to catch up if we fall behind, but
1613 * it's better to try to match offsets from the beginning.
1614 */
c5e8ec8e 1615 if (synchronizing &&
5d3cb0f6 1616 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1617 if (!kvm_check_tsc_unstable()) {
e26101b1 1618 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1619 pr_debug("kvm: matched tsc offset for %llu\n", data);
1620 } else {
857e4099 1621 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1622 data += delta;
07c1419a 1623 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1624 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1625 }
b48aa97e 1626 matched = true;
0d3da0d2 1627 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1628 } else {
1629 /*
1630 * We split periods of matched TSC writes into generations.
1631 * For each generation, we track the original measured
1632 * nanosecond time, offset, and write, so if TSCs are in
1633 * sync, we can match exact offset, and if not, we can match
4a969980 1634 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1635 *
1636 * These values are tracked in kvm->arch.cur_xxx variables.
1637 */
1638 kvm->arch.cur_tsc_generation++;
1639 kvm->arch.cur_tsc_nsec = ns;
1640 kvm->arch.cur_tsc_write = data;
1641 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1642 matched = false;
0d3da0d2 1643 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1644 kvm->arch.cur_tsc_generation, data);
f38e098f 1645 }
e26101b1
ZA		 1646
1647 /*
1648 * We also track th most recent recorded KHZ, write and time to
1649 * allow the matching interval to be extended at each write.
1650 */
f38e098f
ZA		 1651 kvm->arch.last_tsc_nsec = ns;
1652 kvm->arch.last_tsc_write = data;
5d3cb0f6 1653 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1654
b183aa58 1655 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1656
1657 /* Keep track of which generation this VCPU has synchronized to */
1658 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1659 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1660 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1661
d6321d49 1662 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1663 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1664
a545ab6a 1665 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1666 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1667
1668 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1669 if (!matched) {
b48aa97e 1670 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1671 } else if (!already_matched) {
1672 kvm->arch.nr_vcpus_matched_tsc++;
1673 }
b48aa97e
MT		 1674
1675 kvm_track_tsc_matching(vcpu);
1676 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1677}
e26101b1 1678
99e3e30a
ZA		 1679EXPORT_SYMBOL_GPL(kvm_write_tsc);
1680
58ea6767
HZ		 1681static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1682 s64 adjustment)
1683{
ea26e4ec 1684 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1685}
1686
1687static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1688{
1689 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1690 WARN_ON(adjustment < 0);
1691 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1692 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1693}
1694
d828199e
MT		 1695#ifdef CONFIG_X86_64
1696
a5a1d1c2 1697static u64 read_tsc(void)
d828199e 1698{
a5a1d1c2 1699 u64 ret = (u64)rdtsc_ordered();
03b9730b 1700 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1701
1702 if (likely(ret >= last))
1703 return ret;
1704
1705 /*
1706 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1707 * predictable (it's just a function of time and the likely is
d828199e
MT		 1708 * very likely) and there's a data dependence, so force GCC
1709 * to generate a branch instead. I don't barrier() because
1710 * we don't actually need a barrier, and if this function
1711 * ever gets inlined it will generate worse code.
1712 */
1713 asm volatile ("");
1714 return last;
1715}
1716
b0c39dc6 1717static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1718{
1719 long v;
1720 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1721 u64 tsc_pg_val;
1722
1723 switch (gtod->clock.vclock_mode) {
1724 case VCLOCK_HVCLOCK:
1725 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1726 tsc_timestamp);
1727 if (tsc_pg_val != U64_MAX) {
1728 /* TSC page valid */
1729 *mode = VCLOCK_HVCLOCK;
1730 v = (tsc_pg_val - gtod->clock.cycle_last) &
1731 gtod->clock.mask;
1732 } else {
1733 /* TSC page invalid */
1734 *mode = VCLOCK_NONE;
1735 }
1736 break;
1737 case VCLOCK_TSC:
1738 *mode = VCLOCK_TSC;
1739 *tsc_timestamp = read_tsc();
1740 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1741 gtod->clock.mask;
1742 break;
1743 default:
1744 *mode = VCLOCK_NONE;
1745 }
d828199e 1746
b0c39dc6
VK		 1747 if (*mode == VCLOCK_NONE)
1748 *tsc_timestamp = v = 0;
d828199e 1749
d828199e
MT		 1750 return v * gtod->clock.mult;
1751}
1752
b0c39dc6 1753static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1754{
cbcf2dd3 1755 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1756 unsigned long seq;
d828199e 1757 int mode;
cbcf2dd3 1758 u64 ns;
d828199e 1759
d828199e
MT		 1760 do {
1761 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1762 ns = gtod->nsec_base;
b0c39dc6 1763 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1764 ns >>= gtod->clock.shift;
cbcf2dd3 1765 ns += gtod->boot_ns;
d828199e 1766 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1767 *t = ns;
d828199e
MT		 1768
1769 return mode;
1770}
1771
899a31f5 1772static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1773{
1774 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1775 unsigned long seq;
1776 int mode;
1777 u64 ns;
1778
1779 do {
1780 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1781 ts->tv_sec = gtod->wall_time_sec;
1782 ns = gtod->nsec_base;
b0c39dc6 1783 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1784 ns >>= gtod->clock.shift;
1785 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1786
1787 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1788 ts->tv_nsec = ns;
1789
1790 return mode;
1791}
1792
b0c39dc6
VK		 1793/* returns true if host is using TSC based clocksource */
1794static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1795{
d828199e 1796 /* checked again under seqlock below */
b0c39dc6 1797 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1798 return false;
1799
b0c39dc6
VK		 1800 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1801 tsc_timestamp));
d828199e 1802}
55dd00a7 1803
b0c39dc6 1804/* returns true if host is using TSC based clocksource */
899a31f5 1805static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1806 u64 *tsc_timestamp)
55dd00a7
MT		 1807{
1808 /* checked again under seqlock below */
b0c39dc6 1809 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1810 return false;
1811
b0c39dc6 1812 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1813}
d828199e
MT		 1814#endif
1815
1816/*
1817 *
b48aa97e
MT		 1818 * Assuming a stable TSC across physical CPUS, and a stable TSC
1819 * across virtual CPUs, the following condition is possible.
1820 * Each numbered line represents an event visible to both
d828199e
MT		 1821 * CPUs at the next numbered event.
1822 *
1823 * "timespecX" represents host monotonic time. "tscX" represents
1824 * RDTSC value.
1825 *
1826 * VCPU0 on CPU0 | VCPU1 on CPU1
1827 *
1828 * 1. read timespec0,tsc0
1829 * 2. | timespec1 = timespec0 + N
1830 * | tsc1 = tsc0 + M
1831 * 3. transition to guest | transition to guest
1832 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1833 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1834 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1835 *
1836 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1837 *
1838 * - ret0 < ret1
1839 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1840 * ...
1841 * - 0 < N - M => M < N
1842 *
1843 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1844 * always the case (the difference between two distinct xtime instances
1845 * might be smaller then the difference between corresponding TSC reads,
1846 * when updating guest vcpus pvclock areas).
1847 *
1848 * To avoid that problem, do not allow visibility of distinct
1849 * system_timestamp/tsc_timestamp values simultaneously: use a master
1850 * copy of host monotonic time values. Update that master copy
1851 * in lockstep.
1852 *
b48aa97e 1853 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1854 *
1855 */
1856
1857static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1858{
1859#ifdef CONFIG_X86_64
1860 struct kvm_arch *ka = &kvm->arch;
1861 int vclock_mode;
b48aa97e
MT		 1862 bool host_tsc_clocksource, vcpus_matched;
1863
1864 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1865 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1866
1867 /*
1868 * If the host uses TSC clock, then passthrough TSC as stable
1869 * to the guest.
1870 */
b48aa97e 1871 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1872 &ka->master_kernel_ns,
1873 &ka->master_cycle_now);
1874
16a96021 1875 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1876 && !ka->backwards_tsc_observed
54750f2c 1877 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1878
d828199e
MT		 1879 if (ka->use_master_clock)
1880 atomic_set(&kvm_guest_has_master_clock, 1);
1881
1882 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1883 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1884 vcpus_matched);
d828199e
MT		 1885#endif
1886}
1887
2860c4b1
PB		 1888void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1889{
1890 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1891}
1892
2e762ff7
MT		 1893static void kvm_gen_update_masterclock(struct kvm *kvm)
1894{
1895#ifdef CONFIG_X86_64
1896 int i;
1897 struct kvm_vcpu *vcpu;
1898 struct kvm_arch *ka = &kvm->arch;
1899
1900 spin_lock(&ka->pvclock_gtod_sync_lock);
1901 kvm_make_mclock_inprogress_request(kvm);
1902 /* no guest entries from this point */
1903 pvclock_update_vm_gtod_copy(kvm);
1904
1905 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1906 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1907
1908 /* guest entries allowed */
1909 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1910 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1911
1912 spin_unlock(&ka->pvclock_gtod_sync_lock);
1913#endif
1914}
1915
e891a32e 1916u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1917{
108b249c 1918 struct kvm_arch *ka = &kvm->arch;
8b953440 1919 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1920 u64 ret;
108b249c 1921
8b953440
PB		 1922 spin_lock(&ka->pvclock_gtod_sync_lock);
1923 if (!ka->use_master_clock) {
1924 spin_unlock(&ka->pvclock_gtod_sync_lock);
1925 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1926 }
1927
8b953440
PB		 1928 hv_clock.tsc_timestamp = ka->master_cycle_now;
1929 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1930 spin_unlock(&ka->pvclock_gtod_sync_lock);
1931
e2c2206a
WL		 1932 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1933 get_cpu();
1934
e70b57a6
WL		 1935 if (__this_cpu_read(cpu_tsc_khz)) {
1936 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1937 &hv_clock.tsc_shift,
1938 &hv_clock.tsc_to_system_mul);
1939 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1940 } else
1941 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1942
1943 put_cpu();
1944
1945 return ret;
108b249c
PB		 1946}
1947
0d6dd2ff
PB		 1948static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1949{
1950 struct kvm_vcpu_arch *vcpu = &v->arch;
1951 struct pvclock_vcpu_time_info guest_hv_clock;
1952
4e335d9e 1953 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1954 &guest_hv_clock, sizeof(guest_hv_clock))))
1955 return;
1956
1957 /* This VCPU is paused, but it's legal for a guest to read another
1958 * VCPU's kvmclock, so we really have to follow the specification where
1959 * it says that version is odd if data is being modified, and even after
1960 * it is consistent.
1961 *
1962 * Version field updates must be kept separate. This is because
1963 * kvm_write_guest_cached might use a "rep movs" instruction, and
1964 * writes within a string instruction are weakly ordered. So there
1965 * are three writes overall.
1966 *
1967 * As a small optimization, only write the version field in the first
1968 * and third write. The vcpu->pv_time cache is still valid, because the
1969 * version field is the first in the struct.
1970 */
1971 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1972
51c4b8bb
LA		 1973 if (guest_hv_clock.version & 1)
1974 ++guest_hv_clock.version; /* first time write, random junk */
1975
0d6dd2ff 1976 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1977 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1978 &vcpu->hv_clock,
1979 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1980
1981 smp_wmb();
1982
1983 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1984 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1985
1986 if (vcpu->pvclock_set_guest_stopped_request) {
1987 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1988 vcpu->pvclock_set_guest_stopped_request = false;
1989 }
1990
1991 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1992
4e335d9e
PB		 1993 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1994 &vcpu->hv_clock,
1995 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1996
1997 smp_wmb();
1998
1999 vcpu->hv_clock.version++;
4e335d9e
PB		 2000 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2001 &vcpu->hv_clock,
2002 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2003}
2004
34c238a1 2005static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2006{
78db6a50 2007 unsigned long flags, tgt_tsc_khz;
18068523 2008 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2009 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2010 s64 kernel_ns;
d828199e 2011 u64 tsc_timestamp, host_tsc;
51d59c6b 2012 u8 pvclock_flags;
d828199e
MT		 2013 bool use_master_clock;
2014
2015 kernel_ns = 0;
2016 host_tsc = 0;
18068523 2017
d828199e
MT		 2018 /*
2019 * If the host uses TSC clock, then passthrough TSC as stable
2020 * to the guest.
2021 */
2022 spin_lock(&ka->pvclock_gtod_sync_lock);
2023 use_master_clock = ka->use_master_clock;
2024 if (use_master_clock) {
2025 host_tsc = ka->master_cycle_now;
2026 kernel_ns = ka->master_kernel_ns;
2027 }
2028 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2029
2030 /* Keep irq disabled to prevent changes to the clock */
2031 local_irq_save(flags);
78db6a50
PB		 2032 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2033 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2034 local_irq_restore(flags);
2035 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2036 return 1;
2037 }
d828199e 2038 if (!use_master_clock) {
4ea1636b 2039 host_tsc = rdtsc();
108b249c 2040 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2041 }
2042
4ba76538 2043 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2044
c285545f
ZA		 2045 /*
2046 * We may have to catch up the TSC to match elapsed wall clock
2047 * time for two reasons, even if kvmclock is used.
2048 * 1) CPU could have been running below the maximum TSC rate
2049 * 2) Broken TSC compensation resets the base at each VCPU
2050 * entry to avoid unknown leaps of TSC even when running
2051 * again on the same CPU. This may cause apparent elapsed
2052 * time to disappear, and the guest to stand still or run
2053 * very slowly.
2054 */
2055 if (vcpu->tsc_catchup) {
2056 u64 tsc = compute_guest_tsc(v, kernel_ns);
2057 if (tsc > tsc_timestamp) {
f1e2b260 2058 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2059 tsc_timestamp = tsc;
2060 }
50d0a0f9
GH		 2061 }
2062
18068523
GOC		 2063 local_irq_restore(flags);
2064
0d6dd2ff 2065 /* With all the info we got, fill in the values */
18068523 2066
78db6a50
PB		 2067 if (kvm_has_tsc_control)
2068 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2069
2070 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2071 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2072 &vcpu->hv_clock.tsc_shift,
2073 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2074 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2075 }
2076
1d5f066e 2077 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2078 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2079 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2080
d828199e 2081 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2082 pvclock_flags = 0;
d828199e
MT		 2083 if (use_master_clock)
2084 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2085
78c0337a
MT		 2086 vcpu->hv_clock.flags = pvclock_flags;
2087
095cf55d
PB		 2088 if (vcpu->pv_time_enabled)
2089 kvm_setup_pvclock_page(v);
2090 if (v == kvm_get_vcpu(v->kvm, 0))
2091 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2092 return 0;
c8076604
GH		 2093}
2094
0061d53d
MT		 2095/*
2096 * kvmclock updates which are isolated to a given vcpu, such as
2097 * vcpu->cpu migration, should not allow system_timestamp from
2098 * the rest of the vcpus to remain static. Otherwise ntp frequency
2099 * correction applies to one vcpu's system_timestamp but not
2100 * the others.
2101 *
2102 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2103 * We need to rate-limit these requests though, as they can
2104 * considerably slow guests that have a large number of vcpus.
2105 * The time for a remote vcpu to update its kvmclock is bound
2106 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2107 */
2108
7e44e449
AJ		 2109#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2110
2111static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2112{
2113 int i;
7e44e449
AJ		 2114 struct delayed_work *dwork = to_delayed_work(work);
2115 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2116 kvmclock_update_work);
2117 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2118 struct kvm_vcpu *vcpu;
2119
2120 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2121 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2122 kvm_vcpu_kick(vcpu);
2123 }
2124}
2125
7e44e449
AJ		 2126static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2127{
2128 struct kvm *kvm = v->kvm;
2129
105b21bb 2130 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2131 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2132 KVMCLOCK_UPDATE_DELAY);
2133}
2134
332967a3
AJ		 2135#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2136
2137static void kvmclock_sync_fn(struct work_struct *work)
2138{
2139 struct delayed_work *dwork = to_delayed_work(work);
2140 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2141 kvmclock_sync_work);
2142 struct kvm *kvm = container_of(ka, struct kvm, arch);
2143
630994b3
MT		 2144 if (!kvmclock_periodic_sync)
2145 return;
2146
332967a3
AJ		 2147 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2148 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2149 KVMCLOCK_SYNC_PERIOD);
2150}
2151
9ffd986c 2152static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2153{
890ca9ae
HY		 2154 u64 mcg_cap = vcpu->arch.mcg_cap;
2155 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2156 u32 msr = msr_info->index;
2157 u64 data = msr_info->data;
890ca9ae 2158
15c4a640 2159 switch (msr) {
15c4a640 2160 case MSR_IA32_MCG_STATUS:
890ca9ae 2161 vcpu->arch.mcg_status = data;
15c4a640 2162 break;
c7ac679c 2163 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2164 if (!(mcg_cap & MCG_CTL_P))
2165 return 1;
2166 if (data != 0 && data != ~(u64)0)
2167 return -1;
2168 vcpu->arch.mcg_ctl = data;
2169 break;
2170 default:
2171 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2172 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2173 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2174 /* only 0 or all 1s can be written to IA32_MCi_CTL
2175 * some Linux kernels though clear bit 10 in bank 4 to
2176 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2177 * this to avoid an uncatched #GP in the guest
2178 */
890ca9ae 2179 if ((offset & 0x3) == 0 &&
114be429 2180 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2181 return -1;
9ffd986c
WL		 2182 if (!msr_info->host_initiated &&
2183 (offset & 0x3) == 1 && data != 0)
2184 return -1;
890ca9ae
HY		 2185 vcpu->arch.mce_banks[offset] = data;
2186 break;
2187 }
2188 return 1;
2189 }
2190 return 0;
2191}
2192
ffde22ac
ES		 2193static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2194{
2195 struct kvm *kvm = vcpu->kvm;
2196 int lm = is_long_mode(vcpu);
2197 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2198 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2199 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2200 : kvm->arch.xen_hvm_config.blob_size_32;
2201 u32 page_num = data & ~PAGE_MASK;
2202 u64 page_addr = data & PAGE_MASK;
2203 u8 *page;
2204 int r;
2205
2206 r = -E2BIG;
2207 if (page_num >= blob_size)
2208 goto out;
2209 r = -ENOMEM;
ff5c2c03
SL		 2210 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2211 if (IS_ERR(page)) {
2212 r = PTR_ERR(page);
ffde22ac 2213 goto out;
ff5c2c03 2214 }
54bf36aa 2215 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2216 goto out_free;
2217 r = 0;
2218out_free:
2219 kfree(page);
2220out:
2221 return r;
2222}
2223
344d9588
GN		 2224static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2225{
2226 gpa_t gpa = data & ~0x3f;
2227
52a5c155
WL		 2228 /* Bits 3:5 are reserved, Should be zero */
2229 if (data & 0x38)
344d9588
GN		 2230 return 1;
2231
2232 vcpu->arch.apf.msr_val = data;
2233
2234 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2235 kvm_clear_async_pf_completion_queue(vcpu);
2236 kvm_async_pf_hash_reset(vcpu);
2237 return 0;
2238 }
2239
4e335d9e 2240 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2241 sizeof(u32)))
344d9588
GN		 2242 return 1;
2243
6adba527 2244 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2245 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2246 kvm_async_pf_wakeup_all(vcpu);
2247 return 0;
2248}
2249
12f9a48f
GC		 2250static void kvmclock_reset(struct kvm_vcpu *vcpu)
2251{
0b79459b 2252 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2253}
2254
f38a7b75
WL		 2255static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2256{
2257 ++vcpu->stat.tlb_flush;
2258 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2259}
2260
c9aaa895
GC		 2261static void record_steal_time(struct kvm_vcpu *vcpu)
2262{
2263 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2264 return;
2265
4e335d9e 2266 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2267 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2268 return;
2269
f38a7b75
WL		 2270 /*
2271 * Doing a TLB flush here, on the guest's behalf, can avoid
2272 * expensive IPIs.
2273 */
2274 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2275 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2276
35f3fae1
WL		 2277 if (vcpu->arch.st.steal.version & 1)
2278 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2279
2280 vcpu->arch.st.steal.version += 1;
2281
4e335d9e 2282 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2283 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2284
2285 smp_wmb();
2286
c54cdf14
LC		 2287 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2288 vcpu->arch.st.last_steal;
2289 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2290
4e335d9e 2291 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2292 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2293
2294 smp_wmb();
2295
2296 vcpu->arch.st.steal.version += 1;
c9aaa895 2297
4e335d9e 2298 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2299 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2300}
2301
8fe8ab46 2302int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2303{
5753785f 2304 bool pr = false;
8fe8ab46
WA		 2305 u32 msr = msr_info->index;
2306 u64 data = msr_info->data;
5753785f 2307
15c4a640 2308 switch (msr) {
2e32b719 2309 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2310 case MSR_IA32_UCODE_WRITE:
2311 case MSR_VM_HSAVE_PA:
2312 case MSR_AMD64_PATCH_LOADER:
2313 case MSR_AMD64_BU_CFG2:
405a353a 2314 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2315 break;
2316
518e7b94
WL		 2317 case MSR_IA32_UCODE_REV:
2318 if (msr_info->host_initiated)
2319 vcpu->arch.microcode_version = data;
2320 break;
15c4a640 2321 case MSR_EFER:
b69e8cae 2322 return set_efer(vcpu, data);
8f1589d9
AP		 2323 case MSR_K7_HWCR:
2324 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2325 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2326 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2327 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2328 if (data != 0) {
a737f256
CD		 2329 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2330 data);
8f1589d9
AP		 2331 return 1;
2332 }
15c4a640 2333 break;
f7c6d140
AP		 2334 case MSR_FAM10H_MMIO_CONF_BASE:
2335 if (data != 0) {
a737f256
CD		 2336 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2337 "0x%llx\n", data);
f7c6d140
AP		 2338 return 1;
2339 }
15c4a640 2340 break;
b5e2fec0
AG		 2341 case MSR_IA32_DEBUGCTLMSR:
2342 if (!data) {
2343 /* We support the non-activated case already */
2344 break;
2345 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2346 /* Values other than LBR and BTF are vendor-specific,
2347 thus reserved and should throw a #GP */
2348 return 1;
2349 }
a737f256
CD		 2350 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2351 __func__, data);
b5e2fec0 2352 break;
9ba075a6 2353 case 0x200 ... 0x2ff:
ff53604b 2354 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2355 case MSR_IA32_APICBASE:
58cb628d 2356 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2357 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2358 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2359 case MSR_IA32_TSCDEADLINE:
2360 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2361 break;
ba904635 2362 case MSR_IA32_TSC_ADJUST:
d6321d49 2363 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2364 if (!msr_info->host_initiated) {
d913b904 2365 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2366 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2367 }
2368 vcpu->arch.ia32_tsc_adjust_msr = data;
2369 }
2370 break;
15c4a640 2371 case MSR_IA32_MISC_ENABLE:
ad312c7c 2372 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2373 break;
64d60670
PB		 2374 case MSR_IA32_SMBASE:
2375 if (!msr_info->host_initiated)
2376 return 1;
2377 vcpu->arch.smbase = data;
2378 break;
dd259935
PB		 2379 case MSR_IA32_TSC:
2380 kvm_write_tsc(vcpu, msr_info);
2381 break;
52797bf9
LA		 2382 case MSR_SMI_COUNT:
2383 if (!msr_info->host_initiated)
2384 return 1;
2385 vcpu->arch.smi_count = data;
2386 break;
11c6bffa 2387 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2388 case MSR_KVM_WALL_CLOCK:
2389 vcpu->kvm->arch.wall_clock = data;
2390 kvm_write_wall_clock(vcpu->kvm, data);
2391 break;
11c6bffa 2392 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2393 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2394 struct kvm_arch *ka = &vcpu->kvm->arch;
2395
12f9a48f 2396 kvmclock_reset(vcpu);
18068523 2397
54750f2c
MT		 2398 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2399 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2400
2401 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2402 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2403
2404 ka->boot_vcpu_runs_old_kvmclock = tmp;
2405 }
2406
18068523 2407 vcpu->arch.time = data;
0061d53d 2408 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2409
2410 /* we verify if the enable bit is set... */
2411 if (!(data & 1))
2412 break;
2413
4e335d9e 2414 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2415 &vcpu->arch.pv_time, data & ~1ULL,
2416 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2417 vcpu->arch.pv_time_enabled = false;
2418 else
2419 vcpu->arch.pv_time_enabled = true;
32cad84f 2420
18068523
GOC		 2421 break;
2422 }
344d9588
GN		 2423 case MSR_KVM_ASYNC_PF_EN:
2424 if (kvm_pv_enable_async_pf(vcpu, data))
2425 return 1;
2426 break;
c9aaa895
GC		 2427 case MSR_KVM_STEAL_TIME:
2428
2429 if (unlikely(!sched_info_on()))
2430 return 1;
2431
2432 if (data & KVM_STEAL_RESERVED_MASK)
2433 return 1;
2434
4e335d9e 2435 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2436 data & KVM_STEAL_VALID_BITS,
2437 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2438 return 1;
2439
2440 vcpu->arch.st.msr_val = data;
2441
2442 if (!(data & KVM_MSR_ENABLED))
2443 break;
2444
c9aaa895
GC		 2445 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2446
2447 break;
ae7a2a3f
MT		 2448 case MSR_KVM_PV_EOI_EN:
2449 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2450 return 1;
2451 break;
c9aaa895 2452
890ca9ae
HY		 2453 case MSR_IA32_MCG_CTL:
2454 case MSR_IA32_MCG_STATUS:
81760dcc 2455 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2456 return set_msr_mce(vcpu, msr_info);
71db6023 2457
6912ac32
WH		 2458 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2459 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2460 pr = true; /* fall through */
2461 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2462 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2463 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2464 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2465
2466 if (pr || data != 0)
a737f256
CD		 2467 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2468 "0x%x data 0x%llx\n", msr, data);
5753785f 2469 break;
84e0cefa
JS		 2470 case MSR_K7_CLK_CTL:
2471 /*
2472 * Ignore all writes to this no longer documented MSR.
2473 * Writes are only relevant for old K7 processors,
2474 * all pre-dating SVM, but a recommended workaround from
4a969980 2475 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2476 * affected processor models on the command line, hence
2477 * the need to ignore the workaround.
2478 */
2479 break;
55cd8e5a 2480 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2481 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2482 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2483 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2484 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2485 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2486 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2487 return kvm_hv_set_msr_common(vcpu, msr, data,
2488 msr_info->host_initiated);
91c9c3ed 2489 case MSR_IA32_BBL_CR_CTL3:
2490 /* Drop writes to this legacy MSR -- see rdmsr
2491 * counterpart for further detail.
2492 */
fab0aa3b
EM		 2493 if (report_ignored_msrs)
2494 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2495 msr, data);
91c9c3ed 2496 break;
2b036c6b 2497 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2498 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2499 return 1;
2500 vcpu->arch.osvw.length = data;
2501 break;
2502 case MSR_AMD64_OSVW_STATUS:
d6321d49 2503 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2504 return 1;
2505 vcpu->arch.osvw.status = data;
2506 break;
db2336a8
KH		 2507 case MSR_PLATFORM_INFO:
2508 if (!msr_info->host_initiated ||
2509 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2510 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2511 cpuid_fault_enabled(vcpu)))
2512 return 1;
2513 vcpu->arch.msr_platform_info = data;
2514 break;
2515 case MSR_MISC_FEATURES_ENABLES:
2516 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2517 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2518 !supports_cpuid_fault(vcpu)))
2519 return 1;
2520 vcpu->arch.msr_misc_features_enables = data;
2521 break;
15c4a640 2522 default:
ffde22ac
ES		 2523 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2524 return xen_hvm_config(vcpu, data);
c6702c9d 2525 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2526 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2527 if (!ignore_msrs) {
ae0f5499 2528 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2529 msr, data);
ed85c068
AP		 2530 return 1;
2531 } else {
fab0aa3b
EM		 2532 if (report_ignored_msrs)
2533 vcpu_unimpl(vcpu,
2534 "ignored wrmsr: 0x%x data 0x%llx\n",
2535 msr, data);
ed85c068
AP		 2536 break;
2537 }
15c4a640
CO		 2538 }
2539 return 0;
2540}
2541EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2542
2543
2544/*
2545 * Reads an msr value (of 'msr_index') into 'pdata'.
2546 * Returns 0 on success, non-0 otherwise.
2547 * Assumes vcpu_load() was already called.
2548 */
609e36d3 2549int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2550{
609e36d3 2551 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2552}
ff651cb6 2553EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2554
890ca9ae 2555static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2556{
2557 u64 data;
890ca9ae
HY		 2558 u64 mcg_cap = vcpu->arch.mcg_cap;
2559 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2560
2561 switch (msr) {
15c4a640
CO		 2562 case MSR_IA32_P5_MC_ADDR:
2563 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2564 data = 0;
2565 break;
15c4a640 2566 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2567 data = vcpu->arch.mcg_cap;
2568 break;
c7ac679c 2569 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2570 if (!(mcg_cap & MCG_CTL_P))
2571 return 1;
2572 data = vcpu->arch.mcg_ctl;
2573 break;
2574 case MSR_IA32_MCG_STATUS:
2575 data = vcpu->arch.mcg_status;
2576 break;
2577 default:
2578 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2579 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2580 u32 offset = msr - MSR_IA32_MC0_CTL;
2581 data = vcpu->arch.mce_banks[offset];
2582 break;
2583 }
2584 return 1;
2585 }
2586 *pdata = data;
2587 return 0;
2588}
2589
609e36d3 2590int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2591{
609e36d3 2592 switch (msr_info->index) {
890ca9ae 2593 case MSR_IA32_PLATFORM_ID:
15c4a640 2594 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2595 case MSR_IA32_DEBUGCTLMSR:
2596 case MSR_IA32_LASTBRANCHFROMIP:
2597 case MSR_IA32_LASTBRANCHTOIP:
2598 case MSR_IA32_LASTINTFROMIP:
2599 case MSR_IA32_LASTINTTOIP:
60af2ecd 2600 case MSR_K8_SYSCFG:
3afb1121
PB		 2601 case MSR_K8_TSEG_ADDR:
2602 case MSR_K8_TSEG_MASK:
60af2ecd 2603 case MSR_K7_HWCR:
61a6bd67 2604 case MSR_VM_HSAVE_PA:
1fdbd48c 2605 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2606 case MSR_AMD64_NB_CFG:
f7c6d140 2607 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2608 case MSR_AMD64_BU_CFG2:
0c2df2a1 2609 case MSR_IA32_PERF_CTL:
405a353a 2610 case MSR_AMD64_DC_CFG:
609e36d3 2611 msr_info->data = 0;
15c4a640 2612 break;
c51eb52b 2613 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2614 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2615 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2616 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2617 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2618 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2619 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2620 msr_info->data = 0;
5753785f 2621 break;
742bc670 2622 case MSR_IA32_UCODE_REV:
518e7b94 2623 msr_info->data = vcpu->arch.microcode_version;
742bc670 2624 break;
dd259935
PB		 2625 case MSR_IA32_TSC:
2626 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2627 break;
9ba075a6 2628 case MSR_MTRRcap:
9ba075a6 2629 case 0x200 ... 0x2ff:
ff53604b 2630 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2631 case 0xcd: /* fsb frequency */
609e36d3 2632 msr_info->data = 3;
15c4a640 2633 break;
7b914098
JS		 2634 /*
2635 * MSR_EBC_FREQUENCY_ID
2636 * Conservative value valid for even the basic CPU models.
2637 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2638 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2639 * and 266MHz for model 3, or 4. Set Core Clock
2640 * Frequency to System Bus Frequency Ratio to 1 (bits
2641 * 31:24) even though these are only valid for CPU
2642 * models > 2, however guests may end up dividing or
2643 * multiplying by zero otherwise.
2644 */
2645 case MSR_EBC_FREQUENCY_ID:
609e36d3 2646 msr_info->data = 1 << 24;
7b914098 2647 break;
15c4a640 2648 case MSR_IA32_APICBASE:
609e36d3 2649 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2650 break;
0105d1a5 2651 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2652 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2653 break;
a3e06bbe 2654 case MSR_IA32_TSCDEADLINE:
609e36d3 2655 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2656 break;
ba904635 2657 case MSR_IA32_TSC_ADJUST:
609e36d3 2658 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2659 break;
15c4a640 2660 case MSR_IA32_MISC_ENABLE:
609e36d3 2661 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2662 break;
64d60670
PB		 2663 case MSR_IA32_SMBASE:
2664 if (!msr_info->host_initiated)
2665 return 1;
2666 msr_info->data = vcpu->arch.smbase;
15c4a640 2667 break;
52797bf9
LA		 2668 case MSR_SMI_COUNT:
2669 msr_info->data = vcpu->arch.smi_count;
2670 break;
847f0ad8
AG		 2671 case MSR_IA32_PERF_STATUS:
2672 /* TSC increment by tick */
609e36d3 2673 msr_info->data = 1000ULL;
847f0ad8 2674 /* CPU multiplier */
b0996ae4 2675 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2676 break;
15c4a640 2677 case MSR_EFER:
609e36d3 2678 msr_info->data = vcpu->arch.efer;
15c4a640 2679 break;
18068523 2680 case MSR_KVM_WALL_CLOCK:
11c6bffa 2681 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2682 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2683 break;
2684 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2685 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2686 msr_info->data = vcpu->arch.time;
18068523 2687 break;
344d9588 2688 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2689 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2690 break;
c9aaa895 2691 case MSR_KVM_STEAL_TIME:
609e36d3 2692 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2693 break;
1d92128f 2694 case MSR_KVM_PV_EOI_EN:
609e36d3 2695 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2696 break;
890ca9ae
HY		 2697 case MSR_IA32_P5_MC_ADDR:
2698 case MSR_IA32_P5_MC_TYPE:
2699 case MSR_IA32_MCG_CAP:
2700 case MSR_IA32_MCG_CTL:
2701 case MSR_IA32_MCG_STATUS:
81760dcc 2702 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2703 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2704 case MSR_K7_CLK_CTL:
2705 /*
2706 * Provide expected ramp-up count for K7. All other
2707 * are set to zero, indicating minimum divisors for
2708 * every field.
2709 *
2710 * This prevents guest kernels on AMD host with CPU
2711 * type 6, model 8 and higher from exploding due to
2712 * the rdmsr failing.
2713 */
609e36d3 2714 msr_info->data = 0x20000000;
84e0cefa 2715 break;
55cd8e5a 2716 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2717 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2718 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2719 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2720 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2721 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2722 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887
AS		 2723 return kvm_hv_get_msr_common(vcpu,
2724 msr_info->index, &msr_info->data);
55cd8e5a 2725 break;
91c9c3ed 2726 case MSR_IA32_BBL_CR_CTL3:
2727 /* This legacy MSR exists but isn't fully documented in current
2728 * silicon. It is however accessed by winxp in very narrow
2729 * scenarios where it sets bit #19, itself documented as
2730 * a "reserved" bit. Best effort attempt to source coherent
2731 * read data here should the balance of the register be
2732 * interpreted by the guest:
2733 *
2734 * L2 cache control register 3: 64GB range, 256KB size,
2735 * enabled, latency 0x1, configured
2736 */
609e36d3 2737 msr_info->data = 0xbe702111;
91c9c3ed 2738 break;
2b036c6b 2739 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2740 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2741 return 1;
609e36d3 2742 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2743 break;
2744 case MSR_AMD64_OSVW_STATUS:
d6321d49 2745 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2746 return 1;
609e36d3 2747 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2748 break;
db2336a8
KH		 2749 case MSR_PLATFORM_INFO:
2750 msr_info->data = vcpu->arch.msr_platform_info;
2751 break;
2752 case MSR_MISC_FEATURES_ENABLES:
2753 msr_info->data = vcpu->arch.msr_misc_features_enables;
2754 break;
15c4a640 2755 default:
c6702c9d 2756 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2757 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2758 if (!ignore_msrs) {
ae0f5499
BD		 2759 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2760 msr_info->index);
ed85c068
AP		 2761 return 1;
2762 } else {
fab0aa3b
EM		 2763 if (report_ignored_msrs)
2764 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2765 msr_info->index);
609e36d3 2766 msr_info->data = 0;
ed85c068
AP		 2767 }
2768 break;
15c4a640 2769 }
15c4a640
CO		 2770 return 0;
2771}
2772EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2773
313a3dc7
CO		 2774/*
2775 * Read or write a bunch of msrs. All parameters are kernel addresses.
2776 *
2777 * @return number of msrs set successfully.
2778 */
2779static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2780 struct kvm_msr_entry *entries,
2781 int (*do_msr)(struct kvm_vcpu *vcpu,
2782 unsigned index, u64 *data))
2783{
801e459a 2784 int i;
313a3dc7 2785
313a3dc7
CO		 2786 for (i = 0; i < msrs->nmsrs; ++i)
2787 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2788 break;
2789
313a3dc7
CO		 2790 return i;
2791}
2792
2793/*
2794 * Read or write a bunch of msrs. Parameters are user addresses.
2795 *
2796 * @return number of msrs set successfully.
2797 */
2798static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2799 int (*do_msr)(struct kvm_vcpu *vcpu,
2800 unsigned index, u64 *data),
2801 int writeback)
2802{
2803 struct kvm_msrs msrs;
2804 struct kvm_msr_entry *entries;
2805 int r, n;
2806 unsigned size;
2807
2808 r = -EFAULT;
2809 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2810 goto out;
2811
2812 r = -E2BIG;
2813 if (msrs.nmsrs >= MAX_IO_MSRS)
2814 goto out;
2815
313a3dc7 2816 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2817 entries = memdup_user(user_msrs->entries, size);
2818 if (IS_ERR(entries)) {
2819 r = PTR_ERR(entries);
313a3dc7 2820 goto out;
ff5c2c03 2821 }
313a3dc7
CO		 2822
2823 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2824 if (r < 0)
2825 goto out_free;
2826
2827 r = -EFAULT;
2828 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2829 goto out_free;
2830
2831 r = n;
2832
2833out_free:
7a73c028 2834 kfree(entries);
313a3dc7
CO		 2835out:
2836 return r;
2837}
2838
4d5422ce
WL		 2839static inline bool kvm_can_mwait_in_guest(void)
2840{
2841 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2842 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2843 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2844}
2845
784aa3d7 2846int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2847{
4d5422ce 2848 int r = 0;
018d00d2
ZX		 2849
2850 switch (ext) {
2851 case KVM_CAP_IRQCHIP:
2852 case KVM_CAP_HLT:
2853 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2854 case KVM_CAP_SET_TSS_ADDR:
07716717 2855 case KVM_CAP_EXT_CPUID:
9c15bb1d 2856 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2857 case KVM_CAP_CLOCKSOURCE:
7837699f 2858 case KVM_CAP_PIT:
a28e4f5a 2859 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2860 case KVM_CAP_MP_STATE:
ed848624 2861 case KVM_CAP_SYNC_MMU:
a355c85c 2862 case KVM_CAP_USER_NMI:
52d939a0 2863 case KVM_CAP_REINJECT_CONTROL:
4925663a 2864 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2865 case KVM_CAP_IOEVENTFD:
f848a5a8 2866 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2867 case KVM_CAP_PIT2:
e9f42757 2868 case KVM_CAP_PIT_STATE2:
b927a3ce 2869 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2870 case KVM_CAP_XEN_HVM:
3cfc3092 2871 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2872 case KVM_CAP_HYPERV:
10388a07 2873 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2874 case KVM_CAP_HYPERV_SPIN:
5c919412 2875 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2876 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2877 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2878 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 2879 case KVM_CAP_HYPERV_TLBFLUSH:
ab9f4ecb 2880 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2881 case KVM_CAP_DEBUGREGS:
d2be1651 2882 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2883 case KVM_CAP_XSAVE:
344d9588 2884 case KVM_CAP_ASYNC_PF:
92a1f12d 2885 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2886 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2887 case KVM_CAP_READONLY_MEM:
5f66b620 2888 case KVM_CAP_HYPERV_TIME:
100943c5 2889 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2890 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2891 case KVM_CAP_ENABLE_CAP_VM:
2892 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2893 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2894 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2895 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2896 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2897 r = 1;
2898 break;
01643c51
KH		 2899 case KVM_CAP_SYNC_REGS:
2900 r = KVM_SYNC_X86_VALID_FIELDS;
2901 break;
e3fd9a93
PB		 2902 case KVM_CAP_ADJUST_CLOCK:
2903 r = KVM_CLOCK_TSC_STABLE;
2904 break;
4d5422ce 2905 case KVM_CAP_X86_DISABLE_EXITS:
766d3571 2906 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 2907 if(kvm_can_mwait_in_guest())
2908 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 2909 break;
6d396b55
PB		 2910 case KVM_CAP_X86_SMM:
2911 /* SMBASE is usually relocated above 1M on modern chipsets,
2912 * and SMM handlers might indeed rely on 4G segment limits,
2913 * so do not report SMM to be available if real mode is
2914 * emulated via vm86 mode. Still, do not go to great lengths
2915 * to avoid userspace's usage of the feature, because it is a
2916 * fringe case that is not enabled except via specific settings
2917 * of the module parameters.
2918 */
bc226f07 2919 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 2920 break;
774ead3a
AK		 2921 case KVM_CAP_VAPIC:
2922 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2923 break;
f725230a 2924 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2925 r = KVM_SOFT_MAX_VCPUS;
2926 break;
2927 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2928 r = KVM_MAX_VCPUS;
2929 break;
a988b910 2930 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2931 r = KVM_USER_MEM_SLOTS;
a988b910 2932 break;
a68a6a72
MT		 2933 case KVM_CAP_PV_MMU: /* obsolete */
2934 r = 0;
2f333bcb 2935 break;
890ca9ae
HY		 2936 case KVM_CAP_MCE:
2937 r = KVM_MAX_MCE_BANKS;
2938 break;
2d5b5a66 2939 case KVM_CAP_XCRS:
d366bf7e 2940 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2941 break;
92a1f12d
JR		 2942 case KVM_CAP_TSC_CONTROL:
2943 r = kvm_has_tsc_control;
2944 break;
37131313
RK		 2945 case KVM_CAP_X2APIC_API:
2946 r = KVM_X2APIC_API_VALID_FLAGS;
2947 break;
018d00d2 2948 default:
018d00d2
ZX		 2949 break;
2950 }
2951 return r;
2952
2953}
2954
043405e1
CO		 2955long kvm_arch_dev_ioctl(struct file *filp,
2956 unsigned int ioctl, unsigned long arg)
2957{
2958 void __user *argp = (void __user *)arg;
2959 long r;
2960
2961 switch (ioctl) {
2962 case KVM_GET_MSR_INDEX_LIST: {
2963 struct kvm_msr_list __user *user_msr_list = argp;
2964 struct kvm_msr_list msr_list;
2965 unsigned n;
2966
2967 r = -EFAULT;
2968 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2969 goto out;
2970 n = msr_list.nmsrs;
62ef68bb 2971 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2972 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2973 goto out;
2974 r = -E2BIG;
e125e7b6 2975 if (n < msr_list.nmsrs)
043405e1
CO		 2976 goto out;
2977 r = -EFAULT;
2978 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2979 num_msrs_to_save * sizeof(u32)))
2980 goto out;
e125e7b6 2981 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2982 &emulated_msrs,
62ef68bb 2983 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2984 goto out;
2985 r = 0;
2986 break;
2987 }
9c15bb1d
BP		 2988 case KVM_GET_SUPPORTED_CPUID:
2989 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2990 struct kvm_cpuid2 __user *cpuid_arg = argp;
2991 struct kvm_cpuid2 cpuid;
2992
2993 r = -EFAULT;
2994 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2995 goto out;
9c15bb1d
BP		 2996
2997 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2998 ioctl);
674eea0f
AK		 2999 if (r)
3000 goto out;
3001
3002 r = -EFAULT;
3003 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3004 goto out;
3005 r = 0;
3006 break;
3007 }
890ca9ae 3008 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3009 r = -EFAULT;
c45dcc71
AR		 3010 if (copy_to_user(argp, &kvm_mce_cap_supported,
3011 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3012 goto out;
3013 r = 0;
3014 break;
801e459a
TL		 3015 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3016 struct kvm_msr_list __user *user_msr_list = argp;
3017 struct kvm_msr_list msr_list;
3018 unsigned int n;
3019
3020 r = -EFAULT;
3021 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3022 goto out;
3023 n = msr_list.nmsrs;
3024 msr_list.nmsrs = num_msr_based_features;
3025 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3026 goto out;
3027 r = -E2BIG;
3028 if (n < msr_list.nmsrs)
3029 goto out;
3030 r = -EFAULT;
3031 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3032 num_msr_based_features * sizeof(u32)))
3033 goto out;
3034 r = 0;
3035 break;
3036 }
3037 case KVM_GET_MSRS:
3038 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3039 break;
890ca9ae 3040 }
043405e1
CO		 3041 default:
3042 r = -EINVAL;
3043 }
3044out:
3045 return r;
3046}
3047
f5f48ee1
SY		 3048static void wbinvd_ipi(void *garbage)
3049{
3050 wbinvd();
3051}
3052
3053static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3054{
e0f0bbc5 3055 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3056}
3057
313a3dc7
CO		 3058void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3059{
f5f48ee1
SY		 3060 /* Address WBINVD may be executed by guest */
3061 if (need_emulate_wbinvd(vcpu)) {
3062 if (kvm_x86_ops->has_wbinvd_exit())
3063 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3064 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3065 smp_call_function_single(vcpu->cpu,
3066 wbinvd_ipi, NULL, 1);
3067 }
3068
313a3dc7 3069 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3070
0dd6a6ed
ZA		 3071 /* Apply any externally detected TSC adjustments (due to suspend) */
3072 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3073 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3074 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3075 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3076 }
8f6055cb 3077
b0c39dc6 3078 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3079 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3080 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3081 if (tsc_delta < 0)
3082 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3083
b0c39dc6 3084 if (kvm_check_tsc_unstable()) {
07c1419a 3085 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3086 vcpu->arch.last_guest_tsc);
a545ab6a 3087 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3088 vcpu->arch.tsc_catchup = 1;
c285545f 3089 }
a749e247
PB		 3090
3091 if (kvm_lapic_hv_timer_in_use(vcpu))
3092 kvm_lapic_restart_hv_timer(vcpu);
3093
d98d07ca
MT		 3094 /*
3095 * On a host with synchronized TSC, there is no need to update
3096 * kvmclock on vcpu->cpu migration
3097 */
3098 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3099 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3100 if (vcpu->cpu != cpu)
1bd2009e 3101 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3102 vcpu->cpu = cpu;
6b7d7e76 3103 }
c9aaa895 3104
c9aaa895 3105 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3106}
3107
0b9f6c46
PX		 3108static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3109{
3110 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3111 return;
3112
fa55eedd 3113 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3114
4e335d9e 3115 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3116 &vcpu->arch.st.steal.preempted,
3117 offsetof(struct kvm_steal_time, preempted),
3118 sizeof(vcpu->arch.st.steal.preempted));
3119}
3120
313a3dc7
CO		 3121void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3122{
cc0d907c 3123 int idx;
de63ad4c
LM		 3124
3125 if (vcpu->preempted)
3126 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3127
931f261b
AA		 3128 /*
3129 * Disable page faults because we're in atomic context here.
3130 * kvm_write_guest_offset_cached() would call might_fault()
3131 * that relies on pagefault_disable() to tell if there's a
3132 * bug. NOTE: the write to guest memory may not go through if
3133 * during postcopy live migration or if there's heavy guest
3134 * paging.
3135 */
3136 pagefault_disable();
cc0d907c
AA		 3137 /*
3138 * kvm_memslots() will be called by
3139 * kvm_write_guest_offset_cached() so take the srcu lock.
3140 */
3141 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3142 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3143 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3144 pagefault_enable();
02daab21 3145 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3146 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3147 /*
3148 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3149 * on every vmexit, but if not, we might have a stale dr6 from the
3150 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3151 */
3152 set_debugreg(0, 6);
313a3dc7
CO		 3153}
3154
313a3dc7
CO		 3155static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3156 struct kvm_lapic_state *s)
3157{
fa59cc00 3158 if (vcpu->arch.apicv_active)
d62caabb
AS		 3159 kvm_x86_ops->sync_pir_to_irr(vcpu);
3160
a92e2543 3161 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3162}
3163
3164static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3165 struct kvm_lapic_state *s)
3166{
a92e2543
RK		 3167 int r;
3168
3169 r = kvm_apic_set_state(vcpu, s);
3170 if (r)
3171 return r;
cb142eb7 3172 update_cr8_intercept(vcpu);
313a3dc7
CO		 3173
3174 return 0;
3175}
3176
127a457a
MG		 3177static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3178{
3179 return (!lapic_in_kernel(vcpu) ||
3180 kvm_apic_accept_pic_intr(vcpu));
3181}
3182
782d422b
MG		 3183/*
3184 * if userspace requested an interrupt window, check that the
3185 * interrupt window is open.
3186 *
3187 * No need to exit to userspace if we already have an interrupt queued.
3188 */
3189static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3190{
3191 return kvm_arch_interrupt_allowed(vcpu) &&
3192 !kvm_cpu_has_interrupt(vcpu) &&
3193 !kvm_event_needs_reinjection(vcpu) &&
3194 kvm_cpu_accept_dm_intr(vcpu);
3195}
3196
f77bc6a4
ZX		 3197static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3198 struct kvm_interrupt *irq)
3199{
02cdb50f 3200 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3201 return -EINVAL;
1c1a9ce9
SR		 3202
3203 if (!irqchip_in_kernel(vcpu->kvm)) {
3204 kvm_queue_interrupt(vcpu, irq->irq, false);
3205 kvm_make_request(KVM_REQ_EVENT, vcpu);
3206 return 0;
3207 }
3208
3209 /*
3210 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3211 * fail for in-kernel 8259.
3212 */
3213 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3214 return -ENXIO;
f77bc6a4 3215
1c1a9ce9
SR		 3216 if (vcpu->arch.pending_external_vector != -1)
3217 return -EEXIST;
f77bc6a4 3218
1c1a9ce9 3219 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3220 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3221 return 0;
3222}
3223
c4abb7c9
JK		 3224static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3225{
c4abb7c9 3226 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3227
3228 return 0;
3229}
3230
f077825a
PB		 3231static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3232{
64d60670
PB		 3233 kvm_make_request(KVM_REQ_SMI, vcpu);
3234
f077825a
PB		 3235 return 0;
3236}
3237
b209749f
AK		 3238static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3239 struct kvm_tpr_access_ctl *tac)
3240{
3241 if (tac->flags)
3242 return -EINVAL;
3243 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3244 return 0;
3245}
3246
890ca9ae
HY		 3247static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3248 u64 mcg_cap)
3249{
3250 int r;
3251 unsigned bank_num = mcg_cap & 0xff, bank;
3252
3253 r = -EINVAL;
a9e38c3e 3254 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3255 goto out;
c45dcc71 3256 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3257 goto out;
3258 r = 0;
3259 vcpu->arch.mcg_cap = mcg_cap;
3260 /* Init IA32_MCG_CTL to all 1s */
3261 if (mcg_cap & MCG_CTL_P)
3262 vcpu->arch.mcg_ctl = ~(u64)0;
3263 /* Init IA32_MCi_CTL to all 1s */
3264 for (bank = 0; bank < bank_num; bank++)
3265 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3266
3267 if (kvm_x86_ops->setup_mce)
3268 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3269out:
3270 return r;
3271}
3272
3273static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3274 struct kvm_x86_mce *mce)
3275{
3276 u64 mcg_cap = vcpu->arch.mcg_cap;
3277 unsigned bank_num = mcg_cap & 0xff;
3278 u64 *banks = vcpu->arch.mce_banks;
3279
3280 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3281 return -EINVAL;
3282 /*
3283 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3284 * reporting is disabled
3285 */
3286 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3287 vcpu->arch.mcg_ctl != ~(u64)0)
3288 return 0;
3289 banks += 4 * mce->bank;
3290 /*
3291 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3292 * reporting is disabled for the bank
3293 */
3294 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3295 return 0;
3296 if (mce->status & MCI_STATUS_UC) {
3297 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3298 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3299 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3300 return 0;
3301 }
3302 if (banks[1] & MCI_STATUS_VAL)
3303 mce->status |= MCI_STATUS_OVER;
3304 banks[2] = mce->addr;
3305 banks[3] = mce->misc;
3306 vcpu->arch.mcg_status = mce->mcg_status;
3307 banks[1] = mce->status;
3308 kvm_queue_exception(vcpu, MC_VECTOR);
3309 } else if (!(banks[1] & MCI_STATUS_VAL)
3310 || !(banks[1] & MCI_STATUS_UC)) {
3311 if (banks[1] & MCI_STATUS_VAL)
3312 mce->status |= MCI_STATUS_OVER;
3313 banks[2] = mce->addr;
3314 banks[3] = mce->misc;
3315 banks[1] = mce->status;
3316 } else
3317 banks[1] |= MCI_STATUS_OVER;
3318 return 0;
3319}
3320
3cfc3092
JK		 3321static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3322 struct kvm_vcpu_events *events)
3323{
7460fb4a 3324 process_nmi(vcpu);
664f8e26
WL		 3325 /*
3326 * FIXME: pass injected and pending separately. This is only
3327 * needed for nested virtualization, whose state cannot be
3328 * migrated yet. For now we can combine them.
3329 */
03b82a30 3330 events->exception.injected =
664f8e26
WL		 3331 (vcpu->arch.exception.pending ||
3332 vcpu->arch.exception.injected) &&
03b82a30 3333 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3334 events->exception.nr = vcpu->arch.exception.nr;
3335 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3336 events->exception.pad = 0;
3cfc3092
JK		 3337 events->exception.error_code = vcpu->arch.exception.error_code;
3338
03b82a30 3339 events->interrupt.injected =
04140b41 3340 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3341 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3342 events->interrupt.soft = 0;
37ccdcbe 3343 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3344
3345 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3346 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3347 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3348 events->nmi.pad = 0;
3cfc3092 3349
66450a21 3350 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3351
f077825a
PB		 3352 events->smi.smm = is_smm(vcpu);
3353 events->smi.pending = vcpu->arch.smi_pending;
3354 events->smi.smm_inside_nmi =
3355 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3356 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3357
dab4b911 3358 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3359 | KVM_VCPUEVENT_VALID_SHADOW
3360 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3361 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3362}
3363
6ef4e07e
XG		 3364static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3365
3cfc3092
JK		 3366static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3367 struct kvm_vcpu_events *events)
3368{
dab4b911 3369 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3370 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3371 | KVM_VCPUEVENT_VALID_SHADOW
3372 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3373 return -EINVAL;
3374
78e546c8 3375 if (events->exception.injected &&
28d06353
JM		 3376 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3377 is_guest_mode(vcpu)))
78e546c8
PB		 3378 return -EINVAL;
3379
28bf2888
DH		 3380 /* INITs are latched while in SMM */
3381 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3382 (events->smi.smm || events->smi.pending) &&
3383 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3384 return -EINVAL;
3385
7460fb4a 3386 process_nmi(vcpu);
664f8e26 3387 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3388 vcpu->arch.exception.pending = events->exception.injected;
3389 vcpu->arch.exception.nr = events->exception.nr;
3390 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3391 vcpu->arch.exception.error_code = events->exception.error_code;
3392
04140b41 3393 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3394 vcpu->arch.interrupt.nr = events->interrupt.nr;
3395 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3396 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3397 kvm_x86_ops->set_interrupt_shadow(vcpu,
3398 events->interrupt.shadow);
3cfc3092
JK		 3399
3400 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3401 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3402 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3403 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3404
66450a21 3405 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3406 lapic_in_kernel(vcpu))
66450a21 3407 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3408
f077825a 3409 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3410 u32 hflags = vcpu->arch.hflags;
f077825a 3411 if (events->smi.smm)
6ef4e07e 3412 hflags |= HF_SMM_MASK;
f077825a 3413 else
6ef4e07e
XG		 3414 hflags &= ~HF_SMM_MASK;
3415 kvm_set_hflags(vcpu, hflags);
3416
f077825a 3417 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3418
3419 if (events->smi.smm) {
3420 if (events->smi.smm_inside_nmi)
3421 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3422 else
f4ef1910
WL		 3423 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3424 if (lapic_in_kernel(vcpu)) {
3425 if (events->smi.latched_init)
3426 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3427 else
3428 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3429 }
f077825a
PB		 3430 }
3431 }
3432
3842d135
AK		 3433 kvm_make_request(KVM_REQ_EVENT, vcpu);
3434
3cfc3092
JK		 3435 return 0;
3436}
3437
a1efbe77
JK		 3438static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3439 struct kvm_debugregs *dbgregs)
3440{
73aaf249
JK		 3441 unsigned long val;
3442
a1efbe77 3443 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3444 kvm_get_dr(vcpu, 6, &val);
73aaf249 3445 dbgregs->dr6 = val;
a1efbe77
JK		 3446 dbgregs->dr7 = vcpu->arch.dr7;
3447 dbgregs->flags = 0;
97e69aa6 3448 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3449}
3450
3451static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3452 struct kvm_debugregs *dbgregs)
3453{
3454 if (dbgregs->flags)
3455 return -EINVAL;
3456
d14bdb55
PB		 3457 if (dbgregs->dr6 & ~0xffffffffull)
3458 return -EINVAL;
3459 if (dbgregs->dr7 & ~0xffffffffull)
3460 return -EINVAL;
3461
a1efbe77 3462 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3463 kvm_update_dr0123(vcpu);
a1efbe77 3464 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3465 kvm_update_dr6(vcpu);
a1efbe77 3466 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3467 kvm_update_dr7(vcpu);
a1efbe77 3468
a1efbe77
JK		 3469 return 0;
3470}
3471
df1daba7
PB		 3472#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3473
3474static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3475{
c47ada30 3476 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3477 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3478 u64 valid;
3479
3480 /*
3481 * Copy legacy XSAVE area, to avoid complications with CPUID
3482 * leaves 0 and 1 in the loop below.
3483 */
3484 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3485
3486 /* Set XSTATE_BV */
00c87e9a 3487 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3488 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3489
3490 /*
3491 * Copy each region from the possibly compacted offset to the
3492 * non-compacted offset.
3493 */
d91cab78 3494 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3495 while (valid) {
3496 u64 feature = valid & -valid;
3497 int index = fls64(feature) - 1;
3498 void *src = get_xsave_addr(xsave, feature);
3499
3500 if (src) {
3501 u32 size, offset, ecx, edx;
3502 cpuid_count(XSTATE_CPUID, index,
3503 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3504 if (feature == XFEATURE_MASK_PKRU)
3505 memcpy(dest + offset, &vcpu->arch.pkru,
3506 sizeof(vcpu->arch.pkru));
3507 else
3508 memcpy(dest + offset, src, size);
3509
df1daba7
PB		 3510 }
3511
3512 valid -= feature;
3513 }
3514}
3515
3516static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3517{
c47ada30 3518 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3519 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3520 u64 valid;
3521
3522 /*
3523 * Copy legacy XSAVE area, to avoid complications with CPUID
3524 * leaves 0 and 1 in the loop below.
3525 */
3526 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3527
3528 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3529 xsave->header.xfeatures = xstate_bv;
782511b0 3530 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3531 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3532
3533 /*
3534 * Copy each region from the non-compacted offset to the
3535 * possibly compacted offset.
3536 */
d91cab78 3537 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3538 while (valid) {
3539 u64 feature = valid & -valid;
3540 int index = fls64(feature) - 1;
3541 void *dest = get_xsave_addr(xsave, feature);
3542
3543 if (dest) {
3544 u32 size, offset, ecx, edx;
3545 cpuid_count(XSTATE_CPUID, index,
3546 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3547 if (feature == XFEATURE_MASK_PKRU)
3548 memcpy(&vcpu->arch.pkru, src + offset,
3549 sizeof(vcpu->arch.pkru));
3550 else
3551 memcpy(dest, src + offset, size);
ee4100da 3552 }
df1daba7
PB		 3553
3554 valid -= feature;
3555 }
3556}
3557
2d5b5a66
SY		 3558static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3559 struct kvm_xsave *guest_xsave)
3560{
d366bf7e 3561 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3562 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3563 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3564 } else {
2d5b5a66 3565 memcpy(guest_xsave->region,
7366ed77 3566 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3567 sizeof(struct fxregs_state));
2d5b5a66 3568 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3569 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3570 }
3571}
3572
a575813b
WL		 3573#define XSAVE_MXCSR_OFFSET 24
3574
2d5b5a66
SY		 3575static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3576 struct kvm_xsave *guest_xsave)
3577{
3578 u64 xstate_bv =
3579 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3580 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3581
d366bf7e 3582 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3583 /*
3584 * Here we allow setting states that are not present in
3585 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3586 * with old userspace.
3587 */
a575813b
WL		 3588 if (xstate_bv & ~kvm_supported_xcr0() ||
3589 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3590 return -EINVAL;
df1daba7 3591 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3592 } else {
a575813b
WL		 3593 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3594 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3595 return -EINVAL;
7366ed77 3596 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3597 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3598 }
3599 return 0;
3600}
3601
3602static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3603 struct kvm_xcrs *guest_xcrs)
3604{
d366bf7e 3605 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3606 guest_xcrs->nr_xcrs = 0;
3607 return;
3608 }
3609
3610 guest_xcrs->nr_xcrs = 1;
3611 guest_xcrs->flags = 0;
3612 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3613 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3614}
3615
3616static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3617 struct kvm_xcrs *guest_xcrs)
3618{
3619 int i, r = 0;
3620
d366bf7e 3621 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3622 return -EINVAL;
3623
3624 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3625 return -EINVAL;
3626
3627 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3628 /* Only support XCR0 currently */
c67a04cb 3629 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3630 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3631 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3632 break;
3633 }
3634 if (r)
3635 r = -EINVAL;
3636 return r;
3637}
3638
1c0b28c2
EM		 3639/*
3640 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3641 * stopped by the hypervisor. This function will be called from the host only.
3642 * EINVAL is returned when the host attempts to set the flag for a guest that
3643 * does not support pv clocks.
3644 */
3645static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3646{
0b79459b 3647 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3648 return -EINVAL;
51d59c6b 3649 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3650 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3651 return 0;
3652}
3653
5c919412
AS		 3654static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3655 struct kvm_enable_cap *cap)
3656{
3657 if (cap->flags)
3658 return -EINVAL;
3659
3660 switch (cap->cap) {
efc479e6
RK		 3661 case KVM_CAP_HYPERV_SYNIC2:
3662 if (cap->args[0])
3663 return -EINVAL;
5c919412 3664 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3665 if (!irqchip_in_kernel(vcpu->kvm))
3666 return -EINVAL;
efc479e6
RK		 3667 return kvm_hv_activate_synic(vcpu, cap->cap ==
3668 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3669 default:
3670 return -EINVAL;
3671 }
3672}
3673
313a3dc7
CO		 3674long kvm_arch_vcpu_ioctl(struct file *filp,
3675 unsigned int ioctl, unsigned long arg)
3676{
3677 struct kvm_vcpu *vcpu = filp->private_data;
3678 void __user *argp = (void __user *)arg;
3679 int r;
d1ac91d8
AK		 3680 union {
3681 struct kvm_lapic_state *lapic;
3682 struct kvm_xsave *xsave;
3683 struct kvm_xcrs *xcrs;
3684 void *buffer;
3685 } u;
3686
9b062471
CD		 3687 vcpu_load(vcpu);
3688
d1ac91d8 3689 u.buffer = NULL;
313a3dc7
CO		 3690 switch (ioctl) {
3691 case KVM_GET_LAPIC: {
2204ae3c 3692 r = -EINVAL;
bce87cce 3693 if (!lapic_in_kernel(vcpu))
2204ae3c 3694 goto out;
d1ac91d8 3695 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3696
b772ff36 3697 r = -ENOMEM;
d1ac91d8 3698 if (!u.lapic)
b772ff36 3699 goto out;
d1ac91d8 3700 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3701 if (r)
3702 goto out;
3703 r = -EFAULT;
d1ac91d8 3704 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3705 goto out;
3706 r = 0;
3707 break;
3708 }
3709 case KVM_SET_LAPIC: {
2204ae3c 3710 r = -EINVAL;
bce87cce 3711 if (!lapic_in_kernel(vcpu))
2204ae3c 3712 goto out;
ff5c2c03 3713 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3714 if (IS_ERR(u.lapic)) {
3715 r = PTR_ERR(u.lapic);
3716 goto out_nofree;
3717 }
ff5c2c03 3718
d1ac91d8 3719 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3720 break;
3721 }
f77bc6a4
ZX		 3722 case KVM_INTERRUPT: {
3723 struct kvm_interrupt irq;
3724
3725 r = -EFAULT;
3726 if (copy_from_user(&irq, argp, sizeof irq))
3727 goto out;
3728 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3729 break;
3730 }
c4abb7c9
JK		 3731 case KVM_NMI: {
3732 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3733 break;
3734 }
f077825a
PB		 3735 case KVM_SMI: {
3736 r = kvm_vcpu_ioctl_smi(vcpu);
3737 break;
3738 }
313a3dc7
CO		 3739 case KVM_SET_CPUID: {
3740 struct kvm_cpuid __user *cpuid_arg = argp;
3741 struct kvm_cpuid cpuid;
3742
3743 r = -EFAULT;
3744 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3745 goto out;
3746 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3747 break;
3748 }
07716717
DK		 3749 case KVM_SET_CPUID2: {
3750 struct kvm_cpuid2 __user *cpuid_arg = argp;
3751 struct kvm_cpuid2 cpuid;
3752
3753 r = -EFAULT;
3754 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3755 goto out;
3756 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3757 cpuid_arg->entries);
07716717
DK		 3758 break;
3759 }
3760 case KVM_GET_CPUID2: {
3761 struct kvm_cpuid2 __user *cpuid_arg = argp;
3762 struct kvm_cpuid2 cpuid;
3763
3764 r = -EFAULT;
3765 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3766 goto out;
3767 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3768 cpuid_arg->entries);
07716717
DK		 3769 if (r)
3770 goto out;
3771 r = -EFAULT;
3772 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3773 goto out;
3774 r = 0;
3775 break;
3776 }
801e459a
TL		 3777 case KVM_GET_MSRS: {
3778 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3779 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3780 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3781 break;
801e459a
TL		 3782 }
3783 case KVM_SET_MSRS: {
3784 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3785 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3786 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3787 break;
801e459a 3788 }
b209749f
AK		 3789 case KVM_TPR_ACCESS_REPORTING: {
3790 struct kvm_tpr_access_ctl tac;
3791
3792 r = -EFAULT;
3793 if (copy_from_user(&tac, argp, sizeof tac))
3794 goto out;
3795 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3796 if (r)
3797 goto out;
3798 r = -EFAULT;
3799 if (copy_to_user(argp, &tac, sizeof tac))
3800 goto out;
3801 r = 0;
3802 break;
3803 };
b93463aa
AK		 3804 case KVM_SET_VAPIC_ADDR: {
3805 struct kvm_vapic_addr va;
7301d6ab 3806 int idx;
b93463aa
AK		 3807
3808 r = -EINVAL;
35754c98 3809 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3810 goto out;
3811 r = -EFAULT;
3812 if (copy_from_user(&va, argp, sizeof va))
3813 goto out;
7301d6ab 3814 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3815 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3816 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3817 break;
3818 }
890ca9ae
HY		 3819 case KVM_X86_SETUP_MCE: {
3820 u64 mcg_cap;
3821
3822 r = -EFAULT;
3823 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3824 goto out;
3825 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3826 break;
3827 }
3828 case KVM_X86_SET_MCE: {
3829 struct kvm_x86_mce mce;
3830
3831 r = -EFAULT;
3832 if (copy_from_user(&mce, argp, sizeof mce))
3833 goto out;
3834 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3835 break;
3836 }
3cfc3092
JK		 3837 case KVM_GET_VCPU_EVENTS: {
3838 struct kvm_vcpu_events events;
3839
3840 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3841
3842 r = -EFAULT;
3843 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3844 break;
3845 r = 0;
3846 break;
3847 }
3848 case KVM_SET_VCPU_EVENTS: {
3849 struct kvm_vcpu_events events;
3850
3851 r = -EFAULT;
3852 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3853 break;
3854
3855 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3856 break;
3857 }
a1efbe77
JK		 3858 case KVM_GET_DEBUGREGS: {
3859 struct kvm_debugregs dbgregs;
3860
3861 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3862
3863 r = -EFAULT;
3864 if (copy_to_user(argp, &dbgregs,
3865 sizeof(struct kvm_debugregs)))
3866 break;
3867 r = 0;
3868 break;
3869 }
3870 case KVM_SET_DEBUGREGS: {
3871 struct kvm_debugregs dbgregs;
3872
3873 r = -EFAULT;
3874 if (copy_from_user(&dbgregs, argp,
3875 sizeof(struct kvm_debugregs)))
3876 break;
3877
3878 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3879 break;
3880 }
2d5b5a66 3881 case KVM_GET_XSAVE: {
d1ac91d8 3882 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3883 r = -ENOMEM;
d1ac91d8 3884 if (!u.xsave)
2d5b5a66
SY		 3885 break;
3886
d1ac91d8 3887 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3888
3889 r = -EFAULT;
d1ac91d8 3890 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3891 break;
3892 r = 0;
3893 break;
3894 }
3895 case KVM_SET_XSAVE: {
ff5c2c03 3896 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3897 if (IS_ERR(u.xsave)) {
3898 r = PTR_ERR(u.xsave);
3899 goto out_nofree;
3900 }
2d5b5a66 3901
d1ac91d8 3902 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3903 break;
3904 }
3905 case KVM_GET_XCRS: {
d1ac91d8 3906 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3907 r = -ENOMEM;
d1ac91d8 3908 if (!u.xcrs)
2d5b5a66
SY		 3909 break;
3910
d1ac91d8 3911 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3912
3913 r = -EFAULT;
d1ac91d8 3914 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3915 sizeof(struct kvm_xcrs)))
3916 break;
3917 r = 0;
3918 break;
3919 }
3920 case KVM_SET_XCRS: {
ff5c2c03 3921 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3922 if (IS_ERR(u.xcrs)) {
3923 r = PTR_ERR(u.xcrs);
3924 goto out_nofree;
3925 }
2d5b5a66 3926
d1ac91d8 3927 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3928 break;
3929 }
92a1f12d
JR		 3930 case KVM_SET_TSC_KHZ: {
3931 u32 user_tsc_khz;
3932
3933 r = -EINVAL;
92a1f12d
JR		 3934 user_tsc_khz = (u32)arg;
3935
3936 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3937 goto out;
3938
cc578287
ZA		 3939 if (user_tsc_khz == 0)
3940 user_tsc_khz = tsc_khz;
3941
381d585c
HZ		 3942 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3943 r = 0;
92a1f12d 3944
92a1f12d
JR		 3945 goto out;
3946 }
3947 case KVM_GET_TSC_KHZ: {
cc578287 3948 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3949 goto out;
3950 }
1c0b28c2
EM		 3951 case KVM_KVMCLOCK_CTRL: {
3952 r = kvm_set_guest_paused(vcpu);
3953 goto out;
3954 }
5c919412
AS		 3955 case KVM_ENABLE_CAP: {
3956 struct kvm_enable_cap cap;
3957
3958 r = -EFAULT;
3959 if (copy_from_user(&cap, argp, sizeof(cap)))
3960 goto out;
3961 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3962 break;
3963 }
313a3dc7
CO		 3964 default:
3965 r = -EINVAL;
3966 }
3967out:
d1ac91d8 3968 kfree(u.buffer);
9b062471
CD		 3969out_nofree:
3970 vcpu_put(vcpu);
313a3dc7
CO		 3971 return r;
3972}
3973
1499fa80 3974vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 3975{
3976 return VM_FAULT_SIGBUS;
3977}
3978
1fe779f8
CO		 3979static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3980{
3981 int ret;
3982
3983 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3984 return -EINVAL;
1fe779f8
CO		 3985 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3986 return ret;
3987}
3988
b927a3ce
SY		 3989static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3990 u64 ident_addr)
3991{
2ac52ab8 3992 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3993}
3994
1fe779f8
CO		 3995static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3996 u32 kvm_nr_mmu_pages)
3997{
3998 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3999 return -EINVAL;
4000
79fac95e 4001 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4002
4003 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4004 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4005
79fac95e 4006 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4007 return 0;
4008}
4009
4010static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4011{
39de71ec 4012 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4013}
4014
1fe779f8
CO		 4015static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4016{
90bca052 4017 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4018 int r;
4019
4020 r = 0;
4021 switch (chip->chip_id) {
4022 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4023 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4024 sizeof(struct kvm_pic_state));
4025 break;
4026 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4027 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4028 sizeof(struct kvm_pic_state));
4029 break;
4030 case KVM_IRQCHIP_IOAPIC:
33392b49 4031 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4032 break;
4033 default:
4034 r = -EINVAL;
4035 break;
4036 }
4037 return r;
4038}
4039
4040static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4041{
90bca052 4042 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4043 int r;
4044
4045 r = 0;
4046 switch (chip->chip_id) {
4047 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4048 spin_lock(&pic->lock);
4049 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4050 sizeof(struct kvm_pic_state));
90bca052 4051 spin_unlock(&pic->lock);
1fe779f8
CO		 4052 break;
4053 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4054 spin_lock(&pic->lock);
4055 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4056 sizeof(struct kvm_pic_state));
90bca052 4057 spin_unlock(&pic->lock);
1fe779f8
CO		 4058 break;
4059 case KVM_IRQCHIP_IOAPIC:
33392b49 4060 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4061 break;
4062 default:
4063 r = -EINVAL;
4064 break;
4065 }
90bca052 4066 kvm_pic_update_irq(pic);
1fe779f8
CO		 4067 return r;
4068}
4069
e0f63cb9
SY		 4070static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4071{
34f3941c
RK		 4072 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4073
4074 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4075
4076 mutex_lock(&kps->lock);
4077 memcpy(ps, &kps->channels, sizeof(*ps));
4078 mutex_unlock(&kps->lock);
2da29bcc 4079 return 0;
e0f63cb9
SY		 4080}
4081
4082static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4083{
0185604c 4084 int i;
09edea72
RK		 4085 struct kvm_pit *pit = kvm->arch.vpit;
4086
4087 mutex_lock(&pit->pit_state.lock);
34f3941c 4088 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4089 for (i = 0; i < 3; i++)
09edea72
RK		 4090 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4091 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4092 return 0;
e9f42757
BK		 4093}
4094
4095static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4096{
e9f42757
BK		 4097 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4098 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4099 sizeof(ps->channels));
4100 ps->flags = kvm->arch.vpit->pit_state.flags;
4101 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4102 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4103 return 0;
e9f42757
BK		 4104}
4105
4106static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4107{
2da29bcc 4108 int start = 0;
0185604c 4109 int i;
e9f42757 4110 u32 prev_legacy, cur_legacy;
09edea72
RK		 4111 struct kvm_pit *pit = kvm->arch.vpit;
4112
4113 mutex_lock(&pit->pit_state.lock);
4114 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4115 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4116 if (!prev_legacy && cur_legacy)
4117 start = 1;
09edea72
RK		 4118 memcpy(&pit->pit_state.channels, &ps->channels,
4119 sizeof(pit->pit_state.channels));
4120 pit->pit_state.flags = ps->flags;
0185604c 4121 for (i = 0; i < 3; i++)
09edea72 4122 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4123 start && i == 0);
09edea72 4124 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4125 return 0;
e0f63cb9
SY		 4126}
4127
52d939a0
MT		 4128static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4129 struct kvm_reinject_control *control)
4130{
71474e2f
RK		 4131 struct kvm_pit *pit = kvm->arch.vpit;
4132
4133 if (!pit)
52d939a0 4134 return -ENXIO;
b39c90b6 4135
71474e2f
RK		 4136 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4137 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4138 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4139 */
4140 mutex_lock(&pit->pit_state.lock);
4141 kvm_pit_set_reinject(pit, control->pit_reinject);
4142 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4143
52d939a0
MT		 4144 return 0;
4145}
4146
95d4c16c 4147/**
60c34612
TY		 4148 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4149 * @kvm: kvm instance
4150 * @log: slot id and address to which we copy the log
95d4c16c 4151 *
e108ff2f
PB		 4152 * Steps 1-4 below provide general overview of dirty page logging. See
4153 * kvm_get_dirty_log_protect() function description for additional details.
4154 *
4155 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4156 * always flush the TLB (step 4) even if previous step failed and the dirty
4157 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4158 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4159 * writes will be marked dirty for next log read.
95d4c16c 4160 *
60c34612
TY		 4161 * 1. Take a snapshot of the bit and clear it if needed.
4162 * 2. Write protect the corresponding page.
e108ff2f
PB		 4163 * 3. Copy the snapshot to the userspace.
4164 * 4. Flush TLB's if needed.
5bb064dc 4165 */
60c34612 4166int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4167{
60c34612 4168 bool is_dirty = false;
e108ff2f 4169 int r;
5bb064dc 4170
79fac95e 4171 mutex_lock(&kvm->slots_lock);
5bb064dc 4172
88178fd4
KH		 4173 /*
4174 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4175 */
4176 if (kvm_x86_ops->flush_log_dirty)
4177 kvm_x86_ops->flush_log_dirty(kvm);
4178
e108ff2f 4179 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4180
4181 /*
4182 * All the TLBs can be flushed out of mmu lock, see the comments in
4183 * kvm_mmu_slot_remove_write_access().
4184 */
e108ff2f 4185 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4186 if (is_dirty)
4187 kvm_flush_remote_tlbs(kvm);
4188
79fac95e 4189 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4190 return r;
4191}
4192
aa2fbe6d
YZ		 4193int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4194 bool line_status)
23d43cf9
CD		 4195{
4196 if (!irqchip_in_kernel(kvm))
4197 return -ENXIO;
4198
4199 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4200 irq_event->irq, irq_event->level,
4201 line_status);
23d43cf9
CD		 4202 return 0;
4203}
4204
90de4a18
NA		 4205static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4206 struct kvm_enable_cap *cap)
4207{
4208 int r;
4209
4210 if (cap->flags)
4211 return -EINVAL;
4212
4213 switch (cap->cap) {
4214 case KVM_CAP_DISABLE_QUIRKS:
4215 kvm->arch.disabled_quirks = cap->args[0];
4216 r = 0;
4217 break;
49df6397
SR		 4218 case KVM_CAP_SPLIT_IRQCHIP: {
4219 mutex_lock(&kvm->lock);
b053b2ae
SR		 4220 r = -EINVAL;
4221 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4222 goto split_irqchip_unlock;
49df6397
SR		 4223 r = -EEXIST;
4224 if (irqchip_in_kernel(kvm))
4225 goto split_irqchip_unlock;
557abc40 4226 if (kvm->created_vcpus)
49df6397
SR		 4227 goto split_irqchip_unlock;
4228 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4229 if (r)
49df6397
SR		 4230 goto split_irqchip_unlock;
4231 /* Pairs with irqchip_in_kernel. */
4232 smp_wmb();
49776faf 4233 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4234 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4235 r = 0;
4236split_irqchip_unlock:
4237 mutex_unlock(&kvm->lock);
4238 break;
4239 }
37131313
RK		 4240 case KVM_CAP_X2APIC_API:
4241 r = -EINVAL;
4242 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4243 break;
4244
4245 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4246 kvm->arch.x2apic_format = true;
c519265f
RK		 4247 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4248 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4249
4250 r = 0;
4251 break;
4d5422ce
WL		 4252 case KVM_CAP_X86_DISABLE_EXITS:
4253 r = -EINVAL;
4254 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4255 break;
4256
4257 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4258 kvm_can_mwait_in_guest())
4259 kvm->arch.mwait_in_guest = true;
766d3571 4260 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4261 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4262 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4263 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4264 r = 0;
4265 break;
90de4a18
NA		 4266 default:
4267 r = -EINVAL;
4268 break;
4269 }
4270 return r;
4271}
4272
1fe779f8
CO		 4273long kvm_arch_vm_ioctl(struct file *filp,
4274 unsigned int ioctl, unsigned long arg)
4275{
4276 struct kvm *kvm = filp->private_data;
4277 void __user *argp = (void __user *)arg;
367e1319 4278 int r = -ENOTTY;
f0d66275
DH		 4279 /*
4280 * This union makes it completely explicit to gcc-3.x
4281 * that these two variables' stack usage should be
4282 * combined, not added together.
4283 */
4284 union {
4285 struct kvm_pit_state ps;
e9f42757 4286 struct kvm_pit_state2 ps2;
c5ff41ce 4287 struct kvm_pit_config pit_config;
f0d66275 4288 } u;
1fe779f8
CO		 4289
4290 switch (ioctl) {
4291 case KVM_SET_TSS_ADDR:
4292 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4293 break;
b927a3ce
SY		 4294 case KVM_SET_IDENTITY_MAP_ADDR: {
4295 u64 ident_addr;
4296
1af1ac91
DH		 4297 mutex_lock(&kvm->lock);
4298 r = -EINVAL;
4299 if (kvm->created_vcpus)
4300 goto set_identity_unlock;
b927a3ce
SY		 4301 r = -EFAULT;
4302 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4303 goto set_identity_unlock;
b927a3ce 4304 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4305set_identity_unlock:
4306 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4307 break;
4308 }
1fe779f8
CO		 4309 case KVM_SET_NR_MMU_PAGES:
4310 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4311 break;
4312 case KVM_GET_NR_MMU_PAGES:
4313 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4314 break;
3ddea128 4315 case KVM_CREATE_IRQCHIP: {
3ddea128 4316 mutex_lock(&kvm->lock);
09941366 4317
3ddea128 4318 r = -EEXIST;
35e6eaa3 4319 if (irqchip_in_kernel(kvm))
3ddea128 4320 goto create_irqchip_unlock;
09941366 4321
3e515705 4322 r = -EINVAL;
557abc40 4323 if (kvm->created_vcpus)
3e515705 4324 goto create_irqchip_unlock;
09941366
RK		 4325
4326 r = kvm_pic_init(kvm);
4327 if (r)
3ddea128 4328 goto create_irqchip_unlock;
09941366
RK		 4329
4330 r = kvm_ioapic_init(kvm);
4331 if (r) {
09941366 4332 kvm_pic_destroy(kvm);
3ddea128 4333 goto create_irqchip_unlock;
09941366
RK		 4334 }
4335
399ec807
AK		 4336 r = kvm_setup_default_irq_routing(kvm);
4337 if (r) {
72bb2fcd 4338 kvm_ioapic_destroy(kvm);
09941366 4339 kvm_pic_destroy(kvm);
71ba994c 4340 goto create_irqchip_unlock;
399ec807 4341 }
49776faf 4342 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4343 smp_wmb();
49776faf 4344 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4345 create_irqchip_unlock:
4346 mutex_unlock(&kvm->lock);
1fe779f8 4347 break;
3ddea128 4348 }
7837699f 4349 case KVM_CREATE_PIT:
c5ff41ce
JK		 4350 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4351 goto create_pit;
4352 case KVM_CREATE_PIT2:
4353 r = -EFAULT;
4354 if (copy_from_user(&u.pit_config, argp,
4355 sizeof(struct kvm_pit_config)))
4356 goto out;
4357 create_pit:
250715a6 4358 mutex_lock(&kvm->lock);
269e05e4
AK		 4359 r = -EEXIST;
4360 if (kvm->arch.vpit)
4361 goto create_pit_unlock;
7837699f 4362 r = -ENOMEM;
c5ff41ce 4363 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4364 if (kvm->arch.vpit)
4365 r = 0;
269e05e4 4366 create_pit_unlock:
250715a6 4367 mutex_unlock(&kvm->lock);
7837699f 4368 break;
1fe779f8
CO		 4369 case KVM_GET_IRQCHIP: {
4370 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4371 struct kvm_irqchip *chip;
1fe779f8 4372
ff5c2c03
SL		 4373 chip = memdup_user(argp, sizeof(*chip));
4374 if (IS_ERR(chip)) {
4375 r = PTR_ERR(chip);
1fe779f8 4376 goto out;
ff5c2c03
SL		 4377 }
4378
1fe779f8 4379 r = -ENXIO;
826da321 4380 if (!irqchip_kernel(kvm))
f0d66275
DH		 4381 goto get_irqchip_out;
4382 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4383 if (r)
f0d66275 4384 goto get_irqchip_out;
1fe779f8 4385 r = -EFAULT;
f0d66275
DH		 4386 if (copy_to_user(argp, chip, sizeof *chip))
4387 goto get_irqchip_out;
1fe779f8 4388 r = 0;
f0d66275
DH		 4389 get_irqchip_out:
4390 kfree(chip);
1fe779f8
CO		 4391 break;
4392 }
4393 case KVM_SET_IRQCHIP: {
4394 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4395 struct kvm_irqchip *chip;
1fe779f8 4396
ff5c2c03
SL		 4397 chip = memdup_user(argp, sizeof(*chip));
4398 if (IS_ERR(chip)) {
4399 r = PTR_ERR(chip);
1fe779f8 4400 goto out;
ff5c2c03
SL		 4401 }
4402
1fe779f8 4403 r = -ENXIO;
826da321 4404 if (!irqchip_kernel(kvm))
f0d66275
DH		 4405 goto set_irqchip_out;
4406 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4407 if (r)
f0d66275 4408 goto set_irqchip_out;
1fe779f8 4409 r = 0;
f0d66275
DH		 4410 set_irqchip_out:
4411 kfree(chip);
1fe779f8
CO		 4412 break;
4413 }
e0f63cb9 4414 case KVM_GET_PIT: {
e0f63cb9 4415 r = -EFAULT;
f0d66275 4416 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4417 goto out;
4418 r = -ENXIO;
4419 if (!kvm->arch.vpit)
4420 goto out;
f0d66275 4421 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4422 if (r)
4423 goto out;
4424 r = -EFAULT;
f0d66275 4425 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4426 goto out;
4427 r = 0;
4428 break;
4429 }
4430 case KVM_SET_PIT: {
e0f63cb9 4431 r = -EFAULT;
f0d66275 4432 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4433 goto out;
4434 r = -ENXIO;
4435 if (!kvm->arch.vpit)
4436 goto out;
f0d66275 4437 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4438 break;
4439 }
e9f42757
BK		 4440 case KVM_GET_PIT2: {
4441 r = -ENXIO;
4442 if (!kvm->arch.vpit)
4443 goto out;
4444 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4445 if (r)
4446 goto out;
4447 r = -EFAULT;
4448 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4449 goto out;
4450 r = 0;
4451 break;
4452 }
4453 case KVM_SET_PIT2: {
4454 r = -EFAULT;
4455 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4456 goto out;
4457 r = -ENXIO;
4458 if (!kvm->arch.vpit)
4459 goto out;
4460 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4461 break;
4462 }
52d939a0
MT		 4463 case KVM_REINJECT_CONTROL: {
4464 struct kvm_reinject_control control;
4465 r = -EFAULT;
4466 if (copy_from_user(&control, argp, sizeof(control)))
4467 goto out;
4468 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4469 break;
4470 }
d71ba788
PB		 4471 case KVM_SET_BOOT_CPU_ID:
4472 r = 0;
4473 mutex_lock(&kvm->lock);
557abc40 4474 if (kvm->created_vcpus)
d71ba788
PB		 4475 r = -EBUSY;
4476 else
4477 kvm->arch.bsp_vcpu_id = arg;
4478 mutex_unlock(&kvm->lock);
4479 break;
ffde22ac 4480 case KVM_XEN_HVM_CONFIG: {
51776043 4481 struct kvm_xen_hvm_config xhc;
ffde22ac 4482 r = -EFAULT;
51776043 4483 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4484 goto out;
4485 r = -EINVAL;
51776043 4486 if (xhc.flags)
ffde22ac 4487 goto out;
51776043 4488 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4489 r = 0;
4490 break;
4491 }
afbcf7ab 4492 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4493 struct kvm_clock_data user_ns;
4494 u64 now_ns;
afbcf7ab
GC		 4495
4496 r = -EFAULT;
4497 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4498 goto out;
4499
4500 r = -EINVAL;
4501 if (user_ns.flags)
4502 goto out;
4503
4504 r = 0;
0bc48bea
RK		 4505 /*
4506 * TODO: userspace has to take care of races with VCPU_RUN, so
4507 * kvm_gen_update_masterclock() can be cut down to locked
4508 * pvclock_update_vm_gtod_copy().
4509 */
4510 kvm_gen_update_masterclock(kvm);
e891a32e 4511 now_ns = get_kvmclock_ns(kvm);
108b249c 4512 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4513 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4514 break;
4515 }
4516 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4517 struct kvm_clock_data user_ns;
4518 u64 now_ns;
4519
e891a32e 4520 now_ns = get_kvmclock_ns(kvm);
108b249c 4521 user_ns.clock = now_ns;
e3fd9a93 4522 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4523 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4524
4525 r = -EFAULT;
4526 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4527 goto out;
4528 r = 0;
4529 break;
4530 }
90de4a18
NA		 4531 case KVM_ENABLE_CAP: {
4532 struct kvm_enable_cap cap;
afbcf7ab 4533
90de4a18
NA		 4534 r = -EFAULT;
4535 if (copy_from_user(&cap, argp, sizeof(cap)))
4536 goto out;
4537 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4538 break;
4539 }
5acc5c06
BS		 4540 case KVM_MEMORY_ENCRYPT_OP: {
4541 r = -ENOTTY;
4542 if (kvm_x86_ops->mem_enc_op)
4543 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4544 break;
4545 }
69eaedee
BS		 4546 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4547 struct kvm_enc_region region;
4548
4549 r = -EFAULT;
4550 if (copy_from_user(&region, argp, sizeof(region)))
4551 goto out;
4552
4553 r = -ENOTTY;
4554 if (kvm_x86_ops->mem_enc_reg_region)
4555 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4556 break;
4557 }
4558 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4559 struct kvm_enc_region region;
4560
4561 r = -EFAULT;
4562 if (copy_from_user(&region, argp, sizeof(region)))
4563 goto out;
4564
4565 r = -ENOTTY;
4566 if (kvm_x86_ops->mem_enc_unreg_region)
4567 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4568 break;
4569 }
faeb7833
RK		 4570 case KVM_HYPERV_EVENTFD: {
4571 struct kvm_hyperv_eventfd hvevfd;
4572
4573 r = -EFAULT;
4574 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4575 goto out;
4576 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4577 break;
4578 }
1fe779f8 4579 default:
ad6260da 4580 r = -ENOTTY;
1fe779f8
CO		 4581 }
4582out:
4583 return r;
4584}
4585
a16b043c 4586static void kvm_init_msr_list(void)
043405e1
CO		 4587{
4588 u32 dummy[2];
4589 unsigned i, j;
4590
62ef68bb 4591 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4592 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4593 continue;
93c4adc7
PB		 4594
4595 /*
4596 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4597 * to the guests in some cases.
93c4adc7
PB		 4598 */
4599 switch (msrs_to_save[i]) {
4600 case MSR_IA32_BNDCFGS:
4601 if (!kvm_x86_ops->mpx_supported())
4602 continue;
4603 break;
9dbe6cf9
PB		 4604 case MSR_TSC_AUX:
4605 if (!kvm_x86_ops->rdtscp_supported())
4606 continue;
4607 break;
93c4adc7
PB		 4608 default:
4609 break;
4610 }
4611
043405e1
CO		 4612 if (j < i)
4613 msrs_to_save[j] = msrs_to_save[i];
4614 j++;
4615 }
4616 num_msrs_to_save = j;
62ef68bb
PB		 4617
4618 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4619 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4620 continue;
62ef68bb
PB		 4621
4622 if (j < i)
4623 emulated_msrs[j] = emulated_msrs[i];
4624 j++;
4625 }
4626 num_emulated_msrs = j;
801e459a
TL		 4627
4628 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4629 struct kvm_msr_entry msr;
4630
4631 msr.index = msr_based_features[i];
66421c1e 4632 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4633 continue;
4634
4635 if (j < i)
4636 msr_based_features[j] = msr_based_features[i];
4637 j++;
4638 }
4639 num_msr_based_features = j;
043405e1
CO		 4640}
4641
bda9020e
MT		 4642static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4643 const void *v)
bbd9b64e 4644{
70252a10
AK		 4645 int handled = 0;
4646 int n;
4647
4648 do {
4649 n = min(len, 8);
bce87cce 4650 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4651 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4652 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4653 break;
4654 handled += n;
4655 addr += n;
4656 len -= n;
4657 v += n;
4658 } while (len);
bbd9b64e 4659
70252a10 4660 return handled;
bbd9b64e
CO		 4661}
4662
bda9020e 4663static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4664{
70252a10
AK		 4665 int handled = 0;
4666 int n;
4667
4668 do {
4669 n = min(len, 8);
bce87cce 4670 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4671 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4672 addr, n, v))
4673 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4674 break;
e39d200f 4675 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4676 handled += n;
4677 addr += n;
4678 len -= n;
4679 v += n;
4680 } while (len);
bbd9b64e 4681
70252a10 4682 return handled;
bbd9b64e
CO		 4683}
4684
2dafc6c2
GN		 4685static void kvm_set_segment(struct kvm_vcpu *vcpu,
4686 struct kvm_segment *var, int seg)
4687{
4688 kvm_x86_ops->set_segment(vcpu, var, seg);
4689}
4690
4691void kvm_get_segment(struct kvm_vcpu *vcpu,
4692 struct kvm_segment *var, int seg)
4693{
4694 kvm_x86_ops->get_segment(vcpu, var, seg);
4695}
4696
54987b7a
PB		 4697gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4698 struct x86_exception *exception)
02f59dc9
JR		 4699{
4700 gpa_t t_gpa;
02f59dc9
JR		 4701
4702 BUG_ON(!mmu_is_nested(vcpu));
4703
4704 /* NPT walks are always user-walks */
4705 access |= PFERR_USER_MASK;
54987b7a 4706 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4707
4708 return t_gpa;
4709}
4710
ab9ae313
AK		 4711gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4712 struct x86_exception *exception)
1871c602
GN		 4713{
4714 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4715 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4716}
4717
ab9ae313
AK		 4718 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4719 struct x86_exception *exception)
1871c602
GN		 4720{
4721 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4722 access |= PFERR_FETCH_MASK;
ab9ae313 4723 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4724}
4725
ab9ae313
AK		 4726gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4727 struct x86_exception *exception)
1871c602
GN		 4728{
4729 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4730 access |= PFERR_WRITE_MASK;
ab9ae313 4731 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4732}
4733
4734/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4735gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4736 struct x86_exception *exception)
1871c602 4737{
ab9ae313 4738 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4739}
4740
4741static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4742 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4743 struct x86_exception *exception)
bbd9b64e
CO		 4744{
4745 void *data = val;
10589a46 4746 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4747
4748 while (bytes) {
14dfe855 4749 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4750 exception);
bbd9b64e 4751 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4752 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4753 int ret;
4754
bcc55cba 4755 if (gpa == UNMAPPED_GVA)
ab9ae313 4756 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4757 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4758 offset, toread);
10589a46 4759 if (ret < 0) {
c3cd7ffa 4760 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4761 goto out;
4762 }
bbd9b64e 4763
77c2002e
IE		 4764 bytes -= toread;
4765 data += toread;
4766 addr += toread;
bbd9b64e 4767 }
10589a46 4768out:
10589a46 4769 return r;
bbd9b64e 4770}
77c2002e 4771
1871c602 4772/* used for instruction fetching */
0f65dd70
AK		 4773static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4774 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4775 struct x86_exception *exception)
1871c602 4776{
0f65dd70 4777 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4778 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4779 unsigned offset;
4780 int ret;
0f65dd70 4781
44583cba
PB		 4782 /* Inline kvm_read_guest_virt_helper for speed. */
4783 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4784 exception);
4785 if (unlikely(gpa == UNMAPPED_GVA))
4786 return X86EMUL_PROPAGATE_FAULT;
4787
4788 offset = addr & (PAGE_SIZE-1);
4789 if (WARN_ON(offset + bytes > PAGE_SIZE))
4790 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4791 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4792 offset, bytes);
44583cba
PB		 4793 if (unlikely(ret < 0))
4794 return X86EMUL_IO_NEEDED;
4795
4796 return X86EMUL_CONTINUE;
1871c602
GN		 4797}
4798
ce14e868 4799int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 4800 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4801 struct x86_exception *exception)
1871c602
GN		 4802{
4803 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4804
1871c602 4805 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4806 exception);
1871c602 4807}
064aea77 4808EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4809
ce14e868
PB		 4810static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
4811 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 4812 struct x86_exception *exception, bool system)
1871c602 4813{
0f65dd70 4814 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 4815 u32 access = 0;
4816
4817 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4818 access |= PFERR_USER_MASK;
4819
4820 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 4821}
4822
7a036a6f
RK		 4823static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4824 unsigned long addr, void *val, unsigned int bytes)
4825{
4826 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4827 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4828
4829 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4830}
4831
ce14e868
PB		 4832static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4833 struct kvm_vcpu *vcpu, u32 access,
4834 struct x86_exception *exception)
77c2002e
IE		 4835{
4836 void *data = val;
4837 int r = X86EMUL_CONTINUE;
4838
4839 while (bytes) {
14dfe855 4840 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 4841 access,
ab9ae313 4842 exception);
77c2002e
IE		 4843 unsigned offset = addr & (PAGE_SIZE-1);
4844 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4845 int ret;
4846
bcc55cba 4847 if (gpa == UNMAPPED_GVA)
ab9ae313 4848 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4849 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4850 if (ret < 0) {
c3cd7ffa 4851 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4852 goto out;
4853 }
4854
4855 bytes -= towrite;
4856 data += towrite;
4857 addr += towrite;
4858 }
4859out:
4860 return r;
4861}
ce14e868
PB		 4862
4863static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 4864 unsigned int bytes, struct x86_exception *exception,
4865 bool system)
ce14e868
PB		 4866{
4867 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 4868 u32 access = PFERR_WRITE_MASK;
4869
4870 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4871 access |= PFERR_USER_MASK;
ce14e868
PB		 4872
4873 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 4874 access, exception);
ce14e868
PB		 4875}
4876
4877int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
4878 unsigned int bytes, struct x86_exception *exception)
4879{
c595ceee
PB		 4880 /* kvm_write_guest_virt_system can pull in tons of pages. */
4881 vcpu->arch.l1tf_flush_l1d = true;
4882
ce14e868
PB		 4883 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4884 PFERR_WRITE_MASK, exception);
4885}
6a4d7550 4886EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4887
082d06ed
WL		 4888int handle_ud(struct kvm_vcpu *vcpu)
4889{
6c86eedc 4890 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 4891 enum emulation_result er;
6c86eedc
WL		 4892 char sig[5]; /* ud2; .ascii "kvm" */
4893 struct x86_exception e;
4894
4895 if (force_emulation_prefix &&
3c9fa24c
PB		 4896 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
4897 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 4898 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
4899 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
4900 emul_type = 0;
4901 }
082d06ed 4902
6c86eedc 4903 er = emulate_instruction(vcpu, emul_type);
082d06ed
WL		 4904 if (er == EMULATE_USER_EXIT)
4905 return 0;
4906 if (er != EMULATE_DONE)
4907 kvm_queue_exception(vcpu, UD_VECTOR);
4908 return 1;
4909}
4910EXPORT_SYMBOL_GPL(handle_ud);
4911
0f89b207
TL		 4912static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4913 gpa_t gpa, bool write)
4914{
4915 /* For APIC access vmexit */
4916 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4917 return 1;
4918
4919 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4920 trace_vcpu_match_mmio(gva, gpa, write, true);
4921 return 1;
4922 }
4923
4924 return 0;
4925}
4926
af7cc7d1
XG		 4927static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4928 gpa_t *gpa, struct x86_exception *exception,
4929 bool write)
4930{
97d64b78
AK		 4931 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4932 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4933
be94f6b7
HH		 4934 /*
4935 * currently PKRU is only applied to ept enabled guest so
4936 * there is no pkey in EPT page table for L1 guest or EPT
4937 * shadow page table for L2 guest.
4938 */
97d64b78 4939 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4940 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4941 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4942 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4943 (gva & (PAGE_SIZE - 1));
4f022648 4944 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4945 return 1;
4946 }
4947
af7cc7d1
XG		 4948 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4949
4950 if (*gpa == UNMAPPED_GVA)
4951 return -1;
4952
0f89b207 4953 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4954}
4955
3200f405 4956int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4957 const void *val, int bytes)
bbd9b64e
CO		 4958{
4959 int ret;
4960
54bf36aa 4961 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4962 if (ret < 0)
bbd9b64e 4963 return 0;
0eb05bf2 4964 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4965 return 1;
4966}
4967
77d197b2
XG		 4968struct read_write_emulator_ops {
4969 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4970 int bytes);
4971 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4972 void *val, int bytes);
4973 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4974 int bytes, void *val);
4975 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4976 void *val, int bytes);
4977 bool write;
4978};
4979
4980static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4981{
4982 if (vcpu->mmio_read_completed) {
77d197b2 4983 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4984 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4985 vcpu->mmio_read_completed = 0;
4986 return 1;
4987 }
4988
4989 return 0;
4990}
4991
4992static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4993 void *val, int bytes)
4994{
54bf36aa 4995 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4996}
4997
4998static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4999 void *val, int bytes)
5000{
5001 return emulator_write_phys(vcpu, gpa, val, bytes);
5002}
5003
5004static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5005{
e39d200f 5006 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5007 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5008}
5009
5010static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5011 void *val, int bytes)
5012{
e39d200f 5013 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5014 return X86EMUL_IO_NEEDED;
5015}
5016
5017static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5018 void *val, int bytes)
5019{
f78146b0
AK		 5020 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5021
87da7e66 5022 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5023 return X86EMUL_CONTINUE;
5024}
5025
0fbe9b0b 5026static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5027 .read_write_prepare = read_prepare,
5028 .read_write_emulate = read_emulate,
5029 .read_write_mmio = vcpu_mmio_read,
5030 .read_write_exit_mmio = read_exit_mmio,
5031};
5032
0fbe9b0b 5033static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5034 .read_write_emulate = write_emulate,
5035 .read_write_mmio = write_mmio,
5036 .read_write_exit_mmio = write_exit_mmio,
5037 .write = true,
5038};
5039
22388a3c
XG		 5040static int emulator_read_write_onepage(unsigned long addr, void *val,
5041 unsigned int bytes,
5042 struct x86_exception *exception,
5043 struct kvm_vcpu *vcpu,
0fbe9b0b 5044 const struct read_write_emulator_ops *ops)
bbd9b64e 5045{
af7cc7d1
XG		 5046 gpa_t gpa;
5047 int handled, ret;
22388a3c 5048 bool write = ops->write;
f78146b0 5049 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5050 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5051
5052 /*
5053 * If the exit was due to a NPF we may already have a GPA.
5054 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5055 * Note, this cannot be used on string operations since string
5056 * operation using rep will only have the initial GPA from the NPF
5057 * occurred.
5058 */
5059 if (vcpu->arch.gpa_available &&
5060 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5061 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5062 gpa = vcpu->arch.gpa_val;
5063 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5064 } else {
5065 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5066 if (ret < 0)
5067 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5068 }
10589a46 5069
618232e2 5070 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5071 return X86EMUL_CONTINUE;
5072
bbd9b64e
CO		 5073 /*
5074 * Is this MMIO handled locally?
5075 */
22388a3c 5076 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5077 if (handled == bytes)
bbd9b64e 5078 return X86EMUL_CONTINUE;
bbd9b64e 5079
70252a10
AK		 5080 gpa += handled;
5081 bytes -= handled;
5082 val += handled;
5083
87da7e66
XG		 5084 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5085 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5086 frag->gpa = gpa;
5087 frag->data = val;
5088 frag->len = bytes;
f78146b0 5089 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5090}
5091
52eb5a6d
XL		 5092static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5093 unsigned long addr,
22388a3c
XG		 5094 void *val, unsigned int bytes,
5095 struct x86_exception *exception,
0fbe9b0b 5096 const struct read_write_emulator_ops *ops)
bbd9b64e 5097{
0f65dd70 5098 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5099 gpa_t gpa;
5100 int rc;
5101
5102 if (ops->read_write_prepare &&
5103 ops->read_write_prepare(vcpu, val, bytes))
5104 return X86EMUL_CONTINUE;
5105
5106 vcpu->mmio_nr_fragments = 0;
0f65dd70 5107
bbd9b64e
CO		 5108 /* Crossing a page boundary? */
5109 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5110 int now;
bbd9b64e
CO		 5111
5112 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5113 rc = emulator_read_write_onepage(addr, val, now, exception,
5114 vcpu, ops);
5115
bbd9b64e
CO		 5116 if (rc != X86EMUL_CONTINUE)
5117 return rc;
5118 addr += now;
bac15531
NA		 5119 if (ctxt->mode != X86EMUL_MODE_PROT64)
5120 addr = (u32)addr;
bbd9b64e
CO		 5121 val += now;
5122 bytes -= now;
5123 }
22388a3c 5124
f78146b0
AK		 5125 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5126 vcpu, ops);
5127 if (rc != X86EMUL_CONTINUE)
5128 return rc;
5129
5130 if (!vcpu->mmio_nr_fragments)
5131 return rc;
5132
5133 gpa = vcpu->mmio_fragments[0].gpa;
5134
5135 vcpu->mmio_needed = 1;
5136 vcpu->mmio_cur_fragment = 0;
5137
87da7e66 5138 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5139 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5140 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5141 vcpu->run->mmio.phys_addr = gpa;
5142
5143 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5144}
5145
5146static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5147 unsigned long addr,
5148 void *val,
5149 unsigned int bytes,
5150 struct x86_exception *exception)
5151{
5152 return emulator_read_write(ctxt, addr, val, bytes,
5153 exception, &read_emultor);
5154}
5155
52eb5a6d 5156static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5157 unsigned long addr,
5158 const void *val,
5159 unsigned int bytes,
5160 struct x86_exception *exception)
5161{
5162 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5163 exception, &write_emultor);
bbd9b64e 5164}
bbd9b64e 5165
daea3e73
AK		 5166#define CMPXCHG_TYPE(t, ptr, old, new) \
5167 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5168
5169#ifdef CONFIG_X86_64
5170# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5171#else
5172# define CMPXCHG64(ptr, old, new) \
9749a6c0 5173 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5174#endif
5175
0f65dd70
AK		 5176static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5177 unsigned long addr,
bbd9b64e
CO		 5178 const void *old,
5179 const void *new,
5180 unsigned int bytes,
0f65dd70 5181 struct x86_exception *exception)
bbd9b64e 5182{
0f65dd70 5183 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5184 gpa_t gpa;
5185 struct page *page;
5186 char *kaddr;
5187 bool exchanged;
2bacc55c 5188
daea3e73
AK		 5189 /* guests cmpxchg8b have to be emulated atomically */
5190 if (bytes > 8 || (bytes & (bytes - 1)))
5191 goto emul_write;
10589a46 5192
daea3e73 5193 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5194
daea3e73
AK		 5195 if (gpa == UNMAPPED_GVA ||
5196 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5197 goto emul_write;
2bacc55c 5198
daea3e73
AK		 5199 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5200 goto emul_write;
72dc67a6 5201
54bf36aa 5202 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5203 if (is_error_page(page))
c19b8bd6 5204 goto emul_write;
72dc67a6 5205
8fd75e12 5206 kaddr = kmap_atomic(page);
daea3e73
AK		 5207 kaddr += offset_in_page(gpa);
5208 switch (bytes) {
5209 case 1:
5210 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5211 break;
5212 case 2:
5213 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5214 break;
5215 case 4:
5216 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5217 break;
5218 case 8:
5219 exchanged = CMPXCHG64(kaddr, old, new);
5220 break;
5221 default:
5222 BUG();
2bacc55c 5223 }
8fd75e12 5224 kunmap_atomic(kaddr);
daea3e73
AK		 5225 kvm_release_page_dirty(page);
5226
5227 if (!exchanged)
5228 return X86EMUL_CMPXCHG_FAILED;
5229
54bf36aa 5230 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5231 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5232
5233 return X86EMUL_CONTINUE;
4a5f48f6 5234
3200f405 5235emul_write:
daea3e73 5236 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5237
0f65dd70 5238 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5239}
5240
cf8f70bf
GN		 5241static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5242{
cbfc6c91 5243 int r = 0, i;
cf8f70bf 5244
cbfc6c91
WL		 5245 for (i = 0; i < vcpu->arch.pio.count; i++) {
5246 if (vcpu->arch.pio.in)
5247 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5248 vcpu->arch.pio.size, pd);
5249 else
5250 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5251 vcpu->arch.pio.port, vcpu->arch.pio.size,
5252 pd);
5253 if (r)
5254 break;
5255 pd += vcpu->arch.pio.size;
5256 }
cf8f70bf
GN		 5257 return r;
5258}
5259
6f6fbe98
XG		 5260static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5261 unsigned short port, void *val,
5262 unsigned int count, bool in)
cf8f70bf 5263{
cf8f70bf 5264 vcpu->arch.pio.port = port;
6f6fbe98 5265 vcpu->arch.pio.in = in;
7972995b 5266 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5267 vcpu->arch.pio.size = size;
5268
5269 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5270 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5271 return 1;
5272 }
5273
5274 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5275 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5276 vcpu->run->io.size = size;
5277 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5278 vcpu->run->io.count = count;
5279 vcpu->run->io.port = port;
5280
5281 return 0;
5282}
5283
6f6fbe98
XG		 5284static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5285 int size, unsigned short port, void *val,
5286 unsigned int count)
cf8f70bf 5287{
ca1d4a9e 5288 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5289 int ret;
ca1d4a9e 5290
6f6fbe98
XG		 5291 if (vcpu->arch.pio.count)
5292 goto data_avail;
cf8f70bf 5293
cbfc6c91
WL		 5294 memset(vcpu->arch.pio_data, 0, size * count);
5295
6f6fbe98
XG		 5296 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5297 if (ret) {
5298data_avail:
5299 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5300 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5301 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5302 return 1;
5303 }
5304
cf8f70bf
GN		 5305 return 0;
5306}
5307
6f6fbe98
XG		 5308static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5309 int size, unsigned short port,
5310 const void *val, unsigned int count)
5311{
5312 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5313
5314 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5315 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5316 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5317}
5318
bbd9b64e
CO		 5319static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5320{
5321 return kvm_x86_ops->get_segment_base(vcpu, seg);
5322}
5323
3cb16fe7 5324static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5325{
3cb16fe7 5326 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5327}
5328
ae6a2375 5329static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5330{
5331 if (!need_emulate_wbinvd(vcpu))
5332 return X86EMUL_CONTINUE;
5333
5334 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5335 int cpu = get_cpu();
5336
5337 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5338 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5339 wbinvd_ipi, NULL, 1);
2eec7343 5340 put_cpu();
f5f48ee1 5341 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5342 } else
5343 wbinvd();
f5f48ee1
SY		 5344 return X86EMUL_CONTINUE;
5345}
5cb56059
JS		 5346
5347int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5348{
6affcbed
KH		 5349 kvm_emulate_wbinvd_noskip(vcpu);
5350 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5351}
f5f48ee1
SY		 5352EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5353
5cb56059
JS		 5354
5355
bcaf5cc5
AK		 5356static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5357{
5cb56059 5358 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5359}
5360
52eb5a6d
XL		 5361static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5362 unsigned long *dest)
bbd9b64e 5363{
16f8a6f9 5364 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5365}
5366
52eb5a6d
XL		 5367static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5368 unsigned long value)
bbd9b64e 5369{
338dbc97 5370
717746e3 5371 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5372}
5373
52a46617 5374static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5375{
52a46617 5376 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5377}
5378
717746e3 5379static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5380{
717746e3 5381 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5382 unsigned long value;
5383
5384 switch (cr) {
5385 case 0:
5386 value = kvm_read_cr0(vcpu);
5387 break;
5388 case 2:
5389 value = vcpu->arch.cr2;
5390 break;
5391 case 3:
9f8fe504 5392 value = kvm_read_cr3(vcpu);
52a46617
GN		 5393 break;
5394 case 4:
5395 value = kvm_read_cr4(vcpu);
5396 break;
5397 case 8:
5398 value = kvm_get_cr8(vcpu);
5399 break;
5400 default:
a737f256 5401 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5402 return 0;
5403 }
5404
5405 return value;
5406}
5407
717746e3 5408static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5409{
717746e3 5410 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5411 int res = 0;
5412
52a46617
GN		 5413 switch (cr) {
5414 case 0:
49a9b07e 5415 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5416 break;
5417 case 2:
5418 vcpu->arch.cr2 = val;
5419 break;
5420 case 3:
2390218b 5421 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5422 break;
5423 case 4:
a83b29c6 5424 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5425 break;
5426 case 8:
eea1cff9 5427 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5428 break;
5429 default:
a737f256 5430 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5431 res = -1;
52a46617 5432 }
0f12244f
GN		 5433
5434 return res;
52a46617
GN		 5435}
5436
717746e3 5437static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5438{
717746e3 5439 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5440}
5441
4bff1e86 5442static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5443{
4bff1e86 5444 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5445}
5446
4bff1e86 5447static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5448{
4bff1e86 5449 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5450}
5451
1ac9d0cf
AK		 5452static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5453{
5454 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5455}
5456
5457static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5458{
5459 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5460}
5461
4bff1e86
AK		 5462static unsigned long emulator_get_cached_segment_base(
5463 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5464{
4bff1e86 5465 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5466}
5467
1aa36616
AK		 5468static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5469 struct desc_struct *desc, u32 *base3,
5470 int seg)
2dafc6c2
GN		 5471{
5472 struct kvm_segment var;
5473
4bff1e86 5474 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5475 *selector = var.selector;
2dafc6c2 5476
378a8b09
GN		 5477 if (var.unusable) {
5478 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5479 if (base3)
5480 *base3 = 0;
2dafc6c2 5481 return false;
378a8b09 5482 }
2dafc6c2
GN		 5483
5484 if (var.g)
5485 var.limit >>= 12;
5486 set_desc_limit(desc, var.limit);
5487 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5488#ifdef CONFIG_X86_64
5489 if (base3)
5490 *base3 = var.base >> 32;
5491#endif
2dafc6c2
GN		 5492 desc->type = var.type;
5493 desc->s = var.s;
5494 desc->dpl = var.dpl;
5495 desc->p = var.present;
5496 desc->avl = var.avl;
5497 desc->l = var.l;
5498 desc->d = var.db;
5499 desc->g = var.g;
5500
5501 return true;
5502}
5503
1aa36616
AK		 5504static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5505 struct desc_struct *desc, u32 base3,
5506 int seg)
2dafc6c2 5507{
4bff1e86 5508 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5509 struct kvm_segment var;
5510
1aa36616 5511 var.selector = selector;
2dafc6c2 5512 var.base = get_desc_base(desc);
5601d05b
GN		 5513#ifdef CONFIG_X86_64
5514 var.base |= ((u64)base3) << 32;
5515#endif
2dafc6c2
GN		 5516 var.limit = get_desc_limit(desc);
5517 if (desc->g)
5518 var.limit = (var.limit << 12) | 0xfff;
5519 var.type = desc->type;
2dafc6c2
GN		 5520 var.dpl = desc->dpl;
5521 var.db = desc->d;
5522 var.s = desc->s;
5523 var.l = desc->l;
5524 var.g = desc->g;
5525 var.avl = desc->avl;
5526 var.present = desc->p;
5527 var.unusable = !var.present;
5528 var.padding = 0;
5529
5530 kvm_set_segment(vcpu, &var, seg);
5531 return;
5532}
5533
717746e3
AK		 5534static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5535 u32 msr_index, u64 *pdata)
5536{
609e36d3
PB		 5537 struct msr_data msr;
5538 int r;
5539
5540 msr.index = msr_index;
5541 msr.host_initiated = false;
5542 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5543 if (r)
5544 return r;
5545
5546 *pdata = msr.data;
5547 return 0;
717746e3
AK		 5548}
5549
5550static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5551 u32 msr_index, u64 data)
5552{
8fe8ab46
WA		 5553 struct msr_data msr;
5554
5555 msr.data = data;
5556 msr.index = msr_index;
5557 msr.host_initiated = false;
5558 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5559}
5560
64d60670
PB		 5561static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5562{
5563 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5564
5565 return vcpu->arch.smbase;
5566}
5567
5568static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5569{
5570 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5571
5572 vcpu->arch.smbase = smbase;
5573}
5574
67f4d428
NA		 5575static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5576 u32 pmc)
5577{
c6702c9d 5578 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5579}
5580
222d21aa
AK		 5581static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5582 u32 pmc, u64 *pdata)
5583{
c6702c9d 5584 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5585}
5586
6c3287f7
AK		 5587static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5588{
5589 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5590}
5591
2953538e 5592static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5593 struct x86_instruction_info *info,
c4f035c6
AK		 5594 enum x86_intercept_stage stage)
5595{
2953538e 5596 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5597}
5598
e911eb3b
YZ		 5599static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5600 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5601{
e911eb3b 5602 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5603}
5604
dd856efa
AK		 5605static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5606{
5607 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5608}
5609
5610static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5611{
5612 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5613}
5614
801806d9
NA		 5615static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5616{
5617 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5618}
5619
6ed071f0
LP		 5620static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5621{
5622 return emul_to_vcpu(ctxt)->arch.hflags;
5623}
5624
5625static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5626{
5627 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5628}
5629
0234bf88
LP		 5630static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5631{
5632 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5633}
5634
0225fb50 5635static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5636 .read_gpr = emulator_read_gpr,
5637 .write_gpr = emulator_write_gpr,
ce14e868
PB		 5638 .read_std = emulator_read_std,
5639 .write_std = emulator_write_std,
7a036a6f 5640 .read_phys = kvm_read_guest_phys_system,
1871c602 5641 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5642 .read_emulated = emulator_read_emulated,
5643 .write_emulated = emulator_write_emulated,
5644 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5645 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5646 .pio_in_emulated = emulator_pio_in_emulated,
5647 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5648 .get_segment = emulator_get_segment,
5649 .set_segment = emulator_set_segment,
5951c442 5650 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5651 .get_gdt = emulator_get_gdt,
160ce1f1 5652 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5653 .set_gdt = emulator_set_gdt,
5654 .set_idt = emulator_set_idt,
52a46617
GN		 5655 .get_cr = emulator_get_cr,
5656 .set_cr = emulator_set_cr,
9c537244 5657 .cpl = emulator_get_cpl,
35aa5375
GN		 5658 .get_dr = emulator_get_dr,
5659 .set_dr = emulator_set_dr,
64d60670
PB		 5660 .get_smbase = emulator_get_smbase,
5661 .set_smbase = emulator_set_smbase,
717746e3
AK		 5662 .set_msr = emulator_set_msr,
5663 .get_msr = emulator_get_msr,
67f4d428 5664 .check_pmc = emulator_check_pmc,
222d21aa 5665 .read_pmc = emulator_read_pmc,
6c3287f7 5666 .halt = emulator_halt,
bcaf5cc5 5667 .wbinvd = emulator_wbinvd,
d6aa1000 5668 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5669 .intercept = emulator_intercept,
bdb42f5a 5670 .get_cpuid = emulator_get_cpuid,
801806d9 5671 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5672 .get_hflags = emulator_get_hflags,
5673 .set_hflags = emulator_set_hflags,
0234bf88 5674 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5675};
5676
95cb2295
GN		 5677static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5678{
37ccdcbe 5679 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5680 /*
5681 * an sti; sti; sequence only disable interrupts for the first
5682 * instruction. So, if the last instruction, be it emulated or
5683 * not, left the system with the INT_STI flag enabled, it
5684 * means that the last instruction is an sti. We should not
5685 * leave the flag on in this case. The same goes for mov ss
5686 */
37ccdcbe
PB		 5687 if (int_shadow & mask)
5688 mask = 0;
6addfc42 5689 if (unlikely(int_shadow || mask)) {
95cb2295 5690 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5691 if (!mask)
5692 kvm_make_request(KVM_REQ_EVENT, vcpu);
5693 }
95cb2295
GN		 5694}
5695
ef54bcfe 5696static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5697{
5698 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5699 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5700 return kvm_propagate_fault(vcpu, &ctxt->exception);
5701
5702 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5703 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5704 ctxt->exception.error_code);
54b8486f 5705 else
da9cb575 5706 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5707 return false;
54b8486f
GN		 5708}
5709
8ec4722d
MG		 5710static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5711{
adf52235 5712 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5713 int cs_db, cs_l;
5714
8ec4722d
MG		 5715 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5716
adf52235 5717 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5718 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5719
adf52235
TY		 5720 ctxt->eip = kvm_rip_read(vcpu);
5721 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5722 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5723 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5724 cs_db ? X86EMUL_MODE_PROT32 :
5725 X86EMUL_MODE_PROT16;
a584539b 5726 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5727 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5728 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5729
dd856efa 5730 init_decode_cache(ctxt);
7ae441ea 5731 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5732}
5733
71f9833b 5734int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5735{
9d74191a 5736 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5737 int ret;
5738
5739 init_emulate_ctxt(vcpu);
5740
9dac77fa
AK		 5741 ctxt->op_bytes = 2;
5742 ctxt->ad_bytes = 2;
5743 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5744 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5745
5746 if (ret != X86EMUL_CONTINUE)
5747 return EMULATE_FAIL;
5748
9dac77fa 5749 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5750 kvm_rip_write(vcpu, ctxt->eip);
5751 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5752
63995653
MG		 5753 return EMULATE_DONE;
5754}
5755EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5756
e2366171 5757static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5758{
fc3a9157
JR		 5759 int r = EMULATE_DONE;
5760
6d77dbfc
GN		 5761 ++vcpu->stat.insn_emulation_fail;
5762 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5763
5764 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5765 return EMULATE_FAIL;
5766
a2b9e6c1 5767 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5768 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5769 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5770 vcpu->run->internal.ndata = 0;
1f4dcb3b 5771 r = EMULATE_USER_EXIT;
fc3a9157 5772 }
e2366171 5773
6d77dbfc 5774 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5775
5776 return r;
6d77dbfc
GN		 5777}
5778
93c05d3e 5779static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5780 bool write_fault_to_shadow_pgtable,
5781 int emulation_type)
a6f177ef 5782{
95b3cf69 5783 gpa_t gpa = cr2;
ba049e93 5784 kvm_pfn_t pfn;
a6f177ef 5785
991eebf9
GN		 5786 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5787 return false;
5788
95b3cf69
XG		 5789 if (!vcpu->arch.mmu.direct_map) {
5790 /*
5791 * Write permission should be allowed since only
5792 * write access need to be emulated.
5793 */
5794 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5795
95b3cf69
XG		 5796 /*
5797 * If the mapping is invalid in guest, let cpu retry
5798 * it to generate fault.
5799 */
5800 if (gpa == UNMAPPED_GVA)
5801 return true;
5802 }
a6f177ef 5803
8e3d9d06
XG		 5804 /*
5805 * Do not retry the unhandleable instruction if it faults on the
5806 * readonly host memory, otherwise it will goto a infinite loop:
5807 * retry instruction -> write #PF -> emulation fail -> retry
5808 * instruction -> ...
5809 */
5810 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5811
5812 /*
5813 * If the instruction failed on the error pfn, it can not be fixed,
5814 * report the error to userspace.
5815 */
5816 if (is_error_noslot_pfn(pfn))
5817 return false;
5818
5819 kvm_release_pfn_clean(pfn);
5820
5821 /* The instructions are well-emulated on direct mmu. */
5822 if (vcpu->arch.mmu.direct_map) {
5823 unsigned int indirect_shadow_pages;
5824
5825 spin_lock(&vcpu->kvm->mmu_lock);
5826 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5827 spin_unlock(&vcpu->kvm->mmu_lock);
5828
5829 if (indirect_shadow_pages)
5830 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5831
a6f177ef 5832 return true;
8e3d9d06 5833 }
a6f177ef 5834
95b3cf69
XG		 5835 /*
5836 * if emulation was due to access to shadowed page table
5837 * and it failed try to unshadow page and re-enter the
5838 * guest to let CPU execute the instruction.
5839 */
5840 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5841
5842 /*
5843 * If the access faults on its page table, it can not
5844 * be fixed by unprotecting shadow page and it should
5845 * be reported to userspace.
5846 */
5847 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5848}
5849
1cb3f3ae
XG		 5850static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5851 unsigned long cr2, int emulation_type)
5852{
5853 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5854 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5855
5856 last_retry_eip = vcpu->arch.last_retry_eip;
5857 last_retry_addr = vcpu->arch.last_retry_addr;
5858
5859 /*
5860 * If the emulation is caused by #PF and it is non-page_table
5861 * writing instruction, it means the VM-EXIT is caused by shadow
5862 * page protected, we can zap the shadow page and retry this
5863 * instruction directly.
5864 *
5865 * Note: if the guest uses a non-page-table modifying instruction
5866 * on the PDE that points to the instruction, then we will unmap
5867 * the instruction and go to an infinite loop. So, we cache the
5868 * last retried eip and the last fault address, if we meet the eip
5869 * and the address again, we can break out of the potential infinite
5870 * loop.
5871 */
5872 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5873
5874 if (!(emulation_type & EMULTYPE_RETRY))
5875 return false;
5876
5877 if (x86_page_table_writing_insn(ctxt))
5878 return false;
5879
5880 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5881 return false;
5882
5883 vcpu->arch.last_retry_eip = ctxt->eip;
5884 vcpu->arch.last_retry_addr = cr2;
5885
5886 if (!vcpu->arch.mmu.direct_map)
5887 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5888
22368028 5889 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5890
5891 return true;
5892}
5893
716d51ab
GN		 5894static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5895static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5896
64d60670 5897static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5898{
64d60670 5899 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5900 /* This is a good place to trace that we are exiting SMM. */
5901 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5902
c43203ca
PB		 5903 /* Process a latched INIT or SMI, if any. */
5904 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5905 }
699023e2
PB		 5906
5907 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5908}
5909
5910static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5911{
5912 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5913
a584539b 5914 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5915
5916 if (changed & HF_SMM_MASK)
5917 kvm_smm_changed(vcpu);
a584539b
PB		 5918}
5919
4a1e10d5
PB		 5920static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5921 unsigned long *db)
5922{
5923 u32 dr6 = 0;
5924 int i;
5925 u32 enable, rwlen;
5926
5927 enable = dr7;
5928 rwlen = dr7 >> 16;
5929 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5930 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5931 dr6 |= (1 << i);
5932 return dr6;
5933}
5934
c8401dda 5935static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5936{
5937 struct kvm_run *kvm_run = vcpu->run;
5938
c8401dda
PB		 5939 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5940 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5941 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5942 kvm_run->debug.arch.exception = DB_VECTOR;
5943 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5944 *r = EMULATE_USER_EXIT;
5945 } else {
5946 /*
5947 * "Certain debug exceptions may clear bit 0-3. The
5948 * remaining contents of the DR6 register are never
5949 * cleared by the processor".
5950 */
5951 vcpu->arch.dr6 &= ~15;
5952 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5953 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5954 }
5955}
5956
6affcbed
KH		 5957int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5958{
5959 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5960 int r = EMULATE_DONE;
5961
5962 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5963
5964 /*
5965 * rflags is the old, "raw" value of the flags. The new value has
5966 * not been saved yet.
5967 *
5968 * This is correct even for TF set by the guest, because "the
5969 * processor will not generate this exception after the instruction
5970 * that sets the TF flag".
5971 */
5972 if (unlikely(rflags & X86_EFLAGS_TF))
5973 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5974 return r == EMULATE_DONE;
5975}
5976EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5977
4a1e10d5
PB		 5978static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5979{
4a1e10d5
PB		 5980 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5981 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5982 struct kvm_run *kvm_run = vcpu->run;
5983 unsigned long eip = kvm_get_linear_rip(vcpu);
5984 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5985 vcpu->arch.guest_debug_dr7,
5986 vcpu->arch.eff_db);
5987
5988 if (dr6 != 0) {
6f43ed01 5989 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5990 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5991 kvm_run->debug.arch.exception = DB_VECTOR;
5992 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5993 *r = EMULATE_USER_EXIT;
5994 return true;
5995 }
5996 }
5997
4161a569
NA		 5998 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5999 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6000 unsigned long eip = kvm_get_linear_rip(vcpu);
6001 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6002 vcpu->arch.dr7,
6003 vcpu->arch.db);
6004
6005 if (dr6 != 0) {
6006 vcpu->arch.dr6 &= ~15;
6f43ed01 6007 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6008 kvm_queue_exception(vcpu, DB_VECTOR);
6009 *r = EMULATE_DONE;
6010 return true;
6011 }
6012 }
6013
6014 return false;
6015}
6016
04789b66
LA		 6017static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6018{
2d7921c4
AM		 6019 switch (ctxt->opcode_len) {
6020 case 1:
6021 switch (ctxt->b) {
6022 case 0xe4: /* IN */
6023 case 0xe5:
6024 case 0xec:
6025 case 0xed:
6026 case 0xe6: /* OUT */
6027 case 0xe7:
6028 case 0xee:
6029 case 0xef:
6030 case 0x6c: /* INS */
6031 case 0x6d:
6032 case 0x6e: /* OUTS */
6033 case 0x6f:
6034 return true;
6035 }
6036 break;
6037 case 2:
6038 switch (ctxt->b) {
6039 case 0x33: /* RDPMC */
6040 return true;
6041 }
6042 break;
04789b66
LA		 6043 }
6044
6045 return false;
6046}
6047
51d8b661
AP		 6048int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6049 unsigned long cr2,
dc25e89e
AP		 6050 int emulation_type,
6051 void *insn,
6052 int insn_len)
bbd9b64e 6053{
95cb2295 6054 int r;
9d74191a 6055 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6056 bool writeback = true;
93c05d3e 6057 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6058
c595ceee
PB		 6059 vcpu->arch.l1tf_flush_l1d = true;
6060
93c05d3e
XG		 6061 /*
6062 * Clear write_fault_to_shadow_pgtable here to ensure it is
6063 * never reused.
6064 */
6065 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6066 kvm_clear_exception_queue(vcpu);
8d7d8102 6067
571008da 6068 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6069 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6070
6071 /*
6072 * We will reenter on the same instruction since
6073 * we do not set complete_userspace_io. This does not
6074 * handle watchpoints yet, those would be handled in
6075 * the emulate_ops.
6076 */
d391f120
VK		 6077 if (!(emulation_type & EMULTYPE_SKIP) &&
6078 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6079 return r;
6080
9d74191a
TY		 6081 ctxt->interruptibility = 0;
6082 ctxt->have_exception = false;
e0ad0b47 6083 ctxt->exception.vector = -1;
9d74191a 6084 ctxt->perm_ok = false;
bbd9b64e 6085
b51e974f 6086 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6087
9d74191a 6088 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6089
e46479f8 6090 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6091 ++vcpu->stat.insn_emulation;
1d2887e2 6092 if (r != EMULATION_OK) {
4005996e
AK		 6093 if (emulation_type & EMULTYPE_TRAP_UD)
6094 return EMULATE_FAIL;
991eebf9
GN		 6095 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6096 emulation_type))
bbd9b64e 6097 return EMULATE_DONE;
6ea6e843
PB		 6098 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6099 return EMULATE_DONE;
6d77dbfc
GN		 6100 if (emulation_type & EMULTYPE_SKIP)
6101 return EMULATE_FAIL;
e2366171 6102 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6103 }
6104 }
6105
04789b66
LA		 6106 if ((emulation_type & EMULTYPE_VMWARE) &&
6107 !is_vmware_backdoor_opcode(ctxt))
6108 return EMULATE_FAIL;
6109
ba8afb6b 6110 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6111 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6112 if (ctxt->eflags & X86_EFLAGS_RF)
6113 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6114 return EMULATE_DONE;
6115 }
6116
1cb3f3ae
XG		 6117 if (retry_instruction(ctxt, cr2, emulation_type))
6118 return EMULATE_DONE;
6119
7ae441ea 6120 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6121 changes registers values during IO operation */
7ae441ea
GN		 6122 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6123 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6124 emulator_invalidate_register_cache(ctxt);
7ae441ea 6125 }
4d2179e1 6126
5cd21917 6127restart:
0f89b207
TL		 6128 /* Save the faulting GPA (cr2) in the address field */
6129 ctxt->exception.address = cr2;
6130
9d74191a 6131 r = x86_emulate_insn(ctxt);
bbd9b64e 6132
775fde86
JR		 6133 if (r == EMULATION_INTERCEPTED)
6134 return EMULATE_DONE;
6135
d2ddd1c4 6136 if (r == EMULATION_FAILED) {
991eebf9
GN		 6137 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6138 emulation_type))
c3cd7ffa
GN		 6139 return EMULATE_DONE;
6140
e2366171 6141 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6142 }
6143
9d74191a 6144 if (ctxt->have_exception) {
d2ddd1c4 6145 r = EMULATE_DONE;
ef54bcfe
PB		 6146 if (inject_emulated_exception(vcpu))
6147 return r;
d2ddd1c4 6148 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6149 if (!vcpu->arch.pio.in) {
6150 /* FIXME: return into emulator if single-stepping. */
3457e419 6151 vcpu->arch.pio.count = 0;
0912c977 6152 } else {
7ae441ea 6153 writeback = false;
716d51ab
GN		 6154 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6155 }
ac0a48c3 6156 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6157 } else if (vcpu->mmio_needed) {
6158 if (!vcpu->mmio_is_write)
6159 writeback = false;
ac0a48c3 6160 r = EMULATE_USER_EXIT;
716d51ab 6161 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6162 } else if (r == EMULATION_RESTART)
5cd21917 6163 goto restart;
d2ddd1c4
GN		 6164 else
6165 r = EMULATE_DONE;
f850e2e6 6166
7ae441ea 6167 if (writeback) {
6addfc42 6168 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6169 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6170 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6171 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6172 if (r == EMULATE_DONE &&
6173 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6174 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6175 if (!ctxt->have_exception ||
6176 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6177 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6178
6179 /*
6180 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6181 * do nothing, and it will be requested again as soon as
6182 * the shadow expires. But we still need to check here,
6183 * because POPF has no interrupt shadow.
6184 */
6185 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6186 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6187 } else
6188 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6189
6190 return r;
de7d789a 6191}
51d8b661 6192EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6193
dca7f128
SC		 6194static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6195 unsigned short port)
de7d789a 6196{
cf8f70bf 6197 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6198 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6199 size, port, &val, 1);
cf8f70bf 6200 /* do not return to emulator after return from userspace */
7972995b 6201 vcpu->arch.pio.count = 0;
de7d789a
CO		 6202 return ret;
6203}
de7d789a 6204
8370c3d0
TL		 6205static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6206{
6207 unsigned long val;
6208
6209 /* We should only ever be called with arch.pio.count equal to 1 */
6210 BUG_ON(vcpu->arch.pio.count != 1);
6211
6212 /* For size less than 4 we merge, else we zero extend */
6213 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6214 : 0;
6215
6216 /*
6217 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6218 * the copy and tracing
6219 */
6220 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6221 vcpu->arch.pio.port, &val, 1);
6222 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6223
6224 return 1;
6225}
6226
dca7f128
SC		 6227static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6228 unsigned short port)
8370c3d0
TL		 6229{
6230 unsigned long val;
6231 int ret;
6232
6233 /* For size less than 4 we merge, else we zero extend */
6234 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6235
6236 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6237 &val, 1);
6238 if (ret) {
6239 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6240 return ret;
6241 }
6242
6243 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6244
6245 return 0;
6246}
dca7f128
SC		 6247
6248int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6249{
6250 int ret = kvm_skip_emulated_instruction(vcpu);
6251
6252 /*
6253 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6254 * KVM_EXIT_DEBUG here.
6255 */
6256 if (in)
6257 return kvm_fast_pio_in(vcpu, size, port) && ret;
6258 else
6259 return kvm_fast_pio_out(vcpu, size, port) && ret;
6260}
6261EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6262
251a5fd6 6263static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6264{
0a3aee0d 6265 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6266 return 0;
8cfdc000
ZA		 6267}
6268
6269static void tsc_khz_changed(void *data)
c8076604 6270{
8cfdc000
ZA		 6271 struct cpufreq_freqs *freq = data;
6272 unsigned long khz = 0;
6273
6274 if (data)
6275 khz = freq->new;
6276 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6277 khz = cpufreq_quick_get(raw_smp_processor_id());
6278 if (!khz)
6279 khz = tsc_khz;
0a3aee0d 6280 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6281}
6282
5fa4ec9c 6283#ifdef CONFIG_X86_64
0092e434
VK		 6284static void kvm_hyperv_tsc_notifier(void)
6285{
0092e434
VK		 6286 struct kvm *kvm;
6287 struct kvm_vcpu *vcpu;
6288 int cpu;
6289
6290 spin_lock(&kvm_lock);
6291 list_for_each_entry(kvm, &vm_list, vm_list)
6292 kvm_make_mclock_inprogress_request(kvm);
6293
6294 hyperv_stop_tsc_emulation();
6295
6296 /* TSC frequency always matches when on Hyper-V */
6297 for_each_present_cpu(cpu)
6298 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6299 kvm_max_guest_tsc_khz = tsc_khz;
6300
6301 list_for_each_entry(kvm, &vm_list, vm_list) {
6302 struct kvm_arch *ka = &kvm->arch;
6303
6304 spin_lock(&ka->pvclock_gtod_sync_lock);
6305
6306 pvclock_update_vm_gtod_copy(kvm);
6307
6308 kvm_for_each_vcpu(cpu, vcpu, kvm)
6309 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6310
6311 kvm_for_each_vcpu(cpu, vcpu, kvm)
6312 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6313
6314 spin_unlock(&ka->pvclock_gtod_sync_lock);
6315 }
6316 spin_unlock(&kvm_lock);
0092e434 6317}
5fa4ec9c 6318#endif
0092e434 6319
c8076604
GH		 6320static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6321 void *data)
6322{
6323 struct cpufreq_freqs *freq = data;
6324 struct kvm *kvm;
6325 struct kvm_vcpu *vcpu;
6326 int i, send_ipi = 0;
6327
8cfdc000
ZA		 6328 /*
6329 * We allow guests to temporarily run on slowing clocks,
6330 * provided we notify them after, or to run on accelerating
6331 * clocks, provided we notify them before. Thus time never
6332 * goes backwards.
6333 *
6334 * However, we have a problem. We can't atomically update
6335 * the frequency of a given CPU from this function; it is
6336 * merely a notifier, which can be called from any CPU.
6337 * Changing the TSC frequency at arbitrary points in time
6338 * requires a recomputation of local variables related to
6339 * the TSC for each VCPU. We must flag these local variables
6340 * to be updated and be sure the update takes place with the
6341 * new frequency before any guests proceed.
6342 *
6343 * Unfortunately, the combination of hotplug CPU and frequency
6344 * change creates an intractable locking scenario; the order
6345 * of when these callouts happen is undefined with respect to
6346 * CPU hotplug, and they can race with each other. As such,
6347 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6348 * undefined; you can actually have a CPU frequency change take
6349 * place in between the computation of X and the setting of the
6350 * variable. To protect against this problem, all updates of
6351 * the per_cpu tsc_khz variable are done in an interrupt
6352 * protected IPI, and all callers wishing to update the value
6353 * must wait for a synchronous IPI to complete (which is trivial
6354 * if the caller is on the CPU already). This establishes the
6355 * necessary total order on variable updates.
6356 *
6357 * Note that because a guest time update may take place
6358 * anytime after the setting of the VCPU's request bit, the
6359 * correct TSC value must be set before the request. However,
6360 * to ensure the update actually makes it to any guest which
6361 * starts running in hardware virtualization between the set
6362 * and the acquisition of the spinlock, we must also ping the
6363 * CPU after setting the request bit.
6364 *
6365 */
6366
c8076604
GH		 6367 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6368 return 0;
6369 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6370 return 0;
8cfdc000
ZA		 6371
6372 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6373
2f303b74 6374 spin_lock(&kvm_lock);
c8076604 6375 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6376 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6377 if (vcpu->cpu != freq->cpu)
6378 continue;
c285545f 6379 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6380 if (vcpu->cpu != smp_processor_id())
8cfdc000 6381 send_ipi = 1;
c8076604
GH		 6382 }
6383 }
2f303b74 6384 spin_unlock(&kvm_lock);
c8076604
GH		 6385
6386 if (freq->old < freq->new && send_ipi) {
6387 /*
6388 * We upscale the frequency. Must make the guest
6389 * doesn't see old kvmclock values while running with
6390 * the new frequency, otherwise we risk the guest sees
6391 * time go backwards.
6392 *
6393 * In case we update the frequency for another cpu
6394 * (which might be in guest context) send an interrupt
6395 * to kick the cpu out of guest context. Next time
6396 * guest context is entered kvmclock will be updated,
6397 * so the guest will not see stale values.
6398 */
8cfdc000 6399 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6400 }
6401 return 0;
6402}
6403
6404static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6405 .notifier_call = kvmclock_cpufreq_notifier
6406};
6407
251a5fd6 6408static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6409{
251a5fd6
SAS		 6410 tsc_khz_changed(NULL);
6411 return 0;
8cfdc000
ZA		 6412}
6413
b820cc0c
ZA		 6414static void kvm_timer_init(void)
6415{
c285545f 6416 max_tsc_khz = tsc_khz;
460dd42e 6417
b820cc0c 6418 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6419#ifdef CONFIG_CPU_FREQ
6420 struct cpufreq_policy policy;
758f588d
BP		 6421 int cpu;
6422
c285545f 6423 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6424 cpu = get_cpu();
6425 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6426 if (policy.cpuinfo.max_freq)
6427 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6428 put_cpu();
c285545f 6429#endif
b820cc0c
ZA		 6430 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6431 CPUFREQ_TRANSITION_NOTIFIER);
6432 }
c285545f 6433 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6434
73c1b41e 6435 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6436 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6437}
6438
dd60d217
AK		 6439DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6440EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6441
f5132b01 6442int kvm_is_in_guest(void)
ff9d07a0 6443{
086c9855 6444 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6445}
6446
6447static int kvm_is_user_mode(void)
6448{
6449 int user_mode = 3;
dcf46b94 6450
086c9855
AS		 6451 if (__this_cpu_read(current_vcpu))
6452 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6453
ff9d07a0
ZY		 6454 return user_mode != 0;
6455}
6456
6457static unsigned long kvm_get_guest_ip(void)
6458{
6459 unsigned long ip = 0;
dcf46b94 6460
086c9855
AS		 6461 if (__this_cpu_read(current_vcpu))
6462 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6463
ff9d07a0
ZY		 6464 return ip;
6465}
6466
6467static struct perf_guest_info_callbacks kvm_guest_cbs = {
6468 .is_in_guest = kvm_is_in_guest,
6469 .is_user_mode = kvm_is_user_mode,
6470 .get_guest_ip = kvm_get_guest_ip,
6471};
6472
ce88decf
XG		 6473static void kvm_set_mmio_spte_mask(void)
6474{
6475 u64 mask;
6476 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6477
6478 /*
6479 * Set the reserved bits and the present bit of an paging-structure
6480 * entry to generate page fault with PFER.RSV = 1.
6481 */
885032b9 6482 /* Mask the reserved physical address bits. */
d1431483 6483 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6484
885032b9 6485 /* Set the present bit. */
ce88decf
XG		 6486 mask |= 1ull;
6487
6488#ifdef CONFIG_X86_64
6489 /*
6490 * If reserved bit is not supported, clear the present bit to disable
6491 * mmio page fault.
6492 */
6493 if (maxphyaddr == 52)
6494 mask &= ~1ull;
6495#endif
6496
dcdca5fe 6497 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6498}
6499
16e8d74d
MT		 6500#ifdef CONFIG_X86_64
6501static void pvclock_gtod_update_fn(struct work_struct *work)
6502{
d828199e
MT		 6503 struct kvm *kvm;
6504
6505 struct kvm_vcpu *vcpu;
6506 int i;
6507
2f303b74 6508 spin_lock(&kvm_lock);
d828199e
MT		 6509 list_for_each_entry(kvm, &vm_list, vm_list)
6510 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6511 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6512 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6513 spin_unlock(&kvm_lock);
16e8d74d
MT		 6514}
6515
6516static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6517
6518/*
6519 * Notification about pvclock gtod data update.
6520 */
6521static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6522 void *priv)
6523{
6524 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6525 struct timekeeper *tk = priv;
6526
6527 update_pvclock_gtod(tk);
6528
6529 /* disable master clock if host does not trust, or does not
b0c39dc6 6530 * use, TSC based clocksource.
16e8d74d 6531 */
b0c39dc6 6532 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6533 atomic_read(&kvm_guest_has_master_clock) != 0)
6534 queue_work(system_long_wq, &pvclock_gtod_work);
6535
6536 return 0;
6537}
6538
6539static struct notifier_block pvclock_gtod_notifier = {
6540 .notifier_call = pvclock_gtod_notify,
6541};
6542#endif
6543
f8c16bba 6544int kvm_arch_init(void *opaque)
043405e1 6545{
b820cc0c 6546 int r;
6b61edf7 6547 struct kvm_x86_ops *ops = opaque;
f8c16bba 6548
f8c16bba
ZX		 6549 if (kvm_x86_ops) {
6550 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6551 r = -EEXIST;
6552 goto out;
f8c16bba
ZX		 6553 }
6554
6555 if (!ops->cpu_has_kvm_support()) {
6556 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6557 r = -EOPNOTSUPP;
6558 goto out;
f8c16bba
ZX		 6559 }
6560 if (ops->disabled_by_bios()) {
6561 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6562 r = -EOPNOTSUPP;
6563 goto out;
f8c16bba
ZX		 6564 }
6565
013f6a5d
MT		 6566 r = -ENOMEM;
6567 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6568 if (!shared_msrs) {
6569 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6570 goto out;
6571 }
6572
97db56ce
AK		 6573 r = kvm_mmu_module_init();
6574 if (r)
013f6a5d 6575 goto out_free_percpu;
97db56ce 6576
ce88decf 6577 kvm_set_mmio_spte_mask();
97db56ce 6578
f8c16bba 6579 kvm_x86_ops = ops;
920c8377 6580
7b52345e 6581 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6582 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6583 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6584 kvm_timer_init();
c8076604 6585
ff9d07a0
ZY		 6586 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6587
d366bf7e 6588 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6589 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6590
c5cc421b 6591 kvm_lapic_init();
16e8d74d
MT		 6592#ifdef CONFIG_X86_64
6593 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6594
5fa4ec9c 6595 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6596 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6597#endif
6598
f8c16bba 6599 return 0;
56c6d28a 6600
013f6a5d
MT		 6601out_free_percpu:
6602 free_percpu(shared_msrs);
56c6d28a 6603out:
56c6d28a 6604 return r;
043405e1 6605}
8776e519 6606
f8c16bba
ZX		 6607void kvm_arch_exit(void)
6608{
0092e434 6609#ifdef CONFIG_X86_64
5fa4ec9c 6610 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6611 clear_hv_tscchange_cb();
6612#endif
cef84c30 6613 kvm_lapic_exit();
ff9d07a0
ZY		 6614 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6615
888d256e
JK		 6616 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6617 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6618 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6619 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6620#ifdef CONFIG_X86_64
6621 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6622#endif
f8c16bba 6623 kvm_x86_ops = NULL;
56c6d28a 6624 kvm_mmu_module_exit();
013f6a5d 6625 free_percpu(shared_msrs);
56c6d28a 6626}
f8c16bba 6627
5cb56059 6628int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6629{
6630 ++vcpu->stat.halt_exits;
35754c98 6631 if (lapic_in_kernel(vcpu)) {
a4535290 6632 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6633 return 1;
6634 } else {
6635 vcpu->run->exit_reason = KVM_EXIT_HLT;
6636 return 0;
6637 }
6638}
5cb56059
JS		 6639EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6640
6641int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6642{
6affcbed
KH		 6643 int ret = kvm_skip_emulated_instruction(vcpu);
6644 /*
6645 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6646 * KVM_EXIT_DEBUG here.
6647 */
6648 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6649}
8776e519
HB		 6650EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6651
8ef81a9a 6652#ifdef CONFIG_X86_64
55dd00a7
MT		 6653static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6654 unsigned long clock_type)
6655{
6656 struct kvm_clock_pairing clock_pairing;
899a31f5 6657 struct timespec64 ts;
80fbd89c 6658 u64 cycle;
55dd00a7
MT		 6659 int ret;
6660
6661 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6662 return -KVM_EOPNOTSUPP;
6663
6664 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6665 return -KVM_EOPNOTSUPP;
6666
6667 clock_pairing.sec = ts.tv_sec;
6668 clock_pairing.nsec = ts.tv_nsec;
6669 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6670 clock_pairing.flags = 0;
6671
6672 ret = 0;
6673 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6674 sizeof(struct kvm_clock_pairing)))
6675 ret = -KVM_EFAULT;
6676
6677 return ret;
6678}
8ef81a9a 6679#endif
55dd00a7 6680
6aef266c
SV		 6681/*
6682 * kvm_pv_kick_cpu_op: Kick a vcpu.
6683 *
6684 * @apicid - apicid of vcpu to be kicked.
6685 */
6686static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6687{
24d2166b 6688 struct kvm_lapic_irq lapic_irq;
6aef266c 6689
24d2166b
R		 6690 lapic_irq.shorthand = 0;
6691 lapic_irq.dest_mode = 0;
ebd28fcb 6692 lapic_irq.level = 0;
24d2166b 6693 lapic_irq.dest_id = apicid;
93bbf0b8 6694 lapic_irq.msi_redir_hint = false;
6aef266c 6695
24d2166b 6696 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6697 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6698}
6699
d62caabb
AS		 6700void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6701{
6702 vcpu->arch.apicv_active = false;
6703 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6704}
6705
8776e519
HB		 6706int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6707{
6708 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6709 int op_64_bit;
8776e519 6710
696ca779
RK		 6711 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6712 return kvm_hv_hypercall(vcpu);
55cd8e5a 6713
5fdbf976
MT		 6714 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6715 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6716 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6717 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6718 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6719
229456fc 6720 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6721
a449c7aa
NA		 6722 op_64_bit = is_64_bit_mode(vcpu);
6723 if (!op_64_bit) {
8776e519
HB		 6724 nr &= 0xFFFFFFFF;
6725 a0 &= 0xFFFFFFFF;
6726 a1 &= 0xFFFFFFFF;
6727 a2 &= 0xFFFFFFFF;
6728 a3 &= 0xFFFFFFFF;
6729 }
6730
07708c4a
JK		 6731 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6732 ret = -KVM_EPERM;
696ca779 6733 goto out;
07708c4a
JK		 6734 }
6735
8776e519 6736 switch (nr) {
b93463aa
AK		 6737 case KVM_HC_VAPIC_POLL_IRQ:
6738 ret = 0;
6739 break;
6aef266c
SV		 6740 case KVM_HC_KICK_CPU:
6741 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6742 ret = 0;
6743 break;
8ef81a9a 6744#ifdef CONFIG_X86_64
55dd00a7
MT		 6745 case KVM_HC_CLOCK_PAIRING:
6746 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6747 break;
8ef81a9a 6748#endif
8776e519
HB		 6749 default:
6750 ret = -KVM_ENOSYS;
6751 break;
6752 }
696ca779 6753out:
a449c7aa
NA		 6754 if (!op_64_bit)
6755 ret = (u32)ret;
5fdbf976 6756 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 6757
f11c3a8d 6758 ++vcpu->stat.hypercalls;
6356ee0c 6759 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 6760}
6761EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6762
b6785def 6763static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6764{
d6aa1000 6765 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6766 char instruction[3];
5fdbf976 6767 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6768
8776e519 6769 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6770
ce2e852e
DV		 6771 return emulator_write_emulated(ctxt, rip, instruction, 3,
6772 &ctxt->exception);
8776e519
HB		 6773}
6774
851ba692 6775static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6776{
782d422b
MG		 6777 return vcpu->run->request_interrupt_window &&
6778 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6779}
6780
851ba692 6781static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6782{
851ba692
AK		 6783 struct kvm_run *kvm_run = vcpu->run;
6784
91586a3b 6785 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6786 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6787 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6788 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6789 kvm_run->ready_for_interrupt_injection =
6790 pic_in_kernel(vcpu->kvm) ||
782d422b 6791 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6792}
6793
95ba8273
GN		 6794static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6795{
6796 int max_irr, tpr;
6797
6798 if (!kvm_x86_ops->update_cr8_intercept)
6799 return;
6800
bce87cce 6801 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6802 return;
6803
d62caabb
AS		 6804 if (vcpu->arch.apicv_active)
6805 return;
6806
8db3baa2
GN		 6807 if (!vcpu->arch.apic->vapic_addr)
6808 max_irr = kvm_lapic_find_highest_irr(vcpu);
6809 else
6810 max_irr = -1;
95ba8273
GN		 6811
6812 if (max_irr != -1)
6813 max_irr >>= 4;
6814
6815 tpr = kvm_lapic_get_cr8(vcpu);
6816
6817 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6818}
6819
b6b8a145 6820static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6821{
b6b8a145
JK		 6822 int r;
6823
95ba8273 6824 /* try to reinject previous events if any */
664f8e26 6825
1a680e35
LA		 6826 if (vcpu->arch.exception.injected)
6827 kvm_x86_ops->queue_exception(vcpu);
664f8e26 6828 /*
a042c26f
LA		 6829 * Do not inject an NMI or interrupt if there is a pending
6830 * exception. Exceptions and interrupts are recognized at
6831 * instruction boundaries, i.e. the start of an instruction.
6832 * Trap-like exceptions, e.g. #DB, have higher priority than
6833 * NMIs and interrupts, i.e. traps are recognized before an
6834 * NMI/interrupt that's pending on the same instruction.
6835 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
6836 * priority, but are only generated (pended) during instruction
6837 * execution, i.e. a pending fault-like exception means the
6838 * fault occurred on the *previous* instruction and must be
6839 * serviced prior to recognizing any new events in order to
6840 * fully complete the previous instruction.
664f8e26 6841 */
1a680e35
LA		 6842 else if (!vcpu->arch.exception.pending) {
6843 if (vcpu->arch.nmi_injected)
664f8e26 6844 kvm_x86_ops->set_nmi(vcpu);
1a680e35 6845 else if (vcpu->arch.interrupt.injected)
664f8e26 6846 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 6847 }
6848
1a680e35
LA		 6849 /*
6850 * Call check_nested_events() even if we reinjected a previous event
6851 * in order for caller to determine if it should require immediate-exit
6852 * from L2 to L1 due to pending L1 events which require exit
6853 * from L2 to L1.
6854 */
664f8e26
WL		 6855 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6856 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6857 if (r != 0)
6858 return r;
6859 }
6860
6861 /* try to inject new event if pending */
b59bb7bd 6862 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6863 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6864 vcpu->arch.exception.has_error_code,
6865 vcpu->arch.exception.error_code);
d6e8c854 6866
1a680e35 6867 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 6868 vcpu->arch.exception.pending = false;
6869 vcpu->arch.exception.injected = true;
6870
d6e8c854
NA		 6871 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6872 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6873 X86_EFLAGS_RF);
6874
6bdf0662
NA		 6875 if (vcpu->arch.exception.nr == DB_VECTOR &&
6876 (vcpu->arch.dr7 & DR7_GD)) {
6877 vcpu->arch.dr7 &= ~DR7_GD;
6878 kvm_update_dr7(vcpu);
6879 }
6880
cfcd20e5 6881 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 6882 }
6883
6884 /* Don't consider new event if we re-injected an event */
6885 if (kvm_event_needs_reinjection(vcpu))
6886 return 0;
6887
6888 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
6889 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6890 vcpu->arch.smi_pending = false;
52797bf9 6891 ++vcpu->arch.smi_count;
ee2cd4b7 6892 enter_smm(vcpu);
c43203ca 6893 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6894 --vcpu->arch.nmi_pending;
6895 vcpu->arch.nmi_injected = true;
6896 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6897 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6898 /*
6899 * Because interrupts can be injected asynchronously, we are
6900 * calling check_nested_events again here to avoid a race condition.
6901 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6902 * proposal and current concerns. Perhaps we should be setting
6903 * KVM_REQ_EVENT only on certain events and not unconditionally?
6904 */
6905 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6906 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6907 if (r != 0)
6908 return r;
6909 }
95ba8273 6910 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6911 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6912 false);
6913 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6914 }
6915 }
ee2cd4b7 6916
b6b8a145 6917 return 0;
95ba8273
GN		 6918}
6919
7460fb4a
AK		 6920static void process_nmi(struct kvm_vcpu *vcpu)
6921{
6922 unsigned limit = 2;
6923
6924 /*
6925 * x86 is limited to one NMI running, and one NMI pending after it.
6926 * If an NMI is already in progress, limit further NMIs to just one.
6927 * Otherwise, allow two (and we'll inject the first one immediately).
6928 */
6929 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6930 limit = 1;
6931
6932 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6933 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6934 kvm_make_request(KVM_REQ_EVENT, vcpu);
6935}
6936
ee2cd4b7 6937static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6938{
6939 u32 flags = 0;
6940 flags |= seg->g << 23;
6941 flags |= seg->db << 22;
6942 flags |= seg->l << 21;
6943 flags |= seg->avl << 20;
6944 flags |= seg->present << 15;
6945 flags |= seg->dpl << 13;
6946 flags |= seg->s << 12;
6947 flags |= seg->type << 8;
6948 return flags;
6949}
6950
ee2cd4b7 6951static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6952{
6953 struct kvm_segment seg;
6954 int offset;
6955
6956 kvm_get_segment(vcpu, &seg, n);
6957 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6958
6959 if (n < 3)
6960 offset = 0x7f84 + n * 12;
6961 else
6962 offset = 0x7f2c + (n - 3) * 12;
6963
6964 put_smstate(u32, buf, offset + 8, seg.base);
6965 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6966 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6967}
6968
efbb288a 6969#ifdef CONFIG_X86_64
ee2cd4b7 6970static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6971{
6972 struct kvm_segment seg;
6973 int offset;
6974 u16 flags;
6975
6976 kvm_get_segment(vcpu, &seg, n);
6977 offset = 0x7e00 + n * 16;
6978
ee2cd4b7 6979 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6980 put_smstate(u16, buf, offset, seg.selector);
6981 put_smstate(u16, buf, offset + 2, flags);
6982 put_smstate(u32, buf, offset + 4, seg.limit);
6983 put_smstate(u64, buf, offset + 8, seg.base);
6984}
efbb288a 6985#endif
660a5d51 6986
ee2cd4b7 6987static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6988{
6989 struct desc_ptr dt;
6990 struct kvm_segment seg;
6991 unsigned long val;
6992 int i;
6993
6994 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6995 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6996 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6997 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6998
6999 for (i = 0; i < 8; i++)
7000 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7001
7002 kvm_get_dr(vcpu, 6, &val);
7003 put_smstate(u32, buf, 0x7fcc, (u32)val);
7004 kvm_get_dr(vcpu, 7, &val);
7005 put_smstate(u32, buf, 0x7fc8, (u32)val);
7006
7007 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7008 put_smstate(u32, buf, 0x7fc4, seg.selector);
7009 put_smstate(u32, buf, 0x7f64, seg.base);
7010 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7011 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7012
7013 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7014 put_smstate(u32, buf, 0x7fc0, seg.selector);
7015 put_smstate(u32, buf, 0x7f80, seg.base);
7016 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7017 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7018
7019 kvm_x86_ops->get_gdt(vcpu, &dt);
7020 put_smstate(u32, buf, 0x7f74, dt.address);
7021 put_smstate(u32, buf, 0x7f70, dt.size);
7022
7023 kvm_x86_ops->get_idt(vcpu, &dt);
7024 put_smstate(u32, buf, 0x7f58, dt.address);
7025 put_smstate(u32, buf, 0x7f54, dt.size);
7026
7027 for (i = 0; i < 6; i++)
ee2cd4b7 7028 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7029
7030 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7031
7032 /* revision id */
7033 put_smstate(u32, buf, 0x7efc, 0x00020000);
7034 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7035}
7036
ee2cd4b7 7037static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7038{
7039#ifdef CONFIG_X86_64
7040 struct desc_ptr dt;
7041 struct kvm_segment seg;
7042 unsigned long val;
7043 int i;
7044
7045 for (i = 0; i < 16; i++)
7046 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7047
7048 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7049 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7050
7051 kvm_get_dr(vcpu, 6, &val);
7052 put_smstate(u64, buf, 0x7f68, val);
7053 kvm_get_dr(vcpu, 7, &val);
7054 put_smstate(u64, buf, 0x7f60, val);
7055
7056 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7057 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7058 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7059
7060 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7061
7062 /* revision id */
7063 put_smstate(u32, buf, 0x7efc, 0x00020064);
7064
7065 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7066
7067 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7068 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7069 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7070 put_smstate(u32, buf, 0x7e94, seg.limit);
7071 put_smstate(u64, buf, 0x7e98, seg.base);
7072
7073 kvm_x86_ops->get_idt(vcpu, &dt);
7074 put_smstate(u32, buf, 0x7e84, dt.size);
7075 put_smstate(u64, buf, 0x7e88, dt.address);
7076
7077 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7078 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7079 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7080 put_smstate(u32, buf, 0x7e74, seg.limit);
7081 put_smstate(u64, buf, 0x7e78, seg.base);
7082
7083 kvm_x86_ops->get_gdt(vcpu, &dt);
7084 put_smstate(u32, buf, 0x7e64, dt.size);
7085 put_smstate(u64, buf, 0x7e68, dt.address);
7086
7087 for (i = 0; i < 6; i++)
ee2cd4b7 7088 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7089#else
7090 WARN_ON_ONCE(1);
7091#endif
7092}
7093
ee2cd4b7 7094static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7095{
660a5d51 7096 struct kvm_segment cs, ds;
18c3626e 7097 struct desc_ptr dt;
660a5d51
PB		 7098 char buf[512];
7099 u32 cr0;
7100
660a5d51 7101 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7102 memset(buf, 0, 512);
d6321d49 7103 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7104 enter_smm_save_state_64(vcpu, buf);
660a5d51 7105 else
ee2cd4b7 7106 enter_smm_save_state_32(vcpu, buf);
660a5d51 7107
0234bf88
LP		 7108 /*
7109 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7110 * vCPU state (e.g. leave guest mode) after we've saved the state into
7111 * the SMM state-save area.
7112 */
7113 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7114
7115 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7116 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7117
7118 if (kvm_x86_ops->get_nmi_mask(vcpu))
7119 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7120 else
7121 kvm_x86_ops->set_nmi_mask(vcpu, true);
7122
7123 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7124 kvm_rip_write(vcpu, 0x8000);
7125
7126 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7127 kvm_x86_ops->set_cr0(vcpu, cr0);
7128 vcpu->arch.cr0 = cr0;
7129
7130 kvm_x86_ops->set_cr4(vcpu, 0);
7131
18c3626e
PB		 7132 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7133 dt.address = dt.size = 0;
7134 kvm_x86_ops->set_idt(vcpu, &dt);
7135
660a5d51
PB		 7136 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7137
7138 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7139 cs.base = vcpu->arch.smbase;
7140
7141 ds.selector = 0;
7142 ds.base = 0;
7143
7144 cs.limit = ds.limit = 0xffffffff;
7145 cs.type = ds.type = 0x3;
7146 cs.dpl = ds.dpl = 0;
7147 cs.db = ds.db = 0;
7148 cs.s = ds.s = 1;
7149 cs.l = ds.l = 0;
7150 cs.g = ds.g = 1;
7151 cs.avl = ds.avl = 0;
7152 cs.present = ds.present = 1;
7153 cs.unusable = ds.unusable = 0;
7154 cs.padding = ds.padding = 0;
7155
7156 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7157 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7158 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7159 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7160 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7161 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7162
d6321d49 7163 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7164 kvm_x86_ops->set_efer(vcpu, 0);
7165
7166 kvm_update_cpuid(vcpu);
7167 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7168}
7169
ee2cd4b7 7170static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7171{
7172 vcpu->arch.smi_pending = true;
7173 kvm_make_request(KVM_REQ_EVENT, vcpu);
7174}
7175
2860c4b1
PB		 7176void kvm_make_scan_ioapic_request(struct kvm *kvm)
7177{
7178 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7179}
7180
3d81bc7e 7181static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7182{
3d81bc7e
YZ		 7183 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7184 return;
c7c9c56c 7185
6308630b 7186 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7187
b053b2ae 7188 if (irqchip_split(vcpu->kvm))
6308630b 7189 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7190 else {
fa59cc00 7191 if (vcpu->arch.apicv_active)
d62caabb 7192 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7193 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7194 }
e40ff1d6
LA		 7195
7196 if (is_guest_mode(vcpu))
7197 vcpu->arch.load_eoi_exitmap_pending = true;
7198 else
7199 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7200}
7201
7202static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7203{
7204 u64 eoi_exit_bitmap[4];
7205
7206 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7207 return;
7208
5c919412
AS		 7209 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7210 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7211 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7212}
7213
b1394e74
RK		 7214void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7215 unsigned long start, unsigned long end)
7216{
7217 unsigned long apic_address;
7218
7219 /*
7220 * The physical address of apic access page is stored in the VMCS.
7221 * Update it when it becomes invalid.
7222 */
7223 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7224 if (start <= apic_address && apic_address < end)
7225 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7226}
7227
4256f43f
TC		 7228void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7229{
c24ae0dc
TC		 7230 struct page *page = NULL;
7231
35754c98 7232 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7233 return;
7234
4256f43f
TC		 7235 if (!kvm_x86_ops->set_apic_access_page_addr)
7236 return;
7237
c24ae0dc 7238 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7239 if (is_error_page(page))
7240 return;
c24ae0dc
TC		 7241 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7242
7243 /*
7244 * Do not pin apic access page in memory, the MMU notifier
7245 * will call us again if it is migrated or swapped out.
7246 */
7247 put_page(page);
4256f43f
TC		 7248}
7249EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7250
9357d939 7251/*
362c698f 7252 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7253 * exiting to the userspace. Otherwise, the value will be returned to the
7254 * userspace.
7255 */
851ba692 7256static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7257{
7258 int r;
62a193ed
MG		 7259 bool req_int_win =
7260 dm_request_for_irq_injection(vcpu) &&
7261 kvm_cpu_accept_dm_intr(vcpu);
7262
730dca42 7263 bool req_immediate_exit = false;
b6c7a5dc 7264
2fa6e1e1 7265 if (kvm_request_pending(vcpu)) {
a8eeb04a 7266 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7267 kvm_mmu_unload(vcpu);
a8eeb04a 7268 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7269 __kvm_migrate_timers(vcpu);
d828199e
MT		 7270 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7271 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7272 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7273 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7274 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7275 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7276 if (unlikely(r))
7277 goto out;
7278 }
a8eeb04a 7279 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7280 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7281 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7282 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7283 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7284 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7285 r = 0;
7286 goto out;
7287 }
a8eeb04a 7288 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7289 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7290 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7291 r = 0;
7292 goto out;
7293 }
af585b92
GN		 7294 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7295 /* Page is swapped out. Do synthetic halt */
7296 vcpu->arch.apf.halted = true;
7297 r = 1;
7298 goto out;
7299 }
c9aaa895
GC		 7300 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7301 record_steal_time(vcpu);
64d60670
PB		 7302 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7303 process_smi(vcpu);
7460fb4a
AK		 7304 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7305 process_nmi(vcpu);
f5132b01 7306 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7307 kvm_pmu_handle_event(vcpu);
f5132b01 7308 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7309 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7310 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7311 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7312 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7313 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7314 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7315 vcpu->run->eoi.vector =
7316 vcpu->arch.pending_ioapic_eoi;
7317 r = 0;
7318 goto out;
7319 }
7320 }
3d81bc7e
YZ		 7321 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7322 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7323 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7324 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7325 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7326 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7327 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7328 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7329 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7330 r = 0;
7331 goto out;
7332 }
e516cebb
AS		 7333 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7334 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7335 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7336 r = 0;
7337 goto out;
7338 }
db397571
AS		 7339 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7340 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7341 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7342 r = 0;
7343 goto out;
7344 }
f3b138c5
AS		 7345
7346 /*
7347 * KVM_REQ_HV_STIMER has to be processed after
7348 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7349 * depend on the guest clock being up-to-date
7350 */
1f4b34f8
AS		 7351 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7352 kvm_hv_process_stimers(vcpu);
2f52d58c 7353 }
b93463aa 7354
b463a6f7 7355 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7356 ++vcpu->stat.req_event;
66450a21
JK		 7357 kvm_apic_accept_events(vcpu);
7358 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7359 r = 1;
7360 goto out;
7361 }
7362
b6b8a145
JK		 7363 if (inject_pending_event(vcpu, req_int_win) != 0)
7364 req_immediate_exit = true;
321c5658 7365 else {
cc3d967f 7366 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7367 *
cc3d967f
LP		 7368 * SMIs have three cases:
7369 * 1) They can be nested, and then there is nothing to
7370 * do here because RSM will cause a vmexit anyway.
7371 * 2) There is an ISA-specific reason why SMI cannot be
7372 * injected, and the moment when this changes can be
7373 * intercepted.
7374 * 3) Or the SMI can be pending because
7375 * inject_pending_event has completed the injection
7376 * of an IRQ or NMI from the previous vmexit, and
7377 * then we request an immediate exit to inject the
7378 * SMI.
c43203ca
PB		 7379 */
7380 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7381 if (!kvm_x86_ops->enable_smi_window(vcpu))
7382 req_immediate_exit = true;
321c5658
YS		 7383 if (vcpu->arch.nmi_pending)
7384 kvm_x86_ops->enable_nmi_window(vcpu);
7385 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7386 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7387 WARN_ON(vcpu->arch.exception.pending);
321c5658 7388 }
b463a6f7
AK		 7389
7390 if (kvm_lapic_enabled(vcpu)) {
7391 update_cr8_intercept(vcpu);
7392 kvm_lapic_sync_to_vapic(vcpu);
7393 }
7394 }
7395
d8368af8
AK		 7396 r = kvm_mmu_reload(vcpu);
7397 if (unlikely(r)) {
d905c069 7398 goto cancel_injection;
d8368af8
AK		 7399 }
7400
b6c7a5dc
HB		 7401 preempt_disable();
7402
7403 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7404
7405 /*
7406 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7407 * IPI are then delayed after guest entry, which ensures that they
7408 * result in virtual interrupt delivery.
7409 */
7410 local_irq_disable();
6b7e2d09
XG		 7411 vcpu->mode = IN_GUEST_MODE;
7412
01b71917
MT		 7413 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7414
0f127d12 7415 /*
b95234c8 7416 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7417 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7418 *
7419 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7420 * pairs with the memory barrier implicit in pi_test_and_set_on
7421 * (see vmx_deliver_posted_interrupt).
7422 *
7423 * 3) This also orders the write to mode from any reads to the page
7424 * tables done while the VCPU is running. Please see the comment
7425 * in kvm_flush_remote_tlbs.
6b7e2d09 7426 */
01b71917 7427 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7428
b95234c8
PB		 7429 /*
7430 * This handles the case where a posted interrupt was
7431 * notified with kvm_vcpu_kick.
7432 */
fa59cc00
LA		 7433 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7434 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7435
2fa6e1e1 7436 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7437 || need_resched() || signal_pending(current)) {
6b7e2d09 7438 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7439 smp_wmb();
6c142801
AK		 7440 local_irq_enable();
7441 preempt_enable();
01b71917 7442 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7443 r = 1;
d905c069 7444 goto cancel_injection;
6c142801
AK		 7445 }
7446
fc5b7f3b
DM		 7447 kvm_load_guest_xcr0(vcpu);
7448
c43203ca
PB		 7449 if (req_immediate_exit) {
7450 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7451 smp_send_reschedule(vcpu->cpu);
c43203ca 7452 }
d6185f20 7453
8b89fe1f 7454 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7455 if (lapic_timer_advance_ns)
7456 wait_lapic_expire(vcpu);
6edaa530 7457 guest_enter_irqoff();
b6c7a5dc 7458
42dbaa5a 7459 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7460 set_debugreg(0, 7);
7461 set_debugreg(vcpu->arch.eff_db[0], 0);
7462 set_debugreg(vcpu->arch.eff_db[1], 1);
7463 set_debugreg(vcpu->arch.eff_db[2], 2);
7464 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7465 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7466 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7467 }
b6c7a5dc 7468
851ba692 7469 kvm_x86_ops->run(vcpu);
b6c7a5dc 7470
c77fb5fe
PB		 7471 /*
7472 * Do this here before restoring debug registers on the host. And
7473 * since we do this before handling the vmexit, a DR access vmexit
7474 * can (a) read the correct value of the debug registers, (b) set
7475 * KVM_DEBUGREG_WONT_EXIT again.
7476 */
7477 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7478 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7479 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7480 kvm_update_dr0123(vcpu);
7481 kvm_update_dr6(vcpu);
7482 kvm_update_dr7(vcpu);
7483 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7484 }
7485
24f1e32c
FW		 7486 /*
7487 * If the guest has used debug registers, at least dr7
7488 * will be disabled while returning to the host.
7489 * If we don't have active breakpoints in the host, we don't
7490 * care about the messed up debug address registers. But if
7491 * we have some of them active, restore the old state.
7492 */
59d8eb53 7493 if (hw_breakpoint_active())
24f1e32c 7494 hw_breakpoint_restore();
42dbaa5a 7495
4ba76538 7496 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7497
6b7e2d09 7498 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7499 smp_wmb();
a547c6db 7500
fc5b7f3b
DM		 7501 kvm_put_guest_xcr0(vcpu);
7502
dd60d217 7503 kvm_before_interrupt(vcpu);
a547c6db 7504 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7505 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7506
7507 ++vcpu->stat.exits;
7508
f2485b3e 7509 guest_exit_irqoff();
b6c7a5dc 7510
f2485b3e 7511 local_irq_enable();
b6c7a5dc
HB		 7512 preempt_enable();
7513
f656ce01 7514 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7515
b6c7a5dc
HB		 7516 /*
7517 * Profile KVM exit RIPs:
7518 */
7519 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7520 unsigned long rip = kvm_rip_read(vcpu);
7521 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7522 }
7523
cc578287
ZA		 7524 if (unlikely(vcpu->arch.tsc_always_catchup))
7525 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7526
5cfb1d5a
MT		 7527 if (vcpu->arch.apic_attention)
7528 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7529
618232e2 7530 vcpu->arch.gpa_available = false;
851ba692 7531 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7532 return r;
7533
7534cancel_injection:
7535 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7536 if (unlikely(vcpu->arch.apic_attention))
7537 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7538out:
7539 return r;
7540}
b6c7a5dc 7541
362c698f
PB		 7542static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7543{
bf9f6ac8
FW		 7544 if (!kvm_arch_vcpu_runnable(vcpu) &&
7545 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7546 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7547 kvm_vcpu_block(vcpu);
7548 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7549
7550 if (kvm_x86_ops->post_block)
7551 kvm_x86_ops->post_block(vcpu);
7552
9c8fd1ba
PB		 7553 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7554 return 1;
7555 }
362c698f
PB		 7556
7557 kvm_apic_accept_events(vcpu);
7558 switch(vcpu->arch.mp_state) {
7559 case KVM_MP_STATE_HALTED:
7560 vcpu->arch.pv.pv_unhalted = false;
7561 vcpu->arch.mp_state =
7562 KVM_MP_STATE_RUNNABLE;
7563 case KVM_MP_STATE_RUNNABLE:
7564 vcpu->arch.apf.halted = false;
7565 break;
7566 case KVM_MP_STATE_INIT_RECEIVED:
7567 break;
7568 default:
7569 return -EINTR;
7570 break;
7571 }
7572 return 1;
7573}
09cec754 7574
5d9bc648
PB		 7575static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7576{
0ad3bed6
PB		 7577 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7578 kvm_x86_ops->check_nested_events(vcpu, false);
7579
5d9bc648
PB		 7580 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7581 !vcpu->arch.apf.halted);
7582}
7583
362c698f 7584static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7585{
7586 int r;
f656ce01 7587 struct kvm *kvm = vcpu->kvm;
d7690175 7588
f656ce01 7589 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 7590 vcpu->arch.l1tf_flush_l1d = true;
d7690175 7591
362c698f 7592 for (;;) {
58f800d5 7593 if (kvm_vcpu_running(vcpu)) {
851ba692 7594 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7595 } else {
362c698f 7596 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7597 }
7598
09cec754
GN		 7599 if (r <= 0)
7600 break;
7601
72875d8a 7602 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7603 if (kvm_cpu_has_pending_timer(vcpu))
7604 kvm_inject_pending_timer_irqs(vcpu);
7605
782d422b
MG		 7606 if (dm_request_for_irq_injection(vcpu) &&
7607 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7608 r = 0;
7609 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7610 ++vcpu->stat.request_irq_exits;
362c698f 7611 break;
09cec754 7612 }
af585b92
GN		 7613
7614 kvm_check_async_pf_completion(vcpu);
7615
09cec754
GN		 7616 if (signal_pending(current)) {
7617 r = -EINTR;
851ba692 7618 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7619 ++vcpu->stat.signal_exits;
362c698f 7620 break;
09cec754
GN		 7621 }
7622 if (need_resched()) {
f656ce01 7623 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7624 cond_resched();
f656ce01 7625 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7626 }
b6c7a5dc
HB		 7627 }
7628
f656ce01 7629 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7630
7631 return r;
7632}
7633
716d51ab
GN		 7634static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7635{
7636 int r;
7637 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7638 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7639 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7640 if (r != EMULATE_DONE)
7641 return 0;
7642 return 1;
7643}
7644
7645static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7646{
7647 BUG_ON(!vcpu->arch.pio.count);
7648
7649 return complete_emulated_io(vcpu);
7650}
7651
f78146b0
AK		 7652/*
7653 * Implements the following, as a state machine:
7654 *
7655 * read:
7656 * for each fragment
87da7e66
XG		 7657 * for each mmio piece in the fragment
7658 * write gpa, len
7659 * exit
7660 * copy data
f78146b0
AK		 7661 * execute insn
7662 *
7663 * write:
7664 * for each fragment
87da7e66
XG		 7665 * for each mmio piece in the fragment
7666 * write gpa, len
7667 * copy data
7668 * exit
f78146b0 7669 */
716d51ab 7670static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7671{
7672 struct kvm_run *run = vcpu->run;
f78146b0 7673 struct kvm_mmio_fragment *frag;
87da7e66 7674 unsigned len;
5287f194 7675
716d51ab 7676 BUG_ON(!vcpu->mmio_needed);
5287f194 7677
716d51ab 7678 /* Complete previous fragment */
87da7e66
XG		 7679 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7680 len = min(8u, frag->len);
716d51ab 7681 if (!vcpu->mmio_is_write)
87da7e66
XG		 7682 memcpy(frag->data, run->mmio.data, len);
7683
7684 if (frag->len <= 8) {
7685 /* Switch to the next fragment. */
7686 frag++;
7687 vcpu->mmio_cur_fragment++;
7688 } else {
7689 /* Go forward to the next mmio piece. */
7690 frag->data += len;
7691 frag->gpa += len;
7692 frag->len -= len;
7693 }
7694
a08d3b3b 7695 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7696 vcpu->mmio_needed = 0;
0912c977
PB		 7697
7698 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7699 if (vcpu->mmio_is_write)
716d51ab
GN		 7700 return 1;
7701 vcpu->mmio_read_completed = 1;
7702 return complete_emulated_io(vcpu);
7703 }
87da7e66 7704
716d51ab
GN		 7705 run->exit_reason = KVM_EXIT_MMIO;
7706 run->mmio.phys_addr = frag->gpa;
7707 if (vcpu->mmio_is_write)
87da7e66
XG		 7708 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7709 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7710 run->mmio.is_write = vcpu->mmio_is_write;
7711 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7712 return 0;
5287f194
AK		 7713}
7714
b6c7a5dc
HB		 7715int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7716{
7717 int r;
b6c7a5dc 7718
accb757d 7719 vcpu_load(vcpu);
20b7035c 7720 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7721 kvm_load_guest_fpu(vcpu);
7722
a4535290 7723 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7724 if (kvm_run->immediate_exit) {
7725 r = -EINTR;
7726 goto out;
7727 }
b6c7a5dc 7728 kvm_vcpu_block(vcpu);
66450a21 7729 kvm_apic_accept_events(vcpu);
72875d8a 7730 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7731 r = -EAGAIN;
a0595000
JS		 7732 if (signal_pending(current)) {
7733 r = -EINTR;
7734 vcpu->run->exit_reason = KVM_EXIT_INTR;
7735 ++vcpu->stat.signal_exits;
7736 }
ac9f6dc0 7737 goto out;
b6c7a5dc
HB		 7738 }
7739
01643c51
KH		 7740 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7741 r = -EINVAL;
7742 goto out;
7743 }
7744
7745 if (vcpu->run->kvm_dirty_regs) {
7746 r = sync_regs(vcpu);
7747 if (r != 0)
7748 goto out;
7749 }
7750
b6c7a5dc 7751 /* re-sync apic's tpr */
35754c98 7752 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7753 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7754 r = -EINVAL;
7755 goto out;
7756 }
7757 }
b6c7a5dc 7758
716d51ab
GN		 7759 if (unlikely(vcpu->arch.complete_userspace_io)) {
7760 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7761 vcpu->arch.complete_userspace_io = NULL;
7762 r = cui(vcpu);
7763 if (r <= 0)
5663d8f9 7764 goto out;
716d51ab
GN		 7765 } else
7766 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7767
460df4c1
PB		 7768 if (kvm_run->immediate_exit)
7769 r = -EINTR;
7770 else
7771 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7772
7773out:
5663d8f9 7774 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7775 if (vcpu->run->kvm_valid_regs)
7776 store_regs(vcpu);
f1d86e46 7777 post_kvm_run_save(vcpu);
20b7035c 7778 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7779
accb757d 7780 vcpu_put(vcpu);
b6c7a5dc
HB		 7781 return r;
7782}
7783
01643c51 7784static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7785{
7ae441ea
GN		 7786 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7787 /*
7788 * We are here if userspace calls get_regs() in the middle of
7789 * instruction emulation. Registers state needs to be copied
4a969980 7790 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7791 * that usually, but some bad designed PV devices (vmware
7792 * backdoor interface) need this to work
7793 */
dd856efa 7794 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7795 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7796 }
5fdbf976
MT		 7797 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7798 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7799 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7800 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7801 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7802 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7803 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7804 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7805#ifdef CONFIG_X86_64
5fdbf976
MT		 7806 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7807 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7808 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7809 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7810 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7811 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7812 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7813 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7814#endif
7815
5fdbf976 7816 regs->rip = kvm_rip_read(vcpu);
91586a3b 7817 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7818}
b6c7a5dc 7819
01643c51
KH		 7820int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7821{
7822 vcpu_load(vcpu);
7823 __get_regs(vcpu, regs);
1fc9b76b 7824 vcpu_put(vcpu);
b6c7a5dc
HB		 7825 return 0;
7826}
7827
01643c51 7828static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7829{
7ae441ea
GN		 7830 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7831 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7832
5fdbf976
MT		 7833 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7834 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7835 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7836 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7837 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7838 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7839 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7840 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7841#ifdef CONFIG_X86_64
5fdbf976
MT		 7842 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7843 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7844 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7845 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7846 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7847 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7848 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7849 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7850#endif
7851
5fdbf976 7852 kvm_rip_write(vcpu, regs->rip);
d73235d1 7853 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7854
b4f14abd
JK		 7855 vcpu->arch.exception.pending = false;
7856
3842d135 7857 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7858}
3842d135 7859
01643c51
KH		 7860int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7861{
7862 vcpu_load(vcpu);
7863 __set_regs(vcpu, regs);
875656fe 7864 vcpu_put(vcpu);
b6c7a5dc
HB		 7865 return 0;
7866}
7867
b6c7a5dc
HB		 7868void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7869{
7870 struct kvm_segment cs;
7871
3e6e0aab 7872 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7873 *db = cs.db;
7874 *l = cs.l;
7875}
7876EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7877
01643c51 7878static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7879{
89a27f4d 7880 struct desc_ptr dt;
b6c7a5dc 7881
3e6e0aab
GT		 7882 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7883 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7884 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7885 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7886 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7887 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7888
3e6e0aab
GT		 7889 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7890 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7891
7892 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7893 sregs->idt.limit = dt.size;
7894 sregs->idt.base = dt.address;
b6c7a5dc 7895 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7896 sregs->gdt.limit = dt.size;
7897 sregs->gdt.base = dt.address;
b6c7a5dc 7898
4d4ec087 7899 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7900 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7901 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7902 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7903 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7904 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7905 sregs->apic_base = kvm_get_apic_base(vcpu);
7906
923c61bb 7907 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7908
04140b41 7909 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7910 set_bit(vcpu->arch.interrupt.nr,
7911 (unsigned long *)sregs->interrupt_bitmap);
01643c51 7912}
16d7a191 7913
01643c51
KH		 7914int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7915 struct kvm_sregs *sregs)
7916{
7917 vcpu_load(vcpu);
7918 __get_sregs(vcpu, sregs);
bcdec41c 7919 vcpu_put(vcpu);
b6c7a5dc
HB		 7920 return 0;
7921}
7922
62d9f0db
MT		 7923int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7924 struct kvm_mp_state *mp_state)
7925{
fd232561
CD		 7926 vcpu_load(vcpu);
7927
66450a21 7928 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7929 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7930 vcpu->arch.pv.pv_unhalted)
7931 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7932 else
7933 mp_state->mp_state = vcpu->arch.mp_state;
7934
fd232561 7935 vcpu_put(vcpu);
62d9f0db
MT		 7936 return 0;
7937}
7938
7939int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7940 struct kvm_mp_state *mp_state)
7941{
e83dff5e
CD		 7942 int ret = -EINVAL;
7943
7944 vcpu_load(vcpu);
7945
bce87cce 7946 if (!lapic_in_kernel(vcpu) &&
66450a21 7947 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7948 goto out;
66450a21 7949
28bf2888
DH		 7950 /* INITs are latched while in SMM */
7951 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7952 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7953 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7954 goto out;
28bf2888 7955
66450a21
JK		 7956 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7957 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7958 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7959 } else
7960 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7961 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7962
7963 ret = 0;
7964out:
7965 vcpu_put(vcpu);
7966 return ret;
62d9f0db
MT		 7967}
7968
7f3d35fd
KW		 7969int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7970 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7971{
9d74191a 7972 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7973 int ret;
e01c2426 7974
8ec4722d 7975 init_emulate_ctxt(vcpu);
c697518a 7976
7f3d35fd 7977 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7978 has_error_code, error_code);
c697518a 7979
c697518a 7980 if (ret)
19d04437 7981 return EMULATE_FAIL;
37817f29 7982
9d74191a
TY		 7983 kvm_rip_write(vcpu, ctxt->eip);
7984 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7985 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7986 return EMULATE_DONE;
37817f29
IE		 7987}
7988EXPORT_SYMBOL_GPL(kvm_task_switch);
7989
3140c156 7990static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 7991{
37b95951 7992 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7993 /*
7994 * When EFER.LME and CR0.PG are set, the processor is in
7995 * 64-bit mode (though maybe in a 32-bit code segment).
7996 * CR4.PAE and EFER.LMA must be set.
7997 */
37b95951 7998 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7999 || !(sregs->efer & EFER_LMA))
8000 return -EINVAL;
8001 } else {
8002 /*
8003 * Not in 64-bit mode: EFER.LMA is clear and the code
8004 * segment cannot be 64-bit.
8005 */
8006 if (sregs->efer & EFER_LMA || sregs->cs.l)
8007 return -EINVAL;
8008 }
8009
8010 return 0;
8011}
8012
01643c51 8013static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8014{
58cb628d 8015 struct msr_data apic_base_msr;
b6c7a5dc 8016 int mmu_reset_needed = 0;
c4d21882 8017 int cpuid_update_needed = 0;
63f42e02 8018 int pending_vec, max_bits, idx;
89a27f4d 8019 struct desc_ptr dt;
b4ef9d4e
CD		 8020 int ret = -EINVAL;
8021
d6321d49
RK		 8022 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8023 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 8024 goto out;
6d1068b3 8025
f2981033 8026 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8027 goto out;
f2981033 8028
d3802286
JM		 8029 apic_base_msr.data = sregs->apic_base;
8030 apic_base_msr.host_initiated = true;
8031 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8032 goto out;
6d1068b3 8033
89a27f4d
GN		 8034 dt.size = sregs->idt.limit;
8035 dt.address = sregs->idt.base;
b6c7a5dc 8036 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8037 dt.size = sregs->gdt.limit;
8038 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8039 kvm_x86_ops->set_gdt(vcpu, &dt);
8040
ad312c7c 8041 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8042 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8043 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8044 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8045
2d3ad1f4 8046 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8047
f6801dff 8048 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8049 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8050
4d4ec087 8051 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8052 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8053 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8054
fc78f519 8055 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8056 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8057 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8058 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8059 if (cpuid_update_needed)
00b27a3e 8060 kvm_update_cpuid(vcpu);
63f42e02
XG		 8061
8062 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 8063 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 8064 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8065 mmu_reset_needed = 1;
8066 }
63f42e02 8067 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8068
8069 if (mmu_reset_needed)
8070 kvm_mmu_reset_context(vcpu);
8071
a50abc3b 8072 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8073 pending_vec = find_first_bit(
8074 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8075 if (pending_vec < max_bits) {
66fd3f7f 8076 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8077 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8078 }
8079
3e6e0aab
GT		 8080 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8081 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8082 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8083 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8084 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8085 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8086
3e6e0aab
GT		 8087 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8088 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8089
5f0269f5
ME		 8090 update_cr8_intercept(vcpu);
8091
9c3e4aab 8092 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8093 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8094 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8095 !is_protmode(vcpu))
9c3e4aab
MT		 8096 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8097
3842d135
AK		 8098 kvm_make_request(KVM_REQ_EVENT, vcpu);
8099
b4ef9d4e
CD		 8100 ret = 0;
8101out:
01643c51
KH		 8102 return ret;
8103}
8104
8105int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8106 struct kvm_sregs *sregs)
8107{
8108 int ret;
8109
8110 vcpu_load(vcpu);
8111 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8112 vcpu_put(vcpu);
8113 return ret;
b6c7a5dc
HB		 8114}
8115
d0bfb940
JK		 8116int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8117 struct kvm_guest_debug *dbg)
b6c7a5dc 8118{
355be0b9 8119 unsigned long rflags;
ae675ef0 8120 int i, r;
b6c7a5dc 8121
66b56562
CD		 8122 vcpu_load(vcpu);
8123
4f926bf2
JK		 8124 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8125 r = -EBUSY;
8126 if (vcpu->arch.exception.pending)
2122ff5e 8127 goto out;
4f926bf2
JK		 8128 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8129 kvm_queue_exception(vcpu, DB_VECTOR);
8130 else
8131 kvm_queue_exception(vcpu, BP_VECTOR);
8132 }
8133
91586a3b
JK		 8134 /*
8135 * Read rflags as long as potentially injected trace flags are still
8136 * filtered out.
8137 */
8138 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8139
8140 vcpu->guest_debug = dbg->control;
8141 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8142 vcpu->guest_debug = 0;
8143
8144 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8145 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8146 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8147 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8148 } else {
8149 for (i = 0; i < KVM_NR_DB_REGS; i++)
8150 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8151 }
c8639010 8152 kvm_update_dr7(vcpu);
ae675ef0 8153
f92653ee
JK		 8154 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8155 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8156 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8157
91586a3b
JK		 8158 /*
8159 * Trigger an rflags update that will inject or remove the trace
8160 * flags.
8161 */
8162 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8163
a96036b8 8164 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8165
4f926bf2 8166 r = 0;
d0bfb940 8167
2122ff5e 8168out:
66b56562 8169 vcpu_put(vcpu);
b6c7a5dc
HB		 8170 return r;
8171}
8172
8b006791
ZX		 8173/*
8174 * Translate a guest virtual address to a guest physical address.
8175 */
8176int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8177 struct kvm_translation *tr)
8178{
8179 unsigned long vaddr = tr->linear_address;
8180 gpa_t gpa;
f656ce01 8181 int idx;
8b006791 8182
1da5b61d
CD		 8183 vcpu_load(vcpu);
8184
f656ce01 8185 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8186 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8187 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8188 tr->physical_address = gpa;
8189 tr->valid = gpa != UNMAPPED_GVA;
8190 tr->writeable = 1;
8191 tr->usermode = 0;
8b006791 8192
1da5b61d 8193 vcpu_put(vcpu);
8b006791
ZX		 8194 return 0;
8195}
8196
d0752060
HB		 8197int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8198{
1393123e 8199 struct fxregs_state *fxsave;
d0752060 8200
1393123e 8201 vcpu_load(vcpu);
d0752060 8202
1393123e 8203 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8204 memcpy(fpu->fpr, fxsave->st_space, 128);
8205 fpu->fcw = fxsave->cwd;
8206 fpu->fsw = fxsave->swd;
8207 fpu->ftwx = fxsave->twd;
8208 fpu->last_opcode = fxsave->fop;
8209 fpu->last_ip = fxsave->rip;
8210 fpu->last_dp = fxsave->rdp;
8211 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8212
1393123e 8213 vcpu_put(vcpu);
d0752060
HB		 8214 return 0;
8215}
8216
8217int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8218{
6a96bc7f
CD		 8219 struct fxregs_state *fxsave;
8220
8221 vcpu_load(vcpu);
8222
8223 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8224
d0752060
HB		 8225 memcpy(fxsave->st_space, fpu->fpr, 128);
8226 fxsave->cwd = fpu->fcw;
8227 fxsave->swd = fpu->fsw;
8228 fxsave->twd = fpu->ftwx;
8229 fxsave->fop = fpu->last_opcode;
8230 fxsave->rip = fpu->last_ip;
8231 fxsave->rdp = fpu->last_dp;
8232 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8233
6a96bc7f 8234 vcpu_put(vcpu);
d0752060
HB		 8235 return 0;
8236}
8237
01643c51
KH		 8238static void store_regs(struct kvm_vcpu *vcpu)
8239{
8240 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8241
8242 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8243 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8244
8245 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8246 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8247
8248 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8249 kvm_vcpu_ioctl_x86_get_vcpu_events(
8250 vcpu, &vcpu->run->s.regs.events);
8251}
8252
8253static int sync_regs(struct kvm_vcpu *vcpu)
8254{
8255 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8256 return -EINVAL;
8257
8258 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8259 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8260 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8261 }
8262 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8263 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8264 return -EINVAL;
8265 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8266 }
8267 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8268 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8269 vcpu, &vcpu->run->s.regs.events))
8270 return -EINVAL;
8271 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8272 }
8273
8274 return 0;
8275}
8276
0ee6a517 8277static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8278{
bf935b0b 8279 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8280 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8281 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8282 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8283
2acf923e
DC		 8284 /*
8285 * Ensure guest xcr0 is valid for loading
8286 */
d91cab78 8287 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8288
ad312c7c 8289 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8290}
d0752060 8291
f775b13e 8292/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8293void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8294{
f775b13e
RR		 8295 preempt_disable();
8296 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8297 /* PKRU is separately restored in kvm_x86_ops->run. */
8298 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8299 ~XFEATURE_MASK_PKRU);
f775b13e 8300 preempt_enable();
0c04851c 8301 trace_kvm_fpu(1);
d0752060 8302}
d0752060 8303
f775b13e 8304/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8305void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8306{
f775b13e 8307 preempt_disable();
4f836347 8308 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8309 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8310 preempt_enable();
f096ed85 8311 ++vcpu->stat.fpu_reload;
0c04851c 8312 trace_kvm_fpu(0);
d0752060 8313}
e9b11c17
ZX		 8314
8315void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8316{
bd768e14
IY		 8317 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8318
12f9a48f 8319 kvmclock_reset(vcpu);
7f1ea208 8320
e9b11c17 8321 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8322 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8323}
8324
8325struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8326 unsigned int id)
8327{
c447e76b
LL		 8328 struct kvm_vcpu *vcpu;
8329
b0c39dc6 8330 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8331 printk_once(KERN_WARNING
8332 "kvm: SMP vm created on host with unstable TSC; "
8333 "guest TSC will not be reliable\n");
c447e76b
LL		 8334
8335 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8336
c447e76b 8337 return vcpu;
26e5215f 8338}
e9b11c17 8339
26e5215f
AK		 8340int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8341{
19efffa2 8342 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8343 vcpu_load(vcpu);
d28bc9dd 8344 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8345 kvm_mmu_setup(vcpu);
e9b11c17 8346 vcpu_put(vcpu);
ec7660cc 8347 return 0;
e9b11c17
ZX		 8348}
8349
31928aa5 8350void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8351{
8fe8ab46 8352 struct msr_data msr;
332967a3 8353 struct kvm *kvm = vcpu->kvm;
42897d86 8354
d3457c87
RK		 8355 kvm_hv_vcpu_postcreate(vcpu);
8356
ec7660cc 8357 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8358 return;
ec7660cc 8359 vcpu_load(vcpu);
8fe8ab46
WA		 8360 msr.data = 0x0;
8361 msr.index = MSR_IA32_TSC;
8362 msr.host_initiated = true;
8363 kvm_write_tsc(vcpu, &msr);
42897d86 8364 vcpu_put(vcpu);
ec7660cc 8365 mutex_unlock(&vcpu->mutex);
42897d86 8366
630994b3
MT		 8367 if (!kvmclock_periodic_sync)
8368 return;
8369
332967a3
AJ		 8370 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8371 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8372}
8373
d40ccc62 8374void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8375{
344d9588
GN		 8376 vcpu->arch.apf.msr_val = 0;
8377
ec7660cc 8378 vcpu_load(vcpu);
e9b11c17
ZX		 8379 kvm_mmu_unload(vcpu);
8380 vcpu_put(vcpu);
8381
8382 kvm_x86_ops->vcpu_free(vcpu);
8383}
8384
d28bc9dd 8385void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8386{
b7e31be3
RK		 8387 kvm_lapic_reset(vcpu, init_event);
8388
e69fab5d
PB		 8389 vcpu->arch.hflags = 0;
8390
c43203ca 8391 vcpu->arch.smi_pending = 0;
52797bf9 8392 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8393 atomic_set(&vcpu->arch.nmi_queued, 0);
8394 vcpu->arch.nmi_pending = 0;
448fa4a9 8395 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8396 kvm_clear_interrupt_queue(vcpu);
8397 kvm_clear_exception_queue(vcpu);
664f8e26 8398 vcpu->arch.exception.pending = false;
448fa4a9 8399
42dbaa5a 8400 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8401 kvm_update_dr0123(vcpu);
6f43ed01 8402 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8403 kvm_update_dr6(vcpu);
42dbaa5a 8404 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8405 kvm_update_dr7(vcpu);
42dbaa5a 8406
1119022c
NA		 8407 vcpu->arch.cr2 = 0;
8408
3842d135 8409 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8410 vcpu->arch.apf.msr_val = 0;
c9aaa895 8411 vcpu->arch.st.msr_val = 0;
3842d135 8412
12f9a48f
GC		 8413 kvmclock_reset(vcpu);
8414
af585b92
GN		 8415 kvm_clear_async_pf_completion_queue(vcpu);
8416 kvm_async_pf_hash_reset(vcpu);
8417 vcpu->arch.apf.halted = false;
3842d135 8418
a554d207
WL		 8419 if (kvm_mpx_supported()) {
8420 void *mpx_state_buffer;
8421
8422 /*
8423 * To avoid have the INIT path from kvm_apic_has_events() that be
8424 * called with loaded FPU and does not let userspace fix the state.
8425 */
f775b13e
RR		 8426 if (init_event)
8427 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8428 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8429 XFEATURE_MASK_BNDREGS);
8430 if (mpx_state_buffer)
8431 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8432 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8433 XFEATURE_MASK_BNDCSR);
8434 if (mpx_state_buffer)
8435 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8436 if (init_event)
8437 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8438 }
8439
64d60670 8440 if (!init_event) {
d28bc9dd 8441 kvm_pmu_reset(vcpu);
64d60670 8442 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8443
8444 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8445 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8446
8447 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8448 }
f5132b01 8449
66f7b72e
JS		 8450 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8451 vcpu->arch.regs_avail = ~0;
8452 vcpu->arch.regs_dirty = ~0;
8453
a554d207
WL		 8454 vcpu->arch.ia32_xss = 0;
8455
d28bc9dd 8456 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8457}
8458
2b4a273b 8459void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8460{
8461 struct kvm_segment cs;
8462
8463 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8464 cs.selector = vector << 8;
8465 cs.base = vector << 12;
8466 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8467 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8468}
8469
13a34e06 8470int kvm_arch_hardware_enable(void)
e9b11c17 8471{
ca84d1a2
ZA		 8472 struct kvm *kvm;
8473 struct kvm_vcpu *vcpu;
8474 int i;
0dd6a6ed
ZA		 8475 int ret;
8476 u64 local_tsc;
8477 u64 max_tsc = 0;
8478 bool stable, backwards_tsc = false;
18863bdd
AK		 8479
8480 kvm_shared_msr_cpu_online();
13a34e06 8481 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8482 if (ret != 0)
8483 return ret;
8484
4ea1636b 8485 local_tsc = rdtsc();
b0c39dc6 8486 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8487 list_for_each_entry(kvm, &vm_list, vm_list) {
8488 kvm_for_each_vcpu(i, vcpu, kvm) {
8489 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8490 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8491 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8492 backwards_tsc = true;
8493 if (vcpu->arch.last_host_tsc > max_tsc)
8494 max_tsc = vcpu->arch.last_host_tsc;
8495 }
8496 }
8497 }
8498
8499 /*
8500 * Sometimes, even reliable TSCs go backwards. This happens on
8501 * platforms that reset TSC during suspend or hibernate actions, but
8502 * maintain synchronization. We must compensate. Fortunately, we can
8503 * detect that condition here, which happens early in CPU bringup,
8504 * before any KVM threads can be running. Unfortunately, we can't
8505 * bring the TSCs fully up to date with real time, as we aren't yet far
8506 * enough into CPU bringup that we know how much real time has actually
108b249c 8507 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8508 * variables that haven't been updated yet.
8509 *
8510 * So we simply find the maximum observed TSC above, then record the
8511 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8512 * the adjustment will be applied. Note that we accumulate
8513 * adjustments, in case multiple suspend cycles happen before some VCPU
8514 * gets a chance to run again. In the event that no KVM threads get a
8515 * chance to run, we will miss the entire elapsed period, as we'll have
8516 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8517 * loose cycle time. This isn't too big a deal, since the loss will be
8518 * uniform across all VCPUs (not to mention the scenario is extremely
8519 * unlikely). It is possible that a second hibernate recovery happens
8520 * much faster than a first, causing the observed TSC here to be
8521 * smaller; this would require additional padding adjustment, which is
8522 * why we set last_host_tsc to the local tsc observed here.
8523 *
8524 * N.B. - this code below runs only on platforms with reliable TSC,
8525 * as that is the only way backwards_tsc is set above. Also note
8526 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8527 * have the same delta_cyc adjustment applied if backwards_tsc
8528 * is detected. Note further, this adjustment is only done once,
8529 * as we reset last_host_tsc on all VCPUs to stop this from being
8530 * called multiple times (one for each physical CPU bringup).
8531 *
4a969980 8532 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8533 * will be compensated by the logic in vcpu_load, which sets the TSC to
8534 * catchup mode. This will catchup all VCPUs to real time, but cannot
8535 * guarantee that they stay in perfect synchronization.
8536 */
8537 if (backwards_tsc) {
8538 u64 delta_cyc = max_tsc - local_tsc;
8539 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8540 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8541 kvm_for_each_vcpu(i, vcpu, kvm) {
8542 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8543 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8544 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8545 }
8546
8547 /*
8548 * We have to disable TSC offset matching.. if you were
8549 * booting a VM while issuing an S4 host suspend....
8550 * you may have some problem. Solving this issue is
8551 * left as an exercise to the reader.
8552 */
8553 kvm->arch.last_tsc_nsec = 0;
8554 kvm->arch.last_tsc_write = 0;
8555 }
8556
8557 }
8558 return 0;
e9b11c17
ZX		 8559}
8560
13a34e06 8561void kvm_arch_hardware_disable(void)
e9b11c17 8562{
13a34e06
RK		 8563 kvm_x86_ops->hardware_disable();
8564 drop_user_return_notifiers();
e9b11c17
ZX		 8565}
8566
8567int kvm_arch_hardware_setup(void)
8568{
9e9c3fe4
NA		 8569 int r;
8570
8571 r = kvm_x86_ops->hardware_setup();
8572 if (r != 0)
8573 return r;
8574
35181e86
HZ		 8575 if (kvm_has_tsc_control) {
8576 /*
8577 * Make sure the user can only configure tsc_khz values that
8578 * fit into a signed integer.
273ba457 8579 * A min value is not calculated because it will always
35181e86
HZ		 8580 * be 1 on all machines.
8581 */
8582 u64 max = min(0x7fffffffULL,
8583 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8584 kvm_max_guest_tsc_khz = max;
8585
ad721883 8586 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8587 }
ad721883 8588
9e9c3fe4
NA		 8589 kvm_init_msr_list();
8590 return 0;
e9b11c17
ZX		 8591}
8592
8593void kvm_arch_hardware_unsetup(void)
8594{
8595 kvm_x86_ops->hardware_unsetup();
8596}
8597
8598void kvm_arch_check_processor_compat(void *rtn)
8599{
8600 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8601}
8602
8603bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8604{
8605 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8606}
8607EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8608
8609bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8610{
8611 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8612}
8613
54e9818f 8614struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8615EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8616
e9b11c17
ZX		 8617int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8618{
8619 struct page *page;
e9b11c17
ZX		 8620 int r;
8621
b2a05fef 8622 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8623 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8624 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8625 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8626 else
a4535290 8627 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8628
8629 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8630 if (!page) {
8631 r = -ENOMEM;
8632 goto fail;
8633 }
ad312c7c 8634 vcpu->arch.pio_data = page_address(page);
e9b11c17 8635
cc578287 8636 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8637
e9b11c17
ZX		 8638 r = kvm_mmu_create(vcpu);
8639 if (r < 0)
8640 goto fail_free_pio_data;
8641
26de7988 8642 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8643 r = kvm_create_lapic(vcpu);
8644 if (r < 0)
8645 goto fail_mmu_destroy;
54e9818f
GN		 8646 } else
8647 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8648
890ca9ae
HY		 8649 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8650 GFP_KERNEL);
8651 if (!vcpu->arch.mce_banks) {
8652 r = -ENOMEM;
443c39bc 8653 goto fail_free_lapic;
890ca9ae
HY		 8654 }
8655 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8656
f1797359
WY		 8657 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8658 r = -ENOMEM;
f5f48ee1 8659 goto fail_free_mce_banks;
f1797359 8660 }
f5f48ee1 8661
0ee6a517 8662 fx_init(vcpu);
66f7b72e 8663
4344ee98 8664 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8665
5a4f55cd
EK		 8666 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8667
74545705
RK		 8668 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8669
af585b92 8670 kvm_async_pf_hash_reset(vcpu);
f5132b01 8671 kvm_pmu_init(vcpu);
af585b92 8672
1c1a9ce9 8673 vcpu->arch.pending_external_vector = -1;
de63ad4c 8674 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8675
5c919412
AS		 8676 kvm_hv_vcpu_init(vcpu);
8677
e9b11c17 8678 return 0;
0ee6a517 8679
f5f48ee1
SY		 8680fail_free_mce_banks:
8681 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8682fail_free_lapic:
8683 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8684fail_mmu_destroy:
8685 kvm_mmu_destroy(vcpu);
8686fail_free_pio_data:
ad312c7c 8687 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8688fail:
8689 return r;
8690}
8691
8692void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8693{
f656ce01
MT		 8694 int idx;
8695
1f4b34f8 8696 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8697 kvm_pmu_destroy(vcpu);
36cb93fd 8698 kfree(vcpu->arch.mce_banks);
e9b11c17 8699 kvm_free_lapic(vcpu);
f656ce01 8700 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8701 kvm_mmu_destroy(vcpu);
f656ce01 8702 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8703 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8704 if (!lapic_in_kernel(vcpu))
54e9818f 8705 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8706}
d19a9cd2 8707
e790d9ef
RK		 8708void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8709{
c595ceee 8710 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 8711 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8712}
8713
e08b9637 8714int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8715{
e08b9637
CO		 8716 if (type)
8717 return -EINVAL;
8718
6ef768fa 8719 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8720 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8721 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8722 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8723 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8724
5550af4d
SY		 8725 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8726 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8727 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8728 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8729 &kvm->arch.irq_sources_bitmap);
5550af4d 8730
038f8c11 8731 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8732 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8733 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8734
108b249c 8735 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8736 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8737
7e44e449 8738 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8739 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8740
cbc0236a 8741 kvm_hv_init_vm(kvm);
0eb05bf2 8742 kvm_page_track_init(kvm);
13d268ca 8743 kvm_mmu_init_vm(kvm);
0eb05bf2 8744
03543133
SS		 8745 if (kvm_x86_ops->vm_init)
8746 return kvm_x86_ops->vm_init(kvm);
8747
d89f5eff 8748 return 0;
d19a9cd2
ZX		 8749}
8750
8751static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8752{
ec7660cc 8753 vcpu_load(vcpu);
d19a9cd2
ZX		 8754 kvm_mmu_unload(vcpu);
8755 vcpu_put(vcpu);
8756}
8757
8758static void kvm_free_vcpus(struct kvm *kvm)
8759{
8760 unsigned int i;
988a2cae 8761 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8762
8763 /*
8764 * Unpin any mmu pages first.
8765 */
af585b92
GN		 8766 kvm_for_each_vcpu(i, vcpu, kvm) {
8767 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8768 kvm_unload_vcpu_mmu(vcpu);
af585b92 8769 }
988a2cae
GN		 8770 kvm_for_each_vcpu(i, vcpu, kvm)
8771 kvm_arch_vcpu_free(vcpu);
8772
8773 mutex_lock(&kvm->lock);
8774 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8775 kvm->vcpus[i] = NULL;
d19a9cd2 8776
988a2cae
GN		 8777 atomic_set(&kvm->online_vcpus, 0);
8778 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8779}
8780
ad8ba2cd
SY		 8781void kvm_arch_sync_events(struct kvm *kvm)
8782{
332967a3 8783 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8784 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8785 kvm_free_pit(kvm);
ad8ba2cd
SY		 8786}
8787
1d8007bd 8788int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8789{
8790 int i, r;
25188b99 8791 unsigned long hva;
f0d648bd
PB		 8792 struct kvm_memslots *slots = kvm_memslots(kvm);
8793 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8794
8795 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8796 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8797 return -EINVAL;
9da0e4d5 8798
f0d648bd
PB		 8799 slot = id_to_memslot(slots, id);
8800 if (size) {
b21629da 8801 if (slot->npages)
f0d648bd
PB		 8802 return -EEXIST;
8803
8804 /*
8805 * MAP_SHARED to prevent internal slot pages from being moved
8806 * by fork()/COW.
8807 */
8808 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8809 MAP_SHARED | MAP_ANONYMOUS, 0);
8810 if (IS_ERR((void *)hva))
8811 return PTR_ERR((void *)hva);
8812 } else {
8813 if (!slot->npages)
8814 return 0;
8815
8816 hva = 0;
8817 }
8818
8819 old = *slot;
9da0e4d5 8820 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8821 struct kvm_userspace_memory_region m;
9da0e4d5 8822
1d8007bd
PB		 8823 m.slot = id | (i << 16);
8824 m.flags = 0;
8825 m.guest_phys_addr = gpa;
f0d648bd 8826 m.userspace_addr = hva;
1d8007bd 8827 m.memory_size = size;
9da0e4d5
PB		 8828 r = __kvm_set_memory_region(kvm, &m);
8829 if (r < 0)
8830 return r;
8831 }
8832
103c763c
EB		 8833 if (!size)
8834 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8835
9da0e4d5
PB		 8836 return 0;
8837}
8838EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8839
1d8007bd 8840int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8841{
8842 int r;
8843
8844 mutex_lock(&kvm->slots_lock);
1d8007bd 8845 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8846 mutex_unlock(&kvm->slots_lock);
8847
8848 return r;
8849}
8850EXPORT_SYMBOL_GPL(x86_set_memory_region);
8851
d19a9cd2
ZX		 8852void kvm_arch_destroy_vm(struct kvm *kvm)
8853{
27469d29
AH		 8854 if (current->mm == kvm->mm) {
8855 /*
8856 * Free memory regions allocated on behalf of userspace,
8857 * unless the the memory map has changed due to process exit
8858 * or fd copying.
8859 */
1d8007bd
PB		 8860 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8861 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8862 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8863 }
03543133
SS		 8864 if (kvm_x86_ops->vm_destroy)
8865 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8866 kvm_pic_destroy(kvm);
8867 kvm_ioapic_destroy(kvm);
d19a9cd2 8868 kvm_free_vcpus(kvm);
af1bae54 8869 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8870 kvm_mmu_uninit_vm(kvm);
2beb6dad 8871 kvm_page_track_cleanup(kvm);
cbc0236a 8872 kvm_hv_destroy_vm(kvm);
d19a9cd2 8873}
0de10343 8874
5587027c 8875void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8876 struct kvm_memory_slot *dont)
8877{
8878 int i;
8879
d89cc617
TY		 8880 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8881 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8882 kvfree(free->arch.rmap[i]);
d89cc617 8883 free->arch.rmap[i] = NULL;
77d11309 8884 }
d89cc617
TY		 8885 if (i == 0)
8886 continue;
8887
8888 if (!dont || free->arch.lpage_info[i - 1] !=
8889 dont->arch.lpage_info[i - 1]) {
548ef284 8890 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8891 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8892 }
8893 }
21ebbeda
XG		 8894
8895 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8896}
8897
5587027c
AK		 8898int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8899 unsigned long npages)
db3fe4eb
TY		 8900{
8901 int i;
8902
d89cc617 8903 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8904 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8905 unsigned long ugfn;
8906 int lpages;
d89cc617 8907 int level = i + 1;
db3fe4eb
TY		 8908
8909 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8910 slot->base_gfn, level) + 1;
8911
d89cc617 8912 slot->arch.rmap[i] =
778e1cdd
KC		 8913 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
8914 GFP_KERNEL);
d89cc617 8915 if (!slot->arch.rmap[i])
77d11309 8916 goto out_free;
d89cc617
TY		 8917 if (i == 0)
8918 continue;
77d11309 8919
778e1cdd 8920 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
92f94f1e 8921 if (!linfo)
db3fe4eb
TY		 8922 goto out_free;
8923
92f94f1e
XG		 8924 slot->arch.lpage_info[i - 1] = linfo;
8925
db3fe4eb 8926 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8927 linfo[0].disallow_lpage = 1;
db3fe4eb 8928 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8929 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8930 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8931 /*
8932 * If the gfn and userspace address are not aligned wrt each
8933 * other, or if explicitly asked to, disable large page
8934 * support for this slot
8935 */
8936 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8937 !kvm_largepages_enabled()) {
8938 unsigned long j;
8939
8940 for (j = 0; j < lpages; ++j)
92f94f1e 8941 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8942 }
8943 }
8944
21ebbeda
XG		 8945 if (kvm_page_track_create_memslot(slot, npages))
8946 goto out_free;
8947
db3fe4eb
TY		 8948 return 0;
8949
8950out_free:
d89cc617 8951 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8952 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8953 slot->arch.rmap[i] = NULL;
8954 if (i == 0)
8955 continue;
8956
548ef284 8957 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8958 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8959 }
8960 return -ENOMEM;
8961}
8962
15f46015 8963void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8964{
e6dff7d1
TY		 8965 /*
8966 * memslots->generation has been incremented.
8967 * mmio generation may have reached its maximum value.
8968 */
54bf36aa 8969 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8970}
8971
f7784b8e
MT		 8972int kvm_arch_prepare_memory_region(struct kvm *kvm,
8973 struct kvm_memory_slot *memslot,
09170a49 8974 const struct kvm_userspace_memory_region *mem,
7b6195a9 8975 enum kvm_mr_change change)
0de10343 8976{
f7784b8e
MT		 8977 return 0;
8978}
8979
88178fd4
KH		 8980static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8981 struct kvm_memory_slot *new)
8982{
8983 /* Still write protect RO slot */
8984 if (new->flags & KVM_MEM_READONLY) {
8985 kvm_mmu_slot_remove_write_access(kvm, new);
8986 return;
8987 }
8988
8989 /*
8990 * Call kvm_x86_ops dirty logging hooks when they are valid.
8991 *
8992 * kvm_x86_ops->slot_disable_log_dirty is called when:
8993 *
8994 * - KVM_MR_CREATE with dirty logging is disabled
8995 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8996 *
8997 * The reason is, in case of PML, we need to set D-bit for any slots
8998 * with dirty logging disabled in order to eliminate unnecessary GPA
8999 * logging in PML buffer (and potential PML buffer full VMEXT). This
9000 * guarantees leaving PML enabled during guest's lifetime won't have
9001 * any additonal overhead from PML when guest is running with dirty
9002 * logging disabled for memory slots.
9003 *
9004 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9005 * to dirty logging mode.
9006 *
9007 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9008 *
9009 * In case of write protect:
9010 *
9011 * Write protect all pages for dirty logging.
9012 *
9013 * All the sptes including the large sptes which point to this
9014 * slot are set to readonly. We can not create any new large
9015 * spte on this slot until the end of the logging.
9016 *
9017 * See the comments in fast_page_fault().
9018 */
9019 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9020 if (kvm_x86_ops->slot_enable_log_dirty)
9021 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9022 else
9023 kvm_mmu_slot_remove_write_access(kvm, new);
9024 } else {
9025 if (kvm_x86_ops->slot_disable_log_dirty)
9026 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9027 }
9028}
9029
f7784b8e 9030void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9031 const struct kvm_userspace_memory_region *mem,
8482644a 9032 const struct kvm_memory_slot *old,
f36f3f28 9033 const struct kvm_memory_slot *new,
8482644a 9034 enum kvm_mr_change change)
f7784b8e 9035{
8482644a 9036 int nr_mmu_pages = 0;
f7784b8e 9037
48c0e4e9
XG		 9038 if (!kvm->arch.n_requested_mmu_pages)
9039 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9040
48c0e4e9 9041 if (nr_mmu_pages)
0de10343 9042 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9043
3ea3b7fa
WL		 9044 /*
9045 * Dirty logging tracks sptes in 4k granularity, meaning that large
9046 * sptes have to be split. If live migration is successful, the guest
9047 * in the source machine will be destroyed and large sptes will be
9048 * created in the destination. However, if the guest continues to run
9049 * in the source machine (for example if live migration fails), small
9050 * sptes will remain around and cause bad performance.
9051 *
9052 * Scan sptes if dirty logging has been stopped, dropping those
9053 * which can be collapsed into a single large-page spte. Later
9054 * page faults will create the large-page sptes.
9055 */
9056 if ((change != KVM_MR_DELETE) &&
9057 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9058 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9059 kvm_mmu_zap_collapsible_sptes(kvm, new);
9060
c972f3b1 9061 /*
88178fd4 9062 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9063 *
88178fd4
KH		 9064 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9065 * been zapped so no dirty logging staff is needed for old slot. For
9066 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9067 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9068 *
9069 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9070 */
88178fd4 9071 if (change != KVM_MR_DELETE)
f36f3f28 9072 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9073}
1d737c8a 9074
2df72e9b 9075void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9076{
6ca18b69 9077 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9078}
9079
2df72e9b
MT		 9080void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9081 struct kvm_memory_slot *slot)
9082{
ae7cd873 9083 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9084}
9085
5d9bc648
PB		 9086static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9087{
9088 if (!list_empty_careful(&vcpu->async_pf.done))
9089 return true;
9090
9091 if (kvm_apic_has_events(vcpu))
9092 return true;
9093
9094 if (vcpu->arch.pv.pv_unhalted)
9095 return true;
9096
a5f01f8e
WL		 9097 if (vcpu->arch.exception.pending)
9098 return true;
9099
47a66eed
Z		 9100 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9101 (vcpu->arch.nmi_pending &&
9102 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9103 return true;
9104
47a66eed
Z		 9105 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9106 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9107 return true;
9108
5d9bc648
PB		 9109 if (kvm_arch_interrupt_allowed(vcpu) &&
9110 kvm_cpu_has_interrupt(vcpu))
9111 return true;
9112
1f4b34f8
AS		 9113 if (kvm_hv_has_stimer_pending(vcpu))
9114 return true;
9115
5d9bc648
PB		 9116 return false;
9117}
9118
1d737c8a
ZX		 9119int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9120{
5d9bc648 9121 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9122}
5736199a 9123
199b5763
LM		 9124bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9125{
de63ad4c 9126 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9127}
9128
b6d33834 9129int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9130{
b6d33834 9131 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9132}
78646121
GN		 9133
9134int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9135{
9136 return kvm_x86_ops->interrupt_allowed(vcpu);
9137}
229456fc 9138
82b32774 9139unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9140{
82b32774
NA		 9141 if (is_64_bit_mode(vcpu))
9142 return kvm_rip_read(vcpu);
9143 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9144 kvm_rip_read(vcpu));
9145}
9146EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9147
82b32774
NA		 9148bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9149{
9150 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9151}
9152EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9153
94fe45da
JK		 9154unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9155{
9156 unsigned long rflags;
9157
9158 rflags = kvm_x86_ops->get_rflags(vcpu);
9159 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9160 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9161 return rflags;
9162}
9163EXPORT_SYMBOL_GPL(kvm_get_rflags);
9164
6addfc42 9165static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9166{
9167 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9168 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9169 rflags |= X86_EFLAGS_TF;
94fe45da 9170 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9171}
9172
9173void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9174{
9175 __kvm_set_rflags(vcpu, rflags);
3842d135 9176 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9177}
9178EXPORT_SYMBOL_GPL(kvm_set_rflags);
9179
56028d08
GN		 9180void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9181{
9182 int r;
9183
fb67e14f 9184 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 9185 work->wakeup_all)
56028d08
GN		 9186 return;
9187
9188 r = kvm_mmu_reload(vcpu);
9189 if (unlikely(r))
9190 return;
9191
fb67e14f
XG		 9192 if (!vcpu->arch.mmu.direct_map &&
9193 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9194 return;
9195
56028d08
GN		 9196 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9197}
9198
af585b92
GN		 9199static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9200{
9201 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9202}
9203
9204static inline u32 kvm_async_pf_next_probe(u32 key)
9205{
9206 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9207}
9208
9209static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9210{
9211 u32 key = kvm_async_pf_hash_fn(gfn);
9212
9213 while (vcpu->arch.apf.gfns[key] != ~0)
9214 key = kvm_async_pf_next_probe(key);
9215
9216 vcpu->arch.apf.gfns[key] = gfn;
9217}
9218
9219static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9220{
9221 int i;
9222 u32 key = kvm_async_pf_hash_fn(gfn);
9223
9224 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9225 (vcpu->arch.apf.gfns[key] != gfn &&
9226 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9227 key = kvm_async_pf_next_probe(key);
9228
9229 return key;
9230}
9231
9232bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9233{
9234 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9235}
9236
9237static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9238{
9239 u32 i, j, k;
9240
9241 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9242 while (true) {
9243 vcpu->arch.apf.gfns[i] = ~0;
9244 do {
9245 j = kvm_async_pf_next_probe(j);
9246 if (vcpu->arch.apf.gfns[j] == ~0)
9247 return;
9248 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9249 /*
9250 * k lies cyclically in ]i,j]
9251 * | i.k.j |
9252 * |....j i.k.| or |.k..j i...|
9253 */
9254 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9255 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9256 i = j;
9257 }
9258}
9259
7c90705b
GN		 9260static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9261{
4e335d9e
PB		 9262
9263 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9264 sizeof(val));
7c90705b
GN		 9265}
9266
9a6e7c39
WL		 9267static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9268{
9269
9270 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9271 sizeof(u32));
9272}
9273
af585b92
GN		 9274void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9275 struct kvm_async_pf *work)
9276{
6389ee94
AK		 9277 struct x86_exception fault;
9278
7c90705b 9279 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9280 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9281
9282 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9283 (vcpu->arch.apf.send_user_only &&
9284 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9285 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9286 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9287 fault.vector = PF_VECTOR;
9288 fault.error_code_valid = true;
9289 fault.error_code = 0;
9290 fault.nested_page_fault = false;
9291 fault.address = work->arch.token;
adfe20fb 9292 fault.async_page_fault = true;
6389ee94 9293 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9294 }
af585b92
GN		 9295}
9296
9297void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9298 struct kvm_async_pf *work)
9299{
6389ee94 9300 struct x86_exception fault;
9a6e7c39 9301 u32 val;
6389ee94 9302
f2e10669 9303 if (work->wakeup_all)
7c90705b
GN		 9304 work->arch.token = ~0; /* broadcast wakeup */
9305 else
9306 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9307 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9308
9a6e7c39
WL		 9309 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9310 !apf_get_user(vcpu, &val)) {
9311 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9312 vcpu->arch.exception.pending &&
9313 vcpu->arch.exception.nr == PF_VECTOR &&
9314 !apf_put_user(vcpu, 0)) {
9315 vcpu->arch.exception.injected = false;
9316 vcpu->arch.exception.pending = false;
9317 vcpu->arch.exception.nr = 0;
9318 vcpu->arch.exception.has_error_code = false;
9319 vcpu->arch.exception.error_code = 0;
9320 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9321 fault.vector = PF_VECTOR;
9322 fault.error_code_valid = true;
9323 fault.error_code = 0;
9324 fault.nested_page_fault = false;
9325 fault.address = work->arch.token;
9326 fault.async_page_fault = true;
9327 kvm_inject_page_fault(vcpu, &fault);
9328 }
7c90705b 9329 }
e6d53e3b 9330 vcpu->arch.apf.halted = false;
a4fa1635 9331 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9332}
9333
9334bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9335{
9336 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9337 return true;
9338 else
9bc1f09f 9339 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9340}
9341
5544eb9b
PB		 9342void kvm_arch_start_assignment(struct kvm *kvm)
9343{
9344 atomic_inc(&kvm->arch.assigned_device_count);
9345}
9346EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9347
9348void kvm_arch_end_assignment(struct kvm *kvm)
9349{
9350 atomic_dec(&kvm->arch.assigned_device_count);
9351}
9352EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9353
9354bool kvm_arch_has_assigned_device(struct kvm *kvm)
9355{
9356 return atomic_read(&kvm->arch.assigned_device_count);
9357}
9358EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9359
e0f0bbc5
AW		 9360void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9361{
9362 atomic_inc(&kvm->arch.noncoherent_dma_count);
9363}
9364EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9365
9366void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9367{
9368 atomic_dec(&kvm->arch.noncoherent_dma_count);
9369}
9370EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9371
9372bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9373{
9374 return atomic_read(&kvm->arch.noncoherent_dma_count);
9375}
9376EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9377
14717e20
AW		 9378bool kvm_arch_has_irq_bypass(void)
9379{
9380 return kvm_x86_ops->update_pi_irte != NULL;
9381}
9382
87276880
FW		 9383int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9384 struct irq_bypass_producer *prod)
9385{
9386 struct kvm_kernel_irqfd *irqfd =
9387 container_of(cons, struct kvm_kernel_irqfd, consumer);
9388
14717e20 9389 irqfd->producer = prod;
87276880 9390
14717e20
AW		 9391 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9392 prod->irq, irqfd->gsi, 1);
87276880
FW		 9393}
9394
9395void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9396 struct irq_bypass_producer *prod)
9397{
9398 int ret;
9399 struct kvm_kernel_irqfd *irqfd =
9400 container_of(cons, struct kvm_kernel_irqfd, consumer);
9401
87276880
FW		 9402 WARN_ON(irqfd->producer != prod);
9403 irqfd->producer = NULL;
9404
9405 /*
9406 * When producer of consumer is unregistered, we change back to
9407 * remapped mode, so we can re-use the current implementation
bb3541f1 9408 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9409 * int this case doesn't want to receive the interrupts.
9410 */
9411 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9412 if (ret)
9413 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9414 " fails: %d\n", irqfd->consumer.token, ret);
9415}
9416
9417int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9418 uint32_t guest_irq, bool set)
9419{
9420 if (!kvm_x86_ops->update_pi_irte)
9421 return -EINVAL;
9422
9423 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9424}
9425
52004014
FW		 9426bool kvm_vector_hashing_enabled(void)
9427{
9428 return vector_hashing;
9429}
9430EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9431
229456fc 9432EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9433EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9434EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9435EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9436EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9437EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9438EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9439EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9440EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9441EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9442EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9443EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9444EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9445EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9446EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9447EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9448EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9449EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9450EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)