projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86: do not go through vcpu in __get_kvmclock_ns
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
1767e931
PG		 39#include <linux/export.h>
40#include <linux/moduleparam.h>
0de10343 41#include <linux/mman.h>
2bacc55c 42#include <linux/highmem.h>
19de40a8 43#include <linux/iommu.h>
62c476c7 44#include <linux/intel-iommu.h>
c8076604 45#include <linux/cpufreq.h>
18863bdd 46#include <linux/user-return-notifier.h>
a983fb23 47#include <linux/srcu.h>
5a0e3ad6 48#include <linux/slab.h>
ff9d07a0 49#include <linux/perf_event.h>
7bee342a 50#include <linux/uaccess.h>
af585b92 51#include <linux/hash.h>
a1b60c1c 52#include <linux/pci.h>
16e8d74d
MT		 53#include <linux/timekeeper_internal.h>
54#include <linux/pvclock_gtod.h>
87276880
FW		 55#include <linux/kvm_irqfd.h>
56#include <linux/irqbypass.h>
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
043405e1 68
d1898b73
DH		 69#define CREATE_TRACE_POINTS
70#include "trace.h"
71
313a3dc7 72#define MAX_IO_MSRS 256
890ca9ae 73#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 74u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
75EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 76
0f65dd70
AK		 77#define emul_to_vcpu(ctxt) \
78 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
79
50a37eb4
JR		 80/* EFER defaults:
81 * - enable syscall per default because its emulated by KVM
82 * - enable LME and LMA per default on 64 bit KVM
83 */
84#ifdef CONFIG_X86_64
1260edbe
LJ		 85static
86u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 87#else
1260edbe 88static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 89#endif
313a3dc7 90
ba1389b7
AK		 91#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
92#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 93
c519265f
RK		 94#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
95 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 96
cb142eb7 97static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 98static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 99static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 100static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 101
893590c7 102struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 103EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 104
893590c7 105static bool __read_mostly ignore_msrs = 0;
476bc001 106module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 107
9ed96e87
MT		 108unsigned int min_timer_period_us = 500;
109module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
110
630994b3
MT		 111static bool __read_mostly kvmclock_periodic_sync = true;
112module_param(kvmclock_periodic_sync, bool, S_IRUGO);
113
893590c7 114bool __read_mostly kvm_has_tsc_control;
92a1f12d 115EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 116u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 117EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 118u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
119EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
120u64 __read_mostly kvm_max_tsc_scaling_ratio;
121EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 122u64 __read_mostly kvm_default_tsc_scaling_ratio;
123EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 124
cc578287 125/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 126static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 127module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
128
d0659d94 129/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 130unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 131module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
132
52004014
FW		 133static bool __read_mostly vector_hashing = true;
134module_param(vector_hashing, bool, S_IRUGO);
135
893590c7 136static bool __read_mostly backwards_tsc_observed = false;
16a96021 137
18863bdd
AK		 138#define KVM_NR_SHARED_MSRS 16
139
140struct kvm_shared_msrs_global {
141 int nr;
2bf78fa7 142 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 143};
144
145struct kvm_shared_msrs {
146 struct user_return_notifier urn;
147 bool registered;
2bf78fa7
SY		 148 struct kvm_shared_msr_values {
149 u64 host;
150 u64 curr;
151 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 152};
153
154static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 155static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 156
417bc304 157struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 158 { "pf_fixed", VCPU_STAT(pf_fixed) },
159 { "pf_guest", VCPU_STAT(pf_guest) },
160 { "tlb_flush", VCPU_STAT(tlb_flush) },
161 { "invlpg", VCPU_STAT(invlpg) },
162 { "exits", VCPU_STAT(exits) },
163 { "io_exits", VCPU_STAT(io_exits) },
164 { "mmio_exits", VCPU_STAT(mmio_exits) },
165 { "signal_exits", VCPU_STAT(signal_exits) },
166 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 167 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 168 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 169 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 170 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 171 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 172 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 173 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 174 { "request_irq", VCPU_STAT(request_irq_exits) },
175 { "irq_exits", VCPU_STAT(irq_exits) },
176 { "host_state_reload", VCPU_STAT(host_state_reload) },
177 { "efer_reload", VCPU_STAT(efer_reload) },
178 { "fpu_reload", VCPU_STAT(fpu_reload) },
179 { "insn_emulation", VCPU_STAT(insn_emulation) },
180 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 181 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 182 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 183 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
184 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
185 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
186 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
187 { "mmu_flooded", VM_STAT(mmu_flooded) },
188 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 189 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 190 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 191 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 192 { "largepages", VM_STAT(lpages) },
417bc304
HB		 193 { NULL }
194};
195
2acf923e
DC		 196u64 __read_mostly host_xcr0;
197
b6785def 198static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 199
af585b92
GN		 200static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
201{
202 int i;
203 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
204 vcpu->arch.apf.gfns[i] = ~0;
205}
206
18863bdd
AK		 207static void kvm_on_user_return(struct user_return_notifier *urn)
208{
209 unsigned slot;
18863bdd
AK		 210 struct kvm_shared_msrs *locals
211 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 212 struct kvm_shared_msr_values *values;
18863bdd
AK		 213
214 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 215 values = &locals->values[slot];
216 if (values->host != values->curr) {
217 wrmsrl(shared_msrs_global.msrs[slot], values->host);
218 values->curr = values->host;
18863bdd
AK		 219 }
220 }
221 locals->registered = false;
222 user_return_notifier_unregister(urn);
223}
224
2bf78fa7 225static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 226{
18863bdd 227 u64 value;
013f6a5d
MT		 228 unsigned int cpu = smp_processor_id();
229 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 230
2bf78fa7
SY		 231 /* only read, and nobody should modify it at this time,
232 * so don't need lock */
233 if (slot >= shared_msrs_global.nr) {
234 printk(KERN_ERR "kvm: invalid MSR slot!");
235 return;
236 }
237 rdmsrl_safe(msr, &value);
238 smsr->values[slot].host = value;
239 smsr->values[slot].curr = value;
240}
241
242void kvm_define_shared_msr(unsigned slot, u32 msr)
243{
0123be42 244 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 245 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 246 if (slot >= shared_msrs_global.nr)
247 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 248}
249EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
250
251static void kvm_shared_msr_cpu_online(void)
252{
253 unsigned i;
18863bdd
AK		 254
255 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 256 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 257}
258
8b3c3104 259int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 260{
013f6a5d
MT		 261 unsigned int cpu = smp_processor_id();
262 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 263 int err;
18863bdd 264
2bf78fa7 265 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 266 return 0;
2bf78fa7 267 smsr->values[slot].curr = value;
8b3c3104
AH		 268 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
269 if (err)
270 return 1;
271
18863bdd
AK		 272 if (!smsr->registered) {
273 smsr->urn.on_user_return = kvm_on_user_return;
274 user_return_notifier_register(&smsr->urn);
275 smsr->registered = true;
276 }
8b3c3104 277 return 0;
18863bdd
AK		 278}
279EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
280
13a34e06 281static void drop_user_return_notifiers(void)
3548bab5 282{
013f6a5d
MT		 283 unsigned int cpu = smp_processor_id();
284 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 285
286 if (smsr->registered)
287 kvm_on_user_return(&smsr->urn);
288}
289
6866b83e
CO		 290u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
291{
8a5a87d9 292 return vcpu->arch.apic_base;
6866b83e
CO		 293}
294EXPORT_SYMBOL_GPL(kvm_get_apic_base);
295
58cb628d
JK		 296int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
297{
298 u64 old_state = vcpu->arch.apic_base &
299 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
300 u64 new_state = msr_info->data &
301 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
302 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
303 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
304
305 if (!msr_info->host_initiated &&
306 ((msr_info->data & reserved_bits) != 0 ||
307 new_state == X2APIC_ENABLE ||
308 (new_state == MSR_IA32_APICBASE_ENABLE &&
309 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
310 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
311 old_state == 0)))
312 return 1;
313
314 kvm_lapic_set_base(vcpu, msr_info->data);
315 return 0;
6866b83e
CO		 316}
317EXPORT_SYMBOL_GPL(kvm_set_apic_base);
318
2605fc21 319asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 320{
321 /* Fault while not rebooting. We want the trace. */
322 BUG();
323}
324EXPORT_SYMBOL_GPL(kvm_spurious_fault);
325
3fd28fce
ED		 326#define EXCPT_BENIGN 0
327#define EXCPT_CONTRIBUTORY 1
328#define EXCPT_PF 2
329
330static int exception_class(int vector)
331{
332 switch (vector) {
333 case PF_VECTOR:
334 return EXCPT_PF;
335 case DE_VECTOR:
336 case TS_VECTOR:
337 case NP_VECTOR:
338 case SS_VECTOR:
339 case GP_VECTOR:
340 return EXCPT_CONTRIBUTORY;
341 default:
342 break;
343 }
344 return EXCPT_BENIGN;
345}
346
d6e8c854
NA		 347#define EXCPT_FAULT 0
348#define EXCPT_TRAP 1
349#define EXCPT_ABORT 2
350#define EXCPT_INTERRUPT 3
351
352static int exception_type(int vector)
353{
354 unsigned int mask;
355
356 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
357 return EXCPT_INTERRUPT;
358
359 mask = 1 << vector;
360
361 /* #DB is trap, as instruction watchpoints are handled elsewhere */
362 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
363 return EXCPT_TRAP;
364
365 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
366 return EXCPT_ABORT;
367
368 /* Reserved exceptions will result in fault */
369 return EXCPT_FAULT;
370}
371
3fd28fce 372static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 373 unsigned nr, bool has_error, u32 error_code,
374 bool reinject)
3fd28fce
ED		 375{
376 u32 prev_nr;
377 int class1, class2;
378
3842d135
AK		 379 kvm_make_request(KVM_REQ_EVENT, vcpu);
380
3fd28fce
ED		 381 if (!vcpu->arch.exception.pending) {
382 queue:
3ffb2468
NA		 383 if (has_error && !is_protmode(vcpu))
384 has_error = false;
3fd28fce
ED		 385 vcpu->arch.exception.pending = true;
386 vcpu->arch.exception.has_error_code = has_error;
387 vcpu->arch.exception.nr = nr;
388 vcpu->arch.exception.error_code = error_code;
3f0fd292 389 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 390 return;
391 }
392
393 /* to check exception */
394 prev_nr = vcpu->arch.exception.nr;
395 if (prev_nr == DF_VECTOR) {
396 /* triple fault -> shutdown */
a8eeb04a 397 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 398 return;
399 }
400 class1 = exception_class(prev_nr);
401 class2 = exception_class(nr);
402 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
403 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
404 /* generate double fault per SDM Table 5-5 */
405 vcpu->arch.exception.pending = true;
406 vcpu->arch.exception.has_error_code = true;
407 vcpu->arch.exception.nr = DF_VECTOR;
408 vcpu->arch.exception.error_code = 0;
409 } else
410 /* replace previous exception with a new one in a hope
411 that instruction re-execution will regenerate lost
412 exception */
413 goto queue;
414}
415
298101da
AK		 416void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
417{
ce7ddec4 418 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 419}
420EXPORT_SYMBOL_GPL(kvm_queue_exception);
421
ce7ddec4
JR		 422void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
423{
424 kvm_multiple_exception(vcpu, nr, false, 0, true);
425}
426EXPORT_SYMBOL_GPL(kvm_requeue_exception);
427
db8fcefa 428void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 429{
db8fcefa
AP		 430 if (err)
431 kvm_inject_gp(vcpu, 0);
432 else
433 kvm_x86_ops->skip_emulated_instruction(vcpu);
434}
435EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 436
6389ee94 437void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 438{
439 ++vcpu->stat.pf_guest;
6389ee94
AK		 440 vcpu->arch.cr2 = fault->address;
441 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 442}
27d6c865 443EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 444
ef54bcfe 445static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 446{
6389ee94
AK		 447 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
448 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 449 else
6389ee94 450 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 451
452 return fault->nested_page_fault;
d4f8cf66
JR		 453}
454
3419ffc8
SY		 455void kvm_inject_nmi(struct kvm_vcpu *vcpu)
456{
7460fb4a
AK		 457 atomic_inc(&vcpu->arch.nmi_queued);
458 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 459}
460EXPORT_SYMBOL_GPL(kvm_inject_nmi);
461
298101da
AK		 462void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
463{
ce7ddec4 464 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 465}
466EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
467
ce7ddec4
JR		 468void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
469{
470 kvm_multiple_exception(vcpu, nr, true, error_code, true);
471}
472EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
473
0a79b009
AK		 474/*
475 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
476 * a #GP and return false.
477 */
478bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 479{
0a79b009
AK		 480 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
481 return true;
482 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
483 return false;
298101da 484}
0a79b009 485EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 486
16f8a6f9
NA		 487bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
488{
489 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
490 return true;
491
492 kvm_queue_exception(vcpu, UD_VECTOR);
493 return false;
494}
495EXPORT_SYMBOL_GPL(kvm_require_dr);
496
ec92fe44
JR		 497/*
498 * This function will be used to read from the physical memory of the currently
54bf36aa 499 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 500 * can read from guest physical or from the guest's guest physical memory.
501 */
502int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
503 gfn_t ngfn, void *data, int offset, int len,
504 u32 access)
505{
54987b7a 506 struct x86_exception exception;
ec92fe44
JR		 507 gfn_t real_gfn;
508 gpa_t ngpa;
509
510 ngpa = gfn_to_gpa(ngfn);
54987b7a 511 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 512 if (real_gfn == UNMAPPED_GVA)
513 return -EFAULT;
514
515 real_gfn = gpa_to_gfn(real_gfn);
516
54bf36aa 517 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 518}
519EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
520
69b0049a 521static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 522 void *data, int offset, int len, u32 access)
523{
524 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
525 data, offset, len, access);
526}
527
a03490ed
CO		 528/*
529 * Load the pae pdptrs. Return true is they are all valid.
530 */
ff03a073 531int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 532{
533 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
534 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
535 int i;
536 int ret;
ff03a073 537 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 538
ff03a073
JR		 539 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
540 offset * sizeof(u64), sizeof(pdpte),
541 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 542 if (ret < 0) {
543 ret = 0;
544 goto out;
545 }
546 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 547 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 548 (pdpte[i] &
549 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 550 ret = 0;
551 goto out;
552 }
553 }
554 ret = 1;
555
ff03a073 556 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 557 __set_bit(VCPU_EXREG_PDPTR,
558 (unsigned long *)&vcpu->arch.regs_avail);
559 __set_bit(VCPU_EXREG_PDPTR,
560 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 561out:
a03490ed
CO		 562
563 return ret;
564}
cc4b6871 565EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 566
d835dfec
AK		 567static bool pdptrs_changed(struct kvm_vcpu *vcpu)
568{
ff03a073 569 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 570 bool changed = true;
3d06b8bf
JR		 571 int offset;
572 gfn_t gfn;
d835dfec
AK		 573 int r;
574
575 if (is_long_mode(vcpu) || !is_pae(vcpu))
576 return false;
577
6de4f3ad
AK		 578 if (!test_bit(VCPU_EXREG_PDPTR,
579 (unsigned long *)&vcpu->arch.regs_avail))
580 return true;
581
9f8fe504
AK		 582 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
583 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 584 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
585 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 586 if (r < 0)
587 goto out;
ff03a073 588 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 589out:
d835dfec
AK		 590
591 return changed;
592}
593
49a9b07e 594int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 595{
aad82703 596 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 597 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 598
f9a48e6a
AK		 599 cr0 |= X86_CR0_ET;
600
ab344828 601#ifdef CONFIG_X86_64
0f12244f
GN		 602 if (cr0 & 0xffffffff00000000UL)
603 return 1;
ab344828
GN		 604#endif
605
606 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 607
0f12244f
GN		 608 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
609 return 1;
a03490ed 610
0f12244f
GN		 611 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
612 return 1;
a03490ed
CO		 613
614 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
615#ifdef CONFIG_X86_64
f6801dff 616 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 617 int cs_db, cs_l;
618
0f12244f
GN		 619 if (!is_pae(vcpu))
620 return 1;
a03490ed 621 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 622 if (cs_l)
623 return 1;
a03490ed
CO		 624 } else
625#endif
ff03a073 626 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 627 kvm_read_cr3(vcpu)))
0f12244f 628 return 1;
a03490ed
CO		 629 }
630
ad756a16
MJ		 631 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
632 return 1;
633
a03490ed 634 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 635
d170c419 636 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 637 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 638 kvm_async_pf_hash_reset(vcpu);
639 }
e5f3f027 640
aad82703
SY		 641 if ((cr0 ^ old_cr0) & update_bits)
642 kvm_mmu_reset_context(vcpu);
b18d5431 643
879ae188
LE		 644 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
645 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
646 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 647 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
648
0f12244f
GN		 649 return 0;
650}
2d3ad1f4 651EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 652
2d3ad1f4 653void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 654{
49a9b07e 655 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 656}
2d3ad1f4 657EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 658
42bdf991
MT		 659static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
660{
661 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
662 !vcpu->guest_xcr0_loaded) {
663 /* kvm_set_xcr() also depends on this */
664 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
665 vcpu->guest_xcr0_loaded = 1;
666 }
667}
668
669static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
670{
671 if (vcpu->guest_xcr0_loaded) {
672 if (vcpu->arch.xcr0 != host_xcr0)
673 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
674 vcpu->guest_xcr0_loaded = 0;
675 }
676}
677
69b0049a 678static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 679{
56c103ec
LJ		 680 u64 xcr0 = xcr;
681 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 682 u64 valid_bits;
2acf923e
DC		 683
684 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
685 if (index != XCR_XFEATURE_ENABLED_MASK)
686 return 1;
d91cab78 687 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 688 return 1;
d91cab78 689 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 690 return 1;
46c34cb0
PB		 691
692 /*
693 * Do not allow the guest to set bits that we do not support
694 * saving. However, xcr0 bit 0 is always set, even if the
695 * emulated CPU does not support XSAVE (see fx_init).
696 */
d91cab78 697 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 698 if (xcr0 & ~valid_bits)
2acf923e 699 return 1;
46c34cb0 700
d91cab78
DH		 701 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
702 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 703 return 1;
704
d91cab78
DH		 705 if (xcr0 & XFEATURE_MASK_AVX512) {
706 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 707 return 1;
d91cab78 708 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 709 return 1;
710 }
2acf923e 711 vcpu->arch.xcr0 = xcr0;
56c103ec 712
d91cab78 713 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 714 kvm_update_cpuid(vcpu);
2acf923e
DC		 715 return 0;
716}
717
718int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
719{
764bcbc5
Z		 720 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
721 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 722 kvm_inject_gp(vcpu, 0);
723 return 1;
724 }
725 return 0;
726}
727EXPORT_SYMBOL_GPL(kvm_set_xcr);
728
a83b29c6 729int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 730{
fc78f519 731 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 732 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 733 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 734
0f12244f
GN		 735 if (cr4 & CR4_RESERVED_BITS)
736 return 1;
a03490ed 737
2acf923e
DC		 738 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
739 return 1;
740
c68b734f
YW		 741 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
742 return 1;
743
97ec8c06
FW		 744 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
745 return 1;
746
afcbf13f 747 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 748 return 1;
749
b9baba86
HH		 750 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
751 return 1;
752
a03490ed 753 if (is_long_mode(vcpu)) {
0f12244f
GN		 754 if (!(cr4 & X86_CR4_PAE))
755 return 1;
a2edf57f
AK		 756 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
757 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 758 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
759 kvm_read_cr3(vcpu)))
0f12244f
GN		 760 return 1;
761
ad756a16
MJ		 762 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
763 if (!guest_cpuid_has_pcid(vcpu))
764 return 1;
765
766 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
767 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
768 return 1;
769 }
770
5e1746d6 771 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 772 return 1;
a03490ed 773
ad756a16
MJ		 774 if (((cr4 ^ old_cr4) & pdptr_bits) ||
775 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 776 kvm_mmu_reset_context(vcpu);
0f12244f 777
b9baba86 778 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 779 kvm_update_cpuid(vcpu);
2acf923e 780
0f12244f
GN		 781 return 0;
782}
2d3ad1f4 783EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 784
2390218b 785int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 786{
ac146235 787#ifdef CONFIG_X86_64
9d88fca7 788 cr3 &= ~CR3_PCID_INVD;
ac146235 789#endif
9d88fca7 790
9f8fe504 791 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 792 kvm_mmu_sync_roots(vcpu);
77c3913b 793 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 794 return 0;
d835dfec
AK		 795 }
796
a03490ed 797 if (is_long_mode(vcpu)) {
d9f89b88
JK		 798 if (cr3 & CR3_L_MODE_RESERVED_BITS)
799 return 1;
800 } else if (is_pae(vcpu) && is_paging(vcpu) &&
801 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 802 return 1;
a03490ed 803
0f12244f 804 vcpu->arch.cr3 = cr3;
aff48baa 805 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 806 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 807 return 0;
808}
2d3ad1f4 809EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 810
eea1cff9 811int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 812{
0f12244f
GN		 813 if (cr8 & CR8_RESERVED_BITS)
814 return 1;
35754c98 815 if (lapic_in_kernel(vcpu))
a03490ed
CO		 816 kvm_lapic_set_tpr(vcpu, cr8);
817 else
ad312c7c 818 vcpu->arch.cr8 = cr8;
0f12244f
GN		 819 return 0;
820}
2d3ad1f4 821EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 822
2d3ad1f4 823unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 824{
35754c98 825 if (lapic_in_kernel(vcpu))
a03490ed
CO		 826 return kvm_lapic_get_cr8(vcpu);
827 else
ad312c7c 828 return vcpu->arch.cr8;
a03490ed 829}
2d3ad1f4 830EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 831
ae561ede
NA		 832static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
833{
834 int i;
835
836 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
837 for (i = 0; i < KVM_NR_DB_REGS; i++)
838 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
839 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
840 }
841}
842
73aaf249
JK		 843static void kvm_update_dr6(struct kvm_vcpu *vcpu)
844{
845 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
846 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
847}
848
c8639010
JK		 849static void kvm_update_dr7(struct kvm_vcpu *vcpu)
850{
851 unsigned long dr7;
852
853 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
854 dr7 = vcpu->arch.guest_debug_dr7;
855 else
856 dr7 = vcpu->arch.dr7;
857 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 858 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
859 if (dr7 & DR7_BP_EN_MASK)
860 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 861}
862
6f43ed01
NA		 863static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
864{
865 u64 fixed = DR6_FIXED_1;
866
867 if (!guest_cpuid_has_rtm(vcpu))
868 fixed |= DR6_RTM;
869 return fixed;
870}
871
338dbc97 872static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 873{
874 switch (dr) {
875 case 0 ... 3:
876 vcpu->arch.db[dr] = val;
877 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
878 vcpu->arch.eff_db[dr] = val;
879 break;
880 case 4:
020df079
GN		 881 /* fall through */
882 case 6:
338dbc97
GN		 883 if (val & 0xffffffff00000000ULL)
884 return -1; /* #GP */
6f43ed01 885 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 886 kvm_update_dr6(vcpu);
020df079
GN		 887 break;
888 case 5:
020df079
GN		 889 /* fall through */
890 default: /* 7 */
338dbc97
GN		 891 if (val & 0xffffffff00000000ULL)
892 return -1; /* #GP */
020df079 893 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 894 kvm_update_dr7(vcpu);
020df079
GN		 895 break;
896 }
897
898 return 0;
899}
338dbc97
GN		 900
901int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
902{
16f8a6f9 903 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 904 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 905 return 1;
906 }
907 return 0;
338dbc97 908}
020df079
GN		 909EXPORT_SYMBOL_GPL(kvm_set_dr);
910
16f8a6f9 911int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 912{
913 switch (dr) {
914 case 0 ... 3:
915 *val = vcpu->arch.db[dr];
916 break;
917 case 4:
020df079
GN		 918 /* fall through */
919 case 6:
73aaf249
JK		 920 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
921 *val = vcpu->arch.dr6;
922 else
923 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 924 break;
925 case 5:
020df079
GN		 926 /* fall through */
927 default: /* 7 */
928 *val = vcpu->arch.dr7;
929 break;
930 }
338dbc97
GN		 931 return 0;
932}
020df079
GN		 933EXPORT_SYMBOL_GPL(kvm_get_dr);
934
022cd0e8
AK		 935bool kvm_rdpmc(struct kvm_vcpu *vcpu)
936{
937 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
938 u64 data;
939 int err;
940
c6702c9d 941 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 942 if (err)
943 return err;
944 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
945 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
946 return err;
947}
948EXPORT_SYMBOL_GPL(kvm_rdpmc);
949
043405e1
CO		 950/*
951 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
952 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
953 *
954 * This list is modified at module load time to reflect the
e3267cbb 955 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 956 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
957 * may depend on host virtualization features rather than host cpu features.
043405e1 958 */
e3267cbb 959
043405e1
CO		 960static u32 msrs_to_save[] = {
961 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 962 MSR_STAR,
043405e1
CO		 963#ifdef CONFIG_X86_64
964 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
965#endif
b3897a49 966 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 967 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 968};
969
970static unsigned num_msrs_to_save;
971
62ef68bb
PB		 972static u32 emulated_msrs[] = {
973 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
974 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
975 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
976 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 977 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
978 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 979 HV_X64_MSR_RESET,
11c4b1ca 980 HV_X64_MSR_VP_INDEX,
9eec50b8 981 HV_X64_MSR_VP_RUNTIME,
5c919412 982 HV_X64_MSR_SCONTROL,
1f4b34f8 983 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 984 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
985 MSR_KVM_PV_EOI_EN,
986
ba904635 987 MSR_IA32_TSC_ADJUST,
a3e06bbe 988 MSR_IA32_TSCDEADLINE,
043405e1 989 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 990 MSR_IA32_MCG_STATUS,
991 MSR_IA32_MCG_CTL,
c45dcc71 992 MSR_IA32_MCG_EXT_CTL,
64d60670 993 MSR_IA32_SMBASE,
043405e1
CO		 994};
995
62ef68bb
PB		 996static unsigned num_emulated_msrs;
997
384bb783 998bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 999{
b69e8cae 1000 if (efer & efer_reserved_bits)
384bb783 1001 return false;
15c4a640 1002
1b2fd70c
AG		 1003 if (efer & EFER_FFXSR) {
1004 struct kvm_cpuid_entry2 *feat;
1005
1006 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1007 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1008 return false;
1b2fd70c
AG		 1009 }
1010
d8017474
AG		 1011 if (efer & EFER_SVME) {
1012 struct kvm_cpuid_entry2 *feat;
1013
1014 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1015 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1016 return false;
d8017474
AG		 1017 }
1018
384bb783
JK		 1019 return true;
1020}
1021EXPORT_SYMBOL_GPL(kvm_valid_efer);
1022
1023static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1024{
1025 u64 old_efer = vcpu->arch.efer;
1026
1027 if (!kvm_valid_efer(vcpu, efer))
1028 return 1;
1029
1030 if (is_paging(vcpu)
1031 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1032 return 1;
1033
15c4a640 1034 efer &= ~EFER_LMA;
f6801dff 1035 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1036
a3d204e2
SY		 1037 kvm_x86_ops->set_efer(vcpu, efer);
1038
aad82703
SY		 1039 /* Update reserved bits */
1040 if ((efer ^ old_efer) & EFER_NX)
1041 kvm_mmu_reset_context(vcpu);
1042
b69e8cae 1043 return 0;
15c4a640
CO		 1044}
1045
f2b4b7dd
JR		 1046void kvm_enable_efer_bits(u64 mask)
1047{
1048 efer_reserved_bits &= ~mask;
1049}
1050EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1051
15c4a640
CO		 1052/*
1053 * Writes msr value into into the appropriate "register".
1054 * Returns 0 on success, non-0 otherwise.
1055 * Assumes vcpu_load() was already called.
1056 */
8fe8ab46 1057int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1058{
854e8bb1
NA		 1059 switch (msr->index) {
1060 case MSR_FS_BASE:
1061 case MSR_GS_BASE:
1062 case MSR_KERNEL_GS_BASE:
1063 case MSR_CSTAR:
1064 case MSR_LSTAR:
1065 if (is_noncanonical_address(msr->data))
1066 return 1;
1067 break;
1068 case MSR_IA32_SYSENTER_EIP:
1069 case MSR_IA32_SYSENTER_ESP:
1070 /*
1071 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1072 * non-canonical address is written on Intel but not on
1073 * AMD (which ignores the top 32-bits, because it does
1074 * not implement 64-bit SYSENTER).
1075 *
1076 * 64-bit code should hence be able to write a non-canonical
1077 * value on AMD. Making the address canonical ensures that
1078 * vmentry does not fail on Intel after writing a non-canonical
1079 * value, and that something deterministic happens if the guest
1080 * invokes 64-bit SYSENTER.
1081 */
1082 msr->data = get_canonical(msr->data);
1083 }
8fe8ab46 1084 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1085}
854e8bb1 1086EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1087
313a3dc7
CO		 1088/*
1089 * Adapt set_msr() to msr_io()'s calling convention
1090 */
609e36d3
PB		 1091static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1092{
1093 struct msr_data msr;
1094 int r;
1095
1096 msr.index = index;
1097 msr.host_initiated = true;
1098 r = kvm_get_msr(vcpu, &msr);
1099 if (r)
1100 return r;
1101
1102 *data = msr.data;
1103 return 0;
1104}
1105
313a3dc7
CO		 1106static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1107{
8fe8ab46
WA		 1108 struct msr_data msr;
1109
1110 msr.data = *data;
1111 msr.index = index;
1112 msr.host_initiated = true;
1113 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1114}
1115
16e8d74d
MT		 1116#ifdef CONFIG_X86_64
1117struct pvclock_gtod_data {
1118 seqcount_t seq;
1119
1120 struct { /* extract of a clocksource struct */
1121 int vclock_mode;
1122 cycle_t cycle_last;
1123 cycle_t mask;
1124 u32 mult;
1125 u32 shift;
1126 } clock;
1127
cbcf2dd3
TG		 1128 u64 boot_ns;
1129 u64 nsec_base;
16e8d74d
MT		 1130};
1131
1132static struct pvclock_gtod_data pvclock_gtod_data;
1133
1134static void update_pvclock_gtod(struct timekeeper *tk)
1135{
1136 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1137 u64 boot_ns;
1138
876e7881 1139 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1140
1141 write_seqcount_begin(&vdata->seq);
1142
1143 /* copy pvclock gtod data */
876e7881
PZ		 1144 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1145 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1146 vdata->clock.mask = tk->tkr_mono.mask;
1147 vdata->clock.mult = tk->tkr_mono.mult;
1148 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1149
cbcf2dd3 1150 vdata->boot_ns = boot_ns;
876e7881 1151 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1152
1153 write_seqcount_end(&vdata->seq);
1154}
1155#endif
1156
bab5bb39
NK		 1157void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1158{
1159 /*
1160 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1161 * vcpu_enter_guest. This function is only called from
1162 * the physical CPU that is running vcpu.
1163 */
1164 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1165}
16e8d74d 1166
18068523
GOC		 1167static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1168{
9ed3c444
AK		 1169 int version;
1170 int r;
50d0a0f9 1171 struct pvclock_wall_clock wc;
87aeb54f 1172 struct timespec64 boot;
18068523
GOC		 1173
1174 if (!wall_clock)
1175 return;
1176
9ed3c444
AK		 1177 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1178 if (r)
1179 return;
1180
1181 if (version & 1)
1182 ++version; /* first time write, random junk */
1183
1184 ++version;
18068523 1185
1dab1345
NK		 1186 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1187 return;
18068523 1188
50d0a0f9
GH		 1189 /*
1190 * The guest calculates current wall clock time by adding
34c238a1 1191 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1192 * wall clock specified here. guest system time equals host
1193 * system time for us, thus we must fill in host boot time here.
1194 */
87aeb54f 1195 getboottime64(&boot);
50d0a0f9 1196
4b648665 1197 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1198 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1199 boot = timespec64_sub(boot, ts);
4b648665 1200 }
87aeb54f 1201 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1202 wc.nsec = boot.tv_nsec;
1203 wc.version = version;
18068523
GOC		 1204
1205 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1206
1207 version++;
1208 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1209}
1210
50d0a0f9
GH		 1211static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1212{
b51012de
PB		 1213 do_shl32_div32(dividend, divisor);
1214 return dividend;
50d0a0f9
GH		 1215}
1216
3ae13faa 1217static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1218 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1219{
5f4e3f88 1220 uint64_t scaled64;
50d0a0f9
GH		 1221 int32_t shift = 0;
1222 uint64_t tps64;
1223 uint32_t tps32;
1224
3ae13faa
PB		 1225 tps64 = base_hz;
1226 scaled64 = scaled_hz;
50933623 1227 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1228 tps64 >>= 1;
1229 shift--;
1230 }
1231
1232 tps32 = (uint32_t)tps64;
50933623
JK		 1233 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1234 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1235 scaled64 >>= 1;
1236 else
1237 tps32 <<= 1;
50d0a0f9
GH		 1238 shift++;
1239 }
1240
5f4e3f88
ZA		 1241 *pshift = shift;
1242 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1243
3ae13faa
PB		 1244 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1245 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1246}
1247
d828199e 1248#ifdef CONFIG_X86_64
16e8d74d 1249static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1250#endif
16e8d74d 1251
c8076604 1252static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1253static unsigned long max_tsc_khz;
c8076604 1254
cc578287 1255static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1256{
cc578287
ZA		 1257 u64 v = (u64)khz * (1000000 + ppm);
1258 do_div(v, 1000000);
1259 return v;
1e993611
JR		 1260}
1261
381d585c
HZ		 1262static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1263{
1264 u64 ratio;
1265
1266 /* Guest TSC same frequency as host TSC? */
1267 if (!scale) {
1268 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1269 return 0;
1270 }
1271
1272 /* TSC scaling supported? */
1273 if (!kvm_has_tsc_control) {
1274 if (user_tsc_khz > tsc_khz) {
1275 vcpu->arch.tsc_catchup = 1;
1276 vcpu->arch.tsc_always_catchup = 1;
1277 return 0;
1278 } else {
1279 WARN(1, "user requested TSC rate below hardware speed\n");
1280 return -1;
1281 }
1282 }
1283
1284 /* TSC scaling required - calculate ratio */
1285 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1286 user_tsc_khz, tsc_khz);
1287
1288 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1289 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1290 user_tsc_khz);
1291 return -1;
1292 }
1293
1294 vcpu->arch.tsc_scaling_ratio = ratio;
1295 return 0;
1296}
1297
4941b8cb 1298static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1299{
cc578287
ZA		 1300 u32 thresh_lo, thresh_hi;
1301 int use_scaling = 0;
217fc9cf 1302
03ba32ca 1303 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1304 if (user_tsc_khz == 0) {
ad721883
HZ		 1305 /* set tsc_scaling_ratio to a safe value */
1306 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1307 return -1;
ad721883 1308 }
03ba32ca 1309
c285545f 1310 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1311 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1312 &vcpu->arch.virtual_tsc_shift,
1313 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1314 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1315
1316 /*
1317 * Compute the variation in TSC rate which is acceptable
1318 * within the range of tolerance and decide if the
1319 * rate being applied is within that bounds of the hardware
1320 * rate. If so, no scaling or compensation need be done.
1321 */
1322 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1323 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1324 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1325 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1326 use_scaling = 1;
1327 }
4941b8cb 1328 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1329}
1330
1331static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1332{
e26101b1 1333 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1334 vcpu->arch.virtual_tsc_mult,
1335 vcpu->arch.virtual_tsc_shift);
e26101b1 1336 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1337 return tsc;
1338}
1339
69b0049a 1340static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1341{
1342#ifdef CONFIG_X86_64
1343 bool vcpus_matched;
b48aa97e
MT		 1344 struct kvm_arch *ka = &vcpu->kvm->arch;
1345 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1346
1347 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1348 atomic_read(&vcpu->kvm->online_vcpus));
1349
7f187922
MT		 1350 /*
1351 * Once the masterclock is enabled, always perform request in
1352 * order to update it.
1353 *
1354 * In order to enable masterclock, the host clocksource must be TSC
1355 * and the vcpus need to have matched TSCs. When that happens,
1356 * perform request to enable masterclock.
1357 */
1358 if (ka->use_master_clock ||
1359 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1360 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1361
1362 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1363 atomic_read(&vcpu->kvm->online_vcpus),
1364 ka->use_master_clock, gtod->clock.vclock_mode);
1365#endif
1366}
1367
ba904635
WA		 1368static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1369{
3e3f5026 1370 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1371 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1372}
1373
35181e86
HZ		 1374/*
1375 * Multiply tsc by a fixed point number represented by ratio.
1376 *
1377 * The most significant 64-N bits (mult) of ratio represent the
1378 * integral part of the fixed point number; the remaining N bits
1379 * (frac) represent the fractional part, ie. ratio represents a fixed
1380 * point number (mult + frac * 2^(-N)).
1381 *
1382 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1383 */
1384static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1385{
1386 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1387}
1388
1389u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1390{
1391 u64 _tsc = tsc;
1392 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1393
1394 if (ratio != kvm_default_tsc_scaling_ratio)
1395 _tsc = __scale_tsc(ratio, tsc);
1396
1397 return _tsc;
1398}
1399EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1400
07c1419a
HZ		 1401static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1402{
1403 u64 tsc;
1404
1405 tsc = kvm_scale_tsc(vcpu, rdtsc());
1406
1407 return target_tsc - tsc;
1408}
1409
4ba76538
HZ		 1410u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1411{
ea26e4ec 1412 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1413}
1414EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1415
a545ab6a
LC		 1416static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1417{
1418 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1419 vcpu->arch.tsc_offset = offset;
1420}
1421
8fe8ab46 1422void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1423{
1424 struct kvm *kvm = vcpu->kvm;
f38e098f 1425 u64 offset, ns, elapsed;
99e3e30a 1426 unsigned long flags;
02626b6a 1427 s64 usdiff;
b48aa97e 1428 bool matched;
0d3da0d2 1429 bool already_matched;
8fe8ab46 1430 u64 data = msr->data;
99e3e30a 1431
038f8c11 1432 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1433 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1434 ns = ktime_get_boot_ns();
f38e098f 1435 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1436
03ba32ca 1437 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1438 int faulted = 0;
1439
03ba32ca
MT		 1440 /* n.b - signed multiplication and division required */
1441 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1442#ifdef CONFIG_X86_64
03ba32ca 1443 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1444#else
03ba32ca 1445 /* do_div() only does unsigned */
8915aa27
MT		 1446 asm("1: idivl %[divisor]\n"
1447 "2: xor %%edx, %%edx\n"
1448 " movl $0, %[faulted]\n"
1449 "3:\n"
1450 ".section .fixup,\"ax\"\n"
1451 "4: movl $1, %[faulted]\n"
1452 " jmp 3b\n"
1453 ".previous\n"
1454
1455 _ASM_EXTABLE(1b, 4b)
1456
1457 : "=A"(usdiff), [faulted] "=r" (faulted)
1458 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1459
5d3cb0f6 1460#endif
03ba32ca
MT		 1461 do_div(elapsed, 1000);
1462 usdiff -= elapsed;
1463 if (usdiff < 0)
1464 usdiff = -usdiff;
8915aa27
MT		 1465
1466 /* idivl overflow => difference is larger than USEC_PER_SEC */
1467 if (faulted)
1468 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1469 } else
1470 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1471
1472 /*
5d3cb0f6
ZA		 1473 * Special case: TSC write with a small delta (1 second) of virtual
1474 * cycle time against real time is interpreted as an attempt to
1475 * synchronize the CPU.
1476 *
1477 * For a reliable TSC, we can match TSC offsets, and for an unstable
1478 * TSC, we add elapsed time in this computation. We could let the
1479 * compensation code attempt to catch up if we fall behind, but
1480 * it's better to try to match offsets from the beginning.
1481 */
02626b6a 1482 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1483 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1484 if (!check_tsc_unstable()) {
e26101b1 1485 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1486 pr_debug("kvm: matched tsc offset for %llu\n", data);
1487 } else {
857e4099 1488 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1489 data += delta;
07c1419a 1490 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1491 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1492 }
b48aa97e 1493 matched = true;
0d3da0d2 1494 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1495 } else {
1496 /*
1497 * We split periods of matched TSC writes into generations.
1498 * For each generation, we track the original measured
1499 * nanosecond time, offset, and write, so if TSCs are in
1500 * sync, we can match exact offset, and if not, we can match
4a969980 1501 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1502 *
1503 * These values are tracked in kvm->arch.cur_xxx variables.
1504 */
1505 kvm->arch.cur_tsc_generation++;
1506 kvm->arch.cur_tsc_nsec = ns;
1507 kvm->arch.cur_tsc_write = data;
1508 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1509 matched = false;
0d3da0d2 1510 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1511 kvm->arch.cur_tsc_generation, data);
f38e098f 1512 }
e26101b1
ZA		 1513
1514 /*
1515 * We also track th most recent recorded KHZ, write and time to
1516 * allow the matching interval to be extended at each write.
1517 */
f38e098f
ZA		 1518 kvm->arch.last_tsc_nsec = ns;
1519 kvm->arch.last_tsc_write = data;
5d3cb0f6 1520 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1521
b183aa58 1522 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1523
1524 /* Keep track of which generation this VCPU has synchronized to */
1525 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1526 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1527 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1528
ba904635
WA		 1529 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1530 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1531 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1532 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1533
1534 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1535 if (!matched) {
b48aa97e 1536 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1537 } else if (!already_matched) {
1538 kvm->arch.nr_vcpus_matched_tsc++;
1539 }
b48aa97e
MT		 1540
1541 kvm_track_tsc_matching(vcpu);
1542 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1543}
e26101b1 1544
99e3e30a
ZA		 1545EXPORT_SYMBOL_GPL(kvm_write_tsc);
1546
58ea6767
HZ		 1547static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1548 s64 adjustment)
1549{
ea26e4ec 1550 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1551}
1552
1553static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1554{
1555 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1556 WARN_ON(adjustment < 0);
1557 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1558 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1559}
1560
d828199e
MT		 1561#ifdef CONFIG_X86_64
1562
1563static cycle_t read_tsc(void)
1564{
03b9730b
AL		 1565 cycle_t ret = (cycle_t)rdtsc_ordered();
1566 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1567
1568 if (likely(ret >= last))
1569 return ret;
1570
1571 /*
1572 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1573 * predictable (it's just a function of time and the likely is
d828199e
MT		 1574 * very likely) and there's a data dependence, so force GCC
1575 * to generate a branch instead. I don't barrier() because
1576 * we don't actually need a barrier, and if this function
1577 * ever gets inlined it will generate worse code.
1578 */
1579 asm volatile ("");
1580 return last;
1581}
1582
1583static inline u64 vgettsc(cycle_t *cycle_now)
1584{
1585 long v;
1586 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1587
1588 *cycle_now = read_tsc();
1589
1590 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1591 return v * gtod->clock.mult;
1592}
1593
cbcf2dd3 1594static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1595{
cbcf2dd3 1596 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1597 unsigned long seq;
d828199e 1598 int mode;
cbcf2dd3 1599 u64 ns;
d828199e 1600
d828199e
MT		 1601 do {
1602 seq = read_seqcount_begin(&gtod->seq);
1603 mode = gtod->clock.vclock_mode;
cbcf2dd3 1604 ns = gtod->nsec_base;
d828199e
MT		 1605 ns += vgettsc(cycle_now);
1606 ns >>= gtod->clock.shift;
cbcf2dd3 1607 ns += gtod->boot_ns;
d828199e 1608 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1609 *t = ns;
d828199e
MT		 1610
1611 return mode;
1612}
1613
1614/* returns true if host is using tsc clocksource */
1615static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1616{
d828199e
MT		 1617 /* checked again under seqlock below */
1618 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1619 return false;
1620
cbcf2dd3 1621 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1622}
1623#endif
1624
1625/*
1626 *
b48aa97e
MT		 1627 * Assuming a stable TSC across physical CPUS, and a stable TSC
1628 * across virtual CPUs, the following condition is possible.
1629 * Each numbered line represents an event visible to both
d828199e
MT		 1630 * CPUs at the next numbered event.
1631 *
1632 * "timespecX" represents host monotonic time. "tscX" represents
1633 * RDTSC value.
1634 *
1635 * VCPU0 on CPU0 | VCPU1 on CPU1
1636 *
1637 * 1. read timespec0,tsc0
1638 * 2. | timespec1 = timespec0 + N
1639 * | tsc1 = tsc0 + M
1640 * 3. transition to guest | transition to guest
1641 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1642 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1643 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1644 *
1645 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1646 *
1647 * - ret0 < ret1
1648 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1649 * ...
1650 * - 0 < N - M => M < N
1651 *
1652 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1653 * always the case (the difference between two distinct xtime instances
1654 * might be smaller then the difference between corresponding TSC reads,
1655 * when updating guest vcpus pvclock areas).
1656 *
1657 * To avoid that problem, do not allow visibility of distinct
1658 * system_timestamp/tsc_timestamp values simultaneously: use a master
1659 * copy of host monotonic time values. Update that master copy
1660 * in lockstep.
1661 *
b48aa97e 1662 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1663 *
1664 */
1665
1666static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1667{
1668#ifdef CONFIG_X86_64
1669 struct kvm_arch *ka = &kvm->arch;
1670 int vclock_mode;
b48aa97e
MT		 1671 bool host_tsc_clocksource, vcpus_matched;
1672
1673 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1674 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1675
1676 /*
1677 * If the host uses TSC clock, then passthrough TSC as stable
1678 * to the guest.
1679 */
b48aa97e 1680 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1681 &ka->master_kernel_ns,
1682 &ka->master_cycle_now);
1683
16a96021 1684 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1685 && !backwards_tsc_observed
1686 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1687
d828199e
MT		 1688 if (ka->use_master_clock)
1689 atomic_set(&kvm_guest_has_master_clock, 1);
1690
1691 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1692 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1693 vcpus_matched);
d828199e
MT		 1694#endif
1695}
1696
2860c4b1
PB		 1697void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1698{
1699 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1700}
1701
2e762ff7
MT		 1702static void kvm_gen_update_masterclock(struct kvm *kvm)
1703{
1704#ifdef CONFIG_X86_64
1705 int i;
1706 struct kvm_vcpu *vcpu;
1707 struct kvm_arch *ka = &kvm->arch;
1708
1709 spin_lock(&ka->pvclock_gtod_sync_lock);
1710 kvm_make_mclock_inprogress_request(kvm);
1711 /* no guest entries from this point */
1712 pvclock_update_vm_gtod_copy(kvm);
1713
1714 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1715 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1716
1717 /* guest entries allowed */
1718 kvm_for_each_vcpu(i, vcpu, kvm)
1719 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1720
1721 spin_unlock(&ka->pvclock_gtod_sync_lock);
1722#endif
1723}
1724
108b249c
PB		 1725static u64 __get_kvmclock_ns(struct kvm *kvm)
1726{
108b249c 1727 struct kvm_arch *ka = &kvm->arch;
8b953440 1728 struct pvclock_vcpu_time_info hv_clock;
108b249c 1729
8b953440
PB		 1730 spin_lock(&ka->pvclock_gtod_sync_lock);
1731 if (!ka->use_master_clock) {
1732 spin_unlock(&ka->pvclock_gtod_sync_lock);
1733 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1734 }
1735
8b953440
PB		 1736 hv_clock.tsc_timestamp = ka->master_cycle_now;
1737 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1738 spin_unlock(&ka->pvclock_gtod_sync_lock);
1739
1740 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1741 &hv_clock.tsc_shift,
1742 &hv_clock.tsc_to_system_mul);
1743 return __pvclock_read_cycles(&hv_clock, rdtsc());
108b249c
PB		 1744}
1745
1746u64 get_kvmclock_ns(struct kvm *kvm)
1747{
1748 unsigned long flags;
1749 s64 ns;
1750
1751 local_irq_save(flags);
1752 ns = __get_kvmclock_ns(kvm);
1753 local_irq_restore(flags);
1754
1755 return ns;
1756}
1757
0d6dd2ff
PB		 1758static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1759{
1760 struct kvm_vcpu_arch *vcpu = &v->arch;
1761 struct pvclock_vcpu_time_info guest_hv_clock;
1762
1763 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1764 &guest_hv_clock, sizeof(guest_hv_clock))))
1765 return;
1766
1767 /* This VCPU is paused, but it's legal for a guest to read another
1768 * VCPU's kvmclock, so we really have to follow the specification where
1769 * it says that version is odd if data is being modified, and even after
1770 * it is consistent.
1771 *
1772 * Version field updates must be kept separate. This is because
1773 * kvm_write_guest_cached might use a "rep movs" instruction, and
1774 * writes within a string instruction are weakly ordered. So there
1775 * are three writes overall.
1776 *
1777 * As a small optimization, only write the version field in the first
1778 * and third write. The vcpu->pv_time cache is still valid, because the
1779 * version field is the first in the struct.
1780 */
1781 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1782
1783 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1784 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1785 &vcpu->hv_clock,
1786 sizeof(vcpu->hv_clock.version));
1787
1788 smp_wmb();
1789
1790 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1791 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1792
1793 if (vcpu->pvclock_set_guest_stopped_request) {
1794 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1795 vcpu->pvclock_set_guest_stopped_request = false;
1796 }
1797
1798 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1799
1800 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1801 &vcpu->hv_clock,
1802 sizeof(vcpu->hv_clock));
1803
1804 smp_wmb();
1805
1806 vcpu->hv_clock.version++;
1807 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1808 &vcpu->hv_clock,
1809 sizeof(vcpu->hv_clock.version));
1810}
1811
34c238a1 1812static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1813{
78db6a50 1814 unsigned long flags, tgt_tsc_khz;
18068523 1815 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1816 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1817 s64 kernel_ns;
d828199e 1818 u64 tsc_timestamp, host_tsc;
51d59c6b 1819 u8 pvclock_flags;
d828199e
MT		 1820 bool use_master_clock;
1821
1822 kernel_ns = 0;
1823 host_tsc = 0;
18068523 1824
d828199e
MT		 1825 /*
1826 * If the host uses TSC clock, then passthrough TSC as stable
1827 * to the guest.
1828 */
1829 spin_lock(&ka->pvclock_gtod_sync_lock);
1830 use_master_clock = ka->use_master_clock;
1831 if (use_master_clock) {
1832 host_tsc = ka->master_cycle_now;
1833 kernel_ns = ka->master_kernel_ns;
1834 }
1835 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1836
1837 /* Keep irq disabled to prevent changes to the clock */
1838 local_irq_save(flags);
78db6a50
PB		 1839 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1840 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1841 local_irq_restore(flags);
1842 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1843 return 1;
1844 }
d828199e 1845 if (!use_master_clock) {
4ea1636b 1846 host_tsc = rdtsc();
108b249c 1847 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1848 }
1849
4ba76538 1850 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1851
c285545f
ZA		 1852 /*
1853 * We may have to catch up the TSC to match elapsed wall clock
1854 * time for two reasons, even if kvmclock is used.
1855 * 1) CPU could have been running below the maximum TSC rate
1856 * 2) Broken TSC compensation resets the base at each VCPU
1857 * entry to avoid unknown leaps of TSC even when running
1858 * again on the same CPU. This may cause apparent elapsed
1859 * time to disappear, and the guest to stand still or run
1860 * very slowly.
1861 */
1862 if (vcpu->tsc_catchup) {
1863 u64 tsc = compute_guest_tsc(v, kernel_ns);
1864 if (tsc > tsc_timestamp) {
f1e2b260 1865 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1866 tsc_timestamp = tsc;
1867 }
50d0a0f9
GH		 1868 }
1869
18068523
GOC		 1870 local_irq_restore(flags);
1871
0d6dd2ff 1872 /* With all the info we got, fill in the values */
18068523 1873
78db6a50
PB		 1874 if (kvm_has_tsc_control)
1875 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1876
1877 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1878 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1879 &vcpu->hv_clock.tsc_shift,
1880 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1881 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1882 }
1883
1d5f066e 1884 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1885 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1886 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1887
d828199e 1888 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1889 pvclock_flags = 0;
d828199e
MT		 1890 if (use_master_clock)
1891 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1892
78c0337a
MT		 1893 vcpu->hv_clock.flags = pvclock_flags;
1894
095cf55d
PB		 1895 if (vcpu->pv_time_enabled)
1896 kvm_setup_pvclock_page(v);
1897 if (v == kvm_get_vcpu(v->kvm, 0))
1898 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1899 return 0;
c8076604
GH		 1900}
1901
0061d53d
MT		 1902/*
1903 * kvmclock updates which are isolated to a given vcpu, such as
1904 * vcpu->cpu migration, should not allow system_timestamp from
1905 * the rest of the vcpus to remain static. Otherwise ntp frequency
1906 * correction applies to one vcpu's system_timestamp but not
1907 * the others.
1908 *
1909 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1910 * We need to rate-limit these requests though, as they can
1911 * considerably slow guests that have a large number of vcpus.
1912 * The time for a remote vcpu to update its kvmclock is bound
1913 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1914 */
1915
7e44e449
AJ		 1916#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1917
1918static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1919{
1920 int i;
7e44e449
AJ		 1921 struct delayed_work *dwork = to_delayed_work(work);
1922 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1923 kvmclock_update_work);
1924 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1925 struct kvm_vcpu *vcpu;
1926
1927 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1928 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1929 kvm_vcpu_kick(vcpu);
1930 }
1931}
1932
7e44e449
AJ		 1933static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1934{
1935 struct kvm *kvm = v->kvm;
1936
105b21bb 1937 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1938 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1939 KVMCLOCK_UPDATE_DELAY);
1940}
1941
332967a3
AJ		 1942#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1943
1944static void kvmclock_sync_fn(struct work_struct *work)
1945{
1946 struct delayed_work *dwork = to_delayed_work(work);
1947 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1948 kvmclock_sync_work);
1949 struct kvm *kvm = container_of(ka, struct kvm, arch);
1950
630994b3
MT		 1951 if (!kvmclock_periodic_sync)
1952 return;
1953
332967a3
AJ		 1954 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1955 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1956 KVMCLOCK_SYNC_PERIOD);
1957}
1958
890ca9ae 1959static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1960{
890ca9ae
HY		 1961 u64 mcg_cap = vcpu->arch.mcg_cap;
1962 unsigned bank_num = mcg_cap & 0xff;
1963
15c4a640 1964 switch (msr) {
15c4a640 1965 case MSR_IA32_MCG_STATUS:
890ca9ae 1966 vcpu->arch.mcg_status = data;
15c4a640 1967 break;
c7ac679c 1968 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1969 if (!(mcg_cap & MCG_CTL_P))
1970 return 1;
1971 if (data != 0 && data != ~(u64)0)
1972 return -1;
1973 vcpu->arch.mcg_ctl = data;
1974 break;
1975 default:
1976 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1977 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1978 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1979 /* only 0 or all 1s can be written to IA32_MCi_CTL
1980 * some Linux kernels though clear bit 10 in bank 4 to
1981 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1982 * this to avoid an uncatched #GP in the guest
1983 */
890ca9ae 1984 if ((offset & 0x3) == 0 &&
114be429 1985 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1986 return -1;
1987 vcpu->arch.mce_banks[offset] = data;
1988 break;
1989 }
1990 return 1;
1991 }
1992 return 0;
1993}
1994
ffde22ac
ES		 1995static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1996{
1997 struct kvm *kvm = vcpu->kvm;
1998 int lm = is_long_mode(vcpu);
1999 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2000 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2001 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2002 : kvm->arch.xen_hvm_config.blob_size_32;
2003 u32 page_num = data & ~PAGE_MASK;
2004 u64 page_addr = data & PAGE_MASK;
2005 u8 *page;
2006 int r;
2007
2008 r = -E2BIG;
2009 if (page_num >= blob_size)
2010 goto out;
2011 r = -ENOMEM;
ff5c2c03
SL		 2012 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2013 if (IS_ERR(page)) {
2014 r = PTR_ERR(page);
ffde22ac 2015 goto out;
ff5c2c03 2016 }
54bf36aa 2017 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2018 goto out_free;
2019 r = 0;
2020out_free:
2021 kfree(page);
2022out:
2023 return r;
2024}
2025
344d9588
GN		 2026static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2027{
2028 gpa_t gpa = data & ~0x3f;
2029
4a969980 2030 /* Bits 2:5 are reserved, Should be zero */
6adba527 2031 if (data & 0x3c)
344d9588
GN		 2032 return 1;
2033
2034 vcpu->arch.apf.msr_val = data;
2035
2036 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2037 kvm_clear_async_pf_completion_queue(vcpu);
2038 kvm_async_pf_hash_reset(vcpu);
2039 return 0;
2040 }
2041
8f964525
AH		 2042 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2043 sizeof(u32)))
344d9588
GN		 2044 return 1;
2045
6adba527 2046 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2047 kvm_async_pf_wakeup_all(vcpu);
2048 return 0;
2049}
2050
12f9a48f
GC		 2051static void kvmclock_reset(struct kvm_vcpu *vcpu)
2052{
0b79459b 2053 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2054}
2055
c9aaa895
GC		 2056static void record_steal_time(struct kvm_vcpu *vcpu)
2057{
2058 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2059 return;
2060
2061 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2062 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2063 return;
2064
35f3fae1
WL		 2065 if (vcpu->arch.st.steal.version & 1)
2066 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2067
2068 vcpu->arch.st.steal.version += 1;
2069
2070 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2071 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2072
2073 smp_wmb();
2074
c54cdf14
LC		 2075 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2076 vcpu->arch.st.last_steal;
2077 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1
WL		 2078
2079 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2080 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2081
2082 smp_wmb();
2083
2084 vcpu->arch.st.steal.version += 1;
c9aaa895
GC		 2085
2086 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2087 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2088}
2089
8fe8ab46 2090int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2091{
5753785f 2092 bool pr = false;
8fe8ab46
WA		 2093 u32 msr = msr_info->index;
2094 u64 data = msr_info->data;
5753785f 2095
15c4a640 2096 switch (msr) {
2e32b719
BP		 2097 case MSR_AMD64_NB_CFG:
2098 case MSR_IA32_UCODE_REV:
2099 case MSR_IA32_UCODE_WRITE:
2100 case MSR_VM_HSAVE_PA:
2101 case MSR_AMD64_PATCH_LOADER:
2102 case MSR_AMD64_BU_CFG2:
2103 break;
2104
15c4a640 2105 case MSR_EFER:
b69e8cae 2106 return set_efer(vcpu, data);
8f1589d9
AP		 2107 case MSR_K7_HWCR:
2108 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2109 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2110 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2111 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2112 if (data != 0) {
a737f256
CD		 2113 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2114 data);
8f1589d9
AP		 2115 return 1;
2116 }
15c4a640 2117 break;
f7c6d140
AP		 2118 case MSR_FAM10H_MMIO_CONF_BASE:
2119 if (data != 0) {
a737f256
CD		 2120 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2121 "0x%llx\n", data);
f7c6d140
AP		 2122 return 1;
2123 }
15c4a640 2124 break;
b5e2fec0
AG		 2125 case MSR_IA32_DEBUGCTLMSR:
2126 if (!data) {
2127 /* We support the non-activated case already */
2128 break;
2129 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2130 /* Values other than LBR and BTF are vendor-specific,
2131 thus reserved and should throw a #GP */
2132 return 1;
2133 }
a737f256
CD		 2134 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2135 __func__, data);
b5e2fec0 2136 break;
9ba075a6 2137 case 0x200 ... 0x2ff:
ff53604b 2138 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2139 case MSR_IA32_APICBASE:
58cb628d 2140 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2141 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2142 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2143 case MSR_IA32_TSCDEADLINE:
2144 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2145 break;
ba904635
WA		 2146 case MSR_IA32_TSC_ADJUST:
2147 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2148 if (!msr_info->host_initiated) {
d913b904 2149 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2150 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2151 }
2152 vcpu->arch.ia32_tsc_adjust_msr = data;
2153 }
2154 break;
15c4a640 2155 case MSR_IA32_MISC_ENABLE:
ad312c7c 2156 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2157 break;
64d60670
PB		 2158 case MSR_IA32_SMBASE:
2159 if (!msr_info->host_initiated)
2160 return 1;
2161 vcpu->arch.smbase = data;
2162 break;
11c6bffa 2163 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2164 case MSR_KVM_WALL_CLOCK:
2165 vcpu->kvm->arch.wall_clock = data;
2166 kvm_write_wall_clock(vcpu->kvm, data);
2167 break;
11c6bffa 2168 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2169 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2170 u64 gpa_offset;
54750f2c
MT		 2171 struct kvm_arch *ka = &vcpu->kvm->arch;
2172
12f9a48f 2173 kvmclock_reset(vcpu);
18068523 2174
54750f2c
MT		 2175 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2176 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2177
2178 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2179 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2180 &vcpu->requests);
2181
2182 ka->boot_vcpu_runs_old_kvmclock = tmp;
2183 }
2184
18068523 2185 vcpu->arch.time = data;
0061d53d 2186 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2187
2188 /* we verify if the enable bit is set... */
2189 if (!(data & 1))
2190 break;
2191
0b79459b 2192 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2193
0b79459b 2194 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2195 &vcpu->arch.pv_time, data & ~1ULL,
2196 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2197 vcpu->arch.pv_time_enabled = false;
2198 else
2199 vcpu->arch.pv_time_enabled = true;
32cad84f 2200
18068523
GOC		 2201 break;
2202 }
344d9588
GN		 2203 case MSR_KVM_ASYNC_PF_EN:
2204 if (kvm_pv_enable_async_pf(vcpu, data))
2205 return 1;
2206 break;
c9aaa895
GC		 2207 case MSR_KVM_STEAL_TIME:
2208
2209 if (unlikely(!sched_info_on()))
2210 return 1;
2211
2212 if (data & KVM_STEAL_RESERVED_MASK)
2213 return 1;
2214
2215 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2216 data & KVM_STEAL_VALID_BITS,
2217 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2218 return 1;
2219
2220 vcpu->arch.st.msr_val = data;
2221
2222 if (!(data & KVM_MSR_ENABLED))
2223 break;
2224
c9aaa895
GC		 2225 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2226
2227 break;
ae7a2a3f
MT		 2228 case MSR_KVM_PV_EOI_EN:
2229 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2230 return 1;
2231 break;
c9aaa895 2232
890ca9ae
HY		 2233 case MSR_IA32_MCG_CTL:
2234 case MSR_IA32_MCG_STATUS:
81760dcc 2235 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2236 return set_msr_mce(vcpu, msr, data);
71db6023 2237
6912ac32
WH		 2238 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2239 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2240 pr = true; /* fall through */
2241 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2242 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2243 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2244 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2245
2246 if (pr || data != 0)
a737f256
CD		 2247 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2248 "0x%x data 0x%llx\n", msr, data);
5753785f 2249 break;
84e0cefa
JS		 2250 case MSR_K7_CLK_CTL:
2251 /*
2252 * Ignore all writes to this no longer documented MSR.
2253 * Writes are only relevant for old K7 processors,
2254 * all pre-dating SVM, but a recommended workaround from
4a969980 2255 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2256 * affected processor models on the command line, hence
2257 * the need to ignore the workaround.
2258 */
2259 break;
55cd8e5a 2260 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2261 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2262 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2263 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2264 return kvm_hv_set_msr_common(vcpu, msr, data,
2265 msr_info->host_initiated);
91c9c3ed 2266 case MSR_IA32_BBL_CR_CTL3:
2267 /* Drop writes to this legacy MSR -- see rdmsr
2268 * counterpart for further detail.
2269 */
796f4687 2270 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2271 break;
2b036c6b
BO		 2272 case MSR_AMD64_OSVW_ID_LENGTH:
2273 if (!guest_cpuid_has_osvw(vcpu))
2274 return 1;
2275 vcpu->arch.osvw.length = data;
2276 break;
2277 case MSR_AMD64_OSVW_STATUS:
2278 if (!guest_cpuid_has_osvw(vcpu))
2279 return 1;
2280 vcpu->arch.osvw.status = data;
2281 break;
15c4a640 2282 default:
ffde22ac
ES		 2283 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2284 return xen_hvm_config(vcpu, data);
c6702c9d 2285 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2286 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2287 if (!ignore_msrs) {
796f4687 2288 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2289 msr, data);
ed85c068
AP		 2290 return 1;
2291 } else {
796f4687 2292 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2293 msr, data);
ed85c068
AP		 2294 break;
2295 }
15c4a640
CO		 2296 }
2297 return 0;
2298}
2299EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2300
2301
2302/*
2303 * Reads an msr value (of 'msr_index') into 'pdata'.
2304 * Returns 0 on success, non-0 otherwise.
2305 * Assumes vcpu_load() was already called.
2306 */
609e36d3 2307int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2308{
609e36d3 2309 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2310}
ff651cb6 2311EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2312
890ca9ae 2313static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2314{
2315 u64 data;
890ca9ae
HY		 2316 u64 mcg_cap = vcpu->arch.mcg_cap;
2317 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2318
2319 switch (msr) {
15c4a640
CO		 2320 case MSR_IA32_P5_MC_ADDR:
2321 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2322 data = 0;
2323 break;
15c4a640 2324 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2325 data = vcpu->arch.mcg_cap;
2326 break;
c7ac679c 2327 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2328 if (!(mcg_cap & MCG_CTL_P))
2329 return 1;
2330 data = vcpu->arch.mcg_ctl;
2331 break;
2332 case MSR_IA32_MCG_STATUS:
2333 data = vcpu->arch.mcg_status;
2334 break;
2335 default:
2336 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2337 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2338 u32 offset = msr - MSR_IA32_MC0_CTL;
2339 data = vcpu->arch.mce_banks[offset];
2340 break;
2341 }
2342 return 1;
2343 }
2344 *pdata = data;
2345 return 0;
2346}
2347
609e36d3 2348int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2349{
609e36d3 2350 switch (msr_info->index) {
890ca9ae 2351 case MSR_IA32_PLATFORM_ID:
15c4a640 2352 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2353 case MSR_IA32_DEBUGCTLMSR:
2354 case MSR_IA32_LASTBRANCHFROMIP:
2355 case MSR_IA32_LASTBRANCHTOIP:
2356 case MSR_IA32_LASTINTFROMIP:
2357 case MSR_IA32_LASTINTTOIP:
60af2ecd 2358 case MSR_K8_SYSCFG:
3afb1121
PB		 2359 case MSR_K8_TSEG_ADDR:
2360 case MSR_K8_TSEG_MASK:
60af2ecd 2361 case MSR_K7_HWCR:
61a6bd67 2362 case MSR_VM_HSAVE_PA:
1fdbd48c 2363 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2364 case MSR_AMD64_NB_CFG:
f7c6d140 2365 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2366 case MSR_AMD64_BU_CFG2:
0c2df2a1 2367 case MSR_IA32_PERF_CTL:
609e36d3 2368 msr_info->data = 0;
15c4a640 2369 break;
6912ac32
WH		 2370 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2371 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2372 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2373 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2374 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2375 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2376 msr_info->data = 0;
5753785f 2377 break;
742bc670 2378 case MSR_IA32_UCODE_REV:
609e36d3 2379 msr_info->data = 0x100000000ULL;
742bc670 2380 break;
9ba075a6 2381 case MSR_MTRRcap:
9ba075a6 2382 case 0x200 ... 0x2ff:
ff53604b 2383 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2384 case 0xcd: /* fsb frequency */
609e36d3 2385 msr_info->data = 3;
15c4a640 2386 break;
7b914098
JS		 2387 /*
2388 * MSR_EBC_FREQUENCY_ID
2389 * Conservative value valid for even the basic CPU models.
2390 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2391 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2392 * and 266MHz for model 3, or 4. Set Core Clock
2393 * Frequency to System Bus Frequency Ratio to 1 (bits
2394 * 31:24) even though these are only valid for CPU
2395 * models > 2, however guests may end up dividing or
2396 * multiplying by zero otherwise.
2397 */
2398 case MSR_EBC_FREQUENCY_ID:
609e36d3 2399 msr_info->data = 1 << 24;
7b914098 2400 break;
15c4a640 2401 case MSR_IA32_APICBASE:
609e36d3 2402 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2403 break;
0105d1a5 2404 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2405 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2406 break;
a3e06bbe 2407 case MSR_IA32_TSCDEADLINE:
609e36d3 2408 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2409 break;
ba904635 2410 case MSR_IA32_TSC_ADJUST:
609e36d3 2411 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2412 break;
15c4a640 2413 case MSR_IA32_MISC_ENABLE:
609e36d3 2414 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2415 break;
64d60670
PB		 2416 case MSR_IA32_SMBASE:
2417 if (!msr_info->host_initiated)
2418 return 1;
2419 msr_info->data = vcpu->arch.smbase;
15c4a640 2420 break;
847f0ad8
AG		 2421 case MSR_IA32_PERF_STATUS:
2422 /* TSC increment by tick */
609e36d3 2423 msr_info->data = 1000ULL;
847f0ad8 2424 /* CPU multiplier */
b0996ae4 2425 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2426 break;
15c4a640 2427 case MSR_EFER:
609e36d3 2428 msr_info->data = vcpu->arch.efer;
15c4a640 2429 break;
18068523 2430 case MSR_KVM_WALL_CLOCK:
11c6bffa 2431 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2432 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2433 break;
2434 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2435 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2436 msr_info->data = vcpu->arch.time;
18068523 2437 break;
344d9588 2438 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2439 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2440 break;
c9aaa895 2441 case MSR_KVM_STEAL_TIME:
609e36d3 2442 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2443 break;
1d92128f 2444 case MSR_KVM_PV_EOI_EN:
609e36d3 2445 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2446 break;
890ca9ae
HY		 2447 case MSR_IA32_P5_MC_ADDR:
2448 case MSR_IA32_P5_MC_TYPE:
2449 case MSR_IA32_MCG_CAP:
2450 case MSR_IA32_MCG_CTL:
2451 case MSR_IA32_MCG_STATUS:
81760dcc 2452 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2453 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2454 case MSR_K7_CLK_CTL:
2455 /*
2456 * Provide expected ramp-up count for K7. All other
2457 * are set to zero, indicating minimum divisors for
2458 * every field.
2459 *
2460 * This prevents guest kernels on AMD host with CPU
2461 * type 6, model 8 and higher from exploding due to
2462 * the rdmsr failing.
2463 */
609e36d3 2464 msr_info->data = 0x20000000;
84e0cefa 2465 break;
55cd8e5a 2466 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2467 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2468 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2469 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2470 return kvm_hv_get_msr_common(vcpu,
2471 msr_info->index, &msr_info->data);
55cd8e5a 2472 break;
91c9c3ed 2473 case MSR_IA32_BBL_CR_CTL3:
2474 /* This legacy MSR exists but isn't fully documented in current
2475 * silicon. It is however accessed by winxp in very narrow
2476 * scenarios where it sets bit #19, itself documented as
2477 * a "reserved" bit. Best effort attempt to source coherent
2478 * read data here should the balance of the register be
2479 * interpreted by the guest:
2480 *
2481 * L2 cache control register 3: 64GB range, 256KB size,
2482 * enabled, latency 0x1, configured
2483 */
609e36d3 2484 msr_info->data = 0xbe702111;
91c9c3ed 2485 break;
2b036c6b
BO		 2486 case MSR_AMD64_OSVW_ID_LENGTH:
2487 if (!guest_cpuid_has_osvw(vcpu))
2488 return 1;
609e36d3 2489 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2490 break;
2491 case MSR_AMD64_OSVW_STATUS:
2492 if (!guest_cpuid_has_osvw(vcpu))
2493 return 1;
609e36d3 2494 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2495 break;
15c4a640 2496 default:
c6702c9d 2497 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2498 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2499 if (!ignore_msrs) {
609e36d3 2500 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2501 return 1;
2502 } else {
609e36d3
PB		 2503 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2504 msr_info->data = 0;
ed85c068
AP		 2505 }
2506 break;
15c4a640 2507 }
15c4a640
CO		 2508 return 0;
2509}
2510EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2511
313a3dc7
CO		 2512/*
2513 * Read or write a bunch of msrs. All parameters are kernel addresses.
2514 *
2515 * @return number of msrs set successfully.
2516 */
2517static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2518 struct kvm_msr_entry *entries,
2519 int (*do_msr)(struct kvm_vcpu *vcpu,
2520 unsigned index, u64 *data))
2521{
f656ce01 2522 int i, idx;
313a3dc7 2523
f656ce01 2524 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2525 for (i = 0; i < msrs->nmsrs; ++i)
2526 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2527 break;
f656ce01 2528 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2529
313a3dc7
CO		 2530 return i;
2531}
2532
2533/*
2534 * Read or write a bunch of msrs. Parameters are user addresses.
2535 *
2536 * @return number of msrs set successfully.
2537 */
2538static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2539 int (*do_msr)(struct kvm_vcpu *vcpu,
2540 unsigned index, u64 *data),
2541 int writeback)
2542{
2543 struct kvm_msrs msrs;
2544 struct kvm_msr_entry *entries;
2545 int r, n;
2546 unsigned size;
2547
2548 r = -EFAULT;
2549 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2550 goto out;
2551
2552 r = -E2BIG;
2553 if (msrs.nmsrs >= MAX_IO_MSRS)
2554 goto out;
2555
313a3dc7 2556 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2557 entries = memdup_user(user_msrs->entries, size);
2558 if (IS_ERR(entries)) {
2559 r = PTR_ERR(entries);
313a3dc7 2560 goto out;
ff5c2c03 2561 }
313a3dc7
CO		 2562
2563 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2564 if (r < 0)
2565 goto out_free;
2566
2567 r = -EFAULT;
2568 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2569 goto out_free;
2570
2571 r = n;
2572
2573out_free:
7a73c028 2574 kfree(entries);
313a3dc7
CO		 2575out:
2576 return r;
2577}
2578
784aa3d7 2579int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2580{
2581 int r;
2582
2583 switch (ext) {
2584 case KVM_CAP_IRQCHIP:
2585 case KVM_CAP_HLT:
2586 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2587 case KVM_CAP_SET_TSS_ADDR:
07716717 2588 case KVM_CAP_EXT_CPUID:
9c15bb1d 2589 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2590 case KVM_CAP_CLOCKSOURCE:
7837699f 2591 case KVM_CAP_PIT:
a28e4f5a 2592 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2593 case KVM_CAP_MP_STATE:
ed848624 2594 case KVM_CAP_SYNC_MMU:
a355c85c 2595 case KVM_CAP_USER_NMI:
52d939a0 2596 case KVM_CAP_REINJECT_CONTROL:
4925663a 2597 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2598 case KVM_CAP_IOEVENTFD:
f848a5a8 2599 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2600 case KVM_CAP_PIT2:
e9f42757 2601 case KVM_CAP_PIT_STATE2:
b927a3ce 2602 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2603 case KVM_CAP_XEN_HVM:
afbcf7ab 2604 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2605 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2606 case KVM_CAP_HYPERV:
10388a07 2607 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2608 case KVM_CAP_HYPERV_SPIN:
5c919412 2609 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2610 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2611 case KVM_CAP_DEBUGREGS:
d2be1651 2612 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2613 case KVM_CAP_XSAVE:
344d9588 2614 case KVM_CAP_ASYNC_PF:
92a1f12d 2615 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2616 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2617 case KVM_CAP_READONLY_MEM:
5f66b620 2618 case KVM_CAP_HYPERV_TIME:
100943c5 2619 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2620 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2621 case KVM_CAP_ENABLE_CAP_VM:
2622 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2623 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2624 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2625#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2626 case KVM_CAP_ASSIGN_DEV_IRQ:
2627 case KVM_CAP_PCI_2_3:
2628#endif
018d00d2
ZX		 2629 r = 1;
2630 break;
6d396b55
PB		 2631 case KVM_CAP_X86_SMM:
2632 /* SMBASE is usually relocated above 1M on modern chipsets,
2633 * and SMM handlers might indeed rely on 4G segment limits,
2634 * so do not report SMM to be available if real mode is
2635 * emulated via vm86 mode. Still, do not go to great lengths
2636 * to avoid userspace's usage of the feature, because it is a
2637 * fringe case that is not enabled except via specific settings
2638 * of the module parameters.
2639 */
2640 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2641 break;
542472b5
LV		 2642 case KVM_CAP_COALESCED_MMIO:
2643 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2644 break;
774ead3a
AK		 2645 case KVM_CAP_VAPIC:
2646 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2647 break;
f725230a 2648 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2649 r = KVM_SOFT_MAX_VCPUS;
2650 break;
2651 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2652 r = KVM_MAX_VCPUS;
2653 break;
a988b910 2654 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2655 r = KVM_USER_MEM_SLOTS;
a988b910 2656 break;
a68a6a72
MT		 2657 case KVM_CAP_PV_MMU: /* obsolete */
2658 r = 0;
2f333bcb 2659 break;
4cee4b72 2660#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2661 case KVM_CAP_IOMMU:
a1b60c1c 2662 r = iommu_present(&pci_bus_type);
62c476c7 2663 break;
4cee4b72 2664#endif
890ca9ae
HY		 2665 case KVM_CAP_MCE:
2666 r = KVM_MAX_MCE_BANKS;
2667 break;
2d5b5a66 2668 case KVM_CAP_XCRS:
d366bf7e 2669 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2670 break;
92a1f12d
JR		 2671 case KVM_CAP_TSC_CONTROL:
2672 r = kvm_has_tsc_control;
2673 break;
37131313
RK		 2674 case KVM_CAP_X2APIC_API:
2675 r = KVM_X2APIC_API_VALID_FLAGS;
2676 break;
018d00d2
ZX		 2677 default:
2678 r = 0;
2679 break;
2680 }
2681 return r;
2682
2683}
2684
043405e1
CO		 2685long kvm_arch_dev_ioctl(struct file *filp,
2686 unsigned int ioctl, unsigned long arg)
2687{
2688 void __user *argp = (void __user *)arg;
2689 long r;
2690
2691 switch (ioctl) {
2692 case KVM_GET_MSR_INDEX_LIST: {
2693 struct kvm_msr_list __user *user_msr_list = argp;
2694 struct kvm_msr_list msr_list;
2695 unsigned n;
2696
2697 r = -EFAULT;
2698 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2699 goto out;
2700 n = msr_list.nmsrs;
62ef68bb 2701 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2702 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2703 goto out;
2704 r = -E2BIG;
e125e7b6 2705 if (n < msr_list.nmsrs)
043405e1
CO		 2706 goto out;
2707 r = -EFAULT;
2708 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2709 num_msrs_to_save * sizeof(u32)))
2710 goto out;
e125e7b6 2711 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2712 &emulated_msrs,
62ef68bb 2713 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2714 goto out;
2715 r = 0;
2716 break;
2717 }
9c15bb1d
BP		 2718 case KVM_GET_SUPPORTED_CPUID:
2719 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2720 struct kvm_cpuid2 __user *cpuid_arg = argp;
2721 struct kvm_cpuid2 cpuid;
2722
2723 r = -EFAULT;
2724 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2725 goto out;
9c15bb1d
BP		 2726
2727 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2728 ioctl);
674eea0f
AK		 2729 if (r)
2730 goto out;
2731
2732 r = -EFAULT;
2733 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2734 goto out;
2735 r = 0;
2736 break;
2737 }
890ca9ae 2738 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2739 r = -EFAULT;
c45dcc71
AR		 2740 if (copy_to_user(argp, &kvm_mce_cap_supported,
2741 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2742 goto out;
2743 r = 0;
2744 break;
2745 }
043405e1
CO		 2746 default:
2747 r = -EINVAL;
2748 }
2749out:
2750 return r;
2751}
2752
f5f48ee1
SY		 2753static void wbinvd_ipi(void *garbage)
2754{
2755 wbinvd();
2756}
2757
2758static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2759{
e0f0bbc5 2760 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2761}
2762
2860c4b1
PB		 2763static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2764{
2765 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2766}
2767
313a3dc7
CO		 2768void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2769{
f5f48ee1
SY		 2770 /* Address WBINVD may be executed by guest */
2771 if (need_emulate_wbinvd(vcpu)) {
2772 if (kvm_x86_ops->has_wbinvd_exit())
2773 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2774 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2775 smp_call_function_single(vcpu->cpu,
2776 wbinvd_ipi, NULL, 1);
2777 }
2778
313a3dc7 2779 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2780
0dd6a6ed
ZA		 2781 /* Apply any externally detected TSC adjustments (due to suspend) */
2782 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2783 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2784 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2785 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2786 }
8f6055cb 2787
48434c20 2788 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2789 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2790 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2791 if (tsc_delta < 0)
2792 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2793
c285545f 2794 if (check_tsc_unstable()) {
07c1419a 2795 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2796 vcpu->arch.last_guest_tsc);
a545ab6a 2797 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2798 vcpu->arch.tsc_catchup = 1;
c285545f 2799 }
e12c8f36
WL		 2800 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2801 kvm_x86_ops->set_hv_timer(vcpu,
2802 kvm_get_lapic_tscdeadline_msr(vcpu)))
2803 kvm_lapic_switch_to_sw_timer(vcpu);
d98d07ca
MT		 2804 /*
2805 * On a host with synchronized TSC, there is no need to update
2806 * kvmclock on vcpu->cpu migration
2807 */
2808 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2809 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2810 if (vcpu->cpu != cpu)
2811 kvm_migrate_timers(vcpu);
e48672fa 2812 vcpu->cpu = cpu;
6b7d7e76 2813 }
c9aaa895 2814
c9aaa895 2815 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2816}
2817
2818void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2819{
02daab21 2820 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2821 kvm_put_guest_fpu(vcpu);
4ea1636b 2822 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2823}
2824
313a3dc7
CO		 2825static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2826 struct kvm_lapic_state *s)
2827{
d62caabb
AS		 2828 if (vcpu->arch.apicv_active)
2829 kvm_x86_ops->sync_pir_to_irr(vcpu);
2830
a92e2543 2831 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2832}
2833
2834static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2835 struct kvm_lapic_state *s)
2836{
a92e2543
RK		 2837 int r;
2838
2839 r = kvm_apic_set_state(vcpu, s);
2840 if (r)
2841 return r;
cb142eb7 2842 update_cr8_intercept(vcpu);
313a3dc7
CO		 2843
2844 return 0;
2845}
2846
127a457a
MG		 2847static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2848{
2849 return (!lapic_in_kernel(vcpu) ||
2850 kvm_apic_accept_pic_intr(vcpu));
2851}
2852
782d422b
MG		 2853/*
2854 * if userspace requested an interrupt window, check that the
2855 * interrupt window is open.
2856 *
2857 * No need to exit to userspace if we already have an interrupt queued.
2858 */
2859static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2860{
2861 return kvm_arch_interrupt_allowed(vcpu) &&
2862 !kvm_cpu_has_interrupt(vcpu) &&
2863 !kvm_event_needs_reinjection(vcpu) &&
2864 kvm_cpu_accept_dm_intr(vcpu);
2865}
2866
f77bc6a4
ZX		 2867static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2868 struct kvm_interrupt *irq)
2869{
02cdb50f 2870 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2871 return -EINVAL;
1c1a9ce9
SR		 2872
2873 if (!irqchip_in_kernel(vcpu->kvm)) {
2874 kvm_queue_interrupt(vcpu, irq->irq, false);
2875 kvm_make_request(KVM_REQ_EVENT, vcpu);
2876 return 0;
2877 }
2878
2879 /*
2880 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2881 * fail for in-kernel 8259.
2882 */
2883 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2884 return -ENXIO;
f77bc6a4 2885
1c1a9ce9
SR		 2886 if (vcpu->arch.pending_external_vector != -1)
2887 return -EEXIST;
f77bc6a4 2888
1c1a9ce9 2889 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2890 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2891 return 0;
2892}
2893
c4abb7c9
JK		 2894static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2895{
c4abb7c9 2896 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2897
2898 return 0;
2899}
2900
f077825a
PB		 2901static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2902{
64d60670
PB		 2903 kvm_make_request(KVM_REQ_SMI, vcpu);
2904
f077825a
PB		 2905 return 0;
2906}
2907
b209749f
AK		 2908static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2909 struct kvm_tpr_access_ctl *tac)
2910{
2911 if (tac->flags)
2912 return -EINVAL;
2913 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2914 return 0;
2915}
2916
890ca9ae
HY		 2917static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2918 u64 mcg_cap)
2919{
2920 int r;
2921 unsigned bank_num = mcg_cap & 0xff, bank;
2922
2923 r = -EINVAL;
a9e38c3e 2924 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 2925 goto out;
c45dcc71 2926 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 2927 goto out;
2928 r = 0;
2929 vcpu->arch.mcg_cap = mcg_cap;
2930 /* Init IA32_MCG_CTL to all 1s */
2931 if (mcg_cap & MCG_CTL_P)
2932 vcpu->arch.mcg_ctl = ~(u64)0;
2933 /* Init IA32_MCi_CTL to all 1s */
2934 for (bank = 0; bank < bank_num; bank++)
2935 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 2936
2937 if (kvm_x86_ops->setup_mce)
2938 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 2939out:
2940 return r;
2941}
2942
2943static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2944 struct kvm_x86_mce *mce)
2945{
2946 u64 mcg_cap = vcpu->arch.mcg_cap;
2947 unsigned bank_num = mcg_cap & 0xff;
2948 u64 *banks = vcpu->arch.mce_banks;
2949
2950 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2951 return -EINVAL;
2952 /*
2953 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2954 * reporting is disabled
2955 */
2956 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2957 vcpu->arch.mcg_ctl != ~(u64)0)
2958 return 0;
2959 banks += 4 * mce->bank;
2960 /*
2961 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2962 * reporting is disabled for the bank
2963 */
2964 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2965 return 0;
2966 if (mce->status & MCI_STATUS_UC) {
2967 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2968 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2969 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2970 return 0;
2971 }
2972 if (banks[1] & MCI_STATUS_VAL)
2973 mce->status |= MCI_STATUS_OVER;
2974 banks[2] = mce->addr;
2975 banks[3] = mce->misc;
2976 vcpu->arch.mcg_status = mce->mcg_status;
2977 banks[1] = mce->status;
2978 kvm_queue_exception(vcpu, MC_VECTOR);
2979 } else if (!(banks[1] & MCI_STATUS_VAL)
2980 || !(banks[1] & MCI_STATUS_UC)) {
2981 if (banks[1] & MCI_STATUS_VAL)
2982 mce->status |= MCI_STATUS_OVER;
2983 banks[2] = mce->addr;
2984 banks[3] = mce->misc;
2985 banks[1] = mce->status;
2986 } else
2987 banks[1] |= MCI_STATUS_OVER;
2988 return 0;
2989}
2990
3cfc3092
JK		 2991static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2992 struct kvm_vcpu_events *events)
2993{
7460fb4a 2994 process_nmi(vcpu);
03b82a30
JK		 2995 events->exception.injected =
2996 vcpu->arch.exception.pending &&
2997 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2998 events->exception.nr = vcpu->arch.exception.nr;
2999 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3000 events->exception.pad = 0;
3cfc3092
JK		 3001 events->exception.error_code = vcpu->arch.exception.error_code;
3002
03b82a30
JK		 3003 events->interrupt.injected =
3004 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3005 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3006 events->interrupt.soft = 0;
37ccdcbe 3007 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3008
3009 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3010 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3011 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3012 events->nmi.pad = 0;
3cfc3092 3013
66450a21 3014 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3015
f077825a
PB		 3016 events->smi.smm = is_smm(vcpu);
3017 events->smi.pending = vcpu->arch.smi_pending;
3018 events->smi.smm_inside_nmi =
3019 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3020 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3021
dab4b911 3022 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3023 | KVM_VCPUEVENT_VALID_SHADOW
3024 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3025 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3026}
3027
3028static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3029 struct kvm_vcpu_events *events)
3030{
dab4b911 3031 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3032 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3033 | KVM_VCPUEVENT_VALID_SHADOW
3034 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3035 return -EINVAL;
3036
78e546c8
PB		 3037 if (events->exception.injected &&
3038 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
3039 return -EINVAL;
3040
7460fb4a 3041 process_nmi(vcpu);
3cfc3092
JK		 3042 vcpu->arch.exception.pending = events->exception.injected;
3043 vcpu->arch.exception.nr = events->exception.nr;
3044 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3045 vcpu->arch.exception.error_code = events->exception.error_code;
3046
3047 vcpu->arch.interrupt.pending = events->interrupt.injected;
3048 vcpu->arch.interrupt.nr = events->interrupt.nr;
3049 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3050 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3051 kvm_x86_ops->set_interrupt_shadow(vcpu,
3052 events->interrupt.shadow);
3cfc3092
JK		 3053
3054 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3055 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3056 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3057 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3058
66450a21 3059 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3060 lapic_in_kernel(vcpu))
66450a21 3061 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3062
f077825a
PB		 3063 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3064 if (events->smi.smm)
3065 vcpu->arch.hflags |= HF_SMM_MASK;
3066 else
3067 vcpu->arch.hflags &= ~HF_SMM_MASK;
3068 vcpu->arch.smi_pending = events->smi.pending;
3069 if (events->smi.smm_inside_nmi)
3070 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3071 else
3072 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3073 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3074 if (events->smi.latched_init)
3075 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3076 else
3077 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3078 }
3079 }
3080
3842d135
AK		 3081 kvm_make_request(KVM_REQ_EVENT, vcpu);
3082
3cfc3092
JK		 3083 return 0;
3084}
3085
a1efbe77
JK		 3086static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3087 struct kvm_debugregs *dbgregs)
3088{
73aaf249
JK		 3089 unsigned long val;
3090
a1efbe77 3091 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3092 kvm_get_dr(vcpu, 6, &val);
73aaf249 3093 dbgregs->dr6 = val;
a1efbe77
JK		 3094 dbgregs->dr7 = vcpu->arch.dr7;
3095 dbgregs->flags = 0;
97e69aa6 3096 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3097}
3098
3099static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3100 struct kvm_debugregs *dbgregs)
3101{
3102 if (dbgregs->flags)
3103 return -EINVAL;
3104
d14bdb55
PB		 3105 if (dbgregs->dr6 & ~0xffffffffull)
3106 return -EINVAL;
3107 if (dbgregs->dr7 & ~0xffffffffull)
3108 return -EINVAL;
3109
a1efbe77 3110 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3111 kvm_update_dr0123(vcpu);
a1efbe77 3112 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3113 kvm_update_dr6(vcpu);
a1efbe77 3114 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3115 kvm_update_dr7(vcpu);
a1efbe77 3116
a1efbe77
JK		 3117 return 0;
3118}
3119
df1daba7
PB		 3120#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3121
3122static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3123{
c47ada30 3124 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3125 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3126 u64 valid;
3127
3128 /*
3129 * Copy legacy XSAVE area, to avoid complications with CPUID
3130 * leaves 0 and 1 in the loop below.
3131 */
3132 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3133
3134 /* Set XSTATE_BV */
3135 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3136
3137 /*
3138 * Copy each region from the possibly compacted offset to the
3139 * non-compacted offset.
3140 */
d91cab78 3141 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3142 while (valid) {
3143 u64 feature = valid & -valid;
3144 int index = fls64(feature) - 1;
3145 void *src = get_xsave_addr(xsave, feature);
3146
3147 if (src) {
3148 u32 size, offset, ecx, edx;
3149 cpuid_count(XSTATE_CPUID, index,
3150 &size, &offset, &ecx, &edx);
3151 memcpy(dest + offset, src, size);
3152 }
3153
3154 valid -= feature;
3155 }
3156}
3157
3158static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3159{
c47ada30 3160 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3161 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3162 u64 valid;
3163
3164 /*
3165 * Copy legacy XSAVE area, to avoid complications with CPUID
3166 * leaves 0 and 1 in the loop below.
3167 */
3168 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3169
3170 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3171 xsave->header.xfeatures = xstate_bv;
782511b0 3172 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3173 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3174
3175 /*
3176 * Copy each region from the non-compacted offset to the
3177 * possibly compacted offset.
3178 */
d91cab78 3179 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3180 while (valid) {
3181 u64 feature = valid & -valid;
3182 int index = fls64(feature) - 1;
3183 void *dest = get_xsave_addr(xsave, feature);
3184
3185 if (dest) {
3186 u32 size, offset, ecx, edx;
3187 cpuid_count(XSTATE_CPUID, index,
3188 &size, &offset, &ecx, &edx);
3189 memcpy(dest, src + offset, size);
ee4100da 3190 }
df1daba7
PB		 3191
3192 valid -= feature;
3193 }
3194}
3195
2d5b5a66
SY		 3196static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3197 struct kvm_xsave *guest_xsave)
3198{
d366bf7e 3199 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3200 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3201 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3202 } else {
2d5b5a66 3203 memcpy(guest_xsave->region,
7366ed77 3204 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3205 sizeof(struct fxregs_state));
2d5b5a66 3206 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3207 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3208 }
3209}
3210
3211static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3212 struct kvm_xsave *guest_xsave)
3213{
3214 u64 xstate_bv =
3215 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3216
d366bf7e 3217 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3218 /*
3219 * Here we allow setting states that are not present in
3220 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3221 * with old userspace.
3222 */
4ff41732 3223 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3224 return -EINVAL;
df1daba7 3225 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3226 } else {
d91cab78 3227 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3228 return -EINVAL;
7366ed77 3229 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3230 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3231 }
3232 return 0;
3233}
3234
3235static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3236 struct kvm_xcrs *guest_xcrs)
3237{
d366bf7e 3238 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3239 guest_xcrs->nr_xcrs = 0;
3240 return;
3241 }
3242
3243 guest_xcrs->nr_xcrs = 1;
3244 guest_xcrs->flags = 0;
3245 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3246 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3247}
3248
3249static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3250 struct kvm_xcrs *guest_xcrs)
3251{
3252 int i, r = 0;
3253
d366bf7e 3254 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3255 return -EINVAL;
3256
3257 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3258 return -EINVAL;
3259
3260 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3261 /* Only support XCR0 currently */
c67a04cb 3262 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3263 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3264 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3265 break;
3266 }
3267 if (r)
3268 r = -EINVAL;
3269 return r;
3270}
3271
1c0b28c2
EM		 3272/*
3273 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3274 * stopped by the hypervisor. This function will be called from the host only.
3275 * EINVAL is returned when the host attempts to set the flag for a guest that
3276 * does not support pv clocks.
3277 */
3278static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3279{
0b79459b 3280 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3281 return -EINVAL;
51d59c6b 3282 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3283 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3284 return 0;
3285}
3286
5c919412
AS		 3287static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3288 struct kvm_enable_cap *cap)
3289{
3290 if (cap->flags)
3291 return -EINVAL;
3292
3293 switch (cap->cap) {
3294 case KVM_CAP_HYPERV_SYNIC:
3295 return kvm_hv_activate_synic(vcpu);
3296 default:
3297 return -EINVAL;
3298 }
3299}
3300
313a3dc7
CO		 3301long kvm_arch_vcpu_ioctl(struct file *filp,
3302 unsigned int ioctl, unsigned long arg)
3303{
3304 struct kvm_vcpu *vcpu = filp->private_data;
3305 void __user *argp = (void __user *)arg;
3306 int r;
d1ac91d8
AK		 3307 union {
3308 struct kvm_lapic_state *lapic;
3309 struct kvm_xsave *xsave;
3310 struct kvm_xcrs *xcrs;
3311 void *buffer;
3312 } u;
3313
3314 u.buffer = NULL;
313a3dc7
CO		 3315 switch (ioctl) {
3316 case KVM_GET_LAPIC: {
2204ae3c 3317 r = -EINVAL;
bce87cce 3318 if (!lapic_in_kernel(vcpu))
2204ae3c 3319 goto out;
d1ac91d8 3320 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3321
b772ff36 3322 r = -ENOMEM;
d1ac91d8 3323 if (!u.lapic)
b772ff36 3324 goto out;
d1ac91d8 3325 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3326 if (r)
3327 goto out;
3328 r = -EFAULT;
d1ac91d8 3329 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3330 goto out;
3331 r = 0;
3332 break;
3333 }
3334 case KVM_SET_LAPIC: {
2204ae3c 3335 r = -EINVAL;
bce87cce 3336 if (!lapic_in_kernel(vcpu))
2204ae3c 3337 goto out;
ff5c2c03 3338 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3339 if (IS_ERR(u.lapic))
3340 return PTR_ERR(u.lapic);
ff5c2c03 3341
d1ac91d8 3342 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3343 break;
3344 }
f77bc6a4
ZX		 3345 case KVM_INTERRUPT: {
3346 struct kvm_interrupt irq;
3347
3348 r = -EFAULT;
3349 if (copy_from_user(&irq, argp, sizeof irq))
3350 goto out;
3351 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3352 break;
3353 }
c4abb7c9
JK		 3354 case KVM_NMI: {
3355 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3356 break;
3357 }
f077825a
PB		 3358 case KVM_SMI: {
3359 r = kvm_vcpu_ioctl_smi(vcpu);
3360 break;
3361 }
313a3dc7
CO		 3362 case KVM_SET_CPUID: {
3363 struct kvm_cpuid __user *cpuid_arg = argp;
3364 struct kvm_cpuid cpuid;
3365
3366 r = -EFAULT;
3367 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3368 goto out;
3369 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3370 break;
3371 }
07716717
DK		 3372 case KVM_SET_CPUID2: {
3373 struct kvm_cpuid2 __user *cpuid_arg = argp;
3374 struct kvm_cpuid2 cpuid;
3375
3376 r = -EFAULT;
3377 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3378 goto out;
3379 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3380 cpuid_arg->entries);
07716717
DK		 3381 break;
3382 }
3383 case KVM_GET_CPUID2: {
3384 struct kvm_cpuid2 __user *cpuid_arg = argp;
3385 struct kvm_cpuid2 cpuid;
3386
3387 r = -EFAULT;
3388 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3389 goto out;
3390 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3391 cpuid_arg->entries);
07716717
DK		 3392 if (r)
3393 goto out;
3394 r = -EFAULT;
3395 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3396 goto out;
3397 r = 0;
3398 break;
3399 }
313a3dc7 3400 case KVM_GET_MSRS:
609e36d3 3401 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3402 break;
3403 case KVM_SET_MSRS:
3404 r = msr_io(vcpu, argp, do_set_msr, 0);
3405 break;
b209749f
AK		 3406 case KVM_TPR_ACCESS_REPORTING: {
3407 struct kvm_tpr_access_ctl tac;
3408
3409 r = -EFAULT;
3410 if (copy_from_user(&tac, argp, sizeof tac))
3411 goto out;
3412 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3413 if (r)
3414 goto out;
3415 r = -EFAULT;
3416 if (copy_to_user(argp, &tac, sizeof tac))
3417 goto out;
3418 r = 0;
3419 break;
3420 };
b93463aa
AK		 3421 case KVM_SET_VAPIC_ADDR: {
3422 struct kvm_vapic_addr va;
3423
3424 r = -EINVAL;
35754c98 3425 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3426 goto out;
3427 r = -EFAULT;
3428 if (copy_from_user(&va, argp, sizeof va))
3429 goto out;
fda4e2e8 3430 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3431 break;
3432 }
890ca9ae
HY		 3433 case KVM_X86_SETUP_MCE: {
3434 u64 mcg_cap;
3435
3436 r = -EFAULT;
3437 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3438 goto out;
3439 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3440 break;
3441 }
3442 case KVM_X86_SET_MCE: {
3443 struct kvm_x86_mce mce;
3444
3445 r = -EFAULT;
3446 if (copy_from_user(&mce, argp, sizeof mce))
3447 goto out;
3448 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3449 break;
3450 }
3cfc3092
JK		 3451 case KVM_GET_VCPU_EVENTS: {
3452 struct kvm_vcpu_events events;
3453
3454 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3455
3456 r = -EFAULT;
3457 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3458 break;
3459 r = 0;
3460 break;
3461 }
3462 case KVM_SET_VCPU_EVENTS: {
3463 struct kvm_vcpu_events events;
3464
3465 r = -EFAULT;
3466 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3467 break;
3468
3469 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3470 break;
3471 }
a1efbe77
JK		 3472 case KVM_GET_DEBUGREGS: {
3473 struct kvm_debugregs dbgregs;
3474
3475 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3476
3477 r = -EFAULT;
3478 if (copy_to_user(argp, &dbgregs,
3479 sizeof(struct kvm_debugregs)))
3480 break;
3481 r = 0;
3482 break;
3483 }
3484 case KVM_SET_DEBUGREGS: {
3485 struct kvm_debugregs dbgregs;
3486
3487 r = -EFAULT;
3488 if (copy_from_user(&dbgregs, argp,
3489 sizeof(struct kvm_debugregs)))
3490 break;
3491
3492 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3493 break;
3494 }
2d5b5a66 3495 case KVM_GET_XSAVE: {
d1ac91d8 3496 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3497 r = -ENOMEM;
d1ac91d8 3498 if (!u.xsave)
2d5b5a66
SY		 3499 break;
3500
d1ac91d8 3501 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3502
3503 r = -EFAULT;
d1ac91d8 3504 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3505 break;
3506 r = 0;
3507 break;
3508 }
3509 case KVM_SET_XSAVE: {
ff5c2c03 3510 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3511 if (IS_ERR(u.xsave))
3512 return PTR_ERR(u.xsave);
2d5b5a66 3513
d1ac91d8 3514 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3515 break;
3516 }
3517 case KVM_GET_XCRS: {
d1ac91d8 3518 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3519 r = -ENOMEM;
d1ac91d8 3520 if (!u.xcrs)
2d5b5a66
SY		 3521 break;
3522
d1ac91d8 3523 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3524
3525 r = -EFAULT;
d1ac91d8 3526 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3527 sizeof(struct kvm_xcrs)))
3528 break;
3529 r = 0;
3530 break;
3531 }
3532 case KVM_SET_XCRS: {
ff5c2c03 3533 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3534 if (IS_ERR(u.xcrs))
3535 return PTR_ERR(u.xcrs);
2d5b5a66 3536
d1ac91d8 3537 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3538 break;
3539 }
92a1f12d
JR		 3540 case KVM_SET_TSC_KHZ: {
3541 u32 user_tsc_khz;
3542
3543 r = -EINVAL;
92a1f12d
JR		 3544 user_tsc_khz = (u32)arg;
3545
3546 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3547 goto out;
3548
cc578287
ZA		 3549 if (user_tsc_khz == 0)
3550 user_tsc_khz = tsc_khz;
3551
381d585c
HZ		 3552 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3553 r = 0;
92a1f12d 3554
92a1f12d
JR		 3555 goto out;
3556 }
3557 case KVM_GET_TSC_KHZ: {
cc578287 3558 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3559 goto out;
3560 }
1c0b28c2
EM		 3561 case KVM_KVMCLOCK_CTRL: {
3562 r = kvm_set_guest_paused(vcpu);
3563 goto out;
3564 }
5c919412
AS		 3565 case KVM_ENABLE_CAP: {
3566 struct kvm_enable_cap cap;
3567
3568 r = -EFAULT;
3569 if (copy_from_user(&cap, argp, sizeof(cap)))
3570 goto out;
3571 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3572 break;
3573 }
313a3dc7
CO		 3574 default:
3575 r = -EINVAL;
3576 }
3577out:
d1ac91d8 3578 kfree(u.buffer);
313a3dc7
CO		 3579 return r;
3580}
3581
5b1c1493
CO		 3582int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3583{
3584 return VM_FAULT_SIGBUS;
3585}
3586
1fe779f8
CO		 3587static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3588{
3589 int ret;
3590
3591 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3592 return -EINVAL;
1fe779f8
CO		 3593 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3594 return ret;
3595}
3596
b927a3ce
SY		 3597static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3598 u64 ident_addr)
3599{
3600 kvm->arch.ept_identity_map_addr = ident_addr;
3601 return 0;
3602}
3603
1fe779f8
CO		 3604static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3605 u32 kvm_nr_mmu_pages)
3606{
3607 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3608 return -EINVAL;
3609
79fac95e 3610 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3611
3612 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3613 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3614
79fac95e 3615 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3616 return 0;
3617}
3618
3619static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3620{
39de71ec 3621 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3622}
3623
1fe779f8
CO		 3624static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3625{
3626 int r;
3627
3628 r = 0;
3629 switch (chip->chip_id) {
3630 case KVM_IRQCHIP_PIC_MASTER:
3631 memcpy(&chip->chip.pic,
3632 &pic_irqchip(kvm)->pics[0],
3633 sizeof(struct kvm_pic_state));
3634 break;
3635 case KVM_IRQCHIP_PIC_SLAVE:
3636 memcpy(&chip->chip.pic,
3637 &pic_irqchip(kvm)->pics[1],
3638 sizeof(struct kvm_pic_state));
3639 break;
3640 case KVM_IRQCHIP_IOAPIC:
eba0226b 3641 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3642 break;
3643 default:
3644 r = -EINVAL;
3645 break;
3646 }
3647 return r;
3648}
3649
3650static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3651{
3652 int r;
3653
3654 r = 0;
3655 switch (chip->chip_id) {
3656 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3657 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3658 memcpy(&pic_irqchip(kvm)->pics[0],
3659 &chip->chip.pic,
3660 sizeof(struct kvm_pic_state));
f4f51050 3661 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3662 break;
3663 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3664 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3665 memcpy(&pic_irqchip(kvm)->pics[1],
3666 &chip->chip.pic,
3667 sizeof(struct kvm_pic_state));
f4f51050 3668 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3669 break;
3670 case KVM_IRQCHIP_IOAPIC:
eba0226b 3671 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3672 break;
3673 default:
3674 r = -EINVAL;
3675 break;
3676 }
3677 kvm_pic_update_irq(pic_irqchip(kvm));
3678 return r;
3679}
3680
e0f63cb9
SY		 3681static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3682{
34f3941c
RK		 3683 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3684
3685 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3686
3687 mutex_lock(&kps->lock);
3688 memcpy(ps, &kps->channels, sizeof(*ps));
3689 mutex_unlock(&kps->lock);
2da29bcc 3690 return 0;
e0f63cb9
SY		 3691}
3692
3693static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3694{
0185604c 3695 int i;
09edea72
RK		 3696 struct kvm_pit *pit = kvm->arch.vpit;
3697
3698 mutex_lock(&pit->pit_state.lock);
34f3941c 3699 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3700 for (i = 0; i < 3; i++)
09edea72
RK		 3701 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3702 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3703 return 0;
e9f42757
BK		 3704}
3705
3706static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3707{
e9f42757
BK		 3708 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3709 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3710 sizeof(ps->channels));
3711 ps->flags = kvm->arch.vpit->pit_state.flags;
3712 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3713 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3714 return 0;
e9f42757
BK		 3715}
3716
3717static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3718{
2da29bcc 3719 int start = 0;
0185604c 3720 int i;
e9f42757 3721 u32 prev_legacy, cur_legacy;
09edea72
RK		 3722 struct kvm_pit *pit = kvm->arch.vpit;
3723
3724 mutex_lock(&pit->pit_state.lock);
3725 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3726 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3727 if (!prev_legacy && cur_legacy)
3728 start = 1;
09edea72
RK		 3729 memcpy(&pit->pit_state.channels, &ps->channels,
3730 sizeof(pit->pit_state.channels));
3731 pit->pit_state.flags = ps->flags;
0185604c 3732 for (i = 0; i < 3; i++)
09edea72 3733 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3734 start && i == 0);
09edea72 3735 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3736 return 0;
e0f63cb9
SY		 3737}
3738
52d939a0
MT		 3739static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3740 struct kvm_reinject_control *control)
3741{
71474e2f
RK		 3742 struct kvm_pit *pit = kvm->arch.vpit;
3743
3744 if (!pit)
52d939a0 3745 return -ENXIO;
b39c90b6 3746
71474e2f
RK		 3747 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3748 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3749 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3750 */
3751 mutex_lock(&pit->pit_state.lock);
3752 kvm_pit_set_reinject(pit, control->pit_reinject);
3753 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3754
52d939a0
MT		 3755 return 0;
3756}
3757
95d4c16c 3758/**
60c34612
TY		 3759 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3760 * @kvm: kvm instance
3761 * @log: slot id and address to which we copy the log
95d4c16c 3762 *
e108ff2f
PB		 3763 * Steps 1-4 below provide general overview of dirty page logging. See
3764 * kvm_get_dirty_log_protect() function description for additional details.
3765 *
3766 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3767 * always flush the TLB (step 4) even if previous step failed and the dirty
3768 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3769 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3770 * writes will be marked dirty for next log read.
95d4c16c 3771 *
60c34612
TY		 3772 * 1. Take a snapshot of the bit and clear it if needed.
3773 * 2. Write protect the corresponding page.
e108ff2f
PB		 3774 * 3. Copy the snapshot to the userspace.
3775 * 4. Flush TLB's if needed.
5bb064dc 3776 */
60c34612 3777int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3778{
60c34612 3779 bool is_dirty = false;
e108ff2f 3780 int r;
5bb064dc 3781
79fac95e 3782 mutex_lock(&kvm->slots_lock);
5bb064dc 3783
88178fd4
KH		 3784 /*
3785 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3786 */
3787 if (kvm_x86_ops->flush_log_dirty)
3788 kvm_x86_ops->flush_log_dirty(kvm);
3789
e108ff2f 3790 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3791
3792 /*
3793 * All the TLBs can be flushed out of mmu lock, see the comments in
3794 * kvm_mmu_slot_remove_write_access().
3795 */
e108ff2f 3796 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3797 if (is_dirty)
3798 kvm_flush_remote_tlbs(kvm);
3799
79fac95e 3800 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3801 return r;
3802}
3803
aa2fbe6d
YZ		 3804int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3805 bool line_status)
23d43cf9
CD		 3806{
3807 if (!irqchip_in_kernel(kvm))
3808 return -ENXIO;
3809
3810 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3811 irq_event->irq, irq_event->level,
3812 line_status);
23d43cf9
CD		 3813 return 0;
3814}
3815
90de4a18
NA		 3816static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3817 struct kvm_enable_cap *cap)
3818{
3819 int r;
3820
3821 if (cap->flags)
3822 return -EINVAL;
3823
3824 switch (cap->cap) {
3825 case KVM_CAP_DISABLE_QUIRKS:
3826 kvm->arch.disabled_quirks = cap->args[0];
3827 r = 0;
3828 break;
49df6397
SR		 3829 case KVM_CAP_SPLIT_IRQCHIP: {
3830 mutex_lock(&kvm->lock);
b053b2ae
SR		 3831 r = -EINVAL;
3832 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3833 goto split_irqchip_unlock;
49df6397
SR		 3834 r = -EEXIST;
3835 if (irqchip_in_kernel(kvm))
3836 goto split_irqchip_unlock;
557abc40 3837 if (kvm->created_vcpus)
49df6397
SR		 3838 goto split_irqchip_unlock;
3839 r = kvm_setup_empty_irq_routing(kvm);
3840 if (r)
3841 goto split_irqchip_unlock;
3842 /* Pairs with irqchip_in_kernel. */
3843 smp_wmb();
3844 kvm->arch.irqchip_split = true;
b053b2ae 3845 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3846 r = 0;
3847split_irqchip_unlock:
3848 mutex_unlock(&kvm->lock);
3849 break;
3850 }
37131313
RK		 3851 case KVM_CAP_X2APIC_API:
3852 r = -EINVAL;
3853 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3854 break;
3855
3856 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3857 kvm->arch.x2apic_format = true;
c519265f
RK		 3858 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3859 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3860
3861 r = 0;
3862 break;
90de4a18
NA		 3863 default:
3864 r = -EINVAL;
3865 break;
3866 }
3867 return r;
3868}
3869
1fe779f8
CO		 3870long kvm_arch_vm_ioctl(struct file *filp,
3871 unsigned int ioctl, unsigned long arg)
3872{
3873 struct kvm *kvm = filp->private_data;
3874 void __user *argp = (void __user *)arg;
367e1319 3875 int r = -ENOTTY;
f0d66275
DH		 3876 /*
3877 * This union makes it completely explicit to gcc-3.x
3878 * that these two variables' stack usage should be
3879 * combined, not added together.
3880 */
3881 union {
3882 struct kvm_pit_state ps;
e9f42757 3883 struct kvm_pit_state2 ps2;
c5ff41ce 3884 struct kvm_pit_config pit_config;
f0d66275 3885 } u;
1fe779f8
CO		 3886
3887 switch (ioctl) {
3888 case KVM_SET_TSS_ADDR:
3889 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3890 break;
b927a3ce
SY		 3891 case KVM_SET_IDENTITY_MAP_ADDR: {
3892 u64 ident_addr;
3893
3894 r = -EFAULT;
3895 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3896 goto out;
3897 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3898 break;
3899 }
1fe779f8
CO		 3900 case KVM_SET_NR_MMU_PAGES:
3901 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3902 break;
3903 case KVM_GET_NR_MMU_PAGES:
3904 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3905 break;
3ddea128
MT		 3906 case KVM_CREATE_IRQCHIP: {
3907 struct kvm_pic *vpic;
3908
3909 mutex_lock(&kvm->lock);
3910 r = -EEXIST;
3911 if (kvm->arch.vpic)
3912 goto create_irqchip_unlock;
3e515705 3913 r = -EINVAL;
557abc40 3914 if (kvm->created_vcpus)
3e515705 3915 goto create_irqchip_unlock;
1fe779f8 3916 r = -ENOMEM;
3ddea128
MT		 3917 vpic = kvm_create_pic(kvm);
3918 if (vpic) {
1fe779f8
CO		 3919 r = kvm_ioapic_init(kvm);
3920 if (r) {
175504cd 3921 mutex_lock(&kvm->slots_lock);
71ba994c 3922 kvm_destroy_pic(vpic);
175504cd 3923 mutex_unlock(&kvm->slots_lock);
3ddea128 3924 goto create_irqchip_unlock;
1fe779f8
CO		 3925 }
3926 } else
3ddea128 3927 goto create_irqchip_unlock;
399ec807
AK		 3928 r = kvm_setup_default_irq_routing(kvm);
3929 if (r) {
175504cd 3930 mutex_lock(&kvm->slots_lock);
3ddea128 3931 mutex_lock(&kvm->irq_lock);
72bb2fcd 3932 kvm_ioapic_destroy(kvm);
71ba994c 3933 kvm_destroy_pic(vpic);
3ddea128 3934 mutex_unlock(&kvm->irq_lock);
175504cd 3935 mutex_unlock(&kvm->slots_lock);
71ba994c 3936 goto create_irqchip_unlock;
399ec807 3937 }
71ba994c
PB		 3938 /* Write kvm->irq_routing before kvm->arch.vpic. */
3939 smp_wmb();
3940 kvm->arch.vpic = vpic;
3ddea128
MT		 3941 create_irqchip_unlock:
3942 mutex_unlock(&kvm->lock);
1fe779f8 3943 break;
3ddea128 3944 }
7837699f 3945 case KVM_CREATE_PIT:
c5ff41ce
JK		 3946 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3947 goto create_pit;
3948 case KVM_CREATE_PIT2:
3949 r = -EFAULT;
3950 if (copy_from_user(&u.pit_config, argp,
3951 sizeof(struct kvm_pit_config)))
3952 goto out;
3953 create_pit:
250715a6 3954 mutex_lock(&kvm->lock);
269e05e4
AK		 3955 r = -EEXIST;
3956 if (kvm->arch.vpit)
3957 goto create_pit_unlock;
7837699f 3958 r = -ENOMEM;
c5ff41ce 3959 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3960 if (kvm->arch.vpit)
3961 r = 0;
269e05e4 3962 create_pit_unlock:
250715a6 3963 mutex_unlock(&kvm->lock);
7837699f 3964 break;
1fe779f8
CO		 3965 case KVM_GET_IRQCHIP: {
3966 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3967 struct kvm_irqchip *chip;
1fe779f8 3968
ff5c2c03
SL		 3969 chip = memdup_user(argp, sizeof(*chip));
3970 if (IS_ERR(chip)) {
3971 r = PTR_ERR(chip);
1fe779f8 3972 goto out;
ff5c2c03
SL		 3973 }
3974
1fe779f8 3975 r = -ENXIO;
49df6397 3976 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3977 goto get_irqchip_out;
3978 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3979 if (r)
f0d66275 3980 goto get_irqchip_out;
1fe779f8 3981 r = -EFAULT;
f0d66275
DH		 3982 if (copy_to_user(argp, chip, sizeof *chip))
3983 goto get_irqchip_out;
1fe779f8 3984 r = 0;
f0d66275
DH		 3985 get_irqchip_out:
3986 kfree(chip);
1fe779f8
CO		 3987 break;
3988 }
3989 case KVM_SET_IRQCHIP: {
3990 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3991 struct kvm_irqchip *chip;
1fe779f8 3992
ff5c2c03
SL		 3993 chip = memdup_user(argp, sizeof(*chip));
3994 if (IS_ERR(chip)) {
3995 r = PTR_ERR(chip);
1fe779f8 3996 goto out;
ff5c2c03
SL		 3997 }
3998
1fe779f8 3999 r = -ENXIO;
49df6397 4000 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 4001 goto set_irqchip_out;
4002 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4003 if (r)
f0d66275 4004 goto set_irqchip_out;
1fe779f8 4005 r = 0;
f0d66275
DH		 4006 set_irqchip_out:
4007 kfree(chip);
1fe779f8
CO		 4008 break;
4009 }
e0f63cb9 4010 case KVM_GET_PIT: {
e0f63cb9 4011 r = -EFAULT;
f0d66275 4012 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4013 goto out;
4014 r = -ENXIO;
4015 if (!kvm->arch.vpit)
4016 goto out;
f0d66275 4017 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4018 if (r)
4019 goto out;
4020 r = -EFAULT;
f0d66275 4021 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4022 goto out;
4023 r = 0;
4024 break;
4025 }
4026 case KVM_SET_PIT: {
e0f63cb9 4027 r = -EFAULT;
f0d66275 4028 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4029 goto out;
4030 r = -ENXIO;
4031 if (!kvm->arch.vpit)
4032 goto out;
f0d66275 4033 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4034 break;
4035 }
e9f42757
BK		 4036 case KVM_GET_PIT2: {
4037 r = -ENXIO;
4038 if (!kvm->arch.vpit)
4039 goto out;
4040 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4041 if (r)
4042 goto out;
4043 r = -EFAULT;
4044 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4045 goto out;
4046 r = 0;
4047 break;
4048 }
4049 case KVM_SET_PIT2: {
4050 r = -EFAULT;
4051 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4052 goto out;
4053 r = -ENXIO;
4054 if (!kvm->arch.vpit)
4055 goto out;
4056 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4057 break;
4058 }
52d939a0
MT		 4059 case KVM_REINJECT_CONTROL: {
4060 struct kvm_reinject_control control;
4061 r = -EFAULT;
4062 if (copy_from_user(&control, argp, sizeof(control)))
4063 goto out;
4064 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4065 break;
4066 }
d71ba788
PB		 4067 case KVM_SET_BOOT_CPU_ID:
4068 r = 0;
4069 mutex_lock(&kvm->lock);
557abc40 4070 if (kvm->created_vcpus)
d71ba788
PB		 4071 r = -EBUSY;
4072 else
4073 kvm->arch.bsp_vcpu_id = arg;
4074 mutex_unlock(&kvm->lock);
4075 break;
ffde22ac
ES		 4076 case KVM_XEN_HVM_CONFIG: {
4077 r = -EFAULT;
4078 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4079 sizeof(struct kvm_xen_hvm_config)))
4080 goto out;
4081 r = -EINVAL;
4082 if (kvm->arch.xen_hvm_config.flags)
4083 goto out;
4084 r = 0;
4085 break;
4086 }
afbcf7ab 4087 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4088 struct kvm_clock_data user_ns;
4089 u64 now_ns;
afbcf7ab
GC		 4090
4091 r = -EFAULT;
4092 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4093 goto out;
4094
4095 r = -EINVAL;
4096 if (user_ns.flags)
4097 goto out;
4098
4099 r = 0;
395c6b0a 4100 local_irq_disable();
108b249c
PB		 4101 now_ns = __get_kvmclock_ns(kvm);
4102 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
395c6b0a 4103 local_irq_enable();
2e762ff7 4104 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4105 break;
4106 }
4107 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4108 struct kvm_clock_data user_ns;
4109 u64 now_ns;
4110
108b249c
PB		 4111 now_ns = get_kvmclock_ns(kvm);
4112 user_ns.clock = now_ns;
afbcf7ab 4113 user_ns.flags = 0;
97e69aa6 4114 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4115
4116 r = -EFAULT;
4117 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4118 goto out;
4119 r = 0;
4120 break;
4121 }
90de4a18
NA		 4122 case KVM_ENABLE_CAP: {
4123 struct kvm_enable_cap cap;
afbcf7ab 4124
90de4a18
NA		 4125 r = -EFAULT;
4126 if (copy_from_user(&cap, argp, sizeof(cap)))
4127 goto out;
4128 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4129 break;
4130 }
1fe779f8 4131 default:
c274e03a 4132 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4133 }
4134out:
4135 return r;
4136}
4137
a16b043c 4138static void kvm_init_msr_list(void)
043405e1
CO		 4139{
4140 u32 dummy[2];
4141 unsigned i, j;
4142
62ef68bb 4143 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4144 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4145 continue;
93c4adc7
PB		 4146
4147 /*
4148 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4149 * to the guests in some cases.
93c4adc7
PB		 4150 */
4151 switch (msrs_to_save[i]) {
4152 case MSR_IA32_BNDCFGS:
4153 if (!kvm_x86_ops->mpx_supported())
4154 continue;
4155 break;
9dbe6cf9
PB		 4156 case MSR_TSC_AUX:
4157 if (!kvm_x86_ops->rdtscp_supported())
4158 continue;
4159 break;
93c4adc7
PB		 4160 default:
4161 break;
4162 }
4163
043405e1
CO		 4164 if (j < i)
4165 msrs_to_save[j] = msrs_to_save[i];
4166 j++;
4167 }
4168 num_msrs_to_save = j;
62ef68bb
PB		 4169
4170 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4171 switch (emulated_msrs[i]) {
6d396b55
PB		 4172 case MSR_IA32_SMBASE:
4173 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4174 continue;
4175 break;
62ef68bb
PB		 4176 default:
4177 break;
4178 }
4179
4180 if (j < i)
4181 emulated_msrs[j] = emulated_msrs[i];
4182 j++;
4183 }
4184 num_emulated_msrs = j;
043405e1
CO		 4185}
4186
bda9020e
MT		 4187static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4188 const void *v)
bbd9b64e 4189{
70252a10
AK		 4190 int handled = 0;
4191 int n;
4192
4193 do {
4194 n = min(len, 8);
bce87cce 4195 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4196 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4197 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4198 break;
4199 handled += n;
4200 addr += n;
4201 len -= n;
4202 v += n;
4203 } while (len);
bbd9b64e 4204
70252a10 4205 return handled;
bbd9b64e
CO		 4206}
4207
bda9020e 4208static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4209{
70252a10
AK		 4210 int handled = 0;
4211 int n;
4212
4213 do {
4214 n = min(len, 8);
bce87cce 4215 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4216 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4217 addr, n, v))
4218 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4219 break;
4220 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4221 handled += n;
4222 addr += n;
4223 len -= n;
4224 v += n;
4225 } while (len);
bbd9b64e 4226
70252a10 4227 return handled;
bbd9b64e
CO		 4228}
4229
2dafc6c2
GN		 4230static void kvm_set_segment(struct kvm_vcpu *vcpu,
4231 struct kvm_segment *var, int seg)
4232{
4233 kvm_x86_ops->set_segment(vcpu, var, seg);
4234}
4235
4236void kvm_get_segment(struct kvm_vcpu *vcpu,
4237 struct kvm_segment *var, int seg)
4238{
4239 kvm_x86_ops->get_segment(vcpu, var, seg);
4240}
4241
54987b7a
PB		 4242gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4243 struct x86_exception *exception)
02f59dc9
JR		 4244{
4245 gpa_t t_gpa;
02f59dc9
JR		 4246
4247 BUG_ON(!mmu_is_nested(vcpu));
4248
4249 /* NPT walks are always user-walks */
4250 access |= PFERR_USER_MASK;
54987b7a 4251 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4252
4253 return t_gpa;
4254}
4255
ab9ae313
AK		 4256gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4257 struct x86_exception *exception)
1871c602
GN		 4258{
4259 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4260 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4261}
4262
ab9ae313
AK		 4263 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4264 struct x86_exception *exception)
1871c602
GN		 4265{
4266 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4267 access |= PFERR_FETCH_MASK;
ab9ae313 4268 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4269}
4270
ab9ae313
AK		 4271gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4272 struct x86_exception *exception)
1871c602
GN		 4273{
4274 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4275 access |= PFERR_WRITE_MASK;
ab9ae313 4276 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4277}
4278
4279/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4280gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4281 struct x86_exception *exception)
1871c602 4282{
ab9ae313 4283 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4284}
4285
4286static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4287 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4288 struct x86_exception *exception)
bbd9b64e
CO		 4289{
4290 void *data = val;
10589a46 4291 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4292
4293 while (bytes) {
14dfe855 4294 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4295 exception);
bbd9b64e 4296 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4297 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4298 int ret;
4299
bcc55cba 4300 if (gpa == UNMAPPED_GVA)
ab9ae313 4301 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4302 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4303 offset, toread);
10589a46 4304 if (ret < 0) {
c3cd7ffa 4305 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4306 goto out;
4307 }
bbd9b64e 4308
77c2002e
IE		 4309 bytes -= toread;
4310 data += toread;
4311 addr += toread;
bbd9b64e 4312 }
10589a46 4313out:
10589a46 4314 return r;
bbd9b64e 4315}
77c2002e 4316
1871c602 4317/* used for instruction fetching */
0f65dd70
AK		 4318static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4319 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4320 struct x86_exception *exception)
1871c602 4321{
0f65dd70 4322 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4323 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4324 unsigned offset;
4325 int ret;
0f65dd70 4326
44583cba
PB		 4327 /* Inline kvm_read_guest_virt_helper for speed. */
4328 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4329 exception);
4330 if (unlikely(gpa == UNMAPPED_GVA))
4331 return X86EMUL_PROPAGATE_FAULT;
4332
4333 offset = addr & (PAGE_SIZE-1);
4334 if (WARN_ON(offset + bytes > PAGE_SIZE))
4335 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4336 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4337 offset, bytes);
44583cba
PB		 4338 if (unlikely(ret < 0))
4339 return X86EMUL_IO_NEEDED;
4340
4341 return X86EMUL_CONTINUE;
1871c602
GN		 4342}
4343
064aea77 4344int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4345 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4346 struct x86_exception *exception)
1871c602 4347{
0f65dd70 4348 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4349 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4350
1871c602 4351 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4352 exception);
1871c602 4353}
064aea77 4354EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4355
0f65dd70
AK		 4356static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4357 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4358 struct x86_exception *exception)
1871c602 4359{
0f65dd70 4360 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4361 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4362}
4363
7a036a6f
RK		 4364static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4365 unsigned long addr, void *val, unsigned int bytes)
4366{
4367 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4368 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4369
4370 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4371}
4372
6a4d7550 4373int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4374 gva_t addr, void *val,
2dafc6c2 4375 unsigned int bytes,
bcc55cba 4376 struct x86_exception *exception)
77c2002e 4377{
0f65dd70 4378 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4379 void *data = val;
4380 int r = X86EMUL_CONTINUE;
4381
4382 while (bytes) {
14dfe855
JR		 4383 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4384 PFERR_WRITE_MASK,
ab9ae313 4385 exception);
77c2002e
IE		 4386 unsigned offset = addr & (PAGE_SIZE-1);
4387 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4388 int ret;
4389
bcc55cba 4390 if (gpa == UNMAPPED_GVA)
ab9ae313 4391 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4392 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4393 if (ret < 0) {
c3cd7ffa 4394 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4395 goto out;
4396 }
4397
4398 bytes -= towrite;
4399 data += towrite;
4400 addr += towrite;
4401 }
4402out:
4403 return r;
4404}
6a4d7550 4405EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4406
af7cc7d1
XG		 4407static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4408 gpa_t *gpa, struct x86_exception *exception,
4409 bool write)
4410{
97d64b78
AK		 4411 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4412 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4413
be94f6b7
HH		 4414 /*
4415 * currently PKRU is only applied to ept enabled guest so
4416 * there is no pkey in EPT page table for L1 guest or EPT
4417 * shadow page table for L2 guest.
4418 */
97d64b78 4419 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4420 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4421 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4422 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4423 (gva & (PAGE_SIZE - 1));
4f022648 4424 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4425 return 1;
4426 }
4427
af7cc7d1
XG		 4428 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4429
4430 if (*gpa == UNMAPPED_GVA)
4431 return -1;
4432
4433 /* For APIC access vmexit */
4434 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4435 return 1;
4436
4f022648
XG		 4437 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4438 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4439 return 1;
4f022648 4440 }
bebb106a 4441
af7cc7d1
XG		 4442 return 0;
4443}
4444
3200f405 4445int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4446 const void *val, int bytes)
bbd9b64e
CO		 4447{
4448 int ret;
4449
54bf36aa 4450 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4451 if (ret < 0)
bbd9b64e 4452 return 0;
0eb05bf2 4453 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4454 return 1;
4455}
4456
77d197b2
XG		 4457struct read_write_emulator_ops {
4458 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4459 int bytes);
4460 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4461 void *val, int bytes);
4462 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4463 int bytes, void *val);
4464 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4465 void *val, int bytes);
4466 bool write;
4467};
4468
4469static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4470{
4471 if (vcpu->mmio_read_completed) {
77d197b2 4472 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4473 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4474 vcpu->mmio_read_completed = 0;
4475 return 1;
4476 }
4477
4478 return 0;
4479}
4480
4481static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4482 void *val, int bytes)
4483{
54bf36aa 4484 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4485}
4486
4487static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4488 void *val, int bytes)
4489{
4490 return emulator_write_phys(vcpu, gpa, val, bytes);
4491}
4492
4493static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4494{
4495 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4496 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4497}
4498
4499static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4500 void *val, int bytes)
4501{
4502 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4503 return X86EMUL_IO_NEEDED;
4504}
4505
4506static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4507 void *val, int bytes)
4508{
f78146b0
AK		 4509 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4510
87da7e66 4511 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4512 return X86EMUL_CONTINUE;
4513}
4514
0fbe9b0b 4515static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4516 .read_write_prepare = read_prepare,
4517 .read_write_emulate = read_emulate,
4518 .read_write_mmio = vcpu_mmio_read,
4519 .read_write_exit_mmio = read_exit_mmio,
4520};
4521
0fbe9b0b 4522static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4523 .read_write_emulate = write_emulate,
4524 .read_write_mmio = write_mmio,
4525 .read_write_exit_mmio = write_exit_mmio,
4526 .write = true,
4527};
4528
22388a3c
XG		 4529static int emulator_read_write_onepage(unsigned long addr, void *val,
4530 unsigned int bytes,
4531 struct x86_exception *exception,
4532 struct kvm_vcpu *vcpu,
0fbe9b0b 4533 const struct read_write_emulator_ops *ops)
bbd9b64e 4534{
af7cc7d1
XG		 4535 gpa_t gpa;
4536 int handled, ret;
22388a3c 4537 bool write = ops->write;
f78146b0 4538 struct kvm_mmio_fragment *frag;
10589a46 4539
22388a3c 4540 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4541
af7cc7d1 4542 if (ret < 0)
bbd9b64e 4543 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4544
4545 /* For APIC access vmexit */
af7cc7d1 4546 if (ret)
bbd9b64e
CO		 4547 goto mmio;
4548
22388a3c 4549 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4550 return X86EMUL_CONTINUE;
4551
4552mmio:
4553 /*
4554 * Is this MMIO handled locally?
4555 */
22388a3c 4556 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4557 if (handled == bytes)
bbd9b64e 4558 return X86EMUL_CONTINUE;
bbd9b64e 4559
70252a10
AK		 4560 gpa += handled;
4561 bytes -= handled;
4562 val += handled;
4563
87da7e66
XG		 4564 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4565 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4566 frag->gpa = gpa;
4567 frag->data = val;
4568 frag->len = bytes;
f78146b0 4569 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4570}
4571
52eb5a6d
XL		 4572static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4573 unsigned long addr,
22388a3c
XG		 4574 void *val, unsigned int bytes,
4575 struct x86_exception *exception,
0fbe9b0b 4576 const struct read_write_emulator_ops *ops)
bbd9b64e 4577{
0f65dd70 4578 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4579 gpa_t gpa;
4580 int rc;
4581
4582 if (ops->read_write_prepare &&
4583 ops->read_write_prepare(vcpu, val, bytes))
4584 return X86EMUL_CONTINUE;
4585
4586 vcpu->mmio_nr_fragments = 0;
0f65dd70 4587
bbd9b64e
CO		 4588 /* Crossing a page boundary? */
4589 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4590 int now;
bbd9b64e
CO		 4591
4592 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4593 rc = emulator_read_write_onepage(addr, val, now, exception,
4594 vcpu, ops);
4595
bbd9b64e
CO		 4596 if (rc != X86EMUL_CONTINUE)
4597 return rc;
4598 addr += now;
bac15531
NA		 4599 if (ctxt->mode != X86EMUL_MODE_PROT64)
4600 addr = (u32)addr;
bbd9b64e
CO		 4601 val += now;
4602 bytes -= now;
4603 }
22388a3c 4604
f78146b0
AK		 4605 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4606 vcpu, ops);
4607 if (rc != X86EMUL_CONTINUE)
4608 return rc;
4609
4610 if (!vcpu->mmio_nr_fragments)
4611 return rc;
4612
4613 gpa = vcpu->mmio_fragments[0].gpa;
4614
4615 vcpu->mmio_needed = 1;
4616 vcpu->mmio_cur_fragment = 0;
4617
87da7e66 4618 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4619 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4620 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4621 vcpu->run->mmio.phys_addr = gpa;
4622
4623 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4624}
4625
4626static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4627 unsigned long addr,
4628 void *val,
4629 unsigned int bytes,
4630 struct x86_exception *exception)
4631{
4632 return emulator_read_write(ctxt, addr, val, bytes,
4633 exception, &read_emultor);
4634}
4635
52eb5a6d 4636static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4637 unsigned long addr,
4638 const void *val,
4639 unsigned int bytes,
4640 struct x86_exception *exception)
4641{
4642 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4643 exception, &write_emultor);
bbd9b64e 4644}
bbd9b64e 4645
daea3e73
AK		 4646#define CMPXCHG_TYPE(t, ptr, old, new) \
4647 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4648
4649#ifdef CONFIG_X86_64
4650# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4651#else
4652# define CMPXCHG64(ptr, old, new) \
9749a6c0 4653 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4654#endif
4655
0f65dd70
AK		 4656static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4657 unsigned long addr,
bbd9b64e
CO		 4658 const void *old,
4659 const void *new,
4660 unsigned int bytes,
0f65dd70 4661 struct x86_exception *exception)
bbd9b64e 4662{
0f65dd70 4663 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4664 gpa_t gpa;
4665 struct page *page;
4666 char *kaddr;
4667 bool exchanged;
2bacc55c 4668
daea3e73
AK		 4669 /* guests cmpxchg8b have to be emulated atomically */
4670 if (bytes > 8 || (bytes & (bytes - 1)))
4671 goto emul_write;
10589a46 4672
daea3e73 4673 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4674
daea3e73
AK		 4675 if (gpa == UNMAPPED_GVA ||
4676 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4677 goto emul_write;
2bacc55c 4678
daea3e73
AK		 4679 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4680 goto emul_write;
72dc67a6 4681
54bf36aa 4682 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4683 if (is_error_page(page))
c19b8bd6 4684 goto emul_write;
72dc67a6 4685
8fd75e12 4686 kaddr = kmap_atomic(page);
daea3e73
AK		 4687 kaddr += offset_in_page(gpa);
4688 switch (bytes) {
4689 case 1:
4690 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4691 break;
4692 case 2:
4693 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4694 break;
4695 case 4:
4696 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4697 break;
4698 case 8:
4699 exchanged = CMPXCHG64(kaddr, old, new);
4700 break;
4701 default:
4702 BUG();
2bacc55c 4703 }
8fd75e12 4704 kunmap_atomic(kaddr);
daea3e73
AK		 4705 kvm_release_page_dirty(page);
4706
4707 if (!exchanged)
4708 return X86EMUL_CMPXCHG_FAILED;
4709
54bf36aa 4710 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4711 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4712
4713 return X86EMUL_CONTINUE;
4a5f48f6 4714
3200f405 4715emul_write:
daea3e73 4716 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4717
0f65dd70 4718 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4719}
4720
cf8f70bf
GN		 4721static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4722{
4723 /* TODO: String I/O for in kernel device */
4724 int r;
4725
4726 if (vcpu->arch.pio.in)
e32edf4f 4727 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4728 vcpu->arch.pio.size, pd);
4729 else
e32edf4f 4730 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4731 vcpu->arch.pio.port, vcpu->arch.pio.size,
4732 pd);
4733 return r;
4734}
4735
6f6fbe98
XG		 4736static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4737 unsigned short port, void *val,
4738 unsigned int count, bool in)
cf8f70bf 4739{
cf8f70bf 4740 vcpu->arch.pio.port = port;
6f6fbe98 4741 vcpu->arch.pio.in = in;
7972995b 4742 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4743 vcpu->arch.pio.size = size;
4744
4745 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4746 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4747 return 1;
4748 }
4749
4750 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4751 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4752 vcpu->run->io.size = size;
4753 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4754 vcpu->run->io.count = count;
4755 vcpu->run->io.port = port;
4756
4757 return 0;
4758}
4759
6f6fbe98
XG		 4760static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4761 int size, unsigned short port, void *val,
4762 unsigned int count)
cf8f70bf 4763{
ca1d4a9e 4764 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4765 int ret;
ca1d4a9e 4766
6f6fbe98
XG		 4767 if (vcpu->arch.pio.count)
4768 goto data_avail;
cf8f70bf 4769
6f6fbe98
XG		 4770 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4771 if (ret) {
4772data_avail:
4773 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4774 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4775 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4776 return 1;
4777 }
4778
cf8f70bf
GN		 4779 return 0;
4780}
4781
6f6fbe98
XG		 4782static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4783 int size, unsigned short port,
4784 const void *val, unsigned int count)
4785{
4786 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4787
4788 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4789 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4790 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4791}
4792
bbd9b64e
CO		 4793static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4794{
4795 return kvm_x86_ops->get_segment_base(vcpu, seg);
4796}
4797
3cb16fe7 4798static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4799{
3cb16fe7 4800 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4801}
4802
5cb56059 4803int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4804{
4805 if (!need_emulate_wbinvd(vcpu))
4806 return X86EMUL_CONTINUE;
4807
4808 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4809 int cpu = get_cpu();
4810
4811 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4812 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4813 wbinvd_ipi, NULL, 1);
2eec7343 4814 put_cpu();
f5f48ee1 4815 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4816 } else
4817 wbinvd();
f5f48ee1
SY		 4818 return X86EMUL_CONTINUE;
4819}
5cb56059
JS		 4820
4821int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4822{
4823 kvm_x86_ops->skip_emulated_instruction(vcpu);
4824 return kvm_emulate_wbinvd_noskip(vcpu);
4825}
f5f48ee1
SY		 4826EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4827
5cb56059
JS		 4828
4829
bcaf5cc5
AK		 4830static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4831{
5cb56059 4832 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4833}
4834
52eb5a6d
XL		 4835static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4836 unsigned long *dest)
bbd9b64e 4837{
16f8a6f9 4838 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4839}
4840
52eb5a6d
XL		 4841static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4842 unsigned long value)
bbd9b64e 4843{
338dbc97 4844
717746e3 4845 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4846}
4847
52a46617 4848static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4849{
52a46617 4850 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4851}
4852
717746e3 4853static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4854{
717746e3 4855 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4856 unsigned long value;
4857
4858 switch (cr) {
4859 case 0:
4860 value = kvm_read_cr0(vcpu);
4861 break;
4862 case 2:
4863 value = vcpu->arch.cr2;
4864 break;
4865 case 3:
9f8fe504 4866 value = kvm_read_cr3(vcpu);
52a46617
GN		 4867 break;
4868 case 4:
4869 value = kvm_read_cr4(vcpu);
4870 break;
4871 case 8:
4872 value = kvm_get_cr8(vcpu);
4873 break;
4874 default:
a737f256 4875 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4876 return 0;
4877 }
4878
4879 return value;
4880}
4881
717746e3 4882static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4883{
717746e3 4884 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4885 int res = 0;
4886
52a46617
GN		 4887 switch (cr) {
4888 case 0:
49a9b07e 4889 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4890 break;
4891 case 2:
4892 vcpu->arch.cr2 = val;
4893 break;
4894 case 3:
2390218b 4895 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4896 break;
4897 case 4:
a83b29c6 4898 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4899 break;
4900 case 8:
eea1cff9 4901 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4902 break;
4903 default:
a737f256 4904 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4905 res = -1;
52a46617 4906 }
0f12244f
GN		 4907
4908 return res;
52a46617
GN		 4909}
4910
717746e3 4911static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4912{
717746e3 4913 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4914}
4915
4bff1e86 4916static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4917{
4bff1e86 4918 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4919}
4920
4bff1e86 4921static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4922{
4bff1e86 4923 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4924}
4925
1ac9d0cf
AK		 4926static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4927{
4928 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4929}
4930
4931static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4932{
4933 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4934}
4935
4bff1e86
AK		 4936static unsigned long emulator_get_cached_segment_base(
4937 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4938{
4bff1e86 4939 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4940}
4941
1aa36616
AK		 4942static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4943 struct desc_struct *desc, u32 *base3,
4944 int seg)
2dafc6c2
GN		 4945{
4946 struct kvm_segment var;
4947
4bff1e86 4948 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4949 *selector = var.selector;
2dafc6c2 4950
378a8b09
GN		 4951 if (var.unusable) {
4952 memset(desc, 0, sizeof(*desc));
2dafc6c2 4953 return false;
378a8b09 4954 }
2dafc6c2
GN		 4955
4956 if (var.g)
4957 var.limit >>= 12;
4958 set_desc_limit(desc, var.limit);
4959 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4960#ifdef CONFIG_X86_64
4961 if (base3)
4962 *base3 = var.base >> 32;
4963#endif
2dafc6c2
GN		 4964 desc->type = var.type;
4965 desc->s = var.s;
4966 desc->dpl = var.dpl;
4967 desc->p = var.present;
4968 desc->avl = var.avl;
4969 desc->l = var.l;
4970 desc->d = var.db;
4971 desc->g = var.g;
4972
4973 return true;
4974}
4975
1aa36616
AK		 4976static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4977 struct desc_struct *desc, u32 base3,
4978 int seg)
2dafc6c2 4979{
4bff1e86 4980 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4981 struct kvm_segment var;
4982
1aa36616 4983 var.selector = selector;
2dafc6c2 4984 var.base = get_desc_base(desc);
5601d05b
GN		 4985#ifdef CONFIG_X86_64
4986 var.base |= ((u64)base3) << 32;
4987#endif
2dafc6c2
GN		 4988 var.limit = get_desc_limit(desc);
4989 if (desc->g)
4990 var.limit = (var.limit << 12) | 0xfff;
4991 var.type = desc->type;
2dafc6c2
GN		 4992 var.dpl = desc->dpl;
4993 var.db = desc->d;
4994 var.s = desc->s;
4995 var.l = desc->l;
4996 var.g = desc->g;
4997 var.avl = desc->avl;
4998 var.present = desc->p;
4999 var.unusable = !var.present;
5000 var.padding = 0;
5001
5002 kvm_set_segment(vcpu, &var, seg);
5003 return;
5004}
5005
717746e3
AK		 5006static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5007 u32 msr_index, u64 *pdata)
5008{
609e36d3
PB		 5009 struct msr_data msr;
5010 int r;
5011
5012 msr.index = msr_index;
5013 msr.host_initiated = false;
5014 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5015 if (r)
5016 return r;
5017
5018 *pdata = msr.data;
5019 return 0;
717746e3
AK		 5020}
5021
5022static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5023 u32 msr_index, u64 data)
5024{
8fe8ab46
WA		 5025 struct msr_data msr;
5026
5027 msr.data = data;
5028 msr.index = msr_index;
5029 msr.host_initiated = false;
5030 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5031}
5032
64d60670
PB		 5033static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5034{
5035 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5036
5037 return vcpu->arch.smbase;
5038}
5039
5040static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5041{
5042 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5043
5044 vcpu->arch.smbase = smbase;
5045}
5046
67f4d428
NA		 5047static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5048 u32 pmc)
5049{
c6702c9d 5050 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5051}
5052
222d21aa
AK		 5053static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5054 u32 pmc, u64 *pdata)
5055{
c6702c9d 5056 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5057}
5058
6c3287f7
AK		 5059static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5060{
5061 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5062}
5063
5037f6f3
AK		 5064static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5065{
5066 preempt_disable();
5197b808 5067 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5068 /*
5069 * CR0.TS may reference the host fpu state, not the guest fpu state,
5070 * so it may be clear at this point.
5071 */
5072 clts();
5073}
5074
5075static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5076{
5077 preempt_enable();
5078}
5079
2953538e 5080static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5081 struct x86_instruction_info *info,
c4f035c6
AK		 5082 enum x86_intercept_stage stage)
5083{
2953538e 5084 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5085}
5086
0017f93a 5087static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5088 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5089{
0017f93a 5090 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5091}
5092
dd856efa
AK		 5093static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5094{
5095 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5096}
5097
5098static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5099{
5100 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5101}
5102
801806d9
NA		 5103static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5104{
5105 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5106}
5107
0225fb50 5108static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5109 .read_gpr = emulator_read_gpr,
5110 .write_gpr = emulator_write_gpr,
1871c602 5111 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5112 .write_std = kvm_write_guest_virt_system,
7a036a6f 5113 .read_phys = kvm_read_guest_phys_system,
1871c602 5114 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5115 .read_emulated = emulator_read_emulated,
5116 .write_emulated = emulator_write_emulated,
5117 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5118 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5119 .pio_in_emulated = emulator_pio_in_emulated,
5120 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5121 .get_segment = emulator_get_segment,
5122 .set_segment = emulator_set_segment,
5951c442 5123 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5124 .get_gdt = emulator_get_gdt,
160ce1f1 5125 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5126 .set_gdt = emulator_set_gdt,
5127 .set_idt = emulator_set_idt,
52a46617
GN		 5128 .get_cr = emulator_get_cr,
5129 .set_cr = emulator_set_cr,
9c537244 5130 .cpl = emulator_get_cpl,
35aa5375
GN		 5131 .get_dr = emulator_get_dr,
5132 .set_dr = emulator_set_dr,
64d60670
PB		 5133 .get_smbase = emulator_get_smbase,
5134 .set_smbase = emulator_set_smbase,
717746e3
AK		 5135 .set_msr = emulator_set_msr,
5136 .get_msr = emulator_get_msr,
67f4d428 5137 .check_pmc = emulator_check_pmc,
222d21aa 5138 .read_pmc = emulator_read_pmc,
6c3287f7 5139 .halt = emulator_halt,
bcaf5cc5 5140 .wbinvd = emulator_wbinvd,
d6aa1000 5141 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5142 .get_fpu = emulator_get_fpu,
5143 .put_fpu = emulator_put_fpu,
c4f035c6 5144 .intercept = emulator_intercept,
bdb42f5a 5145 .get_cpuid = emulator_get_cpuid,
801806d9 5146 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5147};
5148
95cb2295
GN		 5149static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5150{
37ccdcbe 5151 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5152 /*
5153 * an sti; sti; sequence only disable interrupts for the first
5154 * instruction. So, if the last instruction, be it emulated or
5155 * not, left the system with the INT_STI flag enabled, it
5156 * means that the last instruction is an sti. We should not
5157 * leave the flag on in this case. The same goes for mov ss
5158 */
37ccdcbe
PB		 5159 if (int_shadow & mask)
5160 mask = 0;
6addfc42 5161 if (unlikely(int_shadow || mask)) {
95cb2295 5162 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5163 if (!mask)
5164 kvm_make_request(KVM_REQ_EVENT, vcpu);
5165 }
95cb2295
GN		 5166}
5167
ef54bcfe 5168static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5169{
5170 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5171 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5172 return kvm_propagate_fault(vcpu, &ctxt->exception);
5173
5174 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5175 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5176 ctxt->exception.error_code);
54b8486f 5177 else
da9cb575 5178 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5179 return false;
54b8486f
GN		 5180}
5181
8ec4722d
MG		 5182static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5183{
adf52235 5184 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5185 int cs_db, cs_l;
5186
8ec4722d
MG		 5187 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5188
adf52235
TY		 5189 ctxt->eflags = kvm_get_rflags(vcpu);
5190 ctxt->eip = kvm_rip_read(vcpu);
5191 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5192 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5193 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5194 cs_db ? X86EMUL_MODE_PROT32 :
5195 X86EMUL_MODE_PROT16;
a584539b 5196 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5197 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5198 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5199 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5200
dd856efa 5201 init_decode_cache(ctxt);
7ae441ea 5202 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5203}
5204
71f9833b 5205int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5206{
9d74191a 5207 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5208 int ret;
5209
5210 init_emulate_ctxt(vcpu);
5211
9dac77fa
AK		 5212 ctxt->op_bytes = 2;
5213 ctxt->ad_bytes = 2;
5214 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5215 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5216
5217 if (ret != X86EMUL_CONTINUE)
5218 return EMULATE_FAIL;
5219
9dac77fa 5220 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5221 kvm_rip_write(vcpu, ctxt->eip);
5222 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5223
5224 if (irq == NMI_VECTOR)
7460fb4a 5225 vcpu->arch.nmi_pending = 0;
63995653
MG		 5226 else
5227 vcpu->arch.interrupt.pending = false;
5228
5229 return EMULATE_DONE;
5230}
5231EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5232
6d77dbfc
GN		 5233static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5234{
fc3a9157
JR		 5235 int r = EMULATE_DONE;
5236
6d77dbfc
GN		 5237 ++vcpu->stat.insn_emulation_fail;
5238 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5239 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5240 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5241 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5242 vcpu->run->internal.ndata = 0;
5243 r = EMULATE_FAIL;
5244 }
6d77dbfc 5245 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5246
5247 return r;
6d77dbfc
GN		 5248}
5249
93c05d3e 5250static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5251 bool write_fault_to_shadow_pgtable,
5252 int emulation_type)
a6f177ef 5253{
95b3cf69 5254 gpa_t gpa = cr2;
ba049e93 5255 kvm_pfn_t pfn;
a6f177ef 5256
991eebf9
GN		 5257 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5258 return false;
5259
95b3cf69
XG		 5260 if (!vcpu->arch.mmu.direct_map) {
5261 /*
5262 * Write permission should be allowed since only
5263 * write access need to be emulated.
5264 */
5265 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5266
95b3cf69
XG		 5267 /*
5268 * If the mapping is invalid in guest, let cpu retry
5269 * it to generate fault.
5270 */
5271 if (gpa == UNMAPPED_GVA)
5272 return true;
5273 }
a6f177ef 5274
8e3d9d06
XG		 5275 /*
5276 * Do not retry the unhandleable instruction if it faults on the
5277 * readonly host memory, otherwise it will goto a infinite loop:
5278 * retry instruction -> write #PF -> emulation fail -> retry
5279 * instruction -> ...
5280 */
5281 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5282
5283 /*
5284 * If the instruction failed on the error pfn, it can not be fixed,
5285 * report the error to userspace.
5286 */
5287 if (is_error_noslot_pfn(pfn))
5288 return false;
5289
5290 kvm_release_pfn_clean(pfn);
5291
5292 /* The instructions are well-emulated on direct mmu. */
5293 if (vcpu->arch.mmu.direct_map) {
5294 unsigned int indirect_shadow_pages;
5295
5296 spin_lock(&vcpu->kvm->mmu_lock);
5297 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5298 spin_unlock(&vcpu->kvm->mmu_lock);
5299
5300 if (indirect_shadow_pages)
5301 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5302
a6f177ef 5303 return true;
8e3d9d06 5304 }
a6f177ef 5305
95b3cf69
XG		 5306 /*
5307 * if emulation was due to access to shadowed page table
5308 * and it failed try to unshadow page and re-enter the
5309 * guest to let CPU execute the instruction.
5310 */
5311 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5312
5313 /*
5314 * If the access faults on its page table, it can not
5315 * be fixed by unprotecting shadow page and it should
5316 * be reported to userspace.
5317 */
5318 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5319}
5320
1cb3f3ae
XG		 5321static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5322 unsigned long cr2, int emulation_type)
5323{
5324 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5325 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5326
5327 last_retry_eip = vcpu->arch.last_retry_eip;
5328 last_retry_addr = vcpu->arch.last_retry_addr;
5329
5330 /*
5331 * If the emulation is caused by #PF and it is non-page_table
5332 * writing instruction, it means the VM-EXIT is caused by shadow
5333 * page protected, we can zap the shadow page and retry this
5334 * instruction directly.
5335 *
5336 * Note: if the guest uses a non-page-table modifying instruction
5337 * on the PDE that points to the instruction, then we will unmap
5338 * the instruction and go to an infinite loop. So, we cache the
5339 * last retried eip and the last fault address, if we meet the eip
5340 * and the address again, we can break out of the potential infinite
5341 * loop.
5342 */
5343 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5344
5345 if (!(emulation_type & EMULTYPE_RETRY))
5346 return false;
5347
5348 if (x86_page_table_writing_insn(ctxt))
5349 return false;
5350
5351 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5352 return false;
5353
5354 vcpu->arch.last_retry_eip = ctxt->eip;
5355 vcpu->arch.last_retry_addr = cr2;
5356
5357 if (!vcpu->arch.mmu.direct_map)
5358 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5359
22368028 5360 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5361
5362 return true;
5363}
5364
716d51ab
GN		 5365static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5366static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5367
64d60670 5368static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5369{
64d60670 5370 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5371 /* This is a good place to trace that we are exiting SMM. */
5372 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5373
c43203ca
PB		 5374 /* Process a latched INIT or SMI, if any. */
5375 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5376 }
699023e2
PB		 5377
5378 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5379}
5380
5381static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5382{
5383 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5384
a584539b 5385 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5386
5387 if (changed & HF_SMM_MASK)
5388 kvm_smm_changed(vcpu);
a584539b
PB		 5389}
5390
4a1e10d5
PB		 5391static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5392 unsigned long *db)
5393{
5394 u32 dr6 = 0;
5395 int i;
5396 u32 enable, rwlen;
5397
5398 enable = dr7;
5399 rwlen = dr7 >> 16;
5400 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5401 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5402 dr6 |= (1 << i);
5403 return dr6;
5404}
5405
6addfc42 5406static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5407{
5408 struct kvm_run *kvm_run = vcpu->run;
5409
5410 /*
6addfc42
PB		 5411 * rflags is the old, "raw" value of the flags. The new value has
5412 * not been saved yet.
663f4c61
PB		 5413 *
5414 * This is correct even for TF set by the guest, because "the
5415 * processor will not generate this exception after the instruction
5416 * that sets the TF flag".
5417 */
663f4c61
PB		 5418 if (unlikely(rflags & X86_EFLAGS_TF)) {
5419 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5420 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5421 DR6_RTM;
663f4c61
PB		 5422 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5423 kvm_run->debug.arch.exception = DB_VECTOR;
5424 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5425 *r = EMULATE_USER_EXIT;
5426 } else {
5427 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5428 /*
5429 * "Certain debug exceptions may clear bit 0-3. The
5430 * remaining contents of the DR6 register are never
5431 * cleared by the processor".
5432 */
5433 vcpu->arch.dr6 &= ~15;
6f43ed01 5434 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5435 kvm_queue_exception(vcpu, DB_VECTOR);
5436 }
5437 }
5438}
5439
4a1e10d5
PB		 5440static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5441{
4a1e10d5
PB		 5442 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5443 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5444 struct kvm_run *kvm_run = vcpu->run;
5445 unsigned long eip = kvm_get_linear_rip(vcpu);
5446 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5447 vcpu->arch.guest_debug_dr7,
5448 vcpu->arch.eff_db);
5449
5450 if (dr6 != 0) {
6f43ed01 5451 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5452 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5453 kvm_run->debug.arch.exception = DB_VECTOR;
5454 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5455 *r = EMULATE_USER_EXIT;
5456 return true;
5457 }
5458 }
5459
4161a569
NA		 5460 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5461 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5462 unsigned long eip = kvm_get_linear_rip(vcpu);
5463 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5464 vcpu->arch.dr7,
5465 vcpu->arch.db);
5466
5467 if (dr6 != 0) {
5468 vcpu->arch.dr6 &= ~15;
6f43ed01 5469 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5470 kvm_queue_exception(vcpu, DB_VECTOR);
5471 *r = EMULATE_DONE;
5472 return true;
5473 }
5474 }
5475
5476 return false;
5477}
5478
51d8b661
AP		 5479int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5480 unsigned long cr2,
dc25e89e
AP		 5481 int emulation_type,
5482 void *insn,
5483 int insn_len)
bbd9b64e 5484{
95cb2295 5485 int r;
9d74191a 5486 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5487 bool writeback = true;
93c05d3e 5488 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5489
93c05d3e
XG		 5490 /*
5491 * Clear write_fault_to_shadow_pgtable here to ensure it is
5492 * never reused.
5493 */
5494 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5495 kvm_clear_exception_queue(vcpu);
8d7d8102 5496
571008da 5497 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5498 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5499
5500 /*
5501 * We will reenter on the same instruction since
5502 * we do not set complete_userspace_io. This does not
5503 * handle watchpoints yet, those would be handled in
5504 * the emulate_ops.
5505 */
5506 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5507 return r;
5508
9d74191a
TY		 5509 ctxt->interruptibility = 0;
5510 ctxt->have_exception = false;
e0ad0b47 5511 ctxt->exception.vector = -1;
9d74191a 5512 ctxt->perm_ok = false;
bbd9b64e 5513
b51e974f 5514 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5515
9d74191a 5516 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5517
e46479f8 5518 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5519 ++vcpu->stat.insn_emulation;
1d2887e2 5520 if (r != EMULATION_OK) {
4005996e
AK		 5521 if (emulation_type & EMULTYPE_TRAP_UD)
5522 return EMULATE_FAIL;
991eebf9
GN		 5523 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5524 emulation_type))
bbd9b64e 5525 return EMULATE_DONE;
6d77dbfc
GN		 5526 if (emulation_type & EMULTYPE_SKIP)
5527 return EMULATE_FAIL;
5528 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5529 }
5530 }
5531
ba8afb6b 5532 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5533 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5534 if (ctxt->eflags & X86_EFLAGS_RF)
5535 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5536 return EMULATE_DONE;
5537 }
5538
1cb3f3ae
XG		 5539 if (retry_instruction(ctxt, cr2, emulation_type))
5540 return EMULATE_DONE;
5541
7ae441ea 5542 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5543 changes registers values during IO operation */
7ae441ea
GN		 5544 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5545 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5546 emulator_invalidate_register_cache(ctxt);
7ae441ea 5547 }
4d2179e1 5548
5cd21917 5549restart:
9d74191a 5550 r = x86_emulate_insn(ctxt);
bbd9b64e 5551
775fde86
JR		 5552 if (r == EMULATION_INTERCEPTED)
5553 return EMULATE_DONE;
5554
d2ddd1c4 5555 if (r == EMULATION_FAILED) {
991eebf9
GN		 5556 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5557 emulation_type))
c3cd7ffa
GN		 5558 return EMULATE_DONE;
5559
6d77dbfc 5560 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5561 }
5562
9d74191a 5563 if (ctxt->have_exception) {
d2ddd1c4 5564 r = EMULATE_DONE;
ef54bcfe
PB		 5565 if (inject_emulated_exception(vcpu))
5566 return r;
d2ddd1c4 5567 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5568 if (!vcpu->arch.pio.in) {
5569 /* FIXME: return into emulator if single-stepping. */
3457e419 5570 vcpu->arch.pio.count = 0;
0912c977 5571 } else {
7ae441ea 5572 writeback = false;
716d51ab
GN		 5573 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5574 }
ac0a48c3 5575 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5576 } else if (vcpu->mmio_needed) {
5577 if (!vcpu->mmio_is_write)
5578 writeback = false;
ac0a48c3 5579 r = EMULATE_USER_EXIT;
716d51ab 5580 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5581 } else if (r == EMULATION_RESTART)
5cd21917 5582 goto restart;
d2ddd1c4
GN		 5583 else
5584 r = EMULATE_DONE;
f850e2e6 5585
7ae441ea 5586 if (writeback) {
6addfc42 5587 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5588 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5589 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5590 if (vcpu->arch.hflags != ctxt->emul_flags)
5591 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5592 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5593 if (r == EMULATE_DONE)
6addfc42 5594 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5595 if (!ctxt->have_exception ||
5596 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5597 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5598
5599 /*
5600 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5601 * do nothing, and it will be requested again as soon as
5602 * the shadow expires. But we still need to check here,
5603 * because POPF has no interrupt shadow.
5604 */
5605 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5606 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5607 } else
5608 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5609
5610 return r;
de7d789a 5611}
51d8b661 5612EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5613
cf8f70bf 5614int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5615{
cf8f70bf 5616 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5617 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5618 size, port, &val, 1);
cf8f70bf 5619 /* do not return to emulator after return from userspace */
7972995b 5620 vcpu->arch.pio.count = 0;
de7d789a
CO		 5621 return ret;
5622}
cf8f70bf 5623EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5624
251a5fd6 5625static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5626{
0a3aee0d 5627 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5628 return 0;
8cfdc000
ZA		 5629}
5630
5631static void tsc_khz_changed(void *data)
c8076604 5632{
8cfdc000
ZA		 5633 struct cpufreq_freqs *freq = data;
5634 unsigned long khz = 0;
5635
5636 if (data)
5637 khz = freq->new;
5638 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5639 khz = cpufreq_quick_get(raw_smp_processor_id());
5640 if (!khz)
5641 khz = tsc_khz;
0a3aee0d 5642 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5643}
5644
c8076604
GH		 5645static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5646 void *data)
5647{
5648 struct cpufreq_freqs *freq = data;
5649 struct kvm *kvm;
5650 struct kvm_vcpu *vcpu;
5651 int i, send_ipi = 0;
5652
8cfdc000
ZA		 5653 /*
5654 * We allow guests to temporarily run on slowing clocks,
5655 * provided we notify them after, or to run on accelerating
5656 * clocks, provided we notify them before. Thus time never
5657 * goes backwards.
5658 *
5659 * However, we have a problem. We can't atomically update
5660 * the frequency of a given CPU from this function; it is
5661 * merely a notifier, which can be called from any CPU.
5662 * Changing the TSC frequency at arbitrary points in time
5663 * requires a recomputation of local variables related to
5664 * the TSC for each VCPU. We must flag these local variables
5665 * to be updated and be sure the update takes place with the
5666 * new frequency before any guests proceed.
5667 *
5668 * Unfortunately, the combination of hotplug CPU and frequency
5669 * change creates an intractable locking scenario; the order
5670 * of when these callouts happen is undefined with respect to
5671 * CPU hotplug, and they can race with each other. As such,
5672 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5673 * undefined; you can actually have a CPU frequency change take
5674 * place in between the computation of X and the setting of the
5675 * variable. To protect against this problem, all updates of
5676 * the per_cpu tsc_khz variable are done in an interrupt
5677 * protected IPI, and all callers wishing to update the value
5678 * must wait for a synchronous IPI to complete (which is trivial
5679 * if the caller is on the CPU already). This establishes the
5680 * necessary total order on variable updates.
5681 *
5682 * Note that because a guest time update may take place
5683 * anytime after the setting of the VCPU's request bit, the
5684 * correct TSC value must be set before the request. However,
5685 * to ensure the update actually makes it to any guest which
5686 * starts running in hardware virtualization between the set
5687 * and the acquisition of the spinlock, we must also ping the
5688 * CPU after setting the request bit.
5689 *
5690 */
5691
c8076604
GH		 5692 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5693 return 0;
5694 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5695 return 0;
8cfdc000
ZA		 5696
5697 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5698
2f303b74 5699 spin_lock(&kvm_lock);
c8076604 5700 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5701 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5702 if (vcpu->cpu != freq->cpu)
5703 continue;
c285545f 5704 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5705 if (vcpu->cpu != smp_processor_id())
8cfdc000 5706 send_ipi = 1;
c8076604
GH		 5707 }
5708 }
2f303b74 5709 spin_unlock(&kvm_lock);
c8076604
GH		 5710
5711 if (freq->old < freq->new && send_ipi) {
5712 /*
5713 * We upscale the frequency. Must make the guest
5714 * doesn't see old kvmclock values while running with
5715 * the new frequency, otherwise we risk the guest sees
5716 * time go backwards.
5717 *
5718 * In case we update the frequency for another cpu
5719 * (which might be in guest context) send an interrupt
5720 * to kick the cpu out of guest context. Next time
5721 * guest context is entered kvmclock will be updated,
5722 * so the guest will not see stale values.
5723 */
8cfdc000 5724 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5725 }
5726 return 0;
5727}
5728
5729static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5730 .notifier_call = kvmclock_cpufreq_notifier
5731};
5732
251a5fd6 5733static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5734{
251a5fd6
SAS		 5735 tsc_khz_changed(NULL);
5736 return 0;
8cfdc000
ZA		 5737}
5738
b820cc0c
ZA		 5739static void kvm_timer_init(void)
5740{
c285545f 5741 max_tsc_khz = tsc_khz;
460dd42e 5742
b820cc0c 5743 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5744#ifdef CONFIG_CPU_FREQ
5745 struct cpufreq_policy policy;
758f588d
BP		 5746 int cpu;
5747
c285545f 5748 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5749 cpu = get_cpu();
5750 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5751 if (policy.cpuinfo.max_freq)
5752 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5753 put_cpu();
c285545f 5754#endif
b820cc0c
ZA		 5755 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5756 CPUFREQ_TRANSITION_NOTIFIER);
5757 }
c285545f 5758 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5759
251a5fd6
SAS		 5760 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "AP_X86_KVM_CLK_ONLINE",
5761 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5762}
5763
ff9d07a0
ZY		 5764static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5765
f5132b01 5766int kvm_is_in_guest(void)
ff9d07a0 5767{
086c9855 5768 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5769}
5770
5771static int kvm_is_user_mode(void)
5772{
5773 int user_mode = 3;
dcf46b94 5774
086c9855
AS		 5775 if (__this_cpu_read(current_vcpu))
5776 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5777
ff9d07a0
ZY		 5778 return user_mode != 0;
5779}
5780
5781static unsigned long kvm_get_guest_ip(void)
5782{
5783 unsigned long ip = 0;
dcf46b94 5784
086c9855
AS		 5785 if (__this_cpu_read(current_vcpu))
5786 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5787
ff9d07a0
ZY		 5788 return ip;
5789}
5790
5791static struct perf_guest_info_callbacks kvm_guest_cbs = {
5792 .is_in_guest = kvm_is_in_guest,
5793 .is_user_mode = kvm_is_user_mode,
5794 .get_guest_ip = kvm_get_guest_ip,
5795};
5796
5797void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5798{
086c9855 5799 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5800}
5801EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5802
5803void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5804{
086c9855 5805 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5806}
5807EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5808
ce88decf
XG		 5809static void kvm_set_mmio_spte_mask(void)
5810{
5811 u64 mask;
5812 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5813
5814 /*
5815 * Set the reserved bits and the present bit of an paging-structure
5816 * entry to generate page fault with PFER.RSV = 1.
5817 */
885032b9 5818 /* Mask the reserved physical address bits. */
d1431483 5819 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5820
5821 /* Bit 62 is always reserved for 32bit host. */
5822 mask |= 0x3ull << 62;
5823
5824 /* Set the present bit. */
ce88decf
XG		 5825 mask |= 1ull;
5826
5827#ifdef CONFIG_X86_64
5828 /*
5829 * If reserved bit is not supported, clear the present bit to disable
5830 * mmio page fault.
5831 */
5832 if (maxphyaddr == 52)
5833 mask &= ~1ull;
5834#endif
5835
5836 kvm_mmu_set_mmio_spte_mask(mask);
5837}
5838
16e8d74d
MT		 5839#ifdef CONFIG_X86_64
5840static void pvclock_gtod_update_fn(struct work_struct *work)
5841{
d828199e
MT		 5842 struct kvm *kvm;
5843
5844 struct kvm_vcpu *vcpu;
5845 int i;
5846
2f303b74 5847 spin_lock(&kvm_lock);
d828199e
MT		 5848 list_for_each_entry(kvm, &vm_list, vm_list)
5849 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5850 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5851 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5852 spin_unlock(&kvm_lock);
16e8d74d
MT		 5853}
5854
5855static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5856
5857/*
5858 * Notification about pvclock gtod data update.
5859 */
5860static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5861 void *priv)
5862{
5863 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5864 struct timekeeper *tk = priv;
5865
5866 update_pvclock_gtod(tk);
5867
5868 /* disable master clock if host does not trust, or does not
5869 * use, TSC clocksource
5870 */
5871 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5872 atomic_read(&kvm_guest_has_master_clock) != 0)
5873 queue_work(system_long_wq, &pvclock_gtod_work);
5874
5875 return 0;
5876}
5877
5878static struct notifier_block pvclock_gtod_notifier = {
5879 .notifier_call = pvclock_gtod_notify,
5880};
5881#endif
5882
f8c16bba 5883int kvm_arch_init(void *opaque)
043405e1 5884{
b820cc0c 5885 int r;
6b61edf7 5886 struct kvm_x86_ops *ops = opaque;
f8c16bba 5887
f8c16bba
ZX		 5888 if (kvm_x86_ops) {
5889 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5890 r = -EEXIST;
5891 goto out;
f8c16bba
ZX		 5892 }
5893
5894 if (!ops->cpu_has_kvm_support()) {
5895 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5896 r = -EOPNOTSUPP;
5897 goto out;
f8c16bba
ZX		 5898 }
5899 if (ops->disabled_by_bios()) {
5900 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5901 r = -EOPNOTSUPP;
5902 goto out;
f8c16bba
ZX		 5903 }
5904
013f6a5d
MT		 5905 r = -ENOMEM;
5906 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5907 if (!shared_msrs) {
5908 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5909 goto out;
5910 }
5911
97db56ce
AK		 5912 r = kvm_mmu_module_init();
5913 if (r)
013f6a5d 5914 goto out_free_percpu;
97db56ce 5915
ce88decf 5916 kvm_set_mmio_spte_mask();
97db56ce 5917
f8c16bba 5918 kvm_x86_ops = ops;
920c8377 5919
7b52345e 5920 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8
BD		 5921 PT_DIRTY_MASK, PT64_NX_MASK, 0,
5922 PT_PRESENT_MASK);
b820cc0c 5923 kvm_timer_init();
c8076604 5924
ff9d07a0
ZY		 5925 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5926
d366bf7e 5927 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 5928 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5929
c5cc421b 5930 kvm_lapic_init();
16e8d74d
MT		 5931#ifdef CONFIG_X86_64
5932 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5933#endif
5934
f8c16bba 5935 return 0;
56c6d28a 5936
013f6a5d
MT		 5937out_free_percpu:
5938 free_percpu(shared_msrs);
56c6d28a 5939out:
56c6d28a 5940 return r;
043405e1 5941}
8776e519 5942
f8c16bba
ZX		 5943void kvm_arch_exit(void)
5944{
ff9d07a0
ZY		 5945 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5946
888d256e
JK		 5947 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5948 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5949 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 5950 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 5951#ifdef CONFIG_X86_64
5952 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5953#endif
f8c16bba 5954 kvm_x86_ops = NULL;
56c6d28a 5955 kvm_mmu_module_exit();
013f6a5d 5956 free_percpu(shared_msrs);
56c6d28a 5957}
f8c16bba 5958
5cb56059 5959int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5960{
5961 ++vcpu->stat.halt_exits;
35754c98 5962 if (lapic_in_kernel(vcpu)) {
a4535290 5963 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5964 return 1;
5965 } else {
5966 vcpu->run->exit_reason = KVM_EXIT_HLT;
5967 return 0;
5968 }
5969}
5cb56059
JS		 5970EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5971
5972int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5973{
5974 kvm_x86_ops->skip_emulated_instruction(vcpu);
5975 return kvm_vcpu_halt(vcpu);
5976}
8776e519
HB		 5977EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5978
6aef266c
SV		 5979/*
5980 * kvm_pv_kick_cpu_op: Kick a vcpu.
5981 *
5982 * @apicid - apicid of vcpu to be kicked.
5983 */
5984static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5985{
24d2166b 5986 struct kvm_lapic_irq lapic_irq;
6aef266c 5987
24d2166b
R		 5988 lapic_irq.shorthand = 0;
5989 lapic_irq.dest_mode = 0;
5990 lapic_irq.dest_id = apicid;
93bbf0b8 5991 lapic_irq.msi_redir_hint = false;
6aef266c 5992
24d2166b 5993 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5994 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5995}
5996
d62caabb
AS		 5997void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5998{
5999 vcpu->arch.apicv_active = false;
6000 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6001}
6002
8776e519
HB		 6003int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6004{
6005 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 6006 int op_64_bit, r = 1;
8776e519 6007
5cb56059
JS		 6008 kvm_x86_ops->skip_emulated_instruction(vcpu);
6009
55cd8e5a
GN		 6010 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6011 return kvm_hv_hypercall(vcpu);
6012
5fdbf976
MT		 6013 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6014 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6015 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6016 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6017 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6018
229456fc 6019 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6020
a449c7aa
NA		 6021 op_64_bit = is_64_bit_mode(vcpu);
6022 if (!op_64_bit) {
8776e519
HB		 6023 nr &= 0xFFFFFFFF;
6024 a0 &= 0xFFFFFFFF;
6025 a1 &= 0xFFFFFFFF;
6026 a2 &= 0xFFFFFFFF;
6027 a3 &= 0xFFFFFFFF;
6028 }
6029
07708c4a
JK		 6030 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6031 ret = -KVM_EPERM;
6032 goto out;
6033 }
6034
8776e519 6035 switch (nr) {
b93463aa
AK		 6036 case KVM_HC_VAPIC_POLL_IRQ:
6037 ret = 0;
6038 break;
6aef266c
SV		 6039 case KVM_HC_KICK_CPU:
6040 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6041 ret = 0;
6042 break;
8776e519
HB		 6043 default:
6044 ret = -KVM_ENOSYS;
6045 break;
6046 }
07708c4a 6047out:
a449c7aa
NA		 6048 if (!op_64_bit)
6049 ret = (u32)ret;
5fdbf976 6050 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6051 ++vcpu->stat.hypercalls;
2f333bcb 6052 return r;
8776e519
HB		 6053}
6054EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6055
b6785def 6056static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6057{
d6aa1000 6058 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6059 char instruction[3];
5fdbf976 6060 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6061
8776e519 6062 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6063
9d74191a 6064 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6065}
6066
851ba692 6067static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6068{
782d422b
MG		 6069 return vcpu->run->request_interrupt_window &&
6070 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6071}
6072
851ba692 6073static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6074{
851ba692
AK		 6075 struct kvm_run *kvm_run = vcpu->run;
6076
91586a3b 6077 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6078 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6079 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6080 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6081 kvm_run->ready_for_interrupt_injection =
6082 pic_in_kernel(vcpu->kvm) ||
782d422b 6083 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6084}
6085
95ba8273
GN		 6086static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6087{
6088 int max_irr, tpr;
6089
6090 if (!kvm_x86_ops->update_cr8_intercept)
6091 return;
6092
bce87cce 6093 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6094 return;
6095
d62caabb
AS		 6096 if (vcpu->arch.apicv_active)
6097 return;
6098
8db3baa2
GN		 6099 if (!vcpu->arch.apic->vapic_addr)
6100 max_irr = kvm_lapic_find_highest_irr(vcpu);
6101 else
6102 max_irr = -1;
95ba8273
GN		 6103
6104 if (max_irr != -1)
6105 max_irr >>= 4;
6106
6107 tpr = kvm_lapic_get_cr8(vcpu);
6108
6109 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6110}
6111
b6b8a145 6112static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6113{
b6b8a145
JK		 6114 int r;
6115
95ba8273 6116 /* try to reinject previous events if any */
b59bb7bd 6117 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6118 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6119 vcpu->arch.exception.has_error_code,
6120 vcpu->arch.exception.error_code);
d6e8c854
NA		 6121
6122 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6123 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6124 X86_EFLAGS_RF);
6125
6bdf0662
NA		 6126 if (vcpu->arch.exception.nr == DB_VECTOR &&
6127 (vcpu->arch.dr7 & DR7_GD)) {
6128 vcpu->arch.dr7 &= ~DR7_GD;
6129 kvm_update_dr7(vcpu);
6130 }
6131
b59bb7bd
GN		 6132 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6133 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6134 vcpu->arch.exception.error_code,
6135 vcpu->arch.exception.reinject);
b6b8a145 6136 return 0;
b59bb7bd
GN		 6137 }
6138
95ba8273
GN		 6139 if (vcpu->arch.nmi_injected) {
6140 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6141 return 0;
95ba8273
GN		 6142 }
6143
6144 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6145 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6146 return 0;
6147 }
6148
6149 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6150 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6151 if (r != 0)
6152 return r;
95ba8273
GN		 6153 }
6154
6155 /* try to inject new event if pending */
c43203ca
PB		 6156 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6157 vcpu->arch.smi_pending = false;
ee2cd4b7 6158 enter_smm(vcpu);
c43203ca 6159 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6160 --vcpu->arch.nmi_pending;
6161 vcpu->arch.nmi_injected = true;
6162 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6163 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6164 /*
6165 * Because interrupts can be injected asynchronously, we are
6166 * calling check_nested_events again here to avoid a race condition.
6167 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6168 * proposal and current concerns. Perhaps we should be setting
6169 * KVM_REQ_EVENT only on certain events and not unconditionally?
6170 */
6171 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6172 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6173 if (r != 0)
6174 return r;
6175 }
95ba8273 6176 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6177 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6178 false);
6179 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6180 }
6181 }
ee2cd4b7 6182
b6b8a145 6183 return 0;
95ba8273
GN		 6184}
6185
7460fb4a
AK		 6186static void process_nmi(struct kvm_vcpu *vcpu)
6187{
6188 unsigned limit = 2;
6189
6190 /*
6191 * x86 is limited to one NMI running, and one NMI pending after it.
6192 * If an NMI is already in progress, limit further NMIs to just one.
6193 * Otherwise, allow two (and we'll inject the first one immediately).
6194 */
6195 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6196 limit = 1;
6197
6198 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6199 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6200 kvm_make_request(KVM_REQ_EVENT, vcpu);
6201}
6202
660a5d51
PB		 6203#define put_smstate(type, buf, offset, val) \
6204 *(type *)((buf) + (offset) - 0x7e00) = val
6205
ee2cd4b7 6206static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6207{
6208 u32 flags = 0;
6209 flags |= seg->g << 23;
6210 flags |= seg->db << 22;
6211 flags |= seg->l << 21;
6212 flags |= seg->avl << 20;
6213 flags |= seg->present << 15;
6214 flags |= seg->dpl << 13;
6215 flags |= seg->s << 12;
6216 flags |= seg->type << 8;
6217 return flags;
6218}
6219
ee2cd4b7 6220static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6221{
6222 struct kvm_segment seg;
6223 int offset;
6224
6225 kvm_get_segment(vcpu, &seg, n);
6226 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6227
6228 if (n < 3)
6229 offset = 0x7f84 + n * 12;
6230 else
6231 offset = 0x7f2c + (n - 3) * 12;
6232
6233 put_smstate(u32, buf, offset + 8, seg.base);
6234 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6235 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6236}
6237
efbb288a 6238#ifdef CONFIG_X86_64
ee2cd4b7 6239static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6240{
6241 struct kvm_segment seg;
6242 int offset;
6243 u16 flags;
6244
6245 kvm_get_segment(vcpu, &seg, n);
6246 offset = 0x7e00 + n * 16;
6247
ee2cd4b7 6248 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6249 put_smstate(u16, buf, offset, seg.selector);
6250 put_smstate(u16, buf, offset + 2, flags);
6251 put_smstate(u32, buf, offset + 4, seg.limit);
6252 put_smstate(u64, buf, offset + 8, seg.base);
6253}
efbb288a 6254#endif
660a5d51 6255
ee2cd4b7 6256static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6257{
6258 struct desc_ptr dt;
6259 struct kvm_segment seg;
6260 unsigned long val;
6261 int i;
6262
6263 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6264 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6265 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6266 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6267
6268 for (i = 0; i < 8; i++)
6269 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6270
6271 kvm_get_dr(vcpu, 6, &val);
6272 put_smstate(u32, buf, 0x7fcc, (u32)val);
6273 kvm_get_dr(vcpu, 7, &val);
6274 put_smstate(u32, buf, 0x7fc8, (u32)val);
6275
6276 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6277 put_smstate(u32, buf, 0x7fc4, seg.selector);
6278 put_smstate(u32, buf, 0x7f64, seg.base);
6279 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6280 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6281
6282 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6283 put_smstate(u32, buf, 0x7fc0, seg.selector);
6284 put_smstate(u32, buf, 0x7f80, seg.base);
6285 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6286 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6287
6288 kvm_x86_ops->get_gdt(vcpu, &dt);
6289 put_smstate(u32, buf, 0x7f74, dt.address);
6290 put_smstate(u32, buf, 0x7f70, dt.size);
6291
6292 kvm_x86_ops->get_idt(vcpu, &dt);
6293 put_smstate(u32, buf, 0x7f58, dt.address);
6294 put_smstate(u32, buf, 0x7f54, dt.size);
6295
6296 for (i = 0; i < 6; i++)
ee2cd4b7 6297 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6298
6299 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6300
6301 /* revision id */
6302 put_smstate(u32, buf, 0x7efc, 0x00020000);
6303 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6304}
6305
ee2cd4b7 6306static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6307{
6308#ifdef CONFIG_X86_64
6309 struct desc_ptr dt;
6310 struct kvm_segment seg;
6311 unsigned long val;
6312 int i;
6313
6314 for (i = 0; i < 16; i++)
6315 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6316
6317 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6318 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6319
6320 kvm_get_dr(vcpu, 6, &val);
6321 put_smstate(u64, buf, 0x7f68, val);
6322 kvm_get_dr(vcpu, 7, &val);
6323 put_smstate(u64, buf, 0x7f60, val);
6324
6325 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6326 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6327 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6328
6329 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6330
6331 /* revision id */
6332 put_smstate(u32, buf, 0x7efc, 0x00020064);
6333
6334 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6335
6336 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6337 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6338 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6339 put_smstate(u32, buf, 0x7e94, seg.limit);
6340 put_smstate(u64, buf, 0x7e98, seg.base);
6341
6342 kvm_x86_ops->get_idt(vcpu, &dt);
6343 put_smstate(u32, buf, 0x7e84, dt.size);
6344 put_smstate(u64, buf, 0x7e88, dt.address);
6345
6346 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6347 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6348 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6349 put_smstate(u32, buf, 0x7e74, seg.limit);
6350 put_smstate(u64, buf, 0x7e78, seg.base);
6351
6352 kvm_x86_ops->get_gdt(vcpu, &dt);
6353 put_smstate(u32, buf, 0x7e64, dt.size);
6354 put_smstate(u64, buf, 0x7e68, dt.address);
6355
6356 for (i = 0; i < 6; i++)
ee2cd4b7 6357 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6358#else
6359 WARN_ON_ONCE(1);
6360#endif
6361}
6362
ee2cd4b7 6363static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6364{
660a5d51 6365 struct kvm_segment cs, ds;
18c3626e 6366 struct desc_ptr dt;
660a5d51
PB		 6367 char buf[512];
6368 u32 cr0;
6369
660a5d51
PB		 6370 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6371 vcpu->arch.hflags |= HF_SMM_MASK;
6372 memset(buf, 0, 512);
6373 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6374 enter_smm_save_state_64(vcpu, buf);
660a5d51 6375 else
ee2cd4b7 6376 enter_smm_save_state_32(vcpu, buf);
660a5d51 6377
54bf36aa 6378 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6379
6380 if (kvm_x86_ops->get_nmi_mask(vcpu))
6381 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6382 else
6383 kvm_x86_ops->set_nmi_mask(vcpu, true);
6384
6385 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6386 kvm_rip_write(vcpu, 0x8000);
6387
6388 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6389 kvm_x86_ops->set_cr0(vcpu, cr0);
6390 vcpu->arch.cr0 = cr0;
6391
6392 kvm_x86_ops->set_cr4(vcpu, 0);
6393
18c3626e
PB		 6394 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6395 dt.address = dt.size = 0;
6396 kvm_x86_ops->set_idt(vcpu, &dt);
6397
660a5d51
PB		 6398 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6399
6400 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6401 cs.base = vcpu->arch.smbase;
6402
6403 ds.selector = 0;
6404 ds.base = 0;
6405
6406 cs.limit = ds.limit = 0xffffffff;
6407 cs.type = ds.type = 0x3;
6408 cs.dpl = ds.dpl = 0;
6409 cs.db = ds.db = 0;
6410 cs.s = ds.s = 1;
6411 cs.l = ds.l = 0;
6412 cs.g = ds.g = 1;
6413 cs.avl = ds.avl = 0;
6414 cs.present = ds.present = 1;
6415 cs.unusable = ds.unusable = 0;
6416 cs.padding = ds.padding = 0;
6417
6418 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6419 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6420 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6421 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6422 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6423 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6424
6425 if (guest_cpuid_has_longmode(vcpu))
6426 kvm_x86_ops->set_efer(vcpu, 0);
6427
6428 kvm_update_cpuid(vcpu);
6429 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6430}
6431
ee2cd4b7 6432static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6433{
6434 vcpu->arch.smi_pending = true;
6435 kvm_make_request(KVM_REQ_EVENT, vcpu);
6436}
6437
2860c4b1
PB		 6438void kvm_make_scan_ioapic_request(struct kvm *kvm)
6439{
6440 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6441}
6442
3d81bc7e 6443static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6444{
5c919412
AS		 6445 u64 eoi_exit_bitmap[4];
6446
3d81bc7e
YZ		 6447 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6448 return;
c7c9c56c 6449
6308630b 6450 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6451
b053b2ae 6452 if (irqchip_split(vcpu->kvm))
6308630b 6453 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6454 else {
d62caabb
AS		 6455 if (vcpu->arch.apicv_active)
6456 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6457 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6458 }
5c919412
AS		 6459 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6460 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6461 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6462}
6463
a70656b6
RK		 6464static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6465{
6466 ++vcpu->stat.tlb_flush;
6467 kvm_x86_ops->tlb_flush(vcpu);
6468}
6469
4256f43f
TC		 6470void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6471{
c24ae0dc
TC		 6472 struct page *page = NULL;
6473
35754c98 6474 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6475 return;
6476
4256f43f
TC		 6477 if (!kvm_x86_ops->set_apic_access_page_addr)
6478 return;
6479
c24ae0dc 6480 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6481 if (is_error_page(page))
6482 return;
c24ae0dc
TC		 6483 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6484
6485 /*
6486 * Do not pin apic access page in memory, the MMU notifier
6487 * will call us again if it is migrated or swapped out.
6488 */
6489 put_page(page);
4256f43f
TC		 6490}
6491EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6492
fe71557a
TC		 6493void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6494 unsigned long address)
6495{
c24ae0dc
TC		 6496 /*
6497 * The physical address of apic access page is stored in the VMCS.
6498 * Update it when it becomes invalid.
6499 */
6500 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6501 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6502}
6503
9357d939 6504/*
362c698f 6505 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6506 * exiting to the userspace. Otherwise, the value will be returned to the
6507 * userspace.
6508 */
851ba692 6509static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6510{
6511 int r;
62a193ed
MG		 6512 bool req_int_win =
6513 dm_request_for_irq_injection(vcpu) &&
6514 kvm_cpu_accept_dm_intr(vcpu);
6515
730dca42 6516 bool req_immediate_exit = false;
b6c7a5dc 6517
3e007509 6518 if (vcpu->requests) {
a8eeb04a 6519 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6520 kvm_mmu_unload(vcpu);
a8eeb04a 6521 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6522 __kvm_migrate_timers(vcpu);
d828199e
MT		 6523 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6524 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6525 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6526 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6527 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6528 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6529 if (unlikely(r))
6530 goto out;
6531 }
a8eeb04a 6532 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6533 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6534 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6535 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6536 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6537 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6538 r = 0;
6539 goto out;
6540 }
a8eeb04a 6541 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6542 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6543 r = 0;
6544 goto out;
6545 }
a8eeb04a 6546 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6547 vcpu->fpu_active = 0;
6548 kvm_x86_ops->fpu_deactivate(vcpu);
6549 }
af585b92
GN		 6550 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6551 /* Page is swapped out. Do synthetic halt */
6552 vcpu->arch.apf.halted = true;
6553 r = 1;
6554 goto out;
6555 }
c9aaa895
GC		 6556 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6557 record_steal_time(vcpu);
64d60670
PB		 6558 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6559 process_smi(vcpu);
7460fb4a
AK		 6560 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6561 process_nmi(vcpu);
f5132b01 6562 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6563 kvm_pmu_handle_event(vcpu);
f5132b01 6564 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6565 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6566 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6567 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6568 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6569 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6570 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6571 vcpu->run->eoi.vector =
6572 vcpu->arch.pending_ioapic_eoi;
6573 r = 0;
6574 goto out;
6575 }
6576 }
3d81bc7e
YZ		 6577 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6578 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6579 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6580 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6581 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6582 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6583 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6584 r = 0;
6585 goto out;
6586 }
e516cebb
AS		 6587 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6588 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6589 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6590 r = 0;
6591 goto out;
6592 }
db397571
AS		 6593 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6594 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6595 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6596 r = 0;
6597 goto out;
6598 }
f3b138c5
AS		 6599
6600 /*
6601 * KVM_REQ_HV_STIMER has to be processed after
6602 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6603 * depend on the guest clock being up-to-date
6604 */
1f4b34f8
AS		 6605 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6606 kvm_hv_process_stimers(vcpu);
2f52d58c 6607 }
b93463aa 6608
bf9f6ac8
FW		 6609 /*
6610 * KVM_REQ_EVENT is not set when posted interrupts are set by
6611 * VT-d hardware, so we have to update RVI unconditionally.
6612 */
6613 if (kvm_lapic_enabled(vcpu)) {
6614 /*
6615 * Update architecture specific hints for APIC
6616 * virtual interrupt delivery.
6617 */
d62caabb 6618 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6619 kvm_x86_ops->hwapic_irr_update(vcpu,
6620 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6621 }
b93463aa 6622
b463a6f7 6623 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6624 kvm_apic_accept_events(vcpu);
6625 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6626 r = 1;
6627 goto out;
6628 }
6629
b6b8a145
JK		 6630 if (inject_pending_event(vcpu, req_int_win) != 0)
6631 req_immediate_exit = true;
321c5658 6632 else {
c43203ca
PB		 6633 /* Enable NMI/IRQ window open exits if needed.
6634 *
6635 * SMIs have two cases: 1) they can be nested, and
6636 * then there is nothing to do here because RSM will
6637 * cause a vmexit anyway; 2) or the SMI can be pending
6638 * because inject_pending_event has completed the
6639 * injection of an IRQ or NMI from the previous vmexit,
6640 * and then we request an immediate exit to inject the SMI.
6641 */
6642 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6643 req_immediate_exit = true;
321c5658
YS		 6644 if (vcpu->arch.nmi_pending)
6645 kvm_x86_ops->enable_nmi_window(vcpu);
6646 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6647 kvm_x86_ops->enable_irq_window(vcpu);
6648 }
b463a6f7
AK		 6649
6650 if (kvm_lapic_enabled(vcpu)) {
6651 update_cr8_intercept(vcpu);
6652 kvm_lapic_sync_to_vapic(vcpu);
6653 }
6654 }
6655
d8368af8
AK		 6656 r = kvm_mmu_reload(vcpu);
6657 if (unlikely(r)) {
d905c069 6658 goto cancel_injection;
d8368af8
AK		 6659 }
6660
b6c7a5dc
HB		 6661 preempt_disable();
6662
6663 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6664 if (vcpu->fpu_active)
6665 kvm_load_guest_fpu(vcpu);
6b7e2d09
XG		 6666 vcpu->mode = IN_GUEST_MODE;
6667
01b71917
MT		 6668 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6669
0f127d12
LT		 6670 /*
6671 * We should set ->mode before check ->requests,
6672 * Please see the comment in kvm_make_all_cpus_request.
6673 * This also orders the write to mode from any reads
6674 * to the page tables done while the VCPU is running.
6675 * Please see the comment in kvm_flush_remote_tlbs.
6b7e2d09 6676 */
01b71917 6677 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6678
d94e1dc9 6679 local_irq_disable();
32f88400 6680
6b7e2d09 6681 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6682 || need_resched() || signal_pending(current)) {
6b7e2d09 6683 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6684 smp_wmb();
6c142801
AK		 6685 local_irq_enable();
6686 preempt_enable();
01b71917 6687 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6688 r = 1;
d905c069 6689 goto cancel_injection;
6c142801
AK		 6690 }
6691
fc5b7f3b
DM		 6692 kvm_load_guest_xcr0(vcpu);
6693
c43203ca
PB		 6694 if (req_immediate_exit) {
6695 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6696 smp_send_reschedule(vcpu->cpu);
c43203ca 6697 }
d6185f20 6698
8b89fe1f
PB		 6699 trace_kvm_entry(vcpu->vcpu_id);
6700 wait_lapic_expire(vcpu);
6edaa530 6701 guest_enter_irqoff();
b6c7a5dc 6702
42dbaa5a 6703 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6704 set_debugreg(0, 7);
6705 set_debugreg(vcpu->arch.eff_db[0], 0);
6706 set_debugreg(vcpu->arch.eff_db[1], 1);
6707 set_debugreg(vcpu->arch.eff_db[2], 2);
6708 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6709 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6710 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6711 }
b6c7a5dc 6712
851ba692 6713 kvm_x86_ops->run(vcpu);
b6c7a5dc 6714
c77fb5fe
PB		 6715 /*
6716 * Do this here before restoring debug registers on the host. And
6717 * since we do this before handling the vmexit, a DR access vmexit
6718 * can (a) read the correct value of the debug registers, (b) set
6719 * KVM_DEBUGREG_WONT_EXIT again.
6720 */
6721 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6722 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6723 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6724 kvm_update_dr0123(vcpu);
6725 kvm_update_dr6(vcpu);
6726 kvm_update_dr7(vcpu);
6727 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6728 }
6729
24f1e32c
FW		 6730 /*
6731 * If the guest has used debug registers, at least dr7
6732 * will be disabled while returning to the host.
6733 * If we don't have active breakpoints in the host, we don't
6734 * care about the messed up debug address registers. But if
6735 * we have some of them active, restore the old state.
6736 */
59d8eb53 6737 if (hw_breakpoint_active())
24f1e32c 6738 hw_breakpoint_restore();
42dbaa5a 6739
4ba76538 6740 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6741
6b7e2d09 6742 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6743 smp_wmb();
a547c6db 6744
fc5b7f3b
DM		 6745 kvm_put_guest_xcr0(vcpu);
6746
a547c6db 6747 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6748
6749 ++vcpu->stat.exits;
6750
f2485b3e 6751 guest_exit_irqoff();
b6c7a5dc 6752
f2485b3e 6753 local_irq_enable();
b6c7a5dc
HB		 6754 preempt_enable();
6755
f656ce01 6756 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6757
b6c7a5dc
HB		 6758 /*
6759 * Profile KVM exit RIPs:
6760 */
6761 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6762 unsigned long rip = kvm_rip_read(vcpu);
6763 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6764 }
6765
cc578287
ZA		 6766 if (unlikely(vcpu->arch.tsc_always_catchup))
6767 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6768
5cfb1d5a
MT		 6769 if (vcpu->arch.apic_attention)
6770 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6771
851ba692 6772 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6773 return r;
6774
6775cancel_injection:
6776 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6777 if (unlikely(vcpu->arch.apic_attention))
6778 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6779out:
6780 return r;
6781}
b6c7a5dc 6782
362c698f
PB		 6783static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6784{
bf9f6ac8
FW		 6785 if (!kvm_arch_vcpu_runnable(vcpu) &&
6786 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6787 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6788 kvm_vcpu_block(vcpu);
6789 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6790
6791 if (kvm_x86_ops->post_block)
6792 kvm_x86_ops->post_block(vcpu);
6793
9c8fd1ba
PB		 6794 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6795 return 1;
6796 }
362c698f
PB		 6797
6798 kvm_apic_accept_events(vcpu);
6799 switch(vcpu->arch.mp_state) {
6800 case KVM_MP_STATE_HALTED:
6801 vcpu->arch.pv.pv_unhalted = false;
6802 vcpu->arch.mp_state =
6803 KVM_MP_STATE_RUNNABLE;
6804 case KVM_MP_STATE_RUNNABLE:
6805 vcpu->arch.apf.halted = false;
6806 break;
6807 case KVM_MP_STATE_INIT_RECEIVED:
6808 break;
6809 default:
6810 return -EINTR;
6811 break;
6812 }
6813 return 1;
6814}
09cec754 6815
5d9bc648
PB		 6816static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6817{
6818 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6819 !vcpu->arch.apf.halted);
6820}
6821
362c698f 6822static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6823{
6824 int r;
f656ce01 6825 struct kvm *kvm = vcpu->kvm;
d7690175 6826
f656ce01 6827 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6828
362c698f 6829 for (;;) {
58f800d5 6830 if (kvm_vcpu_running(vcpu)) {
851ba692 6831 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6832 } else {
362c698f 6833 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6834 }
6835
09cec754
GN		 6836 if (r <= 0)
6837 break;
6838
6839 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6840 if (kvm_cpu_has_pending_timer(vcpu))
6841 kvm_inject_pending_timer_irqs(vcpu);
6842
782d422b
MG		 6843 if (dm_request_for_irq_injection(vcpu) &&
6844 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6845 r = 0;
6846 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6847 ++vcpu->stat.request_irq_exits;
362c698f 6848 break;
09cec754 6849 }
af585b92
GN		 6850
6851 kvm_check_async_pf_completion(vcpu);
6852
09cec754
GN		 6853 if (signal_pending(current)) {
6854 r = -EINTR;
851ba692 6855 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6856 ++vcpu->stat.signal_exits;
362c698f 6857 break;
09cec754
GN		 6858 }
6859 if (need_resched()) {
f656ce01 6860 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6861 cond_resched();
f656ce01 6862 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6863 }
b6c7a5dc
HB		 6864 }
6865
f656ce01 6866 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6867
6868 return r;
6869}
6870
716d51ab
GN		 6871static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6872{
6873 int r;
6874 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6875 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6876 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6877 if (r != EMULATE_DONE)
6878 return 0;
6879 return 1;
6880}
6881
6882static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6883{
6884 BUG_ON(!vcpu->arch.pio.count);
6885
6886 return complete_emulated_io(vcpu);
6887}
6888
f78146b0
AK		 6889/*
6890 * Implements the following, as a state machine:
6891 *
6892 * read:
6893 * for each fragment
87da7e66
XG		 6894 * for each mmio piece in the fragment
6895 * write gpa, len
6896 * exit
6897 * copy data
f78146b0
AK		 6898 * execute insn
6899 *
6900 * write:
6901 * for each fragment
87da7e66
XG		 6902 * for each mmio piece in the fragment
6903 * write gpa, len
6904 * copy data
6905 * exit
f78146b0 6906 */
716d51ab 6907static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6908{
6909 struct kvm_run *run = vcpu->run;
f78146b0 6910 struct kvm_mmio_fragment *frag;
87da7e66 6911 unsigned len;
5287f194 6912
716d51ab 6913 BUG_ON(!vcpu->mmio_needed);
5287f194 6914
716d51ab 6915 /* Complete previous fragment */
87da7e66
XG		 6916 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6917 len = min(8u, frag->len);
716d51ab 6918 if (!vcpu->mmio_is_write)
87da7e66
XG		 6919 memcpy(frag->data, run->mmio.data, len);
6920
6921 if (frag->len <= 8) {
6922 /* Switch to the next fragment. */
6923 frag++;
6924 vcpu->mmio_cur_fragment++;
6925 } else {
6926 /* Go forward to the next mmio piece. */
6927 frag->data += len;
6928 frag->gpa += len;
6929 frag->len -= len;
6930 }
6931
a08d3b3b 6932 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6933 vcpu->mmio_needed = 0;
0912c977
PB		 6934
6935 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6936 if (vcpu->mmio_is_write)
716d51ab
GN		 6937 return 1;
6938 vcpu->mmio_read_completed = 1;
6939 return complete_emulated_io(vcpu);
6940 }
87da7e66 6941
716d51ab
GN		 6942 run->exit_reason = KVM_EXIT_MMIO;
6943 run->mmio.phys_addr = frag->gpa;
6944 if (vcpu->mmio_is_write)
87da7e66
XG		 6945 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6946 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6947 run->mmio.is_write = vcpu->mmio_is_write;
6948 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6949 return 0;
5287f194
AK		 6950}
6951
716d51ab 6952
b6c7a5dc
HB		 6953int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6954{
c5bedc68 6955 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6956 int r;
6957 sigset_t sigsaved;
6958
c4d72e2d 6959 fpu__activate_curr(fpu);
e5c30142 6960
ac9f6dc0
AK		 6961 if (vcpu->sigset_active)
6962 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6963
a4535290 6964 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6965 kvm_vcpu_block(vcpu);
66450a21 6966 kvm_apic_accept_events(vcpu);
d7690175 6967 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6968 r = -EAGAIN;
6969 goto out;
b6c7a5dc
HB		 6970 }
6971
b6c7a5dc 6972 /* re-sync apic's tpr */
35754c98 6973 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6974 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6975 r = -EINVAL;
6976 goto out;
6977 }
6978 }
b6c7a5dc 6979
716d51ab
GN		 6980 if (unlikely(vcpu->arch.complete_userspace_io)) {
6981 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6982 vcpu->arch.complete_userspace_io = NULL;
6983 r = cui(vcpu);
6984 if (r <= 0)
6985 goto out;
6986 } else
6987 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6988
362c698f 6989 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6990
6991out:
f1d86e46 6992 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6993 if (vcpu->sigset_active)
6994 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6995
b6c7a5dc
HB		 6996 return r;
6997}
6998
6999int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7000{
7ae441ea
GN		 7001 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7002 /*
7003 * We are here if userspace calls get_regs() in the middle of
7004 * instruction emulation. Registers state needs to be copied
4a969980 7005 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7006 * that usually, but some bad designed PV devices (vmware
7007 * backdoor interface) need this to work
7008 */
dd856efa 7009 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7010 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7011 }
5fdbf976
MT		 7012 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7013 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7014 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7015 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7016 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7017 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7018 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7019 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7020#ifdef CONFIG_X86_64
5fdbf976
MT		 7021 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7022 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7023 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7024 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7025 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7026 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7027 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7028 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7029#endif
7030
5fdbf976 7031 regs->rip = kvm_rip_read(vcpu);
91586a3b 7032 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7033
b6c7a5dc
HB		 7034 return 0;
7035}
7036
7037int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7038{
7ae441ea
GN		 7039 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7040 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7041
5fdbf976
MT		 7042 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7043 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7044 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7045 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7046 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7047 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7048 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7049 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7050#ifdef CONFIG_X86_64
5fdbf976
MT		 7051 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7052 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7053 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7054 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7055 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7056 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7057 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7058 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7059#endif
7060
5fdbf976 7061 kvm_rip_write(vcpu, regs->rip);
91586a3b 7062 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7063
b4f14abd
JK		 7064 vcpu->arch.exception.pending = false;
7065
3842d135
AK		 7066 kvm_make_request(KVM_REQ_EVENT, vcpu);
7067
b6c7a5dc
HB		 7068 return 0;
7069}
7070
b6c7a5dc
HB		 7071void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7072{
7073 struct kvm_segment cs;
7074
3e6e0aab 7075 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7076 *db = cs.db;
7077 *l = cs.l;
7078}
7079EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7080
7081int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7082 struct kvm_sregs *sregs)
7083{
89a27f4d 7084 struct desc_ptr dt;
b6c7a5dc 7085
3e6e0aab
GT		 7086 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7087 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7088 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7089 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7090 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7091 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7092
3e6e0aab
GT		 7093 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7094 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7095
7096 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7097 sregs->idt.limit = dt.size;
7098 sregs->idt.base = dt.address;
b6c7a5dc 7099 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7100 sregs->gdt.limit = dt.size;
7101 sregs->gdt.base = dt.address;
b6c7a5dc 7102
4d4ec087 7103 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7104 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7105 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7106 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7107 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7108 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7109 sregs->apic_base = kvm_get_apic_base(vcpu);
7110
923c61bb 7111 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7112
36752c9b 7113 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7114 set_bit(vcpu->arch.interrupt.nr,
7115 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7116
b6c7a5dc
HB		 7117 return 0;
7118}
7119
62d9f0db
MT		 7120int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7121 struct kvm_mp_state *mp_state)
7122{
66450a21 7123 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7124 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7125 vcpu->arch.pv.pv_unhalted)
7126 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7127 else
7128 mp_state->mp_state = vcpu->arch.mp_state;
7129
62d9f0db
MT		 7130 return 0;
7131}
7132
7133int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7134 struct kvm_mp_state *mp_state)
7135{
bce87cce 7136 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7137 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7138 return -EINVAL;
7139
7140 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7141 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7142 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7143 } else
7144 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7145 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7146 return 0;
7147}
7148
7f3d35fd
KW		 7149int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7150 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7151{
9d74191a 7152 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7153 int ret;
e01c2426 7154
8ec4722d 7155 init_emulate_ctxt(vcpu);
c697518a 7156
7f3d35fd 7157 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7158 has_error_code, error_code);
c697518a 7159
c697518a 7160 if (ret)
19d04437 7161 return EMULATE_FAIL;
37817f29 7162
9d74191a
TY		 7163 kvm_rip_write(vcpu, ctxt->eip);
7164 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7165 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7166 return EMULATE_DONE;
37817f29
IE		 7167}
7168EXPORT_SYMBOL_GPL(kvm_task_switch);
7169
b6c7a5dc
HB		 7170int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7171 struct kvm_sregs *sregs)
7172{
58cb628d 7173 struct msr_data apic_base_msr;
b6c7a5dc 7174 int mmu_reset_needed = 0;
63f42e02 7175 int pending_vec, max_bits, idx;
89a27f4d 7176 struct desc_ptr dt;
b6c7a5dc 7177
6d1068b3
PM		 7178 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7179 return -EINVAL;
7180
89a27f4d
GN		 7181 dt.size = sregs->idt.limit;
7182 dt.address = sregs->idt.base;
b6c7a5dc 7183 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7184 dt.size = sregs->gdt.limit;
7185 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7186 kvm_x86_ops->set_gdt(vcpu, &dt);
7187
ad312c7c 7188 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7189 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7190 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7191 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7192
2d3ad1f4 7193 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7194
f6801dff 7195 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7196 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7197 apic_base_msr.data = sregs->apic_base;
7198 apic_base_msr.host_initiated = true;
7199 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7200
4d4ec087 7201 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7202 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7203 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7204
fc78f519 7205 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7206 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7207 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7208 kvm_update_cpuid(vcpu);
63f42e02
XG		 7209
7210 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7211 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7212 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7213 mmu_reset_needed = 1;
7214 }
63f42e02 7215 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7216
7217 if (mmu_reset_needed)
7218 kvm_mmu_reset_context(vcpu);
7219
a50abc3b 7220 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7221 pending_vec = find_first_bit(
7222 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7223 if (pending_vec < max_bits) {
66fd3f7f 7224 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7225 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7226 }
7227
3e6e0aab
GT		 7228 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7229 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7230 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7231 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7232 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7233 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7234
3e6e0aab
GT		 7235 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7236 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7237
5f0269f5
ME		 7238 update_cr8_intercept(vcpu);
7239
9c3e4aab 7240 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7241 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7242 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7243 !is_protmode(vcpu))
9c3e4aab
MT		 7244 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7245
3842d135
AK		 7246 kvm_make_request(KVM_REQ_EVENT, vcpu);
7247
b6c7a5dc
HB		 7248 return 0;
7249}
7250
d0bfb940
JK		 7251int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7252 struct kvm_guest_debug *dbg)
b6c7a5dc 7253{
355be0b9 7254 unsigned long rflags;
ae675ef0 7255 int i, r;
b6c7a5dc 7256
4f926bf2
JK		 7257 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7258 r = -EBUSY;
7259 if (vcpu->arch.exception.pending)
2122ff5e 7260 goto out;
4f926bf2
JK		 7261 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7262 kvm_queue_exception(vcpu, DB_VECTOR);
7263 else
7264 kvm_queue_exception(vcpu, BP_VECTOR);
7265 }
7266
91586a3b
JK		 7267 /*
7268 * Read rflags as long as potentially injected trace flags are still
7269 * filtered out.
7270 */
7271 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7272
7273 vcpu->guest_debug = dbg->control;
7274 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7275 vcpu->guest_debug = 0;
7276
7277 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7278 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7279 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7280 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7281 } else {
7282 for (i = 0; i < KVM_NR_DB_REGS; i++)
7283 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7284 }
c8639010 7285 kvm_update_dr7(vcpu);
ae675ef0 7286
f92653ee
JK		 7287 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7288 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7289 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7290
91586a3b
JK		 7291 /*
7292 * Trigger an rflags update that will inject or remove the trace
7293 * flags.
7294 */
7295 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7296
a96036b8 7297 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7298
4f926bf2 7299 r = 0;
d0bfb940 7300
2122ff5e 7301out:
b6c7a5dc
HB		 7302
7303 return r;
7304}
7305
8b006791
ZX		 7306/*
7307 * Translate a guest virtual address to a guest physical address.
7308 */
7309int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7310 struct kvm_translation *tr)
7311{
7312 unsigned long vaddr = tr->linear_address;
7313 gpa_t gpa;
f656ce01 7314 int idx;
8b006791 7315
f656ce01 7316 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7317 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7318 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7319 tr->physical_address = gpa;
7320 tr->valid = gpa != UNMAPPED_GVA;
7321 tr->writeable = 1;
7322 tr->usermode = 0;
8b006791
ZX		 7323
7324 return 0;
7325}
7326
d0752060
HB		 7327int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7328{
c47ada30 7329 struct fxregs_state *fxsave =
7366ed77 7330 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7331
d0752060
HB		 7332 memcpy(fpu->fpr, fxsave->st_space, 128);
7333 fpu->fcw = fxsave->cwd;
7334 fpu->fsw = fxsave->swd;
7335 fpu->ftwx = fxsave->twd;
7336 fpu->last_opcode = fxsave->fop;
7337 fpu->last_ip = fxsave->rip;
7338 fpu->last_dp = fxsave->rdp;
7339 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7340
d0752060
HB		 7341 return 0;
7342}
7343
7344int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7345{
c47ada30 7346 struct fxregs_state *fxsave =
7366ed77 7347 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7348
d0752060
HB		 7349 memcpy(fxsave->st_space, fpu->fpr, 128);
7350 fxsave->cwd = fpu->fcw;
7351 fxsave->swd = fpu->fsw;
7352 fxsave->twd = fpu->ftwx;
7353 fxsave->fop = fpu->last_opcode;
7354 fxsave->rip = fpu->last_ip;
7355 fxsave->rdp = fpu->last_dp;
7356 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7357
d0752060
HB		 7358 return 0;
7359}
7360
0ee6a517 7361static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7362{
bf935b0b 7363 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7364 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7365 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7366 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7367
2acf923e
DC		 7368 /*
7369 * Ensure guest xcr0 is valid for loading
7370 */
d91cab78 7371 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7372
ad312c7c 7373 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7374}
d0752060
HB		 7375
7376void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7377{
2608d7a1 7378 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7379 return;
7380
2acf923e
DC		 7381 /*
7382 * Restore all possible states in the guest,
7383 * and assume host would use all available bits.
7384 * Guest xcr0 would be loaded later.
7385 */
d0752060 7386 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7387 __kernel_fpu_begin();
003e2e8b 7388 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7389 trace_kvm_fpu(1);
d0752060 7390}
d0752060
HB		 7391
7392void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7393{
653f52c3
RR		 7394 if (!vcpu->guest_fpu_loaded) {
7395 vcpu->fpu_counter = 0;
d0752060 7396 return;
653f52c3 7397 }
d0752060
HB		 7398
7399 vcpu->guest_fpu_loaded = 0;
4f836347 7400 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7401 __kernel_fpu_end();
f096ed85 7402 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7403 /*
7404 * If using eager FPU mode, or if the guest is a frequent user
7405 * of the FPU, just leave the FPU active for next time.
7406 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7407 * the FPU in bursts will revert to loading it on demand.
7408 */
5a5fbdc0 7409 if (!use_eager_fpu()) {
653f52c3
RR		 7410 if (++vcpu->fpu_counter < 5)
7411 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7412 }
0c04851c 7413 trace_kvm_fpu(0);
d0752060 7414}
e9b11c17
ZX		 7415
7416void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7417{
bd768e14
IY		 7418 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7419
12f9a48f 7420 kvmclock_reset(vcpu);
7f1ea208 7421
e9b11c17 7422 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7423 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7424}
7425
7426struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7427 unsigned int id)
7428{
c447e76b
LL		 7429 struct kvm_vcpu *vcpu;
7430
6755bae8
ZA		 7431 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7432 printk_once(KERN_WARNING
7433 "kvm: SMP vm created on host with unstable TSC; "
7434 "guest TSC will not be reliable\n");
c447e76b
LL		 7435
7436 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7437
c447e76b 7438 return vcpu;
26e5215f 7439}
e9b11c17 7440
26e5215f
AK		 7441int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7442{
7443 int r;
e9b11c17 7444
19efffa2 7445 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7446 r = vcpu_load(vcpu);
7447 if (r)
7448 return r;
d28bc9dd 7449 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7450 kvm_mmu_setup(vcpu);
e9b11c17 7451 vcpu_put(vcpu);
26e5215f 7452 return r;
e9b11c17
ZX		 7453}
7454
31928aa5 7455void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7456{
8fe8ab46 7457 struct msr_data msr;
332967a3 7458 struct kvm *kvm = vcpu->kvm;
42897d86 7459
31928aa5
DD		 7460 if (vcpu_load(vcpu))
7461 return;
8fe8ab46
WA		 7462 msr.data = 0x0;
7463 msr.index = MSR_IA32_TSC;
7464 msr.host_initiated = true;
7465 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7466 vcpu_put(vcpu);
7467
630994b3
MT		 7468 if (!kvmclock_periodic_sync)
7469 return;
7470
332967a3
AJ		 7471 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7472 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7473}
7474
d40ccc62 7475void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7476{
9fc77441 7477 int r;
344d9588
GN		 7478 vcpu->arch.apf.msr_val = 0;
7479
9fc77441
MT		 7480 r = vcpu_load(vcpu);
7481 BUG_ON(r);
e9b11c17
ZX		 7482 kvm_mmu_unload(vcpu);
7483 vcpu_put(vcpu);
7484
7485 kvm_x86_ops->vcpu_free(vcpu);
7486}
7487
d28bc9dd 7488void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7489{
e69fab5d
PB		 7490 vcpu->arch.hflags = 0;
7491
c43203ca 7492 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7493 atomic_set(&vcpu->arch.nmi_queued, 0);
7494 vcpu->arch.nmi_pending = 0;
448fa4a9 7495 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7496 kvm_clear_interrupt_queue(vcpu);
7497 kvm_clear_exception_queue(vcpu);
448fa4a9 7498
42dbaa5a 7499 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7500 kvm_update_dr0123(vcpu);
6f43ed01 7501 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7502 kvm_update_dr6(vcpu);
42dbaa5a 7503 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7504 kvm_update_dr7(vcpu);
42dbaa5a 7505
1119022c
NA		 7506 vcpu->arch.cr2 = 0;
7507
3842d135 7508 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7509 vcpu->arch.apf.msr_val = 0;
c9aaa895 7510 vcpu->arch.st.msr_val = 0;
3842d135 7511
12f9a48f
GC		 7512 kvmclock_reset(vcpu);
7513
af585b92
GN		 7514 kvm_clear_async_pf_completion_queue(vcpu);
7515 kvm_async_pf_hash_reset(vcpu);
7516 vcpu->arch.apf.halted = false;
3842d135 7517
64d60670 7518 if (!init_event) {
d28bc9dd 7519 kvm_pmu_reset(vcpu);
64d60670
PB		 7520 vcpu->arch.smbase = 0x30000;
7521 }
f5132b01 7522
66f7b72e
JS		 7523 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7524 vcpu->arch.regs_avail = ~0;
7525 vcpu->arch.regs_dirty = ~0;
7526
d28bc9dd 7527 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7528}
7529
2b4a273b 7530void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7531{
7532 struct kvm_segment cs;
7533
7534 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7535 cs.selector = vector << 8;
7536 cs.base = vector << 12;
7537 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7538 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7539}
7540
13a34e06 7541int kvm_arch_hardware_enable(void)
e9b11c17 7542{
ca84d1a2
ZA		 7543 struct kvm *kvm;
7544 struct kvm_vcpu *vcpu;
7545 int i;
0dd6a6ed
ZA		 7546 int ret;
7547 u64 local_tsc;
7548 u64 max_tsc = 0;
7549 bool stable, backwards_tsc = false;
18863bdd
AK		 7550
7551 kvm_shared_msr_cpu_online();
13a34e06 7552 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7553 if (ret != 0)
7554 return ret;
7555
4ea1636b 7556 local_tsc = rdtsc();
0dd6a6ed
ZA		 7557 stable = !check_tsc_unstable();
7558 list_for_each_entry(kvm, &vm_list, vm_list) {
7559 kvm_for_each_vcpu(i, vcpu, kvm) {
7560 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7561 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7562 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7563 backwards_tsc = true;
7564 if (vcpu->arch.last_host_tsc > max_tsc)
7565 max_tsc = vcpu->arch.last_host_tsc;
7566 }
7567 }
7568 }
7569
7570 /*
7571 * Sometimes, even reliable TSCs go backwards. This happens on
7572 * platforms that reset TSC during suspend or hibernate actions, but
7573 * maintain synchronization. We must compensate. Fortunately, we can
7574 * detect that condition here, which happens early in CPU bringup,
7575 * before any KVM threads can be running. Unfortunately, we can't
7576 * bring the TSCs fully up to date with real time, as we aren't yet far
7577 * enough into CPU bringup that we know how much real time has actually
108b249c 7578 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7579 * variables that haven't been updated yet.
7580 *
7581 * So we simply find the maximum observed TSC above, then record the
7582 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7583 * the adjustment will be applied. Note that we accumulate
7584 * adjustments, in case multiple suspend cycles happen before some VCPU
7585 * gets a chance to run again. In the event that no KVM threads get a
7586 * chance to run, we will miss the entire elapsed period, as we'll have
7587 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7588 * loose cycle time. This isn't too big a deal, since the loss will be
7589 * uniform across all VCPUs (not to mention the scenario is extremely
7590 * unlikely). It is possible that a second hibernate recovery happens
7591 * much faster than a first, causing the observed TSC here to be
7592 * smaller; this would require additional padding adjustment, which is
7593 * why we set last_host_tsc to the local tsc observed here.
7594 *
7595 * N.B. - this code below runs only on platforms with reliable TSC,
7596 * as that is the only way backwards_tsc is set above. Also note
7597 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7598 * have the same delta_cyc adjustment applied if backwards_tsc
7599 * is detected. Note further, this adjustment is only done once,
7600 * as we reset last_host_tsc on all VCPUs to stop this from being
7601 * called multiple times (one for each physical CPU bringup).
7602 *
4a969980 7603 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7604 * will be compensated by the logic in vcpu_load, which sets the TSC to
7605 * catchup mode. This will catchup all VCPUs to real time, but cannot
7606 * guarantee that they stay in perfect synchronization.
7607 */
7608 if (backwards_tsc) {
7609 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7610 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7611 list_for_each_entry(kvm, &vm_list, vm_list) {
7612 kvm_for_each_vcpu(i, vcpu, kvm) {
7613 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7614 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7615 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7616 }
7617
7618 /*
7619 * We have to disable TSC offset matching.. if you were
7620 * booting a VM while issuing an S4 host suspend....
7621 * you may have some problem. Solving this issue is
7622 * left as an exercise to the reader.
7623 */
7624 kvm->arch.last_tsc_nsec = 0;
7625 kvm->arch.last_tsc_write = 0;
7626 }
7627
7628 }
7629 return 0;
e9b11c17
ZX		 7630}
7631
13a34e06 7632void kvm_arch_hardware_disable(void)
e9b11c17 7633{
13a34e06
RK		 7634 kvm_x86_ops->hardware_disable();
7635 drop_user_return_notifiers();
e9b11c17
ZX		 7636}
7637
7638int kvm_arch_hardware_setup(void)
7639{
9e9c3fe4
NA		 7640 int r;
7641
7642 r = kvm_x86_ops->hardware_setup();
7643 if (r != 0)
7644 return r;
7645
35181e86
HZ		 7646 if (kvm_has_tsc_control) {
7647 /*
7648 * Make sure the user can only configure tsc_khz values that
7649 * fit into a signed integer.
7650 * A min value is not calculated needed because it will always
7651 * be 1 on all machines.
7652 */
7653 u64 max = min(0x7fffffffULL,
7654 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7655 kvm_max_guest_tsc_khz = max;
7656
ad721883 7657 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7658 }
ad721883 7659
9e9c3fe4
NA		 7660 kvm_init_msr_list();
7661 return 0;
e9b11c17
ZX		 7662}
7663
7664void kvm_arch_hardware_unsetup(void)
7665{
7666 kvm_x86_ops->hardware_unsetup();
7667}
7668
7669void kvm_arch_check_processor_compat(void *rtn)
7670{
7671 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7672}
7673
7674bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7675{
7676 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7677}
7678EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7679
7680bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7681{
7682 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7683}
7684
54e9818f 7685struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7686EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7687
e9b11c17
ZX		 7688int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7689{
7690 struct page *page;
7691 struct kvm *kvm;
7692 int r;
7693
7694 BUG_ON(vcpu->kvm == NULL);
7695 kvm = vcpu->kvm;
7696
d62caabb 7697 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7698 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7699 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7700 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7701 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7702 else
a4535290 7703 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7704
7705 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7706 if (!page) {
7707 r = -ENOMEM;
7708 goto fail;
7709 }
ad312c7c 7710 vcpu->arch.pio_data = page_address(page);
e9b11c17 7711
cc578287 7712 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7713
e9b11c17
ZX		 7714 r = kvm_mmu_create(vcpu);
7715 if (r < 0)
7716 goto fail_free_pio_data;
7717
7718 if (irqchip_in_kernel(kvm)) {
7719 r = kvm_create_lapic(vcpu);
7720 if (r < 0)
7721 goto fail_mmu_destroy;
54e9818f
GN		 7722 } else
7723 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7724
890ca9ae
HY		 7725 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7726 GFP_KERNEL);
7727 if (!vcpu->arch.mce_banks) {
7728 r = -ENOMEM;
443c39bc 7729 goto fail_free_lapic;
890ca9ae
HY		 7730 }
7731 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7732
f1797359
WY		 7733 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7734 r = -ENOMEM;
f5f48ee1 7735 goto fail_free_mce_banks;
f1797359 7736 }
f5f48ee1 7737
0ee6a517 7738 fx_init(vcpu);
66f7b72e 7739
ba904635 7740 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7741 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7742
7743 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7744 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7745
5a4f55cd
EK		 7746 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7747
74545705
RK		 7748 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7749
af585b92 7750 kvm_async_pf_hash_reset(vcpu);
f5132b01 7751 kvm_pmu_init(vcpu);
af585b92 7752
1c1a9ce9
SR		 7753 vcpu->arch.pending_external_vector = -1;
7754
5c919412
AS		 7755 kvm_hv_vcpu_init(vcpu);
7756
e9b11c17 7757 return 0;
0ee6a517 7758
f5f48ee1
SY		 7759fail_free_mce_banks:
7760 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7761fail_free_lapic:
7762 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7763fail_mmu_destroy:
7764 kvm_mmu_destroy(vcpu);
7765fail_free_pio_data:
ad312c7c 7766 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7767fail:
7768 return r;
7769}
7770
7771void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7772{
f656ce01
MT		 7773 int idx;
7774
1f4b34f8 7775 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7776 kvm_pmu_destroy(vcpu);
36cb93fd 7777 kfree(vcpu->arch.mce_banks);
e9b11c17 7778 kvm_free_lapic(vcpu);
f656ce01 7779 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7780 kvm_mmu_destroy(vcpu);
f656ce01 7781 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7782 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7783 if (!lapic_in_kernel(vcpu))
54e9818f 7784 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7785}
d19a9cd2 7786
e790d9ef
RK		 7787void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7788{
ae97a3b8 7789 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7790}
7791
e08b9637 7792int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7793{
e08b9637
CO		 7794 if (type)
7795 return -EINVAL;
7796
6ef768fa 7797 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7798 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7799 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7800 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7801 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7802
5550af4d
SY		 7803 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7804 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7805 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7806 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7807 &kvm->arch.irq_sources_bitmap);
5550af4d 7808
038f8c11 7809 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7810 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7811 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7812
108b249c 7813 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 7814 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7815
7e44e449 7816 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7817 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7818
0eb05bf2 7819 kvm_page_track_init(kvm);
13d268ca 7820 kvm_mmu_init_vm(kvm);
0eb05bf2 7821
03543133
SS		 7822 if (kvm_x86_ops->vm_init)
7823 return kvm_x86_ops->vm_init(kvm);
7824
d89f5eff 7825 return 0;
d19a9cd2
ZX		 7826}
7827
7828static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7829{
9fc77441
MT		 7830 int r;
7831 r = vcpu_load(vcpu);
7832 BUG_ON(r);
d19a9cd2
ZX		 7833 kvm_mmu_unload(vcpu);
7834 vcpu_put(vcpu);
7835}
7836
7837static void kvm_free_vcpus(struct kvm *kvm)
7838{
7839 unsigned int i;
988a2cae 7840 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7841
7842 /*
7843 * Unpin any mmu pages first.
7844 */
af585b92
GN		 7845 kvm_for_each_vcpu(i, vcpu, kvm) {
7846 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7847 kvm_unload_vcpu_mmu(vcpu);
af585b92 7848 }
988a2cae
GN		 7849 kvm_for_each_vcpu(i, vcpu, kvm)
7850 kvm_arch_vcpu_free(vcpu);
7851
7852 mutex_lock(&kvm->lock);
7853 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7854 kvm->vcpus[i] = NULL;
d19a9cd2 7855
988a2cae
GN		 7856 atomic_set(&kvm->online_vcpus, 0);
7857 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7858}
7859
ad8ba2cd
SY		 7860void kvm_arch_sync_events(struct kvm *kvm)
7861{
332967a3 7862 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7863 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7864 kvm_free_all_assigned_devices(kvm);
aea924f6 7865 kvm_free_pit(kvm);
ad8ba2cd
SY		 7866}
7867
1d8007bd 7868int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7869{
7870 int i, r;
25188b99 7871 unsigned long hva;
f0d648bd
PB		 7872 struct kvm_memslots *slots = kvm_memslots(kvm);
7873 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7874
7875 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7876 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7877 return -EINVAL;
9da0e4d5 7878
f0d648bd
PB		 7879 slot = id_to_memslot(slots, id);
7880 if (size) {
b21629da 7881 if (slot->npages)
f0d648bd
PB		 7882 return -EEXIST;
7883
7884 /*
7885 * MAP_SHARED to prevent internal slot pages from being moved
7886 * by fork()/COW.
7887 */
7888 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7889 MAP_SHARED | MAP_ANONYMOUS, 0);
7890 if (IS_ERR((void *)hva))
7891 return PTR_ERR((void *)hva);
7892 } else {
7893 if (!slot->npages)
7894 return 0;
7895
7896 hva = 0;
7897 }
7898
7899 old = *slot;
9da0e4d5 7900 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7901 struct kvm_userspace_memory_region m;
9da0e4d5 7902
1d8007bd
PB		 7903 m.slot = id | (i << 16);
7904 m.flags = 0;
7905 m.guest_phys_addr = gpa;
f0d648bd 7906 m.userspace_addr = hva;
1d8007bd 7907 m.memory_size = size;
9da0e4d5
PB		 7908 r = __kvm_set_memory_region(kvm, &m);
7909 if (r < 0)
7910 return r;
7911 }
7912
f0d648bd
PB		 7913 if (!size) {
7914 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7915 WARN_ON(r < 0);
7916 }
7917
9da0e4d5
PB		 7918 return 0;
7919}
7920EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7921
1d8007bd 7922int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7923{
7924 int r;
7925
7926 mutex_lock(&kvm->slots_lock);
1d8007bd 7927 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7928 mutex_unlock(&kvm->slots_lock);
7929
7930 return r;
7931}
7932EXPORT_SYMBOL_GPL(x86_set_memory_region);
7933
d19a9cd2
ZX		 7934void kvm_arch_destroy_vm(struct kvm *kvm)
7935{
27469d29
AH		 7936 if (current->mm == kvm->mm) {
7937 /*
7938 * Free memory regions allocated on behalf of userspace,
7939 * unless the the memory map has changed due to process exit
7940 * or fd copying.
7941 */
1d8007bd
PB		 7942 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7943 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7944 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7945 }
03543133
SS		 7946 if (kvm_x86_ops->vm_destroy)
7947 kvm_x86_ops->vm_destroy(kvm);
6eb55818 7948 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7949 kfree(kvm->arch.vpic);
7950 kfree(kvm->arch.vioapic);
d19a9cd2 7951 kvm_free_vcpus(kvm);
af1bae54 7952 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 7953 kvm_mmu_uninit_vm(kvm);
d19a9cd2 7954}
0de10343 7955
5587027c 7956void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7957 struct kvm_memory_slot *dont)
7958{
7959 int i;
7960
d89cc617
TY		 7961 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7962 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7963 kvfree(free->arch.rmap[i]);
d89cc617 7964 free->arch.rmap[i] = NULL;
77d11309 7965 }
d89cc617
TY		 7966 if (i == 0)
7967 continue;
7968
7969 if (!dont || free->arch.lpage_info[i - 1] !=
7970 dont->arch.lpage_info[i - 1]) {
548ef284 7971 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7972 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7973 }
7974 }
21ebbeda
XG		 7975
7976 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 7977}
7978
5587027c
AK		 7979int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7980 unsigned long npages)
db3fe4eb
TY		 7981{
7982 int i;
7983
d89cc617 7984 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 7985 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 7986 unsigned long ugfn;
7987 int lpages;
d89cc617 7988 int level = i + 1;
db3fe4eb
TY		 7989
7990 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7991 slot->base_gfn, level) + 1;
7992
d89cc617
TY		 7993 slot->arch.rmap[i] =
7994 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7995 if (!slot->arch.rmap[i])
77d11309 7996 goto out_free;
d89cc617
TY		 7997 if (i == 0)
7998 continue;
77d11309 7999
92f94f1e
XG		 8000 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
8001 if (!linfo)
db3fe4eb
TY		 8002 goto out_free;
8003
92f94f1e
XG		 8004 slot->arch.lpage_info[i - 1] = linfo;
8005
db3fe4eb 8006 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8007 linfo[0].disallow_lpage = 1;
db3fe4eb 8008 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8009 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8010 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8011 /*
8012 * If the gfn and userspace address are not aligned wrt each
8013 * other, or if explicitly asked to, disable large page
8014 * support for this slot
8015 */
8016 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8017 !kvm_largepages_enabled()) {
8018 unsigned long j;
8019
8020 for (j = 0; j < lpages; ++j)
92f94f1e 8021 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8022 }
8023 }
8024
21ebbeda
XG		 8025 if (kvm_page_track_create_memslot(slot, npages))
8026 goto out_free;
8027
db3fe4eb
TY		 8028 return 0;
8029
8030out_free:
d89cc617 8031 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8032 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8033 slot->arch.rmap[i] = NULL;
8034 if (i == 0)
8035 continue;
8036
548ef284 8037 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8038 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8039 }
8040 return -ENOMEM;
8041}
8042
15f46015 8043void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8044{
e6dff7d1
TY		 8045 /*
8046 * memslots->generation has been incremented.
8047 * mmio generation may have reached its maximum value.
8048 */
54bf36aa 8049 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8050}
8051
f7784b8e
MT		 8052int kvm_arch_prepare_memory_region(struct kvm *kvm,
8053 struct kvm_memory_slot *memslot,
09170a49 8054 const struct kvm_userspace_memory_region *mem,
7b6195a9 8055 enum kvm_mr_change change)
0de10343 8056{
f7784b8e
MT		 8057 return 0;
8058}
8059
88178fd4
KH		 8060static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8061 struct kvm_memory_slot *new)
8062{
8063 /* Still write protect RO slot */
8064 if (new->flags & KVM_MEM_READONLY) {
8065 kvm_mmu_slot_remove_write_access(kvm, new);
8066 return;
8067 }
8068
8069 /*
8070 * Call kvm_x86_ops dirty logging hooks when they are valid.
8071 *
8072 * kvm_x86_ops->slot_disable_log_dirty is called when:
8073 *
8074 * - KVM_MR_CREATE with dirty logging is disabled
8075 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8076 *
8077 * The reason is, in case of PML, we need to set D-bit for any slots
8078 * with dirty logging disabled in order to eliminate unnecessary GPA
8079 * logging in PML buffer (and potential PML buffer full VMEXT). This
8080 * guarantees leaving PML enabled during guest's lifetime won't have
8081 * any additonal overhead from PML when guest is running with dirty
8082 * logging disabled for memory slots.
8083 *
8084 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8085 * to dirty logging mode.
8086 *
8087 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8088 *
8089 * In case of write protect:
8090 *
8091 * Write protect all pages for dirty logging.
8092 *
8093 * All the sptes including the large sptes which point to this
8094 * slot are set to readonly. We can not create any new large
8095 * spte on this slot until the end of the logging.
8096 *
8097 * See the comments in fast_page_fault().
8098 */
8099 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8100 if (kvm_x86_ops->slot_enable_log_dirty)
8101 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8102 else
8103 kvm_mmu_slot_remove_write_access(kvm, new);
8104 } else {
8105 if (kvm_x86_ops->slot_disable_log_dirty)
8106 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8107 }
8108}
8109
f7784b8e 8110void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8111 const struct kvm_userspace_memory_region *mem,
8482644a 8112 const struct kvm_memory_slot *old,
f36f3f28 8113 const struct kvm_memory_slot *new,
8482644a 8114 enum kvm_mr_change change)
f7784b8e 8115{
8482644a 8116 int nr_mmu_pages = 0;
f7784b8e 8117
48c0e4e9
XG		 8118 if (!kvm->arch.n_requested_mmu_pages)
8119 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8120
48c0e4e9 8121 if (nr_mmu_pages)
0de10343 8122 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8123
3ea3b7fa
WL		 8124 /*
8125 * Dirty logging tracks sptes in 4k granularity, meaning that large
8126 * sptes have to be split. If live migration is successful, the guest
8127 * in the source machine will be destroyed and large sptes will be
8128 * created in the destination. However, if the guest continues to run
8129 * in the source machine (for example if live migration fails), small
8130 * sptes will remain around and cause bad performance.
8131 *
8132 * Scan sptes if dirty logging has been stopped, dropping those
8133 * which can be collapsed into a single large-page spte. Later
8134 * page faults will create the large-page sptes.
8135 */
8136 if ((change != KVM_MR_DELETE) &&
8137 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8138 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8139 kvm_mmu_zap_collapsible_sptes(kvm, new);
8140
c972f3b1 8141 /*
88178fd4 8142 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8143 *
88178fd4
KH		 8144 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8145 * been zapped so no dirty logging staff is needed for old slot. For
8146 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8147 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8148 *
8149 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8150 */
88178fd4 8151 if (change != KVM_MR_DELETE)
f36f3f28 8152 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8153}
1d737c8a 8154
2df72e9b 8155void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8156{
6ca18b69 8157 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8158}
8159
2df72e9b
MT		 8160void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8161 struct kvm_memory_slot *slot)
8162{
6ca18b69 8163 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8164}
8165
5d9bc648
PB		 8166static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8167{
8168 if (!list_empty_careful(&vcpu->async_pf.done))
8169 return true;
8170
8171 if (kvm_apic_has_events(vcpu))
8172 return true;
8173
8174 if (vcpu->arch.pv.pv_unhalted)
8175 return true;
8176
8177 if (atomic_read(&vcpu->arch.nmi_queued))
8178 return true;
8179
73917739
PB		 8180 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8181 return true;
8182
5d9bc648
PB		 8183 if (kvm_arch_interrupt_allowed(vcpu) &&
8184 kvm_cpu_has_interrupt(vcpu))
8185 return true;
8186
1f4b34f8
AS		 8187 if (kvm_hv_has_stimer_pending(vcpu))
8188 return true;
8189
5d9bc648
PB		 8190 return false;
8191}
8192
1d737c8a
ZX		 8193int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8194{
b6b8a145
JK		 8195 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8196 kvm_x86_ops->check_nested_events(vcpu, false);
8197
5d9bc648 8198 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8199}
5736199a 8200
b6d33834 8201int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8202{
b6d33834 8203 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8204}
78646121
GN		 8205
8206int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8207{
8208 return kvm_x86_ops->interrupt_allowed(vcpu);
8209}
229456fc 8210
82b32774 8211unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8212{
82b32774
NA		 8213 if (is_64_bit_mode(vcpu))
8214 return kvm_rip_read(vcpu);
8215 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8216 kvm_rip_read(vcpu));
8217}
8218EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8219
82b32774
NA		 8220bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8221{
8222 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8223}
8224EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8225
94fe45da
JK		 8226unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8227{
8228 unsigned long rflags;
8229
8230 rflags = kvm_x86_ops->get_rflags(vcpu);
8231 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8232 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8233 return rflags;
8234}
8235EXPORT_SYMBOL_GPL(kvm_get_rflags);
8236
6addfc42 8237static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8238{
8239 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8240 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8241 rflags |= X86_EFLAGS_TF;
94fe45da 8242 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8243}
8244
8245void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8246{
8247 __kvm_set_rflags(vcpu, rflags);
3842d135 8248 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8249}
8250EXPORT_SYMBOL_GPL(kvm_set_rflags);
8251
56028d08
GN		 8252void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8253{
8254 int r;
8255
fb67e14f 8256 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8257 work->wakeup_all)
56028d08
GN		 8258 return;
8259
8260 r = kvm_mmu_reload(vcpu);
8261 if (unlikely(r))
8262 return;
8263
fb67e14f
XG		 8264 if (!vcpu->arch.mmu.direct_map &&
8265 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8266 return;
8267
56028d08
GN		 8268 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8269}
8270
af585b92
GN		 8271static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8272{
8273 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8274}
8275
8276static inline u32 kvm_async_pf_next_probe(u32 key)
8277{
8278 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8279}
8280
8281static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8282{
8283 u32 key = kvm_async_pf_hash_fn(gfn);
8284
8285 while (vcpu->arch.apf.gfns[key] != ~0)
8286 key = kvm_async_pf_next_probe(key);
8287
8288 vcpu->arch.apf.gfns[key] = gfn;
8289}
8290
8291static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8292{
8293 int i;
8294 u32 key = kvm_async_pf_hash_fn(gfn);
8295
8296 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8297 (vcpu->arch.apf.gfns[key] != gfn &&
8298 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8299 key = kvm_async_pf_next_probe(key);
8300
8301 return key;
8302}
8303
8304bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8305{
8306 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8307}
8308
8309static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8310{
8311 u32 i, j, k;
8312
8313 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8314 while (true) {
8315 vcpu->arch.apf.gfns[i] = ~0;
8316 do {
8317 j = kvm_async_pf_next_probe(j);
8318 if (vcpu->arch.apf.gfns[j] == ~0)
8319 return;
8320 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8321 /*
8322 * k lies cyclically in ]i,j]
8323 * | i.k.j |
8324 * |....j i.k.| or |.k..j i...|
8325 */
8326 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8327 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8328 i = j;
8329 }
8330}
8331
7c90705b
GN		 8332static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8333{
8334
8335 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8336 sizeof(val));
8337}
8338
af585b92
GN		 8339void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8340 struct kvm_async_pf *work)
8341{
6389ee94
AK		 8342 struct x86_exception fault;
8343
7c90705b 8344 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8345 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8346
8347 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8348 (vcpu->arch.apf.send_user_only &&
8349 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8350 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8351 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8352 fault.vector = PF_VECTOR;
8353 fault.error_code_valid = true;
8354 fault.error_code = 0;
8355 fault.nested_page_fault = false;
8356 fault.address = work->arch.token;
8357 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8358 }
af585b92
GN		 8359}
8360
8361void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8362 struct kvm_async_pf *work)
8363{
6389ee94
AK		 8364 struct x86_exception fault;
8365
7c90705b 8366 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8367 if (work->wakeup_all)
7c90705b
GN		 8368 work->arch.token = ~0; /* broadcast wakeup */
8369 else
8370 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8371
8372 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8373 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8374 fault.vector = PF_VECTOR;
8375 fault.error_code_valid = true;
8376 fault.error_code = 0;
8377 fault.nested_page_fault = false;
8378 fault.address = work->arch.token;
8379 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8380 }
e6d53e3b 8381 vcpu->arch.apf.halted = false;
a4fa1635 8382 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8383}
8384
8385bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8386{
8387 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8388 return true;
8389 else
8390 return !kvm_event_needs_reinjection(vcpu) &&
8391 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8392}
8393
5544eb9b
PB		 8394void kvm_arch_start_assignment(struct kvm *kvm)
8395{
8396 atomic_inc(&kvm->arch.assigned_device_count);
8397}
8398EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8399
8400void kvm_arch_end_assignment(struct kvm *kvm)
8401{
8402 atomic_dec(&kvm->arch.assigned_device_count);
8403}
8404EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8405
8406bool kvm_arch_has_assigned_device(struct kvm *kvm)
8407{
8408 return atomic_read(&kvm->arch.assigned_device_count);
8409}
8410EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8411
e0f0bbc5
AW		 8412void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8413{
8414 atomic_inc(&kvm->arch.noncoherent_dma_count);
8415}
8416EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8417
8418void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8419{
8420 atomic_dec(&kvm->arch.noncoherent_dma_count);
8421}
8422EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8423
8424bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8425{
8426 return atomic_read(&kvm->arch.noncoherent_dma_count);
8427}
8428EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8429
14717e20
AW		 8430bool kvm_arch_has_irq_bypass(void)
8431{
8432 return kvm_x86_ops->update_pi_irte != NULL;
8433}
8434
87276880
FW		 8435int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8436 struct irq_bypass_producer *prod)
8437{
8438 struct kvm_kernel_irqfd *irqfd =
8439 container_of(cons, struct kvm_kernel_irqfd, consumer);
8440
14717e20 8441 irqfd->producer = prod;
87276880 8442
14717e20
AW		 8443 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8444 prod->irq, irqfd->gsi, 1);
87276880
FW		 8445}
8446
8447void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8448 struct irq_bypass_producer *prod)
8449{
8450 int ret;
8451 struct kvm_kernel_irqfd *irqfd =
8452 container_of(cons, struct kvm_kernel_irqfd, consumer);
8453
87276880
FW		 8454 WARN_ON(irqfd->producer != prod);
8455 irqfd->producer = NULL;
8456
8457 /*
8458 * When producer of consumer is unregistered, we change back to
8459 * remapped mode, so we can re-use the current implementation
bb3541f1 8460 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8461 * int this case doesn't want to receive the interrupts.
8462 */
8463 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8464 if (ret)
8465 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8466 " fails: %d\n", irqfd->consumer.token, ret);
8467}
8468
8469int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8470 uint32_t guest_irq, bool set)
8471{
8472 if (!kvm_x86_ops->update_pi_irte)
8473 return -EINVAL;
8474
8475 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8476}
8477
52004014
FW		 8478bool kvm_vector_hashing_enabled(void)
8479{
8480 return vector_hashing;
8481}
8482EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8483
229456fc 8484EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8485EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8486EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8487EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8488EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8489EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8490EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8491EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8492EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8493EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8494EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8495EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8496EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8497EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8498EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8499EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8500EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8501EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8502EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)