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KVM: x86: declare a few variables as __read_mostly
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d
JR		 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
112
cc578287 113/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 114static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 115module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
116
d0659d94 117/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 118unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 119module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
120
893590c7 121static bool __read_mostly backwards_tsc_observed = false;
16a96021 122
18863bdd
AK		 123#define KVM_NR_SHARED_MSRS 16
124
125struct kvm_shared_msrs_global {
126 int nr;
2bf78fa7 127 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 128};
129
130struct kvm_shared_msrs {
131 struct user_return_notifier urn;
132 bool registered;
2bf78fa7
SY		 133 struct kvm_shared_msr_values {
134 u64 host;
135 u64 curr;
136 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 137};
138
139static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 140static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 141
417bc304 142struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 143 { "pf_fixed", VCPU_STAT(pf_fixed) },
144 { "pf_guest", VCPU_STAT(pf_guest) },
145 { "tlb_flush", VCPU_STAT(tlb_flush) },
146 { "invlpg", VCPU_STAT(invlpg) },
147 { "exits", VCPU_STAT(exits) },
148 { "io_exits", VCPU_STAT(io_exits) },
149 { "mmio_exits", VCPU_STAT(mmio_exits) },
150 { "signal_exits", VCPU_STAT(signal_exits) },
151 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 152 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 153 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 154 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 155 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 156 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 157 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 158 { "request_irq", VCPU_STAT(request_irq_exits) },
159 { "irq_exits", VCPU_STAT(irq_exits) },
160 { "host_state_reload", VCPU_STAT(host_state_reload) },
161 { "efer_reload", VCPU_STAT(efer_reload) },
162 { "fpu_reload", VCPU_STAT(fpu_reload) },
163 { "insn_emulation", VCPU_STAT(insn_emulation) },
164 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 165 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 166 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 167 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
168 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
169 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
170 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
171 { "mmu_flooded", VM_STAT(mmu_flooded) },
172 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 173 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 174 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 175 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 176 { "largepages", VM_STAT(lpages) },
417bc304
HB		 177 { NULL }
178};
179
2acf923e
DC		 180u64 __read_mostly host_xcr0;
181
b6785def 182static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 183
af585b92
GN		 184static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
185{
186 int i;
187 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
188 vcpu->arch.apf.gfns[i] = ~0;
189}
190
18863bdd
AK		 191static void kvm_on_user_return(struct user_return_notifier *urn)
192{
193 unsigned slot;
18863bdd
AK		 194 struct kvm_shared_msrs *locals
195 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 196 struct kvm_shared_msr_values *values;
18863bdd
AK		 197
198 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 199 values = &locals->values[slot];
200 if (values->host != values->curr) {
201 wrmsrl(shared_msrs_global.msrs[slot], values->host);
202 values->curr = values->host;
18863bdd
AK		 203 }
204 }
205 locals->registered = false;
206 user_return_notifier_unregister(urn);
207}
208
2bf78fa7 209static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 210{
18863bdd 211 u64 value;
013f6a5d
MT		 212 unsigned int cpu = smp_processor_id();
213 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 214
2bf78fa7
SY		 215 /* only read, and nobody should modify it at this time,
216 * so don't need lock */
217 if (slot >= shared_msrs_global.nr) {
218 printk(KERN_ERR "kvm: invalid MSR slot!");
219 return;
220 }
221 rdmsrl_safe(msr, &value);
222 smsr->values[slot].host = value;
223 smsr->values[slot].curr = value;
224}
225
226void kvm_define_shared_msr(unsigned slot, u32 msr)
227{
0123be42 228 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 229 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 230 if (slot >= shared_msrs_global.nr)
231 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 232}
233EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
234
235static void kvm_shared_msr_cpu_online(void)
236{
237 unsigned i;
18863bdd
AK		 238
239 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 240 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 241}
242
8b3c3104 243int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 244{
013f6a5d
MT		 245 unsigned int cpu = smp_processor_id();
246 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 247 int err;
18863bdd 248
2bf78fa7 249 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 250 return 0;
2bf78fa7 251 smsr->values[slot].curr = value;
8b3c3104
AH		 252 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
253 if (err)
254 return 1;
255
18863bdd
AK		 256 if (!smsr->registered) {
257 smsr->urn.on_user_return = kvm_on_user_return;
258 user_return_notifier_register(&smsr->urn);
259 smsr->registered = true;
260 }
8b3c3104 261 return 0;
18863bdd
AK		 262}
263EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
264
13a34e06 265static void drop_user_return_notifiers(void)
3548bab5 266{
013f6a5d
MT		 267 unsigned int cpu = smp_processor_id();
268 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 269
270 if (smsr->registered)
271 kvm_on_user_return(&smsr->urn);
272}
273
6866b83e
CO		 274u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
275{
8a5a87d9 276 return vcpu->arch.apic_base;
6866b83e
CO		 277}
278EXPORT_SYMBOL_GPL(kvm_get_apic_base);
279
58cb628d
JK		 280int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
281{
282 u64 old_state = vcpu->arch.apic_base &
283 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
284 u64 new_state = msr_info->data &
285 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
286 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
287 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
288
289 if (!msr_info->host_initiated &&
290 ((msr_info->data & reserved_bits) != 0 ||
291 new_state == X2APIC_ENABLE ||
292 (new_state == MSR_IA32_APICBASE_ENABLE &&
293 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
294 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
295 old_state == 0)))
296 return 1;
297
298 kvm_lapic_set_base(vcpu, msr_info->data);
299 return 0;
6866b83e
CO		 300}
301EXPORT_SYMBOL_GPL(kvm_set_apic_base);
302
2605fc21 303asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 304{
305 /* Fault while not rebooting. We want the trace. */
306 BUG();
307}
308EXPORT_SYMBOL_GPL(kvm_spurious_fault);
309
3fd28fce
ED		 310#define EXCPT_BENIGN 0
311#define EXCPT_CONTRIBUTORY 1
312#define EXCPT_PF 2
313
314static int exception_class(int vector)
315{
316 switch (vector) {
317 case PF_VECTOR:
318 return EXCPT_PF;
319 case DE_VECTOR:
320 case TS_VECTOR:
321 case NP_VECTOR:
322 case SS_VECTOR:
323 case GP_VECTOR:
324 return EXCPT_CONTRIBUTORY;
325 default:
326 break;
327 }
328 return EXCPT_BENIGN;
329}
330
d6e8c854
NA		 331#define EXCPT_FAULT 0
332#define EXCPT_TRAP 1
333#define EXCPT_ABORT 2
334#define EXCPT_INTERRUPT 3
335
336static int exception_type(int vector)
337{
338 unsigned int mask;
339
340 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
341 return EXCPT_INTERRUPT;
342
343 mask = 1 << vector;
344
345 /* #DB is trap, as instruction watchpoints are handled elsewhere */
346 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
347 return EXCPT_TRAP;
348
349 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
350 return EXCPT_ABORT;
351
352 /* Reserved exceptions will result in fault */
353 return EXCPT_FAULT;
354}
355
3fd28fce 356static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 357 unsigned nr, bool has_error, u32 error_code,
358 bool reinject)
3fd28fce
ED		 359{
360 u32 prev_nr;
361 int class1, class2;
362
3842d135
AK		 363 kvm_make_request(KVM_REQ_EVENT, vcpu);
364
3fd28fce
ED		 365 if (!vcpu->arch.exception.pending) {
366 queue:
3ffb2468
NA		 367 if (has_error && !is_protmode(vcpu))
368 has_error = false;
3fd28fce
ED		 369 vcpu->arch.exception.pending = true;
370 vcpu->arch.exception.has_error_code = has_error;
371 vcpu->arch.exception.nr = nr;
372 vcpu->arch.exception.error_code = error_code;
3f0fd292 373 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 374 return;
375 }
376
377 /* to check exception */
378 prev_nr = vcpu->arch.exception.nr;
379 if (prev_nr == DF_VECTOR) {
380 /* triple fault -> shutdown */
a8eeb04a 381 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 382 return;
383 }
384 class1 = exception_class(prev_nr);
385 class2 = exception_class(nr);
386 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
387 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
388 /* generate double fault per SDM Table 5-5 */
389 vcpu->arch.exception.pending = true;
390 vcpu->arch.exception.has_error_code = true;
391 vcpu->arch.exception.nr = DF_VECTOR;
392 vcpu->arch.exception.error_code = 0;
393 } else
394 /* replace previous exception with a new one in a hope
395 that instruction re-execution will regenerate lost
396 exception */
397 goto queue;
398}
399
298101da
AK		 400void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
401{
ce7ddec4 402 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 403}
404EXPORT_SYMBOL_GPL(kvm_queue_exception);
405
ce7ddec4
JR		 406void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
407{
408 kvm_multiple_exception(vcpu, nr, false, 0, true);
409}
410EXPORT_SYMBOL_GPL(kvm_requeue_exception);
411
db8fcefa 412void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 413{
db8fcefa
AP		 414 if (err)
415 kvm_inject_gp(vcpu, 0);
416 else
417 kvm_x86_ops->skip_emulated_instruction(vcpu);
418}
419EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 420
6389ee94 421void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 422{
423 ++vcpu->stat.pf_guest;
6389ee94
AK		 424 vcpu->arch.cr2 = fault->address;
425 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 426}
27d6c865 427EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 428
ef54bcfe 429static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 430{
6389ee94
AK		 431 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
432 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 433 else
6389ee94 434 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 435
436 return fault->nested_page_fault;
d4f8cf66
JR		 437}
438
3419ffc8
SY		 439void kvm_inject_nmi(struct kvm_vcpu *vcpu)
440{
7460fb4a
AK		 441 atomic_inc(&vcpu->arch.nmi_queued);
442 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 443}
444EXPORT_SYMBOL_GPL(kvm_inject_nmi);
445
298101da
AK		 446void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
447{
ce7ddec4 448 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 449}
450EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
451
ce7ddec4
JR		 452void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
453{
454 kvm_multiple_exception(vcpu, nr, true, error_code, true);
455}
456EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
457
0a79b009
AK		 458/*
459 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
460 * a #GP and return false.
461 */
462bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 463{
0a79b009
AK		 464 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
465 return true;
466 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
467 return false;
298101da 468}
0a79b009 469EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 470
16f8a6f9
NA		 471bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
472{
473 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
474 return true;
475
476 kvm_queue_exception(vcpu, UD_VECTOR);
477 return false;
478}
479EXPORT_SYMBOL_GPL(kvm_require_dr);
480
ec92fe44
JR		 481/*
482 * This function will be used to read from the physical memory of the currently
54bf36aa 483 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 484 * can read from guest physical or from the guest's guest physical memory.
485 */
486int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
487 gfn_t ngfn, void *data, int offset, int len,
488 u32 access)
489{
54987b7a 490 struct x86_exception exception;
ec92fe44
JR		 491 gfn_t real_gfn;
492 gpa_t ngpa;
493
494 ngpa = gfn_to_gpa(ngfn);
54987b7a 495 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 496 if (real_gfn == UNMAPPED_GVA)
497 return -EFAULT;
498
499 real_gfn = gpa_to_gfn(real_gfn);
500
54bf36aa 501 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 502}
503EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
504
69b0049a 505static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 506 void *data, int offset, int len, u32 access)
507{
508 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
509 data, offset, len, access);
510}
511
a03490ed
CO		 512/*
513 * Load the pae pdptrs. Return true is they are all valid.
514 */
ff03a073 515int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 516{
517 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
518 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
519 int i;
520 int ret;
ff03a073 521 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 522
ff03a073
JR		 523 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
524 offset * sizeof(u64), sizeof(pdpte),
525 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 526 if (ret < 0) {
527 ret = 0;
528 goto out;
529 }
530 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 531 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 532 (pdpte[i] &
533 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 534 ret = 0;
535 goto out;
536 }
537 }
538 ret = 1;
539
ff03a073 540 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 541 __set_bit(VCPU_EXREG_PDPTR,
542 (unsigned long *)&vcpu->arch.regs_avail);
543 __set_bit(VCPU_EXREG_PDPTR,
544 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 545out:
a03490ed
CO		 546
547 return ret;
548}
cc4b6871 549EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 550
d835dfec
AK		 551static bool pdptrs_changed(struct kvm_vcpu *vcpu)
552{
ff03a073 553 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 554 bool changed = true;
3d06b8bf
JR		 555 int offset;
556 gfn_t gfn;
d835dfec
AK		 557 int r;
558
559 if (is_long_mode(vcpu) || !is_pae(vcpu))
560 return false;
561
6de4f3ad
AK		 562 if (!test_bit(VCPU_EXREG_PDPTR,
563 (unsigned long *)&vcpu->arch.regs_avail))
564 return true;
565
9f8fe504
AK		 566 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
567 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 568 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
569 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 570 if (r < 0)
571 goto out;
ff03a073 572 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 573out:
d835dfec
AK		 574
575 return changed;
576}
577
49a9b07e 578int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 579{
aad82703 580 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 581 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 582
f9a48e6a
AK		 583 cr0 |= X86_CR0_ET;
584
ab344828 585#ifdef CONFIG_X86_64
0f12244f
GN		 586 if (cr0 & 0xffffffff00000000UL)
587 return 1;
ab344828
GN		 588#endif
589
590 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 591
0f12244f
GN		 592 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
593 return 1;
a03490ed 594
0f12244f
GN		 595 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
596 return 1;
a03490ed
CO		 597
598 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
599#ifdef CONFIG_X86_64
f6801dff 600 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 601 int cs_db, cs_l;
602
0f12244f
GN		 603 if (!is_pae(vcpu))
604 return 1;
a03490ed 605 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 606 if (cs_l)
607 return 1;
a03490ed
CO		 608 } else
609#endif
ff03a073 610 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 611 kvm_read_cr3(vcpu)))
0f12244f 612 return 1;
a03490ed
CO		 613 }
614
ad756a16
MJ		 615 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
616 return 1;
617
a03490ed 618 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 619
d170c419 620 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 621 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 622 kvm_async_pf_hash_reset(vcpu);
623 }
e5f3f027 624
aad82703
SY		 625 if ((cr0 ^ old_cr0) & update_bits)
626 kvm_mmu_reset_context(vcpu);
b18d5431 627
879ae188
LE		 628 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
629 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
630 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 631 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
632
0f12244f
GN		 633 return 0;
634}
2d3ad1f4 635EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 636
2d3ad1f4 637void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 638{
49a9b07e 639 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 640}
2d3ad1f4 641EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 642
42bdf991
MT		 643static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
644{
645 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
646 !vcpu->guest_xcr0_loaded) {
647 /* kvm_set_xcr() also depends on this */
648 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
649 vcpu->guest_xcr0_loaded = 1;
650 }
651}
652
653static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
654{
655 if (vcpu->guest_xcr0_loaded) {
656 if (vcpu->arch.xcr0 != host_xcr0)
657 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
658 vcpu->guest_xcr0_loaded = 0;
659 }
660}
661
69b0049a 662static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 663{
56c103ec
LJ		 664 u64 xcr0 = xcr;
665 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 666 u64 valid_bits;
2acf923e
DC		 667
668 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
669 if (index != XCR_XFEATURE_ENABLED_MASK)
670 return 1;
2acf923e
DC		 671 if (!(xcr0 & XSTATE_FP))
672 return 1;
673 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
674 return 1;
46c34cb0
PB		 675
676 /*
677 * Do not allow the guest to set bits that we do not support
678 * saving. However, xcr0 bit 0 is always set, even if the
679 * emulated CPU does not support XSAVE (see fx_init).
680 */
681 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
682 if (xcr0 & ~valid_bits)
2acf923e 683 return 1;
46c34cb0 684
390bd528
LJ		 685 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
686 return 1;
687
612263b3
CP		 688 if (xcr0 & XSTATE_AVX512) {
689 if (!(xcr0 & XSTATE_YMM))
690 return 1;
691 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
692 return 1;
693 }
42bdf991 694 kvm_put_guest_xcr0(vcpu);
2acf923e 695 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 696
697 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
698 kvm_update_cpuid(vcpu);
2acf923e
DC		 699 return 0;
700}
701
702int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
703{
764bcbc5
Z		 704 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
705 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 706 kvm_inject_gp(vcpu, 0);
707 return 1;
708 }
709 return 0;
710}
711EXPORT_SYMBOL_GPL(kvm_set_xcr);
712
a83b29c6 713int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 714{
fc78f519 715 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 716 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
717 X86_CR4_SMEP | X86_CR4_SMAP;
718
0f12244f
GN		 719 if (cr4 & CR4_RESERVED_BITS)
720 return 1;
a03490ed 721
2acf923e
DC		 722 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
723 return 1;
724
c68b734f
YW		 725 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
726 return 1;
727
97ec8c06
FW		 728 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
729 return 1;
730
afcbf13f 731 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 732 return 1;
733
a03490ed 734 if (is_long_mode(vcpu)) {
0f12244f
GN		 735 if (!(cr4 & X86_CR4_PAE))
736 return 1;
a2edf57f
AK		 737 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
738 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 739 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
740 kvm_read_cr3(vcpu)))
0f12244f
GN		 741 return 1;
742
ad756a16
MJ		 743 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
744 if (!guest_cpuid_has_pcid(vcpu))
745 return 1;
746
747 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
748 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
749 return 1;
750 }
751
5e1746d6 752 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 753 return 1;
a03490ed 754
ad756a16
MJ		 755 if (((cr4 ^ old_cr4) & pdptr_bits) ||
756 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 757 kvm_mmu_reset_context(vcpu);
0f12244f 758
2acf923e 759 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 760 kvm_update_cpuid(vcpu);
2acf923e 761
0f12244f
GN		 762 return 0;
763}
2d3ad1f4 764EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 765
2390218b 766int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 767{
ac146235 768#ifdef CONFIG_X86_64
9d88fca7 769 cr3 &= ~CR3_PCID_INVD;
ac146235 770#endif
9d88fca7 771
9f8fe504 772 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 773 kvm_mmu_sync_roots(vcpu);
77c3913b 774 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 775 return 0;
d835dfec
AK		 776 }
777
a03490ed 778 if (is_long_mode(vcpu)) {
d9f89b88
JK		 779 if (cr3 & CR3_L_MODE_RESERVED_BITS)
780 return 1;
781 } else if (is_pae(vcpu) && is_paging(vcpu) &&
782 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 783 return 1;
a03490ed 784
0f12244f 785 vcpu->arch.cr3 = cr3;
aff48baa 786 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 787 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 788 return 0;
789}
2d3ad1f4 790EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 791
eea1cff9 792int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 793{
0f12244f
GN		 794 if (cr8 & CR8_RESERVED_BITS)
795 return 1;
35754c98 796 if (lapic_in_kernel(vcpu))
a03490ed
CO		 797 kvm_lapic_set_tpr(vcpu, cr8);
798 else
ad312c7c 799 vcpu->arch.cr8 = cr8;
0f12244f
GN		 800 return 0;
801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 803
2d3ad1f4 804unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 805{
35754c98 806 if (lapic_in_kernel(vcpu))
a03490ed
CO		 807 return kvm_lapic_get_cr8(vcpu);
808 else
ad312c7c 809 return vcpu->arch.cr8;
a03490ed 810}
2d3ad1f4 811EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 812
ae561ede
NA		 813static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
814{
815 int i;
816
817 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
818 for (i = 0; i < KVM_NR_DB_REGS; i++)
819 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
820 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
821 }
822}
823
73aaf249
JK		 824static void kvm_update_dr6(struct kvm_vcpu *vcpu)
825{
826 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
827 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
828}
829
c8639010
JK		 830static void kvm_update_dr7(struct kvm_vcpu *vcpu)
831{
832 unsigned long dr7;
833
834 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
835 dr7 = vcpu->arch.guest_debug_dr7;
836 else
837 dr7 = vcpu->arch.dr7;
838 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 839 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
840 if (dr7 & DR7_BP_EN_MASK)
841 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 842}
843
6f43ed01
NA		 844static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
845{
846 u64 fixed = DR6_FIXED_1;
847
848 if (!guest_cpuid_has_rtm(vcpu))
849 fixed |= DR6_RTM;
850 return fixed;
851}
852
338dbc97 853static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 854{
855 switch (dr) {
856 case 0 ... 3:
857 vcpu->arch.db[dr] = val;
858 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
859 vcpu->arch.eff_db[dr] = val;
860 break;
861 case 4:
020df079
GN		 862 /* fall through */
863 case 6:
338dbc97
GN		 864 if (val & 0xffffffff00000000ULL)
865 return -1; /* #GP */
6f43ed01 866 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 867 kvm_update_dr6(vcpu);
020df079
GN		 868 break;
869 case 5:
020df079
GN		 870 /* fall through */
871 default: /* 7 */
338dbc97
GN		 872 if (val & 0xffffffff00000000ULL)
873 return -1; /* #GP */
020df079 874 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 875 kvm_update_dr7(vcpu);
020df079
GN		 876 break;
877 }
878
879 return 0;
880}
338dbc97
GN		 881
882int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
883{
16f8a6f9 884 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 885 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 886 return 1;
887 }
888 return 0;
338dbc97 889}
020df079
GN		 890EXPORT_SYMBOL_GPL(kvm_set_dr);
891
16f8a6f9 892int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 893{
894 switch (dr) {
895 case 0 ... 3:
896 *val = vcpu->arch.db[dr];
897 break;
898 case 4:
020df079
GN		 899 /* fall through */
900 case 6:
73aaf249
JK		 901 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
902 *val = vcpu->arch.dr6;
903 else
904 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 905 break;
906 case 5:
020df079
GN		 907 /* fall through */
908 default: /* 7 */
909 *val = vcpu->arch.dr7;
910 break;
911 }
338dbc97
GN		 912 return 0;
913}
020df079
GN		 914EXPORT_SYMBOL_GPL(kvm_get_dr);
915
022cd0e8
AK		 916bool kvm_rdpmc(struct kvm_vcpu *vcpu)
917{
918 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
919 u64 data;
920 int err;
921
c6702c9d 922 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 923 if (err)
924 return err;
925 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
926 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
927 return err;
928}
929EXPORT_SYMBOL_GPL(kvm_rdpmc);
930
043405e1
CO		 931/*
932 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
933 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
934 *
935 * This list is modified at module load time to reflect the
e3267cbb 936 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 937 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
938 * may depend on host virtualization features rather than host cpu features.
043405e1 939 */
e3267cbb 940
043405e1
CO		 941static u32 msrs_to_save[] = {
942 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 943 MSR_STAR,
043405e1
CO		 944#ifdef CONFIG_X86_64
945 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
946#endif
b3897a49 947 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 948 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 949};
950
951static unsigned num_msrs_to_save;
952
62ef68bb
PB		 953static u32 emulated_msrs[] = {
954 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
955 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
956 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
957 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 958 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
959 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 960 HV_X64_MSR_RESET,
11c4b1ca 961 HV_X64_MSR_VP_INDEX,
9eec50b8 962 HV_X64_MSR_VP_RUNTIME,
62ef68bb
PB		 963 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
964 MSR_KVM_PV_EOI_EN,
965
ba904635 966 MSR_IA32_TSC_ADJUST,
a3e06bbe 967 MSR_IA32_TSCDEADLINE,
043405e1 968 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 969 MSR_IA32_MCG_STATUS,
970 MSR_IA32_MCG_CTL,
64d60670 971 MSR_IA32_SMBASE,
043405e1
CO		 972};
973
62ef68bb
PB		 974static unsigned num_emulated_msrs;
975
384bb783 976bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 977{
b69e8cae 978 if (efer & efer_reserved_bits)
384bb783 979 return false;
15c4a640 980
1b2fd70c
AG		 981 if (efer & EFER_FFXSR) {
982 struct kvm_cpuid_entry2 *feat;
983
984 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 985 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 986 return false;
1b2fd70c
AG		 987 }
988
d8017474
AG		 989 if (efer & EFER_SVME) {
990 struct kvm_cpuid_entry2 *feat;
991
992 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 993 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 994 return false;
d8017474
AG		 995 }
996
384bb783
JK		 997 return true;
998}
999EXPORT_SYMBOL_GPL(kvm_valid_efer);
1000
1001static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1002{
1003 u64 old_efer = vcpu->arch.efer;
1004
1005 if (!kvm_valid_efer(vcpu, efer))
1006 return 1;
1007
1008 if (is_paging(vcpu)
1009 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1010 return 1;
1011
15c4a640 1012 efer &= ~EFER_LMA;
f6801dff 1013 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1014
a3d204e2
SY		 1015 kvm_x86_ops->set_efer(vcpu, efer);
1016
aad82703
SY		 1017 /* Update reserved bits */
1018 if ((efer ^ old_efer) & EFER_NX)
1019 kvm_mmu_reset_context(vcpu);
1020
b69e8cae 1021 return 0;
15c4a640
CO		 1022}
1023
f2b4b7dd
JR		 1024void kvm_enable_efer_bits(u64 mask)
1025{
1026 efer_reserved_bits &= ~mask;
1027}
1028EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1029
15c4a640
CO		 1030/*
1031 * Writes msr value into into the appropriate "register".
1032 * Returns 0 on success, non-0 otherwise.
1033 * Assumes vcpu_load() was already called.
1034 */
8fe8ab46 1035int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1036{
854e8bb1
NA		 1037 switch (msr->index) {
1038 case MSR_FS_BASE:
1039 case MSR_GS_BASE:
1040 case MSR_KERNEL_GS_BASE:
1041 case MSR_CSTAR:
1042 case MSR_LSTAR:
1043 if (is_noncanonical_address(msr->data))
1044 return 1;
1045 break;
1046 case MSR_IA32_SYSENTER_EIP:
1047 case MSR_IA32_SYSENTER_ESP:
1048 /*
1049 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1050 * non-canonical address is written on Intel but not on
1051 * AMD (which ignores the top 32-bits, because it does
1052 * not implement 64-bit SYSENTER).
1053 *
1054 * 64-bit code should hence be able to write a non-canonical
1055 * value on AMD. Making the address canonical ensures that
1056 * vmentry does not fail on Intel after writing a non-canonical
1057 * value, and that something deterministic happens if the guest
1058 * invokes 64-bit SYSENTER.
1059 */
1060 msr->data = get_canonical(msr->data);
1061 }
8fe8ab46 1062 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1063}
854e8bb1 1064EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1065
313a3dc7
CO		 1066/*
1067 * Adapt set_msr() to msr_io()'s calling convention
1068 */
609e36d3
PB		 1069static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1070{
1071 struct msr_data msr;
1072 int r;
1073
1074 msr.index = index;
1075 msr.host_initiated = true;
1076 r = kvm_get_msr(vcpu, &msr);
1077 if (r)
1078 return r;
1079
1080 *data = msr.data;
1081 return 0;
1082}
1083
313a3dc7
CO		 1084static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1085{
8fe8ab46
WA		 1086 struct msr_data msr;
1087
1088 msr.data = *data;
1089 msr.index = index;
1090 msr.host_initiated = true;
1091 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1092}
1093
16e8d74d
MT		 1094#ifdef CONFIG_X86_64
1095struct pvclock_gtod_data {
1096 seqcount_t seq;
1097
1098 struct { /* extract of a clocksource struct */
1099 int vclock_mode;
1100 cycle_t cycle_last;
1101 cycle_t mask;
1102 u32 mult;
1103 u32 shift;
1104 } clock;
1105
cbcf2dd3
TG		 1106 u64 boot_ns;
1107 u64 nsec_base;
16e8d74d
MT		 1108};
1109
1110static struct pvclock_gtod_data pvclock_gtod_data;
1111
1112static void update_pvclock_gtod(struct timekeeper *tk)
1113{
1114 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1115 u64 boot_ns;
1116
876e7881 1117 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1118
1119 write_seqcount_begin(&vdata->seq);
1120
1121 /* copy pvclock gtod data */
876e7881
PZ		 1122 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1123 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1124 vdata->clock.mask = tk->tkr_mono.mask;
1125 vdata->clock.mult = tk->tkr_mono.mult;
1126 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1127
cbcf2dd3 1128 vdata->boot_ns = boot_ns;
876e7881 1129 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1130
1131 write_seqcount_end(&vdata->seq);
1132}
1133#endif
1134
bab5bb39
NK		 1135void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1136{
1137 /*
1138 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1139 * vcpu_enter_guest. This function is only called from
1140 * the physical CPU that is running vcpu.
1141 */
1142 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1143}
16e8d74d 1144
18068523
GOC		 1145static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1146{
9ed3c444
AK		 1147 int version;
1148 int r;
50d0a0f9 1149 struct pvclock_wall_clock wc;
923de3cf 1150 struct timespec boot;
18068523
GOC		 1151
1152 if (!wall_clock)
1153 return;
1154
9ed3c444
AK		 1155 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1156 if (r)
1157 return;
1158
1159 if (version & 1)
1160 ++version; /* first time write, random junk */
1161
1162 ++version;
18068523 1163
18068523
GOC		 1164 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1165
50d0a0f9
GH		 1166 /*
1167 * The guest calculates current wall clock time by adding
34c238a1 1168 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1169 * wall clock specified here. guest system time equals host
1170 * system time for us, thus we must fill in host boot time here.
1171 */
923de3cf 1172 getboottime(&boot);
50d0a0f9 1173
4b648665
BR		 1174 if (kvm->arch.kvmclock_offset) {
1175 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1176 boot = timespec_sub(boot, ts);
1177 }
50d0a0f9
GH		 1178 wc.sec = boot.tv_sec;
1179 wc.nsec = boot.tv_nsec;
1180 wc.version = version;
18068523
GOC		 1181
1182 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1183
1184 version++;
1185 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1186}
1187
50d0a0f9
GH		 1188static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1189{
1190 uint32_t quotient, remainder;
1191
1192 /* Don't try to replace with do_div(), this one calculates
1193 * "(dividend << 32) / divisor" */
1194 __asm__ ( "divl %4"
1195 : "=a" (quotient), "=d" (remainder)
1196 : "0" (0), "1" (dividend), "r" (divisor) );
1197 return quotient;
1198}
1199
5f4e3f88
ZA		 1200static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1201 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1202{
5f4e3f88 1203 uint64_t scaled64;
50d0a0f9
GH		 1204 int32_t shift = 0;
1205 uint64_t tps64;
1206 uint32_t tps32;
1207
5f4e3f88
ZA		 1208 tps64 = base_khz * 1000LL;
1209 scaled64 = scaled_khz * 1000LL;
50933623 1210 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1211 tps64 >>= 1;
1212 shift--;
1213 }
1214
1215 tps32 = (uint32_t)tps64;
50933623
JK		 1216 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1217 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1218 scaled64 >>= 1;
1219 else
1220 tps32 <<= 1;
50d0a0f9
GH		 1221 shift++;
1222 }
1223
5f4e3f88
ZA		 1224 *pshift = shift;
1225 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1226
5f4e3f88
ZA		 1227 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1228 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1229}
1230
d828199e 1231#ifdef CONFIG_X86_64
16e8d74d 1232static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1233#endif
16e8d74d 1234
c8076604 1235static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1236static unsigned long max_tsc_khz;
c8076604 1237
cc578287 1238static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1239{
cc578287
ZA		 1240 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1241 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1242}
1243
cc578287 1244static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1245{
cc578287
ZA		 1246 u64 v = (u64)khz * (1000000 + ppm);
1247 do_div(v, 1000000);
1248 return v;
1e993611
JR		 1249}
1250
cc578287 1251static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1252{
cc578287
ZA		 1253 u32 thresh_lo, thresh_hi;
1254 int use_scaling = 0;
217fc9cf 1255
03ba32ca
MT		 1256 /* tsc_khz can be zero if TSC calibration fails */
1257 if (this_tsc_khz == 0)
1258 return;
1259
c285545f
ZA		 1260 /* Compute a scale to convert nanoseconds in TSC cycles */
1261 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1262 &vcpu->arch.virtual_tsc_shift,
1263 &vcpu->arch.virtual_tsc_mult);
1264 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1265
1266 /*
1267 * Compute the variation in TSC rate which is acceptable
1268 * within the range of tolerance and decide if the
1269 * rate being applied is within that bounds of the hardware
1270 * rate. If so, no scaling or compensation need be done.
1271 */
1272 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1273 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1274 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1275 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1276 use_scaling = 1;
1277 }
1278 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1279}
1280
1281static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1282{
e26101b1 1283 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1284 vcpu->arch.virtual_tsc_mult,
1285 vcpu->arch.virtual_tsc_shift);
e26101b1 1286 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1287 return tsc;
1288}
1289
69b0049a 1290static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1291{
1292#ifdef CONFIG_X86_64
1293 bool vcpus_matched;
b48aa97e
MT		 1294 struct kvm_arch *ka = &vcpu->kvm->arch;
1295 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1296
1297 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1298 atomic_read(&vcpu->kvm->online_vcpus));
1299
7f187922
MT		 1300 /*
1301 * Once the masterclock is enabled, always perform request in
1302 * order to update it.
1303 *
1304 * In order to enable masterclock, the host clocksource must be TSC
1305 * and the vcpus need to have matched TSCs. When that happens,
1306 * perform request to enable masterclock.
1307 */
1308 if (ka->use_master_clock ||
1309 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1310 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1311
1312 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1313 atomic_read(&vcpu->kvm->online_vcpus),
1314 ka->use_master_clock, gtod->clock.vclock_mode);
1315#endif
1316}
1317
ba904635
WA		 1318static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1319{
1320 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1321 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1322}
1323
8fe8ab46 1324void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1325{
1326 struct kvm *kvm = vcpu->kvm;
f38e098f 1327 u64 offset, ns, elapsed;
99e3e30a 1328 unsigned long flags;
02626b6a 1329 s64 usdiff;
b48aa97e 1330 bool matched;
0d3da0d2 1331 bool already_matched;
8fe8ab46 1332 u64 data = msr->data;
99e3e30a 1333
038f8c11 1334 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1335 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1336 ns = get_kernel_ns();
f38e098f 1337 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1338
03ba32ca 1339 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1340 int faulted = 0;
1341
03ba32ca
MT		 1342 /* n.b - signed multiplication and division required */
1343 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1344#ifdef CONFIG_X86_64
03ba32ca 1345 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1346#else
03ba32ca 1347 /* do_div() only does unsigned */
8915aa27
MT		 1348 asm("1: idivl %[divisor]\n"
1349 "2: xor %%edx, %%edx\n"
1350 " movl $0, %[faulted]\n"
1351 "3:\n"
1352 ".section .fixup,\"ax\"\n"
1353 "4: movl $1, %[faulted]\n"
1354 " jmp 3b\n"
1355 ".previous\n"
1356
1357 _ASM_EXTABLE(1b, 4b)
1358
1359 : "=A"(usdiff), [faulted] "=r" (faulted)
1360 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1361
5d3cb0f6 1362#endif
03ba32ca
MT		 1363 do_div(elapsed, 1000);
1364 usdiff -= elapsed;
1365 if (usdiff < 0)
1366 usdiff = -usdiff;
8915aa27
MT		 1367
1368 /* idivl overflow => difference is larger than USEC_PER_SEC */
1369 if (faulted)
1370 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1371 } else
1372 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1373
1374 /*
5d3cb0f6
ZA		 1375 * Special case: TSC write with a small delta (1 second) of virtual
1376 * cycle time against real time is interpreted as an attempt to
1377 * synchronize the CPU.
1378 *
1379 * For a reliable TSC, we can match TSC offsets, and for an unstable
1380 * TSC, we add elapsed time in this computation. We could let the
1381 * compensation code attempt to catch up if we fall behind, but
1382 * it's better to try to match offsets from the beginning.
1383 */
02626b6a 1384 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1385 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1386 if (!check_tsc_unstable()) {
e26101b1 1387 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1388 pr_debug("kvm: matched tsc offset for %llu\n", data);
1389 } else {
857e4099 1390 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1391 data += delta;
1392 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1393 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1394 }
b48aa97e 1395 matched = true;
0d3da0d2 1396 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1397 } else {
1398 /*
1399 * We split periods of matched TSC writes into generations.
1400 * For each generation, we track the original measured
1401 * nanosecond time, offset, and write, so if TSCs are in
1402 * sync, we can match exact offset, and if not, we can match
4a969980 1403 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1404 *
1405 * These values are tracked in kvm->arch.cur_xxx variables.
1406 */
1407 kvm->arch.cur_tsc_generation++;
1408 kvm->arch.cur_tsc_nsec = ns;
1409 kvm->arch.cur_tsc_write = data;
1410 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1411 matched = false;
0d3da0d2 1412 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1413 kvm->arch.cur_tsc_generation, data);
f38e098f 1414 }
e26101b1
ZA		 1415
1416 /*
1417 * We also track th most recent recorded KHZ, write and time to
1418 * allow the matching interval to be extended at each write.
1419 */
f38e098f
ZA		 1420 kvm->arch.last_tsc_nsec = ns;
1421 kvm->arch.last_tsc_write = data;
5d3cb0f6 1422 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1423
b183aa58 1424 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1425
1426 /* Keep track of which generation this VCPU has synchronized to */
1427 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1428 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1429 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1430
ba904635
WA		 1431 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1432 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1433 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1434 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1435
1436 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1437 if (!matched) {
b48aa97e 1438 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1439 } else if (!already_matched) {
1440 kvm->arch.nr_vcpus_matched_tsc++;
1441 }
b48aa97e
MT		 1442
1443 kvm_track_tsc_matching(vcpu);
1444 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1445}
e26101b1 1446
99e3e30a
ZA		 1447EXPORT_SYMBOL_GPL(kvm_write_tsc);
1448
d828199e
MT		 1449#ifdef CONFIG_X86_64
1450
1451static cycle_t read_tsc(void)
1452{
03b9730b
AL		 1453 cycle_t ret = (cycle_t)rdtsc_ordered();
1454 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1455
1456 if (likely(ret >= last))
1457 return ret;
1458
1459 /*
1460 * GCC likes to generate cmov here, but this branch is extremely
1461 * predictable (it's just a funciton of time and the likely is
1462 * very likely) and there's a data dependence, so force GCC
1463 * to generate a branch instead. I don't barrier() because
1464 * we don't actually need a barrier, and if this function
1465 * ever gets inlined it will generate worse code.
1466 */
1467 asm volatile ("");
1468 return last;
1469}
1470
1471static inline u64 vgettsc(cycle_t *cycle_now)
1472{
1473 long v;
1474 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1475
1476 *cycle_now = read_tsc();
1477
1478 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1479 return v * gtod->clock.mult;
1480}
1481
cbcf2dd3 1482static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1483{
cbcf2dd3 1484 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1485 unsigned long seq;
d828199e 1486 int mode;
cbcf2dd3 1487 u64 ns;
d828199e 1488
d828199e
MT		 1489 do {
1490 seq = read_seqcount_begin(&gtod->seq);
1491 mode = gtod->clock.vclock_mode;
cbcf2dd3 1492 ns = gtod->nsec_base;
d828199e
MT		 1493 ns += vgettsc(cycle_now);
1494 ns >>= gtod->clock.shift;
cbcf2dd3 1495 ns += gtod->boot_ns;
d828199e 1496 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1497 *t = ns;
d828199e
MT		 1498
1499 return mode;
1500}
1501
1502/* returns true if host is using tsc clocksource */
1503static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1504{
d828199e
MT		 1505 /* checked again under seqlock below */
1506 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1507 return false;
1508
cbcf2dd3 1509 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1510}
1511#endif
1512
1513/*
1514 *
b48aa97e
MT		 1515 * Assuming a stable TSC across physical CPUS, and a stable TSC
1516 * across virtual CPUs, the following condition is possible.
1517 * Each numbered line represents an event visible to both
d828199e
MT		 1518 * CPUs at the next numbered event.
1519 *
1520 * "timespecX" represents host monotonic time. "tscX" represents
1521 * RDTSC value.
1522 *
1523 * VCPU0 on CPU0 | VCPU1 on CPU1
1524 *
1525 * 1. read timespec0,tsc0
1526 * 2. | timespec1 = timespec0 + N
1527 * | tsc1 = tsc0 + M
1528 * 3. transition to guest | transition to guest
1529 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1530 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1531 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1532 *
1533 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1534 *
1535 * - ret0 < ret1
1536 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1537 * ...
1538 * - 0 < N - M => M < N
1539 *
1540 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1541 * always the case (the difference between two distinct xtime instances
1542 * might be smaller then the difference between corresponding TSC reads,
1543 * when updating guest vcpus pvclock areas).
1544 *
1545 * To avoid that problem, do not allow visibility of distinct
1546 * system_timestamp/tsc_timestamp values simultaneously: use a master
1547 * copy of host monotonic time values. Update that master copy
1548 * in lockstep.
1549 *
b48aa97e 1550 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1551 *
1552 */
1553
1554static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1555{
1556#ifdef CONFIG_X86_64
1557 struct kvm_arch *ka = &kvm->arch;
1558 int vclock_mode;
b48aa97e
MT		 1559 bool host_tsc_clocksource, vcpus_matched;
1560
1561 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1562 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1563
1564 /*
1565 * If the host uses TSC clock, then passthrough TSC as stable
1566 * to the guest.
1567 */
b48aa97e 1568 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1569 &ka->master_kernel_ns,
1570 &ka->master_cycle_now);
1571
16a96021 1572 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1573 && !backwards_tsc_observed
1574 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1575
d828199e
MT		 1576 if (ka->use_master_clock)
1577 atomic_set(&kvm_guest_has_master_clock, 1);
1578
1579 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1580 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1581 vcpus_matched);
d828199e
MT		 1582#endif
1583}
1584
2e762ff7
MT		 1585static void kvm_gen_update_masterclock(struct kvm *kvm)
1586{
1587#ifdef CONFIG_X86_64
1588 int i;
1589 struct kvm_vcpu *vcpu;
1590 struct kvm_arch *ka = &kvm->arch;
1591
1592 spin_lock(&ka->pvclock_gtod_sync_lock);
1593 kvm_make_mclock_inprogress_request(kvm);
1594 /* no guest entries from this point */
1595 pvclock_update_vm_gtod_copy(kvm);
1596
1597 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1598 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1599
1600 /* guest entries allowed */
1601 kvm_for_each_vcpu(i, vcpu, kvm)
1602 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1603
1604 spin_unlock(&ka->pvclock_gtod_sync_lock);
1605#endif
1606}
1607
34c238a1 1608static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1609{
d828199e 1610 unsigned long flags, this_tsc_khz;
18068523 1611 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1612 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1613 s64 kernel_ns;
d828199e 1614 u64 tsc_timestamp, host_tsc;
0b79459b 1615 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1616 u8 pvclock_flags;
d828199e
MT		 1617 bool use_master_clock;
1618
1619 kernel_ns = 0;
1620 host_tsc = 0;
18068523 1621
d828199e
MT		 1622 /*
1623 * If the host uses TSC clock, then passthrough TSC as stable
1624 * to the guest.
1625 */
1626 spin_lock(&ka->pvclock_gtod_sync_lock);
1627 use_master_clock = ka->use_master_clock;
1628 if (use_master_clock) {
1629 host_tsc = ka->master_cycle_now;
1630 kernel_ns = ka->master_kernel_ns;
1631 }
1632 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1633
1634 /* Keep irq disabled to prevent changes to the clock */
1635 local_irq_save(flags);
89cbc767 1636 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1637 if (unlikely(this_tsc_khz == 0)) {
1638 local_irq_restore(flags);
1639 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1640 return 1;
1641 }
d828199e 1642 if (!use_master_clock) {
4ea1636b 1643 host_tsc = rdtsc();
d828199e
MT		 1644 kernel_ns = get_kernel_ns();
1645 }
1646
1647 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1648
c285545f
ZA		 1649 /*
1650 * We may have to catch up the TSC to match elapsed wall clock
1651 * time for two reasons, even if kvmclock is used.
1652 * 1) CPU could have been running below the maximum TSC rate
1653 * 2) Broken TSC compensation resets the base at each VCPU
1654 * entry to avoid unknown leaps of TSC even when running
1655 * again on the same CPU. This may cause apparent elapsed
1656 * time to disappear, and the guest to stand still or run
1657 * very slowly.
1658 */
1659 if (vcpu->tsc_catchup) {
1660 u64 tsc = compute_guest_tsc(v, kernel_ns);
1661 if (tsc > tsc_timestamp) {
f1e2b260 1662 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1663 tsc_timestamp = tsc;
1664 }
50d0a0f9
GH		 1665 }
1666
18068523
GOC		 1667 local_irq_restore(flags);
1668
0b79459b 1669 if (!vcpu->pv_time_enabled)
c285545f 1670 return 0;
18068523 1671
e48672fa 1672 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1673 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1674 &vcpu->hv_clock.tsc_shift,
1675 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1676 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1677 }
1678
1679 /* With all the info we got, fill in the values */
1d5f066e 1680 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1681 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1682 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1683
09a0c3f1
OH		 1684 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1685 &guest_hv_clock, sizeof(guest_hv_clock))))
1686 return 0;
1687
5dca0d91
RK		 1688 /* This VCPU is paused, but it's legal for a guest to read another
1689 * VCPU's kvmclock, so we really have to follow the specification where
1690 * it says that version is odd if data is being modified, and even after
1691 * it is consistent.
1692 *
1693 * Version field updates must be kept separate. This is because
1694 * kvm_write_guest_cached might use a "rep movs" instruction, and
1695 * writes within a string instruction are weakly ordered. So there
1696 * are three writes overall.
1697 *
1698 * As a small optimization, only write the version field in the first
1699 * and third write. The vcpu->pv_time cache is still valid, because the
1700 * version field is the first in the struct.
18068523 1701 */
5dca0d91
RK		 1702 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1703
1704 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1705 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1706 &vcpu->hv_clock,
1707 sizeof(vcpu->hv_clock.version));
1708
1709 smp_wmb();
78c0337a
MT		 1710
1711 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1712 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1713
1714 if (vcpu->pvclock_set_guest_stopped_request) {
1715 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1716 vcpu->pvclock_set_guest_stopped_request = false;
1717 }
1718
d828199e
MT		 1719 /* If the host uses TSC clocksource, then it is stable */
1720 if (use_master_clock)
1721 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1722
78c0337a
MT		 1723 vcpu->hv_clock.flags = pvclock_flags;
1724
ce1a5e60
DM		 1725 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1726
0b79459b
AH		 1727 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1728 &vcpu->hv_clock,
1729 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1730
1731 smp_wmb();
1732
1733 vcpu->hv_clock.version++;
1734 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1735 &vcpu->hv_clock,
1736 sizeof(vcpu->hv_clock.version));
8cfdc000 1737 return 0;
c8076604
GH		 1738}
1739
0061d53d
MT		 1740/*
1741 * kvmclock updates which are isolated to a given vcpu, such as
1742 * vcpu->cpu migration, should not allow system_timestamp from
1743 * the rest of the vcpus to remain static. Otherwise ntp frequency
1744 * correction applies to one vcpu's system_timestamp but not
1745 * the others.
1746 *
1747 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1748 * We need to rate-limit these requests though, as they can
1749 * considerably slow guests that have a large number of vcpus.
1750 * The time for a remote vcpu to update its kvmclock is bound
1751 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1752 */
1753
7e44e449
AJ		 1754#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1755
1756static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1757{
1758 int i;
7e44e449
AJ		 1759 struct delayed_work *dwork = to_delayed_work(work);
1760 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1761 kvmclock_update_work);
1762 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1763 struct kvm_vcpu *vcpu;
1764
1765 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1766 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1767 kvm_vcpu_kick(vcpu);
1768 }
1769}
1770
7e44e449
AJ		 1771static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1772{
1773 struct kvm *kvm = v->kvm;
1774
105b21bb 1775 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1776 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1777 KVMCLOCK_UPDATE_DELAY);
1778}
1779
332967a3
AJ		 1780#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1781
1782static void kvmclock_sync_fn(struct work_struct *work)
1783{
1784 struct delayed_work *dwork = to_delayed_work(work);
1785 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1786 kvmclock_sync_work);
1787 struct kvm *kvm = container_of(ka, struct kvm, arch);
1788
630994b3
MT		 1789 if (!kvmclock_periodic_sync)
1790 return;
1791
332967a3
AJ		 1792 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1793 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1794 KVMCLOCK_SYNC_PERIOD);
1795}
1796
890ca9ae 1797static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1798{
890ca9ae
HY		 1799 u64 mcg_cap = vcpu->arch.mcg_cap;
1800 unsigned bank_num = mcg_cap & 0xff;
1801
15c4a640 1802 switch (msr) {
15c4a640 1803 case MSR_IA32_MCG_STATUS:
890ca9ae 1804 vcpu->arch.mcg_status = data;
15c4a640 1805 break;
c7ac679c 1806 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1807 if (!(mcg_cap & MCG_CTL_P))
1808 return 1;
1809 if (data != 0 && data != ~(u64)0)
1810 return -1;
1811 vcpu->arch.mcg_ctl = data;
1812 break;
1813 default:
1814 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1815 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1816 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1817 /* only 0 or all 1s can be written to IA32_MCi_CTL
1818 * some Linux kernels though clear bit 10 in bank 4 to
1819 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1820 * this to avoid an uncatched #GP in the guest
1821 */
890ca9ae 1822 if ((offset & 0x3) == 0 &&
114be429 1823 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1824 return -1;
1825 vcpu->arch.mce_banks[offset] = data;
1826 break;
1827 }
1828 return 1;
1829 }
1830 return 0;
1831}
1832
ffde22ac
ES		 1833static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1834{
1835 struct kvm *kvm = vcpu->kvm;
1836 int lm = is_long_mode(vcpu);
1837 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1838 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1839 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1840 : kvm->arch.xen_hvm_config.blob_size_32;
1841 u32 page_num = data & ~PAGE_MASK;
1842 u64 page_addr = data & PAGE_MASK;
1843 u8 *page;
1844 int r;
1845
1846 r = -E2BIG;
1847 if (page_num >= blob_size)
1848 goto out;
1849 r = -ENOMEM;
ff5c2c03
SL		 1850 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1851 if (IS_ERR(page)) {
1852 r = PTR_ERR(page);
ffde22ac 1853 goto out;
ff5c2c03 1854 }
54bf36aa 1855 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1856 goto out_free;
1857 r = 0;
1858out_free:
1859 kfree(page);
1860out:
1861 return r;
1862}
1863
344d9588
GN		 1864static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1865{
1866 gpa_t gpa = data & ~0x3f;
1867
4a969980 1868 /* Bits 2:5 are reserved, Should be zero */
6adba527 1869 if (data & 0x3c)
344d9588
GN		 1870 return 1;
1871
1872 vcpu->arch.apf.msr_val = data;
1873
1874 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1875 kvm_clear_async_pf_completion_queue(vcpu);
1876 kvm_async_pf_hash_reset(vcpu);
1877 return 0;
1878 }
1879
8f964525
AH		 1880 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1881 sizeof(u32)))
344d9588
GN		 1882 return 1;
1883
6adba527 1884 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1885 kvm_async_pf_wakeup_all(vcpu);
1886 return 0;
1887}
1888
12f9a48f
GC		 1889static void kvmclock_reset(struct kvm_vcpu *vcpu)
1890{
0b79459b 1891 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1892}
1893
c9aaa895
GC		 1894static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1895{
1896 u64 delta;
1897
1898 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1899 return;
1900
1901 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1902 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1903 vcpu->arch.st.accum_steal = delta;
1904}
1905
1906static void record_steal_time(struct kvm_vcpu *vcpu)
1907{
7cae2bed
MT		 1908 accumulate_steal_time(vcpu);
1909
c9aaa895
GC		 1910 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1911 return;
1912
1913 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1914 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1915 return;
1916
1917 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1918 vcpu->arch.st.steal.version += 2;
1919 vcpu->arch.st.accum_steal = 0;
1920
1921 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1922 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1923}
1924
8fe8ab46 1925int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1926{
5753785f 1927 bool pr = false;
8fe8ab46
WA		 1928 u32 msr = msr_info->index;
1929 u64 data = msr_info->data;
5753785f 1930
15c4a640 1931 switch (msr) {
2e32b719
BP		 1932 case MSR_AMD64_NB_CFG:
1933 case MSR_IA32_UCODE_REV:
1934 case MSR_IA32_UCODE_WRITE:
1935 case MSR_VM_HSAVE_PA:
1936 case MSR_AMD64_PATCH_LOADER:
1937 case MSR_AMD64_BU_CFG2:
1938 break;
1939
15c4a640 1940 case MSR_EFER:
b69e8cae 1941 return set_efer(vcpu, data);
8f1589d9
AP		 1942 case MSR_K7_HWCR:
1943 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1944 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1945 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 1946 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 1947 if (data != 0) {
a737f256
CD		 1948 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1949 data);
8f1589d9
AP		 1950 return 1;
1951 }
15c4a640 1952 break;
f7c6d140
AP		 1953 case MSR_FAM10H_MMIO_CONF_BASE:
1954 if (data != 0) {
a737f256
CD		 1955 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1956 "0x%llx\n", data);
f7c6d140
AP		 1957 return 1;
1958 }
15c4a640 1959 break;
b5e2fec0
AG		 1960 case MSR_IA32_DEBUGCTLMSR:
1961 if (!data) {
1962 /* We support the non-activated case already */
1963 break;
1964 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1965 /* Values other than LBR and BTF are vendor-specific,
1966 thus reserved and should throw a #GP */
1967 return 1;
1968 }
a737f256
CD		 1969 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1970 __func__, data);
b5e2fec0 1971 break;
9ba075a6 1972 case 0x200 ... 0x2ff:
ff53604b 1973 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 1974 case MSR_IA32_APICBASE:
58cb628d 1975 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 1976 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1977 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1978 case MSR_IA32_TSCDEADLINE:
1979 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1980 break;
ba904635
WA		 1981 case MSR_IA32_TSC_ADJUST:
1982 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1983 if (!msr_info->host_initiated) {
d913b904 1984 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 1985 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 1986 }
1987 vcpu->arch.ia32_tsc_adjust_msr = data;
1988 }
1989 break;
15c4a640 1990 case MSR_IA32_MISC_ENABLE:
ad312c7c 1991 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1992 break;
64d60670
PB		 1993 case MSR_IA32_SMBASE:
1994 if (!msr_info->host_initiated)
1995 return 1;
1996 vcpu->arch.smbase = data;
1997 break;
11c6bffa 1998 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1999 case MSR_KVM_WALL_CLOCK:
2000 vcpu->kvm->arch.wall_clock = data;
2001 kvm_write_wall_clock(vcpu->kvm, data);
2002 break;
11c6bffa 2003 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2004 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2005 u64 gpa_offset;
54750f2c
MT		 2006 struct kvm_arch *ka = &vcpu->kvm->arch;
2007
12f9a48f 2008 kvmclock_reset(vcpu);
18068523 2009
54750f2c
MT		 2010 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2011 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2012
2013 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2014 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2015 &vcpu->requests);
2016
2017 ka->boot_vcpu_runs_old_kvmclock = tmp;
2018 }
2019
18068523 2020 vcpu->arch.time = data;
0061d53d 2021 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2022
2023 /* we verify if the enable bit is set... */
2024 if (!(data & 1))
2025 break;
2026
0b79459b 2027 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2028
0b79459b 2029 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2030 &vcpu->arch.pv_time, data & ~1ULL,
2031 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2032 vcpu->arch.pv_time_enabled = false;
2033 else
2034 vcpu->arch.pv_time_enabled = true;
32cad84f 2035
18068523
GOC		 2036 break;
2037 }
344d9588
GN		 2038 case MSR_KVM_ASYNC_PF_EN:
2039 if (kvm_pv_enable_async_pf(vcpu, data))
2040 return 1;
2041 break;
c9aaa895
GC		 2042 case MSR_KVM_STEAL_TIME:
2043
2044 if (unlikely(!sched_info_on()))
2045 return 1;
2046
2047 if (data & KVM_STEAL_RESERVED_MASK)
2048 return 1;
2049
2050 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2051 data & KVM_STEAL_VALID_BITS,
2052 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2053 return 1;
2054
2055 vcpu->arch.st.msr_val = data;
2056
2057 if (!(data & KVM_MSR_ENABLED))
2058 break;
2059
c9aaa895
GC		 2060 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2061
2062 break;
ae7a2a3f
MT		 2063 case MSR_KVM_PV_EOI_EN:
2064 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2065 return 1;
2066 break;
c9aaa895 2067
890ca9ae
HY		 2068 case MSR_IA32_MCG_CTL:
2069 case MSR_IA32_MCG_STATUS:
81760dcc 2070 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2071 return set_msr_mce(vcpu, msr, data);
71db6023 2072
6912ac32
WH		 2073 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2074 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2075 pr = true; /* fall through */
2076 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2077 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2078 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2079 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2080
2081 if (pr || data != 0)
a737f256
CD		 2082 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2083 "0x%x data 0x%llx\n", msr, data);
5753785f 2084 break;
84e0cefa
JS		 2085 case MSR_K7_CLK_CTL:
2086 /*
2087 * Ignore all writes to this no longer documented MSR.
2088 * Writes are only relevant for old K7 processors,
2089 * all pre-dating SVM, but a recommended workaround from
4a969980 2090 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2091 * affected processor models on the command line, hence
2092 * the need to ignore the workaround.
2093 */
2094 break;
55cd8e5a 2095 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2096 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2097 case HV_X64_MSR_CRASH_CTL:
2098 return kvm_hv_set_msr_common(vcpu, msr, data,
2099 msr_info->host_initiated);
91c9c3ed 2100 case MSR_IA32_BBL_CR_CTL3:
2101 /* Drop writes to this legacy MSR -- see rdmsr
2102 * counterpart for further detail.
2103 */
a737f256 2104 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2105 break;
2b036c6b
BO		 2106 case MSR_AMD64_OSVW_ID_LENGTH:
2107 if (!guest_cpuid_has_osvw(vcpu))
2108 return 1;
2109 vcpu->arch.osvw.length = data;
2110 break;
2111 case MSR_AMD64_OSVW_STATUS:
2112 if (!guest_cpuid_has_osvw(vcpu))
2113 return 1;
2114 vcpu->arch.osvw.status = data;
2115 break;
15c4a640 2116 default:
ffde22ac
ES		 2117 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2118 return xen_hvm_config(vcpu, data);
c6702c9d 2119 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2120 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2121 if (!ignore_msrs) {
a737f256
CD		 2122 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2123 msr, data);
ed85c068
AP		 2124 return 1;
2125 } else {
a737f256
CD		 2126 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2127 msr, data);
ed85c068
AP		 2128 break;
2129 }
15c4a640
CO		 2130 }
2131 return 0;
2132}
2133EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2134
2135
2136/*
2137 * Reads an msr value (of 'msr_index') into 'pdata'.
2138 * Returns 0 on success, non-0 otherwise.
2139 * Assumes vcpu_load() was already called.
2140 */
609e36d3 2141int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2142{
609e36d3 2143 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2144}
ff651cb6 2145EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2146
890ca9ae 2147static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2148{
2149 u64 data;
890ca9ae
HY		 2150 u64 mcg_cap = vcpu->arch.mcg_cap;
2151 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2152
2153 switch (msr) {
15c4a640
CO		 2154 case MSR_IA32_P5_MC_ADDR:
2155 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2156 data = 0;
2157 break;
15c4a640 2158 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2159 data = vcpu->arch.mcg_cap;
2160 break;
c7ac679c 2161 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2162 if (!(mcg_cap & MCG_CTL_P))
2163 return 1;
2164 data = vcpu->arch.mcg_ctl;
2165 break;
2166 case MSR_IA32_MCG_STATUS:
2167 data = vcpu->arch.mcg_status;
2168 break;
2169 default:
2170 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2171 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2172 u32 offset = msr - MSR_IA32_MC0_CTL;
2173 data = vcpu->arch.mce_banks[offset];
2174 break;
2175 }
2176 return 1;
2177 }
2178 *pdata = data;
2179 return 0;
2180}
2181
609e36d3 2182int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2183{
609e36d3 2184 switch (msr_info->index) {
890ca9ae 2185 case MSR_IA32_PLATFORM_ID:
15c4a640 2186 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2187 case MSR_IA32_DEBUGCTLMSR:
2188 case MSR_IA32_LASTBRANCHFROMIP:
2189 case MSR_IA32_LASTBRANCHTOIP:
2190 case MSR_IA32_LASTINTFROMIP:
2191 case MSR_IA32_LASTINTTOIP:
60af2ecd 2192 case MSR_K8_SYSCFG:
3afb1121
PB		 2193 case MSR_K8_TSEG_ADDR:
2194 case MSR_K8_TSEG_MASK:
60af2ecd 2195 case MSR_K7_HWCR:
61a6bd67 2196 case MSR_VM_HSAVE_PA:
1fdbd48c 2197 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2198 case MSR_AMD64_NB_CFG:
f7c6d140 2199 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2200 case MSR_AMD64_BU_CFG2:
609e36d3 2201 msr_info->data = 0;
15c4a640 2202 break;
6912ac32
WH		 2203 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2204 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2205 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2206 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2207 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2208 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2209 msr_info->data = 0;
5753785f 2210 break;
742bc670 2211 case MSR_IA32_UCODE_REV:
609e36d3 2212 msr_info->data = 0x100000000ULL;
742bc670 2213 break;
9ba075a6 2214 case MSR_MTRRcap:
9ba075a6 2215 case 0x200 ... 0x2ff:
ff53604b 2216 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2217 case 0xcd: /* fsb frequency */
609e36d3 2218 msr_info->data = 3;
15c4a640 2219 break;
7b914098
JS		 2220 /*
2221 * MSR_EBC_FREQUENCY_ID
2222 * Conservative value valid for even the basic CPU models.
2223 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2224 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2225 * and 266MHz for model 3, or 4. Set Core Clock
2226 * Frequency to System Bus Frequency Ratio to 1 (bits
2227 * 31:24) even though these are only valid for CPU
2228 * models > 2, however guests may end up dividing or
2229 * multiplying by zero otherwise.
2230 */
2231 case MSR_EBC_FREQUENCY_ID:
609e36d3 2232 msr_info->data = 1 << 24;
7b914098 2233 break;
15c4a640 2234 case MSR_IA32_APICBASE:
609e36d3 2235 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2236 break;
0105d1a5 2237 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2238 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2239 break;
a3e06bbe 2240 case MSR_IA32_TSCDEADLINE:
609e36d3 2241 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2242 break;
ba904635 2243 case MSR_IA32_TSC_ADJUST:
609e36d3 2244 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2245 break;
15c4a640 2246 case MSR_IA32_MISC_ENABLE:
609e36d3 2247 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2248 break;
64d60670
PB		 2249 case MSR_IA32_SMBASE:
2250 if (!msr_info->host_initiated)
2251 return 1;
2252 msr_info->data = vcpu->arch.smbase;
15c4a640 2253 break;
847f0ad8
AG		 2254 case MSR_IA32_PERF_STATUS:
2255 /* TSC increment by tick */
609e36d3 2256 msr_info->data = 1000ULL;
847f0ad8 2257 /* CPU multiplier */
b0996ae4 2258 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2259 break;
15c4a640 2260 case MSR_EFER:
609e36d3 2261 msr_info->data = vcpu->arch.efer;
15c4a640 2262 break;
18068523 2263 case MSR_KVM_WALL_CLOCK:
11c6bffa 2264 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2265 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2266 break;
2267 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2268 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2269 msr_info->data = vcpu->arch.time;
18068523 2270 break;
344d9588 2271 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2272 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2273 break;
c9aaa895 2274 case MSR_KVM_STEAL_TIME:
609e36d3 2275 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2276 break;
1d92128f 2277 case MSR_KVM_PV_EOI_EN:
609e36d3 2278 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2279 break;
890ca9ae
HY		 2280 case MSR_IA32_P5_MC_ADDR:
2281 case MSR_IA32_P5_MC_TYPE:
2282 case MSR_IA32_MCG_CAP:
2283 case MSR_IA32_MCG_CTL:
2284 case MSR_IA32_MCG_STATUS:
81760dcc 2285 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2286 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2287 case MSR_K7_CLK_CTL:
2288 /*
2289 * Provide expected ramp-up count for K7. All other
2290 * are set to zero, indicating minimum divisors for
2291 * every field.
2292 *
2293 * This prevents guest kernels on AMD host with CPU
2294 * type 6, model 8 and higher from exploding due to
2295 * the rdmsr failing.
2296 */
609e36d3 2297 msr_info->data = 0x20000000;
84e0cefa 2298 break;
55cd8e5a 2299 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2300 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2301 case HV_X64_MSR_CRASH_CTL:
e83d5887
AS		 2302 return kvm_hv_get_msr_common(vcpu,
2303 msr_info->index, &msr_info->data);
55cd8e5a 2304 break;
91c9c3ed 2305 case MSR_IA32_BBL_CR_CTL3:
2306 /* This legacy MSR exists but isn't fully documented in current
2307 * silicon. It is however accessed by winxp in very narrow
2308 * scenarios where it sets bit #19, itself documented as
2309 * a "reserved" bit. Best effort attempt to source coherent
2310 * read data here should the balance of the register be
2311 * interpreted by the guest:
2312 *
2313 * L2 cache control register 3: 64GB range, 256KB size,
2314 * enabled, latency 0x1, configured
2315 */
609e36d3 2316 msr_info->data = 0xbe702111;
91c9c3ed 2317 break;
2b036c6b
BO		 2318 case MSR_AMD64_OSVW_ID_LENGTH:
2319 if (!guest_cpuid_has_osvw(vcpu))
2320 return 1;
609e36d3 2321 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2322 break;
2323 case MSR_AMD64_OSVW_STATUS:
2324 if (!guest_cpuid_has_osvw(vcpu))
2325 return 1;
609e36d3 2326 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2327 break;
15c4a640 2328 default:
c6702c9d 2329 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2330 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2331 if (!ignore_msrs) {
609e36d3 2332 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2333 return 1;
2334 } else {
609e36d3
PB		 2335 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2336 msr_info->data = 0;
ed85c068
AP		 2337 }
2338 break;
15c4a640 2339 }
15c4a640
CO		 2340 return 0;
2341}
2342EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2343
313a3dc7
CO		 2344/*
2345 * Read or write a bunch of msrs. All parameters are kernel addresses.
2346 *
2347 * @return number of msrs set successfully.
2348 */
2349static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2350 struct kvm_msr_entry *entries,
2351 int (*do_msr)(struct kvm_vcpu *vcpu,
2352 unsigned index, u64 *data))
2353{
f656ce01 2354 int i, idx;
313a3dc7 2355
f656ce01 2356 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2357 for (i = 0; i < msrs->nmsrs; ++i)
2358 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2359 break;
f656ce01 2360 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2361
313a3dc7
CO		 2362 return i;
2363}
2364
2365/*
2366 * Read or write a bunch of msrs. Parameters are user addresses.
2367 *
2368 * @return number of msrs set successfully.
2369 */
2370static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2371 int (*do_msr)(struct kvm_vcpu *vcpu,
2372 unsigned index, u64 *data),
2373 int writeback)
2374{
2375 struct kvm_msrs msrs;
2376 struct kvm_msr_entry *entries;
2377 int r, n;
2378 unsigned size;
2379
2380 r = -EFAULT;
2381 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2382 goto out;
2383
2384 r = -E2BIG;
2385 if (msrs.nmsrs >= MAX_IO_MSRS)
2386 goto out;
2387
313a3dc7 2388 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2389 entries = memdup_user(user_msrs->entries, size);
2390 if (IS_ERR(entries)) {
2391 r = PTR_ERR(entries);
313a3dc7 2392 goto out;
ff5c2c03 2393 }
313a3dc7
CO		 2394
2395 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2396 if (r < 0)
2397 goto out_free;
2398
2399 r = -EFAULT;
2400 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2401 goto out_free;
2402
2403 r = n;
2404
2405out_free:
7a73c028 2406 kfree(entries);
313a3dc7
CO		 2407out:
2408 return r;
2409}
2410
784aa3d7 2411int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2412{
2413 int r;
2414
2415 switch (ext) {
2416 case KVM_CAP_IRQCHIP:
2417 case KVM_CAP_HLT:
2418 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2419 case KVM_CAP_SET_TSS_ADDR:
07716717 2420 case KVM_CAP_EXT_CPUID:
9c15bb1d 2421 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2422 case KVM_CAP_CLOCKSOURCE:
7837699f 2423 case KVM_CAP_PIT:
a28e4f5a 2424 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2425 case KVM_CAP_MP_STATE:
ed848624 2426 case KVM_CAP_SYNC_MMU:
a355c85c 2427 case KVM_CAP_USER_NMI:
52d939a0 2428 case KVM_CAP_REINJECT_CONTROL:
4925663a 2429 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2430 case KVM_CAP_IOEVENTFD:
f848a5a8 2431 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2432 case KVM_CAP_PIT2:
e9f42757 2433 case KVM_CAP_PIT_STATE2:
b927a3ce 2434 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2435 case KVM_CAP_XEN_HVM:
afbcf7ab 2436 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2437 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2438 case KVM_CAP_HYPERV:
10388a07 2439 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2440 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2441 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2442 case KVM_CAP_DEBUGREGS:
d2be1651 2443 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2444 case KVM_CAP_XSAVE:
344d9588 2445 case KVM_CAP_ASYNC_PF:
92a1f12d 2446 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2447 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2448 case KVM_CAP_READONLY_MEM:
5f66b620 2449 case KVM_CAP_HYPERV_TIME:
100943c5 2450 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2451 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2452 case KVM_CAP_ENABLE_CAP_VM:
2453 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2454 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2455 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2456#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2457 case KVM_CAP_ASSIGN_DEV_IRQ:
2458 case KVM_CAP_PCI_2_3:
2459#endif
018d00d2
ZX		 2460 r = 1;
2461 break;
6d396b55
PB		 2462 case KVM_CAP_X86_SMM:
2463 /* SMBASE is usually relocated above 1M on modern chipsets,
2464 * and SMM handlers might indeed rely on 4G segment limits,
2465 * so do not report SMM to be available if real mode is
2466 * emulated via vm86 mode. Still, do not go to great lengths
2467 * to avoid userspace's usage of the feature, because it is a
2468 * fringe case that is not enabled except via specific settings
2469 * of the module parameters.
2470 */
2471 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2472 break;
542472b5
LV		 2473 case KVM_CAP_COALESCED_MMIO:
2474 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2475 break;
774ead3a
AK		 2476 case KVM_CAP_VAPIC:
2477 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2478 break;
f725230a 2479 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2480 r = KVM_SOFT_MAX_VCPUS;
2481 break;
2482 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2483 r = KVM_MAX_VCPUS;
2484 break;
a988b910 2485 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2486 r = KVM_USER_MEM_SLOTS;
a988b910 2487 break;
a68a6a72
MT		 2488 case KVM_CAP_PV_MMU: /* obsolete */
2489 r = 0;
2f333bcb 2490 break;
4cee4b72 2491#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2492 case KVM_CAP_IOMMU:
a1b60c1c 2493 r = iommu_present(&pci_bus_type);
62c476c7 2494 break;
4cee4b72 2495#endif
890ca9ae
HY		 2496 case KVM_CAP_MCE:
2497 r = KVM_MAX_MCE_BANKS;
2498 break;
2d5b5a66
SY		 2499 case KVM_CAP_XCRS:
2500 r = cpu_has_xsave;
2501 break;
92a1f12d
JR		 2502 case KVM_CAP_TSC_CONTROL:
2503 r = kvm_has_tsc_control;
2504 break;
018d00d2
ZX		 2505 default:
2506 r = 0;
2507 break;
2508 }
2509 return r;
2510
2511}
2512
043405e1
CO		 2513long kvm_arch_dev_ioctl(struct file *filp,
2514 unsigned int ioctl, unsigned long arg)
2515{
2516 void __user *argp = (void __user *)arg;
2517 long r;
2518
2519 switch (ioctl) {
2520 case KVM_GET_MSR_INDEX_LIST: {
2521 struct kvm_msr_list __user *user_msr_list = argp;
2522 struct kvm_msr_list msr_list;
2523 unsigned n;
2524
2525 r = -EFAULT;
2526 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2527 goto out;
2528 n = msr_list.nmsrs;
62ef68bb 2529 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2530 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2531 goto out;
2532 r = -E2BIG;
e125e7b6 2533 if (n < msr_list.nmsrs)
043405e1
CO		 2534 goto out;
2535 r = -EFAULT;
2536 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2537 num_msrs_to_save * sizeof(u32)))
2538 goto out;
e125e7b6 2539 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2540 &emulated_msrs,
62ef68bb 2541 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2542 goto out;
2543 r = 0;
2544 break;
2545 }
9c15bb1d
BP		 2546 case KVM_GET_SUPPORTED_CPUID:
2547 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2548 struct kvm_cpuid2 __user *cpuid_arg = argp;
2549 struct kvm_cpuid2 cpuid;
2550
2551 r = -EFAULT;
2552 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2553 goto out;
9c15bb1d
BP		 2554
2555 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2556 ioctl);
674eea0f
AK		 2557 if (r)
2558 goto out;
2559
2560 r = -EFAULT;
2561 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2562 goto out;
2563 r = 0;
2564 break;
2565 }
890ca9ae
HY		 2566 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2567 u64 mce_cap;
2568
2569 mce_cap = KVM_MCE_CAP_SUPPORTED;
2570 r = -EFAULT;
2571 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2572 goto out;
2573 r = 0;
2574 break;
2575 }
043405e1
CO		 2576 default:
2577 r = -EINVAL;
2578 }
2579out:
2580 return r;
2581}
2582
f5f48ee1
SY		 2583static void wbinvd_ipi(void *garbage)
2584{
2585 wbinvd();
2586}
2587
2588static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2589{
e0f0bbc5 2590 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2591}
2592
313a3dc7
CO		 2593void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2594{
f5f48ee1
SY		 2595 /* Address WBINVD may be executed by guest */
2596 if (need_emulate_wbinvd(vcpu)) {
2597 if (kvm_x86_ops->has_wbinvd_exit())
2598 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2599 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2600 smp_call_function_single(vcpu->cpu,
2601 wbinvd_ipi, NULL, 1);
2602 }
2603
313a3dc7 2604 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2605
0dd6a6ed
ZA		 2606 /* Apply any externally detected TSC adjustments (due to suspend) */
2607 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2608 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2609 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2610 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2611 }
8f6055cb 2612
48434c20 2613 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2614 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2615 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2616 if (tsc_delta < 0)
2617 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2618 if (check_tsc_unstable()) {
b183aa58
ZA		 2619 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2620 vcpu->arch.last_guest_tsc);
2621 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2622 vcpu->arch.tsc_catchup = 1;
c285545f 2623 }
d98d07ca
MT		 2624 /*
2625 * On a host with synchronized TSC, there is no need to update
2626 * kvmclock on vcpu->cpu migration
2627 */
2628 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2629 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2630 if (vcpu->cpu != cpu)
2631 kvm_migrate_timers(vcpu);
e48672fa 2632 vcpu->cpu = cpu;
6b7d7e76 2633 }
c9aaa895 2634
c9aaa895 2635 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2636}
2637
2638void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2639{
02daab21 2640 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2641 kvm_put_guest_fpu(vcpu);
4ea1636b 2642 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2643}
2644
313a3dc7
CO		 2645static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2646 struct kvm_lapic_state *s)
2647{
5a71785d 2648 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2649 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2650
2651 return 0;
2652}
2653
2654static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2655 struct kvm_lapic_state *s)
2656{
64eb0620 2657 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2658 update_cr8_intercept(vcpu);
313a3dc7
CO		 2659
2660 return 0;
2661}
2662
f77bc6a4
ZX		 2663static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2664 struct kvm_interrupt *irq)
2665{
02cdb50f 2666 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2667 return -EINVAL;
1c1a9ce9
SR		 2668
2669 if (!irqchip_in_kernel(vcpu->kvm)) {
2670 kvm_queue_interrupt(vcpu, irq->irq, false);
2671 kvm_make_request(KVM_REQ_EVENT, vcpu);
2672 return 0;
2673 }
2674
2675 /*
2676 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2677 * fail for in-kernel 8259.
2678 */
2679 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2680 return -ENXIO;
f77bc6a4 2681
1c1a9ce9
SR		 2682 if (vcpu->arch.pending_external_vector != -1)
2683 return -EEXIST;
f77bc6a4 2684
1c1a9ce9 2685 vcpu->arch.pending_external_vector = irq->irq;
f77bc6a4
ZX		 2686 return 0;
2687}
2688
c4abb7c9
JK		 2689static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2690{
c4abb7c9 2691 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2692
2693 return 0;
2694}
2695
f077825a
PB		 2696static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2697{
64d60670
PB		 2698 kvm_make_request(KVM_REQ_SMI, vcpu);
2699
f077825a
PB		 2700 return 0;
2701}
2702
b209749f
AK		 2703static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2704 struct kvm_tpr_access_ctl *tac)
2705{
2706 if (tac->flags)
2707 return -EINVAL;
2708 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2709 return 0;
2710}
2711
890ca9ae
HY		 2712static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2713 u64 mcg_cap)
2714{
2715 int r;
2716 unsigned bank_num = mcg_cap & 0xff, bank;
2717
2718 r = -EINVAL;
a9e38c3e 2719 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2720 goto out;
2721 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2722 goto out;
2723 r = 0;
2724 vcpu->arch.mcg_cap = mcg_cap;
2725 /* Init IA32_MCG_CTL to all 1s */
2726 if (mcg_cap & MCG_CTL_P)
2727 vcpu->arch.mcg_ctl = ~(u64)0;
2728 /* Init IA32_MCi_CTL to all 1s */
2729 for (bank = 0; bank < bank_num; bank++)
2730 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2731out:
2732 return r;
2733}
2734
2735static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2736 struct kvm_x86_mce *mce)
2737{
2738 u64 mcg_cap = vcpu->arch.mcg_cap;
2739 unsigned bank_num = mcg_cap & 0xff;
2740 u64 *banks = vcpu->arch.mce_banks;
2741
2742 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2743 return -EINVAL;
2744 /*
2745 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2746 * reporting is disabled
2747 */
2748 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2749 vcpu->arch.mcg_ctl != ~(u64)0)
2750 return 0;
2751 banks += 4 * mce->bank;
2752 /*
2753 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2754 * reporting is disabled for the bank
2755 */
2756 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2757 return 0;
2758 if (mce->status & MCI_STATUS_UC) {
2759 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2760 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2761 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2762 return 0;
2763 }
2764 if (banks[1] & MCI_STATUS_VAL)
2765 mce->status |= MCI_STATUS_OVER;
2766 banks[2] = mce->addr;
2767 banks[3] = mce->misc;
2768 vcpu->arch.mcg_status = mce->mcg_status;
2769 banks[1] = mce->status;
2770 kvm_queue_exception(vcpu, MC_VECTOR);
2771 } else if (!(banks[1] & MCI_STATUS_VAL)
2772 || !(banks[1] & MCI_STATUS_UC)) {
2773 if (banks[1] & MCI_STATUS_VAL)
2774 mce->status |= MCI_STATUS_OVER;
2775 banks[2] = mce->addr;
2776 banks[3] = mce->misc;
2777 banks[1] = mce->status;
2778 } else
2779 banks[1] |= MCI_STATUS_OVER;
2780 return 0;
2781}
2782
3cfc3092
JK		 2783static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2784 struct kvm_vcpu_events *events)
2785{
7460fb4a 2786 process_nmi(vcpu);
03b82a30
JK		 2787 events->exception.injected =
2788 vcpu->arch.exception.pending &&
2789 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2790 events->exception.nr = vcpu->arch.exception.nr;
2791 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2792 events->exception.pad = 0;
3cfc3092
JK		 2793 events->exception.error_code = vcpu->arch.exception.error_code;
2794
03b82a30
JK		 2795 events->interrupt.injected =
2796 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2797 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2798 events->interrupt.soft = 0;
37ccdcbe 2799 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2800
2801 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2802 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2803 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2804 events->nmi.pad = 0;
3cfc3092 2805
66450a21 2806 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2807
f077825a
PB		 2808 events->smi.smm = is_smm(vcpu);
2809 events->smi.pending = vcpu->arch.smi_pending;
2810 events->smi.smm_inside_nmi =
2811 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2812 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2813
dab4b911 2814 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2815 | KVM_VCPUEVENT_VALID_SHADOW
2816 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2817 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2818}
2819
2820static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2821 struct kvm_vcpu_events *events)
2822{
dab4b911 2823 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2824 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2825 | KVM_VCPUEVENT_VALID_SHADOW
2826 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2827 return -EINVAL;
2828
7460fb4a 2829 process_nmi(vcpu);
3cfc3092
JK		 2830 vcpu->arch.exception.pending = events->exception.injected;
2831 vcpu->arch.exception.nr = events->exception.nr;
2832 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2833 vcpu->arch.exception.error_code = events->exception.error_code;
2834
2835 vcpu->arch.interrupt.pending = events->interrupt.injected;
2836 vcpu->arch.interrupt.nr = events->interrupt.nr;
2837 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2838 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2839 kvm_x86_ops->set_interrupt_shadow(vcpu,
2840 events->interrupt.shadow);
3cfc3092
JK		 2841
2842 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2843 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2844 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2845 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2846
66450a21
JK		 2847 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2848 kvm_vcpu_has_lapic(vcpu))
2849 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2850
f077825a
PB		 2851 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2852 if (events->smi.smm)
2853 vcpu->arch.hflags |= HF_SMM_MASK;
2854 else
2855 vcpu->arch.hflags &= ~HF_SMM_MASK;
2856 vcpu->arch.smi_pending = events->smi.pending;
2857 if (events->smi.smm_inside_nmi)
2858 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2859 else
2860 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2861 if (kvm_vcpu_has_lapic(vcpu)) {
2862 if (events->smi.latched_init)
2863 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2864 else
2865 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2866 }
2867 }
2868
3842d135
AK		 2869 kvm_make_request(KVM_REQ_EVENT, vcpu);
2870
3cfc3092
JK		 2871 return 0;
2872}
2873
a1efbe77
JK		 2874static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2875 struct kvm_debugregs *dbgregs)
2876{
73aaf249
JK		 2877 unsigned long val;
2878
a1efbe77 2879 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 2880 kvm_get_dr(vcpu, 6, &val);
73aaf249 2881 dbgregs->dr6 = val;
a1efbe77
JK		 2882 dbgregs->dr7 = vcpu->arch.dr7;
2883 dbgregs->flags = 0;
97e69aa6 2884 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2885}
2886
2887static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2888 struct kvm_debugregs *dbgregs)
2889{
2890 if (dbgregs->flags)
2891 return -EINVAL;
2892
a1efbe77 2893 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 2894 kvm_update_dr0123(vcpu);
a1efbe77 2895 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 2896 kvm_update_dr6(vcpu);
a1efbe77 2897 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 2898 kvm_update_dr7(vcpu);
a1efbe77 2899
a1efbe77
JK		 2900 return 0;
2901}
2902
df1daba7
PB		 2903#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
2904
2905static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
2906{
c47ada30 2907 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 2908 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 2909 u64 valid;
2910
2911 /*
2912 * Copy legacy XSAVE area, to avoid complications with CPUID
2913 * leaves 0 and 1 in the loop below.
2914 */
2915 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
2916
2917 /* Set XSTATE_BV */
2918 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
2919
2920 /*
2921 * Copy each region from the possibly compacted offset to the
2922 * non-compacted offset.
2923 */
2924 valid = xstate_bv & ~XSTATE_FPSSE;
2925 while (valid) {
2926 u64 feature = valid & -valid;
2927 int index = fls64(feature) - 1;
2928 void *src = get_xsave_addr(xsave, feature);
2929
2930 if (src) {
2931 u32 size, offset, ecx, edx;
2932 cpuid_count(XSTATE_CPUID, index,
2933 &size, &offset, &ecx, &edx);
2934 memcpy(dest + offset, src, size);
2935 }
2936
2937 valid -= feature;
2938 }
2939}
2940
2941static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
2942{
c47ada30 2943 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 2944 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
2945 u64 valid;
2946
2947 /*
2948 * Copy legacy XSAVE area, to avoid complications with CPUID
2949 * leaves 0 and 1 in the loop below.
2950 */
2951 memcpy(xsave, src, XSAVE_HDR_OFFSET);
2952
2953 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 2954 xsave->header.xfeatures = xstate_bv;
df1daba7 2955 if (cpu_has_xsaves)
3a54450b 2956 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 2957
2958 /*
2959 * Copy each region from the non-compacted offset to the
2960 * possibly compacted offset.
2961 */
2962 valid = xstate_bv & ~XSTATE_FPSSE;
2963 while (valid) {
2964 u64 feature = valid & -valid;
2965 int index = fls64(feature) - 1;
2966 void *dest = get_xsave_addr(xsave, feature);
2967
2968 if (dest) {
2969 u32 size, offset, ecx, edx;
2970 cpuid_count(XSTATE_CPUID, index,
2971 &size, &offset, &ecx, &edx);
2972 memcpy(dest, src + offset, size);
ee4100da 2973 }
df1daba7
PB		 2974
2975 valid -= feature;
2976 }
2977}
2978
2d5b5a66
SY		 2979static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2980 struct kvm_xsave *guest_xsave)
2981{
4344ee98 2982 if (cpu_has_xsave) {
df1daba7
PB		 2983 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
2984 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 2985 } else {
2d5b5a66 2986 memcpy(guest_xsave->region,
7366ed77 2987 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 2988 sizeof(struct fxregs_state));
2d5b5a66
SY		 2989 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2990 XSTATE_FPSSE;
2991 }
2992}
2993
2994static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2995 struct kvm_xsave *guest_xsave)
2996{
2997 u64 xstate_bv =
2998 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2999
d7876f1b
PB		 3000 if (cpu_has_xsave) {
3001 /*
3002 * Here we allow setting states that are not present in
3003 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3004 * with old userspace.
3005 */
4ff41732 3006 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3007 return -EINVAL;
df1daba7 3008 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3009 } else {
2d5b5a66
SY		 3010 if (xstate_bv & ~XSTATE_FPSSE)
3011 return -EINVAL;
7366ed77 3012 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3013 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3014 }
3015 return 0;
3016}
3017
3018static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3019 struct kvm_xcrs *guest_xcrs)
3020{
3021 if (!cpu_has_xsave) {
3022 guest_xcrs->nr_xcrs = 0;
3023 return;
3024 }
3025
3026 guest_xcrs->nr_xcrs = 1;
3027 guest_xcrs->flags = 0;
3028 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3029 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3030}
3031
3032static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3033 struct kvm_xcrs *guest_xcrs)
3034{
3035 int i, r = 0;
3036
3037 if (!cpu_has_xsave)
3038 return -EINVAL;
3039
3040 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3041 return -EINVAL;
3042
3043 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3044 /* Only support XCR0 currently */
c67a04cb 3045 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3046 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3047 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3048 break;
3049 }
3050 if (r)
3051 r = -EINVAL;
3052 return r;
3053}
3054
1c0b28c2
EM		 3055/*
3056 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3057 * stopped by the hypervisor. This function will be called from the host only.
3058 * EINVAL is returned when the host attempts to set the flag for a guest that
3059 * does not support pv clocks.
3060 */
3061static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3062{
0b79459b 3063 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3064 return -EINVAL;
51d59c6b 3065 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3066 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3067 return 0;
3068}
3069
313a3dc7
CO		 3070long kvm_arch_vcpu_ioctl(struct file *filp,
3071 unsigned int ioctl, unsigned long arg)
3072{
3073 struct kvm_vcpu *vcpu = filp->private_data;
3074 void __user *argp = (void __user *)arg;
3075 int r;
d1ac91d8
AK		 3076 union {
3077 struct kvm_lapic_state *lapic;
3078 struct kvm_xsave *xsave;
3079 struct kvm_xcrs *xcrs;
3080 void *buffer;
3081 } u;
3082
3083 u.buffer = NULL;
313a3dc7
CO		 3084 switch (ioctl) {
3085 case KVM_GET_LAPIC: {
2204ae3c
MT		 3086 r = -EINVAL;
3087 if (!vcpu->arch.apic)
3088 goto out;
d1ac91d8 3089 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3090
b772ff36 3091 r = -ENOMEM;
d1ac91d8 3092 if (!u.lapic)
b772ff36 3093 goto out;
d1ac91d8 3094 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3095 if (r)
3096 goto out;
3097 r = -EFAULT;
d1ac91d8 3098 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3099 goto out;
3100 r = 0;
3101 break;
3102 }
3103 case KVM_SET_LAPIC: {
2204ae3c
MT		 3104 r = -EINVAL;
3105 if (!vcpu->arch.apic)
3106 goto out;
ff5c2c03 3107 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3108 if (IS_ERR(u.lapic))
3109 return PTR_ERR(u.lapic);
ff5c2c03 3110
d1ac91d8 3111 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3112 break;
3113 }
f77bc6a4
ZX		 3114 case KVM_INTERRUPT: {
3115 struct kvm_interrupt irq;
3116
3117 r = -EFAULT;
3118 if (copy_from_user(&irq, argp, sizeof irq))
3119 goto out;
3120 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3121 break;
3122 }
c4abb7c9
JK		 3123 case KVM_NMI: {
3124 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3125 break;
3126 }
f077825a
PB		 3127 case KVM_SMI: {
3128 r = kvm_vcpu_ioctl_smi(vcpu);
3129 break;
3130 }
313a3dc7
CO		 3131 case KVM_SET_CPUID: {
3132 struct kvm_cpuid __user *cpuid_arg = argp;
3133 struct kvm_cpuid cpuid;
3134
3135 r = -EFAULT;
3136 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3137 goto out;
3138 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3139 break;
3140 }
07716717
DK		 3141 case KVM_SET_CPUID2: {
3142 struct kvm_cpuid2 __user *cpuid_arg = argp;
3143 struct kvm_cpuid2 cpuid;
3144
3145 r = -EFAULT;
3146 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3147 goto out;
3148 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3149 cpuid_arg->entries);
07716717
DK		 3150 break;
3151 }
3152 case KVM_GET_CPUID2: {
3153 struct kvm_cpuid2 __user *cpuid_arg = argp;
3154 struct kvm_cpuid2 cpuid;
3155
3156 r = -EFAULT;
3157 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3158 goto out;
3159 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3160 cpuid_arg->entries);
07716717
DK		 3161 if (r)
3162 goto out;
3163 r = -EFAULT;
3164 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3165 goto out;
3166 r = 0;
3167 break;
3168 }
313a3dc7 3169 case KVM_GET_MSRS:
609e36d3 3170 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3171 break;
3172 case KVM_SET_MSRS:
3173 r = msr_io(vcpu, argp, do_set_msr, 0);
3174 break;
b209749f
AK		 3175 case KVM_TPR_ACCESS_REPORTING: {
3176 struct kvm_tpr_access_ctl tac;
3177
3178 r = -EFAULT;
3179 if (copy_from_user(&tac, argp, sizeof tac))
3180 goto out;
3181 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3182 if (r)
3183 goto out;
3184 r = -EFAULT;
3185 if (copy_to_user(argp, &tac, sizeof tac))
3186 goto out;
3187 r = 0;
3188 break;
3189 };
b93463aa
AK		 3190 case KVM_SET_VAPIC_ADDR: {
3191 struct kvm_vapic_addr va;
3192
3193 r = -EINVAL;
35754c98 3194 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3195 goto out;
3196 r = -EFAULT;
3197 if (copy_from_user(&va, argp, sizeof va))
3198 goto out;
fda4e2e8 3199 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3200 break;
3201 }
890ca9ae
HY		 3202 case KVM_X86_SETUP_MCE: {
3203 u64 mcg_cap;
3204
3205 r = -EFAULT;
3206 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3207 goto out;
3208 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3209 break;
3210 }
3211 case KVM_X86_SET_MCE: {
3212 struct kvm_x86_mce mce;
3213
3214 r = -EFAULT;
3215 if (copy_from_user(&mce, argp, sizeof mce))
3216 goto out;
3217 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3218 break;
3219 }
3cfc3092
JK		 3220 case KVM_GET_VCPU_EVENTS: {
3221 struct kvm_vcpu_events events;
3222
3223 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3224
3225 r = -EFAULT;
3226 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3227 break;
3228 r = 0;
3229 break;
3230 }
3231 case KVM_SET_VCPU_EVENTS: {
3232 struct kvm_vcpu_events events;
3233
3234 r = -EFAULT;
3235 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3236 break;
3237
3238 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3239 break;
3240 }
a1efbe77
JK		 3241 case KVM_GET_DEBUGREGS: {
3242 struct kvm_debugregs dbgregs;
3243
3244 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3245
3246 r = -EFAULT;
3247 if (copy_to_user(argp, &dbgregs,
3248 sizeof(struct kvm_debugregs)))
3249 break;
3250 r = 0;
3251 break;
3252 }
3253 case KVM_SET_DEBUGREGS: {
3254 struct kvm_debugregs dbgregs;
3255
3256 r = -EFAULT;
3257 if (copy_from_user(&dbgregs, argp,
3258 sizeof(struct kvm_debugregs)))
3259 break;
3260
3261 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3262 break;
3263 }
2d5b5a66 3264 case KVM_GET_XSAVE: {
d1ac91d8 3265 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3266 r = -ENOMEM;
d1ac91d8 3267 if (!u.xsave)
2d5b5a66
SY		 3268 break;
3269
d1ac91d8 3270 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3271
3272 r = -EFAULT;
d1ac91d8 3273 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3274 break;
3275 r = 0;
3276 break;
3277 }
3278 case KVM_SET_XSAVE: {
ff5c2c03 3279 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3280 if (IS_ERR(u.xsave))
3281 return PTR_ERR(u.xsave);
2d5b5a66 3282
d1ac91d8 3283 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3284 break;
3285 }
3286 case KVM_GET_XCRS: {
d1ac91d8 3287 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3288 r = -ENOMEM;
d1ac91d8 3289 if (!u.xcrs)
2d5b5a66
SY		 3290 break;
3291
d1ac91d8 3292 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3293
3294 r = -EFAULT;
d1ac91d8 3295 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3296 sizeof(struct kvm_xcrs)))
3297 break;
3298 r = 0;
3299 break;
3300 }
3301 case KVM_SET_XCRS: {
ff5c2c03 3302 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3303 if (IS_ERR(u.xcrs))
3304 return PTR_ERR(u.xcrs);
2d5b5a66 3305
d1ac91d8 3306 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3307 break;
3308 }
92a1f12d
JR		 3309 case KVM_SET_TSC_KHZ: {
3310 u32 user_tsc_khz;
3311
3312 r = -EINVAL;
92a1f12d
JR		 3313 user_tsc_khz = (u32)arg;
3314
3315 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3316 goto out;
3317
cc578287
ZA		 3318 if (user_tsc_khz == 0)
3319 user_tsc_khz = tsc_khz;
3320
3321 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3322
3323 r = 0;
3324 goto out;
3325 }
3326 case KVM_GET_TSC_KHZ: {
cc578287 3327 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3328 goto out;
3329 }
1c0b28c2
EM		 3330 case KVM_KVMCLOCK_CTRL: {
3331 r = kvm_set_guest_paused(vcpu);
3332 goto out;
3333 }
313a3dc7
CO		 3334 default:
3335 r = -EINVAL;
3336 }
3337out:
d1ac91d8 3338 kfree(u.buffer);
313a3dc7
CO		 3339 return r;
3340}
3341
5b1c1493
CO		 3342int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3343{
3344 return VM_FAULT_SIGBUS;
3345}
3346
1fe779f8
CO		 3347static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3348{
3349 int ret;
3350
3351 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3352 return -EINVAL;
1fe779f8
CO		 3353 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3354 return ret;
3355}
3356
b927a3ce
SY		 3357static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3358 u64 ident_addr)
3359{
3360 kvm->arch.ept_identity_map_addr = ident_addr;
3361 return 0;
3362}
3363
1fe779f8
CO		 3364static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3365 u32 kvm_nr_mmu_pages)
3366{
3367 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3368 return -EINVAL;
3369
79fac95e 3370 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3371
3372 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3373 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3374
79fac95e 3375 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3376 return 0;
3377}
3378
3379static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3380{
39de71ec 3381 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3382}
3383
1fe779f8
CO		 3384static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3385{
3386 int r;
3387
3388 r = 0;
3389 switch (chip->chip_id) {
3390 case KVM_IRQCHIP_PIC_MASTER:
3391 memcpy(&chip->chip.pic,
3392 &pic_irqchip(kvm)->pics[0],
3393 sizeof(struct kvm_pic_state));
3394 break;
3395 case KVM_IRQCHIP_PIC_SLAVE:
3396 memcpy(&chip->chip.pic,
3397 &pic_irqchip(kvm)->pics[1],
3398 sizeof(struct kvm_pic_state));
3399 break;
3400 case KVM_IRQCHIP_IOAPIC:
eba0226b 3401 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3402 break;
3403 default:
3404 r = -EINVAL;
3405 break;
3406 }
3407 return r;
3408}
3409
3410static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3411{
3412 int r;
3413
3414 r = 0;
3415 switch (chip->chip_id) {
3416 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3417 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3418 memcpy(&pic_irqchip(kvm)->pics[0],
3419 &chip->chip.pic,
3420 sizeof(struct kvm_pic_state));
f4f51050 3421 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3422 break;
3423 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3424 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3425 memcpy(&pic_irqchip(kvm)->pics[1],
3426 &chip->chip.pic,
3427 sizeof(struct kvm_pic_state));
f4f51050 3428 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3429 break;
3430 case KVM_IRQCHIP_IOAPIC:
eba0226b 3431 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3432 break;
3433 default:
3434 r = -EINVAL;
3435 break;
3436 }
3437 kvm_pic_update_irq(pic_irqchip(kvm));
3438 return r;
3439}
3440
e0f63cb9
SY		 3441static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3442{
894a9c55 3443 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3444 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3445 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3446 return 0;
e0f63cb9
SY		 3447}
3448
3449static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3450{
894a9c55 3451 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3452 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3453 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3454 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3455 return 0;
e9f42757
BK		 3456}
3457
3458static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3459{
e9f42757
BK		 3460 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3461 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3462 sizeof(ps->channels));
3463 ps->flags = kvm->arch.vpit->pit_state.flags;
3464 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3465 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3466 return 0;
e9f42757
BK		 3467}
3468
3469static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3470{
2da29bcc 3471 int start = 0;
e9f42757
BK		 3472 u32 prev_legacy, cur_legacy;
3473 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3474 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3475 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3476 if (!prev_legacy && cur_legacy)
3477 start = 1;
3478 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3479 sizeof(kvm->arch.vpit->pit_state.channels));
3480 kvm->arch.vpit->pit_state.flags = ps->flags;
3481 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3482 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3483 return 0;
e0f63cb9
SY		 3484}
3485
52d939a0
MT		 3486static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3487 struct kvm_reinject_control *control)
3488{
3489 if (!kvm->arch.vpit)
3490 return -ENXIO;
894a9c55 3491 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3492 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3493 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3494 return 0;
3495}
3496
95d4c16c 3497/**
60c34612
TY		 3498 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3499 * @kvm: kvm instance
3500 * @log: slot id and address to which we copy the log
95d4c16c 3501 *
e108ff2f
PB		 3502 * Steps 1-4 below provide general overview of dirty page logging. See
3503 * kvm_get_dirty_log_protect() function description for additional details.
3504 *
3505 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3506 * always flush the TLB (step 4) even if previous step failed and the dirty
3507 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3508 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3509 * writes will be marked dirty for next log read.
95d4c16c 3510 *
60c34612
TY		 3511 * 1. Take a snapshot of the bit and clear it if needed.
3512 * 2. Write protect the corresponding page.
e108ff2f
PB		 3513 * 3. Copy the snapshot to the userspace.
3514 * 4. Flush TLB's if needed.
5bb064dc 3515 */
60c34612 3516int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3517{
60c34612 3518 bool is_dirty = false;
e108ff2f 3519 int r;
5bb064dc 3520
79fac95e 3521 mutex_lock(&kvm->slots_lock);
5bb064dc 3522
88178fd4
KH		 3523 /*
3524 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3525 */
3526 if (kvm_x86_ops->flush_log_dirty)
3527 kvm_x86_ops->flush_log_dirty(kvm);
3528
e108ff2f 3529 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3530
3531 /*
3532 * All the TLBs can be flushed out of mmu lock, see the comments in
3533 * kvm_mmu_slot_remove_write_access().
3534 */
e108ff2f 3535 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3536 if (is_dirty)
3537 kvm_flush_remote_tlbs(kvm);
3538
79fac95e 3539 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3540 return r;
3541}
3542
aa2fbe6d
YZ		 3543int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3544 bool line_status)
23d43cf9
CD		 3545{
3546 if (!irqchip_in_kernel(kvm))
3547 return -ENXIO;
3548
3549 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3550 irq_event->irq, irq_event->level,
3551 line_status);
23d43cf9
CD		 3552 return 0;
3553}
3554
90de4a18
NA		 3555static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3556 struct kvm_enable_cap *cap)
3557{
3558 int r;
3559
3560 if (cap->flags)
3561 return -EINVAL;
3562
3563 switch (cap->cap) {
3564 case KVM_CAP_DISABLE_QUIRKS:
3565 kvm->arch.disabled_quirks = cap->args[0];
3566 r = 0;
3567 break;
49df6397
SR		 3568 case KVM_CAP_SPLIT_IRQCHIP: {
3569 mutex_lock(&kvm->lock);
b053b2ae
SR		 3570 r = -EINVAL;
3571 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3572 goto split_irqchip_unlock;
49df6397
SR		 3573 r = -EEXIST;
3574 if (irqchip_in_kernel(kvm))
3575 goto split_irqchip_unlock;
3576 if (atomic_read(&kvm->online_vcpus))
3577 goto split_irqchip_unlock;
3578 r = kvm_setup_empty_irq_routing(kvm);
3579 if (r)
3580 goto split_irqchip_unlock;
3581 /* Pairs with irqchip_in_kernel. */
3582 smp_wmb();
3583 kvm->arch.irqchip_split = true;
b053b2ae 3584 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3585 r = 0;
3586split_irqchip_unlock:
3587 mutex_unlock(&kvm->lock);
3588 break;
3589 }
90de4a18
NA		 3590 default:
3591 r = -EINVAL;
3592 break;
3593 }
3594 return r;
3595}
3596
1fe779f8
CO		 3597long kvm_arch_vm_ioctl(struct file *filp,
3598 unsigned int ioctl, unsigned long arg)
3599{
3600 struct kvm *kvm = filp->private_data;
3601 void __user *argp = (void __user *)arg;
367e1319 3602 int r = -ENOTTY;
f0d66275
DH		 3603 /*
3604 * This union makes it completely explicit to gcc-3.x
3605 * that these two variables' stack usage should be
3606 * combined, not added together.
3607 */
3608 union {
3609 struct kvm_pit_state ps;
e9f42757 3610 struct kvm_pit_state2 ps2;
c5ff41ce 3611 struct kvm_pit_config pit_config;
f0d66275 3612 } u;
1fe779f8
CO		 3613
3614 switch (ioctl) {
3615 case KVM_SET_TSS_ADDR:
3616 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3617 break;
b927a3ce
SY		 3618 case KVM_SET_IDENTITY_MAP_ADDR: {
3619 u64 ident_addr;
3620
3621 r = -EFAULT;
3622 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3623 goto out;
3624 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3625 break;
3626 }
1fe779f8
CO		 3627 case KVM_SET_NR_MMU_PAGES:
3628 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3629 break;
3630 case KVM_GET_NR_MMU_PAGES:
3631 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3632 break;
3ddea128
MT		 3633 case KVM_CREATE_IRQCHIP: {
3634 struct kvm_pic *vpic;
3635
3636 mutex_lock(&kvm->lock);
3637 r = -EEXIST;
3638 if (kvm->arch.vpic)
3639 goto create_irqchip_unlock;
3e515705
AK		 3640 r = -EINVAL;
3641 if (atomic_read(&kvm->online_vcpus))
3642 goto create_irqchip_unlock;
1fe779f8 3643 r = -ENOMEM;
3ddea128
MT		 3644 vpic = kvm_create_pic(kvm);
3645 if (vpic) {
1fe779f8
CO		 3646 r = kvm_ioapic_init(kvm);
3647 if (r) {
175504cd 3648 mutex_lock(&kvm->slots_lock);
71ba994c 3649 kvm_destroy_pic(vpic);
175504cd 3650 mutex_unlock(&kvm->slots_lock);
3ddea128 3651 goto create_irqchip_unlock;
1fe779f8
CO		 3652 }
3653 } else
3ddea128 3654 goto create_irqchip_unlock;
399ec807
AK		 3655 r = kvm_setup_default_irq_routing(kvm);
3656 if (r) {
175504cd 3657 mutex_lock(&kvm->slots_lock);
3ddea128 3658 mutex_lock(&kvm->irq_lock);
72bb2fcd 3659 kvm_ioapic_destroy(kvm);
71ba994c 3660 kvm_destroy_pic(vpic);
3ddea128 3661 mutex_unlock(&kvm->irq_lock);
175504cd 3662 mutex_unlock(&kvm->slots_lock);
71ba994c 3663 goto create_irqchip_unlock;
399ec807 3664 }
71ba994c
PB		 3665 /* Write kvm->irq_routing before kvm->arch.vpic. */
3666 smp_wmb();
3667 kvm->arch.vpic = vpic;
3ddea128
MT		 3668 create_irqchip_unlock:
3669 mutex_unlock(&kvm->lock);
1fe779f8 3670 break;
3ddea128 3671 }
7837699f 3672 case KVM_CREATE_PIT:
c5ff41ce
JK		 3673 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3674 goto create_pit;
3675 case KVM_CREATE_PIT2:
3676 r = -EFAULT;
3677 if (copy_from_user(&u.pit_config, argp,
3678 sizeof(struct kvm_pit_config)))
3679 goto out;
3680 create_pit:
79fac95e 3681 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3682 r = -EEXIST;
3683 if (kvm->arch.vpit)
3684 goto create_pit_unlock;
7837699f 3685 r = -ENOMEM;
c5ff41ce 3686 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3687 if (kvm->arch.vpit)
3688 r = 0;
269e05e4 3689 create_pit_unlock:
79fac95e 3690 mutex_unlock(&kvm->slots_lock);
7837699f 3691 break;
1fe779f8
CO		 3692 case KVM_GET_IRQCHIP: {
3693 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3694 struct kvm_irqchip *chip;
1fe779f8 3695
ff5c2c03
SL		 3696 chip = memdup_user(argp, sizeof(*chip));
3697 if (IS_ERR(chip)) {
3698 r = PTR_ERR(chip);
1fe779f8 3699 goto out;
ff5c2c03
SL		 3700 }
3701
1fe779f8 3702 r = -ENXIO;
49df6397 3703 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3704 goto get_irqchip_out;
3705 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3706 if (r)
f0d66275 3707 goto get_irqchip_out;
1fe779f8 3708 r = -EFAULT;
f0d66275
DH		 3709 if (copy_to_user(argp, chip, sizeof *chip))
3710 goto get_irqchip_out;
1fe779f8 3711 r = 0;
f0d66275
DH		 3712 get_irqchip_out:
3713 kfree(chip);
1fe779f8
CO		 3714 break;
3715 }
3716 case KVM_SET_IRQCHIP: {
3717 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3718 struct kvm_irqchip *chip;
1fe779f8 3719
ff5c2c03
SL		 3720 chip = memdup_user(argp, sizeof(*chip));
3721 if (IS_ERR(chip)) {
3722 r = PTR_ERR(chip);
1fe779f8 3723 goto out;
ff5c2c03
SL		 3724 }
3725
1fe779f8 3726 r = -ENXIO;
49df6397 3727 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3728 goto set_irqchip_out;
3729 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3730 if (r)
f0d66275 3731 goto set_irqchip_out;
1fe779f8 3732 r = 0;
f0d66275
DH		 3733 set_irqchip_out:
3734 kfree(chip);
1fe779f8
CO		 3735 break;
3736 }
e0f63cb9 3737 case KVM_GET_PIT: {
e0f63cb9 3738 r = -EFAULT;
f0d66275 3739 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3740 goto out;
3741 r = -ENXIO;
3742 if (!kvm->arch.vpit)
3743 goto out;
f0d66275 3744 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3745 if (r)
3746 goto out;
3747 r = -EFAULT;
f0d66275 3748 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3749 goto out;
3750 r = 0;
3751 break;
3752 }
3753 case KVM_SET_PIT: {
e0f63cb9 3754 r = -EFAULT;
f0d66275 3755 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3756 goto out;
3757 r = -ENXIO;
3758 if (!kvm->arch.vpit)
3759 goto out;
f0d66275 3760 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3761 break;
3762 }
e9f42757
BK		 3763 case KVM_GET_PIT2: {
3764 r = -ENXIO;
3765 if (!kvm->arch.vpit)
3766 goto out;
3767 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3768 if (r)
3769 goto out;
3770 r = -EFAULT;
3771 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3772 goto out;
3773 r = 0;
3774 break;
3775 }
3776 case KVM_SET_PIT2: {
3777 r = -EFAULT;
3778 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3779 goto out;
3780 r = -ENXIO;
3781 if (!kvm->arch.vpit)
3782 goto out;
3783 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3784 break;
3785 }
52d939a0
MT		 3786 case KVM_REINJECT_CONTROL: {
3787 struct kvm_reinject_control control;
3788 r = -EFAULT;
3789 if (copy_from_user(&control, argp, sizeof(control)))
3790 goto out;
3791 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3792 break;
3793 }
d71ba788
PB		 3794 case KVM_SET_BOOT_CPU_ID:
3795 r = 0;
3796 mutex_lock(&kvm->lock);
3797 if (atomic_read(&kvm->online_vcpus) != 0)
3798 r = -EBUSY;
3799 else
3800 kvm->arch.bsp_vcpu_id = arg;
3801 mutex_unlock(&kvm->lock);
3802 break;
ffde22ac
ES		 3803 case KVM_XEN_HVM_CONFIG: {
3804 r = -EFAULT;
3805 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3806 sizeof(struct kvm_xen_hvm_config)))
3807 goto out;
3808 r = -EINVAL;
3809 if (kvm->arch.xen_hvm_config.flags)
3810 goto out;
3811 r = 0;
3812 break;
3813 }
afbcf7ab 3814 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3815 struct kvm_clock_data user_ns;
3816 u64 now_ns;
3817 s64 delta;
3818
3819 r = -EFAULT;
3820 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3821 goto out;
3822
3823 r = -EINVAL;
3824 if (user_ns.flags)
3825 goto out;
3826
3827 r = 0;
395c6b0a 3828 local_irq_disable();
759379dd 3829 now_ns = get_kernel_ns();
afbcf7ab 3830 delta = user_ns.clock - now_ns;
395c6b0a 3831 local_irq_enable();
afbcf7ab 3832 kvm->arch.kvmclock_offset = delta;
2e762ff7 3833 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3834 break;
3835 }
3836 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3837 struct kvm_clock_data user_ns;
3838 u64 now_ns;
3839
395c6b0a 3840 local_irq_disable();
759379dd 3841 now_ns = get_kernel_ns();
afbcf7ab 3842 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3843 local_irq_enable();
afbcf7ab 3844 user_ns.flags = 0;
97e69aa6 3845 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3846
3847 r = -EFAULT;
3848 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3849 goto out;
3850 r = 0;
3851 break;
3852 }
90de4a18
NA		 3853 case KVM_ENABLE_CAP: {
3854 struct kvm_enable_cap cap;
afbcf7ab 3855
90de4a18
NA		 3856 r = -EFAULT;
3857 if (copy_from_user(&cap, argp, sizeof(cap)))
3858 goto out;
3859 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3860 break;
3861 }
1fe779f8 3862 default:
c274e03a 3863 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 3864 }
3865out:
3866 return r;
3867}
3868
a16b043c 3869static void kvm_init_msr_list(void)
043405e1
CO		 3870{
3871 u32 dummy[2];
3872 unsigned i, j;
3873
62ef68bb 3874 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3875 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3876 continue;
93c4adc7
PB		 3877
3878 /*
3879 * Even MSRs that are valid in the host may not be exposed
3880 * to the guests in some cases. We could work around this
3881 * in VMX with the generic MSR save/load machinery, but it
3882 * is not really worthwhile since it will really only
3883 * happen with nested virtualization.
3884 */
3885 switch (msrs_to_save[i]) {
3886 case MSR_IA32_BNDCFGS:
3887 if (!kvm_x86_ops->mpx_supported())
3888 continue;
3889 break;
3890 default:
3891 break;
3892 }
3893
043405e1
CO		 3894 if (j < i)
3895 msrs_to_save[j] = msrs_to_save[i];
3896 j++;
3897 }
3898 num_msrs_to_save = j;
62ef68bb
PB		 3899
3900 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
3901 switch (emulated_msrs[i]) {
6d396b55
PB		 3902 case MSR_IA32_SMBASE:
3903 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
3904 continue;
3905 break;
62ef68bb
PB		 3906 default:
3907 break;
3908 }
3909
3910 if (j < i)
3911 emulated_msrs[j] = emulated_msrs[i];
3912 j++;
3913 }
3914 num_emulated_msrs = j;
043405e1
CO		 3915}
3916
bda9020e
MT		 3917static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3918 const void *v)
bbd9b64e 3919{
70252a10
AK		 3920 int handled = 0;
3921 int n;
3922
3923 do {
3924 n = min(len, 8);
3925 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3926 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
3927 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3928 break;
3929 handled += n;
3930 addr += n;
3931 len -= n;
3932 v += n;
3933 } while (len);
bbd9b64e 3934
70252a10 3935 return handled;
bbd9b64e
CO		 3936}
3937
bda9020e 3938static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3939{
70252a10
AK		 3940 int handled = 0;
3941 int n;
3942
3943 do {
3944 n = min(len, 8);
3945 if (!(vcpu->arch.apic &&
e32edf4f
NN		 3946 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
3947 addr, n, v))
3948 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 3949 break;
3950 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3951 handled += n;
3952 addr += n;
3953 len -= n;
3954 v += n;
3955 } while (len);
bbd9b64e 3956
70252a10 3957 return handled;
bbd9b64e
CO		 3958}
3959
2dafc6c2
GN		 3960static void kvm_set_segment(struct kvm_vcpu *vcpu,
3961 struct kvm_segment *var, int seg)
3962{
3963 kvm_x86_ops->set_segment(vcpu, var, seg);
3964}
3965
3966void kvm_get_segment(struct kvm_vcpu *vcpu,
3967 struct kvm_segment *var, int seg)
3968{
3969 kvm_x86_ops->get_segment(vcpu, var, seg);
3970}
3971
54987b7a
PB		 3972gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
3973 struct x86_exception *exception)
02f59dc9
JR		 3974{
3975 gpa_t t_gpa;
02f59dc9
JR		 3976
3977 BUG_ON(!mmu_is_nested(vcpu));
3978
3979 /* NPT walks are always user-walks */
3980 access |= PFERR_USER_MASK;
54987b7a 3981 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 3982
3983 return t_gpa;
3984}
3985
ab9ae313
AK		 3986gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3987 struct x86_exception *exception)
1871c602
GN		 3988{
3989 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3990 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3991}
3992
ab9ae313
AK		 3993 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3994 struct x86_exception *exception)
1871c602
GN		 3995{
3996 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3997 access |= PFERR_FETCH_MASK;
ab9ae313 3998 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3999}
4000
ab9ae313
AK		 4001gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4002 struct x86_exception *exception)
1871c602
GN		 4003{
4004 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4005 access |= PFERR_WRITE_MASK;
ab9ae313 4006 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4007}
4008
4009/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4010gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4011 struct x86_exception *exception)
1871c602 4012{
ab9ae313 4013 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4014}
4015
4016static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4017 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4018 struct x86_exception *exception)
bbd9b64e
CO		 4019{
4020 void *data = val;
10589a46 4021 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4022
4023 while (bytes) {
14dfe855 4024 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4025 exception);
bbd9b64e 4026 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4027 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4028 int ret;
4029
bcc55cba 4030 if (gpa == UNMAPPED_GVA)
ab9ae313 4031 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4032 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4033 offset, toread);
10589a46 4034 if (ret < 0) {
c3cd7ffa 4035 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4036 goto out;
4037 }
bbd9b64e 4038
77c2002e
IE		 4039 bytes -= toread;
4040 data += toread;
4041 addr += toread;
bbd9b64e 4042 }
10589a46 4043out:
10589a46 4044 return r;
bbd9b64e 4045}
77c2002e 4046
1871c602 4047/* used for instruction fetching */
0f65dd70
AK		 4048static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4049 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4050 struct x86_exception *exception)
1871c602 4051{
0f65dd70 4052 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4053 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4054 unsigned offset;
4055 int ret;
0f65dd70 4056
44583cba
PB		 4057 /* Inline kvm_read_guest_virt_helper for speed. */
4058 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4059 exception);
4060 if (unlikely(gpa == UNMAPPED_GVA))
4061 return X86EMUL_PROPAGATE_FAULT;
4062
4063 offset = addr & (PAGE_SIZE-1);
4064 if (WARN_ON(offset + bytes > PAGE_SIZE))
4065 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4066 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4067 offset, bytes);
44583cba
PB		 4068 if (unlikely(ret < 0))
4069 return X86EMUL_IO_NEEDED;
4070
4071 return X86EMUL_CONTINUE;
1871c602
GN		 4072}
4073
064aea77 4074int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4075 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4076 struct x86_exception *exception)
1871c602 4077{
0f65dd70 4078 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4079 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4080
1871c602 4081 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4082 exception);
1871c602 4083}
064aea77 4084EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4085
0f65dd70
AK		 4086static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4087 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4088 struct x86_exception *exception)
1871c602 4089{
0f65dd70 4090 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4091 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4092}
4093
7a036a6f
RK		 4094static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4095 unsigned long addr, void *val, unsigned int bytes)
4096{
4097 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4098 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4099
4100 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4101}
4102
6a4d7550 4103int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4104 gva_t addr, void *val,
2dafc6c2 4105 unsigned int bytes,
bcc55cba 4106 struct x86_exception *exception)
77c2002e 4107{
0f65dd70 4108 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4109 void *data = val;
4110 int r = X86EMUL_CONTINUE;
4111
4112 while (bytes) {
14dfe855
JR		 4113 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4114 PFERR_WRITE_MASK,
ab9ae313 4115 exception);
77c2002e
IE		 4116 unsigned offset = addr & (PAGE_SIZE-1);
4117 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4118 int ret;
4119
bcc55cba 4120 if (gpa == UNMAPPED_GVA)
ab9ae313 4121 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4122 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4123 if (ret < 0) {
c3cd7ffa 4124 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4125 goto out;
4126 }
4127
4128 bytes -= towrite;
4129 data += towrite;
4130 addr += towrite;
4131 }
4132out:
4133 return r;
4134}
6a4d7550 4135EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4136
af7cc7d1
XG		 4137static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4138 gpa_t *gpa, struct x86_exception *exception,
4139 bool write)
4140{
97d64b78
AK		 4141 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4142 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4143
97d64b78 4144 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4145 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4146 vcpu->arch.access, access)) {
bebb106a
XG		 4147 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4148 (gva & (PAGE_SIZE - 1));
4f022648 4149 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4150 return 1;
4151 }
4152
af7cc7d1
XG		 4153 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4154
4155 if (*gpa == UNMAPPED_GVA)
4156 return -1;
4157
4158 /* For APIC access vmexit */
4159 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4160 return 1;
4161
4f022648
XG		 4162 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4163 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4164 return 1;
4f022648 4165 }
bebb106a 4166
af7cc7d1
XG		 4167 return 0;
4168}
4169
3200f405 4170int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4171 const void *val, int bytes)
bbd9b64e
CO		 4172{
4173 int ret;
4174
54bf36aa 4175 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4176 if (ret < 0)
bbd9b64e 4177 return 0;
f57f2ef5 4178 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4179 return 1;
4180}
4181
77d197b2
XG		 4182struct read_write_emulator_ops {
4183 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4184 int bytes);
4185 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4186 void *val, int bytes);
4187 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4188 int bytes, void *val);
4189 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4190 void *val, int bytes);
4191 bool write;
4192};
4193
4194static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4195{
4196 if (vcpu->mmio_read_completed) {
77d197b2 4197 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4198 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4199 vcpu->mmio_read_completed = 0;
4200 return 1;
4201 }
4202
4203 return 0;
4204}
4205
4206static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4207 void *val, int bytes)
4208{
54bf36aa 4209 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4210}
4211
4212static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4213 void *val, int bytes)
4214{
4215 return emulator_write_phys(vcpu, gpa, val, bytes);
4216}
4217
4218static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4219{
4220 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4221 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4222}
4223
4224static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4225 void *val, int bytes)
4226{
4227 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4228 return X86EMUL_IO_NEEDED;
4229}
4230
4231static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4232 void *val, int bytes)
4233{
f78146b0
AK		 4234 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4235
87da7e66 4236 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4237 return X86EMUL_CONTINUE;
4238}
4239
0fbe9b0b 4240static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4241 .read_write_prepare = read_prepare,
4242 .read_write_emulate = read_emulate,
4243 .read_write_mmio = vcpu_mmio_read,
4244 .read_write_exit_mmio = read_exit_mmio,
4245};
4246
0fbe9b0b 4247static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4248 .read_write_emulate = write_emulate,
4249 .read_write_mmio = write_mmio,
4250 .read_write_exit_mmio = write_exit_mmio,
4251 .write = true,
4252};
4253
22388a3c
XG		 4254static int emulator_read_write_onepage(unsigned long addr, void *val,
4255 unsigned int bytes,
4256 struct x86_exception *exception,
4257 struct kvm_vcpu *vcpu,
0fbe9b0b 4258 const struct read_write_emulator_ops *ops)
bbd9b64e 4259{
af7cc7d1
XG		 4260 gpa_t gpa;
4261 int handled, ret;
22388a3c 4262 bool write = ops->write;
f78146b0 4263 struct kvm_mmio_fragment *frag;
10589a46 4264
22388a3c 4265 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4266
af7cc7d1 4267 if (ret < 0)
bbd9b64e 4268 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4269
4270 /* For APIC access vmexit */
af7cc7d1 4271 if (ret)
bbd9b64e
CO		 4272 goto mmio;
4273
22388a3c 4274 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4275 return X86EMUL_CONTINUE;
4276
4277mmio:
4278 /*
4279 * Is this MMIO handled locally?
4280 */
22388a3c 4281 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4282 if (handled == bytes)
bbd9b64e 4283 return X86EMUL_CONTINUE;
bbd9b64e 4284
70252a10
AK		 4285 gpa += handled;
4286 bytes -= handled;
4287 val += handled;
4288
87da7e66
XG		 4289 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4290 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4291 frag->gpa = gpa;
4292 frag->data = val;
4293 frag->len = bytes;
f78146b0 4294 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4295}
4296
52eb5a6d
XL		 4297static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4298 unsigned long addr,
22388a3c
XG		 4299 void *val, unsigned int bytes,
4300 struct x86_exception *exception,
0fbe9b0b 4301 const struct read_write_emulator_ops *ops)
bbd9b64e 4302{
0f65dd70 4303 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4304 gpa_t gpa;
4305 int rc;
4306
4307 if (ops->read_write_prepare &&
4308 ops->read_write_prepare(vcpu, val, bytes))
4309 return X86EMUL_CONTINUE;
4310
4311 vcpu->mmio_nr_fragments = 0;
0f65dd70 4312
bbd9b64e
CO		 4313 /* Crossing a page boundary? */
4314 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4315 int now;
bbd9b64e
CO		 4316
4317 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4318 rc = emulator_read_write_onepage(addr, val, now, exception,
4319 vcpu, ops);
4320
bbd9b64e
CO		 4321 if (rc != X86EMUL_CONTINUE)
4322 return rc;
4323 addr += now;
bac15531
NA		 4324 if (ctxt->mode != X86EMUL_MODE_PROT64)
4325 addr = (u32)addr;
bbd9b64e
CO		 4326 val += now;
4327 bytes -= now;
4328 }
22388a3c 4329
f78146b0
AK		 4330 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4331 vcpu, ops);
4332 if (rc != X86EMUL_CONTINUE)
4333 return rc;
4334
4335 if (!vcpu->mmio_nr_fragments)
4336 return rc;
4337
4338 gpa = vcpu->mmio_fragments[0].gpa;
4339
4340 vcpu->mmio_needed = 1;
4341 vcpu->mmio_cur_fragment = 0;
4342
87da7e66 4343 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4344 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4345 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4346 vcpu->run->mmio.phys_addr = gpa;
4347
4348 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4349}
4350
4351static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4352 unsigned long addr,
4353 void *val,
4354 unsigned int bytes,
4355 struct x86_exception *exception)
4356{
4357 return emulator_read_write(ctxt, addr, val, bytes,
4358 exception, &read_emultor);
4359}
4360
52eb5a6d 4361static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4362 unsigned long addr,
4363 const void *val,
4364 unsigned int bytes,
4365 struct x86_exception *exception)
4366{
4367 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4368 exception, &write_emultor);
bbd9b64e 4369}
bbd9b64e 4370
daea3e73
AK		 4371#define CMPXCHG_TYPE(t, ptr, old, new) \
4372 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4373
4374#ifdef CONFIG_X86_64
4375# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4376#else
4377# define CMPXCHG64(ptr, old, new) \
9749a6c0 4378 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4379#endif
4380
0f65dd70
AK		 4381static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4382 unsigned long addr,
bbd9b64e
CO		 4383 const void *old,
4384 const void *new,
4385 unsigned int bytes,
0f65dd70 4386 struct x86_exception *exception)
bbd9b64e 4387{
0f65dd70 4388 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4389 gpa_t gpa;
4390 struct page *page;
4391 char *kaddr;
4392 bool exchanged;
2bacc55c 4393
daea3e73
AK		 4394 /* guests cmpxchg8b have to be emulated atomically */
4395 if (bytes > 8 || (bytes & (bytes - 1)))
4396 goto emul_write;
10589a46 4397
daea3e73 4398 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4399
daea3e73
AK		 4400 if (gpa == UNMAPPED_GVA ||
4401 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4402 goto emul_write;
2bacc55c 4403
daea3e73
AK		 4404 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4405 goto emul_write;
72dc67a6 4406
54bf36aa 4407 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4408 if (is_error_page(page))
c19b8bd6 4409 goto emul_write;
72dc67a6 4410
8fd75e12 4411 kaddr = kmap_atomic(page);
daea3e73
AK		 4412 kaddr += offset_in_page(gpa);
4413 switch (bytes) {
4414 case 1:
4415 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4416 break;
4417 case 2:
4418 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4419 break;
4420 case 4:
4421 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4422 break;
4423 case 8:
4424 exchanged = CMPXCHG64(kaddr, old, new);
4425 break;
4426 default:
4427 BUG();
2bacc55c 4428 }
8fd75e12 4429 kunmap_atomic(kaddr);
daea3e73
AK		 4430 kvm_release_page_dirty(page);
4431
4432 if (!exchanged)
4433 return X86EMUL_CMPXCHG_FAILED;
4434
54bf36aa 4435 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4436 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4437
4438 return X86EMUL_CONTINUE;
4a5f48f6 4439
3200f405 4440emul_write:
daea3e73 4441 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4442
0f65dd70 4443 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4444}
4445
cf8f70bf
GN		 4446static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4447{
4448 /* TODO: String I/O for in kernel device */
4449 int r;
4450
4451 if (vcpu->arch.pio.in)
e32edf4f 4452 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4453 vcpu->arch.pio.size, pd);
4454 else
e32edf4f 4455 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4456 vcpu->arch.pio.port, vcpu->arch.pio.size,
4457 pd);
4458 return r;
4459}
4460
6f6fbe98
XG		 4461static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4462 unsigned short port, void *val,
4463 unsigned int count, bool in)
cf8f70bf 4464{
cf8f70bf 4465 vcpu->arch.pio.port = port;
6f6fbe98 4466 vcpu->arch.pio.in = in;
7972995b 4467 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4468 vcpu->arch.pio.size = size;
4469
4470 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4471 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4472 return 1;
4473 }
4474
4475 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4476 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4477 vcpu->run->io.size = size;
4478 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4479 vcpu->run->io.count = count;
4480 vcpu->run->io.port = port;
4481
4482 return 0;
4483}
4484
6f6fbe98
XG		 4485static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4486 int size, unsigned short port, void *val,
4487 unsigned int count)
cf8f70bf 4488{
ca1d4a9e 4489 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4490 int ret;
ca1d4a9e 4491
6f6fbe98
XG		 4492 if (vcpu->arch.pio.count)
4493 goto data_avail;
cf8f70bf 4494
6f6fbe98
XG		 4495 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4496 if (ret) {
4497data_avail:
4498 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4499 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4500 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4501 return 1;
4502 }
4503
cf8f70bf
GN		 4504 return 0;
4505}
4506
6f6fbe98
XG		 4507static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4508 int size, unsigned short port,
4509 const void *val, unsigned int count)
4510{
4511 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4512
4513 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4514 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4515 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4516}
4517
bbd9b64e
CO		 4518static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4519{
4520 return kvm_x86_ops->get_segment_base(vcpu, seg);
4521}
4522
3cb16fe7 4523static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4524{
3cb16fe7 4525 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4526}
4527
5cb56059 4528int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4529{
4530 if (!need_emulate_wbinvd(vcpu))
4531 return X86EMUL_CONTINUE;
4532
4533 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4534 int cpu = get_cpu();
4535
4536 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4537 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4538 wbinvd_ipi, NULL, 1);
2eec7343 4539 put_cpu();
f5f48ee1 4540 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4541 } else
4542 wbinvd();
f5f48ee1
SY		 4543 return X86EMUL_CONTINUE;
4544}
5cb56059
JS		 4545
4546int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4547{
4548 kvm_x86_ops->skip_emulated_instruction(vcpu);
4549 return kvm_emulate_wbinvd_noskip(vcpu);
4550}
f5f48ee1
SY		 4551EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4552
5cb56059
JS		 4553
4554
bcaf5cc5
AK		 4555static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4556{
5cb56059 4557 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4558}
4559
52eb5a6d
XL		 4560static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4561 unsigned long *dest)
bbd9b64e 4562{
16f8a6f9 4563 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4564}
4565
52eb5a6d
XL		 4566static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4567 unsigned long value)
bbd9b64e 4568{
338dbc97 4569
717746e3 4570 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4571}
4572
52a46617 4573static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4574{
52a46617 4575 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4576}
4577
717746e3 4578static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4579{
717746e3 4580 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4581 unsigned long value;
4582
4583 switch (cr) {
4584 case 0:
4585 value = kvm_read_cr0(vcpu);
4586 break;
4587 case 2:
4588 value = vcpu->arch.cr2;
4589 break;
4590 case 3:
9f8fe504 4591 value = kvm_read_cr3(vcpu);
52a46617
GN		 4592 break;
4593 case 4:
4594 value = kvm_read_cr4(vcpu);
4595 break;
4596 case 8:
4597 value = kvm_get_cr8(vcpu);
4598 break;
4599 default:
a737f256 4600 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4601 return 0;
4602 }
4603
4604 return value;
4605}
4606
717746e3 4607static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4608{
717746e3 4609 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4610 int res = 0;
4611
52a46617
GN		 4612 switch (cr) {
4613 case 0:
49a9b07e 4614 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4615 break;
4616 case 2:
4617 vcpu->arch.cr2 = val;
4618 break;
4619 case 3:
2390218b 4620 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4621 break;
4622 case 4:
a83b29c6 4623 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4624 break;
4625 case 8:
eea1cff9 4626 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4627 break;
4628 default:
a737f256 4629 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4630 res = -1;
52a46617 4631 }
0f12244f
GN		 4632
4633 return res;
52a46617
GN		 4634}
4635
717746e3 4636static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4637{
717746e3 4638 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4639}
4640
4bff1e86 4641static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4642{
4bff1e86 4643 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4644}
4645
4bff1e86 4646static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4647{
4bff1e86 4648 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4649}
4650
1ac9d0cf
AK		 4651static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4652{
4653 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4654}
4655
4656static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4657{
4658 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4659}
4660
4bff1e86
AK		 4661static unsigned long emulator_get_cached_segment_base(
4662 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4663{
4bff1e86 4664 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4665}
4666
1aa36616
AK		 4667static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4668 struct desc_struct *desc, u32 *base3,
4669 int seg)
2dafc6c2
GN		 4670{
4671 struct kvm_segment var;
4672
4bff1e86 4673 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4674 *selector = var.selector;
2dafc6c2 4675
378a8b09
GN		 4676 if (var.unusable) {
4677 memset(desc, 0, sizeof(*desc));
2dafc6c2 4678 return false;
378a8b09 4679 }
2dafc6c2
GN		 4680
4681 if (var.g)
4682 var.limit >>= 12;
4683 set_desc_limit(desc, var.limit);
4684 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4685#ifdef CONFIG_X86_64
4686 if (base3)
4687 *base3 = var.base >> 32;
4688#endif
2dafc6c2
GN		 4689 desc->type = var.type;
4690 desc->s = var.s;
4691 desc->dpl = var.dpl;
4692 desc->p = var.present;
4693 desc->avl = var.avl;
4694 desc->l = var.l;
4695 desc->d = var.db;
4696 desc->g = var.g;
4697
4698 return true;
4699}
4700
1aa36616
AK		 4701static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4702 struct desc_struct *desc, u32 base3,
4703 int seg)
2dafc6c2 4704{
4bff1e86 4705 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4706 struct kvm_segment var;
4707
1aa36616 4708 var.selector = selector;
2dafc6c2 4709 var.base = get_desc_base(desc);
5601d05b
GN		 4710#ifdef CONFIG_X86_64
4711 var.base |= ((u64)base3) << 32;
4712#endif
2dafc6c2
GN		 4713 var.limit = get_desc_limit(desc);
4714 if (desc->g)
4715 var.limit = (var.limit << 12) | 0xfff;
4716 var.type = desc->type;
2dafc6c2
GN		 4717 var.dpl = desc->dpl;
4718 var.db = desc->d;
4719 var.s = desc->s;
4720 var.l = desc->l;
4721 var.g = desc->g;
4722 var.avl = desc->avl;
4723 var.present = desc->p;
4724 var.unusable = !var.present;
4725 var.padding = 0;
4726
4727 kvm_set_segment(vcpu, &var, seg);
4728 return;
4729}
4730
717746e3
AK		 4731static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4732 u32 msr_index, u64 *pdata)
4733{
609e36d3
PB		 4734 struct msr_data msr;
4735 int r;
4736
4737 msr.index = msr_index;
4738 msr.host_initiated = false;
4739 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4740 if (r)
4741 return r;
4742
4743 *pdata = msr.data;
4744 return 0;
717746e3
AK		 4745}
4746
4747static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4748 u32 msr_index, u64 data)
4749{
8fe8ab46
WA		 4750 struct msr_data msr;
4751
4752 msr.data = data;
4753 msr.index = msr_index;
4754 msr.host_initiated = false;
4755 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4756}
4757
64d60670
PB		 4758static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4759{
4760 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4761
4762 return vcpu->arch.smbase;
4763}
4764
4765static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4766{
4767 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4768
4769 vcpu->arch.smbase = smbase;
4770}
4771
67f4d428
NA		 4772static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4773 u32 pmc)
4774{
c6702c9d 4775 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4776}
4777
222d21aa
AK		 4778static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4779 u32 pmc, u64 *pdata)
4780{
c6702c9d 4781 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4782}
4783
6c3287f7
AK		 4784static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4785{
4786 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4787}
4788
5037f6f3
AK		 4789static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4790{
4791 preempt_disable();
5197b808 4792 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4793 /*
4794 * CR0.TS may reference the host fpu state, not the guest fpu state,
4795 * so it may be clear at this point.
4796 */
4797 clts();
4798}
4799
4800static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4801{
4802 preempt_enable();
4803}
4804
2953538e 4805static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4806 struct x86_instruction_info *info,
c4f035c6
AK		 4807 enum x86_intercept_stage stage)
4808{
2953538e 4809 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4810}
4811
0017f93a 4812static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4813 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4814{
0017f93a 4815 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4816}
4817
dd856efa
AK		 4818static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4819{
4820 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4821}
4822
4823static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4824{
4825 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4826}
4827
801806d9
NA		 4828static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4829{
4830 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4831}
4832
0225fb50 4833static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4834 .read_gpr = emulator_read_gpr,
4835 .write_gpr = emulator_write_gpr,
1871c602 4836 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4837 .write_std = kvm_write_guest_virt_system,
7a036a6f 4838 .read_phys = kvm_read_guest_phys_system,
1871c602 4839 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4840 .read_emulated = emulator_read_emulated,
4841 .write_emulated = emulator_write_emulated,
4842 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4843 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4844 .pio_in_emulated = emulator_pio_in_emulated,
4845 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4846 .get_segment = emulator_get_segment,
4847 .set_segment = emulator_set_segment,
5951c442 4848 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4849 .get_gdt = emulator_get_gdt,
160ce1f1 4850 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4851 .set_gdt = emulator_set_gdt,
4852 .set_idt = emulator_set_idt,
52a46617
GN		 4853 .get_cr = emulator_get_cr,
4854 .set_cr = emulator_set_cr,
9c537244 4855 .cpl = emulator_get_cpl,
35aa5375
GN		 4856 .get_dr = emulator_get_dr,
4857 .set_dr = emulator_set_dr,
64d60670
PB		 4858 .get_smbase = emulator_get_smbase,
4859 .set_smbase = emulator_set_smbase,
717746e3
AK		 4860 .set_msr = emulator_set_msr,
4861 .get_msr = emulator_get_msr,
67f4d428 4862 .check_pmc = emulator_check_pmc,
222d21aa 4863 .read_pmc = emulator_read_pmc,
6c3287f7 4864 .halt = emulator_halt,
bcaf5cc5 4865 .wbinvd = emulator_wbinvd,
d6aa1000 4866 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4867 .get_fpu = emulator_get_fpu,
4868 .put_fpu = emulator_put_fpu,
c4f035c6 4869 .intercept = emulator_intercept,
bdb42f5a 4870 .get_cpuid = emulator_get_cpuid,
801806d9 4871 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 4872};
4873
95cb2295
GN		 4874static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4875{
37ccdcbe 4876 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4877 /*
4878 * an sti; sti; sequence only disable interrupts for the first
4879 * instruction. So, if the last instruction, be it emulated or
4880 * not, left the system with the INT_STI flag enabled, it
4881 * means that the last instruction is an sti. We should not
4882 * leave the flag on in this case. The same goes for mov ss
4883 */
37ccdcbe
PB		 4884 if (int_shadow & mask)
4885 mask = 0;
6addfc42 4886 if (unlikely(int_shadow || mask)) {
95cb2295 4887 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4888 if (!mask)
4889 kvm_make_request(KVM_REQ_EVENT, vcpu);
4890 }
95cb2295
GN		 4891}
4892
ef54bcfe 4893static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4894{
4895 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4896 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4897 return kvm_propagate_fault(vcpu, &ctxt->exception);
4898
4899 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4900 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4901 ctxt->exception.error_code);
54b8486f 4902 else
da9cb575 4903 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4904 return false;
54b8486f
GN		 4905}
4906
8ec4722d
MG		 4907static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4908{
adf52235 4909 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4910 int cs_db, cs_l;
4911
8ec4722d
MG		 4912 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4913
adf52235
TY		 4914 ctxt->eflags = kvm_get_rflags(vcpu);
4915 ctxt->eip = kvm_rip_read(vcpu);
4916 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4917 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4918 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4919 cs_db ? X86EMUL_MODE_PROT32 :
4920 X86EMUL_MODE_PROT16;
a584539b 4921 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 4922 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
4923 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 4924 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 4925
dd856efa 4926 init_decode_cache(ctxt);
7ae441ea 4927 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4928}
4929
71f9833b 4930int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4931{
9d74191a 4932 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4933 int ret;
4934
4935 init_emulate_ctxt(vcpu);
4936
9dac77fa
AK		 4937 ctxt->op_bytes = 2;
4938 ctxt->ad_bytes = 2;
4939 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4940 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4941
4942 if (ret != X86EMUL_CONTINUE)
4943 return EMULATE_FAIL;
4944
9dac77fa 4945 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4946 kvm_rip_write(vcpu, ctxt->eip);
4947 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4948
4949 if (irq == NMI_VECTOR)
7460fb4a 4950 vcpu->arch.nmi_pending = 0;
63995653
MG		 4951 else
4952 vcpu->arch.interrupt.pending = false;
4953
4954 return EMULATE_DONE;
4955}
4956EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4957
6d77dbfc
GN		 4958static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4959{
fc3a9157
JR		 4960 int r = EMULATE_DONE;
4961
6d77dbfc
GN		 4962 ++vcpu->stat.insn_emulation_fail;
4963 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 4964 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 4965 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4966 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4967 vcpu->run->internal.ndata = 0;
4968 r = EMULATE_FAIL;
4969 }
6d77dbfc 4970 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4971
4972 return r;
6d77dbfc
GN		 4973}
4974
93c05d3e 4975static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4976 bool write_fault_to_shadow_pgtable,
4977 int emulation_type)
a6f177ef 4978{
95b3cf69 4979 gpa_t gpa = cr2;
8e3d9d06 4980 pfn_t pfn;
a6f177ef 4981
991eebf9
GN		 4982 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4983 return false;
4984
95b3cf69
XG		 4985 if (!vcpu->arch.mmu.direct_map) {
4986 /*
4987 * Write permission should be allowed since only
4988 * write access need to be emulated.
4989 */
4990 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4991
95b3cf69
XG		 4992 /*
4993 * If the mapping is invalid in guest, let cpu retry
4994 * it to generate fault.
4995 */
4996 if (gpa == UNMAPPED_GVA)
4997 return true;
4998 }
a6f177ef 4999
8e3d9d06
XG		 5000 /*
5001 * Do not retry the unhandleable instruction if it faults on the
5002 * readonly host memory, otherwise it will goto a infinite loop:
5003 * retry instruction -> write #PF -> emulation fail -> retry
5004 * instruction -> ...
5005 */
5006 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5007
5008 /*
5009 * If the instruction failed on the error pfn, it can not be fixed,
5010 * report the error to userspace.
5011 */
5012 if (is_error_noslot_pfn(pfn))
5013 return false;
5014
5015 kvm_release_pfn_clean(pfn);
5016
5017 /* The instructions are well-emulated on direct mmu. */
5018 if (vcpu->arch.mmu.direct_map) {
5019 unsigned int indirect_shadow_pages;
5020
5021 spin_lock(&vcpu->kvm->mmu_lock);
5022 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5023 spin_unlock(&vcpu->kvm->mmu_lock);
5024
5025 if (indirect_shadow_pages)
5026 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5027
a6f177ef 5028 return true;
8e3d9d06 5029 }
a6f177ef 5030
95b3cf69
XG		 5031 /*
5032 * if emulation was due to access to shadowed page table
5033 * and it failed try to unshadow page and re-enter the
5034 * guest to let CPU execute the instruction.
5035 */
5036 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5037
5038 /*
5039 * If the access faults on its page table, it can not
5040 * be fixed by unprotecting shadow page and it should
5041 * be reported to userspace.
5042 */
5043 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5044}
5045
1cb3f3ae
XG		 5046static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5047 unsigned long cr2, int emulation_type)
5048{
5049 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5050 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5051
5052 last_retry_eip = vcpu->arch.last_retry_eip;
5053 last_retry_addr = vcpu->arch.last_retry_addr;
5054
5055 /*
5056 * If the emulation is caused by #PF and it is non-page_table
5057 * writing instruction, it means the VM-EXIT is caused by shadow
5058 * page protected, we can zap the shadow page and retry this
5059 * instruction directly.
5060 *
5061 * Note: if the guest uses a non-page-table modifying instruction
5062 * on the PDE that points to the instruction, then we will unmap
5063 * the instruction and go to an infinite loop. So, we cache the
5064 * last retried eip and the last fault address, if we meet the eip
5065 * and the address again, we can break out of the potential infinite
5066 * loop.
5067 */
5068 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5069
5070 if (!(emulation_type & EMULTYPE_RETRY))
5071 return false;
5072
5073 if (x86_page_table_writing_insn(ctxt))
5074 return false;
5075
5076 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5077 return false;
5078
5079 vcpu->arch.last_retry_eip = ctxt->eip;
5080 vcpu->arch.last_retry_addr = cr2;
5081
5082 if (!vcpu->arch.mmu.direct_map)
5083 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5084
22368028 5085 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5086
5087 return true;
5088}
5089
716d51ab
GN		 5090static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5091static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5092
64d60670 5093static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5094{
64d60670 5095 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5096 /* This is a good place to trace that we are exiting SMM. */
5097 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5098
64d60670
PB		 5099 if (unlikely(vcpu->arch.smi_pending)) {
5100 kvm_make_request(KVM_REQ_SMI, vcpu);
5101 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5102 } else {
5103 /* Process a latched INIT, if any. */
5104 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5105 }
5106 }
699023e2
PB		 5107
5108 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5109}
5110
5111static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5112{
5113 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5114
a584539b 5115 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5116
5117 if (changed & HF_SMM_MASK)
5118 kvm_smm_changed(vcpu);
a584539b
PB		 5119}
5120
4a1e10d5
PB		 5121static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5122 unsigned long *db)
5123{
5124 u32 dr6 = 0;
5125 int i;
5126 u32 enable, rwlen;
5127
5128 enable = dr7;
5129 rwlen = dr7 >> 16;
5130 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5131 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5132 dr6 |= (1 << i);
5133 return dr6;
5134}
5135
6addfc42 5136static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5137{
5138 struct kvm_run *kvm_run = vcpu->run;
5139
5140 /*
6addfc42
PB		 5141 * rflags is the old, "raw" value of the flags. The new value has
5142 * not been saved yet.
663f4c61
PB		 5143 *
5144 * This is correct even for TF set by the guest, because "the
5145 * processor will not generate this exception after the instruction
5146 * that sets the TF flag".
5147 */
663f4c61
PB		 5148 if (unlikely(rflags & X86_EFLAGS_TF)) {
5149 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5150 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5151 DR6_RTM;
663f4c61
PB		 5152 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5153 kvm_run->debug.arch.exception = DB_VECTOR;
5154 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5155 *r = EMULATE_USER_EXIT;
5156 } else {
5157 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5158 /*
5159 * "Certain debug exceptions may clear bit 0-3. The
5160 * remaining contents of the DR6 register are never
5161 * cleared by the processor".
5162 */
5163 vcpu->arch.dr6 &= ~15;
6f43ed01 5164 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5165 kvm_queue_exception(vcpu, DB_VECTOR);
5166 }
5167 }
5168}
5169
4a1e10d5
PB		 5170static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5171{
4a1e10d5
PB		 5172 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5173 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5174 struct kvm_run *kvm_run = vcpu->run;
5175 unsigned long eip = kvm_get_linear_rip(vcpu);
5176 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5177 vcpu->arch.guest_debug_dr7,
5178 vcpu->arch.eff_db);
5179
5180 if (dr6 != 0) {
6f43ed01 5181 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5182 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5183 kvm_run->debug.arch.exception = DB_VECTOR;
5184 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5185 *r = EMULATE_USER_EXIT;
5186 return true;
5187 }
5188 }
5189
4161a569
NA		 5190 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5191 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5192 unsigned long eip = kvm_get_linear_rip(vcpu);
5193 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5194 vcpu->arch.dr7,
5195 vcpu->arch.db);
5196
5197 if (dr6 != 0) {
5198 vcpu->arch.dr6 &= ~15;
6f43ed01 5199 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5200 kvm_queue_exception(vcpu, DB_VECTOR);
5201 *r = EMULATE_DONE;
5202 return true;
5203 }
5204 }
5205
5206 return false;
5207}
5208
51d8b661
AP		 5209int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5210 unsigned long cr2,
dc25e89e
AP		 5211 int emulation_type,
5212 void *insn,
5213 int insn_len)
bbd9b64e 5214{
95cb2295 5215 int r;
9d74191a 5216 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5217 bool writeback = true;
93c05d3e 5218 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5219
93c05d3e
XG		 5220 /*
5221 * Clear write_fault_to_shadow_pgtable here to ensure it is
5222 * never reused.
5223 */
5224 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5225 kvm_clear_exception_queue(vcpu);
8d7d8102 5226
571008da 5227 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5228 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5229
5230 /*
5231 * We will reenter on the same instruction since
5232 * we do not set complete_userspace_io. This does not
5233 * handle watchpoints yet, those would be handled in
5234 * the emulate_ops.
5235 */
5236 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5237 return r;
5238
9d74191a
TY		 5239 ctxt->interruptibility = 0;
5240 ctxt->have_exception = false;
e0ad0b47 5241 ctxt->exception.vector = -1;
9d74191a 5242 ctxt->perm_ok = false;
bbd9b64e 5243
b51e974f 5244 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5245
9d74191a 5246 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5247
e46479f8 5248 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5249 ++vcpu->stat.insn_emulation;
1d2887e2 5250 if (r != EMULATION_OK) {
4005996e
AK		 5251 if (emulation_type & EMULTYPE_TRAP_UD)
5252 return EMULATE_FAIL;
991eebf9
GN		 5253 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5254 emulation_type))
bbd9b64e 5255 return EMULATE_DONE;
6d77dbfc
GN		 5256 if (emulation_type & EMULTYPE_SKIP)
5257 return EMULATE_FAIL;
5258 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5259 }
5260 }
5261
ba8afb6b 5262 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5263 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5264 if (ctxt->eflags & X86_EFLAGS_RF)
5265 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5266 return EMULATE_DONE;
5267 }
5268
1cb3f3ae
XG		 5269 if (retry_instruction(ctxt, cr2, emulation_type))
5270 return EMULATE_DONE;
5271
7ae441ea 5272 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5273 changes registers values during IO operation */
7ae441ea
GN		 5274 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5275 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5276 emulator_invalidate_register_cache(ctxt);
7ae441ea 5277 }
4d2179e1 5278
5cd21917 5279restart:
9d74191a 5280 r = x86_emulate_insn(ctxt);
bbd9b64e 5281
775fde86
JR		 5282 if (r == EMULATION_INTERCEPTED)
5283 return EMULATE_DONE;
5284
d2ddd1c4 5285 if (r == EMULATION_FAILED) {
991eebf9
GN		 5286 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5287 emulation_type))
c3cd7ffa
GN		 5288 return EMULATE_DONE;
5289
6d77dbfc 5290 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5291 }
5292
9d74191a 5293 if (ctxt->have_exception) {
d2ddd1c4 5294 r = EMULATE_DONE;
ef54bcfe
PB		 5295 if (inject_emulated_exception(vcpu))
5296 return r;
d2ddd1c4 5297 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5298 if (!vcpu->arch.pio.in) {
5299 /* FIXME: return into emulator if single-stepping. */
3457e419 5300 vcpu->arch.pio.count = 0;
0912c977 5301 } else {
7ae441ea 5302 writeback = false;
716d51ab
GN		 5303 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5304 }
ac0a48c3 5305 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5306 } else if (vcpu->mmio_needed) {
5307 if (!vcpu->mmio_is_write)
5308 writeback = false;
ac0a48c3 5309 r = EMULATE_USER_EXIT;
716d51ab 5310 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5311 } else if (r == EMULATION_RESTART)
5cd21917 5312 goto restart;
d2ddd1c4
GN		 5313 else
5314 r = EMULATE_DONE;
f850e2e6 5315
7ae441ea 5316 if (writeback) {
6addfc42 5317 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5318 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5319 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5320 if (vcpu->arch.hflags != ctxt->emul_flags)
5321 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5322 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5323 if (r == EMULATE_DONE)
6addfc42 5324 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5325 if (!ctxt->have_exception ||
5326 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5327 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5328
5329 /*
5330 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5331 * do nothing, and it will be requested again as soon as
5332 * the shadow expires. But we still need to check here,
5333 * because POPF has no interrupt shadow.
5334 */
5335 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5336 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5337 } else
5338 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5339
5340 return r;
de7d789a 5341}
51d8b661 5342EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5343
cf8f70bf 5344int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5345{
cf8f70bf 5346 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5347 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5348 size, port, &val, 1);
cf8f70bf 5349 /* do not return to emulator after return from userspace */
7972995b 5350 vcpu->arch.pio.count = 0;
de7d789a
CO		 5351 return ret;
5352}
cf8f70bf 5353EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5354
8cfdc000
ZA		 5355static void tsc_bad(void *info)
5356{
0a3aee0d 5357 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5358}
5359
5360static void tsc_khz_changed(void *data)
c8076604 5361{
8cfdc000
ZA		 5362 struct cpufreq_freqs *freq = data;
5363 unsigned long khz = 0;
5364
5365 if (data)
5366 khz = freq->new;
5367 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5368 khz = cpufreq_quick_get(raw_smp_processor_id());
5369 if (!khz)
5370 khz = tsc_khz;
0a3aee0d 5371 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5372}
5373
c8076604
GH		 5374static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5375 void *data)
5376{
5377 struct cpufreq_freqs *freq = data;
5378 struct kvm *kvm;
5379 struct kvm_vcpu *vcpu;
5380 int i, send_ipi = 0;
5381
8cfdc000
ZA		 5382 /*
5383 * We allow guests to temporarily run on slowing clocks,
5384 * provided we notify them after, or to run on accelerating
5385 * clocks, provided we notify them before. Thus time never
5386 * goes backwards.
5387 *
5388 * However, we have a problem. We can't atomically update
5389 * the frequency of a given CPU from this function; it is
5390 * merely a notifier, which can be called from any CPU.
5391 * Changing the TSC frequency at arbitrary points in time
5392 * requires a recomputation of local variables related to
5393 * the TSC for each VCPU. We must flag these local variables
5394 * to be updated and be sure the update takes place with the
5395 * new frequency before any guests proceed.
5396 *
5397 * Unfortunately, the combination of hotplug CPU and frequency
5398 * change creates an intractable locking scenario; the order
5399 * of when these callouts happen is undefined with respect to
5400 * CPU hotplug, and they can race with each other. As such,
5401 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5402 * undefined; you can actually have a CPU frequency change take
5403 * place in between the computation of X and the setting of the
5404 * variable. To protect against this problem, all updates of
5405 * the per_cpu tsc_khz variable are done in an interrupt
5406 * protected IPI, and all callers wishing to update the value
5407 * must wait for a synchronous IPI to complete (which is trivial
5408 * if the caller is on the CPU already). This establishes the
5409 * necessary total order on variable updates.
5410 *
5411 * Note that because a guest time update may take place
5412 * anytime after the setting of the VCPU's request bit, the
5413 * correct TSC value must be set before the request. However,
5414 * to ensure the update actually makes it to any guest which
5415 * starts running in hardware virtualization between the set
5416 * and the acquisition of the spinlock, we must also ping the
5417 * CPU after setting the request bit.
5418 *
5419 */
5420
c8076604
GH		 5421 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5422 return 0;
5423 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5424 return 0;
8cfdc000
ZA		 5425
5426 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5427
2f303b74 5428 spin_lock(&kvm_lock);
c8076604 5429 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5430 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5431 if (vcpu->cpu != freq->cpu)
5432 continue;
c285545f 5433 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5434 if (vcpu->cpu != smp_processor_id())
8cfdc000 5435 send_ipi = 1;
c8076604
GH		 5436 }
5437 }
2f303b74 5438 spin_unlock(&kvm_lock);
c8076604
GH		 5439
5440 if (freq->old < freq->new && send_ipi) {
5441 /*
5442 * We upscale the frequency. Must make the guest
5443 * doesn't see old kvmclock values while running with
5444 * the new frequency, otherwise we risk the guest sees
5445 * time go backwards.
5446 *
5447 * In case we update the frequency for another cpu
5448 * (which might be in guest context) send an interrupt
5449 * to kick the cpu out of guest context. Next time
5450 * guest context is entered kvmclock will be updated,
5451 * so the guest will not see stale values.
5452 */
8cfdc000 5453 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5454 }
5455 return 0;
5456}
5457
5458static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5459 .notifier_call = kvmclock_cpufreq_notifier
5460};
5461
5462static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5463 unsigned long action, void *hcpu)
5464{
5465 unsigned int cpu = (unsigned long)hcpu;
5466
5467 switch (action) {
5468 case CPU_ONLINE:
5469 case CPU_DOWN_FAILED:
5470 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5471 break;
5472 case CPU_DOWN_PREPARE:
5473 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5474 break;
5475 }
5476 return NOTIFY_OK;
5477}
5478
5479static struct notifier_block kvmclock_cpu_notifier_block = {
5480 .notifier_call = kvmclock_cpu_notifier,
5481 .priority = -INT_MAX
c8076604
GH		 5482};
5483
b820cc0c
ZA		 5484static void kvm_timer_init(void)
5485{
5486 int cpu;
5487
c285545f 5488 max_tsc_khz = tsc_khz;
460dd42e
SB		 5489
5490 cpu_notifier_register_begin();
b820cc0c 5491 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5492#ifdef CONFIG_CPU_FREQ
5493 struct cpufreq_policy policy;
5494 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5495 cpu = get_cpu();
5496 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5497 if (policy.cpuinfo.max_freq)
5498 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5499 put_cpu();
c285545f 5500#endif
b820cc0c
ZA		 5501 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5502 CPUFREQ_TRANSITION_NOTIFIER);
5503 }
c285545f 5504 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5505 for_each_online_cpu(cpu)
5506 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5507
5508 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5509 cpu_notifier_register_done();
5510
b820cc0c
ZA		 5511}
5512
ff9d07a0
ZY		 5513static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5514
f5132b01 5515int kvm_is_in_guest(void)
ff9d07a0 5516{
086c9855 5517 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5518}
5519
5520static int kvm_is_user_mode(void)
5521{
5522 int user_mode = 3;
dcf46b94 5523
086c9855
AS		 5524 if (__this_cpu_read(current_vcpu))
5525 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5526
ff9d07a0
ZY		 5527 return user_mode != 0;
5528}
5529
5530static unsigned long kvm_get_guest_ip(void)
5531{
5532 unsigned long ip = 0;
dcf46b94 5533
086c9855
AS		 5534 if (__this_cpu_read(current_vcpu))
5535 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5536
ff9d07a0
ZY		 5537 return ip;
5538}
5539
5540static struct perf_guest_info_callbacks kvm_guest_cbs = {
5541 .is_in_guest = kvm_is_in_guest,
5542 .is_user_mode = kvm_is_user_mode,
5543 .get_guest_ip = kvm_get_guest_ip,
5544};
5545
5546void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5547{
086c9855 5548 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5549}
5550EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5551
5552void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5553{
086c9855 5554 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5555}
5556EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5557
ce88decf
XG		 5558static void kvm_set_mmio_spte_mask(void)
5559{
5560 u64 mask;
5561 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5562
5563 /*
5564 * Set the reserved bits and the present bit of an paging-structure
5565 * entry to generate page fault with PFER.RSV = 1.
5566 */
885032b9 5567 /* Mask the reserved physical address bits. */
d1431483 5568 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5569
5570 /* Bit 62 is always reserved for 32bit host. */
5571 mask |= 0x3ull << 62;
5572
5573 /* Set the present bit. */
ce88decf
XG		 5574 mask |= 1ull;
5575
5576#ifdef CONFIG_X86_64
5577 /*
5578 * If reserved bit is not supported, clear the present bit to disable
5579 * mmio page fault.
5580 */
5581 if (maxphyaddr == 52)
5582 mask &= ~1ull;
5583#endif
5584
5585 kvm_mmu_set_mmio_spte_mask(mask);
5586}
5587
16e8d74d
MT		 5588#ifdef CONFIG_X86_64
5589static void pvclock_gtod_update_fn(struct work_struct *work)
5590{
d828199e
MT		 5591 struct kvm *kvm;
5592
5593 struct kvm_vcpu *vcpu;
5594 int i;
5595
2f303b74 5596 spin_lock(&kvm_lock);
d828199e
MT		 5597 list_for_each_entry(kvm, &vm_list, vm_list)
5598 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5599 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5600 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5601 spin_unlock(&kvm_lock);
16e8d74d
MT		 5602}
5603
5604static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5605
5606/*
5607 * Notification about pvclock gtod data update.
5608 */
5609static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5610 void *priv)
5611{
5612 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5613 struct timekeeper *tk = priv;
5614
5615 update_pvclock_gtod(tk);
5616
5617 /* disable master clock if host does not trust, or does not
5618 * use, TSC clocksource
5619 */
5620 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5621 atomic_read(&kvm_guest_has_master_clock) != 0)
5622 queue_work(system_long_wq, &pvclock_gtod_work);
5623
5624 return 0;
5625}
5626
5627static struct notifier_block pvclock_gtod_notifier = {
5628 .notifier_call = pvclock_gtod_notify,
5629};
5630#endif
5631
f8c16bba 5632int kvm_arch_init(void *opaque)
043405e1 5633{
b820cc0c 5634 int r;
6b61edf7 5635 struct kvm_x86_ops *ops = opaque;
f8c16bba 5636
f8c16bba
ZX		 5637 if (kvm_x86_ops) {
5638 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5639 r = -EEXIST;
5640 goto out;
f8c16bba
ZX		 5641 }
5642
5643 if (!ops->cpu_has_kvm_support()) {
5644 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5645 r = -EOPNOTSUPP;
5646 goto out;
f8c16bba
ZX		 5647 }
5648 if (ops->disabled_by_bios()) {
5649 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5650 r = -EOPNOTSUPP;
5651 goto out;
f8c16bba
ZX		 5652 }
5653
013f6a5d
MT		 5654 r = -ENOMEM;
5655 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5656 if (!shared_msrs) {
5657 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5658 goto out;
5659 }
5660
97db56ce
AK		 5661 r = kvm_mmu_module_init();
5662 if (r)
013f6a5d 5663 goto out_free_percpu;
97db56ce 5664
ce88decf 5665 kvm_set_mmio_spte_mask();
97db56ce 5666
f8c16bba 5667 kvm_x86_ops = ops;
920c8377 5668
7b52345e 5669 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5670 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5671
b820cc0c 5672 kvm_timer_init();
c8076604 5673
ff9d07a0
ZY		 5674 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5675
2acf923e
DC		 5676 if (cpu_has_xsave)
5677 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5678
c5cc421b 5679 kvm_lapic_init();
16e8d74d
MT		 5680#ifdef CONFIG_X86_64
5681 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5682#endif
5683
f8c16bba 5684 return 0;
56c6d28a 5685
013f6a5d
MT		 5686out_free_percpu:
5687 free_percpu(shared_msrs);
56c6d28a 5688out:
56c6d28a 5689 return r;
043405e1 5690}
8776e519 5691
f8c16bba
ZX		 5692void kvm_arch_exit(void)
5693{
ff9d07a0
ZY		 5694 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5695
888d256e
JK		 5696 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5697 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5698 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5699 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5700#ifdef CONFIG_X86_64
5701 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5702#endif
f8c16bba 5703 kvm_x86_ops = NULL;
56c6d28a 5704 kvm_mmu_module_exit();
013f6a5d 5705 free_percpu(shared_msrs);
56c6d28a 5706}
f8c16bba 5707
5cb56059 5708int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5709{
5710 ++vcpu->stat.halt_exits;
35754c98 5711 if (lapic_in_kernel(vcpu)) {
a4535290 5712 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5713 return 1;
5714 } else {
5715 vcpu->run->exit_reason = KVM_EXIT_HLT;
5716 return 0;
5717 }
5718}
5cb56059
JS		 5719EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5720
5721int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5722{
5723 kvm_x86_ops->skip_emulated_instruction(vcpu);
5724 return kvm_vcpu_halt(vcpu);
5725}
8776e519
HB		 5726EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5727
6aef266c
SV		 5728/*
5729 * kvm_pv_kick_cpu_op: Kick a vcpu.
5730 *
5731 * @apicid - apicid of vcpu to be kicked.
5732 */
5733static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5734{
24d2166b 5735 struct kvm_lapic_irq lapic_irq;
6aef266c 5736
24d2166b
R		 5737 lapic_irq.shorthand = 0;
5738 lapic_irq.dest_mode = 0;
5739 lapic_irq.dest_id = apicid;
93bbf0b8 5740 lapic_irq.msi_redir_hint = false;
6aef266c 5741
24d2166b 5742 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5743 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5744}
5745
8776e519
HB		 5746int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5747{
5748 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5749 int op_64_bit, r = 1;
8776e519 5750
5cb56059
JS		 5751 kvm_x86_ops->skip_emulated_instruction(vcpu);
5752
55cd8e5a
GN		 5753 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5754 return kvm_hv_hypercall(vcpu);
5755
5fdbf976
MT		 5756 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5757 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5758 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5759 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5760 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5761
229456fc 5762 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5763
a449c7aa
NA		 5764 op_64_bit = is_64_bit_mode(vcpu);
5765 if (!op_64_bit) {
8776e519
HB		 5766 nr &= 0xFFFFFFFF;
5767 a0 &= 0xFFFFFFFF;
5768 a1 &= 0xFFFFFFFF;
5769 a2 &= 0xFFFFFFFF;
5770 a3 &= 0xFFFFFFFF;
5771 }
5772
07708c4a
JK		 5773 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5774 ret = -KVM_EPERM;
5775 goto out;
5776 }
5777
8776e519 5778 switch (nr) {
b93463aa
AK		 5779 case KVM_HC_VAPIC_POLL_IRQ:
5780 ret = 0;
5781 break;
6aef266c
SV		 5782 case KVM_HC_KICK_CPU:
5783 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5784 ret = 0;
5785 break;
8776e519
HB		 5786 default:
5787 ret = -KVM_ENOSYS;
5788 break;
5789 }
07708c4a 5790out:
a449c7aa
NA		 5791 if (!op_64_bit)
5792 ret = (u32)ret;
5fdbf976 5793 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5794 ++vcpu->stat.hypercalls;
2f333bcb 5795 return r;
8776e519
HB		 5796}
5797EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5798
b6785def 5799static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5800{
d6aa1000 5801 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5802 char instruction[3];
5fdbf976 5803 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5804
8776e519 5805 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5806
9d74191a 5807 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5808}
5809
b6c7a5dc
HB		 5810/*
5811 * Check if userspace requested an interrupt window, and that the
5812 * interrupt window is open.
5813 *
5814 * No need to exit to userspace if we already have an interrupt queued.
5815 */
851ba692 5816static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5817{
1c1a9ce9
SR		 5818 if (!vcpu->run->request_interrupt_window || pic_in_kernel(vcpu->kvm))
5819 return false;
5820
5821 if (kvm_cpu_has_interrupt(vcpu))
5822 return false;
5823
5824 return (irqchip_split(vcpu->kvm)
5825 ? kvm_apic_accept_pic_intr(vcpu)
5826 : kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5827}
5828
851ba692 5829static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5830{
851ba692
AK		 5831 struct kvm_run *kvm_run = vcpu->run;
5832
91586a3b 5833 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5834 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5835 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5836 kvm_run->apic_base = kvm_get_apic_base(vcpu);
1c1a9ce9 5837 if (!irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5838 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5839 kvm_arch_interrupt_allowed(vcpu) &&
5840 !kvm_cpu_has_interrupt(vcpu) &&
5841 !kvm_event_needs_reinjection(vcpu);
1c1a9ce9
SR		 5842 else if (!pic_in_kernel(vcpu->kvm))
5843 kvm_run->ready_for_interrupt_injection =
5844 kvm_apic_accept_pic_intr(vcpu) &&
5845 !kvm_cpu_has_interrupt(vcpu);
5846 else
5847 kvm_run->ready_for_interrupt_injection = 1;
b6c7a5dc
HB		 5848}
5849
95ba8273
GN		 5850static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5851{
5852 int max_irr, tpr;
5853
5854 if (!kvm_x86_ops->update_cr8_intercept)
5855 return;
5856
88c808fd
AK		 5857 if (!vcpu->arch.apic)
5858 return;
5859
8db3baa2
GN		 5860 if (!vcpu->arch.apic->vapic_addr)
5861 max_irr = kvm_lapic_find_highest_irr(vcpu);
5862 else
5863 max_irr = -1;
95ba8273
GN		 5864
5865 if (max_irr != -1)
5866 max_irr >>= 4;
5867
5868 tpr = kvm_lapic_get_cr8(vcpu);
5869
5870 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5871}
5872
b6b8a145 5873static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5874{
b6b8a145
JK		 5875 int r;
5876
95ba8273 5877 /* try to reinject previous events if any */
b59bb7bd 5878 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5879 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5880 vcpu->arch.exception.has_error_code,
5881 vcpu->arch.exception.error_code);
d6e8c854
NA		 5882
5883 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5884 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5885 X86_EFLAGS_RF);
5886
6bdf0662
NA		 5887 if (vcpu->arch.exception.nr == DB_VECTOR &&
5888 (vcpu->arch.dr7 & DR7_GD)) {
5889 vcpu->arch.dr7 &= ~DR7_GD;
5890 kvm_update_dr7(vcpu);
5891 }
5892
b59bb7bd
GN		 5893 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5894 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5895 vcpu->arch.exception.error_code,
5896 vcpu->arch.exception.reinject);
b6b8a145 5897 return 0;
b59bb7bd
GN		 5898 }
5899
95ba8273
GN		 5900 if (vcpu->arch.nmi_injected) {
5901 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5902 return 0;
95ba8273
GN		 5903 }
5904
5905 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5906 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5907 return 0;
5908 }
5909
5910 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5911 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5912 if (r != 0)
5913 return r;
95ba8273
GN		 5914 }
5915
5916 /* try to inject new event if pending */
5917 if (vcpu->arch.nmi_pending) {
5918 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5919 --vcpu->arch.nmi_pending;
95ba8273
GN		 5920 vcpu->arch.nmi_injected = true;
5921 kvm_x86_ops->set_nmi(vcpu);
5922 }
c7c9c56c 5923 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5924 /*
5925 * Because interrupts can be injected asynchronously, we are
5926 * calling check_nested_events again here to avoid a race condition.
5927 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5928 * proposal and current concerns. Perhaps we should be setting
5929 * KVM_REQ_EVENT only on certain events and not unconditionally?
5930 */
5931 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5932 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5933 if (r != 0)
5934 return r;
5935 }
95ba8273 5936 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5937 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5938 false);
5939 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5940 }
5941 }
b6b8a145 5942 return 0;
95ba8273
GN		 5943}
5944
7460fb4a
AK		 5945static void process_nmi(struct kvm_vcpu *vcpu)
5946{
5947 unsigned limit = 2;
5948
5949 /*
5950 * x86 is limited to one NMI running, and one NMI pending after it.
5951 * If an NMI is already in progress, limit further NMIs to just one.
5952 * Otherwise, allow two (and we'll inject the first one immediately).
5953 */
5954 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5955 limit = 1;
5956
5957 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5958 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5959 kvm_make_request(KVM_REQ_EVENT, vcpu);
5960}
5961
660a5d51
PB		 5962#define put_smstate(type, buf, offset, val) \
5963 *(type *)((buf) + (offset) - 0x7e00) = val
5964
5965static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
5966{
5967 u32 flags = 0;
5968 flags |= seg->g << 23;
5969 flags |= seg->db << 22;
5970 flags |= seg->l << 21;
5971 flags |= seg->avl << 20;
5972 flags |= seg->present << 15;
5973 flags |= seg->dpl << 13;
5974 flags |= seg->s << 12;
5975 flags |= seg->type << 8;
5976 return flags;
5977}
5978
5979static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
5980{
5981 struct kvm_segment seg;
5982 int offset;
5983
5984 kvm_get_segment(vcpu, &seg, n);
5985 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
5986
5987 if (n < 3)
5988 offset = 0x7f84 + n * 12;
5989 else
5990 offset = 0x7f2c + (n - 3) * 12;
5991
5992 put_smstate(u32, buf, offset + 8, seg.base);
5993 put_smstate(u32, buf, offset + 4, seg.limit);
5994 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
5995}
5996
efbb288a 5997#ifdef CONFIG_X86_64
660a5d51
PB		 5998static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
5999{
6000 struct kvm_segment seg;
6001 int offset;
6002 u16 flags;
6003
6004 kvm_get_segment(vcpu, &seg, n);
6005 offset = 0x7e00 + n * 16;
6006
6007 flags = process_smi_get_segment_flags(&seg) >> 8;
6008 put_smstate(u16, buf, offset, seg.selector);
6009 put_smstate(u16, buf, offset + 2, flags);
6010 put_smstate(u32, buf, offset + 4, seg.limit);
6011 put_smstate(u64, buf, offset + 8, seg.base);
6012}
efbb288a 6013#endif
660a5d51
PB		 6014
6015static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6016{
6017 struct desc_ptr dt;
6018 struct kvm_segment seg;
6019 unsigned long val;
6020 int i;
6021
6022 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6023 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6024 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6025 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6026
6027 for (i = 0; i < 8; i++)
6028 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6029
6030 kvm_get_dr(vcpu, 6, &val);
6031 put_smstate(u32, buf, 0x7fcc, (u32)val);
6032 kvm_get_dr(vcpu, 7, &val);
6033 put_smstate(u32, buf, 0x7fc8, (u32)val);
6034
6035 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6036 put_smstate(u32, buf, 0x7fc4, seg.selector);
6037 put_smstate(u32, buf, 0x7f64, seg.base);
6038 put_smstate(u32, buf, 0x7f60, seg.limit);
6039 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6040
6041 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6042 put_smstate(u32, buf, 0x7fc0, seg.selector);
6043 put_smstate(u32, buf, 0x7f80, seg.base);
6044 put_smstate(u32, buf, 0x7f7c, seg.limit);
6045 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6046
6047 kvm_x86_ops->get_gdt(vcpu, &dt);
6048 put_smstate(u32, buf, 0x7f74, dt.address);
6049 put_smstate(u32, buf, 0x7f70, dt.size);
6050
6051 kvm_x86_ops->get_idt(vcpu, &dt);
6052 put_smstate(u32, buf, 0x7f58, dt.address);
6053 put_smstate(u32, buf, 0x7f54, dt.size);
6054
6055 for (i = 0; i < 6; i++)
6056 process_smi_save_seg_32(vcpu, buf, i);
6057
6058 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6059
6060 /* revision id */
6061 put_smstate(u32, buf, 0x7efc, 0x00020000);
6062 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6063}
6064
6065static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6066{
6067#ifdef CONFIG_X86_64
6068 struct desc_ptr dt;
6069 struct kvm_segment seg;
6070 unsigned long val;
6071 int i;
6072
6073 for (i = 0; i < 16; i++)
6074 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6075
6076 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6077 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6078
6079 kvm_get_dr(vcpu, 6, &val);
6080 put_smstate(u64, buf, 0x7f68, val);
6081 kvm_get_dr(vcpu, 7, &val);
6082 put_smstate(u64, buf, 0x7f60, val);
6083
6084 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6085 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6086 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6087
6088 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6089
6090 /* revision id */
6091 put_smstate(u32, buf, 0x7efc, 0x00020064);
6092
6093 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6094
6095 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6096 put_smstate(u16, buf, 0x7e90, seg.selector);
6097 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6098 put_smstate(u32, buf, 0x7e94, seg.limit);
6099 put_smstate(u64, buf, 0x7e98, seg.base);
6100
6101 kvm_x86_ops->get_idt(vcpu, &dt);
6102 put_smstate(u32, buf, 0x7e84, dt.size);
6103 put_smstate(u64, buf, 0x7e88, dt.address);
6104
6105 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6106 put_smstate(u16, buf, 0x7e70, seg.selector);
6107 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6108 put_smstate(u32, buf, 0x7e74, seg.limit);
6109 put_smstate(u64, buf, 0x7e78, seg.base);
6110
6111 kvm_x86_ops->get_gdt(vcpu, &dt);
6112 put_smstate(u32, buf, 0x7e64, dt.size);
6113 put_smstate(u64, buf, 0x7e68, dt.address);
6114
6115 for (i = 0; i < 6; i++)
6116 process_smi_save_seg_64(vcpu, buf, i);
6117#else
6118 WARN_ON_ONCE(1);
6119#endif
6120}
6121
64d60670
PB		 6122static void process_smi(struct kvm_vcpu *vcpu)
6123{
660a5d51 6124 struct kvm_segment cs, ds;
18c3626e 6125 struct desc_ptr dt;
660a5d51
PB		 6126 char buf[512];
6127 u32 cr0;
6128
64d60670
PB		 6129 if (is_smm(vcpu)) {
6130 vcpu->arch.smi_pending = true;
6131 return;
6132 }
6133
660a5d51
PB		 6134 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6135 vcpu->arch.hflags |= HF_SMM_MASK;
6136 memset(buf, 0, 512);
6137 if (guest_cpuid_has_longmode(vcpu))
6138 process_smi_save_state_64(vcpu, buf);
6139 else
6140 process_smi_save_state_32(vcpu, buf);
6141
54bf36aa 6142 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6143
6144 if (kvm_x86_ops->get_nmi_mask(vcpu))
6145 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6146 else
6147 kvm_x86_ops->set_nmi_mask(vcpu, true);
6148
6149 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6150 kvm_rip_write(vcpu, 0x8000);
6151
6152 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6153 kvm_x86_ops->set_cr0(vcpu, cr0);
6154 vcpu->arch.cr0 = cr0;
6155
6156 kvm_x86_ops->set_cr4(vcpu, 0);
6157
18c3626e
PB		 6158 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6159 dt.address = dt.size = 0;
6160 kvm_x86_ops->set_idt(vcpu, &dt);
6161
660a5d51
PB		 6162 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6163
6164 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6165 cs.base = vcpu->arch.smbase;
6166
6167 ds.selector = 0;
6168 ds.base = 0;
6169
6170 cs.limit = ds.limit = 0xffffffff;
6171 cs.type = ds.type = 0x3;
6172 cs.dpl = ds.dpl = 0;
6173 cs.db = ds.db = 0;
6174 cs.s = ds.s = 1;
6175 cs.l = ds.l = 0;
6176 cs.g = ds.g = 1;
6177 cs.avl = ds.avl = 0;
6178 cs.present = ds.present = 1;
6179 cs.unusable = ds.unusable = 0;
6180 cs.padding = ds.padding = 0;
6181
6182 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6183 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6184 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6185 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6186 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6187 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6188
6189 if (guest_cpuid_has_longmode(vcpu))
6190 kvm_x86_ops->set_efer(vcpu, 0);
6191
6192 kvm_update_cpuid(vcpu);
6193 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6194}
6195
3d81bc7e 6196static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6197{
3d81bc7e
YZ		 6198 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6199 return;
c7c9c56c 6200
3bb345f3 6201 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8);
c7c9c56c 6202
b053b2ae
SR		 6203 if (irqchip_split(vcpu->kvm))
6204 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap);
db2bdcbb
RK		 6205 else {
6206 kvm_x86_ops->sync_pir_to_irr(vcpu);
b053b2ae 6207 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap);
db2bdcbb 6208 }
3bb345f3 6209 kvm_x86_ops->load_eoi_exitmap(vcpu);
c7c9c56c
YZ		 6210}
6211
a70656b6
RK		 6212static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6213{
6214 ++vcpu->stat.tlb_flush;
6215 kvm_x86_ops->tlb_flush(vcpu);
6216}
6217
4256f43f
TC		 6218void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6219{
c24ae0dc
TC		 6220 struct page *page = NULL;
6221
35754c98 6222 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6223 return;
6224
4256f43f
TC		 6225 if (!kvm_x86_ops->set_apic_access_page_addr)
6226 return;
6227
c24ae0dc 6228 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6229 if (is_error_page(page))
6230 return;
c24ae0dc
TC		 6231 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6232
6233 /*
6234 * Do not pin apic access page in memory, the MMU notifier
6235 * will call us again if it is migrated or swapped out.
6236 */
6237 put_page(page);
4256f43f
TC		 6238}
6239EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6240
fe71557a
TC		 6241void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6242 unsigned long address)
6243{
c24ae0dc
TC		 6244 /*
6245 * The physical address of apic access page is stored in the VMCS.
6246 * Update it when it becomes invalid.
6247 */
6248 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6249 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6250}
6251
9357d939 6252/*
362c698f 6253 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6254 * exiting to the userspace. Otherwise, the value will be returned to the
6255 * userspace.
6256 */
851ba692 6257static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6258{
6259 int r;
35754c98 6260 bool req_int_win = !lapic_in_kernel(vcpu) &&
851ba692 6261 vcpu->run->request_interrupt_window;
730dca42 6262 bool req_immediate_exit = false;
b6c7a5dc 6263
3e007509 6264 if (vcpu->requests) {
a8eeb04a 6265 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6266 kvm_mmu_unload(vcpu);
a8eeb04a 6267 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6268 __kvm_migrate_timers(vcpu);
d828199e
MT		 6269 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6270 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6271 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6272 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6273 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6274 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6275 if (unlikely(r))
6276 goto out;
6277 }
a8eeb04a 6278 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6279 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6280 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6281 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6282 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6283 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6284 r = 0;
6285 goto out;
6286 }
a8eeb04a 6287 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6288 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6289 r = 0;
6290 goto out;
6291 }
a8eeb04a 6292 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6293 vcpu->fpu_active = 0;
6294 kvm_x86_ops->fpu_deactivate(vcpu);
6295 }
af585b92
GN		 6296 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6297 /* Page is swapped out. Do synthetic halt */
6298 vcpu->arch.apf.halted = true;
6299 r = 1;
6300 goto out;
6301 }
c9aaa895
GC		 6302 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6303 record_steal_time(vcpu);
64d60670
PB		 6304 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6305 process_smi(vcpu);
7460fb4a
AK		 6306 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6307 process_nmi(vcpu);
f5132b01 6308 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6309 kvm_pmu_handle_event(vcpu);
f5132b01 6310 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6311 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6312 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6313 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6314 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6315 (void *) vcpu->arch.eoi_exit_bitmap)) {
6316 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6317 vcpu->run->eoi.vector =
6318 vcpu->arch.pending_ioapic_eoi;
6319 r = 0;
6320 goto out;
6321 }
6322 }
3d81bc7e
YZ		 6323 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6324 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6325 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6326 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6327 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6328 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6329 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6330 r = 0;
6331 goto out;
6332 }
e516cebb
AS		 6333 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6334 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6335 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6336 r = 0;
6337 goto out;
6338 }
2f52d58c 6339 }
b93463aa 6340
bf9f6ac8
FW		 6341 /*
6342 * KVM_REQ_EVENT is not set when posted interrupts are set by
6343 * VT-d hardware, so we have to update RVI unconditionally.
6344 */
6345 if (kvm_lapic_enabled(vcpu)) {
6346 /*
6347 * Update architecture specific hints for APIC
6348 * virtual interrupt delivery.
6349 */
6350 if (kvm_x86_ops->hwapic_irr_update)
6351 kvm_x86_ops->hwapic_irr_update(vcpu,
6352 kvm_lapic_find_highest_irr(vcpu));
6353 }
6354
b463a6f7 6355 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6356 kvm_apic_accept_events(vcpu);
6357 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6358 r = 1;
6359 goto out;
6360 }
6361
b6b8a145
JK		 6362 if (inject_pending_event(vcpu, req_int_win) != 0)
6363 req_immediate_exit = true;
b463a6f7 6364 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6365 else if (vcpu->arch.nmi_pending)
c9a7953f 6366 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6367 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6368 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6369
6370 if (kvm_lapic_enabled(vcpu)) {
6371 update_cr8_intercept(vcpu);
6372 kvm_lapic_sync_to_vapic(vcpu);
6373 }
6374 }
6375
d8368af8
AK		 6376 r = kvm_mmu_reload(vcpu);
6377 if (unlikely(r)) {
d905c069 6378 goto cancel_injection;
d8368af8
AK		 6379 }
6380
b6c7a5dc
HB		 6381 preempt_disable();
6382
6383 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6384 if (vcpu->fpu_active)
6385 kvm_load_guest_fpu(vcpu);
2acf923e 6386 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6387
6b7e2d09
XG		 6388 vcpu->mode = IN_GUEST_MODE;
6389
01b71917
MT		 6390 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6391
6b7e2d09
XG		 6392 /* We should set ->mode before check ->requests,
6393 * see the comment in make_all_cpus_request.
6394 */
01b71917 6395 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6396
d94e1dc9 6397 local_irq_disable();
32f88400 6398
6b7e2d09 6399 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6400 || need_resched() || signal_pending(current)) {
6b7e2d09 6401 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6402 smp_wmb();
6c142801
AK		 6403 local_irq_enable();
6404 preempt_enable();
01b71917 6405 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6406 r = 1;
d905c069 6407 goto cancel_injection;
6c142801
AK		 6408 }
6409
d6185f20
NHE		 6410 if (req_immediate_exit)
6411 smp_send_reschedule(vcpu->cpu);
6412
ccf73aaf 6413 __kvm_guest_enter();
b6c7a5dc 6414
42dbaa5a 6415 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6416 set_debugreg(0, 7);
6417 set_debugreg(vcpu->arch.eff_db[0], 0);
6418 set_debugreg(vcpu->arch.eff_db[1], 1);
6419 set_debugreg(vcpu->arch.eff_db[2], 2);
6420 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6421 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6422 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6423 }
b6c7a5dc 6424
229456fc 6425 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6426 wait_lapic_expire(vcpu);
851ba692 6427 kvm_x86_ops->run(vcpu);
b6c7a5dc 6428
c77fb5fe
PB		 6429 /*
6430 * Do this here before restoring debug registers on the host. And
6431 * since we do this before handling the vmexit, a DR access vmexit
6432 * can (a) read the correct value of the debug registers, (b) set
6433 * KVM_DEBUGREG_WONT_EXIT again.
6434 */
6435 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6436 int i;
6437
6438 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6439 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6440 for (i = 0; i < KVM_NR_DB_REGS; i++)
6441 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6442 }
6443
24f1e32c
FW		 6444 /*
6445 * If the guest has used debug registers, at least dr7
6446 * will be disabled while returning to the host.
6447 * If we don't have active breakpoints in the host, we don't
6448 * care about the messed up debug address registers. But if
6449 * we have some of them active, restore the old state.
6450 */
59d8eb53 6451 if (hw_breakpoint_active())
24f1e32c 6452 hw_breakpoint_restore();
42dbaa5a 6453
886b470c 6454 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
4ea1636b 6455 rdtsc());
1d5f066e 6456
6b7e2d09 6457 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6458 smp_wmb();
a547c6db
YZ		 6459
6460 /* Interrupt is enabled by handle_external_intr() */
6461 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6462
6463 ++vcpu->stat.exits;
6464
6465 /*
6466 * We must have an instruction between local_irq_enable() and
6467 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6468 * the interrupt shadow. The stat.exits increment will do nicely.
6469 * But we need to prevent reordering, hence this barrier():
6470 */
6471 barrier();
6472
6473 kvm_guest_exit();
6474
6475 preempt_enable();
6476
f656ce01 6477 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6478
b6c7a5dc
HB		 6479 /*
6480 * Profile KVM exit RIPs:
6481 */
6482 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6483 unsigned long rip = kvm_rip_read(vcpu);
6484 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6485 }
6486
cc578287
ZA		 6487 if (unlikely(vcpu->arch.tsc_always_catchup))
6488 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6489
5cfb1d5a
MT		 6490 if (vcpu->arch.apic_attention)
6491 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6492
851ba692 6493 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6494 return r;
6495
6496cancel_injection:
6497 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6498 if (unlikely(vcpu->arch.apic_attention))
6499 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6500out:
6501 return r;
6502}
b6c7a5dc 6503
362c698f
PB		 6504static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6505{
bf9f6ac8
FW		 6506 if (!kvm_arch_vcpu_runnable(vcpu) &&
6507 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6508 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6509 kvm_vcpu_block(vcpu);
6510 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6511
6512 if (kvm_x86_ops->post_block)
6513 kvm_x86_ops->post_block(vcpu);
6514
9c8fd1ba
PB		 6515 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6516 return 1;
6517 }
362c698f
PB		 6518
6519 kvm_apic_accept_events(vcpu);
6520 switch(vcpu->arch.mp_state) {
6521 case KVM_MP_STATE_HALTED:
6522 vcpu->arch.pv.pv_unhalted = false;
6523 vcpu->arch.mp_state =
6524 KVM_MP_STATE_RUNNABLE;
6525 case KVM_MP_STATE_RUNNABLE:
6526 vcpu->arch.apf.halted = false;
6527 break;
6528 case KVM_MP_STATE_INIT_RECEIVED:
6529 break;
6530 default:
6531 return -EINTR;
6532 break;
6533 }
6534 return 1;
6535}
09cec754 6536
5d9bc648
PB		 6537static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6538{
6539 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6540 !vcpu->arch.apf.halted);
6541}
6542
362c698f 6543static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6544{
6545 int r;
f656ce01 6546 struct kvm *kvm = vcpu->kvm;
d7690175 6547
f656ce01 6548 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6549
362c698f 6550 for (;;) {
58f800d5 6551 if (kvm_vcpu_running(vcpu)) {
851ba692 6552 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6553 } else {
362c698f 6554 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6555 }
6556
09cec754
GN		 6557 if (r <= 0)
6558 break;
6559
6560 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6561 if (kvm_cpu_has_pending_timer(vcpu))
6562 kvm_inject_pending_timer_irqs(vcpu);
6563
851ba692 6564 if (dm_request_for_irq_injection(vcpu)) {
4ca7dd8c
PB		 6565 r = 0;
6566 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6567 ++vcpu->stat.request_irq_exits;
362c698f 6568 break;
09cec754 6569 }
af585b92
GN		 6570
6571 kvm_check_async_pf_completion(vcpu);
6572
09cec754
GN		 6573 if (signal_pending(current)) {
6574 r = -EINTR;
851ba692 6575 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6576 ++vcpu->stat.signal_exits;
362c698f 6577 break;
09cec754
GN		 6578 }
6579 if (need_resched()) {
f656ce01 6580 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6581 cond_resched();
f656ce01 6582 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6583 }
b6c7a5dc
HB		 6584 }
6585
f656ce01 6586 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6587
6588 return r;
6589}
6590
716d51ab
GN		 6591static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6592{
6593 int r;
6594 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6595 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6596 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6597 if (r != EMULATE_DONE)
6598 return 0;
6599 return 1;
6600}
6601
6602static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6603{
6604 BUG_ON(!vcpu->arch.pio.count);
6605
6606 return complete_emulated_io(vcpu);
6607}
6608
f78146b0
AK		 6609/*
6610 * Implements the following, as a state machine:
6611 *
6612 * read:
6613 * for each fragment
87da7e66
XG		 6614 * for each mmio piece in the fragment
6615 * write gpa, len
6616 * exit
6617 * copy data
f78146b0
AK		 6618 * execute insn
6619 *
6620 * write:
6621 * for each fragment
87da7e66
XG		 6622 * for each mmio piece in the fragment
6623 * write gpa, len
6624 * copy data
6625 * exit
f78146b0 6626 */
716d51ab 6627static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6628{
6629 struct kvm_run *run = vcpu->run;
f78146b0 6630 struct kvm_mmio_fragment *frag;
87da7e66 6631 unsigned len;
5287f194 6632
716d51ab 6633 BUG_ON(!vcpu->mmio_needed);
5287f194 6634
716d51ab 6635 /* Complete previous fragment */
87da7e66
XG		 6636 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6637 len = min(8u, frag->len);
716d51ab 6638 if (!vcpu->mmio_is_write)
87da7e66
XG		 6639 memcpy(frag->data, run->mmio.data, len);
6640
6641 if (frag->len <= 8) {
6642 /* Switch to the next fragment. */
6643 frag++;
6644 vcpu->mmio_cur_fragment++;
6645 } else {
6646 /* Go forward to the next mmio piece. */
6647 frag->data += len;
6648 frag->gpa += len;
6649 frag->len -= len;
6650 }
6651
a08d3b3b 6652 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6653 vcpu->mmio_needed = 0;
0912c977
PB		 6654
6655 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6656 if (vcpu->mmio_is_write)
716d51ab
GN		 6657 return 1;
6658 vcpu->mmio_read_completed = 1;
6659 return complete_emulated_io(vcpu);
6660 }
87da7e66 6661
716d51ab
GN		 6662 run->exit_reason = KVM_EXIT_MMIO;
6663 run->mmio.phys_addr = frag->gpa;
6664 if (vcpu->mmio_is_write)
87da7e66
XG		 6665 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6666 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6667 run->mmio.is_write = vcpu->mmio_is_write;
6668 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6669 return 0;
5287f194
AK		 6670}
6671
716d51ab 6672
b6c7a5dc
HB		 6673int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6674{
c5bedc68 6675 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6676 int r;
6677 sigset_t sigsaved;
6678
c4d72e2d 6679 fpu__activate_curr(fpu);
e5c30142 6680
ac9f6dc0
AK		 6681 if (vcpu->sigset_active)
6682 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6683
a4535290 6684 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6685 kvm_vcpu_block(vcpu);
66450a21 6686 kvm_apic_accept_events(vcpu);
d7690175 6687 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6688 r = -EAGAIN;
6689 goto out;
b6c7a5dc
HB		 6690 }
6691
b6c7a5dc 6692 /* re-sync apic's tpr */
35754c98 6693 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6694 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6695 r = -EINVAL;
6696 goto out;
6697 }
6698 }
b6c7a5dc 6699
716d51ab
GN		 6700 if (unlikely(vcpu->arch.complete_userspace_io)) {
6701 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6702 vcpu->arch.complete_userspace_io = NULL;
6703 r = cui(vcpu);
6704 if (r <= 0)
6705 goto out;
6706 } else
6707 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6708
362c698f 6709 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6710
6711out:
f1d86e46 6712 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6713 if (vcpu->sigset_active)
6714 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6715
b6c7a5dc
HB		 6716 return r;
6717}
6718
6719int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6720{
7ae441ea
GN		 6721 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6722 /*
6723 * We are here if userspace calls get_regs() in the middle of
6724 * instruction emulation. Registers state needs to be copied
4a969980 6725 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6726 * that usually, but some bad designed PV devices (vmware
6727 * backdoor interface) need this to work
6728 */
dd856efa 6729 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6730 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6731 }
5fdbf976
MT		 6732 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6733 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6734 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6735 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6736 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6737 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6738 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6739 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6740#ifdef CONFIG_X86_64
5fdbf976
MT		 6741 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6742 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6743 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6744 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6745 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6746 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6747 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6748 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6749#endif
6750
5fdbf976 6751 regs->rip = kvm_rip_read(vcpu);
91586a3b 6752 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6753
b6c7a5dc
HB		 6754 return 0;
6755}
6756
6757int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6758{
7ae441ea
GN		 6759 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6760 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6761
5fdbf976
MT		 6762 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6763 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6764 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6765 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6766 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6767 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6768 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6769 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6770#ifdef CONFIG_X86_64
5fdbf976
MT		 6771 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6772 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6773 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6774 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6775 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6776 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6777 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6778 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6779#endif
6780
5fdbf976 6781 kvm_rip_write(vcpu, regs->rip);
91586a3b 6782 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6783
b4f14abd
JK		 6784 vcpu->arch.exception.pending = false;
6785
3842d135
AK		 6786 kvm_make_request(KVM_REQ_EVENT, vcpu);
6787
b6c7a5dc
HB		 6788 return 0;
6789}
6790
b6c7a5dc
HB		 6791void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6792{
6793 struct kvm_segment cs;
6794
3e6e0aab 6795 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6796 *db = cs.db;
6797 *l = cs.l;
6798}
6799EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6800
6801int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6802 struct kvm_sregs *sregs)
6803{
89a27f4d 6804 struct desc_ptr dt;
b6c7a5dc 6805
3e6e0aab
GT		 6806 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6807 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6808 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6809 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6810 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6811 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6812
3e6e0aab
GT		 6813 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6814 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6815
6816 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6817 sregs->idt.limit = dt.size;
6818 sregs->idt.base = dt.address;
b6c7a5dc 6819 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6820 sregs->gdt.limit = dt.size;
6821 sregs->gdt.base = dt.address;
b6c7a5dc 6822
4d4ec087 6823 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6824 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6825 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6826 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6827 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6828 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6829 sregs->apic_base = kvm_get_apic_base(vcpu);
6830
923c61bb 6831 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6832
36752c9b 6833 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6834 set_bit(vcpu->arch.interrupt.nr,
6835 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6836
b6c7a5dc
HB		 6837 return 0;
6838}
6839
62d9f0db
MT		 6840int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6841 struct kvm_mp_state *mp_state)
6842{
66450a21 6843 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6844 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6845 vcpu->arch.pv.pv_unhalted)
6846 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6847 else
6848 mp_state->mp_state = vcpu->arch.mp_state;
6849
62d9f0db
MT		 6850 return 0;
6851}
6852
6853int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6854 struct kvm_mp_state *mp_state)
6855{
66450a21
JK		 6856 if (!kvm_vcpu_has_lapic(vcpu) &&
6857 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6858 return -EINVAL;
6859
6860 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6861 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6862 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6863 } else
6864 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6865 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6866 return 0;
6867}
6868
7f3d35fd
KW		 6869int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6870 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6871{
9d74191a 6872 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6873 int ret;
e01c2426 6874
8ec4722d 6875 init_emulate_ctxt(vcpu);
c697518a 6876
7f3d35fd 6877 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6878 has_error_code, error_code);
c697518a 6879
c697518a 6880 if (ret)
19d04437 6881 return EMULATE_FAIL;
37817f29 6882
9d74191a
TY		 6883 kvm_rip_write(vcpu, ctxt->eip);
6884 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6885 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6886 return EMULATE_DONE;
37817f29
IE		 6887}
6888EXPORT_SYMBOL_GPL(kvm_task_switch);
6889
b6c7a5dc
HB		 6890int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6891 struct kvm_sregs *sregs)
6892{
58cb628d 6893 struct msr_data apic_base_msr;
b6c7a5dc 6894 int mmu_reset_needed = 0;
63f42e02 6895 int pending_vec, max_bits, idx;
89a27f4d 6896 struct desc_ptr dt;
b6c7a5dc 6897
6d1068b3
PM		 6898 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6899 return -EINVAL;
6900
89a27f4d
GN		 6901 dt.size = sregs->idt.limit;
6902 dt.address = sregs->idt.base;
b6c7a5dc 6903 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6904 dt.size = sregs->gdt.limit;
6905 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6906 kvm_x86_ops->set_gdt(vcpu, &dt);
6907
ad312c7c 6908 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6909 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6910 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6911 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6912
2d3ad1f4 6913 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6914
f6801dff 6915 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6916 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6917 apic_base_msr.data = sregs->apic_base;
6918 apic_base_msr.host_initiated = true;
6919 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6920
4d4ec087 6921 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6922 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6923 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6924
fc78f519 6925 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6926 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6927 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6928 kvm_update_cpuid(vcpu);
63f42e02
XG		 6929
6930 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6931 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6932 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6933 mmu_reset_needed = 1;
6934 }
63f42e02 6935 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6936
6937 if (mmu_reset_needed)
6938 kvm_mmu_reset_context(vcpu);
6939
a50abc3b 6940 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6941 pending_vec = find_first_bit(
6942 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6943 if (pending_vec < max_bits) {
66fd3f7f 6944 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6945 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6946 }
6947
3e6e0aab
GT		 6948 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6949 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6950 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6951 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6952 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6953 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6954
3e6e0aab
GT		 6955 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6956 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6957
5f0269f5
ME		 6958 update_cr8_intercept(vcpu);
6959
9c3e4aab 6960 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6961 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6962 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6963 !is_protmode(vcpu))
9c3e4aab
MT		 6964 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6965
3842d135
AK		 6966 kvm_make_request(KVM_REQ_EVENT, vcpu);
6967
b6c7a5dc
HB		 6968 return 0;
6969}
6970
d0bfb940
JK		 6971int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6972 struct kvm_guest_debug *dbg)
b6c7a5dc 6973{
355be0b9 6974 unsigned long rflags;
ae675ef0 6975 int i, r;
b6c7a5dc 6976
4f926bf2
JK		 6977 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6978 r = -EBUSY;
6979 if (vcpu->arch.exception.pending)
2122ff5e 6980 goto out;
4f926bf2
JK		 6981 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6982 kvm_queue_exception(vcpu, DB_VECTOR);
6983 else
6984 kvm_queue_exception(vcpu, BP_VECTOR);
6985 }
6986
91586a3b
JK		 6987 /*
6988 * Read rflags as long as potentially injected trace flags are still
6989 * filtered out.
6990 */
6991 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6992
6993 vcpu->guest_debug = dbg->control;
6994 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6995 vcpu->guest_debug = 0;
6996
6997 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6998 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6999 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7000 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7001 } else {
7002 for (i = 0; i < KVM_NR_DB_REGS; i++)
7003 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7004 }
c8639010 7005 kvm_update_dr7(vcpu);
ae675ef0 7006
f92653ee
JK		 7007 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7008 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7009 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7010
91586a3b
JK		 7011 /*
7012 * Trigger an rflags update that will inject or remove the trace
7013 * flags.
7014 */
7015 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7016
c8639010 7017 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 7018
4f926bf2 7019 r = 0;
d0bfb940 7020
2122ff5e 7021out:
b6c7a5dc
HB		 7022
7023 return r;
7024}
7025
8b006791
ZX		 7026/*
7027 * Translate a guest virtual address to a guest physical address.
7028 */
7029int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7030 struct kvm_translation *tr)
7031{
7032 unsigned long vaddr = tr->linear_address;
7033 gpa_t gpa;
f656ce01 7034 int idx;
8b006791 7035
f656ce01 7036 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7037 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7038 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7039 tr->physical_address = gpa;
7040 tr->valid = gpa != UNMAPPED_GVA;
7041 tr->writeable = 1;
7042 tr->usermode = 0;
8b006791
ZX		 7043
7044 return 0;
7045}
7046
d0752060
HB		 7047int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7048{
c47ada30 7049 struct fxregs_state *fxsave =
7366ed77 7050 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7051
d0752060
HB		 7052 memcpy(fpu->fpr, fxsave->st_space, 128);
7053 fpu->fcw = fxsave->cwd;
7054 fpu->fsw = fxsave->swd;
7055 fpu->ftwx = fxsave->twd;
7056 fpu->last_opcode = fxsave->fop;
7057 fpu->last_ip = fxsave->rip;
7058 fpu->last_dp = fxsave->rdp;
7059 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7060
d0752060
HB		 7061 return 0;
7062}
7063
7064int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7065{
c47ada30 7066 struct fxregs_state *fxsave =
7366ed77 7067 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7068
d0752060
HB		 7069 memcpy(fxsave->st_space, fpu->fpr, 128);
7070 fxsave->cwd = fpu->fcw;
7071 fxsave->swd = fpu->fsw;
7072 fxsave->twd = fpu->ftwx;
7073 fxsave->fop = fpu->last_opcode;
7074 fxsave->rip = fpu->last_ip;
7075 fxsave->rdp = fpu->last_dp;
7076 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7077
d0752060
HB		 7078 return 0;
7079}
7080
0ee6a517 7081static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7082{
bf935b0b 7083 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7084 if (cpu_has_xsaves)
7366ed77 7085 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7086 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7087
2acf923e
DC		 7088 /*
7089 * Ensure guest xcr0 is valid for loading
7090 */
7091 vcpu->arch.xcr0 = XSTATE_FP;
7092
ad312c7c 7093 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7094}
d0752060
HB		 7095
7096void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7097{
2608d7a1 7098 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7099 return;
7100
2acf923e
DC		 7101 /*
7102 * Restore all possible states in the guest,
7103 * and assume host would use all available bits.
7104 * Guest xcr0 would be loaded later.
7105 */
7106 kvm_put_guest_xcr0(vcpu);
d0752060 7107 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7108 __kernel_fpu_begin();
003e2e8b 7109 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7110 trace_kvm_fpu(1);
d0752060 7111}
d0752060
HB		 7112
7113void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7114{
2acf923e
DC		 7115 kvm_put_guest_xcr0(vcpu);
7116
653f52c3
RR		 7117 if (!vcpu->guest_fpu_loaded) {
7118 vcpu->fpu_counter = 0;
d0752060 7119 return;
653f52c3 7120 }
d0752060
HB		 7121
7122 vcpu->guest_fpu_loaded = 0;
4f836347 7123 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7124 __kernel_fpu_end();
f096ed85 7125 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7126 /*
7127 * If using eager FPU mode, or if the guest is a frequent user
7128 * of the FPU, just leave the FPU active for next time.
7129 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7130 * the FPU in bursts will revert to loading it on demand.
7131 */
a9b4fb7e 7132 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7133 if (++vcpu->fpu_counter < 5)
7134 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7135 }
0c04851c 7136 trace_kvm_fpu(0);
d0752060 7137}
e9b11c17
ZX		 7138
7139void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7140{
12f9a48f 7141 kvmclock_reset(vcpu);
7f1ea208 7142
f5f48ee1 7143 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7144 kvm_x86_ops->vcpu_free(vcpu);
7145}
7146
7147struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7148 unsigned int id)
7149{
c447e76b
LL		 7150 struct kvm_vcpu *vcpu;
7151
6755bae8
ZA		 7152 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7153 printk_once(KERN_WARNING
7154 "kvm: SMP vm created on host with unstable TSC; "
7155 "guest TSC will not be reliable\n");
c447e76b
LL		 7156
7157 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7158
c447e76b 7159 return vcpu;
26e5215f 7160}
e9b11c17 7161
26e5215f
AK		 7162int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7163{
7164 int r;
e9b11c17 7165
19efffa2 7166 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7167 r = vcpu_load(vcpu);
7168 if (r)
7169 return r;
d28bc9dd 7170 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7171 kvm_mmu_setup(vcpu);
e9b11c17 7172 vcpu_put(vcpu);
26e5215f 7173 return r;
e9b11c17
ZX		 7174}
7175
31928aa5 7176void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7177{
8fe8ab46 7178 struct msr_data msr;
332967a3 7179 struct kvm *kvm = vcpu->kvm;
42897d86 7180
31928aa5
DD		 7181 if (vcpu_load(vcpu))
7182 return;
8fe8ab46
WA		 7183 msr.data = 0x0;
7184 msr.index = MSR_IA32_TSC;
7185 msr.host_initiated = true;
7186 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7187 vcpu_put(vcpu);
7188
630994b3
MT		 7189 if (!kvmclock_periodic_sync)
7190 return;
7191
332967a3
AJ		 7192 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7193 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7194}
7195
d40ccc62 7196void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7197{
9fc77441 7198 int r;
344d9588
GN		 7199 vcpu->arch.apf.msr_val = 0;
7200
9fc77441
MT		 7201 r = vcpu_load(vcpu);
7202 BUG_ON(r);
e9b11c17
ZX		 7203 kvm_mmu_unload(vcpu);
7204 vcpu_put(vcpu);
7205
7206 kvm_x86_ops->vcpu_free(vcpu);
7207}
7208
d28bc9dd 7209void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7210{
e69fab5d
PB		 7211 vcpu->arch.hflags = 0;
7212
7460fb4a
AK		 7213 atomic_set(&vcpu->arch.nmi_queued, 0);
7214 vcpu->arch.nmi_pending = 0;
448fa4a9 7215 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7216 kvm_clear_interrupt_queue(vcpu);
7217 kvm_clear_exception_queue(vcpu);
448fa4a9 7218
42dbaa5a 7219 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7220 kvm_update_dr0123(vcpu);
6f43ed01 7221 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7222 kvm_update_dr6(vcpu);
42dbaa5a 7223 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7224 kvm_update_dr7(vcpu);
42dbaa5a 7225
1119022c
NA		 7226 vcpu->arch.cr2 = 0;
7227
3842d135 7228 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7229 vcpu->arch.apf.msr_val = 0;
c9aaa895 7230 vcpu->arch.st.msr_val = 0;
3842d135 7231
12f9a48f
GC		 7232 kvmclock_reset(vcpu);
7233
af585b92
GN		 7234 kvm_clear_async_pf_completion_queue(vcpu);
7235 kvm_async_pf_hash_reset(vcpu);
7236 vcpu->arch.apf.halted = false;
3842d135 7237
64d60670 7238 if (!init_event) {
d28bc9dd 7239 kvm_pmu_reset(vcpu);
64d60670
PB		 7240 vcpu->arch.smbase = 0x30000;
7241 }
f5132b01 7242
66f7b72e
JS		 7243 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7244 vcpu->arch.regs_avail = ~0;
7245 vcpu->arch.regs_dirty = ~0;
7246
d28bc9dd 7247 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7248}
7249
2b4a273b 7250void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7251{
7252 struct kvm_segment cs;
7253
7254 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7255 cs.selector = vector << 8;
7256 cs.base = vector << 12;
7257 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7258 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7259}
7260
13a34e06 7261int kvm_arch_hardware_enable(void)
e9b11c17 7262{
ca84d1a2
ZA		 7263 struct kvm *kvm;
7264 struct kvm_vcpu *vcpu;
7265 int i;
0dd6a6ed
ZA		 7266 int ret;
7267 u64 local_tsc;
7268 u64 max_tsc = 0;
7269 bool stable, backwards_tsc = false;
18863bdd
AK		 7270
7271 kvm_shared_msr_cpu_online();
13a34e06 7272 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7273 if (ret != 0)
7274 return ret;
7275
4ea1636b 7276 local_tsc = rdtsc();
0dd6a6ed
ZA		 7277 stable = !check_tsc_unstable();
7278 list_for_each_entry(kvm, &vm_list, vm_list) {
7279 kvm_for_each_vcpu(i, vcpu, kvm) {
7280 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7281 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7282 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7283 backwards_tsc = true;
7284 if (vcpu->arch.last_host_tsc > max_tsc)
7285 max_tsc = vcpu->arch.last_host_tsc;
7286 }
7287 }
7288 }
7289
7290 /*
7291 * Sometimes, even reliable TSCs go backwards. This happens on
7292 * platforms that reset TSC during suspend or hibernate actions, but
7293 * maintain synchronization. We must compensate. Fortunately, we can
7294 * detect that condition here, which happens early in CPU bringup,
7295 * before any KVM threads can be running. Unfortunately, we can't
7296 * bring the TSCs fully up to date with real time, as we aren't yet far
7297 * enough into CPU bringup that we know how much real time has actually
7298 * elapsed; our helper function, get_kernel_ns() will be using boot
7299 * variables that haven't been updated yet.
7300 *
7301 * So we simply find the maximum observed TSC above, then record the
7302 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7303 * the adjustment will be applied. Note that we accumulate
7304 * adjustments, in case multiple suspend cycles happen before some VCPU
7305 * gets a chance to run again. In the event that no KVM threads get a
7306 * chance to run, we will miss the entire elapsed period, as we'll have
7307 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7308 * loose cycle time. This isn't too big a deal, since the loss will be
7309 * uniform across all VCPUs (not to mention the scenario is extremely
7310 * unlikely). It is possible that a second hibernate recovery happens
7311 * much faster than a first, causing the observed TSC here to be
7312 * smaller; this would require additional padding adjustment, which is
7313 * why we set last_host_tsc to the local tsc observed here.
7314 *
7315 * N.B. - this code below runs only on platforms with reliable TSC,
7316 * as that is the only way backwards_tsc is set above. Also note
7317 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7318 * have the same delta_cyc adjustment applied if backwards_tsc
7319 * is detected. Note further, this adjustment is only done once,
7320 * as we reset last_host_tsc on all VCPUs to stop this from being
7321 * called multiple times (one for each physical CPU bringup).
7322 *
4a969980 7323 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7324 * will be compensated by the logic in vcpu_load, which sets the TSC to
7325 * catchup mode. This will catchup all VCPUs to real time, but cannot
7326 * guarantee that they stay in perfect synchronization.
7327 */
7328 if (backwards_tsc) {
7329 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7330 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7331 list_for_each_entry(kvm, &vm_list, vm_list) {
7332 kvm_for_each_vcpu(i, vcpu, kvm) {
7333 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7334 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7335 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7336 }
7337
7338 /*
7339 * We have to disable TSC offset matching.. if you were
7340 * booting a VM while issuing an S4 host suspend....
7341 * you may have some problem. Solving this issue is
7342 * left as an exercise to the reader.
7343 */
7344 kvm->arch.last_tsc_nsec = 0;
7345 kvm->arch.last_tsc_write = 0;
7346 }
7347
7348 }
7349 return 0;
e9b11c17
ZX		 7350}
7351
13a34e06 7352void kvm_arch_hardware_disable(void)
e9b11c17 7353{
13a34e06
RK		 7354 kvm_x86_ops->hardware_disable();
7355 drop_user_return_notifiers();
e9b11c17
ZX		 7356}
7357
7358int kvm_arch_hardware_setup(void)
7359{
9e9c3fe4
NA		 7360 int r;
7361
7362 r = kvm_x86_ops->hardware_setup();
7363 if (r != 0)
7364 return r;
7365
7366 kvm_init_msr_list();
7367 return 0;
e9b11c17
ZX		 7368}
7369
7370void kvm_arch_hardware_unsetup(void)
7371{
7372 kvm_x86_ops->hardware_unsetup();
7373}
7374
7375void kvm_arch_check_processor_compat(void *rtn)
7376{
7377 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7378}
7379
7380bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7381{
7382 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7383}
7384EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7385
7386bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7387{
7388 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7389}
7390
3e515705
AK		 7391bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7392{
35754c98 7393 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7394}
7395
54e9818f
GN		 7396struct static_key kvm_no_apic_vcpu __read_mostly;
7397
e9b11c17
ZX		 7398int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7399{
7400 struct page *page;
7401 struct kvm *kvm;
7402 int r;
7403
7404 BUG_ON(vcpu->kvm == NULL);
7405 kvm = vcpu->kvm;
7406
6aef266c 7407 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7408 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7409 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7410 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7411 else
a4535290 7412 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7413
7414 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7415 if (!page) {
7416 r = -ENOMEM;
7417 goto fail;
7418 }
ad312c7c 7419 vcpu->arch.pio_data = page_address(page);
e9b11c17 7420
cc578287 7421 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7422
e9b11c17
ZX		 7423 r = kvm_mmu_create(vcpu);
7424 if (r < 0)
7425 goto fail_free_pio_data;
7426
7427 if (irqchip_in_kernel(kvm)) {
7428 r = kvm_create_lapic(vcpu);
7429 if (r < 0)
7430 goto fail_mmu_destroy;
54e9818f
GN		 7431 } else
7432 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7433
890ca9ae
HY		 7434 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7435 GFP_KERNEL);
7436 if (!vcpu->arch.mce_banks) {
7437 r = -ENOMEM;
443c39bc 7438 goto fail_free_lapic;
890ca9ae
HY		 7439 }
7440 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7441
f1797359
WY		 7442 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7443 r = -ENOMEM;
f5f48ee1 7444 goto fail_free_mce_banks;
f1797359 7445 }
f5f48ee1 7446
0ee6a517 7447 fx_init(vcpu);
66f7b72e 7448
ba904635 7449 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7450 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7451
7452 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7453 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7454
5a4f55cd
EK		 7455 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7456
74545705
RK		 7457 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7458
af585b92 7459 kvm_async_pf_hash_reset(vcpu);
f5132b01 7460 kvm_pmu_init(vcpu);
af585b92 7461
1c1a9ce9
SR		 7462 vcpu->arch.pending_external_vector = -1;
7463
e9b11c17 7464 return 0;
0ee6a517 7465
f5f48ee1
SY		 7466fail_free_mce_banks:
7467 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7468fail_free_lapic:
7469 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7470fail_mmu_destroy:
7471 kvm_mmu_destroy(vcpu);
7472fail_free_pio_data:
ad312c7c 7473 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7474fail:
7475 return r;
7476}
7477
7478void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7479{
f656ce01
MT		 7480 int idx;
7481
f5132b01 7482 kvm_pmu_destroy(vcpu);
36cb93fd 7483 kfree(vcpu->arch.mce_banks);
e9b11c17 7484 kvm_free_lapic(vcpu);
f656ce01 7485 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7486 kvm_mmu_destroy(vcpu);
f656ce01 7487 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7488 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7489 if (!lapic_in_kernel(vcpu))
54e9818f 7490 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7491}
d19a9cd2 7492
e790d9ef
RK		 7493void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7494{
ae97a3b8 7495 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7496}
7497
e08b9637 7498int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7499{
e08b9637
CO		 7500 if (type)
7501 return -EINVAL;
7502
6ef768fa 7503 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7504 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7505 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7506 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7507 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7508
5550af4d
SY		 7509 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7510 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7511 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7512 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7513 &kvm->arch.irq_sources_bitmap);
5550af4d 7514
038f8c11 7515 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7516 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7517 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7518
7519 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7520
7e44e449 7521 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7522 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7523
d89f5eff 7524 return 0;
d19a9cd2
ZX		 7525}
7526
7527static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7528{
9fc77441
MT		 7529 int r;
7530 r = vcpu_load(vcpu);
7531 BUG_ON(r);
d19a9cd2
ZX		 7532 kvm_mmu_unload(vcpu);
7533 vcpu_put(vcpu);
7534}
7535
7536static void kvm_free_vcpus(struct kvm *kvm)
7537{
7538 unsigned int i;
988a2cae 7539 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7540
7541 /*
7542 * Unpin any mmu pages first.
7543 */
af585b92
GN		 7544 kvm_for_each_vcpu(i, vcpu, kvm) {
7545 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7546 kvm_unload_vcpu_mmu(vcpu);
af585b92 7547 }
988a2cae
GN		 7548 kvm_for_each_vcpu(i, vcpu, kvm)
7549 kvm_arch_vcpu_free(vcpu);
7550
7551 mutex_lock(&kvm->lock);
7552 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7553 kvm->vcpus[i] = NULL;
d19a9cd2 7554
988a2cae
GN		 7555 atomic_set(&kvm->online_vcpus, 0);
7556 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7557}
7558
ad8ba2cd
SY		 7559void kvm_arch_sync_events(struct kvm *kvm)
7560{
332967a3 7561 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7562 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7563 kvm_free_all_assigned_devices(kvm);
aea924f6 7564 kvm_free_pit(kvm);
ad8ba2cd
SY		 7565}
7566
1d8007bd 7567int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7568{
7569 int i, r;
25188b99 7570 unsigned long hva;
f0d648bd
PB		 7571 struct kvm_memslots *slots = kvm_memslots(kvm);
7572 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7573
7574 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7575 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7576 return -EINVAL;
9da0e4d5 7577
f0d648bd
PB		 7578 slot = id_to_memslot(slots, id);
7579 if (size) {
7580 if (WARN_ON(slot->npages))
7581 return -EEXIST;
7582
7583 /*
7584 * MAP_SHARED to prevent internal slot pages from being moved
7585 * by fork()/COW.
7586 */
7587 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7588 MAP_SHARED | MAP_ANONYMOUS, 0);
7589 if (IS_ERR((void *)hva))
7590 return PTR_ERR((void *)hva);
7591 } else {
7592 if (!slot->npages)
7593 return 0;
9da0e4d5 7594
f0d648bd
PB		 7595 hva = 0;
7596 }
7597
7598 old = *slot;
9da0e4d5 7599 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7600 struct kvm_userspace_memory_region m;
9da0e4d5 7601
1d8007bd
PB		 7602 m.slot = id | (i << 16);
7603 m.flags = 0;
7604 m.guest_phys_addr = gpa;
f0d648bd 7605 m.userspace_addr = hva;
1d8007bd 7606 m.memory_size = size;
9da0e4d5
PB		 7607 r = __kvm_set_memory_region(kvm, &m);
7608 if (r < 0)
7609 return r;
7610 }
7611
f0d648bd
PB		 7612 if (!size) {
7613 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7614 WARN_ON(r < 0);
7615 }
7616
9da0e4d5
PB		 7617 return 0;
7618}
7619EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7620
1d8007bd 7621int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7622{
7623 int r;
7624
7625 mutex_lock(&kvm->slots_lock);
1d8007bd 7626 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7627 mutex_unlock(&kvm->slots_lock);
7628
7629 return r;
7630}
7631EXPORT_SYMBOL_GPL(x86_set_memory_region);
7632
d19a9cd2
ZX		 7633void kvm_arch_destroy_vm(struct kvm *kvm)
7634{
27469d29
AH		 7635 if (current->mm == kvm->mm) {
7636 /*
7637 * Free memory regions allocated on behalf of userspace,
7638 * unless the the memory map has changed due to process exit
7639 * or fd copying.
7640 */
1d8007bd
PB		 7641 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7642 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7643 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7644 }
6eb55818 7645 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7646 kfree(kvm->arch.vpic);
7647 kfree(kvm->arch.vioapic);
d19a9cd2 7648 kvm_free_vcpus(kvm);
1e08ec4a 7649 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7650}
0de10343 7651
5587027c 7652void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7653 struct kvm_memory_slot *dont)
7654{
7655 int i;
7656
d89cc617
TY		 7657 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7658 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7659 kvfree(free->arch.rmap[i]);
d89cc617 7660 free->arch.rmap[i] = NULL;
77d11309 7661 }
d89cc617
TY		 7662 if (i == 0)
7663 continue;
7664
7665 if (!dont || free->arch.lpage_info[i - 1] !=
7666 dont->arch.lpage_info[i - 1]) {
548ef284 7667 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7668 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7669 }
7670 }
7671}
7672
5587027c
AK		 7673int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7674 unsigned long npages)
db3fe4eb
TY		 7675{
7676 int i;
7677
d89cc617 7678 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7679 unsigned long ugfn;
7680 int lpages;
d89cc617 7681 int level = i + 1;
db3fe4eb
TY		 7682
7683 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7684 slot->base_gfn, level) + 1;
7685
d89cc617
TY		 7686 slot->arch.rmap[i] =
7687 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7688 if (!slot->arch.rmap[i])
77d11309 7689 goto out_free;
d89cc617
TY		 7690 if (i == 0)
7691 continue;
77d11309 7692
d89cc617
TY		 7693 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7694 sizeof(*slot->arch.lpage_info[i - 1]));
7695 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7696 goto out_free;
7697
7698 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7699 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7700 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7701 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7702 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7703 /*
7704 * If the gfn and userspace address are not aligned wrt each
7705 * other, or if explicitly asked to, disable large page
7706 * support for this slot
7707 */
7708 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7709 !kvm_largepages_enabled()) {
7710 unsigned long j;
7711
7712 for (j = 0; j < lpages; ++j)
d89cc617 7713 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7714 }
7715 }
7716
7717 return 0;
7718
7719out_free:
d89cc617 7720 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7721 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7722 slot->arch.rmap[i] = NULL;
7723 if (i == 0)
7724 continue;
7725
548ef284 7726 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7727 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7728 }
7729 return -ENOMEM;
7730}
7731
15f46015 7732void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7733{
e6dff7d1
TY		 7734 /*
7735 * memslots->generation has been incremented.
7736 * mmio generation may have reached its maximum value.
7737 */
54bf36aa 7738 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7739}
7740
f7784b8e
MT		 7741int kvm_arch_prepare_memory_region(struct kvm *kvm,
7742 struct kvm_memory_slot *memslot,
09170a49 7743 const struct kvm_userspace_memory_region *mem,
7b6195a9 7744 enum kvm_mr_change change)
0de10343 7745{
f7784b8e
MT		 7746 return 0;
7747}
7748
88178fd4
KH		 7749static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7750 struct kvm_memory_slot *new)
7751{
7752 /* Still write protect RO slot */
7753 if (new->flags & KVM_MEM_READONLY) {
7754 kvm_mmu_slot_remove_write_access(kvm, new);
7755 return;
7756 }
7757
7758 /*
7759 * Call kvm_x86_ops dirty logging hooks when they are valid.
7760 *
7761 * kvm_x86_ops->slot_disable_log_dirty is called when:
7762 *
7763 * - KVM_MR_CREATE with dirty logging is disabled
7764 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7765 *
7766 * The reason is, in case of PML, we need to set D-bit for any slots
7767 * with dirty logging disabled in order to eliminate unnecessary GPA
7768 * logging in PML buffer (and potential PML buffer full VMEXT). This
7769 * guarantees leaving PML enabled during guest's lifetime won't have
7770 * any additonal overhead from PML when guest is running with dirty
7771 * logging disabled for memory slots.
7772 *
7773 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7774 * to dirty logging mode.
7775 *
7776 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7777 *
7778 * In case of write protect:
7779 *
7780 * Write protect all pages for dirty logging.
7781 *
7782 * All the sptes including the large sptes which point to this
7783 * slot are set to readonly. We can not create any new large
7784 * spte on this slot until the end of the logging.
7785 *
7786 * See the comments in fast_page_fault().
7787 */
7788 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7789 if (kvm_x86_ops->slot_enable_log_dirty)
7790 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7791 else
7792 kvm_mmu_slot_remove_write_access(kvm, new);
7793 } else {
7794 if (kvm_x86_ops->slot_disable_log_dirty)
7795 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7796 }
7797}
7798
f7784b8e 7799void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7800 const struct kvm_userspace_memory_region *mem,
8482644a 7801 const struct kvm_memory_slot *old,
f36f3f28 7802 const struct kvm_memory_slot *new,
8482644a 7803 enum kvm_mr_change change)
f7784b8e 7804{
8482644a 7805 int nr_mmu_pages = 0;
f7784b8e 7806
48c0e4e9
XG		 7807 if (!kvm->arch.n_requested_mmu_pages)
7808 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7809
48c0e4e9 7810 if (nr_mmu_pages)
0de10343 7811 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7812
3ea3b7fa
WL		 7813 /*
7814 * Dirty logging tracks sptes in 4k granularity, meaning that large
7815 * sptes have to be split. If live migration is successful, the guest
7816 * in the source machine will be destroyed and large sptes will be
7817 * created in the destination. However, if the guest continues to run
7818 * in the source machine (for example if live migration fails), small
7819 * sptes will remain around and cause bad performance.
7820 *
7821 * Scan sptes if dirty logging has been stopped, dropping those
7822 * which can be collapsed into a single large-page spte. Later
7823 * page faults will create the large-page sptes.
7824 */
7825 if ((change != KVM_MR_DELETE) &&
7826 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7827 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7828 kvm_mmu_zap_collapsible_sptes(kvm, new);
7829
c972f3b1 7830 /*
88178fd4 7831 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7832 *
88178fd4
KH		 7833 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7834 * been zapped so no dirty logging staff is needed for old slot. For
7835 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7836 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7837 *
7838 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7839 */
88178fd4 7840 if (change != KVM_MR_DELETE)
f36f3f28 7841 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7842}
1d737c8a 7843
2df72e9b 7844void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7845{
6ca18b69 7846 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7847}
7848
2df72e9b
MT		 7849void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7850 struct kvm_memory_slot *slot)
7851{
6ca18b69 7852 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7853}
7854
5d9bc648
PB		 7855static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
7856{
7857 if (!list_empty_careful(&vcpu->async_pf.done))
7858 return true;
7859
7860 if (kvm_apic_has_events(vcpu))
7861 return true;
7862
7863 if (vcpu->arch.pv.pv_unhalted)
7864 return true;
7865
7866 if (atomic_read(&vcpu->arch.nmi_queued))
7867 return true;
7868
73917739
PB		 7869 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
7870 return true;
7871
5d9bc648
PB		 7872 if (kvm_arch_interrupt_allowed(vcpu) &&
7873 kvm_cpu_has_interrupt(vcpu))
7874 return true;
7875
7876 return false;
7877}
7878
1d737c8a
ZX		 7879int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7880{
b6b8a145
JK		 7881 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7882 kvm_x86_ops->check_nested_events(vcpu, false);
7883
5d9bc648 7884 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 7885}
5736199a 7886
b6d33834 7887int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7888{
b6d33834 7889 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7890}
78646121
GN		 7891
7892int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7893{
7894 return kvm_x86_ops->interrupt_allowed(vcpu);
7895}
229456fc 7896
82b32774 7897unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 7898{
82b32774
NA		 7899 if (is_64_bit_mode(vcpu))
7900 return kvm_rip_read(vcpu);
7901 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
7902 kvm_rip_read(vcpu));
7903}
7904EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 7905
82b32774
NA		 7906bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7907{
7908 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 7909}
7910EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7911
94fe45da
JK		 7912unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7913{
7914 unsigned long rflags;
7915
7916 rflags = kvm_x86_ops->get_rflags(vcpu);
7917 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7918 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7919 return rflags;
7920}
7921EXPORT_SYMBOL_GPL(kvm_get_rflags);
7922
6addfc42 7923static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7924{
7925 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7926 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7927 rflags |= X86_EFLAGS_TF;
94fe45da 7928 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7929}
7930
7931void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7932{
7933 __kvm_set_rflags(vcpu, rflags);
3842d135 7934 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7935}
7936EXPORT_SYMBOL_GPL(kvm_set_rflags);
7937
56028d08
GN		 7938void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7939{
7940 int r;
7941
fb67e14f 7942 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7943 work->wakeup_all)
56028d08
GN		 7944 return;
7945
7946 r = kvm_mmu_reload(vcpu);
7947 if (unlikely(r))
7948 return;
7949
fb67e14f
XG		 7950 if (!vcpu->arch.mmu.direct_map &&
7951 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7952 return;
7953
56028d08
GN		 7954 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7955}
7956
af585b92
GN		 7957static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7958{
7959 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7960}
7961
7962static inline u32 kvm_async_pf_next_probe(u32 key)
7963{
7964 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7965}
7966
7967static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7968{
7969 u32 key = kvm_async_pf_hash_fn(gfn);
7970
7971 while (vcpu->arch.apf.gfns[key] != ~0)
7972 key = kvm_async_pf_next_probe(key);
7973
7974 vcpu->arch.apf.gfns[key] = gfn;
7975}
7976
7977static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7978{
7979 int i;
7980 u32 key = kvm_async_pf_hash_fn(gfn);
7981
7982 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7983 (vcpu->arch.apf.gfns[key] != gfn &&
7984 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7985 key = kvm_async_pf_next_probe(key);
7986
7987 return key;
7988}
7989
7990bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7991{
7992 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7993}
7994
7995static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7996{
7997 u32 i, j, k;
7998
7999 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8000 while (true) {
8001 vcpu->arch.apf.gfns[i] = ~0;
8002 do {
8003 j = kvm_async_pf_next_probe(j);
8004 if (vcpu->arch.apf.gfns[j] == ~0)
8005 return;
8006 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8007 /*
8008 * k lies cyclically in ]i,j]
8009 * | i.k.j |
8010 * |....j i.k.| or |.k..j i...|
8011 */
8012 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8013 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8014 i = j;
8015 }
8016}
8017
7c90705b
GN		 8018static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8019{
8020
8021 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8022 sizeof(val));
8023}
8024
af585b92
GN		 8025void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8026 struct kvm_async_pf *work)
8027{
6389ee94
AK		 8028 struct x86_exception fault;
8029
7c90705b 8030 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8031 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8032
8033 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8034 (vcpu->arch.apf.send_user_only &&
8035 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8036 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8037 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8038 fault.vector = PF_VECTOR;
8039 fault.error_code_valid = true;
8040 fault.error_code = 0;
8041 fault.nested_page_fault = false;
8042 fault.address = work->arch.token;
8043 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8044 }
af585b92
GN		 8045}
8046
8047void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8048 struct kvm_async_pf *work)
8049{
6389ee94
AK		 8050 struct x86_exception fault;
8051
7c90705b 8052 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8053 if (work->wakeup_all)
7c90705b
GN		 8054 work->arch.token = ~0; /* broadcast wakeup */
8055 else
8056 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8057
8058 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8059 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8060 fault.vector = PF_VECTOR;
8061 fault.error_code_valid = true;
8062 fault.error_code = 0;
8063 fault.nested_page_fault = false;
8064 fault.address = work->arch.token;
8065 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8066 }
e6d53e3b 8067 vcpu->arch.apf.halted = false;
a4fa1635 8068 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8069}
8070
8071bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8072{
8073 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8074 return true;
8075 else
8076 return !kvm_event_needs_reinjection(vcpu) &&
8077 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8078}
8079
5544eb9b
PB		 8080void kvm_arch_start_assignment(struct kvm *kvm)
8081{
8082 atomic_inc(&kvm->arch.assigned_device_count);
8083}
8084EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8085
8086void kvm_arch_end_assignment(struct kvm *kvm)
8087{
8088 atomic_dec(&kvm->arch.assigned_device_count);
8089}
8090EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8091
8092bool kvm_arch_has_assigned_device(struct kvm *kvm)
8093{
8094 return atomic_read(&kvm->arch.assigned_device_count);
8095}
8096EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8097
e0f0bbc5
AW		 8098void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8099{
8100 atomic_inc(&kvm->arch.noncoherent_dma_count);
8101}
8102EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8103
8104void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8105{
8106 atomic_dec(&kvm->arch.noncoherent_dma_count);
8107}
8108EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8109
8110bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8111{
8112 return atomic_read(&kvm->arch.noncoherent_dma_count);
8113}
8114EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8115
87276880
FW		 8116int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8117 struct irq_bypass_producer *prod)
8118{
8119 struct kvm_kernel_irqfd *irqfd =
8120 container_of(cons, struct kvm_kernel_irqfd, consumer);
8121
8122 if (kvm_x86_ops->update_pi_irte) {
8123 irqfd->producer = prod;
8124 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8125 prod->irq, irqfd->gsi, 1);
8126 }
8127
8128 return -EINVAL;
8129}
8130
8131void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8132 struct irq_bypass_producer *prod)
8133{
8134 int ret;
8135 struct kvm_kernel_irqfd *irqfd =
8136 container_of(cons, struct kvm_kernel_irqfd, consumer);
8137
8138 if (!kvm_x86_ops->update_pi_irte) {
8139 WARN_ON(irqfd->producer != NULL);
8140 return;
8141 }
8142
8143 WARN_ON(irqfd->producer != prod);
8144 irqfd->producer = NULL;
8145
8146 /*
8147 * When producer of consumer is unregistered, we change back to
8148 * remapped mode, so we can re-use the current implementation
8149 * when the irq is masked/disabed or the consumer side (KVM
8150 * int this case doesn't want to receive the interrupts.
8151 */
8152 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8153 if (ret)
8154 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8155 " fails: %d\n", irqfd->consumer.token, ret);
8156}
8157
8158int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8159 uint32_t guest_irq, bool set)
8160{
8161 if (!kvm_x86_ops->update_pi_irte)
8162 return -EINVAL;
8163
8164 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8165}
8166
229456fc 8167EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8168EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8169EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8170EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8171EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8172EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8173EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8174EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8175EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8176EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8177EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8178EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8179EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8180EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8181EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8182EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8183EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
Linux 6.x block layer and io_uring tree(s)