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KVM: x86: Check non-canonical addresses upon WRMSR
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
92a1f12d
JR		 101bool kvm_has_tsc_control;
102EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103u32 kvm_max_guest_tsc_khz;
104EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105
cc578287
ZA		 106/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107static u32 tsc_tolerance_ppm = 250;
108module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109
16a96021
MT		 110static bool backwards_tsc_observed = false;
111
18863bdd
AK		 112#define KVM_NR_SHARED_MSRS 16
113
114struct kvm_shared_msrs_global {
115 int nr;
2bf78fa7 116 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 117};
118
119struct kvm_shared_msrs {
120 struct user_return_notifier urn;
121 bool registered;
2bf78fa7
SY		 122 struct kvm_shared_msr_values {
123 u64 host;
124 u64 curr;
125 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 126};
127
128static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 129static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 130
417bc304 131struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 132 { "pf_fixed", VCPU_STAT(pf_fixed) },
133 { "pf_guest", VCPU_STAT(pf_guest) },
134 { "tlb_flush", VCPU_STAT(tlb_flush) },
135 { "invlpg", VCPU_STAT(invlpg) },
136 { "exits", VCPU_STAT(exits) },
137 { "io_exits", VCPU_STAT(io_exits) },
138 { "mmio_exits", VCPU_STAT(mmio_exits) },
139 { "signal_exits", VCPU_STAT(signal_exits) },
140 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 141 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 142 { "halt_exits", VCPU_STAT(halt_exits) },
143 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 144 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 145 { "request_irq", VCPU_STAT(request_irq_exits) },
146 { "irq_exits", VCPU_STAT(irq_exits) },
147 { "host_state_reload", VCPU_STAT(host_state_reload) },
148 { "efer_reload", VCPU_STAT(efer_reload) },
149 { "fpu_reload", VCPU_STAT(fpu_reload) },
150 { "insn_emulation", VCPU_STAT(insn_emulation) },
151 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 152 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 153 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 154 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
155 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
156 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
157 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
158 { "mmu_flooded", VM_STAT(mmu_flooded) },
159 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 160 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 161 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 162 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 163 { "largepages", VM_STAT(lpages) },
417bc304
HB		 164 { NULL }
165};
166
2acf923e
DC		 167u64 __read_mostly host_xcr0;
168
b6785def 169static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 170
af585b92
GN		 171static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
172{
173 int i;
174 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
175 vcpu->arch.apf.gfns[i] = ~0;
176}
177
18863bdd
AK		 178static void kvm_on_user_return(struct user_return_notifier *urn)
179{
180 unsigned slot;
18863bdd
AK		 181 struct kvm_shared_msrs *locals
182 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 183 struct kvm_shared_msr_values *values;
18863bdd
AK		 184
185 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 186 values = &locals->values[slot];
187 if (values->host != values->curr) {
188 wrmsrl(shared_msrs_global.msrs[slot], values->host);
189 values->curr = values->host;
18863bdd
AK		 190 }
191 }
192 locals->registered = false;
193 user_return_notifier_unregister(urn);
194}
195
2bf78fa7 196static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 197{
18863bdd 198 u64 value;
013f6a5d
MT		 199 unsigned int cpu = smp_processor_id();
200 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 201
2bf78fa7
SY		 202 /* only read, and nobody should modify it at this time,
203 * so don't need lock */
204 if (slot >= shared_msrs_global.nr) {
205 printk(KERN_ERR "kvm: invalid MSR slot!");
206 return;
207 }
208 rdmsrl_safe(msr, &value);
209 smsr->values[slot].host = value;
210 smsr->values[slot].curr = value;
211}
212
213void kvm_define_shared_msr(unsigned slot, u32 msr)
214{
0123be42 215 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 216 if (slot >= shared_msrs_global.nr)
217 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 218 shared_msrs_global.msrs[slot] = msr;
219 /* we need ensured the shared_msr_global have been updated */
220 smp_wmb();
18863bdd
AK		 221}
222EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
223
224static void kvm_shared_msr_cpu_online(void)
225{
226 unsigned i;
18863bdd
AK		 227
228 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 229 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 230}
231
d5696725 232void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 233{
013f6a5d
MT		 234 unsigned int cpu = smp_processor_id();
235 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 236
2bf78fa7 237 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 238 return;
2bf78fa7
SY		 239 smsr->values[slot].curr = value;
240 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 241 if (!smsr->registered) {
242 smsr->urn.on_user_return = kvm_on_user_return;
243 user_return_notifier_register(&smsr->urn);
244 smsr->registered = true;
245 }
246}
247EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
248
13a34e06 249static void drop_user_return_notifiers(void)
3548bab5 250{
013f6a5d
MT		 251 unsigned int cpu = smp_processor_id();
252 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 253
254 if (smsr->registered)
255 kvm_on_user_return(&smsr->urn);
256}
257
6866b83e
CO		 258u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
259{
8a5a87d9 260 return vcpu->arch.apic_base;
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_get_apic_base);
263
58cb628d
JK		 264int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
265{
266 u64 old_state = vcpu->arch.apic_base &
267 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
268 u64 new_state = msr_info->data &
269 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
270 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
271 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
272
273 if (!msr_info->host_initiated &&
274 ((msr_info->data & reserved_bits) != 0 ||
275 new_state == X2APIC_ENABLE ||
276 (new_state == MSR_IA32_APICBASE_ENABLE &&
277 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
278 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
279 old_state == 0)))
280 return 1;
281
282 kvm_lapic_set_base(vcpu, msr_info->data);
283 return 0;
6866b83e
CO		 284}
285EXPORT_SYMBOL_GPL(kvm_set_apic_base);
286
2605fc21 287asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 288{
289 /* Fault while not rebooting. We want the trace. */
290 BUG();
291}
292EXPORT_SYMBOL_GPL(kvm_spurious_fault);
293
3fd28fce
ED		 294#define EXCPT_BENIGN 0
295#define EXCPT_CONTRIBUTORY 1
296#define EXCPT_PF 2
297
298static int exception_class(int vector)
299{
300 switch (vector) {
301 case PF_VECTOR:
302 return EXCPT_PF;
303 case DE_VECTOR:
304 case TS_VECTOR:
305 case NP_VECTOR:
306 case SS_VECTOR:
307 case GP_VECTOR:
308 return EXCPT_CONTRIBUTORY;
309 default:
310 break;
311 }
312 return EXCPT_BENIGN;
313}
314
d6e8c854
NA		 315#define EXCPT_FAULT 0
316#define EXCPT_TRAP 1
317#define EXCPT_ABORT 2
318#define EXCPT_INTERRUPT 3
319
320static int exception_type(int vector)
321{
322 unsigned int mask;
323
324 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
325 return EXCPT_INTERRUPT;
326
327 mask = 1 << vector;
328
329 /* #DB is trap, as instruction watchpoints are handled elsewhere */
330 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
331 return EXCPT_TRAP;
332
333 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
334 return EXCPT_ABORT;
335
336 /* Reserved exceptions will result in fault */
337 return EXCPT_FAULT;
338}
339
3fd28fce 340static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 341 unsigned nr, bool has_error, u32 error_code,
342 bool reinject)
3fd28fce
ED		 343{
344 u32 prev_nr;
345 int class1, class2;
346
3842d135
AK		 347 kvm_make_request(KVM_REQ_EVENT, vcpu);
348
3fd28fce
ED		 349 if (!vcpu->arch.exception.pending) {
350 queue:
351 vcpu->arch.exception.pending = true;
352 vcpu->arch.exception.has_error_code = has_error;
353 vcpu->arch.exception.nr = nr;
354 vcpu->arch.exception.error_code = error_code;
3f0fd292 355 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 356 return;
357 }
358
359 /* to check exception */
360 prev_nr = vcpu->arch.exception.nr;
361 if (prev_nr == DF_VECTOR) {
362 /* triple fault -> shutdown */
a8eeb04a 363 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 364 return;
365 }
366 class1 = exception_class(prev_nr);
367 class2 = exception_class(nr);
368 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
369 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
370 /* generate double fault per SDM Table 5-5 */
371 vcpu->arch.exception.pending = true;
372 vcpu->arch.exception.has_error_code = true;
373 vcpu->arch.exception.nr = DF_VECTOR;
374 vcpu->arch.exception.error_code = 0;
375 } else
376 /* replace previous exception with a new one in a hope
377 that instruction re-execution will regenerate lost
378 exception */
379 goto queue;
380}
381
298101da
AK		 382void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
383{
ce7ddec4 384 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 385}
386EXPORT_SYMBOL_GPL(kvm_queue_exception);
387
ce7ddec4
JR		 388void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
389{
390 kvm_multiple_exception(vcpu, nr, false, 0, true);
391}
392EXPORT_SYMBOL_GPL(kvm_requeue_exception);
393
db8fcefa 394void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 395{
db8fcefa
AP		 396 if (err)
397 kvm_inject_gp(vcpu, 0);
398 else
399 kvm_x86_ops->skip_emulated_instruction(vcpu);
400}
401EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 402
6389ee94 403void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 404{
405 ++vcpu->stat.pf_guest;
6389ee94
AK		 406 vcpu->arch.cr2 = fault->address;
407 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 408}
27d6c865 409EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 410
ef54bcfe 411static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 412{
6389ee94
AK		 413 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
414 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 415 else
6389ee94 416 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 417
418 return fault->nested_page_fault;
d4f8cf66
JR		 419}
420
3419ffc8
SY		 421void kvm_inject_nmi(struct kvm_vcpu *vcpu)
422{
7460fb4a
AK		 423 atomic_inc(&vcpu->arch.nmi_queued);
424 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 425}
426EXPORT_SYMBOL_GPL(kvm_inject_nmi);
427
298101da
AK		 428void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
429{
ce7ddec4 430 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 431}
432EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
433
ce7ddec4
JR		 434void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
435{
436 kvm_multiple_exception(vcpu, nr, true, error_code, true);
437}
438EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
439
0a79b009
AK		 440/*
441 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
442 * a #GP and return false.
443 */
444bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 445{
0a79b009
AK		 446 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
447 return true;
448 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
449 return false;
298101da 450}
0a79b009 451EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 452
ec92fe44
JR		 453/*
454 * This function will be used to read from the physical memory of the currently
455 * running guest. The difference to kvm_read_guest_page is that this function
456 * can read from guest physical or from the guest's guest physical memory.
457 */
458int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
459 gfn_t ngfn, void *data, int offset, int len,
460 u32 access)
461{
54987b7a 462 struct x86_exception exception;
ec92fe44
JR		 463 gfn_t real_gfn;
464 gpa_t ngpa;
465
466 ngpa = gfn_to_gpa(ngfn);
54987b7a 467 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 468 if (real_gfn == UNMAPPED_GVA)
469 return -EFAULT;
470
471 real_gfn = gpa_to_gfn(real_gfn);
472
473 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
474}
475EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
476
3d06b8bf
JR		 477int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
478 void *data, int offset, int len, u32 access)
479{
480 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
481 data, offset, len, access);
482}
483
a03490ed
CO		 484/*
485 * Load the pae pdptrs. Return true is they are all valid.
486 */
ff03a073 487int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 488{
489 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
490 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
491 int i;
492 int ret;
ff03a073 493 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 494
ff03a073
JR		 495 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
496 offset * sizeof(u64), sizeof(pdpte),
497 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 498 if (ret < 0) {
499 ret = 0;
500 goto out;
501 }
502 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 503 if (is_present_gpte(pdpte[i]) &&
20c466b5 504 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 505 ret = 0;
506 goto out;
507 }
508 }
509 ret = 1;
510
ff03a073 511 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 512 __set_bit(VCPU_EXREG_PDPTR,
513 (unsigned long *)&vcpu->arch.regs_avail);
514 __set_bit(VCPU_EXREG_PDPTR,
515 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 516out:
a03490ed
CO		 517
518 return ret;
519}
cc4b6871 520EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 521
d835dfec
AK		 522static bool pdptrs_changed(struct kvm_vcpu *vcpu)
523{
ff03a073 524 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 525 bool changed = true;
3d06b8bf
JR		 526 int offset;
527 gfn_t gfn;
d835dfec
AK		 528 int r;
529
530 if (is_long_mode(vcpu) || !is_pae(vcpu))
531 return false;
532
6de4f3ad
AK		 533 if (!test_bit(VCPU_EXREG_PDPTR,
534 (unsigned long *)&vcpu->arch.regs_avail))
535 return true;
536
9f8fe504
AK		 537 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
538 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 539 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
540 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 541 if (r < 0)
542 goto out;
ff03a073 543 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 544out:
d835dfec
AK		 545
546 return changed;
547}
548
49a9b07e 549int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 550{
aad82703
SY		 551 unsigned long old_cr0 = kvm_read_cr0(vcpu);
552 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
553 X86_CR0_CD | X86_CR0_NW;
554
f9a48e6a
AK		 555 cr0 |= X86_CR0_ET;
556
ab344828 557#ifdef CONFIG_X86_64
0f12244f
GN		 558 if (cr0 & 0xffffffff00000000UL)
559 return 1;
ab344828
GN		 560#endif
561
562 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 563
0f12244f
GN		 564 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
565 return 1;
a03490ed 566
0f12244f
GN		 567 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
568 return 1;
a03490ed
CO		 569
570 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
571#ifdef CONFIG_X86_64
f6801dff 572 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 573 int cs_db, cs_l;
574
0f12244f
GN		 575 if (!is_pae(vcpu))
576 return 1;
a03490ed 577 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 578 if (cs_l)
579 return 1;
a03490ed
CO		 580 } else
581#endif
ff03a073 582 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 583 kvm_read_cr3(vcpu)))
0f12244f 584 return 1;
a03490ed
CO		 585 }
586
ad756a16
MJ		 587 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
588 return 1;
589
a03490ed 590 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 591
d170c419 592 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 593 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 594 kvm_async_pf_hash_reset(vcpu);
595 }
e5f3f027 596
aad82703
SY		 597 if ((cr0 ^ old_cr0) & update_bits)
598 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 599 return 0;
600}
2d3ad1f4 601EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 602
2d3ad1f4 603void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 604{
49a9b07e 605 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 606}
2d3ad1f4 607EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 608
42bdf991
MT		 609static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
610{
611 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
612 !vcpu->guest_xcr0_loaded) {
613 /* kvm_set_xcr() also depends on this */
614 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
615 vcpu->guest_xcr0_loaded = 1;
616 }
617}
618
619static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
620{
621 if (vcpu->guest_xcr0_loaded) {
622 if (vcpu->arch.xcr0 != host_xcr0)
623 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
624 vcpu->guest_xcr0_loaded = 0;
625 }
626}
627
2acf923e
DC		 628int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
629{
56c103ec
LJ		 630 u64 xcr0 = xcr;
631 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 632 u64 valid_bits;
2acf923e
DC		 633
634 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
635 if (index != XCR_XFEATURE_ENABLED_MASK)
636 return 1;
2acf923e
DC		 637 if (!(xcr0 & XSTATE_FP))
638 return 1;
639 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
640 return 1;
46c34cb0
PB		 641
642 /*
643 * Do not allow the guest to set bits that we do not support
644 * saving. However, xcr0 bit 0 is always set, even if the
645 * emulated CPU does not support XSAVE (see fx_init).
646 */
647 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
648 if (xcr0 & ~valid_bits)
2acf923e 649 return 1;
46c34cb0 650
390bd528
LJ		 651 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
652 return 1;
653
42bdf991 654 kvm_put_guest_xcr0(vcpu);
2acf923e 655 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 656
657 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
658 kvm_update_cpuid(vcpu);
2acf923e
DC		 659 return 0;
660}
661
662int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
663{
764bcbc5
Z		 664 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
665 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 666 kvm_inject_gp(vcpu, 0);
667 return 1;
668 }
669 return 0;
670}
671EXPORT_SYMBOL_GPL(kvm_set_xcr);
672
a83b29c6 673int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 674{
fc78f519 675 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 676 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
677 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 678 if (cr4 & CR4_RESERVED_BITS)
679 return 1;
a03490ed 680
2acf923e
DC		 681 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
682 return 1;
683
c68b734f
YW		 684 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
685 return 1;
686
97ec8c06
FW		 687 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
688 return 1;
689
afcbf13f 690 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 691 return 1;
692
a03490ed 693 if (is_long_mode(vcpu)) {
0f12244f
GN		 694 if (!(cr4 & X86_CR4_PAE))
695 return 1;
a2edf57f
AK		 696 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
697 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 698 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
699 kvm_read_cr3(vcpu)))
0f12244f
GN		 700 return 1;
701
ad756a16
MJ		 702 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
703 if (!guest_cpuid_has_pcid(vcpu))
704 return 1;
705
706 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
707 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
708 return 1;
709 }
710
5e1746d6 711 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 712 return 1;
a03490ed 713
ad756a16
MJ		 714 if (((cr4 ^ old_cr4) & pdptr_bits) ||
715 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 716 kvm_mmu_reset_context(vcpu);
0f12244f 717
97ec8c06
FW		 718 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
719 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
720
2acf923e 721 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 722 kvm_update_cpuid(vcpu);
2acf923e 723
0f12244f
GN		 724 return 0;
725}
2d3ad1f4 726EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 727
2390218b 728int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 729{
9f8fe504 730 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 731 kvm_mmu_sync_roots(vcpu);
77c3913b 732 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 733 return 0;
d835dfec
AK		 734 }
735
a03490ed 736 if (is_long_mode(vcpu)) {
d9f89b88
JK		 737 if (cr3 & CR3_L_MODE_RESERVED_BITS)
738 return 1;
739 } else if (is_pae(vcpu) && is_paging(vcpu) &&
740 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 741 return 1;
a03490ed 742
0f12244f 743 vcpu->arch.cr3 = cr3;
aff48baa 744 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 745 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 746 return 0;
747}
2d3ad1f4 748EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 749
eea1cff9 750int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 751{
0f12244f
GN		 752 if (cr8 & CR8_RESERVED_BITS)
753 return 1;
a03490ed
CO		 754 if (irqchip_in_kernel(vcpu->kvm))
755 kvm_lapic_set_tpr(vcpu, cr8);
756 else
ad312c7c 757 vcpu->arch.cr8 = cr8;
0f12244f
GN		 758 return 0;
759}
2d3ad1f4 760EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 761
2d3ad1f4 762unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 763{
764 if (irqchip_in_kernel(vcpu->kvm))
765 return kvm_lapic_get_cr8(vcpu);
766 else
ad312c7c 767 return vcpu->arch.cr8;
a03490ed 768}
2d3ad1f4 769EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 770
73aaf249
JK		 771static void kvm_update_dr6(struct kvm_vcpu *vcpu)
772{
773 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
774 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
775}
776
c8639010
JK		 777static void kvm_update_dr7(struct kvm_vcpu *vcpu)
778{
779 unsigned long dr7;
780
781 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
782 dr7 = vcpu->arch.guest_debug_dr7;
783 else
784 dr7 = vcpu->arch.dr7;
785 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 786 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
787 if (dr7 & DR7_BP_EN_MASK)
788 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 789}
790
6f43ed01
NA		 791static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
792{
793 u64 fixed = DR6_FIXED_1;
794
795 if (!guest_cpuid_has_rtm(vcpu))
796 fixed |= DR6_RTM;
797 return fixed;
798}
799
338dbc97 800static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 801{
802 switch (dr) {
803 case 0 ... 3:
804 vcpu->arch.db[dr] = val;
805 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
806 vcpu->arch.eff_db[dr] = val;
807 break;
808 case 4:
338dbc97
GN		 809 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
810 return 1; /* #UD */
020df079
GN		 811 /* fall through */
812 case 6:
338dbc97
GN		 813 if (val & 0xffffffff00000000ULL)
814 return -1; /* #GP */
6f43ed01 815 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 816 kvm_update_dr6(vcpu);
020df079
GN		 817 break;
818 case 5:
338dbc97
GN		 819 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
820 return 1; /* #UD */
020df079
GN		 821 /* fall through */
822 default: /* 7 */
338dbc97
GN		 823 if (val & 0xffffffff00000000ULL)
824 return -1; /* #GP */
020df079 825 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 826 kvm_update_dr7(vcpu);
020df079
GN		 827 break;
828 }
829
830 return 0;
831}
338dbc97
GN		 832
833int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
834{
835 int res;
836
837 res = __kvm_set_dr(vcpu, dr, val);
838 if (res > 0)
839 kvm_queue_exception(vcpu, UD_VECTOR);
840 else if (res < 0)
841 kvm_inject_gp(vcpu, 0);
842
843 return res;
844}
020df079
GN		 845EXPORT_SYMBOL_GPL(kvm_set_dr);
846
338dbc97 847static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 848{
849 switch (dr) {
850 case 0 ... 3:
851 *val = vcpu->arch.db[dr];
852 break;
853 case 4:
338dbc97 854 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 855 return 1;
020df079
GN		 856 /* fall through */
857 case 6:
73aaf249
JK		 858 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
859 *val = vcpu->arch.dr6;
860 else
861 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 862 break;
863 case 5:
338dbc97 864 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 865 return 1;
020df079
GN		 866 /* fall through */
867 default: /* 7 */
868 *val = vcpu->arch.dr7;
869 break;
870 }
871
872 return 0;
873}
338dbc97
GN		 874
875int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
876{
877 if (_kvm_get_dr(vcpu, dr, val)) {
878 kvm_queue_exception(vcpu, UD_VECTOR);
879 return 1;
880 }
881 return 0;
882}
020df079
GN		 883EXPORT_SYMBOL_GPL(kvm_get_dr);
884
022cd0e8
AK		 885bool kvm_rdpmc(struct kvm_vcpu *vcpu)
886{
887 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
888 u64 data;
889 int err;
890
891 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
892 if (err)
893 return err;
894 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
895 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
896 return err;
897}
898EXPORT_SYMBOL_GPL(kvm_rdpmc);
899
043405e1
CO		 900/*
901 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
902 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
903 *
904 * This list is modified at module load time to reflect the
e3267cbb
GC		 905 * capabilities of the host cpu. This capabilities test skips MSRs that are
906 * kvm-specific. Those are put in the beginning of the list.
043405e1 907 */
e3267cbb 908
e984097b 909#define KVM_SAVE_MSRS_BEGIN 12
043405e1 910static u32 msrs_to_save[] = {
e3267cbb 911 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 912 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 913 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 914 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 915 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 916 MSR_KVM_PV_EOI_EN,
043405e1 917 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 918 MSR_STAR,
043405e1
CO		 919#ifdef CONFIG_X86_64
920 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
921#endif
b3897a49 922 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 923 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 924};
925
926static unsigned num_msrs_to_save;
927
f1d24831 928static const u32 emulated_msrs[] = {
ba904635 929 MSR_IA32_TSC_ADJUST,
a3e06bbe 930 MSR_IA32_TSCDEADLINE,
043405e1 931 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 932 MSR_IA32_MCG_STATUS,
933 MSR_IA32_MCG_CTL,
043405e1
CO		 934};
935
384bb783 936bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 937{
b69e8cae 938 if (efer & efer_reserved_bits)
384bb783 939 return false;
15c4a640 940
1b2fd70c
AG		 941 if (efer & EFER_FFXSR) {
942 struct kvm_cpuid_entry2 *feat;
943
944 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 945 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 946 return false;
1b2fd70c
AG		 947 }
948
d8017474
AG		 949 if (efer & EFER_SVME) {
950 struct kvm_cpuid_entry2 *feat;
951
952 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 953 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 954 return false;
d8017474
AG		 955 }
956
384bb783
JK		 957 return true;
958}
959EXPORT_SYMBOL_GPL(kvm_valid_efer);
960
961static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
962{
963 u64 old_efer = vcpu->arch.efer;
964
965 if (!kvm_valid_efer(vcpu, efer))
966 return 1;
967
968 if (is_paging(vcpu)
969 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
970 return 1;
971
15c4a640 972 efer &= ~EFER_LMA;
f6801dff 973 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 974
a3d204e2
SY		 975 kvm_x86_ops->set_efer(vcpu, efer);
976
aad82703
SY		 977 /* Update reserved bits */
978 if ((efer ^ old_efer) & EFER_NX)
979 kvm_mmu_reset_context(vcpu);
980
b69e8cae 981 return 0;
15c4a640
CO		 982}
983
f2b4b7dd
JR		 984void kvm_enable_efer_bits(u64 mask)
985{
986 efer_reserved_bits &= ~mask;
987}
988EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
989
15c4a640
CO		 990/*
991 * Writes msr value into into the appropriate "register".
992 * Returns 0 on success, non-0 otherwise.
993 * Assumes vcpu_load() was already called.
994 */
8fe8ab46 995int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 996{
854e8bb1
NA		 997 switch (msr->index) {
998 case MSR_FS_BASE:
999 case MSR_GS_BASE:
1000 case MSR_KERNEL_GS_BASE:
1001 case MSR_CSTAR:
1002 case MSR_LSTAR:
1003 if (is_noncanonical_address(msr->data))
1004 return 1;
1005 break;
1006 case MSR_IA32_SYSENTER_EIP:
1007 case MSR_IA32_SYSENTER_ESP:
1008 /*
1009 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1010 * non-canonical address is written on Intel but not on
1011 * AMD (which ignores the top 32-bits, because it does
1012 * not implement 64-bit SYSENTER).
1013 *
1014 * 64-bit code should hence be able to write a non-canonical
1015 * value on AMD. Making the address canonical ensures that
1016 * vmentry does not fail on Intel after writing a non-canonical
1017 * value, and that something deterministic happens if the guest
1018 * invokes 64-bit SYSENTER.
1019 */
1020 msr->data = get_canonical(msr->data);
1021 }
8fe8ab46 1022 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1023}
854e8bb1 1024EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1025
313a3dc7
CO		 1026/*
1027 * Adapt set_msr() to msr_io()'s calling convention
1028 */
1029static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1030{
8fe8ab46
WA		 1031 struct msr_data msr;
1032
1033 msr.data = *data;
1034 msr.index = index;
1035 msr.host_initiated = true;
1036 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1037}
1038
16e8d74d
MT		 1039#ifdef CONFIG_X86_64
1040struct pvclock_gtod_data {
1041 seqcount_t seq;
1042
1043 struct { /* extract of a clocksource struct */
1044 int vclock_mode;
1045 cycle_t cycle_last;
1046 cycle_t mask;
1047 u32 mult;
1048 u32 shift;
1049 } clock;
1050
cbcf2dd3
TG		 1051 u64 boot_ns;
1052 u64 nsec_base;
16e8d74d
MT		 1053};
1054
1055static struct pvclock_gtod_data pvclock_gtod_data;
1056
1057static void update_pvclock_gtod(struct timekeeper *tk)
1058{
1059 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1060 u64 boot_ns;
1061
d28ede83 1062 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
16e8d74d
MT		 1063
1064 write_seqcount_begin(&vdata->seq);
1065
1066 /* copy pvclock gtod data */
d28ede83
TG		 1067 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1068 vdata->clock.cycle_last = tk->tkr.cycle_last;
1069 vdata->clock.mask = tk->tkr.mask;
1070 vdata->clock.mult = tk->tkr.mult;
1071 vdata->clock.shift = tk->tkr.shift;
16e8d74d 1072
cbcf2dd3 1073 vdata->boot_ns = boot_ns;
d28ede83 1074 vdata->nsec_base = tk->tkr.xtime_nsec;
16e8d74d
MT		 1075
1076 write_seqcount_end(&vdata->seq);
1077}
1078#endif
1079
1080
18068523
GOC		 1081static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1082{
9ed3c444
AK		 1083 int version;
1084 int r;
50d0a0f9 1085 struct pvclock_wall_clock wc;
923de3cf 1086 struct timespec boot;
18068523
GOC		 1087
1088 if (!wall_clock)
1089 return;
1090
9ed3c444
AK		 1091 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1092 if (r)
1093 return;
1094
1095 if (version & 1)
1096 ++version; /* first time write, random junk */
1097
1098 ++version;
18068523 1099
18068523
GOC		 1100 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1101
50d0a0f9
GH		 1102 /*
1103 * The guest calculates current wall clock time by adding
34c238a1 1104 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1105 * wall clock specified here. guest system time equals host
1106 * system time for us, thus we must fill in host boot time here.
1107 */
923de3cf 1108 getboottime(&boot);
50d0a0f9 1109
4b648665
BR		 1110 if (kvm->arch.kvmclock_offset) {
1111 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1112 boot = timespec_sub(boot, ts);
1113 }
50d0a0f9
GH		 1114 wc.sec = boot.tv_sec;
1115 wc.nsec = boot.tv_nsec;
1116 wc.version = version;
18068523
GOC		 1117
1118 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1119
1120 version++;
1121 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1122}
1123
50d0a0f9
GH		 1124static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1125{
1126 uint32_t quotient, remainder;
1127
1128 /* Don't try to replace with do_div(), this one calculates
1129 * "(dividend << 32) / divisor" */
1130 __asm__ ( "divl %4"
1131 : "=a" (quotient), "=d" (remainder)
1132 : "0" (0), "1" (dividend), "r" (divisor) );
1133 return quotient;
1134}
1135
5f4e3f88
ZA		 1136static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1137 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1138{
5f4e3f88 1139 uint64_t scaled64;
50d0a0f9
GH		 1140 int32_t shift = 0;
1141 uint64_t tps64;
1142 uint32_t tps32;
1143
5f4e3f88
ZA		 1144 tps64 = base_khz * 1000LL;
1145 scaled64 = scaled_khz * 1000LL;
50933623 1146 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1147 tps64 >>= 1;
1148 shift--;
1149 }
1150
1151 tps32 = (uint32_t)tps64;
50933623
JK		 1152 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1153 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1154 scaled64 >>= 1;
1155 else
1156 tps32 <<= 1;
50d0a0f9
GH		 1157 shift++;
1158 }
1159
5f4e3f88
ZA		 1160 *pshift = shift;
1161 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1162
5f4e3f88
ZA		 1163 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1164 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1165}
1166
759379dd
ZA		 1167static inline u64 get_kernel_ns(void)
1168{
bb0b5812 1169 return ktime_get_boot_ns();
50d0a0f9
GH		 1170}
1171
d828199e 1172#ifdef CONFIG_X86_64
16e8d74d 1173static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1174#endif
16e8d74d 1175
c8076604 1176static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1177unsigned long max_tsc_khz;
c8076604 1178
cc578287 1179static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1180{
cc578287
ZA		 1181 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1182 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1183}
1184
cc578287 1185static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1186{
cc578287
ZA		 1187 u64 v = (u64)khz * (1000000 + ppm);
1188 do_div(v, 1000000);
1189 return v;
1e993611
JR		 1190}
1191
cc578287 1192static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1193{
cc578287
ZA		 1194 u32 thresh_lo, thresh_hi;
1195 int use_scaling = 0;
217fc9cf 1196
03ba32ca
MT		 1197 /* tsc_khz can be zero if TSC calibration fails */
1198 if (this_tsc_khz == 0)
1199 return;
1200
c285545f
ZA		 1201 /* Compute a scale to convert nanoseconds in TSC cycles */
1202 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1203 &vcpu->arch.virtual_tsc_shift,
1204 &vcpu->arch.virtual_tsc_mult);
1205 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1206
1207 /*
1208 * Compute the variation in TSC rate which is acceptable
1209 * within the range of tolerance and decide if the
1210 * rate being applied is within that bounds of the hardware
1211 * rate. If so, no scaling or compensation need be done.
1212 */
1213 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1214 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1215 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1216 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1217 use_scaling = 1;
1218 }
1219 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1220}
1221
1222static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1223{
e26101b1 1224 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1225 vcpu->arch.virtual_tsc_mult,
1226 vcpu->arch.virtual_tsc_shift);
e26101b1 1227 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1228 return tsc;
1229}
1230
b48aa97e
MT		 1231void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1232{
1233#ifdef CONFIG_X86_64
1234 bool vcpus_matched;
1235 bool do_request = false;
1236 struct kvm_arch *ka = &vcpu->kvm->arch;
1237 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1238
1239 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1240 atomic_read(&vcpu->kvm->online_vcpus));
1241
1242 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1243 if (!ka->use_master_clock)
1244 do_request = 1;
1245
1246 if (!vcpus_matched && ka->use_master_clock)
1247 do_request = 1;
1248
1249 if (do_request)
1250 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1251
1252 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1253 atomic_read(&vcpu->kvm->online_vcpus),
1254 ka->use_master_clock, gtod->clock.vclock_mode);
1255#endif
1256}
1257
ba904635
WA		 1258static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1259{
1260 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1261 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1262}
1263
8fe8ab46 1264void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1265{
1266 struct kvm *kvm = vcpu->kvm;
f38e098f 1267 u64 offset, ns, elapsed;
99e3e30a 1268 unsigned long flags;
02626b6a 1269 s64 usdiff;
b48aa97e 1270 bool matched;
0d3da0d2 1271 bool already_matched;
8fe8ab46 1272 u64 data = msr->data;
99e3e30a 1273
038f8c11 1274 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1275 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1276 ns = get_kernel_ns();
f38e098f 1277 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1278
03ba32ca 1279 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1280 int faulted = 0;
1281
03ba32ca
MT		 1282 /* n.b - signed multiplication and division required */
1283 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1284#ifdef CONFIG_X86_64
03ba32ca 1285 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1286#else
03ba32ca 1287 /* do_div() only does unsigned */
8915aa27
MT		 1288 asm("1: idivl %[divisor]\n"
1289 "2: xor %%edx, %%edx\n"
1290 " movl $0, %[faulted]\n"
1291 "3:\n"
1292 ".section .fixup,\"ax\"\n"
1293 "4: movl $1, %[faulted]\n"
1294 " jmp 3b\n"
1295 ".previous\n"
1296
1297 _ASM_EXTABLE(1b, 4b)
1298
1299 : "=A"(usdiff), [faulted] "=r" (faulted)
1300 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1301
5d3cb0f6 1302#endif
03ba32ca
MT		 1303 do_div(elapsed, 1000);
1304 usdiff -= elapsed;
1305 if (usdiff < 0)
1306 usdiff = -usdiff;
8915aa27
MT		 1307
1308 /* idivl overflow => difference is larger than USEC_PER_SEC */
1309 if (faulted)
1310 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1311 } else
1312 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1313
1314 /*
5d3cb0f6
ZA		 1315 * Special case: TSC write with a small delta (1 second) of virtual
1316 * cycle time against real time is interpreted as an attempt to
1317 * synchronize the CPU.
1318 *
1319 * For a reliable TSC, we can match TSC offsets, and for an unstable
1320 * TSC, we add elapsed time in this computation. We could let the
1321 * compensation code attempt to catch up if we fall behind, but
1322 * it's better to try to match offsets from the beginning.
1323 */
02626b6a 1324 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1325 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1326 if (!check_tsc_unstable()) {
e26101b1 1327 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1328 pr_debug("kvm: matched tsc offset for %llu\n", data);
1329 } else {
857e4099 1330 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1331 data += delta;
1332 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1333 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1334 }
b48aa97e 1335 matched = true;
0d3da0d2 1336 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1337 } else {
1338 /*
1339 * We split periods of matched TSC writes into generations.
1340 * For each generation, we track the original measured
1341 * nanosecond time, offset, and write, so if TSCs are in
1342 * sync, we can match exact offset, and if not, we can match
4a969980 1343 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1344 *
1345 * These values are tracked in kvm->arch.cur_xxx variables.
1346 */
1347 kvm->arch.cur_tsc_generation++;
1348 kvm->arch.cur_tsc_nsec = ns;
1349 kvm->arch.cur_tsc_write = data;
1350 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1351 matched = false;
0d3da0d2 1352 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1353 kvm->arch.cur_tsc_generation, data);
f38e098f 1354 }
e26101b1
ZA		 1355
1356 /*
1357 * We also track th most recent recorded KHZ, write and time to
1358 * allow the matching interval to be extended at each write.
1359 */
f38e098f
ZA		 1360 kvm->arch.last_tsc_nsec = ns;
1361 kvm->arch.last_tsc_write = data;
5d3cb0f6 1362 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1363
b183aa58 1364 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1365
1366 /* Keep track of which generation this VCPU has synchronized to */
1367 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1368 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1369 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1370
ba904635
WA		 1371 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1372 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1373 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1374 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1375
1376 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1377 if (!matched) {
b48aa97e 1378 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1379 } else if (!already_matched) {
1380 kvm->arch.nr_vcpus_matched_tsc++;
1381 }
b48aa97e
MT		 1382
1383 kvm_track_tsc_matching(vcpu);
1384 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1385}
e26101b1 1386
99e3e30a
ZA		 1387EXPORT_SYMBOL_GPL(kvm_write_tsc);
1388
d828199e
MT		 1389#ifdef CONFIG_X86_64
1390
1391static cycle_t read_tsc(void)
1392{
1393 cycle_t ret;
1394 u64 last;
1395
1396 /*
1397 * Empirically, a fence (of type that depends on the CPU)
1398 * before rdtsc is enough to ensure that rdtsc is ordered
1399 * with respect to loads. The various CPU manuals are unclear
1400 * as to whether rdtsc can be reordered with later loads,
1401 * but no one has ever seen it happen.
1402 */
1403 rdtsc_barrier();
1404 ret = (cycle_t)vget_cycles();
1405
1406 last = pvclock_gtod_data.clock.cycle_last;
1407
1408 if (likely(ret >= last))
1409 return ret;
1410
1411 /*
1412 * GCC likes to generate cmov here, but this branch is extremely
1413 * predictable (it's just a funciton of time and the likely is
1414 * very likely) and there's a data dependence, so force GCC
1415 * to generate a branch instead. I don't barrier() because
1416 * we don't actually need a barrier, and if this function
1417 * ever gets inlined it will generate worse code.
1418 */
1419 asm volatile ("");
1420 return last;
1421}
1422
1423static inline u64 vgettsc(cycle_t *cycle_now)
1424{
1425 long v;
1426 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1427
1428 *cycle_now = read_tsc();
1429
1430 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1431 return v * gtod->clock.mult;
1432}
1433
cbcf2dd3 1434static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1435{
cbcf2dd3 1436 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1437 unsigned long seq;
d828199e 1438 int mode;
cbcf2dd3 1439 u64 ns;
d828199e 1440
d828199e
MT		 1441 do {
1442 seq = read_seqcount_begin(&gtod->seq);
1443 mode = gtod->clock.vclock_mode;
cbcf2dd3 1444 ns = gtod->nsec_base;
d828199e
MT		 1445 ns += vgettsc(cycle_now);
1446 ns >>= gtod->clock.shift;
cbcf2dd3 1447 ns += gtod->boot_ns;
d828199e 1448 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1449 *t = ns;
d828199e
MT		 1450
1451 return mode;
1452}
1453
1454/* returns true if host is using tsc clocksource */
1455static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1456{
d828199e
MT		 1457 /* checked again under seqlock below */
1458 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1459 return false;
1460
cbcf2dd3 1461 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1462}
1463#endif
1464
1465/*
1466 *
b48aa97e
MT		 1467 * Assuming a stable TSC across physical CPUS, and a stable TSC
1468 * across virtual CPUs, the following condition is possible.
1469 * Each numbered line represents an event visible to both
d828199e
MT		 1470 * CPUs at the next numbered event.
1471 *
1472 * "timespecX" represents host monotonic time. "tscX" represents
1473 * RDTSC value.
1474 *
1475 * VCPU0 on CPU0 | VCPU1 on CPU1
1476 *
1477 * 1. read timespec0,tsc0
1478 * 2. | timespec1 = timespec0 + N
1479 * | tsc1 = tsc0 + M
1480 * 3. transition to guest | transition to guest
1481 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1482 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1483 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1484 *
1485 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1486 *
1487 * - ret0 < ret1
1488 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1489 * ...
1490 * - 0 < N - M => M < N
1491 *
1492 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1493 * always the case (the difference between two distinct xtime instances
1494 * might be smaller then the difference between corresponding TSC reads,
1495 * when updating guest vcpus pvclock areas).
1496 *
1497 * To avoid that problem, do not allow visibility of distinct
1498 * system_timestamp/tsc_timestamp values simultaneously: use a master
1499 * copy of host monotonic time values. Update that master copy
1500 * in lockstep.
1501 *
b48aa97e 1502 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1503 *
1504 */
1505
1506static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1507{
1508#ifdef CONFIG_X86_64
1509 struct kvm_arch *ka = &kvm->arch;
1510 int vclock_mode;
b48aa97e
MT		 1511 bool host_tsc_clocksource, vcpus_matched;
1512
1513 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1514 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1515
1516 /*
1517 * If the host uses TSC clock, then passthrough TSC as stable
1518 * to the guest.
1519 */
b48aa97e 1520 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1521 &ka->master_kernel_ns,
1522 &ka->master_cycle_now);
1523
16a96021
MT		 1524 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1525 && !backwards_tsc_observed;
b48aa97e 1526
d828199e
MT		 1527 if (ka->use_master_clock)
1528 atomic_set(&kvm_guest_has_master_clock, 1);
1529
1530 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1531 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1532 vcpus_matched);
d828199e
MT		 1533#endif
1534}
1535
2e762ff7
MT		 1536static void kvm_gen_update_masterclock(struct kvm *kvm)
1537{
1538#ifdef CONFIG_X86_64
1539 int i;
1540 struct kvm_vcpu *vcpu;
1541 struct kvm_arch *ka = &kvm->arch;
1542
1543 spin_lock(&ka->pvclock_gtod_sync_lock);
1544 kvm_make_mclock_inprogress_request(kvm);
1545 /* no guest entries from this point */
1546 pvclock_update_vm_gtod_copy(kvm);
1547
1548 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1549 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1550
1551 /* guest entries allowed */
1552 kvm_for_each_vcpu(i, vcpu, kvm)
1553 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1554
1555 spin_unlock(&ka->pvclock_gtod_sync_lock);
1556#endif
1557}
1558
34c238a1 1559static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1560{
d828199e 1561 unsigned long flags, this_tsc_khz;
18068523 1562 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1563 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1564 s64 kernel_ns;
d828199e 1565 u64 tsc_timestamp, host_tsc;
0b79459b 1566 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1567 u8 pvclock_flags;
d828199e
MT		 1568 bool use_master_clock;
1569
1570 kernel_ns = 0;
1571 host_tsc = 0;
18068523 1572
d828199e
MT		 1573 /*
1574 * If the host uses TSC clock, then passthrough TSC as stable
1575 * to the guest.
1576 */
1577 spin_lock(&ka->pvclock_gtod_sync_lock);
1578 use_master_clock = ka->use_master_clock;
1579 if (use_master_clock) {
1580 host_tsc = ka->master_cycle_now;
1581 kernel_ns = ka->master_kernel_ns;
1582 }
1583 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1584
1585 /* Keep irq disabled to prevent changes to the clock */
1586 local_irq_save(flags);
89cbc767 1587 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1588 if (unlikely(this_tsc_khz == 0)) {
1589 local_irq_restore(flags);
1590 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1591 return 1;
1592 }
d828199e
MT		 1593 if (!use_master_clock) {
1594 host_tsc = native_read_tsc();
1595 kernel_ns = get_kernel_ns();
1596 }
1597
1598 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1599
c285545f
ZA		 1600 /*
1601 * We may have to catch up the TSC to match elapsed wall clock
1602 * time for two reasons, even if kvmclock is used.
1603 * 1) CPU could have been running below the maximum TSC rate
1604 * 2) Broken TSC compensation resets the base at each VCPU
1605 * entry to avoid unknown leaps of TSC even when running
1606 * again on the same CPU. This may cause apparent elapsed
1607 * time to disappear, and the guest to stand still or run
1608 * very slowly.
1609 */
1610 if (vcpu->tsc_catchup) {
1611 u64 tsc = compute_guest_tsc(v, kernel_ns);
1612 if (tsc > tsc_timestamp) {
f1e2b260 1613 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1614 tsc_timestamp = tsc;
1615 }
50d0a0f9
GH		 1616 }
1617
18068523
GOC		 1618 local_irq_restore(flags);
1619
0b79459b 1620 if (!vcpu->pv_time_enabled)
c285545f 1621 return 0;
18068523 1622
e48672fa 1623 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1624 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1625 &vcpu->hv_clock.tsc_shift,
1626 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1627 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1628 }
1629
1630 /* With all the info we got, fill in the values */
1d5f066e 1631 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1632 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1633 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1634
18068523
GOC		 1635 /*
1636 * The interface expects us to write an even number signaling that the
1637 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1638 * state, we just increase by 2 at the end.
18068523 1639 */
50d0a0f9 1640 vcpu->hv_clock.version += 2;
18068523 1641
0b79459b
AH		 1642 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1643 &guest_hv_clock, sizeof(guest_hv_clock))))
1644 return 0;
78c0337a
MT		 1645
1646 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1647 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1648
1649 if (vcpu->pvclock_set_guest_stopped_request) {
1650 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1651 vcpu->pvclock_set_guest_stopped_request = false;
1652 }
1653
d828199e
MT		 1654 /* If the host uses TSC clocksource, then it is stable */
1655 if (use_master_clock)
1656 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1657
78c0337a
MT		 1658 vcpu->hv_clock.flags = pvclock_flags;
1659
0b79459b
AH		 1660 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1661 &vcpu->hv_clock,
1662 sizeof(vcpu->hv_clock));
8cfdc000 1663 return 0;
c8076604
GH		 1664}
1665
0061d53d
MT		 1666/*
1667 * kvmclock updates which are isolated to a given vcpu, such as
1668 * vcpu->cpu migration, should not allow system_timestamp from
1669 * the rest of the vcpus to remain static. Otherwise ntp frequency
1670 * correction applies to one vcpu's system_timestamp but not
1671 * the others.
1672 *
1673 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1674 * We need to rate-limit these requests though, as they can
1675 * considerably slow guests that have a large number of vcpus.
1676 * The time for a remote vcpu to update its kvmclock is bound
1677 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1678 */
1679
7e44e449
AJ		 1680#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1681
1682static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1683{
1684 int i;
7e44e449
AJ		 1685 struct delayed_work *dwork = to_delayed_work(work);
1686 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1687 kvmclock_update_work);
1688 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1689 struct kvm_vcpu *vcpu;
1690
1691 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1692 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1693 kvm_vcpu_kick(vcpu);
1694 }
1695}
1696
7e44e449
AJ		 1697static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1698{
1699 struct kvm *kvm = v->kvm;
1700
105b21bb 1701 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1702 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1703 KVMCLOCK_UPDATE_DELAY);
1704}
1705
332967a3
AJ		 1706#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1707
1708static void kvmclock_sync_fn(struct work_struct *work)
1709{
1710 struct delayed_work *dwork = to_delayed_work(work);
1711 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1712 kvmclock_sync_work);
1713 struct kvm *kvm = container_of(ka, struct kvm, arch);
1714
1715 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1716 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1717 KVMCLOCK_SYNC_PERIOD);
1718}
1719
9ba075a6
AK		 1720static bool msr_mtrr_valid(unsigned msr)
1721{
1722 switch (msr) {
1723 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1724 case MSR_MTRRfix64K_00000:
1725 case MSR_MTRRfix16K_80000:
1726 case MSR_MTRRfix16K_A0000:
1727 case MSR_MTRRfix4K_C0000:
1728 case MSR_MTRRfix4K_C8000:
1729 case MSR_MTRRfix4K_D0000:
1730 case MSR_MTRRfix4K_D8000:
1731 case MSR_MTRRfix4K_E0000:
1732 case MSR_MTRRfix4K_E8000:
1733 case MSR_MTRRfix4K_F0000:
1734 case MSR_MTRRfix4K_F8000:
1735 case MSR_MTRRdefType:
1736 case MSR_IA32_CR_PAT:
1737 return true;
1738 case 0x2f8:
1739 return true;
1740 }
1741 return false;
1742}
1743
d6289b93
MT		 1744static bool valid_pat_type(unsigned t)
1745{
1746 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1747}
1748
1749static bool valid_mtrr_type(unsigned t)
1750{
1751 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1752}
1753
4566654b 1754bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1755{
1756 int i;
fd275235 1757 u64 mask;
d6289b93
MT		 1758
1759 if (!msr_mtrr_valid(msr))
1760 return false;
1761
1762 if (msr == MSR_IA32_CR_PAT) {
1763 for (i = 0; i < 8; i++)
1764 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1765 return false;
1766 return true;
1767 } else if (msr == MSR_MTRRdefType) {
1768 if (data & ~0xcff)
1769 return false;
1770 return valid_mtrr_type(data & 0xff);
1771 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1772 for (i = 0; i < 8 ; i++)
1773 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1774 return false;
1775 return true;
1776 }
1777
1778 /* variable MTRRs */
adfb5d27
WL		 1779 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1780
fd275235 1781 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1782 if ((msr & 1) == 0) {
adfb5d27 1783 /* MTRR base */
d7a2a246
WL		 1784 if (!valid_mtrr_type(data & 0xff))
1785 return false;
1786 mask |= 0xf00;
1787 } else
1788 /* MTRR mask */
1789 mask |= 0x7ff;
1790 if (data & mask) {
1791 kvm_inject_gp(vcpu, 0);
1792 return false;
1793 }
1794
adfb5d27 1795 return true;
d6289b93 1796}
4566654b 1797EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1798
9ba075a6
AK		 1799static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1800{
0bed3b56
SY		 1801 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1802
4566654b 1803 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1804 return 1;
1805
0bed3b56
SY		 1806 if (msr == MSR_MTRRdefType) {
1807 vcpu->arch.mtrr_state.def_type = data;
1808 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1809 } else if (msr == MSR_MTRRfix64K_00000)
1810 p[0] = data;
1811 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1812 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1813 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1814 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1815 else if (msr == MSR_IA32_CR_PAT)
1816 vcpu->arch.pat = data;
1817 else { /* Variable MTRRs */
1818 int idx, is_mtrr_mask;
1819 u64 *pt;
1820
1821 idx = (msr - 0x200) / 2;
1822 is_mtrr_mask = msr - 0x200 - 2 * idx;
1823 if (!is_mtrr_mask)
1824 pt =
1825 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1826 else
1827 pt =
1828 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1829 *pt = data;
1830 }
1831
1832 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1833 return 0;
1834}
15c4a640 1835
890ca9ae 1836static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1837{
890ca9ae
HY		 1838 u64 mcg_cap = vcpu->arch.mcg_cap;
1839 unsigned bank_num = mcg_cap & 0xff;
1840
15c4a640 1841 switch (msr) {
15c4a640 1842 case MSR_IA32_MCG_STATUS:
890ca9ae 1843 vcpu->arch.mcg_status = data;
15c4a640 1844 break;
c7ac679c 1845 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1846 if (!(mcg_cap & MCG_CTL_P))
1847 return 1;
1848 if (data != 0 && data != ~(u64)0)
1849 return -1;
1850 vcpu->arch.mcg_ctl = data;
1851 break;
1852 default:
1853 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1854 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1855 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1856 /* only 0 or all 1s can be written to IA32_MCi_CTL
1857 * some Linux kernels though clear bit 10 in bank 4 to
1858 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1859 * this to avoid an uncatched #GP in the guest
1860 */
890ca9ae 1861 if ((offset & 0x3) == 0 &&
114be429 1862 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1863 return -1;
1864 vcpu->arch.mce_banks[offset] = data;
1865 break;
1866 }
1867 return 1;
1868 }
1869 return 0;
1870}
1871
ffde22ac
ES		 1872static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1873{
1874 struct kvm *kvm = vcpu->kvm;
1875 int lm = is_long_mode(vcpu);
1876 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1877 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1878 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1879 : kvm->arch.xen_hvm_config.blob_size_32;
1880 u32 page_num = data & ~PAGE_MASK;
1881 u64 page_addr = data & PAGE_MASK;
1882 u8 *page;
1883 int r;
1884
1885 r = -E2BIG;
1886 if (page_num >= blob_size)
1887 goto out;
1888 r = -ENOMEM;
ff5c2c03
SL		 1889 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1890 if (IS_ERR(page)) {
1891 r = PTR_ERR(page);
ffde22ac 1892 goto out;
ff5c2c03 1893 }
ffde22ac
ES		 1894 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1895 goto out_free;
1896 r = 0;
1897out_free:
1898 kfree(page);
1899out:
1900 return r;
1901}
1902
55cd8e5a
GN		 1903static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1904{
1905 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1906}
1907
1908static bool kvm_hv_msr_partition_wide(u32 msr)
1909{
1910 bool r = false;
1911 switch (msr) {
1912 case HV_X64_MSR_GUEST_OS_ID:
1913 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1914 case HV_X64_MSR_REFERENCE_TSC:
1915 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1916 r = true;
1917 break;
1918 }
1919
1920 return r;
1921}
1922
1923static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1924{
1925 struct kvm *kvm = vcpu->kvm;
1926
1927 switch (msr) {
1928 case HV_X64_MSR_GUEST_OS_ID:
1929 kvm->arch.hv_guest_os_id = data;
1930 /* setting guest os id to zero disables hypercall page */
1931 if (!kvm->arch.hv_guest_os_id)
1932 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1933 break;
1934 case HV_X64_MSR_HYPERCALL: {
1935 u64 gfn;
1936 unsigned long addr;
1937 u8 instructions[4];
1938
1939 /* if guest os id is not set hypercall should remain disabled */
1940 if (!kvm->arch.hv_guest_os_id)
1941 break;
1942 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1943 kvm->arch.hv_hypercall = data;
1944 break;
1945 }
1946 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1947 addr = gfn_to_hva(kvm, gfn);
1948 if (kvm_is_error_hva(addr))
1949 return 1;
1950 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1951 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1952 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1953 return 1;
1954 kvm->arch.hv_hypercall = data;
b94b64c9 1955 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1956 break;
1957 }
e984097b
VR		 1958 case HV_X64_MSR_REFERENCE_TSC: {
1959 u64 gfn;
1960 HV_REFERENCE_TSC_PAGE tsc_ref;
1961 memset(&tsc_ref, 0, sizeof(tsc_ref));
1962 kvm->arch.hv_tsc_page = data;
1963 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1964 break;
1965 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1966 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1967 &tsc_ref, sizeof(tsc_ref)))
1968 return 1;
1969 mark_page_dirty(kvm, gfn);
1970 break;
1971 }
55cd8e5a 1972 default:
a737f256
CD		 1973 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1974 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1975 return 1;
1976 }
1977 return 0;
1978}
1979
1980static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1981{
10388a07
GN		 1982 switch (msr) {
1983 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1984 u64 gfn;
10388a07 1985 unsigned long addr;
55cd8e5a 1986
10388a07
GN		 1987 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1988 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1989 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1990 return 1;
10388a07
GN		 1991 break;
1992 }
b3af1e88
VR		 1993 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1994 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1995 if (kvm_is_error_hva(addr))
1996 return 1;
8b0cedff 1997 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1998 return 1;
1999 vcpu->arch.hv_vapic = data;
b3af1e88 2000 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2001 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2002 return 1;
10388a07
GN		 2003 break;
2004 }
2005 case HV_X64_MSR_EOI:
2006 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2007 case HV_X64_MSR_ICR:
2008 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2009 case HV_X64_MSR_TPR:
2010 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2011 default:
a737f256
CD		 2012 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2013 "data 0x%llx\n", msr, data);
10388a07
GN		 2014 return 1;
2015 }
2016
2017 return 0;
55cd8e5a
GN		 2018}
2019
344d9588
GN		 2020static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2021{
2022 gpa_t gpa = data & ~0x3f;
2023
4a969980 2024 /* Bits 2:5 are reserved, Should be zero */
6adba527 2025 if (data & 0x3c)
344d9588
GN		 2026 return 1;
2027
2028 vcpu->arch.apf.msr_val = data;
2029
2030 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2031 kvm_clear_async_pf_completion_queue(vcpu);
2032 kvm_async_pf_hash_reset(vcpu);
2033 return 0;
2034 }
2035
8f964525
AH		 2036 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2037 sizeof(u32)))
344d9588
GN		 2038 return 1;
2039
6adba527 2040 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2041 kvm_async_pf_wakeup_all(vcpu);
2042 return 0;
2043}
2044
12f9a48f
GC		 2045static void kvmclock_reset(struct kvm_vcpu *vcpu)
2046{
0b79459b 2047 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2048}
2049
c9aaa895
GC		 2050static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2051{
2052 u64 delta;
2053
2054 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2055 return;
2056
2057 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2058 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2059 vcpu->arch.st.accum_steal = delta;
2060}
2061
2062static void record_steal_time(struct kvm_vcpu *vcpu)
2063{
2064 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2065 return;
2066
2067 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2068 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2069 return;
2070
2071 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2072 vcpu->arch.st.steal.version += 2;
2073 vcpu->arch.st.accum_steal = 0;
2074
2075 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2076 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2077}
2078
8fe8ab46 2079int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2080{
5753785f 2081 bool pr = false;
8fe8ab46
WA		 2082 u32 msr = msr_info->index;
2083 u64 data = msr_info->data;
5753785f 2084
15c4a640 2085 switch (msr) {
2e32b719
BP		 2086 case MSR_AMD64_NB_CFG:
2087 case MSR_IA32_UCODE_REV:
2088 case MSR_IA32_UCODE_WRITE:
2089 case MSR_VM_HSAVE_PA:
2090 case MSR_AMD64_PATCH_LOADER:
2091 case MSR_AMD64_BU_CFG2:
2092 break;
2093
15c4a640 2094 case MSR_EFER:
b69e8cae 2095 return set_efer(vcpu, data);
8f1589d9
AP		 2096 case MSR_K7_HWCR:
2097 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2098 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2099 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2100 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2101 if (data != 0) {
a737f256
CD		 2102 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2103 data);
8f1589d9
AP		 2104 return 1;
2105 }
15c4a640 2106 break;
f7c6d140
AP		 2107 case MSR_FAM10H_MMIO_CONF_BASE:
2108 if (data != 0) {
a737f256
CD		 2109 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2110 "0x%llx\n", data);
f7c6d140
AP		 2111 return 1;
2112 }
15c4a640 2113 break;
b5e2fec0
AG		 2114 case MSR_IA32_DEBUGCTLMSR:
2115 if (!data) {
2116 /* We support the non-activated case already */
2117 break;
2118 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2119 /* Values other than LBR and BTF are vendor-specific,
2120 thus reserved and should throw a #GP */
2121 return 1;
2122 }
a737f256
CD		 2123 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2124 __func__, data);
b5e2fec0 2125 break;
9ba075a6
AK		 2126 case 0x200 ... 0x2ff:
2127 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2128 case MSR_IA32_APICBASE:
58cb628d 2129 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2130 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2131 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2132 case MSR_IA32_TSCDEADLINE:
2133 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2134 break;
ba904635
WA		 2135 case MSR_IA32_TSC_ADJUST:
2136 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2137 if (!msr_info->host_initiated) {
2138 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2139 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2140 }
2141 vcpu->arch.ia32_tsc_adjust_msr = data;
2142 }
2143 break;
15c4a640 2144 case MSR_IA32_MISC_ENABLE:
ad312c7c 2145 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2146 break;
11c6bffa 2147 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2148 case MSR_KVM_WALL_CLOCK:
2149 vcpu->kvm->arch.wall_clock = data;
2150 kvm_write_wall_clock(vcpu->kvm, data);
2151 break;
11c6bffa 2152 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2153 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2154 u64 gpa_offset;
12f9a48f 2155 kvmclock_reset(vcpu);
18068523
GOC		 2156
2157 vcpu->arch.time = data;
0061d53d 2158 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2159
2160 /* we verify if the enable bit is set... */
2161 if (!(data & 1))
2162 break;
2163
0b79459b 2164 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2165
0b79459b 2166 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2167 &vcpu->arch.pv_time, data & ~1ULL,
2168 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2169 vcpu->arch.pv_time_enabled = false;
2170 else
2171 vcpu->arch.pv_time_enabled = true;
32cad84f 2172
18068523
GOC		 2173 break;
2174 }
344d9588
GN		 2175 case MSR_KVM_ASYNC_PF_EN:
2176 if (kvm_pv_enable_async_pf(vcpu, data))
2177 return 1;
2178 break;
c9aaa895
GC		 2179 case MSR_KVM_STEAL_TIME:
2180
2181 if (unlikely(!sched_info_on()))
2182 return 1;
2183
2184 if (data & KVM_STEAL_RESERVED_MASK)
2185 return 1;
2186
2187 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2188 data & KVM_STEAL_VALID_BITS,
2189 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2190 return 1;
2191
2192 vcpu->arch.st.msr_val = data;
2193
2194 if (!(data & KVM_MSR_ENABLED))
2195 break;
2196
2197 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2198
2199 preempt_disable();
2200 accumulate_steal_time(vcpu);
2201 preempt_enable();
2202
2203 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2204
2205 break;
ae7a2a3f
MT		 2206 case MSR_KVM_PV_EOI_EN:
2207 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2208 return 1;
2209 break;
c9aaa895 2210
890ca9ae
HY		 2211 case MSR_IA32_MCG_CTL:
2212 case MSR_IA32_MCG_STATUS:
81760dcc 2213 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2214 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2215
2216 /* Performance counters are not protected by a CPUID bit,
2217 * so we should check all of them in the generic path for the sake of
2218 * cross vendor migration.
2219 * Writing a zero into the event select MSRs disables them,
2220 * which we perfectly emulate ;-). Any other value should be at least
2221 * reported, some guests depend on them.
2222 */
71db6023
AP		 2223 case MSR_K7_EVNTSEL0:
2224 case MSR_K7_EVNTSEL1:
2225 case MSR_K7_EVNTSEL2:
2226 case MSR_K7_EVNTSEL3:
2227 if (data != 0)
a737f256
CD		 2228 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2229 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2230 break;
2231 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2232 * so we ignore writes to make it happy.
2233 */
71db6023
AP		 2234 case MSR_K7_PERFCTR0:
2235 case MSR_K7_PERFCTR1:
2236 case MSR_K7_PERFCTR2:
2237 case MSR_K7_PERFCTR3:
a737f256
CD		 2238 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2239 "0x%x data 0x%llx\n", msr, data);
71db6023 2240 break;
5753785f
GN		 2241 case MSR_P6_PERFCTR0:
2242 case MSR_P6_PERFCTR1:
2243 pr = true;
2244 case MSR_P6_EVNTSEL0:
2245 case MSR_P6_EVNTSEL1:
2246 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2247 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2248
2249 if (pr || data != 0)
a737f256
CD		 2250 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2251 "0x%x data 0x%llx\n", msr, data);
5753785f 2252 break;
84e0cefa
JS		 2253 case MSR_K7_CLK_CTL:
2254 /*
2255 * Ignore all writes to this no longer documented MSR.
2256 * Writes are only relevant for old K7 processors,
2257 * all pre-dating SVM, but a recommended workaround from
4a969980 2258 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2259 * affected processor models on the command line, hence
2260 * the need to ignore the workaround.
2261 */
2262 break;
55cd8e5a
GN		 2263 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2264 if (kvm_hv_msr_partition_wide(msr)) {
2265 int r;
2266 mutex_lock(&vcpu->kvm->lock);
2267 r = set_msr_hyperv_pw(vcpu, msr, data);
2268 mutex_unlock(&vcpu->kvm->lock);
2269 return r;
2270 } else
2271 return set_msr_hyperv(vcpu, msr, data);
2272 break;
91c9c3ed 2273 case MSR_IA32_BBL_CR_CTL3:
2274 /* Drop writes to this legacy MSR -- see rdmsr
2275 * counterpart for further detail.
2276 */
a737f256 2277 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2278 break;
2b036c6b
BO		 2279 case MSR_AMD64_OSVW_ID_LENGTH:
2280 if (!guest_cpuid_has_osvw(vcpu))
2281 return 1;
2282 vcpu->arch.osvw.length = data;
2283 break;
2284 case MSR_AMD64_OSVW_STATUS:
2285 if (!guest_cpuid_has_osvw(vcpu))
2286 return 1;
2287 vcpu->arch.osvw.status = data;
2288 break;
15c4a640 2289 default:
ffde22ac
ES		 2290 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2291 return xen_hvm_config(vcpu, data);
f5132b01 2292 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2293 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2294 if (!ignore_msrs) {
a737f256
CD		 2295 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2296 msr, data);
ed85c068
AP		 2297 return 1;
2298 } else {
a737f256
CD		 2299 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2300 msr, data);
ed85c068
AP		 2301 break;
2302 }
15c4a640
CO		 2303 }
2304 return 0;
2305}
2306EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2307
2308
2309/*
2310 * Reads an msr value (of 'msr_index') into 'pdata'.
2311 * Returns 0 on success, non-0 otherwise.
2312 * Assumes vcpu_load() was already called.
2313 */
2314int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2315{
2316 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2317}
2318
9ba075a6
AK		 2319static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2320{
0bed3b56
SY		 2321 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2322
9ba075a6
AK		 2323 if (!msr_mtrr_valid(msr))
2324 return 1;
2325
0bed3b56
SY		 2326 if (msr == MSR_MTRRdefType)
2327 *pdata = vcpu->arch.mtrr_state.def_type +
2328 (vcpu->arch.mtrr_state.enabled << 10);
2329 else if (msr == MSR_MTRRfix64K_00000)
2330 *pdata = p[0];
2331 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2332 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2333 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2334 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2335 else if (msr == MSR_IA32_CR_PAT)
2336 *pdata = vcpu->arch.pat;
2337 else { /* Variable MTRRs */
2338 int idx, is_mtrr_mask;
2339 u64 *pt;
2340
2341 idx = (msr - 0x200) / 2;
2342 is_mtrr_mask = msr - 0x200 - 2 * idx;
2343 if (!is_mtrr_mask)
2344 pt =
2345 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2346 else
2347 pt =
2348 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2349 *pdata = *pt;
2350 }
2351
9ba075a6
AK		 2352 return 0;
2353}
2354
890ca9ae 2355static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2356{
2357 u64 data;
890ca9ae
HY		 2358 u64 mcg_cap = vcpu->arch.mcg_cap;
2359 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2360
2361 switch (msr) {
15c4a640
CO		 2362 case MSR_IA32_P5_MC_ADDR:
2363 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2364 data = 0;
2365 break;
15c4a640 2366 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2367 data = vcpu->arch.mcg_cap;
2368 break;
c7ac679c 2369 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2370 if (!(mcg_cap & MCG_CTL_P))
2371 return 1;
2372 data = vcpu->arch.mcg_ctl;
2373 break;
2374 case MSR_IA32_MCG_STATUS:
2375 data = vcpu->arch.mcg_status;
2376 break;
2377 default:
2378 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2379 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2380 u32 offset = msr - MSR_IA32_MC0_CTL;
2381 data = vcpu->arch.mce_banks[offset];
2382 break;
2383 }
2384 return 1;
2385 }
2386 *pdata = data;
2387 return 0;
2388}
2389
55cd8e5a
GN		 2390static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2391{
2392 u64 data = 0;
2393 struct kvm *kvm = vcpu->kvm;
2394
2395 switch (msr) {
2396 case HV_X64_MSR_GUEST_OS_ID:
2397 data = kvm->arch.hv_guest_os_id;
2398 break;
2399 case HV_X64_MSR_HYPERCALL:
2400 data = kvm->arch.hv_hypercall;
2401 break;
e984097b
VR		 2402 case HV_X64_MSR_TIME_REF_COUNT: {
2403 data =
2404 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2405 break;
2406 }
2407 case HV_X64_MSR_REFERENCE_TSC:
2408 data = kvm->arch.hv_tsc_page;
2409 break;
55cd8e5a 2410 default:
a737f256 2411 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2412 return 1;
2413 }
2414
2415 *pdata = data;
2416 return 0;
2417}
2418
2419static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2420{
2421 u64 data = 0;
2422
2423 switch (msr) {
2424 case HV_X64_MSR_VP_INDEX: {
2425 int r;
2426 struct kvm_vcpu *v;
684851a1
TY		 2427 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2428 if (v == vcpu) {
55cd8e5a 2429 data = r;
684851a1
TY		 2430 break;
2431 }
2432 }
55cd8e5a
GN		 2433 break;
2434 }
10388a07
GN		 2435 case HV_X64_MSR_EOI:
2436 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2437 case HV_X64_MSR_ICR:
2438 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2439 case HV_X64_MSR_TPR:
2440 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2441 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2442 data = vcpu->arch.hv_vapic;
2443 break;
55cd8e5a 2444 default:
a737f256 2445 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2446 return 1;
2447 }
2448 *pdata = data;
2449 return 0;
2450}
2451
890ca9ae
HY		 2452int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2453{
2454 u64 data;
2455
2456 switch (msr) {
890ca9ae 2457 case MSR_IA32_PLATFORM_ID:
15c4a640 2458 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2459 case MSR_IA32_DEBUGCTLMSR:
2460 case MSR_IA32_LASTBRANCHFROMIP:
2461 case MSR_IA32_LASTBRANCHTOIP:
2462 case MSR_IA32_LASTINTFROMIP:
2463 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2464 case MSR_K8_SYSCFG:
2465 case MSR_K7_HWCR:
61a6bd67 2466 case MSR_VM_HSAVE_PA:
9e699624 2467 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2468 case MSR_K7_EVNTSEL1:
2469 case MSR_K7_EVNTSEL2:
2470 case MSR_K7_EVNTSEL3:
1f3ee616 2471 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2472 case MSR_K7_PERFCTR1:
2473 case MSR_K7_PERFCTR2:
2474 case MSR_K7_PERFCTR3:
1fdbd48c 2475 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2476 case MSR_AMD64_NB_CFG:
f7c6d140 2477 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2478 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2479 data = 0;
2480 break;
5753785f
GN		 2481 case MSR_P6_PERFCTR0:
2482 case MSR_P6_PERFCTR1:
2483 case MSR_P6_EVNTSEL0:
2484 case MSR_P6_EVNTSEL1:
2485 if (kvm_pmu_msr(vcpu, msr))
2486 return kvm_pmu_get_msr(vcpu, msr, pdata);
2487 data = 0;
2488 break;
742bc670
MT		 2489 case MSR_IA32_UCODE_REV:
2490 data = 0x100000000ULL;
2491 break;
9ba075a6
AK		 2492 case MSR_MTRRcap:
2493 data = 0x500 | KVM_NR_VAR_MTRR;
2494 break;
2495 case 0x200 ... 0x2ff:
2496 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2497 case 0xcd: /* fsb frequency */
2498 data = 3;
2499 break;
7b914098
JS		 2500 /*
2501 * MSR_EBC_FREQUENCY_ID
2502 * Conservative value valid for even the basic CPU models.
2503 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2504 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2505 * and 266MHz for model 3, or 4. Set Core Clock
2506 * Frequency to System Bus Frequency Ratio to 1 (bits
2507 * 31:24) even though these are only valid for CPU
2508 * models > 2, however guests may end up dividing or
2509 * multiplying by zero otherwise.
2510 */
2511 case MSR_EBC_FREQUENCY_ID:
2512 data = 1 << 24;
2513 break;
15c4a640
CO		 2514 case MSR_IA32_APICBASE:
2515 data = kvm_get_apic_base(vcpu);
2516 break;
0105d1a5
GN		 2517 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2518 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2519 break;
a3e06bbe
LJ		 2520 case MSR_IA32_TSCDEADLINE:
2521 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2522 break;
ba904635
WA		 2523 case MSR_IA32_TSC_ADJUST:
2524 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2525 break;
15c4a640 2526 case MSR_IA32_MISC_ENABLE:
ad312c7c 2527 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2528 break;
847f0ad8
AG		 2529 case MSR_IA32_PERF_STATUS:
2530 /* TSC increment by tick */
2531 data = 1000ULL;
2532 /* CPU multiplier */
2533 data |= (((uint64_t)4ULL) << 40);
2534 break;
15c4a640 2535 case MSR_EFER:
f6801dff 2536 data = vcpu->arch.efer;
15c4a640 2537 break;
18068523 2538 case MSR_KVM_WALL_CLOCK:
11c6bffa 2539 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2540 data = vcpu->kvm->arch.wall_clock;
2541 break;
2542 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2543 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2544 data = vcpu->arch.time;
2545 break;
344d9588
GN		 2546 case MSR_KVM_ASYNC_PF_EN:
2547 data = vcpu->arch.apf.msr_val;
2548 break;
c9aaa895
GC		 2549 case MSR_KVM_STEAL_TIME:
2550 data = vcpu->arch.st.msr_val;
2551 break;
1d92128f
MT		 2552 case MSR_KVM_PV_EOI_EN:
2553 data = vcpu->arch.pv_eoi.msr_val;
2554 break;
890ca9ae
HY		 2555 case MSR_IA32_P5_MC_ADDR:
2556 case MSR_IA32_P5_MC_TYPE:
2557 case MSR_IA32_MCG_CAP:
2558 case MSR_IA32_MCG_CTL:
2559 case MSR_IA32_MCG_STATUS:
81760dcc 2560 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2561 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2562 case MSR_K7_CLK_CTL:
2563 /*
2564 * Provide expected ramp-up count for K7. All other
2565 * are set to zero, indicating minimum divisors for
2566 * every field.
2567 *
2568 * This prevents guest kernels on AMD host with CPU
2569 * type 6, model 8 and higher from exploding due to
2570 * the rdmsr failing.
2571 */
2572 data = 0x20000000;
2573 break;
55cd8e5a
GN		 2574 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2575 if (kvm_hv_msr_partition_wide(msr)) {
2576 int r;
2577 mutex_lock(&vcpu->kvm->lock);
2578 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2579 mutex_unlock(&vcpu->kvm->lock);
2580 return r;
2581 } else
2582 return get_msr_hyperv(vcpu, msr, pdata);
2583 break;
91c9c3ed 2584 case MSR_IA32_BBL_CR_CTL3:
2585 /* This legacy MSR exists but isn't fully documented in current
2586 * silicon. It is however accessed by winxp in very narrow
2587 * scenarios where it sets bit #19, itself documented as
2588 * a "reserved" bit. Best effort attempt to source coherent
2589 * read data here should the balance of the register be
2590 * interpreted by the guest:
2591 *
2592 * L2 cache control register 3: 64GB range, 256KB size,
2593 * enabled, latency 0x1, configured
2594 */
2595 data = 0xbe702111;
2596 break;
2b036c6b
BO		 2597 case MSR_AMD64_OSVW_ID_LENGTH:
2598 if (!guest_cpuid_has_osvw(vcpu))
2599 return 1;
2600 data = vcpu->arch.osvw.length;
2601 break;
2602 case MSR_AMD64_OSVW_STATUS:
2603 if (!guest_cpuid_has_osvw(vcpu))
2604 return 1;
2605 data = vcpu->arch.osvw.status;
2606 break;
15c4a640 2607 default:
f5132b01
GN		 2608 if (kvm_pmu_msr(vcpu, msr))
2609 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2610 if (!ignore_msrs) {
a737f256 2611 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2612 return 1;
2613 } else {
a737f256 2614 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2615 data = 0;
2616 }
2617 break;
15c4a640
CO		 2618 }
2619 *pdata = data;
2620 return 0;
2621}
2622EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2623
313a3dc7
CO		 2624/*
2625 * Read or write a bunch of msrs. All parameters are kernel addresses.
2626 *
2627 * @return number of msrs set successfully.
2628 */
2629static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2630 struct kvm_msr_entry *entries,
2631 int (*do_msr)(struct kvm_vcpu *vcpu,
2632 unsigned index, u64 *data))
2633{
f656ce01 2634 int i, idx;
313a3dc7 2635
f656ce01 2636 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2637 for (i = 0; i < msrs->nmsrs; ++i)
2638 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2639 break;
f656ce01 2640 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2641
313a3dc7
CO		 2642 return i;
2643}
2644
2645/*
2646 * Read or write a bunch of msrs. Parameters are user addresses.
2647 *
2648 * @return number of msrs set successfully.
2649 */
2650static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2651 int (*do_msr)(struct kvm_vcpu *vcpu,
2652 unsigned index, u64 *data),
2653 int writeback)
2654{
2655 struct kvm_msrs msrs;
2656 struct kvm_msr_entry *entries;
2657 int r, n;
2658 unsigned size;
2659
2660 r = -EFAULT;
2661 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2662 goto out;
2663
2664 r = -E2BIG;
2665 if (msrs.nmsrs >= MAX_IO_MSRS)
2666 goto out;
2667
313a3dc7 2668 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2669 entries = memdup_user(user_msrs->entries, size);
2670 if (IS_ERR(entries)) {
2671 r = PTR_ERR(entries);
313a3dc7 2672 goto out;
ff5c2c03 2673 }
313a3dc7
CO		 2674
2675 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2676 if (r < 0)
2677 goto out_free;
2678
2679 r = -EFAULT;
2680 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2681 goto out_free;
2682
2683 r = n;
2684
2685out_free:
7a73c028 2686 kfree(entries);
313a3dc7
CO		 2687out:
2688 return r;
2689}
2690
784aa3d7 2691int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2692{
2693 int r;
2694
2695 switch (ext) {
2696 case KVM_CAP_IRQCHIP:
2697 case KVM_CAP_HLT:
2698 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2699 case KVM_CAP_SET_TSS_ADDR:
07716717 2700 case KVM_CAP_EXT_CPUID:
9c15bb1d 2701 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2702 case KVM_CAP_CLOCKSOURCE:
7837699f 2703 case KVM_CAP_PIT:
a28e4f5a 2704 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2705 case KVM_CAP_MP_STATE:
ed848624 2706 case KVM_CAP_SYNC_MMU:
a355c85c 2707 case KVM_CAP_USER_NMI:
52d939a0 2708 case KVM_CAP_REINJECT_CONTROL:
4925663a 2709 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2710 case KVM_CAP_IRQFD:
d34e6b17 2711 case KVM_CAP_IOEVENTFD:
f848a5a8 2712 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2713 case KVM_CAP_PIT2:
e9f42757 2714 case KVM_CAP_PIT_STATE2:
b927a3ce 2715 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2716 case KVM_CAP_XEN_HVM:
afbcf7ab 2717 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2718 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2719 case KVM_CAP_HYPERV:
10388a07 2720 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2721 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2722 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2723 case KVM_CAP_DEBUGREGS:
d2be1651 2724 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2725 case KVM_CAP_XSAVE:
344d9588 2726 case KVM_CAP_ASYNC_PF:
92a1f12d 2727 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2728 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2729 case KVM_CAP_READONLY_MEM:
5f66b620 2730 case KVM_CAP_HYPERV_TIME:
100943c5 2731 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2732#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2733 case KVM_CAP_ASSIGN_DEV_IRQ:
2734 case KVM_CAP_PCI_2_3:
2735#endif
018d00d2
ZX		 2736 r = 1;
2737 break;
542472b5
LV		 2738 case KVM_CAP_COALESCED_MMIO:
2739 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2740 break;
774ead3a
AK		 2741 case KVM_CAP_VAPIC:
2742 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2743 break;
f725230a 2744 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2745 r = KVM_SOFT_MAX_VCPUS;
2746 break;
2747 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2748 r = KVM_MAX_VCPUS;
2749 break;
a988b910 2750 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2751 r = KVM_USER_MEM_SLOTS;
a988b910 2752 break;
a68a6a72
MT		 2753 case KVM_CAP_PV_MMU: /* obsolete */
2754 r = 0;
2f333bcb 2755 break;
4cee4b72 2756#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2757 case KVM_CAP_IOMMU:
a1b60c1c 2758 r = iommu_present(&pci_bus_type);
62c476c7 2759 break;
4cee4b72 2760#endif
890ca9ae
HY		 2761 case KVM_CAP_MCE:
2762 r = KVM_MAX_MCE_BANKS;
2763 break;
2d5b5a66
SY		 2764 case KVM_CAP_XCRS:
2765 r = cpu_has_xsave;
2766 break;
92a1f12d
JR		 2767 case KVM_CAP_TSC_CONTROL:
2768 r = kvm_has_tsc_control;
2769 break;
4d25a066
JK		 2770 case KVM_CAP_TSC_DEADLINE_TIMER:
2771 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2772 break;
018d00d2
ZX		 2773 default:
2774 r = 0;
2775 break;
2776 }
2777 return r;
2778
2779}
2780
043405e1
CO		 2781long kvm_arch_dev_ioctl(struct file *filp,
2782 unsigned int ioctl, unsigned long arg)
2783{
2784 void __user *argp = (void __user *)arg;
2785 long r;
2786
2787 switch (ioctl) {
2788 case KVM_GET_MSR_INDEX_LIST: {
2789 struct kvm_msr_list __user *user_msr_list = argp;
2790 struct kvm_msr_list msr_list;
2791 unsigned n;
2792
2793 r = -EFAULT;
2794 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2795 goto out;
2796 n = msr_list.nmsrs;
2797 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2798 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2799 goto out;
2800 r = -E2BIG;
e125e7b6 2801 if (n < msr_list.nmsrs)
043405e1
CO		 2802 goto out;
2803 r = -EFAULT;
2804 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2805 num_msrs_to_save * sizeof(u32)))
2806 goto out;
e125e7b6 2807 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2808 &emulated_msrs,
2809 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2810 goto out;
2811 r = 0;
2812 break;
2813 }
9c15bb1d
BP		 2814 case KVM_GET_SUPPORTED_CPUID:
2815 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2816 struct kvm_cpuid2 __user *cpuid_arg = argp;
2817 struct kvm_cpuid2 cpuid;
2818
2819 r = -EFAULT;
2820 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2821 goto out;
9c15bb1d
BP		 2822
2823 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2824 ioctl);
674eea0f
AK		 2825 if (r)
2826 goto out;
2827
2828 r = -EFAULT;
2829 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2830 goto out;
2831 r = 0;
2832 break;
2833 }
890ca9ae
HY		 2834 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2835 u64 mce_cap;
2836
2837 mce_cap = KVM_MCE_CAP_SUPPORTED;
2838 r = -EFAULT;
2839 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2840 goto out;
2841 r = 0;
2842 break;
2843 }
043405e1
CO		 2844 default:
2845 r = -EINVAL;
2846 }
2847out:
2848 return r;
2849}
2850
f5f48ee1
SY		 2851static void wbinvd_ipi(void *garbage)
2852{
2853 wbinvd();
2854}
2855
2856static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2857{
e0f0bbc5 2858 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2859}
2860
313a3dc7
CO		 2861void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2862{
f5f48ee1
SY		 2863 /* Address WBINVD may be executed by guest */
2864 if (need_emulate_wbinvd(vcpu)) {
2865 if (kvm_x86_ops->has_wbinvd_exit())
2866 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2867 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2868 smp_call_function_single(vcpu->cpu,
2869 wbinvd_ipi, NULL, 1);
2870 }
2871
313a3dc7 2872 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2873
0dd6a6ed
ZA		 2874 /* Apply any externally detected TSC adjustments (due to suspend) */
2875 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2876 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2877 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2879 }
8f6055cb 2880
48434c20 2881 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2882 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2883 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2884 if (tsc_delta < 0)
2885 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2886 if (check_tsc_unstable()) {
b183aa58
ZA		 2887 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2888 vcpu->arch.last_guest_tsc);
2889 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2890 vcpu->arch.tsc_catchup = 1;
c285545f 2891 }
d98d07ca
MT		 2892 /*
2893 * On a host with synchronized TSC, there is no need to update
2894 * kvmclock on vcpu->cpu migration
2895 */
2896 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2897 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2898 if (vcpu->cpu != cpu)
2899 kvm_migrate_timers(vcpu);
e48672fa 2900 vcpu->cpu = cpu;
6b7d7e76 2901 }
c9aaa895
GC		 2902
2903 accumulate_steal_time(vcpu);
2904 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2905}
2906
2907void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2908{
02daab21 2909 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2910 kvm_put_guest_fpu(vcpu);
6f526ec5 2911 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2912}
2913
313a3dc7
CO		 2914static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2915 struct kvm_lapic_state *s)
2916{
5a71785d 2917 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2918 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2919
2920 return 0;
2921}
2922
2923static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2924 struct kvm_lapic_state *s)
2925{
64eb0620 2926 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2927 update_cr8_intercept(vcpu);
313a3dc7
CO		 2928
2929 return 0;
2930}
2931
f77bc6a4
ZX		 2932static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2933 struct kvm_interrupt *irq)
2934{
02cdb50f 2935 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2936 return -EINVAL;
2937 if (irqchip_in_kernel(vcpu->kvm))
2938 return -ENXIO;
f77bc6a4 2939
66fd3f7f 2940 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2941 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2942
f77bc6a4
ZX		 2943 return 0;
2944}
2945
c4abb7c9
JK		 2946static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2947{
c4abb7c9 2948 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2949
2950 return 0;
2951}
2952
b209749f
AK		 2953static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2954 struct kvm_tpr_access_ctl *tac)
2955{
2956 if (tac->flags)
2957 return -EINVAL;
2958 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2959 return 0;
2960}
2961
890ca9ae
HY		 2962static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2963 u64 mcg_cap)
2964{
2965 int r;
2966 unsigned bank_num = mcg_cap & 0xff, bank;
2967
2968 r = -EINVAL;
a9e38c3e 2969 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2970 goto out;
2971 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2972 goto out;
2973 r = 0;
2974 vcpu->arch.mcg_cap = mcg_cap;
2975 /* Init IA32_MCG_CTL to all 1s */
2976 if (mcg_cap & MCG_CTL_P)
2977 vcpu->arch.mcg_ctl = ~(u64)0;
2978 /* Init IA32_MCi_CTL to all 1s */
2979 for (bank = 0; bank < bank_num; bank++)
2980 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2981out:
2982 return r;
2983}
2984
2985static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2986 struct kvm_x86_mce *mce)
2987{
2988 u64 mcg_cap = vcpu->arch.mcg_cap;
2989 unsigned bank_num = mcg_cap & 0xff;
2990 u64 *banks = vcpu->arch.mce_banks;
2991
2992 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2993 return -EINVAL;
2994 /*
2995 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2996 * reporting is disabled
2997 */
2998 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2999 vcpu->arch.mcg_ctl != ~(u64)0)
3000 return 0;
3001 banks += 4 * mce->bank;
3002 /*
3003 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3004 * reporting is disabled for the bank
3005 */
3006 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3007 return 0;
3008 if (mce->status & MCI_STATUS_UC) {
3009 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3010 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3011 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3012 return 0;
3013 }
3014 if (banks[1] & MCI_STATUS_VAL)
3015 mce->status |= MCI_STATUS_OVER;
3016 banks[2] = mce->addr;
3017 banks[3] = mce->misc;
3018 vcpu->arch.mcg_status = mce->mcg_status;
3019 banks[1] = mce->status;
3020 kvm_queue_exception(vcpu, MC_VECTOR);
3021 } else if (!(banks[1] & MCI_STATUS_VAL)
3022 || !(banks[1] & MCI_STATUS_UC)) {
3023 if (banks[1] & MCI_STATUS_VAL)
3024 mce->status |= MCI_STATUS_OVER;
3025 banks[2] = mce->addr;
3026 banks[3] = mce->misc;
3027 banks[1] = mce->status;
3028 } else
3029 banks[1] |= MCI_STATUS_OVER;
3030 return 0;
3031}
3032
3cfc3092
JK		 3033static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3034 struct kvm_vcpu_events *events)
3035{
7460fb4a 3036 process_nmi(vcpu);
03b82a30
JK		 3037 events->exception.injected =
3038 vcpu->arch.exception.pending &&
3039 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3040 events->exception.nr = vcpu->arch.exception.nr;
3041 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3042 events->exception.pad = 0;
3cfc3092
JK		 3043 events->exception.error_code = vcpu->arch.exception.error_code;
3044
03b82a30
JK		 3045 events->interrupt.injected =
3046 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3047 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3048 events->interrupt.soft = 0;
37ccdcbe 3049 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3050
3051 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3052 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3053 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3054 events->nmi.pad = 0;
3cfc3092 3055
66450a21 3056 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3057
dab4b911 3058 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3059 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3060 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3061}
3062
3063static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3064 struct kvm_vcpu_events *events)
3065{
dab4b911 3066 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3067 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3068 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3069 return -EINVAL;
3070
7460fb4a 3071 process_nmi(vcpu);
3cfc3092
JK		 3072 vcpu->arch.exception.pending = events->exception.injected;
3073 vcpu->arch.exception.nr = events->exception.nr;
3074 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3075 vcpu->arch.exception.error_code = events->exception.error_code;
3076
3077 vcpu->arch.interrupt.pending = events->interrupt.injected;
3078 vcpu->arch.interrupt.nr = events->interrupt.nr;
3079 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3080 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3081 kvm_x86_ops->set_interrupt_shadow(vcpu,
3082 events->interrupt.shadow);
3cfc3092
JK		 3083
3084 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3085 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3086 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3087 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3088
66450a21
JK		 3089 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3090 kvm_vcpu_has_lapic(vcpu))
3091 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3092
3842d135
AK		 3093 kvm_make_request(KVM_REQ_EVENT, vcpu);
3094
3cfc3092
JK		 3095 return 0;
3096}
3097
a1efbe77
JK		 3098static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3099 struct kvm_debugregs *dbgregs)
3100{
73aaf249
JK		 3101 unsigned long val;
3102
a1efbe77 3103 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3104 _kvm_get_dr(vcpu, 6, &val);
3105 dbgregs->dr6 = val;
a1efbe77
JK		 3106 dbgregs->dr7 = vcpu->arch.dr7;
3107 dbgregs->flags = 0;
97e69aa6 3108 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3109}
3110
3111static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3112 struct kvm_debugregs *dbgregs)
3113{
3114 if (dbgregs->flags)
3115 return -EINVAL;
3116
a1efbe77
JK		 3117 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3118 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3119 kvm_update_dr6(vcpu);
a1efbe77 3120 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3121 kvm_update_dr7(vcpu);
a1efbe77 3122
a1efbe77
JK		 3123 return 0;
3124}
3125
2d5b5a66
SY		 3126static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3127 struct kvm_xsave *guest_xsave)
3128{
4344ee98 3129 if (cpu_has_xsave) {
2d5b5a66
SY		 3130 memcpy(guest_xsave->region,
3131 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3132 vcpu->arch.guest_xstate_size);
3133 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3134 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3135 } else {
2d5b5a66
SY		 3136 memcpy(guest_xsave->region,
3137 &vcpu->arch.guest_fpu.state->fxsave,
3138 sizeof(struct i387_fxsave_struct));
3139 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3140 XSTATE_FPSSE;
3141 }
3142}
3143
3144static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3145 struct kvm_xsave *guest_xsave)
3146{
3147 u64 xstate_bv =
3148 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3149
d7876f1b
PB		 3150 if (cpu_has_xsave) {
3151 /*
3152 * Here we allow setting states that are not present in
3153 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3154 * with old userspace.
3155 */
4ff41732 3156 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3157 return -EINVAL;
2d5b5a66 3158 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3159 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3160 } else {
2d5b5a66
SY		 3161 if (xstate_bv & ~XSTATE_FPSSE)
3162 return -EINVAL;
3163 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3164 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3165 }
3166 return 0;
3167}
3168
3169static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3170 struct kvm_xcrs *guest_xcrs)
3171{
3172 if (!cpu_has_xsave) {
3173 guest_xcrs->nr_xcrs = 0;
3174 return;
3175 }
3176
3177 guest_xcrs->nr_xcrs = 1;
3178 guest_xcrs->flags = 0;
3179 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3180 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3181}
3182
3183static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3184 struct kvm_xcrs *guest_xcrs)
3185{
3186 int i, r = 0;
3187
3188 if (!cpu_has_xsave)
3189 return -EINVAL;
3190
3191 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3192 return -EINVAL;
3193
3194 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3195 /* Only support XCR0 currently */
c67a04cb 3196 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3197 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3198 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3199 break;
3200 }
3201 if (r)
3202 r = -EINVAL;
3203 return r;
3204}
3205
1c0b28c2
EM		 3206/*
3207 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3208 * stopped by the hypervisor. This function will be called from the host only.
3209 * EINVAL is returned when the host attempts to set the flag for a guest that
3210 * does not support pv clocks.
3211 */
3212static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3213{
0b79459b 3214 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3215 return -EINVAL;
51d59c6b 3216 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3217 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3218 return 0;
3219}
3220
313a3dc7
CO		 3221long kvm_arch_vcpu_ioctl(struct file *filp,
3222 unsigned int ioctl, unsigned long arg)
3223{
3224 struct kvm_vcpu *vcpu = filp->private_data;
3225 void __user *argp = (void __user *)arg;
3226 int r;
d1ac91d8
AK		 3227 union {
3228 struct kvm_lapic_state *lapic;
3229 struct kvm_xsave *xsave;
3230 struct kvm_xcrs *xcrs;
3231 void *buffer;
3232 } u;
3233
3234 u.buffer = NULL;
313a3dc7
CO		 3235 switch (ioctl) {
3236 case KVM_GET_LAPIC: {
2204ae3c
MT		 3237 r = -EINVAL;
3238 if (!vcpu->arch.apic)
3239 goto out;
d1ac91d8 3240 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3241
b772ff36 3242 r = -ENOMEM;
d1ac91d8 3243 if (!u.lapic)
b772ff36 3244 goto out;
d1ac91d8 3245 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3246 if (r)
3247 goto out;
3248 r = -EFAULT;
d1ac91d8 3249 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3250 goto out;
3251 r = 0;
3252 break;
3253 }
3254 case KVM_SET_LAPIC: {
2204ae3c
MT		 3255 r = -EINVAL;
3256 if (!vcpu->arch.apic)
3257 goto out;
ff5c2c03 3258 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3259 if (IS_ERR(u.lapic))
3260 return PTR_ERR(u.lapic);
ff5c2c03 3261
d1ac91d8 3262 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3263 break;
3264 }
f77bc6a4
ZX		 3265 case KVM_INTERRUPT: {
3266 struct kvm_interrupt irq;
3267
3268 r = -EFAULT;
3269 if (copy_from_user(&irq, argp, sizeof irq))
3270 goto out;
3271 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3272 break;
3273 }
c4abb7c9
JK		 3274 case KVM_NMI: {
3275 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3276 break;
3277 }
313a3dc7
CO		 3278 case KVM_SET_CPUID: {
3279 struct kvm_cpuid __user *cpuid_arg = argp;
3280 struct kvm_cpuid cpuid;
3281
3282 r = -EFAULT;
3283 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3284 goto out;
3285 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3286 break;
3287 }
07716717
DK		 3288 case KVM_SET_CPUID2: {
3289 struct kvm_cpuid2 __user *cpuid_arg = argp;
3290 struct kvm_cpuid2 cpuid;
3291
3292 r = -EFAULT;
3293 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3294 goto out;
3295 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3296 cpuid_arg->entries);
07716717
DK		 3297 break;
3298 }
3299 case KVM_GET_CPUID2: {
3300 struct kvm_cpuid2 __user *cpuid_arg = argp;
3301 struct kvm_cpuid2 cpuid;
3302
3303 r = -EFAULT;
3304 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3305 goto out;
3306 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3307 cpuid_arg->entries);
07716717
DK		 3308 if (r)
3309 goto out;
3310 r = -EFAULT;
3311 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3312 goto out;
3313 r = 0;
3314 break;
3315 }
313a3dc7
CO		 3316 case KVM_GET_MSRS:
3317 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3318 break;
3319 case KVM_SET_MSRS:
3320 r = msr_io(vcpu, argp, do_set_msr, 0);
3321 break;
b209749f
AK		 3322 case KVM_TPR_ACCESS_REPORTING: {
3323 struct kvm_tpr_access_ctl tac;
3324
3325 r = -EFAULT;
3326 if (copy_from_user(&tac, argp, sizeof tac))
3327 goto out;
3328 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3329 if (r)
3330 goto out;
3331 r = -EFAULT;
3332 if (copy_to_user(argp, &tac, sizeof tac))
3333 goto out;
3334 r = 0;
3335 break;
3336 };
b93463aa
AK		 3337 case KVM_SET_VAPIC_ADDR: {
3338 struct kvm_vapic_addr va;
3339
3340 r = -EINVAL;
3341 if (!irqchip_in_kernel(vcpu->kvm))
3342 goto out;
3343 r = -EFAULT;
3344 if (copy_from_user(&va, argp, sizeof va))
3345 goto out;
fda4e2e8 3346 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3347 break;
3348 }
890ca9ae
HY		 3349 case KVM_X86_SETUP_MCE: {
3350 u64 mcg_cap;
3351
3352 r = -EFAULT;
3353 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3354 goto out;
3355 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3356 break;
3357 }
3358 case KVM_X86_SET_MCE: {
3359 struct kvm_x86_mce mce;
3360
3361 r = -EFAULT;
3362 if (copy_from_user(&mce, argp, sizeof mce))
3363 goto out;
3364 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3365 break;
3366 }
3cfc3092
JK		 3367 case KVM_GET_VCPU_EVENTS: {
3368 struct kvm_vcpu_events events;
3369
3370 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3371
3372 r = -EFAULT;
3373 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3374 break;
3375 r = 0;
3376 break;
3377 }
3378 case KVM_SET_VCPU_EVENTS: {
3379 struct kvm_vcpu_events events;
3380
3381 r = -EFAULT;
3382 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3383 break;
3384
3385 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3386 break;
3387 }
a1efbe77
JK		 3388 case KVM_GET_DEBUGREGS: {
3389 struct kvm_debugregs dbgregs;
3390
3391 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3392
3393 r = -EFAULT;
3394 if (copy_to_user(argp, &dbgregs,
3395 sizeof(struct kvm_debugregs)))
3396 break;
3397 r = 0;
3398 break;
3399 }
3400 case KVM_SET_DEBUGREGS: {
3401 struct kvm_debugregs dbgregs;
3402
3403 r = -EFAULT;
3404 if (copy_from_user(&dbgregs, argp,
3405 sizeof(struct kvm_debugregs)))
3406 break;
3407
3408 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3409 break;
3410 }
2d5b5a66 3411 case KVM_GET_XSAVE: {
d1ac91d8 3412 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3413 r = -ENOMEM;
d1ac91d8 3414 if (!u.xsave)
2d5b5a66
SY		 3415 break;
3416
d1ac91d8 3417 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3418
3419 r = -EFAULT;
d1ac91d8 3420 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3421 break;
3422 r = 0;
3423 break;
3424 }
3425 case KVM_SET_XSAVE: {
ff5c2c03 3426 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3427 if (IS_ERR(u.xsave))
3428 return PTR_ERR(u.xsave);
2d5b5a66 3429
d1ac91d8 3430 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3431 break;
3432 }
3433 case KVM_GET_XCRS: {
d1ac91d8 3434 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3435 r = -ENOMEM;
d1ac91d8 3436 if (!u.xcrs)
2d5b5a66
SY		 3437 break;
3438
d1ac91d8 3439 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3440
3441 r = -EFAULT;
d1ac91d8 3442 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3443 sizeof(struct kvm_xcrs)))
3444 break;
3445 r = 0;
3446 break;
3447 }
3448 case KVM_SET_XCRS: {
ff5c2c03 3449 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3450 if (IS_ERR(u.xcrs))
3451 return PTR_ERR(u.xcrs);
2d5b5a66 3452
d1ac91d8 3453 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3454 break;
3455 }
92a1f12d
JR		 3456 case KVM_SET_TSC_KHZ: {
3457 u32 user_tsc_khz;
3458
3459 r = -EINVAL;
92a1f12d
JR		 3460 user_tsc_khz = (u32)arg;
3461
3462 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3463 goto out;
3464
cc578287
ZA		 3465 if (user_tsc_khz == 0)
3466 user_tsc_khz = tsc_khz;
3467
3468 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3469
3470 r = 0;
3471 goto out;
3472 }
3473 case KVM_GET_TSC_KHZ: {
cc578287 3474 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3475 goto out;
3476 }
1c0b28c2
EM		 3477 case KVM_KVMCLOCK_CTRL: {
3478 r = kvm_set_guest_paused(vcpu);
3479 goto out;
3480 }
313a3dc7
CO		 3481 default:
3482 r = -EINVAL;
3483 }
3484out:
d1ac91d8 3485 kfree(u.buffer);
313a3dc7
CO		 3486 return r;
3487}
3488
5b1c1493
CO		 3489int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3490{
3491 return VM_FAULT_SIGBUS;
3492}
3493
1fe779f8
CO		 3494static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3495{
3496 int ret;
3497
3498 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3499 return -EINVAL;
1fe779f8
CO		 3500 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3501 return ret;
3502}
3503
b927a3ce
SY		 3504static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3505 u64 ident_addr)
3506{
3507 kvm->arch.ept_identity_map_addr = ident_addr;
3508 return 0;
3509}
3510
1fe779f8
CO		 3511static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3512 u32 kvm_nr_mmu_pages)
3513{
3514 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3515 return -EINVAL;
3516
79fac95e 3517 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3518
3519 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3520 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3521
79fac95e 3522 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3523 return 0;
3524}
3525
3526static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3527{
39de71ec 3528 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3529}
3530
1fe779f8
CO		 3531static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3532{
3533 int r;
3534
3535 r = 0;
3536 switch (chip->chip_id) {
3537 case KVM_IRQCHIP_PIC_MASTER:
3538 memcpy(&chip->chip.pic,
3539 &pic_irqchip(kvm)->pics[0],
3540 sizeof(struct kvm_pic_state));
3541 break;
3542 case KVM_IRQCHIP_PIC_SLAVE:
3543 memcpy(&chip->chip.pic,
3544 &pic_irqchip(kvm)->pics[1],
3545 sizeof(struct kvm_pic_state));
3546 break;
3547 case KVM_IRQCHIP_IOAPIC:
eba0226b 3548 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3549 break;
3550 default:
3551 r = -EINVAL;
3552 break;
3553 }
3554 return r;
3555}
3556
3557static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3558{
3559 int r;
3560
3561 r = 0;
3562 switch (chip->chip_id) {
3563 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3564 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3565 memcpy(&pic_irqchip(kvm)->pics[0],
3566 &chip->chip.pic,
3567 sizeof(struct kvm_pic_state));
f4f51050 3568 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3569 break;
3570 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3571 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3572 memcpy(&pic_irqchip(kvm)->pics[1],
3573 &chip->chip.pic,
3574 sizeof(struct kvm_pic_state));
f4f51050 3575 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3576 break;
3577 case KVM_IRQCHIP_IOAPIC:
eba0226b 3578 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3579 break;
3580 default:
3581 r = -EINVAL;
3582 break;
3583 }
3584 kvm_pic_update_irq(pic_irqchip(kvm));
3585 return r;
3586}
3587
e0f63cb9
SY		 3588static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3589{
3590 int r = 0;
3591
894a9c55 3592 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3593 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3594 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3595 return r;
3596}
3597
3598static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3599{
3600 int r = 0;
3601
894a9c55 3602 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3603 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3604 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3605 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3606 return r;
3607}
3608
3609static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3610{
3611 int r = 0;
3612
3613 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3614 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3615 sizeof(ps->channels));
3616 ps->flags = kvm->arch.vpit->pit_state.flags;
3617 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3618 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3619 return r;
3620}
3621
3622static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3623{
3624 int r = 0, start = 0;
3625 u32 prev_legacy, cur_legacy;
3626 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3627 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3628 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3629 if (!prev_legacy && cur_legacy)
3630 start = 1;
3631 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3632 sizeof(kvm->arch.vpit->pit_state.channels));
3633 kvm->arch.vpit->pit_state.flags = ps->flags;
3634 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3635 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3636 return r;
3637}
3638
52d939a0
MT		 3639static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3640 struct kvm_reinject_control *control)
3641{
3642 if (!kvm->arch.vpit)
3643 return -ENXIO;
894a9c55 3644 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3645 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3646 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3647 return 0;
3648}
3649
95d4c16c 3650/**
60c34612
TY		 3651 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3652 * @kvm: kvm instance
3653 * @log: slot id and address to which we copy the log
95d4c16c 3654 *
60c34612
TY		 3655 * We need to keep it in mind that VCPU threads can write to the bitmap
3656 * concurrently. So, to avoid losing data, we keep the following order for
3657 * each bit:
95d4c16c 3658 *
60c34612
TY		 3659 * 1. Take a snapshot of the bit and clear it if needed.
3660 * 2. Write protect the corresponding page.
3661 * 3. Flush TLB's if needed.
3662 * 4. Copy the snapshot to the userspace.
95d4c16c 3663 *
60c34612
TY		 3664 * Between 2 and 3, the guest may write to the page using the remaining TLB
3665 * entry. This is not a problem because the page will be reported dirty at
3666 * step 4 using the snapshot taken before and step 3 ensures that successive
3667 * writes will be logged for the next call.
5bb064dc 3668 */
60c34612 3669int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3670{
7850ac54 3671 int r;
5bb064dc 3672 struct kvm_memory_slot *memslot;
60c34612
TY		 3673 unsigned long n, i;
3674 unsigned long *dirty_bitmap;
3675 unsigned long *dirty_bitmap_buffer;
3676 bool is_dirty = false;
5bb064dc 3677
79fac95e 3678 mutex_lock(&kvm->slots_lock);
5bb064dc 3679
b050b015 3680 r = -EINVAL;
bbacc0c1 3681 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3682 goto out;
3683
28a37544 3684 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3685
3686 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3687 r = -ENOENT;
60c34612 3688 if (!dirty_bitmap)
b050b015
MT		 3689 goto out;
3690
87bf6e7d 3691 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3692
60c34612
TY		 3693 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3694 memset(dirty_bitmap_buffer, 0, n);
b050b015 3695
60c34612 3696 spin_lock(&kvm->mmu_lock);
b050b015 3697
60c34612
TY		 3698 for (i = 0; i < n / sizeof(long); i++) {
3699 unsigned long mask;
3700 gfn_t offset;
cdfca7b3 3701
60c34612
TY		 3702 if (!dirty_bitmap[i])
3703 continue;
b050b015 3704
60c34612 3705 is_dirty = true;
914ebccd 3706
60c34612
TY		 3707 mask = xchg(&dirty_bitmap[i], 0);
3708 dirty_bitmap_buffer[i] = mask;
edde99ce 3709
60c34612
TY		 3710 offset = i * BITS_PER_LONG;
3711 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3712 }
60c34612
TY		 3713
3714 spin_unlock(&kvm->mmu_lock);
3715
198c74f4
XG		 3716 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3717 lockdep_assert_held(&kvm->slots_lock);
3718
3719 /*
3720 * All the TLBs can be flushed out of mmu lock, see the comments in
3721 * kvm_mmu_slot_remove_write_access().
3722 */
3723 if (is_dirty)
3724 kvm_flush_remote_tlbs(kvm);
3725
60c34612
TY		 3726 r = -EFAULT;
3727 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3728 goto out;
b050b015 3729
5bb064dc
ZX		 3730 r = 0;
3731out:
79fac95e 3732 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3733 return r;
3734}
3735
aa2fbe6d
YZ		 3736int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3737 bool line_status)
23d43cf9
CD		 3738{
3739 if (!irqchip_in_kernel(kvm))
3740 return -ENXIO;
3741
3742 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3743 irq_event->irq, irq_event->level,
3744 line_status);
23d43cf9
CD		 3745 return 0;
3746}
3747
1fe779f8
CO		 3748long kvm_arch_vm_ioctl(struct file *filp,
3749 unsigned int ioctl, unsigned long arg)
3750{
3751 struct kvm *kvm = filp->private_data;
3752 void __user *argp = (void __user *)arg;
367e1319 3753 int r = -ENOTTY;
f0d66275
DH		 3754 /*
3755 * This union makes it completely explicit to gcc-3.x
3756 * that these two variables' stack usage should be
3757 * combined, not added together.
3758 */
3759 union {
3760 struct kvm_pit_state ps;
e9f42757 3761 struct kvm_pit_state2 ps2;
c5ff41ce 3762 struct kvm_pit_config pit_config;
f0d66275 3763 } u;
1fe779f8
CO		 3764
3765 switch (ioctl) {
3766 case KVM_SET_TSS_ADDR:
3767 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3768 break;
b927a3ce
SY		 3769 case KVM_SET_IDENTITY_MAP_ADDR: {
3770 u64 ident_addr;
3771
3772 r = -EFAULT;
3773 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3774 goto out;
3775 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3776 break;
3777 }
1fe779f8
CO		 3778 case KVM_SET_NR_MMU_PAGES:
3779 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3780 break;
3781 case KVM_GET_NR_MMU_PAGES:
3782 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3783 break;
3ddea128
MT		 3784 case KVM_CREATE_IRQCHIP: {
3785 struct kvm_pic *vpic;
3786
3787 mutex_lock(&kvm->lock);
3788 r = -EEXIST;
3789 if (kvm->arch.vpic)
3790 goto create_irqchip_unlock;
3e515705
AK		 3791 r = -EINVAL;
3792 if (atomic_read(&kvm->online_vcpus))
3793 goto create_irqchip_unlock;
1fe779f8 3794 r = -ENOMEM;
3ddea128
MT		 3795 vpic = kvm_create_pic(kvm);
3796 if (vpic) {
1fe779f8
CO		 3797 r = kvm_ioapic_init(kvm);
3798 if (r) {
175504cd 3799 mutex_lock(&kvm->slots_lock);
72bb2fcd 3800 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3801 &vpic->dev_master);
3802 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3803 &vpic->dev_slave);
3804 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3805 &vpic->dev_eclr);
175504cd 3806 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3807 kfree(vpic);
3808 goto create_irqchip_unlock;
1fe779f8
CO		 3809 }
3810 } else
3ddea128
MT		 3811 goto create_irqchip_unlock;
3812 smp_wmb();
3813 kvm->arch.vpic = vpic;
3814 smp_wmb();
399ec807
AK		 3815 r = kvm_setup_default_irq_routing(kvm);
3816 if (r) {
175504cd 3817 mutex_lock(&kvm->slots_lock);
3ddea128 3818 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3819 kvm_ioapic_destroy(kvm);
3820 kvm_destroy_pic(kvm);
3ddea128 3821 mutex_unlock(&kvm->irq_lock);
175504cd 3822 mutex_unlock(&kvm->slots_lock);
399ec807 3823 }
3ddea128
MT		 3824 create_irqchip_unlock:
3825 mutex_unlock(&kvm->lock);
1fe779f8 3826 break;
3ddea128 3827 }
7837699f 3828 case KVM_CREATE_PIT:
c5ff41ce
JK		 3829 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3830 goto create_pit;
3831 case KVM_CREATE_PIT2:
3832 r = -EFAULT;
3833 if (copy_from_user(&u.pit_config, argp,
3834 sizeof(struct kvm_pit_config)))
3835 goto out;
3836 create_pit:
79fac95e 3837 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3838 r = -EEXIST;
3839 if (kvm->arch.vpit)
3840 goto create_pit_unlock;
7837699f 3841 r = -ENOMEM;
c5ff41ce 3842 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3843 if (kvm->arch.vpit)
3844 r = 0;
269e05e4 3845 create_pit_unlock:
79fac95e 3846 mutex_unlock(&kvm->slots_lock);
7837699f 3847 break;
1fe779f8
CO		 3848 case KVM_GET_IRQCHIP: {
3849 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3850 struct kvm_irqchip *chip;
1fe779f8 3851
ff5c2c03
SL		 3852 chip = memdup_user(argp, sizeof(*chip));
3853 if (IS_ERR(chip)) {
3854 r = PTR_ERR(chip);
1fe779f8 3855 goto out;
ff5c2c03
SL		 3856 }
3857
1fe779f8
CO		 3858 r = -ENXIO;
3859 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3860 goto get_irqchip_out;
3861 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3862 if (r)
f0d66275 3863 goto get_irqchip_out;
1fe779f8 3864 r = -EFAULT;
f0d66275
DH		 3865 if (copy_to_user(argp, chip, sizeof *chip))
3866 goto get_irqchip_out;
1fe779f8 3867 r = 0;
f0d66275
DH		 3868 get_irqchip_out:
3869 kfree(chip);
1fe779f8
CO		 3870 break;
3871 }
3872 case KVM_SET_IRQCHIP: {
3873 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3874 struct kvm_irqchip *chip;
1fe779f8 3875
ff5c2c03
SL		 3876 chip = memdup_user(argp, sizeof(*chip));
3877 if (IS_ERR(chip)) {
3878 r = PTR_ERR(chip);
1fe779f8 3879 goto out;
ff5c2c03
SL		 3880 }
3881
1fe779f8
CO		 3882 r = -ENXIO;
3883 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3884 goto set_irqchip_out;
3885 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3886 if (r)
f0d66275 3887 goto set_irqchip_out;
1fe779f8 3888 r = 0;
f0d66275
DH		 3889 set_irqchip_out:
3890 kfree(chip);
1fe779f8
CO		 3891 break;
3892 }
e0f63cb9 3893 case KVM_GET_PIT: {
e0f63cb9 3894 r = -EFAULT;
f0d66275 3895 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3896 goto out;
3897 r = -ENXIO;
3898 if (!kvm->arch.vpit)
3899 goto out;
f0d66275 3900 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3901 if (r)
3902 goto out;
3903 r = -EFAULT;
f0d66275 3904 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3905 goto out;
3906 r = 0;
3907 break;
3908 }
3909 case KVM_SET_PIT: {
e0f63cb9 3910 r = -EFAULT;
f0d66275 3911 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3912 goto out;
3913 r = -ENXIO;
3914 if (!kvm->arch.vpit)
3915 goto out;
f0d66275 3916 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3917 break;
3918 }
e9f42757
BK		 3919 case KVM_GET_PIT2: {
3920 r = -ENXIO;
3921 if (!kvm->arch.vpit)
3922 goto out;
3923 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3924 if (r)
3925 goto out;
3926 r = -EFAULT;
3927 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3928 goto out;
3929 r = 0;
3930 break;
3931 }
3932 case KVM_SET_PIT2: {
3933 r = -EFAULT;
3934 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3935 goto out;
3936 r = -ENXIO;
3937 if (!kvm->arch.vpit)
3938 goto out;
3939 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3940 break;
3941 }
52d939a0
MT		 3942 case KVM_REINJECT_CONTROL: {
3943 struct kvm_reinject_control control;
3944 r = -EFAULT;
3945 if (copy_from_user(&control, argp, sizeof(control)))
3946 goto out;
3947 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3948 break;
3949 }
ffde22ac
ES		 3950 case KVM_XEN_HVM_CONFIG: {
3951 r = -EFAULT;
3952 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3953 sizeof(struct kvm_xen_hvm_config)))
3954 goto out;
3955 r = -EINVAL;
3956 if (kvm->arch.xen_hvm_config.flags)
3957 goto out;
3958 r = 0;
3959 break;
3960 }
afbcf7ab 3961 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3962 struct kvm_clock_data user_ns;
3963 u64 now_ns;
3964 s64 delta;
3965
3966 r = -EFAULT;
3967 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3968 goto out;
3969
3970 r = -EINVAL;
3971 if (user_ns.flags)
3972 goto out;
3973
3974 r = 0;
395c6b0a 3975 local_irq_disable();
759379dd 3976 now_ns = get_kernel_ns();
afbcf7ab 3977 delta = user_ns.clock - now_ns;
395c6b0a 3978 local_irq_enable();
afbcf7ab 3979 kvm->arch.kvmclock_offset = delta;
2e762ff7 3980 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3981 break;
3982 }
3983 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3984 struct kvm_clock_data user_ns;
3985 u64 now_ns;
3986
395c6b0a 3987 local_irq_disable();
759379dd 3988 now_ns = get_kernel_ns();
afbcf7ab 3989 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3990 local_irq_enable();
afbcf7ab 3991 user_ns.flags = 0;
97e69aa6 3992 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3993
3994 r = -EFAULT;
3995 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3996 goto out;
3997 r = 0;
3998 break;
3999 }
4000
1fe779f8
CO		 4001 default:
4002 ;
4003 }
4004out:
4005 return r;
4006}
4007
a16b043c 4008static void kvm_init_msr_list(void)
043405e1
CO		 4009{
4010 u32 dummy[2];
4011 unsigned i, j;
4012
e3267cbb
GC		 4013 /* skip the first msrs in the list. KVM-specific */
4014 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4015 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4016 continue;
93c4adc7
PB		 4017
4018 /*
4019 * Even MSRs that are valid in the host may not be exposed
4020 * to the guests in some cases. We could work around this
4021 * in VMX with the generic MSR save/load machinery, but it
4022 * is not really worthwhile since it will really only
4023 * happen with nested virtualization.
4024 */
4025 switch (msrs_to_save[i]) {
4026 case MSR_IA32_BNDCFGS:
4027 if (!kvm_x86_ops->mpx_supported())
4028 continue;
4029 break;
4030 default:
4031 break;
4032 }
4033
043405e1
CO		 4034 if (j < i)
4035 msrs_to_save[j] = msrs_to_save[i];
4036 j++;
4037 }
4038 num_msrs_to_save = j;
4039}
4040
bda9020e
MT		 4041static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4042 const void *v)
bbd9b64e 4043{
70252a10
AK		 4044 int handled = 0;
4045 int n;
4046
4047 do {
4048 n = min(len, 8);
4049 if (!(vcpu->arch.apic &&
4050 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4051 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4052 break;
4053 handled += n;
4054 addr += n;
4055 len -= n;
4056 v += n;
4057 } while (len);
bbd9b64e 4058
70252a10 4059 return handled;
bbd9b64e
CO		 4060}
4061
bda9020e 4062static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4063{
70252a10
AK		 4064 int handled = 0;
4065 int n;
4066
4067 do {
4068 n = min(len, 8);
4069 if (!(vcpu->arch.apic &&
4070 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4071 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4072 break;
4073 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4074 handled += n;
4075 addr += n;
4076 len -= n;
4077 v += n;
4078 } while (len);
bbd9b64e 4079
70252a10 4080 return handled;
bbd9b64e
CO		 4081}
4082
2dafc6c2
GN		 4083static void kvm_set_segment(struct kvm_vcpu *vcpu,
4084 struct kvm_segment *var, int seg)
4085{
4086 kvm_x86_ops->set_segment(vcpu, var, seg);
4087}
4088
4089void kvm_get_segment(struct kvm_vcpu *vcpu,
4090 struct kvm_segment *var, int seg)
4091{
4092 kvm_x86_ops->get_segment(vcpu, var, seg);
4093}
4094
54987b7a
PB		 4095gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4096 struct x86_exception *exception)
02f59dc9
JR		 4097{
4098 gpa_t t_gpa;
02f59dc9
JR		 4099
4100 BUG_ON(!mmu_is_nested(vcpu));
4101
4102 /* NPT walks are always user-walks */
4103 access |= PFERR_USER_MASK;
54987b7a 4104 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4105
4106 return t_gpa;
4107}
4108
ab9ae313
AK		 4109gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4110 struct x86_exception *exception)
1871c602
GN		 4111{
4112 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4113 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4114}
4115
ab9ae313
AK		 4116 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4117 struct x86_exception *exception)
1871c602
GN		 4118{
4119 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4120 access |= PFERR_FETCH_MASK;
ab9ae313 4121 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4122}
4123
ab9ae313
AK		 4124gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4125 struct x86_exception *exception)
1871c602
GN		 4126{
4127 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4128 access |= PFERR_WRITE_MASK;
ab9ae313 4129 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4130}
4131
4132/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4133gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4134 struct x86_exception *exception)
1871c602 4135{
ab9ae313 4136 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4137}
4138
4139static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4140 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4141 struct x86_exception *exception)
bbd9b64e
CO		 4142{
4143 void *data = val;
10589a46 4144 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4145
4146 while (bytes) {
14dfe855 4147 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4148 exception);
bbd9b64e 4149 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4150 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4151 int ret;
4152
bcc55cba 4153 if (gpa == UNMAPPED_GVA)
ab9ae313 4154 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4155 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4156 offset, toread);
10589a46 4157 if (ret < 0) {
c3cd7ffa 4158 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4159 goto out;
4160 }
bbd9b64e 4161
77c2002e
IE		 4162 bytes -= toread;
4163 data += toread;
4164 addr += toread;
bbd9b64e 4165 }
10589a46 4166out:
10589a46 4167 return r;
bbd9b64e 4168}
77c2002e 4169
1871c602 4170/* used for instruction fetching */
0f65dd70
AK		 4171static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4172 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4173 struct x86_exception *exception)
1871c602 4174{
0f65dd70 4175 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4176 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4177 unsigned offset;
4178 int ret;
0f65dd70 4179
44583cba
PB		 4180 /* Inline kvm_read_guest_virt_helper for speed. */
4181 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4182 exception);
4183 if (unlikely(gpa == UNMAPPED_GVA))
4184 return X86EMUL_PROPAGATE_FAULT;
4185
4186 offset = addr & (PAGE_SIZE-1);
4187 if (WARN_ON(offset + bytes > PAGE_SIZE))
4188 bytes = (unsigned)PAGE_SIZE - offset;
4189 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4190 offset, bytes);
4191 if (unlikely(ret < 0))
4192 return X86EMUL_IO_NEEDED;
4193
4194 return X86EMUL_CONTINUE;
1871c602
GN		 4195}
4196
064aea77 4197int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4198 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4199 struct x86_exception *exception)
1871c602 4200{
0f65dd70 4201 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4202 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4203
1871c602 4204 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4205 exception);
1871c602 4206}
064aea77 4207EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4208
0f65dd70
AK		 4209static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4210 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4211 struct x86_exception *exception)
1871c602 4212{
0f65dd70 4213 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4214 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4215}
4216
6a4d7550 4217int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4218 gva_t addr, void *val,
2dafc6c2 4219 unsigned int bytes,
bcc55cba 4220 struct x86_exception *exception)
77c2002e 4221{
0f65dd70 4222 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4223 void *data = val;
4224 int r = X86EMUL_CONTINUE;
4225
4226 while (bytes) {
14dfe855
JR		 4227 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4228 PFERR_WRITE_MASK,
ab9ae313 4229 exception);
77c2002e
IE		 4230 unsigned offset = addr & (PAGE_SIZE-1);
4231 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4232 int ret;
4233
bcc55cba 4234 if (gpa == UNMAPPED_GVA)
ab9ae313 4235 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4236 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4237 if (ret < 0) {
c3cd7ffa 4238 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4239 goto out;
4240 }
4241
4242 bytes -= towrite;
4243 data += towrite;
4244 addr += towrite;
4245 }
4246out:
4247 return r;
4248}
6a4d7550 4249EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4250
af7cc7d1
XG		 4251static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4252 gpa_t *gpa, struct x86_exception *exception,
4253 bool write)
4254{
97d64b78
AK		 4255 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4256 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4257
97d64b78 4258 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4259 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4260 vcpu->arch.access, access)) {
bebb106a
XG		 4261 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4262 (gva & (PAGE_SIZE - 1));
4f022648 4263 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4264 return 1;
4265 }
4266
af7cc7d1
XG		 4267 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4268
4269 if (*gpa == UNMAPPED_GVA)
4270 return -1;
4271
4272 /* For APIC access vmexit */
4273 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4274 return 1;
4275
4f022648
XG		 4276 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4277 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4278 return 1;
4f022648 4279 }
bebb106a 4280
af7cc7d1
XG		 4281 return 0;
4282}
4283
3200f405 4284int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4285 const void *val, int bytes)
bbd9b64e
CO		 4286{
4287 int ret;
4288
4289 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4290 if (ret < 0)
bbd9b64e 4291 return 0;
f57f2ef5 4292 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4293 return 1;
4294}
4295
77d197b2
XG		 4296struct read_write_emulator_ops {
4297 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4298 int bytes);
4299 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4300 void *val, int bytes);
4301 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4302 int bytes, void *val);
4303 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4304 void *val, int bytes);
4305 bool write;
4306};
4307
4308static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4309{
4310 if (vcpu->mmio_read_completed) {
77d197b2 4311 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4312 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4313 vcpu->mmio_read_completed = 0;
4314 return 1;
4315 }
4316
4317 return 0;
4318}
4319
4320static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4321 void *val, int bytes)
4322{
4323 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4324}
4325
4326static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4327 void *val, int bytes)
4328{
4329 return emulator_write_phys(vcpu, gpa, val, bytes);
4330}
4331
4332static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4333{
4334 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4335 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4336}
4337
4338static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4339 void *val, int bytes)
4340{
4341 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4342 return X86EMUL_IO_NEEDED;
4343}
4344
4345static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4346 void *val, int bytes)
4347{
f78146b0
AK		 4348 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4349
87da7e66 4350 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4351 return X86EMUL_CONTINUE;
4352}
4353
0fbe9b0b 4354static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4355 .read_write_prepare = read_prepare,
4356 .read_write_emulate = read_emulate,
4357 .read_write_mmio = vcpu_mmio_read,
4358 .read_write_exit_mmio = read_exit_mmio,
4359};
4360
0fbe9b0b 4361static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4362 .read_write_emulate = write_emulate,
4363 .read_write_mmio = write_mmio,
4364 .read_write_exit_mmio = write_exit_mmio,
4365 .write = true,
4366};
4367
22388a3c
XG		 4368static int emulator_read_write_onepage(unsigned long addr, void *val,
4369 unsigned int bytes,
4370 struct x86_exception *exception,
4371 struct kvm_vcpu *vcpu,
0fbe9b0b 4372 const struct read_write_emulator_ops *ops)
bbd9b64e 4373{
af7cc7d1
XG		 4374 gpa_t gpa;
4375 int handled, ret;
22388a3c 4376 bool write = ops->write;
f78146b0 4377 struct kvm_mmio_fragment *frag;
10589a46 4378
22388a3c 4379 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4380
af7cc7d1 4381 if (ret < 0)
bbd9b64e 4382 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4383
4384 /* For APIC access vmexit */
af7cc7d1 4385 if (ret)
bbd9b64e
CO		 4386 goto mmio;
4387
22388a3c 4388 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4389 return X86EMUL_CONTINUE;
4390
4391mmio:
4392 /*
4393 * Is this MMIO handled locally?
4394 */
22388a3c 4395 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4396 if (handled == bytes)
bbd9b64e 4397 return X86EMUL_CONTINUE;
bbd9b64e 4398
70252a10
AK		 4399 gpa += handled;
4400 bytes -= handled;
4401 val += handled;
4402
87da7e66
XG		 4403 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4404 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4405 frag->gpa = gpa;
4406 frag->data = val;
4407 frag->len = bytes;
f78146b0 4408 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4409}
4410
22388a3c
XG		 4411int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4412 void *val, unsigned int bytes,
4413 struct x86_exception *exception,
0fbe9b0b 4414 const struct read_write_emulator_ops *ops)
bbd9b64e 4415{
0f65dd70 4416 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4417 gpa_t gpa;
4418 int rc;
4419
4420 if (ops->read_write_prepare &&
4421 ops->read_write_prepare(vcpu, val, bytes))
4422 return X86EMUL_CONTINUE;
4423
4424 vcpu->mmio_nr_fragments = 0;
0f65dd70 4425
bbd9b64e
CO		 4426 /* Crossing a page boundary? */
4427 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4428 int now;
bbd9b64e
CO		 4429
4430 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4431 rc = emulator_read_write_onepage(addr, val, now, exception,
4432 vcpu, ops);
4433
bbd9b64e
CO		 4434 if (rc != X86EMUL_CONTINUE)
4435 return rc;
4436 addr += now;
4437 val += now;
4438 bytes -= now;
4439 }
22388a3c 4440
f78146b0
AK		 4441 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4442 vcpu, ops);
4443 if (rc != X86EMUL_CONTINUE)
4444 return rc;
4445
4446 if (!vcpu->mmio_nr_fragments)
4447 return rc;
4448
4449 gpa = vcpu->mmio_fragments[0].gpa;
4450
4451 vcpu->mmio_needed = 1;
4452 vcpu->mmio_cur_fragment = 0;
4453
87da7e66 4454 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4455 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4456 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4457 vcpu->run->mmio.phys_addr = gpa;
4458
4459 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4460}
4461
4462static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4463 unsigned long addr,
4464 void *val,
4465 unsigned int bytes,
4466 struct x86_exception *exception)
4467{
4468 return emulator_read_write(ctxt, addr, val, bytes,
4469 exception, &read_emultor);
4470}
4471
4472int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4473 unsigned long addr,
4474 const void *val,
4475 unsigned int bytes,
4476 struct x86_exception *exception)
4477{
4478 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4479 exception, &write_emultor);
bbd9b64e 4480}
bbd9b64e 4481
daea3e73
AK		 4482#define CMPXCHG_TYPE(t, ptr, old, new) \
4483 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4484
4485#ifdef CONFIG_X86_64
4486# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4487#else
4488# define CMPXCHG64(ptr, old, new) \
9749a6c0 4489 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4490#endif
4491
0f65dd70
AK		 4492static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4493 unsigned long addr,
bbd9b64e
CO		 4494 const void *old,
4495 const void *new,
4496 unsigned int bytes,
0f65dd70 4497 struct x86_exception *exception)
bbd9b64e 4498{
0f65dd70 4499 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4500 gpa_t gpa;
4501 struct page *page;
4502 char *kaddr;
4503 bool exchanged;
2bacc55c 4504
daea3e73
AK		 4505 /* guests cmpxchg8b have to be emulated atomically */
4506 if (bytes > 8 || (bytes & (bytes - 1)))
4507 goto emul_write;
10589a46 4508
daea3e73 4509 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4510
daea3e73
AK		 4511 if (gpa == UNMAPPED_GVA ||
4512 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4513 goto emul_write;
2bacc55c 4514
daea3e73
AK		 4515 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4516 goto emul_write;
72dc67a6 4517
daea3e73 4518 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4519 if (is_error_page(page))
c19b8bd6 4520 goto emul_write;
72dc67a6 4521
8fd75e12 4522 kaddr = kmap_atomic(page);
daea3e73
AK		 4523 kaddr += offset_in_page(gpa);
4524 switch (bytes) {
4525 case 1:
4526 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4527 break;
4528 case 2:
4529 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4530 break;
4531 case 4:
4532 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4533 break;
4534 case 8:
4535 exchanged = CMPXCHG64(kaddr, old, new);
4536 break;
4537 default:
4538 BUG();
2bacc55c 4539 }
8fd75e12 4540 kunmap_atomic(kaddr);
daea3e73
AK		 4541 kvm_release_page_dirty(page);
4542
4543 if (!exchanged)
4544 return X86EMUL_CMPXCHG_FAILED;
4545
d3714010 4546 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4547 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4548
4549 return X86EMUL_CONTINUE;
4a5f48f6 4550
3200f405 4551emul_write:
daea3e73 4552 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4553
0f65dd70 4554 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4555}
4556
cf8f70bf
GN		 4557static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4558{
4559 /* TODO: String I/O for in kernel device */
4560 int r;
4561
4562 if (vcpu->arch.pio.in)
4563 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4564 vcpu->arch.pio.size, pd);
4565 else
4566 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4567 vcpu->arch.pio.port, vcpu->arch.pio.size,
4568 pd);
4569 return r;
4570}
4571
6f6fbe98
XG		 4572static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4573 unsigned short port, void *val,
4574 unsigned int count, bool in)
cf8f70bf 4575{
cf8f70bf 4576 vcpu->arch.pio.port = port;
6f6fbe98 4577 vcpu->arch.pio.in = in;
7972995b 4578 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4579 vcpu->arch.pio.size = size;
4580
4581 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4582 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4583 return 1;
4584 }
4585
4586 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4587 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4588 vcpu->run->io.size = size;
4589 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4590 vcpu->run->io.count = count;
4591 vcpu->run->io.port = port;
4592
4593 return 0;
4594}
4595
6f6fbe98
XG		 4596static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4597 int size, unsigned short port, void *val,
4598 unsigned int count)
cf8f70bf 4599{
ca1d4a9e 4600 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4601 int ret;
ca1d4a9e 4602
6f6fbe98
XG		 4603 if (vcpu->arch.pio.count)
4604 goto data_avail;
cf8f70bf 4605
6f6fbe98
XG		 4606 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4607 if (ret) {
4608data_avail:
4609 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4610 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4611 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4612 return 1;
4613 }
4614
cf8f70bf
GN		 4615 return 0;
4616}
4617
6f6fbe98
XG		 4618static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4619 int size, unsigned short port,
4620 const void *val, unsigned int count)
4621{
4622 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4623
4624 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4625 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4626 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4627}
4628
bbd9b64e
CO		 4629static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4630{
4631 return kvm_x86_ops->get_segment_base(vcpu, seg);
4632}
4633
3cb16fe7 4634static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4635{
3cb16fe7 4636 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4637}
4638
f5f48ee1
SY		 4639int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4640{
4641 if (!need_emulate_wbinvd(vcpu))
4642 return X86EMUL_CONTINUE;
4643
4644 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4645 int cpu = get_cpu();
4646
4647 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4648 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4649 wbinvd_ipi, NULL, 1);
2eec7343 4650 put_cpu();
f5f48ee1 4651 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4652 } else
4653 wbinvd();
f5f48ee1
SY		 4654 return X86EMUL_CONTINUE;
4655}
4656EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4657
bcaf5cc5
AK		 4658static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4659{
4660 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4661}
4662
717746e3 4663int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4664{
717746e3 4665 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4666}
4667
717746e3 4668int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4669{
338dbc97 4670
717746e3 4671 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4672}
4673
52a46617 4674static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4675{
52a46617 4676 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4677}
4678
717746e3 4679static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4680{
717746e3 4681 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4682 unsigned long value;
4683
4684 switch (cr) {
4685 case 0:
4686 value = kvm_read_cr0(vcpu);
4687 break;
4688 case 2:
4689 value = vcpu->arch.cr2;
4690 break;
4691 case 3:
9f8fe504 4692 value = kvm_read_cr3(vcpu);
52a46617
GN		 4693 break;
4694 case 4:
4695 value = kvm_read_cr4(vcpu);
4696 break;
4697 case 8:
4698 value = kvm_get_cr8(vcpu);
4699 break;
4700 default:
a737f256 4701 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4702 return 0;
4703 }
4704
4705 return value;
4706}
4707
717746e3 4708static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4709{
717746e3 4710 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4711 int res = 0;
4712
52a46617
GN		 4713 switch (cr) {
4714 case 0:
49a9b07e 4715 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4716 break;
4717 case 2:
4718 vcpu->arch.cr2 = val;
4719 break;
4720 case 3:
2390218b 4721 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4722 break;
4723 case 4:
a83b29c6 4724 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4725 break;
4726 case 8:
eea1cff9 4727 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4728 break;
4729 default:
a737f256 4730 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4731 res = -1;
52a46617 4732 }
0f12244f
GN		 4733
4734 return res;
52a46617
GN		 4735}
4736
717746e3 4737static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4738{
717746e3 4739 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4740}
4741
4bff1e86 4742static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4743{
4bff1e86 4744 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4745}
4746
4bff1e86 4747static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4748{
4bff1e86 4749 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4750}
4751
1ac9d0cf
AK		 4752static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4753{
4754 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4755}
4756
4757static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4758{
4759 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4760}
4761
4bff1e86
AK		 4762static unsigned long emulator_get_cached_segment_base(
4763 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4764{
4bff1e86 4765 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4766}
4767
1aa36616
AK		 4768static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4769 struct desc_struct *desc, u32 *base3,
4770 int seg)
2dafc6c2
GN		 4771{
4772 struct kvm_segment var;
4773
4bff1e86 4774 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4775 *selector = var.selector;
2dafc6c2 4776
378a8b09
GN		 4777 if (var.unusable) {
4778 memset(desc, 0, sizeof(*desc));
2dafc6c2 4779 return false;
378a8b09 4780 }
2dafc6c2
GN		 4781
4782 if (var.g)
4783 var.limit >>= 12;
4784 set_desc_limit(desc, var.limit);
4785 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4786#ifdef CONFIG_X86_64
4787 if (base3)
4788 *base3 = var.base >> 32;
4789#endif
2dafc6c2
GN		 4790 desc->type = var.type;
4791 desc->s = var.s;
4792 desc->dpl = var.dpl;
4793 desc->p = var.present;
4794 desc->avl = var.avl;
4795 desc->l = var.l;
4796 desc->d = var.db;
4797 desc->g = var.g;
4798
4799 return true;
4800}
4801
1aa36616
AK		 4802static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4803 struct desc_struct *desc, u32 base3,
4804 int seg)
2dafc6c2 4805{
4bff1e86 4806 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4807 struct kvm_segment var;
4808
1aa36616 4809 var.selector = selector;
2dafc6c2 4810 var.base = get_desc_base(desc);
5601d05b
GN		 4811#ifdef CONFIG_X86_64
4812 var.base |= ((u64)base3) << 32;
4813#endif
2dafc6c2
GN		 4814 var.limit = get_desc_limit(desc);
4815 if (desc->g)
4816 var.limit = (var.limit << 12) | 0xfff;
4817 var.type = desc->type;
2dafc6c2
GN		 4818 var.dpl = desc->dpl;
4819 var.db = desc->d;
4820 var.s = desc->s;
4821 var.l = desc->l;
4822 var.g = desc->g;
4823 var.avl = desc->avl;
4824 var.present = desc->p;
4825 var.unusable = !var.present;
4826 var.padding = 0;
4827
4828 kvm_set_segment(vcpu, &var, seg);
4829 return;
4830}
4831
717746e3
AK		 4832static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4833 u32 msr_index, u64 *pdata)
4834{
4835 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4836}
4837
4838static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4839 u32 msr_index, u64 data)
4840{
8fe8ab46
WA		 4841 struct msr_data msr;
4842
4843 msr.data = data;
4844 msr.index = msr_index;
4845 msr.host_initiated = false;
4846 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4847}
4848
67f4d428
NA		 4849static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4850 u32 pmc)
4851{
4852 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4853}
4854
222d21aa
AK		 4855static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4856 u32 pmc, u64 *pdata)
4857{
4858 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4859}
4860
6c3287f7
AK		 4861static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4862{
4863 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4864}
4865
5037f6f3
AK		 4866static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4867{
4868 preempt_disable();
5197b808 4869 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4870 /*
4871 * CR0.TS may reference the host fpu state, not the guest fpu state,
4872 * so it may be clear at this point.
4873 */
4874 clts();
4875}
4876
4877static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4878{
4879 preempt_enable();
4880}
4881
2953538e 4882static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4883 struct x86_instruction_info *info,
c4f035c6
AK		 4884 enum x86_intercept_stage stage)
4885{
2953538e 4886 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4887}
4888
0017f93a 4889static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4890 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4891{
0017f93a 4892 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4893}
4894
dd856efa
AK		 4895static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4896{
4897 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4898}
4899
4900static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4901{
4902 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4903}
4904
0225fb50 4905static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4906 .read_gpr = emulator_read_gpr,
4907 .write_gpr = emulator_write_gpr,
1871c602 4908 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4909 .write_std = kvm_write_guest_virt_system,
1871c602 4910 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4911 .read_emulated = emulator_read_emulated,
4912 .write_emulated = emulator_write_emulated,
4913 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4914 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4915 .pio_in_emulated = emulator_pio_in_emulated,
4916 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4917 .get_segment = emulator_get_segment,
4918 .set_segment = emulator_set_segment,
5951c442 4919 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4920 .get_gdt = emulator_get_gdt,
160ce1f1 4921 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4922 .set_gdt = emulator_set_gdt,
4923 .set_idt = emulator_set_idt,
52a46617
GN		 4924 .get_cr = emulator_get_cr,
4925 .set_cr = emulator_set_cr,
9c537244 4926 .cpl = emulator_get_cpl,
35aa5375
GN		 4927 .get_dr = emulator_get_dr,
4928 .set_dr = emulator_set_dr,
717746e3
AK		 4929 .set_msr = emulator_set_msr,
4930 .get_msr = emulator_get_msr,
67f4d428 4931 .check_pmc = emulator_check_pmc,
222d21aa 4932 .read_pmc = emulator_read_pmc,
6c3287f7 4933 .halt = emulator_halt,
bcaf5cc5 4934 .wbinvd = emulator_wbinvd,
d6aa1000 4935 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4936 .get_fpu = emulator_get_fpu,
4937 .put_fpu = emulator_put_fpu,
c4f035c6 4938 .intercept = emulator_intercept,
bdb42f5a 4939 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4940};
4941
95cb2295
GN		 4942static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4943{
37ccdcbe 4944 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4945 /*
4946 * an sti; sti; sequence only disable interrupts for the first
4947 * instruction. So, if the last instruction, be it emulated or
4948 * not, left the system with the INT_STI flag enabled, it
4949 * means that the last instruction is an sti. We should not
4950 * leave the flag on in this case. The same goes for mov ss
4951 */
37ccdcbe
PB		 4952 if (int_shadow & mask)
4953 mask = 0;
6addfc42 4954 if (unlikely(int_shadow || mask)) {
95cb2295 4955 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4956 if (!mask)
4957 kvm_make_request(KVM_REQ_EVENT, vcpu);
4958 }
95cb2295
GN		 4959}
4960
ef54bcfe 4961static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4962{
4963 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4964 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4965 return kvm_propagate_fault(vcpu, &ctxt->exception);
4966
4967 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4968 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4969 ctxt->exception.error_code);
54b8486f 4970 else
da9cb575 4971 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4972 return false;
54b8486f
GN		 4973}
4974
8ec4722d
MG		 4975static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4976{
adf52235 4977 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4978 int cs_db, cs_l;
4979
8ec4722d
MG		 4980 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4981
adf52235
TY		 4982 ctxt->eflags = kvm_get_rflags(vcpu);
4983 ctxt->eip = kvm_rip_read(vcpu);
4984 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4985 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4986 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4987 cs_db ? X86EMUL_MODE_PROT32 :
4988 X86EMUL_MODE_PROT16;
4989 ctxt->guest_mode = is_guest_mode(vcpu);
4990
dd856efa 4991 init_decode_cache(ctxt);
7ae441ea 4992 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4993}
4994
71f9833b 4995int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4996{
9d74191a 4997 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4998 int ret;
4999
5000 init_emulate_ctxt(vcpu);
5001
9dac77fa
AK		 5002 ctxt->op_bytes = 2;
5003 ctxt->ad_bytes = 2;
5004 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5005 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5006
5007 if (ret != X86EMUL_CONTINUE)
5008 return EMULATE_FAIL;
5009
9dac77fa 5010 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5011 kvm_rip_write(vcpu, ctxt->eip);
5012 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5013
5014 if (irq == NMI_VECTOR)
7460fb4a 5015 vcpu->arch.nmi_pending = 0;
63995653
MG		 5016 else
5017 vcpu->arch.interrupt.pending = false;
5018
5019 return EMULATE_DONE;
5020}
5021EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5022
6d77dbfc
GN		 5023static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5024{
fc3a9157
JR		 5025 int r = EMULATE_DONE;
5026
6d77dbfc
GN		 5027 ++vcpu->stat.insn_emulation_fail;
5028 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5029 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5030 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5031 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5032 vcpu->run->internal.ndata = 0;
5033 r = EMULATE_FAIL;
5034 }
6d77dbfc 5035 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5036
5037 return r;
6d77dbfc
GN		 5038}
5039
93c05d3e 5040static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5041 bool write_fault_to_shadow_pgtable,
5042 int emulation_type)
a6f177ef 5043{
95b3cf69 5044 gpa_t gpa = cr2;
8e3d9d06 5045 pfn_t pfn;
a6f177ef 5046
991eebf9
GN		 5047 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5048 return false;
5049
95b3cf69
XG		 5050 if (!vcpu->arch.mmu.direct_map) {
5051 /*
5052 * Write permission should be allowed since only
5053 * write access need to be emulated.
5054 */
5055 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5056
95b3cf69
XG		 5057 /*
5058 * If the mapping is invalid in guest, let cpu retry
5059 * it to generate fault.
5060 */
5061 if (gpa == UNMAPPED_GVA)
5062 return true;
5063 }
a6f177ef 5064
8e3d9d06
XG		 5065 /*
5066 * Do not retry the unhandleable instruction if it faults on the
5067 * readonly host memory, otherwise it will goto a infinite loop:
5068 * retry instruction -> write #PF -> emulation fail -> retry
5069 * instruction -> ...
5070 */
5071 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5072
5073 /*
5074 * If the instruction failed on the error pfn, it can not be fixed,
5075 * report the error to userspace.
5076 */
5077 if (is_error_noslot_pfn(pfn))
5078 return false;
5079
5080 kvm_release_pfn_clean(pfn);
5081
5082 /* The instructions are well-emulated on direct mmu. */
5083 if (vcpu->arch.mmu.direct_map) {
5084 unsigned int indirect_shadow_pages;
5085
5086 spin_lock(&vcpu->kvm->mmu_lock);
5087 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5088 spin_unlock(&vcpu->kvm->mmu_lock);
5089
5090 if (indirect_shadow_pages)
5091 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5092
a6f177ef 5093 return true;
8e3d9d06 5094 }
a6f177ef 5095
95b3cf69
XG		 5096 /*
5097 * if emulation was due to access to shadowed page table
5098 * and it failed try to unshadow page and re-enter the
5099 * guest to let CPU execute the instruction.
5100 */
5101 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5102
5103 /*
5104 * If the access faults on its page table, it can not
5105 * be fixed by unprotecting shadow page and it should
5106 * be reported to userspace.
5107 */
5108 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5109}
5110
1cb3f3ae
XG		 5111static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5112 unsigned long cr2, int emulation_type)
5113{
5114 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5115 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5116
5117 last_retry_eip = vcpu->arch.last_retry_eip;
5118 last_retry_addr = vcpu->arch.last_retry_addr;
5119
5120 /*
5121 * If the emulation is caused by #PF and it is non-page_table
5122 * writing instruction, it means the VM-EXIT is caused by shadow
5123 * page protected, we can zap the shadow page and retry this
5124 * instruction directly.
5125 *
5126 * Note: if the guest uses a non-page-table modifying instruction
5127 * on the PDE that points to the instruction, then we will unmap
5128 * the instruction and go to an infinite loop. So, we cache the
5129 * last retried eip and the last fault address, if we meet the eip
5130 * and the address again, we can break out of the potential infinite
5131 * loop.
5132 */
5133 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5134
5135 if (!(emulation_type & EMULTYPE_RETRY))
5136 return false;
5137
5138 if (x86_page_table_writing_insn(ctxt))
5139 return false;
5140
5141 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5142 return false;
5143
5144 vcpu->arch.last_retry_eip = ctxt->eip;
5145 vcpu->arch.last_retry_addr = cr2;
5146
5147 if (!vcpu->arch.mmu.direct_map)
5148 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5149
22368028 5150 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5151
5152 return true;
5153}
5154
716d51ab
GN		 5155static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5156static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5157
4a1e10d5
PB		 5158static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5159 unsigned long *db)
5160{
5161 u32 dr6 = 0;
5162 int i;
5163 u32 enable, rwlen;
5164
5165 enable = dr7;
5166 rwlen = dr7 >> 16;
5167 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5168 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5169 dr6 |= (1 << i);
5170 return dr6;
5171}
5172
6addfc42 5173static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5174{
5175 struct kvm_run *kvm_run = vcpu->run;
5176
5177 /*
6addfc42
PB		 5178 * rflags is the old, "raw" value of the flags. The new value has
5179 * not been saved yet.
663f4c61
PB		 5180 *
5181 * This is correct even for TF set by the guest, because "the
5182 * processor will not generate this exception after the instruction
5183 * that sets the TF flag".
5184 */
663f4c61
PB		 5185 if (unlikely(rflags & X86_EFLAGS_TF)) {
5186 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5187 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5188 DR6_RTM;
663f4c61
PB		 5189 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5190 kvm_run->debug.arch.exception = DB_VECTOR;
5191 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5192 *r = EMULATE_USER_EXIT;
5193 } else {
5194 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5195 /*
5196 * "Certain debug exceptions may clear bit 0-3. The
5197 * remaining contents of the DR6 register are never
5198 * cleared by the processor".
5199 */
5200 vcpu->arch.dr6 &= ~15;
6f43ed01 5201 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5202 kvm_queue_exception(vcpu, DB_VECTOR);
5203 }
5204 }
5205}
5206
4a1e10d5
PB		 5207static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5208{
5209 struct kvm_run *kvm_run = vcpu->run;
5210 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5211 u32 dr6 = 0;
5212
5213 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5214 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5215 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5216 vcpu->arch.guest_debug_dr7,
5217 vcpu->arch.eff_db);
5218
5219 if (dr6 != 0) {
6f43ed01 5220 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
4a1e10d5
PB		 5221 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5222 get_segment_base(vcpu, VCPU_SREG_CS);
5223
5224 kvm_run->debug.arch.exception = DB_VECTOR;
5225 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5226 *r = EMULATE_USER_EXIT;
5227 return true;
5228 }
5229 }
5230
4161a569
NA		 5231 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5232 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
4a1e10d5
PB		 5233 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5234 vcpu->arch.dr7,
5235 vcpu->arch.db);
5236
5237 if (dr6 != 0) {
5238 vcpu->arch.dr6 &= ~15;
6f43ed01 5239 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5240 kvm_queue_exception(vcpu, DB_VECTOR);
5241 *r = EMULATE_DONE;
5242 return true;
5243 }
5244 }
5245
5246 return false;
5247}
5248
51d8b661
AP		 5249int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5250 unsigned long cr2,
dc25e89e
AP		 5251 int emulation_type,
5252 void *insn,
5253 int insn_len)
bbd9b64e 5254{
95cb2295 5255 int r;
9d74191a 5256 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5257 bool writeback = true;
93c05d3e 5258 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5259
93c05d3e
XG		 5260 /*
5261 * Clear write_fault_to_shadow_pgtable here to ensure it is
5262 * never reused.
5263 */
5264 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5265 kvm_clear_exception_queue(vcpu);
8d7d8102 5266
571008da 5267 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5268 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5269
5270 /*
5271 * We will reenter on the same instruction since
5272 * we do not set complete_userspace_io. This does not
5273 * handle watchpoints yet, those would be handled in
5274 * the emulate_ops.
5275 */
5276 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5277 return r;
5278
9d74191a
TY		 5279 ctxt->interruptibility = 0;
5280 ctxt->have_exception = false;
e0ad0b47 5281 ctxt->exception.vector = -1;
9d74191a 5282 ctxt->perm_ok = false;
bbd9b64e 5283
b51e974f 5284 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5285
9d74191a 5286 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5287
e46479f8 5288 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5289 ++vcpu->stat.insn_emulation;
1d2887e2 5290 if (r != EMULATION_OK) {
4005996e
AK		 5291 if (emulation_type & EMULTYPE_TRAP_UD)
5292 return EMULATE_FAIL;
991eebf9
GN		 5293 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5294 emulation_type))
bbd9b64e 5295 return EMULATE_DONE;
6d77dbfc
GN		 5296 if (emulation_type & EMULTYPE_SKIP)
5297 return EMULATE_FAIL;
5298 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5299 }
5300 }
5301
ba8afb6b 5302 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5303 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5304 if (ctxt->eflags & X86_EFLAGS_RF)
5305 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5306 return EMULATE_DONE;
5307 }
5308
1cb3f3ae
XG		 5309 if (retry_instruction(ctxt, cr2, emulation_type))
5310 return EMULATE_DONE;
5311
7ae441ea 5312 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5313 changes registers values during IO operation */
7ae441ea
GN		 5314 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5315 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5316 emulator_invalidate_register_cache(ctxt);
7ae441ea 5317 }
4d2179e1 5318
5cd21917 5319restart:
9d74191a 5320 r = x86_emulate_insn(ctxt);
bbd9b64e 5321
775fde86
JR		 5322 if (r == EMULATION_INTERCEPTED)
5323 return EMULATE_DONE;
5324
d2ddd1c4 5325 if (r == EMULATION_FAILED) {
991eebf9
GN		 5326 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5327 emulation_type))
c3cd7ffa
GN		 5328 return EMULATE_DONE;
5329
6d77dbfc 5330 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5331 }
5332
9d74191a 5333 if (ctxt->have_exception) {
d2ddd1c4 5334 r = EMULATE_DONE;
ef54bcfe
PB		 5335 if (inject_emulated_exception(vcpu))
5336 return r;
d2ddd1c4 5337 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5338 if (!vcpu->arch.pio.in) {
5339 /* FIXME: return into emulator if single-stepping. */
3457e419 5340 vcpu->arch.pio.count = 0;
0912c977 5341 } else {
7ae441ea 5342 writeback = false;
716d51ab
GN		 5343 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5344 }
ac0a48c3 5345 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5346 } else if (vcpu->mmio_needed) {
5347 if (!vcpu->mmio_is_write)
5348 writeback = false;
ac0a48c3 5349 r = EMULATE_USER_EXIT;
716d51ab 5350 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5351 } else if (r == EMULATION_RESTART)
5cd21917 5352 goto restart;
d2ddd1c4
GN		 5353 else
5354 r = EMULATE_DONE;
f850e2e6 5355
7ae441ea 5356 if (writeback) {
6addfc42 5357 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5358 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5359 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5360 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5361 if (r == EMULATE_DONE)
6addfc42
PB		 5362 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5363 __kvm_set_rflags(vcpu, ctxt->eflags);
5364
5365 /*
5366 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5367 * do nothing, and it will be requested again as soon as
5368 * the shadow expires. But we still need to check here,
5369 * because POPF has no interrupt shadow.
5370 */
5371 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5372 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5373 } else
5374 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5375
5376 return r;
de7d789a 5377}
51d8b661 5378EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5379
cf8f70bf 5380int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5381{
cf8f70bf 5382 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5383 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5384 size, port, &val, 1);
cf8f70bf 5385 /* do not return to emulator after return from userspace */
7972995b 5386 vcpu->arch.pio.count = 0;
de7d789a
CO		 5387 return ret;
5388}
cf8f70bf 5389EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5390
8cfdc000
ZA		 5391static void tsc_bad(void *info)
5392{
0a3aee0d 5393 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5394}
5395
5396static void tsc_khz_changed(void *data)
c8076604 5397{
8cfdc000
ZA		 5398 struct cpufreq_freqs *freq = data;
5399 unsigned long khz = 0;
5400
5401 if (data)
5402 khz = freq->new;
5403 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5404 khz = cpufreq_quick_get(raw_smp_processor_id());
5405 if (!khz)
5406 khz = tsc_khz;
0a3aee0d 5407 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5408}
5409
c8076604
GH		 5410static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5411 void *data)
5412{
5413 struct cpufreq_freqs *freq = data;
5414 struct kvm *kvm;
5415 struct kvm_vcpu *vcpu;
5416 int i, send_ipi = 0;
5417
8cfdc000
ZA		 5418 /*
5419 * We allow guests to temporarily run on slowing clocks,
5420 * provided we notify them after, or to run on accelerating
5421 * clocks, provided we notify them before. Thus time never
5422 * goes backwards.
5423 *
5424 * However, we have a problem. We can't atomically update
5425 * the frequency of a given CPU from this function; it is
5426 * merely a notifier, which can be called from any CPU.
5427 * Changing the TSC frequency at arbitrary points in time
5428 * requires a recomputation of local variables related to
5429 * the TSC for each VCPU. We must flag these local variables
5430 * to be updated and be sure the update takes place with the
5431 * new frequency before any guests proceed.
5432 *
5433 * Unfortunately, the combination of hotplug CPU and frequency
5434 * change creates an intractable locking scenario; the order
5435 * of when these callouts happen is undefined with respect to
5436 * CPU hotplug, and they can race with each other. As such,
5437 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5438 * undefined; you can actually have a CPU frequency change take
5439 * place in between the computation of X and the setting of the
5440 * variable. To protect against this problem, all updates of
5441 * the per_cpu tsc_khz variable are done in an interrupt
5442 * protected IPI, and all callers wishing to update the value
5443 * must wait for a synchronous IPI to complete (which is trivial
5444 * if the caller is on the CPU already). This establishes the
5445 * necessary total order on variable updates.
5446 *
5447 * Note that because a guest time update may take place
5448 * anytime after the setting of the VCPU's request bit, the
5449 * correct TSC value must be set before the request. However,
5450 * to ensure the update actually makes it to any guest which
5451 * starts running in hardware virtualization between the set
5452 * and the acquisition of the spinlock, we must also ping the
5453 * CPU after setting the request bit.
5454 *
5455 */
5456
c8076604
GH		 5457 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5458 return 0;
5459 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5460 return 0;
8cfdc000
ZA		 5461
5462 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5463
2f303b74 5464 spin_lock(&kvm_lock);
c8076604 5465 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5466 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5467 if (vcpu->cpu != freq->cpu)
5468 continue;
c285545f 5469 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5470 if (vcpu->cpu != smp_processor_id())
8cfdc000 5471 send_ipi = 1;
c8076604
GH		 5472 }
5473 }
2f303b74 5474 spin_unlock(&kvm_lock);
c8076604
GH		 5475
5476 if (freq->old < freq->new && send_ipi) {
5477 /*
5478 * We upscale the frequency. Must make the guest
5479 * doesn't see old kvmclock values while running with
5480 * the new frequency, otherwise we risk the guest sees
5481 * time go backwards.
5482 *
5483 * In case we update the frequency for another cpu
5484 * (which might be in guest context) send an interrupt
5485 * to kick the cpu out of guest context. Next time
5486 * guest context is entered kvmclock will be updated,
5487 * so the guest will not see stale values.
5488 */
8cfdc000 5489 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5490 }
5491 return 0;
5492}
5493
5494static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5495 .notifier_call = kvmclock_cpufreq_notifier
5496};
5497
5498static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5499 unsigned long action, void *hcpu)
5500{
5501 unsigned int cpu = (unsigned long)hcpu;
5502
5503 switch (action) {
5504 case CPU_ONLINE:
5505 case CPU_DOWN_FAILED:
5506 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5507 break;
5508 case CPU_DOWN_PREPARE:
5509 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5510 break;
5511 }
5512 return NOTIFY_OK;
5513}
5514
5515static struct notifier_block kvmclock_cpu_notifier_block = {
5516 .notifier_call = kvmclock_cpu_notifier,
5517 .priority = -INT_MAX
c8076604
GH		 5518};
5519
b820cc0c
ZA		 5520static void kvm_timer_init(void)
5521{
5522 int cpu;
5523
c285545f 5524 max_tsc_khz = tsc_khz;
460dd42e
SB		 5525
5526 cpu_notifier_register_begin();
b820cc0c 5527 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5528#ifdef CONFIG_CPU_FREQ
5529 struct cpufreq_policy policy;
5530 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5531 cpu = get_cpu();
5532 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5533 if (policy.cpuinfo.max_freq)
5534 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5535 put_cpu();
c285545f 5536#endif
b820cc0c
ZA		 5537 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5538 CPUFREQ_TRANSITION_NOTIFIER);
5539 }
c285545f 5540 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5541 for_each_online_cpu(cpu)
5542 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5543
5544 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5545 cpu_notifier_register_done();
5546
b820cc0c
ZA		 5547}
5548
ff9d07a0
ZY		 5549static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5550
f5132b01 5551int kvm_is_in_guest(void)
ff9d07a0 5552{
086c9855 5553 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5554}
5555
5556static int kvm_is_user_mode(void)
5557{
5558 int user_mode = 3;
dcf46b94 5559
086c9855
AS		 5560 if (__this_cpu_read(current_vcpu))
5561 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5562
ff9d07a0
ZY		 5563 return user_mode != 0;
5564}
5565
5566static unsigned long kvm_get_guest_ip(void)
5567{
5568 unsigned long ip = 0;
dcf46b94 5569
086c9855
AS		 5570 if (__this_cpu_read(current_vcpu))
5571 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5572
ff9d07a0
ZY		 5573 return ip;
5574}
5575
5576static struct perf_guest_info_callbacks kvm_guest_cbs = {
5577 .is_in_guest = kvm_is_in_guest,
5578 .is_user_mode = kvm_is_user_mode,
5579 .get_guest_ip = kvm_get_guest_ip,
5580};
5581
5582void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5583{
086c9855 5584 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5585}
5586EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5587
5588void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5589{
086c9855 5590 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5591}
5592EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5593
ce88decf
XG		 5594static void kvm_set_mmio_spte_mask(void)
5595{
5596 u64 mask;
5597 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5598
5599 /*
5600 * Set the reserved bits and the present bit of an paging-structure
5601 * entry to generate page fault with PFER.RSV = 1.
5602 */
885032b9 5603 /* Mask the reserved physical address bits. */
d1431483 5604 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5605
5606 /* Bit 62 is always reserved for 32bit host. */
5607 mask |= 0x3ull << 62;
5608
5609 /* Set the present bit. */
ce88decf
XG		 5610 mask |= 1ull;
5611
5612#ifdef CONFIG_X86_64
5613 /*
5614 * If reserved bit is not supported, clear the present bit to disable
5615 * mmio page fault.
5616 */
5617 if (maxphyaddr == 52)
5618 mask &= ~1ull;
5619#endif
5620
5621 kvm_mmu_set_mmio_spte_mask(mask);
5622}
5623
16e8d74d
MT		 5624#ifdef CONFIG_X86_64
5625static void pvclock_gtod_update_fn(struct work_struct *work)
5626{
d828199e
MT		 5627 struct kvm *kvm;
5628
5629 struct kvm_vcpu *vcpu;
5630 int i;
5631
2f303b74 5632 spin_lock(&kvm_lock);
d828199e
MT		 5633 list_for_each_entry(kvm, &vm_list, vm_list)
5634 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5635 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5636 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5637 spin_unlock(&kvm_lock);
16e8d74d
MT		 5638}
5639
5640static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5641
5642/*
5643 * Notification about pvclock gtod data update.
5644 */
5645static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5646 void *priv)
5647{
5648 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5649 struct timekeeper *tk = priv;
5650
5651 update_pvclock_gtod(tk);
5652
5653 /* disable master clock if host does not trust, or does not
5654 * use, TSC clocksource
5655 */
5656 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5657 atomic_read(&kvm_guest_has_master_clock) != 0)
5658 queue_work(system_long_wq, &pvclock_gtod_work);
5659
5660 return 0;
5661}
5662
5663static struct notifier_block pvclock_gtod_notifier = {
5664 .notifier_call = pvclock_gtod_notify,
5665};
5666#endif
5667
f8c16bba 5668int kvm_arch_init(void *opaque)
043405e1 5669{
b820cc0c 5670 int r;
6b61edf7 5671 struct kvm_x86_ops *ops = opaque;
f8c16bba 5672
f8c16bba
ZX		 5673 if (kvm_x86_ops) {
5674 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5675 r = -EEXIST;
5676 goto out;
f8c16bba
ZX		 5677 }
5678
5679 if (!ops->cpu_has_kvm_support()) {
5680 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5681 r = -EOPNOTSUPP;
5682 goto out;
f8c16bba
ZX		 5683 }
5684 if (ops->disabled_by_bios()) {
5685 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5686 r = -EOPNOTSUPP;
5687 goto out;
f8c16bba
ZX		 5688 }
5689
013f6a5d
MT		 5690 r = -ENOMEM;
5691 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5692 if (!shared_msrs) {
5693 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5694 goto out;
5695 }
5696
97db56ce
AK		 5697 r = kvm_mmu_module_init();
5698 if (r)
013f6a5d 5699 goto out_free_percpu;
97db56ce 5700
ce88decf 5701 kvm_set_mmio_spte_mask();
97db56ce 5702
f8c16bba 5703 kvm_x86_ops = ops;
920c8377
PB		 5704 kvm_init_msr_list();
5705
7b52345e 5706 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5707 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5708
b820cc0c 5709 kvm_timer_init();
c8076604 5710
ff9d07a0
ZY		 5711 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5712
2acf923e
DC		 5713 if (cpu_has_xsave)
5714 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5715
c5cc421b 5716 kvm_lapic_init();
16e8d74d
MT		 5717#ifdef CONFIG_X86_64
5718 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5719#endif
5720
f8c16bba 5721 return 0;
56c6d28a 5722
013f6a5d
MT		 5723out_free_percpu:
5724 free_percpu(shared_msrs);
56c6d28a 5725out:
56c6d28a 5726 return r;
043405e1 5727}
8776e519 5728
f8c16bba
ZX		 5729void kvm_arch_exit(void)
5730{
ff9d07a0
ZY		 5731 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5732
888d256e
JK		 5733 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5734 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5735 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5736 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5737#ifdef CONFIG_X86_64
5738 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5739#endif
f8c16bba 5740 kvm_x86_ops = NULL;
56c6d28a 5741 kvm_mmu_module_exit();
013f6a5d 5742 free_percpu(shared_msrs);
56c6d28a 5743}
f8c16bba 5744
8776e519
HB		 5745int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5746{
5747 ++vcpu->stat.halt_exits;
5748 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5749 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5750 return 1;
5751 } else {
5752 vcpu->run->exit_reason = KVM_EXIT_HLT;
5753 return 0;
5754 }
5755}
5756EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5757
55cd8e5a
GN		 5758int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5759{
5760 u64 param, ingpa, outgpa, ret;
5761 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5762 bool fast, longmode;
55cd8e5a
GN		 5763
5764 /*
5765 * hypercall generates UD from non zero cpl and real mode
5766 * per HYPER-V spec
5767 */
3eeb3288 5768 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5769 kvm_queue_exception(vcpu, UD_VECTOR);
5770 return 0;
5771 }
5772
a449c7aa 5773 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5774
5775 if (!longmode) {
ccd46936
GN		 5776 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5777 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5778 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5779 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5780 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5781 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5782 }
5783#ifdef CONFIG_X86_64
5784 else {
5785 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5786 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5787 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5788 }
5789#endif
5790
5791 code = param & 0xffff;
5792 fast = (param >> 16) & 0x1;
5793 rep_cnt = (param >> 32) & 0xfff;
5794 rep_idx = (param >> 48) & 0xfff;
5795
5796 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5797
c25bc163
GN		 5798 switch (code) {
5799 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5800 kvm_vcpu_on_spin(vcpu);
5801 break;
5802 default:
5803 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5804 break;
5805 }
55cd8e5a
GN		 5806
5807 ret = res | (((u64)rep_done & 0xfff) << 32);
5808 if (longmode) {
5809 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5810 } else {
5811 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5812 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5813 }
5814
5815 return 1;
5816}
5817
6aef266c
SV		 5818/*
5819 * kvm_pv_kick_cpu_op: Kick a vcpu.
5820 *
5821 * @apicid - apicid of vcpu to be kicked.
5822 */
5823static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5824{
24d2166b 5825 struct kvm_lapic_irq lapic_irq;
6aef266c 5826
24d2166b
R		 5827 lapic_irq.shorthand = 0;
5828 lapic_irq.dest_mode = 0;
5829 lapic_irq.dest_id = apicid;
6aef266c 5830
24d2166b
R		 5831 lapic_irq.delivery_mode = APIC_DM_REMRD;
5832 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5833}
5834
8776e519
HB		 5835int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5836{
5837 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5838 int op_64_bit, r = 1;
8776e519 5839
55cd8e5a
GN		 5840 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5841 return kvm_hv_hypercall(vcpu);
5842
5fdbf976
MT		 5843 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5844 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5845 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5846 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5847 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5848
229456fc 5849 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5850
a449c7aa
NA		 5851 op_64_bit = is_64_bit_mode(vcpu);
5852 if (!op_64_bit) {
8776e519
HB		 5853 nr &= 0xFFFFFFFF;
5854 a0 &= 0xFFFFFFFF;
5855 a1 &= 0xFFFFFFFF;
5856 a2 &= 0xFFFFFFFF;
5857 a3 &= 0xFFFFFFFF;
5858 }
5859
07708c4a
JK		 5860 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5861 ret = -KVM_EPERM;
5862 goto out;
5863 }
5864
8776e519 5865 switch (nr) {
b93463aa
AK		 5866 case KVM_HC_VAPIC_POLL_IRQ:
5867 ret = 0;
5868 break;
6aef266c
SV		 5869 case KVM_HC_KICK_CPU:
5870 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5871 ret = 0;
5872 break;
8776e519
HB		 5873 default:
5874 ret = -KVM_ENOSYS;
5875 break;
5876 }
07708c4a 5877out:
a449c7aa
NA		 5878 if (!op_64_bit)
5879 ret = (u32)ret;
5fdbf976 5880 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5881 ++vcpu->stat.hypercalls;
2f333bcb 5882 return r;
8776e519
HB		 5883}
5884EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5885
b6785def 5886static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5887{
d6aa1000 5888 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5889 char instruction[3];
5fdbf976 5890 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5891
8776e519 5892 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5893
9d74191a 5894 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5895}
5896
b6c7a5dc
HB		 5897/*
5898 * Check if userspace requested an interrupt window, and that the
5899 * interrupt window is open.
5900 *
5901 * No need to exit to userspace if we already have an interrupt queued.
5902 */
851ba692 5903static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5904{
8061823a 5905 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5906 vcpu->run->request_interrupt_window &&
5df56646 5907 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5908}
5909
851ba692 5910static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5911{
851ba692
AK		 5912 struct kvm_run *kvm_run = vcpu->run;
5913
91586a3b 5914 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5915 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5916 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5917 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5918 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5919 else
b6c7a5dc 5920 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5921 kvm_arch_interrupt_allowed(vcpu) &&
5922 !kvm_cpu_has_interrupt(vcpu) &&
5923 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5924}
5925
95ba8273
GN		 5926static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5927{
5928 int max_irr, tpr;
5929
5930 if (!kvm_x86_ops->update_cr8_intercept)
5931 return;
5932
88c808fd
AK		 5933 if (!vcpu->arch.apic)
5934 return;
5935
8db3baa2
GN		 5936 if (!vcpu->arch.apic->vapic_addr)
5937 max_irr = kvm_lapic_find_highest_irr(vcpu);
5938 else
5939 max_irr = -1;
95ba8273
GN		 5940
5941 if (max_irr != -1)
5942 max_irr >>= 4;
5943
5944 tpr = kvm_lapic_get_cr8(vcpu);
5945
5946 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5947}
5948
b6b8a145 5949static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5950{
b6b8a145
JK		 5951 int r;
5952
95ba8273 5953 /* try to reinject previous events if any */
b59bb7bd 5954 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5955 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5956 vcpu->arch.exception.has_error_code,
5957 vcpu->arch.exception.error_code);
d6e8c854
NA		 5958
5959 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5960 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5961 X86_EFLAGS_RF);
5962
b59bb7bd
GN		 5963 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5964 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5965 vcpu->arch.exception.error_code,
5966 vcpu->arch.exception.reinject);
b6b8a145 5967 return 0;
b59bb7bd
GN		 5968 }
5969
95ba8273
GN		 5970 if (vcpu->arch.nmi_injected) {
5971 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5972 return 0;
95ba8273
GN		 5973 }
5974
5975 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5976 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5977 return 0;
5978 }
5979
5980 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5981 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5982 if (r != 0)
5983 return r;
95ba8273
GN		 5984 }
5985
5986 /* try to inject new event if pending */
5987 if (vcpu->arch.nmi_pending) {
5988 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5989 --vcpu->arch.nmi_pending;
95ba8273
GN		 5990 vcpu->arch.nmi_injected = true;
5991 kvm_x86_ops->set_nmi(vcpu);
5992 }
c7c9c56c 5993 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5994 /*
5995 * Because interrupts can be injected asynchronously, we are
5996 * calling check_nested_events again here to avoid a race condition.
5997 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5998 * proposal and current concerns. Perhaps we should be setting
5999 * KVM_REQ_EVENT only on certain events and not unconditionally?
6000 */
6001 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6002 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6003 if (r != 0)
6004 return r;
6005 }
95ba8273 6006 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6007 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6008 false);
6009 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6010 }
6011 }
b6b8a145 6012 return 0;
95ba8273
GN		 6013}
6014
7460fb4a
AK		 6015static void process_nmi(struct kvm_vcpu *vcpu)
6016{
6017 unsigned limit = 2;
6018
6019 /*
6020 * x86 is limited to one NMI running, and one NMI pending after it.
6021 * If an NMI is already in progress, limit further NMIs to just one.
6022 * Otherwise, allow two (and we'll inject the first one immediately).
6023 */
6024 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6025 limit = 1;
6026
6027 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6028 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6029 kvm_make_request(KVM_REQ_EVENT, vcpu);
6030}
6031
3d81bc7e 6032static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6033{
6034 u64 eoi_exit_bitmap[4];
cf9e65b7 6035 u32 tmr[8];
c7c9c56c 6036
3d81bc7e
YZ		 6037 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6038 return;
c7c9c56c
YZ		 6039
6040 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6041 memset(tmr, 0, 32);
c7c9c56c 6042
cf9e65b7 6043 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6044 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6045 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6046}
6047
a70656b6
RK		 6048static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6049{
6050 ++vcpu->stat.tlb_flush;
6051 kvm_x86_ops->tlb_flush(vcpu);
6052}
6053
4256f43f
TC		 6054void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6055{
c24ae0dc
TC		 6056 struct page *page = NULL;
6057
f439ed27
PB		 6058 if (!irqchip_in_kernel(vcpu->kvm))
6059 return;
6060
4256f43f
TC		 6061 if (!kvm_x86_ops->set_apic_access_page_addr)
6062 return;
6063
c24ae0dc
TC		 6064 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6065 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6066
6067 /*
6068 * Do not pin apic access page in memory, the MMU notifier
6069 * will call us again if it is migrated or swapped out.
6070 */
6071 put_page(page);
4256f43f
TC		 6072}
6073EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6074
fe71557a
TC		 6075void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6076 unsigned long address)
6077{
c24ae0dc
TC		 6078 /*
6079 * The physical address of apic access page is stored in the VMCS.
6080 * Update it when it becomes invalid.
6081 */
6082 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6083 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6084}
6085
9357d939
TY		 6086/*
6087 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6088 * exiting to the userspace. Otherwise, the value will be returned to the
6089 * userspace.
6090 */
851ba692 6091static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6092{
6093 int r;
6a8b1d13 6094 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6095 vcpu->run->request_interrupt_window;
730dca42 6096 bool req_immediate_exit = false;
b6c7a5dc 6097
3e007509 6098 if (vcpu->requests) {
a8eeb04a 6099 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6100 kvm_mmu_unload(vcpu);
a8eeb04a 6101 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6102 __kvm_migrate_timers(vcpu);
d828199e
MT		 6103 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6104 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6105 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6106 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6107 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6108 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6109 if (unlikely(r))
6110 goto out;
6111 }
a8eeb04a 6112 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6113 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6114 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6115 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6116 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6117 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6118 r = 0;
6119 goto out;
6120 }
a8eeb04a 6121 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6122 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6123 r = 0;
6124 goto out;
6125 }
a8eeb04a 6126 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6127 vcpu->fpu_active = 0;
6128 kvm_x86_ops->fpu_deactivate(vcpu);
6129 }
af585b92
GN		 6130 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6131 /* Page is swapped out. Do synthetic halt */
6132 vcpu->arch.apf.halted = true;
6133 r = 1;
6134 goto out;
6135 }
c9aaa895
GC		 6136 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6137 record_steal_time(vcpu);
7460fb4a
AK		 6138 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6139 process_nmi(vcpu);
f5132b01
GN		 6140 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6141 kvm_handle_pmu_event(vcpu);
6142 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6143 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6144 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6145 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6146 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6147 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6148 }
b93463aa 6149
b463a6f7 6150 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6151 kvm_apic_accept_events(vcpu);
6152 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6153 r = 1;
6154 goto out;
6155 }
6156
b6b8a145
JK		 6157 if (inject_pending_event(vcpu, req_int_win) != 0)
6158 req_immediate_exit = true;
b463a6f7 6159 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6160 else if (vcpu->arch.nmi_pending)
c9a7953f 6161 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6162 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6163 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6164
6165 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6166 /*
6167 * Update architecture specific hints for APIC
6168 * virtual interrupt delivery.
6169 */
6170 if (kvm_x86_ops->hwapic_irr_update)
6171 kvm_x86_ops->hwapic_irr_update(vcpu,
6172 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6173 update_cr8_intercept(vcpu);
6174 kvm_lapic_sync_to_vapic(vcpu);
6175 }
6176 }
6177
d8368af8
AK		 6178 r = kvm_mmu_reload(vcpu);
6179 if (unlikely(r)) {
d905c069 6180 goto cancel_injection;
d8368af8
AK		 6181 }
6182
b6c7a5dc
HB		 6183 preempt_disable();
6184
6185 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6186 if (vcpu->fpu_active)
6187 kvm_load_guest_fpu(vcpu);
2acf923e 6188 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6189
6b7e2d09
XG		 6190 vcpu->mode = IN_GUEST_MODE;
6191
01b71917
MT		 6192 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6193
6b7e2d09
XG		 6194 /* We should set ->mode before check ->requests,
6195 * see the comment in make_all_cpus_request.
6196 */
01b71917 6197 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6198
d94e1dc9 6199 local_irq_disable();
32f88400 6200
6b7e2d09 6201 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6202 || need_resched() || signal_pending(current)) {
6b7e2d09 6203 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6204 smp_wmb();
6c142801
AK		 6205 local_irq_enable();
6206 preempt_enable();
01b71917 6207 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6208 r = 1;
d905c069 6209 goto cancel_injection;
6c142801
AK		 6210 }
6211
d6185f20
NHE		 6212 if (req_immediate_exit)
6213 smp_send_reschedule(vcpu->cpu);
6214
b6c7a5dc
HB		 6215 kvm_guest_enter();
6216
42dbaa5a 6217 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6218 set_debugreg(0, 7);
6219 set_debugreg(vcpu->arch.eff_db[0], 0);
6220 set_debugreg(vcpu->arch.eff_db[1], 1);
6221 set_debugreg(vcpu->arch.eff_db[2], 2);
6222 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6223 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6224 }
b6c7a5dc 6225
229456fc 6226 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6227 kvm_x86_ops->run(vcpu);
b6c7a5dc 6228
c77fb5fe
PB		 6229 /*
6230 * Do this here before restoring debug registers on the host. And
6231 * since we do this before handling the vmexit, a DR access vmexit
6232 * can (a) read the correct value of the debug registers, (b) set
6233 * KVM_DEBUGREG_WONT_EXIT again.
6234 */
6235 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6236 int i;
6237
6238 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6239 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6240 for (i = 0; i < KVM_NR_DB_REGS; i++)
6241 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6242 }
6243
24f1e32c
FW		 6244 /*
6245 * If the guest has used debug registers, at least dr7
6246 * will be disabled while returning to the host.
6247 * If we don't have active breakpoints in the host, we don't
6248 * care about the messed up debug address registers. But if
6249 * we have some of them active, restore the old state.
6250 */
59d8eb53 6251 if (hw_breakpoint_active())
24f1e32c 6252 hw_breakpoint_restore();
42dbaa5a 6253
886b470c
MT		 6254 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6255 native_read_tsc());
1d5f066e 6256
6b7e2d09 6257 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6258 smp_wmb();
a547c6db
YZ		 6259
6260 /* Interrupt is enabled by handle_external_intr() */
6261 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6262
6263 ++vcpu->stat.exits;
6264
6265 /*
6266 * We must have an instruction between local_irq_enable() and
6267 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6268 * the interrupt shadow. The stat.exits increment will do nicely.
6269 * But we need to prevent reordering, hence this barrier():
6270 */
6271 barrier();
6272
6273 kvm_guest_exit();
6274
6275 preempt_enable();
6276
f656ce01 6277 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6278
b6c7a5dc
HB		 6279 /*
6280 * Profile KVM exit RIPs:
6281 */
6282 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6283 unsigned long rip = kvm_rip_read(vcpu);
6284 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6285 }
6286
cc578287
ZA		 6287 if (unlikely(vcpu->arch.tsc_always_catchup))
6288 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6289
5cfb1d5a
MT		 6290 if (vcpu->arch.apic_attention)
6291 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6292
851ba692 6293 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6294 return r;
6295
6296cancel_injection:
6297 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6298 if (unlikely(vcpu->arch.apic_attention))
6299 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6300out:
6301 return r;
6302}
b6c7a5dc 6303
09cec754 6304
851ba692 6305static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6306{
6307 int r;
f656ce01 6308 struct kvm *kvm = vcpu->kvm;
d7690175 6309
f656ce01 6310 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6311
6312 r = 1;
6313 while (r > 0) {
af585b92
GN		 6314 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6315 !vcpu->arch.apf.halted)
851ba692 6316 r = vcpu_enter_guest(vcpu);
d7690175 6317 else {
f656ce01 6318 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6319 kvm_vcpu_block(vcpu);
f656ce01 6320 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6321 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6322 kvm_apic_accept_events(vcpu);
09cec754
GN		 6323 switch(vcpu->arch.mp_state) {
6324 case KVM_MP_STATE_HALTED:
6aef266c 6325 vcpu->arch.pv.pv_unhalted = false;
d7690175 6326 vcpu->arch.mp_state =
09cec754
GN		 6327 KVM_MP_STATE_RUNNABLE;
6328 case KVM_MP_STATE_RUNNABLE:
af585b92 6329 vcpu->arch.apf.halted = false;
09cec754 6330 break;
66450a21
JK		 6331 case KVM_MP_STATE_INIT_RECEIVED:
6332 break;
09cec754
GN		 6333 default:
6334 r = -EINTR;
6335 break;
6336 }
6337 }
d7690175
MT		 6338 }
6339
09cec754
GN		 6340 if (r <= 0)
6341 break;
6342
6343 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6344 if (kvm_cpu_has_pending_timer(vcpu))
6345 kvm_inject_pending_timer_irqs(vcpu);
6346
851ba692 6347 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6348 r = -EINTR;
851ba692 6349 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6350 ++vcpu->stat.request_irq_exits;
6351 }
af585b92
GN		 6352
6353 kvm_check_async_pf_completion(vcpu);
6354
09cec754
GN		 6355 if (signal_pending(current)) {
6356 r = -EINTR;
851ba692 6357 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6358 ++vcpu->stat.signal_exits;
6359 }
6360 if (need_resched()) {
f656ce01 6361 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6362 cond_resched();
f656ce01 6363 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6364 }
b6c7a5dc
HB		 6365 }
6366
f656ce01 6367 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6368
6369 return r;
6370}
6371
716d51ab
GN		 6372static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6373{
6374 int r;
6375 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6376 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6377 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6378 if (r != EMULATE_DONE)
6379 return 0;
6380 return 1;
6381}
6382
6383static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6384{
6385 BUG_ON(!vcpu->arch.pio.count);
6386
6387 return complete_emulated_io(vcpu);
6388}
6389
f78146b0
AK		 6390/*
6391 * Implements the following, as a state machine:
6392 *
6393 * read:
6394 * for each fragment
87da7e66
XG		 6395 * for each mmio piece in the fragment
6396 * write gpa, len
6397 * exit
6398 * copy data
f78146b0
AK		 6399 * execute insn
6400 *
6401 * write:
6402 * for each fragment
87da7e66
XG		 6403 * for each mmio piece in the fragment
6404 * write gpa, len
6405 * copy data
6406 * exit
f78146b0 6407 */
716d51ab 6408static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6409{
6410 struct kvm_run *run = vcpu->run;
f78146b0 6411 struct kvm_mmio_fragment *frag;
87da7e66 6412 unsigned len;
5287f194 6413
716d51ab 6414 BUG_ON(!vcpu->mmio_needed);
5287f194 6415
716d51ab 6416 /* Complete previous fragment */
87da7e66
XG		 6417 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6418 len = min(8u, frag->len);
716d51ab 6419 if (!vcpu->mmio_is_write)
87da7e66
XG		 6420 memcpy(frag->data, run->mmio.data, len);
6421
6422 if (frag->len <= 8) {
6423 /* Switch to the next fragment. */
6424 frag++;
6425 vcpu->mmio_cur_fragment++;
6426 } else {
6427 /* Go forward to the next mmio piece. */
6428 frag->data += len;
6429 frag->gpa += len;
6430 frag->len -= len;
6431 }
6432
a08d3b3b 6433 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6434 vcpu->mmio_needed = 0;
0912c977
PB		 6435
6436 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6437 if (vcpu->mmio_is_write)
716d51ab
GN		 6438 return 1;
6439 vcpu->mmio_read_completed = 1;
6440 return complete_emulated_io(vcpu);
6441 }
87da7e66 6442
716d51ab
GN		 6443 run->exit_reason = KVM_EXIT_MMIO;
6444 run->mmio.phys_addr = frag->gpa;
6445 if (vcpu->mmio_is_write)
87da7e66
XG		 6446 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6447 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6448 run->mmio.is_write = vcpu->mmio_is_write;
6449 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6450 return 0;
5287f194
AK		 6451}
6452
716d51ab 6453
b6c7a5dc
HB		 6454int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6455{
6456 int r;
6457 sigset_t sigsaved;
6458
e5c30142
AK		 6459 if (!tsk_used_math(current) && init_fpu(current))
6460 return -ENOMEM;
6461
ac9f6dc0
AK		 6462 if (vcpu->sigset_active)
6463 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6464
a4535290 6465 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6466 kvm_vcpu_block(vcpu);
66450a21 6467 kvm_apic_accept_events(vcpu);
d7690175 6468 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6469 r = -EAGAIN;
6470 goto out;
b6c7a5dc
HB		 6471 }
6472
b6c7a5dc 6473 /* re-sync apic's tpr */
eea1cff9
AP		 6474 if (!irqchip_in_kernel(vcpu->kvm)) {
6475 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6476 r = -EINVAL;
6477 goto out;
6478 }
6479 }
b6c7a5dc 6480
716d51ab
GN		 6481 if (unlikely(vcpu->arch.complete_userspace_io)) {
6482 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6483 vcpu->arch.complete_userspace_io = NULL;
6484 r = cui(vcpu);
6485 if (r <= 0)
6486 goto out;
6487 } else
6488 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6489
851ba692 6490 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6491
6492out:
f1d86e46 6493 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6494 if (vcpu->sigset_active)
6495 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6496
b6c7a5dc
HB		 6497 return r;
6498}
6499
6500int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6501{
7ae441ea
GN		 6502 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6503 /*
6504 * We are here if userspace calls get_regs() in the middle of
6505 * instruction emulation. Registers state needs to be copied
4a969980 6506 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6507 * that usually, but some bad designed PV devices (vmware
6508 * backdoor interface) need this to work
6509 */
dd856efa 6510 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6511 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6512 }
5fdbf976
MT		 6513 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6514 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6515 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6516 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6517 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6518 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6519 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6520 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6521#ifdef CONFIG_X86_64
5fdbf976
MT		 6522 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6523 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6524 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6525 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6526 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6527 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6528 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6529 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6530#endif
6531
5fdbf976 6532 regs->rip = kvm_rip_read(vcpu);
91586a3b 6533 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6534
b6c7a5dc
HB		 6535 return 0;
6536}
6537
6538int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6539{
7ae441ea
GN		 6540 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6541 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6542
5fdbf976
MT		 6543 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6544 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6545 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6546 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6547 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6548 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6549 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6550 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6551#ifdef CONFIG_X86_64
5fdbf976
MT		 6552 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6553 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6554 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6555 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6556 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6557 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6558 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6559 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6560#endif
6561
5fdbf976 6562 kvm_rip_write(vcpu, regs->rip);
91586a3b 6563 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6564
b4f14abd
JK		 6565 vcpu->arch.exception.pending = false;
6566
3842d135
AK		 6567 kvm_make_request(KVM_REQ_EVENT, vcpu);
6568
b6c7a5dc
HB		 6569 return 0;
6570}
6571
b6c7a5dc
HB		 6572void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6573{
6574 struct kvm_segment cs;
6575
3e6e0aab 6576 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6577 *db = cs.db;
6578 *l = cs.l;
6579}
6580EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6581
6582int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6583 struct kvm_sregs *sregs)
6584{
89a27f4d 6585 struct desc_ptr dt;
b6c7a5dc 6586
3e6e0aab
GT		 6587 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6588 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6589 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6590 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6591 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6592 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6593
3e6e0aab
GT		 6594 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6595 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6596
6597 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6598 sregs->idt.limit = dt.size;
6599 sregs->idt.base = dt.address;
b6c7a5dc 6600 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6601 sregs->gdt.limit = dt.size;
6602 sregs->gdt.base = dt.address;
b6c7a5dc 6603
4d4ec087 6604 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6605 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6606 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6607 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6608 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6609 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6610 sregs->apic_base = kvm_get_apic_base(vcpu);
6611
923c61bb 6612 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6613
36752c9b 6614 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6615 set_bit(vcpu->arch.interrupt.nr,
6616 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6617
b6c7a5dc
HB		 6618 return 0;
6619}
6620
62d9f0db
MT		 6621int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6622 struct kvm_mp_state *mp_state)
6623{
66450a21 6624 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6625 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6626 vcpu->arch.pv.pv_unhalted)
6627 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6628 else
6629 mp_state->mp_state = vcpu->arch.mp_state;
6630
62d9f0db
MT		 6631 return 0;
6632}
6633
6634int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6635 struct kvm_mp_state *mp_state)
6636{
66450a21
JK		 6637 if (!kvm_vcpu_has_lapic(vcpu) &&
6638 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6639 return -EINVAL;
6640
6641 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6642 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6643 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6644 } else
6645 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6646 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6647 return 0;
6648}
6649
7f3d35fd
KW		 6650int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6651 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6652{
9d74191a 6653 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6654 int ret;
e01c2426 6655
8ec4722d 6656 init_emulate_ctxt(vcpu);
c697518a 6657
7f3d35fd 6658 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6659 has_error_code, error_code);
c697518a 6660
c697518a 6661 if (ret)
19d04437 6662 return EMULATE_FAIL;
37817f29 6663
9d74191a
TY		 6664 kvm_rip_write(vcpu, ctxt->eip);
6665 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6666 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6667 return EMULATE_DONE;
37817f29
IE		 6668}
6669EXPORT_SYMBOL_GPL(kvm_task_switch);
6670
b6c7a5dc
HB		 6671int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6672 struct kvm_sregs *sregs)
6673{
58cb628d 6674 struct msr_data apic_base_msr;
b6c7a5dc 6675 int mmu_reset_needed = 0;
63f42e02 6676 int pending_vec, max_bits, idx;
89a27f4d 6677 struct desc_ptr dt;
b6c7a5dc 6678
6d1068b3
PM		 6679 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6680 return -EINVAL;
6681
89a27f4d
GN		 6682 dt.size = sregs->idt.limit;
6683 dt.address = sregs->idt.base;
b6c7a5dc 6684 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6685 dt.size = sregs->gdt.limit;
6686 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6687 kvm_x86_ops->set_gdt(vcpu, &dt);
6688
ad312c7c 6689 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6690 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6691 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6692 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6693
2d3ad1f4 6694 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6695
f6801dff 6696 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6697 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6698 apic_base_msr.data = sregs->apic_base;
6699 apic_base_msr.host_initiated = true;
6700 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6701
4d4ec087 6702 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6703 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6704 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6705
fc78f519 6706 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6707 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6708 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6709 kvm_update_cpuid(vcpu);
63f42e02
XG		 6710
6711 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6712 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6713 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6714 mmu_reset_needed = 1;
6715 }
63f42e02 6716 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6717
6718 if (mmu_reset_needed)
6719 kvm_mmu_reset_context(vcpu);
6720
a50abc3b 6721 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6722 pending_vec = find_first_bit(
6723 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6724 if (pending_vec < max_bits) {
66fd3f7f 6725 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6726 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6727 }
6728
3e6e0aab
GT		 6729 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6730 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6731 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6732 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6733 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6734 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6735
3e6e0aab
GT		 6736 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6737 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6738
5f0269f5
ME		 6739 update_cr8_intercept(vcpu);
6740
9c3e4aab 6741 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6742 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6743 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6744 !is_protmode(vcpu))
9c3e4aab
MT		 6745 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6746
3842d135
AK		 6747 kvm_make_request(KVM_REQ_EVENT, vcpu);
6748
b6c7a5dc
HB		 6749 return 0;
6750}
6751
d0bfb940
JK		 6752int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6753 struct kvm_guest_debug *dbg)
b6c7a5dc 6754{
355be0b9 6755 unsigned long rflags;
ae675ef0 6756 int i, r;
b6c7a5dc 6757
4f926bf2
JK		 6758 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6759 r = -EBUSY;
6760 if (vcpu->arch.exception.pending)
2122ff5e 6761 goto out;
4f926bf2
JK		 6762 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6763 kvm_queue_exception(vcpu, DB_VECTOR);
6764 else
6765 kvm_queue_exception(vcpu, BP_VECTOR);
6766 }
6767
91586a3b
JK		 6768 /*
6769 * Read rflags as long as potentially injected trace flags are still
6770 * filtered out.
6771 */
6772 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6773
6774 vcpu->guest_debug = dbg->control;
6775 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6776 vcpu->guest_debug = 0;
6777
6778 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6779 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6780 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6781 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6782 } else {
6783 for (i = 0; i < KVM_NR_DB_REGS; i++)
6784 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6785 }
c8639010 6786 kvm_update_dr7(vcpu);
ae675ef0 6787
f92653ee
JK		 6788 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6789 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6790 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6791
91586a3b
JK		 6792 /*
6793 * Trigger an rflags update that will inject or remove the trace
6794 * flags.
6795 */
6796 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6797
c8639010 6798 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6799
4f926bf2 6800 r = 0;
d0bfb940 6801
2122ff5e 6802out:
b6c7a5dc
HB		 6803
6804 return r;
6805}
6806
8b006791
ZX		 6807/*
6808 * Translate a guest virtual address to a guest physical address.
6809 */
6810int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6811 struct kvm_translation *tr)
6812{
6813 unsigned long vaddr = tr->linear_address;
6814 gpa_t gpa;
f656ce01 6815 int idx;
8b006791 6816
f656ce01 6817 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6818 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6819 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6820 tr->physical_address = gpa;
6821 tr->valid = gpa != UNMAPPED_GVA;
6822 tr->writeable = 1;
6823 tr->usermode = 0;
8b006791
ZX		 6824
6825 return 0;
6826}
6827
d0752060
HB		 6828int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6829{
98918833
SY		 6830 struct i387_fxsave_struct *fxsave =
6831 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6832
d0752060
HB		 6833 memcpy(fpu->fpr, fxsave->st_space, 128);
6834 fpu->fcw = fxsave->cwd;
6835 fpu->fsw = fxsave->swd;
6836 fpu->ftwx = fxsave->twd;
6837 fpu->last_opcode = fxsave->fop;
6838 fpu->last_ip = fxsave->rip;
6839 fpu->last_dp = fxsave->rdp;
6840 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6841
d0752060
HB		 6842 return 0;
6843}
6844
6845int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6846{
98918833
SY		 6847 struct i387_fxsave_struct *fxsave =
6848 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6849
d0752060
HB		 6850 memcpy(fxsave->st_space, fpu->fpr, 128);
6851 fxsave->cwd = fpu->fcw;
6852 fxsave->swd = fpu->fsw;
6853 fxsave->twd = fpu->ftwx;
6854 fxsave->fop = fpu->last_opcode;
6855 fxsave->rip = fpu->last_ip;
6856 fxsave->rdp = fpu->last_dp;
6857 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6858
d0752060
HB		 6859 return 0;
6860}
6861
10ab25cd 6862int fx_init(struct kvm_vcpu *vcpu)
d0752060 6863{
10ab25cd
JK		 6864 int err;
6865
6866 err = fpu_alloc(&vcpu->arch.guest_fpu);
6867 if (err)
6868 return err;
6869
98918833 6870 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6871
2acf923e
DC		 6872 /*
6873 * Ensure guest xcr0 is valid for loading
6874 */
6875 vcpu->arch.xcr0 = XSTATE_FP;
6876
ad312c7c 6877 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6878
6879 return 0;
d0752060
HB		 6880}
6881EXPORT_SYMBOL_GPL(fx_init);
6882
98918833
SY		 6883static void fx_free(struct kvm_vcpu *vcpu)
6884{
6885 fpu_free(&vcpu->arch.guest_fpu);
6886}
6887
d0752060
HB		 6888void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6889{
2608d7a1 6890 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6891 return;
6892
2acf923e
DC		 6893 /*
6894 * Restore all possible states in the guest,
6895 * and assume host would use all available bits.
6896 * Guest xcr0 would be loaded later.
6897 */
6898 kvm_put_guest_xcr0(vcpu);
d0752060 6899 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6900 __kernel_fpu_begin();
98918833 6901 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6902 trace_kvm_fpu(1);
d0752060 6903}
d0752060
HB		 6904
6905void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6906{
2acf923e
DC		 6907 kvm_put_guest_xcr0(vcpu);
6908
d0752060
HB		 6909 if (!vcpu->guest_fpu_loaded)
6910 return;
6911
6912 vcpu->guest_fpu_loaded = 0;
98918833 6913 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6914 __kernel_fpu_end();
f096ed85 6915 ++vcpu->stat.fpu_reload;
a8eeb04a 6916 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6917 trace_kvm_fpu(0);
d0752060 6918}
e9b11c17
ZX		 6919
6920void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6921{
12f9a48f 6922 kvmclock_reset(vcpu);
7f1ea208 6923
f5f48ee1 6924 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6925 fx_free(vcpu);
e9b11c17
ZX		 6926 kvm_x86_ops->vcpu_free(vcpu);
6927}
6928
6929struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6930 unsigned int id)
6931{
6755bae8
ZA		 6932 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6933 printk_once(KERN_WARNING
6934 "kvm: SMP vm created on host with unstable TSC; "
6935 "guest TSC will not be reliable\n");
26e5215f
AK		 6936 return kvm_x86_ops->vcpu_create(kvm, id);
6937}
e9b11c17 6938
26e5215f
AK		 6939int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6940{
6941 int r;
e9b11c17 6942
0bed3b56 6943 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6944 r = vcpu_load(vcpu);
6945 if (r)
6946 return r;
57f252f2 6947 kvm_vcpu_reset(vcpu);
8a3c1a33 6948 kvm_mmu_setup(vcpu);
e9b11c17 6949 vcpu_put(vcpu);
e9b11c17 6950
26e5215f 6951 return r;
e9b11c17
ZX		 6952}
6953
42897d86
MT		 6954int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6955{
6956 int r;
8fe8ab46 6957 struct msr_data msr;
332967a3 6958 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6959
6960 r = vcpu_load(vcpu);
6961 if (r)
6962 return r;
8fe8ab46
WA		 6963 msr.data = 0x0;
6964 msr.index = MSR_IA32_TSC;
6965 msr.host_initiated = true;
6966 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6967 vcpu_put(vcpu);
6968
332967a3
AJ		 6969 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6970 KVMCLOCK_SYNC_PERIOD);
6971
42897d86
MT		 6972 return r;
6973}
6974
d40ccc62 6975void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6976{
9fc77441 6977 int r;
344d9588
GN		 6978 vcpu->arch.apf.msr_val = 0;
6979
9fc77441
MT		 6980 r = vcpu_load(vcpu);
6981 BUG_ON(r);
e9b11c17
ZX		 6982 kvm_mmu_unload(vcpu);
6983 vcpu_put(vcpu);
6984
98918833 6985 fx_free(vcpu);
e9b11c17
ZX		 6986 kvm_x86_ops->vcpu_free(vcpu);
6987}
6988
66450a21 6989void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6990{
7460fb4a
AK		 6991 atomic_set(&vcpu->arch.nmi_queued, 0);
6992 vcpu->arch.nmi_pending = 0;
448fa4a9 6993 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 6994 kvm_clear_interrupt_queue(vcpu);
6995 kvm_clear_exception_queue(vcpu);
448fa4a9 6996
42dbaa5a 6997 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6f43ed01 6998 vcpu->arch.dr6 = DR6_INIT;
73aaf249 6999 kvm_update_dr6(vcpu);
42dbaa5a 7000 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7001 kvm_update_dr7(vcpu);
42dbaa5a 7002
3842d135 7003 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7004 vcpu->arch.apf.msr_val = 0;
c9aaa895 7005 vcpu->arch.st.msr_val = 0;
3842d135 7006
12f9a48f
GC		 7007 kvmclock_reset(vcpu);
7008
af585b92
GN		 7009 kvm_clear_async_pf_completion_queue(vcpu);
7010 kvm_async_pf_hash_reset(vcpu);
7011 vcpu->arch.apf.halted = false;
3842d135 7012
f5132b01
GN		 7013 kvm_pmu_reset(vcpu);
7014
66f7b72e
JS		 7015 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7016 vcpu->arch.regs_avail = ~0;
7017 vcpu->arch.regs_dirty = ~0;
7018
57f252f2 7019 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 7020}
7021
66450a21
JK		 7022void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
7023{
7024 struct kvm_segment cs;
7025
7026 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7027 cs.selector = vector << 8;
7028 cs.base = vector << 12;
7029 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7030 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7031}
7032
13a34e06 7033int kvm_arch_hardware_enable(void)
e9b11c17 7034{
ca84d1a2
ZA		 7035 struct kvm *kvm;
7036 struct kvm_vcpu *vcpu;
7037 int i;
0dd6a6ed
ZA		 7038 int ret;
7039 u64 local_tsc;
7040 u64 max_tsc = 0;
7041 bool stable, backwards_tsc = false;
18863bdd
AK		 7042
7043 kvm_shared_msr_cpu_online();
13a34e06 7044 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7045 if (ret != 0)
7046 return ret;
7047
7048 local_tsc = native_read_tsc();
7049 stable = !check_tsc_unstable();
7050 list_for_each_entry(kvm, &vm_list, vm_list) {
7051 kvm_for_each_vcpu(i, vcpu, kvm) {
7052 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7053 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7054 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7055 backwards_tsc = true;
7056 if (vcpu->arch.last_host_tsc > max_tsc)
7057 max_tsc = vcpu->arch.last_host_tsc;
7058 }
7059 }
7060 }
7061
7062 /*
7063 * Sometimes, even reliable TSCs go backwards. This happens on
7064 * platforms that reset TSC during suspend or hibernate actions, but
7065 * maintain synchronization. We must compensate. Fortunately, we can
7066 * detect that condition here, which happens early in CPU bringup,
7067 * before any KVM threads can be running. Unfortunately, we can't
7068 * bring the TSCs fully up to date with real time, as we aren't yet far
7069 * enough into CPU bringup that we know how much real time has actually
7070 * elapsed; our helper function, get_kernel_ns() will be using boot
7071 * variables that haven't been updated yet.
7072 *
7073 * So we simply find the maximum observed TSC above, then record the
7074 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7075 * the adjustment will be applied. Note that we accumulate
7076 * adjustments, in case multiple suspend cycles happen before some VCPU
7077 * gets a chance to run again. In the event that no KVM threads get a
7078 * chance to run, we will miss the entire elapsed period, as we'll have
7079 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7080 * loose cycle time. This isn't too big a deal, since the loss will be
7081 * uniform across all VCPUs (not to mention the scenario is extremely
7082 * unlikely). It is possible that a second hibernate recovery happens
7083 * much faster than a first, causing the observed TSC here to be
7084 * smaller; this would require additional padding adjustment, which is
7085 * why we set last_host_tsc to the local tsc observed here.
7086 *
7087 * N.B. - this code below runs only on platforms with reliable TSC,
7088 * as that is the only way backwards_tsc is set above. Also note
7089 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7090 * have the same delta_cyc adjustment applied if backwards_tsc
7091 * is detected. Note further, this adjustment is only done once,
7092 * as we reset last_host_tsc on all VCPUs to stop this from being
7093 * called multiple times (one for each physical CPU bringup).
7094 *
4a969980 7095 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7096 * will be compensated by the logic in vcpu_load, which sets the TSC to
7097 * catchup mode. This will catchup all VCPUs to real time, but cannot
7098 * guarantee that they stay in perfect synchronization.
7099 */
7100 if (backwards_tsc) {
7101 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7102 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7103 list_for_each_entry(kvm, &vm_list, vm_list) {
7104 kvm_for_each_vcpu(i, vcpu, kvm) {
7105 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7106 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7107 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7108 }
7109
7110 /*
7111 * We have to disable TSC offset matching.. if you were
7112 * booting a VM while issuing an S4 host suspend....
7113 * you may have some problem. Solving this issue is
7114 * left as an exercise to the reader.
7115 */
7116 kvm->arch.last_tsc_nsec = 0;
7117 kvm->arch.last_tsc_write = 0;
7118 }
7119
7120 }
7121 return 0;
e9b11c17
ZX		 7122}
7123
13a34e06 7124void kvm_arch_hardware_disable(void)
e9b11c17 7125{
13a34e06
RK		 7126 kvm_x86_ops->hardware_disable();
7127 drop_user_return_notifiers();
e9b11c17
ZX		 7128}
7129
7130int kvm_arch_hardware_setup(void)
7131{
7132 return kvm_x86_ops->hardware_setup();
7133}
7134
7135void kvm_arch_hardware_unsetup(void)
7136{
7137 kvm_x86_ops->hardware_unsetup();
7138}
7139
7140void kvm_arch_check_processor_compat(void *rtn)
7141{
7142 kvm_x86_ops->check_processor_compatibility(rtn);
7143}
7144
3e515705
AK		 7145bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7146{
7147 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7148}
7149
54e9818f
GN		 7150struct static_key kvm_no_apic_vcpu __read_mostly;
7151
e9b11c17
ZX		 7152int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7153{
7154 struct page *page;
7155 struct kvm *kvm;
7156 int r;
7157
7158 BUG_ON(vcpu->kvm == NULL);
7159 kvm = vcpu->kvm;
7160
6aef266c 7161 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7162 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7163 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7164 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7165 else
a4535290 7166 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7167
7168 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7169 if (!page) {
7170 r = -ENOMEM;
7171 goto fail;
7172 }
ad312c7c 7173 vcpu->arch.pio_data = page_address(page);
e9b11c17 7174
cc578287 7175 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7176
e9b11c17
ZX		 7177 r = kvm_mmu_create(vcpu);
7178 if (r < 0)
7179 goto fail_free_pio_data;
7180
7181 if (irqchip_in_kernel(kvm)) {
7182 r = kvm_create_lapic(vcpu);
7183 if (r < 0)
7184 goto fail_mmu_destroy;
54e9818f
GN		 7185 } else
7186 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7187
890ca9ae
HY		 7188 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7189 GFP_KERNEL);
7190 if (!vcpu->arch.mce_banks) {
7191 r = -ENOMEM;
443c39bc 7192 goto fail_free_lapic;
890ca9ae
HY		 7193 }
7194 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7195
f1797359
WY		 7196 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7197 r = -ENOMEM;
f5f48ee1 7198 goto fail_free_mce_banks;
f1797359 7199 }
f5f48ee1 7200
66f7b72e
JS		 7201 r = fx_init(vcpu);
7202 if (r)
7203 goto fail_free_wbinvd_dirty_mask;
7204
ba904635 7205 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7206 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7207
7208 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7209 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7210
af585b92 7211 kvm_async_pf_hash_reset(vcpu);
f5132b01 7212 kvm_pmu_init(vcpu);
af585b92 7213
e9b11c17 7214 return 0;
66f7b72e
JS		 7215fail_free_wbinvd_dirty_mask:
7216 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7217fail_free_mce_banks:
7218 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7219fail_free_lapic:
7220 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7221fail_mmu_destroy:
7222 kvm_mmu_destroy(vcpu);
7223fail_free_pio_data:
ad312c7c 7224 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7225fail:
7226 return r;
7227}
7228
7229void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7230{
f656ce01
MT		 7231 int idx;
7232
f5132b01 7233 kvm_pmu_destroy(vcpu);
36cb93fd 7234 kfree(vcpu->arch.mce_banks);
e9b11c17 7235 kvm_free_lapic(vcpu);
f656ce01 7236 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7237 kvm_mmu_destroy(vcpu);
f656ce01 7238 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7239 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7240 if (!irqchip_in_kernel(vcpu->kvm))
7241 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7242}
d19a9cd2 7243
e790d9ef
RK		 7244void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7245{
ae97a3b8 7246 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7247}
7248
e08b9637 7249int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7250{
e08b9637
CO		 7251 if (type)
7252 return -EINVAL;
7253
f05e70ac 7254 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7255 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7256 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7257 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7258
5550af4d
SY		 7259 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7260 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7261 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7262 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7263 &kvm->arch.irq_sources_bitmap);
5550af4d 7264
038f8c11 7265 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7266 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7267 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7268
7269 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7270
7e44e449 7271 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7272 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7273
d89f5eff 7274 return 0;
d19a9cd2
ZX		 7275}
7276
7277static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7278{
9fc77441
MT		 7279 int r;
7280 r = vcpu_load(vcpu);
7281 BUG_ON(r);
d19a9cd2
ZX		 7282 kvm_mmu_unload(vcpu);
7283 vcpu_put(vcpu);
7284}
7285
7286static void kvm_free_vcpus(struct kvm *kvm)
7287{
7288 unsigned int i;
988a2cae 7289 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7290
7291 /*
7292 * Unpin any mmu pages first.
7293 */
af585b92
GN		 7294 kvm_for_each_vcpu(i, vcpu, kvm) {
7295 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7296 kvm_unload_vcpu_mmu(vcpu);
af585b92 7297 }
988a2cae
GN		 7298 kvm_for_each_vcpu(i, vcpu, kvm)
7299 kvm_arch_vcpu_free(vcpu);
7300
7301 mutex_lock(&kvm->lock);
7302 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7303 kvm->vcpus[i] = NULL;
d19a9cd2 7304
988a2cae
GN		 7305 atomic_set(&kvm->online_vcpus, 0);
7306 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7307}
7308
ad8ba2cd
SY		 7309void kvm_arch_sync_events(struct kvm *kvm)
7310{
332967a3 7311 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7312 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7313 kvm_free_all_assigned_devices(kvm);
aea924f6 7314 kvm_free_pit(kvm);
ad8ba2cd
SY		 7315}
7316
d19a9cd2
ZX		 7317void kvm_arch_destroy_vm(struct kvm *kvm)
7318{
27469d29
AH		 7319 if (current->mm == kvm->mm) {
7320 /*
7321 * Free memory regions allocated on behalf of userspace,
7322 * unless the the memory map has changed due to process exit
7323 * or fd copying.
7324 */
7325 struct kvm_userspace_memory_region mem;
7326 memset(&mem, 0, sizeof(mem));
7327 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7328 kvm_set_memory_region(kvm, &mem);
7329
7330 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7331 kvm_set_memory_region(kvm, &mem);
7332
7333 mem.slot = TSS_PRIVATE_MEMSLOT;
7334 kvm_set_memory_region(kvm, &mem);
7335 }
6eb55818 7336 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7337 kfree(kvm->arch.vpic);
7338 kfree(kvm->arch.vioapic);
d19a9cd2 7339 kvm_free_vcpus(kvm);
1e08ec4a 7340 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7341}
0de10343 7342
5587027c 7343void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7344 struct kvm_memory_slot *dont)
7345{
7346 int i;
7347
d89cc617
TY		 7348 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7349 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7350 kvm_kvfree(free->arch.rmap[i]);
7351 free->arch.rmap[i] = NULL;
77d11309 7352 }
d89cc617
TY		 7353 if (i == 0)
7354 continue;
7355
7356 if (!dont || free->arch.lpage_info[i - 1] !=
7357 dont->arch.lpage_info[i - 1]) {
7358 kvm_kvfree(free->arch.lpage_info[i - 1]);
7359 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7360 }
7361 }
7362}
7363
5587027c
AK		 7364int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7365 unsigned long npages)
db3fe4eb
TY		 7366{
7367 int i;
7368
d89cc617 7369 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7370 unsigned long ugfn;
7371 int lpages;
d89cc617 7372 int level = i + 1;
db3fe4eb
TY		 7373
7374 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7375 slot->base_gfn, level) + 1;
7376
d89cc617
TY		 7377 slot->arch.rmap[i] =
7378 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7379 if (!slot->arch.rmap[i])
77d11309 7380 goto out_free;
d89cc617
TY		 7381 if (i == 0)
7382 continue;
77d11309 7383
d89cc617
TY		 7384 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7385 sizeof(*slot->arch.lpage_info[i - 1]));
7386 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7387 goto out_free;
7388
7389 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7390 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7391 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7392 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7393 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7394 /*
7395 * If the gfn and userspace address are not aligned wrt each
7396 * other, or if explicitly asked to, disable large page
7397 * support for this slot
7398 */
7399 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7400 !kvm_largepages_enabled()) {
7401 unsigned long j;
7402
7403 for (j = 0; j < lpages; ++j)
d89cc617 7404 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7405 }
7406 }
7407
7408 return 0;
7409
7410out_free:
d89cc617
TY		 7411 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7412 kvm_kvfree(slot->arch.rmap[i]);
7413 slot->arch.rmap[i] = NULL;
7414 if (i == 0)
7415 continue;
7416
7417 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7418 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7419 }
7420 return -ENOMEM;
7421}
7422
e59dbe09
TY		 7423void kvm_arch_memslots_updated(struct kvm *kvm)
7424{
e6dff7d1
TY		 7425 /*
7426 * memslots->generation has been incremented.
7427 * mmio generation may have reached its maximum value.
7428 */
7429 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7430}
7431
f7784b8e
MT		 7432int kvm_arch_prepare_memory_region(struct kvm *kvm,
7433 struct kvm_memory_slot *memslot,
f7784b8e 7434 struct kvm_userspace_memory_region *mem,
7b6195a9 7435 enum kvm_mr_change change)
0de10343 7436{
7a905b14
TY		 7437 /*
7438 * Only private memory slots need to be mapped here since
7439 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7440 */
7b6195a9 7441 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7442 unsigned long userspace_addr;
604b38ac 7443
7a905b14
TY		 7444 /*
7445 * MAP_SHARED to prevent internal slot pages from being moved
7446 * by fork()/COW.
7447 */
7b6195a9 7448 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7449 PROT_READ | PROT_WRITE,
7450 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7451
7a905b14
TY		 7452 if (IS_ERR((void *)userspace_addr))
7453 return PTR_ERR((void *)userspace_addr);
604b38ac 7454
7a905b14 7455 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7456 }
7457
f7784b8e
MT		 7458 return 0;
7459}
7460
7461void kvm_arch_commit_memory_region(struct kvm *kvm,
7462 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7463 const struct kvm_memory_slot *old,
7464 enum kvm_mr_change change)
f7784b8e
MT		 7465{
7466
8482644a 7467 int nr_mmu_pages = 0;
f7784b8e 7468
8482644a 7469 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7470 int ret;
7471
8482644a
TY		 7472 ret = vm_munmap(old->userspace_addr,
7473 old->npages * PAGE_SIZE);
f7784b8e
MT		 7474 if (ret < 0)
7475 printk(KERN_WARNING
7476 "kvm_vm_ioctl_set_memory_region: "
7477 "failed to munmap memory\n");
7478 }
7479
48c0e4e9
XG		 7480 if (!kvm->arch.n_requested_mmu_pages)
7481 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7482
48c0e4e9 7483 if (nr_mmu_pages)
0de10343 7484 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7485 /*
7486 * Write protect all pages for dirty logging.
c126d94f
XG		 7487 *
7488 * All the sptes including the large sptes which point to this
7489 * slot are set to readonly. We can not create any new large
7490 * spte on this slot until the end of the logging.
7491 *
7492 * See the comments in fast_page_fault().
c972f3b1 7493 */
8482644a 7494 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7495 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7496}
1d737c8a 7497
2df72e9b 7498void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7499{
6ca18b69 7500 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7501}
7502
2df72e9b
MT		 7503void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7504 struct kvm_memory_slot *slot)
7505{
6ca18b69 7506 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7507}
7508
1d737c8a
ZX		 7509int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7510{
b6b8a145
JK		 7511 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7512 kvm_x86_ops->check_nested_events(vcpu, false);
7513
af585b92
GN		 7514 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7515 !vcpu->arch.apf.halted)
7516 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7517 || kvm_apic_has_events(vcpu)
6aef266c 7518 || vcpu->arch.pv.pv_unhalted
7460fb4a 7519 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7520 (kvm_arch_interrupt_allowed(vcpu) &&
7521 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7522}
5736199a 7523
b6d33834 7524int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7525{
b6d33834 7526 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7527}
78646121
GN		 7528
7529int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7530{
7531 return kvm_x86_ops->interrupt_allowed(vcpu);
7532}
229456fc 7533
f92653ee
JK		 7534bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7535{
7536 unsigned long current_rip = kvm_rip_read(vcpu) +
7537 get_segment_base(vcpu, VCPU_SREG_CS);
7538
7539 return current_rip == linear_rip;
7540}
7541EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7542
94fe45da
JK		 7543unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7544{
7545 unsigned long rflags;
7546
7547 rflags = kvm_x86_ops->get_rflags(vcpu);
7548 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7549 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7550 return rflags;
7551}
7552EXPORT_SYMBOL_GPL(kvm_get_rflags);
7553
6addfc42 7554static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7555{
7556 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7557 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7558 rflags |= X86_EFLAGS_TF;
94fe45da 7559 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7560}
7561
7562void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7563{
7564 __kvm_set_rflags(vcpu, rflags);
3842d135 7565 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7566}
7567EXPORT_SYMBOL_GPL(kvm_set_rflags);
7568
56028d08
GN		 7569void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7570{
7571 int r;
7572
fb67e14f 7573 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7574 work->wakeup_all)
56028d08
GN		 7575 return;
7576
7577 r = kvm_mmu_reload(vcpu);
7578 if (unlikely(r))
7579 return;
7580
fb67e14f
XG		 7581 if (!vcpu->arch.mmu.direct_map &&
7582 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7583 return;
7584
56028d08
GN		 7585 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7586}
7587
af585b92
GN		 7588static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7589{
7590 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7591}
7592
7593static inline u32 kvm_async_pf_next_probe(u32 key)
7594{
7595 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7596}
7597
7598static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7599{
7600 u32 key = kvm_async_pf_hash_fn(gfn);
7601
7602 while (vcpu->arch.apf.gfns[key] != ~0)
7603 key = kvm_async_pf_next_probe(key);
7604
7605 vcpu->arch.apf.gfns[key] = gfn;
7606}
7607
7608static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7609{
7610 int i;
7611 u32 key = kvm_async_pf_hash_fn(gfn);
7612
7613 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7614 (vcpu->arch.apf.gfns[key] != gfn &&
7615 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7616 key = kvm_async_pf_next_probe(key);
7617
7618 return key;
7619}
7620
7621bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7622{
7623 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7624}
7625
7626static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7627{
7628 u32 i, j, k;
7629
7630 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7631 while (true) {
7632 vcpu->arch.apf.gfns[i] = ~0;
7633 do {
7634 j = kvm_async_pf_next_probe(j);
7635 if (vcpu->arch.apf.gfns[j] == ~0)
7636 return;
7637 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7638 /*
7639 * k lies cyclically in ]i,j]
7640 * | i.k.j |
7641 * |....j i.k.| or |.k..j i...|
7642 */
7643 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7644 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7645 i = j;
7646 }
7647}
7648
7c90705b
GN		 7649static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7650{
7651
7652 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7653 sizeof(val));
7654}
7655
af585b92
GN		 7656void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7657 struct kvm_async_pf *work)
7658{
6389ee94
AK		 7659 struct x86_exception fault;
7660
7c90705b 7661 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7662 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7663
7664 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7665 (vcpu->arch.apf.send_user_only &&
7666 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7667 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7668 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7669 fault.vector = PF_VECTOR;
7670 fault.error_code_valid = true;
7671 fault.error_code = 0;
7672 fault.nested_page_fault = false;
7673 fault.address = work->arch.token;
7674 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7675 }
af585b92
GN		 7676}
7677
7678void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7679 struct kvm_async_pf *work)
7680{
6389ee94
AK		 7681 struct x86_exception fault;
7682
7c90705b 7683 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7684 if (work->wakeup_all)
7c90705b
GN		 7685 work->arch.token = ~0; /* broadcast wakeup */
7686 else
7687 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7688
7689 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7690 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7691 fault.vector = PF_VECTOR;
7692 fault.error_code_valid = true;
7693 fault.error_code = 0;
7694 fault.nested_page_fault = false;
7695 fault.address = work->arch.token;
7696 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7697 }
e6d53e3b 7698 vcpu->arch.apf.halted = false;
a4fa1635 7699 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7700}
7701
7702bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7703{
7704 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7705 return true;
7706 else
7707 return !kvm_event_needs_reinjection(vcpu) &&
7708 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7709}
7710
e0f0bbc5
AW		 7711void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7712{
7713 atomic_inc(&kvm->arch.noncoherent_dma_count);
7714}
7715EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7716
7717void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7718{
7719 atomic_dec(&kvm->arch.noncoherent_dma_count);
7720}
7721EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7722
7723bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7724{
7725 return atomic_read(&kvm->arch.noncoherent_dma_count);
7726}
7727EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7728
229456fc
MT		 7729EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7730EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7731EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7732EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7733EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7734EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7735EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7736EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7737EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7738EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7739EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7740EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7741EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 7742EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
Linux 6.x block layer and io_uring tree(s)