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KVM: remove unnecessary return value check
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
aec51dc4 49#include <trace/events/kvm.h>
2ed152af 50
229456fc
MT		 51#define CREATE_TRACE_POINTS
52#include "trace.h"
043405e1 53
24f1e32c 54#include <asm/debugreg.h>
d825ed0a 55#include <asm/msr.h>
a5f61300 56#include <asm/desc.h>
0bed3b56 57#include <asm/mtrr.h>
890ca9ae 58#include <asm/mce.h>
7cf30855 59#include <asm/i387.h>
1361b83a 60#include <asm/fpu-internal.h> /* Ugh! */
98918833 61#include <asm/xcr.h>
1d5f066e 62#include <asm/pvclock.h>
217fc9cf 63#include <asm/div64.h>
043405e1 64
313a3dc7 65#define MAX_IO_MSRS 256
890ca9ae 66#define KVM_MAX_MCE_BANKS 32
5854dbca 67#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 68
0f65dd70
AK		 69#define emul_to_vcpu(ctxt) \
70 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
1260edbe
LJ		 77static
78u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 79#else
1260edbe 80static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 81#endif
313a3dc7 82
ba1389b7
AK		 83#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 85
cb142eb7 86static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 87static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
476bc001
RR		 92static bool ignore_msrs = 0;
93module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 94
92a1f12d
JR		 95bool kvm_has_tsc_control;
96EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97u32 kvm_max_guest_tsc_khz;
98EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
cc578287
ZA		 100/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101static u32 tsc_tolerance_ppm = 250;
102module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103
18863bdd
AK		 104#define KVM_NR_SHARED_MSRS 16
105
106struct kvm_shared_msrs_global {
107 int nr;
2bf78fa7 108 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111struct kvm_shared_msrs {
112 struct user_return_notifier urn;
113 bool registered;
2bf78fa7
SY		 114 struct kvm_shared_msr_values {
115 u64 host;
116 u64 curr;
117 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 118};
119
120static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122
417bc304 123struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 124 { "pf_fixed", VCPU_STAT(pf_fixed) },
125 { "pf_guest", VCPU_STAT(pf_guest) },
126 { "tlb_flush", VCPU_STAT(tlb_flush) },
127 { "invlpg", VCPU_STAT(invlpg) },
128 { "exits", VCPU_STAT(exits) },
129 { "io_exits", VCPU_STAT(io_exits) },
130 { "mmio_exits", VCPU_STAT(mmio_exits) },
131 { "signal_exits", VCPU_STAT(signal_exits) },
132 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 133 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 134 { "halt_exits", VCPU_STAT(halt_exits) },
135 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 136 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 137 { "request_irq", VCPU_STAT(request_irq_exits) },
138 { "irq_exits", VCPU_STAT(irq_exits) },
139 { "host_state_reload", VCPU_STAT(host_state_reload) },
140 { "efer_reload", VCPU_STAT(efer_reload) },
141 { "fpu_reload", VCPU_STAT(fpu_reload) },
142 { "insn_emulation", VCPU_STAT(insn_emulation) },
143 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 144 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 145 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 146 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150 { "mmu_flooded", VM_STAT(mmu_flooded) },
151 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 152 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 153 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 154 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 155 { "largepages", VM_STAT(lpages) },
417bc304
HB		 156 { NULL }
157};
158
2acf923e
DC		 159u64 __read_mostly host_xcr0;
160
b6785def 161static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 162
8b6e4547
JK		 163static int kvm_vcpu_reset(struct kvm_vcpu *vcpu);
164
af585b92
GN		 165static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
166{
167 int i;
168 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
169 vcpu->arch.apf.gfns[i] = ~0;
170}
171
18863bdd
AK		 172static void kvm_on_user_return(struct user_return_notifier *urn)
173{
174 unsigned slot;
18863bdd
AK		 175 struct kvm_shared_msrs *locals
176 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 177 struct kvm_shared_msr_values *values;
18863bdd
AK		 178
179 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 180 values = &locals->values[slot];
181 if (values->host != values->curr) {
182 wrmsrl(shared_msrs_global.msrs[slot], values->host);
183 values->curr = values->host;
18863bdd
AK		 184 }
185 }
186 locals->registered = false;
187 user_return_notifier_unregister(urn);
188}
189
2bf78fa7 190static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 191{
2bf78fa7 192 struct kvm_shared_msrs *smsr;
18863bdd
AK		 193 u64 value;
194
2bf78fa7
SY		 195 smsr = &__get_cpu_var(shared_msrs);
196 /* only read, and nobody should modify it at this time,
197 * so don't need lock */
198 if (slot >= shared_msrs_global.nr) {
199 printk(KERN_ERR "kvm: invalid MSR slot!");
200 return;
201 }
202 rdmsrl_safe(msr, &value);
203 smsr->values[slot].host = value;
204 smsr->values[slot].curr = value;
205}
206
207void kvm_define_shared_msr(unsigned slot, u32 msr)
208{
18863bdd
AK		 209 if (slot >= shared_msrs_global.nr)
210 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 211 shared_msrs_global.msrs[slot] = msr;
212 /* we need ensured the shared_msr_global have been updated */
213 smp_wmb();
18863bdd
AK		 214}
215EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
216
217static void kvm_shared_msr_cpu_online(void)
218{
219 unsigned i;
18863bdd
AK		 220
221 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 222 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 223}
224
d5696725 225void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 226{
227 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
228
2bf78fa7 229 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 230 return;
2bf78fa7
SY		 231 smsr->values[slot].curr = value;
232 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 233 if (!smsr->registered) {
234 smsr->urn.on_user_return = kvm_on_user_return;
235 user_return_notifier_register(&smsr->urn);
236 smsr->registered = true;
237 }
238}
239EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
240
3548bab5
AK		 241static void drop_user_return_notifiers(void *ignore)
242{
243 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
244
245 if (smsr->registered)
246 kvm_on_user_return(&smsr->urn);
247}
248
6866b83e
CO		 249u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
250{
8a5a87d9 251 return vcpu->arch.apic_base;
6866b83e
CO		 252}
253EXPORT_SYMBOL_GPL(kvm_get_apic_base);
254
255void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
256{
257 /* TODO: reserve bits check */
8a5a87d9 258 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 259}
260EXPORT_SYMBOL_GPL(kvm_set_apic_base);
261
3fd28fce
ED		 262#define EXCPT_BENIGN 0
263#define EXCPT_CONTRIBUTORY 1
264#define EXCPT_PF 2
265
266static int exception_class(int vector)
267{
268 switch (vector) {
269 case PF_VECTOR:
270 return EXCPT_PF;
271 case DE_VECTOR:
272 case TS_VECTOR:
273 case NP_VECTOR:
274 case SS_VECTOR:
275 case GP_VECTOR:
276 return EXCPT_CONTRIBUTORY;
277 default:
278 break;
279 }
280 return EXCPT_BENIGN;
281}
282
283static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 284 unsigned nr, bool has_error, u32 error_code,
285 bool reinject)
3fd28fce
ED		 286{
287 u32 prev_nr;
288 int class1, class2;
289
3842d135
AK		 290 kvm_make_request(KVM_REQ_EVENT, vcpu);
291
3fd28fce
ED		 292 if (!vcpu->arch.exception.pending) {
293 queue:
294 vcpu->arch.exception.pending = true;
295 vcpu->arch.exception.has_error_code = has_error;
296 vcpu->arch.exception.nr = nr;
297 vcpu->arch.exception.error_code = error_code;
3f0fd292 298 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 299 return;
300 }
301
302 /* to check exception */
303 prev_nr = vcpu->arch.exception.nr;
304 if (prev_nr == DF_VECTOR) {
305 /* triple fault -> shutdown */
a8eeb04a 306 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 307 return;
308 }
309 class1 = exception_class(prev_nr);
310 class2 = exception_class(nr);
311 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
312 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
313 /* generate double fault per SDM Table 5-5 */
314 vcpu->arch.exception.pending = true;
315 vcpu->arch.exception.has_error_code = true;
316 vcpu->arch.exception.nr = DF_VECTOR;
317 vcpu->arch.exception.error_code = 0;
318 } else
319 /* replace previous exception with a new one in a hope
320 that instruction re-execution will regenerate lost
321 exception */
322 goto queue;
323}
324
298101da
AK		 325void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
326{
ce7ddec4 327 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 328}
329EXPORT_SYMBOL_GPL(kvm_queue_exception);
330
ce7ddec4
JR		 331void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332{
333 kvm_multiple_exception(vcpu, nr, false, 0, true);
334}
335EXPORT_SYMBOL_GPL(kvm_requeue_exception);
336
db8fcefa 337void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 338{
db8fcefa
AP		 339 if (err)
340 kvm_inject_gp(vcpu, 0);
341 else
342 kvm_x86_ops->skip_emulated_instruction(vcpu);
343}
344EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 345
6389ee94 346void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 347{
348 ++vcpu->stat.pf_guest;
6389ee94
AK		 349 vcpu->arch.cr2 = fault->address;
350 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 351}
27d6c865 352EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 353
6389ee94 354void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 355{
6389ee94
AK		 356 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
357 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 358 else
6389ee94 359 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 360}
361
3419ffc8
SY		 362void kvm_inject_nmi(struct kvm_vcpu *vcpu)
363{
7460fb4a
AK		 364 atomic_inc(&vcpu->arch.nmi_queued);
365 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 366}
367EXPORT_SYMBOL_GPL(kvm_inject_nmi);
368
298101da
AK		 369void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
370{
ce7ddec4 371 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 372}
373EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
374
ce7ddec4
JR		 375void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
376{
377 kvm_multiple_exception(vcpu, nr, true, error_code, true);
378}
379EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
380
0a79b009
AK		 381/*
382 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
383 * a #GP and return false.
384 */
385bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 386{
0a79b009
AK		 387 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
388 return true;
389 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
390 return false;
298101da 391}
0a79b009 392EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 393
ec92fe44
JR		 394/*
395 * This function will be used to read from the physical memory of the currently
396 * running guest. The difference to kvm_read_guest_page is that this function
397 * can read from guest physical or from the guest's guest physical memory.
398 */
399int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
400 gfn_t ngfn, void *data, int offset, int len,
401 u32 access)
402{
403 gfn_t real_gfn;
404 gpa_t ngpa;
405
406 ngpa = gfn_to_gpa(ngfn);
407 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
408 if (real_gfn == UNMAPPED_GVA)
409 return -EFAULT;
410
411 real_gfn = gpa_to_gfn(real_gfn);
412
413 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
414}
415EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
416
3d06b8bf
JR		 417int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
418 void *data, int offset, int len, u32 access)
419{
420 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
421 data, offset, len, access);
422}
423
a03490ed
CO		 424/*
425 * Load the pae pdptrs. Return true is they are all valid.
426 */
ff03a073 427int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 428{
429 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
430 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
431 int i;
432 int ret;
ff03a073 433 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 434
ff03a073
JR		 435 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
436 offset * sizeof(u64), sizeof(pdpte),
437 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 438 if (ret < 0) {
439 ret = 0;
440 goto out;
441 }
442 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 443 if (is_present_gpte(pdpte[i]) &&
20c466b5 444 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 445 ret = 0;
446 goto out;
447 }
448 }
449 ret = 1;
450
ff03a073 451 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 452 __set_bit(VCPU_EXREG_PDPTR,
453 (unsigned long *)&vcpu->arch.regs_avail);
454 __set_bit(VCPU_EXREG_PDPTR,
455 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 456out:
a03490ed
CO		 457
458 return ret;
459}
cc4b6871 460EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 461
d835dfec
AK		 462static bool pdptrs_changed(struct kvm_vcpu *vcpu)
463{
ff03a073 464 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 465 bool changed = true;
3d06b8bf
JR		 466 int offset;
467 gfn_t gfn;
d835dfec
AK		 468 int r;
469
470 if (is_long_mode(vcpu) || !is_pae(vcpu))
471 return false;
472
6de4f3ad
AK		 473 if (!test_bit(VCPU_EXREG_PDPTR,
474 (unsigned long *)&vcpu->arch.regs_avail))
475 return true;
476
9f8fe504
AK		 477 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
478 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 479 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
480 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 481 if (r < 0)
482 goto out;
ff03a073 483 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 484out:
d835dfec
AK		 485
486 return changed;
487}
488
49a9b07e 489int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 490{
aad82703
SY		 491 unsigned long old_cr0 = kvm_read_cr0(vcpu);
492 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
493 X86_CR0_CD | X86_CR0_NW;
494
f9a48e6a
AK		 495 cr0 |= X86_CR0_ET;
496
ab344828 497#ifdef CONFIG_X86_64
0f12244f
GN		 498 if (cr0 & 0xffffffff00000000UL)
499 return 1;
ab344828
GN		 500#endif
501
502 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 503
0f12244f
GN		 504 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
505 return 1;
a03490ed 506
0f12244f
GN		 507 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
508 return 1;
a03490ed
CO		 509
510 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
511#ifdef CONFIG_X86_64
f6801dff 512 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 513 int cs_db, cs_l;
514
0f12244f
GN		 515 if (!is_pae(vcpu))
516 return 1;
a03490ed 517 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 518 if (cs_l)
519 return 1;
a03490ed
CO		 520 } else
521#endif
ff03a073 522 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 523 kvm_read_cr3(vcpu)))
0f12244f 524 return 1;
a03490ed
CO		 525 }
526
ad756a16
MJ		 527 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
528 return 1;
529
a03490ed 530 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 531
d170c419 532 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 533 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 534 kvm_async_pf_hash_reset(vcpu);
535 }
e5f3f027 536
aad82703
SY		 537 if ((cr0 ^ old_cr0) & update_bits)
538 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 539 return 0;
540}
2d3ad1f4 541EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 542
2d3ad1f4 543void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 544{
49a9b07e 545 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 546}
2d3ad1f4 547EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 548
2acf923e
DC		 549int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
550{
551 u64 xcr0;
552
553 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
554 if (index != XCR_XFEATURE_ENABLED_MASK)
555 return 1;
556 xcr0 = xcr;
557 if (kvm_x86_ops->get_cpl(vcpu) != 0)
558 return 1;
559 if (!(xcr0 & XSTATE_FP))
560 return 1;
561 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
562 return 1;
563 if (xcr0 & ~host_xcr0)
564 return 1;
565 vcpu->arch.xcr0 = xcr0;
566 vcpu->guest_xcr0_loaded = 0;
567 return 0;
568}
569
570int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
571{
572 if (__kvm_set_xcr(vcpu, index, xcr)) {
573 kvm_inject_gp(vcpu, 0);
574 return 1;
575 }
576 return 0;
577}
578EXPORT_SYMBOL_GPL(kvm_set_xcr);
579
a83b29c6 580int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 581{
fc78f519 582 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 583 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
584 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 585 if (cr4 & CR4_RESERVED_BITS)
586 return 1;
a03490ed 587
2acf923e
DC		 588 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
589 return 1;
590
c68b734f
YW		 591 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
592 return 1;
593
74dc2b4f
YW		 594 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
595 return 1;
596
a03490ed 597 if (is_long_mode(vcpu)) {
0f12244f
GN		 598 if (!(cr4 & X86_CR4_PAE))
599 return 1;
a2edf57f
AK		 600 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
601 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 602 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
603 kvm_read_cr3(vcpu)))
0f12244f
GN		 604 return 1;
605
ad756a16
MJ		 606 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
607 if (!guest_cpuid_has_pcid(vcpu))
608 return 1;
609
610 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
611 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
612 return 1;
613 }
614
5e1746d6 615 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 616 return 1;
a03490ed 617
ad756a16
MJ		 618 if (((cr4 ^ old_cr4) & pdptr_bits) ||
619 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 620 kvm_mmu_reset_context(vcpu);
0f12244f 621
2acf923e 622 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 623 kvm_update_cpuid(vcpu);
2acf923e 624
0f12244f
GN		 625 return 0;
626}
2d3ad1f4 627EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 628
2390218b 629int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 630{
9f8fe504 631 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 632 kvm_mmu_sync_roots(vcpu);
d835dfec 633 kvm_mmu_flush_tlb(vcpu);
0f12244f 634 return 0;
d835dfec
AK		 635 }
636
a03490ed 637 if (is_long_mode(vcpu)) {
471842ec 638 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 639 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
640 return 1;
641 } else
642 if (cr3 & CR3_L_MODE_RESERVED_BITS)
643 return 1;
a03490ed
CO		 644 } else {
645 if (is_pae(vcpu)) {
0f12244f
GN		 646 if (cr3 & CR3_PAE_RESERVED_BITS)
647 return 1;
ff03a073
JR		 648 if (is_paging(vcpu) &&
649 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 650 return 1;
a03490ed
CO		 651 }
652 /*
653 * We don't check reserved bits in nonpae mode, because
654 * this isn't enforced, and VMware depends on this.
655 */
656 }
657
a03490ed
CO		 658 /*
659 * Does the new cr3 value map to physical memory? (Note, we
660 * catch an invalid cr3 even in real-mode, because it would
661 * cause trouble later on when we turn on paging anyway.)
662 *
663 * A real CPU would silently accept an invalid cr3 and would
664 * attempt to use it - with largely undefined (and often hard
665 * to debug) behavior on the guest side.
666 */
667 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 668 return 1;
669 vcpu->arch.cr3 = cr3;
aff48baa 670 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 671 vcpu->arch.mmu.new_cr3(vcpu);
672 return 0;
673}
2d3ad1f4 674EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 675
eea1cff9 676int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 677{
0f12244f
GN		 678 if (cr8 & CR8_RESERVED_BITS)
679 return 1;
a03490ed
CO		 680 if (irqchip_in_kernel(vcpu->kvm))
681 kvm_lapic_set_tpr(vcpu, cr8);
682 else
ad312c7c 683 vcpu->arch.cr8 = cr8;
0f12244f
GN		 684 return 0;
685}
2d3ad1f4 686EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 687
2d3ad1f4 688unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 689{
690 if (irqchip_in_kernel(vcpu->kvm))
691 return kvm_lapic_get_cr8(vcpu);
692 else
ad312c7c 693 return vcpu->arch.cr8;
a03490ed 694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 696
c8639010
JK		 697static void kvm_update_dr7(struct kvm_vcpu *vcpu)
698{
699 unsigned long dr7;
700
701 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
702 dr7 = vcpu->arch.guest_debug_dr7;
703 else
704 dr7 = vcpu->arch.dr7;
705 kvm_x86_ops->set_dr7(vcpu, dr7);
706 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
707}
708
338dbc97 709static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 710{
711 switch (dr) {
712 case 0 ... 3:
713 vcpu->arch.db[dr] = val;
714 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
715 vcpu->arch.eff_db[dr] = val;
716 break;
717 case 4:
338dbc97
GN		 718 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
719 return 1; /* #UD */
020df079
GN		 720 /* fall through */
721 case 6:
338dbc97
GN		 722 if (val & 0xffffffff00000000ULL)
723 return -1; /* #GP */
020df079
GN		 724 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
725 break;
726 case 5:
338dbc97
GN		 727 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
728 return 1; /* #UD */
020df079
GN		 729 /* fall through */
730 default: /* 7 */
338dbc97
GN		 731 if (val & 0xffffffff00000000ULL)
732 return -1; /* #GP */
020df079 733 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 734 kvm_update_dr7(vcpu);
020df079
GN		 735 break;
736 }
737
738 return 0;
739}
338dbc97
GN		 740
741int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
742{
743 int res;
744
745 res = __kvm_set_dr(vcpu, dr, val);
746 if (res > 0)
747 kvm_queue_exception(vcpu, UD_VECTOR);
748 else if (res < 0)
749 kvm_inject_gp(vcpu, 0);
750
751 return res;
752}
020df079
GN		 753EXPORT_SYMBOL_GPL(kvm_set_dr);
754
338dbc97 755static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 756{
757 switch (dr) {
758 case 0 ... 3:
759 *val = vcpu->arch.db[dr];
760 break;
761 case 4:
338dbc97 762 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 763 return 1;
020df079
GN		 764 /* fall through */
765 case 6:
766 *val = vcpu->arch.dr6;
767 break;
768 case 5:
338dbc97 769 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 770 return 1;
020df079
GN		 771 /* fall through */
772 default: /* 7 */
773 *val = vcpu->arch.dr7;
774 break;
775 }
776
777 return 0;
778}
338dbc97
GN		 779
780int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
781{
782 if (_kvm_get_dr(vcpu, dr, val)) {
783 kvm_queue_exception(vcpu, UD_VECTOR);
784 return 1;
785 }
786 return 0;
787}
020df079
GN		 788EXPORT_SYMBOL_GPL(kvm_get_dr);
789
022cd0e8
AK		 790bool kvm_rdpmc(struct kvm_vcpu *vcpu)
791{
792 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
793 u64 data;
794 int err;
795
796 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
797 if (err)
798 return err;
799 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
800 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
801 return err;
802}
803EXPORT_SYMBOL_GPL(kvm_rdpmc);
804
043405e1
CO		 805/*
806 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
807 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
808 *
809 * This list is modified at module load time to reflect the
e3267cbb
GC		 810 * capabilities of the host cpu. This capabilities test skips MSRs that are
811 * kvm-specific. Those are put in the beginning of the list.
043405e1 812 */
e3267cbb 813
439793d4 814#define KVM_SAVE_MSRS_BEGIN 10
043405e1 815static u32 msrs_to_save[] = {
e3267cbb 816 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 817 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 818 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 819 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 820 MSR_KVM_PV_EOI_EN,
043405e1 821 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 822 MSR_STAR,
043405e1
CO		 823#ifdef CONFIG_X86_64
824 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
825#endif
e90aa41e 826 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 827};
828
829static unsigned num_msrs_to_save;
830
f1d24831 831static const u32 emulated_msrs[] = {
a3e06bbe 832 MSR_IA32_TSCDEADLINE,
043405e1 833 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 834 MSR_IA32_MCG_STATUS,
835 MSR_IA32_MCG_CTL,
043405e1
CO		 836};
837
b69e8cae 838static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 839{
aad82703
SY		 840 u64 old_efer = vcpu->arch.efer;
841
b69e8cae
RJ		 842 if (efer & efer_reserved_bits)
843 return 1;
15c4a640
CO		 844
845 if (is_paging(vcpu)
b69e8cae
RJ		 846 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
847 return 1;
15c4a640 848
1b2fd70c
AG		 849 if (efer & EFER_FFXSR) {
850 struct kvm_cpuid_entry2 *feat;
851
852 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 853 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
854 return 1;
1b2fd70c
AG		 855 }
856
d8017474
AG		 857 if (efer & EFER_SVME) {
858 struct kvm_cpuid_entry2 *feat;
859
860 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 861 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
862 return 1;
d8017474
AG		 863 }
864
15c4a640 865 efer &= ~EFER_LMA;
f6801dff 866 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 867
a3d204e2
SY		 868 kvm_x86_ops->set_efer(vcpu, efer);
869
9645bb56 870 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 871
aad82703
SY		 872 /* Update reserved bits */
873 if ((efer ^ old_efer) & EFER_NX)
874 kvm_mmu_reset_context(vcpu);
875
b69e8cae 876 return 0;
15c4a640
CO		 877}
878
f2b4b7dd
JR		 879void kvm_enable_efer_bits(u64 mask)
880{
881 efer_reserved_bits &= ~mask;
882}
883EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
884
885
15c4a640
CO		 886/*
887 * Writes msr value into into the appropriate "register".
888 * Returns 0 on success, non-0 otherwise.
889 * Assumes vcpu_load() was already called.
890 */
891int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
892{
893 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
894}
895
313a3dc7
CO		 896/*
897 * Adapt set_msr() to msr_io()'s calling convention
898 */
899static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
900{
901 return kvm_set_msr(vcpu, index, *data);
902}
903
18068523
GOC		 904static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
905{
9ed3c444
AK		 906 int version;
907 int r;
50d0a0f9 908 struct pvclock_wall_clock wc;
923de3cf 909 struct timespec boot;
18068523
GOC		 910
911 if (!wall_clock)
912 return;
913
9ed3c444
AK		 914 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
915 if (r)
916 return;
917
918 if (version & 1)
919 ++version; /* first time write, random junk */
920
921 ++version;
18068523 922
18068523
GOC		 923 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
924
50d0a0f9
GH		 925 /*
926 * The guest calculates current wall clock time by adding
34c238a1 927 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 928 * wall clock specified here. guest system time equals host
929 * system time for us, thus we must fill in host boot time here.
930 */
923de3cf 931 getboottime(&boot);
50d0a0f9 932
4b648665
BR		 933 if (kvm->arch.kvmclock_offset) {
934 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
935 boot = timespec_sub(boot, ts);
936 }
50d0a0f9
GH		 937 wc.sec = boot.tv_sec;
938 wc.nsec = boot.tv_nsec;
939 wc.version = version;
18068523
GOC		 940
941 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
942
943 version++;
944 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 945}
946
50d0a0f9
GH		 947static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
948{
949 uint32_t quotient, remainder;
950
951 /* Don't try to replace with do_div(), this one calculates
952 * "(dividend << 32) / divisor" */
953 __asm__ ( "divl %4"
954 : "=a" (quotient), "=d" (remainder)
955 : "0" (0), "1" (dividend), "r" (divisor) );
956 return quotient;
957}
958
5f4e3f88
ZA		 959static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
960 s8 *pshift, u32 *pmultiplier)
50d0a0f9 961{
5f4e3f88 962 uint64_t scaled64;
50d0a0f9
GH		 963 int32_t shift = 0;
964 uint64_t tps64;
965 uint32_t tps32;
966
5f4e3f88
ZA		 967 tps64 = base_khz * 1000LL;
968 scaled64 = scaled_khz * 1000LL;
50933623 969 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 970 tps64 >>= 1;
971 shift--;
972 }
973
974 tps32 = (uint32_t)tps64;
50933623
JK		 975 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
976 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 977 scaled64 >>= 1;
978 else
979 tps32 <<= 1;
50d0a0f9
GH		 980 shift++;
981 }
982
5f4e3f88
ZA		 983 *pshift = shift;
984 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 985
5f4e3f88
ZA		 986 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
987 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 988}
989
759379dd
ZA		 990static inline u64 get_kernel_ns(void)
991{
992 struct timespec ts;
993
994 WARN_ON(preemptible());
995 ktime_get_ts(&ts);
996 monotonic_to_bootbased(&ts);
997 return timespec_to_ns(&ts);
50d0a0f9
GH		 998}
999
c8076604 1000static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1001unsigned long max_tsc_khz;
c8076604 1002
cc578287 1003static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1004{
cc578287
ZA		 1005 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1006 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1007}
1008
cc578287 1009static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1010{
cc578287
ZA		 1011 u64 v = (u64)khz * (1000000 + ppm);
1012 do_div(v, 1000000);
1013 return v;
1e993611
JR		 1014}
1015
cc578287 1016static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1017{
cc578287
ZA		 1018 u32 thresh_lo, thresh_hi;
1019 int use_scaling = 0;
217fc9cf 1020
c285545f
ZA		 1021 /* Compute a scale to convert nanoseconds in TSC cycles */
1022 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1023 &vcpu->arch.virtual_tsc_shift,
1024 &vcpu->arch.virtual_tsc_mult);
1025 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1026
1027 /*
1028 * Compute the variation in TSC rate which is acceptable
1029 * within the range of tolerance and decide if the
1030 * rate being applied is within that bounds of the hardware
1031 * rate. If so, no scaling or compensation need be done.
1032 */
1033 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1034 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1035 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1036 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1037 use_scaling = 1;
1038 }
1039 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1040}
1041
1042static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1043{
e26101b1 1044 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1045 vcpu->arch.virtual_tsc_mult,
1046 vcpu->arch.virtual_tsc_shift);
e26101b1 1047 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1048 return tsc;
1049}
1050
99e3e30a
ZA		 1051void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1052{
1053 struct kvm *kvm = vcpu->kvm;
f38e098f 1054 u64 offset, ns, elapsed;
99e3e30a 1055 unsigned long flags;
02626b6a 1056 s64 usdiff;
99e3e30a 1057
038f8c11 1058 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1059 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1060 ns = get_kernel_ns();
f38e098f 1061 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1062
1063 /* n.b - signed multiplication and division required */
02626b6a 1064 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1065#ifdef CONFIG_X86_64
02626b6a 1066 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6
ZA		 1067#else
1068 /* do_div() only does unsigned */
1069 asm("idivl %2; xor %%edx, %%edx"
02626b6a
MT		 1070 : "=A"(usdiff)
1071 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1072#endif
02626b6a
MT		 1073 do_div(elapsed, 1000);
1074 usdiff -= elapsed;
1075 if (usdiff < 0)
1076 usdiff = -usdiff;
f38e098f
ZA		 1077
1078 /*
5d3cb0f6
ZA		 1079 * Special case: TSC write with a small delta (1 second) of virtual
1080 * cycle time against real time is interpreted as an attempt to
1081 * synchronize the CPU.
1082 *
1083 * For a reliable TSC, we can match TSC offsets, and for an unstable
1084 * TSC, we add elapsed time in this computation. We could let the
1085 * compensation code attempt to catch up if we fall behind, but
1086 * it's better to try to match offsets from the beginning.
1087 */
02626b6a 1088 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1089 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1090 if (!check_tsc_unstable()) {
e26101b1 1091 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1092 pr_debug("kvm: matched tsc offset for %llu\n", data);
1093 } else {
857e4099 1094 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1095 data += delta;
1096 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1097 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1098 }
e26101b1
ZA		 1099 } else {
1100 /*
1101 * We split periods of matched TSC writes into generations.
1102 * For each generation, we track the original measured
1103 * nanosecond time, offset, and write, so if TSCs are in
1104 * sync, we can match exact offset, and if not, we can match
4a969980 1105 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1106 *
1107 * These values are tracked in kvm->arch.cur_xxx variables.
1108 */
1109 kvm->arch.cur_tsc_generation++;
1110 kvm->arch.cur_tsc_nsec = ns;
1111 kvm->arch.cur_tsc_write = data;
1112 kvm->arch.cur_tsc_offset = offset;
1113 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1114 kvm->arch.cur_tsc_generation, data);
f38e098f 1115 }
e26101b1
ZA		 1116
1117 /*
1118 * We also track th most recent recorded KHZ, write and time to
1119 * allow the matching interval to be extended at each write.
1120 */
f38e098f
ZA		 1121 kvm->arch.last_tsc_nsec = ns;
1122 kvm->arch.last_tsc_write = data;
5d3cb0f6 1123 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1124
1125 /* Reset of TSC must disable overshoot protection below */
1126 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1127 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1128
1129 /* Keep track of which generation this VCPU has synchronized to */
1130 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1131 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1132 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1133
1134 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1135 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a 1136}
e26101b1 1137
99e3e30a
ZA		 1138EXPORT_SYMBOL_GPL(kvm_write_tsc);
1139
34c238a1 1140static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1141{
18068523
GOC		 1142 unsigned long flags;
1143 struct kvm_vcpu_arch *vcpu = &v->arch;
1144 void *shared_kaddr;
463656c0 1145 unsigned long this_tsc_khz;
1d5f066e
ZA		 1146 s64 kernel_ns, max_kernel_ns;
1147 u64 tsc_timestamp;
51d59c6b 1148 u8 pvclock_flags;
18068523 1149
18068523
GOC		 1150 /* Keep irq disabled to prevent changes to the clock */
1151 local_irq_save(flags);
d5c1785d 1152 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1153 kernel_ns = get_kernel_ns();
cc578287 1154 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
8cfdc000 1155 if (unlikely(this_tsc_khz == 0)) {
c285545f 1156 local_irq_restore(flags);
34c238a1 1157 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1158 return 1;
1159 }
18068523 1160
c285545f
ZA		 1161 /*
1162 * We may have to catch up the TSC to match elapsed wall clock
1163 * time for two reasons, even if kvmclock is used.
1164 * 1) CPU could have been running below the maximum TSC rate
1165 * 2) Broken TSC compensation resets the base at each VCPU
1166 * entry to avoid unknown leaps of TSC even when running
1167 * again on the same CPU. This may cause apparent elapsed
1168 * time to disappear, and the guest to stand still or run
1169 * very slowly.
1170 */
1171 if (vcpu->tsc_catchup) {
1172 u64 tsc = compute_guest_tsc(v, kernel_ns);
1173 if (tsc > tsc_timestamp) {
f1e2b260 1174 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1175 tsc_timestamp = tsc;
1176 }
50d0a0f9
GH		 1177 }
1178
18068523
GOC		 1179 local_irq_restore(flags);
1180
c285545f
ZA		 1181 if (!vcpu->time_page)
1182 return 0;
18068523 1183
1d5f066e
ZA		 1184 /*
1185 * Time as measured by the TSC may go backwards when resetting the base
1186 * tsc_timestamp. The reason for this is that the TSC resolution is
1187 * higher than the resolution of the other clock scales. Thus, many
1188 * possible measurments of the TSC correspond to one measurement of any
1189 * other clock, and so a spread of values is possible. This is not a
1190 * problem for the computation of the nanosecond clock; with TSC rates
1191 * around 1GHZ, there can only be a few cycles which correspond to one
1192 * nanosecond value, and any path through this code will inevitably
1193 * take longer than that. However, with the kernel_ns value itself,
1194 * the precision may be much lower, down to HZ granularity. If the
1195 * first sampling of TSC against kernel_ns ends in the low part of the
1196 * range, and the second in the high end of the range, we can get:
1197 *
1198 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1199 *
1200 * As the sampling errors potentially range in the thousands of cycles,
1201 * it is possible such a time value has already been observed by the
1202 * guest. To protect against this, we must compute the system time as
1203 * observed by the guest and ensure the new system time is greater.
1204 */
1205 max_kernel_ns = 0;
b183aa58 1206 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1207 max_kernel_ns = vcpu->last_guest_tsc -
1208 vcpu->hv_clock.tsc_timestamp;
1209 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1210 vcpu->hv_clock.tsc_to_system_mul,
1211 vcpu->hv_clock.tsc_shift);
1212 max_kernel_ns += vcpu->last_kernel_ns;
1213 }
afbcf7ab 1214
e48672fa 1215 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1216 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1217 &vcpu->hv_clock.tsc_shift,
1218 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1219 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1220 }
1221
1d5f066e
ZA		 1222 if (max_kernel_ns > kernel_ns)
1223 kernel_ns = max_kernel_ns;
1224
8cfdc000 1225 /* With all the info we got, fill in the values */
1d5f066e 1226 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1227 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1228 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1229 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b
MT		 1230
1231 pvclock_flags = 0;
1232 if (vcpu->pvclock_set_guest_stopped_request) {
1233 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1234 vcpu->pvclock_set_guest_stopped_request = false;
1235 }
1236
1237 vcpu->hv_clock.flags = pvclock_flags;
371bcf64 1238
18068523
GOC		 1239 /*
1240 * The interface expects us to write an even number signaling that the
1241 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1242 * state, we just increase by 2 at the end.
18068523 1243 */
50d0a0f9 1244 vcpu->hv_clock.version += 2;
18068523 1245
8fd75e12 1246 shared_kaddr = kmap_atomic(vcpu->time_page);
18068523
GOC		 1247
1248 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1249 sizeof(vcpu->hv_clock));
18068523 1250
8fd75e12 1251 kunmap_atomic(shared_kaddr);
18068523
GOC		 1252
1253 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1254 return 0;
c8076604
GH		 1255}
1256
9ba075a6
AK		 1257static bool msr_mtrr_valid(unsigned msr)
1258{
1259 switch (msr) {
1260 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1261 case MSR_MTRRfix64K_00000:
1262 case MSR_MTRRfix16K_80000:
1263 case MSR_MTRRfix16K_A0000:
1264 case MSR_MTRRfix4K_C0000:
1265 case MSR_MTRRfix4K_C8000:
1266 case MSR_MTRRfix4K_D0000:
1267 case MSR_MTRRfix4K_D8000:
1268 case MSR_MTRRfix4K_E0000:
1269 case MSR_MTRRfix4K_E8000:
1270 case MSR_MTRRfix4K_F0000:
1271 case MSR_MTRRfix4K_F8000:
1272 case MSR_MTRRdefType:
1273 case MSR_IA32_CR_PAT:
1274 return true;
1275 case 0x2f8:
1276 return true;
1277 }
1278 return false;
1279}
1280
d6289b93
MT		 1281static bool valid_pat_type(unsigned t)
1282{
1283 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1284}
1285
1286static bool valid_mtrr_type(unsigned t)
1287{
1288 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1289}
1290
1291static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1292{
1293 int i;
1294
1295 if (!msr_mtrr_valid(msr))
1296 return false;
1297
1298 if (msr == MSR_IA32_CR_PAT) {
1299 for (i = 0; i < 8; i++)
1300 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1301 return false;
1302 return true;
1303 } else if (msr == MSR_MTRRdefType) {
1304 if (data & ~0xcff)
1305 return false;
1306 return valid_mtrr_type(data & 0xff);
1307 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1308 for (i = 0; i < 8 ; i++)
1309 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1310 return false;
1311 return true;
1312 }
1313
1314 /* variable MTRRs */
1315 return valid_mtrr_type(data & 0xff);
1316}
1317
9ba075a6
AK		 1318static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1319{
0bed3b56
SY		 1320 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1321
d6289b93 1322 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1323 return 1;
1324
0bed3b56
SY		 1325 if (msr == MSR_MTRRdefType) {
1326 vcpu->arch.mtrr_state.def_type = data;
1327 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1328 } else if (msr == MSR_MTRRfix64K_00000)
1329 p[0] = data;
1330 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1331 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1332 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1333 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1334 else if (msr == MSR_IA32_CR_PAT)
1335 vcpu->arch.pat = data;
1336 else { /* Variable MTRRs */
1337 int idx, is_mtrr_mask;
1338 u64 *pt;
1339
1340 idx = (msr - 0x200) / 2;
1341 is_mtrr_mask = msr - 0x200 - 2 * idx;
1342 if (!is_mtrr_mask)
1343 pt =
1344 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1345 else
1346 pt =
1347 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1348 *pt = data;
1349 }
1350
1351 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1352 return 0;
1353}
15c4a640 1354
890ca9ae 1355static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1356{
890ca9ae
HY		 1357 u64 mcg_cap = vcpu->arch.mcg_cap;
1358 unsigned bank_num = mcg_cap & 0xff;
1359
15c4a640 1360 switch (msr) {
15c4a640 1361 case MSR_IA32_MCG_STATUS:
890ca9ae 1362 vcpu->arch.mcg_status = data;
15c4a640 1363 break;
c7ac679c 1364 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1365 if (!(mcg_cap & MCG_CTL_P))
1366 return 1;
1367 if (data != 0 && data != ~(u64)0)
1368 return -1;
1369 vcpu->arch.mcg_ctl = data;
1370 break;
1371 default:
1372 if (msr >= MSR_IA32_MC0_CTL &&
1373 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1374 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1375 /* only 0 or all 1s can be written to IA32_MCi_CTL
1376 * some Linux kernels though clear bit 10 in bank 4 to
1377 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1378 * this to avoid an uncatched #GP in the guest
1379 */
890ca9ae 1380 if ((offset & 0x3) == 0 &&
114be429 1381 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1382 return -1;
1383 vcpu->arch.mce_banks[offset] = data;
1384 break;
1385 }
1386 return 1;
1387 }
1388 return 0;
1389}
1390
ffde22ac
ES		 1391static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1392{
1393 struct kvm *kvm = vcpu->kvm;
1394 int lm = is_long_mode(vcpu);
1395 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1396 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1397 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1398 : kvm->arch.xen_hvm_config.blob_size_32;
1399 u32 page_num = data & ~PAGE_MASK;
1400 u64 page_addr = data & PAGE_MASK;
1401 u8 *page;
1402 int r;
1403
1404 r = -E2BIG;
1405 if (page_num >= blob_size)
1406 goto out;
1407 r = -ENOMEM;
ff5c2c03
SL		 1408 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1409 if (IS_ERR(page)) {
1410 r = PTR_ERR(page);
ffde22ac 1411 goto out;
ff5c2c03 1412 }
ffde22ac
ES		 1413 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1414 goto out_free;
1415 r = 0;
1416out_free:
1417 kfree(page);
1418out:
1419 return r;
1420}
1421
55cd8e5a
GN		 1422static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1423{
1424 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1425}
1426
1427static bool kvm_hv_msr_partition_wide(u32 msr)
1428{
1429 bool r = false;
1430 switch (msr) {
1431 case HV_X64_MSR_GUEST_OS_ID:
1432 case HV_X64_MSR_HYPERCALL:
1433 r = true;
1434 break;
1435 }
1436
1437 return r;
1438}
1439
1440static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1441{
1442 struct kvm *kvm = vcpu->kvm;
1443
1444 switch (msr) {
1445 case HV_X64_MSR_GUEST_OS_ID:
1446 kvm->arch.hv_guest_os_id = data;
1447 /* setting guest os id to zero disables hypercall page */
1448 if (!kvm->arch.hv_guest_os_id)
1449 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1450 break;
1451 case HV_X64_MSR_HYPERCALL: {
1452 u64 gfn;
1453 unsigned long addr;
1454 u8 instructions[4];
1455
1456 /* if guest os id is not set hypercall should remain disabled */
1457 if (!kvm->arch.hv_guest_os_id)
1458 break;
1459 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1460 kvm->arch.hv_hypercall = data;
1461 break;
1462 }
1463 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1464 addr = gfn_to_hva(kvm, gfn);
1465 if (kvm_is_error_hva(addr))
1466 return 1;
1467 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1468 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1469 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1470 return 1;
1471 kvm->arch.hv_hypercall = data;
1472 break;
1473 }
1474 default:
a737f256
CD		 1475 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1476 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1477 return 1;
1478 }
1479 return 0;
1480}
1481
1482static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1483{
10388a07
GN		 1484 switch (msr) {
1485 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1486 unsigned long addr;
55cd8e5a 1487
10388a07
GN		 1488 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1489 vcpu->arch.hv_vapic = data;
1490 break;
1491 }
1492 addr = gfn_to_hva(vcpu->kvm, data >>
1493 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1494 if (kvm_is_error_hva(addr))
1495 return 1;
8b0cedff 1496 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1497 return 1;
1498 vcpu->arch.hv_vapic = data;
1499 break;
1500 }
1501 case HV_X64_MSR_EOI:
1502 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1503 case HV_X64_MSR_ICR:
1504 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1505 case HV_X64_MSR_TPR:
1506 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1507 default:
a737f256
CD		 1508 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1509 "data 0x%llx\n", msr, data);
10388a07
GN		 1510 return 1;
1511 }
1512
1513 return 0;
55cd8e5a
GN		 1514}
1515
344d9588
GN		 1516static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1517{
1518 gpa_t gpa = data & ~0x3f;
1519
4a969980 1520 /* Bits 2:5 are reserved, Should be zero */
6adba527 1521 if (data & 0x3c)
344d9588
GN		 1522 return 1;
1523
1524 vcpu->arch.apf.msr_val = data;
1525
1526 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1527 kvm_clear_async_pf_completion_queue(vcpu);
1528 kvm_async_pf_hash_reset(vcpu);
1529 return 0;
1530 }
1531
1532 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1533 return 1;
1534
6adba527 1535 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1536 kvm_async_pf_wakeup_all(vcpu);
1537 return 0;
1538}
1539
12f9a48f
GC		 1540static void kvmclock_reset(struct kvm_vcpu *vcpu)
1541{
1542 if (vcpu->arch.time_page) {
1543 kvm_release_page_dirty(vcpu->arch.time_page);
1544 vcpu->arch.time_page = NULL;
1545 }
1546}
1547
c9aaa895
GC		 1548static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1549{
1550 u64 delta;
1551
1552 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1553 return;
1554
1555 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1556 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1557 vcpu->arch.st.accum_steal = delta;
1558}
1559
1560static void record_steal_time(struct kvm_vcpu *vcpu)
1561{
1562 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1563 return;
1564
1565 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1566 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1567 return;
1568
1569 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1570 vcpu->arch.st.steal.version += 2;
1571 vcpu->arch.st.accum_steal = 0;
1572
1573 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1574 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1575}
1576
15c4a640
CO		 1577int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1578{
5753785f
GN		 1579 bool pr = false;
1580
15c4a640 1581 switch (msr) {
15c4a640 1582 case MSR_EFER:
b69e8cae 1583 return set_efer(vcpu, data);
8f1589d9
AP		 1584 case MSR_K7_HWCR:
1585 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1586 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1587 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1588 if (data != 0) {
a737f256
CD		 1589 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1590 data);
8f1589d9
AP		 1591 return 1;
1592 }
15c4a640 1593 break;
f7c6d140
AP		 1594 case MSR_FAM10H_MMIO_CONF_BASE:
1595 if (data != 0) {
a737f256
CD		 1596 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1597 "0x%llx\n", data);
f7c6d140
AP		 1598 return 1;
1599 }
15c4a640 1600 break;
c323c0e5 1601 case MSR_AMD64_NB_CFG:
c7ac679c 1602 break;
b5e2fec0
AG		 1603 case MSR_IA32_DEBUGCTLMSR:
1604 if (!data) {
1605 /* We support the non-activated case already */
1606 break;
1607 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1608 /* Values other than LBR and BTF are vendor-specific,
1609 thus reserved and should throw a #GP */
1610 return 1;
1611 }
a737f256
CD		 1612 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1613 __func__, data);
b5e2fec0 1614 break;
15c4a640
CO		 1615 case MSR_IA32_UCODE_REV:
1616 case MSR_IA32_UCODE_WRITE:
61a6bd67 1617 case MSR_VM_HSAVE_PA:
6098ca93 1618 case MSR_AMD64_PATCH_LOADER:
15c4a640 1619 break;
9ba075a6
AK		 1620 case 0x200 ... 0x2ff:
1621 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1622 case MSR_IA32_APICBASE:
1623 kvm_set_apic_base(vcpu, data);
1624 break;
0105d1a5
GN		 1625 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1626 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1627 case MSR_IA32_TSCDEADLINE:
1628 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1629 break;
15c4a640 1630 case MSR_IA32_MISC_ENABLE:
ad312c7c 1631 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1632 break;
11c6bffa 1633 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1634 case MSR_KVM_WALL_CLOCK:
1635 vcpu->kvm->arch.wall_clock = data;
1636 kvm_write_wall_clock(vcpu->kvm, data);
1637 break;
11c6bffa 1638 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1639 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1640 kvmclock_reset(vcpu);
18068523
GOC		 1641
1642 vcpu->arch.time = data;
c285545f 1643 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1644
1645 /* we verify if the enable bit is set... */
1646 if (!(data & 1))
1647 break;
1648
1649 /* ...but clean it before doing the actual write */
1650 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1651
18068523
GOC		 1652 vcpu->arch.time_page =
1653 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523 1654
32cad84f 1655 if (is_error_page(vcpu->arch.time_page))
18068523 1656 vcpu->arch.time_page = NULL;
32cad84f 1657
18068523
GOC		 1658 break;
1659 }
344d9588
GN		 1660 case MSR_KVM_ASYNC_PF_EN:
1661 if (kvm_pv_enable_async_pf(vcpu, data))
1662 return 1;
1663 break;
c9aaa895
GC		 1664 case MSR_KVM_STEAL_TIME:
1665
1666 if (unlikely(!sched_info_on()))
1667 return 1;
1668
1669 if (data & KVM_STEAL_RESERVED_MASK)
1670 return 1;
1671
1672 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1673 data & KVM_STEAL_VALID_BITS))
1674 return 1;
1675
1676 vcpu->arch.st.msr_val = data;
1677
1678 if (!(data & KVM_MSR_ENABLED))
1679 break;
1680
1681 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1682
1683 preempt_disable();
1684 accumulate_steal_time(vcpu);
1685 preempt_enable();
1686
1687 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1688
1689 break;
ae7a2a3f
MT		 1690 case MSR_KVM_PV_EOI_EN:
1691 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1692 return 1;
1693 break;
c9aaa895 1694
890ca9ae
HY		 1695 case MSR_IA32_MCG_CTL:
1696 case MSR_IA32_MCG_STATUS:
1697 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1698 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1699
1700 /* Performance counters are not protected by a CPUID bit,
1701 * so we should check all of them in the generic path for the sake of
1702 * cross vendor migration.
1703 * Writing a zero into the event select MSRs disables them,
1704 * which we perfectly emulate ;-). Any other value should be at least
1705 * reported, some guests depend on them.
1706 */
71db6023
AP		 1707 case MSR_K7_EVNTSEL0:
1708 case MSR_K7_EVNTSEL1:
1709 case MSR_K7_EVNTSEL2:
1710 case MSR_K7_EVNTSEL3:
1711 if (data != 0)
a737f256
CD		 1712 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1713 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 1714 break;
1715 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1716 * so we ignore writes to make it happy.
1717 */
71db6023
AP		 1718 case MSR_K7_PERFCTR0:
1719 case MSR_K7_PERFCTR1:
1720 case MSR_K7_PERFCTR2:
1721 case MSR_K7_PERFCTR3:
a737f256
CD		 1722 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1723 "0x%x data 0x%llx\n", msr, data);
71db6023 1724 break;
5753785f
GN		 1725 case MSR_P6_PERFCTR0:
1726 case MSR_P6_PERFCTR1:
1727 pr = true;
1728 case MSR_P6_EVNTSEL0:
1729 case MSR_P6_EVNTSEL1:
1730 if (kvm_pmu_msr(vcpu, msr))
1731 return kvm_pmu_set_msr(vcpu, msr, data);
1732
1733 if (pr || data != 0)
a737f256
CD		 1734 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1735 "0x%x data 0x%llx\n", msr, data);
5753785f 1736 break;
84e0cefa
JS		 1737 case MSR_K7_CLK_CTL:
1738 /*
1739 * Ignore all writes to this no longer documented MSR.
1740 * Writes are only relevant for old K7 processors,
1741 * all pre-dating SVM, but a recommended workaround from
4a969980 1742 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 1743 * affected processor models on the command line, hence
1744 * the need to ignore the workaround.
1745 */
1746 break;
55cd8e5a
GN		 1747 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1748 if (kvm_hv_msr_partition_wide(msr)) {
1749 int r;
1750 mutex_lock(&vcpu->kvm->lock);
1751 r = set_msr_hyperv_pw(vcpu, msr, data);
1752 mutex_unlock(&vcpu->kvm->lock);
1753 return r;
1754 } else
1755 return set_msr_hyperv(vcpu, msr, data);
1756 break;
91c9c3ed 1757 case MSR_IA32_BBL_CR_CTL3:
1758 /* Drop writes to this legacy MSR -- see rdmsr
1759 * counterpart for further detail.
1760 */
a737f256 1761 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 1762 break;
2b036c6b
BO		 1763 case MSR_AMD64_OSVW_ID_LENGTH:
1764 if (!guest_cpuid_has_osvw(vcpu))
1765 return 1;
1766 vcpu->arch.osvw.length = data;
1767 break;
1768 case MSR_AMD64_OSVW_STATUS:
1769 if (!guest_cpuid_has_osvw(vcpu))
1770 return 1;
1771 vcpu->arch.osvw.status = data;
1772 break;
15c4a640 1773 default:
ffde22ac
ES		 1774 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1775 return xen_hvm_config(vcpu, data);
f5132b01
GN		 1776 if (kvm_pmu_msr(vcpu, msr))
1777 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068 1778 if (!ignore_msrs) {
a737f256
CD		 1779 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1780 msr, data);
ed85c068
AP		 1781 return 1;
1782 } else {
a737f256
CD		 1783 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1784 msr, data);
ed85c068
AP		 1785 break;
1786 }
15c4a640
CO		 1787 }
1788 return 0;
1789}
1790EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1791
1792
1793/*
1794 * Reads an msr value (of 'msr_index') into 'pdata'.
1795 * Returns 0 on success, non-0 otherwise.
1796 * Assumes vcpu_load() was already called.
1797 */
1798int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1799{
1800 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1801}
1802
9ba075a6
AK		 1803static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1804{
0bed3b56
SY		 1805 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1806
9ba075a6
AK		 1807 if (!msr_mtrr_valid(msr))
1808 return 1;
1809
0bed3b56
SY		 1810 if (msr == MSR_MTRRdefType)
1811 *pdata = vcpu->arch.mtrr_state.def_type +
1812 (vcpu->arch.mtrr_state.enabled << 10);
1813 else if (msr == MSR_MTRRfix64K_00000)
1814 *pdata = p[0];
1815 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1816 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1817 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1818 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1819 else if (msr == MSR_IA32_CR_PAT)
1820 *pdata = vcpu->arch.pat;
1821 else { /* Variable MTRRs */
1822 int idx, is_mtrr_mask;
1823 u64 *pt;
1824
1825 idx = (msr - 0x200) / 2;
1826 is_mtrr_mask = msr - 0x200 - 2 * idx;
1827 if (!is_mtrr_mask)
1828 pt =
1829 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1830 else
1831 pt =
1832 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1833 *pdata = *pt;
1834 }
1835
9ba075a6
AK		 1836 return 0;
1837}
1838
890ca9ae 1839static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1840{
1841 u64 data;
890ca9ae
HY		 1842 u64 mcg_cap = vcpu->arch.mcg_cap;
1843 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1844
1845 switch (msr) {
15c4a640
CO		 1846 case MSR_IA32_P5_MC_ADDR:
1847 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1848 data = 0;
1849 break;
15c4a640 1850 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1851 data = vcpu->arch.mcg_cap;
1852 break;
c7ac679c 1853 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1854 if (!(mcg_cap & MCG_CTL_P))
1855 return 1;
1856 data = vcpu->arch.mcg_ctl;
1857 break;
1858 case MSR_IA32_MCG_STATUS:
1859 data = vcpu->arch.mcg_status;
1860 break;
1861 default:
1862 if (msr >= MSR_IA32_MC0_CTL &&
1863 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1864 u32 offset = msr - MSR_IA32_MC0_CTL;
1865 data = vcpu->arch.mce_banks[offset];
1866 break;
1867 }
1868 return 1;
1869 }
1870 *pdata = data;
1871 return 0;
1872}
1873
55cd8e5a
GN		 1874static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1875{
1876 u64 data = 0;
1877 struct kvm *kvm = vcpu->kvm;
1878
1879 switch (msr) {
1880 case HV_X64_MSR_GUEST_OS_ID:
1881 data = kvm->arch.hv_guest_os_id;
1882 break;
1883 case HV_X64_MSR_HYPERCALL:
1884 data = kvm->arch.hv_hypercall;
1885 break;
1886 default:
a737f256 1887 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1888 return 1;
1889 }
1890
1891 *pdata = data;
1892 return 0;
1893}
1894
1895static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1896{
1897 u64 data = 0;
1898
1899 switch (msr) {
1900 case HV_X64_MSR_VP_INDEX: {
1901 int r;
1902 struct kvm_vcpu *v;
1903 kvm_for_each_vcpu(r, v, vcpu->kvm)
1904 if (v == vcpu)
1905 data = r;
1906 break;
1907 }
10388a07
GN		 1908 case HV_X64_MSR_EOI:
1909 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1910 case HV_X64_MSR_ICR:
1911 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1912 case HV_X64_MSR_TPR:
1913 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1914 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1915 data = vcpu->arch.hv_vapic;
1916 break;
55cd8e5a 1917 default:
a737f256 1918 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1919 return 1;
1920 }
1921 *pdata = data;
1922 return 0;
1923}
1924
890ca9ae
HY		 1925int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1926{
1927 u64 data;
1928
1929 switch (msr) {
890ca9ae 1930 case MSR_IA32_PLATFORM_ID:
15c4a640 1931 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1932 case MSR_IA32_DEBUGCTLMSR:
1933 case MSR_IA32_LASTBRANCHFROMIP:
1934 case MSR_IA32_LASTBRANCHTOIP:
1935 case MSR_IA32_LASTINTFROMIP:
1936 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1937 case MSR_K8_SYSCFG:
1938 case MSR_K7_HWCR:
61a6bd67 1939 case MSR_VM_HSAVE_PA:
9e699624 1940 case MSR_K7_EVNTSEL0:
1f3ee616 1941 case MSR_K7_PERFCTR0:
1fdbd48c 1942 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1943 case MSR_AMD64_NB_CFG:
f7c6d140 1944 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1945 data = 0;
1946 break;
5753785f
GN		 1947 case MSR_P6_PERFCTR0:
1948 case MSR_P6_PERFCTR1:
1949 case MSR_P6_EVNTSEL0:
1950 case MSR_P6_EVNTSEL1:
1951 if (kvm_pmu_msr(vcpu, msr))
1952 return kvm_pmu_get_msr(vcpu, msr, pdata);
1953 data = 0;
1954 break;
742bc670
MT		 1955 case MSR_IA32_UCODE_REV:
1956 data = 0x100000000ULL;
1957 break;
9ba075a6
AK		 1958 case MSR_MTRRcap:
1959 data = 0x500 | KVM_NR_VAR_MTRR;
1960 break;
1961 case 0x200 ... 0x2ff:
1962 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1963 case 0xcd: /* fsb frequency */
1964 data = 3;
1965 break;
7b914098
JS		 1966 /*
1967 * MSR_EBC_FREQUENCY_ID
1968 * Conservative value valid for even the basic CPU models.
1969 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1970 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1971 * and 266MHz for model 3, or 4. Set Core Clock
1972 * Frequency to System Bus Frequency Ratio to 1 (bits
1973 * 31:24) even though these are only valid for CPU
1974 * models > 2, however guests may end up dividing or
1975 * multiplying by zero otherwise.
1976 */
1977 case MSR_EBC_FREQUENCY_ID:
1978 data = 1 << 24;
1979 break;
15c4a640
CO		 1980 case MSR_IA32_APICBASE:
1981 data = kvm_get_apic_base(vcpu);
1982 break;
0105d1a5
GN		 1983 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1984 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1985 break;
a3e06bbe
LJ		 1986 case MSR_IA32_TSCDEADLINE:
1987 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1988 break;
15c4a640 1989 case MSR_IA32_MISC_ENABLE:
ad312c7c 1990 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1991 break;
847f0ad8
AG		 1992 case MSR_IA32_PERF_STATUS:
1993 /* TSC increment by tick */
1994 data = 1000ULL;
1995 /* CPU multiplier */
1996 data |= (((uint64_t)4ULL) << 40);
1997 break;
15c4a640 1998 case MSR_EFER:
f6801dff 1999 data = vcpu->arch.efer;
15c4a640 2000 break;
18068523 2001 case MSR_KVM_WALL_CLOCK:
11c6bffa 2002 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2003 data = vcpu->kvm->arch.wall_clock;
2004 break;
2005 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2006 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2007 data = vcpu->arch.time;
2008 break;
344d9588
GN		 2009 case MSR_KVM_ASYNC_PF_EN:
2010 data = vcpu->arch.apf.msr_val;
2011 break;
c9aaa895
GC		 2012 case MSR_KVM_STEAL_TIME:
2013 data = vcpu->arch.st.msr_val;
2014 break;
1d92128f
MT		 2015 case MSR_KVM_PV_EOI_EN:
2016 data = vcpu->arch.pv_eoi.msr_val;
2017 break;
890ca9ae
HY		 2018 case MSR_IA32_P5_MC_ADDR:
2019 case MSR_IA32_P5_MC_TYPE:
2020 case MSR_IA32_MCG_CAP:
2021 case MSR_IA32_MCG_CTL:
2022 case MSR_IA32_MCG_STATUS:
2023 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2024 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2025 case MSR_K7_CLK_CTL:
2026 /*
2027 * Provide expected ramp-up count for K7. All other
2028 * are set to zero, indicating minimum divisors for
2029 * every field.
2030 *
2031 * This prevents guest kernels on AMD host with CPU
2032 * type 6, model 8 and higher from exploding due to
2033 * the rdmsr failing.
2034 */
2035 data = 0x20000000;
2036 break;
55cd8e5a
GN		 2037 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2038 if (kvm_hv_msr_partition_wide(msr)) {
2039 int r;
2040 mutex_lock(&vcpu->kvm->lock);
2041 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2042 mutex_unlock(&vcpu->kvm->lock);
2043 return r;
2044 } else
2045 return get_msr_hyperv(vcpu, msr, pdata);
2046 break;
91c9c3ed 2047 case MSR_IA32_BBL_CR_CTL3:
2048 /* This legacy MSR exists but isn't fully documented in current
2049 * silicon. It is however accessed by winxp in very narrow
2050 * scenarios where it sets bit #19, itself documented as
2051 * a "reserved" bit. Best effort attempt to source coherent
2052 * read data here should the balance of the register be
2053 * interpreted by the guest:
2054 *
2055 * L2 cache control register 3: 64GB range, 256KB size,
2056 * enabled, latency 0x1, configured
2057 */
2058 data = 0xbe702111;
2059 break;
2b036c6b
BO		 2060 case MSR_AMD64_OSVW_ID_LENGTH:
2061 if (!guest_cpuid_has_osvw(vcpu))
2062 return 1;
2063 data = vcpu->arch.osvw.length;
2064 break;
2065 case MSR_AMD64_OSVW_STATUS:
2066 if (!guest_cpuid_has_osvw(vcpu))
2067 return 1;
2068 data = vcpu->arch.osvw.status;
2069 break;
15c4a640 2070 default:
f5132b01
GN		 2071 if (kvm_pmu_msr(vcpu, msr))
2072 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2073 if (!ignore_msrs) {
a737f256 2074 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2075 return 1;
2076 } else {
a737f256 2077 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2078 data = 0;
2079 }
2080 break;
15c4a640
CO		 2081 }
2082 *pdata = data;
2083 return 0;
2084}
2085EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2086
313a3dc7
CO		 2087/*
2088 * Read or write a bunch of msrs. All parameters are kernel addresses.
2089 *
2090 * @return number of msrs set successfully.
2091 */
2092static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2093 struct kvm_msr_entry *entries,
2094 int (*do_msr)(struct kvm_vcpu *vcpu,
2095 unsigned index, u64 *data))
2096{
f656ce01 2097 int i, idx;
313a3dc7 2098
f656ce01 2099 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2100 for (i = 0; i < msrs->nmsrs; ++i)
2101 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2102 break;
f656ce01 2103 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2104
313a3dc7
CO		 2105 return i;
2106}
2107
2108/*
2109 * Read or write a bunch of msrs. Parameters are user addresses.
2110 *
2111 * @return number of msrs set successfully.
2112 */
2113static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2114 int (*do_msr)(struct kvm_vcpu *vcpu,
2115 unsigned index, u64 *data),
2116 int writeback)
2117{
2118 struct kvm_msrs msrs;
2119 struct kvm_msr_entry *entries;
2120 int r, n;
2121 unsigned size;
2122
2123 r = -EFAULT;
2124 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2125 goto out;
2126
2127 r = -E2BIG;
2128 if (msrs.nmsrs >= MAX_IO_MSRS)
2129 goto out;
2130
313a3dc7 2131 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2132 entries = memdup_user(user_msrs->entries, size);
2133 if (IS_ERR(entries)) {
2134 r = PTR_ERR(entries);
313a3dc7 2135 goto out;
ff5c2c03 2136 }
313a3dc7
CO		 2137
2138 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2139 if (r < 0)
2140 goto out_free;
2141
2142 r = -EFAULT;
2143 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2144 goto out_free;
2145
2146 r = n;
2147
2148out_free:
7a73c028 2149 kfree(entries);
313a3dc7
CO		 2150out:
2151 return r;
2152}
2153
018d00d2
ZX		 2154int kvm_dev_ioctl_check_extension(long ext)
2155{
2156 int r;
2157
2158 switch (ext) {
2159 case KVM_CAP_IRQCHIP:
2160 case KVM_CAP_HLT:
2161 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2162 case KVM_CAP_SET_TSS_ADDR:
07716717 2163 case KVM_CAP_EXT_CPUID:
c8076604 2164 case KVM_CAP_CLOCKSOURCE:
7837699f 2165 case KVM_CAP_PIT:
a28e4f5a 2166 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2167 case KVM_CAP_MP_STATE:
ed848624 2168 case KVM_CAP_SYNC_MMU:
a355c85c 2169 case KVM_CAP_USER_NMI:
52d939a0 2170 case KVM_CAP_REINJECT_CONTROL:
4925663a 2171 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2172 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2173 case KVM_CAP_IRQFD:
d34e6b17 2174 case KVM_CAP_IOEVENTFD:
c5ff41ce 2175 case KVM_CAP_PIT2:
e9f42757 2176 case KVM_CAP_PIT_STATE2:
b927a3ce 2177 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2178 case KVM_CAP_XEN_HVM:
afbcf7ab 2179 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2180 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2181 case KVM_CAP_HYPERV:
10388a07 2182 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2183 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2184 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2185 case KVM_CAP_DEBUGREGS:
d2be1651 2186 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2187 case KVM_CAP_XSAVE:
344d9588 2188 case KVM_CAP_ASYNC_PF:
92a1f12d 2189 case KVM_CAP_GET_TSC_KHZ:
07700a94 2190 case KVM_CAP_PCI_2_3:
1c0b28c2 2191 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2192 case KVM_CAP_READONLY_MEM:
7a84428a 2193 case KVM_CAP_IRQFD_RESAMPLE:
018d00d2
ZX		 2194 r = 1;
2195 break;
542472b5
LV		 2196 case KVM_CAP_COALESCED_MMIO:
2197 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2198 break;
774ead3a
AK		 2199 case KVM_CAP_VAPIC:
2200 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2201 break;
f725230a 2202 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2203 r = KVM_SOFT_MAX_VCPUS;
2204 break;
2205 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2206 r = KVM_MAX_VCPUS;
2207 break;
a988b910
AK		 2208 case KVM_CAP_NR_MEMSLOTS:
2209 r = KVM_MEMORY_SLOTS;
2210 break;
a68a6a72
MT		 2211 case KVM_CAP_PV_MMU: /* obsolete */
2212 r = 0;
2f333bcb 2213 break;
62c476c7 2214 case KVM_CAP_IOMMU:
a1b60c1c 2215 r = iommu_present(&pci_bus_type);
62c476c7 2216 break;
890ca9ae
HY		 2217 case KVM_CAP_MCE:
2218 r = KVM_MAX_MCE_BANKS;
2219 break;
2d5b5a66
SY		 2220 case KVM_CAP_XCRS:
2221 r = cpu_has_xsave;
2222 break;
92a1f12d
JR		 2223 case KVM_CAP_TSC_CONTROL:
2224 r = kvm_has_tsc_control;
2225 break;
4d25a066
JK		 2226 case KVM_CAP_TSC_DEADLINE_TIMER:
2227 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2228 break;
018d00d2
ZX		 2229 default:
2230 r = 0;
2231 break;
2232 }
2233 return r;
2234
2235}
2236
043405e1
CO		 2237long kvm_arch_dev_ioctl(struct file *filp,
2238 unsigned int ioctl, unsigned long arg)
2239{
2240 void __user *argp = (void __user *)arg;
2241 long r;
2242
2243 switch (ioctl) {
2244 case KVM_GET_MSR_INDEX_LIST: {
2245 struct kvm_msr_list __user *user_msr_list = argp;
2246 struct kvm_msr_list msr_list;
2247 unsigned n;
2248
2249 r = -EFAULT;
2250 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2251 goto out;
2252 n = msr_list.nmsrs;
2253 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2254 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2255 goto out;
2256 r = -E2BIG;
e125e7b6 2257 if (n < msr_list.nmsrs)
043405e1
CO		 2258 goto out;
2259 r = -EFAULT;
2260 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2261 num_msrs_to_save * sizeof(u32)))
2262 goto out;
e125e7b6 2263 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2264 &emulated_msrs,
2265 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2266 goto out;
2267 r = 0;
2268 break;
2269 }
674eea0f
AK		 2270 case KVM_GET_SUPPORTED_CPUID: {
2271 struct kvm_cpuid2 __user *cpuid_arg = argp;
2272 struct kvm_cpuid2 cpuid;
2273
2274 r = -EFAULT;
2275 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2276 goto out;
2277 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2278 cpuid_arg->entries);
674eea0f
AK		 2279 if (r)
2280 goto out;
2281
2282 r = -EFAULT;
2283 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2284 goto out;
2285 r = 0;
2286 break;
2287 }
890ca9ae
HY		 2288 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2289 u64 mce_cap;
2290
2291 mce_cap = KVM_MCE_CAP_SUPPORTED;
2292 r = -EFAULT;
2293 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2294 goto out;
2295 r = 0;
2296 break;
2297 }
043405e1
CO		 2298 default:
2299 r = -EINVAL;
2300 }
2301out:
2302 return r;
2303}
2304
f5f48ee1
SY		 2305static void wbinvd_ipi(void *garbage)
2306{
2307 wbinvd();
2308}
2309
2310static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2311{
2312 return vcpu->kvm->arch.iommu_domain &&
2313 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2314}
2315
313a3dc7
CO		 2316void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2317{
f5f48ee1
SY		 2318 /* Address WBINVD may be executed by guest */
2319 if (need_emulate_wbinvd(vcpu)) {
2320 if (kvm_x86_ops->has_wbinvd_exit())
2321 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2322 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2323 smp_call_function_single(vcpu->cpu,
2324 wbinvd_ipi, NULL, 1);
2325 }
2326
313a3dc7 2327 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2328
0dd6a6ed
ZA		 2329 /* Apply any externally detected TSC adjustments (due to suspend) */
2330 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2331 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2332 vcpu->arch.tsc_offset_adjustment = 0;
2333 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2334 }
8f6055cb 2335
48434c20 2336 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2337 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2338 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2339 if (tsc_delta < 0)
2340 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2341 if (check_tsc_unstable()) {
b183aa58
ZA		 2342 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2343 vcpu->arch.last_guest_tsc);
2344 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2345 vcpu->arch.tsc_catchup = 1;
c285545f 2346 }
1aa8ceef 2347 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2348 if (vcpu->cpu != cpu)
2349 kvm_migrate_timers(vcpu);
e48672fa 2350 vcpu->cpu = cpu;
6b7d7e76 2351 }
c9aaa895
GC		 2352
2353 accumulate_steal_time(vcpu);
2354 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2355}
2356
2357void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2358{
02daab21 2359 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2360 kvm_put_guest_fpu(vcpu);
6f526ec5 2361 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2362}
2363
313a3dc7
CO		 2364static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2365 struct kvm_lapic_state *s)
2366{
ad312c7c 2367 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2368
2369 return 0;
2370}
2371
2372static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2373 struct kvm_lapic_state *s)
2374{
64eb0620 2375 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2376 update_cr8_intercept(vcpu);
313a3dc7
CO		 2377
2378 return 0;
2379}
2380
f77bc6a4
ZX		 2381static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2382 struct kvm_interrupt *irq)
2383{
a50abc3b 2384 if (irq->irq < 0 || irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2385 return -EINVAL;
2386 if (irqchip_in_kernel(vcpu->kvm))
2387 return -ENXIO;
f77bc6a4 2388
66fd3f7f 2389 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2390 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2391
f77bc6a4
ZX		 2392 return 0;
2393}
2394
c4abb7c9
JK		 2395static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2396{
c4abb7c9 2397 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2398
2399 return 0;
2400}
2401
b209749f
AK		 2402static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2403 struct kvm_tpr_access_ctl *tac)
2404{
2405 if (tac->flags)
2406 return -EINVAL;
2407 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2408 return 0;
2409}
2410
890ca9ae
HY		 2411static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2412 u64 mcg_cap)
2413{
2414 int r;
2415 unsigned bank_num = mcg_cap & 0xff, bank;
2416
2417 r = -EINVAL;
a9e38c3e 2418 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2419 goto out;
2420 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2421 goto out;
2422 r = 0;
2423 vcpu->arch.mcg_cap = mcg_cap;
2424 /* Init IA32_MCG_CTL to all 1s */
2425 if (mcg_cap & MCG_CTL_P)
2426 vcpu->arch.mcg_ctl = ~(u64)0;
2427 /* Init IA32_MCi_CTL to all 1s */
2428 for (bank = 0; bank < bank_num; bank++)
2429 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2430out:
2431 return r;
2432}
2433
2434static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2435 struct kvm_x86_mce *mce)
2436{
2437 u64 mcg_cap = vcpu->arch.mcg_cap;
2438 unsigned bank_num = mcg_cap & 0xff;
2439 u64 *banks = vcpu->arch.mce_banks;
2440
2441 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2442 return -EINVAL;
2443 /*
2444 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2445 * reporting is disabled
2446 */
2447 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2448 vcpu->arch.mcg_ctl != ~(u64)0)
2449 return 0;
2450 banks += 4 * mce->bank;
2451 /*
2452 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2453 * reporting is disabled for the bank
2454 */
2455 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2456 return 0;
2457 if (mce->status & MCI_STATUS_UC) {
2458 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2459 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2460 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2461 return 0;
2462 }
2463 if (banks[1] & MCI_STATUS_VAL)
2464 mce->status |= MCI_STATUS_OVER;
2465 banks[2] = mce->addr;
2466 banks[3] = mce->misc;
2467 vcpu->arch.mcg_status = mce->mcg_status;
2468 banks[1] = mce->status;
2469 kvm_queue_exception(vcpu, MC_VECTOR);
2470 } else if (!(banks[1] & MCI_STATUS_VAL)
2471 || !(banks[1] & MCI_STATUS_UC)) {
2472 if (banks[1] & MCI_STATUS_VAL)
2473 mce->status |= MCI_STATUS_OVER;
2474 banks[2] = mce->addr;
2475 banks[3] = mce->misc;
2476 banks[1] = mce->status;
2477 } else
2478 banks[1] |= MCI_STATUS_OVER;
2479 return 0;
2480}
2481
3cfc3092
JK		 2482static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2483 struct kvm_vcpu_events *events)
2484{
7460fb4a 2485 process_nmi(vcpu);
03b82a30
JK		 2486 events->exception.injected =
2487 vcpu->arch.exception.pending &&
2488 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2489 events->exception.nr = vcpu->arch.exception.nr;
2490 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2491 events->exception.pad = 0;
3cfc3092
JK		 2492 events->exception.error_code = vcpu->arch.exception.error_code;
2493
03b82a30
JK		 2494 events->interrupt.injected =
2495 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2496 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2497 events->interrupt.soft = 0;
48005f64
JK		 2498 events->interrupt.shadow =
2499 kvm_x86_ops->get_interrupt_shadow(vcpu,
2500 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2501
2502 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2503 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2504 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2505 events->nmi.pad = 0;
3cfc3092
JK		 2506
2507 events->sipi_vector = vcpu->arch.sipi_vector;
2508
dab4b911 2509 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2510 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2511 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2512 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2513}
2514
2515static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2516 struct kvm_vcpu_events *events)
2517{
dab4b911 2518 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2519 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2520 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2521 return -EINVAL;
2522
7460fb4a 2523 process_nmi(vcpu);
3cfc3092
JK		 2524 vcpu->arch.exception.pending = events->exception.injected;
2525 vcpu->arch.exception.nr = events->exception.nr;
2526 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2527 vcpu->arch.exception.error_code = events->exception.error_code;
2528
2529 vcpu->arch.interrupt.pending = events->interrupt.injected;
2530 vcpu->arch.interrupt.nr = events->interrupt.nr;
2531 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2532 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2533 kvm_x86_ops->set_interrupt_shadow(vcpu,
2534 events->interrupt.shadow);
3cfc3092
JK		 2535
2536 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2537 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2538 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2539 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2540
dab4b911
JK		 2541 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2542 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2543
3842d135
AK		 2544 kvm_make_request(KVM_REQ_EVENT, vcpu);
2545
3cfc3092
JK		 2546 return 0;
2547}
2548
a1efbe77
JK		 2549static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2550 struct kvm_debugregs *dbgregs)
2551{
a1efbe77
JK		 2552 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2553 dbgregs->dr6 = vcpu->arch.dr6;
2554 dbgregs->dr7 = vcpu->arch.dr7;
2555 dbgregs->flags = 0;
97e69aa6 2556 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2557}
2558
2559static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2560 struct kvm_debugregs *dbgregs)
2561{
2562 if (dbgregs->flags)
2563 return -EINVAL;
2564
a1efbe77
JK		 2565 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2566 vcpu->arch.dr6 = dbgregs->dr6;
2567 vcpu->arch.dr7 = dbgregs->dr7;
2568
a1efbe77
JK		 2569 return 0;
2570}
2571
2d5b5a66
SY		 2572static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2573 struct kvm_xsave *guest_xsave)
2574{
2575 if (cpu_has_xsave)
2576 memcpy(guest_xsave->region,
2577 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2578 xstate_size);
2d5b5a66
SY		 2579 else {
2580 memcpy(guest_xsave->region,
2581 &vcpu->arch.guest_fpu.state->fxsave,
2582 sizeof(struct i387_fxsave_struct));
2583 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2584 XSTATE_FPSSE;
2585 }
2586}
2587
2588static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2589 struct kvm_xsave *guest_xsave)
2590{
2591 u64 xstate_bv =
2592 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2593
2594 if (cpu_has_xsave)
2595 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2596 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2597 else {
2598 if (xstate_bv & ~XSTATE_FPSSE)
2599 return -EINVAL;
2600 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2601 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2602 }
2603 return 0;
2604}
2605
2606static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2607 struct kvm_xcrs *guest_xcrs)
2608{
2609 if (!cpu_has_xsave) {
2610 guest_xcrs->nr_xcrs = 0;
2611 return;
2612 }
2613
2614 guest_xcrs->nr_xcrs = 1;
2615 guest_xcrs->flags = 0;
2616 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2617 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2618}
2619
2620static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2621 struct kvm_xcrs *guest_xcrs)
2622{
2623 int i, r = 0;
2624
2625 if (!cpu_has_xsave)
2626 return -EINVAL;
2627
2628 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2629 return -EINVAL;
2630
2631 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2632 /* Only support XCR0 currently */
2633 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2634 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2635 guest_xcrs->xcrs[0].value);
2636 break;
2637 }
2638 if (r)
2639 r = -EINVAL;
2640 return r;
2641}
2642
1c0b28c2
EM		 2643/*
2644 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2645 * stopped by the hypervisor. This function will be called from the host only.
2646 * EINVAL is returned when the host attempts to set the flag for a guest that
2647 * does not support pv clocks.
2648 */
2649static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2650{
1c0b28c2
EM		 2651 if (!vcpu->arch.time_page)
2652 return -EINVAL;
51d59c6b 2653 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 2654 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2655 return 0;
2656}
2657
313a3dc7
CO		 2658long kvm_arch_vcpu_ioctl(struct file *filp,
2659 unsigned int ioctl, unsigned long arg)
2660{
2661 struct kvm_vcpu *vcpu = filp->private_data;
2662 void __user *argp = (void __user *)arg;
2663 int r;
d1ac91d8
AK		 2664 union {
2665 struct kvm_lapic_state *lapic;
2666 struct kvm_xsave *xsave;
2667 struct kvm_xcrs *xcrs;
2668 void *buffer;
2669 } u;
2670
2671 u.buffer = NULL;
313a3dc7
CO		 2672 switch (ioctl) {
2673 case KVM_GET_LAPIC: {
2204ae3c
MT		 2674 r = -EINVAL;
2675 if (!vcpu->arch.apic)
2676 goto out;
d1ac91d8 2677 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2678
b772ff36 2679 r = -ENOMEM;
d1ac91d8 2680 if (!u.lapic)
b772ff36 2681 goto out;
d1ac91d8 2682 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2683 if (r)
2684 goto out;
2685 r = -EFAULT;
d1ac91d8 2686 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2687 goto out;
2688 r = 0;
2689 break;
2690 }
2691 case KVM_SET_LAPIC: {
2204ae3c
MT		 2692 if (!vcpu->arch.apic)
2693 goto out;
ff5c2c03 2694 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 2695 if (IS_ERR(u.lapic))
2696 return PTR_ERR(u.lapic);
ff5c2c03 2697
d1ac91d8 2698 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2699 break;
2700 }
f77bc6a4
ZX		 2701 case KVM_INTERRUPT: {
2702 struct kvm_interrupt irq;
2703
2704 r = -EFAULT;
2705 if (copy_from_user(&irq, argp, sizeof irq))
2706 goto out;
2707 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 2708 break;
2709 }
c4abb7c9
JK		 2710 case KVM_NMI: {
2711 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 2712 break;
2713 }
313a3dc7
CO		 2714 case KVM_SET_CPUID: {
2715 struct kvm_cpuid __user *cpuid_arg = argp;
2716 struct kvm_cpuid cpuid;
2717
2718 r = -EFAULT;
2719 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2720 goto out;
2721 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 2722 break;
2723 }
07716717
DK		 2724 case KVM_SET_CPUID2: {
2725 struct kvm_cpuid2 __user *cpuid_arg = argp;
2726 struct kvm_cpuid2 cpuid;
2727
2728 r = -EFAULT;
2729 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2730 goto out;
2731 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2732 cpuid_arg->entries);
07716717
DK		 2733 break;
2734 }
2735 case KVM_GET_CPUID2: {
2736 struct kvm_cpuid2 __user *cpuid_arg = argp;
2737 struct kvm_cpuid2 cpuid;
2738
2739 r = -EFAULT;
2740 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2741 goto out;
2742 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2743 cpuid_arg->entries);
07716717
DK		 2744 if (r)
2745 goto out;
2746 r = -EFAULT;
2747 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2748 goto out;
2749 r = 0;
2750 break;
2751 }
313a3dc7
CO		 2752 case KVM_GET_MSRS:
2753 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2754 break;
2755 case KVM_SET_MSRS:
2756 r = msr_io(vcpu, argp, do_set_msr, 0);
2757 break;
b209749f
AK		 2758 case KVM_TPR_ACCESS_REPORTING: {
2759 struct kvm_tpr_access_ctl tac;
2760
2761 r = -EFAULT;
2762 if (copy_from_user(&tac, argp, sizeof tac))
2763 goto out;
2764 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2765 if (r)
2766 goto out;
2767 r = -EFAULT;
2768 if (copy_to_user(argp, &tac, sizeof tac))
2769 goto out;
2770 r = 0;
2771 break;
2772 };
b93463aa
AK		 2773 case KVM_SET_VAPIC_ADDR: {
2774 struct kvm_vapic_addr va;
2775
2776 r = -EINVAL;
2777 if (!irqchip_in_kernel(vcpu->kvm))
2778 goto out;
2779 r = -EFAULT;
2780 if (copy_from_user(&va, argp, sizeof va))
2781 goto out;
2782 r = 0;
2783 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2784 break;
2785 }
890ca9ae
HY		 2786 case KVM_X86_SETUP_MCE: {
2787 u64 mcg_cap;
2788
2789 r = -EFAULT;
2790 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2791 goto out;
2792 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2793 break;
2794 }
2795 case KVM_X86_SET_MCE: {
2796 struct kvm_x86_mce mce;
2797
2798 r = -EFAULT;
2799 if (copy_from_user(&mce, argp, sizeof mce))
2800 goto out;
2801 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2802 break;
2803 }
3cfc3092
JK		 2804 case KVM_GET_VCPU_EVENTS: {
2805 struct kvm_vcpu_events events;
2806
2807 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2808
2809 r = -EFAULT;
2810 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2811 break;
2812 r = 0;
2813 break;
2814 }
2815 case KVM_SET_VCPU_EVENTS: {
2816 struct kvm_vcpu_events events;
2817
2818 r = -EFAULT;
2819 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2820 break;
2821
2822 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2823 break;
2824 }
a1efbe77
JK		 2825 case KVM_GET_DEBUGREGS: {
2826 struct kvm_debugregs dbgregs;
2827
2828 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2829
2830 r = -EFAULT;
2831 if (copy_to_user(argp, &dbgregs,
2832 sizeof(struct kvm_debugregs)))
2833 break;
2834 r = 0;
2835 break;
2836 }
2837 case KVM_SET_DEBUGREGS: {
2838 struct kvm_debugregs dbgregs;
2839
2840 r = -EFAULT;
2841 if (copy_from_user(&dbgregs, argp,
2842 sizeof(struct kvm_debugregs)))
2843 break;
2844
2845 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2846 break;
2847 }
2d5b5a66 2848 case KVM_GET_XSAVE: {
d1ac91d8 2849 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2850 r = -ENOMEM;
d1ac91d8 2851 if (!u.xsave)
2d5b5a66
SY		 2852 break;
2853
d1ac91d8 2854 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2855
2856 r = -EFAULT;
d1ac91d8 2857 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2858 break;
2859 r = 0;
2860 break;
2861 }
2862 case KVM_SET_XSAVE: {
ff5c2c03 2863 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 2864 if (IS_ERR(u.xsave))
2865 return PTR_ERR(u.xsave);
2d5b5a66 2866
d1ac91d8 2867 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2868 break;
2869 }
2870 case KVM_GET_XCRS: {
d1ac91d8 2871 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2872 r = -ENOMEM;
d1ac91d8 2873 if (!u.xcrs)
2d5b5a66
SY		 2874 break;
2875
d1ac91d8 2876 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2877
2878 r = -EFAULT;
d1ac91d8 2879 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2880 sizeof(struct kvm_xcrs)))
2881 break;
2882 r = 0;
2883 break;
2884 }
2885 case KVM_SET_XCRS: {
ff5c2c03 2886 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 2887 if (IS_ERR(u.xcrs))
2888 return PTR_ERR(u.xcrs);
2d5b5a66 2889
d1ac91d8 2890 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2891 break;
2892 }
92a1f12d
JR		 2893 case KVM_SET_TSC_KHZ: {
2894 u32 user_tsc_khz;
2895
2896 r = -EINVAL;
92a1f12d
JR		 2897 user_tsc_khz = (u32)arg;
2898
2899 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2900 goto out;
2901
cc578287
ZA		 2902 if (user_tsc_khz == 0)
2903 user_tsc_khz = tsc_khz;
2904
2905 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 2906
2907 r = 0;
2908 goto out;
2909 }
2910 case KVM_GET_TSC_KHZ: {
cc578287 2911 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 2912 goto out;
2913 }
1c0b28c2
EM		 2914 case KVM_KVMCLOCK_CTRL: {
2915 r = kvm_set_guest_paused(vcpu);
2916 goto out;
2917 }
313a3dc7
CO		 2918 default:
2919 r = -EINVAL;
2920 }
2921out:
d1ac91d8 2922 kfree(u.buffer);
313a3dc7
CO		 2923 return r;
2924}
2925
5b1c1493
CO		 2926int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2927{
2928 return VM_FAULT_SIGBUS;
2929}
2930
1fe779f8
CO		 2931static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2932{
2933 int ret;
2934
2935 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 2936 return -EINVAL;
1fe779f8
CO		 2937 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2938 return ret;
2939}
2940
b927a3ce
SY		 2941static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2942 u64 ident_addr)
2943{
2944 kvm->arch.ept_identity_map_addr = ident_addr;
2945 return 0;
2946}
2947
1fe779f8
CO		 2948static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2949 u32 kvm_nr_mmu_pages)
2950{
2951 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2952 return -EINVAL;
2953
79fac95e 2954 mutex_lock(&kvm->slots_lock);
7c8a83b7 2955 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2956
2957 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2958 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2959
7c8a83b7 2960 spin_unlock(&kvm->mmu_lock);
79fac95e 2961 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2962 return 0;
2963}
2964
2965static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2966{
39de71ec 2967 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2968}
2969
1fe779f8
CO		 2970static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2971{
2972 int r;
2973
2974 r = 0;
2975 switch (chip->chip_id) {
2976 case KVM_IRQCHIP_PIC_MASTER:
2977 memcpy(&chip->chip.pic,
2978 &pic_irqchip(kvm)->pics[0],
2979 sizeof(struct kvm_pic_state));
2980 break;
2981 case KVM_IRQCHIP_PIC_SLAVE:
2982 memcpy(&chip->chip.pic,
2983 &pic_irqchip(kvm)->pics[1],
2984 sizeof(struct kvm_pic_state));
2985 break;
2986 case KVM_IRQCHIP_IOAPIC:
eba0226b 2987 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2988 break;
2989 default:
2990 r = -EINVAL;
2991 break;
2992 }
2993 return r;
2994}
2995
2996static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2997{
2998 int r;
2999
3000 r = 0;
3001 switch (chip->chip_id) {
3002 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3003 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3004 memcpy(&pic_irqchip(kvm)->pics[0],
3005 &chip->chip.pic,
3006 sizeof(struct kvm_pic_state));
f4f51050 3007 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3008 break;
3009 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3010 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3011 memcpy(&pic_irqchip(kvm)->pics[1],
3012 &chip->chip.pic,
3013 sizeof(struct kvm_pic_state));
f4f51050 3014 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3015 break;
3016 case KVM_IRQCHIP_IOAPIC:
eba0226b 3017 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3018 break;
3019 default:
3020 r = -EINVAL;
3021 break;
3022 }
3023 kvm_pic_update_irq(pic_irqchip(kvm));
3024 return r;
3025}
3026
e0f63cb9
SY		 3027static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3028{
3029 int r = 0;
3030
894a9c55 3031 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3032 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3033 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3034 return r;
3035}
3036
3037static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3038{
3039 int r = 0;
3040
894a9c55 3041 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3042 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3043 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3044 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3045 return r;
3046}
3047
3048static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3049{
3050 int r = 0;
3051
3052 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3053 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3054 sizeof(ps->channels));
3055 ps->flags = kvm->arch.vpit->pit_state.flags;
3056 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3057 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3058 return r;
3059}
3060
3061static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3062{
3063 int r = 0, start = 0;
3064 u32 prev_legacy, cur_legacy;
3065 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3066 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3067 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3068 if (!prev_legacy && cur_legacy)
3069 start = 1;
3070 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3071 sizeof(kvm->arch.vpit->pit_state.channels));
3072 kvm->arch.vpit->pit_state.flags = ps->flags;
3073 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3074 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3075 return r;
3076}
3077
52d939a0
MT		 3078static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3079 struct kvm_reinject_control *control)
3080{
3081 if (!kvm->arch.vpit)
3082 return -ENXIO;
894a9c55 3083 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3084 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3085 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3086 return 0;
3087}
3088
95d4c16c 3089/**
60c34612
TY		 3090 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3091 * @kvm: kvm instance
3092 * @log: slot id and address to which we copy the log
95d4c16c 3093 *
60c34612
TY		 3094 * We need to keep it in mind that VCPU threads can write to the bitmap
3095 * concurrently. So, to avoid losing data, we keep the following order for
3096 * each bit:
95d4c16c 3097 *
60c34612
TY		 3098 * 1. Take a snapshot of the bit and clear it if needed.
3099 * 2. Write protect the corresponding page.
3100 * 3. Flush TLB's if needed.
3101 * 4. Copy the snapshot to the userspace.
95d4c16c 3102 *
60c34612
TY		 3103 * Between 2 and 3, the guest may write to the page using the remaining TLB
3104 * entry. This is not a problem because the page will be reported dirty at
3105 * step 4 using the snapshot taken before and step 3 ensures that successive
3106 * writes will be logged for the next call.
5bb064dc 3107 */
60c34612 3108int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3109{
7850ac54 3110 int r;
5bb064dc 3111 struct kvm_memory_slot *memslot;
60c34612
TY		 3112 unsigned long n, i;
3113 unsigned long *dirty_bitmap;
3114 unsigned long *dirty_bitmap_buffer;
3115 bool is_dirty = false;
5bb064dc 3116
79fac95e 3117 mutex_lock(&kvm->slots_lock);
5bb064dc 3118
b050b015
MT		 3119 r = -EINVAL;
3120 if (log->slot >= KVM_MEMORY_SLOTS)
3121 goto out;
3122
28a37544 3123 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3124
3125 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3126 r = -ENOENT;
60c34612 3127 if (!dirty_bitmap)
b050b015
MT		 3128 goto out;
3129
87bf6e7d 3130 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3131
60c34612
TY		 3132 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3133 memset(dirty_bitmap_buffer, 0, n);
b050b015 3134
60c34612 3135 spin_lock(&kvm->mmu_lock);
b050b015 3136
60c34612
TY		 3137 for (i = 0; i < n / sizeof(long); i++) {
3138 unsigned long mask;
3139 gfn_t offset;
cdfca7b3 3140
60c34612
TY		 3141 if (!dirty_bitmap[i])
3142 continue;
b050b015 3143
60c34612 3144 is_dirty = true;
914ebccd 3145
60c34612
TY		 3146 mask = xchg(&dirty_bitmap[i], 0);
3147 dirty_bitmap_buffer[i] = mask;
edde99ce 3148
60c34612
TY		 3149 offset = i * BITS_PER_LONG;
3150 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3151 }
60c34612
TY		 3152 if (is_dirty)
3153 kvm_flush_remote_tlbs(kvm);
3154
3155 spin_unlock(&kvm->mmu_lock);
3156
3157 r = -EFAULT;
3158 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3159 goto out;
b050b015 3160
5bb064dc
ZX		 3161 r = 0;
3162out:
79fac95e 3163 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3164 return r;
3165}
3166
23d43cf9
CD		 3167int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3168{
3169 if (!irqchip_in_kernel(kvm))
3170 return -ENXIO;
3171
3172 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3173 irq_event->irq, irq_event->level);
3174 return 0;
3175}
3176
1fe779f8
CO		 3177long kvm_arch_vm_ioctl(struct file *filp,
3178 unsigned int ioctl, unsigned long arg)
3179{
3180 struct kvm *kvm = filp->private_data;
3181 void __user *argp = (void __user *)arg;
367e1319 3182 int r = -ENOTTY;
f0d66275
DH		 3183 /*
3184 * This union makes it completely explicit to gcc-3.x
3185 * that these two variables' stack usage should be
3186 * combined, not added together.
3187 */
3188 union {
3189 struct kvm_pit_state ps;
e9f42757 3190 struct kvm_pit_state2 ps2;
c5ff41ce 3191 struct kvm_pit_config pit_config;
f0d66275 3192 } u;
1fe779f8
CO		 3193
3194 switch (ioctl) {
3195 case KVM_SET_TSS_ADDR:
3196 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3197 break;
b927a3ce
SY		 3198 case KVM_SET_IDENTITY_MAP_ADDR: {
3199 u64 ident_addr;
3200
3201 r = -EFAULT;
3202 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3203 goto out;
3204 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3205 break;
3206 }
1fe779f8
CO		 3207 case KVM_SET_NR_MMU_PAGES:
3208 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3209 break;
3210 case KVM_GET_NR_MMU_PAGES:
3211 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3212 break;
3ddea128
MT		 3213 case KVM_CREATE_IRQCHIP: {
3214 struct kvm_pic *vpic;
3215
3216 mutex_lock(&kvm->lock);
3217 r = -EEXIST;
3218 if (kvm->arch.vpic)
3219 goto create_irqchip_unlock;
3e515705
AK		 3220 r = -EINVAL;
3221 if (atomic_read(&kvm->online_vcpus))
3222 goto create_irqchip_unlock;
1fe779f8 3223 r = -ENOMEM;
3ddea128
MT		 3224 vpic = kvm_create_pic(kvm);
3225 if (vpic) {
1fe779f8
CO		 3226 r = kvm_ioapic_init(kvm);
3227 if (r) {
175504cd 3228 mutex_lock(&kvm->slots_lock);
72bb2fcd 3229 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3230 &vpic->dev_master);
3231 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3232 &vpic->dev_slave);
3233 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3234 &vpic->dev_eclr);
175504cd 3235 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3236 kfree(vpic);
3237 goto create_irqchip_unlock;
1fe779f8
CO		 3238 }
3239 } else
3ddea128
MT		 3240 goto create_irqchip_unlock;
3241 smp_wmb();
3242 kvm->arch.vpic = vpic;
3243 smp_wmb();
399ec807
AK		 3244 r = kvm_setup_default_irq_routing(kvm);
3245 if (r) {
175504cd 3246 mutex_lock(&kvm->slots_lock);
3ddea128 3247 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3248 kvm_ioapic_destroy(kvm);
3249 kvm_destroy_pic(kvm);
3ddea128 3250 mutex_unlock(&kvm->irq_lock);
175504cd 3251 mutex_unlock(&kvm->slots_lock);
399ec807 3252 }
3ddea128
MT		 3253 create_irqchip_unlock:
3254 mutex_unlock(&kvm->lock);
1fe779f8 3255 break;
3ddea128 3256 }
7837699f 3257 case KVM_CREATE_PIT:
c5ff41ce
JK		 3258 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3259 goto create_pit;
3260 case KVM_CREATE_PIT2:
3261 r = -EFAULT;
3262 if (copy_from_user(&u.pit_config, argp,
3263 sizeof(struct kvm_pit_config)))
3264 goto out;
3265 create_pit:
79fac95e 3266 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3267 r = -EEXIST;
3268 if (kvm->arch.vpit)
3269 goto create_pit_unlock;
7837699f 3270 r = -ENOMEM;
c5ff41ce 3271 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3272 if (kvm->arch.vpit)
3273 r = 0;
269e05e4 3274 create_pit_unlock:
79fac95e 3275 mutex_unlock(&kvm->slots_lock);
7837699f 3276 break;
1fe779f8
CO		 3277 case KVM_GET_IRQCHIP: {
3278 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3279 struct kvm_irqchip *chip;
1fe779f8 3280
ff5c2c03
SL		 3281 chip = memdup_user(argp, sizeof(*chip));
3282 if (IS_ERR(chip)) {
3283 r = PTR_ERR(chip);
1fe779f8 3284 goto out;
ff5c2c03
SL		 3285 }
3286
1fe779f8
CO		 3287 r = -ENXIO;
3288 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3289 goto get_irqchip_out;
3290 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3291 if (r)
f0d66275 3292 goto get_irqchip_out;
1fe779f8 3293 r = -EFAULT;
f0d66275
DH		 3294 if (copy_to_user(argp, chip, sizeof *chip))
3295 goto get_irqchip_out;
1fe779f8 3296 r = 0;
f0d66275
DH		 3297 get_irqchip_out:
3298 kfree(chip);
1fe779f8
CO		 3299 break;
3300 }
3301 case KVM_SET_IRQCHIP: {
3302 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3303 struct kvm_irqchip *chip;
1fe779f8 3304
ff5c2c03
SL		 3305 chip = memdup_user(argp, sizeof(*chip));
3306 if (IS_ERR(chip)) {
3307 r = PTR_ERR(chip);
1fe779f8 3308 goto out;
ff5c2c03
SL		 3309 }
3310
1fe779f8
CO		 3311 r = -ENXIO;
3312 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3313 goto set_irqchip_out;
3314 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3315 if (r)
f0d66275 3316 goto set_irqchip_out;
1fe779f8 3317 r = 0;
f0d66275
DH		 3318 set_irqchip_out:
3319 kfree(chip);
1fe779f8
CO		 3320 break;
3321 }
e0f63cb9 3322 case KVM_GET_PIT: {
e0f63cb9 3323 r = -EFAULT;
f0d66275 3324 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3325 goto out;
3326 r = -ENXIO;
3327 if (!kvm->arch.vpit)
3328 goto out;
f0d66275 3329 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3330 if (r)
3331 goto out;
3332 r = -EFAULT;
f0d66275 3333 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3334 goto out;
3335 r = 0;
3336 break;
3337 }
3338 case KVM_SET_PIT: {
e0f63cb9 3339 r = -EFAULT;
f0d66275 3340 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3341 goto out;
3342 r = -ENXIO;
3343 if (!kvm->arch.vpit)
3344 goto out;
f0d66275 3345 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3346 break;
3347 }
e9f42757
BK		 3348 case KVM_GET_PIT2: {
3349 r = -ENXIO;
3350 if (!kvm->arch.vpit)
3351 goto out;
3352 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3353 if (r)
3354 goto out;
3355 r = -EFAULT;
3356 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3357 goto out;
3358 r = 0;
3359 break;
3360 }
3361 case KVM_SET_PIT2: {
3362 r = -EFAULT;
3363 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3364 goto out;
3365 r = -ENXIO;
3366 if (!kvm->arch.vpit)
3367 goto out;
3368 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3369 break;
3370 }
52d939a0
MT		 3371 case KVM_REINJECT_CONTROL: {
3372 struct kvm_reinject_control control;
3373 r = -EFAULT;
3374 if (copy_from_user(&control, argp, sizeof(control)))
3375 goto out;
3376 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3377 break;
3378 }
ffde22ac
ES		 3379 case KVM_XEN_HVM_CONFIG: {
3380 r = -EFAULT;
3381 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3382 sizeof(struct kvm_xen_hvm_config)))
3383 goto out;
3384 r = -EINVAL;
3385 if (kvm->arch.xen_hvm_config.flags)
3386 goto out;
3387 r = 0;
3388 break;
3389 }
afbcf7ab 3390 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3391 struct kvm_clock_data user_ns;
3392 u64 now_ns;
3393 s64 delta;
3394
3395 r = -EFAULT;
3396 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3397 goto out;
3398
3399 r = -EINVAL;
3400 if (user_ns.flags)
3401 goto out;
3402
3403 r = 0;
395c6b0a 3404 local_irq_disable();
759379dd 3405 now_ns = get_kernel_ns();
afbcf7ab 3406 delta = user_ns.clock - now_ns;
395c6b0a 3407 local_irq_enable();
afbcf7ab
GC		 3408 kvm->arch.kvmclock_offset = delta;
3409 break;
3410 }
3411 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3412 struct kvm_clock_data user_ns;
3413 u64 now_ns;
3414
395c6b0a 3415 local_irq_disable();
759379dd 3416 now_ns = get_kernel_ns();
afbcf7ab 3417 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3418 local_irq_enable();
afbcf7ab 3419 user_ns.flags = 0;
97e69aa6 3420 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3421
3422 r = -EFAULT;
3423 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3424 goto out;
3425 r = 0;
3426 break;
3427 }
3428
1fe779f8
CO		 3429 default:
3430 ;
3431 }
3432out:
3433 return r;
3434}
3435
a16b043c 3436static void kvm_init_msr_list(void)
043405e1
CO		 3437{
3438 u32 dummy[2];
3439 unsigned i, j;
3440
e3267cbb
GC		 3441 /* skip the first msrs in the list. KVM-specific */
3442 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3443 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3444 continue;
3445 if (j < i)
3446 msrs_to_save[j] = msrs_to_save[i];
3447 j++;
3448 }
3449 num_msrs_to_save = j;
3450}
3451
bda9020e
MT		 3452static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3453 const void *v)
bbd9b64e 3454{
70252a10
AK		 3455 int handled = 0;
3456 int n;
3457
3458 do {
3459 n = min(len, 8);
3460 if (!(vcpu->arch.apic &&
3461 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3462 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3463 break;
3464 handled += n;
3465 addr += n;
3466 len -= n;
3467 v += n;
3468 } while (len);
bbd9b64e 3469
70252a10 3470 return handled;
bbd9b64e
CO		 3471}
3472
bda9020e 3473static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3474{
70252a10
AK		 3475 int handled = 0;
3476 int n;
3477
3478 do {
3479 n = min(len, 8);
3480 if (!(vcpu->arch.apic &&
3481 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3482 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3483 break;
3484 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3485 handled += n;
3486 addr += n;
3487 len -= n;
3488 v += n;
3489 } while (len);
bbd9b64e 3490
70252a10 3491 return handled;
bbd9b64e
CO		 3492}
3493
2dafc6c2
GN		 3494static void kvm_set_segment(struct kvm_vcpu *vcpu,
3495 struct kvm_segment *var, int seg)
3496{
3497 kvm_x86_ops->set_segment(vcpu, var, seg);
3498}
3499
3500void kvm_get_segment(struct kvm_vcpu *vcpu,
3501 struct kvm_segment *var, int seg)
3502{
3503 kvm_x86_ops->get_segment(vcpu, var, seg);
3504}
3505
e459e322 3506gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3507{
3508 gpa_t t_gpa;
ab9ae313 3509 struct x86_exception exception;
02f59dc9
JR		 3510
3511 BUG_ON(!mmu_is_nested(vcpu));
3512
3513 /* NPT walks are always user-walks */
3514 access |= PFERR_USER_MASK;
ab9ae313 3515 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3516
3517 return t_gpa;
3518}
3519
ab9ae313
AK		 3520gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3521 struct x86_exception *exception)
1871c602
GN		 3522{
3523 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3524 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3525}
3526
ab9ae313
AK		 3527 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3528 struct x86_exception *exception)
1871c602
GN		 3529{
3530 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3531 access |= PFERR_FETCH_MASK;
ab9ae313 3532 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3533}
3534
ab9ae313
AK		 3535gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3536 struct x86_exception *exception)
1871c602
GN		 3537{
3538 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3539 access |= PFERR_WRITE_MASK;
ab9ae313 3540 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3541}
3542
3543/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3544gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3545 struct x86_exception *exception)
1871c602 3546{
ab9ae313 3547 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3548}
3549
3550static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3551 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3552 struct x86_exception *exception)
bbd9b64e
CO		 3553{
3554 void *data = val;
10589a46 3555 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3556
3557 while (bytes) {
14dfe855 3558 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3559 exception);
bbd9b64e 3560 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3561 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3562 int ret;
3563
bcc55cba 3564 if (gpa == UNMAPPED_GVA)
ab9ae313 3565 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3566 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3567 if (ret < 0) {
c3cd7ffa 3568 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3569 goto out;
3570 }
bbd9b64e 3571
77c2002e
IE		 3572 bytes -= toread;
3573 data += toread;
3574 addr += toread;
bbd9b64e 3575 }
10589a46 3576out:
10589a46 3577 return r;
bbd9b64e 3578}
77c2002e 3579
1871c602 3580/* used for instruction fetching */
0f65dd70
AK		 3581static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3582 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3583 struct x86_exception *exception)
1871c602 3584{
0f65dd70 3585 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3586 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3587
1871c602 3588 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3589 access | PFERR_FETCH_MASK,
3590 exception);
1871c602
GN		 3591}
3592
064aea77 3593int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3594 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3595 struct x86_exception *exception)
1871c602 3596{
0f65dd70 3597 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3598 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3599
1871c602 3600 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3601 exception);
1871c602 3602}
064aea77 3603EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3604
0f65dd70
AK		 3605static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3606 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3607 struct x86_exception *exception)
1871c602 3608{
0f65dd70 3609 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3610 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3611}
3612
6a4d7550 3613int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3614 gva_t addr, void *val,
2dafc6c2 3615 unsigned int bytes,
bcc55cba 3616 struct x86_exception *exception)
77c2002e 3617{
0f65dd70 3618 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3619 void *data = val;
3620 int r = X86EMUL_CONTINUE;
3621
3622 while (bytes) {
14dfe855
JR		 3623 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3624 PFERR_WRITE_MASK,
ab9ae313 3625 exception);
77c2002e
IE		 3626 unsigned offset = addr & (PAGE_SIZE-1);
3627 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3628 int ret;
3629
bcc55cba 3630 if (gpa == UNMAPPED_GVA)
ab9ae313 3631 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3632 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3633 if (ret < 0) {
c3cd7ffa 3634 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3635 goto out;
3636 }
3637
3638 bytes -= towrite;
3639 data += towrite;
3640 addr += towrite;
3641 }
3642out:
3643 return r;
3644}
6a4d7550 3645EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3646
af7cc7d1
XG		 3647static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3648 gpa_t *gpa, struct x86_exception *exception,
3649 bool write)
3650{
97d64b78
AK		 3651 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3652 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 3653
97d64b78
AK		 3654 if (vcpu_match_mmio_gva(vcpu, gva)
3655 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 3656 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3657 (gva & (PAGE_SIZE - 1));
4f022648 3658 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3659 return 1;
3660 }
3661
af7cc7d1
XG		 3662 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3663
3664 if (*gpa == UNMAPPED_GVA)
3665 return -1;
3666
3667 /* For APIC access vmexit */
3668 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3669 return 1;
3670
4f022648
XG		 3671 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3672 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3673 return 1;
4f022648 3674 }
bebb106a 3675
af7cc7d1
XG		 3676 return 0;
3677}
3678
3200f405 3679int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3680 const void *val, int bytes)
bbd9b64e
CO		 3681{
3682 int ret;
3683
3684 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3685 if (ret < 0)
bbd9b64e 3686 return 0;
f57f2ef5 3687 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3688 return 1;
3689}
3690
77d197b2
XG		 3691struct read_write_emulator_ops {
3692 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3693 int bytes);
3694 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3695 void *val, int bytes);
3696 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3697 int bytes, void *val);
3698 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3699 void *val, int bytes);
3700 bool write;
3701};
3702
3703static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3704{
3705 if (vcpu->mmio_read_completed) {
77d197b2 3706 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 3707 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 3708 vcpu->mmio_read_completed = 0;
3709 return 1;
3710 }
3711
3712 return 0;
3713}
3714
3715static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3716 void *val, int bytes)
3717{
3718 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3719}
3720
3721static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3722 void *val, int bytes)
3723{
3724 return emulator_write_phys(vcpu, gpa, val, bytes);
3725}
3726
3727static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3728{
3729 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3730 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3731}
3732
3733static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3734 void *val, int bytes)
3735{
3736 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3737 return X86EMUL_IO_NEEDED;
3738}
3739
3740static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3741 void *val, int bytes)
3742{
f78146b0
AK		 3743 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3744
3745 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
77d197b2
XG		 3746 return X86EMUL_CONTINUE;
3747}
3748
0fbe9b0b 3749static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 3750 .read_write_prepare = read_prepare,
3751 .read_write_emulate = read_emulate,
3752 .read_write_mmio = vcpu_mmio_read,
3753 .read_write_exit_mmio = read_exit_mmio,
3754};
3755
0fbe9b0b 3756static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 3757 .read_write_emulate = write_emulate,
3758 .read_write_mmio = write_mmio,
3759 .read_write_exit_mmio = write_exit_mmio,
3760 .write = true,
3761};
3762
22388a3c
XG		 3763static int emulator_read_write_onepage(unsigned long addr, void *val,
3764 unsigned int bytes,
3765 struct x86_exception *exception,
3766 struct kvm_vcpu *vcpu,
0fbe9b0b 3767 const struct read_write_emulator_ops *ops)
bbd9b64e 3768{
af7cc7d1
XG		 3769 gpa_t gpa;
3770 int handled, ret;
22388a3c 3771 bool write = ops->write;
f78146b0 3772 struct kvm_mmio_fragment *frag;
10589a46 3773
22388a3c 3774 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3775
af7cc7d1 3776 if (ret < 0)
bbd9b64e 3777 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3778
3779 /* For APIC access vmexit */
af7cc7d1 3780 if (ret)
bbd9b64e
CO		 3781 goto mmio;
3782
22388a3c 3783 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3784 return X86EMUL_CONTINUE;
3785
3786mmio:
3787 /*
3788 * Is this MMIO handled locally?
3789 */
22388a3c 3790 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3791 if (handled == bytes)
bbd9b64e 3792 return X86EMUL_CONTINUE;
bbd9b64e 3793
70252a10
AK		 3794 gpa += handled;
3795 bytes -= handled;
3796 val += handled;
3797
f78146b0
AK		 3798 while (bytes) {
3799 unsigned now = min(bytes, 8U);
bbd9b64e 3800
f78146b0
AK		 3801 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3802 frag->gpa = gpa;
3803 frag->data = val;
3804 frag->len = now;
3805
3806 gpa += now;
3807 val += now;
3808 bytes -= now;
3809 }
3810 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3811}
3812
22388a3c
XG		 3813int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3814 void *val, unsigned int bytes,
3815 struct x86_exception *exception,
0fbe9b0b 3816 const struct read_write_emulator_ops *ops)
bbd9b64e 3817{
0f65dd70 3818 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 3819 gpa_t gpa;
3820 int rc;
3821
3822 if (ops->read_write_prepare &&
3823 ops->read_write_prepare(vcpu, val, bytes))
3824 return X86EMUL_CONTINUE;
3825
3826 vcpu->mmio_nr_fragments = 0;
0f65dd70 3827
bbd9b64e
CO		 3828 /* Crossing a page boundary? */
3829 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 3830 int now;
bbd9b64e
CO		 3831
3832 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3833 rc = emulator_read_write_onepage(addr, val, now, exception,
3834 vcpu, ops);
3835
bbd9b64e
CO		 3836 if (rc != X86EMUL_CONTINUE)
3837 return rc;
3838 addr += now;
3839 val += now;
3840 bytes -= now;
3841 }
22388a3c 3842
f78146b0
AK		 3843 rc = emulator_read_write_onepage(addr, val, bytes, exception,
3844 vcpu, ops);
3845 if (rc != X86EMUL_CONTINUE)
3846 return rc;
3847
3848 if (!vcpu->mmio_nr_fragments)
3849 return rc;
3850
3851 gpa = vcpu->mmio_fragments[0].gpa;
3852
3853 vcpu->mmio_needed = 1;
3854 vcpu->mmio_cur_fragment = 0;
3855
3856 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3857 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3858 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3859 vcpu->run->mmio.phys_addr = gpa;
3860
3861 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 3862}
3863
3864static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3865 unsigned long addr,
3866 void *val,
3867 unsigned int bytes,
3868 struct x86_exception *exception)
3869{
3870 return emulator_read_write(ctxt, addr, val, bytes,
3871 exception, &read_emultor);
3872}
3873
3874int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3875 unsigned long addr,
3876 const void *val,
3877 unsigned int bytes,
3878 struct x86_exception *exception)
3879{
3880 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3881 exception, &write_emultor);
bbd9b64e 3882}
bbd9b64e 3883
daea3e73
AK		 3884#define CMPXCHG_TYPE(t, ptr, old, new) \
3885 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3886
3887#ifdef CONFIG_X86_64
3888# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3889#else
3890# define CMPXCHG64(ptr, old, new) \
9749a6c0 3891 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3892#endif
3893
0f65dd70
AK		 3894static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3895 unsigned long addr,
bbd9b64e
CO		 3896 const void *old,
3897 const void *new,
3898 unsigned int bytes,
0f65dd70 3899 struct x86_exception *exception)
bbd9b64e 3900{
0f65dd70 3901 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3902 gpa_t gpa;
3903 struct page *page;
3904 char *kaddr;
3905 bool exchanged;
2bacc55c 3906
daea3e73
AK		 3907 /* guests cmpxchg8b have to be emulated atomically */
3908 if (bytes > 8 || (bytes & (bytes - 1)))
3909 goto emul_write;
10589a46 3910
daea3e73 3911 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3912
daea3e73
AK		 3913 if (gpa == UNMAPPED_GVA ||
3914 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3915 goto emul_write;
2bacc55c 3916
daea3e73
AK		 3917 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3918 goto emul_write;
72dc67a6 3919
daea3e73 3920 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 3921 if (is_error_page(page))
c19b8bd6 3922 goto emul_write;
72dc67a6 3923
8fd75e12 3924 kaddr = kmap_atomic(page);
daea3e73
AK		 3925 kaddr += offset_in_page(gpa);
3926 switch (bytes) {
3927 case 1:
3928 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3929 break;
3930 case 2:
3931 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3932 break;
3933 case 4:
3934 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3935 break;
3936 case 8:
3937 exchanged = CMPXCHG64(kaddr, old, new);
3938 break;
3939 default:
3940 BUG();
2bacc55c 3941 }
8fd75e12 3942 kunmap_atomic(kaddr);
daea3e73
AK		 3943 kvm_release_page_dirty(page);
3944
3945 if (!exchanged)
3946 return X86EMUL_CMPXCHG_FAILED;
3947
f57f2ef5 3948 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 3949
3950 return X86EMUL_CONTINUE;
4a5f48f6 3951
3200f405 3952emul_write:
daea3e73 3953 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3954
0f65dd70 3955 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 3956}
3957
cf8f70bf
GN		 3958static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3959{
3960 /* TODO: String I/O for in kernel device */
3961 int r;
3962
3963 if (vcpu->arch.pio.in)
3964 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3965 vcpu->arch.pio.size, pd);
3966 else
3967 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3968 vcpu->arch.pio.port, vcpu->arch.pio.size,
3969 pd);
3970 return r;
3971}
3972
6f6fbe98
XG		 3973static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3974 unsigned short port, void *val,
3975 unsigned int count, bool in)
cf8f70bf 3976{
6f6fbe98 3977 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 3978
3979 vcpu->arch.pio.port = port;
6f6fbe98 3980 vcpu->arch.pio.in = in;
7972995b 3981 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3982 vcpu->arch.pio.size = size;
3983
3984 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3985 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3986 return 1;
3987 }
3988
3989 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 3990 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 3991 vcpu->run->io.size = size;
3992 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3993 vcpu->run->io.count = count;
3994 vcpu->run->io.port = port;
3995
3996 return 0;
3997}
3998
6f6fbe98
XG		 3999static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4000 int size, unsigned short port, void *val,
4001 unsigned int count)
cf8f70bf 4002{
ca1d4a9e 4003 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4004 int ret;
ca1d4a9e 4005
6f6fbe98
XG		 4006 if (vcpu->arch.pio.count)
4007 goto data_avail;
cf8f70bf 4008
6f6fbe98
XG		 4009 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4010 if (ret) {
4011data_avail:
4012 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4013 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4014 return 1;
4015 }
4016
cf8f70bf
GN		 4017 return 0;
4018}
4019
6f6fbe98
XG		 4020static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4021 int size, unsigned short port,
4022 const void *val, unsigned int count)
4023{
4024 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4025
4026 memcpy(vcpu->arch.pio_data, val, size * count);
4027 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4028}
4029
bbd9b64e
CO		 4030static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4031{
4032 return kvm_x86_ops->get_segment_base(vcpu, seg);
4033}
4034
3cb16fe7 4035static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4036{
3cb16fe7 4037 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4038}
4039
f5f48ee1
SY		 4040int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4041{
4042 if (!need_emulate_wbinvd(vcpu))
4043 return X86EMUL_CONTINUE;
4044
4045 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4046 int cpu = get_cpu();
4047
4048 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4049 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4050 wbinvd_ipi, NULL, 1);
2eec7343 4051 put_cpu();
f5f48ee1 4052 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4053 } else
4054 wbinvd();
f5f48ee1
SY		 4055 return X86EMUL_CONTINUE;
4056}
4057EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4058
bcaf5cc5
AK		 4059static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4060{
4061 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4062}
4063
717746e3 4064int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4065{
717746e3 4066 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4067}
4068
717746e3 4069int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4070{
338dbc97 4071
717746e3 4072 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4073}
4074
52a46617 4075static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4076{
52a46617 4077 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4078}
4079
717746e3 4080static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4081{
717746e3 4082 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4083 unsigned long value;
4084
4085 switch (cr) {
4086 case 0:
4087 value = kvm_read_cr0(vcpu);
4088 break;
4089 case 2:
4090 value = vcpu->arch.cr2;
4091 break;
4092 case 3:
9f8fe504 4093 value = kvm_read_cr3(vcpu);
52a46617
GN		 4094 break;
4095 case 4:
4096 value = kvm_read_cr4(vcpu);
4097 break;
4098 case 8:
4099 value = kvm_get_cr8(vcpu);
4100 break;
4101 default:
a737f256 4102 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4103 return 0;
4104 }
4105
4106 return value;
4107}
4108
717746e3 4109static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4110{
717746e3 4111 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4112 int res = 0;
4113
52a46617
GN		 4114 switch (cr) {
4115 case 0:
49a9b07e 4116 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4117 break;
4118 case 2:
4119 vcpu->arch.cr2 = val;
4120 break;
4121 case 3:
2390218b 4122 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4123 break;
4124 case 4:
a83b29c6 4125 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4126 break;
4127 case 8:
eea1cff9 4128 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4129 break;
4130 default:
a737f256 4131 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4132 res = -1;
52a46617 4133 }
0f12244f
GN		 4134
4135 return res;
52a46617
GN		 4136}
4137
4cee4798
KW		 4138static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4139{
4140 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4141}
4142
717746e3 4143static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4144{
717746e3 4145 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4146}
4147
4bff1e86 4148static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4149{
4bff1e86 4150 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4151}
4152
4bff1e86 4153static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4154{
4bff1e86 4155 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4156}
4157
1ac9d0cf
AK		 4158static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4159{
4160 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4161}
4162
4163static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4164{
4165 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4166}
4167
4bff1e86
AK		 4168static unsigned long emulator_get_cached_segment_base(
4169 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4170{
4bff1e86 4171 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4172}
4173
1aa36616
AK		 4174static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4175 struct desc_struct *desc, u32 *base3,
4176 int seg)
2dafc6c2
GN		 4177{
4178 struct kvm_segment var;
4179
4bff1e86 4180 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4181 *selector = var.selector;
2dafc6c2
GN		 4182
4183 if (var.unusable)
4184 return false;
4185
4186 if (var.g)
4187 var.limit >>= 12;
4188 set_desc_limit(desc, var.limit);
4189 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4190#ifdef CONFIG_X86_64
4191 if (base3)
4192 *base3 = var.base >> 32;
4193#endif
2dafc6c2
GN		 4194 desc->type = var.type;
4195 desc->s = var.s;
4196 desc->dpl = var.dpl;
4197 desc->p = var.present;
4198 desc->avl = var.avl;
4199 desc->l = var.l;
4200 desc->d = var.db;
4201 desc->g = var.g;
4202
4203 return true;
4204}
4205
1aa36616
AK		 4206static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4207 struct desc_struct *desc, u32 base3,
4208 int seg)
2dafc6c2 4209{
4bff1e86 4210 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4211 struct kvm_segment var;
4212
1aa36616 4213 var.selector = selector;
2dafc6c2 4214 var.base = get_desc_base(desc);
5601d05b
GN		 4215#ifdef CONFIG_X86_64
4216 var.base |= ((u64)base3) << 32;
4217#endif
2dafc6c2
GN		 4218 var.limit = get_desc_limit(desc);
4219 if (desc->g)
4220 var.limit = (var.limit << 12) | 0xfff;
4221 var.type = desc->type;
4222 var.present = desc->p;
4223 var.dpl = desc->dpl;
4224 var.db = desc->d;
4225 var.s = desc->s;
4226 var.l = desc->l;
4227 var.g = desc->g;
4228 var.avl = desc->avl;
4229 var.present = desc->p;
4230 var.unusable = !var.present;
4231 var.padding = 0;
4232
4233 kvm_set_segment(vcpu, &var, seg);
4234 return;
4235}
4236
717746e3
AK		 4237static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4238 u32 msr_index, u64 *pdata)
4239{
4240 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4241}
4242
4243static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4244 u32 msr_index, u64 data)
4245{
4246 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4247}
4248
222d21aa
AK		 4249static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4250 u32 pmc, u64 *pdata)
4251{
4252 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4253}
4254
6c3287f7
AK		 4255static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4256{
4257 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4258}
4259
5037f6f3
AK		 4260static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4261{
4262 preempt_disable();
5197b808 4263 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4264 /*
4265 * CR0.TS may reference the host fpu state, not the guest fpu state,
4266 * so it may be clear at this point.
4267 */
4268 clts();
4269}
4270
4271static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4272{
4273 preempt_enable();
4274}
4275
2953538e 4276static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4277 struct x86_instruction_info *info,
c4f035c6
AK		 4278 enum x86_intercept_stage stage)
4279{
2953538e 4280 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4281}
4282
0017f93a 4283static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4284 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4285{
0017f93a 4286 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4287}
4288
dd856efa
AK		 4289static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4290{
4291 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4292}
4293
4294static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4295{
4296 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4297}
4298
0225fb50 4299static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4300 .read_gpr = emulator_read_gpr,
4301 .write_gpr = emulator_write_gpr,
1871c602 4302 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4303 .write_std = kvm_write_guest_virt_system,
1871c602 4304 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4305 .read_emulated = emulator_read_emulated,
4306 .write_emulated = emulator_write_emulated,
4307 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4308 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4309 .pio_in_emulated = emulator_pio_in_emulated,
4310 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4311 .get_segment = emulator_get_segment,
4312 .set_segment = emulator_set_segment,
5951c442 4313 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4314 .get_gdt = emulator_get_gdt,
160ce1f1 4315 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4316 .set_gdt = emulator_set_gdt,
4317 .set_idt = emulator_set_idt,
52a46617
GN		 4318 .get_cr = emulator_get_cr,
4319 .set_cr = emulator_set_cr,
4cee4798 4320 .set_rflags = emulator_set_rflags,
9c537244 4321 .cpl = emulator_get_cpl,
35aa5375
GN		 4322 .get_dr = emulator_get_dr,
4323 .set_dr = emulator_set_dr,
717746e3
AK		 4324 .set_msr = emulator_set_msr,
4325 .get_msr = emulator_get_msr,
222d21aa 4326 .read_pmc = emulator_read_pmc,
6c3287f7 4327 .halt = emulator_halt,
bcaf5cc5 4328 .wbinvd = emulator_wbinvd,
d6aa1000 4329 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4330 .get_fpu = emulator_get_fpu,
4331 .put_fpu = emulator_put_fpu,
c4f035c6 4332 .intercept = emulator_intercept,
bdb42f5a 4333 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4334};
4335
95cb2295
GN		 4336static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4337{
4338 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4339 /*
4340 * an sti; sti; sequence only disable interrupts for the first
4341 * instruction. So, if the last instruction, be it emulated or
4342 * not, left the system with the INT_STI flag enabled, it
4343 * means that the last instruction is an sti. We should not
4344 * leave the flag on in this case. The same goes for mov ss
4345 */
4346 if (!(int_shadow & mask))
4347 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4348}
4349
54b8486f
GN		 4350static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4351{
4352 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4353 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4354 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4355 else if (ctxt->exception.error_code_valid)
4356 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4357 ctxt->exception.error_code);
54b8486f 4358 else
da9cb575 4359 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4360}
4361
dd856efa 4362static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4363{
9dac77fa 4364 memset(&ctxt->twobyte, 0,
dd856efa 4365 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4366
9dac77fa
AK		 4367 ctxt->fetch.start = 0;
4368 ctxt->fetch.end = 0;
4369 ctxt->io_read.pos = 0;
4370 ctxt->io_read.end = 0;
4371 ctxt->mem_read.pos = 0;
4372 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4373}
4374
8ec4722d
MG		 4375static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4376{
adf52235 4377 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4378 int cs_db, cs_l;
4379
8ec4722d
MG		 4380 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4381
adf52235
TY		 4382 ctxt->eflags = kvm_get_rflags(vcpu);
4383 ctxt->eip = kvm_rip_read(vcpu);
4384 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4385 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4386 cs_l ? X86EMUL_MODE_PROT64 :
4387 cs_db ? X86EMUL_MODE_PROT32 :
4388 X86EMUL_MODE_PROT16;
4389 ctxt->guest_mode = is_guest_mode(vcpu);
4390
dd856efa 4391 init_decode_cache(ctxt);
7ae441ea 4392 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4393}
4394
71f9833b 4395int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4396{
9d74191a 4397 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4398 int ret;
4399
4400 init_emulate_ctxt(vcpu);
4401
9dac77fa
AK		 4402 ctxt->op_bytes = 2;
4403 ctxt->ad_bytes = 2;
4404 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4405 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4406
4407 if (ret != X86EMUL_CONTINUE)
4408 return EMULATE_FAIL;
4409
9dac77fa 4410 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4411 kvm_rip_write(vcpu, ctxt->eip);
4412 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4413
4414 if (irq == NMI_VECTOR)
7460fb4a 4415 vcpu->arch.nmi_pending = 0;
63995653
MG		 4416 else
4417 vcpu->arch.interrupt.pending = false;
4418
4419 return EMULATE_DONE;
4420}
4421EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4422
6d77dbfc
GN		 4423static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4424{
fc3a9157
JR		 4425 int r = EMULATE_DONE;
4426
6d77dbfc
GN		 4427 ++vcpu->stat.insn_emulation_fail;
4428 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4429 if (!is_guest_mode(vcpu)) {
4430 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4431 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4432 vcpu->run->internal.ndata = 0;
4433 r = EMULATE_FAIL;
4434 }
6d77dbfc 4435 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4436
4437 return r;
6d77dbfc
GN		 4438}
4439
a6f177ef
GN		 4440static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4441{
4442 gpa_t gpa;
8e3d9d06 4443 pfn_t pfn;
a6f177ef 4444
68be0803
GN		 4445 if (tdp_enabled)
4446 return false;
4447
a6f177ef
GN		 4448 /*
4449 * if emulation was due to access to shadowed page table
4a969980 4450 * and it failed try to unshadow page and re-enter the
a6f177ef
GN		 4451 * guest to let CPU execute the instruction.
4452 */
4453 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4454 return true;
4455
4456 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4457
4458 if (gpa == UNMAPPED_GVA)
4459 return true; /* let cpu generate fault */
4460
8e3d9d06
XG		 4461 /*
4462 * Do not retry the unhandleable instruction if it faults on the
4463 * readonly host memory, otherwise it will goto a infinite loop:
4464 * retry instruction -> write #PF -> emulation fail -> retry
4465 * instruction -> ...
4466 */
4467 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
81c52c56 4468 if (!is_error_noslot_pfn(pfn)) {
8e3d9d06 4469 kvm_release_pfn_clean(pfn);
a6f177ef 4470 return true;
8e3d9d06 4471 }
a6f177ef
GN		 4472
4473 return false;
4474}
4475
1cb3f3ae
XG		 4476static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4477 unsigned long cr2, int emulation_type)
4478{
4479 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4480 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4481
4482 last_retry_eip = vcpu->arch.last_retry_eip;
4483 last_retry_addr = vcpu->arch.last_retry_addr;
4484
4485 /*
4486 * If the emulation is caused by #PF and it is non-page_table
4487 * writing instruction, it means the VM-EXIT is caused by shadow
4488 * page protected, we can zap the shadow page and retry this
4489 * instruction directly.
4490 *
4491 * Note: if the guest uses a non-page-table modifying instruction
4492 * on the PDE that points to the instruction, then we will unmap
4493 * the instruction and go to an infinite loop. So, we cache the
4494 * last retried eip and the last fault address, if we meet the eip
4495 * and the address again, we can break out of the potential infinite
4496 * loop.
4497 */
4498 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4499
4500 if (!(emulation_type & EMULTYPE_RETRY))
4501 return false;
4502
4503 if (x86_page_table_writing_insn(ctxt))
4504 return false;
4505
4506 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4507 return false;
4508
4509 vcpu->arch.last_retry_eip = ctxt->eip;
4510 vcpu->arch.last_retry_addr = cr2;
4511
4512 if (!vcpu->arch.mmu.direct_map)
4513 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4514
4515 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4516
4517 return true;
4518}
4519
716d51ab
GN		 4520static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4521static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4522
51d8b661
AP		 4523int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4524 unsigned long cr2,
dc25e89e
AP		 4525 int emulation_type,
4526 void *insn,
4527 int insn_len)
bbd9b64e 4528{
95cb2295 4529 int r;
9d74191a 4530 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4531 bool writeback = true;
bbd9b64e 4532
26eef70c 4533 kvm_clear_exception_queue(vcpu);
8d7d8102 4534
571008da 4535 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4536 init_emulate_ctxt(vcpu);
9d74191a
TY		 4537 ctxt->interruptibility = 0;
4538 ctxt->have_exception = false;
4539 ctxt->perm_ok = false;
bbd9b64e 4540
9d74191a 4541 ctxt->only_vendor_specific_insn
4005996e
AK		 4542 = emulation_type & EMULTYPE_TRAP_UD;
4543
9d74191a 4544 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4545
e46479f8 4546 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4547 ++vcpu->stat.insn_emulation;
1d2887e2 4548 if (r != EMULATION_OK) {
4005996e
AK		 4549 if (emulation_type & EMULTYPE_TRAP_UD)
4550 return EMULATE_FAIL;
a6f177ef 4551 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4552 return EMULATE_DONE;
6d77dbfc
GN		 4553 if (emulation_type & EMULTYPE_SKIP)
4554 return EMULATE_FAIL;
4555 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4556 }
4557 }
4558
ba8afb6b 4559 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4560 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4561 return EMULATE_DONE;
4562 }
4563
1cb3f3ae
XG		 4564 if (retry_instruction(ctxt, cr2, emulation_type))
4565 return EMULATE_DONE;
4566
7ae441ea 4567 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4568 changes registers values during IO operation */
7ae441ea
GN		 4569 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4570 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 4571 emulator_invalidate_register_cache(ctxt);
7ae441ea 4572 }
4d2179e1 4573
5cd21917 4574restart:
9d74191a 4575 r = x86_emulate_insn(ctxt);
bbd9b64e 4576
775fde86
JR		 4577 if (r == EMULATION_INTERCEPTED)
4578 return EMULATE_DONE;
4579
d2ddd1c4 4580 if (r == EMULATION_FAILED) {
a6f177ef 4581 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4582 return EMULATE_DONE;
4583
6d77dbfc 4584 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4585 }
4586
9d74191a 4587 if (ctxt->have_exception) {
54b8486f 4588 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4589 r = EMULATE_DONE;
4590 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4591 if (!vcpu->arch.pio.in)
4592 vcpu->arch.pio.count = 0;
716d51ab 4593 else {
7ae441ea 4594 writeback = false;
716d51ab
GN		 4595 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4596 }
e85d28f8 4597 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4598 } else if (vcpu->mmio_needed) {
4599 if (!vcpu->mmio_is_write)
4600 writeback = false;
e85d28f8 4601 r = EMULATE_DO_MMIO;
716d51ab 4602 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 4603 } else if (r == EMULATION_RESTART)
5cd21917 4604 goto restart;
d2ddd1c4
GN		 4605 else
4606 r = EMULATE_DONE;
f850e2e6 4607
7ae441ea 4608 if (writeback) {
9d74191a
TY		 4609 toggle_interruptibility(vcpu, ctxt->interruptibility);
4610 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4611 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 4612 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4613 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4614 } else
4615 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4616
4617 return r;
de7d789a 4618}
51d8b661 4619EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4620
cf8f70bf 4621int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4622{
cf8f70bf 4623 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4624 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4625 size, port, &val, 1);
cf8f70bf 4626 /* do not return to emulator after return from userspace */
7972995b 4627 vcpu->arch.pio.count = 0;
de7d789a
CO		 4628 return ret;
4629}
cf8f70bf 4630EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4631
8cfdc000
ZA		 4632static void tsc_bad(void *info)
4633{
0a3aee0d 4634 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4635}
4636
4637static void tsc_khz_changed(void *data)
c8076604 4638{
8cfdc000
ZA		 4639 struct cpufreq_freqs *freq = data;
4640 unsigned long khz = 0;
4641
4642 if (data)
4643 khz = freq->new;
4644 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4645 khz = cpufreq_quick_get(raw_smp_processor_id());
4646 if (!khz)
4647 khz = tsc_khz;
0a3aee0d 4648 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4649}
4650
c8076604
GH		 4651static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4652 void *data)
4653{
4654 struct cpufreq_freqs *freq = data;
4655 struct kvm *kvm;
4656 struct kvm_vcpu *vcpu;
4657 int i, send_ipi = 0;
4658
8cfdc000
ZA		 4659 /*
4660 * We allow guests to temporarily run on slowing clocks,
4661 * provided we notify them after, or to run on accelerating
4662 * clocks, provided we notify them before. Thus time never
4663 * goes backwards.
4664 *
4665 * However, we have a problem. We can't atomically update
4666 * the frequency of a given CPU from this function; it is
4667 * merely a notifier, which can be called from any CPU.
4668 * Changing the TSC frequency at arbitrary points in time
4669 * requires a recomputation of local variables related to
4670 * the TSC for each VCPU. We must flag these local variables
4671 * to be updated and be sure the update takes place with the
4672 * new frequency before any guests proceed.
4673 *
4674 * Unfortunately, the combination of hotplug CPU and frequency
4675 * change creates an intractable locking scenario; the order
4676 * of when these callouts happen is undefined with respect to
4677 * CPU hotplug, and they can race with each other. As such,
4678 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4679 * undefined; you can actually have a CPU frequency change take
4680 * place in between the computation of X and the setting of the
4681 * variable. To protect against this problem, all updates of
4682 * the per_cpu tsc_khz variable are done in an interrupt
4683 * protected IPI, and all callers wishing to update the value
4684 * must wait for a synchronous IPI to complete (which is trivial
4685 * if the caller is on the CPU already). This establishes the
4686 * necessary total order on variable updates.
4687 *
4688 * Note that because a guest time update may take place
4689 * anytime after the setting of the VCPU's request bit, the
4690 * correct TSC value must be set before the request. However,
4691 * to ensure the update actually makes it to any guest which
4692 * starts running in hardware virtualization between the set
4693 * and the acquisition of the spinlock, we must also ping the
4694 * CPU after setting the request bit.
4695 *
4696 */
4697
c8076604
GH		 4698 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4699 return 0;
4700 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4701 return 0;
8cfdc000
ZA		 4702
4703 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4704
e935b837 4705 raw_spin_lock(&kvm_lock);
c8076604 4706 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4707 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4708 if (vcpu->cpu != freq->cpu)
4709 continue;
c285545f 4710 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4711 if (vcpu->cpu != smp_processor_id())
8cfdc000 4712 send_ipi = 1;
c8076604
GH		 4713 }
4714 }
e935b837 4715 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4716
4717 if (freq->old < freq->new && send_ipi) {
4718 /*
4719 * We upscale the frequency. Must make the guest
4720 * doesn't see old kvmclock values while running with
4721 * the new frequency, otherwise we risk the guest sees
4722 * time go backwards.
4723 *
4724 * In case we update the frequency for another cpu
4725 * (which might be in guest context) send an interrupt
4726 * to kick the cpu out of guest context. Next time
4727 * guest context is entered kvmclock will be updated,
4728 * so the guest will not see stale values.
4729 */
8cfdc000 4730 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4731 }
4732 return 0;
4733}
4734
4735static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4736 .notifier_call = kvmclock_cpufreq_notifier
4737};
4738
4739static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4740 unsigned long action, void *hcpu)
4741{
4742 unsigned int cpu = (unsigned long)hcpu;
4743
4744 switch (action) {
4745 case CPU_ONLINE:
4746 case CPU_DOWN_FAILED:
4747 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4748 break;
4749 case CPU_DOWN_PREPARE:
4750 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4751 break;
4752 }
4753 return NOTIFY_OK;
4754}
4755
4756static struct notifier_block kvmclock_cpu_notifier_block = {
4757 .notifier_call = kvmclock_cpu_notifier,
4758 .priority = -INT_MAX
c8076604
GH		 4759};
4760
b820cc0c
ZA		 4761static void kvm_timer_init(void)
4762{
4763 int cpu;
4764
c285545f 4765 max_tsc_khz = tsc_khz;
8cfdc000 4766 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4767 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4768#ifdef CONFIG_CPU_FREQ
4769 struct cpufreq_policy policy;
4770 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4771 cpu = get_cpu();
4772 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4773 if (policy.cpuinfo.max_freq)
4774 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4775 put_cpu();
c285545f 4776#endif
b820cc0c
ZA		 4777 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4778 CPUFREQ_TRANSITION_NOTIFIER);
4779 }
c285545f 4780 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4781 for_each_online_cpu(cpu)
4782 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4783}
4784
ff9d07a0
ZY		 4785static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4786
f5132b01 4787int kvm_is_in_guest(void)
ff9d07a0 4788{
086c9855 4789 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4790}
4791
4792static int kvm_is_user_mode(void)
4793{
4794 int user_mode = 3;
dcf46b94 4795
086c9855
AS		 4796 if (__this_cpu_read(current_vcpu))
4797 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4798
ff9d07a0
ZY		 4799 return user_mode != 0;
4800}
4801
4802static unsigned long kvm_get_guest_ip(void)
4803{
4804 unsigned long ip = 0;
dcf46b94 4805
086c9855
AS		 4806 if (__this_cpu_read(current_vcpu))
4807 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4808
ff9d07a0
ZY		 4809 return ip;
4810}
4811
4812static struct perf_guest_info_callbacks kvm_guest_cbs = {
4813 .is_in_guest = kvm_is_in_guest,
4814 .is_user_mode = kvm_is_user_mode,
4815 .get_guest_ip = kvm_get_guest_ip,
4816};
4817
4818void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4819{
086c9855 4820 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4821}
4822EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4823
4824void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4825{
086c9855 4826 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4827}
4828EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4829
ce88decf
XG		 4830static void kvm_set_mmio_spte_mask(void)
4831{
4832 u64 mask;
4833 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4834
4835 /*
4836 * Set the reserved bits and the present bit of an paging-structure
4837 * entry to generate page fault with PFER.RSV = 1.
4838 */
4839 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4840 mask |= 1ull;
4841
4842#ifdef CONFIG_X86_64
4843 /*
4844 * If reserved bit is not supported, clear the present bit to disable
4845 * mmio page fault.
4846 */
4847 if (maxphyaddr == 52)
4848 mask &= ~1ull;
4849#endif
4850
4851 kvm_mmu_set_mmio_spte_mask(mask);
4852}
4853
f8c16bba 4854int kvm_arch_init(void *opaque)
043405e1 4855{
b820cc0c 4856 int r;
f8c16bba
ZX		 4857 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4858
f8c16bba
ZX		 4859 if (kvm_x86_ops) {
4860 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4861 r = -EEXIST;
4862 goto out;
f8c16bba
ZX		 4863 }
4864
4865 if (!ops->cpu_has_kvm_support()) {
4866 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4867 r = -EOPNOTSUPP;
4868 goto out;
f8c16bba
ZX		 4869 }
4870 if (ops->disabled_by_bios()) {
4871 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4872 r = -EOPNOTSUPP;
4873 goto out;
f8c16bba
ZX		 4874 }
4875
97db56ce
AK		 4876 r = kvm_mmu_module_init();
4877 if (r)
4878 goto out;
4879
ce88decf 4880 kvm_set_mmio_spte_mask();
97db56ce
AK		 4881 kvm_init_msr_list();
4882
f8c16bba 4883 kvm_x86_ops = ops;
7b52345e 4884 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4885 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4886
b820cc0c 4887 kvm_timer_init();
c8076604 4888
ff9d07a0
ZY		 4889 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4890
2acf923e
DC		 4891 if (cpu_has_xsave)
4892 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4893
c5cc421b 4894 kvm_lapic_init();
f8c16bba 4895 return 0;
56c6d28a
ZX		 4896
4897out:
56c6d28a 4898 return r;
043405e1 4899}
8776e519 4900
f8c16bba
ZX		 4901void kvm_arch_exit(void)
4902{
ff9d07a0
ZY		 4903 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4904
888d256e
JK		 4905 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4906 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4907 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4908 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4909 kvm_x86_ops = NULL;
56c6d28a
ZX		 4910 kvm_mmu_module_exit();
4911}
f8c16bba 4912
8776e519
HB		 4913int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4914{
4915 ++vcpu->stat.halt_exits;
4916 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4917 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4918 return 1;
4919 } else {
4920 vcpu->run->exit_reason = KVM_EXIT_HLT;
4921 return 0;
4922 }
4923}
4924EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4925
55cd8e5a
GN		 4926int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4927{
4928 u64 param, ingpa, outgpa, ret;
4929 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4930 bool fast, longmode;
4931 int cs_db, cs_l;
4932
4933 /*
4934 * hypercall generates UD from non zero cpl and real mode
4935 * per HYPER-V spec
4936 */
3eeb3288 4937 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4938 kvm_queue_exception(vcpu, UD_VECTOR);
4939 return 0;
4940 }
4941
4942 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4943 longmode = is_long_mode(vcpu) && cs_l == 1;
4944
4945 if (!longmode) {
ccd46936
GN		 4946 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4947 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4948 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4949 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4950 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4951 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4952 }
4953#ifdef CONFIG_X86_64
4954 else {
4955 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4956 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4957 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4958 }
4959#endif
4960
4961 code = param & 0xffff;
4962 fast = (param >> 16) & 0x1;
4963 rep_cnt = (param >> 32) & 0xfff;
4964 rep_idx = (param >> 48) & 0xfff;
4965
4966 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4967
c25bc163
GN		 4968 switch (code) {
4969 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4970 kvm_vcpu_on_spin(vcpu);
4971 break;
4972 default:
4973 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4974 break;
4975 }
55cd8e5a
GN		 4976
4977 ret = res | (((u64)rep_done & 0xfff) << 32);
4978 if (longmode) {
4979 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4980 } else {
4981 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4982 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4983 }
4984
4985 return 1;
4986}
4987
8776e519
HB		 4988int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4989{
4990 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4991 int r = 1;
8776e519 4992
55cd8e5a
GN		 4993 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4994 return kvm_hv_hypercall(vcpu);
4995
5fdbf976
MT		 4996 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4997 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4998 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4999 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5000 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5001
229456fc 5002 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5003
8776e519
HB		 5004 if (!is_long_mode(vcpu)) {
5005 nr &= 0xFFFFFFFF;
5006 a0 &= 0xFFFFFFFF;
5007 a1 &= 0xFFFFFFFF;
5008 a2 &= 0xFFFFFFFF;
5009 a3 &= 0xFFFFFFFF;
5010 }
5011
07708c4a
JK		 5012 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5013 ret = -KVM_EPERM;
5014 goto out;
5015 }
5016
8776e519 5017 switch (nr) {
b93463aa
AK		 5018 case KVM_HC_VAPIC_POLL_IRQ:
5019 ret = 0;
5020 break;
8776e519
HB		 5021 default:
5022 ret = -KVM_ENOSYS;
5023 break;
5024 }
07708c4a 5025out:
5fdbf976 5026 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5027 ++vcpu->stat.hypercalls;
2f333bcb 5028 return r;
8776e519
HB		 5029}
5030EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5031
b6785def 5032static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5033{
d6aa1000 5034 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5035 char instruction[3];
5fdbf976 5036 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5037
8776e519
HB		 5038 /*
5039 * Blow out the MMU to ensure that no other VCPU has an active mapping
5040 * to ensure that the updated hypercall appears atomically across all
5041 * VCPUs.
5042 */
5043 kvm_mmu_zap_all(vcpu->kvm);
5044
8776e519 5045 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5046
9d74191a 5047 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5048}
5049
b6c7a5dc
HB		 5050/*
5051 * Check if userspace requested an interrupt window, and that the
5052 * interrupt window is open.
5053 *
5054 * No need to exit to userspace if we already have an interrupt queued.
5055 */
851ba692 5056static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5057{
8061823a 5058 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5059 vcpu->run->request_interrupt_window &&
5df56646 5060 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5061}
5062
851ba692 5063static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5064{
851ba692
AK		 5065 struct kvm_run *kvm_run = vcpu->run;
5066
91586a3b 5067 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5068 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5069 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5070 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5071 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5072 else
b6c7a5dc 5073 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5074 kvm_arch_interrupt_allowed(vcpu) &&
5075 !kvm_cpu_has_interrupt(vcpu) &&
5076 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5077}
5078
4484141a 5079static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5080{
5081 struct kvm_lapic *apic = vcpu->arch.apic;
5082 struct page *page;
5083
5084 if (!apic || !apic->vapic_addr)
4484141a 5085 return 0;
b93463aa
AK		 5086
5087 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5088 if (is_error_page(page))
5089 return -EFAULT;
72dc67a6
IE		 5090
5091 vcpu->arch.apic->vapic_page = page;
4484141a 5092 return 0;
b93463aa
AK		 5093}
5094
5095static void vapic_exit(struct kvm_vcpu *vcpu)
5096{
5097 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5098 int idx;
b93463aa
AK		 5099
5100 if (!apic || !apic->vapic_addr)
5101 return;
5102
f656ce01 5103 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5104 kvm_release_page_dirty(apic->vapic_page);
5105 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5106 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5107}
5108
95ba8273
GN		 5109static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5110{
5111 int max_irr, tpr;
5112
5113 if (!kvm_x86_ops->update_cr8_intercept)
5114 return;
5115
88c808fd
AK		 5116 if (!vcpu->arch.apic)
5117 return;
5118
8db3baa2
GN		 5119 if (!vcpu->arch.apic->vapic_addr)
5120 max_irr = kvm_lapic_find_highest_irr(vcpu);
5121 else
5122 max_irr = -1;
95ba8273
GN		 5123
5124 if (max_irr != -1)
5125 max_irr >>= 4;
5126
5127 tpr = kvm_lapic_get_cr8(vcpu);
5128
5129 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5130}
5131
851ba692 5132static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5133{
5134 /* try to reinject previous events if any */
b59bb7bd 5135 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5136 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5137 vcpu->arch.exception.has_error_code,
5138 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5139 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5140 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5141 vcpu->arch.exception.error_code,
5142 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5143 return;
5144 }
5145
95ba8273
GN		 5146 if (vcpu->arch.nmi_injected) {
5147 kvm_x86_ops->set_nmi(vcpu);
5148 return;
5149 }
5150
5151 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5152 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5153 return;
5154 }
5155
5156 /* try to inject new event if pending */
5157 if (vcpu->arch.nmi_pending) {
5158 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5159 --vcpu->arch.nmi_pending;
95ba8273
GN		 5160 vcpu->arch.nmi_injected = true;
5161 kvm_x86_ops->set_nmi(vcpu);
5162 }
5163 } else if (kvm_cpu_has_interrupt(vcpu)) {
5164 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5165 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5166 false);
5167 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5168 }
5169 }
5170}
5171
2acf923e
DC		 5172static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5173{
5174 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5175 !vcpu->guest_xcr0_loaded) {
5176 /* kvm_set_xcr() also depends on this */
5177 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5178 vcpu->guest_xcr0_loaded = 1;
5179 }
5180}
5181
5182static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5183{
5184 if (vcpu->guest_xcr0_loaded) {
5185 if (vcpu->arch.xcr0 != host_xcr0)
5186 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5187 vcpu->guest_xcr0_loaded = 0;
5188 }
5189}
5190
7460fb4a
AK		 5191static void process_nmi(struct kvm_vcpu *vcpu)
5192{
5193 unsigned limit = 2;
5194
5195 /*
5196 * x86 is limited to one NMI running, and one NMI pending after it.
5197 * If an NMI is already in progress, limit further NMIs to just one.
5198 * Otherwise, allow two (and we'll inject the first one immediately).
5199 */
5200 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5201 limit = 1;
5202
5203 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5204 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5205 kvm_make_request(KVM_REQ_EVENT, vcpu);
5206}
5207
851ba692 5208static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5209{
5210 int r;
6a8b1d13 5211 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5212 vcpu->run->request_interrupt_window;
d6185f20 5213 bool req_immediate_exit = 0;
b6c7a5dc 5214
3e007509 5215 if (vcpu->requests) {
a8eeb04a 5216 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5217 kvm_mmu_unload(vcpu);
a8eeb04a 5218 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5219 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5220 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5221 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5222 if (unlikely(r))
5223 goto out;
5224 }
a8eeb04a 5225 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5226 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5227 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5228 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5229 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5230 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5231 r = 0;
5232 goto out;
5233 }
a8eeb04a 5234 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5235 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5236 r = 0;
5237 goto out;
5238 }
a8eeb04a 5239 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5240 vcpu->fpu_active = 0;
5241 kvm_x86_ops->fpu_deactivate(vcpu);
5242 }
af585b92
GN		 5243 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5244 /* Page is swapped out. Do synthetic halt */
5245 vcpu->arch.apf.halted = true;
5246 r = 1;
5247 goto out;
5248 }
c9aaa895
GC		 5249 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5250 record_steal_time(vcpu);
7460fb4a
AK		 5251 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5252 process_nmi(vcpu);
d6185f20
NHE		 5253 req_immediate_exit =
5254 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5255 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5256 kvm_handle_pmu_event(vcpu);
5257 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5258 kvm_deliver_pmi(vcpu);
2f52d58c 5259 }
b93463aa 5260
b463a6f7
AK		 5261 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5262 inject_pending_event(vcpu);
5263
5264 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5265 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5266 kvm_x86_ops->enable_nmi_window(vcpu);
5267 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5268 kvm_x86_ops->enable_irq_window(vcpu);
5269
5270 if (kvm_lapic_enabled(vcpu)) {
5271 update_cr8_intercept(vcpu);
5272 kvm_lapic_sync_to_vapic(vcpu);
5273 }
5274 }
5275
d8368af8
AK		 5276 r = kvm_mmu_reload(vcpu);
5277 if (unlikely(r)) {
d905c069 5278 goto cancel_injection;
d8368af8
AK		 5279 }
5280
b6c7a5dc
HB		 5281 preempt_disable();
5282
5283 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5284 if (vcpu->fpu_active)
5285 kvm_load_guest_fpu(vcpu);
2acf923e 5286 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5287
6b7e2d09
XG		 5288 vcpu->mode = IN_GUEST_MODE;
5289
5290 /* We should set ->mode before check ->requests,
5291 * see the comment in make_all_cpus_request.
5292 */
5293 smp_mb();
b6c7a5dc 5294
d94e1dc9 5295 local_irq_disable();
32f88400 5296
6b7e2d09 5297 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5298 || need_resched() || signal_pending(current)) {
6b7e2d09 5299 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5300 smp_wmb();
6c142801
AK		 5301 local_irq_enable();
5302 preempt_enable();
5303 r = 1;
d905c069 5304 goto cancel_injection;
6c142801
AK		 5305 }
5306
f656ce01 5307 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5308
d6185f20
NHE		 5309 if (req_immediate_exit)
5310 smp_send_reschedule(vcpu->cpu);
5311
b6c7a5dc
HB		 5312 kvm_guest_enter();
5313
42dbaa5a 5314 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5315 set_debugreg(0, 7);
5316 set_debugreg(vcpu->arch.eff_db[0], 0);
5317 set_debugreg(vcpu->arch.eff_db[1], 1);
5318 set_debugreg(vcpu->arch.eff_db[2], 2);
5319 set_debugreg(vcpu->arch.eff_db[3], 3);
5320 }
b6c7a5dc 5321
229456fc 5322 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5323 kvm_x86_ops->run(vcpu);
b6c7a5dc 5324
24f1e32c
FW		 5325 /*
5326 * If the guest has used debug registers, at least dr7
5327 * will be disabled while returning to the host.
5328 * If we don't have active breakpoints in the host, we don't
5329 * care about the messed up debug address registers. But if
5330 * we have some of them active, restore the old state.
5331 */
59d8eb53 5332 if (hw_breakpoint_active())
24f1e32c 5333 hw_breakpoint_restore();
42dbaa5a 5334
d5c1785d 5335 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5336
6b7e2d09 5337 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5338 smp_wmb();
b6c7a5dc
HB		 5339 local_irq_enable();
5340
5341 ++vcpu->stat.exits;
5342
5343 /*
5344 * We must have an instruction between local_irq_enable() and
5345 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5346 * the interrupt shadow. The stat.exits increment will do nicely.
5347 * But we need to prevent reordering, hence this barrier():
5348 */
5349 barrier();
5350
5351 kvm_guest_exit();
5352
5353 preempt_enable();
5354
f656ce01 5355 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5356
b6c7a5dc
HB		 5357 /*
5358 * Profile KVM exit RIPs:
5359 */
5360 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5361 unsigned long rip = kvm_rip_read(vcpu);
5362 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5363 }
5364
cc578287
ZA		 5365 if (unlikely(vcpu->arch.tsc_always_catchup))
5366 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5367
5cfb1d5a
MT		 5368 if (vcpu->arch.apic_attention)
5369 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5370
851ba692 5371 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5372 return r;
5373
5374cancel_injection:
5375 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5376 if (unlikely(vcpu->arch.apic_attention))
5377 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5378out:
5379 return r;
5380}
b6c7a5dc 5381
09cec754 5382
851ba692 5383static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5384{
5385 int r;
f656ce01 5386 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5387
5388 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5389 pr_debug("vcpu %d received sipi with vector # %x\n",
5390 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5391 kvm_lapic_reset(vcpu);
8b6e4547 5392 r = kvm_vcpu_reset(vcpu);
d7690175
MT		 5393 if (r)
5394 return r;
5395 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5396 }
5397
f656ce01 5398 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 5399 r = vapic_enter(vcpu);
5400 if (r) {
5401 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5402 return r;
5403 }
d7690175
MT		 5404
5405 r = 1;
5406 while (r > 0) {
af585b92
GN		 5407 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5408 !vcpu->arch.apf.halted)
851ba692 5409 r = vcpu_enter_guest(vcpu);
d7690175 5410 else {
f656ce01 5411 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5412 kvm_vcpu_block(vcpu);
f656ce01 5413 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5414 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5415 {
5416 switch(vcpu->arch.mp_state) {
5417 case KVM_MP_STATE_HALTED:
d7690175 5418 vcpu->arch.mp_state =
09cec754
GN		 5419 KVM_MP_STATE_RUNNABLE;
5420 case KVM_MP_STATE_RUNNABLE:
af585b92 5421 vcpu->arch.apf.halted = false;
09cec754
GN		 5422 break;
5423 case KVM_MP_STATE_SIPI_RECEIVED:
5424 default:
5425 r = -EINTR;
5426 break;
5427 }
5428 }
d7690175
MT		 5429 }
5430
09cec754
GN		 5431 if (r <= 0)
5432 break;
5433
5434 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5435 if (kvm_cpu_has_pending_timer(vcpu))
5436 kvm_inject_pending_timer_irqs(vcpu);
5437
851ba692 5438 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5439 r = -EINTR;
851ba692 5440 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5441 ++vcpu->stat.request_irq_exits;
5442 }
af585b92
GN		 5443
5444 kvm_check_async_pf_completion(vcpu);
5445
09cec754
GN		 5446 if (signal_pending(current)) {
5447 r = -EINTR;
851ba692 5448 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5449 ++vcpu->stat.signal_exits;
5450 }
5451 if (need_resched()) {
f656ce01 5452 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5453 kvm_resched(vcpu);
f656ce01 5454 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5455 }
b6c7a5dc
HB		 5456 }
5457
f656ce01 5458 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5459
b93463aa
AK		 5460 vapic_exit(vcpu);
5461
b6c7a5dc
HB		 5462 return r;
5463}
5464
716d51ab
GN		 5465static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5466{
5467 int r;
5468 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5469 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5470 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5471 if (r != EMULATE_DONE)
5472 return 0;
5473 return 1;
5474}
5475
5476static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5477{
5478 BUG_ON(!vcpu->arch.pio.count);
5479
5480 return complete_emulated_io(vcpu);
5481}
5482
f78146b0
AK		 5483/*
5484 * Implements the following, as a state machine:
5485 *
5486 * read:
5487 * for each fragment
5488 * write gpa, len
5489 * exit
5490 * copy data
5491 * execute insn
5492 *
5493 * write:
5494 * for each fragment
5495 * write gpa, len
5496 * copy data
5497 * exit
5498 */
716d51ab 5499static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 5500{
5501 struct kvm_run *run = vcpu->run;
f78146b0 5502 struct kvm_mmio_fragment *frag;
5287f194 5503
716d51ab 5504 BUG_ON(!vcpu->mmio_needed);
5287f194 5505
716d51ab
GN		 5506 /* Complete previous fragment */
5507 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
5508 if (!vcpu->mmio_is_write)
5509 memcpy(frag->data, run->mmio.data, frag->len);
5510 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5511 vcpu->mmio_needed = 0;
cef4dea0 5512 if (vcpu->mmio_is_write)
716d51ab
GN		 5513 return 1;
5514 vcpu->mmio_read_completed = 1;
5515 return complete_emulated_io(vcpu);
5516 }
5517 /* Initiate next fragment */
5518 ++frag;
5519 run->exit_reason = KVM_EXIT_MMIO;
5520 run->mmio.phys_addr = frag->gpa;
5521 if (vcpu->mmio_is_write)
5522 memcpy(run->mmio.data, frag->data, frag->len);
5523 run->mmio.len = frag->len;
5524 run->mmio.is_write = vcpu->mmio_is_write;
5525 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5526 return 0;
5287f194
AK		 5527}
5528
716d51ab 5529
b6c7a5dc
HB		 5530int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5531{
5532 int r;
5533 sigset_t sigsaved;
5534
e5c30142
AK		 5535 if (!tsk_used_math(current) && init_fpu(current))
5536 return -ENOMEM;
5537
ac9f6dc0
AK		 5538 if (vcpu->sigset_active)
5539 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5540
a4535290 5541 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5542 kvm_vcpu_block(vcpu);
d7690175 5543 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5544 r = -EAGAIN;
5545 goto out;
b6c7a5dc
HB		 5546 }
5547
b6c7a5dc 5548 /* re-sync apic's tpr */
eea1cff9
AP		 5549 if (!irqchip_in_kernel(vcpu->kvm)) {
5550 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5551 r = -EINVAL;
5552 goto out;
5553 }
5554 }
b6c7a5dc 5555
716d51ab
GN		 5556 if (unlikely(vcpu->arch.complete_userspace_io)) {
5557 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
5558 vcpu->arch.complete_userspace_io = NULL;
5559 r = cui(vcpu);
5560 if (r <= 0)
5561 goto out;
5562 } else
5563 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 5564
851ba692 5565 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5566
5567out:
f1d86e46 5568 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5569 if (vcpu->sigset_active)
5570 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5571
b6c7a5dc
HB		 5572 return r;
5573}
5574
5575int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5576{
7ae441ea
GN		 5577 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5578 /*
5579 * We are here if userspace calls get_regs() in the middle of
5580 * instruction emulation. Registers state needs to be copied
4a969980 5581 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 5582 * that usually, but some bad designed PV devices (vmware
5583 * backdoor interface) need this to work
5584 */
dd856efa 5585 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 5586 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5587 }
5fdbf976
MT		 5588 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5589 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5590 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5591 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5592 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5593 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5594 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5595 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5596#ifdef CONFIG_X86_64
5fdbf976
MT		 5597 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5598 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5599 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5600 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5601 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5602 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5603 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5604 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5605#endif
5606
5fdbf976 5607 regs->rip = kvm_rip_read(vcpu);
91586a3b 5608 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5609
b6c7a5dc
HB		 5610 return 0;
5611}
5612
5613int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5614{
7ae441ea
GN		 5615 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5616 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5617
5fdbf976
MT		 5618 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5619 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5620 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5621 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5622 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5623 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5624 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5625 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5626#ifdef CONFIG_X86_64
5fdbf976
MT		 5627 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5628 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5629 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5630 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5631 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5632 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5633 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5634 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5635#endif
5636
5fdbf976 5637 kvm_rip_write(vcpu, regs->rip);
91586a3b 5638 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5639
b4f14abd
JK		 5640 vcpu->arch.exception.pending = false;
5641
3842d135
AK		 5642 kvm_make_request(KVM_REQ_EVENT, vcpu);
5643
b6c7a5dc
HB		 5644 return 0;
5645}
5646
b6c7a5dc
HB		 5647void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5648{
5649 struct kvm_segment cs;
5650
3e6e0aab 5651 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5652 *db = cs.db;
5653 *l = cs.l;
5654}
5655EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5656
5657int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5658 struct kvm_sregs *sregs)
5659{
89a27f4d 5660 struct desc_ptr dt;
b6c7a5dc 5661
3e6e0aab
GT		 5662 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5663 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5664 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5665 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5666 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5667 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5668
3e6e0aab
GT		 5669 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5670 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5671
5672 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5673 sregs->idt.limit = dt.size;
5674 sregs->idt.base = dt.address;
b6c7a5dc 5675 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5676 sregs->gdt.limit = dt.size;
5677 sregs->gdt.base = dt.address;
b6c7a5dc 5678
4d4ec087 5679 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5680 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5681 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5682 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5683 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5684 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5685 sregs->apic_base = kvm_get_apic_base(vcpu);
5686
923c61bb 5687 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5688
36752c9b 5689 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5690 set_bit(vcpu->arch.interrupt.nr,
5691 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5692
b6c7a5dc
HB		 5693 return 0;
5694}
5695
62d9f0db
MT		 5696int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5697 struct kvm_mp_state *mp_state)
5698{
62d9f0db 5699 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5700 return 0;
5701}
5702
5703int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5704 struct kvm_mp_state *mp_state)
5705{
62d9f0db 5706 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5707 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5708 return 0;
5709}
5710
7f3d35fd
KW		 5711int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5712 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 5713{
9d74191a 5714 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5715 int ret;
e01c2426 5716
8ec4722d 5717 init_emulate_ctxt(vcpu);
c697518a 5718
7f3d35fd 5719 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 5720 has_error_code, error_code);
c697518a 5721
c697518a 5722 if (ret)
19d04437 5723 return EMULATE_FAIL;
37817f29 5724
9d74191a
TY		 5725 kvm_rip_write(vcpu, ctxt->eip);
5726 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5727 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5728 return EMULATE_DONE;
37817f29
IE		 5729}
5730EXPORT_SYMBOL_GPL(kvm_task_switch);
5731
b6c7a5dc
HB		 5732int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5733 struct kvm_sregs *sregs)
5734{
5735 int mmu_reset_needed = 0;
63f42e02 5736 int pending_vec, max_bits, idx;
89a27f4d 5737 struct desc_ptr dt;
b6c7a5dc 5738
89a27f4d
GN		 5739 dt.size = sregs->idt.limit;
5740 dt.address = sregs->idt.base;
b6c7a5dc 5741 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5742 dt.size = sregs->gdt.limit;
5743 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5744 kvm_x86_ops->set_gdt(vcpu, &dt);
5745
ad312c7c 5746 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5747 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5748 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5749 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5750
2d3ad1f4 5751 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5752
f6801dff 5753 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5754 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5755 kvm_set_apic_base(vcpu, sregs->apic_base);
5756
4d4ec087 5757 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5758 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5759 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5760
fc78f519 5761 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5762 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5763 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5764 kvm_update_cpuid(vcpu);
63f42e02
XG		 5765
5766 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5767 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5768 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5769 mmu_reset_needed = 1;
5770 }
63f42e02 5771 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5772
5773 if (mmu_reset_needed)
5774 kvm_mmu_reset_context(vcpu);
5775
a50abc3b 5776 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 5777 pending_vec = find_first_bit(
5778 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5779 if (pending_vec < max_bits) {
66fd3f7f 5780 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5781 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5782 }
5783
3e6e0aab
GT		 5784 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5785 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5786 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5787 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5788 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5789 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5790
3e6e0aab
GT		 5791 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5792 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5793
5f0269f5
ME		 5794 update_cr8_intercept(vcpu);
5795
9c3e4aab 5796 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5797 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5798 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5799 !is_protmode(vcpu))
9c3e4aab
MT		 5800 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5801
3842d135
AK		 5802 kvm_make_request(KVM_REQ_EVENT, vcpu);
5803
b6c7a5dc
HB		 5804 return 0;
5805}
5806
d0bfb940
JK		 5807int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5808 struct kvm_guest_debug *dbg)
b6c7a5dc 5809{
355be0b9 5810 unsigned long rflags;
ae675ef0 5811 int i, r;
b6c7a5dc 5812
4f926bf2
JK		 5813 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5814 r = -EBUSY;
5815 if (vcpu->arch.exception.pending)
2122ff5e 5816 goto out;
4f926bf2
JK		 5817 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5818 kvm_queue_exception(vcpu, DB_VECTOR);
5819 else
5820 kvm_queue_exception(vcpu, BP_VECTOR);
5821 }
5822
91586a3b
JK		 5823 /*
5824 * Read rflags as long as potentially injected trace flags are still
5825 * filtered out.
5826 */
5827 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5828
5829 vcpu->guest_debug = dbg->control;
5830 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5831 vcpu->guest_debug = 0;
5832
5833 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5834 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5835 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 5836 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 5837 } else {
5838 for (i = 0; i < KVM_NR_DB_REGS; i++)
5839 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 5840 }
c8639010 5841 kvm_update_dr7(vcpu);
ae675ef0 5842
f92653ee
JK		 5843 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5844 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5845 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5846
91586a3b
JK		 5847 /*
5848 * Trigger an rflags update that will inject or remove the trace
5849 * flags.
5850 */
5851 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5852
c8639010 5853 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 5854
4f926bf2 5855 r = 0;
d0bfb940 5856
2122ff5e 5857out:
b6c7a5dc
HB		 5858
5859 return r;
5860}
5861
8b006791
ZX		 5862/*
5863 * Translate a guest virtual address to a guest physical address.
5864 */
5865int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5866 struct kvm_translation *tr)
5867{
5868 unsigned long vaddr = tr->linear_address;
5869 gpa_t gpa;
f656ce01 5870 int idx;
8b006791 5871
f656ce01 5872 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5873 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5874 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5875 tr->physical_address = gpa;
5876 tr->valid = gpa != UNMAPPED_GVA;
5877 tr->writeable = 1;
5878 tr->usermode = 0;
8b006791
ZX		 5879
5880 return 0;
5881}
5882
d0752060
HB		 5883int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5884{
98918833
SY		 5885 struct i387_fxsave_struct *fxsave =
5886 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5887
d0752060
HB		 5888 memcpy(fpu->fpr, fxsave->st_space, 128);
5889 fpu->fcw = fxsave->cwd;
5890 fpu->fsw = fxsave->swd;
5891 fpu->ftwx = fxsave->twd;
5892 fpu->last_opcode = fxsave->fop;
5893 fpu->last_ip = fxsave->rip;
5894 fpu->last_dp = fxsave->rdp;
5895 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5896
d0752060
HB		 5897 return 0;
5898}
5899
5900int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5901{
98918833
SY		 5902 struct i387_fxsave_struct *fxsave =
5903 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5904
d0752060
HB		 5905 memcpy(fxsave->st_space, fpu->fpr, 128);
5906 fxsave->cwd = fpu->fcw;
5907 fxsave->swd = fpu->fsw;
5908 fxsave->twd = fpu->ftwx;
5909 fxsave->fop = fpu->last_opcode;
5910 fxsave->rip = fpu->last_ip;
5911 fxsave->rdp = fpu->last_dp;
5912 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5913
d0752060
HB		 5914 return 0;
5915}
5916
10ab25cd 5917int fx_init(struct kvm_vcpu *vcpu)
d0752060 5918{
10ab25cd
JK		 5919 int err;
5920
5921 err = fpu_alloc(&vcpu->arch.guest_fpu);
5922 if (err)
5923 return err;
5924
98918833 5925 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5926
2acf923e
DC		 5927 /*
5928 * Ensure guest xcr0 is valid for loading
5929 */
5930 vcpu->arch.xcr0 = XSTATE_FP;
5931
ad312c7c 5932 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5933
5934 return 0;
d0752060
HB		 5935}
5936EXPORT_SYMBOL_GPL(fx_init);
5937
98918833
SY		 5938static void fx_free(struct kvm_vcpu *vcpu)
5939{
5940 fpu_free(&vcpu->arch.guest_fpu);
5941}
5942
d0752060
HB		 5943void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5944{
2608d7a1 5945 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5946 return;
5947
2acf923e
DC		 5948 /*
5949 * Restore all possible states in the guest,
5950 * and assume host would use all available bits.
5951 * Guest xcr0 would be loaded later.
5952 */
5953 kvm_put_guest_xcr0(vcpu);
d0752060 5954 vcpu->guest_fpu_loaded = 1;
b1a74bf8 5955 __kernel_fpu_begin();
98918833 5956 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5957 trace_kvm_fpu(1);
d0752060 5958}
d0752060
HB		 5959
5960void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5961{
2acf923e
DC		 5962 kvm_put_guest_xcr0(vcpu);
5963
d0752060
HB		 5964 if (!vcpu->guest_fpu_loaded)
5965 return;
5966
5967 vcpu->guest_fpu_loaded = 0;
98918833 5968 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 5969 __kernel_fpu_end();
f096ed85 5970 ++vcpu->stat.fpu_reload;
a8eeb04a 5971 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5972 trace_kvm_fpu(0);
d0752060 5973}
e9b11c17
ZX		 5974
5975void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5976{
12f9a48f 5977 kvmclock_reset(vcpu);
7f1ea208 5978
f5f48ee1 5979 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5980 fx_free(vcpu);
e9b11c17
ZX		 5981 kvm_x86_ops->vcpu_free(vcpu);
5982}
5983
5984struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5985 unsigned int id)
5986{
6755bae8
ZA		 5987 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5988 printk_once(KERN_WARNING
5989 "kvm: SMP vm created on host with unstable TSC; "
5990 "guest TSC will not be reliable\n");
26e5215f
AK		 5991 return kvm_x86_ops->vcpu_create(kvm, id);
5992}
e9b11c17 5993
26e5215f
AK		 5994int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5995{
5996 int r;
e9b11c17 5997
0bed3b56 5998 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 5999 r = vcpu_load(vcpu);
6000 if (r)
6001 return r;
8b6e4547 6002 r = kvm_vcpu_reset(vcpu);
e9b11c17
ZX		 6003 if (r == 0)
6004 r = kvm_mmu_setup(vcpu);
6005 vcpu_put(vcpu);
e9b11c17 6006
26e5215f 6007 return r;
e9b11c17
ZX		 6008}
6009
d40ccc62 6010void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6011{
9fc77441 6012 int r;
344d9588
GN		 6013 vcpu->arch.apf.msr_val = 0;
6014
9fc77441
MT		 6015 r = vcpu_load(vcpu);
6016 BUG_ON(r);
e9b11c17
ZX		 6017 kvm_mmu_unload(vcpu);
6018 vcpu_put(vcpu);
6019
98918833 6020 fx_free(vcpu);
e9b11c17
ZX		 6021 kvm_x86_ops->vcpu_free(vcpu);
6022}
6023
8b6e4547 6024static int kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6025{
7460fb4a
AK		 6026 atomic_set(&vcpu->arch.nmi_queued, 0);
6027 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6028 vcpu->arch.nmi_injected = false;
6029
42dbaa5a
JK		 6030 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6031 vcpu->arch.dr6 = DR6_FIXED_1;
6032 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6033 kvm_update_dr7(vcpu);
42dbaa5a 6034
3842d135 6035 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6036 vcpu->arch.apf.msr_val = 0;
c9aaa895 6037 vcpu->arch.st.msr_val = 0;
3842d135 6038
12f9a48f
GC		 6039 kvmclock_reset(vcpu);
6040
af585b92
GN		 6041 kvm_clear_async_pf_completion_queue(vcpu);
6042 kvm_async_pf_hash_reset(vcpu);
6043 vcpu->arch.apf.halted = false;
3842d135 6044
f5132b01
GN		 6045 kvm_pmu_reset(vcpu);
6046
e9b11c17
ZX		 6047 return kvm_x86_ops->vcpu_reset(vcpu);
6048}
6049
10474ae8 6050int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6051{
ca84d1a2
ZA		 6052 struct kvm *kvm;
6053 struct kvm_vcpu *vcpu;
6054 int i;
0dd6a6ed
ZA		 6055 int ret;
6056 u64 local_tsc;
6057 u64 max_tsc = 0;
6058 bool stable, backwards_tsc = false;
18863bdd
AK		 6059
6060 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6061 ret = kvm_x86_ops->hardware_enable(garbage);
6062 if (ret != 0)
6063 return ret;
6064
6065 local_tsc = native_read_tsc();
6066 stable = !check_tsc_unstable();
6067 list_for_each_entry(kvm, &vm_list, vm_list) {
6068 kvm_for_each_vcpu(i, vcpu, kvm) {
6069 if (!stable && vcpu->cpu == smp_processor_id())
6070 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6071 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6072 backwards_tsc = true;
6073 if (vcpu->arch.last_host_tsc > max_tsc)
6074 max_tsc = vcpu->arch.last_host_tsc;
6075 }
6076 }
6077 }
6078
6079 /*
6080 * Sometimes, even reliable TSCs go backwards. This happens on
6081 * platforms that reset TSC during suspend or hibernate actions, but
6082 * maintain synchronization. We must compensate. Fortunately, we can
6083 * detect that condition here, which happens early in CPU bringup,
6084 * before any KVM threads can be running. Unfortunately, we can't
6085 * bring the TSCs fully up to date with real time, as we aren't yet far
6086 * enough into CPU bringup that we know how much real time has actually
6087 * elapsed; our helper function, get_kernel_ns() will be using boot
6088 * variables that haven't been updated yet.
6089 *
6090 * So we simply find the maximum observed TSC above, then record the
6091 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6092 * the adjustment will be applied. Note that we accumulate
6093 * adjustments, in case multiple suspend cycles happen before some VCPU
6094 * gets a chance to run again. In the event that no KVM threads get a
6095 * chance to run, we will miss the entire elapsed period, as we'll have
6096 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6097 * loose cycle time. This isn't too big a deal, since the loss will be
6098 * uniform across all VCPUs (not to mention the scenario is extremely
6099 * unlikely). It is possible that a second hibernate recovery happens
6100 * much faster than a first, causing the observed TSC here to be
6101 * smaller; this would require additional padding adjustment, which is
6102 * why we set last_host_tsc to the local tsc observed here.
6103 *
6104 * N.B. - this code below runs only on platforms with reliable TSC,
6105 * as that is the only way backwards_tsc is set above. Also note
6106 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6107 * have the same delta_cyc adjustment applied if backwards_tsc
6108 * is detected. Note further, this adjustment is only done once,
6109 * as we reset last_host_tsc on all VCPUs to stop this from being
6110 * called multiple times (one for each physical CPU bringup).
6111 *
4a969980 6112 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6113 * will be compensated by the logic in vcpu_load, which sets the TSC to
6114 * catchup mode. This will catchup all VCPUs to real time, but cannot
6115 * guarantee that they stay in perfect synchronization.
6116 */
6117 if (backwards_tsc) {
6118 u64 delta_cyc = max_tsc - local_tsc;
6119 list_for_each_entry(kvm, &vm_list, vm_list) {
6120 kvm_for_each_vcpu(i, vcpu, kvm) {
6121 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6122 vcpu->arch.last_host_tsc = local_tsc;
6123 }
6124
6125 /*
6126 * We have to disable TSC offset matching.. if you were
6127 * booting a VM while issuing an S4 host suspend....
6128 * you may have some problem. Solving this issue is
6129 * left as an exercise to the reader.
6130 */
6131 kvm->arch.last_tsc_nsec = 0;
6132 kvm->arch.last_tsc_write = 0;
6133 }
6134
6135 }
6136 return 0;
e9b11c17
ZX		 6137}
6138
6139void kvm_arch_hardware_disable(void *garbage)
6140{
6141 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6142 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6143}
6144
6145int kvm_arch_hardware_setup(void)
6146{
6147 return kvm_x86_ops->hardware_setup();
6148}
6149
6150void kvm_arch_hardware_unsetup(void)
6151{
6152 kvm_x86_ops->hardware_unsetup();
6153}
6154
6155void kvm_arch_check_processor_compat(void *rtn)
6156{
6157 kvm_x86_ops->check_processor_compatibility(rtn);
6158}
6159
3e515705
AK		 6160bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6161{
6162 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6163}
6164
54e9818f
GN		 6165struct static_key kvm_no_apic_vcpu __read_mostly;
6166
e9b11c17
ZX		 6167int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6168{
6169 struct page *page;
6170 struct kvm *kvm;
6171 int r;
6172
6173 BUG_ON(vcpu->kvm == NULL);
6174 kvm = vcpu->kvm;
6175
9aabc88f 6176 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6177 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6178 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6179 else
a4535290 6180 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6181
6182 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6183 if (!page) {
6184 r = -ENOMEM;
6185 goto fail;
6186 }
ad312c7c 6187 vcpu->arch.pio_data = page_address(page);
e9b11c17 6188
cc578287 6189 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6190
e9b11c17
ZX		 6191 r = kvm_mmu_create(vcpu);
6192 if (r < 0)
6193 goto fail_free_pio_data;
6194
6195 if (irqchip_in_kernel(kvm)) {
6196 r = kvm_create_lapic(vcpu);
6197 if (r < 0)
6198 goto fail_mmu_destroy;
54e9818f
GN		 6199 } else
6200 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6201
890ca9ae
HY		 6202 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6203 GFP_KERNEL);
6204 if (!vcpu->arch.mce_banks) {
6205 r = -ENOMEM;
443c39bc 6206 goto fail_free_lapic;
890ca9ae
HY		 6207 }
6208 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6209
f5f48ee1
SY		 6210 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6211 goto fail_free_mce_banks;
6212
af585b92 6213 kvm_async_pf_hash_reset(vcpu);
f5132b01 6214 kvm_pmu_init(vcpu);
af585b92 6215
e9b11c17 6216 return 0;
f5f48ee1
SY		 6217fail_free_mce_banks:
6218 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6219fail_free_lapic:
6220 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6221fail_mmu_destroy:
6222 kvm_mmu_destroy(vcpu);
6223fail_free_pio_data:
ad312c7c 6224 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6225fail:
6226 return r;
6227}
6228
6229void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6230{
f656ce01
MT		 6231 int idx;
6232
f5132b01 6233 kvm_pmu_destroy(vcpu);
36cb93fd 6234 kfree(vcpu->arch.mce_banks);
e9b11c17 6235 kvm_free_lapic(vcpu);
f656ce01 6236 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6237 kvm_mmu_destroy(vcpu);
f656ce01 6238 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6239 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6240 if (!irqchip_in_kernel(vcpu->kvm))
6241 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6242}
d19a9cd2 6243
e08b9637 6244int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6245{
e08b9637
CO		 6246 if (type)
6247 return -EINVAL;
6248
f05e70ac 6249 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6250 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6251
5550af4d
SY		 6252 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6253 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6254 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6255 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6256 &kvm->arch.irq_sources_bitmap);
5550af4d 6257
038f8c11 6258 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6259 mutex_init(&kvm->arch.apic_map_lock);
53f658b3 6260
d89f5eff 6261 return 0;
d19a9cd2
ZX		 6262}
6263
6264static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6265{
9fc77441
MT		 6266 int r;
6267 r = vcpu_load(vcpu);
6268 BUG_ON(r);
d19a9cd2
ZX		 6269 kvm_mmu_unload(vcpu);
6270 vcpu_put(vcpu);
6271}
6272
6273static void kvm_free_vcpus(struct kvm *kvm)
6274{
6275 unsigned int i;
988a2cae 6276 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6277
6278 /*
6279 * Unpin any mmu pages first.
6280 */
af585b92
GN		 6281 kvm_for_each_vcpu(i, vcpu, kvm) {
6282 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6283 kvm_unload_vcpu_mmu(vcpu);
af585b92 6284 }
988a2cae
GN		 6285 kvm_for_each_vcpu(i, vcpu, kvm)
6286 kvm_arch_vcpu_free(vcpu);
6287
6288 mutex_lock(&kvm->lock);
6289 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6290 kvm->vcpus[i] = NULL;
d19a9cd2 6291
988a2cae
GN		 6292 atomic_set(&kvm->online_vcpus, 0);
6293 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6294}
6295
ad8ba2cd
SY		 6296void kvm_arch_sync_events(struct kvm *kvm)
6297{
ba4cef31 6298 kvm_free_all_assigned_devices(kvm);
aea924f6 6299 kvm_free_pit(kvm);
ad8ba2cd
SY		 6300}
6301
d19a9cd2
ZX		 6302void kvm_arch_destroy_vm(struct kvm *kvm)
6303{
6eb55818 6304 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6305 kfree(kvm->arch.vpic);
6306 kfree(kvm->arch.vioapic);
d19a9cd2 6307 kvm_free_vcpus(kvm);
3d45830c
AK		 6308 if (kvm->arch.apic_access_page)
6309 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6310 if (kvm->arch.ept_identity_pagetable)
6311 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 6312 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 6313}
0de10343 6314
db3fe4eb
TY		 6315void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6316 struct kvm_memory_slot *dont)
6317{
6318 int i;
6319
d89cc617
TY		 6320 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6321 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6322 kvm_kvfree(free->arch.rmap[i]);
6323 free->arch.rmap[i] = NULL;
77d11309 6324 }
d89cc617
TY		 6325 if (i == 0)
6326 continue;
6327
6328 if (!dont || free->arch.lpage_info[i - 1] !=
6329 dont->arch.lpage_info[i - 1]) {
6330 kvm_kvfree(free->arch.lpage_info[i - 1]);
6331 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6332 }
6333 }
6334}
6335
6336int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6337{
6338 int i;
6339
d89cc617 6340 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6341 unsigned long ugfn;
6342 int lpages;
d89cc617 6343 int level = i + 1;
db3fe4eb
TY		 6344
6345 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6346 slot->base_gfn, level) + 1;
6347
d89cc617
TY		 6348 slot->arch.rmap[i] =
6349 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6350 if (!slot->arch.rmap[i])
77d11309 6351 goto out_free;
d89cc617
TY		 6352 if (i == 0)
6353 continue;
77d11309 6354
d89cc617
TY		 6355 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6356 sizeof(*slot->arch.lpage_info[i - 1]));
6357 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6358 goto out_free;
6359
6360 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6361 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6362 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6363 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6364 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6365 /*
6366 * If the gfn and userspace address are not aligned wrt each
6367 * other, or if explicitly asked to, disable large page
6368 * support for this slot
6369 */
6370 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6371 !kvm_largepages_enabled()) {
6372 unsigned long j;
6373
6374 for (j = 0; j < lpages; ++j)
d89cc617 6375 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6376 }
6377 }
6378
6379 return 0;
6380
6381out_free:
d89cc617
TY		 6382 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6383 kvm_kvfree(slot->arch.rmap[i]);
6384 slot->arch.rmap[i] = NULL;
6385 if (i == 0)
6386 continue;
6387
6388 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6389 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6390 }
6391 return -ENOMEM;
6392}
6393
f7784b8e
MT		 6394int kvm_arch_prepare_memory_region(struct kvm *kvm,
6395 struct kvm_memory_slot *memslot,
0de10343 6396 struct kvm_memory_slot old,
f7784b8e 6397 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6398 int user_alloc)
6399{
f7784b8e 6400 int npages = memslot->npages;
7ac77099
AK		 6401 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6402
6403 /* Prevent internal slot pages from being moved by fork()/COW. */
6404 if (memslot->id >= KVM_MEMORY_SLOTS)
6405 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6406
6407 /*To keep backward compatibility with older userspace,
4a969980 6408 *x86 needs to handle !user_alloc case.
0de10343
ZX		 6409 */
6410 if (!user_alloc) {
aab2eb7a 6411 if (npages && !old.npages) {
604b38ac
AA		 6412 unsigned long userspace_addr;
6413
6be5ceb0 6414 userspace_addr = vm_mmap(NULL, 0,
604b38ac
AA		 6415 npages * PAGE_SIZE,
6416 PROT_READ | PROT_WRITE,
7ac77099 6417 map_flags,
604b38ac 6418 0);
0de10343 6419
604b38ac
AA		 6420 if (IS_ERR((void *)userspace_addr))
6421 return PTR_ERR((void *)userspace_addr);
6422
604b38ac 6423 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6424 }
6425 }
6426
f7784b8e
MT		 6427
6428 return 0;
6429}
6430
6431void kvm_arch_commit_memory_region(struct kvm *kvm,
6432 struct kvm_userspace_memory_region *mem,
6433 struct kvm_memory_slot old,
6434 int user_alloc)
6435{
6436
48c0e4e9 6437 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e 6438
aab2eb7a 6439 if (!user_alloc && !old.user_alloc && old.npages && !npages) {
f7784b8e
MT		 6440 int ret;
6441
bfce281c 6442 ret = vm_munmap(old.userspace_addr,
f7784b8e 6443 old.npages * PAGE_SIZE);
f7784b8e
MT		 6444 if (ret < 0)
6445 printk(KERN_WARNING
6446 "kvm_vm_ioctl_set_memory_region: "
6447 "failed to munmap memory\n");
6448 }
6449
48c0e4e9
XG		 6450 if (!kvm->arch.n_requested_mmu_pages)
6451 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6452
7c8a83b7 6453 spin_lock(&kvm->mmu_lock);
48c0e4e9 6454 if (nr_mmu_pages)
0de10343 6455 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6456 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6457 spin_unlock(&kvm->mmu_lock);
3b4dc3a0
MT		 6458 /*
6459 * If memory slot is created, or moved, we need to clear all
6460 * mmio sptes.
6461 */
6462 if (npages && old.base_gfn != mem->guest_phys_addr >> PAGE_SHIFT) {
6463 kvm_mmu_zap_all(kvm);
6464 kvm_reload_remote_mmus(kvm);
6465 }
0de10343 6466}
1d737c8a 6467
2df72e9b 6468void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f
MT		 6469{
6470 kvm_mmu_zap_all(kvm);
8986ecc0 6471 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6472}
6473
2df72e9b
MT		 6474void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
6475 struct kvm_memory_slot *slot)
6476{
6477 kvm_arch_flush_shadow_all(kvm);
6478}
6479
1d737c8a
ZX		 6480int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6481{
af585b92
GN		 6482 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6483 !vcpu->arch.apf.halted)
6484 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6485 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6486 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6487 (kvm_arch_interrupt_allowed(vcpu) &&
6488 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6489}
5736199a 6490
b6d33834 6491int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 6492{
b6d33834 6493 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 6494}
78646121
GN		 6495
6496int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6497{
6498 return kvm_x86_ops->interrupt_allowed(vcpu);
6499}
229456fc 6500
f92653ee
JK		 6501bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6502{
6503 unsigned long current_rip = kvm_rip_read(vcpu) +
6504 get_segment_base(vcpu, VCPU_SREG_CS);
6505
6506 return current_rip == linear_rip;
6507}
6508EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6509
94fe45da
JK		 6510unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6511{
6512 unsigned long rflags;
6513
6514 rflags = kvm_x86_ops->get_rflags(vcpu);
6515 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6516 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6517 return rflags;
6518}
6519EXPORT_SYMBOL_GPL(kvm_get_rflags);
6520
6521void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6522{
6523 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6524 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6525 rflags |= X86_EFLAGS_TF;
94fe45da 6526 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6527 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6528}
6529EXPORT_SYMBOL_GPL(kvm_set_rflags);
6530
56028d08
GN		 6531void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6532{
6533 int r;
6534
fb67e14f 6535 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6536 is_error_page(work->page))
56028d08
GN		 6537 return;
6538
6539 r = kvm_mmu_reload(vcpu);
6540 if (unlikely(r))
6541 return;
6542
fb67e14f
XG		 6543 if (!vcpu->arch.mmu.direct_map &&
6544 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6545 return;
6546
56028d08
GN		 6547 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6548}
6549
af585b92
GN		 6550static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6551{
6552 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6553}
6554
6555static inline u32 kvm_async_pf_next_probe(u32 key)
6556{
6557 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6558}
6559
6560static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6561{
6562 u32 key = kvm_async_pf_hash_fn(gfn);
6563
6564 while (vcpu->arch.apf.gfns[key] != ~0)
6565 key = kvm_async_pf_next_probe(key);
6566
6567 vcpu->arch.apf.gfns[key] = gfn;
6568}
6569
6570static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6571{
6572 int i;
6573 u32 key = kvm_async_pf_hash_fn(gfn);
6574
6575 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6576 (vcpu->arch.apf.gfns[key] != gfn &&
6577 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6578 key = kvm_async_pf_next_probe(key);
6579
6580 return key;
6581}
6582
6583bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6584{
6585 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6586}
6587
6588static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6589{
6590 u32 i, j, k;
6591
6592 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6593 while (true) {
6594 vcpu->arch.apf.gfns[i] = ~0;
6595 do {
6596 j = kvm_async_pf_next_probe(j);
6597 if (vcpu->arch.apf.gfns[j] == ~0)
6598 return;
6599 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6600 /*
6601 * k lies cyclically in ]i,j]
6602 * | i.k.j |
6603 * |....j i.k.| or |.k..j i...|
6604 */
6605 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6606 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6607 i = j;
6608 }
6609}
6610
7c90705b
GN		 6611static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6612{
6613
6614 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6615 sizeof(val));
6616}
6617
af585b92
GN		 6618void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6619 struct kvm_async_pf *work)
6620{
6389ee94
AK		 6621 struct x86_exception fault;
6622
7c90705b 6623 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6624 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6625
6626 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6627 (vcpu->arch.apf.send_user_only &&
6628 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6629 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6630 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6631 fault.vector = PF_VECTOR;
6632 fault.error_code_valid = true;
6633 fault.error_code = 0;
6634 fault.nested_page_fault = false;
6635 fault.address = work->arch.token;
6636 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6637 }
af585b92
GN		 6638}
6639
6640void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6641 struct kvm_async_pf *work)
6642{
6389ee94
AK		 6643 struct x86_exception fault;
6644
7c90705b
GN		 6645 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6646 if (is_error_page(work->page))
6647 work->arch.token = ~0; /* broadcast wakeup */
6648 else
6649 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6650
6651 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6652 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6653 fault.vector = PF_VECTOR;
6654 fault.error_code_valid = true;
6655 fault.error_code = 0;
6656 fault.nested_page_fault = false;
6657 fault.address = work->arch.token;
6658 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6659 }
e6d53e3b 6660 vcpu->arch.apf.halted = false;
a4fa1635 6661 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 6662}
6663
6664bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6665{
6666 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6667 return true;
6668 else
6669 return !kvm_event_needs_reinjection(vcpu) &&
6670 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6671}
6672
229456fc
MT		 6673EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6674EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6675EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6676EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6677EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6678EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6679EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6680EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6681EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6682EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6683EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6684EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux 6.x block layer and io_uring tree(s)