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KVM: x86: add SYNC_REGS_SIZE_BYTES #define.
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 105
893590c7 106struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 107EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 108
893590c7 109static bool __read_mostly ignore_msrs = 0;
476bc001 110module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 111
fab0aa3b
EM		 112static bool __read_mostly report_ignored_msrs = true;
113module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
114
9ed96e87
MT		 115unsigned int min_timer_period_us = 500;
116module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
117
630994b3
MT		 118static bool __read_mostly kvmclock_periodic_sync = true;
119module_param(kvmclock_periodic_sync, bool, S_IRUGO);
120
893590c7 121bool __read_mostly kvm_has_tsc_control;
92a1f12d 122EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 123u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 125u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
126EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
127u64 __read_mostly kvm_max_tsc_scaling_ratio;
128EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 129u64 __read_mostly kvm_default_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 131
cc578287 132/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 133static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 134module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
135
d0659d94 136/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 137unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 138module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
139
52004014
FW		 140static bool __read_mostly vector_hashing = true;
141module_param(vector_hashing, bool, S_IRUGO);
142
18863bdd
AK		 143#define KVM_NR_SHARED_MSRS 16
144
145struct kvm_shared_msrs_global {
146 int nr;
2bf78fa7 147 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 148};
149
150struct kvm_shared_msrs {
151 struct user_return_notifier urn;
152 bool registered;
2bf78fa7
SY		 153 struct kvm_shared_msr_values {
154 u64 host;
155 u64 curr;
156 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 157};
158
159static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 160static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 161
417bc304 162struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 163 { "pf_fixed", VCPU_STAT(pf_fixed) },
164 { "pf_guest", VCPU_STAT(pf_guest) },
165 { "tlb_flush", VCPU_STAT(tlb_flush) },
166 { "invlpg", VCPU_STAT(invlpg) },
167 { "exits", VCPU_STAT(exits) },
168 { "io_exits", VCPU_STAT(io_exits) },
169 { "mmio_exits", VCPU_STAT(mmio_exits) },
170 { "signal_exits", VCPU_STAT(signal_exits) },
171 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 172 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 173 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 174 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 175 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 176 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 177 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 178 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 179 { "request_irq", VCPU_STAT(request_irq_exits) },
180 { "irq_exits", VCPU_STAT(irq_exits) },
181 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 182 { "fpu_reload", VCPU_STAT(fpu_reload) },
183 { "insn_emulation", VCPU_STAT(insn_emulation) },
184 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 185 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 186 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 187 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 188 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
189 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
190 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
191 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
192 { "mmu_flooded", VM_STAT(mmu_flooded) },
193 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 194 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 195 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 196 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 197 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 198 { "max_mmu_page_hash_collisions",
199 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 200 { NULL }
201};
202
2acf923e
DC		 203u64 __read_mostly host_xcr0;
204
b6785def 205static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 206
af585b92
GN		 207static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
208{
209 int i;
210 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
211 vcpu->arch.apf.gfns[i] = ~0;
212}
213
18863bdd
AK		 214static void kvm_on_user_return(struct user_return_notifier *urn)
215{
216 unsigned slot;
18863bdd
AK		 217 struct kvm_shared_msrs *locals
218 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 219 struct kvm_shared_msr_values *values;
1650b4eb
IA		 220 unsigned long flags;
221
222 /*
223 * Disabling irqs at this point since the following code could be
224 * interrupted and executed through kvm_arch_hardware_disable()
225 */
226 local_irq_save(flags);
227 if (locals->registered) {
228 locals->registered = false;
229 user_return_notifier_unregister(urn);
230 }
231 local_irq_restore(flags);
18863bdd 232 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 233 values = &locals->values[slot];
234 if (values->host != values->curr) {
235 wrmsrl(shared_msrs_global.msrs[slot], values->host);
236 values->curr = values->host;
18863bdd
AK		 237 }
238 }
18863bdd
AK		 239}
240
2bf78fa7 241static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 242{
18863bdd 243 u64 value;
013f6a5d
MT		 244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 246
2bf78fa7
SY		 247 /* only read, and nobody should modify it at this time,
248 * so don't need lock */
249 if (slot >= shared_msrs_global.nr) {
250 printk(KERN_ERR "kvm: invalid MSR slot!");
251 return;
252 }
253 rdmsrl_safe(msr, &value);
254 smsr->values[slot].host = value;
255 smsr->values[slot].curr = value;
256}
257
258void kvm_define_shared_msr(unsigned slot, u32 msr)
259{
0123be42 260 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 261 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 262 if (slot >= shared_msrs_global.nr)
263 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 264}
265EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
266
267static void kvm_shared_msr_cpu_online(void)
268{
269 unsigned i;
18863bdd
AK		 270
271 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 272 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 273}
274
8b3c3104 275int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 276{
013f6a5d
MT		 277 unsigned int cpu = smp_processor_id();
278 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 279 int err;
18863bdd 280
2bf78fa7 281 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 282 return 0;
2bf78fa7 283 smsr->values[slot].curr = value;
8b3c3104
AH		 284 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
285 if (err)
286 return 1;
287
18863bdd
AK		 288 if (!smsr->registered) {
289 smsr->urn.on_user_return = kvm_on_user_return;
290 user_return_notifier_register(&smsr->urn);
291 smsr->registered = true;
292 }
8b3c3104 293 return 0;
18863bdd
AK		 294}
295EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
296
13a34e06 297static void drop_user_return_notifiers(void)
3548bab5 298{
013f6a5d
MT		 299 unsigned int cpu = smp_processor_id();
300 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 301
302 if (smsr->registered)
303 kvm_on_user_return(&smsr->urn);
304}
305
6866b83e
CO		 306u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
307{
8a5a87d9 308 return vcpu->arch.apic_base;
6866b83e
CO		 309}
310EXPORT_SYMBOL_GPL(kvm_get_apic_base);
311
58cb628d
JK		 312int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
313{
314 u64 old_state = vcpu->arch.apic_base &
315 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
316 u64 new_state = msr_info->data &
317 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 318 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
319 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 320
d3802286
JM		 321 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
322 return 1;
58cb628d 323 if (!msr_info->host_initiated &&
d3802286 324 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 325 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
326 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
327 old_state == 0)))
328 return 1;
329
330 kvm_lapic_set_base(vcpu, msr_info->data);
331 return 0;
6866b83e
CO		 332}
333EXPORT_SYMBOL_GPL(kvm_set_apic_base);
334
2605fc21 335asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 336{
337 /* Fault while not rebooting. We want the trace. */
338 BUG();
339}
340EXPORT_SYMBOL_GPL(kvm_spurious_fault);
341
3fd28fce
ED		 342#define EXCPT_BENIGN 0
343#define EXCPT_CONTRIBUTORY 1
344#define EXCPT_PF 2
345
346static int exception_class(int vector)
347{
348 switch (vector) {
349 case PF_VECTOR:
350 return EXCPT_PF;
351 case DE_VECTOR:
352 case TS_VECTOR:
353 case NP_VECTOR:
354 case SS_VECTOR:
355 case GP_VECTOR:
356 return EXCPT_CONTRIBUTORY;
357 default:
358 break;
359 }
360 return EXCPT_BENIGN;
361}
362
d6e8c854
NA		 363#define EXCPT_FAULT 0
364#define EXCPT_TRAP 1
365#define EXCPT_ABORT 2
366#define EXCPT_INTERRUPT 3
367
368static int exception_type(int vector)
369{
370 unsigned int mask;
371
372 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
373 return EXCPT_INTERRUPT;
374
375 mask = 1 << vector;
376
377 /* #DB is trap, as instruction watchpoints are handled elsewhere */
378 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
379 return EXCPT_TRAP;
380
381 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
382 return EXCPT_ABORT;
383
384 /* Reserved exceptions will result in fault */
385 return EXCPT_FAULT;
386}
387
3fd28fce 388static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 389 unsigned nr, bool has_error, u32 error_code,
390 bool reinject)
3fd28fce
ED		 391{
392 u32 prev_nr;
393 int class1, class2;
394
3842d135
AK		 395 kvm_make_request(KVM_REQ_EVENT, vcpu);
396
664f8e26 397 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 398 queue:
3ffb2468
NA		 399 if (has_error && !is_protmode(vcpu))
400 has_error = false;
664f8e26
WL		 401 if (reinject) {
402 /*
403 * On vmentry, vcpu->arch.exception.pending is only
404 * true if an event injection was blocked by
405 * nested_run_pending. In that case, however,
406 * vcpu_enter_guest requests an immediate exit,
407 * and the guest shouldn't proceed far enough to
408 * need reinjection.
409 */
410 WARN_ON_ONCE(vcpu->arch.exception.pending);
411 vcpu->arch.exception.injected = true;
412 } else {
413 vcpu->arch.exception.pending = true;
414 vcpu->arch.exception.injected = false;
415 }
3fd28fce
ED		 416 vcpu->arch.exception.has_error_code = has_error;
417 vcpu->arch.exception.nr = nr;
418 vcpu->arch.exception.error_code = error_code;
419 return;
420 }
421
422 /* to check exception */
423 prev_nr = vcpu->arch.exception.nr;
424 if (prev_nr == DF_VECTOR) {
425 /* triple fault -> shutdown */
a8eeb04a 426 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 427 return;
428 }
429 class1 = exception_class(prev_nr);
430 class2 = exception_class(nr);
431 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
432 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 433 /*
434 * Generate double fault per SDM Table 5-5. Set
435 * exception.pending = true so that the double fault
436 * can trigger a nested vmexit.
437 */
3fd28fce 438 vcpu->arch.exception.pending = true;
664f8e26 439 vcpu->arch.exception.injected = false;
3fd28fce
ED		 440 vcpu->arch.exception.has_error_code = true;
441 vcpu->arch.exception.nr = DF_VECTOR;
442 vcpu->arch.exception.error_code = 0;
443 } else
444 /* replace previous exception with a new one in a hope
445 that instruction re-execution will regenerate lost
446 exception */
447 goto queue;
448}
449
298101da
AK		 450void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
451{
ce7ddec4 452 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 453}
454EXPORT_SYMBOL_GPL(kvm_queue_exception);
455
ce7ddec4
JR		 456void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
457{
458 kvm_multiple_exception(vcpu, nr, false, 0, true);
459}
460EXPORT_SYMBOL_GPL(kvm_requeue_exception);
461
6affcbed 462int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 463{
db8fcefa
AP		 464 if (err)
465 kvm_inject_gp(vcpu, 0);
466 else
6affcbed
KH		 467 return kvm_skip_emulated_instruction(vcpu);
468
469 return 1;
db8fcefa
AP		 470}
471EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 472
6389ee94 473void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 474{
475 ++vcpu->stat.pf_guest;
adfe20fb
WL		 476 vcpu->arch.exception.nested_apf =
477 is_guest_mode(vcpu) && fault->async_page_fault;
478 if (vcpu->arch.exception.nested_apf)
479 vcpu->arch.apf.nested_apf_token = fault->address;
480 else
481 vcpu->arch.cr2 = fault->address;
6389ee94 482 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 483}
27d6c865 484EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 485
ef54bcfe 486static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 487{
6389ee94
AK		 488 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
489 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 490 else
6389ee94 491 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 492
493 return fault->nested_page_fault;
d4f8cf66
JR		 494}
495
3419ffc8
SY		 496void kvm_inject_nmi(struct kvm_vcpu *vcpu)
497{
7460fb4a
AK		 498 atomic_inc(&vcpu->arch.nmi_queued);
499 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 500}
501EXPORT_SYMBOL_GPL(kvm_inject_nmi);
502
298101da
AK		 503void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
504{
ce7ddec4 505 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 506}
507EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
508
ce7ddec4
JR		 509void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
510{
511 kvm_multiple_exception(vcpu, nr, true, error_code, true);
512}
513EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
514
0a79b009
AK		 515/*
516 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
517 * a #GP and return false.
518 */
519bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 520{
0a79b009
AK		 521 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
522 return true;
523 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
524 return false;
298101da 525}
0a79b009 526EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 527
16f8a6f9
NA		 528bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
529{
530 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
531 return true;
532
533 kvm_queue_exception(vcpu, UD_VECTOR);
534 return false;
535}
536EXPORT_SYMBOL_GPL(kvm_require_dr);
537
ec92fe44
JR		 538/*
539 * This function will be used to read from the physical memory of the currently
54bf36aa 540 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 541 * can read from guest physical or from the guest's guest physical memory.
542 */
543int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
544 gfn_t ngfn, void *data, int offset, int len,
545 u32 access)
546{
54987b7a 547 struct x86_exception exception;
ec92fe44
JR		 548 gfn_t real_gfn;
549 gpa_t ngpa;
550
551 ngpa = gfn_to_gpa(ngfn);
54987b7a 552 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 553 if (real_gfn == UNMAPPED_GVA)
554 return -EFAULT;
555
556 real_gfn = gpa_to_gfn(real_gfn);
557
54bf36aa 558 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 559}
560EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
561
69b0049a 562static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 563 void *data, int offset, int len, u32 access)
564{
565 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
566 data, offset, len, access);
567}
568
a03490ed
CO		 569/*
570 * Load the pae pdptrs. Return true is they are all valid.
571 */
ff03a073 572int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 573{
574 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
575 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
576 int i;
577 int ret;
ff03a073 578 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 579
ff03a073
JR		 580 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
581 offset * sizeof(u64), sizeof(pdpte),
582 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 583 if (ret < 0) {
584 ret = 0;
585 goto out;
586 }
587 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 588 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 589 (pdpte[i] &
590 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 591 ret = 0;
592 goto out;
593 }
594 }
595 ret = 1;
596
ff03a073 597 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 598 __set_bit(VCPU_EXREG_PDPTR,
599 (unsigned long *)&vcpu->arch.regs_avail);
600 __set_bit(VCPU_EXREG_PDPTR,
601 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 602out:
a03490ed
CO		 603
604 return ret;
605}
cc4b6871 606EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 607
9ed38ffa 608bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 609{
ff03a073 610 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 611 bool changed = true;
3d06b8bf
JR		 612 int offset;
613 gfn_t gfn;
d835dfec
AK		 614 int r;
615
616 if (is_long_mode(vcpu) || !is_pae(vcpu))
617 return false;
618
6de4f3ad
AK		 619 if (!test_bit(VCPU_EXREG_PDPTR,
620 (unsigned long *)&vcpu->arch.regs_avail))
621 return true;
622
a512177e
PB		 623 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
624 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 625 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
626 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 627 if (r < 0)
628 goto out;
ff03a073 629 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 630out:
d835dfec
AK		 631
632 return changed;
633}
9ed38ffa 634EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 635
49a9b07e 636int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 637{
aad82703 638 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 639 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 640
f9a48e6a
AK		 641 cr0 |= X86_CR0_ET;
642
ab344828 643#ifdef CONFIG_X86_64
0f12244f
GN		 644 if (cr0 & 0xffffffff00000000UL)
645 return 1;
ab344828
GN		 646#endif
647
648 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 649
0f12244f
GN		 650 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
651 return 1;
a03490ed 652
0f12244f
GN		 653 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
654 return 1;
a03490ed
CO		 655
656 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
657#ifdef CONFIG_X86_64
f6801dff 658 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 659 int cs_db, cs_l;
660
0f12244f
GN		 661 if (!is_pae(vcpu))
662 return 1;
a03490ed 663 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 664 if (cs_l)
665 return 1;
a03490ed
CO		 666 } else
667#endif
ff03a073 668 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 669 kvm_read_cr3(vcpu)))
0f12244f 670 return 1;
a03490ed
CO		 671 }
672
ad756a16
MJ		 673 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
674 return 1;
675
a03490ed 676 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 677
d170c419 678 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 679 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 680 kvm_async_pf_hash_reset(vcpu);
681 }
e5f3f027 682
aad82703
SY		 683 if ((cr0 ^ old_cr0) & update_bits)
684 kvm_mmu_reset_context(vcpu);
b18d5431 685
879ae188
LE		 686 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
687 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
688 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 689 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
690
0f12244f
GN		 691 return 0;
692}
2d3ad1f4 693EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 694
2d3ad1f4 695void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 696{
49a9b07e 697 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 698}
2d3ad1f4 699EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 700
42bdf991
MT		 701static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
702{
703 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
704 !vcpu->guest_xcr0_loaded) {
705 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 706 if (vcpu->arch.xcr0 != host_xcr0)
707 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 708 vcpu->guest_xcr0_loaded = 1;
709 }
710}
711
712static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
713{
714 if (vcpu->guest_xcr0_loaded) {
715 if (vcpu->arch.xcr0 != host_xcr0)
716 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
717 vcpu->guest_xcr0_loaded = 0;
718 }
719}
720
69b0049a 721static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 722{
56c103ec
LJ		 723 u64 xcr0 = xcr;
724 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 725 u64 valid_bits;
2acf923e
DC		 726
727 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
728 if (index != XCR_XFEATURE_ENABLED_MASK)
729 return 1;
d91cab78 730 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 731 return 1;
d91cab78 732 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 733 return 1;
46c34cb0
PB		 734
735 /*
736 * Do not allow the guest to set bits that we do not support
737 * saving. However, xcr0 bit 0 is always set, even if the
738 * emulated CPU does not support XSAVE (see fx_init).
739 */
d91cab78 740 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 741 if (xcr0 & ~valid_bits)
2acf923e 742 return 1;
46c34cb0 743
d91cab78
DH		 744 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
745 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 746 return 1;
747
d91cab78
DH		 748 if (xcr0 & XFEATURE_MASK_AVX512) {
749 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 750 return 1;
d91cab78 751 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 752 return 1;
753 }
2acf923e 754 vcpu->arch.xcr0 = xcr0;
56c103ec 755
d91cab78 756 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 757 kvm_update_cpuid(vcpu);
2acf923e
DC		 758 return 0;
759}
760
761int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
762{
764bcbc5
Z		 763 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
764 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 765 kvm_inject_gp(vcpu, 0);
766 return 1;
767 }
768 return 0;
769}
770EXPORT_SYMBOL_GPL(kvm_set_xcr);
771
a83b29c6 772int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 773{
fc78f519 774 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 775 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 776 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 777
0f12244f
GN		 778 if (cr4 & CR4_RESERVED_BITS)
779 return 1;
a03490ed 780
d6321d49 781 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 782 return 1;
783
d6321d49 784 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 785 return 1;
786
d6321d49 787 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 788 return 1;
789
d6321d49 790 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 791 return 1;
792
d6321d49 793 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 794 return 1;
795
fd8cb433 796 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 797 return 1;
798
ae3e61e1
PB		 799 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
800 return 1;
801
a03490ed 802 if (is_long_mode(vcpu)) {
0f12244f
GN		 803 if (!(cr4 & X86_CR4_PAE))
804 return 1;
a2edf57f
AK		 805 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
806 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 807 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
808 kvm_read_cr3(vcpu)))
0f12244f
GN		 809 return 1;
810
ad756a16 811 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 812 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 813 return 1;
814
815 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
816 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
817 return 1;
818 }
819
5e1746d6 820 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 821 return 1;
a03490ed 822
ad756a16
MJ		 823 if (((cr4 ^ old_cr4) & pdptr_bits) ||
824 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 825 kvm_mmu_reset_context(vcpu);
0f12244f 826
b9baba86 827 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 828 kvm_update_cpuid(vcpu);
2acf923e 829
0f12244f
GN		 830 return 0;
831}
2d3ad1f4 832EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 833
2390218b 834int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 835{
ac146235 836#ifdef CONFIG_X86_64
9d88fca7 837 cr3 &= ~CR3_PCID_INVD;
ac146235 838#endif
9d88fca7 839
9f8fe504 840 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 841 kvm_mmu_sync_roots(vcpu);
77c3913b 842 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 843 return 0;
d835dfec
AK		 844 }
845
d1cd3ce9
YZ		 846 if (is_long_mode(vcpu) &&
847 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
848 return 1;
849 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 850 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 851 return 1;
a03490ed 852
0f12244f 853 vcpu->arch.cr3 = cr3;
aff48baa 854 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 855 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 856 return 0;
857}
2d3ad1f4 858EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 859
eea1cff9 860int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 861{
0f12244f
GN		 862 if (cr8 & CR8_RESERVED_BITS)
863 return 1;
35754c98 864 if (lapic_in_kernel(vcpu))
a03490ed
CO		 865 kvm_lapic_set_tpr(vcpu, cr8);
866 else
ad312c7c 867 vcpu->arch.cr8 = cr8;
0f12244f
GN		 868 return 0;
869}
2d3ad1f4 870EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 871
2d3ad1f4 872unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 873{
35754c98 874 if (lapic_in_kernel(vcpu))
a03490ed
CO		 875 return kvm_lapic_get_cr8(vcpu);
876 else
ad312c7c 877 return vcpu->arch.cr8;
a03490ed 878}
2d3ad1f4 879EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 880
ae561ede
NA		 881static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
882{
883 int i;
884
885 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
886 for (i = 0; i < KVM_NR_DB_REGS; i++)
887 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
888 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
889 }
890}
891
73aaf249
JK		 892static void kvm_update_dr6(struct kvm_vcpu *vcpu)
893{
894 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
895 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
896}
897
c8639010
JK		 898static void kvm_update_dr7(struct kvm_vcpu *vcpu)
899{
900 unsigned long dr7;
901
902 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
903 dr7 = vcpu->arch.guest_debug_dr7;
904 else
905 dr7 = vcpu->arch.dr7;
906 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 907 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
908 if (dr7 & DR7_BP_EN_MASK)
909 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 910}
911
6f43ed01
NA		 912static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
913{
914 u64 fixed = DR6_FIXED_1;
915
d6321d49 916 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 917 fixed |= DR6_RTM;
918 return fixed;
919}
920
338dbc97 921static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 922{
923 switch (dr) {
924 case 0 ... 3:
925 vcpu->arch.db[dr] = val;
926 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
927 vcpu->arch.eff_db[dr] = val;
928 break;
929 case 4:
020df079
GN		 930 /* fall through */
931 case 6:
338dbc97
GN		 932 if (val & 0xffffffff00000000ULL)
933 return -1; /* #GP */
6f43ed01 934 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 935 kvm_update_dr6(vcpu);
020df079
GN		 936 break;
937 case 5:
020df079
GN		 938 /* fall through */
939 default: /* 7 */
338dbc97
GN		 940 if (val & 0xffffffff00000000ULL)
941 return -1; /* #GP */
020df079 942 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 943 kvm_update_dr7(vcpu);
020df079
GN		 944 break;
945 }
946
947 return 0;
948}
338dbc97
GN		 949
950int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
951{
16f8a6f9 952 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 953 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 954 return 1;
955 }
956 return 0;
338dbc97 957}
020df079
GN		 958EXPORT_SYMBOL_GPL(kvm_set_dr);
959
16f8a6f9 960int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 961{
962 switch (dr) {
963 case 0 ... 3:
964 *val = vcpu->arch.db[dr];
965 break;
966 case 4:
020df079
GN		 967 /* fall through */
968 case 6:
73aaf249
JK		 969 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
970 *val = vcpu->arch.dr6;
971 else
972 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 973 break;
974 case 5:
020df079
GN		 975 /* fall through */
976 default: /* 7 */
977 *val = vcpu->arch.dr7;
978 break;
979 }
338dbc97
GN		 980 return 0;
981}
020df079
GN		 982EXPORT_SYMBOL_GPL(kvm_get_dr);
983
022cd0e8
AK		 984bool kvm_rdpmc(struct kvm_vcpu *vcpu)
985{
986 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
987 u64 data;
988 int err;
989
c6702c9d 990 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 991 if (err)
992 return err;
993 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
994 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
995 return err;
996}
997EXPORT_SYMBOL_GPL(kvm_rdpmc);
998
043405e1
CO		 999/*
1000 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1001 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1002 *
1003 * This list is modified at module load time to reflect the
e3267cbb 1004 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1005 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1006 * may depend on host virtualization features rather than host cpu features.
043405e1 1007 */
e3267cbb 1008
043405e1
CO		 1009static u32 msrs_to_save[] = {
1010 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1011 MSR_STAR,
043405e1
CO		 1012#ifdef CONFIG_X86_64
1013 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1014#endif
b3897a49 1015 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1016 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1017 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1018};
1019
1020static unsigned num_msrs_to_save;
1021
62ef68bb
PB		 1022static u32 emulated_msrs[] = {
1023 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1024 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1025 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1026 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1027 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1028 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1029 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1030 HV_X64_MSR_RESET,
11c4b1ca 1031 HV_X64_MSR_VP_INDEX,
9eec50b8 1032 HV_X64_MSR_VP_RUNTIME,
5c919412 1033 HV_X64_MSR_SCONTROL,
1f4b34f8 1034 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1035 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1036 MSR_KVM_PV_EOI_EN,
1037
ba904635 1038 MSR_IA32_TSC_ADJUST,
a3e06bbe 1039 MSR_IA32_TSCDEADLINE,
043405e1 1040 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1041 MSR_IA32_MCG_STATUS,
1042 MSR_IA32_MCG_CTL,
c45dcc71 1043 MSR_IA32_MCG_EXT_CTL,
64d60670 1044 MSR_IA32_SMBASE,
52797bf9 1045 MSR_SMI_COUNT,
db2336a8
KH		 1046 MSR_PLATFORM_INFO,
1047 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1048};
1049
62ef68bb
PB		 1050static unsigned num_emulated_msrs;
1051
801e459a
TL		 1052/*
1053 * List of msr numbers which are used to expose MSR-based features that
1054 * can be used by a hypervisor to validate requested CPU features.
1055 */
1056static u32 msr_based_features[] = {
d1d93fa9 1057 MSR_F10H_DECFG,
518e7b94 1058 MSR_IA32_UCODE_REV,
801e459a
TL		 1059};
1060
1061static unsigned int num_msr_based_features;
1062
66421c1e
WL		 1063static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1064{
1065 switch (msr->index) {
518e7b94
WL		 1066 case MSR_IA32_UCODE_REV:
1067 rdmsrl(msr->index, msr->data);
1068 break;
66421c1e
WL		 1069 default:
1070 if (kvm_x86_ops->get_msr_feature(msr))
1071 return 1;
1072 }
1073 return 0;
1074}
1075
801e459a
TL		 1076static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1077{
1078 struct kvm_msr_entry msr;
66421c1e 1079 int r;
801e459a
TL		 1080
1081 msr.index = index;
66421c1e
WL		 1082 r = kvm_get_msr_feature(&msr);
1083 if (r)
1084 return r;
801e459a
TL		 1085
1086 *data = msr.data;
1087
1088 return 0;
1089}
1090
384bb783 1091bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1092{
b69e8cae 1093 if (efer & efer_reserved_bits)
384bb783 1094 return false;
15c4a640 1095
1b4d56b8 1096 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1097 return false;
1b2fd70c 1098
1b4d56b8 1099 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1100 return false;
d8017474 1101
384bb783
JK		 1102 return true;
1103}
1104EXPORT_SYMBOL_GPL(kvm_valid_efer);
1105
1106static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1107{
1108 u64 old_efer = vcpu->arch.efer;
1109
1110 if (!kvm_valid_efer(vcpu, efer))
1111 return 1;
1112
1113 if (is_paging(vcpu)
1114 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1115 return 1;
1116
15c4a640 1117 efer &= ~EFER_LMA;
f6801dff 1118 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1119
a3d204e2
SY		 1120 kvm_x86_ops->set_efer(vcpu, efer);
1121
aad82703
SY		 1122 /* Update reserved bits */
1123 if ((efer ^ old_efer) & EFER_NX)
1124 kvm_mmu_reset_context(vcpu);
1125
b69e8cae 1126 return 0;
15c4a640
CO		 1127}
1128
f2b4b7dd
JR		 1129void kvm_enable_efer_bits(u64 mask)
1130{
1131 efer_reserved_bits &= ~mask;
1132}
1133EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1134
15c4a640
CO		 1135/*
1136 * Writes msr value into into the appropriate "register".
1137 * Returns 0 on success, non-0 otherwise.
1138 * Assumes vcpu_load() was already called.
1139 */
8fe8ab46 1140int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1141{
854e8bb1
NA		 1142 switch (msr->index) {
1143 case MSR_FS_BASE:
1144 case MSR_GS_BASE:
1145 case MSR_KERNEL_GS_BASE:
1146 case MSR_CSTAR:
1147 case MSR_LSTAR:
fd8cb433 1148 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1149 return 1;
1150 break;
1151 case MSR_IA32_SYSENTER_EIP:
1152 case MSR_IA32_SYSENTER_ESP:
1153 /*
1154 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1155 * non-canonical address is written on Intel but not on
1156 * AMD (which ignores the top 32-bits, because it does
1157 * not implement 64-bit SYSENTER).
1158 *
1159 * 64-bit code should hence be able to write a non-canonical
1160 * value on AMD. Making the address canonical ensures that
1161 * vmentry does not fail on Intel after writing a non-canonical
1162 * value, and that something deterministic happens if the guest
1163 * invokes 64-bit SYSENTER.
1164 */
fd8cb433 1165 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1166 }
8fe8ab46 1167 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1168}
854e8bb1 1169EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1170
313a3dc7
CO		 1171/*
1172 * Adapt set_msr() to msr_io()'s calling convention
1173 */
609e36d3
PB		 1174static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1175{
1176 struct msr_data msr;
1177 int r;
1178
1179 msr.index = index;
1180 msr.host_initiated = true;
1181 r = kvm_get_msr(vcpu, &msr);
1182 if (r)
1183 return r;
1184
1185 *data = msr.data;
1186 return 0;
1187}
1188
313a3dc7
CO		 1189static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1190{
8fe8ab46
WA		 1191 struct msr_data msr;
1192
1193 msr.data = *data;
1194 msr.index = index;
1195 msr.host_initiated = true;
1196 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1197}
1198
16e8d74d
MT		 1199#ifdef CONFIG_X86_64
1200struct pvclock_gtod_data {
1201 seqcount_t seq;
1202
1203 struct { /* extract of a clocksource struct */
1204 int vclock_mode;
a5a1d1c2
TG		 1205 u64 cycle_last;
1206 u64 mask;
16e8d74d
MT		 1207 u32 mult;
1208 u32 shift;
1209 } clock;
1210
cbcf2dd3
TG		 1211 u64 boot_ns;
1212 u64 nsec_base;
55dd00a7 1213 u64 wall_time_sec;
16e8d74d
MT		 1214};
1215
1216static struct pvclock_gtod_data pvclock_gtod_data;
1217
1218static void update_pvclock_gtod(struct timekeeper *tk)
1219{
1220 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1221 u64 boot_ns;
1222
876e7881 1223 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1224
1225 write_seqcount_begin(&vdata->seq);
1226
1227 /* copy pvclock gtod data */
876e7881
PZ		 1228 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1229 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1230 vdata->clock.mask = tk->tkr_mono.mask;
1231 vdata->clock.mult = tk->tkr_mono.mult;
1232 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1233
cbcf2dd3 1234 vdata->boot_ns = boot_ns;
876e7881 1235 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1236
55dd00a7
MT		 1237 vdata->wall_time_sec = tk->xtime_sec;
1238
16e8d74d
MT		 1239 write_seqcount_end(&vdata->seq);
1240}
1241#endif
1242
bab5bb39
NK		 1243void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1244{
1245 /*
1246 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1247 * vcpu_enter_guest. This function is only called from
1248 * the physical CPU that is running vcpu.
1249 */
1250 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1251}
16e8d74d 1252
18068523
GOC		 1253static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1254{
9ed3c444
AK		 1255 int version;
1256 int r;
50d0a0f9 1257 struct pvclock_wall_clock wc;
87aeb54f 1258 struct timespec64 boot;
18068523
GOC		 1259
1260 if (!wall_clock)
1261 return;
1262
9ed3c444
AK		 1263 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1264 if (r)
1265 return;
1266
1267 if (version & 1)
1268 ++version; /* first time write, random junk */
1269
1270 ++version;
18068523 1271
1dab1345
NK		 1272 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1273 return;
18068523 1274
50d0a0f9
GH		 1275 /*
1276 * The guest calculates current wall clock time by adding
34c238a1 1277 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1278 * wall clock specified here. guest system time equals host
1279 * system time for us, thus we must fill in host boot time here.
1280 */
87aeb54f 1281 getboottime64(&boot);
50d0a0f9 1282
4b648665 1283 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1284 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1285 boot = timespec64_sub(boot, ts);
4b648665 1286 }
87aeb54f 1287 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1288 wc.nsec = boot.tv_nsec;
1289 wc.version = version;
18068523
GOC		 1290
1291 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1292
1293 version++;
1294 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1295}
1296
50d0a0f9
GH		 1297static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1298{
b51012de
PB		 1299 do_shl32_div32(dividend, divisor);
1300 return dividend;
50d0a0f9
GH		 1301}
1302
3ae13faa 1303static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1304 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1305{
5f4e3f88 1306 uint64_t scaled64;
50d0a0f9
GH		 1307 int32_t shift = 0;
1308 uint64_t tps64;
1309 uint32_t tps32;
1310
3ae13faa
PB		 1311 tps64 = base_hz;
1312 scaled64 = scaled_hz;
50933623 1313 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1314 tps64 >>= 1;
1315 shift--;
1316 }
1317
1318 tps32 = (uint32_t)tps64;
50933623
JK		 1319 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1320 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1321 scaled64 >>= 1;
1322 else
1323 tps32 <<= 1;
50d0a0f9
GH		 1324 shift++;
1325 }
1326
5f4e3f88
ZA		 1327 *pshift = shift;
1328 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1329
3ae13faa
PB		 1330 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1331 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1332}
1333
d828199e 1334#ifdef CONFIG_X86_64
16e8d74d 1335static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1336#endif
16e8d74d 1337
c8076604 1338static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1339static unsigned long max_tsc_khz;
c8076604 1340
cc578287 1341static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1342{
cc578287
ZA		 1343 u64 v = (u64)khz * (1000000 + ppm);
1344 do_div(v, 1000000);
1345 return v;
1e993611
JR		 1346}
1347
381d585c
HZ		 1348static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1349{
1350 u64 ratio;
1351
1352 /* Guest TSC same frequency as host TSC? */
1353 if (!scale) {
1354 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1355 return 0;
1356 }
1357
1358 /* TSC scaling supported? */
1359 if (!kvm_has_tsc_control) {
1360 if (user_tsc_khz > tsc_khz) {
1361 vcpu->arch.tsc_catchup = 1;
1362 vcpu->arch.tsc_always_catchup = 1;
1363 return 0;
1364 } else {
1365 WARN(1, "user requested TSC rate below hardware speed\n");
1366 return -1;
1367 }
1368 }
1369
1370 /* TSC scaling required - calculate ratio */
1371 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1372 user_tsc_khz, tsc_khz);
1373
1374 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1375 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1376 user_tsc_khz);
1377 return -1;
1378 }
1379
1380 vcpu->arch.tsc_scaling_ratio = ratio;
1381 return 0;
1382}
1383
4941b8cb 1384static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1385{
cc578287
ZA		 1386 u32 thresh_lo, thresh_hi;
1387 int use_scaling = 0;
217fc9cf 1388
03ba32ca 1389 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1390 if (user_tsc_khz == 0) {
ad721883
HZ		 1391 /* set tsc_scaling_ratio to a safe value */
1392 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1393 return -1;
ad721883 1394 }
03ba32ca 1395
c285545f 1396 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1397 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1398 &vcpu->arch.virtual_tsc_shift,
1399 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1400 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1401
1402 /*
1403 * Compute the variation in TSC rate which is acceptable
1404 * within the range of tolerance and decide if the
1405 * rate being applied is within that bounds of the hardware
1406 * rate. If so, no scaling or compensation need be done.
1407 */
1408 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1409 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1410 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1411 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1412 use_scaling = 1;
1413 }
4941b8cb 1414 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1415}
1416
1417static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1418{
e26101b1 1419 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1420 vcpu->arch.virtual_tsc_mult,
1421 vcpu->arch.virtual_tsc_shift);
e26101b1 1422 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1423 return tsc;
1424}
1425
b0c39dc6
VK		 1426static inline int gtod_is_based_on_tsc(int mode)
1427{
1428 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1429}
1430
69b0049a 1431static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1432{
1433#ifdef CONFIG_X86_64
1434 bool vcpus_matched;
b48aa97e
MT		 1435 struct kvm_arch *ka = &vcpu->kvm->arch;
1436 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1437
1438 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1439 atomic_read(&vcpu->kvm->online_vcpus));
1440
7f187922
MT		 1441 /*
1442 * Once the masterclock is enabled, always perform request in
1443 * order to update it.
1444 *
1445 * In order to enable masterclock, the host clocksource must be TSC
1446 * and the vcpus need to have matched TSCs. When that happens,
1447 * perform request to enable masterclock.
1448 */
1449 if (ka->use_master_clock ||
b0c39dc6 1450 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1451 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1452
1453 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1454 atomic_read(&vcpu->kvm->online_vcpus),
1455 ka->use_master_clock, gtod->clock.vclock_mode);
1456#endif
1457}
1458
ba904635
WA		 1459static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1460{
3e3f5026 1461 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1462 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1463}
1464
35181e86
HZ		 1465/*
1466 * Multiply tsc by a fixed point number represented by ratio.
1467 *
1468 * The most significant 64-N bits (mult) of ratio represent the
1469 * integral part of the fixed point number; the remaining N bits
1470 * (frac) represent the fractional part, ie. ratio represents a fixed
1471 * point number (mult + frac * 2^(-N)).
1472 *
1473 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1474 */
1475static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1476{
1477 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1478}
1479
1480u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1481{
1482 u64 _tsc = tsc;
1483 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1484
1485 if (ratio != kvm_default_tsc_scaling_ratio)
1486 _tsc = __scale_tsc(ratio, tsc);
1487
1488 return _tsc;
1489}
1490EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1491
07c1419a
HZ		 1492static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1493{
1494 u64 tsc;
1495
1496 tsc = kvm_scale_tsc(vcpu, rdtsc());
1497
1498 return target_tsc - tsc;
1499}
1500
4ba76538
HZ		 1501u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1502{
ea26e4ec 1503 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1504}
1505EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1506
a545ab6a
LC		 1507static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1508{
1509 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1510 vcpu->arch.tsc_offset = offset;
1511}
1512
b0c39dc6
VK		 1513static inline bool kvm_check_tsc_unstable(void)
1514{
1515#ifdef CONFIG_X86_64
1516 /*
1517 * TSC is marked unstable when we're running on Hyper-V,
1518 * 'TSC page' clocksource is good.
1519 */
1520 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1521 return false;
1522#endif
1523 return check_tsc_unstable();
1524}
1525
8fe8ab46 1526void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1527{
1528 struct kvm *kvm = vcpu->kvm;
f38e098f 1529 u64 offset, ns, elapsed;
99e3e30a 1530 unsigned long flags;
b48aa97e 1531 bool matched;
0d3da0d2 1532 bool already_matched;
8fe8ab46 1533 u64 data = msr->data;
c5e8ec8e 1534 bool synchronizing = false;
99e3e30a 1535
038f8c11 1536 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1537 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1538 ns = ktime_get_boot_ns();
f38e098f 1539 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1540
03ba32ca 1541 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1542 if (data == 0 && msr->host_initiated) {
1543 /*
1544 * detection of vcpu initialization -- need to sync
1545 * with other vCPUs. This particularly helps to keep
1546 * kvm_clock stable after CPU hotplug
1547 */
1548 synchronizing = true;
1549 } else {
1550 u64 tsc_exp = kvm->arch.last_tsc_write +
1551 nsec_to_cycles(vcpu, elapsed);
1552 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1553 /*
1554 * Special case: TSC write with a small delta (1 second)
1555 * of virtual cycle time against real time is
1556 * interpreted as an attempt to synchronize the CPU.
1557 */
1558 synchronizing = data < tsc_exp + tsc_hz &&
1559 data + tsc_hz > tsc_exp;
1560 }
c5e8ec8e 1561 }
f38e098f
ZA		 1562
1563 /*
5d3cb0f6
ZA		 1564 * For a reliable TSC, we can match TSC offsets, and for an unstable
1565 * TSC, we add elapsed time in this computation. We could let the
1566 * compensation code attempt to catch up if we fall behind, but
1567 * it's better to try to match offsets from the beginning.
1568 */
c5e8ec8e 1569 if (synchronizing &&
5d3cb0f6 1570 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1571 if (!kvm_check_tsc_unstable()) {
e26101b1 1572 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1573 pr_debug("kvm: matched tsc offset for %llu\n", data);
1574 } else {
857e4099 1575 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1576 data += delta;
07c1419a 1577 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1578 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1579 }
b48aa97e 1580 matched = true;
0d3da0d2 1581 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1582 } else {
1583 /*
1584 * We split periods of matched TSC writes into generations.
1585 * For each generation, we track the original measured
1586 * nanosecond time, offset, and write, so if TSCs are in
1587 * sync, we can match exact offset, and if not, we can match
4a969980 1588 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1589 *
1590 * These values are tracked in kvm->arch.cur_xxx variables.
1591 */
1592 kvm->arch.cur_tsc_generation++;
1593 kvm->arch.cur_tsc_nsec = ns;
1594 kvm->arch.cur_tsc_write = data;
1595 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1596 matched = false;
0d3da0d2 1597 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1598 kvm->arch.cur_tsc_generation, data);
f38e098f 1599 }
e26101b1
ZA		 1600
1601 /*
1602 * We also track th most recent recorded KHZ, write and time to
1603 * allow the matching interval to be extended at each write.
1604 */
f38e098f
ZA		 1605 kvm->arch.last_tsc_nsec = ns;
1606 kvm->arch.last_tsc_write = data;
5d3cb0f6 1607 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1608
b183aa58 1609 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1610
1611 /* Keep track of which generation this VCPU has synchronized to */
1612 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1613 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1614 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1615
d6321d49 1616 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1617 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1618
a545ab6a 1619 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1620 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1621
1622 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1623 if (!matched) {
b48aa97e 1624 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1625 } else if (!already_matched) {
1626 kvm->arch.nr_vcpus_matched_tsc++;
1627 }
b48aa97e
MT		 1628
1629 kvm_track_tsc_matching(vcpu);
1630 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1631}
e26101b1 1632
99e3e30a
ZA		 1633EXPORT_SYMBOL_GPL(kvm_write_tsc);
1634
58ea6767
HZ		 1635static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1636 s64 adjustment)
1637{
ea26e4ec 1638 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1639}
1640
1641static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1642{
1643 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1644 WARN_ON(adjustment < 0);
1645 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1646 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1647}
1648
d828199e
MT		 1649#ifdef CONFIG_X86_64
1650
a5a1d1c2 1651static u64 read_tsc(void)
d828199e 1652{
a5a1d1c2 1653 u64 ret = (u64)rdtsc_ordered();
03b9730b 1654 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1655
1656 if (likely(ret >= last))
1657 return ret;
1658
1659 /*
1660 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1661 * predictable (it's just a function of time and the likely is
d828199e
MT		 1662 * very likely) and there's a data dependence, so force GCC
1663 * to generate a branch instead. I don't barrier() because
1664 * we don't actually need a barrier, and if this function
1665 * ever gets inlined it will generate worse code.
1666 */
1667 asm volatile ("");
1668 return last;
1669}
1670
b0c39dc6 1671static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1672{
1673 long v;
1674 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1675 u64 tsc_pg_val;
1676
1677 switch (gtod->clock.vclock_mode) {
1678 case VCLOCK_HVCLOCK:
1679 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1680 tsc_timestamp);
1681 if (tsc_pg_val != U64_MAX) {
1682 /* TSC page valid */
1683 *mode = VCLOCK_HVCLOCK;
1684 v = (tsc_pg_val - gtod->clock.cycle_last) &
1685 gtod->clock.mask;
1686 } else {
1687 /* TSC page invalid */
1688 *mode = VCLOCK_NONE;
1689 }
1690 break;
1691 case VCLOCK_TSC:
1692 *mode = VCLOCK_TSC;
1693 *tsc_timestamp = read_tsc();
1694 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1695 gtod->clock.mask;
1696 break;
1697 default:
1698 *mode = VCLOCK_NONE;
1699 }
d828199e 1700
b0c39dc6
VK		 1701 if (*mode == VCLOCK_NONE)
1702 *tsc_timestamp = v = 0;
d828199e 1703
d828199e
MT		 1704 return v * gtod->clock.mult;
1705}
1706
b0c39dc6 1707static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1708{
cbcf2dd3 1709 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1710 unsigned long seq;
d828199e 1711 int mode;
cbcf2dd3 1712 u64 ns;
d828199e 1713
d828199e
MT		 1714 do {
1715 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1716 ns = gtod->nsec_base;
b0c39dc6 1717 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1718 ns >>= gtod->clock.shift;
cbcf2dd3 1719 ns += gtod->boot_ns;
d828199e 1720 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1721 *t = ns;
d828199e
MT		 1722
1723 return mode;
1724}
1725
b0c39dc6 1726static int do_realtime(struct timespec *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1727{
1728 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1729 unsigned long seq;
1730 int mode;
1731 u64 ns;
1732
1733 do {
1734 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1735 ts->tv_sec = gtod->wall_time_sec;
1736 ns = gtod->nsec_base;
b0c39dc6 1737 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1738 ns >>= gtod->clock.shift;
1739 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1740
1741 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1742 ts->tv_nsec = ns;
1743
1744 return mode;
1745}
1746
b0c39dc6
VK		 1747/* returns true if host is using TSC based clocksource */
1748static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1749{
d828199e 1750 /* checked again under seqlock below */
b0c39dc6 1751 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1752 return false;
1753
b0c39dc6
VK		 1754 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1755 tsc_timestamp));
d828199e 1756}
55dd00a7 1757
b0c39dc6 1758/* returns true if host is using TSC based clocksource */
55dd00a7 1759static bool kvm_get_walltime_and_clockread(struct timespec *ts,
b0c39dc6 1760 u64 *tsc_timestamp)
55dd00a7
MT		 1761{
1762 /* checked again under seqlock below */
b0c39dc6 1763 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1764 return false;
1765
b0c39dc6 1766 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1767}
d828199e
MT		 1768#endif
1769
1770/*
1771 *
b48aa97e
MT		 1772 * Assuming a stable TSC across physical CPUS, and a stable TSC
1773 * across virtual CPUs, the following condition is possible.
1774 * Each numbered line represents an event visible to both
d828199e
MT		 1775 * CPUs at the next numbered event.
1776 *
1777 * "timespecX" represents host monotonic time. "tscX" represents
1778 * RDTSC value.
1779 *
1780 * VCPU0 on CPU0 | VCPU1 on CPU1
1781 *
1782 * 1. read timespec0,tsc0
1783 * 2. | timespec1 = timespec0 + N
1784 * | tsc1 = tsc0 + M
1785 * 3. transition to guest | transition to guest
1786 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1787 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1788 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1789 *
1790 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1791 *
1792 * - ret0 < ret1
1793 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1794 * ...
1795 * - 0 < N - M => M < N
1796 *
1797 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1798 * always the case (the difference between two distinct xtime instances
1799 * might be smaller then the difference between corresponding TSC reads,
1800 * when updating guest vcpus pvclock areas).
1801 *
1802 * To avoid that problem, do not allow visibility of distinct
1803 * system_timestamp/tsc_timestamp values simultaneously: use a master
1804 * copy of host monotonic time values. Update that master copy
1805 * in lockstep.
1806 *
b48aa97e 1807 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1808 *
1809 */
1810
1811static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1812{
1813#ifdef CONFIG_X86_64
1814 struct kvm_arch *ka = &kvm->arch;
1815 int vclock_mode;
b48aa97e
MT		 1816 bool host_tsc_clocksource, vcpus_matched;
1817
1818 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1819 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1820
1821 /*
1822 * If the host uses TSC clock, then passthrough TSC as stable
1823 * to the guest.
1824 */
b48aa97e 1825 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1826 &ka->master_kernel_ns,
1827 &ka->master_cycle_now);
1828
16a96021 1829 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1830 && !ka->backwards_tsc_observed
54750f2c 1831 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1832
d828199e
MT		 1833 if (ka->use_master_clock)
1834 atomic_set(&kvm_guest_has_master_clock, 1);
1835
1836 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1837 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1838 vcpus_matched);
d828199e
MT		 1839#endif
1840}
1841
2860c4b1
PB		 1842void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1843{
1844 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1845}
1846
2e762ff7
MT		 1847static void kvm_gen_update_masterclock(struct kvm *kvm)
1848{
1849#ifdef CONFIG_X86_64
1850 int i;
1851 struct kvm_vcpu *vcpu;
1852 struct kvm_arch *ka = &kvm->arch;
1853
1854 spin_lock(&ka->pvclock_gtod_sync_lock);
1855 kvm_make_mclock_inprogress_request(kvm);
1856 /* no guest entries from this point */
1857 pvclock_update_vm_gtod_copy(kvm);
1858
1859 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1860 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1861
1862 /* guest entries allowed */
1863 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1864 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1865
1866 spin_unlock(&ka->pvclock_gtod_sync_lock);
1867#endif
1868}
1869
e891a32e 1870u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1871{
108b249c 1872 struct kvm_arch *ka = &kvm->arch;
8b953440 1873 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1874 u64 ret;
108b249c 1875
8b953440
PB		 1876 spin_lock(&ka->pvclock_gtod_sync_lock);
1877 if (!ka->use_master_clock) {
1878 spin_unlock(&ka->pvclock_gtod_sync_lock);
1879 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1880 }
1881
8b953440
PB		 1882 hv_clock.tsc_timestamp = ka->master_cycle_now;
1883 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1884 spin_unlock(&ka->pvclock_gtod_sync_lock);
1885
e2c2206a
WL		 1886 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1887 get_cpu();
1888
e70b57a6
WL		 1889 if (__this_cpu_read(cpu_tsc_khz)) {
1890 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1891 &hv_clock.tsc_shift,
1892 &hv_clock.tsc_to_system_mul);
1893 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1894 } else
1895 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1896
1897 put_cpu();
1898
1899 return ret;
108b249c
PB		 1900}
1901
0d6dd2ff
PB		 1902static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1903{
1904 struct kvm_vcpu_arch *vcpu = &v->arch;
1905 struct pvclock_vcpu_time_info guest_hv_clock;
1906
4e335d9e 1907 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1908 &guest_hv_clock, sizeof(guest_hv_clock))))
1909 return;
1910
1911 /* This VCPU is paused, but it's legal for a guest to read another
1912 * VCPU's kvmclock, so we really have to follow the specification where
1913 * it says that version is odd if data is being modified, and even after
1914 * it is consistent.
1915 *
1916 * Version field updates must be kept separate. This is because
1917 * kvm_write_guest_cached might use a "rep movs" instruction, and
1918 * writes within a string instruction are weakly ordered. So there
1919 * are three writes overall.
1920 *
1921 * As a small optimization, only write the version field in the first
1922 * and third write. The vcpu->pv_time cache is still valid, because the
1923 * version field is the first in the struct.
1924 */
1925 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1926
51c4b8bb
LA		 1927 if (guest_hv_clock.version & 1)
1928 ++guest_hv_clock.version; /* first time write, random junk */
1929
0d6dd2ff 1930 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1931 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1932 &vcpu->hv_clock,
1933 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1934
1935 smp_wmb();
1936
1937 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1938 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1939
1940 if (vcpu->pvclock_set_guest_stopped_request) {
1941 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1942 vcpu->pvclock_set_guest_stopped_request = false;
1943 }
1944
1945 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1946
4e335d9e
PB		 1947 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1948 &vcpu->hv_clock,
1949 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1950
1951 smp_wmb();
1952
1953 vcpu->hv_clock.version++;
4e335d9e
PB		 1954 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1955 &vcpu->hv_clock,
1956 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1957}
1958
34c238a1 1959static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1960{
78db6a50 1961 unsigned long flags, tgt_tsc_khz;
18068523 1962 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1963 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1964 s64 kernel_ns;
d828199e 1965 u64 tsc_timestamp, host_tsc;
51d59c6b 1966 u8 pvclock_flags;
d828199e
MT		 1967 bool use_master_clock;
1968
1969 kernel_ns = 0;
1970 host_tsc = 0;
18068523 1971
d828199e
MT		 1972 /*
1973 * If the host uses TSC clock, then passthrough TSC as stable
1974 * to the guest.
1975 */
1976 spin_lock(&ka->pvclock_gtod_sync_lock);
1977 use_master_clock = ka->use_master_clock;
1978 if (use_master_clock) {
1979 host_tsc = ka->master_cycle_now;
1980 kernel_ns = ka->master_kernel_ns;
1981 }
1982 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1983
1984 /* Keep irq disabled to prevent changes to the clock */
1985 local_irq_save(flags);
78db6a50
PB		 1986 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1987 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1988 local_irq_restore(flags);
1989 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1990 return 1;
1991 }
d828199e 1992 if (!use_master_clock) {
4ea1636b 1993 host_tsc = rdtsc();
108b249c 1994 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1995 }
1996
4ba76538 1997 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1998
c285545f
ZA		 1999 /*
2000 * We may have to catch up the TSC to match elapsed wall clock
2001 * time for two reasons, even if kvmclock is used.
2002 * 1) CPU could have been running below the maximum TSC rate
2003 * 2) Broken TSC compensation resets the base at each VCPU
2004 * entry to avoid unknown leaps of TSC even when running
2005 * again on the same CPU. This may cause apparent elapsed
2006 * time to disappear, and the guest to stand still or run
2007 * very slowly.
2008 */
2009 if (vcpu->tsc_catchup) {
2010 u64 tsc = compute_guest_tsc(v, kernel_ns);
2011 if (tsc > tsc_timestamp) {
f1e2b260 2012 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2013 tsc_timestamp = tsc;
2014 }
50d0a0f9
GH		 2015 }
2016
18068523
GOC		 2017 local_irq_restore(flags);
2018
0d6dd2ff 2019 /* With all the info we got, fill in the values */
18068523 2020
78db6a50
PB		 2021 if (kvm_has_tsc_control)
2022 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2023
2024 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2025 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2026 &vcpu->hv_clock.tsc_shift,
2027 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2028 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2029 }
2030
1d5f066e 2031 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2032 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2033 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2034
d828199e 2035 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2036 pvclock_flags = 0;
d828199e
MT		 2037 if (use_master_clock)
2038 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2039
78c0337a
MT		 2040 vcpu->hv_clock.flags = pvclock_flags;
2041
095cf55d
PB		 2042 if (vcpu->pv_time_enabled)
2043 kvm_setup_pvclock_page(v);
2044 if (v == kvm_get_vcpu(v->kvm, 0))
2045 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2046 return 0;
c8076604
GH		 2047}
2048
0061d53d
MT		 2049/*
2050 * kvmclock updates which are isolated to a given vcpu, such as
2051 * vcpu->cpu migration, should not allow system_timestamp from
2052 * the rest of the vcpus to remain static. Otherwise ntp frequency
2053 * correction applies to one vcpu's system_timestamp but not
2054 * the others.
2055 *
2056 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2057 * We need to rate-limit these requests though, as they can
2058 * considerably slow guests that have a large number of vcpus.
2059 * The time for a remote vcpu to update its kvmclock is bound
2060 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2061 */
2062
7e44e449
AJ		 2063#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2064
2065static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2066{
2067 int i;
7e44e449
AJ		 2068 struct delayed_work *dwork = to_delayed_work(work);
2069 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2070 kvmclock_update_work);
2071 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2072 struct kvm_vcpu *vcpu;
2073
2074 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2075 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2076 kvm_vcpu_kick(vcpu);
2077 }
2078}
2079
7e44e449
AJ		 2080static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2081{
2082 struct kvm *kvm = v->kvm;
2083
105b21bb 2084 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2085 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2086 KVMCLOCK_UPDATE_DELAY);
2087}
2088
332967a3
AJ		 2089#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2090
2091static void kvmclock_sync_fn(struct work_struct *work)
2092{
2093 struct delayed_work *dwork = to_delayed_work(work);
2094 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2095 kvmclock_sync_work);
2096 struct kvm *kvm = container_of(ka, struct kvm, arch);
2097
630994b3
MT		 2098 if (!kvmclock_periodic_sync)
2099 return;
2100
332967a3
AJ		 2101 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2102 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2103 KVMCLOCK_SYNC_PERIOD);
2104}
2105
9ffd986c 2106static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2107{
890ca9ae
HY		 2108 u64 mcg_cap = vcpu->arch.mcg_cap;
2109 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2110 u32 msr = msr_info->index;
2111 u64 data = msr_info->data;
890ca9ae 2112
15c4a640 2113 switch (msr) {
15c4a640 2114 case MSR_IA32_MCG_STATUS:
890ca9ae 2115 vcpu->arch.mcg_status = data;
15c4a640 2116 break;
c7ac679c 2117 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2118 if (!(mcg_cap & MCG_CTL_P))
2119 return 1;
2120 if (data != 0 && data != ~(u64)0)
2121 return -1;
2122 vcpu->arch.mcg_ctl = data;
2123 break;
2124 default:
2125 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2126 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2127 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2128 /* only 0 or all 1s can be written to IA32_MCi_CTL
2129 * some Linux kernels though clear bit 10 in bank 4 to
2130 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2131 * this to avoid an uncatched #GP in the guest
2132 */
890ca9ae 2133 if ((offset & 0x3) == 0 &&
114be429 2134 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2135 return -1;
9ffd986c
WL		 2136 if (!msr_info->host_initiated &&
2137 (offset & 0x3) == 1 && data != 0)
2138 return -1;
890ca9ae
HY		 2139 vcpu->arch.mce_banks[offset] = data;
2140 break;
2141 }
2142 return 1;
2143 }
2144 return 0;
2145}
2146
ffde22ac
ES		 2147static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2148{
2149 struct kvm *kvm = vcpu->kvm;
2150 int lm = is_long_mode(vcpu);
2151 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2152 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2153 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2154 : kvm->arch.xen_hvm_config.blob_size_32;
2155 u32 page_num = data & ~PAGE_MASK;
2156 u64 page_addr = data & PAGE_MASK;
2157 u8 *page;
2158 int r;
2159
2160 r = -E2BIG;
2161 if (page_num >= blob_size)
2162 goto out;
2163 r = -ENOMEM;
ff5c2c03
SL		 2164 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2165 if (IS_ERR(page)) {
2166 r = PTR_ERR(page);
ffde22ac 2167 goto out;
ff5c2c03 2168 }
54bf36aa 2169 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2170 goto out_free;
2171 r = 0;
2172out_free:
2173 kfree(page);
2174out:
2175 return r;
2176}
2177
344d9588
GN		 2178static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2179{
2180 gpa_t gpa = data & ~0x3f;
2181
52a5c155
WL		 2182 /* Bits 3:5 are reserved, Should be zero */
2183 if (data & 0x38)
344d9588
GN		 2184 return 1;
2185
2186 vcpu->arch.apf.msr_val = data;
2187
2188 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2189 kvm_clear_async_pf_completion_queue(vcpu);
2190 kvm_async_pf_hash_reset(vcpu);
2191 return 0;
2192 }
2193
4e335d9e 2194 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2195 sizeof(u32)))
344d9588
GN		 2196 return 1;
2197
6adba527 2198 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2199 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2200 kvm_async_pf_wakeup_all(vcpu);
2201 return 0;
2202}
2203
12f9a48f
GC		 2204static void kvmclock_reset(struct kvm_vcpu *vcpu)
2205{
0b79459b 2206 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2207}
2208
f38a7b75
WL		 2209static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2210{
2211 ++vcpu->stat.tlb_flush;
2212 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2213}
2214
c9aaa895
GC		 2215static void record_steal_time(struct kvm_vcpu *vcpu)
2216{
2217 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2218 return;
2219
4e335d9e 2220 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2221 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2222 return;
2223
f38a7b75
WL		 2224 /*
2225 * Doing a TLB flush here, on the guest's behalf, can avoid
2226 * expensive IPIs.
2227 */
2228 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2229 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2230
35f3fae1
WL		 2231 if (vcpu->arch.st.steal.version & 1)
2232 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2233
2234 vcpu->arch.st.steal.version += 1;
2235
4e335d9e 2236 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2237 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2238
2239 smp_wmb();
2240
c54cdf14
LC		 2241 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2242 vcpu->arch.st.last_steal;
2243 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2244
4e335d9e 2245 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2246 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2247
2248 smp_wmb();
2249
2250 vcpu->arch.st.steal.version += 1;
c9aaa895 2251
4e335d9e 2252 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2253 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2254}
2255
8fe8ab46 2256int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2257{
5753785f 2258 bool pr = false;
8fe8ab46
WA		 2259 u32 msr = msr_info->index;
2260 u64 data = msr_info->data;
5753785f 2261
15c4a640 2262 switch (msr) {
2e32b719 2263 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2264 case MSR_IA32_UCODE_WRITE:
2265 case MSR_VM_HSAVE_PA:
2266 case MSR_AMD64_PATCH_LOADER:
2267 case MSR_AMD64_BU_CFG2:
405a353a 2268 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2269 break;
2270
518e7b94
WL		 2271 case MSR_IA32_UCODE_REV:
2272 if (msr_info->host_initiated)
2273 vcpu->arch.microcode_version = data;
2274 break;
15c4a640 2275 case MSR_EFER:
b69e8cae 2276 return set_efer(vcpu, data);
8f1589d9
AP		 2277 case MSR_K7_HWCR:
2278 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2279 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2280 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2281 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2282 if (data != 0) {
a737f256
CD		 2283 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2284 data);
8f1589d9
AP		 2285 return 1;
2286 }
15c4a640 2287 break;
f7c6d140
AP		 2288 case MSR_FAM10H_MMIO_CONF_BASE:
2289 if (data != 0) {
a737f256
CD		 2290 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2291 "0x%llx\n", data);
f7c6d140
AP		 2292 return 1;
2293 }
15c4a640 2294 break;
b5e2fec0
AG		 2295 case MSR_IA32_DEBUGCTLMSR:
2296 if (!data) {
2297 /* We support the non-activated case already */
2298 break;
2299 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2300 /* Values other than LBR and BTF are vendor-specific,
2301 thus reserved and should throw a #GP */
2302 return 1;
2303 }
a737f256
CD		 2304 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2305 __func__, data);
b5e2fec0 2306 break;
9ba075a6 2307 case 0x200 ... 0x2ff:
ff53604b 2308 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2309 case MSR_IA32_APICBASE:
58cb628d 2310 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2311 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2312 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2313 case MSR_IA32_TSCDEADLINE:
2314 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2315 break;
ba904635 2316 case MSR_IA32_TSC_ADJUST:
d6321d49 2317 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2318 if (!msr_info->host_initiated) {
d913b904 2319 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2320 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2321 }
2322 vcpu->arch.ia32_tsc_adjust_msr = data;
2323 }
2324 break;
15c4a640 2325 case MSR_IA32_MISC_ENABLE:
ad312c7c 2326 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2327 break;
64d60670
PB		 2328 case MSR_IA32_SMBASE:
2329 if (!msr_info->host_initiated)
2330 return 1;
2331 vcpu->arch.smbase = data;
2332 break;
52797bf9
LA		 2333 case MSR_SMI_COUNT:
2334 if (!msr_info->host_initiated)
2335 return 1;
2336 vcpu->arch.smi_count = data;
2337 break;
11c6bffa 2338 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2339 case MSR_KVM_WALL_CLOCK:
2340 vcpu->kvm->arch.wall_clock = data;
2341 kvm_write_wall_clock(vcpu->kvm, data);
2342 break;
11c6bffa 2343 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2344 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2345 struct kvm_arch *ka = &vcpu->kvm->arch;
2346
12f9a48f 2347 kvmclock_reset(vcpu);
18068523 2348
54750f2c
MT		 2349 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2350 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2351
2352 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2353 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2354
2355 ka->boot_vcpu_runs_old_kvmclock = tmp;
2356 }
2357
18068523 2358 vcpu->arch.time = data;
0061d53d 2359 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2360
2361 /* we verify if the enable bit is set... */
2362 if (!(data & 1))
2363 break;
2364
4e335d9e 2365 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2366 &vcpu->arch.pv_time, data & ~1ULL,
2367 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2368 vcpu->arch.pv_time_enabled = false;
2369 else
2370 vcpu->arch.pv_time_enabled = true;
32cad84f 2371
18068523
GOC		 2372 break;
2373 }
344d9588
GN		 2374 case MSR_KVM_ASYNC_PF_EN:
2375 if (kvm_pv_enable_async_pf(vcpu, data))
2376 return 1;
2377 break;
c9aaa895
GC		 2378 case MSR_KVM_STEAL_TIME:
2379
2380 if (unlikely(!sched_info_on()))
2381 return 1;
2382
2383 if (data & KVM_STEAL_RESERVED_MASK)
2384 return 1;
2385
4e335d9e 2386 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2387 data & KVM_STEAL_VALID_BITS,
2388 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2389 return 1;
2390
2391 vcpu->arch.st.msr_val = data;
2392
2393 if (!(data & KVM_MSR_ENABLED))
2394 break;
2395
c9aaa895
GC		 2396 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2397
2398 break;
ae7a2a3f
MT		 2399 case MSR_KVM_PV_EOI_EN:
2400 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2401 return 1;
2402 break;
c9aaa895 2403
890ca9ae
HY		 2404 case MSR_IA32_MCG_CTL:
2405 case MSR_IA32_MCG_STATUS:
81760dcc 2406 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2407 return set_msr_mce(vcpu, msr_info);
71db6023 2408
6912ac32
WH		 2409 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2410 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2411 pr = true; /* fall through */
2412 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2413 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2414 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2415 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2416
2417 if (pr || data != 0)
a737f256
CD		 2418 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2419 "0x%x data 0x%llx\n", msr, data);
5753785f 2420 break;
84e0cefa
JS		 2421 case MSR_K7_CLK_CTL:
2422 /*
2423 * Ignore all writes to this no longer documented MSR.
2424 * Writes are only relevant for old K7 processors,
2425 * all pre-dating SVM, but a recommended workaround from
4a969980 2426 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2427 * affected processor models on the command line, hence
2428 * the need to ignore the workaround.
2429 */
2430 break;
55cd8e5a 2431 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2432 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2433 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2434 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2435 return kvm_hv_set_msr_common(vcpu, msr, data,
2436 msr_info->host_initiated);
91c9c3ed 2437 case MSR_IA32_BBL_CR_CTL3:
2438 /* Drop writes to this legacy MSR -- see rdmsr
2439 * counterpart for further detail.
2440 */
fab0aa3b
EM		 2441 if (report_ignored_msrs)
2442 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2443 msr, data);
91c9c3ed 2444 break;
2b036c6b 2445 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2446 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2447 return 1;
2448 vcpu->arch.osvw.length = data;
2449 break;
2450 case MSR_AMD64_OSVW_STATUS:
d6321d49 2451 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2452 return 1;
2453 vcpu->arch.osvw.status = data;
2454 break;
db2336a8
KH		 2455 case MSR_PLATFORM_INFO:
2456 if (!msr_info->host_initiated ||
2457 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2458 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2459 cpuid_fault_enabled(vcpu)))
2460 return 1;
2461 vcpu->arch.msr_platform_info = data;
2462 break;
2463 case MSR_MISC_FEATURES_ENABLES:
2464 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2465 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2466 !supports_cpuid_fault(vcpu)))
2467 return 1;
2468 vcpu->arch.msr_misc_features_enables = data;
2469 break;
15c4a640 2470 default:
ffde22ac
ES		 2471 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2472 return xen_hvm_config(vcpu, data);
c6702c9d 2473 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2474 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2475 if (!ignore_msrs) {
ae0f5499 2476 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2477 msr, data);
ed85c068
AP		 2478 return 1;
2479 } else {
fab0aa3b
EM		 2480 if (report_ignored_msrs)
2481 vcpu_unimpl(vcpu,
2482 "ignored wrmsr: 0x%x data 0x%llx\n",
2483 msr, data);
ed85c068
AP		 2484 break;
2485 }
15c4a640
CO		 2486 }
2487 return 0;
2488}
2489EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2490
2491
2492/*
2493 * Reads an msr value (of 'msr_index') into 'pdata'.
2494 * Returns 0 on success, non-0 otherwise.
2495 * Assumes vcpu_load() was already called.
2496 */
609e36d3 2497int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2498{
609e36d3 2499 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2500}
ff651cb6 2501EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2502
890ca9ae 2503static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2504{
2505 u64 data;
890ca9ae
HY		 2506 u64 mcg_cap = vcpu->arch.mcg_cap;
2507 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2508
2509 switch (msr) {
15c4a640
CO		 2510 case MSR_IA32_P5_MC_ADDR:
2511 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2512 data = 0;
2513 break;
15c4a640 2514 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2515 data = vcpu->arch.mcg_cap;
2516 break;
c7ac679c 2517 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2518 if (!(mcg_cap & MCG_CTL_P))
2519 return 1;
2520 data = vcpu->arch.mcg_ctl;
2521 break;
2522 case MSR_IA32_MCG_STATUS:
2523 data = vcpu->arch.mcg_status;
2524 break;
2525 default:
2526 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2527 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2528 u32 offset = msr - MSR_IA32_MC0_CTL;
2529 data = vcpu->arch.mce_banks[offset];
2530 break;
2531 }
2532 return 1;
2533 }
2534 *pdata = data;
2535 return 0;
2536}
2537
609e36d3 2538int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2539{
609e36d3 2540 switch (msr_info->index) {
890ca9ae 2541 case MSR_IA32_PLATFORM_ID:
15c4a640 2542 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2543 case MSR_IA32_DEBUGCTLMSR:
2544 case MSR_IA32_LASTBRANCHFROMIP:
2545 case MSR_IA32_LASTBRANCHTOIP:
2546 case MSR_IA32_LASTINTFROMIP:
2547 case MSR_IA32_LASTINTTOIP:
60af2ecd 2548 case MSR_K8_SYSCFG:
3afb1121
PB		 2549 case MSR_K8_TSEG_ADDR:
2550 case MSR_K8_TSEG_MASK:
60af2ecd 2551 case MSR_K7_HWCR:
61a6bd67 2552 case MSR_VM_HSAVE_PA:
1fdbd48c 2553 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2554 case MSR_AMD64_NB_CFG:
f7c6d140 2555 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2556 case MSR_AMD64_BU_CFG2:
0c2df2a1 2557 case MSR_IA32_PERF_CTL:
405a353a 2558 case MSR_AMD64_DC_CFG:
609e36d3 2559 msr_info->data = 0;
15c4a640 2560 break;
6912ac32
WH		 2561 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2562 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2563 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2564 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2565 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2566 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2567 msr_info->data = 0;
5753785f 2568 break;
742bc670 2569 case MSR_IA32_UCODE_REV:
518e7b94 2570 msr_info->data = vcpu->arch.microcode_version;
742bc670 2571 break;
9ba075a6 2572 case MSR_MTRRcap:
9ba075a6 2573 case 0x200 ... 0x2ff:
ff53604b 2574 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2575 case 0xcd: /* fsb frequency */
609e36d3 2576 msr_info->data = 3;
15c4a640 2577 break;
7b914098
JS		 2578 /*
2579 * MSR_EBC_FREQUENCY_ID
2580 * Conservative value valid for even the basic CPU models.
2581 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2582 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2583 * and 266MHz for model 3, or 4. Set Core Clock
2584 * Frequency to System Bus Frequency Ratio to 1 (bits
2585 * 31:24) even though these are only valid for CPU
2586 * models > 2, however guests may end up dividing or
2587 * multiplying by zero otherwise.
2588 */
2589 case MSR_EBC_FREQUENCY_ID:
609e36d3 2590 msr_info->data = 1 << 24;
7b914098 2591 break;
15c4a640 2592 case MSR_IA32_APICBASE:
609e36d3 2593 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2594 break;
0105d1a5 2595 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2596 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2597 break;
a3e06bbe 2598 case MSR_IA32_TSCDEADLINE:
609e36d3 2599 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2600 break;
ba904635 2601 case MSR_IA32_TSC_ADJUST:
609e36d3 2602 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2603 break;
15c4a640 2604 case MSR_IA32_MISC_ENABLE:
609e36d3 2605 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2606 break;
64d60670
PB		 2607 case MSR_IA32_SMBASE:
2608 if (!msr_info->host_initiated)
2609 return 1;
2610 msr_info->data = vcpu->arch.smbase;
15c4a640 2611 break;
52797bf9
LA		 2612 case MSR_SMI_COUNT:
2613 msr_info->data = vcpu->arch.smi_count;
2614 break;
847f0ad8
AG		 2615 case MSR_IA32_PERF_STATUS:
2616 /* TSC increment by tick */
609e36d3 2617 msr_info->data = 1000ULL;
847f0ad8 2618 /* CPU multiplier */
b0996ae4 2619 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2620 break;
15c4a640 2621 case MSR_EFER:
609e36d3 2622 msr_info->data = vcpu->arch.efer;
15c4a640 2623 break;
18068523 2624 case MSR_KVM_WALL_CLOCK:
11c6bffa 2625 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2626 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2627 break;
2628 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2629 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2630 msr_info->data = vcpu->arch.time;
18068523 2631 break;
344d9588 2632 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2633 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2634 break;
c9aaa895 2635 case MSR_KVM_STEAL_TIME:
609e36d3 2636 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2637 break;
1d92128f 2638 case MSR_KVM_PV_EOI_EN:
609e36d3 2639 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2640 break;
890ca9ae
HY		 2641 case MSR_IA32_P5_MC_ADDR:
2642 case MSR_IA32_P5_MC_TYPE:
2643 case MSR_IA32_MCG_CAP:
2644 case MSR_IA32_MCG_CTL:
2645 case MSR_IA32_MCG_STATUS:
81760dcc 2646 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2647 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2648 case MSR_K7_CLK_CTL:
2649 /*
2650 * Provide expected ramp-up count for K7. All other
2651 * are set to zero, indicating minimum divisors for
2652 * every field.
2653 *
2654 * This prevents guest kernels on AMD host with CPU
2655 * type 6, model 8 and higher from exploding due to
2656 * the rdmsr failing.
2657 */
609e36d3 2658 msr_info->data = 0x20000000;
84e0cefa 2659 break;
55cd8e5a 2660 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2661 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2662 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2663 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2664 return kvm_hv_get_msr_common(vcpu,
2665 msr_info->index, &msr_info->data);
55cd8e5a 2666 break;
91c9c3ed 2667 case MSR_IA32_BBL_CR_CTL3:
2668 /* This legacy MSR exists but isn't fully documented in current
2669 * silicon. It is however accessed by winxp in very narrow
2670 * scenarios where it sets bit #19, itself documented as
2671 * a "reserved" bit. Best effort attempt to source coherent
2672 * read data here should the balance of the register be
2673 * interpreted by the guest:
2674 *
2675 * L2 cache control register 3: 64GB range, 256KB size,
2676 * enabled, latency 0x1, configured
2677 */
609e36d3 2678 msr_info->data = 0xbe702111;
91c9c3ed 2679 break;
2b036c6b 2680 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2681 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2682 return 1;
609e36d3 2683 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2684 break;
2685 case MSR_AMD64_OSVW_STATUS:
d6321d49 2686 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2687 return 1;
609e36d3 2688 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2689 break;
db2336a8
KH		 2690 case MSR_PLATFORM_INFO:
2691 msr_info->data = vcpu->arch.msr_platform_info;
2692 break;
2693 case MSR_MISC_FEATURES_ENABLES:
2694 msr_info->data = vcpu->arch.msr_misc_features_enables;
2695 break;
15c4a640 2696 default:
c6702c9d 2697 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2698 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2699 if (!ignore_msrs) {
ae0f5499
BD		 2700 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2701 msr_info->index);
ed85c068
AP		 2702 return 1;
2703 } else {
fab0aa3b
EM		 2704 if (report_ignored_msrs)
2705 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2706 msr_info->index);
609e36d3 2707 msr_info->data = 0;
ed85c068
AP		 2708 }
2709 break;
15c4a640 2710 }
15c4a640
CO		 2711 return 0;
2712}
2713EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2714
313a3dc7
CO		 2715/*
2716 * Read or write a bunch of msrs. All parameters are kernel addresses.
2717 *
2718 * @return number of msrs set successfully.
2719 */
2720static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2721 struct kvm_msr_entry *entries,
2722 int (*do_msr)(struct kvm_vcpu *vcpu,
2723 unsigned index, u64 *data))
2724{
801e459a 2725 int i;
313a3dc7 2726
313a3dc7
CO		 2727 for (i = 0; i < msrs->nmsrs; ++i)
2728 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2729 break;
2730
313a3dc7
CO		 2731 return i;
2732}
2733
2734/*
2735 * Read or write a bunch of msrs. Parameters are user addresses.
2736 *
2737 * @return number of msrs set successfully.
2738 */
2739static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2740 int (*do_msr)(struct kvm_vcpu *vcpu,
2741 unsigned index, u64 *data),
2742 int writeback)
2743{
2744 struct kvm_msrs msrs;
2745 struct kvm_msr_entry *entries;
2746 int r, n;
2747 unsigned size;
2748
2749 r = -EFAULT;
2750 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2751 goto out;
2752
2753 r = -E2BIG;
2754 if (msrs.nmsrs >= MAX_IO_MSRS)
2755 goto out;
2756
313a3dc7 2757 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2758 entries = memdup_user(user_msrs->entries, size);
2759 if (IS_ERR(entries)) {
2760 r = PTR_ERR(entries);
313a3dc7 2761 goto out;
ff5c2c03 2762 }
313a3dc7
CO		 2763
2764 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2765 if (r < 0)
2766 goto out_free;
2767
2768 r = -EFAULT;
2769 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2770 goto out_free;
2771
2772 r = n;
2773
2774out_free:
7a73c028 2775 kfree(entries);
313a3dc7
CO		 2776out:
2777 return r;
2778}
2779
784aa3d7 2780int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2781{
2782 int r;
2783
2784 switch (ext) {
2785 case KVM_CAP_IRQCHIP:
2786 case KVM_CAP_HLT:
2787 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2788 case KVM_CAP_SET_TSS_ADDR:
07716717 2789 case KVM_CAP_EXT_CPUID:
9c15bb1d 2790 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2791 case KVM_CAP_CLOCKSOURCE:
7837699f 2792 case KVM_CAP_PIT:
a28e4f5a 2793 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2794 case KVM_CAP_MP_STATE:
ed848624 2795 case KVM_CAP_SYNC_MMU:
a355c85c 2796 case KVM_CAP_USER_NMI:
52d939a0 2797 case KVM_CAP_REINJECT_CONTROL:
4925663a 2798 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2799 case KVM_CAP_IOEVENTFD:
f848a5a8 2800 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2801 case KVM_CAP_PIT2:
e9f42757 2802 case KVM_CAP_PIT_STATE2:
b927a3ce 2803 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2804 case KVM_CAP_XEN_HVM:
3cfc3092 2805 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2806 case KVM_CAP_HYPERV:
10388a07 2807 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2808 case KVM_CAP_HYPERV_SPIN:
5c919412 2809 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2810 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2811 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2812 case KVM_CAP_HYPERV_EVENTFD:
ab9f4ecb 2813 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2814 case KVM_CAP_DEBUGREGS:
d2be1651 2815 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2816 case KVM_CAP_XSAVE:
344d9588 2817 case KVM_CAP_ASYNC_PF:
92a1f12d 2818 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2819 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2820 case KVM_CAP_READONLY_MEM:
5f66b620 2821 case KVM_CAP_HYPERV_TIME:
100943c5 2822 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2823 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2824 case KVM_CAP_ENABLE_CAP_VM:
2825 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2826 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2827 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2828 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2829 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2830 r = 1;
2831 break;
e3fd9a93
PB		 2832 case KVM_CAP_ADJUST_CLOCK:
2833 r = KVM_CLOCK_TSC_STABLE;
2834 break;
668fffa3
MT		 2835 case KVM_CAP_X86_GUEST_MWAIT:
2836 r = kvm_mwait_in_guest();
2837 break;
6d396b55
PB		 2838 case KVM_CAP_X86_SMM:
2839 /* SMBASE is usually relocated above 1M on modern chipsets,
2840 * and SMM handlers might indeed rely on 4G segment limits,
2841 * so do not report SMM to be available if real mode is
2842 * emulated via vm86 mode. Still, do not go to great lengths
2843 * to avoid userspace's usage of the feature, because it is a
2844 * fringe case that is not enabled except via specific settings
2845 * of the module parameters.
2846 */
2847 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2848 break;
774ead3a
AK		 2849 case KVM_CAP_VAPIC:
2850 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2851 break;
f725230a 2852 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2853 r = KVM_SOFT_MAX_VCPUS;
2854 break;
2855 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2856 r = KVM_MAX_VCPUS;
2857 break;
a988b910 2858 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2859 r = KVM_USER_MEM_SLOTS;
a988b910 2860 break;
a68a6a72
MT		 2861 case KVM_CAP_PV_MMU: /* obsolete */
2862 r = 0;
2f333bcb 2863 break;
890ca9ae
HY		 2864 case KVM_CAP_MCE:
2865 r = KVM_MAX_MCE_BANKS;
2866 break;
2d5b5a66 2867 case KVM_CAP_XCRS:
d366bf7e 2868 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2869 break;
92a1f12d
JR		 2870 case KVM_CAP_TSC_CONTROL:
2871 r = kvm_has_tsc_control;
2872 break;
37131313
RK		 2873 case KVM_CAP_X2APIC_API:
2874 r = KVM_X2APIC_API_VALID_FLAGS;
2875 break;
018d00d2
ZX		 2876 default:
2877 r = 0;
2878 break;
2879 }
2880 return r;
2881
2882}
2883
043405e1
CO		 2884long kvm_arch_dev_ioctl(struct file *filp,
2885 unsigned int ioctl, unsigned long arg)
2886{
2887 void __user *argp = (void __user *)arg;
2888 long r;
2889
2890 switch (ioctl) {
2891 case KVM_GET_MSR_INDEX_LIST: {
2892 struct kvm_msr_list __user *user_msr_list = argp;
2893 struct kvm_msr_list msr_list;
2894 unsigned n;
2895
2896 r = -EFAULT;
2897 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2898 goto out;
2899 n = msr_list.nmsrs;
62ef68bb 2900 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2901 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2902 goto out;
2903 r = -E2BIG;
e125e7b6 2904 if (n < msr_list.nmsrs)
043405e1
CO		 2905 goto out;
2906 r = -EFAULT;
2907 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2908 num_msrs_to_save * sizeof(u32)))
2909 goto out;
e125e7b6 2910 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2911 &emulated_msrs,
62ef68bb 2912 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2913 goto out;
2914 r = 0;
2915 break;
2916 }
9c15bb1d
BP		 2917 case KVM_GET_SUPPORTED_CPUID:
2918 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2919 struct kvm_cpuid2 __user *cpuid_arg = argp;
2920 struct kvm_cpuid2 cpuid;
2921
2922 r = -EFAULT;
2923 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2924 goto out;
9c15bb1d
BP		 2925
2926 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2927 ioctl);
674eea0f
AK		 2928 if (r)
2929 goto out;
2930
2931 r = -EFAULT;
2932 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2933 goto out;
2934 r = 0;
2935 break;
2936 }
890ca9ae 2937 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2938 r = -EFAULT;
c45dcc71
AR		 2939 if (copy_to_user(argp, &kvm_mce_cap_supported,
2940 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2941 goto out;
2942 r = 0;
2943 break;
801e459a
TL		 2944 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
2945 struct kvm_msr_list __user *user_msr_list = argp;
2946 struct kvm_msr_list msr_list;
2947 unsigned int n;
2948
2949 r = -EFAULT;
2950 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
2951 goto out;
2952 n = msr_list.nmsrs;
2953 msr_list.nmsrs = num_msr_based_features;
2954 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
2955 goto out;
2956 r = -E2BIG;
2957 if (n < msr_list.nmsrs)
2958 goto out;
2959 r = -EFAULT;
2960 if (copy_to_user(user_msr_list->indices, &msr_based_features,
2961 num_msr_based_features * sizeof(u32)))
2962 goto out;
2963 r = 0;
2964 break;
2965 }
2966 case KVM_GET_MSRS:
2967 r = msr_io(NULL, argp, do_get_msr_feature, 1);
2968 break;
890ca9ae 2969 }
043405e1
CO		 2970 default:
2971 r = -EINVAL;
2972 }
2973out:
2974 return r;
2975}
2976
f5f48ee1
SY		 2977static void wbinvd_ipi(void *garbage)
2978{
2979 wbinvd();
2980}
2981
2982static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2983{
e0f0bbc5 2984 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2985}
2986
313a3dc7
CO		 2987void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2988{
f5f48ee1
SY		 2989 /* Address WBINVD may be executed by guest */
2990 if (need_emulate_wbinvd(vcpu)) {
2991 if (kvm_x86_ops->has_wbinvd_exit())
2992 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2993 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2994 smp_call_function_single(vcpu->cpu,
2995 wbinvd_ipi, NULL, 1);
2996 }
2997
313a3dc7 2998 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2999
0dd6a6ed
ZA		 3000 /* Apply any externally detected TSC adjustments (due to suspend) */
3001 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3002 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3003 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3004 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3005 }
8f6055cb 3006
b0c39dc6 3007 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3008 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3009 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3010 if (tsc_delta < 0)
3011 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3012
b0c39dc6 3013 if (kvm_check_tsc_unstable()) {
07c1419a 3014 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3015 vcpu->arch.last_guest_tsc);
a545ab6a 3016 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3017 vcpu->arch.tsc_catchup = 1;
c285545f 3018 }
a749e247
PB		 3019
3020 if (kvm_lapic_hv_timer_in_use(vcpu))
3021 kvm_lapic_restart_hv_timer(vcpu);
3022
d98d07ca
MT		 3023 /*
3024 * On a host with synchronized TSC, there is no need to update
3025 * kvmclock on vcpu->cpu migration
3026 */
3027 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3028 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3029 if (vcpu->cpu != cpu)
1bd2009e 3030 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3031 vcpu->cpu = cpu;
6b7d7e76 3032 }
c9aaa895 3033
c9aaa895 3034 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3035}
3036
0b9f6c46
PX		 3037static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3038{
3039 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3040 return;
3041
fa55eedd 3042 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3043
4e335d9e 3044 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3045 &vcpu->arch.st.steal.preempted,
3046 offsetof(struct kvm_steal_time, preempted),
3047 sizeof(vcpu->arch.st.steal.preempted));
3048}
3049
313a3dc7
CO		 3050void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3051{
cc0d907c 3052 int idx;
de63ad4c
LM		 3053
3054 if (vcpu->preempted)
3055 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3056
931f261b
AA		 3057 /*
3058 * Disable page faults because we're in atomic context here.
3059 * kvm_write_guest_offset_cached() would call might_fault()
3060 * that relies on pagefault_disable() to tell if there's a
3061 * bug. NOTE: the write to guest memory may not go through if
3062 * during postcopy live migration or if there's heavy guest
3063 * paging.
3064 */
3065 pagefault_disable();
cc0d907c
AA		 3066 /*
3067 * kvm_memslots() will be called by
3068 * kvm_write_guest_offset_cached() so take the srcu lock.
3069 */
3070 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3071 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3072 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3073 pagefault_enable();
02daab21 3074 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3075 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3076 /*
3077 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3078 * on every vmexit, but if not, we might have a stale dr6 from the
3079 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3080 */
3081 set_debugreg(0, 6);
313a3dc7
CO		 3082}
3083
313a3dc7
CO		 3084static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3085 struct kvm_lapic_state *s)
3086{
fa59cc00 3087 if (vcpu->arch.apicv_active)
d62caabb
AS		 3088 kvm_x86_ops->sync_pir_to_irr(vcpu);
3089
a92e2543 3090 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3091}
3092
3093static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3094 struct kvm_lapic_state *s)
3095{
a92e2543
RK		 3096 int r;
3097
3098 r = kvm_apic_set_state(vcpu, s);
3099 if (r)
3100 return r;
cb142eb7 3101 update_cr8_intercept(vcpu);
313a3dc7
CO		 3102
3103 return 0;
3104}
3105
127a457a
MG		 3106static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3107{
3108 return (!lapic_in_kernel(vcpu) ||
3109 kvm_apic_accept_pic_intr(vcpu));
3110}
3111
782d422b
MG		 3112/*
3113 * if userspace requested an interrupt window, check that the
3114 * interrupt window is open.
3115 *
3116 * No need to exit to userspace if we already have an interrupt queued.
3117 */
3118static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3119{
3120 return kvm_arch_interrupt_allowed(vcpu) &&
3121 !kvm_cpu_has_interrupt(vcpu) &&
3122 !kvm_event_needs_reinjection(vcpu) &&
3123 kvm_cpu_accept_dm_intr(vcpu);
3124}
3125
f77bc6a4
ZX		 3126static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3127 struct kvm_interrupt *irq)
3128{
02cdb50f 3129 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3130 return -EINVAL;
1c1a9ce9
SR		 3131
3132 if (!irqchip_in_kernel(vcpu->kvm)) {
3133 kvm_queue_interrupt(vcpu, irq->irq, false);
3134 kvm_make_request(KVM_REQ_EVENT, vcpu);
3135 return 0;
3136 }
3137
3138 /*
3139 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3140 * fail for in-kernel 8259.
3141 */
3142 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3143 return -ENXIO;
f77bc6a4 3144
1c1a9ce9
SR		 3145 if (vcpu->arch.pending_external_vector != -1)
3146 return -EEXIST;
f77bc6a4 3147
1c1a9ce9 3148 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3149 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3150 return 0;
3151}
3152
c4abb7c9
JK		 3153static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3154{
c4abb7c9 3155 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3156
3157 return 0;
3158}
3159
f077825a
PB		 3160static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3161{
64d60670
PB		 3162 kvm_make_request(KVM_REQ_SMI, vcpu);
3163
f077825a
PB		 3164 return 0;
3165}
3166
b209749f
AK		 3167static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3168 struct kvm_tpr_access_ctl *tac)
3169{
3170 if (tac->flags)
3171 return -EINVAL;
3172 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3173 return 0;
3174}
3175
890ca9ae
HY		 3176static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3177 u64 mcg_cap)
3178{
3179 int r;
3180 unsigned bank_num = mcg_cap & 0xff, bank;
3181
3182 r = -EINVAL;
a9e38c3e 3183 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3184 goto out;
c45dcc71 3185 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3186 goto out;
3187 r = 0;
3188 vcpu->arch.mcg_cap = mcg_cap;
3189 /* Init IA32_MCG_CTL to all 1s */
3190 if (mcg_cap & MCG_CTL_P)
3191 vcpu->arch.mcg_ctl = ~(u64)0;
3192 /* Init IA32_MCi_CTL to all 1s */
3193 for (bank = 0; bank < bank_num; bank++)
3194 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3195
3196 if (kvm_x86_ops->setup_mce)
3197 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3198out:
3199 return r;
3200}
3201
3202static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3203 struct kvm_x86_mce *mce)
3204{
3205 u64 mcg_cap = vcpu->arch.mcg_cap;
3206 unsigned bank_num = mcg_cap & 0xff;
3207 u64 *banks = vcpu->arch.mce_banks;
3208
3209 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3210 return -EINVAL;
3211 /*
3212 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3213 * reporting is disabled
3214 */
3215 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3216 vcpu->arch.mcg_ctl != ~(u64)0)
3217 return 0;
3218 banks += 4 * mce->bank;
3219 /*
3220 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3221 * reporting is disabled for the bank
3222 */
3223 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3224 return 0;
3225 if (mce->status & MCI_STATUS_UC) {
3226 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3227 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3228 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3229 return 0;
3230 }
3231 if (banks[1] & MCI_STATUS_VAL)
3232 mce->status |= MCI_STATUS_OVER;
3233 banks[2] = mce->addr;
3234 banks[3] = mce->misc;
3235 vcpu->arch.mcg_status = mce->mcg_status;
3236 banks[1] = mce->status;
3237 kvm_queue_exception(vcpu, MC_VECTOR);
3238 } else if (!(banks[1] & MCI_STATUS_VAL)
3239 || !(banks[1] & MCI_STATUS_UC)) {
3240 if (banks[1] & MCI_STATUS_VAL)
3241 mce->status |= MCI_STATUS_OVER;
3242 banks[2] = mce->addr;
3243 banks[3] = mce->misc;
3244 banks[1] = mce->status;
3245 } else
3246 banks[1] |= MCI_STATUS_OVER;
3247 return 0;
3248}
3249
3cfc3092
JK		 3250static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3251 struct kvm_vcpu_events *events)
3252{
7460fb4a 3253 process_nmi(vcpu);
664f8e26
WL		 3254 /*
3255 * FIXME: pass injected and pending separately. This is only
3256 * needed for nested virtualization, whose state cannot be
3257 * migrated yet. For now we can combine them.
3258 */
03b82a30 3259 events->exception.injected =
664f8e26
WL		 3260 (vcpu->arch.exception.pending ||
3261 vcpu->arch.exception.injected) &&
03b82a30 3262 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3263 events->exception.nr = vcpu->arch.exception.nr;
3264 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3265 events->exception.pad = 0;
3cfc3092
JK		 3266 events->exception.error_code = vcpu->arch.exception.error_code;
3267
03b82a30
JK		 3268 events->interrupt.injected =
3269 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3270 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3271 events->interrupt.soft = 0;
37ccdcbe 3272 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3273
3274 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3275 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3276 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3277 events->nmi.pad = 0;
3cfc3092 3278
66450a21 3279 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3280
f077825a
PB		 3281 events->smi.smm = is_smm(vcpu);
3282 events->smi.pending = vcpu->arch.smi_pending;
3283 events->smi.smm_inside_nmi =
3284 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3285 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3286
dab4b911 3287 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3288 | KVM_VCPUEVENT_VALID_SHADOW
3289 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3290 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3291}
3292
6ef4e07e
XG		 3293static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3294
3cfc3092
JK		 3295static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3296 struct kvm_vcpu_events *events)
3297{
dab4b911 3298 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3299 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3300 | KVM_VCPUEVENT_VALID_SHADOW
3301 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3302 return -EINVAL;
3303
78e546c8 3304 if (events->exception.injected &&
28d06353
JM		 3305 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3306 is_guest_mode(vcpu)))
78e546c8
PB		 3307 return -EINVAL;
3308
28bf2888
DH		 3309 /* INITs are latched while in SMM */
3310 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3311 (events->smi.smm || events->smi.pending) &&
3312 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3313 return -EINVAL;
3314
7460fb4a 3315 process_nmi(vcpu);
664f8e26 3316 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3317 vcpu->arch.exception.pending = events->exception.injected;
3318 vcpu->arch.exception.nr = events->exception.nr;
3319 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3320 vcpu->arch.exception.error_code = events->exception.error_code;
3321
3322 vcpu->arch.interrupt.pending = events->interrupt.injected;
3323 vcpu->arch.interrupt.nr = events->interrupt.nr;
3324 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3325 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3326 kvm_x86_ops->set_interrupt_shadow(vcpu,
3327 events->interrupt.shadow);
3cfc3092
JK		 3328
3329 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3330 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3331 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3332 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3333
66450a21 3334 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3335 lapic_in_kernel(vcpu))
66450a21 3336 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3337
f077825a 3338 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3339 u32 hflags = vcpu->arch.hflags;
f077825a 3340 if (events->smi.smm)
6ef4e07e 3341 hflags |= HF_SMM_MASK;
f077825a 3342 else
6ef4e07e
XG		 3343 hflags &= ~HF_SMM_MASK;
3344 kvm_set_hflags(vcpu, hflags);
3345
f077825a 3346 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3347
3348 if (events->smi.smm) {
3349 if (events->smi.smm_inside_nmi)
3350 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3351 else
f4ef1910
WL		 3352 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3353 if (lapic_in_kernel(vcpu)) {
3354 if (events->smi.latched_init)
3355 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3356 else
3357 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3358 }
f077825a
PB		 3359 }
3360 }
3361
3842d135
AK		 3362 kvm_make_request(KVM_REQ_EVENT, vcpu);
3363
3cfc3092
JK		 3364 return 0;
3365}
3366
a1efbe77
JK		 3367static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3368 struct kvm_debugregs *dbgregs)
3369{
73aaf249
JK		 3370 unsigned long val;
3371
a1efbe77 3372 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3373 kvm_get_dr(vcpu, 6, &val);
73aaf249 3374 dbgregs->dr6 = val;
a1efbe77
JK		 3375 dbgregs->dr7 = vcpu->arch.dr7;
3376 dbgregs->flags = 0;
97e69aa6 3377 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3378}
3379
3380static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3381 struct kvm_debugregs *dbgregs)
3382{
3383 if (dbgregs->flags)
3384 return -EINVAL;
3385
d14bdb55
PB		 3386 if (dbgregs->dr6 & ~0xffffffffull)
3387 return -EINVAL;
3388 if (dbgregs->dr7 & ~0xffffffffull)
3389 return -EINVAL;
3390
a1efbe77 3391 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3392 kvm_update_dr0123(vcpu);
a1efbe77 3393 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3394 kvm_update_dr6(vcpu);
a1efbe77 3395 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3396 kvm_update_dr7(vcpu);
a1efbe77 3397
a1efbe77
JK		 3398 return 0;
3399}
3400
df1daba7
PB		 3401#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3402
3403static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3404{
c47ada30 3405 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3406 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3407 u64 valid;
3408
3409 /*
3410 * Copy legacy XSAVE area, to avoid complications with CPUID
3411 * leaves 0 and 1 in the loop below.
3412 */
3413 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3414
3415 /* Set XSTATE_BV */
00c87e9a 3416 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3417 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3418
3419 /*
3420 * Copy each region from the possibly compacted offset to the
3421 * non-compacted offset.
3422 */
d91cab78 3423 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3424 while (valid) {
3425 u64 feature = valid & -valid;
3426 int index = fls64(feature) - 1;
3427 void *src = get_xsave_addr(xsave, feature);
3428
3429 if (src) {
3430 u32 size, offset, ecx, edx;
3431 cpuid_count(XSTATE_CPUID, index,
3432 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3433 if (feature == XFEATURE_MASK_PKRU)
3434 memcpy(dest + offset, &vcpu->arch.pkru,
3435 sizeof(vcpu->arch.pkru));
3436 else
3437 memcpy(dest + offset, src, size);
3438
df1daba7
PB		 3439 }
3440
3441 valid -= feature;
3442 }
3443}
3444
3445static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3446{
c47ada30 3447 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3448 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3449 u64 valid;
3450
3451 /*
3452 * Copy legacy XSAVE area, to avoid complications with CPUID
3453 * leaves 0 and 1 in the loop below.
3454 */
3455 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3456
3457 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3458 xsave->header.xfeatures = xstate_bv;
782511b0 3459 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3460 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3461
3462 /*
3463 * Copy each region from the non-compacted offset to the
3464 * possibly compacted offset.
3465 */
d91cab78 3466 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3467 while (valid) {
3468 u64 feature = valid & -valid;
3469 int index = fls64(feature) - 1;
3470 void *dest = get_xsave_addr(xsave, feature);
3471
3472 if (dest) {
3473 u32 size, offset, ecx, edx;
3474 cpuid_count(XSTATE_CPUID, index,
3475 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3476 if (feature == XFEATURE_MASK_PKRU)
3477 memcpy(&vcpu->arch.pkru, src + offset,
3478 sizeof(vcpu->arch.pkru));
3479 else
3480 memcpy(dest, src + offset, size);
ee4100da 3481 }
df1daba7
PB		 3482
3483 valid -= feature;
3484 }
3485}
3486
2d5b5a66
SY		 3487static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3488 struct kvm_xsave *guest_xsave)
3489{
d366bf7e 3490 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3491 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3492 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3493 } else {
2d5b5a66 3494 memcpy(guest_xsave->region,
7366ed77 3495 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3496 sizeof(struct fxregs_state));
2d5b5a66 3497 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3498 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3499 }
3500}
3501
a575813b
WL		 3502#define XSAVE_MXCSR_OFFSET 24
3503
2d5b5a66
SY		 3504static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3505 struct kvm_xsave *guest_xsave)
3506{
3507 u64 xstate_bv =
3508 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3509 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3510
d366bf7e 3511 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3512 /*
3513 * Here we allow setting states that are not present in
3514 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3515 * with old userspace.
3516 */
a575813b
WL		 3517 if (xstate_bv & ~kvm_supported_xcr0() ||
3518 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3519 return -EINVAL;
df1daba7 3520 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3521 } else {
a575813b
WL		 3522 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3523 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3524 return -EINVAL;
7366ed77 3525 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3526 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3527 }
3528 return 0;
3529}
3530
3531static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3532 struct kvm_xcrs *guest_xcrs)
3533{
d366bf7e 3534 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3535 guest_xcrs->nr_xcrs = 0;
3536 return;
3537 }
3538
3539 guest_xcrs->nr_xcrs = 1;
3540 guest_xcrs->flags = 0;
3541 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3542 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3543}
3544
3545static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3546 struct kvm_xcrs *guest_xcrs)
3547{
3548 int i, r = 0;
3549
d366bf7e 3550 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3551 return -EINVAL;
3552
3553 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3554 return -EINVAL;
3555
3556 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3557 /* Only support XCR0 currently */
c67a04cb 3558 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3559 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3560 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3561 break;
3562 }
3563 if (r)
3564 r = -EINVAL;
3565 return r;
3566}
3567
1c0b28c2
EM		 3568/*
3569 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3570 * stopped by the hypervisor. This function will be called from the host only.
3571 * EINVAL is returned when the host attempts to set the flag for a guest that
3572 * does not support pv clocks.
3573 */
3574static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3575{
0b79459b 3576 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3577 return -EINVAL;
51d59c6b 3578 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3579 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3580 return 0;
3581}
3582
5c919412
AS		 3583static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3584 struct kvm_enable_cap *cap)
3585{
3586 if (cap->flags)
3587 return -EINVAL;
3588
3589 switch (cap->cap) {
efc479e6
RK		 3590 case KVM_CAP_HYPERV_SYNIC2:
3591 if (cap->args[0])
3592 return -EINVAL;
5c919412 3593 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3594 if (!irqchip_in_kernel(vcpu->kvm))
3595 return -EINVAL;
efc479e6
RK		 3596 return kvm_hv_activate_synic(vcpu, cap->cap ==
3597 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3598 default:
3599 return -EINVAL;
3600 }
3601}
3602
313a3dc7
CO		 3603long kvm_arch_vcpu_ioctl(struct file *filp,
3604 unsigned int ioctl, unsigned long arg)
3605{
3606 struct kvm_vcpu *vcpu = filp->private_data;
3607 void __user *argp = (void __user *)arg;
3608 int r;
d1ac91d8
AK		 3609 union {
3610 struct kvm_lapic_state *lapic;
3611 struct kvm_xsave *xsave;
3612 struct kvm_xcrs *xcrs;
3613 void *buffer;
3614 } u;
3615
9b062471
CD		 3616 vcpu_load(vcpu);
3617
d1ac91d8 3618 u.buffer = NULL;
313a3dc7
CO		 3619 switch (ioctl) {
3620 case KVM_GET_LAPIC: {
2204ae3c 3621 r = -EINVAL;
bce87cce 3622 if (!lapic_in_kernel(vcpu))
2204ae3c 3623 goto out;
d1ac91d8 3624 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3625
b772ff36 3626 r = -ENOMEM;
d1ac91d8 3627 if (!u.lapic)
b772ff36 3628 goto out;
d1ac91d8 3629 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3630 if (r)
3631 goto out;
3632 r = -EFAULT;
d1ac91d8 3633 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3634 goto out;
3635 r = 0;
3636 break;
3637 }
3638 case KVM_SET_LAPIC: {
2204ae3c 3639 r = -EINVAL;
bce87cce 3640 if (!lapic_in_kernel(vcpu))
2204ae3c 3641 goto out;
ff5c2c03 3642 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3643 if (IS_ERR(u.lapic)) {
3644 r = PTR_ERR(u.lapic);
3645 goto out_nofree;
3646 }
ff5c2c03 3647
d1ac91d8 3648 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3649 break;
3650 }
f77bc6a4
ZX		 3651 case KVM_INTERRUPT: {
3652 struct kvm_interrupt irq;
3653
3654 r = -EFAULT;
3655 if (copy_from_user(&irq, argp, sizeof irq))
3656 goto out;
3657 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3658 break;
3659 }
c4abb7c9
JK		 3660 case KVM_NMI: {
3661 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3662 break;
3663 }
f077825a
PB		 3664 case KVM_SMI: {
3665 r = kvm_vcpu_ioctl_smi(vcpu);
3666 break;
3667 }
313a3dc7
CO		 3668 case KVM_SET_CPUID: {
3669 struct kvm_cpuid __user *cpuid_arg = argp;
3670 struct kvm_cpuid cpuid;
3671
3672 r = -EFAULT;
3673 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3674 goto out;
3675 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3676 break;
3677 }
07716717
DK		 3678 case KVM_SET_CPUID2: {
3679 struct kvm_cpuid2 __user *cpuid_arg = argp;
3680 struct kvm_cpuid2 cpuid;
3681
3682 r = -EFAULT;
3683 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3684 goto out;
3685 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3686 cpuid_arg->entries);
07716717
DK		 3687 break;
3688 }
3689 case KVM_GET_CPUID2: {
3690 struct kvm_cpuid2 __user *cpuid_arg = argp;
3691 struct kvm_cpuid2 cpuid;
3692
3693 r = -EFAULT;
3694 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3695 goto out;
3696 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3697 cpuid_arg->entries);
07716717
DK		 3698 if (r)
3699 goto out;
3700 r = -EFAULT;
3701 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3702 goto out;
3703 r = 0;
3704 break;
3705 }
801e459a
TL		 3706 case KVM_GET_MSRS: {
3707 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3708 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3709 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3710 break;
801e459a
TL		 3711 }
3712 case KVM_SET_MSRS: {
3713 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3714 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3715 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3716 break;
801e459a 3717 }
b209749f
AK		 3718 case KVM_TPR_ACCESS_REPORTING: {
3719 struct kvm_tpr_access_ctl tac;
3720
3721 r = -EFAULT;
3722 if (copy_from_user(&tac, argp, sizeof tac))
3723 goto out;
3724 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3725 if (r)
3726 goto out;
3727 r = -EFAULT;
3728 if (copy_to_user(argp, &tac, sizeof tac))
3729 goto out;
3730 r = 0;
3731 break;
3732 };
b93463aa
AK		 3733 case KVM_SET_VAPIC_ADDR: {
3734 struct kvm_vapic_addr va;
7301d6ab 3735 int idx;
b93463aa
AK		 3736
3737 r = -EINVAL;
35754c98 3738 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3739 goto out;
3740 r = -EFAULT;
3741 if (copy_from_user(&va, argp, sizeof va))
3742 goto out;
7301d6ab 3743 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3744 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3745 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3746 break;
3747 }
890ca9ae
HY		 3748 case KVM_X86_SETUP_MCE: {
3749 u64 mcg_cap;
3750
3751 r = -EFAULT;
3752 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3753 goto out;
3754 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3755 break;
3756 }
3757 case KVM_X86_SET_MCE: {
3758 struct kvm_x86_mce mce;
3759
3760 r = -EFAULT;
3761 if (copy_from_user(&mce, argp, sizeof mce))
3762 goto out;
3763 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3764 break;
3765 }
3cfc3092
JK		 3766 case KVM_GET_VCPU_EVENTS: {
3767 struct kvm_vcpu_events events;
3768
3769 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3770
3771 r = -EFAULT;
3772 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3773 break;
3774 r = 0;
3775 break;
3776 }
3777 case KVM_SET_VCPU_EVENTS: {
3778 struct kvm_vcpu_events events;
3779
3780 r = -EFAULT;
3781 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3782 break;
3783
3784 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3785 break;
3786 }
a1efbe77
JK		 3787 case KVM_GET_DEBUGREGS: {
3788 struct kvm_debugregs dbgregs;
3789
3790 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3791
3792 r = -EFAULT;
3793 if (copy_to_user(argp, &dbgregs,
3794 sizeof(struct kvm_debugregs)))
3795 break;
3796 r = 0;
3797 break;
3798 }
3799 case KVM_SET_DEBUGREGS: {
3800 struct kvm_debugregs dbgregs;
3801
3802 r = -EFAULT;
3803 if (copy_from_user(&dbgregs, argp,
3804 sizeof(struct kvm_debugregs)))
3805 break;
3806
3807 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3808 break;
3809 }
2d5b5a66 3810 case KVM_GET_XSAVE: {
d1ac91d8 3811 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3812 r = -ENOMEM;
d1ac91d8 3813 if (!u.xsave)
2d5b5a66
SY		 3814 break;
3815
d1ac91d8 3816 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3817
3818 r = -EFAULT;
d1ac91d8 3819 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3820 break;
3821 r = 0;
3822 break;
3823 }
3824 case KVM_SET_XSAVE: {
ff5c2c03 3825 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3826 if (IS_ERR(u.xsave)) {
3827 r = PTR_ERR(u.xsave);
3828 goto out_nofree;
3829 }
2d5b5a66 3830
d1ac91d8 3831 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3832 break;
3833 }
3834 case KVM_GET_XCRS: {
d1ac91d8 3835 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3836 r = -ENOMEM;
d1ac91d8 3837 if (!u.xcrs)
2d5b5a66
SY		 3838 break;
3839
d1ac91d8 3840 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3841
3842 r = -EFAULT;
d1ac91d8 3843 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3844 sizeof(struct kvm_xcrs)))
3845 break;
3846 r = 0;
3847 break;
3848 }
3849 case KVM_SET_XCRS: {
ff5c2c03 3850 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3851 if (IS_ERR(u.xcrs)) {
3852 r = PTR_ERR(u.xcrs);
3853 goto out_nofree;
3854 }
2d5b5a66 3855
d1ac91d8 3856 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3857 break;
3858 }
92a1f12d
JR		 3859 case KVM_SET_TSC_KHZ: {
3860 u32 user_tsc_khz;
3861
3862 r = -EINVAL;
92a1f12d
JR		 3863 user_tsc_khz = (u32)arg;
3864
3865 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3866 goto out;
3867
cc578287
ZA		 3868 if (user_tsc_khz == 0)
3869 user_tsc_khz = tsc_khz;
3870
381d585c
HZ		 3871 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3872 r = 0;
92a1f12d 3873
92a1f12d
JR		 3874 goto out;
3875 }
3876 case KVM_GET_TSC_KHZ: {
cc578287 3877 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3878 goto out;
3879 }
1c0b28c2
EM		 3880 case KVM_KVMCLOCK_CTRL: {
3881 r = kvm_set_guest_paused(vcpu);
3882 goto out;
3883 }
5c919412
AS		 3884 case KVM_ENABLE_CAP: {
3885 struct kvm_enable_cap cap;
3886
3887 r = -EFAULT;
3888 if (copy_from_user(&cap, argp, sizeof(cap)))
3889 goto out;
3890 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3891 break;
3892 }
313a3dc7
CO		 3893 default:
3894 r = -EINVAL;
3895 }
3896out:
d1ac91d8 3897 kfree(u.buffer);
9b062471
CD		 3898out_nofree:
3899 vcpu_put(vcpu);
313a3dc7
CO		 3900 return r;
3901}
3902
5b1c1493
CO		 3903int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3904{
3905 return VM_FAULT_SIGBUS;
3906}
3907
1fe779f8
CO		 3908static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3909{
3910 int ret;
3911
3912 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3913 return -EINVAL;
1fe779f8
CO		 3914 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3915 return ret;
3916}
3917
b927a3ce
SY		 3918static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3919 u64 ident_addr)
3920{
3921 kvm->arch.ept_identity_map_addr = ident_addr;
3922 return 0;
3923}
3924
1fe779f8
CO		 3925static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3926 u32 kvm_nr_mmu_pages)
3927{
3928 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3929 return -EINVAL;
3930
79fac95e 3931 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3932
3933 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3934 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3935
79fac95e 3936 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3937 return 0;
3938}
3939
3940static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3941{
39de71ec 3942 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3943}
3944
1fe779f8
CO		 3945static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3946{
90bca052 3947 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3948 int r;
3949
3950 r = 0;
3951 switch (chip->chip_id) {
3952 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3953 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3954 sizeof(struct kvm_pic_state));
3955 break;
3956 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3957 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3958 sizeof(struct kvm_pic_state));
3959 break;
3960 case KVM_IRQCHIP_IOAPIC:
33392b49 3961 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3962 break;
3963 default:
3964 r = -EINVAL;
3965 break;
3966 }
3967 return r;
3968}
3969
3970static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3971{
90bca052 3972 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3973 int r;
3974
3975 r = 0;
3976 switch (chip->chip_id) {
3977 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3978 spin_lock(&pic->lock);
3979 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3980 sizeof(struct kvm_pic_state));
90bca052 3981 spin_unlock(&pic->lock);
1fe779f8
CO		 3982 break;
3983 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3984 spin_lock(&pic->lock);
3985 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3986 sizeof(struct kvm_pic_state));
90bca052 3987 spin_unlock(&pic->lock);
1fe779f8
CO		 3988 break;
3989 case KVM_IRQCHIP_IOAPIC:
33392b49 3990 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3991 break;
3992 default:
3993 r = -EINVAL;
3994 break;
3995 }
90bca052 3996 kvm_pic_update_irq(pic);
1fe779f8
CO		 3997 return r;
3998}
3999
e0f63cb9
SY		 4000static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4001{
34f3941c
RK		 4002 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4003
4004 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4005
4006 mutex_lock(&kps->lock);
4007 memcpy(ps, &kps->channels, sizeof(*ps));
4008 mutex_unlock(&kps->lock);
2da29bcc 4009 return 0;
e0f63cb9
SY		 4010}
4011
4012static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4013{
0185604c 4014 int i;
09edea72
RK		 4015 struct kvm_pit *pit = kvm->arch.vpit;
4016
4017 mutex_lock(&pit->pit_state.lock);
34f3941c 4018 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4019 for (i = 0; i < 3; i++)
09edea72
RK		 4020 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4021 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4022 return 0;
e9f42757
BK		 4023}
4024
4025static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4026{
e9f42757
BK		 4027 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4028 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4029 sizeof(ps->channels));
4030 ps->flags = kvm->arch.vpit->pit_state.flags;
4031 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4032 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4033 return 0;
e9f42757
BK		 4034}
4035
4036static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4037{
2da29bcc 4038 int start = 0;
0185604c 4039 int i;
e9f42757 4040 u32 prev_legacy, cur_legacy;
09edea72
RK		 4041 struct kvm_pit *pit = kvm->arch.vpit;
4042
4043 mutex_lock(&pit->pit_state.lock);
4044 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4045 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4046 if (!prev_legacy && cur_legacy)
4047 start = 1;
09edea72
RK		 4048 memcpy(&pit->pit_state.channels, &ps->channels,
4049 sizeof(pit->pit_state.channels));
4050 pit->pit_state.flags = ps->flags;
0185604c 4051 for (i = 0; i < 3; i++)
09edea72 4052 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4053 start && i == 0);
09edea72 4054 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4055 return 0;
e0f63cb9
SY		 4056}
4057
52d939a0
MT		 4058static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4059 struct kvm_reinject_control *control)
4060{
71474e2f
RK		 4061 struct kvm_pit *pit = kvm->arch.vpit;
4062
4063 if (!pit)
52d939a0 4064 return -ENXIO;
b39c90b6 4065
71474e2f
RK		 4066 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4067 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4068 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4069 */
4070 mutex_lock(&pit->pit_state.lock);
4071 kvm_pit_set_reinject(pit, control->pit_reinject);
4072 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4073
52d939a0
MT		 4074 return 0;
4075}
4076
95d4c16c 4077/**
60c34612
TY		 4078 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4079 * @kvm: kvm instance
4080 * @log: slot id and address to which we copy the log
95d4c16c 4081 *
e108ff2f
PB		 4082 * Steps 1-4 below provide general overview of dirty page logging. See
4083 * kvm_get_dirty_log_protect() function description for additional details.
4084 *
4085 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4086 * always flush the TLB (step 4) even if previous step failed and the dirty
4087 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4088 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4089 * writes will be marked dirty for next log read.
95d4c16c 4090 *
60c34612
TY		 4091 * 1. Take a snapshot of the bit and clear it if needed.
4092 * 2. Write protect the corresponding page.
e108ff2f
PB		 4093 * 3. Copy the snapshot to the userspace.
4094 * 4. Flush TLB's if needed.
5bb064dc 4095 */
60c34612 4096int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4097{
60c34612 4098 bool is_dirty = false;
e108ff2f 4099 int r;
5bb064dc 4100
79fac95e 4101 mutex_lock(&kvm->slots_lock);
5bb064dc 4102
88178fd4
KH		 4103 /*
4104 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4105 */
4106 if (kvm_x86_ops->flush_log_dirty)
4107 kvm_x86_ops->flush_log_dirty(kvm);
4108
e108ff2f 4109 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4110
4111 /*
4112 * All the TLBs can be flushed out of mmu lock, see the comments in
4113 * kvm_mmu_slot_remove_write_access().
4114 */
e108ff2f 4115 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4116 if (is_dirty)
4117 kvm_flush_remote_tlbs(kvm);
4118
79fac95e 4119 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4120 return r;
4121}
4122
aa2fbe6d
YZ		 4123int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4124 bool line_status)
23d43cf9
CD		 4125{
4126 if (!irqchip_in_kernel(kvm))
4127 return -ENXIO;
4128
4129 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4130 irq_event->irq, irq_event->level,
4131 line_status);
23d43cf9
CD		 4132 return 0;
4133}
4134
90de4a18
NA		 4135static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4136 struct kvm_enable_cap *cap)
4137{
4138 int r;
4139
4140 if (cap->flags)
4141 return -EINVAL;
4142
4143 switch (cap->cap) {
4144 case KVM_CAP_DISABLE_QUIRKS:
4145 kvm->arch.disabled_quirks = cap->args[0];
4146 r = 0;
4147 break;
49df6397
SR		 4148 case KVM_CAP_SPLIT_IRQCHIP: {
4149 mutex_lock(&kvm->lock);
b053b2ae
SR		 4150 r = -EINVAL;
4151 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4152 goto split_irqchip_unlock;
49df6397
SR		 4153 r = -EEXIST;
4154 if (irqchip_in_kernel(kvm))
4155 goto split_irqchip_unlock;
557abc40 4156 if (kvm->created_vcpus)
49df6397
SR		 4157 goto split_irqchip_unlock;
4158 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4159 if (r)
49df6397
SR		 4160 goto split_irqchip_unlock;
4161 /* Pairs with irqchip_in_kernel. */
4162 smp_wmb();
49776faf 4163 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4164 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4165 r = 0;
4166split_irqchip_unlock:
4167 mutex_unlock(&kvm->lock);
4168 break;
4169 }
37131313
RK		 4170 case KVM_CAP_X2APIC_API:
4171 r = -EINVAL;
4172 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4173 break;
4174
4175 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4176 kvm->arch.x2apic_format = true;
c519265f
RK		 4177 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4178 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4179
4180 r = 0;
4181 break;
90de4a18
NA		 4182 default:
4183 r = -EINVAL;
4184 break;
4185 }
4186 return r;
4187}
4188
1fe779f8
CO		 4189long kvm_arch_vm_ioctl(struct file *filp,
4190 unsigned int ioctl, unsigned long arg)
4191{
4192 struct kvm *kvm = filp->private_data;
4193 void __user *argp = (void __user *)arg;
367e1319 4194 int r = -ENOTTY;
f0d66275
DH		 4195 /*
4196 * This union makes it completely explicit to gcc-3.x
4197 * that these two variables' stack usage should be
4198 * combined, not added together.
4199 */
4200 union {
4201 struct kvm_pit_state ps;
e9f42757 4202 struct kvm_pit_state2 ps2;
c5ff41ce 4203 struct kvm_pit_config pit_config;
f0d66275 4204 } u;
1fe779f8
CO		 4205
4206 switch (ioctl) {
4207 case KVM_SET_TSS_ADDR:
4208 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4209 break;
b927a3ce
SY		 4210 case KVM_SET_IDENTITY_MAP_ADDR: {
4211 u64 ident_addr;
4212
1af1ac91
DH		 4213 mutex_lock(&kvm->lock);
4214 r = -EINVAL;
4215 if (kvm->created_vcpus)
4216 goto set_identity_unlock;
b927a3ce
SY		 4217 r = -EFAULT;
4218 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4219 goto set_identity_unlock;
b927a3ce 4220 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4221set_identity_unlock:
4222 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4223 break;
4224 }
1fe779f8
CO		 4225 case KVM_SET_NR_MMU_PAGES:
4226 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4227 break;
4228 case KVM_GET_NR_MMU_PAGES:
4229 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4230 break;
3ddea128 4231 case KVM_CREATE_IRQCHIP: {
3ddea128 4232 mutex_lock(&kvm->lock);
09941366 4233
3ddea128 4234 r = -EEXIST;
35e6eaa3 4235 if (irqchip_in_kernel(kvm))
3ddea128 4236 goto create_irqchip_unlock;
09941366 4237
3e515705 4238 r = -EINVAL;
557abc40 4239 if (kvm->created_vcpus)
3e515705 4240 goto create_irqchip_unlock;
09941366
RK		 4241
4242 r = kvm_pic_init(kvm);
4243 if (r)
3ddea128 4244 goto create_irqchip_unlock;
09941366
RK		 4245
4246 r = kvm_ioapic_init(kvm);
4247 if (r) {
09941366 4248 kvm_pic_destroy(kvm);
3ddea128 4249 goto create_irqchip_unlock;
09941366
RK		 4250 }
4251
399ec807
AK		 4252 r = kvm_setup_default_irq_routing(kvm);
4253 if (r) {
72bb2fcd 4254 kvm_ioapic_destroy(kvm);
09941366 4255 kvm_pic_destroy(kvm);
71ba994c 4256 goto create_irqchip_unlock;
399ec807 4257 }
49776faf 4258 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4259 smp_wmb();
49776faf 4260 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4261 create_irqchip_unlock:
4262 mutex_unlock(&kvm->lock);
1fe779f8 4263 break;
3ddea128 4264 }
7837699f 4265 case KVM_CREATE_PIT:
c5ff41ce
JK		 4266 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4267 goto create_pit;
4268 case KVM_CREATE_PIT2:
4269 r = -EFAULT;
4270 if (copy_from_user(&u.pit_config, argp,
4271 sizeof(struct kvm_pit_config)))
4272 goto out;
4273 create_pit:
250715a6 4274 mutex_lock(&kvm->lock);
269e05e4
AK		 4275 r = -EEXIST;
4276 if (kvm->arch.vpit)
4277 goto create_pit_unlock;
7837699f 4278 r = -ENOMEM;
c5ff41ce 4279 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4280 if (kvm->arch.vpit)
4281 r = 0;
269e05e4 4282 create_pit_unlock:
250715a6 4283 mutex_unlock(&kvm->lock);
7837699f 4284 break;
1fe779f8
CO		 4285 case KVM_GET_IRQCHIP: {
4286 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4287 struct kvm_irqchip *chip;
1fe779f8 4288
ff5c2c03
SL		 4289 chip = memdup_user(argp, sizeof(*chip));
4290 if (IS_ERR(chip)) {
4291 r = PTR_ERR(chip);
1fe779f8 4292 goto out;
ff5c2c03
SL		 4293 }
4294
1fe779f8 4295 r = -ENXIO;
826da321 4296 if (!irqchip_kernel(kvm))
f0d66275
DH		 4297 goto get_irqchip_out;
4298 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4299 if (r)
f0d66275 4300 goto get_irqchip_out;
1fe779f8 4301 r = -EFAULT;
f0d66275
DH		 4302 if (copy_to_user(argp, chip, sizeof *chip))
4303 goto get_irqchip_out;
1fe779f8 4304 r = 0;
f0d66275
DH		 4305 get_irqchip_out:
4306 kfree(chip);
1fe779f8
CO		 4307 break;
4308 }
4309 case KVM_SET_IRQCHIP: {
4310 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4311 struct kvm_irqchip *chip;
1fe779f8 4312
ff5c2c03
SL		 4313 chip = memdup_user(argp, sizeof(*chip));
4314 if (IS_ERR(chip)) {
4315 r = PTR_ERR(chip);
1fe779f8 4316 goto out;
ff5c2c03
SL		 4317 }
4318
1fe779f8 4319 r = -ENXIO;
826da321 4320 if (!irqchip_kernel(kvm))
f0d66275
DH		 4321 goto set_irqchip_out;
4322 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4323 if (r)
f0d66275 4324 goto set_irqchip_out;
1fe779f8 4325 r = 0;
f0d66275
DH		 4326 set_irqchip_out:
4327 kfree(chip);
1fe779f8
CO		 4328 break;
4329 }
e0f63cb9 4330 case KVM_GET_PIT: {
e0f63cb9 4331 r = -EFAULT;
f0d66275 4332 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4333 goto out;
4334 r = -ENXIO;
4335 if (!kvm->arch.vpit)
4336 goto out;
f0d66275 4337 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4338 if (r)
4339 goto out;
4340 r = -EFAULT;
f0d66275 4341 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4342 goto out;
4343 r = 0;
4344 break;
4345 }
4346 case KVM_SET_PIT: {
e0f63cb9 4347 r = -EFAULT;
f0d66275 4348 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4349 goto out;
4350 r = -ENXIO;
4351 if (!kvm->arch.vpit)
4352 goto out;
f0d66275 4353 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4354 break;
4355 }
e9f42757
BK		 4356 case KVM_GET_PIT2: {
4357 r = -ENXIO;
4358 if (!kvm->arch.vpit)
4359 goto out;
4360 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4361 if (r)
4362 goto out;
4363 r = -EFAULT;
4364 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4365 goto out;
4366 r = 0;
4367 break;
4368 }
4369 case KVM_SET_PIT2: {
4370 r = -EFAULT;
4371 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4372 goto out;
4373 r = -ENXIO;
4374 if (!kvm->arch.vpit)
4375 goto out;
4376 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4377 break;
4378 }
52d939a0
MT		 4379 case KVM_REINJECT_CONTROL: {
4380 struct kvm_reinject_control control;
4381 r = -EFAULT;
4382 if (copy_from_user(&control, argp, sizeof(control)))
4383 goto out;
4384 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4385 break;
4386 }
d71ba788
PB		 4387 case KVM_SET_BOOT_CPU_ID:
4388 r = 0;
4389 mutex_lock(&kvm->lock);
557abc40 4390 if (kvm->created_vcpus)
d71ba788
PB		 4391 r = -EBUSY;
4392 else
4393 kvm->arch.bsp_vcpu_id = arg;
4394 mutex_unlock(&kvm->lock);
4395 break;
ffde22ac 4396 case KVM_XEN_HVM_CONFIG: {
51776043 4397 struct kvm_xen_hvm_config xhc;
ffde22ac 4398 r = -EFAULT;
51776043 4399 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4400 goto out;
4401 r = -EINVAL;
51776043 4402 if (xhc.flags)
ffde22ac 4403 goto out;
51776043 4404 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4405 r = 0;
4406 break;
4407 }
afbcf7ab 4408 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4409 struct kvm_clock_data user_ns;
4410 u64 now_ns;
afbcf7ab
GC		 4411
4412 r = -EFAULT;
4413 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4414 goto out;
4415
4416 r = -EINVAL;
4417 if (user_ns.flags)
4418 goto out;
4419
4420 r = 0;
0bc48bea
RK		 4421 /*
4422 * TODO: userspace has to take care of races with VCPU_RUN, so
4423 * kvm_gen_update_masterclock() can be cut down to locked
4424 * pvclock_update_vm_gtod_copy().
4425 */
4426 kvm_gen_update_masterclock(kvm);
e891a32e 4427 now_ns = get_kvmclock_ns(kvm);
108b249c 4428 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4429 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4430 break;
4431 }
4432 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4433 struct kvm_clock_data user_ns;
4434 u64 now_ns;
4435
e891a32e 4436 now_ns = get_kvmclock_ns(kvm);
108b249c 4437 user_ns.clock = now_ns;
e3fd9a93 4438 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4439 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4440
4441 r = -EFAULT;
4442 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4443 goto out;
4444 r = 0;
4445 break;
4446 }
90de4a18
NA		 4447 case KVM_ENABLE_CAP: {
4448 struct kvm_enable_cap cap;
afbcf7ab 4449
90de4a18
NA		 4450 r = -EFAULT;
4451 if (copy_from_user(&cap, argp, sizeof(cap)))
4452 goto out;
4453 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4454 break;
4455 }
5acc5c06
BS		 4456 case KVM_MEMORY_ENCRYPT_OP: {
4457 r = -ENOTTY;
4458 if (kvm_x86_ops->mem_enc_op)
4459 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4460 break;
4461 }
69eaedee
BS		 4462 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4463 struct kvm_enc_region region;
4464
4465 r = -EFAULT;
4466 if (copy_from_user(&region, argp, sizeof(region)))
4467 goto out;
4468
4469 r = -ENOTTY;
4470 if (kvm_x86_ops->mem_enc_reg_region)
4471 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4472 break;
4473 }
4474 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4475 struct kvm_enc_region region;
4476
4477 r = -EFAULT;
4478 if (copy_from_user(&region, argp, sizeof(region)))
4479 goto out;
4480
4481 r = -ENOTTY;
4482 if (kvm_x86_ops->mem_enc_unreg_region)
4483 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4484 break;
4485 }
faeb7833
RK		 4486 case KVM_HYPERV_EVENTFD: {
4487 struct kvm_hyperv_eventfd hvevfd;
4488
4489 r = -EFAULT;
4490 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4491 goto out;
4492 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4493 break;
4494 }
1fe779f8 4495 default:
ad6260da 4496 r = -ENOTTY;
1fe779f8
CO		 4497 }
4498out:
4499 return r;
4500}
4501
a16b043c 4502static void kvm_init_msr_list(void)
043405e1
CO		 4503{
4504 u32 dummy[2];
4505 unsigned i, j;
4506
62ef68bb 4507 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4508 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4509 continue;
93c4adc7
PB		 4510
4511 /*
4512 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4513 * to the guests in some cases.
93c4adc7
PB		 4514 */
4515 switch (msrs_to_save[i]) {
4516 case MSR_IA32_BNDCFGS:
4517 if (!kvm_x86_ops->mpx_supported())
4518 continue;
4519 break;
9dbe6cf9
PB		 4520 case MSR_TSC_AUX:
4521 if (!kvm_x86_ops->rdtscp_supported())
4522 continue;
4523 break;
93c4adc7
PB		 4524 default:
4525 break;
4526 }
4527
043405e1
CO		 4528 if (j < i)
4529 msrs_to_save[j] = msrs_to_save[i];
4530 j++;
4531 }
4532 num_msrs_to_save = j;
62ef68bb
PB		 4533
4534 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4535 switch (emulated_msrs[i]) {
6d396b55
PB		 4536 case MSR_IA32_SMBASE:
4537 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4538 continue;
4539 break;
62ef68bb
PB		 4540 default:
4541 break;
4542 }
4543
4544 if (j < i)
4545 emulated_msrs[j] = emulated_msrs[i];
4546 j++;
4547 }
4548 num_emulated_msrs = j;
801e459a
TL		 4549
4550 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4551 struct kvm_msr_entry msr;
4552
4553 msr.index = msr_based_features[i];
66421c1e 4554 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4555 continue;
4556
4557 if (j < i)
4558 msr_based_features[j] = msr_based_features[i];
4559 j++;
4560 }
4561 num_msr_based_features = j;
043405e1
CO		 4562}
4563
bda9020e
MT		 4564static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4565 const void *v)
bbd9b64e 4566{
70252a10
AK		 4567 int handled = 0;
4568 int n;
4569
4570 do {
4571 n = min(len, 8);
bce87cce 4572 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4573 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4574 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4575 break;
4576 handled += n;
4577 addr += n;
4578 len -= n;
4579 v += n;
4580 } while (len);
bbd9b64e 4581
70252a10 4582 return handled;
bbd9b64e
CO		 4583}
4584
bda9020e 4585static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4586{
70252a10
AK		 4587 int handled = 0;
4588 int n;
4589
4590 do {
4591 n = min(len, 8);
bce87cce 4592 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4593 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4594 addr, n, v))
4595 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4596 break;
e39d200f 4597 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4598 handled += n;
4599 addr += n;
4600 len -= n;
4601 v += n;
4602 } while (len);
bbd9b64e 4603
70252a10 4604 return handled;
bbd9b64e
CO		 4605}
4606
2dafc6c2
GN		 4607static void kvm_set_segment(struct kvm_vcpu *vcpu,
4608 struct kvm_segment *var, int seg)
4609{
4610 kvm_x86_ops->set_segment(vcpu, var, seg);
4611}
4612
4613void kvm_get_segment(struct kvm_vcpu *vcpu,
4614 struct kvm_segment *var, int seg)
4615{
4616 kvm_x86_ops->get_segment(vcpu, var, seg);
4617}
4618
54987b7a
PB		 4619gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4620 struct x86_exception *exception)
02f59dc9
JR		 4621{
4622 gpa_t t_gpa;
02f59dc9
JR		 4623
4624 BUG_ON(!mmu_is_nested(vcpu));
4625
4626 /* NPT walks are always user-walks */
4627 access |= PFERR_USER_MASK;
54987b7a 4628 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4629
4630 return t_gpa;
4631}
4632
ab9ae313
AK		 4633gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4634 struct x86_exception *exception)
1871c602
GN		 4635{
4636 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4637 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4638}
4639
ab9ae313
AK		 4640 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4641 struct x86_exception *exception)
1871c602
GN		 4642{
4643 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4644 access |= PFERR_FETCH_MASK;
ab9ae313 4645 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4646}
4647
ab9ae313
AK		 4648gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4649 struct x86_exception *exception)
1871c602
GN		 4650{
4651 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4652 access |= PFERR_WRITE_MASK;
ab9ae313 4653 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4654}
4655
4656/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4657gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4658 struct x86_exception *exception)
1871c602 4659{
ab9ae313 4660 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4661}
4662
4663static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4664 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4665 struct x86_exception *exception)
bbd9b64e
CO		 4666{
4667 void *data = val;
10589a46 4668 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4669
4670 while (bytes) {
14dfe855 4671 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4672 exception);
bbd9b64e 4673 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4674 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4675 int ret;
4676
bcc55cba 4677 if (gpa == UNMAPPED_GVA)
ab9ae313 4678 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4679 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4680 offset, toread);
10589a46 4681 if (ret < 0) {
c3cd7ffa 4682 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4683 goto out;
4684 }
bbd9b64e 4685
77c2002e
IE		 4686 bytes -= toread;
4687 data += toread;
4688 addr += toread;
bbd9b64e 4689 }
10589a46 4690out:
10589a46 4691 return r;
bbd9b64e 4692}
77c2002e 4693
1871c602 4694/* used for instruction fetching */
0f65dd70
AK		 4695static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4696 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4697 struct x86_exception *exception)
1871c602 4698{
0f65dd70 4699 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4700 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4701 unsigned offset;
4702 int ret;
0f65dd70 4703
44583cba
PB		 4704 /* Inline kvm_read_guest_virt_helper for speed. */
4705 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4706 exception);
4707 if (unlikely(gpa == UNMAPPED_GVA))
4708 return X86EMUL_PROPAGATE_FAULT;
4709
4710 offset = addr & (PAGE_SIZE-1);
4711 if (WARN_ON(offset + bytes > PAGE_SIZE))
4712 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4713 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4714 offset, bytes);
44583cba
PB		 4715 if (unlikely(ret < 0))
4716 return X86EMUL_IO_NEEDED;
4717
4718 return X86EMUL_CONTINUE;
1871c602
GN		 4719}
4720
064aea77 4721int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4722 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4723 struct x86_exception *exception)
1871c602 4724{
0f65dd70 4725 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4726 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4727
1871c602 4728 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4729 exception);
1871c602 4730}
064aea77 4731EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4732
0f65dd70
AK		 4733static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4734 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4735 struct x86_exception *exception)
1871c602 4736{
0f65dd70 4737 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4738 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4739}
4740
7a036a6f
RK		 4741static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4742 unsigned long addr, void *val, unsigned int bytes)
4743{
4744 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4745 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4746
4747 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4748}
4749
6a4d7550 4750int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4751 gva_t addr, void *val,
2dafc6c2 4752 unsigned int bytes,
bcc55cba 4753 struct x86_exception *exception)
77c2002e 4754{
0f65dd70 4755 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4756 void *data = val;
4757 int r = X86EMUL_CONTINUE;
4758
4759 while (bytes) {
14dfe855
JR		 4760 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4761 PFERR_WRITE_MASK,
ab9ae313 4762 exception);
77c2002e
IE		 4763 unsigned offset = addr & (PAGE_SIZE-1);
4764 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4765 int ret;
4766
bcc55cba 4767 if (gpa == UNMAPPED_GVA)
ab9ae313 4768 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4769 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4770 if (ret < 0) {
c3cd7ffa 4771 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4772 goto out;
4773 }
4774
4775 bytes -= towrite;
4776 data += towrite;
4777 addr += towrite;
4778 }
4779out:
4780 return r;
4781}
6a4d7550 4782EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4783
0f89b207
TL		 4784static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4785 gpa_t gpa, bool write)
4786{
4787 /* For APIC access vmexit */
4788 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4789 return 1;
4790
4791 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4792 trace_vcpu_match_mmio(gva, gpa, write, true);
4793 return 1;
4794 }
4795
4796 return 0;
4797}
4798
af7cc7d1
XG		 4799static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4800 gpa_t *gpa, struct x86_exception *exception,
4801 bool write)
4802{
97d64b78
AK		 4803 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4804 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4805
be94f6b7
HH		 4806 /*
4807 * currently PKRU is only applied to ept enabled guest so
4808 * there is no pkey in EPT page table for L1 guest or EPT
4809 * shadow page table for L2 guest.
4810 */
97d64b78 4811 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4812 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4813 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4814 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4815 (gva & (PAGE_SIZE - 1));
4f022648 4816 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4817 return 1;
4818 }
4819
af7cc7d1
XG		 4820 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4821
4822 if (*gpa == UNMAPPED_GVA)
4823 return -1;
4824
0f89b207 4825 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4826}
4827
3200f405 4828int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4829 const void *val, int bytes)
bbd9b64e
CO		 4830{
4831 int ret;
4832
54bf36aa 4833 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4834 if (ret < 0)
bbd9b64e 4835 return 0;
0eb05bf2 4836 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4837 return 1;
4838}
4839
77d197b2
XG		 4840struct read_write_emulator_ops {
4841 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4842 int bytes);
4843 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4844 void *val, int bytes);
4845 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4846 int bytes, void *val);
4847 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4848 void *val, int bytes);
4849 bool write;
4850};
4851
4852static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4853{
4854 if (vcpu->mmio_read_completed) {
77d197b2 4855 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4856 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4857 vcpu->mmio_read_completed = 0;
4858 return 1;
4859 }
4860
4861 return 0;
4862}
4863
4864static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4865 void *val, int bytes)
4866{
54bf36aa 4867 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4868}
4869
4870static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4871 void *val, int bytes)
4872{
4873 return emulator_write_phys(vcpu, gpa, val, bytes);
4874}
4875
4876static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4877{
e39d200f 4878 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4879 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4880}
4881
4882static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4883 void *val, int bytes)
4884{
e39d200f 4885 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4886 return X86EMUL_IO_NEEDED;
4887}
4888
4889static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4890 void *val, int bytes)
4891{
f78146b0
AK		 4892 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4893
87da7e66 4894 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4895 return X86EMUL_CONTINUE;
4896}
4897
0fbe9b0b 4898static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4899 .read_write_prepare = read_prepare,
4900 .read_write_emulate = read_emulate,
4901 .read_write_mmio = vcpu_mmio_read,
4902 .read_write_exit_mmio = read_exit_mmio,
4903};
4904
0fbe9b0b 4905static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4906 .read_write_emulate = write_emulate,
4907 .read_write_mmio = write_mmio,
4908 .read_write_exit_mmio = write_exit_mmio,
4909 .write = true,
4910};
4911
22388a3c
XG		 4912static int emulator_read_write_onepage(unsigned long addr, void *val,
4913 unsigned int bytes,
4914 struct x86_exception *exception,
4915 struct kvm_vcpu *vcpu,
0fbe9b0b 4916 const struct read_write_emulator_ops *ops)
bbd9b64e 4917{
af7cc7d1
XG		 4918 gpa_t gpa;
4919 int handled, ret;
22388a3c 4920 bool write = ops->write;
f78146b0 4921 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4922 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4923
4924 /*
4925 * If the exit was due to a NPF we may already have a GPA.
4926 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4927 * Note, this cannot be used on string operations since string
4928 * operation using rep will only have the initial GPA from the NPF
4929 * occurred.
4930 */
4931 if (vcpu->arch.gpa_available &&
4932 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4933 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4934 gpa = vcpu->arch.gpa_val;
4935 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4936 } else {
4937 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4938 if (ret < 0)
4939 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4940 }
10589a46 4941
618232e2 4942 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4943 return X86EMUL_CONTINUE;
4944
bbd9b64e
CO		 4945 /*
4946 * Is this MMIO handled locally?
4947 */
22388a3c 4948 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4949 if (handled == bytes)
bbd9b64e 4950 return X86EMUL_CONTINUE;
bbd9b64e 4951
70252a10
AK		 4952 gpa += handled;
4953 bytes -= handled;
4954 val += handled;
4955
87da7e66
XG		 4956 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4957 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4958 frag->gpa = gpa;
4959 frag->data = val;
4960 frag->len = bytes;
f78146b0 4961 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4962}
4963
52eb5a6d
XL		 4964static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4965 unsigned long addr,
22388a3c
XG		 4966 void *val, unsigned int bytes,
4967 struct x86_exception *exception,
0fbe9b0b 4968 const struct read_write_emulator_ops *ops)
bbd9b64e 4969{
0f65dd70 4970 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4971 gpa_t gpa;
4972 int rc;
4973
4974 if (ops->read_write_prepare &&
4975 ops->read_write_prepare(vcpu, val, bytes))
4976 return X86EMUL_CONTINUE;
4977
4978 vcpu->mmio_nr_fragments = 0;
0f65dd70 4979
bbd9b64e
CO		 4980 /* Crossing a page boundary? */
4981 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4982 int now;
bbd9b64e
CO		 4983
4984 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4985 rc = emulator_read_write_onepage(addr, val, now, exception,
4986 vcpu, ops);
4987
bbd9b64e
CO		 4988 if (rc != X86EMUL_CONTINUE)
4989 return rc;
4990 addr += now;
bac15531
NA		 4991 if (ctxt->mode != X86EMUL_MODE_PROT64)
4992 addr = (u32)addr;
bbd9b64e
CO		 4993 val += now;
4994 bytes -= now;
4995 }
22388a3c 4996
f78146b0
AK		 4997 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4998 vcpu, ops);
4999 if (rc != X86EMUL_CONTINUE)
5000 return rc;
5001
5002 if (!vcpu->mmio_nr_fragments)
5003 return rc;
5004
5005 gpa = vcpu->mmio_fragments[0].gpa;
5006
5007 vcpu->mmio_needed = 1;
5008 vcpu->mmio_cur_fragment = 0;
5009
87da7e66 5010 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5011 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5012 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5013 vcpu->run->mmio.phys_addr = gpa;
5014
5015 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5016}
5017
5018static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5019 unsigned long addr,
5020 void *val,
5021 unsigned int bytes,
5022 struct x86_exception *exception)
5023{
5024 return emulator_read_write(ctxt, addr, val, bytes,
5025 exception, &read_emultor);
5026}
5027
52eb5a6d 5028static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5029 unsigned long addr,
5030 const void *val,
5031 unsigned int bytes,
5032 struct x86_exception *exception)
5033{
5034 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5035 exception, &write_emultor);
bbd9b64e 5036}
bbd9b64e 5037
daea3e73
AK		 5038#define CMPXCHG_TYPE(t, ptr, old, new) \
5039 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5040
5041#ifdef CONFIG_X86_64
5042# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5043#else
5044# define CMPXCHG64(ptr, old, new) \
9749a6c0 5045 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5046#endif
5047
0f65dd70
AK		 5048static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5049 unsigned long addr,
bbd9b64e
CO		 5050 const void *old,
5051 const void *new,
5052 unsigned int bytes,
0f65dd70 5053 struct x86_exception *exception)
bbd9b64e 5054{
0f65dd70 5055 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5056 gpa_t gpa;
5057 struct page *page;
5058 char *kaddr;
5059 bool exchanged;
2bacc55c 5060
daea3e73
AK		 5061 /* guests cmpxchg8b have to be emulated atomically */
5062 if (bytes > 8 || (bytes & (bytes - 1)))
5063 goto emul_write;
10589a46 5064
daea3e73 5065 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5066
daea3e73
AK		 5067 if (gpa == UNMAPPED_GVA ||
5068 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5069 goto emul_write;
2bacc55c 5070
daea3e73
AK		 5071 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5072 goto emul_write;
72dc67a6 5073
54bf36aa 5074 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5075 if (is_error_page(page))
c19b8bd6 5076 goto emul_write;
72dc67a6 5077
8fd75e12 5078 kaddr = kmap_atomic(page);
daea3e73
AK		 5079 kaddr += offset_in_page(gpa);
5080 switch (bytes) {
5081 case 1:
5082 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5083 break;
5084 case 2:
5085 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5086 break;
5087 case 4:
5088 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5089 break;
5090 case 8:
5091 exchanged = CMPXCHG64(kaddr, old, new);
5092 break;
5093 default:
5094 BUG();
2bacc55c 5095 }
8fd75e12 5096 kunmap_atomic(kaddr);
daea3e73
AK		 5097 kvm_release_page_dirty(page);
5098
5099 if (!exchanged)
5100 return X86EMUL_CMPXCHG_FAILED;
5101
54bf36aa 5102 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5103 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5104
5105 return X86EMUL_CONTINUE;
4a5f48f6 5106
3200f405 5107emul_write:
daea3e73 5108 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5109
0f65dd70 5110 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5111}
5112
cf8f70bf
GN		 5113static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5114{
cbfc6c91 5115 int r = 0, i;
cf8f70bf 5116
cbfc6c91
WL		 5117 for (i = 0; i < vcpu->arch.pio.count; i++) {
5118 if (vcpu->arch.pio.in)
5119 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5120 vcpu->arch.pio.size, pd);
5121 else
5122 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5123 vcpu->arch.pio.port, vcpu->arch.pio.size,
5124 pd);
5125 if (r)
5126 break;
5127 pd += vcpu->arch.pio.size;
5128 }
cf8f70bf
GN		 5129 return r;
5130}
5131
6f6fbe98
XG		 5132static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5133 unsigned short port, void *val,
5134 unsigned int count, bool in)
cf8f70bf 5135{
cf8f70bf 5136 vcpu->arch.pio.port = port;
6f6fbe98 5137 vcpu->arch.pio.in = in;
7972995b 5138 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5139 vcpu->arch.pio.size = size;
5140
5141 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5142 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5143 return 1;
5144 }
5145
5146 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5147 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5148 vcpu->run->io.size = size;
5149 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5150 vcpu->run->io.count = count;
5151 vcpu->run->io.port = port;
5152
5153 return 0;
5154}
5155
6f6fbe98
XG		 5156static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5157 int size, unsigned short port, void *val,
5158 unsigned int count)
cf8f70bf 5159{
ca1d4a9e 5160 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5161 int ret;
ca1d4a9e 5162
6f6fbe98
XG		 5163 if (vcpu->arch.pio.count)
5164 goto data_avail;
cf8f70bf 5165
cbfc6c91
WL		 5166 memset(vcpu->arch.pio_data, 0, size * count);
5167
6f6fbe98
XG		 5168 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5169 if (ret) {
5170data_avail:
5171 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5172 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5173 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5174 return 1;
5175 }
5176
cf8f70bf
GN		 5177 return 0;
5178}
5179
6f6fbe98
XG		 5180static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5181 int size, unsigned short port,
5182 const void *val, unsigned int count)
5183{
5184 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5185
5186 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5187 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5188 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5189}
5190
bbd9b64e
CO		 5191static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5192{
5193 return kvm_x86_ops->get_segment_base(vcpu, seg);
5194}
5195
3cb16fe7 5196static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5197{
3cb16fe7 5198 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5199}
5200
ae6a2375 5201static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5202{
5203 if (!need_emulate_wbinvd(vcpu))
5204 return X86EMUL_CONTINUE;
5205
5206 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5207 int cpu = get_cpu();
5208
5209 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5210 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5211 wbinvd_ipi, NULL, 1);
2eec7343 5212 put_cpu();
f5f48ee1 5213 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5214 } else
5215 wbinvd();
f5f48ee1
SY		 5216 return X86EMUL_CONTINUE;
5217}
5cb56059
JS		 5218
5219int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5220{
6affcbed
KH		 5221 kvm_emulate_wbinvd_noskip(vcpu);
5222 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5223}
f5f48ee1
SY		 5224EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5225
5cb56059
JS		 5226
5227
bcaf5cc5
AK		 5228static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5229{
5cb56059 5230 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5231}
5232
52eb5a6d
XL		 5233static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5234 unsigned long *dest)
bbd9b64e 5235{
16f8a6f9 5236 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5237}
5238
52eb5a6d
XL		 5239static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5240 unsigned long value)
bbd9b64e 5241{
338dbc97 5242
717746e3 5243 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5244}
5245
52a46617 5246static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5247{
52a46617 5248 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5249}
5250
717746e3 5251static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5252{
717746e3 5253 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5254 unsigned long value;
5255
5256 switch (cr) {
5257 case 0:
5258 value = kvm_read_cr0(vcpu);
5259 break;
5260 case 2:
5261 value = vcpu->arch.cr2;
5262 break;
5263 case 3:
9f8fe504 5264 value = kvm_read_cr3(vcpu);
52a46617
GN		 5265 break;
5266 case 4:
5267 value = kvm_read_cr4(vcpu);
5268 break;
5269 case 8:
5270 value = kvm_get_cr8(vcpu);
5271 break;
5272 default:
a737f256 5273 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5274 return 0;
5275 }
5276
5277 return value;
5278}
5279
717746e3 5280static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5281{
717746e3 5282 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5283 int res = 0;
5284
52a46617
GN		 5285 switch (cr) {
5286 case 0:
49a9b07e 5287 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5288 break;
5289 case 2:
5290 vcpu->arch.cr2 = val;
5291 break;
5292 case 3:
2390218b 5293 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5294 break;
5295 case 4:
a83b29c6 5296 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5297 break;
5298 case 8:
eea1cff9 5299 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5300 break;
5301 default:
a737f256 5302 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5303 res = -1;
52a46617 5304 }
0f12244f
GN		 5305
5306 return res;
52a46617
GN		 5307}
5308
717746e3 5309static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5310{
717746e3 5311 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5312}
5313
4bff1e86 5314static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5315{
4bff1e86 5316 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5317}
5318
4bff1e86 5319static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5320{
4bff1e86 5321 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5322}
5323
1ac9d0cf
AK		 5324static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5325{
5326 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5327}
5328
5329static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5330{
5331 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5332}
5333
4bff1e86
AK		 5334static unsigned long emulator_get_cached_segment_base(
5335 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5336{
4bff1e86 5337 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5338}
5339
1aa36616
AK		 5340static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5341 struct desc_struct *desc, u32 *base3,
5342 int seg)
2dafc6c2
GN		 5343{
5344 struct kvm_segment var;
5345
4bff1e86 5346 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5347 *selector = var.selector;
2dafc6c2 5348
378a8b09
GN		 5349 if (var.unusable) {
5350 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5351 if (base3)
5352 *base3 = 0;
2dafc6c2 5353 return false;
378a8b09 5354 }
2dafc6c2
GN		 5355
5356 if (var.g)
5357 var.limit >>= 12;
5358 set_desc_limit(desc, var.limit);
5359 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5360#ifdef CONFIG_X86_64
5361 if (base3)
5362 *base3 = var.base >> 32;
5363#endif
2dafc6c2
GN		 5364 desc->type = var.type;
5365 desc->s = var.s;
5366 desc->dpl = var.dpl;
5367 desc->p = var.present;
5368 desc->avl = var.avl;
5369 desc->l = var.l;
5370 desc->d = var.db;
5371 desc->g = var.g;
5372
5373 return true;
5374}
5375
1aa36616
AK		 5376static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5377 struct desc_struct *desc, u32 base3,
5378 int seg)
2dafc6c2 5379{
4bff1e86 5380 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5381 struct kvm_segment var;
5382
1aa36616 5383 var.selector = selector;
2dafc6c2 5384 var.base = get_desc_base(desc);
5601d05b
GN		 5385#ifdef CONFIG_X86_64
5386 var.base |= ((u64)base3) << 32;
5387#endif
2dafc6c2
GN		 5388 var.limit = get_desc_limit(desc);
5389 if (desc->g)
5390 var.limit = (var.limit << 12) | 0xfff;
5391 var.type = desc->type;
2dafc6c2
GN		 5392 var.dpl = desc->dpl;
5393 var.db = desc->d;
5394 var.s = desc->s;
5395 var.l = desc->l;
5396 var.g = desc->g;
5397 var.avl = desc->avl;
5398 var.present = desc->p;
5399 var.unusable = !var.present;
5400 var.padding = 0;
5401
5402 kvm_set_segment(vcpu, &var, seg);
5403 return;
5404}
5405
717746e3
AK		 5406static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5407 u32 msr_index, u64 *pdata)
5408{
609e36d3
PB		 5409 struct msr_data msr;
5410 int r;
5411
5412 msr.index = msr_index;
5413 msr.host_initiated = false;
5414 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5415 if (r)
5416 return r;
5417
5418 *pdata = msr.data;
5419 return 0;
717746e3
AK		 5420}
5421
5422static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5423 u32 msr_index, u64 data)
5424{
8fe8ab46
WA		 5425 struct msr_data msr;
5426
5427 msr.data = data;
5428 msr.index = msr_index;
5429 msr.host_initiated = false;
5430 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5431}
5432
64d60670
PB		 5433static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5434{
5435 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5436
5437 return vcpu->arch.smbase;
5438}
5439
5440static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5441{
5442 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5443
5444 vcpu->arch.smbase = smbase;
5445}
5446
67f4d428
NA		 5447static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5448 u32 pmc)
5449{
c6702c9d 5450 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5451}
5452
222d21aa
AK		 5453static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5454 u32 pmc, u64 *pdata)
5455{
c6702c9d 5456 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5457}
5458
6c3287f7
AK		 5459static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5460{
5461 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5462}
5463
2953538e 5464static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5465 struct x86_instruction_info *info,
c4f035c6
AK		 5466 enum x86_intercept_stage stage)
5467{
2953538e 5468 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5469}
5470
e911eb3b
YZ		 5471static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5472 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5473{
e911eb3b 5474 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5475}
5476
dd856efa
AK		 5477static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5478{
5479 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5480}
5481
5482static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5483{
5484 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5485}
5486
801806d9
NA		 5487static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5488{
5489 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5490}
5491
6ed071f0
LP		 5492static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5493{
5494 return emul_to_vcpu(ctxt)->arch.hflags;
5495}
5496
5497static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5498{
5499 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5500}
5501
0234bf88
LP		 5502static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5503{
5504 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5505}
5506
0225fb50 5507static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5508 .read_gpr = emulator_read_gpr,
5509 .write_gpr = emulator_write_gpr,
1871c602 5510 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5511 .write_std = kvm_write_guest_virt_system,
7a036a6f 5512 .read_phys = kvm_read_guest_phys_system,
1871c602 5513 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5514 .read_emulated = emulator_read_emulated,
5515 .write_emulated = emulator_write_emulated,
5516 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5517 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5518 .pio_in_emulated = emulator_pio_in_emulated,
5519 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5520 .get_segment = emulator_get_segment,
5521 .set_segment = emulator_set_segment,
5951c442 5522 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5523 .get_gdt = emulator_get_gdt,
160ce1f1 5524 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5525 .set_gdt = emulator_set_gdt,
5526 .set_idt = emulator_set_idt,
52a46617
GN		 5527 .get_cr = emulator_get_cr,
5528 .set_cr = emulator_set_cr,
9c537244 5529 .cpl = emulator_get_cpl,
35aa5375
GN		 5530 .get_dr = emulator_get_dr,
5531 .set_dr = emulator_set_dr,
64d60670
PB		 5532 .get_smbase = emulator_get_smbase,
5533 .set_smbase = emulator_set_smbase,
717746e3
AK		 5534 .set_msr = emulator_set_msr,
5535 .get_msr = emulator_get_msr,
67f4d428 5536 .check_pmc = emulator_check_pmc,
222d21aa 5537 .read_pmc = emulator_read_pmc,
6c3287f7 5538 .halt = emulator_halt,
bcaf5cc5 5539 .wbinvd = emulator_wbinvd,
d6aa1000 5540 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5541 .intercept = emulator_intercept,
bdb42f5a 5542 .get_cpuid = emulator_get_cpuid,
801806d9 5543 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5544 .get_hflags = emulator_get_hflags,
5545 .set_hflags = emulator_set_hflags,
0234bf88 5546 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5547};
5548
95cb2295
GN		 5549static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5550{
37ccdcbe 5551 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5552 /*
5553 * an sti; sti; sequence only disable interrupts for the first
5554 * instruction. So, if the last instruction, be it emulated or
5555 * not, left the system with the INT_STI flag enabled, it
5556 * means that the last instruction is an sti. We should not
5557 * leave the flag on in this case. The same goes for mov ss
5558 */
37ccdcbe
PB		 5559 if (int_shadow & mask)
5560 mask = 0;
6addfc42 5561 if (unlikely(int_shadow || mask)) {
95cb2295 5562 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5563 if (!mask)
5564 kvm_make_request(KVM_REQ_EVENT, vcpu);
5565 }
95cb2295
GN		 5566}
5567
ef54bcfe 5568static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5569{
5570 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5571 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5572 return kvm_propagate_fault(vcpu, &ctxt->exception);
5573
5574 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5575 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5576 ctxt->exception.error_code);
54b8486f 5577 else
da9cb575 5578 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5579 return false;
54b8486f
GN		 5580}
5581
8ec4722d
MG		 5582static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5583{
adf52235 5584 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5585 int cs_db, cs_l;
5586
8ec4722d
MG		 5587 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5588
adf52235 5589 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5590 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5591
adf52235
TY		 5592 ctxt->eip = kvm_rip_read(vcpu);
5593 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5594 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5595 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5596 cs_db ? X86EMUL_MODE_PROT32 :
5597 X86EMUL_MODE_PROT16;
a584539b 5598 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5599 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5600 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5601
dd856efa 5602 init_decode_cache(ctxt);
7ae441ea 5603 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5604}
5605
71f9833b 5606int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5607{
9d74191a 5608 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5609 int ret;
5610
5611 init_emulate_ctxt(vcpu);
5612
9dac77fa
AK		 5613 ctxt->op_bytes = 2;
5614 ctxt->ad_bytes = 2;
5615 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5616 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5617
5618 if (ret != X86EMUL_CONTINUE)
5619 return EMULATE_FAIL;
5620
9dac77fa 5621 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5622 kvm_rip_write(vcpu, ctxt->eip);
5623 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5624
5625 if (irq == NMI_VECTOR)
7460fb4a 5626 vcpu->arch.nmi_pending = 0;
63995653
MG		 5627 else
5628 vcpu->arch.interrupt.pending = false;
5629
5630 return EMULATE_DONE;
5631}
5632EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5633
6d77dbfc
GN		 5634static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5635{
fc3a9157
JR		 5636 int r = EMULATE_DONE;
5637
6d77dbfc
GN		 5638 ++vcpu->stat.insn_emulation_fail;
5639 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5640 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5641 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5642 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5643 vcpu->run->internal.ndata = 0;
1f4dcb3b 5644 r = EMULATE_USER_EXIT;
fc3a9157 5645 }
6d77dbfc 5646 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5647
5648 return r;
6d77dbfc
GN		 5649}
5650
93c05d3e 5651static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5652 bool write_fault_to_shadow_pgtable,
5653 int emulation_type)
a6f177ef 5654{
95b3cf69 5655 gpa_t gpa = cr2;
ba049e93 5656 kvm_pfn_t pfn;
a6f177ef 5657
991eebf9
GN		 5658 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5659 return false;
5660
95b3cf69
XG		 5661 if (!vcpu->arch.mmu.direct_map) {
5662 /*
5663 * Write permission should be allowed since only
5664 * write access need to be emulated.
5665 */
5666 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5667
95b3cf69
XG		 5668 /*
5669 * If the mapping is invalid in guest, let cpu retry
5670 * it to generate fault.
5671 */
5672 if (gpa == UNMAPPED_GVA)
5673 return true;
5674 }
a6f177ef 5675
8e3d9d06
XG		 5676 /*
5677 * Do not retry the unhandleable instruction if it faults on the
5678 * readonly host memory, otherwise it will goto a infinite loop:
5679 * retry instruction -> write #PF -> emulation fail -> retry
5680 * instruction -> ...
5681 */
5682 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5683
5684 /*
5685 * If the instruction failed on the error pfn, it can not be fixed,
5686 * report the error to userspace.
5687 */
5688 if (is_error_noslot_pfn(pfn))
5689 return false;
5690
5691 kvm_release_pfn_clean(pfn);
5692
5693 /* The instructions are well-emulated on direct mmu. */
5694 if (vcpu->arch.mmu.direct_map) {
5695 unsigned int indirect_shadow_pages;
5696
5697 spin_lock(&vcpu->kvm->mmu_lock);
5698 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5699 spin_unlock(&vcpu->kvm->mmu_lock);
5700
5701 if (indirect_shadow_pages)
5702 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5703
a6f177ef 5704 return true;
8e3d9d06 5705 }
a6f177ef 5706
95b3cf69
XG		 5707 /*
5708 * if emulation was due to access to shadowed page table
5709 * and it failed try to unshadow page and re-enter the
5710 * guest to let CPU execute the instruction.
5711 */
5712 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5713
5714 /*
5715 * If the access faults on its page table, it can not
5716 * be fixed by unprotecting shadow page and it should
5717 * be reported to userspace.
5718 */
5719 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5720}
5721
1cb3f3ae
XG		 5722static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5723 unsigned long cr2, int emulation_type)
5724{
5725 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5726 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5727
5728 last_retry_eip = vcpu->arch.last_retry_eip;
5729 last_retry_addr = vcpu->arch.last_retry_addr;
5730
5731 /*
5732 * If the emulation is caused by #PF and it is non-page_table
5733 * writing instruction, it means the VM-EXIT is caused by shadow
5734 * page protected, we can zap the shadow page and retry this
5735 * instruction directly.
5736 *
5737 * Note: if the guest uses a non-page-table modifying instruction
5738 * on the PDE that points to the instruction, then we will unmap
5739 * the instruction and go to an infinite loop. So, we cache the
5740 * last retried eip and the last fault address, if we meet the eip
5741 * and the address again, we can break out of the potential infinite
5742 * loop.
5743 */
5744 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5745
5746 if (!(emulation_type & EMULTYPE_RETRY))
5747 return false;
5748
5749 if (x86_page_table_writing_insn(ctxt))
5750 return false;
5751
5752 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5753 return false;
5754
5755 vcpu->arch.last_retry_eip = ctxt->eip;
5756 vcpu->arch.last_retry_addr = cr2;
5757
5758 if (!vcpu->arch.mmu.direct_map)
5759 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5760
22368028 5761 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5762
5763 return true;
5764}
5765
716d51ab
GN		 5766static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5767static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5768
64d60670 5769static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5770{
64d60670 5771 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5772 /* This is a good place to trace that we are exiting SMM. */
5773 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5774
c43203ca
PB		 5775 /* Process a latched INIT or SMI, if any. */
5776 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5777 }
699023e2
PB		 5778
5779 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5780}
5781
5782static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5783{
5784 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5785
a584539b 5786 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5787
5788 if (changed & HF_SMM_MASK)
5789 kvm_smm_changed(vcpu);
a584539b
PB		 5790}
5791
4a1e10d5
PB		 5792static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5793 unsigned long *db)
5794{
5795 u32 dr6 = 0;
5796 int i;
5797 u32 enable, rwlen;
5798
5799 enable = dr7;
5800 rwlen = dr7 >> 16;
5801 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5802 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5803 dr6 |= (1 << i);
5804 return dr6;
5805}
5806
c8401dda 5807static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5808{
5809 struct kvm_run *kvm_run = vcpu->run;
5810
c8401dda
PB		 5811 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5812 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5813 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5814 kvm_run->debug.arch.exception = DB_VECTOR;
5815 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5816 *r = EMULATE_USER_EXIT;
5817 } else {
5818 /*
5819 * "Certain debug exceptions may clear bit 0-3. The
5820 * remaining contents of the DR6 register are never
5821 * cleared by the processor".
5822 */
5823 vcpu->arch.dr6 &= ~15;
5824 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5825 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5826 }
5827}
5828
6affcbed
KH		 5829int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5830{
5831 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5832 int r = EMULATE_DONE;
5833
5834 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5835
5836 /*
5837 * rflags is the old, "raw" value of the flags. The new value has
5838 * not been saved yet.
5839 *
5840 * This is correct even for TF set by the guest, because "the
5841 * processor will not generate this exception after the instruction
5842 * that sets the TF flag".
5843 */
5844 if (unlikely(rflags & X86_EFLAGS_TF))
5845 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5846 return r == EMULATE_DONE;
5847}
5848EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5849
4a1e10d5
PB		 5850static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5851{
4a1e10d5
PB		 5852 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5853 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5854 struct kvm_run *kvm_run = vcpu->run;
5855 unsigned long eip = kvm_get_linear_rip(vcpu);
5856 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5857 vcpu->arch.guest_debug_dr7,
5858 vcpu->arch.eff_db);
5859
5860 if (dr6 != 0) {
6f43ed01 5861 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5862 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5863 kvm_run->debug.arch.exception = DB_VECTOR;
5864 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5865 *r = EMULATE_USER_EXIT;
5866 return true;
5867 }
5868 }
5869
4161a569
NA		 5870 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5871 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5872 unsigned long eip = kvm_get_linear_rip(vcpu);
5873 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5874 vcpu->arch.dr7,
5875 vcpu->arch.db);
5876
5877 if (dr6 != 0) {
5878 vcpu->arch.dr6 &= ~15;
6f43ed01 5879 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5880 kvm_queue_exception(vcpu, DB_VECTOR);
5881 *r = EMULATE_DONE;
5882 return true;
5883 }
5884 }
5885
5886 return false;
5887}
5888
51d8b661
AP		 5889int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5890 unsigned long cr2,
dc25e89e
AP		 5891 int emulation_type,
5892 void *insn,
5893 int insn_len)
bbd9b64e 5894{
95cb2295 5895 int r;
9d74191a 5896 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5897 bool writeback = true;
93c05d3e 5898 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5899
93c05d3e
XG		 5900 /*
5901 * Clear write_fault_to_shadow_pgtable here to ensure it is
5902 * never reused.
5903 */
5904 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5905 kvm_clear_exception_queue(vcpu);
8d7d8102 5906
571008da 5907 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5908 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5909
5910 /*
5911 * We will reenter on the same instruction since
5912 * we do not set complete_userspace_io. This does not
5913 * handle watchpoints yet, those would be handled in
5914 * the emulate_ops.
5915 */
d391f120
VK		 5916 if (!(emulation_type & EMULTYPE_SKIP) &&
5917 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 5918 return r;
5919
9d74191a
TY		 5920 ctxt->interruptibility = 0;
5921 ctxt->have_exception = false;
e0ad0b47 5922 ctxt->exception.vector = -1;
9d74191a 5923 ctxt->perm_ok = false;
bbd9b64e 5924
b51e974f 5925 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5926
9d74191a 5927 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5928
e46479f8 5929 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5930 ++vcpu->stat.insn_emulation;
1d2887e2 5931 if (r != EMULATION_OK) {
4005996e
AK		 5932 if (emulation_type & EMULTYPE_TRAP_UD)
5933 return EMULATE_FAIL;
991eebf9
GN		 5934 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5935 emulation_type))
bbd9b64e 5936 return EMULATE_DONE;
6ea6e843
PB		 5937 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5938 return EMULATE_DONE;
6d77dbfc
GN		 5939 if (emulation_type & EMULTYPE_SKIP)
5940 return EMULATE_FAIL;
5941 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5942 }
5943 }
5944
ba8afb6b 5945 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5946 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5947 if (ctxt->eflags & X86_EFLAGS_RF)
5948 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5949 return EMULATE_DONE;
5950 }
5951
1cb3f3ae
XG		 5952 if (retry_instruction(ctxt, cr2, emulation_type))
5953 return EMULATE_DONE;
5954
7ae441ea 5955 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5956 changes registers values during IO operation */
7ae441ea
GN		 5957 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5958 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5959 emulator_invalidate_register_cache(ctxt);
7ae441ea 5960 }
4d2179e1 5961
5cd21917 5962restart:
0f89b207
TL		 5963 /* Save the faulting GPA (cr2) in the address field */
5964 ctxt->exception.address = cr2;
5965
9d74191a 5966 r = x86_emulate_insn(ctxt);
bbd9b64e 5967
775fde86
JR		 5968 if (r == EMULATION_INTERCEPTED)
5969 return EMULATE_DONE;
5970
d2ddd1c4 5971 if (r == EMULATION_FAILED) {
991eebf9
GN		 5972 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5973 emulation_type))
c3cd7ffa
GN		 5974 return EMULATE_DONE;
5975
6d77dbfc 5976 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5977 }
5978
9d74191a 5979 if (ctxt->have_exception) {
d2ddd1c4 5980 r = EMULATE_DONE;
ef54bcfe
PB		 5981 if (inject_emulated_exception(vcpu))
5982 return r;
d2ddd1c4 5983 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5984 if (!vcpu->arch.pio.in) {
5985 /* FIXME: return into emulator if single-stepping. */
3457e419 5986 vcpu->arch.pio.count = 0;
0912c977 5987 } else {
7ae441ea 5988 writeback = false;
716d51ab
GN		 5989 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5990 }
ac0a48c3 5991 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5992 } else if (vcpu->mmio_needed) {
5993 if (!vcpu->mmio_is_write)
5994 writeback = false;
ac0a48c3 5995 r = EMULATE_USER_EXIT;
716d51ab 5996 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5997 } else if (r == EMULATION_RESTART)
5cd21917 5998 goto restart;
d2ddd1c4
GN		 5999 else
6000 r = EMULATE_DONE;
f850e2e6 6001
7ae441ea 6002 if (writeback) {
6addfc42 6003 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6004 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6005 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6006 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6007 if (r == EMULATE_DONE &&
6008 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6009 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6010 if (!ctxt->have_exception ||
6011 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6012 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6013
6014 /*
6015 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6016 * do nothing, and it will be requested again as soon as
6017 * the shadow expires. But we still need to check here,
6018 * because POPF has no interrupt shadow.
6019 */
6020 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6021 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6022 } else
6023 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6024
6025 return r;
de7d789a 6026}
51d8b661 6027EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6028
cf8f70bf 6029int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 6030{
cf8f70bf 6031 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6032 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6033 size, port, &val, 1);
cf8f70bf 6034 /* do not return to emulator after return from userspace */
7972995b 6035 vcpu->arch.pio.count = 0;
de7d789a
CO		 6036 return ret;
6037}
cf8f70bf 6038EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 6039
8370c3d0
TL		 6040static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6041{
6042 unsigned long val;
6043
6044 /* We should only ever be called with arch.pio.count equal to 1 */
6045 BUG_ON(vcpu->arch.pio.count != 1);
6046
6047 /* For size less than 4 we merge, else we zero extend */
6048 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6049 : 0;
6050
6051 /*
6052 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6053 * the copy and tracing
6054 */
6055 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6056 vcpu->arch.pio.port, &val, 1);
6057 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6058
6059 return 1;
6060}
6061
6062int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
6063{
6064 unsigned long val;
6065 int ret;
6066
6067 /* For size less than 4 we merge, else we zero extend */
6068 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6069
6070 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6071 &val, 1);
6072 if (ret) {
6073 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6074 return ret;
6075 }
6076
6077 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6078
6079 return 0;
6080}
6081EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
6082
251a5fd6 6083static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6084{
0a3aee0d 6085 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6086 return 0;
8cfdc000
ZA		 6087}
6088
6089static void tsc_khz_changed(void *data)
c8076604 6090{
8cfdc000
ZA		 6091 struct cpufreq_freqs *freq = data;
6092 unsigned long khz = 0;
6093
6094 if (data)
6095 khz = freq->new;
6096 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6097 khz = cpufreq_quick_get(raw_smp_processor_id());
6098 if (!khz)
6099 khz = tsc_khz;
0a3aee0d 6100 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6101}
6102
5fa4ec9c 6103#ifdef CONFIG_X86_64
0092e434
VK		 6104static void kvm_hyperv_tsc_notifier(void)
6105{
0092e434
VK		 6106 struct kvm *kvm;
6107 struct kvm_vcpu *vcpu;
6108 int cpu;
6109
6110 spin_lock(&kvm_lock);
6111 list_for_each_entry(kvm, &vm_list, vm_list)
6112 kvm_make_mclock_inprogress_request(kvm);
6113
6114 hyperv_stop_tsc_emulation();
6115
6116 /* TSC frequency always matches when on Hyper-V */
6117 for_each_present_cpu(cpu)
6118 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6119 kvm_max_guest_tsc_khz = tsc_khz;
6120
6121 list_for_each_entry(kvm, &vm_list, vm_list) {
6122 struct kvm_arch *ka = &kvm->arch;
6123
6124 spin_lock(&ka->pvclock_gtod_sync_lock);
6125
6126 pvclock_update_vm_gtod_copy(kvm);
6127
6128 kvm_for_each_vcpu(cpu, vcpu, kvm)
6129 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6130
6131 kvm_for_each_vcpu(cpu, vcpu, kvm)
6132 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6133
6134 spin_unlock(&ka->pvclock_gtod_sync_lock);
6135 }
6136 spin_unlock(&kvm_lock);
0092e434 6137}
5fa4ec9c 6138#endif
0092e434 6139
c8076604
GH		 6140static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6141 void *data)
6142{
6143 struct cpufreq_freqs *freq = data;
6144 struct kvm *kvm;
6145 struct kvm_vcpu *vcpu;
6146 int i, send_ipi = 0;
6147
8cfdc000
ZA		 6148 /*
6149 * We allow guests to temporarily run on slowing clocks,
6150 * provided we notify them after, or to run on accelerating
6151 * clocks, provided we notify them before. Thus time never
6152 * goes backwards.
6153 *
6154 * However, we have a problem. We can't atomically update
6155 * the frequency of a given CPU from this function; it is
6156 * merely a notifier, which can be called from any CPU.
6157 * Changing the TSC frequency at arbitrary points in time
6158 * requires a recomputation of local variables related to
6159 * the TSC for each VCPU. We must flag these local variables
6160 * to be updated and be sure the update takes place with the
6161 * new frequency before any guests proceed.
6162 *
6163 * Unfortunately, the combination of hotplug CPU and frequency
6164 * change creates an intractable locking scenario; the order
6165 * of when these callouts happen is undefined with respect to
6166 * CPU hotplug, and they can race with each other. As such,
6167 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6168 * undefined; you can actually have a CPU frequency change take
6169 * place in between the computation of X and the setting of the
6170 * variable. To protect against this problem, all updates of
6171 * the per_cpu tsc_khz variable are done in an interrupt
6172 * protected IPI, and all callers wishing to update the value
6173 * must wait for a synchronous IPI to complete (which is trivial
6174 * if the caller is on the CPU already). This establishes the
6175 * necessary total order on variable updates.
6176 *
6177 * Note that because a guest time update may take place
6178 * anytime after the setting of the VCPU's request bit, the
6179 * correct TSC value must be set before the request. However,
6180 * to ensure the update actually makes it to any guest which
6181 * starts running in hardware virtualization between the set
6182 * and the acquisition of the spinlock, we must also ping the
6183 * CPU after setting the request bit.
6184 *
6185 */
6186
c8076604
GH		 6187 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6188 return 0;
6189 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6190 return 0;
8cfdc000
ZA		 6191
6192 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6193
2f303b74 6194 spin_lock(&kvm_lock);
c8076604 6195 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6196 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6197 if (vcpu->cpu != freq->cpu)
6198 continue;
c285545f 6199 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6200 if (vcpu->cpu != smp_processor_id())
8cfdc000 6201 send_ipi = 1;
c8076604
GH		 6202 }
6203 }
2f303b74 6204 spin_unlock(&kvm_lock);
c8076604
GH		 6205
6206 if (freq->old < freq->new && send_ipi) {
6207 /*
6208 * We upscale the frequency. Must make the guest
6209 * doesn't see old kvmclock values while running with
6210 * the new frequency, otherwise we risk the guest sees
6211 * time go backwards.
6212 *
6213 * In case we update the frequency for another cpu
6214 * (which might be in guest context) send an interrupt
6215 * to kick the cpu out of guest context. Next time
6216 * guest context is entered kvmclock will be updated,
6217 * so the guest will not see stale values.
6218 */
8cfdc000 6219 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6220 }
6221 return 0;
6222}
6223
6224static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6225 .notifier_call = kvmclock_cpufreq_notifier
6226};
6227
251a5fd6 6228static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6229{
251a5fd6
SAS		 6230 tsc_khz_changed(NULL);
6231 return 0;
8cfdc000
ZA		 6232}
6233
b820cc0c
ZA		 6234static void kvm_timer_init(void)
6235{
c285545f 6236 max_tsc_khz = tsc_khz;
460dd42e 6237
b820cc0c 6238 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6239#ifdef CONFIG_CPU_FREQ
6240 struct cpufreq_policy policy;
758f588d
BP		 6241 int cpu;
6242
c285545f 6243 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6244 cpu = get_cpu();
6245 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6246 if (policy.cpuinfo.max_freq)
6247 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6248 put_cpu();
c285545f 6249#endif
b820cc0c
ZA		 6250 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6251 CPUFREQ_TRANSITION_NOTIFIER);
6252 }
c285545f 6253 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6254
73c1b41e 6255 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6256 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6257}
6258
ff9d07a0
ZY		 6259static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6260
f5132b01 6261int kvm_is_in_guest(void)
ff9d07a0 6262{
086c9855 6263 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6264}
6265
6266static int kvm_is_user_mode(void)
6267{
6268 int user_mode = 3;
dcf46b94 6269
086c9855
AS		 6270 if (__this_cpu_read(current_vcpu))
6271 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6272
ff9d07a0
ZY		 6273 return user_mode != 0;
6274}
6275
6276static unsigned long kvm_get_guest_ip(void)
6277{
6278 unsigned long ip = 0;
dcf46b94 6279
086c9855
AS		 6280 if (__this_cpu_read(current_vcpu))
6281 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6282
ff9d07a0
ZY		 6283 return ip;
6284}
6285
6286static struct perf_guest_info_callbacks kvm_guest_cbs = {
6287 .is_in_guest = kvm_is_in_guest,
6288 .is_user_mode = kvm_is_user_mode,
6289 .get_guest_ip = kvm_get_guest_ip,
6290};
6291
6292void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6293{
086c9855 6294 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6295}
6296EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6297
6298void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6299{
086c9855 6300 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6301}
6302EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6303
ce88decf
XG		 6304static void kvm_set_mmio_spte_mask(void)
6305{
6306 u64 mask;
6307 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6308
6309 /*
6310 * Set the reserved bits and the present bit of an paging-structure
6311 * entry to generate page fault with PFER.RSV = 1.
6312 */
885032b9 6313 /* Mask the reserved physical address bits. */
d1431483 6314 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6315
885032b9 6316 /* Set the present bit. */
ce88decf
XG		 6317 mask |= 1ull;
6318
6319#ifdef CONFIG_X86_64
6320 /*
6321 * If reserved bit is not supported, clear the present bit to disable
6322 * mmio page fault.
6323 */
6324 if (maxphyaddr == 52)
6325 mask &= ~1ull;
6326#endif
6327
dcdca5fe 6328 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6329}
6330
16e8d74d
MT		 6331#ifdef CONFIG_X86_64
6332static void pvclock_gtod_update_fn(struct work_struct *work)
6333{
d828199e
MT		 6334 struct kvm *kvm;
6335
6336 struct kvm_vcpu *vcpu;
6337 int i;
6338
2f303b74 6339 spin_lock(&kvm_lock);
d828199e
MT		 6340 list_for_each_entry(kvm, &vm_list, vm_list)
6341 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6342 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6343 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6344 spin_unlock(&kvm_lock);
16e8d74d
MT		 6345}
6346
6347static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6348
6349/*
6350 * Notification about pvclock gtod data update.
6351 */
6352static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6353 void *priv)
6354{
6355 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6356 struct timekeeper *tk = priv;
6357
6358 update_pvclock_gtod(tk);
6359
6360 /* disable master clock if host does not trust, or does not
b0c39dc6 6361 * use, TSC based clocksource.
16e8d74d 6362 */
b0c39dc6 6363 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6364 atomic_read(&kvm_guest_has_master_clock) != 0)
6365 queue_work(system_long_wq, &pvclock_gtod_work);
6366
6367 return 0;
6368}
6369
6370static struct notifier_block pvclock_gtod_notifier = {
6371 .notifier_call = pvclock_gtod_notify,
6372};
6373#endif
6374
f8c16bba 6375int kvm_arch_init(void *opaque)
043405e1 6376{
b820cc0c 6377 int r;
6b61edf7 6378 struct kvm_x86_ops *ops = opaque;
f8c16bba 6379
f8c16bba
ZX		 6380 if (kvm_x86_ops) {
6381 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6382 r = -EEXIST;
6383 goto out;
f8c16bba
ZX		 6384 }
6385
6386 if (!ops->cpu_has_kvm_support()) {
6387 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6388 r = -EOPNOTSUPP;
6389 goto out;
f8c16bba
ZX		 6390 }
6391 if (ops->disabled_by_bios()) {
6392 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6393 r = -EOPNOTSUPP;
6394 goto out;
f8c16bba
ZX		 6395 }
6396
013f6a5d
MT		 6397 r = -ENOMEM;
6398 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6399 if (!shared_msrs) {
6400 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6401 goto out;
6402 }
6403
97db56ce
AK		 6404 r = kvm_mmu_module_init();
6405 if (r)
013f6a5d 6406 goto out_free_percpu;
97db56ce 6407
ce88decf 6408 kvm_set_mmio_spte_mask();
97db56ce 6409
f8c16bba 6410 kvm_x86_ops = ops;
920c8377 6411
7b52345e 6412 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6413 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6414 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6415 kvm_timer_init();
c8076604 6416
ff9d07a0
ZY		 6417 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6418
d366bf7e 6419 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6420 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6421
c5cc421b 6422 kvm_lapic_init();
16e8d74d
MT		 6423#ifdef CONFIG_X86_64
6424 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6425
5fa4ec9c 6426 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6427 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6428#endif
6429
f8c16bba 6430 return 0;
56c6d28a 6431
013f6a5d
MT		 6432out_free_percpu:
6433 free_percpu(shared_msrs);
56c6d28a 6434out:
56c6d28a 6435 return r;
043405e1 6436}
8776e519 6437
f8c16bba
ZX		 6438void kvm_arch_exit(void)
6439{
0092e434 6440#ifdef CONFIG_X86_64
5fa4ec9c 6441 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6442 clear_hv_tscchange_cb();
6443#endif
cef84c30 6444 kvm_lapic_exit();
ff9d07a0
ZY		 6445 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6446
888d256e
JK		 6447 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6448 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6449 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6450 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6451#ifdef CONFIG_X86_64
6452 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6453#endif
f8c16bba 6454 kvm_x86_ops = NULL;
56c6d28a 6455 kvm_mmu_module_exit();
013f6a5d 6456 free_percpu(shared_msrs);
56c6d28a 6457}
f8c16bba 6458
5cb56059 6459int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6460{
6461 ++vcpu->stat.halt_exits;
35754c98 6462 if (lapic_in_kernel(vcpu)) {
a4535290 6463 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6464 return 1;
6465 } else {
6466 vcpu->run->exit_reason = KVM_EXIT_HLT;
6467 return 0;
6468 }
6469}
5cb56059
JS		 6470EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6471
6472int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6473{
6affcbed
KH		 6474 int ret = kvm_skip_emulated_instruction(vcpu);
6475 /*
6476 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6477 * KVM_EXIT_DEBUG here.
6478 */
6479 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6480}
8776e519
HB		 6481EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6482
8ef81a9a 6483#ifdef CONFIG_X86_64
55dd00a7
MT		 6484static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6485 unsigned long clock_type)
6486{
6487 struct kvm_clock_pairing clock_pairing;
6488 struct timespec ts;
80fbd89c 6489 u64 cycle;
55dd00a7
MT		 6490 int ret;
6491
6492 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6493 return -KVM_EOPNOTSUPP;
6494
6495 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6496 return -KVM_EOPNOTSUPP;
6497
6498 clock_pairing.sec = ts.tv_sec;
6499 clock_pairing.nsec = ts.tv_nsec;
6500 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6501 clock_pairing.flags = 0;
6502
6503 ret = 0;
6504 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6505 sizeof(struct kvm_clock_pairing)))
6506 ret = -KVM_EFAULT;
6507
6508 return ret;
6509}
8ef81a9a 6510#endif
55dd00a7 6511
6aef266c
SV		 6512/*
6513 * kvm_pv_kick_cpu_op: Kick a vcpu.
6514 *
6515 * @apicid - apicid of vcpu to be kicked.
6516 */
6517static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6518{
24d2166b 6519 struct kvm_lapic_irq lapic_irq;
6aef266c 6520
24d2166b
R		 6521 lapic_irq.shorthand = 0;
6522 lapic_irq.dest_mode = 0;
ebd28fcb 6523 lapic_irq.level = 0;
24d2166b 6524 lapic_irq.dest_id = apicid;
93bbf0b8 6525 lapic_irq.msi_redir_hint = false;
6aef266c 6526
24d2166b 6527 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6528 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6529}
6530
d62caabb
AS		 6531void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6532{
6533 vcpu->arch.apicv_active = false;
6534 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6535}
6536
8776e519
HB		 6537int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6538{
6539 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6540 int op_64_bit, r;
8776e519 6541
6affcbed 6542 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6543
55cd8e5a
GN		 6544 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6545 return kvm_hv_hypercall(vcpu);
6546
5fdbf976
MT		 6547 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6548 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6549 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6550 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6551 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6552
229456fc 6553 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6554
a449c7aa
NA		 6555 op_64_bit = is_64_bit_mode(vcpu);
6556 if (!op_64_bit) {
8776e519
HB		 6557 nr &= 0xFFFFFFFF;
6558 a0 &= 0xFFFFFFFF;
6559 a1 &= 0xFFFFFFFF;
6560 a2 &= 0xFFFFFFFF;
6561 a3 &= 0xFFFFFFFF;
6562 }
6563
07708c4a
JK		 6564 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6565 ret = -KVM_EPERM;
6566 goto out;
6567 }
6568
8776e519 6569 switch (nr) {
b93463aa
AK		 6570 case KVM_HC_VAPIC_POLL_IRQ:
6571 ret = 0;
6572 break;
6aef266c
SV		 6573 case KVM_HC_KICK_CPU:
6574 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6575 ret = 0;
6576 break;
8ef81a9a 6577#ifdef CONFIG_X86_64
55dd00a7
MT		 6578 case KVM_HC_CLOCK_PAIRING:
6579 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6580 break;
8ef81a9a 6581#endif
8776e519
HB		 6582 default:
6583 ret = -KVM_ENOSYS;
6584 break;
6585 }
07708c4a 6586out:
a449c7aa
NA		 6587 if (!op_64_bit)
6588 ret = (u32)ret;
5fdbf976 6589 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6590 ++vcpu->stat.hypercalls;
2f333bcb 6591 return r;
8776e519
HB		 6592}
6593EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6594
b6785def 6595static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6596{
d6aa1000 6597 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6598 char instruction[3];
5fdbf976 6599 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6600
8776e519 6601 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6602
ce2e852e
DV		 6603 return emulator_write_emulated(ctxt, rip, instruction, 3,
6604 &ctxt->exception);
8776e519
HB		 6605}
6606
851ba692 6607static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6608{
782d422b
MG		 6609 return vcpu->run->request_interrupt_window &&
6610 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6611}
6612
851ba692 6613static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6614{
851ba692
AK		 6615 struct kvm_run *kvm_run = vcpu->run;
6616
91586a3b 6617 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6618 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6619 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6620 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6621 kvm_run->ready_for_interrupt_injection =
6622 pic_in_kernel(vcpu->kvm) ||
782d422b 6623 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6624}
6625
95ba8273
GN		 6626static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6627{
6628 int max_irr, tpr;
6629
6630 if (!kvm_x86_ops->update_cr8_intercept)
6631 return;
6632
bce87cce 6633 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6634 return;
6635
d62caabb
AS		 6636 if (vcpu->arch.apicv_active)
6637 return;
6638
8db3baa2
GN		 6639 if (!vcpu->arch.apic->vapic_addr)
6640 max_irr = kvm_lapic_find_highest_irr(vcpu);
6641 else
6642 max_irr = -1;
95ba8273
GN		 6643
6644 if (max_irr != -1)
6645 max_irr >>= 4;
6646
6647 tpr = kvm_lapic_get_cr8(vcpu);
6648
6649 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6650}
6651
b6b8a145 6652static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6653{
b6b8a145
JK		 6654 int r;
6655
95ba8273 6656 /* try to reinject previous events if any */
664f8e26
WL		 6657 if (vcpu->arch.exception.injected) {
6658 kvm_x86_ops->queue_exception(vcpu);
6659 return 0;
6660 }
6661
6662 /*
6663 * Exceptions must be injected immediately, or the exception
6664 * frame will have the address of the NMI or interrupt handler.
6665 */
6666 if (!vcpu->arch.exception.pending) {
6667 if (vcpu->arch.nmi_injected) {
6668 kvm_x86_ops->set_nmi(vcpu);
6669 return 0;
6670 }
6671
6672 if (vcpu->arch.interrupt.pending) {
6673 kvm_x86_ops->set_irq(vcpu);
6674 return 0;
6675 }
6676 }
6677
6678 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6679 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6680 if (r != 0)
6681 return r;
6682 }
6683
6684 /* try to inject new event if pending */
b59bb7bd 6685 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6686 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6687 vcpu->arch.exception.has_error_code,
6688 vcpu->arch.exception.error_code);
d6e8c854 6689
664f8e26
WL		 6690 vcpu->arch.exception.pending = false;
6691 vcpu->arch.exception.injected = true;
6692
d6e8c854
NA		 6693 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6694 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6695 X86_EFLAGS_RF);
6696
6bdf0662
NA		 6697 if (vcpu->arch.exception.nr == DB_VECTOR &&
6698 (vcpu->arch.dr7 & DR7_GD)) {
6699 vcpu->arch.dr7 &= ~DR7_GD;
6700 kvm_update_dr7(vcpu);
6701 }
6702
cfcd20e5 6703 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6704 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6705 vcpu->arch.smi_pending = false;
52797bf9 6706 ++vcpu->arch.smi_count;
ee2cd4b7 6707 enter_smm(vcpu);
c43203ca 6708 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6709 --vcpu->arch.nmi_pending;
6710 vcpu->arch.nmi_injected = true;
6711 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6712 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6713 /*
6714 * Because interrupts can be injected asynchronously, we are
6715 * calling check_nested_events again here to avoid a race condition.
6716 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6717 * proposal and current concerns. Perhaps we should be setting
6718 * KVM_REQ_EVENT only on certain events and not unconditionally?
6719 */
6720 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6721 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6722 if (r != 0)
6723 return r;
6724 }
95ba8273 6725 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6726 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6727 false);
6728 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6729 }
6730 }
ee2cd4b7 6731
b6b8a145 6732 return 0;
95ba8273
GN		 6733}
6734
7460fb4a
AK		 6735static void process_nmi(struct kvm_vcpu *vcpu)
6736{
6737 unsigned limit = 2;
6738
6739 /*
6740 * x86 is limited to one NMI running, and one NMI pending after it.
6741 * If an NMI is already in progress, limit further NMIs to just one.
6742 * Otherwise, allow two (and we'll inject the first one immediately).
6743 */
6744 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6745 limit = 1;
6746
6747 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6748 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6749 kvm_make_request(KVM_REQ_EVENT, vcpu);
6750}
6751
ee2cd4b7 6752static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6753{
6754 u32 flags = 0;
6755 flags |= seg->g << 23;
6756 flags |= seg->db << 22;
6757 flags |= seg->l << 21;
6758 flags |= seg->avl << 20;
6759 flags |= seg->present << 15;
6760 flags |= seg->dpl << 13;
6761 flags |= seg->s << 12;
6762 flags |= seg->type << 8;
6763 return flags;
6764}
6765
ee2cd4b7 6766static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6767{
6768 struct kvm_segment seg;
6769 int offset;
6770
6771 kvm_get_segment(vcpu, &seg, n);
6772 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6773
6774 if (n < 3)
6775 offset = 0x7f84 + n * 12;
6776 else
6777 offset = 0x7f2c + (n - 3) * 12;
6778
6779 put_smstate(u32, buf, offset + 8, seg.base);
6780 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6781 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6782}
6783
efbb288a 6784#ifdef CONFIG_X86_64
ee2cd4b7 6785static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6786{
6787 struct kvm_segment seg;
6788 int offset;
6789 u16 flags;
6790
6791 kvm_get_segment(vcpu, &seg, n);
6792 offset = 0x7e00 + n * 16;
6793
ee2cd4b7 6794 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6795 put_smstate(u16, buf, offset, seg.selector);
6796 put_smstate(u16, buf, offset + 2, flags);
6797 put_smstate(u32, buf, offset + 4, seg.limit);
6798 put_smstate(u64, buf, offset + 8, seg.base);
6799}
efbb288a 6800#endif
660a5d51 6801
ee2cd4b7 6802static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6803{
6804 struct desc_ptr dt;
6805 struct kvm_segment seg;
6806 unsigned long val;
6807 int i;
6808
6809 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6810 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6811 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6812 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6813
6814 for (i = 0; i < 8; i++)
6815 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6816
6817 kvm_get_dr(vcpu, 6, &val);
6818 put_smstate(u32, buf, 0x7fcc, (u32)val);
6819 kvm_get_dr(vcpu, 7, &val);
6820 put_smstate(u32, buf, 0x7fc8, (u32)val);
6821
6822 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6823 put_smstate(u32, buf, 0x7fc4, seg.selector);
6824 put_smstate(u32, buf, 0x7f64, seg.base);
6825 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6826 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6827
6828 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6829 put_smstate(u32, buf, 0x7fc0, seg.selector);
6830 put_smstate(u32, buf, 0x7f80, seg.base);
6831 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6832 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6833
6834 kvm_x86_ops->get_gdt(vcpu, &dt);
6835 put_smstate(u32, buf, 0x7f74, dt.address);
6836 put_smstate(u32, buf, 0x7f70, dt.size);
6837
6838 kvm_x86_ops->get_idt(vcpu, &dt);
6839 put_smstate(u32, buf, 0x7f58, dt.address);
6840 put_smstate(u32, buf, 0x7f54, dt.size);
6841
6842 for (i = 0; i < 6; i++)
ee2cd4b7 6843 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6844
6845 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6846
6847 /* revision id */
6848 put_smstate(u32, buf, 0x7efc, 0x00020000);
6849 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6850}
6851
ee2cd4b7 6852static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6853{
6854#ifdef CONFIG_X86_64
6855 struct desc_ptr dt;
6856 struct kvm_segment seg;
6857 unsigned long val;
6858 int i;
6859
6860 for (i = 0; i < 16; i++)
6861 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6862
6863 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6864 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6865
6866 kvm_get_dr(vcpu, 6, &val);
6867 put_smstate(u64, buf, 0x7f68, val);
6868 kvm_get_dr(vcpu, 7, &val);
6869 put_smstate(u64, buf, 0x7f60, val);
6870
6871 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6872 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6873 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6874
6875 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6876
6877 /* revision id */
6878 put_smstate(u32, buf, 0x7efc, 0x00020064);
6879
6880 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6881
6882 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6883 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6884 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6885 put_smstate(u32, buf, 0x7e94, seg.limit);
6886 put_smstate(u64, buf, 0x7e98, seg.base);
6887
6888 kvm_x86_ops->get_idt(vcpu, &dt);
6889 put_smstate(u32, buf, 0x7e84, dt.size);
6890 put_smstate(u64, buf, 0x7e88, dt.address);
6891
6892 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6893 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6894 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6895 put_smstate(u32, buf, 0x7e74, seg.limit);
6896 put_smstate(u64, buf, 0x7e78, seg.base);
6897
6898 kvm_x86_ops->get_gdt(vcpu, &dt);
6899 put_smstate(u32, buf, 0x7e64, dt.size);
6900 put_smstate(u64, buf, 0x7e68, dt.address);
6901
6902 for (i = 0; i < 6; i++)
ee2cd4b7 6903 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6904#else
6905 WARN_ON_ONCE(1);
6906#endif
6907}
6908
ee2cd4b7 6909static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6910{
660a5d51 6911 struct kvm_segment cs, ds;
18c3626e 6912 struct desc_ptr dt;
660a5d51
PB		 6913 char buf[512];
6914 u32 cr0;
6915
660a5d51 6916 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6917 memset(buf, 0, 512);
d6321d49 6918 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6919 enter_smm_save_state_64(vcpu, buf);
660a5d51 6920 else
ee2cd4b7 6921 enter_smm_save_state_32(vcpu, buf);
660a5d51 6922
0234bf88
LP		 6923 /*
6924 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6925 * vCPU state (e.g. leave guest mode) after we've saved the state into
6926 * the SMM state-save area.
6927 */
6928 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6929
6930 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6931 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6932
6933 if (kvm_x86_ops->get_nmi_mask(vcpu))
6934 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6935 else
6936 kvm_x86_ops->set_nmi_mask(vcpu, true);
6937
6938 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6939 kvm_rip_write(vcpu, 0x8000);
6940
6941 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6942 kvm_x86_ops->set_cr0(vcpu, cr0);
6943 vcpu->arch.cr0 = cr0;
6944
6945 kvm_x86_ops->set_cr4(vcpu, 0);
6946
18c3626e
PB		 6947 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6948 dt.address = dt.size = 0;
6949 kvm_x86_ops->set_idt(vcpu, &dt);
6950
660a5d51
PB		 6951 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6952
6953 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6954 cs.base = vcpu->arch.smbase;
6955
6956 ds.selector = 0;
6957 ds.base = 0;
6958
6959 cs.limit = ds.limit = 0xffffffff;
6960 cs.type = ds.type = 0x3;
6961 cs.dpl = ds.dpl = 0;
6962 cs.db = ds.db = 0;
6963 cs.s = ds.s = 1;
6964 cs.l = ds.l = 0;
6965 cs.g = ds.g = 1;
6966 cs.avl = ds.avl = 0;
6967 cs.present = ds.present = 1;
6968 cs.unusable = ds.unusable = 0;
6969 cs.padding = ds.padding = 0;
6970
6971 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6972 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6973 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6974 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6975 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6976 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6977
d6321d49 6978 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6979 kvm_x86_ops->set_efer(vcpu, 0);
6980
6981 kvm_update_cpuid(vcpu);
6982 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6983}
6984
ee2cd4b7 6985static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6986{
6987 vcpu->arch.smi_pending = true;
6988 kvm_make_request(KVM_REQ_EVENT, vcpu);
6989}
6990
2860c4b1
PB		 6991void kvm_make_scan_ioapic_request(struct kvm *kvm)
6992{
6993 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6994}
6995
3d81bc7e 6996static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6997{
5c919412
AS		 6998 u64 eoi_exit_bitmap[4];
6999
3d81bc7e
YZ		 7000 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7001 return;
c7c9c56c 7002
6308630b 7003 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7004
b053b2ae 7005 if (irqchip_split(vcpu->kvm))
6308630b 7006 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7007 else {
fa59cc00 7008 if (vcpu->arch.apicv_active)
d62caabb 7009 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7010 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7011 }
5c919412
AS		 7012 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7013 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7014 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7015}
7016
b1394e74
RK		 7017void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7018 unsigned long start, unsigned long end)
7019{
7020 unsigned long apic_address;
7021
7022 /*
7023 * The physical address of apic access page is stored in the VMCS.
7024 * Update it when it becomes invalid.
7025 */
7026 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7027 if (start <= apic_address && apic_address < end)
7028 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7029}
7030
4256f43f
TC		 7031void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7032{
c24ae0dc
TC		 7033 struct page *page = NULL;
7034
35754c98 7035 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7036 return;
7037
4256f43f
TC		 7038 if (!kvm_x86_ops->set_apic_access_page_addr)
7039 return;
7040
c24ae0dc 7041 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7042 if (is_error_page(page))
7043 return;
c24ae0dc
TC		 7044 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7045
7046 /*
7047 * Do not pin apic access page in memory, the MMU notifier
7048 * will call us again if it is migrated or swapped out.
7049 */
7050 put_page(page);
4256f43f
TC		 7051}
7052EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7053
9357d939 7054/*
362c698f 7055 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7056 * exiting to the userspace. Otherwise, the value will be returned to the
7057 * userspace.
7058 */
851ba692 7059static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7060{
7061 int r;
62a193ed
MG		 7062 bool req_int_win =
7063 dm_request_for_irq_injection(vcpu) &&
7064 kvm_cpu_accept_dm_intr(vcpu);
7065
730dca42 7066 bool req_immediate_exit = false;
b6c7a5dc 7067
2fa6e1e1 7068 if (kvm_request_pending(vcpu)) {
a8eeb04a 7069 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7070 kvm_mmu_unload(vcpu);
a8eeb04a 7071 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7072 __kvm_migrate_timers(vcpu);
d828199e
MT		 7073 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7074 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7075 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7076 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7077 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7078 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7079 if (unlikely(r))
7080 goto out;
7081 }
a8eeb04a 7082 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7083 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7084 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7085 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7086 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7087 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7088 r = 0;
7089 goto out;
7090 }
a8eeb04a 7091 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7092 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7093 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7094 r = 0;
7095 goto out;
7096 }
af585b92
GN		 7097 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7098 /* Page is swapped out. Do synthetic halt */
7099 vcpu->arch.apf.halted = true;
7100 r = 1;
7101 goto out;
7102 }
c9aaa895
GC		 7103 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7104 record_steal_time(vcpu);
64d60670
PB		 7105 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7106 process_smi(vcpu);
7460fb4a
AK		 7107 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7108 process_nmi(vcpu);
f5132b01 7109 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7110 kvm_pmu_handle_event(vcpu);
f5132b01 7111 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7112 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7113 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7114 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7115 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7116 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7117 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7118 vcpu->run->eoi.vector =
7119 vcpu->arch.pending_ioapic_eoi;
7120 r = 0;
7121 goto out;
7122 }
7123 }
3d81bc7e
YZ		 7124 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7125 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 7126 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7127 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7128 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7129 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7130 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7131 r = 0;
7132 goto out;
7133 }
e516cebb
AS		 7134 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7135 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7136 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7137 r = 0;
7138 goto out;
7139 }
db397571
AS		 7140 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7141 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7142 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7143 r = 0;
7144 goto out;
7145 }
f3b138c5
AS		 7146
7147 /*
7148 * KVM_REQ_HV_STIMER has to be processed after
7149 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7150 * depend on the guest clock being up-to-date
7151 */
1f4b34f8
AS		 7152 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7153 kvm_hv_process_stimers(vcpu);
2f52d58c 7154 }
b93463aa 7155
b463a6f7 7156 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7157 ++vcpu->stat.req_event;
66450a21
JK		 7158 kvm_apic_accept_events(vcpu);
7159 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7160 r = 1;
7161 goto out;
7162 }
7163
b6b8a145
JK		 7164 if (inject_pending_event(vcpu, req_int_win) != 0)
7165 req_immediate_exit = true;
321c5658 7166 else {
cc3d967f 7167 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7168 *
cc3d967f
LP		 7169 * SMIs have three cases:
7170 * 1) They can be nested, and then there is nothing to
7171 * do here because RSM will cause a vmexit anyway.
7172 * 2) There is an ISA-specific reason why SMI cannot be
7173 * injected, and the moment when this changes can be
7174 * intercepted.
7175 * 3) Or the SMI can be pending because
7176 * inject_pending_event has completed the injection
7177 * of an IRQ or NMI from the previous vmexit, and
7178 * then we request an immediate exit to inject the
7179 * SMI.
c43203ca
PB		 7180 */
7181 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7182 if (!kvm_x86_ops->enable_smi_window(vcpu))
7183 req_immediate_exit = true;
321c5658
YS		 7184 if (vcpu->arch.nmi_pending)
7185 kvm_x86_ops->enable_nmi_window(vcpu);
7186 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7187 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7188 WARN_ON(vcpu->arch.exception.pending);
321c5658 7189 }
b463a6f7
AK		 7190
7191 if (kvm_lapic_enabled(vcpu)) {
7192 update_cr8_intercept(vcpu);
7193 kvm_lapic_sync_to_vapic(vcpu);
7194 }
7195 }
7196
d8368af8
AK		 7197 r = kvm_mmu_reload(vcpu);
7198 if (unlikely(r)) {
d905c069 7199 goto cancel_injection;
d8368af8
AK		 7200 }
7201
b6c7a5dc
HB		 7202 preempt_disable();
7203
7204 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7205
7206 /*
7207 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7208 * IPI are then delayed after guest entry, which ensures that they
7209 * result in virtual interrupt delivery.
7210 */
7211 local_irq_disable();
6b7e2d09
XG		 7212 vcpu->mode = IN_GUEST_MODE;
7213
01b71917
MT		 7214 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7215
0f127d12 7216 /*
b95234c8 7217 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7218 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7219 *
7220 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7221 * pairs with the memory barrier implicit in pi_test_and_set_on
7222 * (see vmx_deliver_posted_interrupt).
7223 *
7224 * 3) This also orders the write to mode from any reads to the page
7225 * tables done while the VCPU is running. Please see the comment
7226 * in kvm_flush_remote_tlbs.
6b7e2d09 7227 */
01b71917 7228 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7229
b95234c8
PB		 7230 /*
7231 * This handles the case where a posted interrupt was
7232 * notified with kvm_vcpu_kick.
7233 */
fa59cc00
LA		 7234 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7235 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7236
2fa6e1e1 7237 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7238 || need_resched() || signal_pending(current)) {
6b7e2d09 7239 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7240 smp_wmb();
6c142801
AK		 7241 local_irq_enable();
7242 preempt_enable();
01b71917 7243 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7244 r = 1;
d905c069 7245 goto cancel_injection;
6c142801
AK		 7246 }
7247
fc5b7f3b
DM		 7248 kvm_load_guest_xcr0(vcpu);
7249
c43203ca
PB		 7250 if (req_immediate_exit) {
7251 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7252 smp_send_reschedule(vcpu->cpu);
c43203ca 7253 }
d6185f20 7254
8b89fe1f 7255 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7256 if (lapic_timer_advance_ns)
7257 wait_lapic_expire(vcpu);
6edaa530 7258 guest_enter_irqoff();
b6c7a5dc 7259
42dbaa5a 7260 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7261 set_debugreg(0, 7);
7262 set_debugreg(vcpu->arch.eff_db[0], 0);
7263 set_debugreg(vcpu->arch.eff_db[1], 1);
7264 set_debugreg(vcpu->arch.eff_db[2], 2);
7265 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7266 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7267 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7268 }
b6c7a5dc 7269
851ba692 7270 kvm_x86_ops->run(vcpu);
b6c7a5dc 7271
c77fb5fe
PB		 7272 /*
7273 * Do this here before restoring debug registers on the host. And
7274 * since we do this before handling the vmexit, a DR access vmexit
7275 * can (a) read the correct value of the debug registers, (b) set
7276 * KVM_DEBUGREG_WONT_EXIT again.
7277 */
7278 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7279 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7280 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7281 kvm_update_dr0123(vcpu);
7282 kvm_update_dr6(vcpu);
7283 kvm_update_dr7(vcpu);
7284 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7285 }
7286
24f1e32c
FW		 7287 /*
7288 * If the guest has used debug registers, at least dr7
7289 * will be disabled while returning to the host.
7290 * If we don't have active breakpoints in the host, we don't
7291 * care about the messed up debug address registers. But if
7292 * we have some of them active, restore the old state.
7293 */
59d8eb53 7294 if (hw_breakpoint_active())
24f1e32c 7295 hw_breakpoint_restore();
42dbaa5a 7296
4ba76538 7297 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7298
6b7e2d09 7299 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7300 smp_wmb();
a547c6db 7301
fc5b7f3b
DM		 7302 kvm_put_guest_xcr0(vcpu);
7303
a547c6db 7304 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7305
7306 ++vcpu->stat.exits;
7307
f2485b3e 7308 guest_exit_irqoff();
b6c7a5dc 7309
f2485b3e 7310 local_irq_enable();
b6c7a5dc
HB		 7311 preempt_enable();
7312
f656ce01 7313 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7314
b6c7a5dc
HB		 7315 /*
7316 * Profile KVM exit RIPs:
7317 */
7318 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7319 unsigned long rip = kvm_rip_read(vcpu);
7320 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7321 }
7322
cc578287
ZA		 7323 if (unlikely(vcpu->arch.tsc_always_catchup))
7324 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7325
5cfb1d5a
MT		 7326 if (vcpu->arch.apic_attention)
7327 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7328
618232e2 7329 vcpu->arch.gpa_available = false;
851ba692 7330 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7331 return r;
7332
7333cancel_injection:
7334 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7335 if (unlikely(vcpu->arch.apic_attention))
7336 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7337out:
7338 return r;
7339}
b6c7a5dc 7340
362c698f
PB		 7341static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7342{
bf9f6ac8
FW		 7343 if (!kvm_arch_vcpu_runnable(vcpu) &&
7344 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7345 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7346 kvm_vcpu_block(vcpu);
7347 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7348
7349 if (kvm_x86_ops->post_block)
7350 kvm_x86_ops->post_block(vcpu);
7351
9c8fd1ba
PB		 7352 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7353 return 1;
7354 }
362c698f
PB		 7355
7356 kvm_apic_accept_events(vcpu);
7357 switch(vcpu->arch.mp_state) {
7358 case KVM_MP_STATE_HALTED:
7359 vcpu->arch.pv.pv_unhalted = false;
7360 vcpu->arch.mp_state =
7361 KVM_MP_STATE_RUNNABLE;
7362 case KVM_MP_STATE_RUNNABLE:
7363 vcpu->arch.apf.halted = false;
7364 break;
7365 case KVM_MP_STATE_INIT_RECEIVED:
7366 break;
7367 default:
7368 return -EINTR;
7369 break;
7370 }
7371 return 1;
7372}
09cec754 7373
5d9bc648
PB		 7374static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7375{
0ad3bed6
PB		 7376 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7377 kvm_x86_ops->check_nested_events(vcpu, false);
7378
5d9bc648
PB		 7379 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7380 !vcpu->arch.apf.halted);
7381}
7382
362c698f 7383static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7384{
7385 int r;
f656ce01 7386 struct kvm *kvm = vcpu->kvm;
d7690175 7387
f656ce01 7388 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7389
362c698f 7390 for (;;) {
58f800d5 7391 if (kvm_vcpu_running(vcpu)) {
851ba692 7392 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7393 } else {
362c698f 7394 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7395 }
7396
09cec754
GN		 7397 if (r <= 0)
7398 break;
7399
72875d8a 7400 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7401 if (kvm_cpu_has_pending_timer(vcpu))
7402 kvm_inject_pending_timer_irqs(vcpu);
7403
782d422b
MG		 7404 if (dm_request_for_irq_injection(vcpu) &&
7405 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7406 r = 0;
7407 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7408 ++vcpu->stat.request_irq_exits;
362c698f 7409 break;
09cec754 7410 }
af585b92
GN		 7411
7412 kvm_check_async_pf_completion(vcpu);
7413
09cec754
GN		 7414 if (signal_pending(current)) {
7415 r = -EINTR;
851ba692 7416 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7417 ++vcpu->stat.signal_exits;
362c698f 7418 break;
09cec754
GN		 7419 }
7420 if (need_resched()) {
f656ce01 7421 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7422 cond_resched();
f656ce01 7423 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7424 }
b6c7a5dc
HB		 7425 }
7426
f656ce01 7427 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7428
7429 return r;
7430}
7431
716d51ab
GN		 7432static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7433{
7434 int r;
7435 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7436 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7437 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7438 if (r != EMULATE_DONE)
7439 return 0;
7440 return 1;
7441}
7442
7443static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7444{
7445 BUG_ON(!vcpu->arch.pio.count);
7446
7447 return complete_emulated_io(vcpu);
7448}
7449
f78146b0
AK		 7450/*
7451 * Implements the following, as a state machine:
7452 *
7453 * read:
7454 * for each fragment
87da7e66
XG		 7455 * for each mmio piece in the fragment
7456 * write gpa, len
7457 * exit
7458 * copy data
f78146b0
AK		 7459 * execute insn
7460 *
7461 * write:
7462 * for each fragment
87da7e66
XG		 7463 * for each mmio piece in the fragment
7464 * write gpa, len
7465 * copy data
7466 * exit
f78146b0 7467 */
716d51ab 7468static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7469{
7470 struct kvm_run *run = vcpu->run;
f78146b0 7471 struct kvm_mmio_fragment *frag;
87da7e66 7472 unsigned len;
5287f194 7473
716d51ab 7474 BUG_ON(!vcpu->mmio_needed);
5287f194 7475
716d51ab 7476 /* Complete previous fragment */
87da7e66
XG		 7477 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7478 len = min(8u, frag->len);
716d51ab 7479 if (!vcpu->mmio_is_write)
87da7e66
XG		 7480 memcpy(frag->data, run->mmio.data, len);
7481
7482 if (frag->len <= 8) {
7483 /* Switch to the next fragment. */
7484 frag++;
7485 vcpu->mmio_cur_fragment++;
7486 } else {
7487 /* Go forward to the next mmio piece. */
7488 frag->data += len;
7489 frag->gpa += len;
7490 frag->len -= len;
7491 }
7492
a08d3b3b 7493 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7494 vcpu->mmio_needed = 0;
0912c977
PB		 7495
7496 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7497 if (vcpu->mmio_is_write)
716d51ab
GN		 7498 return 1;
7499 vcpu->mmio_read_completed = 1;
7500 return complete_emulated_io(vcpu);
7501 }
87da7e66 7502
716d51ab
GN		 7503 run->exit_reason = KVM_EXIT_MMIO;
7504 run->mmio.phys_addr = frag->gpa;
7505 if (vcpu->mmio_is_write)
87da7e66
XG		 7506 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7507 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7508 run->mmio.is_write = vcpu->mmio_is_write;
7509 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7510 return 0;
5287f194
AK		 7511}
7512
716d51ab 7513
b6c7a5dc
HB		 7514int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7515{
7516 int r;
b6c7a5dc 7517
accb757d 7518 vcpu_load(vcpu);
20b7035c 7519 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7520 kvm_load_guest_fpu(vcpu);
7521
a4535290 7522 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7523 if (kvm_run->immediate_exit) {
7524 r = -EINTR;
7525 goto out;
7526 }
b6c7a5dc 7527 kvm_vcpu_block(vcpu);
66450a21 7528 kvm_apic_accept_events(vcpu);
72875d8a 7529 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7530 r = -EAGAIN;
a0595000
JS		 7531 if (signal_pending(current)) {
7532 r = -EINTR;
7533 vcpu->run->exit_reason = KVM_EXIT_INTR;
7534 ++vcpu->stat.signal_exits;
7535 }
ac9f6dc0 7536 goto out;
b6c7a5dc
HB		 7537 }
7538
b6c7a5dc 7539 /* re-sync apic's tpr */
35754c98 7540 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7541 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7542 r = -EINVAL;
7543 goto out;
7544 }
7545 }
b6c7a5dc 7546
716d51ab
GN		 7547 if (unlikely(vcpu->arch.complete_userspace_io)) {
7548 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7549 vcpu->arch.complete_userspace_io = NULL;
7550 r = cui(vcpu);
7551 if (r <= 0)
5663d8f9 7552 goto out;
716d51ab
GN		 7553 } else
7554 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7555
460df4c1
PB		 7556 if (kvm_run->immediate_exit)
7557 r = -EINTR;
7558 else
7559 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7560
7561out:
5663d8f9 7562 kvm_put_guest_fpu(vcpu);
f1d86e46 7563 post_kvm_run_save(vcpu);
20b7035c 7564 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7565
accb757d 7566 vcpu_put(vcpu);
b6c7a5dc
HB		 7567 return r;
7568}
7569
7570int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7571{
1fc9b76b
CD		 7572 vcpu_load(vcpu);
7573
7ae441ea
GN		 7574 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7575 /*
7576 * We are here if userspace calls get_regs() in the middle of
7577 * instruction emulation. Registers state needs to be copied
4a969980 7578 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7579 * that usually, but some bad designed PV devices (vmware
7580 * backdoor interface) need this to work
7581 */
dd856efa 7582 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7583 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7584 }
5fdbf976
MT		 7585 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7586 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7587 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7588 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7589 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7590 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7591 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7592 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7593#ifdef CONFIG_X86_64
5fdbf976
MT		 7594 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7595 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7596 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7597 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7598 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7599 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7600 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7601 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7602#endif
7603
5fdbf976 7604 regs->rip = kvm_rip_read(vcpu);
91586a3b 7605 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7606
1fc9b76b 7607 vcpu_put(vcpu);
b6c7a5dc
HB		 7608 return 0;
7609}
7610
7611int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7612{
875656fe
CD		 7613 vcpu_load(vcpu);
7614
7ae441ea
GN		 7615 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7616 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7617
5fdbf976
MT		 7618 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7619 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7620 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7621 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7622 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7623 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7624 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7625 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7626#ifdef CONFIG_X86_64
5fdbf976
MT		 7627 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7628 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7629 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7630 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7631 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7632 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7633 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7634 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7635#endif
7636
5fdbf976 7637 kvm_rip_write(vcpu, regs->rip);
d73235d1 7638 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7639
b4f14abd
JK		 7640 vcpu->arch.exception.pending = false;
7641
3842d135
AK		 7642 kvm_make_request(KVM_REQ_EVENT, vcpu);
7643
875656fe 7644 vcpu_put(vcpu);
b6c7a5dc
HB		 7645 return 0;
7646}
7647
b6c7a5dc
HB		 7648void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7649{
7650 struct kvm_segment cs;
7651
3e6e0aab 7652 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7653 *db = cs.db;
7654 *l = cs.l;
7655}
7656EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7657
7658int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7659 struct kvm_sregs *sregs)
7660{
89a27f4d 7661 struct desc_ptr dt;
b6c7a5dc 7662
bcdec41c
CD		 7663 vcpu_load(vcpu);
7664
3e6e0aab
GT		 7665 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7666 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7667 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7668 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7669 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7670 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7671
3e6e0aab
GT		 7672 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7673 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7674
7675 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7676 sregs->idt.limit = dt.size;
7677 sregs->idt.base = dt.address;
b6c7a5dc 7678 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7679 sregs->gdt.limit = dt.size;
7680 sregs->gdt.base = dt.address;
b6c7a5dc 7681
4d4ec087 7682 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7683 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7684 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7685 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7686 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7687 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7688 sregs->apic_base = kvm_get_apic_base(vcpu);
7689
923c61bb 7690 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7691
36752c9b 7692 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7693 set_bit(vcpu->arch.interrupt.nr,
7694 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7695
bcdec41c 7696 vcpu_put(vcpu);
b6c7a5dc
HB		 7697 return 0;
7698}
7699
62d9f0db
MT		 7700int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7701 struct kvm_mp_state *mp_state)
7702{
fd232561
CD		 7703 vcpu_load(vcpu);
7704
66450a21 7705 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7706 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7707 vcpu->arch.pv.pv_unhalted)
7708 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7709 else
7710 mp_state->mp_state = vcpu->arch.mp_state;
7711
fd232561 7712 vcpu_put(vcpu);
62d9f0db
MT		 7713 return 0;
7714}
7715
7716int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7717 struct kvm_mp_state *mp_state)
7718{
e83dff5e
CD		 7719 int ret = -EINVAL;
7720
7721 vcpu_load(vcpu);
7722
bce87cce 7723 if (!lapic_in_kernel(vcpu) &&
66450a21 7724 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7725 goto out;
66450a21 7726
28bf2888
DH		 7727 /* INITs are latched while in SMM */
7728 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7729 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7730 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7731 goto out;
28bf2888 7732
66450a21
JK		 7733 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7734 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7735 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7736 } else
7737 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7738 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7739
7740 ret = 0;
7741out:
7742 vcpu_put(vcpu);
7743 return ret;
62d9f0db
MT		 7744}
7745
7f3d35fd
KW		 7746int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7747 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7748{
9d74191a 7749 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7750 int ret;
e01c2426 7751
8ec4722d 7752 init_emulate_ctxt(vcpu);
c697518a 7753
7f3d35fd 7754 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7755 has_error_code, error_code);
c697518a 7756
c697518a 7757 if (ret)
19d04437 7758 return EMULATE_FAIL;
37817f29 7759
9d74191a
TY		 7760 kvm_rip_write(vcpu, ctxt->eip);
7761 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7762 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7763 return EMULATE_DONE;
37817f29
IE		 7764}
7765EXPORT_SYMBOL_GPL(kvm_task_switch);
7766
f2981033
LT		 7767int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7768{
37b95951 7769 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7770 /*
7771 * When EFER.LME and CR0.PG are set, the processor is in
7772 * 64-bit mode (though maybe in a 32-bit code segment).
7773 * CR4.PAE and EFER.LMA must be set.
7774 */
37b95951 7775 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7776 || !(sregs->efer & EFER_LMA))
7777 return -EINVAL;
7778 } else {
7779 /*
7780 * Not in 64-bit mode: EFER.LMA is clear and the code
7781 * segment cannot be 64-bit.
7782 */
7783 if (sregs->efer & EFER_LMA || sregs->cs.l)
7784 return -EINVAL;
7785 }
7786
7787 return 0;
7788}
7789
b6c7a5dc
HB		 7790int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7791 struct kvm_sregs *sregs)
7792{
58cb628d 7793 struct msr_data apic_base_msr;
b6c7a5dc 7794 int mmu_reset_needed = 0;
63f42e02 7795 int pending_vec, max_bits, idx;
89a27f4d 7796 struct desc_ptr dt;
b4ef9d4e
CD		 7797 int ret = -EINVAL;
7798
7799 vcpu_load(vcpu);
b6c7a5dc 7800
d6321d49
RK		 7801 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7802 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7803 goto out;
6d1068b3 7804
f2981033 7805 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 7806 goto out;
f2981033 7807
d3802286
JM		 7808 apic_base_msr.data = sregs->apic_base;
7809 apic_base_msr.host_initiated = true;
7810 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 7811 goto out;
6d1068b3 7812
89a27f4d
GN		 7813 dt.size = sregs->idt.limit;
7814 dt.address = sregs->idt.base;
b6c7a5dc 7815 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7816 dt.size = sregs->gdt.limit;
7817 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7818 kvm_x86_ops->set_gdt(vcpu, &dt);
7819
ad312c7c 7820 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7821 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7822 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7823 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7824
2d3ad1f4 7825 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7826
f6801dff 7827 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7828 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7829
4d4ec087 7830 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7831 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7832 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7833
fc78f519 7834 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7835 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7836 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7837 kvm_update_cpuid(vcpu);
63f42e02
XG		 7838
7839 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7840 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7841 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7842 mmu_reset_needed = 1;
7843 }
63f42e02 7844 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7845
7846 if (mmu_reset_needed)
7847 kvm_mmu_reset_context(vcpu);
7848
a50abc3b 7849 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7850 pending_vec = find_first_bit(
7851 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7852 if (pending_vec < max_bits) {
66fd3f7f 7853 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7854 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7855 }
7856
3e6e0aab
GT		 7857 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7858 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7859 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7860 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7861 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7862 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7863
3e6e0aab
GT		 7864 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7865 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7866
5f0269f5
ME		 7867 update_cr8_intercept(vcpu);
7868
9c3e4aab 7869 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7870 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7871 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7872 !is_protmode(vcpu))
9c3e4aab
MT		 7873 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7874
3842d135
AK		 7875 kvm_make_request(KVM_REQ_EVENT, vcpu);
7876
b4ef9d4e
CD		 7877 ret = 0;
7878out:
7879 vcpu_put(vcpu);
7880 return ret;
b6c7a5dc
HB		 7881}
7882
d0bfb940
JK		 7883int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7884 struct kvm_guest_debug *dbg)
b6c7a5dc 7885{
355be0b9 7886 unsigned long rflags;
ae675ef0 7887 int i, r;
b6c7a5dc 7888
66b56562
CD		 7889 vcpu_load(vcpu);
7890
4f926bf2
JK		 7891 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7892 r = -EBUSY;
7893 if (vcpu->arch.exception.pending)
2122ff5e 7894 goto out;
4f926bf2
JK		 7895 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7896 kvm_queue_exception(vcpu, DB_VECTOR);
7897 else
7898 kvm_queue_exception(vcpu, BP_VECTOR);
7899 }
7900
91586a3b
JK		 7901 /*
7902 * Read rflags as long as potentially injected trace flags are still
7903 * filtered out.
7904 */
7905 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7906
7907 vcpu->guest_debug = dbg->control;
7908 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7909 vcpu->guest_debug = 0;
7910
7911 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7912 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7913 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7914 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7915 } else {
7916 for (i = 0; i < KVM_NR_DB_REGS; i++)
7917 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7918 }
c8639010 7919 kvm_update_dr7(vcpu);
ae675ef0 7920
f92653ee
JK		 7921 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7922 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7923 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7924
91586a3b
JK		 7925 /*
7926 * Trigger an rflags update that will inject or remove the trace
7927 * flags.
7928 */
7929 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7930
a96036b8 7931 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7932
4f926bf2 7933 r = 0;
d0bfb940 7934
2122ff5e 7935out:
66b56562 7936 vcpu_put(vcpu);
b6c7a5dc
HB		 7937 return r;
7938}
7939
8b006791
ZX		 7940/*
7941 * Translate a guest virtual address to a guest physical address.
7942 */
7943int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7944 struct kvm_translation *tr)
7945{
7946 unsigned long vaddr = tr->linear_address;
7947 gpa_t gpa;
f656ce01 7948 int idx;
8b006791 7949
1da5b61d
CD		 7950 vcpu_load(vcpu);
7951
f656ce01 7952 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7953 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7954 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7955 tr->physical_address = gpa;
7956 tr->valid = gpa != UNMAPPED_GVA;
7957 tr->writeable = 1;
7958 tr->usermode = 0;
8b006791 7959
1da5b61d 7960 vcpu_put(vcpu);
8b006791
ZX		 7961 return 0;
7962}
7963
d0752060
HB		 7964int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7965{
1393123e 7966 struct fxregs_state *fxsave;
d0752060 7967
1393123e 7968 vcpu_load(vcpu);
d0752060 7969
1393123e 7970 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 7971 memcpy(fpu->fpr, fxsave->st_space, 128);
7972 fpu->fcw = fxsave->cwd;
7973 fpu->fsw = fxsave->swd;
7974 fpu->ftwx = fxsave->twd;
7975 fpu->last_opcode = fxsave->fop;
7976 fpu->last_ip = fxsave->rip;
7977 fpu->last_dp = fxsave->rdp;
7978 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7979
1393123e 7980 vcpu_put(vcpu);
d0752060
HB		 7981 return 0;
7982}
7983
7984int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7985{
6a96bc7f
CD		 7986 struct fxregs_state *fxsave;
7987
7988 vcpu_load(vcpu);
7989
7990 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7991
d0752060
HB		 7992 memcpy(fxsave->st_space, fpu->fpr, 128);
7993 fxsave->cwd = fpu->fcw;
7994 fxsave->swd = fpu->fsw;
7995 fxsave->twd = fpu->ftwx;
7996 fxsave->fop = fpu->last_opcode;
7997 fxsave->rip = fpu->last_ip;
7998 fxsave->rdp = fpu->last_dp;
7999 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8000
6a96bc7f 8001 vcpu_put(vcpu);
d0752060
HB		 8002 return 0;
8003}
8004
0ee6a517 8005static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8006{
bf935b0b 8007 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8008 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8009 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8010 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8011
2acf923e
DC		 8012 /*
8013 * Ensure guest xcr0 is valid for loading
8014 */
d91cab78 8015 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8016
ad312c7c 8017 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8018}
d0752060 8019
f775b13e 8020/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8021void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8022{
f775b13e
RR		 8023 preempt_disable();
8024 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8025 /* PKRU is separately restored in kvm_x86_ops->run. */
8026 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8027 ~XFEATURE_MASK_PKRU);
f775b13e 8028 preempt_enable();
0c04851c 8029 trace_kvm_fpu(1);
d0752060 8030}
d0752060 8031
f775b13e 8032/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8033void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8034{
f775b13e 8035 preempt_disable();
4f836347 8036 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8037 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8038 preempt_enable();
f096ed85 8039 ++vcpu->stat.fpu_reload;
0c04851c 8040 trace_kvm_fpu(0);
d0752060 8041}
e9b11c17
ZX		 8042
8043void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8044{
bd768e14
IY		 8045 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8046
12f9a48f 8047 kvmclock_reset(vcpu);
7f1ea208 8048
e9b11c17 8049 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8050 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8051}
8052
8053struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8054 unsigned int id)
8055{
c447e76b
LL		 8056 struct kvm_vcpu *vcpu;
8057
b0c39dc6 8058 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8059 printk_once(KERN_WARNING
8060 "kvm: SMP vm created on host with unstable TSC; "
8061 "guest TSC will not be reliable\n");
c447e76b
LL		 8062
8063 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8064
c447e76b 8065 return vcpu;
26e5215f 8066}
e9b11c17 8067
26e5215f
AK		 8068int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8069{
19efffa2 8070 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8071 vcpu_load(vcpu);
d28bc9dd 8072 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8073 kvm_mmu_setup(vcpu);
e9b11c17 8074 vcpu_put(vcpu);
ec7660cc 8075 return 0;
e9b11c17
ZX		 8076}
8077
31928aa5 8078void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8079{
8fe8ab46 8080 struct msr_data msr;
332967a3 8081 struct kvm *kvm = vcpu->kvm;
42897d86 8082
d3457c87
RK		 8083 kvm_hv_vcpu_postcreate(vcpu);
8084
ec7660cc 8085 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8086 return;
ec7660cc 8087 vcpu_load(vcpu);
8fe8ab46
WA		 8088 msr.data = 0x0;
8089 msr.index = MSR_IA32_TSC;
8090 msr.host_initiated = true;
8091 kvm_write_tsc(vcpu, &msr);
42897d86 8092 vcpu_put(vcpu);
ec7660cc 8093 mutex_unlock(&vcpu->mutex);
42897d86 8094
630994b3
MT		 8095 if (!kvmclock_periodic_sync)
8096 return;
8097
332967a3
AJ		 8098 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8099 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8100}
8101
d40ccc62 8102void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8103{
344d9588
GN		 8104 vcpu->arch.apf.msr_val = 0;
8105
ec7660cc 8106 vcpu_load(vcpu);
e9b11c17
ZX		 8107 kvm_mmu_unload(vcpu);
8108 vcpu_put(vcpu);
8109
8110 kvm_x86_ops->vcpu_free(vcpu);
8111}
8112
d28bc9dd 8113void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8114{
b7e31be3
RK		 8115 kvm_lapic_reset(vcpu, init_event);
8116
e69fab5d
PB		 8117 vcpu->arch.hflags = 0;
8118
c43203ca 8119 vcpu->arch.smi_pending = 0;
52797bf9 8120 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8121 atomic_set(&vcpu->arch.nmi_queued, 0);
8122 vcpu->arch.nmi_pending = 0;
448fa4a9 8123 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8124 kvm_clear_interrupt_queue(vcpu);
8125 kvm_clear_exception_queue(vcpu);
664f8e26 8126 vcpu->arch.exception.pending = false;
448fa4a9 8127
42dbaa5a 8128 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8129 kvm_update_dr0123(vcpu);
6f43ed01 8130 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8131 kvm_update_dr6(vcpu);
42dbaa5a 8132 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8133 kvm_update_dr7(vcpu);
42dbaa5a 8134
1119022c
NA		 8135 vcpu->arch.cr2 = 0;
8136
3842d135 8137 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8138 vcpu->arch.apf.msr_val = 0;
c9aaa895 8139 vcpu->arch.st.msr_val = 0;
3842d135 8140
12f9a48f
GC		 8141 kvmclock_reset(vcpu);
8142
af585b92
GN		 8143 kvm_clear_async_pf_completion_queue(vcpu);
8144 kvm_async_pf_hash_reset(vcpu);
8145 vcpu->arch.apf.halted = false;
3842d135 8146
a554d207
WL		 8147 if (kvm_mpx_supported()) {
8148 void *mpx_state_buffer;
8149
8150 /*
8151 * To avoid have the INIT path from kvm_apic_has_events() that be
8152 * called with loaded FPU and does not let userspace fix the state.
8153 */
f775b13e
RR		 8154 if (init_event)
8155 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8156 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8157 XFEATURE_MASK_BNDREGS);
8158 if (mpx_state_buffer)
8159 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8160 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8161 XFEATURE_MASK_BNDCSR);
8162 if (mpx_state_buffer)
8163 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8164 if (init_event)
8165 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8166 }
8167
64d60670 8168 if (!init_event) {
d28bc9dd 8169 kvm_pmu_reset(vcpu);
64d60670 8170 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8171
8172 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8173 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8174
8175 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8176 }
f5132b01 8177
66f7b72e
JS		 8178 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8179 vcpu->arch.regs_avail = ~0;
8180 vcpu->arch.regs_dirty = ~0;
8181
a554d207
WL		 8182 vcpu->arch.ia32_xss = 0;
8183
d28bc9dd 8184 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8185}
8186
2b4a273b 8187void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8188{
8189 struct kvm_segment cs;
8190
8191 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8192 cs.selector = vector << 8;
8193 cs.base = vector << 12;
8194 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8195 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8196}
8197
13a34e06 8198int kvm_arch_hardware_enable(void)
e9b11c17 8199{
ca84d1a2
ZA		 8200 struct kvm *kvm;
8201 struct kvm_vcpu *vcpu;
8202 int i;
0dd6a6ed
ZA		 8203 int ret;
8204 u64 local_tsc;
8205 u64 max_tsc = 0;
8206 bool stable, backwards_tsc = false;
18863bdd
AK		 8207
8208 kvm_shared_msr_cpu_online();
13a34e06 8209 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8210 if (ret != 0)
8211 return ret;
8212
4ea1636b 8213 local_tsc = rdtsc();
b0c39dc6 8214 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8215 list_for_each_entry(kvm, &vm_list, vm_list) {
8216 kvm_for_each_vcpu(i, vcpu, kvm) {
8217 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8218 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8219 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8220 backwards_tsc = true;
8221 if (vcpu->arch.last_host_tsc > max_tsc)
8222 max_tsc = vcpu->arch.last_host_tsc;
8223 }
8224 }
8225 }
8226
8227 /*
8228 * Sometimes, even reliable TSCs go backwards. This happens on
8229 * platforms that reset TSC during suspend or hibernate actions, but
8230 * maintain synchronization. We must compensate. Fortunately, we can
8231 * detect that condition here, which happens early in CPU bringup,
8232 * before any KVM threads can be running. Unfortunately, we can't
8233 * bring the TSCs fully up to date with real time, as we aren't yet far
8234 * enough into CPU bringup that we know how much real time has actually
108b249c 8235 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8236 * variables that haven't been updated yet.
8237 *
8238 * So we simply find the maximum observed TSC above, then record the
8239 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8240 * the adjustment will be applied. Note that we accumulate
8241 * adjustments, in case multiple suspend cycles happen before some VCPU
8242 * gets a chance to run again. In the event that no KVM threads get a
8243 * chance to run, we will miss the entire elapsed period, as we'll have
8244 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8245 * loose cycle time. This isn't too big a deal, since the loss will be
8246 * uniform across all VCPUs (not to mention the scenario is extremely
8247 * unlikely). It is possible that a second hibernate recovery happens
8248 * much faster than a first, causing the observed TSC here to be
8249 * smaller; this would require additional padding adjustment, which is
8250 * why we set last_host_tsc to the local tsc observed here.
8251 *
8252 * N.B. - this code below runs only on platforms with reliable TSC,
8253 * as that is the only way backwards_tsc is set above. Also note
8254 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8255 * have the same delta_cyc adjustment applied if backwards_tsc
8256 * is detected. Note further, this adjustment is only done once,
8257 * as we reset last_host_tsc on all VCPUs to stop this from being
8258 * called multiple times (one for each physical CPU bringup).
8259 *
4a969980 8260 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8261 * will be compensated by the logic in vcpu_load, which sets the TSC to
8262 * catchup mode. This will catchup all VCPUs to real time, but cannot
8263 * guarantee that they stay in perfect synchronization.
8264 */
8265 if (backwards_tsc) {
8266 u64 delta_cyc = max_tsc - local_tsc;
8267 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8268 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8269 kvm_for_each_vcpu(i, vcpu, kvm) {
8270 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8271 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8272 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8273 }
8274
8275 /*
8276 * We have to disable TSC offset matching.. if you were
8277 * booting a VM while issuing an S4 host suspend....
8278 * you may have some problem. Solving this issue is
8279 * left as an exercise to the reader.
8280 */
8281 kvm->arch.last_tsc_nsec = 0;
8282 kvm->arch.last_tsc_write = 0;
8283 }
8284
8285 }
8286 return 0;
e9b11c17
ZX		 8287}
8288
13a34e06 8289void kvm_arch_hardware_disable(void)
e9b11c17 8290{
13a34e06
RK		 8291 kvm_x86_ops->hardware_disable();
8292 drop_user_return_notifiers();
e9b11c17
ZX		 8293}
8294
8295int kvm_arch_hardware_setup(void)
8296{
9e9c3fe4
NA		 8297 int r;
8298
8299 r = kvm_x86_ops->hardware_setup();
8300 if (r != 0)
8301 return r;
8302
35181e86
HZ		 8303 if (kvm_has_tsc_control) {
8304 /*
8305 * Make sure the user can only configure tsc_khz values that
8306 * fit into a signed integer.
8307 * A min value is not calculated needed because it will always
8308 * be 1 on all machines.
8309 */
8310 u64 max = min(0x7fffffffULL,
8311 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8312 kvm_max_guest_tsc_khz = max;
8313
ad721883 8314 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8315 }
ad721883 8316
9e9c3fe4
NA		 8317 kvm_init_msr_list();
8318 return 0;
e9b11c17
ZX		 8319}
8320
8321void kvm_arch_hardware_unsetup(void)
8322{
8323 kvm_x86_ops->hardware_unsetup();
8324}
8325
8326void kvm_arch_check_processor_compat(void *rtn)
8327{
8328 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8329}
8330
8331bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8332{
8333 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8334}
8335EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8336
8337bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8338{
8339 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8340}
8341
54e9818f 8342struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8343EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8344
e9b11c17
ZX		 8345int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8346{
8347 struct page *page;
e9b11c17
ZX		 8348 int r;
8349
b2a05fef 8350 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8351 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8352 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8353 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8354 else
a4535290 8355 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8356
8357 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8358 if (!page) {
8359 r = -ENOMEM;
8360 goto fail;
8361 }
ad312c7c 8362 vcpu->arch.pio_data = page_address(page);
e9b11c17 8363
cc578287 8364 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8365
e9b11c17
ZX		 8366 r = kvm_mmu_create(vcpu);
8367 if (r < 0)
8368 goto fail_free_pio_data;
8369
26de7988 8370 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8371 r = kvm_create_lapic(vcpu);
8372 if (r < 0)
8373 goto fail_mmu_destroy;
54e9818f
GN		 8374 } else
8375 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8376
890ca9ae
HY		 8377 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8378 GFP_KERNEL);
8379 if (!vcpu->arch.mce_banks) {
8380 r = -ENOMEM;
443c39bc 8381 goto fail_free_lapic;
890ca9ae
HY		 8382 }
8383 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8384
f1797359
WY		 8385 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8386 r = -ENOMEM;
f5f48ee1 8387 goto fail_free_mce_banks;
f1797359 8388 }
f5f48ee1 8389
0ee6a517 8390 fx_init(vcpu);
66f7b72e 8391
4344ee98 8392 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8393
5a4f55cd
EK		 8394 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8395
74545705
RK		 8396 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8397
af585b92 8398 kvm_async_pf_hash_reset(vcpu);
f5132b01 8399 kvm_pmu_init(vcpu);
af585b92 8400
1c1a9ce9 8401 vcpu->arch.pending_external_vector = -1;
de63ad4c 8402 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8403
5c919412
AS		 8404 kvm_hv_vcpu_init(vcpu);
8405
e9b11c17 8406 return 0;
0ee6a517 8407
f5f48ee1
SY		 8408fail_free_mce_banks:
8409 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8410fail_free_lapic:
8411 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8412fail_mmu_destroy:
8413 kvm_mmu_destroy(vcpu);
8414fail_free_pio_data:
ad312c7c 8415 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8416fail:
8417 return r;
8418}
8419
8420void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8421{
f656ce01
MT		 8422 int idx;
8423
1f4b34f8 8424 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8425 kvm_pmu_destroy(vcpu);
36cb93fd 8426 kfree(vcpu->arch.mce_banks);
e9b11c17 8427 kvm_free_lapic(vcpu);
f656ce01 8428 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8429 kvm_mmu_destroy(vcpu);
f656ce01 8430 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8431 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8432 if (!lapic_in_kernel(vcpu))
54e9818f 8433 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8434}
d19a9cd2 8435
e790d9ef
RK		 8436void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8437{
ae97a3b8 8438 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8439}
8440
e08b9637 8441int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8442{
e08b9637
CO		 8443 if (type)
8444 return -EINVAL;
8445
6ef768fa 8446 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8447 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8448 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8449 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8450 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8451
5550af4d
SY		 8452 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8453 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8454 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8455 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8456 &kvm->arch.irq_sources_bitmap);
5550af4d 8457
038f8c11 8458 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8459 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8460 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8461
108b249c 8462 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8463 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8464
7e44e449 8465 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8466 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8467
cbc0236a 8468 kvm_hv_init_vm(kvm);
0eb05bf2 8469 kvm_page_track_init(kvm);
13d268ca 8470 kvm_mmu_init_vm(kvm);
0eb05bf2 8471
03543133
SS		 8472 if (kvm_x86_ops->vm_init)
8473 return kvm_x86_ops->vm_init(kvm);
8474
d89f5eff 8475 return 0;
d19a9cd2
ZX		 8476}
8477
8478static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8479{
ec7660cc 8480 vcpu_load(vcpu);
d19a9cd2
ZX		 8481 kvm_mmu_unload(vcpu);
8482 vcpu_put(vcpu);
8483}
8484
8485static void kvm_free_vcpus(struct kvm *kvm)
8486{
8487 unsigned int i;
988a2cae 8488 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8489
8490 /*
8491 * Unpin any mmu pages first.
8492 */
af585b92
GN		 8493 kvm_for_each_vcpu(i, vcpu, kvm) {
8494 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8495 kvm_unload_vcpu_mmu(vcpu);
af585b92 8496 }
988a2cae
GN		 8497 kvm_for_each_vcpu(i, vcpu, kvm)
8498 kvm_arch_vcpu_free(vcpu);
8499
8500 mutex_lock(&kvm->lock);
8501 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8502 kvm->vcpus[i] = NULL;
d19a9cd2 8503
988a2cae
GN		 8504 atomic_set(&kvm->online_vcpus, 0);
8505 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8506}
8507
ad8ba2cd
SY		 8508void kvm_arch_sync_events(struct kvm *kvm)
8509{
332967a3 8510 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8511 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8512 kvm_free_pit(kvm);
ad8ba2cd
SY		 8513}
8514
1d8007bd 8515int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8516{
8517 int i, r;
25188b99 8518 unsigned long hva;
f0d648bd
PB		 8519 struct kvm_memslots *slots = kvm_memslots(kvm);
8520 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8521
8522 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8523 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8524 return -EINVAL;
9da0e4d5 8525
f0d648bd
PB		 8526 slot = id_to_memslot(slots, id);
8527 if (size) {
b21629da 8528 if (slot->npages)
f0d648bd
PB		 8529 return -EEXIST;
8530
8531 /*
8532 * MAP_SHARED to prevent internal slot pages from being moved
8533 * by fork()/COW.
8534 */
8535 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8536 MAP_SHARED | MAP_ANONYMOUS, 0);
8537 if (IS_ERR((void *)hva))
8538 return PTR_ERR((void *)hva);
8539 } else {
8540 if (!slot->npages)
8541 return 0;
8542
8543 hva = 0;
8544 }
8545
8546 old = *slot;
9da0e4d5 8547 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8548 struct kvm_userspace_memory_region m;
9da0e4d5 8549
1d8007bd
PB		 8550 m.slot = id | (i << 16);
8551 m.flags = 0;
8552 m.guest_phys_addr = gpa;
f0d648bd 8553 m.userspace_addr = hva;
1d8007bd 8554 m.memory_size = size;
9da0e4d5
PB		 8555 r = __kvm_set_memory_region(kvm, &m);
8556 if (r < 0)
8557 return r;
8558 }
8559
103c763c
EB		 8560 if (!size)
8561 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8562
9da0e4d5
PB		 8563 return 0;
8564}
8565EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8566
1d8007bd 8567int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8568{
8569 int r;
8570
8571 mutex_lock(&kvm->slots_lock);
1d8007bd 8572 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8573 mutex_unlock(&kvm->slots_lock);
8574
8575 return r;
8576}
8577EXPORT_SYMBOL_GPL(x86_set_memory_region);
8578
d19a9cd2
ZX		 8579void kvm_arch_destroy_vm(struct kvm *kvm)
8580{
27469d29
AH		 8581 if (current->mm == kvm->mm) {
8582 /*
8583 * Free memory regions allocated on behalf of userspace,
8584 * unless the the memory map has changed due to process exit
8585 * or fd copying.
8586 */
1d8007bd
PB		 8587 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8588 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8589 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8590 }
03543133
SS		 8591 if (kvm_x86_ops->vm_destroy)
8592 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8593 kvm_pic_destroy(kvm);
8594 kvm_ioapic_destroy(kvm);
d19a9cd2 8595 kvm_free_vcpus(kvm);
af1bae54 8596 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8597 kvm_mmu_uninit_vm(kvm);
2beb6dad 8598 kvm_page_track_cleanup(kvm);
cbc0236a 8599 kvm_hv_destroy_vm(kvm);
d19a9cd2 8600}
0de10343 8601
5587027c 8602void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8603 struct kvm_memory_slot *dont)
8604{
8605 int i;
8606
d89cc617
TY		 8607 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8608 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8609 kvfree(free->arch.rmap[i]);
d89cc617 8610 free->arch.rmap[i] = NULL;
77d11309 8611 }
d89cc617
TY		 8612 if (i == 0)
8613 continue;
8614
8615 if (!dont || free->arch.lpage_info[i - 1] !=
8616 dont->arch.lpage_info[i - 1]) {
548ef284 8617 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8618 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8619 }
8620 }
21ebbeda
XG		 8621
8622 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8623}
8624
5587027c
AK		 8625int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8626 unsigned long npages)
db3fe4eb
TY		 8627{
8628 int i;
8629
d89cc617 8630 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8631 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8632 unsigned long ugfn;
8633 int lpages;
d89cc617 8634 int level = i + 1;
db3fe4eb
TY		 8635
8636 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8637 slot->base_gfn, level) + 1;
8638
d89cc617 8639 slot->arch.rmap[i] =
a7c3e901 8640 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8641 if (!slot->arch.rmap[i])
77d11309 8642 goto out_free;
d89cc617
TY		 8643 if (i == 0)
8644 continue;
77d11309 8645
a7c3e901 8646 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8647 if (!linfo)
db3fe4eb
TY		 8648 goto out_free;
8649
92f94f1e
XG		 8650 slot->arch.lpage_info[i - 1] = linfo;
8651
db3fe4eb 8652 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8653 linfo[0].disallow_lpage = 1;
db3fe4eb 8654 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8655 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8656 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8657 /*
8658 * If the gfn and userspace address are not aligned wrt each
8659 * other, or if explicitly asked to, disable large page
8660 * support for this slot
8661 */
8662 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8663 !kvm_largepages_enabled()) {
8664 unsigned long j;
8665
8666 for (j = 0; j < lpages; ++j)
92f94f1e 8667 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8668 }
8669 }
8670
21ebbeda
XG		 8671 if (kvm_page_track_create_memslot(slot, npages))
8672 goto out_free;
8673
db3fe4eb
TY		 8674 return 0;
8675
8676out_free:
d89cc617 8677 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8678 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8679 slot->arch.rmap[i] = NULL;
8680 if (i == 0)
8681 continue;
8682
548ef284 8683 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8684 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8685 }
8686 return -ENOMEM;
8687}
8688
15f46015 8689void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8690{
e6dff7d1
TY		 8691 /*
8692 * memslots->generation has been incremented.
8693 * mmio generation may have reached its maximum value.
8694 */
54bf36aa 8695 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8696}
8697
f7784b8e
MT		 8698int kvm_arch_prepare_memory_region(struct kvm *kvm,
8699 struct kvm_memory_slot *memslot,
09170a49 8700 const struct kvm_userspace_memory_region *mem,
7b6195a9 8701 enum kvm_mr_change change)
0de10343 8702{
f7784b8e
MT		 8703 return 0;
8704}
8705
88178fd4
KH		 8706static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8707 struct kvm_memory_slot *new)
8708{
8709 /* Still write protect RO slot */
8710 if (new->flags & KVM_MEM_READONLY) {
8711 kvm_mmu_slot_remove_write_access(kvm, new);
8712 return;
8713 }
8714
8715 /*
8716 * Call kvm_x86_ops dirty logging hooks when they are valid.
8717 *
8718 * kvm_x86_ops->slot_disable_log_dirty is called when:
8719 *
8720 * - KVM_MR_CREATE with dirty logging is disabled
8721 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8722 *
8723 * The reason is, in case of PML, we need to set D-bit for any slots
8724 * with dirty logging disabled in order to eliminate unnecessary GPA
8725 * logging in PML buffer (and potential PML buffer full VMEXT). This
8726 * guarantees leaving PML enabled during guest's lifetime won't have
8727 * any additonal overhead from PML when guest is running with dirty
8728 * logging disabled for memory slots.
8729 *
8730 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8731 * to dirty logging mode.
8732 *
8733 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8734 *
8735 * In case of write protect:
8736 *
8737 * Write protect all pages for dirty logging.
8738 *
8739 * All the sptes including the large sptes which point to this
8740 * slot are set to readonly. We can not create any new large
8741 * spte on this slot until the end of the logging.
8742 *
8743 * See the comments in fast_page_fault().
8744 */
8745 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8746 if (kvm_x86_ops->slot_enable_log_dirty)
8747 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8748 else
8749 kvm_mmu_slot_remove_write_access(kvm, new);
8750 } else {
8751 if (kvm_x86_ops->slot_disable_log_dirty)
8752 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8753 }
8754}
8755
f7784b8e 8756void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8757 const struct kvm_userspace_memory_region *mem,
8482644a 8758 const struct kvm_memory_slot *old,
f36f3f28 8759 const struct kvm_memory_slot *new,
8482644a 8760 enum kvm_mr_change change)
f7784b8e 8761{
8482644a 8762 int nr_mmu_pages = 0;
f7784b8e 8763
48c0e4e9
XG		 8764 if (!kvm->arch.n_requested_mmu_pages)
8765 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8766
48c0e4e9 8767 if (nr_mmu_pages)
0de10343 8768 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8769
3ea3b7fa
WL		 8770 /*
8771 * Dirty logging tracks sptes in 4k granularity, meaning that large
8772 * sptes have to be split. If live migration is successful, the guest
8773 * in the source machine will be destroyed and large sptes will be
8774 * created in the destination. However, if the guest continues to run
8775 * in the source machine (for example if live migration fails), small
8776 * sptes will remain around and cause bad performance.
8777 *
8778 * Scan sptes if dirty logging has been stopped, dropping those
8779 * which can be collapsed into a single large-page spte. Later
8780 * page faults will create the large-page sptes.
8781 */
8782 if ((change != KVM_MR_DELETE) &&
8783 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8784 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8785 kvm_mmu_zap_collapsible_sptes(kvm, new);
8786
c972f3b1 8787 /*
88178fd4 8788 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8789 *
88178fd4
KH		 8790 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8791 * been zapped so no dirty logging staff is needed for old slot. For
8792 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8793 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8794 *
8795 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8796 */
88178fd4 8797 if (change != KVM_MR_DELETE)
f36f3f28 8798 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8799}
1d737c8a 8800
2df72e9b 8801void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8802{
6ca18b69 8803 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8804}
8805
2df72e9b
MT		 8806void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8807 struct kvm_memory_slot *slot)
8808{
ae7cd873 8809 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8810}
8811
5d9bc648
PB		 8812static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8813{
8814 if (!list_empty_careful(&vcpu->async_pf.done))
8815 return true;
8816
8817 if (kvm_apic_has_events(vcpu))
8818 return true;
8819
8820 if (vcpu->arch.pv.pv_unhalted)
8821 return true;
8822
a5f01f8e
WL		 8823 if (vcpu->arch.exception.pending)
8824 return true;
8825
47a66eed
Z		 8826 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8827 (vcpu->arch.nmi_pending &&
8828 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8829 return true;
8830
47a66eed
Z		 8831 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8832 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8833 return true;
8834
5d9bc648
PB		 8835 if (kvm_arch_interrupt_allowed(vcpu) &&
8836 kvm_cpu_has_interrupt(vcpu))
8837 return true;
8838
1f4b34f8
AS		 8839 if (kvm_hv_has_stimer_pending(vcpu))
8840 return true;
8841
5d9bc648
PB		 8842 return false;
8843}
8844
1d737c8a
ZX		 8845int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8846{
5d9bc648 8847 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8848}
5736199a 8849
199b5763
LM		 8850bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8851{
de63ad4c 8852 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8853}
8854
b6d33834 8855int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8856{
b6d33834 8857 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8858}
78646121
GN		 8859
8860int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8861{
8862 return kvm_x86_ops->interrupt_allowed(vcpu);
8863}
229456fc 8864
82b32774 8865unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8866{
82b32774
NA		 8867 if (is_64_bit_mode(vcpu))
8868 return kvm_rip_read(vcpu);
8869 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8870 kvm_rip_read(vcpu));
8871}
8872EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8873
82b32774
NA		 8874bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8875{
8876 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8877}
8878EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8879
94fe45da
JK		 8880unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8881{
8882 unsigned long rflags;
8883
8884 rflags = kvm_x86_ops->get_rflags(vcpu);
8885 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8886 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8887 return rflags;
8888}
8889EXPORT_SYMBOL_GPL(kvm_get_rflags);
8890
6addfc42 8891static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8892{
8893 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8894 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8895 rflags |= X86_EFLAGS_TF;
94fe45da 8896 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8897}
8898
8899void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8900{
8901 __kvm_set_rflags(vcpu, rflags);
3842d135 8902 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8903}
8904EXPORT_SYMBOL_GPL(kvm_set_rflags);
8905
56028d08
GN		 8906void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8907{
8908 int r;
8909
fb67e14f 8910 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8911 work->wakeup_all)
56028d08
GN		 8912 return;
8913
8914 r = kvm_mmu_reload(vcpu);
8915 if (unlikely(r))
8916 return;
8917
fb67e14f
XG		 8918 if (!vcpu->arch.mmu.direct_map &&
8919 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8920 return;
8921
56028d08
GN		 8922 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8923}
8924
af585b92
GN		 8925static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8926{
8927 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8928}
8929
8930static inline u32 kvm_async_pf_next_probe(u32 key)
8931{
8932 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8933}
8934
8935static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8936{
8937 u32 key = kvm_async_pf_hash_fn(gfn);
8938
8939 while (vcpu->arch.apf.gfns[key] != ~0)
8940 key = kvm_async_pf_next_probe(key);
8941
8942 vcpu->arch.apf.gfns[key] = gfn;
8943}
8944
8945static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8946{
8947 int i;
8948 u32 key = kvm_async_pf_hash_fn(gfn);
8949
8950 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8951 (vcpu->arch.apf.gfns[key] != gfn &&
8952 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8953 key = kvm_async_pf_next_probe(key);
8954
8955 return key;
8956}
8957
8958bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8959{
8960 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8961}
8962
8963static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8964{
8965 u32 i, j, k;
8966
8967 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8968 while (true) {
8969 vcpu->arch.apf.gfns[i] = ~0;
8970 do {
8971 j = kvm_async_pf_next_probe(j);
8972 if (vcpu->arch.apf.gfns[j] == ~0)
8973 return;
8974 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8975 /*
8976 * k lies cyclically in ]i,j]
8977 * | i.k.j |
8978 * |....j i.k.| or |.k..j i...|
8979 */
8980 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8981 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8982 i = j;
8983 }
8984}
8985
7c90705b
GN		 8986static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8987{
4e335d9e
PB		 8988
8989 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8990 sizeof(val));
7c90705b
GN		 8991}
8992
9a6e7c39
WL		 8993static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8994{
8995
8996 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8997 sizeof(u32));
8998}
8999
af585b92
GN		 9000void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9001 struct kvm_async_pf *work)
9002{
6389ee94
AK		 9003 struct x86_exception fault;
9004
7c90705b 9005 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9006 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9007
9008 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9009 (vcpu->arch.apf.send_user_only &&
9010 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9011 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9012 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9013 fault.vector = PF_VECTOR;
9014 fault.error_code_valid = true;
9015 fault.error_code = 0;
9016 fault.nested_page_fault = false;
9017 fault.address = work->arch.token;
adfe20fb 9018 fault.async_page_fault = true;
6389ee94 9019 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9020 }
af585b92
GN		 9021}
9022
9023void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9024 struct kvm_async_pf *work)
9025{
6389ee94 9026 struct x86_exception fault;
9a6e7c39 9027 u32 val;
6389ee94 9028
f2e10669 9029 if (work->wakeup_all)
7c90705b
GN		 9030 work->arch.token = ~0; /* broadcast wakeup */
9031 else
9032 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9033 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9034
9a6e7c39
WL		 9035 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9036 !apf_get_user(vcpu, &val)) {
9037 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9038 vcpu->arch.exception.pending &&
9039 vcpu->arch.exception.nr == PF_VECTOR &&
9040 !apf_put_user(vcpu, 0)) {
9041 vcpu->arch.exception.injected = false;
9042 vcpu->arch.exception.pending = false;
9043 vcpu->arch.exception.nr = 0;
9044 vcpu->arch.exception.has_error_code = false;
9045 vcpu->arch.exception.error_code = 0;
9046 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9047 fault.vector = PF_VECTOR;
9048 fault.error_code_valid = true;
9049 fault.error_code = 0;
9050 fault.nested_page_fault = false;
9051 fault.address = work->arch.token;
9052 fault.async_page_fault = true;
9053 kvm_inject_page_fault(vcpu, &fault);
9054 }
7c90705b 9055 }
e6d53e3b 9056 vcpu->arch.apf.halted = false;
a4fa1635 9057 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9058}
9059
9060bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9061{
9062 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9063 return true;
9064 else
9bc1f09f 9065 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9066}
9067
5544eb9b
PB		 9068void kvm_arch_start_assignment(struct kvm *kvm)
9069{
9070 atomic_inc(&kvm->arch.assigned_device_count);
9071}
9072EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9073
9074void kvm_arch_end_assignment(struct kvm *kvm)
9075{
9076 atomic_dec(&kvm->arch.assigned_device_count);
9077}
9078EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9079
9080bool kvm_arch_has_assigned_device(struct kvm *kvm)
9081{
9082 return atomic_read(&kvm->arch.assigned_device_count);
9083}
9084EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9085
e0f0bbc5
AW		 9086void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9087{
9088 atomic_inc(&kvm->arch.noncoherent_dma_count);
9089}
9090EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9091
9092void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9093{
9094 atomic_dec(&kvm->arch.noncoherent_dma_count);
9095}
9096EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9097
9098bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9099{
9100 return atomic_read(&kvm->arch.noncoherent_dma_count);
9101}
9102EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9103
14717e20
AW		 9104bool kvm_arch_has_irq_bypass(void)
9105{
9106 return kvm_x86_ops->update_pi_irte != NULL;
9107}
9108
87276880
FW		 9109int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9110 struct irq_bypass_producer *prod)
9111{
9112 struct kvm_kernel_irqfd *irqfd =
9113 container_of(cons, struct kvm_kernel_irqfd, consumer);
9114
14717e20 9115 irqfd->producer = prod;
87276880 9116
14717e20
AW		 9117 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9118 prod->irq, irqfd->gsi, 1);
87276880
FW		 9119}
9120
9121void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9122 struct irq_bypass_producer *prod)
9123{
9124 int ret;
9125 struct kvm_kernel_irqfd *irqfd =
9126 container_of(cons, struct kvm_kernel_irqfd, consumer);
9127
87276880
FW		 9128 WARN_ON(irqfd->producer != prod);
9129 irqfd->producer = NULL;
9130
9131 /*
9132 * When producer of consumer is unregistered, we change back to
9133 * remapped mode, so we can re-use the current implementation
bb3541f1 9134 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9135 * int this case doesn't want to receive the interrupts.
9136 */
9137 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9138 if (ret)
9139 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9140 " fails: %d\n", irqfd->consumer.token, ret);
9141}
9142
9143int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9144 uint32_t guest_irq, bool set)
9145{
9146 if (!kvm_x86_ops->update_pi_irte)
9147 return -EINVAL;
9148
9149 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9150}
9151
52004014
FW		 9152bool kvm_vector_hashing_enabled(void)
9153{
9154 return vector_hashing;
9155}
9156EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9157
229456fc 9158EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9159EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9160EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9161EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9162EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9163EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9164EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9165EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9166EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9167EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9168EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9169EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9170EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9171EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9172EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9173EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9174EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9175EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9176EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)