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kvm: Fix nonsense handling of compat ioctl
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
aec51dc4 49#include <trace/events/kvm.h>
2ed152af 50
229456fc
MT		 51#define CREATE_TRACE_POINTS
52#include "trace.h"
043405e1 53
24f1e32c 54#include <asm/debugreg.h>
d825ed0a 55#include <asm/msr.h>
a5f61300 56#include <asm/desc.h>
0bed3b56 57#include <asm/mtrr.h>
890ca9ae 58#include <asm/mce.h>
7cf30855 59#include <asm/i387.h>
1361b83a 60#include <asm/fpu-internal.h> /* Ugh! */
98918833 61#include <asm/xcr.h>
1d5f066e 62#include <asm/pvclock.h>
217fc9cf 63#include <asm/div64.h>
043405e1 64
313a3dc7 65#define MAX_IO_MSRS 256
890ca9ae 66#define KVM_MAX_MCE_BANKS 32
5854dbca 67#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 68
0f65dd70
AK		 69#define emul_to_vcpu(ctxt) \
70 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
1260edbe
LJ		 77static
78u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 79#else
1260edbe 80static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 81#endif
313a3dc7 82
ba1389b7
AK		 83#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 85
cb142eb7 86static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 87static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
476bc001
RR		 92static bool ignore_msrs = 0;
93module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 94
92a1f12d
JR		 95bool kvm_has_tsc_control;
96EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97u32 kvm_max_guest_tsc_khz;
98EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
cc578287
ZA		 100/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101static u32 tsc_tolerance_ppm = 250;
102module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103
18863bdd
AK		 104#define KVM_NR_SHARED_MSRS 16
105
106struct kvm_shared_msrs_global {
107 int nr;
2bf78fa7 108 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111struct kvm_shared_msrs {
112 struct user_return_notifier urn;
113 bool registered;
2bf78fa7
SY		 114 struct kvm_shared_msr_values {
115 u64 host;
116 u64 curr;
117 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 118};
119
120static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122
417bc304 123struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 124 { "pf_fixed", VCPU_STAT(pf_fixed) },
125 { "pf_guest", VCPU_STAT(pf_guest) },
126 { "tlb_flush", VCPU_STAT(tlb_flush) },
127 { "invlpg", VCPU_STAT(invlpg) },
128 { "exits", VCPU_STAT(exits) },
129 { "io_exits", VCPU_STAT(io_exits) },
130 { "mmio_exits", VCPU_STAT(mmio_exits) },
131 { "signal_exits", VCPU_STAT(signal_exits) },
132 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 133 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 134 { "halt_exits", VCPU_STAT(halt_exits) },
135 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 136 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 137 { "request_irq", VCPU_STAT(request_irq_exits) },
138 { "irq_exits", VCPU_STAT(irq_exits) },
139 { "host_state_reload", VCPU_STAT(host_state_reload) },
140 { "efer_reload", VCPU_STAT(efer_reload) },
141 { "fpu_reload", VCPU_STAT(fpu_reload) },
142 { "insn_emulation", VCPU_STAT(insn_emulation) },
143 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 144 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 145 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 146 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150 { "mmu_flooded", VM_STAT(mmu_flooded) },
151 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 152 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 153 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 154 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 155 { "largepages", VM_STAT(lpages) },
417bc304
HB		 156 { NULL }
157};
158
2acf923e
DC		 159u64 __read_mostly host_xcr0;
160
d6aa1000
AK		 161int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
162
af585b92
GN		 163static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
164{
165 int i;
166 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
167 vcpu->arch.apf.gfns[i] = ~0;
168}
169
18863bdd
AK		 170static void kvm_on_user_return(struct user_return_notifier *urn)
171{
172 unsigned slot;
18863bdd
AK		 173 struct kvm_shared_msrs *locals
174 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 175 struct kvm_shared_msr_values *values;
18863bdd
AK		 176
177 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 178 values = &locals->values[slot];
179 if (values->host != values->curr) {
180 wrmsrl(shared_msrs_global.msrs[slot], values->host);
181 values->curr = values->host;
18863bdd
AK		 182 }
183 }
184 locals->registered = false;
185 user_return_notifier_unregister(urn);
186}
187
2bf78fa7 188static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 189{
2bf78fa7 190 struct kvm_shared_msrs *smsr;
18863bdd
AK		 191 u64 value;
192
2bf78fa7
SY		 193 smsr = &__get_cpu_var(shared_msrs);
194 /* only read, and nobody should modify it at this time,
195 * so don't need lock */
196 if (slot >= shared_msrs_global.nr) {
197 printk(KERN_ERR "kvm: invalid MSR slot!");
198 return;
199 }
200 rdmsrl_safe(msr, &value);
201 smsr->values[slot].host = value;
202 smsr->values[slot].curr = value;
203}
204
205void kvm_define_shared_msr(unsigned slot, u32 msr)
206{
18863bdd
AK		 207 if (slot >= shared_msrs_global.nr)
208 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 209 shared_msrs_global.msrs[slot] = msr;
210 /* we need ensured the shared_msr_global have been updated */
211 smp_wmb();
18863bdd
AK		 212}
213EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
214
215static void kvm_shared_msr_cpu_online(void)
216{
217 unsigned i;
18863bdd
AK		 218
219 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 220 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 221}
222
d5696725 223void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 224{
225 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226
2bf78fa7 227 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 228 return;
2bf78fa7
SY		 229 smsr->values[slot].curr = value;
230 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 231 if (!smsr->registered) {
232 smsr->urn.on_user_return = kvm_on_user_return;
233 user_return_notifier_register(&smsr->urn);
234 smsr->registered = true;
235 }
236}
237EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
238
3548bab5
AK		 239static void drop_user_return_notifiers(void *ignore)
240{
241 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
242
243 if (smsr->registered)
244 kvm_on_user_return(&smsr->urn);
245}
246
6866b83e
CO		 247u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
248{
249 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 250 return vcpu->arch.apic_base;
6866b83e 251 else
ad312c7c 252 return vcpu->arch.apic_base;
6866b83e
CO		 253}
254EXPORT_SYMBOL_GPL(kvm_get_apic_base);
255
256void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
257{
258 /* TODO: reserve bits check */
259 if (irqchip_in_kernel(vcpu->kvm))
260 kvm_lapic_set_base(vcpu, data);
261 else
ad312c7c 262 vcpu->arch.apic_base = data;
6866b83e
CO		 263}
264EXPORT_SYMBOL_GPL(kvm_set_apic_base);
265
3fd28fce
ED		 266#define EXCPT_BENIGN 0
267#define EXCPT_CONTRIBUTORY 1
268#define EXCPT_PF 2
269
270static int exception_class(int vector)
271{
272 switch (vector) {
273 case PF_VECTOR:
274 return EXCPT_PF;
275 case DE_VECTOR:
276 case TS_VECTOR:
277 case NP_VECTOR:
278 case SS_VECTOR:
279 case GP_VECTOR:
280 return EXCPT_CONTRIBUTORY;
281 default:
282 break;
283 }
284 return EXCPT_BENIGN;
285}
286
287static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 288 unsigned nr, bool has_error, u32 error_code,
289 bool reinject)
3fd28fce
ED		 290{
291 u32 prev_nr;
292 int class1, class2;
293
3842d135
AK		 294 kvm_make_request(KVM_REQ_EVENT, vcpu);
295
3fd28fce
ED		 296 if (!vcpu->arch.exception.pending) {
297 queue:
298 vcpu->arch.exception.pending = true;
299 vcpu->arch.exception.has_error_code = has_error;
300 vcpu->arch.exception.nr = nr;
301 vcpu->arch.exception.error_code = error_code;
3f0fd292 302 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 303 return;
304 }
305
306 /* to check exception */
307 prev_nr = vcpu->arch.exception.nr;
308 if (prev_nr == DF_VECTOR) {
309 /* triple fault -> shutdown */
a8eeb04a 310 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 311 return;
312 }
313 class1 = exception_class(prev_nr);
314 class2 = exception_class(nr);
315 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
316 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
317 /* generate double fault per SDM Table 5-5 */
318 vcpu->arch.exception.pending = true;
319 vcpu->arch.exception.has_error_code = true;
320 vcpu->arch.exception.nr = DF_VECTOR;
321 vcpu->arch.exception.error_code = 0;
322 } else
323 /* replace previous exception with a new one in a hope
324 that instruction re-execution will regenerate lost
325 exception */
326 goto queue;
327}
328
298101da
AK		 329void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
ce7ddec4 331 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 332}
333EXPORT_SYMBOL_GPL(kvm_queue_exception);
334
ce7ddec4
JR		 335void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
336{
337 kvm_multiple_exception(vcpu, nr, false, 0, true);
338}
339EXPORT_SYMBOL_GPL(kvm_requeue_exception);
340
db8fcefa 341void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 342{
db8fcefa
AP		 343 if (err)
344 kvm_inject_gp(vcpu, 0);
345 else
346 kvm_x86_ops->skip_emulated_instruction(vcpu);
347}
348EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 349
6389ee94 350void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 351{
352 ++vcpu->stat.pf_guest;
6389ee94
AK		 353 vcpu->arch.cr2 = fault->address;
354 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 355}
27d6c865 356EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 357
6389ee94 358void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 359{
6389ee94
AK		 360 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
361 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 362 else
6389ee94 363 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 364}
365
3419ffc8
SY		 366void kvm_inject_nmi(struct kvm_vcpu *vcpu)
367{
7460fb4a
AK		 368 atomic_inc(&vcpu->arch.nmi_queued);
369 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 370}
371EXPORT_SYMBOL_GPL(kvm_inject_nmi);
372
298101da
AK		 373void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374{
ce7ddec4 375 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 376}
377EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
378
ce7ddec4
JR		 379void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
380{
381 kvm_multiple_exception(vcpu, nr, true, error_code, true);
382}
383EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
384
0a79b009
AK		 385/*
386 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
387 * a #GP and return false.
388 */
389bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 390{
0a79b009
AK		 391 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
392 return true;
393 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
394 return false;
298101da 395}
0a79b009 396EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 397
ec92fe44
JR		 398/*
399 * This function will be used to read from the physical memory of the currently
400 * running guest. The difference to kvm_read_guest_page is that this function
401 * can read from guest physical or from the guest's guest physical memory.
402 */
403int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
404 gfn_t ngfn, void *data, int offset, int len,
405 u32 access)
406{
407 gfn_t real_gfn;
408 gpa_t ngpa;
409
410 ngpa = gfn_to_gpa(ngfn);
411 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
412 if (real_gfn == UNMAPPED_GVA)
413 return -EFAULT;
414
415 real_gfn = gpa_to_gfn(real_gfn);
416
417 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
418}
419EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
420
3d06b8bf
JR		 421int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
422 void *data, int offset, int len, u32 access)
423{
424 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
425 data, offset, len, access);
426}
427
a03490ed
CO		 428/*
429 * Load the pae pdptrs. Return true is they are all valid.
430 */
ff03a073 431int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 432{
433 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
434 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
435 int i;
436 int ret;
ff03a073 437 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 438
ff03a073
JR		 439 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
440 offset * sizeof(u64), sizeof(pdpte),
441 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 442 if (ret < 0) {
443 ret = 0;
444 goto out;
445 }
446 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 447 if (is_present_gpte(pdpte[i]) &&
20c466b5 448 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 449 ret = 0;
450 goto out;
451 }
452 }
453 ret = 1;
454
ff03a073 455 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_avail);
458 __set_bit(VCPU_EXREG_PDPTR,
459 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 460out:
a03490ed
CO		 461
462 return ret;
463}
cc4b6871 464EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 465
d835dfec
AK		 466static bool pdptrs_changed(struct kvm_vcpu *vcpu)
467{
ff03a073 468 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 469 bool changed = true;
3d06b8bf
JR		 470 int offset;
471 gfn_t gfn;
d835dfec
AK		 472 int r;
473
474 if (is_long_mode(vcpu) || !is_pae(vcpu))
475 return false;
476
6de4f3ad
AK		 477 if (!test_bit(VCPU_EXREG_PDPTR,
478 (unsigned long *)&vcpu->arch.regs_avail))
479 return true;
480
9f8fe504
AK		 481 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
482 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 483 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
484 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 485 if (r < 0)
486 goto out;
ff03a073 487 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 488out:
d835dfec
AK		 489
490 return changed;
491}
492
49a9b07e 493int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 494{
aad82703
SY		 495 unsigned long old_cr0 = kvm_read_cr0(vcpu);
496 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
497 X86_CR0_CD | X86_CR0_NW;
498
f9a48e6a
AK		 499 cr0 |= X86_CR0_ET;
500
ab344828 501#ifdef CONFIG_X86_64
0f12244f
GN		 502 if (cr0 & 0xffffffff00000000UL)
503 return 1;
ab344828
GN		 504#endif
505
506 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 507
0f12244f
GN		 508 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
509 return 1;
a03490ed 510
0f12244f
GN		 511 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
512 return 1;
a03490ed
CO		 513
514 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
515#ifdef CONFIG_X86_64
f6801dff 516 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 517 int cs_db, cs_l;
518
0f12244f
GN		 519 if (!is_pae(vcpu))
520 return 1;
a03490ed 521 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 522 if (cs_l)
523 return 1;
a03490ed
CO		 524 } else
525#endif
ff03a073 526 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 527 kvm_read_cr3(vcpu)))
0f12244f 528 return 1;
a03490ed
CO		 529 }
530
ad756a16
MJ		 531 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
532 return 1;
533
a03490ed 534 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 535
d170c419 536 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 537 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 538 kvm_async_pf_hash_reset(vcpu);
539 }
e5f3f027 540
aad82703
SY		 541 if ((cr0 ^ old_cr0) & update_bits)
542 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 543 return 0;
544}
2d3ad1f4 545EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 546
2d3ad1f4 547void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 548{
49a9b07e 549 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 550}
2d3ad1f4 551EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 552
2acf923e
DC		 553int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
554{
555 u64 xcr0;
556
557 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
558 if (index != XCR_XFEATURE_ENABLED_MASK)
559 return 1;
560 xcr0 = xcr;
561 if (kvm_x86_ops->get_cpl(vcpu) != 0)
562 return 1;
563 if (!(xcr0 & XSTATE_FP))
564 return 1;
565 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
566 return 1;
567 if (xcr0 & ~host_xcr0)
568 return 1;
569 vcpu->arch.xcr0 = xcr0;
570 vcpu->guest_xcr0_loaded = 0;
571 return 0;
572}
573
574int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
575{
576 if (__kvm_set_xcr(vcpu, index, xcr)) {
577 kvm_inject_gp(vcpu, 0);
578 return 1;
579 }
580 return 0;
581}
582EXPORT_SYMBOL_GPL(kvm_set_xcr);
583
a83b29c6 584int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 585{
fc78f519 586 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 587 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
588 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 589 if (cr4 & CR4_RESERVED_BITS)
590 return 1;
a03490ed 591
2acf923e
DC		 592 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
593 return 1;
594
c68b734f
YW		 595 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
596 return 1;
597
74dc2b4f
YW		 598 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
599 return 1;
600
a03490ed 601 if (is_long_mode(vcpu)) {
0f12244f
GN		 602 if (!(cr4 & X86_CR4_PAE))
603 return 1;
a2edf57f
AK		 604 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
605 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 606 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
607 kvm_read_cr3(vcpu)))
0f12244f
GN		 608 return 1;
609
ad756a16
MJ		 610 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
611 if (!guest_cpuid_has_pcid(vcpu))
612 return 1;
613
614 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
615 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
616 return 1;
617 }
618
5e1746d6 619 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 620 return 1;
a03490ed 621
ad756a16
MJ		 622 if (((cr4 ^ old_cr4) & pdptr_bits) ||
623 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 624 kvm_mmu_reset_context(vcpu);
0f12244f 625
2acf923e 626 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 627 kvm_update_cpuid(vcpu);
2acf923e 628
0f12244f
GN		 629 return 0;
630}
2d3ad1f4 631EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 632
2390218b 633int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 634{
9f8fe504 635 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 636 kvm_mmu_sync_roots(vcpu);
d835dfec 637 kvm_mmu_flush_tlb(vcpu);
0f12244f 638 return 0;
d835dfec
AK		 639 }
640
a03490ed 641 if (is_long_mode(vcpu)) {
ad756a16
MJ		 642 if (kvm_read_cr4(vcpu) & X86_CR4_PCIDE) {
643 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
644 return 1;
645 } else
646 if (cr3 & CR3_L_MODE_RESERVED_BITS)
647 return 1;
a03490ed
CO		 648 } else {
649 if (is_pae(vcpu)) {
0f12244f
GN		 650 if (cr3 & CR3_PAE_RESERVED_BITS)
651 return 1;
ff03a073
JR		 652 if (is_paging(vcpu) &&
653 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 654 return 1;
a03490ed
CO		 655 }
656 /*
657 * We don't check reserved bits in nonpae mode, because
658 * this isn't enforced, and VMware depends on this.
659 */
660 }
661
a03490ed
CO		 662 /*
663 * Does the new cr3 value map to physical memory? (Note, we
664 * catch an invalid cr3 even in real-mode, because it would
665 * cause trouble later on when we turn on paging anyway.)
666 *
667 * A real CPU would silently accept an invalid cr3 and would
668 * attempt to use it - with largely undefined (and often hard
669 * to debug) behavior on the guest side.
670 */
671 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 672 return 1;
673 vcpu->arch.cr3 = cr3;
aff48baa 674 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 675 vcpu->arch.mmu.new_cr3(vcpu);
676 return 0;
677}
2d3ad1f4 678EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 679
eea1cff9 680int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 681{
0f12244f
GN		 682 if (cr8 & CR8_RESERVED_BITS)
683 return 1;
a03490ed
CO		 684 if (irqchip_in_kernel(vcpu->kvm))
685 kvm_lapic_set_tpr(vcpu, cr8);
686 else
ad312c7c 687 vcpu->arch.cr8 = cr8;
0f12244f
GN		 688 return 0;
689}
2d3ad1f4 690EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 691
2d3ad1f4 692unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 693{
694 if (irqchip_in_kernel(vcpu->kvm))
695 return kvm_lapic_get_cr8(vcpu);
696 else
ad312c7c 697 return vcpu->arch.cr8;
a03490ed 698}
2d3ad1f4 699EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 700
338dbc97 701static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 702{
703 switch (dr) {
704 case 0 ... 3:
705 vcpu->arch.db[dr] = val;
706 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
707 vcpu->arch.eff_db[dr] = val;
708 break;
709 case 4:
338dbc97
GN		 710 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
711 return 1; /* #UD */
020df079
GN		 712 /* fall through */
713 case 6:
338dbc97
GN		 714 if (val & 0xffffffff00000000ULL)
715 return -1; /* #GP */
020df079
GN		 716 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
717 break;
718 case 5:
338dbc97
GN		 719 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
720 return 1; /* #UD */
020df079
GN		 721 /* fall through */
722 default: /* 7 */
338dbc97
GN		 723 if (val & 0xffffffff00000000ULL)
724 return -1; /* #GP */
020df079
GN		 725 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
726 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
727 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
728 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
729 }
730 break;
731 }
732
733 return 0;
734}
338dbc97
GN		 735
736int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
737{
738 int res;
739
740 res = __kvm_set_dr(vcpu, dr, val);
741 if (res > 0)
742 kvm_queue_exception(vcpu, UD_VECTOR);
743 else if (res < 0)
744 kvm_inject_gp(vcpu, 0);
745
746 return res;
747}
020df079
GN		 748EXPORT_SYMBOL_GPL(kvm_set_dr);
749
338dbc97 750static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 751{
752 switch (dr) {
753 case 0 ... 3:
754 *val = vcpu->arch.db[dr];
755 break;
756 case 4:
338dbc97 757 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 758 return 1;
020df079
GN		 759 /* fall through */
760 case 6:
761 *val = vcpu->arch.dr6;
762 break;
763 case 5:
338dbc97 764 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 765 return 1;
020df079
GN		 766 /* fall through */
767 default: /* 7 */
768 *val = vcpu->arch.dr7;
769 break;
770 }
771
772 return 0;
773}
338dbc97
GN		 774
775int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
776{
777 if (_kvm_get_dr(vcpu, dr, val)) {
778 kvm_queue_exception(vcpu, UD_VECTOR);
779 return 1;
780 }
781 return 0;
782}
020df079
GN		 783EXPORT_SYMBOL_GPL(kvm_get_dr);
784
022cd0e8
AK		 785bool kvm_rdpmc(struct kvm_vcpu *vcpu)
786{
787 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
788 u64 data;
789 int err;
790
791 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
792 if (err)
793 return err;
794 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
795 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
796 return err;
797}
798EXPORT_SYMBOL_GPL(kvm_rdpmc);
799
043405e1
CO		 800/*
801 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
802 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
803 *
804 * This list is modified at module load time to reflect the
e3267cbb
GC		 805 * capabilities of the host cpu. This capabilities test skips MSRs that are
806 * kvm-specific. Those are put in the beginning of the list.
043405e1 807 */
e3267cbb 808
439793d4 809#define KVM_SAVE_MSRS_BEGIN 10
043405e1 810static u32 msrs_to_save[] = {
e3267cbb 811 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 812 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 813 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 814 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 815 MSR_KVM_PV_EOI_EN,
043405e1 816 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 817 MSR_STAR,
043405e1
CO		 818#ifdef CONFIG_X86_64
819 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
820#endif
e90aa41e 821 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 822};
823
824static unsigned num_msrs_to_save;
825
826static u32 emulated_msrs[] = {
a3e06bbe 827 MSR_IA32_TSCDEADLINE,
043405e1 828 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 829 MSR_IA32_MCG_STATUS,
830 MSR_IA32_MCG_CTL,
043405e1
CO		 831};
832
b69e8cae 833static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 834{
aad82703
SY		 835 u64 old_efer = vcpu->arch.efer;
836
b69e8cae
RJ		 837 if (efer & efer_reserved_bits)
838 return 1;
15c4a640
CO		 839
840 if (is_paging(vcpu)
b69e8cae
RJ		 841 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
842 return 1;
15c4a640 843
1b2fd70c
AG		 844 if (efer & EFER_FFXSR) {
845 struct kvm_cpuid_entry2 *feat;
846
847 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 848 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
849 return 1;
1b2fd70c
AG		 850 }
851
d8017474
AG		 852 if (efer & EFER_SVME) {
853 struct kvm_cpuid_entry2 *feat;
854
855 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 856 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
857 return 1;
d8017474
AG		 858 }
859
15c4a640 860 efer &= ~EFER_LMA;
f6801dff 861 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 862
a3d204e2
SY		 863 kvm_x86_ops->set_efer(vcpu, efer);
864
9645bb56 865 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 866
aad82703
SY		 867 /* Update reserved bits */
868 if ((efer ^ old_efer) & EFER_NX)
869 kvm_mmu_reset_context(vcpu);
870
b69e8cae 871 return 0;
15c4a640
CO		 872}
873
f2b4b7dd
JR		 874void kvm_enable_efer_bits(u64 mask)
875{
876 efer_reserved_bits &= ~mask;
877}
878EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
879
880
15c4a640
CO		 881/*
882 * Writes msr value into into the appropriate "register".
883 * Returns 0 on success, non-0 otherwise.
884 * Assumes vcpu_load() was already called.
885 */
886int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
887{
888 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
889}
890
313a3dc7
CO		 891/*
892 * Adapt set_msr() to msr_io()'s calling convention
893 */
894static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
895{
896 return kvm_set_msr(vcpu, index, *data);
897}
898
18068523
GOC		 899static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
900{
9ed3c444
AK		 901 int version;
902 int r;
50d0a0f9 903 struct pvclock_wall_clock wc;
923de3cf 904 struct timespec boot;
18068523
GOC		 905
906 if (!wall_clock)
907 return;
908
9ed3c444
AK		 909 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
910 if (r)
911 return;
912
913 if (version & 1)
914 ++version; /* first time write, random junk */
915
916 ++version;
18068523 917
18068523
GOC		 918 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
919
50d0a0f9
GH		 920 /*
921 * The guest calculates current wall clock time by adding
34c238a1 922 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 923 * wall clock specified here. guest system time equals host
924 * system time for us, thus we must fill in host boot time here.
925 */
923de3cf 926 getboottime(&boot);
50d0a0f9 927
4b648665
BR		 928 if (kvm->arch.kvmclock_offset) {
929 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
930 boot = timespec_sub(boot, ts);
931 }
50d0a0f9
GH		 932 wc.sec = boot.tv_sec;
933 wc.nsec = boot.tv_nsec;
934 wc.version = version;
18068523
GOC		 935
936 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
937
938 version++;
939 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 940}
941
50d0a0f9
GH		 942static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
943{
944 uint32_t quotient, remainder;
945
946 /* Don't try to replace with do_div(), this one calculates
947 * "(dividend << 32) / divisor" */
948 __asm__ ( "divl %4"
949 : "=a" (quotient), "=d" (remainder)
950 : "0" (0), "1" (dividend), "r" (divisor) );
951 return quotient;
952}
953
5f4e3f88
ZA		 954static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
955 s8 *pshift, u32 *pmultiplier)
50d0a0f9 956{
5f4e3f88 957 uint64_t scaled64;
50d0a0f9
GH		 958 int32_t shift = 0;
959 uint64_t tps64;
960 uint32_t tps32;
961
5f4e3f88
ZA		 962 tps64 = base_khz * 1000LL;
963 scaled64 = scaled_khz * 1000LL;
50933623 964 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 965 tps64 >>= 1;
966 shift--;
967 }
968
969 tps32 = (uint32_t)tps64;
50933623
JK		 970 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
971 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 972 scaled64 >>= 1;
973 else
974 tps32 <<= 1;
50d0a0f9
GH		 975 shift++;
976 }
977
5f4e3f88
ZA		 978 *pshift = shift;
979 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 980
5f4e3f88
ZA		 981 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
982 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 983}
984
759379dd
ZA		 985static inline u64 get_kernel_ns(void)
986{
987 struct timespec ts;
988
989 WARN_ON(preemptible());
990 ktime_get_ts(&ts);
991 monotonic_to_bootbased(&ts);
992 return timespec_to_ns(&ts);
50d0a0f9
GH		 993}
994
c8076604 995static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 996unsigned long max_tsc_khz;
c8076604 997
cc578287 998static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 999{
cc578287
ZA		 1000 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1001 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1002}
1003
cc578287 1004static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1005{
cc578287
ZA		 1006 u64 v = (u64)khz * (1000000 + ppm);
1007 do_div(v, 1000000);
1008 return v;
1e993611
JR		 1009}
1010
cc578287 1011static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1012{
cc578287
ZA		 1013 u32 thresh_lo, thresh_hi;
1014 int use_scaling = 0;
217fc9cf 1015
c285545f
ZA		 1016 /* Compute a scale to convert nanoseconds in TSC cycles */
1017 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1018 &vcpu->arch.virtual_tsc_shift,
1019 &vcpu->arch.virtual_tsc_mult);
1020 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1021
1022 /*
1023 * Compute the variation in TSC rate which is acceptable
1024 * within the range of tolerance and decide if the
1025 * rate being applied is within that bounds of the hardware
1026 * rate. If so, no scaling or compensation need be done.
1027 */
1028 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1029 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1030 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1031 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1032 use_scaling = 1;
1033 }
1034 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1035}
1036
1037static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1038{
e26101b1 1039 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1040 vcpu->arch.virtual_tsc_mult,
1041 vcpu->arch.virtual_tsc_shift);
e26101b1 1042 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1043 return tsc;
1044}
1045
99e3e30a
ZA		 1046void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1047{
1048 struct kvm *kvm = vcpu->kvm;
f38e098f 1049 u64 offset, ns, elapsed;
99e3e30a 1050 unsigned long flags;
02626b6a 1051 s64 usdiff;
99e3e30a 1052
038f8c11 1053 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1054 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1055 ns = get_kernel_ns();
f38e098f 1056 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1057
1058 /* n.b - signed multiplication and division required */
02626b6a 1059 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1060#ifdef CONFIG_X86_64
02626b6a 1061 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6
ZA		 1062#else
1063 /* do_div() only does unsigned */
1064 asm("idivl %2; xor %%edx, %%edx"
02626b6a
MT		 1065 : "=A"(usdiff)
1066 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1067#endif
02626b6a
MT		 1068 do_div(elapsed, 1000);
1069 usdiff -= elapsed;
1070 if (usdiff < 0)
1071 usdiff = -usdiff;
f38e098f
ZA		 1072
1073 /*
5d3cb0f6
ZA		 1074 * Special case: TSC write with a small delta (1 second) of virtual
1075 * cycle time against real time is interpreted as an attempt to
1076 * synchronize the CPU.
1077 *
1078 * For a reliable TSC, we can match TSC offsets, and for an unstable
1079 * TSC, we add elapsed time in this computation. We could let the
1080 * compensation code attempt to catch up if we fall behind, but
1081 * it's better to try to match offsets from the beginning.
1082 */
02626b6a 1083 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1084 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1085 if (!check_tsc_unstable()) {
e26101b1 1086 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1087 pr_debug("kvm: matched tsc offset for %llu\n", data);
1088 } else {
857e4099 1089 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1090 data += delta;
1091 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1092 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1093 }
e26101b1
ZA		 1094 } else {
1095 /*
1096 * We split periods of matched TSC writes into generations.
1097 * For each generation, we track the original measured
1098 * nanosecond time, offset, and write, so if TSCs are in
1099 * sync, we can match exact offset, and if not, we can match
1100 * exact software computaion in compute_guest_tsc()
1101 *
1102 * These values are tracked in kvm->arch.cur_xxx variables.
1103 */
1104 kvm->arch.cur_tsc_generation++;
1105 kvm->arch.cur_tsc_nsec = ns;
1106 kvm->arch.cur_tsc_write = data;
1107 kvm->arch.cur_tsc_offset = offset;
1108 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1109 kvm->arch.cur_tsc_generation, data);
f38e098f 1110 }
e26101b1
ZA		 1111
1112 /*
1113 * We also track th most recent recorded KHZ, write and time to
1114 * allow the matching interval to be extended at each write.
1115 */
f38e098f
ZA		 1116 kvm->arch.last_tsc_nsec = ns;
1117 kvm->arch.last_tsc_write = data;
5d3cb0f6 1118 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1119
1120 /* Reset of TSC must disable overshoot protection below */
1121 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1122 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1123
1124 /* Keep track of which generation this VCPU has synchronized to */
1125 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1126 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1127 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1128
1129 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1130 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a 1131}
e26101b1 1132
99e3e30a
ZA		 1133EXPORT_SYMBOL_GPL(kvm_write_tsc);
1134
34c238a1 1135static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1136{
18068523
GOC		 1137 unsigned long flags;
1138 struct kvm_vcpu_arch *vcpu = &v->arch;
1139 void *shared_kaddr;
463656c0 1140 unsigned long this_tsc_khz;
1d5f066e
ZA		 1141 s64 kernel_ns, max_kernel_ns;
1142 u64 tsc_timestamp;
18068523 1143
18068523
GOC		 1144 /* Keep irq disabled to prevent changes to the clock */
1145 local_irq_save(flags);
d5c1785d 1146 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1147 kernel_ns = get_kernel_ns();
cc578287 1148 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
8cfdc000 1149 if (unlikely(this_tsc_khz == 0)) {
c285545f 1150 local_irq_restore(flags);
34c238a1 1151 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1152 return 1;
1153 }
18068523 1154
c285545f
ZA		 1155 /*
1156 * We may have to catch up the TSC to match elapsed wall clock
1157 * time for two reasons, even if kvmclock is used.
1158 * 1) CPU could have been running below the maximum TSC rate
1159 * 2) Broken TSC compensation resets the base at each VCPU
1160 * entry to avoid unknown leaps of TSC even when running
1161 * again on the same CPU. This may cause apparent elapsed
1162 * time to disappear, and the guest to stand still or run
1163 * very slowly.
1164 */
1165 if (vcpu->tsc_catchup) {
1166 u64 tsc = compute_guest_tsc(v, kernel_ns);
1167 if (tsc > tsc_timestamp) {
f1e2b260 1168 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1169 tsc_timestamp = tsc;
1170 }
50d0a0f9
GH		 1171 }
1172
18068523
GOC		 1173 local_irq_restore(flags);
1174
c285545f
ZA		 1175 if (!vcpu->time_page)
1176 return 0;
18068523 1177
1d5f066e
ZA		 1178 /*
1179 * Time as measured by the TSC may go backwards when resetting the base
1180 * tsc_timestamp. The reason for this is that the TSC resolution is
1181 * higher than the resolution of the other clock scales. Thus, many
1182 * possible measurments of the TSC correspond to one measurement of any
1183 * other clock, and so a spread of values is possible. This is not a
1184 * problem for the computation of the nanosecond clock; with TSC rates
1185 * around 1GHZ, there can only be a few cycles which correspond to one
1186 * nanosecond value, and any path through this code will inevitably
1187 * take longer than that. However, with the kernel_ns value itself,
1188 * the precision may be much lower, down to HZ granularity. If the
1189 * first sampling of TSC against kernel_ns ends in the low part of the
1190 * range, and the second in the high end of the range, we can get:
1191 *
1192 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1193 *
1194 * As the sampling errors potentially range in the thousands of cycles,
1195 * it is possible such a time value has already been observed by the
1196 * guest. To protect against this, we must compute the system time as
1197 * observed by the guest and ensure the new system time is greater.
1198 */
1199 max_kernel_ns = 0;
b183aa58 1200 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1201 max_kernel_ns = vcpu->last_guest_tsc -
1202 vcpu->hv_clock.tsc_timestamp;
1203 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1204 vcpu->hv_clock.tsc_to_system_mul,
1205 vcpu->hv_clock.tsc_shift);
1206 max_kernel_ns += vcpu->last_kernel_ns;
1207 }
afbcf7ab 1208
e48672fa 1209 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1210 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1211 &vcpu->hv_clock.tsc_shift,
1212 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1213 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1214 }
1215
1d5f066e
ZA		 1216 if (max_kernel_ns > kernel_ns)
1217 kernel_ns = max_kernel_ns;
1218
8cfdc000 1219 /* With all the info we got, fill in the values */
1d5f066e 1220 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1221 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1222 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1223 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1224 vcpu->hv_clock.flags = 0;
1225
18068523
GOC		 1226 /*
1227 * The interface expects us to write an even number signaling that the
1228 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1229 * state, we just increase by 2 at the end.
18068523 1230 */
50d0a0f9 1231 vcpu->hv_clock.version += 2;
18068523 1232
8fd75e12 1233 shared_kaddr = kmap_atomic(vcpu->time_page);
18068523
GOC		 1234
1235 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1236 sizeof(vcpu->hv_clock));
18068523 1237
8fd75e12 1238 kunmap_atomic(shared_kaddr);
18068523
GOC		 1239
1240 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1241 return 0;
c8076604
GH		 1242}
1243
9ba075a6
AK		 1244static bool msr_mtrr_valid(unsigned msr)
1245{
1246 switch (msr) {
1247 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1248 case MSR_MTRRfix64K_00000:
1249 case MSR_MTRRfix16K_80000:
1250 case MSR_MTRRfix16K_A0000:
1251 case MSR_MTRRfix4K_C0000:
1252 case MSR_MTRRfix4K_C8000:
1253 case MSR_MTRRfix4K_D0000:
1254 case MSR_MTRRfix4K_D8000:
1255 case MSR_MTRRfix4K_E0000:
1256 case MSR_MTRRfix4K_E8000:
1257 case MSR_MTRRfix4K_F0000:
1258 case MSR_MTRRfix4K_F8000:
1259 case MSR_MTRRdefType:
1260 case MSR_IA32_CR_PAT:
1261 return true;
1262 case 0x2f8:
1263 return true;
1264 }
1265 return false;
1266}
1267
d6289b93
MT		 1268static bool valid_pat_type(unsigned t)
1269{
1270 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1271}
1272
1273static bool valid_mtrr_type(unsigned t)
1274{
1275 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1276}
1277
1278static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1279{
1280 int i;
1281
1282 if (!msr_mtrr_valid(msr))
1283 return false;
1284
1285 if (msr == MSR_IA32_CR_PAT) {
1286 for (i = 0; i < 8; i++)
1287 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1288 return false;
1289 return true;
1290 } else if (msr == MSR_MTRRdefType) {
1291 if (data & ~0xcff)
1292 return false;
1293 return valid_mtrr_type(data & 0xff);
1294 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1295 for (i = 0; i < 8 ; i++)
1296 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1297 return false;
1298 return true;
1299 }
1300
1301 /* variable MTRRs */
1302 return valid_mtrr_type(data & 0xff);
1303}
1304
9ba075a6
AK		 1305static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1306{
0bed3b56
SY		 1307 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1308
d6289b93 1309 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1310 return 1;
1311
0bed3b56
SY		 1312 if (msr == MSR_MTRRdefType) {
1313 vcpu->arch.mtrr_state.def_type = data;
1314 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1315 } else if (msr == MSR_MTRRfix64K_00000)
1316 p[0] = data;
1317 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1318 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1319 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1320 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1321 else if (msr == MSR_IA32_CR_PAT)
1322 vcpu->arch.pat = data;
1323 else { /* Variable MTRRs */
1324 int idx, is_mtrr_mask;
1325 u64 *pt;
1326
1327 idx = (msr - 0x200) / 2;
1328 is_mtrr_mask = msr - 0x200 - 2 * idx;
1329 if (!is_mtrr_mask)
1330 pt =
1331 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1332 else
1333 pt =
1334 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1335 *pt = data;
1336 }
1337
1338 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1339 return 0;
1340}
15c4a640 1341
890ca9ae 1342static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1343{
890ca9ae
HY		 1344 u64 mcg_cap = vcpu->arch.mcg_cap;
1345 unsigned bank_num = mcg_cap & 0xff;
1346
15c4a640 1347 switch (msr) {
15c4a640 1348 case MSR_IA32_MCG_STATUS:
890ca9ae 1349 vcpu->arch.mcg_status = data;
15c4a640 1350 break;
c7ac679c 1351 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1352 if (!(mcg_cap & MCG_CTL_P))
1353 return 1;
1354 if (data != 0 && data != ~(u64)0)
1355 return -1;
1356 vcpu->arch.mcg_ctl = data;
1357 break;
1358 default:
1359 if (msr >= MSR_IA32_MC0_CTL &&
1360 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1361 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1362 /* only 0 or all 1s can be written to IA32_MCi_CTL
1363 * some Linux kernels though clear bit 10 in bank 4 to
1364 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1365 * this to avoid an uncatched #GP in the guest
1366 */
890ca9ae 1367 if ((offset & 0x3) == 0 &&
114be429 1368 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1369 return -1;
1370 vcpu->arch.mce_banks[offset] = data;
1371 break;
1372 }
1373 return 1;
1374 }
1375 return 0;
1376}
1377
ffde22ac
ES		 1378static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1379{
1380 struct kvm *kvm = vcpu->kvm;
1381 int lm = is_long_mode(vcpu);
1382 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1383 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1384 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1385 : kvm->arch.xen_hvm_config.blob_size_32;
1386 u32 page_num = data & ~PAGE_MASK;
1387 u64 page_addr = data & PAGE_MASK;
1388 u8 *page;
1389 int r;
1390
1391 r = -E2BIG;
1392 if (page_num >= blob_size)
1393 goto out;
1394 r = -ENOMEM;
ff5c2c03
SL		 1395 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1396 if (IS_ERR(page)) {
1397 r = PTR_ERR(page);
ffde22ac 1398 goto out;
ff5c2c03 1399 }
ffde22ac
ES		 1400 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1401 goto out_free;
1402 r = 0;
1403out_free:
1404 kfree(page);
1405out:
1406 return r;
1407}
1408
55cd8e5a
GN		 1409static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1410{
1411 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1412}
1413
1414static bool kvm_hv_msr_partition_wide(u32 msr)
1415{
1416 bool r = false;
1417 switch (msr) {
1418 case HV_X64_MSR_GUEST_OS_ID:
1419 case HV_X64_MSR_HYPERCALL:
1420 r = true;
1421 break;
1422 }
1423
1424 return r;
1425}
1426
1427static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1428{
1429 struct kvm *kvm = vcpu->kvm;
1430
1431 switch (msr) {
1432 case HV_X64_MSR_GUEST_OS_ID:
1433 kvm->arch.hv_guest_os_id = data;
1434 /* setting guest os id to zero disables hypercall page */
1435 if (!kvm->arch.hv_guest_os_id)
1436 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1437 break;
1438 case HV_X64_MSR_HYPERCALL: {
1439 u64 gfn;
1440 unsigned long addr;
1441 u8 instructions[4];
1442
1443 /* if guest os id is not set hypercall should remain disabled */
1444 if (!kvm->arch.hv_guest_os_id)
1445 break;
1446 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1447 kvm->arch.hv_hypercall = data;
1448 break;
1449 }
1450 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1451 addr = gfn_to_hva(kvm, gfn);
1452 if (kvm_is_error_hva(addr))
1453 return 1;
1454 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1455 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1456 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1457 return 1;
1458 kvm->arch.hv_hypercall = data;
1459 break;
1460 }
1461 default:
a737f256
CD		 1462 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1463 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1464 return 1;
1465 }
1466 return 0;
1467}
1468
1469static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1470{
10388a07
GN		 1471 switch (msr) {
1472 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1473 unsigned long addr;
55cd8e5a 1474
10388a07
GN		 1475 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1476 vcpu->arch.hv_vapic = data;
1477 break;
1478 }
1479 addr = gfn_to_hva(vcpu->kvm, data >>
1480 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1481 if (kvm_is_error_hva(addr))
1482 return 1;
8b0cedff 1483 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1484 return 1;
1485 vcpu->arch.hv_vapic = data;
1486 break;
1487 }
1488 case HV_X64_MSR_EOI:
1489 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1490 case HV_X64_MSR_ICR:
1491 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1492 case HV_X64_MSR_TPR:
1493 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1494 default:
a737f256
CD		 1495 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1496 "data 0x%llx\n", msr, data);
10388a07
GN		 1497 return 1;
1498 }
1499
1500 return 0;
55cd8e5a
GN		 1501}
1502
344d9588
GN		 1503static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1504{
1505 gpa_t gpa = data & ~0x3f;
1506
6adba527
GN		 1507 /* Bits 2:5 are resrved, Should be zero */
1508 if (data & 0x3c)
344d9588
GN		 1509 return 1;
1510
1511 vcpu->arch.apf.msr_val = data;
1512
1513 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1514 kvm_clear_async_pf_completion_queue(vcpu);
1515 kvm_async_pf_hash_reset(vcpu);
1516 return 0;
1517 }
1518
1519 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1520 return 1;
1521
6adba527 1522 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1523 kvm_async_pf_wakeup_all(vcpu);
1524 return 0;
1525}
1526
12f9a48f
GC		 1527static void kvmclock_reset(struct kvm_vcpu *vcpu)
1528{
1529 if (vcpu->arch.time_page) {
1530 kvm_release_page_dirty(vcpu->arch.time_page);
1531 vcpu->arch.time_page = NULL;
1532 }
1533}
1534
c9aaa895
GC		 1535static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1536{
1537 u64 delta;
1538
1539 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1540 return;
1541
1542 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1543 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1544 vcpu->arch.st.accum_steal = delta;
1545}
1546
1547static void record_steal_time(struct kvm_vcpu *vcpu)
1548{
1549 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1550 return;
1551
1552 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1553 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1554 return;
1555
1556 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1557 vcpu->arch.st.steal.version += 2;
1558 vcpu->arch.st.accum_steal = 0;
1559
1560 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1561 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1562}
1563
15c4a640
CO		 1564int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1565{
5753785f
GN		 1566 bool pr = false;
1567
15c4a640 1568 switch (msr) {
15c4a640 1569 case MSR_EFER:
b69e8cae 1570 return set_efer(vcpu, data);
8f1589d9
AP		 1571 case MSR_K7_HWCR:
1572 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1573 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1574 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1575 if (data != 0) {
a737f256
CD		 1576 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1577 data);
8f1589d9
AP		 1578 return 1;
1579 }
15c4a640 1580 break;
f7c6d140
AP		 1581 case MSR_FAM10H_MMIO_CONF_BASE:
1582 if (data != 0) {
a737f256
CD		 1583 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1584 "0x%llx\n", data);
f7c6d140
AP		 1585 return 1;
1586 }
15c4a640 1587 break;
c323c0e5 1588 case MSR_AMD64_NB_CFG:
c7ac679c 1589 break;
b5e2fec0
AG		 1590 case MSR_IA32_DEBUGCTLMSR:
1591 if (!data) {
1592 /* We support the non-activated case already */
1593 break;
1594 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1595 /* Values other than LBR and BTF are vendor-specific,
1596 thus reserved and should throw a #GP */
1597 return 1;
1598 }
a737f256
CD		 1599 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1600 __func__, data);
b5e2fec0 1601 break;
15c4a640
CO		 1602 case MSR_IA32_UCODE_REV:
1603 case MSR_IA32_UCODE_WRITE:
61a6bd67 1604 case MSR_VM_HSAVE_PA:
6098ca93 1605 case MSR_AMD64_PATCH_LOADER:
15c4a640 1606 break;
9ba075a6
AK		 1607 case 0x200 ... 0x2ff:
1608 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1609 case MSR_IA32_APICBASE:
1610 kvm_set_apic_base(vcpu, data);
1611 break;
0105d1a5
GN		 1612 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1613 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1614 case MSR_IA32_TSCDEADLINE:
1615 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1616 break;
15c4a640 1617 case MSR_IA32_MISC_ENABLE:
ad312c7c 1618 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1619 break;
11c6bffa 1620 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1621 case MSR_KVM_WALL_CLOCK:
1622 vcpu->kvm->arch.wall_clock = data;
1623 kvm_write_wall_clock(vcpu->kvm, data);
1624 break;
11c6bffa 1625 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1626 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1627 kvmclock_reset(vcpu);
18068523
GOC		 1628
1629 vcpu->arch.time = data;
c285545f 1630 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1631
1632 /* we verify if the enable bit is set... */
1633 if (!(data & 1))
1634 break;
1635
1636 /* ...but clean it before doing the actual write */
1637 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1638
18068523
GOC		 1639 vcpu->arch.time_page =
1640 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1641
1642 if (is_error_page(vcpu->arch.time_page)) {
1643 kvm_release_page_clean(vcpu->arch.time_page);
1644 vcpu->arch.time_page = NULL;
1645 }
18068523
GOC		 1646 break;
1647 }
344d9588
GN		 1648 case MSR_KVM_ASYNC_PF_EN:
1649 if (kvm_pv_enable_async_pf(vcpu, data))
1650 return 1;
1651 break;
c9aaa895
GC		 1652 case MSR_KVM_STEAL_TIME:
1653
1654 if (unlikely(!sched_info_on()))
1655 return 1;
1656
1657 if (data & KVM_STEAL_RESERVED_MASK)
1658 return 1;
1659
1660 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1661 data & KVM_STEAL_VALID_BITS))
1662 return 1;
1663
1664 vcpu->arch.st.msr_val = data;
1665
1666 if (!(data & KVM_MSR_ENABLED))
1667 break;
1668
1669 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1670
1671 preempt_disable();
1672 accumulate_steal_time(vcpu);
1673 preempt_enable();
1674
1675 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1676
1677 break;
ae7a2a3f
MT		 1678 case MSR_KVM_PV_EOI_EN:
1679 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1680 return 1;
1681 break;
c9aaa895 1682
890ca9ae
HY		 1683 case MSR_IA32_MCG_CTL:
1684 case MSR_IA32_MCG_STATUS:
1685 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1686 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1687
1688 /* Performance counters are not protected by a CPUID bit,
1689 * so we should check all of them in the generic path for the sake of
1690 * cross vendor migration.
1691 * Writing a zero into the event select MSRs disables them,
1692 * which we perfectly emulate ;-). Any other value should be at least
1693 * reported, some guests depend on them.
1694 */
71db6023
AP		 1695 case MSR_K7_EVNTSEL0:
1696 case MSR_K7_EVNTSEL1:
1697 case MSR_K7_EVNTSEL2:
1698 case MSR_K7_EVNTSEL3:
1699 if (data != 0)
a737f256
CD		 1700 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1701 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 1702 break;
1703 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1704 * so we ignore writes to make it happy.
1705 */
71db6023
AP		 1706 case MSR_K7_PERFCTR0:
1707 case MSR_K7_PERFCTR1:
1708 case MSR_K7_PERFCTR2:
1709 case MSR_K7_PERFCTR3:
a737f256
CD		 1710 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1711 "0x%x data 0x%llx\n", msr, data);
71db6023 1712 break;
5753785f
GN		 1713 case MSR_P6_PERFCTR0:
1714 case MSR_P6_PERFCTR1:
1715 pr = true;
1716 case MSR_P6_EVNTSEL0:
1717 case MSR_P6_EVNTSEL1:
1718 if (kvm_pmu_msr(vcpu, msr))
1719 return kvm_pmu_set_msr(vcpu, msr, data);
1720
1721 if (pr || data != 0)
a737f256
CD		 1722 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1723 "0x%x data 0x%llx\n", msr, data);
5753785f 1724 break;
84e0cefa
JS		 1725 case MSR_K7_CLK_CTL:
1726 /*
1727 * Ignore all writes to this no longer documented MSR.
1728 * Writes are only relevant for old K7 processors,
1729 * all pre-dating SVM, but a recommended workaround from
1730 * AMD for these chips. It is possible to speicify the
1731 * affected processor models on the command line, hence
1732 * the need to ignore the workaround.
1733 */
1734 break;
55cd8e5a
GN		 1735 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1736 if (kvm_hv_msr_partition_wide(msr)) {
1737 int r;
1738 mutex_lock(&vcpu->kvm->lock);
1739 r = set_msr_hyperv_pw(vcpu, msr, data);
1740 mutex_unlock(&vcpu->kvm->lock);
1741 return r;
1742 } else
1743 return set_msr_hyperv(vcpu, msr, data);
1744 break;
91c9c3ed 1745 case MSR_IA32_BBL_CR_CTL3:
1746 /* Drop writes to this legacy MSR -- see rdmsr
1747 * counterpart for further detail.
1748 */
a737f256 1749 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 1750 break;
2b036c6b
BO		 1751 case MSR_AMD64_OSVW_ID_LENGTH:
1752 if (!guest_cpuid_has_osvw(vcpu))
1753 return 1;
1754 vcpu->arch.osvw.length = data;
1755 break;
1756 case MSR_AMD64_OSVW_STATUS:
1757 if (!guest_cpuid_has_osvw(vcpu))
1758 return 1;
1759 vcpu->arch.osvw.status = data;
1760 break;
15c4a640 1761 default:
ffde22ac
ES		 1762 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1763 return xen_hvm_config(vcpu, data);
f5132b01
GN		 1764 if (kvm_pmu_msr(vcpu, msr))
1765 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068 1766 if (!ignore_msrs) {
a737f256
CD		 1767 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1768 msr, data);
ed85c068
AP		 1769 return 1;
1770 } else {
a737f256
CD		 1771 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1772 msr, data);
ed85c068
AP		 1773 break;
1774 }
15c4a640
CO		 1775 }
1776 return 0;
1777}
1778EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1779
1780
1781/*
1782 * Reads an msr value (of 'msr_index') into 'pdata'.
1783 * Returns 0 on success, non-0 otherwise.
1784 * Assumes vcpu_load() was already called.
1785 */
1786int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1787{
1788 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1789}
1790
9ba075a6
AK		 1791static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1792{
0bed3b56
SY		 1793 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1794
9ba075a6
AK		 1795 if (!msr_mtrr_valid(msr))
1796 return 1;
1797
0bed3b56
SY		 1798 if (msr == MSR_MTRRdefType)
1799 *pdata = vcpu->arch.mtrr_state.def_type +
1800 (vcpu->arch.mtrr_state.enabled << 10);
1801 else if (msr == MSR_MTRRfix64K_00000)
1802 *pdata = p[0];
1803 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1804 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1805 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1806 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1807 else if (msr == MSR_IA32_CR_PAT)
1808 *pdata = vcpu->arch.pat;
1809 else { /* Variable MTRRs */
1810 int idx, is_mtrr_mask;
1811 u64 *pt;
1812
1813 idx = (msr - 0x200) / 2;
1814 is_mtrr_mask = msr - 0x200 - 2 * idx;
1815 if (!is_mtrr_mask)
1816 pt =
1817 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1818 else
1819 pt =
1820 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1821 *pdata = *pt;
1822 }
1823
9ba075a6
AK		 1824 return 0;
1825}
1826
890ca9ae 1827static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1828{
1829 u64 data;
890ca9ae
HY		 1830 u64 mcg_cap = vcpu->arch.mcg_cap;
1831 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1832
1833 switch (msr) {
15c4a640
CO		 1834 case MSR_IA32_P5_MC_ADDR:
1835 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1836 data = 0;
1837 break;
15c4a640 1838 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1839 data = vcpu->arch.mcg_cap;
1840 break;
c7ac679c 1841 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1842 if (!(mcg_cap & MCG_CTL_P))
1843 return 1;
1844 data = vcpu->arch.mcg_ctl;
1845 break;
1846 case MSR_IA32_MCG_STATUS:
1847 data = vcpu->arch.mcg_status;
1848 break;
1849 default:
1850 if (msr >= MSR_IA32_MC0_CTL &&
1851 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1852 u32 offset = msr - MSR_IA32_MC0_CTL;
1853 data = vcpu->arch.mce_banks[offset];
1854 break;
1855 }
1856 return 1;
1857 }
1858 *pdata = data;
1859 return 0;
1860}
1861
55cd8e5a
GN		 1862static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1863{
1864 u64 data = 0;
1865 struct kvm *kvm = vcpu->kvm;
1866
1867 switch (msr) {
1868 case HV_X64_MSR_GUEST_OS_ID:
1869 data = kvm->arch.hv_guest_os_id;
1870 break;
1871 case HV_X64_MSR_HYPERCALL:
1872 data = kvm->arch.hv_hypercall;
1873 break;
1874 default:
a737f256 1875 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1876 return 1;
1877 }
1878
1879 *pdata = data;
1880 return 0;
1881}
1882
1883static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1884{
1885 u64 data = 0;
1886
1887 switch (msr) {
1888 case HV_X64_MSR_VP_INDEX: {
1889 int r;
1890 struct kvm_vcpu *v;
1891 kvm_for_each_vcpu(r, v, vcpu->kvm)
1892 if (v == vcpu)
1893 data = r;
1894 break;
1895 }
10388a07
GN		 1896 case HV_X64_MSR_EOI:
1897 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1898 case HV_X64_MSR_ICR:
1899 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1900 case HV_X64_MSR_TPR:
1901 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1902 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1903 data = vcpu->arch.hv_vapic;
1904 break;
55cd8e5a 1905 default:
a737f256 1906 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1907 return 1;
1908 }
1909 *pdata = data;
1910 return 0;
1911}
1912
890ca9ae
HY		 1913int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1914{
1915 u64 data;
1916
1917 switch (msr) {
890ca9ae 1918 case MSR_IA32_PLATFORM_ID:
15c4a640 1919 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1920 case MSR_IA32_DEBUGCTLMSR:
1921 case MSR_IA32_LASTBRANCHFROMIP:
1922 case MSR_IA32_LASTBRANCHTOIP:
1923 case MSR_IA32_LASTINTFROMIP:
1924 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1925 case MSR_K8_SYSCFG:
1926 case MSR_K7_HWCR:
61a6bd67 1927 case MSR_VM_HSAVE_PA:
9e699624 1928 case MSR_K7_EVNTSEL0:
1f3ee616 1929 case MSR_K7_PERFCTR0:
1fdbd48c 1930 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1931 case MSR_AMD64_NB_CFG:
f7c6d140 1932 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1933 data = 0;
1934 break;
5753785f
GN		 1935 case MSR_P6_PERFCTR0:
1936 case MSR_P6_PERFCTR1:
1937 case MSR_P6_EVNTSEL0:
1938 case MSR_P6_EVNTSEL1:
1939 if (kvm_pmu_msr(vcpu, msr))
1940 return kvm_pmu_get_msr(vcpu, msr, pdata);
1941 data = 0;
1942 break;
742bc670
MT		 1943 case MSR_IA32_UCODE_REV:
1944 data = 0x100000000ULL;
1945 break;
9ba075a6
AK		 1946 case MSR_MTRRcap:
1947 data = 0x500 | KVM_NR_VAR_MTRR;
1948 break;
1949 case 0x200 ... 0x2ff:
1950 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1951 case 0xcd: /* fsb frequency */
1952 data = 3;
1953 break;
7b914098
JS		 1954 /*
1955 * MSR_EBC_FREQUENCY_ID
1956 * Conservative value valid for even the basic CPU models.
1957 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1958 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1959 * and 266MHz for model 3, or 4. Set Core Clock
1960 * Frequency to System Bus Frequency Ratio to 1 (bits
1961 * 31:24) even though these are only valid for CPU
1962 * models > 2, however guests may end up dividing or
1963 * multiplying by zero otherwise.
1964 */
1965 case MSR_EBC_FREQUENCY_ID:
1966 data = 1 << 24;
1967 break;
15c4a640
CO		 1968 case MSR_IA32_APICBASE:
1969 data = kvm_get_apic_base(vcpu);
1970 break;
0105d1a5
GN		 1971 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1972 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1973 break;
a3e06bbe
LJ		 1974 case MSR_IA32_TSCDEADLINE:
1975 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1976 break;
15c4a640 1977 case MSR_IA32_MISC_ENABLE:
ad312c7c 1978 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1979 break;
847f0ad8
AG		 1980 case MSR_IA32_PERF_STATUS:
1981 /* TSC increment by tick */
1982 data = 1000ULL;
1983 /* CPU multiplier */
1984 data |= (((uint64_t)4ULL) << 40);
1985 break;
15c4a640 1986 case MSR_EFER:
f6801dff 1987 data = vcpu->arch.efer;
15c4a640 1988 break;
18068523 1989 case MSR_KVM_WALL_CLOCK:
11c6bffa 1990 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1991 data = vcpu->kvm->arch.wall_clock;
1992 break;
1993 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1994 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1995 data = vcpu->arch.time;
1996 break;
344d9588
GN		 1997 case MSR_KVM_ASYNC_PF_EN:
1998 data = vcpu->arch.apf.msr_val;
1999 break;
c9aaa895
GC		 2000 case MSR_KVM_STEAL_TIME:
2001 data = vcpu->arch.st.msr_val;
2002 break;
890ca9ae
HY		 2003 case MSR_IA32_P5_MC_ADDR:
2004 case MSR_IA32_P5_MC_TYPE:
2005 case MSR_IA32_MCG_CAP:
2006 case MSR_IA32_MCG_CTL:
2007 case MSR_IA32_MCG_STATUS:
2008 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2009 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2010 case MSR_K7_CLK_CTL:
2011 /*
2012 * Provide expected ramp-up count for K7. All other
2013 * are set to zero, indicating minimum divisors for
2014 * every field.
2015 *
2016 * This prevents guest kernels on AMD host with CPU
2017 * type 6, model 8 and higher from exploding due to
2018 * the rdmsr failing.
2019 */
2020 data = 0x20000000;
2021 break;
55cd8e5a
GN		 2022 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2023 if (kvm_hv_msr_partition_wide(msr)) {
2024 int r;
2025 mutex_lock(&vcpu->kvm->lock);
2026 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2027 mutex_unlock(&vcpu->kvm->lock);
2028 return r;
2029 } else
2030 return get_msr_hyperv(vcpu, msr, pdata);
2031 break;
91c9c3ed 2032 case MSR_IA32_BBL_CR_CTL3:
2033 /* This legacy MSR exists but isn't fully documented in current
2034 * silicon. It is however accessed by winxp in very narrow
2035 * scenarios where it sets bit #19, itself documented as
2036 * a "reserved" bit. Best effort attempt to source coherent
2037 * read data here should the balance of the register be
2038 * interpreted by the guest:
2039 *
2040 * L2 cache control register 3: 64GB range, 256KB size,
2041 * enabled, latency 0x1, configured
2042 */
2043 data = 0xbe702111;
2044 break;
2b036c6b
BO		 2045 case MSR_AMD64_OSVW_ID_LENGTH:
2046 if (!guest_cpuid_has_osvw(vcpu))
2047 return 1;
2048 data = vcpu->arch.osvw.length;
2049 break;
2050 case MSR_AMD64_OSVW_STATUS:
2051 if (!guest_cpuid_has_osvw(vcpu))
2052 return 1;
2053 data = vcpu->arch.osvw.status;
2054 break;
15c4a640 2055 default:
f5132b01
GN		 2056 if (kvm_pmu_msr(vcpu, msr))
2057 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2058 if (!ignore_msrs) {
a737f256 2059 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2060 return 1;
2061 } else {
a737f256 2062 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2063 data = 0;
2064 }
2065 break;
15c4a640
CO		 2066 }
2067 *pdata = data;
2068 return 0;
2069}
2070EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2071
313a3dc7
CO		 2072/*
2073 * Read or write a bunch of msrs. All parameters are kernel addresses.
2074 *
2075 * @return number of msrs set successfully.
2076 */
2077static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2078 struct kvm_msr_entry *entries,
2079 int (*do_msr)(struct kvm_vcpu *vcpu,
2080 unsigned index, u64 *data))
2081{
f656ce01 2082 int i, idx;
313a3dc7 2083
f656ce01 2084 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2085 for (i = 0; i < msrs->nmsrs; ++i)
2086 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2087 break;
f656ce01 2088 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2089
313a3dc7
CO		 2090 return i;
2091}
2092
2093/*
2094 * Read or write a bunch of msrs. Parameters are user addresses.
2095 *
2096 * @return number of msrs set successfully.
2097 */
2098static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2099 int (*do_msr)(struct kvm_vcpu *vcpu,
2100 unsigned index, u64 *data),
2101 int writeback)
2102{
2103 struct kvm_msrs msrs;
2104 struct kvm_msr_entry *entries;
2105 int r, n;
2106 unsigned size;
2107
2108 r = -EFAULT;
2109 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2110 goto out;
2111
2112 r = -E2BIG;
2113 if (msrs.nmsrs >= MAX_IO_MSRS)
2114 goto out;
2115
313a3dc7 2116 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2117 entries = memdup_user(user_msrs->entries, size);
2118 if (IS_ERR(entries)) {
2119 r = PTR_ERR(entries);
313a3dc7 2120 goto out;
ff5c2c03 2121 }
313a3dc7
CO		 2122
2123 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2124 if (r < 0)
2125 goto out_free;
2126
2127 r = -EFAULT;
2128 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2129 goto out_free;
2130
2131 r = n;
2132
2133out_free:
7a73c028 2134 kfree(entries);
313a3dc7
CO		 2135out:
2136 return r;
2137}
2138
018d00d2
ZX		 2139int kvm_dev_ioctl_check_extension(long ext)
2140{
2141 int r;
2142
2143 switch (ext) {
2144 case KVM_CAP_IRQCHIP:
2145 case KVM_CAP_HLT:
2146 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2147 case KVM_CAP_SET_TSS_ADDR:
07716717 2148 case KVM_CAP_EXT_CPUID:
c8076604 2149 case KVM_CAP_CLOCKSOURCE:
7837699f 2150 case KVM_CAP_PIT:
a28e4f5a 2151 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2152 case KVM_CAP_MP_STATE:
ed848624 2153 case KVM_CAP_SYNC_MMU:
a355c85c 2154 case KVM_CAP_USER_NMI:
52d939a0 2155 case KVM_CAP_REINJECT_CONTROL:
4925663a 2156 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2157 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2158 case KVM_CAP_IRQFD:
d34e6b17 2159 case KVM_CAP_IOEVENTFD:
c5ff41ce 2160 case KVM_CAP_PIT2:
e9f42757 2161 case KVM_CAP_PIT_STATE2:
b927a3ce 2162 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2163 case KVM_CAP_XEN_HVM:
afbcf7ab 2164 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2165 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2166 case KVM_CAP_HYPERV:
10388a07 2167 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2168 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2169 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2170 case KVM_CAP_DEBUGREGS:
d2be1651 2171 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2172 case KVM_CAP_XSAVE:
344d9588 2173 case KVM_CAP_ASYNC_PF:
92a1f12d 2174 case KVM_CAP_GET_TSC_KHZ:
07700a94 2175 case KVM_CAP_PCI_2_3:
1c0b28c2 2176 case KVM_CAP_KVMCLOCK_CTRL:
018d00d2
ZX		 2177 r = 1;
2178 break;
542472b5
LV		 2179 case KVM_CAP_COALESCED_MMIO:
2180 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2181 break;
774ead3a
AK		 2182 case KVM_CAP_VAPIC:
2183 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2184 break;
f725230a 2185 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2186 r = KVM_SOFT_MAX_VCPUS;
2187 break;
2188 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2189 r = KVM_MAX_VCPUS;
2190 break;
a988b910
AK		 2191 case KVM_CAP_NR_MEMSLOTS:
2192 r = KVM_MEMORY_SLOTS;
2193 break;
a68a6a72
MT		 2194 case KVM_CAP_PV_MMU: /* obsolete */
2195 r = 0;
2f333bcb 2196 break;
62c476c7 2197 case KVM_CAP_IOMMU:
a1b60c1c 2198 r = iommu_present(&pci_bus_type);
62c476c7 2199 break;
890ca9ae
HY		 2200 case KVM_CAP_MCE:
2201 r = KVM_MAX_MCE_BANKS;
2202 break;
2d5b5a66
SY		 2203 case KVM_CAP_XCRS:
2204 r = cpu_has_xsave;
2205 break;
92a1f12d
JR		 2206 case KVM_CAP_TSC_CONTROL:
2207 r = kvm_has_tsc_control;
2208 break;
4d25a066
JK		 2209 case KVM_CAP_TSC_DEADLINE_TIMER:
2210 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2211 break;
018d00d2
ZX		 2212 default:
2213 r = 0;
2214 break;
2215 }
2216 return r;
2217
2218}
2219
043405e1
CO		 2220long kvm_arch_dev_ioctl(struct file *filp,
2221 unsigned int ioctl, unsigned long arg)
2222{
2223 void __user *argp = (void __user *)arg;
2224 long r;
2225
2226 switch (ioctl) {
2227 case KVM_GET_MSR_INDEX_LIST: {
2228 struct kvm_msr_list __user *user_msr_list = argp;
2229 struct kvm_msr_list msr_list;
2230 unsigned n;
2231
2232 r = -EFAULT;
2233 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2234 goto out;
2235 n = msr_list.nmsrs;
2236 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2237 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2238 goto out;
2239 r = -E2BIG;
e125e7b6 2240 if (n < msr_list.nmsrs)
043405e1
CO		 2241 goto out;
2242 r = -EFAULT;
2243 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2244 num_msrs_to_save * sizeof(u32)))
2245 goto out;
e125e7b6 2246 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2247 &emulated_msrs,
2248 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2249 goto out;
2250 r = 0;
2251 break;
2252 }
674eea0f
AK		 2253 case KVM_GET_SUPPORTED_CPUID: {
2254 struct kvm_cpuid2 __user *cpuid_arg = argp;
2255 struct kvm_cpuid2 cpuid;
2256
2257 r = -EFAULT;
2258 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2259 goto out;
2260 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2261 cpuid_arg->entries);
674eea0f
AK		 2262 if (r)
2263 goto out;
2264
2265 r = -EFAULT;
2266 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2267 goto out;
2268 r = 0;
2269 break;
2270 }
890ca9ae
HY		 2271 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2272 u64 mce_cap;
2273
2274 mce_cap = KVM_MCE_CAP_SUPPORTED;
2275 r = -EFAULT;
2276 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2277 goto out;
2278 r = 0;
2279 break;
2280 }
043405e1
CO		 2281 default:
2282 r = -EINVAL;
2283 }
2284out:
2285 return r;
2286}
2287
f5f48ee1
SY		 2288static void wbinvd_ipi(void *garbage)
2289{
2290 wbinvd();
2291}
2292
2293static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2294{
2295 return vcpu->kvm->arch.iommu_domain &&
2296 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2297}
2298
313a3dc7
CO		 2299void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2300{
f5f48ee1
SY		 2301 /* Address WBINVD may be executed by guest */
2302 if (need_emulate_wbinvd(vcpu)) {
2303 if (kvm_x86_ops->has_wbinvd_exit())
2304 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2305 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2306 smp_call_function_single(vcpu->cpu,
2307 wbinvd_ipi, NULL, 1);
2308 }
2309
313a3dc7 2310 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2311
0dd6a6ed
ZA		 2312 /* Apply any externally detected TSC adjustments (due to suspend) */
2313 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2314 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2315 vcpu->arch.tsc_offset_adjustment = 0;
2316 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2317 }
8f6055cb 2318
48434c20 2319 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2320 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2321 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2322 if (tsc_delta < 0)
2323 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2324 if (check_tsc_unstable()) {
b183aa58
ZA		 2325 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2326 vcpu->arch.last_guest_tsc);
2327 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2328 vcpu->arch.tsc_catchup = 1;
c285545f 2329 }
1aa8ceef 2330 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2331 if (vcpu->cpu != cpu)
2332 kvm_migrate_timers(vcpu);
e48672fa 2333 vcpu->cpu = cpu;
6b7d7e76 2334 }
c9aaa895
GC		 2335
2336 accumulate_steal_time(vcpu);
2337 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2338}
2339
2340void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2341{
02daab21 2342 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2343 kvm_put_guest_fpu(vcpu);
6f526ec5 2344 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2345}
2346
313a3dc7
CO		 2347static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2348 struct kvm_lapic_state *s)
2349{
ad312c7c 2350 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2351
2352 return 0;
2353}
2354
2355static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2356 struct kvm_lapic_state *s)
2357{
ad312c7c 2358 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2359 kvm_apic_post_state_restore(vcpu);
cb142eb7 2360 update_cr8_intercept(vcpu);
313a3dc7
CO		 2361
2362 return 0;
2363}
2364
f77bc6a4
ZX		 2365static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2366 struct kvm_interrupt *irq)
2367{
2368 if (irq->irq < 0 || irq->irq >= 256)
2369 return -EINVAL;
2370 if (irqchip_in_kernel(vcpu->kvm))
2371 return -ENXIO;
f77bc6a4 2372
66fd3f7f 2373 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2374 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2375
f77bc6a4
ZX		 2376 return 0;
2377}
2378
c4abb7c9
JK		 2379static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2380{
c4abb7c9 2381 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2382
2383 return 0;
2384}
2385
b209749f
AK		 2386static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2387 struct kvm_tpr_access_ctl *tac)
2388{
2389 if (tac->flags)
2390 return -EINVAL;
2391 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2392 return 0;
2393}
2394
890ca9ae
HY		 2395static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2396 u64 mcg_cap)
2397{
2398 int r;
2399 unsigned bank_num = mcg_cap & 0xff, bank;
2400
2401 r = -EINVAL;
a9e38c3e 2402 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2403 goto out;
2404 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2405 goto out;
2406 r = 0;
2407 vcpu->arch.mcg_cap = mcg_cap;
2408 /* Init IA32_MCG_CTL to all 1s */
2409 if (mcg_cap & MCG_CTL_P)
2410 vcpu->arch.mcg_ctl = ~(u64)0;
2411 /* Init IA32_MCi_CTL to all 1s */
2412 for (bank = 0; bank < bank_num; bank++)
2413 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2414out:
2415 return r;
2416}
2417
2418static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2419 struct kvm_x86_mce *mce)
2420{
2421 u64 mcg_cap = vcpu->arch.mcg_cap;
2422 unsigned bank_num = mcg_cap & 0xff;
2423 u64 *banks = vcpu->arch.mce_banks;
2424
2425 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2426 return -EINVAL;
2427 /*
2428 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2429 * reporting is disabled
2430 */
2431 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2432 vcpu->arch.mcg_ctl != ~(u64)0)
2433 return 0;
2434 banks += 4 * mce->bank;
2435 /*
2436 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2437 * reporting is disabled for the bank
2438 */
2439 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2440 return 0;
2441 if (mce->status & MCI_STATUS_UC) {
2442 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2443 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2444 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2445 return 0;
2446 }
2447 if (banks[1] & MCI_STATUS_VAL)
2448 mce->status |= MCI_STATUS_OVER;
2449 banks[2] = mce->addr;
2450 banks[3] = mce->misc;
2451 vcpu->arch.mcg_status = mce->mcg_status;
2452 banks[1] = mce->status;
2453 kvm_queue_exception(vcpu, MC_VECTOR);
2454 } else if (!(banks[1] & MCI_STATUS_VAL)
2455 || !(banks[1] & MCI_STATUS_UC)) {
2456 if (banks[1] & MCI_STATUS_VAL)
2457 mce->status |= MCI_STATUS_OVER;
2458 banks[2] = mce->addr;
2459 banks[3] = mce->misc;
2460 banks[1] = mce->status;
2461 } else
2462 banks[1] |= MCI_STATUS_OVER;
2463 return 0;
2464}
2465
3cfc3092
JK		 2466static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2467 struct kvm_vcpu_events *events)
2468{
7460fb4a 2469 process_nmi(vcpu);
03b82a30
JK		 2470 events->exception.injected =
2471 vcpu->arch.exception.pending &&
2472 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2473 events->exception.nr = vcpu->arch.exception.nr;
2474 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2475 events->exception.pad = 0;
3cfc3092
JK		 2476 events->exception.error_code = vcpu->arch.exception.error_code;
2477
03b82a30
JK		 2478 events->interrupt.injected =
2479 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2480 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2481 events->interrupt.soft = 0;
48005f64
JK		 2482 events->interrupt.shadow =
2483 kvm_x86_ops->get_interrupt_shadow(vcpu,
2484 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2485
2486 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2487 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2488 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2489 events->nmi.pad = 0;
3cfc3092
JK		 2490
2491 events->sipi_vector = vcpu->arch.sipi_vector;
2492
dab4b911 2493 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2494 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2495 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2496 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2497}
2498
2499static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2500 struct kvm_vcpu_events *events)
2501{
dab4b911 2502 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2503 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2504 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2505 return -EINVAL;
2506
7460fb4a 2507 process_nmi(vcpu);
3cfc3092
JK		 2508 vcpu->arch.exception.pending = events->exception.injected;
2509 vcpu->arch.exception.nr = events->exception.nr;
2510 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2511 vcpu->arch.exception.error_code = events->exception.error_code;
2512
2513 vcpu->arch.interrupt.pending = events->interrupt.injected;
2514 vcpu->arch.interrupt.nr = events->interrupt.nr;
2515 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2516 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2517 kvm_x86_ops->set_interrupt_shadow(vcpu,
2518 events->interrupt.shadow);
3cfc3092
JK		 2519
2520 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2521 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2522 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2523 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2524
dab4b911
JK		 2525 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2526 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2527
3842d135
AK		 2528 kvm_make_request(KVM_REQ_EVENT, vcpu);
2529
3cfc3092
JK		 2530 return 0;
2531}
2532
a1efbe77
JK		 2533static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2534 struct kvm_debugregs *dbgregs)
2535{
a1efbe77
JK		 2536 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2537 dbgregs->dr6 = vcpu->arch.dr6;
2538 dbgregs->dr7 = vcpu->arch.dr7;
2539 dbgregs->flags = 0;
97e69aa6 2540 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2541}
2542
2543static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2544 struct kvm_debugregs *dbgregs)
2545{
2546 if (dbgregs->flags)
2547 return -EINVAL;
2548
a1efbe77
JK		 2549 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2550 vcpu->arch.dr6 = dbgregs->dr6;
2551 vcpu->arch.dr7 = dbgregs->dr7;
2552
a1efbe77
JK		 2553 return 0;
2554}
2555
2d5b5a66
SY		 2556static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2557 struct kvm_xsave *guest_xsave)
2558{
2559 if (cpu_has_xsave)
2560 memcpy(guest_xsave->region,
2561 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2562 xstate_size);
2d5b5a66
SY		 2563 else {
2564 memcpy(guest_xsave->region,
2565 &vcpu->arch.guest_fpu.state->fxsave,
2566 sizeof(struct i387_fxsave_struct));
2567 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2568 XSTATE_FPSSE;
2569 }
2570}
2571
2572static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2573 struct kvm_xsave *guest_xsave)
2574{
2575 u64 xstate_bv =
2576 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2577
2578 if (cpu_has_xsave)
2579 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2580 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2581 else {
2582 if (xstate_bv & ~XSTATE_FPSSE)
2583 return -EINVAL;
2584 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2585 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2586 }
2587 return 0;
2588}
2589
2590static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2591 struct kvm_xcrs *guest_xcrs)
2592{
2593 if (!cpu_has_xsave) {
2594 guest_xcrs->nr_xcrs = 0;
2595 return;
2596 }
2597
2598 guest_xcrs->nr_xcrs = 1;
2599 guest_xcrs->flags = 0;
2600 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2601 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2602}
2603
2604static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2605 struct kvm_xcrs *guest_xcrs)
2606{
2607 int i, r = 0;
2608
2609 if (!cpu_has_xsave)
2610 return -EINVAL;
2611
2612 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2613 return -EINVAL;
2614
2615 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2616 /* Only support XCR0 currently */
2617 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2618 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2619 guest_xcrs->xcrs[0].value);
2620 break;
2621 }
2622 if (r)
2623 r = -EINVAL;
2624 return r;
2625}
2626
1c0b28c2
EM		 2627/*
2628 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2629 * stopped by the hypervisor. This function will be called from the host only.
2630 * EINVAL is returned when the host attempts to set the flag for a guest that
2631 * does not support pv clocks.
2632 */
2633static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2634{
2635 struct pvclock_vcpu_time_info *src = &vcpu->arch.hv_clock;
2636 if (!vcpu->arch.time_page)
2637 return -EINVAL;
2638 src->flags |= PVCLOCK_GUEST_STOPPED;
2639 mark_page_dirty(vcpu->kvm, vcpu->arch.time >> PAGE_SHIFT);
2640 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2641 return 0;
2642}
2643
313a3dc7
CO		 2644long kvm_arch_vcpu_ioctl(struct file *filp,
2645 unsigned int ioctl, unsigned long arg)
2646{
2647 struct kvm_vcpu *vcpu = filp->private_data;
2648 void __user *argp = (void __user *)arg;
2649 int r;
d1ac91d8
AK		 2650 union {
2651 struct kvm_lapic_state *lapic;
2652 struct kvm_xsave *xsave;
2653 struct kvm_xcrs *xcrs;
2654 void *buffer;
2655 } u;
2656
2657 u.buffer = NULL;
313a3dc7
CO		 2658 switch (ioctl) {
2659 case KVM_GET_LAPIC: {
2204ae3c
MT		 2660 r = -EINVAL;
2661 if (!vcpu->arch.apic)
2662 goto out;
d1ac91d8 2663 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2664
b772ff36 2665 r = -ENOMEM;
d1ac91d8 2666 if (!u.lapic)
b772ff36 2667 goto out;
d1ac91d8 2668 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2669 if (r)
2670 goto out;
2671 r = -EFAULT;
d1ac91d8 2672 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2673 goto out;
2674 r = 0;
2675 break;
2676 }
2677 case KVM_SET_LAPIC: {
2204ae3c
MT		 2678 r = -EINVAL;
2679 if (!vcpu->arch.apic)
2680 goto out;
ff5c2c03
SL		 2681 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2682 if (IS_ERR(u.lapic)) {
2683 r = PTR_ERR(u.lapic);
313a3dc7 2684 goto out;
ff5c2c03
SL		 2685 }
2686
d1ac91d8 2687 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2688 if (r)
2689 goto out;
2690 r = 0;
2691 break;
2692 }
f77bc6a4
ZX		 2693 case KVM_INTERRUPT: {
2694 struct kvm_interrupt irq;
2695
2696 r = -EFAULT;
2697 if (copy_from_user(&irq, argp, sizeof irq))
2698 goto out;
2699 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2700 if (r)
2701 goto out;
2702 r = 0;
2703 break;
2704 }
c4abb7c9
JK		 2705 case KVM_NMI: {
2706 r = kvm_vcpu_ioctl_nmi(vcpu);
2707 if (r)
2708 goto out;
2709 r = 0;
2710 break;
2711 }
313a3dc7
CO		 2712 case KVM_SET_CPUID: {
2713 struct kvm_cpuid __user *cpuid_arg = argp;
2714 struct kvm_cpuid cpuid;
2715
2716 r = -EFAULT;
2717 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2718 goto out;
2719 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2720 if (r)
2721 goto out;
2722 break;
2723 }
07716717
DK		 2724 case KVM_SET_CPUID2: {
2725 struct kvm_cpuid2 __user *cpuid_arg = argp;
2726 struct kvm_cpuid2 cpuid;
2727
2728 r = -EFAULT;
2729 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2730 goto out;
2731 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2732 cpuid_arg->entries);
07716717
DK		 2733 if (r)
2734 goto out;
2735 break;
2736 }
2737 case KVM_GET_CPUID2: {
2738 struct kvm_cpuid2 __user *cpuid_arg = argp;
2739 struct kvm_cpuid2 cpuid;
2740
2741 r = -EFAULT;
2742 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2743 goto out;
2744 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2745 cpuid_arg->entries);
07716717
DK		 2746 if (r)
2747 goto out;
2748 r = -EFAULT;
2749 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2750 goto out;
2751 r = 0;
2752 break;
2753 }
313a3dc7
CO		 2754 case KVM_GET_MSRS:
2755 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2756 break;
2757 case KVM_SET_MSRS:
2758 r = msr_io(vcpu, argp, do_set_msr, 0);
2759 break;
b209749f
AK		 2760 case KVM_TPR_ACCESS_REPORTING: {
2761 struct kvm_tpr_access_ctl tac;
2762
2763 r = -EFAULT;
2764 if (copy_from_user(&tac, argp, sizeof tac))
2765 goto out;
2766 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2767 if (r)
2768 goto out;
2769 r = -EFAULT;
2770 if (copy_to_user(argp, &tac, sizeof tac))
2771 goto out;
2772 r = 0;
2773 break;
2774 };
b93463aa
AK		 2775 case KVM_SET_VAPIC_ADDR: {
2776 struct kvm_vapic_addr va;
2777
2778 r = -EINVAL;
2779 if (!irqchip_in_kernel(vcpu->kvm))
2780 goto out;
2781 r = -EFAULT;
2782 if (copy_from_user(&va, argp, sizeof va))
2783 goto out;
2784 r = 0;
2785 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2786 break;
2787 }
890ca9ae
HY		 2788 case KVM_X86_SETUP_MCE: {
2789 u64 mcg_cap;
2790
2791 r = -EFAULT;
2792 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2793 goto out;
2794 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2795 break;
2796 }
2797 case KVM_X86_SET_MCE: {
2798 struct kvm_x86_mce mce;
2799
2800 r = -EFAULT;
2801 if (copy_from_user(&mce, argp, sizeof mce))
2802 goto out;
2803 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2804 break;
2805 }
3cfc3092
JK		 2806 case KVM_GET_VCPU_EVENTS: {
2807 struct kvm_vcpu_events events;
2808
2809 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2810
2811 r = -EFAULT;
2812 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2813 break;
2814 r = 0;
2815 break;
2816 }
2817 case KVM_SET_VCPU_EVENTS: {
2818 struct kvm_vcpu_events events;
2819
2820 r = -EFAULT;
2821 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2822 break;
2823
2824 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2825 break;
2826 }
a1efbe77
JK		 2827 case KVM_GET_DEBUGREGS: {
2828 struct kvm_debugregs dbgregs;
2829
2830 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2831
2832 r = -EFAULT;
2833 if (copy_to_user(argp, &dbgregs,
2834 sizeof(struct kvm_debugregs)))
2835 break;
2836 r = 0;
2837 break;
2838 }
2839 case KVM_SET_DEBUGREGS: {
2840 struct kvm_debugregs dbgregs;
2841
2842 r = -EFAULT;
2843 if (copy_from_user(&dbgregs, argp,
2844 sizeof(struct kvm_debugregs)))
2845 break;
2846
2847 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2848 break;
2849 }
2d5b5a66 2850 case KVM_GET_XSAVE: {
d1ac91d8 2851 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2852 r = -ENOMEM;
d1ac91d8 2853 if (!u.xsave)
2d5b5a66
SY		 2854 break;
2855
d1ac91d8 2856 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2857
2858 r = -EFAULT;
d1ac91d8 2859 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2860 break;
2861 r = 0;
2862 break;
2863 }
2864 case KVM_SET_XSAVE: {
ff5c2c03
SL		 2865 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2866 if (IS_ERR(u.xsave)) {
2867 r = PTR_ERR(u.xsave);
2868 goto out;
2869 }
2d5b5a66 2870
d1ac91d8 2871 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2872 break;
2873 }
2874 case KVM_GET_XCRS: {
d1ac91d8 2875 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2876 r = -ENOMEM;
d1ac91d8 2877 if (!u.xcrs)
2d5b5a66
SY		 2878 break;
2879
d1ac91d8 2880 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2881
2882 r = -EFAULT;
d1ac91d8 2883 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2884 sizeof(struct kvm_xcrs)))
2885 break;
2886 r = 0;
2887 break;
2888 }
2889 case KVM_SET_XCRS: {
ff5c2c03
SL		 2890 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2891 if (IS_ERR(u.xcrs)) {
2892 r = PTR_ERR(u.xcrs);
2893 goto out;
2894 }
2d5b5a66 2895
d1ac91d8 2896 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2897 break;
2898 }
92a1f12d
JR		 2899 case KVM_SET_TSC_KHZ: {
2900 u32 user_tsc_khz;
2901
2902 r = -EINVAL;
92a1f12d
JR		 2903 user_tsc_khz = (u32)arg;
2904
2905 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2906 goto out;
2907
cc578287
ZA		 2908 if (user_tsc_khz == 0)
2909 user_tsc_khz = tsc_khz;
2910
2911 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 2912
2913 r = 0;
2914 goto out;
2915 }
2916 case KVM_GET_TSC_KHZ: {
cc578287 2917 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 2918 goto out;
2919 }
1c0b28c2
EM		 2920 case KVM_KVMCLOCK_CTRL: {
2921 r = kvm_set_guest_paused(vcpu);
2922 goto out;
2923 }
313a3dc7
CO		 2924 default:
2925 r = -EINVAL;
2926 }
2927out:
d1ac91d8 2928 kfree(u.buffer);
313a3dc7
CO		 2929 return r;
2930}
2931
5b1c1493
CO		 2932int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2933{
2934 return VM_FAULT_SIGBUS;
2935}
2936
1fe779f8
CO		 2937static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2938{
2939 int ret;
2940
2941 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2942 return -1;
2943 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2944 return ret;
2945}
2946
b927a3ce
SY		 2947static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2948 u64 ident_addr)
2949{
2950 kvm->arch.ept_identity_map_addr = ident_addr;
2951 return 0;
2952}
2953
1fe779f8
CO		 2954static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2955 u32 kvm_nr_mmu_pages)
2956{
2957 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2958 return -EINVAL;
2959
79fac95e 2960 mutex_lock(&kvm->slots_lock);
7c8a83b7 2961 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2962
2963 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2964 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2965
7c8a83b7 2966 spin_unlock(&kvm->mmu_lock);
79fac95e 2967 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2968 return 0;
2969}
2970
2971static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2972{
39de71ec 2973 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2974}
2975
1fe779f8
CO		 2976static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2977{
2978 int r;
2979
2980 r = 0;
2981 switch (chip->chip_id) {
2982 case KVM_IRQCHIP_PIC_MASTER:
2983 memcpy(&chip->chip.pic,
2984 &pic_irqchip(kvm)->pics[0],
2985 sizeof(struct kvm_pic_state));
2986 break;
2987 case KVM_IRQCHIP_PIC_SLAVE:
2988 memcpy(&chip->chip.pic,
2989 &pic_irqchip(kvm)->pics[1],
2990 sizeof(struct kvm_pic_state));
2991 break;
2992 case KVM_IRQCHIP_IOAPIC:
eba0226b 2993 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2994 break;
2995 default:
2996 r = -EINVAL;
2997 break;
2998 }
2999 return r;
3000}
3001
3002static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3003{
3004 int r;
3005
3006 r = 0;
3007 switch (chip->chip_id) {
3008 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3009 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3010 memcpy(&pic_irqchip(kvm)->pics[0],
3011 &chip->chip.pic,
3012 sizeof(struct kvm_pic_state));
f4f51050 3013 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3014 break;
3015 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3016 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3017 memcpy(&pic_irqchip(kvm)->pics[1],
3018 &chip->chip.pic,
3019 sizeof(struct kvm_pic_state));
f4f51050 3020 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3021 break;
3022 case KVM_IRQCHIP_IOAPIC:
eba0226b 3023 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3024 break;
3025 default:
3026 r = -EINVAL;
3027 break;
3028 }
3029 kvm_pic_update_irq(pic_irqchip(kvm));
3030 return r;
3031}
3032
e0f63cb9
SY		 3033static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3034{
3035 int r = 0;
3036
894a9c55 3037 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3038 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3039 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3040 return r;
3041}
3042
3043static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3044{
3045 int r = 0;
3046
894a9c55 3047 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3048 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3049 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3050 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3051 return r;
3052}
3053
3054static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3055{
3056 int r = 0;
3057
3058 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3059 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3060 sizeof(ps->channels));
3061 ps->flags = kvm->arch.vpit->pit_state.flags;
3062 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3063 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3064 return r;
3065}
3066
3067static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3068{
3069 int r = 0, start = 0;
3070 u32 prev_legacy, cur_legacy;
3071 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3072 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3073 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3074 if (!prev_legacy && cur_legacy)
3075 start = 1;
3076 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3077 sizeof(kvm->arch.vpit->pit_state.channels));
3078 kvm->arch.vpit->pit_state.flags = ps->flags;
3079 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3080 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3081 return r;
3082}
3083
52d939a0
MT		 3084static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3085 struct kvm_reinject_control *control)
3086{
3087 if (!kvm->arch.vpit)
3088 return -ENXIO;
894a9c55 3089 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3090 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3091 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3092 return 0;
3093}
3094
95d4c16c 3095/**
60c34612
TY		 3096 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3097 * @kvm: kvm instance
3098 * @log: slot id and address to which we copy the log
95d4c16c 3099 *
60c34612
TY		 3100 * We need to keep it in mind that VCPU threads can write to the bitmap
3101 * concurrently. So, to avoid losing data, we keep the following order for
3102 * each bit:
95d4c16c 3103 *
60c34612
TY		 3104 * 1. Take a snapshot of the bit and clear it if needed.
3105 * 2. Write protect the corresponding page.
3106 * 3. Flush TLB's if needed.
3107 * 4. Copy the snapshot to the userspace.
95d4c16c 3108 *
60c34612
TY		 3109 * Between 2 and 3, the guest may write to the page using the remaining TLB
3110 * entry. This is not a problem because the page will be reported dirty at
3111 * step 4 using the snapshot taken before and step 3 ensures that successive
3112 * writes will be logged for the next call.
5bb064dc 3113 */
60c34612 3114int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3115{
7850ac54 3116 int r;
5bb064dc 3117 struct kvm_memory_slot *memslot;
60c34612
TY		 3118 unsigned long n, i;
3119 unsigned long *dirty_bitmap;
3120 unsigned long *dirty_bitmap_buffer;
3121 bool is_dirty = false;
5bb064dc 3122
79fac95e 3123 mutex_lock(&kvm->slots_lock);
5bb064dc 3124
b050b015
MT		 3125 r = -EINVAL;
3126 if (log->slot >= KVM_MEMORY_SLOTS)
3127 goto out;
3128
28a37544 3129 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3130
3131 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3132 r = -ENOENT;
60c34612 3133 if (!dirty_bitmap)
b050b015
MT		 3134 goto out;
3135
87bf6e7d 3136 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3137
60c34612
TY		 3138 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3139 memset(dirty_bitmap_buffer, 0, n);
b050b015 3140
60c34612 3141 spin_lock(&kvm->mmu_lock);
b050b015 3142
60c34612
TY		 3143 for (i = 0; i < n / sizeof(long); i++) {
3144 unsigned long mask;
3145 gfn_t offset;
cdfca7b3 3146
60c34612
TY		 3147 if (!dirty_bitmap[i])
3148 continue;
b050b015 3149
60c34612 3150 is_dirty = true;
914ebccd 3151
60c34612
TY		 3152 mask = xchg(&dirty_bitmap[i], 0);
3153 dirty_bitmap_buffer[i] = mask;
edde99ce 3154
60c34612
TY		 3155 offset = i * BITS_PER_LONG;
3156 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3157 }
60c34612
TY		 3158 if (is_dirty)
3159 kvm_flush_remote_tlbs(kvm);
3160
3161 spin_unlock(&kvm->mmu_lock);
3162
3163 r = -EFAULT;
3164 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3165 goto out;
b050b015 3166
5bb064dc
ZX		 3167 r = 0;
3168out:
79fac95e 3169 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3170 return r;
3171}
3172
1fe779f8
CO		 3173long kvm_arch_vm_ioctl(struct file *filp,
3174 unsigned int ioctl, unsigned long arg)
3175{
3176 struct kvm *kvm = filp->private_data;
3177 void __user *argp = (void __user *)arg;
367e1319 3178 int r = -ENOTTY;
f0d66275
DH		 3179 /*
3180 * This union makes it completely explicit to gcc-3.x
3181 * that these two variables' stack usage should be
3182 * combined, not added together.
3183 */
3184 union {
3185 struct kvm_pit_state ps;
e9f42757 3186 struct kvm_pit_state2 ps2;
c5ff41ce 3187 struct kvm_pit_config pit_config;
f0d66275 3188 } u;
1fe779f8
CO		 3189
3190 switch (ioctl) {
3191 case KVM_SET_TSS_ADDR:
3192 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3193 if (r < 0)
3194 goto out;
3195 break;
b927a3ce
SY		 3196 case KVM_SET_IDENTITY_MAP_ADDR: {
3197 u64 ident_addr;
3198
3199 r = -EFAULT;
3200 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3201 goto out;
3202 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3203 if (r < 0)
3204 goto out;
3205 break;
3206 }
1fe779f8
CO		 3207 case KVM_SET_NR_MMU_PAGES:
3208 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3209 if (r)
3210 goto out;
3211 break;
3212 case KVM_GET_NR_MMU_PAGES:
3213 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3214 break;
3ddea128
MT		 3215 case KVM_CREATE_IRQCHIP: {
3216 struct kvm_pic *vpic;
3217
3218 mutex_lock(&kvm->lock);
3219 r = -EEXIST;
3220 if (kvm->arch.vpic)
3221 goto create_irqchip_unlock;
3e515705
AK		 3222 r = -EINVAL;
3223 if (atomic_read(&kvm->online_vcpus))
3224 goto create_irqchip_unlock;
1fe779f8 3225 r = -ENOMEM;
3ddea128
MT		 3226 vpic = kvm_create_pic(kvm);
3227 if (vpic) {
1fe779f8
CO		 3228 r = kvm_ioapic_init(kvm);
3229 if (r) {
175504cd 3230 mutex_lock(&kvm->slots_lock);
72bb2fcd 3231 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3232 &vpic->dev_master);
3233 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3234 &vpic->dev_slave);
3235 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3236 &vpic->dev_eclr);
175504cd 3237 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3238 kfree(vpic);
3239 goto create_irqchip_unlock;
1fe779f8
CO		 3240 }
3241 } else
3ddea128
MT		 3242 goto create_irqchip_unlock;
3243 smp_wmb();
3244 kvm->arch.vpic = vpic;
3245 smp_wmb();
399ec807
AK		 3246 r = kvm_setup_default_irq_routing(kvm);
3247 if (r) {
175504cd 3248 mutex_lock(&kvm->slots_lock);
3ddea128 3249 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3250 kvm_ioapic_destroy(kvm);
3251 kvm_destroy_pic(kvm);
3ddea128 3252 mutex_unlock(&kvm->irq_lock);
175504cd 3253 mutex_unlock(&kvm->slots_lock);
399ec807 3254 }
3ddea128
MT		 3255 create_irqchip_unlock:
3256 mutex_unlock(&kvm->lock);
1fe779f8 3257 break;
3ddea128 3258 }
7837699f 3259 case KVM_CREATE_PIT:
c5ff41ce
JK		 3260 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3261 goto create_pit;
3262 case KVM_CREATE_PIT2:
3263 r = -EFAULT;
3264 if (copy_from_user(&u.pit_config, argp,
3265 sizeof(struct kvm_pit_config)))
3266 goto out;
3267 create_pit:
79fac95e 3268 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3269 r = -EEXIST;
3270 if (kvm->arch.vpit)
3271 goto create_pit_unlock;
7837699f 3272 r = -ENOMEM;
c5ff41ce 3273 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3274 if (kvm->arch.vpit)
3275 r = 0;
269e05e4 3276 create_pit_unlock:
79fac95e 3277 mutex_unlock(&kvm->slots_lock);
7837699f 3278 break;
4925663a 3279 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3280 case KVM_IRQ_LINE: {
3281 struct kvm_irq_level irq_event;
3282
3283 r = -EFAULT;
3284 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3285 goto out;
160d2f6c 3286 r = -ENXIO;
1fe779f8 3287 if (irqchip_in_kernel(kvm)) {
4925663a 3288 __s32 status;
4925663a
GN		 3289 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3290 irq_event.irq, irq_event.level);
4925663a 3291 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3292 r = -EFAULT;
4925663a
GN		 3293 irq_event.status = status;
3294 if (copy_to_user(argp, &irq_event,
3295 sizeof irq_event))
3296 goto out;
3297 }
1fe779f8
CO		 3298 r = 0;
3299 }
3300 break;
3301 }
3302 case KVM_GET_IRQCHIP: {
3303 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3304 struct kvm_irqchip *chip;
1fe779f8 3305
ff5c2c03
SL		 3306 chip = memdup_user(argp, sizeof(*chip));
3307 if (IS_ERR(chip)) {
3308 r = PTR_ERR(chip);
1fe779f8 3309 goto out;
ff5c2c03
SL		 3310 }
3311
1fe779f8
CO		 3312 r = -ENXIO;
3313 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3314 goto get_irqchip_out;
3315 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3316 if (r)
f0d66275 3317 goto get_irqchip_out;
1fe779f8 3318 r = -EFAULT;
f0d66275
DH		 3319 if (copy_to_user(argp, chip, sizeof *chip))
3320 goto get_irqchip_out;
1fe779f8 3321 r = 0;
f0d66275
DH		 3322 get_irqchip_out:
3323 kfree(chip);
3324 if (r)
3325 goto out;
1fe779f8
CO		 3326 break;
3327 }
3328 case KVM_SET_IRQCHIP: {
3329 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3330 struct kvm_irqchip *chip;
1fe779f8 3331
ff5c2c03
SL		 3332 chip = memdup_user(argp, sizeof(*chip));
3333 if (IS_ERR(chip)) {
3334 r = PTR_ERR(chip);
1fe779f8 3335 goto out;
ff5c2c03
SL		 3336 }
3337
1fe779f8
CO		 3338 r = -ENXIO;
3339 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3340 goto set_irqchip_out;
3341 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3342 if (r)
f0d66275 3343 goto set_irqchip_out;
1fe779f8 3344 r = 0;
f0d66275
DH		 3345 set_irqchip_out:
3346 kfree(chip);
3347 if (r)
3348 goto out;
1fe779f8
CO		 3349 break;
3350 }
e0f63cb9 3351 case KVM_GET_PIT: {
e0f63cb9 3352 r = -EFAULT;
f0d66275 3353 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3354 goto out;
3355 r = -ENXIO;
3356 if (!kvm->arch.vpit)
3357 goto out;
f0d66275 3358 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3359 if (r)
3360 goto out;
3361 r = -EFAULT;
f0d66275 3362 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3363 goto out;
3364 r = 0;
3365 break;
3366 }
3367 case KVM_SET_PIT: {
e0f63cb9 3368 r = -EFAULT;
f0d66275 3369 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3370 goto out;
3371 r = -ENXIO;
3372 if (!kvm->arch.vpit)
3373 goto out;
f0d66275 3374 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3375 if (r)
3376 goto out;
3377 r = 0;
3378 break;
3379 }
e9f42757
BK		 3380 case KVM_GET_PIT2: {
3381 r = -ENXIO;
3382 if (!kvm->arch.vpit)
3383 goto out;
3384 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3385 if (r)
3386 goto out;
3387 r = -EFAULT;
3388 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3389 goto out;
3390 r = 0;
3391 break;
3392 }
3393 case KVM_SET_PIT2: {
3394 r = -EFAULT;
3395 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3396 goto out;
3397 r = -ENXIO;
3398 if (!kvm->arch.vpit)
3399 goto out;
3400 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3401 if (r)
3402 goto out;
3403 r = 0;
3404 break;
3405 }
52d939a0
MT		 3406 case KVM_REINJECT_CONTROL: {
3407 struct kvm_reinject_control control;
3408 r = -EFAULT;
3409 if (copy_from_user(&control, argp, sizeof(control)))
3410 goto out;
3411 r = kvm_vm_ioctl_reinject(kvm, &control);
3412 if (r)
3413 goto out;
3414 r = 0;
3415 break;
3416 }
ffde22ac
ES		 3417 case KVM_XEN_HVM_CONFIG: {
3418 r = -EFAULT;
3419 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3420 sizeof(struct kvm_xen_hvm_config)))
3421 goto out;
3422 r = -EINVAL;
3423 if (kvm->arch.xen_hvm_config.flags)
3424 goto out;
3425 r = 0;
3426 break;
3427 }
afbcf7ab 3428 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3429 struct kvm_clock_data user_ns;
3430 u64 now_ns;
3431 s64 delta;
3432
3433 r = -EFAULT;
3434 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3435 goto out;
3436
3437 r = -EINVAL;
3438 if (user_ns.flags)
3439 goto out;
3440
3441 r = 0;
395c6b0a 3442 local_irq_disable();
759379dd 3443 now_ns = get_kernel_ns();
afbcf7ab 3444 delta = user_ns.clock - now_ns;
395c6b0a 3445 local_irq_enable();
afbcf7ab
GC		 3446 kvm->arch.kvmclock_offset = delta;
3447 break;
3448 }
3449 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3450 struct kvm_clock_data user_ns;
3451 u64 now_ns;
3452
395c6b0a 3453 local_irq_disable();
759379dd 3454 now_ns = get_kernel_ns();
afbcf7ab 3455 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3456 local_irq_enable();
afbcf7ab 3457 user_ns.flags = 0;
97e69aa6 3458 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3459
3460 r = -EFAULT;
3461 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3462 goto out;
3463 r = 0;
3464 break;
3465 }
3466
1fe779f8
CO		 3467 default:
3468 ;
3469 }
3470out:
3471 return r;
3472}
3473
a16b043c 3474static void kvm_init_msr_list(void)
043405e1
CO		 3475{
3476 u32 dummy[2];
3477 unsigned i, j;
3478
e3267cbb
GC		 3479 /* skip the first msrs in the list. KVM-specific */
3480 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3481 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3482 continue;
3483 if (j < i)
3484 msrs_to_save[j] = msrs_to_save[i];
3485 j++;
3486 }
3487 num_msrs_to_save = j;
3488}
3489
bda9020e
MT		 3490static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3491 const void *v)
bbd9b64e 3492{
70252a10
AK		 3493 int handled = 0;
3494 int n;
3495
3496 do {
3497 n = min(len, 8);
3498 if (!(vcpu->arch.apic &&
3499 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3500 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3501 break;
3502 handled += n;
3503 addr += n;
3504 len -= n;
3505 v += n;
3506 } while (len);
bbd9b64e 3507
70252a10 3508 return handled;
bbd9b64e
CO		 3509}
3510
bda9020e 3511static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3512{
70252a10
AK		 3513 int handled = 0;
3514 int n;
3515
3516 do {
3517 n = min(len, 8);
3518 if (!(vcpu->arch.apic &&
3519 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3520 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3521 break;
3522 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3523 handled += n;
3524 addr += n;
3525 len -= n;
3526 v += n;
3527 } while (len);
bbd9b64e 3528
70252a10 3529 return handled;
bbd9b64e
CO		 3530}
3531
2dafc6c2
GN		 3532static void kvm_set_segment(struct kvm_vcpu *vcpu,
3533 struct kvm_segment *var, int seg)
3534{
3535 kvm_x86_ops->set_segment(vcpu, var, seg);
3536}
3537
3538void kvm_get_segment(struct kvm_vcpu *vcpu,
3539 struct kvm_segment *var, int seg)
3540{
3541 kvm_x86_ops->get_segment(vcpu, var, seg);
3542}
3543
e459e322 3544gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3545{
3546 gpa_t t_gpa;
ab9ae313 3547 struct x86_exception exception;
02f59dc9
JR		 3548
3549 BUG_ON(!mmu_is_nested(vcpu));
3550
3551 /* NPT walks are always user-walks */
3552 access |= PFERR_USER_MASK;
ab9ae313 3553 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3554
3555 return t_gpa;
3556}
3557
ab9ae313
AK		 3558gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3559 struct x86_exception *exception)
1871c602
GN		 3560{
3561 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3562 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3563}
3564
ab9ae313
AK		 3565 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3566 struct x86_exception *exception)
1871c602
GN		 3567{
3568 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3569 access |= PFERR_FETCH_MASK;
ab9ae313 3570 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3571}
3572
ab9ae313
AK		 3573gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3574 struct x86_exception *exception)
1871c602
GN		 3575{
3576 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3577 access |= PFERR_WRITE_MASK;
ab9ae313 3578 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3579}
3580
3581/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3582gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3583 struct x86_exception *exception)
1871c602 3584{
ab9ae313 3585 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3586}
3587
3588static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3589 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3590 struct x86_exception *exception)
bbd9b64e
CO		 3591{
3592 void *data = val;
10589a46 3593 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3594
3595 while (bytes) {
14dfe855 3596 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3597 exception);
bbd9b64e 3598 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3599 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3600 int ret;
3601
bcc55cba 3602 if (gpa == UNMAPPED_GVA)
ab9ae313 3603 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3604 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3605 if (ret < 0) {
c3cd7ffa 3606 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3607 goto out;
3608 }
bbd9b64e 3609
77c2002e
IE		 3610 bytes -= toread;
3611 data += toread;
3612 addr += toread;
bbd9b64e 3613 }
10589a46 3614out:
10589a46 3615 return r;
bbd9b64e 3616}
77c2002e 3617
1871c602 3618/* used for instruction fetching */
0f65dd70
AK		 3619static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3620 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3621 struct x86_exception *exception)
1871c602 3622{
0f65dd70 3623 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3624 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3625
1871c602 3626 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3627 access | PFERR_FETCH_MASK,
3628 exception);
1871c602
GN		 3629}
3630
064aea77 3631int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3632 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3633 struct x86_exception *exception)
1871c602 3634{
0f65dd70 3635 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3636 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3637
1871c602 3638 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3639 exception);
1871c602 3640}
064aea77 3641EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3642
0f65dd70
AK		 3643static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3644 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3645 struct x86_exception *exception)
1871c602 3646{
0f65dd70 3647 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3648 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3649}
3650
6a4d7550 3651int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3652 gva_t addr, void *val,
2dafc6c2 3653 unsigned int bytes,
bcc55cba 3654 struct x86_exception *exception)
77c2002e 3655{
0f65dd70 3656 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3657 void *data = val;
3658 int r = X86EMUL_CONTINUE;
3659
3660 while (bytes) {
14dfe855
JR		 3661 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3662 PFERR_WRITE_MASK,
ab9ae313 3663 exception);
77c2002e
IE		 3664 unsigned offset = addr & (PAGE_SIZE-1);
3665 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3666 int ret;
3667
bcc55cba 3668 if (gpa == UNMAPPED_GVA)
ab9ae313 3669 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3670 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3671 if (ret < 0) {
c3cd7ffa 3672 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3673 goto out;
3674 }
3675
3676 bytes -= towrite;
3677 data += towrite;
3678 addr += towrite;
3679 }
3680out:
3681 return r;
3682}
6a4d7550 3683EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3684
af7cc7d1
XG		 3685static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3686 gpa_t *gpa, struct x86_exception *exception,
3687 bool write)
3688{
3689 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3690
bebb106a
XG		 3691 if (vcpu_match_mmio_gva(vcpu, gva) &&
3692 check_write_user_access(vcpu, write, access,
3693 vcpu->arch.access)) {
3694 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3695 (gva & (PAGE_SIZE - 1));
4f022648 3696 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3697 return 1;
3698 }
3699
af7cc7d1
XG		 3700 if (write)
3701 access |= PFERR_WRITE_MASK;
3702
3703 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3704
3705 if (*gpa == UNMAPPED_GVA)
3706 return -1;
3707
3708 /* For APIC access vmexit */
3709 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3710 return 1;
3711
4f022648
XG		 3712 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3713 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3714 return 1;
4f022648 3715 }
bebb106a 3716
af7cc7d1
XG		 3717 return 0;
3718}
3719
3200f405 3720int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3721 const void *val, int bytes)
bbd9b64e
CO		 3722{
3723 int ret;
3724
3725 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3726 if (ret < 0)
bbd9b64e 3727 return 0;
f57f2ef5 3728 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3729 return 1;
3730}
3731
77d197b2
XG		 3732struct read_write_emulator_ops {
3733 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3734 int bytes);
3735 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3736 void *val, int bytes);
3737 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3738 int bytes, void *val);
3739 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3740 void *val, int bytes);
3741 bool write;
3742};
3743
3744static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3745{
3746 if (vcpu->mmio_read_completed) {
77d197b2 3747 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 3748 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 3749 vcpu->mmio_read_completed = 0;
3750 return 1;
3751 }
3752
3753 return 0;
3754}
3755
3756static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3757 void *val, int bytes)
3758{
3759 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3760}
3761
3762static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3763 void *val, int bytes)
3764{
3765 return emulator_write_phys(vcpu, gpa, val, bytes);
3766}
3767
3768static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3769{
3770 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3771 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3772}
3773
3774static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3775 void *val, int bytes)
3776{
3777 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3778 return X86EMUL_IO_NEEDED;
3779}
3780
3781static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3782 void *val, int bytes)
3783{
f78146b0
AK		 3784 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3785
3786 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
77d197b2
XG		 3787 return X86EMUL_CONTINUE;
3788}
3789
3790static struct read_write_emulator_ops read_emultor = {
3791 .read_write_prepare = read_prepare,
3792 .read_write_emulate = read_emulate,
3793 .read_write_mmio = vcpu_mmio_read,
3794 .read_write_exit_mmio = read_exit_mmio,
3795};
3796
3797static struct read_write_emulator_ops write_emultor = {
3798 .read_write_emulate = write_emulate,
3799 .read_write_mmio = write_mmio,
3800 .read_write_exit_mmio = write_exit_mmio,
3801 .write = true,
3802};
3803
22388a3c
XG		 3804static int emulator_read_write_onepage(unsigned long addr, void *val,
3805 unsigned int bytes,
3806 struct x86_exception *exception,
3807 struct kvm_vcpu *vcpu,
3808 struct read_write_emulator_ops *ops)
bbd9b64e 3809{
af7cc7d1
XG		 3810 gpa_t gpa;
3811 int handled, ret;
22388a3c 3812 bool write = ops->write;
f78146b0 3813 struct kvm_mmio_fragment *frag;
10589a46 3814
22388a3c 3815 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3816
af7cc7d1 3817 if (ret < 0)
bbd9b64e 3818 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3819
3820 /* For APIC access vmexit */
af7cc7d1 3821 if (ret)
bbd9b64e
CO		 3822 goto mmio;
3823
22388a3c 3824 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3825 return X86EMUL_CONTINUE;
3826
3827mmio:
3828 /*
3829 * Is this MMIO handled locally?
3830 */
22388a3c 3831 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3832 if (handled == bytes)
bbd9b64e 3833 return X86EMUL_CONTINUE;
bbd9b64e 3834
70252a10
AK		 3835 gpa += handled;
3836 bytes -= handled;
3837 val += handled;
3838
f78146b0
AK		 3839 while (bytes) {
3840 unsigned now = min(bytes, 8U);
bbd9b64e 3841
f78146b0
AK		 3842 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3843 frag->gpa = gpa;
3844 frag->data = val;
3845 frag->len = now;
3846
3847 gpa += now;
3848 val += now;
3849 bytes -= now;
3850 }
3851 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3852}
3853
22388a3c
XG		 3854int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3855 void *val, unsigned int bytes,
3856 struct x86_exception *exception,
3857 struct read_write_emulator_ops *ops)
bbd9b64e 3858{
0f65dd70 3859 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 3860 gpa_t gpa;
3861 int rc;
3862
3863 if (ops->read_write_prepare &&
3864 ops->read_write_prepare(vcpu, val, bytes))
3865 return X86EMUL_CONTINUE;
3866
3867 vcpu->mmio_nr_fragments = 0;
0f65dd70 3868
bbd9b64e
CO		 3869 /* Crossing a page boundary? */
3870 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 3871 int now;
bbd9b64e
CO		 3872
3873 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3874 rc = emulator_read_write_onepage(addr, val, now, exception,
3875 vcpu, ops);
3876
bbd9b64e
CO		 3877 if (rc != X86EMUL_CONTINUE)
3878 return rc;
3879 addr += now;
3880 val += now;
3881 bytes -= now;
3882 }
22388a3c 3883
f78146b0
AK		 3884 rc = emulator_read_write_onepage(addr, val, bytes, exception,
3885 vcpu, ops);
3886 if (rc != X86EMUL_CONTINUE)
3887 return rc;
3888
3889 if (!vcpu->mmio_nr_fragments)
3890 return rc;
3891
3892 gpa = vcpu->mmio_fragments[0].gpa;
3893
3894 vcpu->mmio_needed = 1;
3895 vcpu->mmio_cur_fragment = 0;
3896
3897 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3898 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3899 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3900 vcpu->run->mmio.phys_addr = gpa;
3901
3902 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 3903}
3904
3905static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3906 unsigned long addr,
3907 void *val,
3908 unsigned int bytes,
3909 struct x86_exception *exception)
3910{
3911 return emulator_read_write(ctxt, addr, val, bytes,
3912 exception, &read_emultor);
3913}
3914
3915int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3916 unsigned long addr,
3917 const void *val,
3918 unsigned int bytes,
3919 struct x86_exception *exception)
3920{
3921 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3922 exception, &write_emultor);
bbd9b64e 3923}
bbd9b64e 3924
daea3e73
AK		 3925#define CMPXCHG_TYPE(t, ptr, old, new) \
3926 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3927
3928#ifdef CONFIG_X86_64
3929# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3930#else
3931# define CMPXCHG64(ptr, old, new) \
9749a6c0 3932 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3933#endif
3934
0f65dd70
AK		 3935static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3936 unsigned long addr,
bbd9b64e
CO		 3937 const void *old,
3938 const void *new,
3939 unsigned int bytes,
0f65dd70 3940 struct x86_exception *exception)
bbd9b64e 3941{
0f65dd70 3942 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3943 gpa_t gpa;
3944 struct page *page;
3945 char *kaddr;
3946 bool exchanged;
2bacc55c 3947
daea3e73
AK		 3948 /* guests cmpxchg8b have to be emulated atomically */
3949 if (bytes > 8 || (bytes & (bytes - 1)))
3950 goto emul_write;
10589a46 3951
daea3e73 3952 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3953
daea3e73
AK		 3954 if (gpa == UNMAPPED_GVA ||
3955 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3956 goto emul_write;
2bacc55c 3957
daea3e73
AK		 3958 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3959 goto emul_write;
72dc67a6 3960
daea3e73 3961 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3962 if (is_error_page(page)) {
3963 kvm_release_page_clean(page);
3964 goto emul_write;
3965 }
72dc67a6 3966
8fd75e12 3967 kaddr = kmap_atomic(page);
daea3e73
AK		 3968 kaddr += offset_in_page(gpa);
3969 switch (bytes) {
3970 case 1:
3971 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3972 break;
3973 case 2:
3974 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3975 break;
3976 case 4:
3977 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3978 break;
3979 case 8:
3980 exchanged = CMPXCHG64(kaddr, old, new);
3981 break;
3982 default:
3983 BUG();
2bacc55c 3984 }
8fd75e12 3985 kunmap_atomic(kaddr);
daea3e73
AK		 3986 kvm_release_page_dirty(page);
3987
3988 if (!exchanged)
3989 return X86EMUL_CMPXCHG_FAILED;
3990
f57f2ef5 3991 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 3992
3993 return X86EMUL_CONTINUE;
4a5f48f6 3994
3200f405 3995emul_write:
daea3e73 3996 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3997
0f65dd70 3998 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 3999}
4000
cf8f70bf
GN		 4001static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4002{
4003 /* TODO: String I/O for in kernel device */
4004 int r;
4005
4006 if (vcpu->arch.pio.in)
4007 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4008 vcpu->arch.pio.size, pd);
4009 else
4010 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4011 vcpu->arch.pio.port, vcpu->arch.pio.size,
4012 pd);
4013 return r;
4014}
4015
6f6fbe98
XG		 4016static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4017 unsigned short port, void *val,
4018 unsigned int count, bool in)
cf8f70bf 4019{
6f6fbe98 4020 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4021
4022 vcpu->arch.pio.port = port;
6f6fbe98 4023 vcpu->arch.pio.in = in;
7972995b 4024 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4025 vcpu->arch.pio.size = size;
4026
4027 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4028 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4029 return 1;
4030 }
4031
4032 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4033 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4034 vcpu->run->io.size = size;
4035 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4036 vcpu->run->io.count = count;
4037 vcpu->run->io.port = port;
4038
4039 return 0;
4040}
4041
6f6fbe98
XG		 4042static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4043 int size, unsigned short port, void *val,
4044 unsigned int count)
cf8f70bf 4045{
ca1d4a9e 4046 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4047 int ret;
ca1d4a9e 4048
6f6fbe98
XG		 4049 if (vcpu->arch.pio.count)
4050 goto data_avail;
cf8f70bf 4051
6f6fbe98
XG		 4052 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4053 if (ret) {
4054data_avail:
4055 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4056 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4057 return 1;
4058 }
4059
cf8f70bf
GN		 4060 return 0;
4061}
4062
6f6fbe98
XG		 4063static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4064 int size, unsigned short port,
4065 const void *val, unsigned int count)
4066{
4067 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4068
4069 memcpy(vcpu->arch.pio_data, val, size * count);
4070 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4071}
4072
bbd9b64e
CO		 4073static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4074{
4075 return kvm_x86_ops->get_segment_base(vcpu, seg);
4076}
4077
3cb16fe7 4078static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4079{
3cb16fe7 4080 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4081}
4082
f5f48ee1
SY		 4083int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4084{
4085 if (!need_emulate_wbinvd(vcpu))
4086 return X86EMUL_CONTINUE;
4087
4088 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4089 int cpu = get_cpu();
4090
4091 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4092 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4093 wbinvd_ipi, NULL, 1);
2eec7343 4094 put_cpu();
f5f48ee1 4095 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4096 } else
4097 wbinvd();
f5f48ee1
SY		 4098 return X86EMUL_CONTINUE;
4099}
4100EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4101
bcaf5cc5
AK		 4102static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4103{
4104 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4105}
4106
717746e3 4107int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4108{
717746e3 4109 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4110}
4111
717746e3 4112int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4113{
338dbc97 4114
717746e3 4115 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4116}
4117
52a46617 4118static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4119{
52a46617 4120 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4121}
4122
717746e3 4123static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4124{
717746e3 4125 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4126 unsigned long value;
4127
4128 switch (cr) {
4129 case 0:
4130 value = kvm_read_cr0(vcpu);
4131 break;
4132 case 2:
4133 value = vcpu->arch.cr2;
4134 break;
4135 case 3:
9f8fe504 4136 value = kvm_read_cr3(vcpu);
52a46617
GN		 4137 break;
4138 case 4:
4139 value = kvm_read_cr4(vcpu);
4140 break;
4141 case 8:
4142 value = kvm_get_cr8(vcpu);
4143 break;
4144 default:
a737f256 4145 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4146 return 0;
4147 }
4148
4149 return value;
4150}
4151
717746e3 4152static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4153{
717746e3 4154 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4155 int res = 0;
4156
52a46617
GN		 4157 switch (cr) {
4158 case 0:
49a9b07e 4159 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4160 break;
4161 case 2:
4162 vcpu->arch.cr2 = val;
4163 break;
4164 case 3:
2390218b 4165 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4166 break;
4167 case 4:
a83b29c6 4168 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4169 break;
4170 case 8:
eea1cff9 4171 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4172 break;
4173 default:
a737f256 4174 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4175 res = -1;
52a46617 4176 }
0f12244f
GN		 4177
4178 return res;
52a46617
GN		 4179}
4180
4cee4798
KW		 4181static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4182{
4183 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4184}
4185
717746e3 4186static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4187{
717746e3 4188 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4189}
4190
4bff1e86 4191static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4192{
4bff1e86 4193 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4194}
4195
4bff1e86 4196static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4197{
4bff1e86 4198 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4199}
4200
1ac9d0cf
AK		 4201static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4202{
4203 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4204}
4205
4206static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4207{
4208 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4209}
4210
4bff1e86
AK		 4211static unsigned long emulator_get_cached_segment_base(
4212 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4213{
4bff1e86 4214 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4215}
4216
1aa36616
AK		 4217static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4218 struct desc_struct *desc, u32 *base3,
4219 int seg)
2dafc6c2
GN		 4220{
4221 struct kvm_segment var;
4222
4bff1e86 4223 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4224 *selector = var.selector;
2dafc6c2
GN		 4225
4226 if (var.unusable)
4227 return false;
4228
4229 if (var.g)
4230 var.limit >>= 12;
4231 set_desc_limit(desc, var.limit);
4232 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4233#ifdef CONFIG_X86_64
4234 if (base3)
4235 *base3 = var.base >> 32;
4236#endif
2dafc6c2
GN		 4237 desc->type = var.type;
4238 desc->s = var.s;
4239 desc->dpl = var.dpl;
4240 desc->p = var.present;
4241 desc->avl = var.avl;
4242 desc->l = var.l;
4243 desc->d = var.db;
4244 desc->g = var.g;
4245
4246 return true;
4247}
4248
1aa36616
AK		 4249static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4250 struct desc_struct *desc, u32 base3,
4251 int seg)
2dafc6c2 4252{
4bff1e86 4253 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4254 struct kvm_segment var;
4255
1aa36616 4256 var.selector = selector;
2dafc6c2 4257 var.base = get_desc_base(desc);
5601d05b
GN		 4258#ifdef CONFIG_X86_64
4259 var.base |= ((u64)base3) << 32;
4260#endif
2dafc6c2
GN		 4261 var.limit = get_desc_limit(desc);
4262 if (desc->g)
4263 var.limit = (var.limit << 12) | 0xfff;
4264 var.type = desc->type;
4265 var.present = desc->p;
4266 var.dpl = desc->dpl;
4267 var.db = desc->d;
4268 var.s = desc->s;
4269 var.l = desc->l;
4270 var.g = desc->g;
4271 var.avl = desc->avl;
4272 var.present = desc->p;
4273 var.unusable = !var.present;
4274 var.padding = 0;
4275
4276 kvm_set_segment(vcpu, &var, seg);
4277 return;
4278}
4279
717746e3
AK		 4280static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4281 u32 msr_index, u64 *pdata)
4282{
4283 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4284}
4285
4286static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4287 u32 msr_index, u64 data)
4288{
4289 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4290}
4291
222d21aa
AK		 4292static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4293 u32 pmc, u64 *pdata)
4294{
4295 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4296}
4297
6c3287f7
AK		 4298static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4299{
4300 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4301}
4302
5037f6f3
AK		 4303static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4304{
4305 preempt_disable();
5197b808 4306 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4307 /*
4308 * CR0.TS may reference the host fpu state, not the guest fpu state,
4309 * so it may be clear at this point.
4310 */
4311 clts();
4312}
4313
4314static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4315{
4316 preempt_enable();
4317}
4318
2953538e 4319static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4320 struct x86_instruction_info *info,
c4f035c6
AK		 4321 enum x86_intercept_stage stage)
4322{
2953538e 4323 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4324}
4325
0017f93a 4326static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4327 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4328{
0017f93a 4329 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4330}
4331
14af3f3c 4332static struct x86_emulate_ops emulate_ops = {
1871c602 4333 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4334 .write_std = kvm_write_guest_virt_system,
1871c602 4335 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4336 .read_emulated = emulator_read_emulated,
4337 .write_emulated = emulator_write_emulated,
4338 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4339 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4340 .pio_in_emulated = emulator_pio_in_emulated,
4341 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4342 .get_segment = emulator_get_segment,
4343 .set_segment = emulator_set_segment,
5951c442 4344 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4345 .get_gdt = emulator_get_gdt,
160ce1f1 4346 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4347 .set_gdt = emulator_set_gdt,
4348 .set_idt = emulator_set_idt,
52a46617
GN		 4349 .get_cr = emulator_get_cr,
4350 .set_cr = emulator_set_cr,
4cee4798 4351 .set_rflags = emulator_set_rflags,
9c537244 4352 .cpl = emulator_get_cpl,
35aa5375
GN		 4353 .get_dr = emulator_get_dr,
4354 .set_dr = emulator_set_dr,
717746e3
AK		 4355 .set_msr = emulator_set_msr,
4356 .get_msr = emulator_get_msr,
222d21aa 4357 .read_pmc = emulator_read_pmc,
6c3287f7 4358 .halt = emulator_halt,
bcaf5cc5 4359 .wbinvd = emulator_wbinvd,
d6aa1000 4360 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4361 .get_fpu = emulator_get_fpu,
4362 .put_fpu = emulator_put_fpu,
c4f035c6 4363 .intercept = emulator_intercept,
bdb42f5a 4364 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4365};
4366
5fdbf976
MT		 4367static void cache_all_regs(struct kvm_vcpu *vcpu)
4368{
4369 kvm_register_read(vcpu, VCPU_REGS_RAX);
4370 kvm_register_read(vcpu, VCPU_REGS_RSP);
4371 kvm_register_read(vcpu, VCPU_REGS_RIP);
4372 vcpu->arch.regs_dirty = ~0;
4373}
4374
95cb2295
GN		 4375static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4376{
4377 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4378 /*
4379 * an sti; sti; sequence only disable interrupts for the first
4380 * instruction. So, if the last instruction, be it emulated or
4381 * not, left the system with the INT_STI flag enabled, it
4382 * means that the last instruction is an sti. We should not
4383 * leave the flag on in this case. The same goes for mov ss
4384 */
4385 if (!(int_shadow & mask))
4386 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4387}
4388
54b8486f
GN		 4389static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4390{
4391 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4392 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4393 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4394 else if (ctxt->exception.error_code_valid)
4395 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4396 ctxt->exception.error_code);
54b8486f 4397 else
da9cb575 4398 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4399}
4400
9dac77fa 4401static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4402 const unsigned long *regs)
4403{
9dac77fa
AK		 4404 memset(&ctxt->twobyte, 0,
4405 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4406 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4407
9dac77fa
AK		 4408 ctxt->fetch.start = 0;
4409 ctxt->fetch.end = 0;
4410 ctxt->io_read.pos = 0;
4411 ctxt->io_read.end = 0;
4412 ctxt->mem_read.pos = 0;
4413 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4414}
4415
8ec4722d
MG		 4416static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4417{
adf52235 4418 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4419 int cs_db, cs_l;
4420
2aab2c5b
GN		 4421 /*
4422 * TODO: fix emulate.c to use guest_read/write_register
4423 * instead of direct ->regs accesses, can save hundred cycles
4424 * on Intel for instructions that don't read/change RSP, for
4425 * for example.
4426 */
8ec4722d
MG		 4427 cache_all_regs(vcpu);
4428
4429 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4430
adf52235
TY		 4431 ctxt->eflags = kvm_get_rflags(vcpu);
4432 ctxt->eip = kvm_rip_read(vcpu);
4433 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4434 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4435 cs_l ? X86EMUL_MODE_PROT64 :
4436 cs_db ? X86EMUL_MODE_PROT32 :
4437 X86EMUL_MODE_PROT16;
4438 ctxt->guest_mode = is_guest_mode(vcpu);
4439
9dac77fa 4440 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4441 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4442}
4443
71f9833b 4444int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4445{
9d74191a 4446 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4447 int ret;
4448
4449 init_emulate_ctxt(vcpu);
4450
9dac77fa
AK		 4451 ctxt->op_bytes = 2;
4452 ctxt->ad_bytes = 2;
4453 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4454 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4455
4456 if (ret != X86EMUL_CONTINUE)
4457 return EMULATE_FAIL;
4458
9dac77fa
AK		 4459 ctxt->eip = ctxt->_eip;
4460 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4461 kvm_rip_write(vcpu, ctxt->eip);
4462 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4463
4464 if (irq == NMI_VECTOR)
7460fb4a 4465 vcpu->arch.nmi_pending = 0;
63995653
MG		 4466 else
4467 vcpu->arch.interrupt.pending = false;
4468
4469 return EMULATE_DONE;
4470}
4471EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4472
6d77dbfc
GN		 4473static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4474{
fc3a9157
JR		 4475 int r = EMULATE_DONE;
4476
6d77dbfc
GN		 4477 ++vcpu->stat.insn_emulation_fail;
4478 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4479 if (!is_guest_mode(vcpu)) {
4480 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4481 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4482 vcpu->run->internal.ndata = 0;
4483 r = EMULATE_FAIL;
4484 }
6d77dbfc 4485 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4486
4487 return r;
6d77dbfc
GN		 4488}
4489
a6f177ef
GN		 4490static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4491{
4492 gpa_t gpa;
4493
68be0803
GN		 4494 if (tdp_enabled)
4495 return false;
4496
a6f177ef
GN		 4497 /*
4498 * if emulation was due to access to shadowed page table
4499 * and it failed try to unshadow page and re-entetr the
4500 * guest to let CPU execute the instruction.
4501 */
4502 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4503 return true;
4504
4505 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4506
4507 if (gpa == UNMAPPED_GVA)
4508 return true; /* let cpu generate fault */
4509
4510 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4511 return true;
4512
4513 return false;
4514}
4515
1cb3f3ae
XG		 4516static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4517 unsigned long cr2, int emulation_type)
4518{
4519 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4520 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4521
4522 last_retry_eip = vcpu->arch.last_retry_eip;
4523 last_retry_addr = vcpu->arch.last_retry_addr;
4524
4525 /*
4526 * If the emulation is caused by #PF and it is non-page_table
4527 * writing instruction, it means the VM-EXIT is caused by shadow
4528 * page protected, we can zap the shadow page and retry this
4529 * instruction directly.
4530 *
4531 * Note: if the guest uses a non-page-table modifying instruction
4532 * on the PDE that points to the instruction, then we will unmap
4533 * the instruction and go to an infinite loop. So, we cache the
4534 * last retried eip and the last fault address, if we meet the eip
4535 * and the address again, we can break out of the potential infinite
4536 * loop.
4537 */
4538 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4539
4540 if (!(emulation_type & EMULTYPE_RETRY))
4541 return false;
4542
4543 if (x86_page_table_writing_insn(ctxt))
4544 return false;
4545
4546 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4547 return false;
4548
4549 vcpu->arch.last_retry_eip = ctxt->eip;
4550 vcpu->arch.last_retry_addr = cr2;
4551
4552 if (!vcpu->arch.mmu.direct_map)
4553 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4554
4555 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4556
4557 return true;
4558}
4559
51d8b661
AP		 4560int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4561 unsigned long cr2,
dc25e89e
AP		 4562 int emulation_type,
4563 void *insn,
4564 int insn_len)
bbd9b64e 4565{
95cb2295 4566 int r;
9d74191a 4567 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4568 bool writeback = true;
bbd9b64e 4569
26eef70c 4570 kvm_clear_exception_queue(vcpu);
8d7d8102 4571
571008da 4572 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4573 init_emulate_ctxt(vcpu);
9d74191a
TY		 4574 ctxt->interruptibility = 0;
4575 ctxt->have_exception = false;
4576 ctxt->perm_ok = false;
bbd9b64e 4577
9d74191a 4578 ctxt->only_vendor_specific_insn
4005996e
AK		 4579 = emulation_type & EMULTYPE_TRAP_UD;
4580
9d74191a 4581 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4582
e46479f8 4583 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4584 ++vcpu->stat.insn_emulation;
1d2887e2 4585 if (r != EMULATION_OK) {
4005996e
AK		 4586 if (emulation_type & EMULTYPE_TRAP_UD)
4587 return EMULATE_FAIL;
a6f177ef 4588 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4589 return EMULATE_DONE;
6d77dbfc
GN		 4590 if (emulation_type & EMULTYPE_SKIP)
4591 return EMULATE_FAIL;
4592 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4593 }
4594 }
4595
ba8afb6b 4596 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4597 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4598 return EMULATE_DONE;
4599 }
4600
1cb3f3ae
XG		 4601 if (retry_instruction(ctxt, cr2, emulation_type))
4602 return EMULATE_DONE;
4603
7ae441ea 4604 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4605 changes registers values during IO operation */
7ae441ea
GN		 4606 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4607 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4608 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4609 }
4d2179e1 4610
5cd21917 4611restart:
9d74191a 4612 r = x86_emulate_insn(ctxt);
bbd9b64e 4613
775fde86
JR		 4614 if (r == EMULATION_INTERCEPTED)
4615 return EMULATE_DONE;
4616
d2ddd1c4 4617 if (r == EMULATION_FAILED) {
a6f177ef 4618 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4619 return EMULATE_DONE;
4620
6d77dbfc 4621 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4622 }
4623
9d74191a 4624 if (ctxt->have_exception) {
54b8486f 4625 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4626 r = EMULATE_DONE;
4627 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4628 if (!vcpu->arch.pio.in)
4629 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4630 else
4631 writeback = false;
e85d28f8 4632 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4633 } else if (vcpu->mmio_needed) {
4634 if (!vcpu->mmio_is_write)
4635 writeback = false;
e85d28f8 4636 r = EMULATE_DO_MMIO;
7ae441ea 4637 } else if (r == EMULATION_RESTART)
5cd21917 4638 goto restart;
d2ddd1c4
GN		 4639 else
4640 r = EMULATE_DONE;
f850e2e6 4641
7ae441ea 4642 if (writeback) {
9d74191a
TY		 4643 toggle_interruptibility(vcpu, ctxt->interruptibility);
4644 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4645 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4646 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4647 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4648 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4649 } else
4650 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4651
4652 return r;
de7d789a 4653}
51d8b661 4654EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4655
cf8f70bf 4656int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4657{
cf8f70bf 4658 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4659 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4660 size, port, &val, 1);
cf8f70bf 4661 /* do not return to emulator after return from userspace */
7972995b 4662 vcpu->arch.pio.count = 0;
de7d789a
CO		 4663 return ret;
4664}
cf8f70bf 4665EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4666
8cfdc000
ZA		 4667static void tsc_bad(void *info)
4668{
0a3aee0d 4669 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4670}
4671
4672static void tsc_khz_changed(void *data)
c8076604 4673{
8cfdc000
ZA		 4674 struct cpufreq_freqs *freq = data;
4675 unsigned long khz = 0;
4676
4677 if (data)
4678 khz = freq->new;
4679 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4680 khz = cpufreq_quick_get(raw_smp_processor_id());
4681 if (!khz)
4682 khz = tsc_khz;
0a3aee0d 4683 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4684}
4685
c8076604
GH		 4686static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4687 void *data)
4688{
4689 struct cpufreq_freqs *freq = data;
4690 struct kvm *kvm;
4691 struct kvm_vcpu *vcpu;
4692 int i, send_ipi = 0;
4693
8cfdc000
ZA		 4694 /*
4695 * We allow guests to temporarily run on slowing clocks,
4696 * provided we notify them after, or to run on accelerating
4697 * clocks, provided we notify them before. Thus time never
4698 * goes backwards.
4699 *
4700 * However, we have a problem. We can't atomically update
4701 * the frequency of a given CPU from this function; it is
4702 * merely a notifier, which can be called from any CPU.
4703 * Changing the TSC frequency at arbitrary points in time
4704 * requires a recomputation of local variables related to
4705 * the TSC for each VCPU. We must flag these local variables
4706 * to be updated and be sure the update takes place with the
4707 * new frequency before any guests proceed.
4708 *
4709 * Unfortunately, the combination of hotplug CPU and frequency
4710 * change creates an intractable locking scenario; the order
4711 * of when these callouts happen is undefined with respect to
4712 * CPU hotplug, and they can race with each other. As such,
4713 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4714 * undefined; you can actually have a CPU frequency change take
4715 * place in between the computation of X and the setting of the
4716 * variable. To protect against this problem, all updates of
4717 * the per_cpu tsc_khz variable are done in an interrupt
4718 * protected IPI, and all callers wishing to update the value
4719 * must wait for a synchronous IPI to complete (which is trivial
4720 * if the caller is on the CPU already). This establishes the
4721 * necessary total order on variable updates.
4722 *
4723 * Note that because a guest time update may take place
4724 * anytime after the setting of the VCPU's request bit, the
4725 * correct TSC value must be set before the request. However,
4726 * to ensure the update actually makes it to any guest which
4727 * starts running in hardware virtualization between the set
4728 * and the acquisition of the spinlock, we must also ping the
4729 * CPU after setting the request bit.
4730 *
4731 */
4732
c8076604
GH		 4733 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4734 return 0;
4735 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4736 return 0;
8cfdc000
ZA		 4737
4738 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4739
e935b837 4740 raw_spin_lock(&kvm_lock);
c8076604 4741 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4742 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4743 if (vcpu->cpu != freq->cpu)
4744 continue;
c285545f 4745 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4746 if (vcpu->cpu != smp_processor_id())
8cfdc000 4747 send_ipi = 1;
c8076604
GH		 4748 }
4749 }
e935b837 4750 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4751
4752 if (freq->old < freq->new && send_ipi) {
4753 /*
4754 * We upscale the frequency. Must make the guest
4755 * doesn't see old kvmclock values while running with
4756 * the new frequency, otherwise we risk the guest sees
4757 * time go backwards.
4758 *
4759 * In case we update the frequency for another cpu
4760 * (which might be in guest context) send an interrupt
4761 * to kick the cpu out of guest context. Next time
4762 * guest context is entered kvmclock will be updated,
4763 * so the guest will not see stale values.
4764 */
8cfdc000 4765 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4766 }
4767 return 0;
4768}
4769
4770static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4771 .notifier_call = kvmclock_cpufreq_notifier
4772};
4773
4774static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4775 unsigned long action, void *hcpu)
4776{
4777 unsigned int cpu = (unsigned long)hcpu;
4778
4779 switch (action) {
4780 case CPU_ONLINE:
4781 case CPU_DOWN_FAILED:
4782 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4783 break;
4784 case CPU_DOWN_PREPARE:
4785 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4786 break;
4787 }
4788 return NOTIFY_OK;
4789}
4790
4791static struct notifier_block kvmclock_cpu_notifier_block = {
4792 .notifier_call = kvmclock_cpu_notifier,
4793 .priority = -INT_MAX
c8076604
GH		 4794};
4795
b820cc0c
ZA		 4796static void kvm_timer_init(void)
4797{
4798 int cpu;
4799
c285545f 4800 max_tsc_khz = tsc_khz;
8cfdc000 4801 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4802 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4803#ifdef CONFIG_CPU_FREQ
4804 struct cpufreq_policy policy;
4805 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4806 cpu = get_cpu();
4807 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4808 if (policy.cpuinfo.max_freq)
4809 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4810 put_cpu();
c285545f 4811#endif
b820cc0c
ZA		 4812 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4813 CPUFREQ_TRANSITION_NOTIFIER);
4814 }
c285545f 4815 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4816 for_each_online_cpu(cpu)
4817 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4818}
4819
ff9d07a0
ZY		 4820static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4821
f5132b01 4822int kvm_is_in_guest(void)
ff9d07a0 4823{
086c9855 4824 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4825}
4826
4827static int kvm_is_user_mode(void)
4828{
4829 int user_mode = 3;
dcf46b94 4830
086c9855
AS		 4831 if (__this_cpu_read(current_vcpu))
4832 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4833
ff9d07a0
ZY		 4834 return user_mode != 0;
4835}
4836
4837static unsigned long kvm_get_guest_ip(void)
4838{
4839 unsigned long ip = 0;
dcf46b94 4840
086c9855
AS		 4841 if (__this_cpu_read(current_vcpu))
4842 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4843
ff9d07a0
ZY		 4844 return ip;
4845}
4846
4847static struct perf_guest_info_callbacks kvm_guest_cbs = {
4848 .is_in_guest = kvm_is_in_guest,
4849 .is_user_mode = kvm_is_user_mode,
4850 .get_guest_ip = kvm_get_guest_ip,
4851};
4852
4853void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4854{
086c9855 4855 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4856}
4857EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4858
4859void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4860{
086c9855 4861 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4862}
4863EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4864
ce88decf
XG		 4865static void kvm_set_mmio_spte_mask(void)
4866{
4867 u64 mask;
4868 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4869
4870 /*
4871 * Set the reserved bits and the present bit of an paging-structure
4872 * entry to generate page fault with PFER.RSV = 1.
4873 */
4874 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4875 mask |= 1ull;
4876
4877#ifdef CONFIG_X86_64
4878 /*
4879 * If reserved bit is not supported, clear the present bit to disable
4880 * mmio page fault.
4881 */
4882 if (maxphyaddr == 52)
4883 mask &= ~1ull;
4884#endif
4885
4886 kvm_mmu_set_mmio_spte_mask(mask);
4887}
4888
f8c16bba 4889int kvm_arch_init(void *opaque)
043405e1 4890{
b820cc0c 4891 int r;
f8c16bba
ZX		 4892 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4893
f8c16bba
ZX		 4894 if (kvm_x86_ops) {
4895 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4896 r = -EEXIST;
4897 goto out;
f8c16bba
ZX		 4898 }
4899
4900 if (!ops->cpu_has_kvm_support()) {
4901 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4902 r = -EOPNOTSUPP;
4903 goto out;
f8c16bba
ZX		 4904 }
4905 if (ops->disabled_by_bios()) {
4906 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4907 r = -EOPNOTSUPP;
4908 goto out;
f8c16bba
ZX		 4909 }
4910
97db56ce
AK		 4911 r = kvm_mmu_module_init();
4912 if (r)
4913 goto out;
4914
ce88decf 4915 kvm_set_mmio_spte_mask();
97db56ce
AK		 4916 kvm_init_msr_list();
4917
f8c16bba 4918 kvm_x86_ops = ops;
7b52345e 4919 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4920 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4921
b820cc0c 4922 kvm_timer_init();
c8076604 4923
ff9d07a0
ZY		 4924 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4925
2acf923e
DC		 4926 if (cpu_has_xsave)
4927 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4928
f8c16bba 4929 return 0;
56c6d28a
ZX		 4930
4931out:
56c6d28a 4932 return r;
043405e1 4933}
8776e519 4934
f8c16bba
ZX		 4935void kvm_arch_exit(void)
4936{
ff9d07a0
ZY		 4937 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4938
888d256e
JK		 4939 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4940 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4941 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4942 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4943 kvm_x86_ops = NULL;
56c6d28a
ZX		 4944 kvm_mmu_module_exit();
4945}
f8c16bba 4946
8776e519
HB		 4947int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4948{
4949 ++vcpu->stat.halt_exits;
4950 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4951 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4952 return 1;
4953 } else {
4954 vcpu->run->exit_reason = KVM_EXIT_HLT;
4955 return 0;
4956 }
4957}
4958EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4959
55cd8e5a
GN		 4960int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4961{
4962 u64 param, ingpa, outgpa, ret;
4963 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4964 bool fast, longmode;
4965 int cs_db, cs_l;
4966
4967 /*
4968 * hypercall generates UD from non zero cpl and real mode
4969 * per HYPER-V spec
4970 */
3eeb3288 4971 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4972 kvm_queue_exception(vcpu, UD_VECTOR);
4973 return 0;
4974 }
4975
4976 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4977 longmode = is_long_mode(vcpu) && cs_l == 1;
4978
4979 if (!longmode) {
ccd46936
GN		 4980 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4981 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4982 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4983 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4984 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4985 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4986 }
4987#ifdef CONFIG_X86_64
4988 else {
4989 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4990 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4991 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4992 }
4993#endif
4994
4995 code = param & 0xffff;
4996 fast = (param >> 16) & 0x1;
4997 rep_cnt = (param >> 32) & 0xfff;
4998 rep_idx = (param >> 48) & 0xfff;
4999
5000 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5001
c25bc163
GN		 5002 switch (code) {
5003 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5004 kvm_vcpu_on_spin(vcpu);
5005 break;
5006 default:
5007 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5008 break;
5009 }
55cd8e5a
GN		 5010
5011 ret = res | (((u64)rep_done & 0xfff) << 32);
5012 if (longmode) {
5013 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5014 } else {
5015 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5016 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5017 }
5018
5019 return 1;
5020}
5021
8776e519
HB		 5022int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5023{
5024 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5025 int r = 1;
8776e519 5026
55cd8e5a
GN		 5027 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5028 return kvm_hv_hypercall(vcpu);
5029
5fdbf976
MT		 5030 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5031 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5032 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5033 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5034 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5035
229456fc 5036 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5037
8776e519
HB		 5038 if (!is_long_mode(vcpu)) {
5039 nr &= 0xFFFFFFFF;
5040 a0 &= 0xFFFFFFFF;
5041 a1 &= 0xFFFFFFFF;
5042 a2 &= 0xFFFFFFFF;
5043 a3 &= 0xFFFFFFFF;
5044 }
5045
07708c4a
JK		 5046 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5047 ret = -KVM_EPERM;
5048 goto out;
5049 }
5050
8776e519 5051 switch (nr) {
b93463aa
AK		 5052 case KVM_HC_VAPIC_POLL_IRQ:
5053 ret = 0;
5054 break;
8776e519
HB		 5055 default:
5056 ret = -KVM_ENOSYS;
5057 break;
5058 }
07708c4a 5059out:
5fdbf976 5060 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5061 ++vcpu->stat.hypercalls;
2f333bcb 5062 return r;
8776e519
HB		 5063}
5064EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5065
d6aa1000 5066int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5067{
d6aa1000 5068 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5069 char instruction[3];
5fdbf976 5070 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5071
8776e519
HB		 5072 /*
5073 * Blow out the MMU to ensure that no other VCPU has an active mapping
5074 * to ensure that the updated hypercall appears atomically across all
5075 * VCPUs.
5076 */
5077 kvm_mmu_zap_all(vcpu->kvm);
5078
8776e519 5079 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5080
9d74191a 5081 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5082}
5083
b6c7a5dc
HB		 5084/*
5085 * Check if userspace requested an interrupt window, and that the
5086 * interrupt window is open.
5087 *
5088 * No need to exit to userspace if we already have an interrupt queued.
5089 */
851ba692 5090static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5091{
8061823a 5092 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5093 vcpu->run->request_interrupt_window &&
5df56646 5094 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5095}
5096
851ba692 5097static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5098{
851ba692
AK		 5099 struct kvm_run *kvm_run = vcpu->run;
5100
91586a3b 5101 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5102 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5103 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5104 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5105 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5106 else
b6c7a5dc 5107 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5108 kvm_arch_interrupt_allowed(vcpu) &&
5109 !kvm_cpu_has_interrupt(vcpu) &&
5110 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5111}
5112
b93463aa
AK		 5113static void vapic_enter(struct kvm_vcpu *vcpu)
5114{
5115 struct kvm_lapic *apic = vcpu->arch.apic;
5116 struct page *page;
5117
5118 if (!apic || !apic->vapic_addr)
5119 return;
5120
5121 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5122
5123 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5124}
5125
5126static void vapic_exit(struct kvm_vcpu *vcpu)
5127{
5128 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5129 int idx;
b93463aa
AK		 5130
5131 if (!apic || !apic->vapic_addr)
5132 return;
5133
f656ce01 5134 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5135 kvm_release_page_dirty(apic->vapic_page);
5136 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5137 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5138}
5139
95ba8273
GN		 5140static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5141{
5142 int max_irr, tpr;
5143
5144 if (!kvm_x86_ops->update_cr8_intercept)
5145 return;
5146
88c808fd
AK		 5147 if (!vcpu->arch.apic)
5148 return;
5149
8db3baa2
GN		 5150 if (!vcpu->arch.apic->vapic_addr)
5151 max_irr = kvm_lapic_find_highest_irr(vcpu);
5152 else
5153 max_irr = -1;
95ba8273
GN		 5154
5155 if (max_irr != -1)
5156 max_irr >>= 4;
5157
5158 tpr = kvm_lapic_get_cr8(vcpu);
5159
5160 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5161}
5162
851ba692 5163static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5164{
5165 /* try to reinject previous events if any */
b59bb7bd 5166 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5167 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5168 vcpu->arch.exception.has_error_code,
5169 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5170 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5171 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5172 vcpu->arch.exception.error_code,
5173 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5174 return;
5175 }
5176
95ba8273
GN		 5177 if (vcpu->arch.nmi_injected) {
5178 kvm_x86_ops->set_nmi(vcpu);
5179 return;
5180 }
5181
5182 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5183 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5184 return;
5185 }
5186
5187 /* try to inject new event if pending */
5188 if (vcpu->arch.nmi_pending) {
5189 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5190 --vcpu->arch.nmi_pending;
95ba8273
GN		 5191 vcpu->arch.nmi_injected = true;
5192 kvm_x86_ops->set_nmi(vcpu);
5193 }
5194 } else if (kvm_cpu_has_interrupt(vcpu)) {
5195 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5196 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5197 false);
5198 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5199 }
5200 }
5201}
5202
2acf923e
DC		 5203static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5204{
5205 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5206 !vcpu->guest_xcr0_loaded) {
5207 /* kvm_set_xcr() also depends on this */
5208 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5209 vcpu->guest_xcr0_loaded = 1;
5210 }
5211}
5212
5213static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5214{
5215 if (vcpu->guest_xcr0_loaded) {
5216 if (vcpu->arch.xcr0 != host_xcr0)
5217 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5218 vcpu->guest_xcr0_loaded = 0;
5219 }
5220}
5221
7460fb4a
AK		 5222static void process_nmi(struct kvm_vcpu *vcpu)
5223{
5224 unsigned limit = 2;
5225
5226 /*
5227 * x86 is limited to one NMI running, and one NMI pending after it.
5228 * If an NMI is already in progress, limit further NMIs to just one.
5229 * Otherwise, allow two (and we'll inject the first one immediately).
5230 */
5231 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5232 limit = 1;
5233
5234 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5235 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5236 kvm_make_request(KVM_REQ_EVENT, vcpu);
5237}
5238
851ba692 5239static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5240{
5241 int r;
6a8b1d13 5242 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5243 vcpu->run->request_interrupt_window;
d6185f20 5244 bool req_immediate_exit = 0;
b6c7a5dc 5245
3e007509 5246 if (vcpu->requests) {
a8eeb04a 5247 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5248 kvm_mmu_unload(vcpu);
a8eeb04a 5249 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5250 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5251 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5252 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5253 if (unlikely(r))
5254 goto out;
5255 }
a8eeb04a 5256 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5257 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5258 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5259 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5260 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5261 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5262 r = 0;
5263 goto out;
5264 }
a8eeb04a 5265 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5266 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5267 r = 0;
5268 goto out;
5269 }
a8eeb04a 5270 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5271 vcpu->fpu_active = 0;
5272 kvm_x86_ops->fpu_deactivate(vcpu);
5273 }
af585b92
GN		 5274 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5275 /* Page is swapped out. Do synthetic halt */
5276 vcpu->arch.apf.halted = true;
5277 r = 1;
5278 goto out;
5279 }
c9aaa895
GC		 5280 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5281 record_steal_time(vcpu);
7460fb4a
AK		 5282 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5283 process_nmi(vcpu);
d6185f20
NHE		 5284 req_immediate_exit =
5285 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5286 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5287 kvm_handle_pmu_event(vcpu);
5288 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5289 kvm_deliver_pmi(vcpu);
2f52d58c 5290 }
b93463aa 5291
b463a6f7
AK		 5292 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5293 inject_pending_event(vcpu);
5294
5295 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5296 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5297 kvm_x86_ops->enable_nmi_window(vcpu);
5298 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5299 kvm_x86_ops->enable_irq_window(vcpu);
5300
5301 if (kvm_lapic_enabled(vcpu)) {
5302 update_cr8_intercept(vcpu);
5303 kvm_lapic_sync_to_vapic(vcpu);
5304 }
5305 }
5306
d8368af8
AK		 5307 r = kvm_mmu_reload(vcpu);
5308 if (unlikely(r)) {
d905c069 5309 goto cancel_injection;
d8368af8
AK		 5310 }
5311
b6c7a5dc
HB		 5312 preempt_disable();
5313
5314 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5315 if (vcpu->fpu_active)
5316 kvm_load_guest_fpu(vcpu);
2acf923e 5317 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5318
6b7e2d09
XG		 5319 vcpu->mode = IN_GUEST_MODE;
5320
5321 /* We should set ->mode before check ->requests,
5322 * see the comment in make_all_cpus_request.
5323 */
5324 smp_mb();
b6c7a5dc 5325
d94e1dc9 5326 local_irq_disable();
32f88400 5327
6b7e2d09 5328 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5329 || need_resched() || signal_pending(current)) {
6b7e2d09 5330 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5331 smp_wmb();
6c142801
AK		 5332 local_irq_enable();
5333 preempt_enable();
5334 r = 1;
d905c069 5335 goto cancel_injection;
6c142801
AK		 5336 }
5337
f656ce01 5338 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5339
d6185f20
NHE		 5340 if (req_immediate_exit)
5341 smp_send_reschedule(vcpu->cpu);
5342
b6c7a5dc
HB		 5343 kvm_guest_enter();
5344
42dbaa5a 5345 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5346 set_debugreg(0, 7);
5347 set_debugreg(vcpu->arch.eff_db[0], 0);
5348 set_debugreg(vcpu->arch.eff_db[1], 1);
5349 set_debugreg(vcpu->arch.eff_db[2], 2);
5350 set_debugreg(vcpu->arch.eff_db[3], 3);
5351 }
b6c7a5dc 5352
229456fc 5353 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5354 kvm_x86_ops->run(vcpu);
b6c7a5dc 5355
24f1e32c
FW		 5356 /*
5357 * If the guest has used debug registers, at least dr7
5358 * will be disabled while returning to the host.
5359 * If we don't have active breakpoints in the host, we don't
5360 * care about the messed up debug address registers. But if
5361 * we have some of them active, restore the old state.
5362 */
59d8eb53 5363 if (hw_breakpoint_active())
24f1e32c 5364 hw_breakpoint_restore();
42dbaa5a 5365
d5c1785d 5366 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5367
6b7e2d09 5368 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5369 smp_wmb();
b6c7a5dc
HB		 5370 local_irq_enable();
5371
5372 ++vcpu->stat.exits;
5373
5374 /*
5375 * We must have an instruction between local_irq_enable() and
5376 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5377 * the interrupt shadow. The stat.exits increment will do nicely.
5378 * But we need to prevent reordering, hence this barrier():
5379 */
5380 barrier();
5381
5382 kvm_guest_exit();
5383
5384 preempt_enable();
5385
f656ce01 5386 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5387
b6c7a5dc
HB		 5388 /*
5389 * Profile KVM exit RIPs:
5390 */
5391 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5392 unsigned long rip = kvm_rip_read(vcpu);
5393 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5394 }
5395
cc578287
ZA		 5396 if (unlikely(vcpu->arch.tsc_always_catchup))
5397 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5398
5cfb1d5a
MT		 5399 if (vcpu->arch.apic_attention)
5400 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5401
851ba692 5402 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5403 return r;
5404
5405cancel_injection:
5406 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5407 if (unlikely(vcpu->arch.apic_attention))
5408 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5409out:
5410 return r;
5411}
b6c7a5dc 5412
09cec754 5413
851ba692 5414static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5415{
5416 int r;
f656ce01 5417 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5418
5419 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5420 pr_debug("vcpu %d received sipi with vector # %x\n",
5421 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5422 kvm_lapic_reset(vcpu);
5f179287 5423 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5424 if (r)
5425 return r;
5426 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5427 }
5428
f656ce01 5429 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5430 vapic_enter(vcpu);
5431
5432 r = 1;
5433 while (r > 0) {
af585b92
GN		 5434 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5435 !vcpu->arch.apf.halted)
851ba692 5436 r = vcpu_enter_guest(vcpu);
d7690175 5437 else {
f656ce01 5438 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5439 kvm_vcpu_block(vcpu);
f656ce01 5440 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5441 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5442 {
5443 switch(vcpu->arch.mp_state) {
5444 case KVM_MP_STATE_HALTED:
d7690175 5445 vcpu->arch.mp_state =
09cec754
GN		 5446 KVM_MP_STATE_RUNNABLE;
5447 case KVM_MP_STATE_RUNNABLE:
af585b92 5448 vcpu->arch.apf.halted = false;
09cec754
GN		 5449 break;
5450 case KVM_MP_STATE_SIPI_RECEIVED:
5451 default:
5452 r = -EINTR;
5453 break;
5454 }
5455 }
d7690175
MT		 5456 }
5457
09cec754
GN		 5458 if (r <= 0)
5459 break;
5460
5461 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5462 if (kvm_cpu_has_pending_timer(vcpu))
5463 kvm_inject_pending_timer_irqs(vcpu);
5464
851ba692 5465 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5466 r = -EINTR;
851ba692 5467 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5468 ++vcpu->stat.request_irq_exits;
5469 }
af585b92
GN		 5470
5471 kvm_check_async_pf_completion(vcpu);
5472
09cec754
GN		 5473 if (signal_pending(current)) {
5474 r = -EINTR;
851ba692 5475 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5476 ++vcpu->stat.signal_exits;
5477 }
5478 if (need_resched()) {
f656ce01 5479 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5480 kvm_resched(vcpu);
f656ce01 5481 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5482 }
b6c7a5dc
HB		 5483 }
5484
f656ce01 5485 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5486
b93463aa
AK		 5487 vapic_exit(vcpu);
5488
b6c7a5dc
HB		 5489 return r;
5490}
5491
f78146b0
AK		 5492/*
5493 * Implements the following, as a state machine:
5494 *
5495 * read:
5496 * for each fragment
5497 * write gpa, len
5498 * exit
5499 * copy data
5500 * execute insn
5501 *
5502 * write:
5503 * for each fragment
5504 * write gpa, len
5505 * copy data
5506 * exit
5507 */
5287f194
AK		 5508static int complete_mmio(struct kvm_vcpu *vcpu)
5509{
5510 struct kvm_run *run = vcpu->run;
f78146b0 5511 struct kvm_mmio_fragment *frag;
5287f194
AK		 5512 int r;
5513
5514 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5515 return 1;
5516
5517 if (vcpu->mmio_needed) {
f78146b0
AK		 5518 /* Complete previous fragment */
5519 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
cef4dea0 5520 if (!vcpu->mmio_is_write)
f78146b0
AK		 5521 memcpy(frag->data, run->mmio.data, frag->len);
5522 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5523 vcpu->mmio_needed = 0;
5524 if (vcpu->mmio_is_write)
5525 return 1;
5526 vcpu->mmio_read_completed = 1;
5527 goto done;
cef4dea0 5528 }
f78146b0
AK		 5529 /* Initiate next fragment */
5530 ++frag;
5531 run->exit_reason = KVM_EXIT_MMIO;
5532 run->mmio.phys_addr = frag->gpa;
cef4dea0 5533 if (vcpu->mmio_is_write)
f78146b0
AK		 5534 memcpy(run->mmio.data, frag->data, frag->len);
5535 run->mmio.len = frag->len;
5536 run->mmio.is_write = vcpu->mmio_is_write;
5537 return 0;
5538
5287f194 5539 }
f78146b0 5540done:
5287f194
AK		 5541 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5542 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5543 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5544 if (r != EMULATE_DONE)
5545 return 0;
5546 return 1;
5547}
5548
b6c7a5dc
HB		 5549int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5550{
5551 int r;
5552 sigset_t sigsaved;
5553
e5c30142
AK		 5554 if (!tsk_used_math(current) && init_fpu(current))
5555 return -ENOMEM;
5556
ac9f6dc0
AK		 5557 if (vcpu->sigset_active)
5558 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5559
a4535290 5560 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5561 kvm_vcpu_block(vcpu);
d7690175 5562 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5563 r = -EAGAIN;
5564 goto out;
b6c7a5dc
HB		 5565 }
5566
b6c7a5dc 5567 /* re-sync apic's tpr */
eea1cff9
AP		 5568 if (!irqchip_in_kernel(vcpu->kvm)) {
5569 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5570 r = -EINVAL;
5571 goto out;
5572 }
5573 }
b6c7a5dc 5574
5287f194
AK		 5575 r = complete_mmio(vcpu);
5576 if (r <= 0)
5577 goto out;
5578
851ba692 5579 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5580
5581out:
f1d86e46 5582 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5583 if (vcpu->sigset_active)
5584 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5585
b6c7a5dc
HB		 5586 return r;
5587}
5588
5589int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5590{
7ae441ea
GN		 5591 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5592 /*
5593 * We are here if userspace calls get_regs() in the middle of
5594 * instruction emulation. Registers state needs to be copied
5595 * back from emulation context to vcpu. Usrapace shouldn't do
5596 * that usually, but some bad designed PV devices (vmware
5597 * backdoor interface) need this to work
5598 */
9dac77fa
AK		 5599 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5600 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5601 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5602 }
5fdbf976
MT		 5603 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5604 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5605 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5606 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5607 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5608 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5609 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5610 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5611#ifdef CONFIG_X86_64
5fdbf976
MT		 5612 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5613 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5614 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5615 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5616 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5617 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5618 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5619 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5620#endif
5621
5fdbf976 5622 regs->rip = kvm_rip_read(vcpu);
91586a3b 5623 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5624
b6c7a5dc
HB		 5625 return 0;
5626}
5627
5628int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5629{
7ae441ea
GN		 5630 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5631 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5632
5fdbf976
MT		 5633 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5634 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5635 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5636 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5637 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5638 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5639 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5640 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5641#ifdef CONFIG_X86_64
5fdbf976
MT		 5642 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5643 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5644 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5645 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5646 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5647 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5648 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5649 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5650#endif
5651
5fdbf976 5652 kvm_rip_write(vcpu, regs->rip);
91586a3b 5653 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5654
b4f14abd
JK		 5655 vcpu->arch.exception.pending = false;
5656
3842d135
AK		 5657 kvm_make_request(KVM_REQ_EVENT, vcpu);
5658
b6c7a5dc
HB		 5659 return 0;
5660}
5661
b6c7a5dc
HB		 5662void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5663{
5664 struct kvm_segment cs;
5665
3e6e0aab 5666 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5667 *db = cs.db;
5668 *l = cs.l;
5669}
5670EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5671
5672int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5673 struct kvm_sregs *sregs)
5674{
89a27f4d 5675 struct desc_ptr dt;
b6c7a5dc 5676
3e6e0aab
GT		 5677 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5678 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5679 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5680 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5681 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5682 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5683
3e6e0aab
GT		 5684 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5685 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5686
5687 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5688 sregs->idt.limit = dt.size;
5689 sregs->idt.base = dt.address;
b6c7a5dc 5690 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5691 sregs->gdt.limit = dt.size;
5692 sregs->gdt.base = dt.address;
b6c7a5dc 5693
4d4ec087 5694 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5695 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5696 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5697 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5698 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5699 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5700 sregs->apic_base = kvm_get_apic_base(vcpu);
5701
923c61bb 5702 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5703
36752c9b 5704 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5705 set_bit(vcpu->arch.interrupt.nr,
5706 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5707
b6c7a5dc
HB		 5708 return 0;
5709}
5710
62d9f0db
MT		 5711int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5712 struct kvm_mp_state *mp_state)
5713{
62d9f0db 5714 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5715 return 0;
5716}
5717
5718int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5719 struct kvm_mp_state *mp_state)
5720{
62d9f0db 5721 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5722 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5723 return 0;
5724}
5725
7f3d35fd
KW		 5726int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5727 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 5728{
9d74191a 5729 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5730 int ret;
e01c2426 5731
8ec4722d 5732 init_emulate_ctxt(vcpu);
c697518a 5733
7f3d35fd 5734 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 5735 has_error_code, error_code);
c697518a 5736
c697518a 5737 if (ret)
19d04437 5738 return EMULATE_FAIL;
37817f29 5739
9dac77fa 5740 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 5741 kvm_rip_write(vcpu, ctxt->eip);
5742 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5743 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5744 return EMULATE_DONE;
37817f29
IE		 5745}
5746EXPORT_SYMBOL_GPL(kvm_task_switch);
5747
b6c7a5dc
HB		 5748int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5749 struct kvm_sregs *sregs)
5750{
5751 int mmu_reset_needed = 0;
63f42e02 5752 int pending_vec, max_bits, idx;
89a27f4d 5753 struct desc_ptr dt;
b6c7a5dc 5754
89a27f4d
GN		 5755 dt.size = sregs->idt.limit;
5756 dt.address = sregs->idt.base;
b6c7a5dc 5757 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5758 dt.size = sregs->gdt.limit;
5759 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5760 kvm_x86_ops->set_gdt(vcpu, &dt);
5761
ad312c7c 5762 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5763 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5764 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5765 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5766
2d3ad1f4 5767 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5768
f6801dff 5769 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5770 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5771 kvm_set_apic_base(vcpu, sregs->apic_base);
5772
4d4ec087 5773 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5774 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5775 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5776
fc78f519 5777 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5778 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5779 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5780 kvm_update_cpuid(vcpu);
63f42e02
XG		 5781
5782 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5783 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5784 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5785 mmu_reset_needed = 1;
5786 }
63f42e02 5787 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5788
5789 if (mmu_reset_needed)
5790 kvm_mmu_reset_context(vcpu);
5791
923c61bb
GN		 5792 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5793 pending_vec = find_first_bit(
5794 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5795 if (pending_vec < max_bits) {
66fd3f7f 5796 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5797 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5798 }
5799
3e6e0aab
GT		 5800 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5801 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5802 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5803 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5804 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5805 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5806
3e6e0aab
GT		 5807 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5808 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5809
5f0269f5
ME		 5810 update_cr8_intercept(vcpu);
5811
9c3e4aab 5812 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5813 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5814 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5815 !is_protmode(vcpu))
9c3e4aab
MT		 5816 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5817
3842d135
AK		 5818 kvm_make_request(KVM_REQ_EVENT, vcpu);
5819
b6c7a5dc
HB		 5820 return 0;
5821}
5822
d0bfb940
JK		 5823int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5824 struct kvm_guest_debug *dbg)
b6c7a5dc 5825{
355be0b9 5826 unsigned long rflags;
ae675ef0 5827 int i, r;
b6c7a5dc 5828
4f926bf2
JK		 5829 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5830 r = -EBUSY;
5831 if (vcpu->arch.exception.pending)
2122ff5e 5832 goto out;
4f926bf2
JK		 5833 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5834 kvm_queue_exception(vcpu, DB_VECTOR);
5835 else
5836 kvm_queue_exception(vcpu, BP_VECTOR);
5837 }
5838
91586a3b
JK		 5839 /*
5840 * Read rflags as long as potentially injected trace flags are still
5841 * filtered out.
5842 */
5843 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5844
5845 vcpu->guest_debug = dbg->control;
5846 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5847 vcpu->guest_debug = 0;
5848
5849 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5850 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5851 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5852 vcpu->arch.switch_db_regs =
5853 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5854 } else {
5855 for (i = 0; i < KVM_NR_DB_REGS; i++)
5856 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5857 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5858 }
5859
f92653ee
JK		 5860 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5861 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5862 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5863
91586a3b
JK		 5864 /*
5865 * Trigger an rflags update that will inject or remove the trace
5866 * flags.
5867 */
5868 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5869
355be0b9 5870 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5871
4f926bf2 5872 r = 0;
d0bfb940 5873
2122ff5e 5874out:
b6c7a5dc
HB		 5875
5876 return r;
5877}
5878
8b006791
ZX		 5879/*
5880 * Translate a guest virtual address to a guest physical address.
5881 */
5882int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5883 struct kvm_translation *tr)
5884{
5885 unsigned long vaddr = tr->linear_address;
5886 gpa_t gpa;
f656ce01 5887 int idx;
8b006791 5888
f656ce01 5889 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5890 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5891 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5892 tr->physical_address = gpa;
5893 tr->valid = gpa != UNMAPPED_GVA;
5894 tr->writeable = 1;
5895 tr->usermode = 0;
8b006791
ZX		 5896
5897 return 0;
5898}
5899
d0752060
HB		 5900int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5901{
98918833
SY		 5902 struct i387_fxsave_struct *fxsave =
5903 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5904
d0752060
HB		 5905 memcpy(fpu->fpr, fxsave->st_space, 128);
5906 fpu->fcw = fxsave->cwd;
5907 fpu->fsw = fxsave->swd;
5908 fpu->ftwx = fxsave->twd;
5909 fpu->last_opcode = fxsave->fop;
5910 fpu->last_ip = fxsave->rip;
5911 fpu->last_dp = fxsave->rdp;
5912 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5913
d0752060
HB		 5914 return 0;
5915}
5916
5917int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5918{
98918833
SY		 5919 struct i387_fxsave_struct *fxsave =
5920 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5921
d0752060
HB		 5922 memcpy(fxsave->st_space, fpu->fpr, 128);
5923 fxsave->cwd = fpu->fcw;
5924 fxsave->swd = fpu->fsw;
5925 fxsave->twd = fpu->ftwx;
5926 fxsave->fop = fpu->last_opcode;
5927 fxsave->rip = fpu->last_ip;
5928 fxsave->rdp = fpu->last_dp;
5929 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5930
d0752060
HB		 5931 return 0;
5932}
5933
10ab25cd 5934int fx_init(struct kvm_vcpu *vcpu)
d0752060 5935{
10ab25cd
JK		 5936 int err;
5937
5938 err = fpu_alloc(&vcpu->arch.guest_fpu);
5939 if (err)
5940 return err;
5941
98918833 5942 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5943
2acf923e
DC		 5944 /*
5945 * Ensure guest xcr0 is valid for loading
5946 */
5947 vcpu->arch.xcr0 = XSTATE_FP;
5948
ad312c7c 5949 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5950
5951 return 0;
d0752060
HB		 5952}
5953EXPORT_SYMBOL_GPL(fx_init);
5954
98918833
SY		 5955static void fx_free(struct kvm_vcpu *vcpu)
5956{
5957 fpu_free(&vcpu->arch.guest_fpu);
5958}
5959
d0752060
HB		 5960void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5961{
2608d7a1 5962 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5963 return;
5964
2acf923e
DC		 5965 /*
5966 * Restore all possible states in the guest,
5967 * and assume host would use all available bits.
5968 * Guest xcr0 would be loaded later.
5969 */
5970 kvm_put_guest_xcr0(vcpu);
d0752060 5971 vcpu->guest_fpu_loaded = 1;
7cf30855 5972 unlazy_fpu(current);
98918833 5973 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5974 trace_kvm_fpu(1);
d0752060 5975}
d0752060
HB		 5976
5977void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5978{
2acf923e
DC		 5979 kvm_put_guest_xcr0(vcpu);
5980
d0752060
HB		 5981 if (!vcpu->guest_fpu_loaded)
5982 return;
5983
5984 vcpu->guest_fpu_loaded = 0;
98918833 5985 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5986 ++vcpu->stat.fpu_reload;
a8eeb04a 5987 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5988 trace_kvm_fpu(0);
d0752060 5989}
e9b11c17
ZX		 5990
5991void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5992{
12f9a48f 5993 kvmclock_reset(vcpu);
7f1ea208 5994
f5f48ee1 5995 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5996 fx_free(vcpu);
e9b11c17
ZX		 5997 kvm_x86_ops->vcpu_free(vcpu);
5998}
5999
6000struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6001 unsigned int id)
6002{
6755bae8
ZA		 6003 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6004 printk_once(KERN_WARNING
6005 "kvm: SMP vm created on host with unstable TSC; "
6006 "guest TSC will not be reliable\n");
26e5215f
AK		 6007 return kvm_x86_ops->vcpu_create(kvm, id);
6008}
e9b11c17 6009
26e5215f
AK		 6010int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6011{
6012 int r;
e9b11c17 6013
0bed3b56 6014 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 6015 vcpu_load(vcpu);
6016 r = kvm_arch_vcpu_reset(vcpu);
6017 if (r == 0)
6018 r = kvm_mmu_setup(vcpu);
6019 vcpu_put(vcpu);
e9b11c17 6020
26e5215f 6021 return r;
e9b11c17
ZX		 6022}
6023
d40ccc62 6024void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6025{
344d9588
GN		 6026 vcpu->arch.apf.msr_val = 0;
6027
e9b11c17
ZX		 6028 vcpu_load(vcpu);
6029 kvm_mmu_unload(vcpu);
6030 vcpu_put(vcpu);
6031
98918833 6032 fx_free(vcpu);
e9b11c17
ZX		 6033 kvm_x86_ops->vcpu_free(vcpu);
6034}
6035
6036int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6037{
7460fb4a
AK		 6038 atomic_set(&vcpu->arch.nmi_queued, 0);
6039 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6040 vcpu->arch.nmi_injected = false;
6041
42dbaa5a
JK		 6042 vcpu->arch.switch_db_regs = 0;
6043 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6044 vcpu->arch.dr6 = DR6_FIXED_1;
6045 vcpu->arch.dr7 = DR7_FIXED_1;
6046
3842d135 6047 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6048 vcpu->arch.apf.msr_val = 0;
c9aaa895 6049 vcpu->arch.st.msr_val = 0;
3842d135 6050
12f9a48f
GC		 6051 kvmclock_reset(vcpu);
6052
af585b92
GN		 6053 kvm_clear_async_pf_completion_queue(vcpu);
6054 kvm_async_pf_hash_reset(vcpu);
6055 vcpu->arch.apf.halted = false;
3842d135 6056
f5132b01
GN		 6057 kvm_pmu_reset(vcpu);
6058
e9b11c17
ZX		 6059 return kvm_x86_ops->vcpu_reset(vcpu);
6060}
6061
10474ae8 6062int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6063{
ca84d1a2
ZA		 6064 struct kvm *kvm;
6065 struct kvm_vcpu *vcpu;
6066 int i;
0dd6a6ed
ZA		 6067 int ret;
6068 u64 local_tsc;
6069 u64 max_tsc = 0;
6070 bool stable, backwards_tsc = false;
18863bdd
AK		 6071
6072 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6073 ret = kvm_x86_ops->hardware_enable(garbage);
6074 if (ret != 0)
6075 return ret;
6076
6077 local_tsc = native_read_tsc();
6078 stable = !check_tsc_unstable();
6079 list_for_each_entry(kvm, &vm_list, vm_list) {
6080 kvm_for_each_vcpu(i, vcpu, kvm) {
6081 if (!stable && vcpu->cpu == smp_processor_id())
6082 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6083 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6084 backwards_tsc = true;
6085 if (vcpu->arch.last_host_tsc > max_tsc)
6086 max_tsc = vcpu->arch.last_host_tsc;
6087 }
6088 }
6089 }
6090
6091 /*
6092 * Sometimes, even reliable TSCs go backwards. This happens on
6093 * platforms that reset TSC during suspend or hibernate actions, but
6094 * maintain synchronization. We must compensate. Fortunately, we can
6095 * detect that condition here, which happens early in CPU bringup,
6096 * before any KVM threads can be running. Unfortunately, we can't
6097 * bring the TSCs fully up to date with real time, as we aren't yet far
6098 * enough into CPU bringup that we know how much real time has actually
6099 * elapsed; our helper function, get_kernel_ns() will be using boot
6100 * variables that haven't been updated yet.
6101 *
6102 * So we simply find the maximum observed TSC above, then record the
6103 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6104 * the adjustment will be applied. Note that we accumulate
6105 * adjustments, in case multiple suspend cycles happen before some VCPU
6106 * gets a chance to run again. In the event that no KVM threads get a
6107 * chance to run, we will miss the entire elapsed period, as we'll have
6108 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6109 * loose cycle time. This isn't too big a deal, since the loss will be
6110 * uniform across all VCPUs (not to mention the scenario is extremely
6111 * unlikely). It is possible that a second hibernate recovery happens
6112 * much faster than a first, causing the observed TSC here to be
6113 * smaller; this would require additional padding adjustment, which is
6114 * why we set last_host_tsc to the local tsc observed here.
6115 *
6116 * N.B. - this code below runs only on platforms with reliable TSC,
6117 * as that is the only way backwards_tsc is set above. Also note
6118 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6119 * have the same delta_cyc adjustment applied if backwards_tsc
6120 * is detected. Note further, this adjustment is only done once,
6121 * as we reset last_host_tsc on all VCPUs to stop this from being
6122 * called multiple times (one for each physical CPU bringup).
6123 *
6124 * Platforms with unnreliable TSCs don't have to deal with this, they
6125 * will be compensated by the logic in vcpu_load, which sets the TSC to
6126 * catchup mode. This will catchup all VCPUs to real time, but cannot
6127 * guarantee that they stay in perfect synchronization.
6128 */
6129 if (backwards_tsc) {
6130 u64 delta_cyc = max_tsc - local_tsc;
6131 list_for_each_entry(kvm, &vm_list, vm_list) {
6132 kvm_for_each_vcpu(i, vcpu, kvm) {
6133 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6134 vcpu->arch.last_host_tsc = local_tsc;
6135 }
6136
6137 /*
6138 * We have to disable TSC offset matching.. if you were
6139 * booting a VM while issuing an S4 host suspend....
6140 * you may have some problem. Solving this issue is
6141 * left as an exercise to the reader.
6142 */
6143 kvm->arch.last_tsc_nsec = 0;
6144 kvm->arch.last_tsc_write = 0;
6145 }
6146
6147 }
6148 return 0;
e9b11c17
ZX		 6149}
6150
6151void kvm_arch_hardware_disable(void *garbage)
6152{
6153 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6154 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6155}
6156
6157int kvm_arch_hardware_setup(void)
6158{
6159 return kvm_x86_ops->hardware_setup();
6160}
6161
6162void kvm_arch_hardware_unsetup(void)
6163{
6164 kvm_x86_ops->hardware_unsetup();
6165}
6166
6167void kvm_arch_check_processor_compat(void *rtn)
6168{
6169 kvm_x86_ops->check_processor_compatibility(rtn);
6170}
6171
3e515705
AK		 6172bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6173{
6174 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6175}
6176
e9b11c17
ZX		 6177int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6178{
6179 struct page *page;
6180 struct kvm *kvm;
6181 int r;
6182
6183 BUG_ON(vcpu->kvm == NULL);
6184 kvm = vcpu->kvm;
6185
9aabc88f 6186 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6187 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6188 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6189 else
a4535290 6190 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6191
6192 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6193 if (!page) {
6194 r = -ENOMEM;
6195 goto fail;
6196 }
ad312c7c 6197 vcpu->arch.pio_data = page_address(page);
e9b11c17 6198
cc578287 6199 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6200
e9b11c17
ZX		 6201 r = kvm_mmu_create(vcpu);
6202 if (r < 0)
6203 goto fail_free_pio_data;
6204
6205 if (irqchip_in_kernel(kvm)) {
6206 r = kvm_create_lapic(vcpu);
6207 if (r < 0)
6208 goto fail_mmu_destroy;
6209 }
6210
890ca9ae
HY		 6211 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6212 GFP_KERNEL);
6213 if (!vcpu->arch.mce_banks) {
6214 r = -ENOMEM;
443c39bc 6215 goto fail_free_lapic;
890ca9ae
HY		 6216 }
6217 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6218
f5f48ee1
SY		 6219 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6220 goto fail_free_mce_banks;
6221
af585b92 6222 kvm_async_pf_hash_reset(vcpu);
f5132b01 6223 kvm_pmu_init(vcpu);
af585b92 6224
e9b11c17 6225 return 0;
f5f48ee1
SY		 6226fail_free_mce_banks:
6227 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6228fail_free_lapic:
6229 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6230fail_mmu_destroy:
6231 kvm_mmu_destroy(vcpu);
6232fail_free_pio_data:
ad312c7c 6233 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6234fail:
6235 return r;
6236}
6237
6238void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6239{
f656ce01
MT		 6240 int idx;
6241
f5132b01 6242 kvm_pmu_destroy(vcpu);
36cb93fd 6243 kfree(vcpu->arch.mce_banks);
e9b11c17 6244 kvm_free_lapic(vcpu);
f656ce01 6245 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6246 kvm_mmu_destroy(vcpu);
f656ce01 6247 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6248 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6249}
d19a9cd2 6250
e08b9637 6251int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6252{
e08b9637
CO		 6253 if (type)
6254 return -EINVAL;
6255
f05e70ac 6256 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6257 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6258
5550af4d
SY		 6259 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6260 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6261
038f8c11 6262 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6263
d89f5eff 6264 return 0;
d19a9cd2
ZX		 6265}
6266
6267static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6268{
6269 vcpu_load(vcpu);
6270 kvm_mmu_unload(vcpu);
6271 vcpu_put(vcpu);
6272}
6273
6274static void kvm_free_vcpus(struct kvm *kvm)
6275{
6276 unsigned int i;
988a2cae 6277 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6278
6279 /*
6280 * Unpin any mmu pages first.
6281 */
af585b92
GN		 6282 kvm_for_each_vcpu(i, vcpu, kvm) {
6283 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6284 kvm_unload_vcpu_mmu(vcpu);
af585b92 6285 }
988a2cae
GN		 6286 kvm_for_each_vcpu(i, vcpu, kvm)
6287 kvm_arch_vcpu_free(vcpu);
6288
6289 mutex_lock(&kvm->lock);
6290 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6291 kvm->vcpus[i] = NULL;
d19a9cd2 6292
988a2cae
GN		 6293 atomic_set(&kvm->online_vcpus, 0);
6294 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6295}
6296
ad8ba2cd
SY		 6297void kvm_arch_sync_events(struct kvm *kvm)
6298{
ba4cef31 6299 kvm_free_all_assigned_devices(kvm);
aea924f6 6300 kvm_free_pit(kvm);
ad8ba2cd
SY		 6301}
6302
d19a9cd2
ZX		 6303void kvm_arch_destroy_vm(struct kvm *kvm)
6304{
6eb55818 6305 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6306 kfree(kvm->arch.vpic);
6307 kfree(kvm->arch.vioapic);
d19a9cd2 6308 kvm_free_vcpus(kvm);
3d45830c
AK		 6309 if (kvm->arch.apic_access_page)
6310 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6311 if (kvm->arch.ept_identity_pagetable)
6312 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6313}
0de10343 6314
db3fe4eb
TY		 6315void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6316 struct kvm_memory_slot *dont)
6317{
6318 int i;
6319
6320 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6321 if (!dont || free->arch.lpage_info[i] != dont->arch.lpage_info[i]) {
c1a7b32a 6322 kvm_kvfree(free->arch.lpage_info[i]);
db3fe4eb
TY		 6323 free->arch.lpage_info[i] = NULL;
6324 }
6325 }
6326}
6327
6328int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6329{
6330 int i;
6331
6332 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6333 unsigned long ugfn;
6334 int lpages;
6335 int level = i + 2;
6336
6337 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6338 slot->base_gfn, level) + 1;
6339
6340 slot->arch.lpage_info[i] =
c1a7b32a 6341 kvm_kvzalloc(lpages * sizeof(*slot->arch.lpage_info[i]));
db3fe4eb
TY		 6342 if (!slot->arch.lpage_info[i])
6343 goto out_free;
6344
6345 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6346 slot->arch.lpage_info[i][0].write_count = 1;
6347 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6348 slot->arch.lpage_info[i][lpages - 1].write_count = 1;
6349 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6350 /*
6351 * If the gfn and userspace address are not aligned wrt each
6352 * other, or if explicitly asked to, disable large page
6353 * support for this slot
6354 */
6355 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6356 !kvm_largepages_enabled()) {
6357 unsigned long j;
6358
6359 for (j = 0; j < lpages; ++j)
6360 slot->arch.lpage_info[i][j].write_count = 1;
6361 }
6362 }
6363
6364 return 0;
6365
6366out_free:
6367 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
9e40b67b 6368 kvm_kvfree(slot->arch.lpage_info[i]);
db3fe4eb
TY		 6369 slot->arch.lpage_info[i] = NULL;
6370 }
6371 return -ENOMEM;
6372}
6373
f7784b8e
MT		 6374int kvm_arch_prepare_memory_region(struct kvm *kvm,
6375 struct kvm_memory_slot *memslot,
0de10343 6376 struct kvm_memory_slot old,
f7784b8e 6377 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6378 int user_alloc)
6379{
f7784b8e 6380 int npages = memslot->npages;
7ac77099
AK		 6381 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6382
6383 /* Prevent internal slot pages from being moved by fork()/COW. */
6384 if (memslot->id >= KVM_MEMORY_SLOTS)
6385 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6386
6387 /*To keep backward compatibility with older userspace,
6388 *x86 needs to hanlde !user_alloc case.
6389 */
6390 if (!user_alloc) {
6391 if (npages && !old.rmap) {
604b38ac
AA		 6392 unsigned long userspace_addr;
6393
6be5ceb0 6394 userspace_addr = vm_mmap(NULL, 0,
604b38ac
AA		 6395 npages * PAGE_SIZE,
6396 PROT_READ | PROT_WRITE,
7ac77099 6397 map_flags,
604b38ac 6398 0);
0de10343 6399
604b38ac
AA		 6400 if (IS_ERR((void *)userspace_addr))
6401 return PTR_ERR((void *)userspace_addr);
6402
604b38ac 6403 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6404 }
6405 }
6406
f7784b8e
MT		 6407
6408 return 0;
6409}
6410
6411void kvm_arch_commit_memory_region(struct kvm *kvm,
6412 struct kvm_userspace_memory_region *mem,
6413 struct kvm_memory_slot old,
6414 int user_alloc)
6415{
6416
48c0e4e9 6417 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6418
6419 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6420 int ret;
6421
bfce281c 6422 ret = vm_munmap(old.userspace_addr,
f7784b8e 6423 old.npages * PAGE_SIZE);
f7784b8e
MT		 6424 if (ret < 0)
6425 printk(KERN_WARNING
6426 "kvm_vm_ioctl_set_memory_region: "
6427 "failed to munmap memory\n");
6428 }
6429
48c0e4e9
XG		 6430 if (!kvm->arch.n_requested_mmu_pages)
6431 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6432
7c8a83b7 6433 spin_lock(&kvm->mmu_lock);
48c0e4e9 6434 if (nr_mmu_pages)
0de10343 6435 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6436 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6437 spin_unlock(&kvm->mmu_lock);
0de10343 6438}
1d737c8a 6439
34d4cb8f
MT		 6440void kvm_arch_flush_shadow(struct kvm *kvm)
6441{
6442 kvm_mmu_zap_all(kvm);
8986ecc0 6443 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6444}
6445
1d737c8a
ZX		 6446int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6447{
af585b92
GN		 6448 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6449 !vcpu->arch.apf.halted)
6450 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6451 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6452 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6453 (kvm_arch_interrupt_allowed(vcpu) &&
6454 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6455}
5736199a 6456
b6d33834 6457int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 6458{
b6d33834 6459 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 6460}
78646121
GN		 6461
6462int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6463{
6464 return kvm_x86_ops->interrupt_allowed(vcpu);
6465}
229456fc 6466
f92653ee
JK		 6467bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6468{
6469 unsigned long current_rip = kvm_rip_read(vcpu) +
6470 get_segment_base(vcpu, VCPU_SREG_CS);
6471
6472 return current_rip == linear_rip;
6473}
6474EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6475
94fe45da
JK		 6476unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6477{
6478 unsigned long rflags;
6479
6480 rflags = kvm_x86_ops->get_rflags(vcpu);
6481 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6482 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6483 return rflags;
6484}
6485EXPORT_SYMBOL_GPL(kvm_get_rflags);
6486
6487void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6488{
6489 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6490 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6491 rflags |= X86_EFLAGS_TF;
94fe45da 6492 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6493 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6494}
6495EXPORT_SYMBOL_GPL(kvm_set_rflags);
6496
56028d08
GN		 6497void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6498{
6499 int r;
6500
fb67e14f 6501 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6502 is_error_page(work->page))
56028d08
GN		 6503 return;
6504
6505 r = kvm_mmu_reload(vcpu);
6506 if (unlikely(r))
6507 return;
6508
fb67e14f
XG		 6509 if (!vcpu->arch.mmu.direct_map &&
6510 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6511 return;
6512
56028d08
GN		 6513 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6514}
6515
af585b92
GN		 6516static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6517{
6518 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6519}
6520
6521static inline u32 kvm_async_pf_next_probe(u32 key)
6522{
6523 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6524}
6525
6526static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6527{
6528 u32 key = kvm_async_pf_hash_fn(gfn);
6529
6530 while (vcpu->arch.apf.gfns[key] != ~0)
6531 key = kvm_async_pf_next_probe(key);
6532
6533 vcpu->arch.apf.gfns[key] = gfn;
6534}
6535
6536static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6537{
6538 int i;
6539 u32 key = kvm_async_pf_hash_fn(gfn);
6540
6541 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6542 (vcpu->arch.apf.gfns[key] != gfn &&
6543 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6544 key = kvm_async_pf_next_probe(key);
6545
6546 return key;
6547}
6548
6549bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6550{
6551 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6552}
6553
6554static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6555{
6556 u32 i, j, k;
6557
6558 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6559 while (true) {
6560 vcpu->arch.apf.gfns[i] = ~0;
6561 do {
6562 j = kvm_async_pf_next_probe(j);
6563 if (vcpu->arch.apf.gfns[j] == ~0)
6564 return;
6565 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6566 /*
6567 * k lies cyclically in ]i,j]
6568 * | i.k.j |
6569 * |....j i.k.| or |.k..j i...|
6570 */
6571 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6572 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6573 i = j;
6574 }
6575}
6576
7c90705b
GN		 6577static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6578{
6579
6580 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6581 sizeof(val));
6582}
6583
af585b92
GN		 6584void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6585 struct kvm_async_pf *work)
6586{
6389ee94
AK		 6587 struct x86_exception fault;
6588
7c90705b 6589 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6590 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6591
6592 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6593 (vcpu->arch.apf.send_user_only &&
6594 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6595 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6596 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6597 fault.vector = PF_VECTOR;
6598 fault.error_code_valid = true;
6599 fault.error_code = 0;
6600 fault.nested_page_fault = false;
6601 fault.address = work->arch.token;
6602 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6603 }
af585b92
GN		 6604}
6605
6606void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6607 struct kvm_async_pf *work)
6608{
6389ee94
AK		 6609 struct x86_exception fault;
6610
7c90705b
GN		 6611 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6612 if (is_error_page(work->page))
6613 work->arch.token = ~0; /* broadcast wakeup */
6614 else
6615 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6616
6617 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6618 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6619 fault.vector = PF_VECTOR;
6620 fault.error_code_valid = true;
6621 fault.error_code = 0;
6622 fault.nested_page_fault = false;
6623 fault.address = work->arch.token;
6624 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6625 }
e6d53e3b 6626 vcpu->arch.apf.halted = false;
a4fa1635 6627 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 6628}
6629
6630bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6631{
6632 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6633 return true;
6634 else
6635 return !kvm_event_needs_reinjection(vcpu) &&
6636 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6637}
6638
229456fc
MT		 6639EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6640EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6641EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6642EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6643EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6644EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6645EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6646EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6647EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6648EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6649EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6650EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux 6.x block layer and io_uring tree(s)