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KVM: x86: Clear DR6[0:3] on #DB during handle_dr
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
92a1f12d
JR		 101bool kvm_has_tsc_control;
102EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103u32 kvm_max_guest_tsc_khz;
104EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105
cc578287
ZA		 106/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107static u32 tsc_tolerance_ppm = 250;
108module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109
16a96021
MT		 110static bool backwards_tsc_observed = false;
111
18863bdd
AK		 112#define KVM_NR_SHARED_MSRS 16
113
114struct kvm_shared_msrs_global {
115 int nr;
2bf78fa7 116 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 117};
118
119struct kvm_shared_msrs {
120 struct user_return_notifier urn;
121 bool registered;
2bf78fa7
SY		 122 struct kvm_shared_msr_values {
123 u64 host;
124 u64 curr;
125 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 126};
127
128static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 129static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 130
417bc304 131struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 132 { "pf_fixed", VCPU_STAT(pf_fixed) },
133 { "pf_guest", VCPU_STAT(pf_guest) },
134 { "tlb_flush", VCPU_STAT(tlb_flush) },
135 { "invlpg", VCPU_STAT(invlpg) },
136 { "exits", VCPU_STAT(exits) },
137 { "io_exits", VCPU_STAT(io_exits) },
138 { "mmio_exits", VCPU_STAT(mmio_exits) },
139 { "signal_exits", VCPU_STAT(signal_exits) },
140 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 141 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 142 { "halt_exits", VCPU_STAT(halt_exits) },
143 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 144 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 145 { "request_irq", VCPU_STAT(request_irq_exits) },
146 { "irq_exits", VCPU_STAT(irq_exits) },
147 { "host_state_reload", VCPU_STAT(host_state_reload) },
148 { "efer_reload", VCPU_STAT(efer_reload) },
149 { "fpu_reload", VCPU_STAT(fpu_reload) },
150 { "insn_emulation", VCPU_STAT(insn_emulation) },
151 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 152 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 153 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 154 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
155 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
156 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
157 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
158 { "mmu_flooded", VM_STAT(mmu_flooded) },
159 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 160 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 161 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 162 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 163 { "largepages", VM_STAT(lpages) },
417bc304
HB		 164 { NULL }
165};
166
2acf923e
DC		 167u64 __read_mostly host_xcr0;
168
b6785def 169static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 170
af585b92
GN		 171static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
172{
173 int i;
174 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
175 vcpu->arch.apf.gfns[i] = ~0;
176}
177
18863bdd
AK		 178static void kvm_on_user_return(struct user_return_notifier *urn)
179{
180 unsigned slot;
18863bdd
AK		 181 struct kvm_shared_msrs *locals
182 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 183 struct kvm_shared_msr_values *values;
18863bdd
AK		 184
185 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 186 values = &locals->values[slot];
187 if (values->host != values->curr) {
188 wrmsrl(shared_msrs_global.msrs[slot], values->host);
189 values->curr = values->host;
18863bdd
AK		 190 }
191 }
192 locals->registered = false;
193 user_return_notifier_unregister(urn);
194}
195
2bf78fa7 196static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 197{
18863bdd 198 u64 value;
013f6a5d
MT		 199 unsigned int cpu = smp_processor_id();
200 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 201
2bf78fa7
SY		 202 /* only read, and nobody should modify it at this time,
203 * so don't need lock */
204 if (slot >= shared_msrs_global.nr) {
205 printk(KERN_ERR "kvm: invalid MSR slot!");
206 return;
207 }
208 rdmsrl_safe(msr, &value);
209 smsr->values[slot].host = value;
210 smsr->values[slot].curr = value;
211}
212
213void kvm_define_shared_msr(unsigned slot, u32 msr)
214{
0123be42 215 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 216 if (slot >= shared_msrs_global.nr)
217 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 218 shared_msrs_global.msrs[slot] = msr;
219 /* we need ensured the shared_msr_global have been updated */
220 smp_wmb();
18863bdd
AK		 221}
222EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
223
224static void kvm_shared_msr_cpu_online(void)
225{
226 unsigned i;
18863bdd
AK		 227
228 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 229 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 230}
231
8b3c3104 232int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 233{
013f6a5d
MT		 234 unsigned int cpu = smp_processor_id();
235 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 236 int err;
18863bdd 237
2bf78fa7 238 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 239 return 0;
2bf78fa7 240 smsr->values[slot].curr = value;
8b3c3104
AH		 241 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
242 if (err)
243 return 1;
244
18863bdd
AK		 245 if (!smsr->registered) {
246 smsr->urn.on_user_return = kvm_on_user_return;
247 user_return_notifier_register(&smsr->urn);
248 smsr->registered = true;
249 }
8b3c3104 250 return 0;
18863bdd
AK		 251}
252EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
253
13a34e06 254static void drop_user_return_notifiers(void)
3548bab5 255{
013f6a5d
MT		 256 unsigned int cpu = smp_processor_id();
257 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 258
259 if (smsr->registered)
260 kvm_on_user_return(&smsr->urn);
261}
262
6866b83e
CO		 263u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
264{
8a5a87d9 265 return vcpu->arch.apic_base;
6866b83e
CO		 266}
267EXPORT_SYMBOL_GPL(kvm_get_apic_base);
268
58cb628d
JK		 269int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
270{
271 u64 old_state = vcpu->arch.apic_base &
272 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
273 u64 new_state = msr_info->data &
274 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
275 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
276 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
277
278 if (!msr_info->host_initiated &&
279 ((msr_info->data & reserved_bits) != 0 ||
280 new_state == X2APIC_ENABLE ||
281 (new_state == MSR_IA32_APICBASE_ENABLE &&
282 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
283 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
284 old_state == 0)))
285 return 1;
286
287 kvm_lapic_set_base(vcpu, msr_info->data);
288 return 0;
6866b83e
CO		 289}
290EXPORT_SYMBOL_GPL(kvm_set_apic_base);
291
2605fc21 292asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 293{
294 /* Fault while not rebooting. We want the trace. */
295 BUG();
296}
297EXPORT_SYMBOL_GPL(kvm_spurious_fault);
298
3fd28fce
ED		 299#define EXCPT_BENIGN 0
300#define EXCPT_CONTRIBUTORY 1
301#define EXCPT_PF 2
302
303static int exception_class(int vector)
304{
305 switch (vector) {
306 case PF_VECTOR:
307 return EXCPT_PF;
308 case DE_VECTOR:
309 case TS_VECTOR:
310 case NP_VECTOR:
311 case SS_VECTOR:
312 case GP_VECTOR:
313 return EXCPT_CONTRIBUTORY;
314 default:
315 break;
316 }
317 return EXCPT_BENIGN;
318}
319
d6e8c854
NA		 320#define EXCPT_FAULT 0
321#define EXCPT_TRAP 1
322#define EXCPT_ABORT 2
323#define EXCPT_INTERRUPT 3
324
325static int exception_type(int vector)
326{
327 unsigned int mask;
328
329 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
330 return EXCPT_INTERRUPT;
331
332 mask = 1 << vector;
333
334 /* #DB is trap, as instruction watchpoints are handled elsewhere */
335 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
336 return EXCPT_TRAP;
337
338 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
339 return EXCPT_ABORT;
340
341 /* Reserved exceptions will result in fault */
342 return EXCPT_FAULT;
343}
344
3fd28fce 345static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 346 unsigned nr, bool has_error, u32 error_code,
347 bool reinject)
3fd28fce
ED		 348{
349 u32 prev_nr;
350 int class1, class2;
351
3842d135
AK		 352 kvm_make_request(KVM_REQ_EVENT, vcpu);
353
3fd28fce
ED		 354 if (!vcpu->arch.exception.pending) {
355 queue:
3ffb2468
NA		 356 if (has_error && !is_protmode(vcpu))
357 has_error = false;
3fd28fce
ED		 358 vcpu->arch.exception.pending = true;
359 vcpu->arch.exception.has_error_code = has_error;
360 vcpu->arch.exception.nr = nr;
361 vcpu->arch.exception.error_code = error_code;
3f0fd292 362 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 363 return;
364 }
365
366 /* to check exception */
367 prev_nr = vcpu->arch.exception.nr;
368 if (prev_nr == DF_VECTOR) {
369 /* triple fault -> shutdown */
a8eeb04a 370 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 371 return;
372 }
373 class1 = exception_class(prev_nr);
374 class2 = exception_class(nr);
375 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
376 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
377 /* generate double fault per SDM Table 5-5 */
378 vcpu->arch.exception.pending = true;
379 vcpu->arch.exception.has_error_code = true;
380 vcpu->arch.exception.nr = DF_VECTOR;
381 vcpu->arch.exception.error_code = 0;
382 } else
383 /* replace previous exception with a new one in a hope
384 that instruction re-execution will regenerate lost
385 exception */
386 goto queue;
387}
388
298101da
AK		 389void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
390{
ce7ddec4 391 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 392}
393EXPORT_SYMBOL_GPL(kvm_queue_exception);
394
ce7ddec4
JR		 395void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
396{
397 kvm_multiple_exception(vcpu, nr, false, 0, true);
398}
399EXPORT_SYMBOL_GPL(kvm_requeue_exception);
400
db8fcefa 401void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 402{
db8fcefa
AP		 403 if (err)
404 kvm_inject_gp(vcpu, 0);
405 else
406 kvm_x86_ops->skip_emulated_instruction(vcpu);
407}
408EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 409
6389ee94 410void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 411{
412 ++vcpu->stat.pf_guest;
6389ee94
AK		 413 vcpu->arch.cr2 = fault->address;
414 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 415}
27d6c865 416EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 417
ef54bcfe 418static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 419{
6389ee94
AK		 420 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
421 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 422 else
6389ee94 423 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 424
425 return fault->nested_page_fault;
d4f8cf66
JR		 426}
427
3419ffc8
SY		 428void kvm_inject_nmi(struct kvm_vcpu *vcpu)
429{
7460fb4a
AK		 430 atomic_inc(&vcpu->arch.nmi_queued);
431 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 432}
433EXPORT_SYMBOL_GPL(kvm_inject_nmi);
434
298101da
AK		 435void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
436{
ce7ddec4 437 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 438}
439EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
440
ce7ddec4
JR		 441void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
442{
443 kvm_multiple_exception(vcpu, nr, true, error_code, true);
444}
445EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
446
0a79b009
AK		 447/*
448 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
449 * a #GP and return false.
450 */
451bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 452{
0a79b009
AK		 453 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
454 return true;
455 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
456 return false;
298101da 457}
0a79b009 458EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 459
16f8a6f9
NA		 460bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
461{
462 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
463 return true;
464
465 kvm_queue_exception(vcpu, UD_VECTOR);
466 return false;
467}
468EXPORT_SYMBOL_GPL(kvm_require_dr);
469
ec92fe44
JR		 470/*
471 * This function will be used to read from the physical memory of the currently
472 * running guest. The difference to kvm_read_guest_page is that this function
473 * can read from guest physical or from the guest's guest physical memory.
474 */
475int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
476 gfn_t ngfn, void *data, int offset, int len,
477 u32 access)
478{
54987b7a 479 struct x86_exception exception;
ec92fe44
JR		 480 gfn_t real_gfn;
481 gpa_t ngpa;
482
483 ngpa = gfn_to_gpa(ngfn);
54987b7a 484 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 485 if (real_gfn == UNMAPPED_GVA)
486 return -EFAULT;
487
488 real_gfn = gpa_to_gfn(real_gfn);
489
490 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
491}
492EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
493
3d06b8bf
JR		 494int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
495 void *data, int offset, int len, u32 access)
496{
497 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
498 data, offset, len, access);
499}
500
a03490ed
CO		 501/*
502 * Load the pae pdptrs. Return true is they are all valid.
503 */
ff03a073 504int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 505{
506 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
507 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
508 int i;
509 int ret;
ff03a073 510 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 511
ff03a073
JR		 512 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
513 offset * sizeof(u64), sizeof(pdpte),
514 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 515 if (ret < 0) {
516 ret = 0;
517 goto out;
518 }
519 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 520 if (is_present_gpte(pdpte[i]) &&
20c466b5 521 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 522 ret = 0;
523 goto out;
524 }
525 }
526 ret = 1;
527
ff03a073 528 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 529 __set_bit(VCPU_EXREG_PDPTR,
530 (unsigned long *)&vcpu->arch.regs_avail);
531 __set_bit(VCPU_EXREG_PDPTR,
532 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 533out:
a03490ed
CO		 534
535 return ret;
536}
cc4b6871 537EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 538
d835dfec
AK		 539static bool pdptrs_changed(struct kvm_vcpu *vcpu)
540{
ff03a073 541 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 542 bool changed = true;
3d06b8bf
JR		 543 int offset;
544 gfn_t gfn;
d835dfec
AK		 545 int r;
546
547 if (is_long_mode(vcpu) || !is_pae(vcpu))
548 return false;
549
6de4f3ad
AK		 550 if (!test_bit(VCPU_EXREG_PDPTR,
551 (unsigned long *)&vcpu->arch.regs_avail))
552 return true;
553
9f8fe504
AK		 554 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
555 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 556 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
557 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 558 if (r < 0)
559 goto out;
ff03a073 560 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 561out:
d835dfec
AK		 562
563 return changed;
564}
565
49a9b07e 566int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 567{
aad82703
SY		 568 unsigned long old_cr0 = kvm_read_cr0(vcpu);
569 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
570 X86_CR0_CD | X86_CR0_NW;
571
f9a48e6a
AK		 572 cr0 |= X86_CR0_ET;
573
ab344828 574#ifdef CONFIG_X86_64
0f12244f
GN		 575 if (cr0 & 0xffffffff00000000UL)
576 return 1;
ab344828
GN		 577#endif
578
579 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 580
0f12244f
GN		 581 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
582 return 1;
a03490ed 583
0f12244f
GN		 584 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
585 return 1;
a03490ed
CO		 586
587 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
588#ifdef CONFIG_X86_64
f6801dff 589 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 590 int cs_db, cs_l;
591
0f12244f
GN		 592 if (!is_pae(vcpu))
593 return 1;
a03490ed 594 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 595 if (cs_l)
596 return 1;
a03490ed
CO		 597 } else
598#endif
ff03a073 599 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 600 kvm_read_cr3(vcpu)))
0f12244f 601 return 1;
a03490ed
CO		 602 }
603
ad756a16
MJ		 604 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
605 return 1;
606
a03490ed 607 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 608
d170c419 609 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 610 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 611 kvm_async_pf_hash_reset(vcpu);
612 }
e5f3f027 613
aad82703
SY		 614 if ((cr0 ^ old_cr0) & update_bits)
615 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 616 return 0;
617}
2d3ad1f4 618EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 619
2d3ad1f4 620void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 621{
49a9b07e 622 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 623}
2d3ad1f4 624EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 625
42bdf991
MT		 626static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
627{
628 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
629 !vcpu->guest_xcr0_loaded) {
630 /* kvm_set_xcr() also depends on this */
631 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
632 vcpu->guest_xcr0_loaded = 1;
633 }
634}
635
636static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
637{
638 if (vcpu->guest_xcr0_loaded) {
639 if (vcpu->arch.xcr0 != host_xcr0)
640 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
641 vcpu->guest_xcr0_loaded = 0;
642 }
643}
644
2acf923e
DC		 645int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
646{
56c103ec
LJ		 647 u64 xcr0 = xcr;
648 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 649 u64 valid_bits;
2acf923e
DC		 650
651 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
652 if (index != XCR_XFEATURE_ENABLED_MASK)
653 return 1;
2acf923e
DC		 654 if (!(xcr0 & XSTATE_FP))
655 return 1;
656 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
657 return 1;
46c34cb0
PB		 658
659 /*
660 * Do not allow the guest to set bits that we do not support
661 * saving. However, xcr0 bit 0 is always set, even if the
662 * emulated CPU does not support XSAVE (see fx_init).
663 */
664 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
665 if (xcr0 & ~valid_bits)
2acf923e 666 return 1;
46c34cb0 667
390bd528
LJ		 668 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
669 return 1;
670
612263b3
CP		 671 if (xcr0 & XSTATE_AVX512) {
672 if (!(xcr0 & XSTATE_YMM))
673 return 1;
674 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
675 return 1;
676 }
42bdf991 677 kvm_put_guest_xcr0(vcpu);
2acf923e 678 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 679
680 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
681 kvm_update_cpuid(vcpu);
2acf923e
DC		 682 return 0;
683}
684
685int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
686{
764bcbc5
Z		 687 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
688 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 689 kvm_inject_gp(vcpu, 0);
690 return 1;
691 }
692 return 0;
693}
694EXPORT_SYMBOL_GPL(kvm_set_xcr);
695
a83b29c6 696int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 697{
fc78f519 698 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 699 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
700 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 701 if (cr4 & CR4_RESERVED_BITS)
702 return 1;
a03490ed 703
2acf923e
DC		 704 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
705 return 1;
706
c68b734f
YW		 707 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
708 return 1;
709
97ec8c06
FW		 710 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
711 return 1;
712
afcbf13f 713 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 714 return 1;
715
a03490ed 716 if (is_long_mode(vcpu)) {
0f12244f
GN		 717 if (!(cr4 & X86_CR4_PAE))
718 return 1;
a2edf57f
AK		 719 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
720 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 721 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
722 kvm_read_cr3(vcpu)))
0f12244f
GN		 723 return 1;
724
ad756a16
MJ		 725 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
726 if (!guest_cpuid_has_pcid(vcpu))
727 return 1;
728
729 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
730 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
731 return 1;
732 }
733
5e1746d6 734 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 735 return 1;
a03490ed 736
ad756a16
MJ		 737 if (((cr4 ^ old_cr4) & pdptr_bits) ||
738 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 739 kvm_mmu_reset_context(vcpu);
0f12244f 740
97ec8c06
FW		 741 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
742 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
743
2acf923e 744 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 745 kvm_update_cpuid(vcpu);
2acf923e 746
0f12244f
GN		 747 return 0;
748}
2d3ad1f4 749EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 750
2390218b 751int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 752{
9f8fe504 753 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 754 kvm_mmu_sync_roots(vcpu);
77c3913b 755 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 756 return 0;
d835dfec
AK		 757 }
758
a03490ed 759 if (is_long_mode(vcpu)) {
d9f89b88
JK		 760 if (cr3 & CR3_L_MODE_RESERVED_BITS)
761 return 1;
762 } else if (is_pae(vcpu) && is_paging(vcpu) &&
763 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 764 return 1;
a03490ed 765
0f12244f 766 vcpu->arch.cr3 = cr3;
aff48baa 767 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 768 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 769 return 0;
770}
2d3ad1f4 771EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 772
eea1cff9 773int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 774{
0f12244f
GN		 775 if (cr8 & CR8_RESERVED_BITS)
776 return 1;
a03490ed
CO		 777 if (irqchip_in_kernel(vcpu->kvm))
778 kvm_lapic_set_tpr(vcpu, cr8);
779 else
ad312c7c 780 vcpu->arch.cr8 = cr8;
0f12244f
GN		 781 return 0;
782}
2d3ad1f4 783EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 784
2d3ad1f4 785unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 786{
787 if (irqchip_in_kernel(vcpu->kvm))
788 return kvm_lapic_get_cr8(vcpu);
789 else
ad312c7c 790 return vcpu->arch.cr8;
a03490ed 791}
2d3ad1f4 792EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 793
73aaf249
JK		 794static void kvm_update_dr6(struct kvm_vcpu *vcpu)
795{
796 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
797 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
798}
799
c8639010
JK		 800static void kvm_update_dr7(struct kvm_vcpu *vcpu)
801{
802 unsigned long dr7;
803
804 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
805 dr7 = vcpu->arch.guest_debug_dr7;
806 else
807 dr7 = vcpu->arch.dr7;
808 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 809 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
810 if (dr7 & DR7_BP_EN_MASK)
811 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 812}
813
6f43ed01
NA		 814static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
815{
816 u64 fixed = DR6_FIXED_1;
817
818 if (!guest_cpuid_has_rtm(vcpu))
819 fixed |= DR6_RTM;
820 return fixed;
821}
822
338dbc97 823static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 824{
825 switch (dr) {
826 case 0 ... 3:
827 vcpu->arch.db[dr] = val;
828 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
829 vcpu->arch.eff_db[dr] = val;
830 break;
831 case 4:
020df079
GN		 832 /* fall through */
833 case 6:
338dbc97
GN		 834 if (val & 0xffffffff00000000ULL)
835 return -1; /* #GP */
6f43ed01 836 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 837 kvm_update_dr6(vcpu);
020df079
GN		 838 break;
839 case 5:
020df079
GN		 840 /* fall through */
841 default: /* 7 */
338dbc97
GN		 842 if (val & 0xffffffff00000000ULL)
843 return -1; /* #GP */
020df079 844 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 845 kvm_update_dr7(vcpu);
020df079
GN		 846 break;
847 }
848
849 return 0;
850}
338dbc97
GN		 851
852int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
853{
16f8a6f9 854 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 855 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 856 return 1;
857 }
858 return 0;
338dbc97 859}
020df079
GN		 860EXPORT_SYMBOL_GPL(kvm_set_dr);
861
16f8a6f9 862int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 863{
864 switch (dr) {
865 case 0 ... 3:
866 *val = vcpu->arch.db[dr];
867 break;
868 case 4:
020df079
GN		 869 /* fall through */
870 case 6:
73aaf249
JK		 871 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
872 *val = vcpu->arch.dr6;
873 else
874 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 875 break;
876 case 5:
020df079
GN		 877 /* fall through */
878 default: /* 7 */
879 *val = vcpu->arch.dr7;
880 break;
881 }
338dbc97
GN		 882 return 0;
883}
020df079
GN		 884EXPORT_SYMBOL_GPL(kvm_get_dr);
885
022cd0e8
AK		 886bool kvm_rdpmc(struct kvm_vcpu *vcpu)
887{
888 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
889 u64 data;
890 int err;
891
892 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
893 if (err)
894 return err;
895 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
896 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
897 return err;
898}
899EXPORT_SYMBOL_GPL(kvm_rdpmc);
900
043405e1
CO		 901/*
902 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
903 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
904 *
905 * This list is modified at module load time to reflect the
e3267cbb
GC		 906 * capabilities of the host cpu. This capabilities test skips MSRs that are
907 * kvm-specific. Those are put in the beginning of the list.
043405e1 908 */
e3267cbb 909
e984097b 910#define KVM_SAVE_MSRS_BEGIN 12
043405e1 911static u32 msrs_to_save[] = {
e3267cbb 912 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 913 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 914 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 915 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 916 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 917 MSR_KVM_PV_EOI_EN,
043405e1 918 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 919 MSR_STAR,
043405e1
CO		 920#ifdef CONFIG_X86_64
921 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
922#endif
b3897a49 923 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 924 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 925};
926
927static unsigned num_msrs_to_save;
928
f1d24831 929static const u32 emulated_msrs[] = {
ba904635 930 MSR_IA32_TSC_ADJUST,
a3e06bbe 931 MSR_IA32_TSCDEADLINE,
043405e1 932 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 933 MSR_IA32_MCG_STATUS,
934 MSR_IA32_MCG_CTL,
043405e1
CO		 935};
936
384bb783 937bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 938{
b69e8cae 939 if (efer & efer_reserved_bits)
384bb783 940 return false;
15c4a640 941
1b2fd70c
AG		 942 if (efer & EFER_FFXSR) {
943 struct kvm_cpuid_entry2 *feat;
944
945 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 946 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 947 return false;
1b2fd70c
AG		 948 }
949
d8017474
AG		 950 if (efer & EFER_SVME) {
951 struct kvm_cpuid_entry2 *feat;
952
953 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 954 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 955 return false;
d8017474
AG		 956 }
957
384bb783
JK		 958 return true;
959}
960EXPORT_SYMBOL_GPL(kvm_valid_efer);
961
962static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
963{
964 u64 old_efer = vcpu->arch.efer;
965
966 if (!kvm_valid_efer(vcpu, efer))
967 return 1;
968
969 if (is_paging(vcpu)
970 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
971 return 1;
972
15c4a640 973 efer &= ~EFER_LMA;
f6801dff 974 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 975
a3d204e2
SY		 976 kvm_x86_ops->set_efer(vcpu, efer);
977
aad82703
SY		 978 /* Update reserved bits */
979 if ((efer ^ old_efer) & EFER_NX)
980 kvm_mmu_reset_context(vcpu);
981
b69e8cae 982 return 0;
15c4a640
CO		 983}
984
f2b4b7dd
JR		 985void kvm_enable_efer_bits(u64 mask)
986{
987 efer_reserved_bits &= ~mask;
988}
989EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
990
15c4a640
CO		 991/*
992 * Writes msr value into into the appropriate "register".
993 * Returns 0 on success, non-0 otherwise.
994 * Assumes vcpu_load() was already called.
995 */
8fe8ab46 996int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 997{
854e8bb1
NA		 998 switch (msr->index) {
999 case MSR_FS_BASE:
1000 case MSR_GS_BASE:
1001 case MSR_KERNEL_GS_BASE:
1002 case MSR_CSTAR:
1003 case MSR_LSTAR:
1004 if (is_noncanonical_address(msr->data))
1005 return 1;
1006 break;
1007 case MSR_IA32_SYSENTER_EIP:
1008 case MSR_IA32_SYSENTER_ESP:
1009 /*
1010 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1011 * non-canonical address is written on Intel but not on
1012 * AMD (which ignores the top 32-bits, because it does
1013 * not implement 64-bit SYSENTER).
1014 *
1015 * 64-bit code should hence be able to write a non-canonical
1016 * value on AMD. Making the address canonical ensures that
1017 * vmentry does not fail on Intel after writing a non-canonical
1018 * value, and that something deterministic happens if the guest
1019 * invokes 64-bit SYSENTER.
1020 */
1021 msr->data = get_canonical(msr->data);
1022 }
8fe8ab46 1023 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1024}
854e8bb1 1025EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1026
313a3dc7
CO		 1027/*
1028 * Adapt set_msr() to msr_io()'s calling convention
1029 */
1030static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1031{
8fe8ab46
WA		 1032 struct msr_data msr;
1033
1034 msr.data = *data;
1035 msr.index = index;
1036 msr.host_initiated = true;
1037 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1038}
1039
16e8d74d
MT		 1040#ifdef CONFIG_X86_64
1041struct pvclock_gtod_data {
1042 seqcount_t seq;
1043
1044 struct { /* extract of a clocksource struct */
1045 int vclock_mode;
1046 cycle_t cycle_last;
1047 cycle_t mask;
1048 u32 mult;
1049 u32 shift;
1050 } clock;
1051
cbcf2dd3
TG		 1052 u64 boot_ns;
1053 u64 nsec_base;
16e8d74d
MT		 1054};
1055
1056static struct pvclock_gtod_data pvclock_gtod_data;
1057
1058static void update_pvclock_gtod(struct timekeeper *tk)
1059{
1060 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1061 u64 boot_ns;
1062
d28ede83 1063 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
16e8d74d
MT		 1064
1065 write_seqcount_begin(&vdata->seq);
1066
1067 /* copy pvclock gtod data */
d28ede83
TG		 1068 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1069 vdata->clock.cycle_last = tk->tkr.cycle_last;
1070 vdata->clock.mask = tk->tkr.mask;
1071 vdata->clock.mult = tk->tkr.mult;
1072 vdata->clock.shift = tk->tkr.shift;
16e8d74d 1073
cbcf2dd3 1074 vdata->boot_ns = boot_ns;
d28ede83 1075 vdata->nsec_base = tk->tkr.xtime_nsec;
16e8d74d
MT		 1076
1077 write_seqcount_end(&vdata->seq);
1078}
1079#endif
1080
1081
18068523
GOC		 1082static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1083{
9ed3c444
AK		 1084 int version;
1085 int r;
50d0a0f9 1086 struct pvclock_wall_clock wc;
923de3cf 1087 struct timespec boot;
18068523
GOC		 1088
1089 if (!wall_clock)
1090 return;
1091
9ed3c444
AK		 1092 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1093 if (r)
1094 return;
1095
1096 if (version & 1)
1097 ++version; /* first time write, random junk */
1098
1099 ++version;
18068523 1100
18068523
GOC		 1101 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1102
50d0a0f9
GH		 1103 /*
1104 * The guest calculates current wall clock time by adding
34c238a1 1105 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1106 * wall clock specified here. guest system time equals host
1107 * system time for us, thus we must fill in host boot time here.
1108 */
923de3cf 1109 getboottime(&boot);
50d0a0f9 1110
4b648665
BR		 1111 if (kvm->arch.kvmclock_offset) {
1112 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1113 boot = timespec_sub(boot, ts);
1114 }
50d0a0f9
GH		 1115 wc.sec = boot.tv_sec;
1116 wc.nsec = boot.tv_nsec;
1117 wc.version = version;
18068523
GOC		 1118
1119 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1120
1121 version++;
1122 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1123}
1124
50d0a0f9
GH		 1125static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1126{
1127 uint32_t quotient, remainder;
1128
1129 /* Don't try to replace with do_div(), this one calculates
1130 * "(dividend << 32) / divisor" */
1131 __asm__ ( "divl %4"
1132 : "=a" (quotient), "=d" (remainder)
1133 : "0" (0), "1" (dividend), "r" (divisor) );
1134 return quotient;
1135}
1136
5f4e3f88
ZA		 1137static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1138 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1139{
5f4e3f88 1140 uint64_t scaled64;
50d0a0f9
GH		 1141 int32_t shift = 0;
1142 uint64_t tps64;
1143 uint32_t tps32;
1144
5f4e3f88
ZA		 1145 tps64 = base_khz * 1000LL;
1146 scaled64 = scaled_khz * 1000LL;
50933623 1147 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1148 tps64 >>= 1;
1149 shift--;
1150 }
1151
1152 tps32 = (uint32_t)tps64;
50933623
JK		 1153 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1154 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1155 scaled64 >>= 1;
1156 else
1157 tps32 <<= 1;
50d0a0f9
GH		 1158 shift++;
1159 }
1160
5f4e3f88
ZA		 1161 *pshift = shift;
1162 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1163
5f4e3f88
ZA		 1164 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1165 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1166}
1167
759379dd
ZA		 1168static inline u64 get_kernel_ns(void)
1169{
bb0b5812 1170 return ktime_get_boot_ns();
50d0a0f9
GH		 1171}
1172
d828199e 1173#ifdef CONFIG_X86_64
16e8d74d 1174static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1175#endif
16e8d74d 1176
c8076604 1177static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1178unsigned long max_tsc_khz;
c8076604 1179
cc578287 1180static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1181{
cc578287
ZA		 1182 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1183 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1184}
1185
cc578287 1186static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1187{
cc578287
ZA		 1188 u64 v = (u64)khz * (1000000 + ppm);
1189 do_div(v, 1000000);
1190 return v;
1e993611
JR		 1191}
1192
cc578287 1193static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1194{
cc578287
ZA		 1195 u32 thresh_lo, thresh_hi;
1196 int use_scaling = 0;
217fc9cf 1197
03ba32ca
MT		 1198 /* tsc_khz can be zero if TSC calibration fails */
1199 if (this_tsc_khz == 0)
1200 return;
1201
c285545f
ZA		 1202 /* Compute a scale to convert nanoseconds in TSC cycles */
1203 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1204 &vcpu->arch.virtual_tsc_shift,
1205 &vcpu->arch.virtual_tsc_mult);
1206 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1207
1208 /*
1209 * Compute the variation in TSC rate which is acceptable
1210 * within the range of tolerance and decide if the
1211 * rate being applied is within that bounds of the hardware
1212 * rate. If so, no scaling or compensation need be done.
1213 */
1214 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1215 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1216 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1217 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1218 use_scaling = 1;
1219 }
1220 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1221}
1222
1223static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1224{
e26101b1 1225 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1226 vcpu->arch.virtual_tsc_mult,
1227 vcpu->arch.virtual_tsc_shift);
e26101b1 1228 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1229 return tsc;
1230}
1231
b48aa97e
MT		 1232void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1233{
1234#ifdef CONFIG_X86_64
1235 bool vcpus_matched;
1236 bool do_request = false;
1237 struct kvm_arch *ka = &vcpu->kvm->arch;
1238 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1239
1240 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1241 atomic_read(&vcpu->kvm->online_vcpus));
1242
1243 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1244 if (!ka->use_master_clock)
1245 do_request = 1;
1246
1247 if (!vcpus_matched && ka->use_master_clock)
1248 do_request = 1;
1249
1250 if (do_request)
1251 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1252
1253 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1254 atomic_read(&vcpu->kvm->online_vcpus),
1255 ka->use_master_clock, gtod->clock.vclock_mode);
1256#endif
1257}
1258
ba904635
WA		 1259static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1260{
1261 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1262 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1263}
1264
8fe8ab46 1265void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1266{
1267 struct kvm *kvm = vcpu->kvm;
f38e098f 1268 u64 offset, ns, elapsed;
99e3e30a 1269 unsigned long flags;
02626b6a 1270 s64 usdiff;
b48aa97e 1271 bool matched;
0d3da0d2 1272 bool already_matched;
8fe8ab46 1273 u64 data = msr->data;
99e3e30a 1274
038f8c11 1275 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1276 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1277 ns = get_kernel_ns();
f38e098f 1278 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1279
03ba32ca 1280 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1281 int faulted = 0;
1282
03ba32ca
MT		 1283 /* n.b - signed multiplication and division required */
1284 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1285#ifdef CONFIG_X86_64
03ba32ca 1286 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1287#else
03ba32ca 1288 /* do_div() only does unsigned */
8915aa27
MT		 1289 asm("1: idivl %[divisor]\n"
1290 "2: xor %%edx, %%edx\n"
1291 " movl $0, %[faulted]\n"
1292 "3:\n"
1293 ".section .fixup,\"ax\"\n"
1294 "4: movl $1, %[faulted]\n"
1295 " jmp 3b\n"
1296 ".previous\n"
1297
1298 _ASM_EXTABLE(1b, 4b)
1299
1300 : "=A"(usdiff), [faulted] "=r" (faulted)
1301 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1302
5d3cb0f6 1303#endif
03ba32ca
MT		 1304 do_div(elapsed, 1000);
1305 usdiff -= elapsed;
1306 if (usdiff < 0)
1307 usdiff = -usdiff;
8915aa27
MT		 1308
1309 /* idivl overflow => difference is larger than USEC_PER_SEC */
1310 if (faulted)
1311 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1312 } else
1313 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1314
1315 /*
5d3cb0f6
ZA		 1316 * Special case: TSC write with a small delta (1 second) of virtual
1317 * cycle time against real time is interpreted as an attempt to
1318 * synchronize the CPU.
1319 *
1320 * For a reliable TSC, we can match TSC offsets, and for an unstable
1321 * TSC, we add elapsed time in this computation. We could let the
1322 * compensation code attempt to catch up if we fall behind, but
1323 * it's better to try to match offsets from the beginning.
1324 */
02626b6a 1325 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1326 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1327 if (!check_tsc_unstable()) {
e26101b1 1328 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1329 pr_debug("kvm: matched tsc offset for %llu\n", data);
1330 } else {
857e4099 1331 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1332 data += delta;
1333 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1334 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1335 }
b48aa97e 1336 matched = true;
0d3da0d2 1337 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1338 } else {
1339 /*
1340 * We split periods of matched TSC writes into generations.
1341 * For each generation, we track the original measured
1342 * nanosecond time, offset, and write, so if TSCs are in
1343 * sync, we can match exact offset, and if not, we can match
4a969980 1344 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1345 *
1346 * These values are tracked in kvm->arch.cur_xxx variables.
1347 */
1348 kvm->arch.cur_tsc_generation++;
1349 kvm->arch.cur_tsc_nsec = ns;
1350 kvm->arch.cur_tsc_write = data;
1351 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1352 matched = false;
0d3da0d2 1353 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1354 kvm->arch.cur_tsc_generation, data);
f38e098f 1355 }
e26101b1
ZA		 1356
1357 /*
1358 * We also track th most recent recorded KHZ, write and time to
1359 * allow the matching interval to be extended at each write.
1360 */
f38e098f
ZA		 1361 kvm->arch.last_tsc_nsec = ns;
1362 kvm->arch.last_tsc_write = data;
5d3cb0f6 1363 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1364
b183aa58 1365 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1366
1367 /* Keep track of which generation this VCPU has synchronized to */
1368 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1369 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1370 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1371
ba904635
WA		 1372 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1373 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1374 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1375 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1376
1377 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1378 if (!matched) {
b48aa97e 1379 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1380 } else if (!already_matched) {
1381 kvm->arch.nr_vcpus_matched_tsc++;
1382 }
b48aa97e
MT		 1383
1384 kvm_track_tsc_matching(vcpu);
1385 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1386}
e26101b1 1387
99e3e30a
ZA		 1388EXPORT_SYMBOL_GPL(kvm_write_tsc);
1389
d828199e
MT		 1390#ifdef CONFIG_X86_64
1391
1392static cycle_t read_tsc(void)
1393{
1394 cycle_t ret;
1395 u64 last;
1396
1397 /*
1398 * Empirically, a fence (of type that depends on the CPU)
1399 * before rdtsc is enough to ensure that rdtsc is ordered
1400 * with respect to loads. The various CPU manuals are unclear
1401 * as to whether rdtsc can be reordered with later loads,
1402 * but no one has ever seen it happen.
1403 */
1404 rdtsc_barrier();
1405 ret = (cycle_t)vget_cycles();
1406
1407 last = pvclock_gtod_data.clock.cycle_last;
1408
1409 if (likely(ret >= last))
1410 return ret;
1411
1412 /*
1413 * GCC likes to generate cmov here, but this branch is extremely
1414 * predictable (it's just a funciton of time and the likely is
1415 * very likely) and there's a data dependence, so force GCC
1416 * to generate a branch instead. I don't barrier() because
1417 * we don't actually need a barrier, and if this function
1418 * ever gets inlined it will generate worse code.
1419 */
1420 asm volatile ("");
1421 return last;
1422}
1423
1424static inline u64 vgettsc(cycle_t *cycle_now)
1425{
1426 long v;
1427 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1428
1429 *cycle_now = read_tsc();
1430
1431 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1432 return v * gtod->clock.mult;
1433}
1434
cbcf2dd3 1435static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1436{
cbcf2dd3 1437 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1438 unsigned long seq;
d828199e 1439 int mode;
cbcf2dd3 1440 u64 ns;
d828199e 1441
d828199e
MT		 1442 do {
1443 seq = read_seqcount_begin(&gtod->seq);
1444 mode = gtod->clock.vclock_mode;
cbcf2dd3 1445 ns = gtod->nsec_base;
d828199e
MT		 1446 ns += vgettsc(cycle_now);
1447 ns >>= gtod->clock.shift;
cbcf2dd3 1448 ns += gtod->boot_ns;
d828199e 1449 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1450 *t = ns;
d828199e
MT		 1451
1452 return mode;
1453}
1454
1455/* returns true if host is using tsc clocksource */
1456static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1457{
d828199e
MT		 1458 /* checked again under seqlock below */
1459 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1460 return false;
1461
cbcf2dd3 1462 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1463}
1464#endif
1465
1466/*
1467 *
b48aa97e
MT		 1468 * Assuming a stable TSC across physical CPUS, and a stable TSC
1469 * across virtual CPUs, the following condition is possible.
1470 * Each numbered line represents an event visible to both
d828199e
MT		 1471 * CPUs at the next numbered event.
1472 *
1473 * "timespecX" represents host monotonic time. "tscX" represents
1474 * RDTSC value.
1475 *
1476 * VCPU0 on CPU0 | VCPU1 on CPU1
1477 *
1478 * 1. read timespec0,tsc0
1479 * 2. | timespec1 = timespec0 + N
1480 * | tsc1 = tsc0 + M
1481 * 3. transition to guest | transition to guest
1482 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1483 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1484 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1485 *
1486 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1487 *
1488 * - ret0 < ret1
1489 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1490 * ...
1491 * - 0 < N - M => M < N
1492 *
1493 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1494 * always the case (the difference between two distinct xtime instances
1495 * might be smaller then the difference between corresponding TSC reads,
1496 * when updating guest vcpus pvclock areas).
1497 *
1498 * To avoid that problem, do not allow visibility of distinct
1499 * system_timestamp/tsc_timestamp values simultaneously: use a master
1500 * copy of host monotonic time values. Update that master copy
1501 * in lockstep.
1502 *
b48aa97e 1503 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1504 *
1505 */
1506
1507static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1508{
1509#ifdef CONFIG_X86_64
1510 struct kvm_arch *ka = &kvm->arch;
1511 int vclock_mode;
b48aa97e
MT		 1512 bool host_tsc_clocksource, vcpus_matched;
1513
1514 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1515 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1516
1517 /*
1518 * If the host uses TSC clock, then passthrough TSC as stable
1519 * to the guest.
1520 */
b48aa97e 1521 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1522 &ka->master_kernel_ns,
1523 &ka->master_cycle_now);
1524
16a96021
MT		 1525 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1526 && !backwards_tsc_observed;
b48aa97e 1527
d828199e
MT		 1528 if (ka->use_master_clock)
1529 atomic_set(&kvm_guest_has_master_clock, 1);
1530
1531 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1532 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1533 vcpus_matched);
d828199e
MT		 1534#endif
1535}
1536
2e762ff7
MT		 1537static void kvm_gen_update_masterclock(struct kvm *kvm)
1538{
1539#ifdef CONFIG_X86_64
1540 int i;
1541 struct kvm_vcpu *vcpu;
1542 struct kvm_arch *ka = &kvm->arch;
1543
1544 spin_lock(&ka->pvclock_gtod_sync_lock);
1545 kvm_make_mclock_inprogress_request(kvm);
1546 /* no guest entries from this point */
1547 pvclock_update_vm_gtod_copy(kvm);
1548
1549 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1550 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1551
1552 /* guest entries allowed */
1553 kvm_for_each_vcpu(i, vcpu, kvm)
1554 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1555
1556 spin_unlock(&ka->pvclock_gtod_sync_lock);
1557#endif
1558}
1559
34c238a1 1560static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1561{
d828199e 1562 unsigned long flags, this_tsc_khz;
18068523 1563 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1564 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1565 s64 kernel_ns;
d828199e 1566 u64 tsc_timestamp, host_tsc;
0b79459b 1567 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1568 u8 pvclock_flags;
d828199e
MT		 1569 bool use_master_clock;
1570
1571 kernel_ns = 0;
1572 host_tsc = 0;
18068523 1573
d828199e
MT		 1574 /*
1575 * If the host uses TSC clock, then passthrough TSC as stable
1576 * to the guest.
1577 */
1578 spin_lock(&ka->pvclock_gtod_sync_lock);
1579 use_master_clock = ka->use_master_clock;
1580 if (use_master_clock) {
1581 host_tsc = ka->master_cycle_now;
1582 kernel_ns = ka->master_kernel_ns;
1583 }
1584 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1585
1586 /* Keep irq disabled to prevent changes to the clock */
1587 local_irq_save(flags);
89cbc767 1588 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1589 if (unlikely(this_tsc_khz == 0)) {
1590 local_irq_restore(flags);
1591 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1592 return 1;
1593 }
d828199e
MT		 1594 if (!use_master_clock) {
1595 host_tsc = native_read_tsc();
1596 kernel_ns = get_kernel_ns();
1597 }
1598
1599 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1600
c285545f
ZA		 1601 /*
1602 * We may have to catch up the TSC to match elapsed wall clock
1603 * time for two reasons, even if kvmclock is used.
1604 * 1) CPU could have been running below the maximum TSC rate
1605 * 2) Broken TSC compensation resets the base at each VCPU
1606 * entry to avoid unknown leaps of TSC even when running
1607 * again on the same CPU. This may cause apparent elapsed
1608 * time to disappear, and the guest to stand still or run
1609 * very slowly.
1610 */
1611 if (vcpu->tsc_catchup) {
1612 u64 tsc = compute_guest_tsc(v, kernel_ns);
1613 if (tsc > tsc_timestamp) {
f1e2b260 1614 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1615 tsc_timestamp = tsc;
1616 }
50d0a0f9
GH		 1617 }
1618
18068523
GOC		 1619 local_irq_restore(flags);
1620
0b79459b 1621 if (!vcpu->pv_time_enabled)
c285545f 1622 return 0;
18068523 1623
e48672fa 1624 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1625 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1626 &vcpu->hv_clock.tsc_shift,
1627 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1628 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1629 }
1630
1631 /* With all the info we got, fill in the values */
1d5f066e 1632 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1633 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1634 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1635
18068523
GOC		 1636 /*
1637 * The interface expects us to write an even number signaling that the
1638 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1639 * state, we just increase by 2 at the end.
18068523 1640 */
50d0a0f9 1641 vcpu->hv_clock.version += 2;
18068523 1642
0b79459b
AH		 1643 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1644 &guest_hv_clock, sizeof(guest_hv_clock))))
1645 return 0;
78c0337a
MT		 1646
1647 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1648 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1649
1650 if (vcpu->pvclock_set_guest_stopped_request) {
1651 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1652 vcpu->pvclock_set_guest_stopped_request = false;
1653 }
1654
d828199e
MT		 1655 /* If the host uses TSC clocksource, then it is stable */
1656 if (use_master_clock)
1657 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1658
78c0337a
MT		 1659 vcpu->hv_clock.flags = pvclock_flags;
1660
0b79459b
AH		 1661 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1662 &vcpu->hv_clock,
1663 sizeof(vcpu->hv_clock));
8cfdc000 1664 return 0;
c8076604
GH		 1665}
1666
0061d53d
MT		 1667/*
1668 * kvmclock updates which are isolated to a given vcpu, such as
1669 * vcpu->cpu migration, should not allow system_timestamp from
1670 * the rest of the vcpus to remain static. Otherwise ntp frequency
1671 * correction applies to one vcpu's system_timestamp but not
1672 * the others.
1673 *
1674 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1675 * We need to rate-limit these requests though, as they can
1676 * considerably slow guests that have a large number of vcpus.
1677 * The time for a remote vcpu to update its kvmclock is bound
1678 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1679 */
1680
7e44e449
AJ		 1681#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1682
1683static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1684{
1685 int i;
7e44e449
AJ		 1686 struct delayed_work *dwork = to_delayed_work(work);
1687 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1688 kvmclock_update_work);
1689 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1690 struct kvm_vcpu *vcpu;
1691
1692 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1693 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1694 kvm_vcpu_kick(vcpu);
1695 }
1696}
1697
7e44e449
AJ		 1698static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1699{
1700 struct kvm *kvm = v->kvm;
1701
105b21bb 1702 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1703 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1704 KVMCLOCK_UPDATE_DELAY);
1705}
1706
332967a3
AJ		 1707#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1708
1709static void kvmclock_sync_fn(struct work_struct *work)
1710{
1711 struct delayed_work *dwork = to_delayed_work(work);
1712 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1713 kvmclock_sync_work);
1714 struct kvm *kvm = container_of(ka, struct kvm, arch);
1715
1716 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1717 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1718 KVMCLOCK_SYNC_PERIOD);
1719}
1720
9ba075a6
AK		 1721static bool msr_mtrr_valid(unsigned msr)
1722{
1723 switch (msr) {
1724 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1725 case MSR_MTRRfix64K_00000:
1726 case MSR_MTRRfix16K_80000:
1727 case MSR_MTRRfix16K_A0000:
1728 case MSR_MTRRfix4K_C0000:
1729 case MSR_MTRRfix4K_C8000:
1730 case MSR_MTRRfix4K_D0000:
1731 case MSR_MTRRfix4K_D8000:
1732 case MSR_MTRRfix4K_E0000:
1733 case MSR_MTRRfix4K_E8000:
1734 case MSR_MTRRfix4K_F0000:
1735 case MSR_MTRRfix4K_F8000:
1736 case MSR_MTRRdefType:
1737 case MSR_IA32_CR_PAT:
1738 return true;
1739 case 0x2f8:
1740 return true;
1741 }
1742 return false;
1743}
1744
d6289b93
MT		 1745static bool valid_pat_type(unsigned t)
1746{
1747 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1748}
1749
1750static bool valid_mtrr_type(unsigned t)
1751{
1752 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1753}
1754
4566654b 1755bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
d6289b93
MT		 1756{
1757 int i;
fd275235 1758 u64 mask;
d6289b93
MT		 1759
1760 if (!msr_mtrr_valid(msr))
1761 return false;
1762
1763 if (msr == MSR_IA32_CR_PAT) {
1764 for (i = 0; i < 8; i++)
1765 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1766 return false;
1767 return true;
1768 } else if (msr == MSR_MTRRdefType) {
1769 if (data & ~0xcff)
1770 return false;
1771 return valid_mtrr_type(data & 0xff);
1772 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1773 for (i = 0; i < 8 ; i++)
1774 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1775 return false;
1776 return true;
1777 }
1778
1779 /* variable MTRRs */
adfb5d27
WL		 1780 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1781
fd275235 1782 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1783 if ((msr & 1) == 0) {
adfb5d27 1784 /* MTRR base */
d7a2a246
WL		 1785 if (!valid_mtrr_type(data & 0xff))
1786 return false;
1787 mask |= 0xf00;
1788 } else
1789 /* MTRR mask */
1790 mask |= 0x7ff;
1791 if (data & mask) {
1792 kvm_inject_gp(vcpu, 0);
1793 return false;
1794 }
1795
adfb5d27 1796 return true;
d6289b93 1797}
4566654b 1798EXPORT_SYMBOL_GPL(kvm_mtrr_valid);
d6289b93 1799
9ba075a6
AK		 1800static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1801{
0bed3b56
SY		 1802 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1803
4566654b 1804 if (!kvm_mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1805 return 1;
1806
0bed3b56
SY		 1807 if (msr == MSR_MTRRdefType) {
1808 vcpu->arch.mtrr_state.def_type = data;
1809 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1810 } else if (msr == MSR_MTRRfix64K_00000)
1811 p[0] = data;
1812 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1813 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1814 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1815 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1816 else if (msr == MSR_IA32_CR_PAT)
1817 vcpu->arch.pat = data;
1818 else { /* Variable MTRRs */
1819 int idx, is_mtrr_mask;
1820 u64 *pt;
1821
1822 idx = (msr - 0x200) / 2;
1823 is_mtrr_mask = msr - 0x200 - 2 * idx;
1824 if (!is_mtrr_mask)
1825 pt =
1826 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1827 else
1828 pt =
1829 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1830 *pt = data;
1831 }
1832
1833 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1834 return 0;
1835}
15c4a640 1836
890ca9ae 1837static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1838{
890ca9ae
HY		 1839 u64 mcg_cap = vcpu->arch.mcg_cap;
1840 unsigned bank_num = mcg_cap & 0xff;
1841
15c4a640 1842 switch (msr) {
15c4a640 1843 case MSR_IA32_MCG_STATUS:
890ca9ae 1844 vcpu->arch.mcg_status = data;
15c4a640 1845 break;
c7ac679c 1846 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1847 if (!(mcg_cap & MCG_CTL_P))
1848 return 1;
1849 if (data != 0 && data != ~(u64)0)
1850 return -1;
1851 vcpu->arch.mcg_ctl = data;
1852 break;
1853 default:
1854 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1855 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1856 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1857 /* only 0 or all 1s can be written to IA32_MCi_CTL
1858 * some Linux kernels though clear bit 10 in bank 4 to
1859 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1860 * this to avoid an uncatched #GP in the guest
1861 */
890ca9ae 1862 if ((offset & 0x3) == 0 &&
114be429 1863 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1864 return -1;
1865 vcpu->arch.mce_banks[offset] = data;
1866 break;
1867 }
1868 return 1;
1869 }
1870 return 0;
1871}
1872
ffde22ac
ES		 1873static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1874{
1875 struct kvm *kvm = vcpu->kvm;
1876 int lm = is_long_mode(vcpu);
1877 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1878 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1879 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1880 : kvm->arch.xen_hvm_config.blob_size_32;
1881 u32 page_num = data & ~PAGE_MASK;
1882 u64 page_addr = data & PAGE_MASK;
1883 u8 *page;
1884 int r;
1885
1886 r = -E2BIG;
1887 if (page_num >= blob_size)
1888 goto out;
1889 r = -ENOMEM;
ff5c2c03
SL		 1890 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1891 if (IS_ERR(page)) {
1892 r = PTR_ERR(page);
ffde22ac 1893 goto out;
ff5c2c03 1894 }
ffde22ac
ES		 1895 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1896 goto out_free;
1897 r = 0;
1898out_free:
1899 kfree(page);
1900out:
1901 return r;
1902}
1903
55cd8e5a
GN		 1904static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1905{
1906 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1907}
1908
1909static bool kvm_hv_msr_partition_wide(u32 msr)
1910{
1911 bool r = false;
1912 switch (msr) {
1913 case HV_X64_MSR_GUEST_OS_ID:
1914 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1915 case HV_X64_MSR_REFERENCE_TSC:
1916 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1917 r = true;
1918 break;
1919 }
1920
1921 return r;
1922}
1923
1924static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1925{
1926 struct kvm *kvm = vcpu->kvm;
1927
1928 switch (msr) {
1929 case HV_X64_MSR_GUEST_OS_ID:
1930 kvm->arch.hv_guest_os_id = data;
1931 /* setting guest os id to zero disables hypercall page */
1932 if (!kvm->arch.hv_guest_os_id)
1933 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1934 break;
1935 case HV_X64_MSR_HYPERCALL: {
1936 u64 gfn;
1937 unsigned long addr;
1938 u8 instructions[4];
1939
1940 /* if guest os id is not set hypercall should remain disabled */
1941 if (!kvm->arch.hv_guest_os_id)
1942 break;
1943 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1944 kvm->arch.hv_hypercall = data;
1945 break;
1946 }
1947 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1948 addr = gfn_to_hva(kvm, gfn);
1949 if (kvm_is_error_hva(addr))
1950 return 1;
1951 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1952 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1953 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1954 return 1;
1955 kvm->arch.hv_hypercall = data;
b94b64c9 1956 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1957 break;
1958 }
e984097b
VR		 1959 case HV_X64_MSR_REFERENCE_TSC: {
1960 u64 gfn;
1961 HV_REFERENCE_TSC_PAGE tsc_ref;
1962 memset(&tsc_ref, 0, sizeof(tsc_ref));
1963 kvm->arch.hv_tsc_page = data;
1964 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1965 break;
1966 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1967 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1968 &tsc_ref, sizeof(tsc_ref)))
1969 return 1;
1970 mark_page_dirty(kvm, gfn);
1971 break;
1972 }
55cd8e5a 1973 default:
a737f256
CD		 1974 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1975 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1976 return 1;
1977 }
1978 return 0;
1979}
1980
1981static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1982{
10388a07
GN		 1983 switch (msr) {
1984 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1985 u64 gfn;
10388a07 1986 unsigned long addr;
55cd8e5a 1987
10388a07
GN		 1988 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1989 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1990 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1991 return 1;
10388a07
GN		 1992 break;
1993 }
b3af1e88
VR		 1994 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1995 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1996 if (kvm_is_error_hva(addr))
1997 return 1;
8b0cedff 1998 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1999 return 1;
2000 vcpu->arch.hv_vapic = data;
b3af1e88 2001 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 2002 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
2003 return 1;
10388a07
GN		 2004 break;
2005 }
2006 case HV_X64_MSR_EOI:
2007 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
2008 case HV_X64_MSR_ICR:
2009 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
2010 case HV_X64_MSR_TPR:
2011 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
2012 default:
a737f256
CD		 2013 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
2014 "data 0x%llx\n", msr, data);
10388a07
GN		 2015 return 1;
2016 }
2017
2018 return 0;
55cd8e5a
GN		 2019}
2020
344d9588
GN		 2021static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2022{
2023 gpa_t gpa = data & ~0x3f;
2024
4a969980 2025 /* Bits 2:5 are reserved, Should be zero */
6adba527 2026 if (data & 0x3c)
344d9588
GN		 2027 return 1;
2028
2029 vcpu->arch.apf.msr_val = data;
2030
2031 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2032 kvm_clear_async_pf_completion_queue(vcpu);
2033 kvm_async_pf_hash_reset(vcpu);
2034 return 0;
2035 }
2036
8f964525
AH		 2037 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2038 sizeof(u32)))
344d9588
GN		 2039 return 1;
2040
6adba527 2041 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2042 kvm_async_pf_wakeup_all(vcpu);
2043 return 0;
2044}
2045
12f9a48f
GC		 2046static void kvmclock_reset(struct kvm_vcpu *vcpu)
2047{
0b79459b 2048 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2049}
2050
c9aaa895
GC		 2051static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2052{
2053 u64 delta;
2054
2055 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2056 return;
2057
2058 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2059 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2060 vcpu->arch.st.accum_steal = delta;
2061}
2062
2063static void record_steal_time(struct kvm_vcpu *vcpu)
2064{
2065 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2066 return;
2067
2068 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2069 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2070 return;
2071
2072 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2073 vcpu->arch.st.steal.version += 2;
2074 vcpu->arch.st.accum_steal = 0;
2075
2076 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2077 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2078}
2079
8fe8ab46 2080int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2081{
5753785f 2082 bool pr = false;
8fe8ab46
WA		 2083 u32 msr = msr_info->index;
2084 u64 data = msr_info->data;
5753785f 2085
15c4a640 2086 switch (msr) {
2e32b719
BP		 2087 case MSR_AMD64_NB_CFG:
2088 case MSR_IA32_UCODE_REV:
2089 case MSR_IA32_UCODE_WRITE:
2090 case MSR_VM_HSAVE_PA:
2091 case MSR_AMD64_PATCH_LOADER:
2092 case MSR_AMD64_BU_CFG2:
2093 break;
2094
15c4a640 2095 case MSR_EFER:
b69e8cae 2096 return set_efer(vcpu, data);
8f1589d9
AP		 2097 case MSR_K7_HWCR:
2098 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2099 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2100 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2101 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2102 if (data != 0) {
a737f256
CD		 2103 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2104 data);
8f1589d9
AP		 2105 return 1;
2106 }
15c4a640 2107 break;
f7c6d140
AP		 2108 case MSR_FAM10H_MMIO_CONF_BASE:
2109 if (data != 0) {
a737f256
CD		 2110 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2111 "0x%llx\n", data);
f7c6d140
AP		 2112 return 1;
2113 }
15c4a640 2114 break;
b5e2fec0
AG		 2115 case MSR_IA32_DEBUGCTLMSR:
2116 if (!data) {
2117 /* We support the non-activated case already */
2118 break;
2119 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2120 /* Values other than LBR and BTF are vendor-specific,
2121 thus reserved and should throw a #GP */
2122 return 1;
2123 }
a737f256
CD		 2124 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2125 __func__, data);
b5e2fec0 2126 break;
9ba075a6
AK		 2127 case 0x200 ... 0x2ff:
2128 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2129 case MSR_IA32_APICBASE:
58cb628d 2130 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2131 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2132 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2133 case MSR_IA32_TSCDEADLINE:
2134 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2135 break;
ba904635
WA		 2136 case MSR_IA32_TSC_ADJUST:
2137 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2138 if (!msr_info->host_initiated) {
2139 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2140 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2141 }
2142 vcpu->arch.ia32_tsc_adjust_msr = data;
2143 }
2144 break;
15c4a640 2145 case MSR_IA32_MISC_ENABLE:
ad312c7c 2146 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2147 break;
11c6bffa 2148 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2149 case MSR_KVM_WALL_CLOCK:
2150 vcpu->kvm->arch.wall_clock = data;
2151 kvm_write_wall_clock(vcpu->kvm, data);
2152 break;
11c6bffa 2153 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2154 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2155 u64 gpa_offset;
12f9a48f 2156 kvmclock_reset(vcpu);
18068523
GOC		 2157
2158 vcpu->arch.time = data;
0061d53d 2159 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2160
2161 /* we verify if the enable bit is set... */
2162 if (!(data & 1))
2163 break;
2164
0b79459b 2165 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2166
0b79459b 2167 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2168 &vcpu->arch.pv_time, data & ~1ULL,
2169 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2170 vcpu->arch.pv_time_enabled = false;
2171 else
2172 vcpu->arch.pv_time_enabled = true;
32cad84f 2173
18068523
GOC		 2174 break;
2175 }
344d9588
GN		 2176 case MSR_KVM_ASYNC_PF_EN:
2177 if (kvm_pv_enable_async_pf(vcpu, data))
2178 return 1;
2179 break;
c9aaa895
GC		 2180 case MSR_KVM_STEAL_TIME:
2181
2182 if (unlikely(!sched_info_on()))
2183 return 1;
2184
2185 if (data & KVM_STEAL_RESERVED_MASK)
2186 return 1;
2187
2188 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2189 data & KVM_STEAL_VALID_BITS,
2190 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2191 return 1;
2192
2193 vcpu->arch.st.msr_val = data;
2194
2195 if (!(data & KVM_MSR_ENABLED))
2196 break;
2197
2198 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2199
2200 preempt_disable();
2201 accumulate_steal_time(vcpu);
2202 preempt_enable();
2203
2204 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2205
2206 break;
ae7a2a3f
MT		 2207 case MSR_KVM_PV_EOI_EN:
2208 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2209 return 1;
2210 break;
c9aaa895 2211
890ca9ae
HY		 2212 case MSR_IA32_MCG_CTL:
2213 case MSR_IA32_MCG_STATUS:
81760dcc 2214 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2215 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2216
2217 /* Performance counters are not protected by a CPUID bit,
2218 * so we should check all of them in the generic path for the sake of
2219 * cross vendor migration.
2220 * Writing a zero into the event select MSRs disables them,
2221 * which we perfectly emulate ;-). Any other value should be at least
2222 * reported, some guests depend on them.
2223 */
71db6023
AP		 2224 case MSR_K7_EVNTSEL0:
2225 case MSR_K7_EVNTSEL1:
2226 case MSR_K7_EVNTSEL2:
2227 case MSR_K7_EVNTSEL3:
2228 if (data != 0)
a737f256
CD		 2229 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2230 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2231 break;
2232 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2233 * so we ignore writes to make it happy.
2234 */
71db6023
AP		 2235 case MSR_K7_PERFCTR0:
2236 case MSR_K7_PERFCTR1:
2237 case MSR_K7_PERFCTR2:
2238 case MSR_K7_PERFCTR3:
a737f256
CD		 2239 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2240 "0x%x data 0x%llx\n", msr, data);
71db6023 2241 break;
5753785f
GN		 2242 case MSR_P6_PERFCTR0:
2243 case MSR_P6_PERFCTR1:
2244 pr = true;
2245 case MSR_P6_EVNTSEL0:
2246 case MSR_P6_EVNTSEL1:
2247 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2248 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2249
2250 if (pr || data != 0)
a737f256
CD		 2251 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2252 "0x%x data 0x%llx\n", msr, data);
5753785f 2253 break;
84e0cefa
JS		 2254 case MSR_K7_CLK_CTL:
2255 /*
2256 * Ignore all writes to this no longer documented MSR.
2257 * Writes are only relevant for old K7 processors,
2258 * all pre-dating SVM, but a recommended workaround from
4a969980 2259 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2260 * affected processor models on the command line, hence
2261 * the need to ignore the workaround.
2262 */
2263 break;
55cd8e5a
GN		 2264 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2265 if (kvm_hv_msr_partition_wide(msr)) {
2266 int r;
2267 mutex_lock(&vcpu->kvm->lock);
2268 r = set_msr_hyperv_pw(vcpu, msr, data);
2269 mutex_unlock(&vcpu->kvm->lock);
2270 return r;
2271 } else
2272 return set_msr_hyperv(vcpu, msr, data);
2273 break;
91c9c3ed 2274 case MSR_IA32_BBL_CR_CTL3:
2275 /* Drop writes to this legacy MSR -- see rdmsr
2276 * counterpart for further detail.
2277 */
a737f256 2278 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2279 break;
2b036c6b
BO		 2280 case MSR_AMD64_OSVW_ID_LENGTH:
2281 if (!guest_cpuid_has_osvw(vcpu))
2282 return 1;
2283 vcpu->arch.osvw.length = data;
2284 break;
2285 case MSR_AMD64_OSVW_STATUS:
2286 if (!guest_cpuid_has_osvw(vcpu))
2287 return 1;
2288 vcpu->arch.osvw.status = data;
2289 break;
15c4a640 2290 default:
ffde22ac
ES		 2291 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2292 return xen_hvm_config(vcpu, data);
f5132b01 2293 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2294 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2295 if (!ignore_msrs) {
a737f256
CD		 2296 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2297 msr, data);
ed85c068
AP		 2298 return 1;
2299 } else {
a737f256
CD		 2300 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2301 msr, data);
ed85c068
AP		 2302 break;
2303 }
15c4a640
CO		 2304 }
2305 return 0;
2306}
2307EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2308
2309
2310/*
2311 * Reads an msr value (of 'msr_index') into 'pdata'.
2312 * Returns 0 on success, non-0 otherwise.
2313 * Assumes vcpu_load() was already called.
2314 */
2315int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2316{
2317 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2318}
2319
9ba075a6
AK		 2320static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2321{
0bed3b56
SY		 2322 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2323
9ba075a6
AK		 2324 if (!msr_mtrr_valid(msr))
2325 return 1;
2326
0bed3b56
SY		 2327 if (msr == MSR_MTRRdefType)
2328 *pdata = vcpu->arch.mtrr_state.def_type +
2329 (vcpu->arch.mtrr_state.enabled << 10);
2330 else if (msr == MSR_MTRRfix64K_00000)
2331 *pdata = p[0];
2332 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2333 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2334 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2335 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2336 else if (msr == MSR_IA32_CR_PAT)
2337 *pdata = vcpu->arch.pat;
2338 else { /* Variable MTRRs */
2339 int idx, is_mtrr_mask;
2340 u64 *pt;
2341
2342 idx = (msr - 0x200) / 2;
2343 is_mtrr_mask = msr - 0x200 - 2 * idx;
2344 if (!is_mtrr_mask)
2345 pt =
2346 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2347 else
2348 pt =
2349 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2350 *pdata = *pt;
2351 }
2352
9ba075a6
AK		 2353 return 0;
2354}
2355
890ca9ae 2356static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2357{
2358 u64 data;
890ca9ae
HY		 2359 u64 mcg_cap = vcpu->arch.mcg_cap;
2360 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2361
2362 switch (msr) {
15c4a640
CO		 2363 case MSR_IA32_P5_MC_ADDR:
2364 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2365 data = 0;
2366 break;
15c4a640 2367 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2368 data = vcpu->arch.mcg_cap;
2369 break;
c7ac679c 2370 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2371 if (!(mcg_cap & MCG_CTL_P))
2372 return 1;
2373 data = vcpu->arch.mcg_ctl;
2374 break;
2375 case MSR_IA32_MCG_STATUS:
2376 data = vcpu->arch.mcg_status;
2377 break;
2378 default:
2379 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2380 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2381 u32 offset = msr - MSR_IA32_MC0_CTL;
2382 data = vcpu->arch.mce_banks[offset];
2383 break;
2384 }
2385 return 1;
2386 }
2387 *pdata = data;
2388 return 0;
2389}
2390
55cd8e5a
GN		 2391static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2392{
2393 u64 data = 0;
2394 struct kvm *kvm = vcpu->kvm;
2395
2396 switch (msr) {
2397 case HV_X64_MSR_GUEST_OS_ID:
2398 data = kvm->arch.hv_guest_os_id;
2399 break;
2400 case HV_X64_MSR_HYPERCALL:
2401 data = kvm->arch.hv_hypercall;
2402 break;
e984097b
VR		 2403 case HV_X64_MSR_TIME_REF_COUNT: {
2404 data =
2405 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2406 break;
2407 }
2408 case HV_X64_MSR_REFERENCE_TSC:
2409 data = kvm->arch.hv_tsc_page;
2410 break;
55cd8e5a 2411 default:
a737f256 2412 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2413 return 1;
2414 }
2415
2416 *pdata = data;
2417 return 0;
2418}
2419
2420static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2421{
2422 u64 data = 0;
2423
2424 switch (msr) {
2425 case HV_X64_MSR_VP_INDEX: {
2426 int r;
2427 struct kvm_vcpu *v;
684851a1
TY		 2428 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2429 if (v == vcpu) {
55cd8e5a 2430 data = r;
684851a1
TY		 2431 break;
2432 }
2433 }
55cd8e5a
GN		 2434 break;
2435 }
10388a07
GN		 2436 case HV_X64_MSR_EOI:
2437 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2438 case HV_X64_MSR_ICR:
2439 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2440 case HV_X64_MSR_TPR:
2441 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2442 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2443 data = vcpu->arch.hv_vapic;
2444 break;
55cd8e5a 2445 default:
a737f256 2446 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2447 return 1;
2448 }
2449 *pdata = data;
2450 return 0;
2451}
2452
890ca9ae
HY		 2453int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2454{
2455 u64 data;
2456
2457 switch (msr) {
890ca9ae 2458 case MSR_IA32_PLATFORM_ID:
15c4a640 2459 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2460 case MSR_IA32_DEBUGCTLMSR:
2461 case MSR_IA32_LASTBRANCHFROMIP:
2462 case MSR_IA32_LASTBRANCHTOIP:
2463 case MSR_IA32_LASTINTFROMIP:
2464 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2465 case MSR_K8_SYSCFG:
2466 case MSR_K7_HWCR:
61a6bd67 2467 case MSR_VM_HSAVE_PA:
9e699624 2468 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2469 case MSR_K7_EVNTSEL1:
2470 case MSR_K7_EVNTSEL2:
2471 case MSR_K7_EVNTSEL3:
1f3ee616 2472 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2473 case MSR_K7_PERFCTR1:
2474 case MSR_K7_PERFCTR2:
2475 case MSR_K7_PERFCTR3:
1fdbd48c 2476 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2477 case MSR_AMD64_NB_CFG:
f7c6d140 2478 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2479 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2480 data = 0;
2481 break;
5753785f
GN		 2482 case MSR_P6_PERFCTR0:
2483 case MSR_P6_PERFCTR1:
2484 case MSR_P6_EVNTSEL0:
2485 case MSR_P6_EVNTSEL1:
2486 if (kvm_pmu_msr(vcpu, msr))
2487 return kvm_pmu_get_msr(vcpu, msr, pdata);
2488 data = 0;
2489 break;
742bc670
MT		 2490 case MSR_IA32_UCODE_REV:
2491 data = 0x100000000ULL;
2492 break;
9ba075a6
AK		 2493 case MSR_MTRRcap:
2494 data = 0x500 | KVM_NR_VAR_MTRR;
2495 break;
2496 case 0x200 ... 0x2ff:
2497 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2498 case 0xcd: /* fsb frequency */
2499 data = 3;
2500 break;
7b914098
JS		 2501 /*
2502 * MSR_EBC_FREQUENCY_ID
2503 * Conservative value valid for even the basic CPU models.
2504 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2505 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2506 * and 266MHz for model 3, or 4. Set Core Clock
2507 * Frequency to System Bus Frequency Ratio to 1 (bits
2508 * 31:24) even though these are only valid for CPU
2509 * models > 2, however guests may end up dividing or
2510 * multiplying by zero otherwise.
2511 */
2512 case MSR_EBC_FREQUENCY_ID:
2513 data = 1 << 24;
2514 break;
15c4a640
CO		 2515 case MSR_IA32_APICBASE:
2516 data = kvm_get_apic_base(vcpu);
2517 break;
0105d1a5
GN		 2518 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2519 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2520 break;
a3e06bbe
LJ		 2521 case MSR_IA32_TSCDEADLINE:
2522 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2523 break;
ba904635
WA		 2524 case MSR_IA32_TSC_ADJUST:
2525 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2526 break;
15c4a640 2527 case MSR_IA32_MISC_ENABLE:
ad312c7c 2528 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2529 break;
847f0ad8
AG		 2530 case MSR_IA32_PERF_STATUS:
2531 /* TSC increment by tick */
2532 data = 1000ULL;
2533 /* CPU multiplier */
2534 data |= (((uint64_t)4ULL) << 40);
2535 break;
15c4a640 2536 case MSR_EFER:
f6801dff 2537 data = vcpu->arch.efer;
15c4a640 2538 break;
18068523 2539 case MSR_KVM_WALL_CLOCK:
11c6bffa 2540 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2541 data = vcpu->kvm->arch.wall_clock;
2542 break;
2543 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2544 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2545 data = vcpu->arch.time;
2546 break;
344d9588
GN		 2547 case MSR_KVM_ASYNC_PF_EN:
2548 data = vcpu->arch.apf.msr_val;
2549 break;
c9aaa895
GC		 2550 case MSR_KVM_STEAL_TIME:
2551 data = vcpu->arch.st.msr_val;
2552 break;
1d92128f
MT		 2553 case MSR_KVM_PV_EOI_EN:
2554 data = vcpu->arch.pv_eoi.msr_val;
2555 break;
890ca9ae
HY		 2556 case MSR_IA32_P5_MC_ADDR:
2557 case MSR_IA32_P5_MC_TYPE:
2558 case MSR_IA32_MCG_CAP:
2559 case MSR_IA32_MCG_CTL:
2560 case MSR_IA32_MCG_STATUS:
81760dcc 2561 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2562 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2563 case MSR_K7_CLK_CTL:
2564 /*
2565 * Provide expected ramp-up count for K7. All other
2566 * are set to zero, indicating minimum divisors for
2567 * every field.
2568 *
2569 * This prevents guest kernels on AMD host with CPU
2570 * type 6, model 8 and higher from exploding due to
2571 * the rdmsr failing.
2572 */
2573 data = 0x20000000;
2574 break;
55cd8e5a
GN		 2575 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2576 if (kvm_hv_msr_partition_wide(msr)) {
2577 int r;
2578 mutex_lock(&vcpu->kvm->lock);
2579 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2580 mutex_unlock(&vcpu->kvm->lock);
2581 return r;
2582 } else
2583 return get_msr_hyperv(vcpu, msr, pdata);
2584 break;
91c9c3ed 2585 case MSR_IA32_BBL_CR_CTL3:
2586 /* This legacy MSR exists but isn't fully documented in current
2587 * silicon. It is however accessed by winxp in very narrow
2588 * scenarios where it sets bit #19, itself documented as
2589 * a "reserved" bit. Best effort attempt to source coherent
2590 * read data here should the balance of the register be
2591 * interpreted by the guest:
2592 *
2593 * L2 cache control register 3: 64GB range, 256KB size,
2594 * enabled, latency 0x1, configured
2595 */
2596 data = 0xbe702111;
2597 break;
2b036c6b
BO		 2598 case MSR_AMD64_OSVW_ID_LENGTH:
2599 if (!guest_cpuid_has_osvw(vcpu))
2600 return 1;
2601 data = vcpu->arch.osvw.length;
2602 break;
2603 case MSR_AMD64_OSVW_STATUS:
2604 if (!guest_cpuid_has_osvw(vcpu))
2605 return 1;
2606 data = vcpu->arch.osvw.status;
2607 break;
15c4a640 2608 default:
f5132b01
GN		 2609 if (kvm_pmu_msr(vcpu, msr))
2610 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2611 if (!ignore_msrs) {
a737f256 2612 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2613 return 1;
2614 } else {
a737f256 2615 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2616 data = 0;
2617 }
2618 break;
15c4a640
CO		 2619 }
2620 *pdata = data;
2621 return 0;
2622}
2623EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2624
313a3dc7
CO		 2625/*
2626 * Read or write a bunch of msrs. All parameters are kernel addresses.
2627 *
2628 * @return number of msrs set successfully.
2629 */
2630static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2631 struct kvm_msr_entry *entries,
2632 int (*do_msr)(struct kvm_vcpu *vcpu,
2633 unsigned index, u64 *data))
2634{
f656ce01 2635 int i, idx;
313a3dc7 2636
f656ce01 2637 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2638 for (i = 0; i < msrs->nmsrs; ++i)
2639 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2640 break;
f656ce01 2641 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2642
313a3dc7
CO		 2643 return i;
2644}
2645
2646/*
2647 * Read or write a bunch of msrs. Parameters are user addresses.
2648 *
2649 * @return number of msrs set successfully.
2650 */
2651static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2652 int (*do_msr)(struct kvm_vcpu *vcpu,
2653 unsigned index, u64 *data),
2654 int writeback)
2655{
2656 struct kvm_msrs msrs;
2657 struct kvm_msr_entry *entries;
2658 int r, n;
2659 unsigned size;
2660
2661 r = -EFAULT;
2662 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2663 goto out;
2664
2665 r = -E2BIG;
2666 if (msrs.nmsrs >= MAX_IO_MSRS)
2667 goto out;
2668
313a3dc7 2669 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2670 entries = memdup_user(user_msrs->entries, size);
2671 if (IS_ERR(entries)) {
2672 r = PTR_ERR(entries);
313a3dc7 2673 goto out;
ff5c2c03 2674 }
313a3dc7
CO		 2675
2676 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2677 if (r < 0)
2678 goto out_free;
2679
2680 r = -EFAULT;
2681 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2682 goto out_free;
2683
2684 r = n;
2685
2686out_free:
7a73c028 2687 kfree(entries);
313a3dc7
CO		 2688out:
2689 return r;
2690}
2691
784aa3d7 2692int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2693{
2694 int r;
2695
2696 switch (ext) {
2697 case KVM_CAP_IRQCHIP:
2698 case KVM_CAP_HLT:
2699 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2700 case KVM_CAP_SET_TSS_ADDR:
07716717 2701 case KVM_CAP_EXT_CPUID:
9c15bb1d 2702 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2703 case KVM_CAP_CLOCKSOURCE:
7837699f 2704 case KVM_CAP_PIT:
a28e4f5a 2705 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2706 case KVM_CAP_MP_STATE:
ed848624 2707 case KVM_CAP_SYNC_MMU:
a355c85c 2708 case KVM_CAP_USER_NMI:
52d939a0 2709 case KVM_CAP_REINJECT_CONTROL:
4925663a 2710 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2711 case KVM_CAP_IRQFD:
d34e6b17 2712 case KVM_CAP_IOEVENTFD:
f848a5a8 2713 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2714 case KVM_CAP_PIT2:
e9f42757 2715 case KVM_CAP_PIT_STATE2:
b927a3ce 2716 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2717 case KVM_CAP_XEN_HVM:
afbcf7ab 2718 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2719 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2720 case KVM_CAP_HYPERV:
10388a07 2721 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2722 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2723 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2724 case KVM_CAP_DEBUGREGS:
d2be1651 2725 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2726 case KVM_CAP_XSAVE:
344d9588 2727 case KVM_CAP_ASYNC_PF:
92a1f12d 2728 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2729 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2730 case KVM_CAP_READONLY_MEM:
5f66b620 2731 case KVM_CAP_HYPERV_TIME:
100943c5 2732 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2733#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2734 case KVM_CAP_ASSIGN_DEV_IRQ:
2735 case KVM_CAP_PCI_2_3:
2736#endif
018d00d2
ZX		 2737 r = 1;
2738 break;
542472b5
LV		 2739 case KVM_CAP_COALESCED_MMIO:
2740 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2741 break;
774ead3a
AK		 2742 case KVM_CAP_VAPIC:
2743 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2744 break;
f725230a 2745 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2746 r = KVM_SOFT_MAX_VCPUS;
2747 break;
2748 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2749 r = KVM_MAX_VCPUS;
2750 break;
a988b910 2751 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2752 r = KVM_USER_MEM_SLOTS;
a988b910 2753 break;
a68a6a72
MT		 2754 case KVM_CAP_PV_MMU: /* obsolete */
2755 r = 0;
2f333bcb 2756 break;
4cee4b72 2757#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2758 case KVM_CAP_IOMMU:
a1b60c1c 2759 r = iommu_present(&pci_bus_type);
62c476c7 2760 break;
4cee4b72 2761#endif
890ca9ae
HY		 2762 case KVM_CAP_MCE:
2763 r = KVM_MAX_MCE_BANKS;
2764 break;
2d5b5a66
SY		 2765 case KVM_CAP_XCRS:
2766 r = cpu_has_xsave;
2767 break;
92a1f12d
JR		 2768 case KVM_CAP_TSC_CONTROL:
2769 r = kvm_has_tsc_control;
2770 break;
4d25a066
JK		 2771 case KVM_CAP_TSC_DEADLINE_TIMER:
2772 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2773 break;
018d00d2
ZX		 2774 default:
2775 r = 0;
2776 break;
2777 }
2778 return r;
2779
2780}
2781
043405e1
CO		 2782long kvm_arch_dev_ioctl(struct file *filp,
2783 unsigned int ioctl, unsigned long arg)
2784{
2785 void __user *argp = (void __user *)arg;
2786 long r;
2787
2788 switch (ioctl) {
2789 case KVM_GET_MSR_INDEX_LIST: {
2790 struct kvm_msr_list __user *user_msr_list = argp;
2791 struct kvm_msr_list msr_list;
2792 unsigned n;
2793
2794 r = -EFAULT;
2795 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2796 goto out;
2797 n = msr_list.nmsrs;
2798 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2799 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2800 goto out;
2801 r = -E2BIG;
e125e7b6 2802 if (n < msr_list.nmsrs)
043405e1
CO		 2803 goto out;
2804 r = -EFAULT;
2805 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2806 num_msrs_to_save * sizeof(u32)))
2807 goto out;
e125e7b6 2808 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2809 &emulated_msrs,
2810 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2811 goto out;
2812 r = 0;
2813 break;
2814 }
9c15bb1d
BP		 2815 case KVM_GET_SUPPORTED_CPUID:
2816 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2817 struct kvm_cpuid2 __user *cpuid_arg = argp;
2818 struct kvm_cpuid2 cpuid;
2819
2820 r = -EFAULT;
2821 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2822 goto out;
9c15bb1d
BP		 2823
2824 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2825 ioctl);
674eea0f
AK		 2826 if (r)
2827 goto out;
2828
2829 r = -EFAULT;
2830 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2831 goto out;
2832 r = 0;
2833 break;
2834 }
890ca9ae
HY		 2835 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2836 u64 mce_cap;
2837
2838 mce_cap = KVM_MCE_CAP_SUPPORTED;
2839 r = -EFAULT;
2840 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2841 goto out;
2842 r = 0;
2843 break;
2844 }
043405e1
CO		 2845 default:
2846 r = -EINVAL;
2847 }
2848out:
2849 return r;
2850}
2851
f5f48ee1
SY		 2852static void wbinvd_ipi(void *garbage)
2853{
2854 wbinvd();
2855}
2856
2857static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2858{
e0f0bbc5 2859 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2860}
2861
313a3dc7
CO		 2862void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2863{
f5f48ee1
SY		 2864 /* Address WBINVD may be executed by guest */
2865 if (need_emulate_wbinvd(vcpu)) {
2866 if (kvm_x86_ops->has_wbinvd_exit())
2867 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2868 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2869 smp_call_function_single(vcpu->cpu,
2870 wbinvd_ipi, NULL, 1);
2871 }
2872
313a3dc7 2873 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2874
0dd6a6ed
ZA		 2875 /* Apply any externally detected TSC adjustments (due to suspend) */
2876 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2877 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2878 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2879 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2880 }
8f6055cb 2881
48434c20 2882 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2883 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2884 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2885 if (tsc_delta < 0)
2886 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2887 if (check_tsc_unstable()) {
b183aa58
ZA		 2888 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2889 vcpu->arch.last_guest_tsc);
2890 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2891 vcpu->arch.tsc_catchup = 1;
c285545f 2892 }
d98d07ca
MT		 2893 /*
2894 * On a host with synchronized TSC, there is no need to update
2895 * kvmclock on vcpu->cpu migration
2896 */
2897 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2898 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2899 if (vcpu->cpu != cpu)
2900 kvm_migrate_timers(vcpu);
e48672fa 2901 vcpu->cpu = cpu;
6b7d7e76 2902 }
c9aaa895
GC		 2903
2904 accumulate_steal_time(vcpu);
2905 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2906}
2907
2908void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2909{
02daab21 2910 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2911 kvm_put_guest_fpu(vcpu);
6f526ec5 2912 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2913}
2914
313a3dc7
CO		 2915static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2916 struct kvm_lapic_state *s)
2917{
5a71785d 2918 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2919 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2920
2921 return 0;
2922}
2923
2924static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2925 struct kvm_lapic_state *s)
2926{
64eb0620 2927 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2928 update_cr8_intercept(vcpu);
313a3dc7
CO		 2929
2930 return 0;
2931}
2932
f77bc6a4
ZX		 2933static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2934 struct kvm_interrupt *irq)
2935{
02cdb50f 2936 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2937 return -EINVAL;
2938 if (irqchip_in_kernel(vcpu->kvm))
2939 return -ENXIO;
f77bc6a4 2940
66fd3f7f 2941 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2942 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2943
f77bc6a4
ZX		 2944 return 0;
2945}
2946
c4abb7c9
JK		 2947static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2948{
c4abb7c9 2949 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2950
2951 return 0;
2952}
2953
b209749f
AK		 2954static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2955 struct kvm_tpr_access_ctl *tac)
2956{
2957 if (tac->flags)
2958 return -EINVAL;
2959 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2960 return 0;
2961}
2962
890ca9ae
HY		 2963static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2964 u64 mcg_cap)
2965{
2966 int r;
2967 unsigned bank_num = mcg_cap & 0xff, bank;
2968
2969 r = -EINVAL;
a9e38c3e 2970 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2971 goto out;
2972 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2973 goto out;
2974 r = 0;
2975 vcpu->arch.mcg_cap = mcg_cap;
2976 /* Init IA32_MCG_CTL to all 1s */
2977 if (mcg_cap & MCG_CTL_P)
2978 vcpu->arch.mcg_ctl = ~(u64)0;
2979 /* Init IA32_MCi_CTL to all 1s */
2980 for (bank = 0; bank < bank_num; bank++)
2981 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2982out:
2983 return r;
2984}
2985
2986static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2987 struct kvm_x86_mce *mce)
2988{
2989 u64 mcg_cap = vcpu->arch.mcg_cap;
2990 unsigned bank_num = mcg_cap & 0xff;
2991 u64 *banks = vcpu->arch.mce_banks;
2992
2993 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2994 return -EINVAL;
2995 /*
2996 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2997 * reporting is disabled
2998 */
2999 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3000 vcpu->arch.mcg_ctl != ~(u64)0)
3001 return 0;
3002 banks += 4 * mce->bank;
3003 /*
3004 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3005 * reporting is disabled for the bank
3006 */
3007 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3008 return 0;
3009 if (mce->status & MCI_STATUS_UC) {
3010 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3011 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3012 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3013 return 0;
3014 }
3015 if (banks[1] & MCI_STATUS_VAL)
3016 mce->status |= MCI_STATUS_OVER;
3017 banks[2] = mce->addr;
3018 banks[3] = mce->misc;
3019 vcpu->arch.mcg_status = mce->mcg_status;
3020 banks[1] = mce->status;
3021 kvm_queue_exception(vcpu, MC_VECTOR);
3022 } else if (!(banks[1] & MCI_STATUS_VAL)
3023 || !(banks[1] & MCI_STATUS_UC)) {
3024 if (banks[1] & MCI_STATUS_VAL)
3025 mce->status |= MCI_STATUS_OVER;
3026 banks[2] = mce->addr;
3027 banks[3] = mce->misc;
3028 banks[1] = mce->status;
3029 } else
3030 banks[1] |= MCI_STATUS_OVER;
3031 return 0;
3032}
3033
3cfc3092
JK		 3034static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3035 struct kvm_vcpu_events *events)
3036{
7460fb4a 3037 process_nmi(vcpu);
03b82a30
JK		 3038 events->exception.injected =
3039 vcpu->arch.exception.pending &&
3040 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3041 events->exception.nr = vcpu->arch.exception.nr;
3042 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3043 events->exception.pad = 0;
3cfc3092
JK		 3044 events->exception.error_code = vcpu->arch.exception.error_code;
3045
03b82a30
JK		 3046 events->interrupt.injected =
3047 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3048 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3049 events->interrupt.soft = 0;
37ccdcbe 3050 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3051
3052 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3053 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3054 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3055 events->nmi.pad = 0;
3cfc3092 3056
66450a21 3057 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3058
dab4b911 3059 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3060 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3061 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3062}
3063
3064static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3065 struct kvm_vcpu_events *events)
3066{
dab4b911 3067 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3068 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3069 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3070 return -EINVAL;
3071
7460fb4a 3072 process_nmi(vcpu);
3cfc3092
JK		 3073 vcpu->arch.exception.pending = events->exception.injected;
3074 vcpu->arch.exception.nr = events->exception.nr;
3075 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3076 vcpu->arch.exception.error_code = events->exception.error_code;
3077
3078 vcpu->arch.interrupt.pending = events->interrupt.injected;
3079 vcpu->arch.interrupt.nr = events->interrupt.nr;
3080 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3081 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3082 kvm_x86_ops->set_interrupt_shadow(vcpu,
3083 events->interrupt.shadow);
3cfc3092
JK		 3084
3085 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3086 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3087 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3088 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3089
66450a21
JK		 3090 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3091 kvm_vcpu_has_lapic(vcpu))
3092 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3093
3842d135
AK		 3094 kvm_make_request(KVM_REQ_EVENT, vcpu);
3095
3cfc3092
JK		 3096 return 0;
3097}
3098
a1efbe77
JK		 3099static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3100 struct kvm_debugregs *dbgregs)
3101{
73aaf249
JK		 3102 unsigned long val;
3103
a1efbe77 3104 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3105 kvm_get_dr(vcpu, 6, &val);
73aaf249 3106 dbgregs->dr6 = val;
a1efbe77
JK		 3107 dbgregs->dr7 = vcpu->arch.dr7;
3108 dbgregs->flags = 0;
97e69aa6 3109 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3110}
3111
3112static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3113 struct kvm_debugregs *dbgregs)
3114{
3115 if (dbgregs->flags)
3116 return -EINVAL;
3117
a1efbe77
JK		 3118 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3119 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3120 kvm_update_dr6(vcpu);
a1efbe77 3121 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3122 kvm_update_dr7(vcpu);
a1efbe77 3123
a1efbe77
JK		 3124 return 0;
3125}
3126
2d5b5a66
SY		 3127static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3128 struct kvm_xsave *guest_xsave)
3129{
4344ee98 3130 if (cpu_has_xsave) {
2d5b5a66
SY		 3131 memcpy(guest_xsave->region,
3132 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3133 vcpu->arch.guest_xstate_size);
3134 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3135 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3136 } else {
2d5b5a66
SY		 3137 memcpy(guest_xsave->region,
3138 &vcpu->arch.guest_fpu.state->fxsave,
3139 sizeof(struct i387_fxsave_struct));
3140 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3141 XSTATE_FPSSE;
3142 }
3143}
3144
3145static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3146 struct kvm_xsave *guest_xsave)
3147{
3148 u64 xstate_bv =
3149 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3150
d7876f1b
PB		 3151 if (cpu_has_xsave) {
3152 /*
3153 * Here we allow setting states that are not present in
3154 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3155 * with old userspace.
3156 */
4ff41732 3157 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3158 return -EINVAL;
2d5b5a66 3159 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3160 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3161 } else {
2d5b5a66
SY		 3162 if (xstate_bv & ~XSTATE_FPSSE)
3163 return -EINVAL;
3164 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3165 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3166 }
3167 return 0;
3168}
3169
3170static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3171 struct kvm_xcrs *guest_xcrs)
3172{
3173 if (!cpu_has_xsave) {
3174 guest_xcrs->nr_xcrs = 0;
3175 return;
3176 }
3177
3178 guest_xcrs->nr_xcrs = 1;
3179 guest_xcrs->flags = 0;
3180 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3181 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3182}
3183
3184static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3185 struct kvm_xcrs *guest_xcrs)
3186{
3187 int i, r = 0;
3188
3189 if (!cpu_has_xsave)
3190 return -EINVAL;
3191
3192 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3193 return -EINVAL;
3194
3195 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3196 /* Only support XCR0 currently */
c67a04cb 3197 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3198 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3199 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3200 break;
3201 }
3202 if (r)
3203 r = -EINVAL;
3204 return r;
3205}
3206
1c0b28c2
EM		 3207/*
3208 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3209 * stopped by the hypervisor. This function will be called from the host only.
3210 * EINVAL is returned when the host attempts to set the flag for a guest that
3211 * does not support pv clocks.
3212 */
3213static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3214{
0b79459b 3215 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3216 return -EINVAL;
51d59c6b 3217 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3218 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3219 return 0;
3220}
3221
313a3dc7
CO		 3222long kvm_arch_vcpu_ioctl(struct file *filp,
3223 unsigned int ioctl, unsigned long arg)
3224{
3225 struct kvm_vcpu *vcpu = filp->private_data;
3226 void __user *argp = (void __user *)arg;
3227 int r;
d1ac91d8
AK		 3228 union {
3229 struct kvm_lapic_state *lapic;
3230 struct kvm_xsave *xsave;
3231 struct kvm_xcrs *xcrs;
3232 void *buffer;
3233 } u;
3234
3235 u.buffer = NULL;
313a3dc7
CO		 3236 switch (ioctl) {
3237 case KVM_GET_LAPIC: {
2204ae3c
MT		 3238 r = -EINVAL;
3239 if (!vcpu->arch.apic)
3240 goto out;
d1ac91d8 3241 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3242
b772ff36 3243 r = -ENOMEM;
d1ac91d8 3244 if (!u.lapic)
b772ff36 3245 goto out;
d1ac91d8 3246 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3247 if (r)
3248 goto out;
3249 r = -EFAULT;
d1ac91d8 3250 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3251 goto out;
3252 r = 0;
3253 break;
3254 }
3255 case KVM_SET_LAPIC: {
2204ae3c
MT		 3256 r = -EINVAL;
3257 if (!vcpu->arch.apic)
3258 goto out;
ff5c2c03 3259 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3260 if (IS_ERR(u.lapic))
3261 return PTR_ERR(u.lapic);
ff5c2c03 3262
d1ac91d8 3263 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3264 break;
3265 }
f77bc6a4
ZX		 3266 case KVM_INTERRUPT: {
3267 struct kvm_interrupt irq;
3268
3269 r = -EFAULT;
3270 if (copy_from_user(&irq, argp, sizeof irq))
3271 goto out;
3272 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3273 break;
3274 }
c4abb7c9
JK		 3275 case KVM_NMI: {
3276 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3277 break;
3278 }
313a3dc7
CO		 3279 case KVM_SET_CPUID: {
3280 struct kvm_cpuid __user *cpuid_arg = argp;
3281 struct kvm_cpuid cpuid;
3282
3283 r = -EFAULT;
3284 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3285 goto out;
3286 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3287 break;
3288 }
07716717
DK		 3289 case KVM_SET_CPUID2: {
3290 struct kvm_cpuid2 __user *cpuid_arg = argp;
3291 struct kvm_cpuid2 cpuid;
3292
3293 r = -EFAULT;
3294 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3295 goto out;
3296 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3297 cpuid_arg->entries);
07716717
DK		 3298 break;
3299 }
3300 case KVM_GET_CPUID2: {
3301 struct kvm_cpuid2 __user *cpuid_arg = argp;
3302 struct kvm_cpuid2 cpuid;
3303
3304 r = -EFAULT;
3305 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3306 goto out;
3307 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3308 cpuid_arg->entries);
07716717
DK		 3309 if (r)
3310 goto out;
3311 r = -EFAULT;
3312 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3313 goto out;
3314 r = 0;
3315 break;
3316 }
313a3dc7
CO		 3317 case KVM_GET_MSRS:
3318 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3319 break;
3320 case KVM_SET_MSRS:
3321 r = msr_io(vcpu, argp, do_set_msr, 0);
3322 break;
b209749f
AK		 3323 case KVM_TPR_ACCESS_REPORTING: {
3324 struct kvm_tpr_access_ctl tac;
3325
3326 r = -EFAULT;
3327 if (copy_from_user(&tac, argp, sizeof tac))
3328 goto out;
3329 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3330 if (r)
3331 goto out;
3332 r = -EFAULT;
3333 if (copy_to_user(argp, &tac, sizeof tac))
3334 goto out;
3335 r = 0;
3336 break;
3337 };
b93463aa
AK		 3338 case KVM_SET_VAPIC_ADDR: {
3339 struct kvm_vapic_addr va;
3340
3341 r = -EINVAL;
3342 if (!irqchip_in_kernel(vcpu->kvm))
3343 goto out;
3344 r = -EFAULT;
3345 if (copy_from_user(&va, argp, sizeof va))
3346 goto out;
fda4e2e8 3347 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3348 break;
3349 }
890ca9ae
HY		 3350 case KVM_X86_SETUP_MCE: {
3351 u64 mcg_cap;
3352
3353 r = -EFAULT;
3354 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3355 goto out;
3356 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3357 break;
3358 }
3359 case KVM_X86_SET_MCE: {
3360 struct kvm_x86_mce mce;
3361
3362 r = -EFAULT;
3363 if (copy_from_user(&mce, argp, sizeof mce))
3364 goto out;
3365 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3366 break;
3367 }
3cfc3092
JK		 3368 case KVM_GET_VCPU_EVENTS: {
3369 struct kvm_vcpu_events events;
3370
3371 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3372
3373 r = -EFAULT;
3374 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3375 break;
3376 r = 0;
3377 break;
3378 }
3379 case KVM_SET_VCPU_EVENTS: {
3380 struct kvm_vcpu_events events;
3381
3382 r = -EFAULT;
3383 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3384 break;
3385
3386 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3387 break;
3388 }
a1efbe77
JK		 3389 case KVM_GET_DEBUGREGS: {
3390 struct kvm_debugregs dbgregs;
3391
3392 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3393
3394 r = -EFAULT;
3395 if (copy_to_user(argp, &dbgregs,
3396 sizeof(struct kvm_debugregs)))
3397 break;
3398 r = 0;
3399 break;
3400 }
3401 case KVM_SET_DEBUGREGS: {
3402 struct kvm_debugregs dbgregs;
3403
3404 r = -EFAULT;
3405 if (copy_from_user(&dbgregs, argp,
3406 sizeof(struct kvm_debugregs)))
3407 break;
3408
3409 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3410 break;
3411 }
2d5b5a66 3412 case KVM_GET_XSAVE: {
d1ac91d8 3413 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3414 r = -ENOMEM;
d1ac91d8 3415 if (!u.xsave)
2d5b5a66
SY		 3416 break;
3417
d1ac91d8 3418 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3419
3420 r = -EFAULT;
d1ac91d8 3421 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3422 break;
3423 r = 0;
3424 break;
3425 }
3426 case KVM_SET_XSAVE: {
ff5c2c03 3427 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3428 if (IS_ERR(u.xsave))
3429 return PTR_ERR(u.xsave);
2d5b5a66 3430
d1ac91d8 3431 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3432 break;
3433 }
3434 case KVM_GET_XCRS: {
d1ac91d8 3435 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3436 r = -ENOMEM;
d1ac91d8 3437 if (!u.xcrs)
2d5b5a66
SY		 3438 break;
3439
d1ac91d8 3440 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3441
3442 r = -EFAULT;
d1ac91d8 3443 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3444 sizeof(struct kvm_xcrs)))
3445 break;
3446 r = 0;
3447 break;
3448 }
3449 case KVM_SET_XCRS: {
ff5c2c03 3450 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3451 if (IS_ERR(u.xcrs))
3452 return PTR_ERR(u.xcrs);
2d5b5a66 3453
d1ac91d8 3454 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3455 break;
3456 }
92a1f12d
JR		 3457 case KVM_SET_TSC_KHZ: {
3458 u32 user_tsc_khz;
3459
3460 r = -EINVAL;
92a1f12d
JR		 3461 user_tsc_khz = (u32)arg;
3462
3463 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3464 goto out;
3465
cc578287
ZA		 3466 if (user_tsc_khz == 0)
3467 user_tsc_khz = tsc_khz;
3468
3469 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3470
3471 r = 0;
3472 goto out;
3473 }
3474 case KVM_GET_TSC_KHZ: {
cc578287 3475 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3476 goto out;
3477 }
1c0b28c2
EM		 3478 case KVM_KVMCLOCK_CTRL: {
3479 r = kvm_set_guest_paused(vcpu);
3480 goto out;
3481 }
313a3dc7
CO		 3482 default:
3483 r = -EINVAL;
3484 }
3485out:
d1ac91d8 3486 kfree(u.buffer);
313a3dc7
CO		 3487 return r;
3488}
3489
5b1c1493
CO		 3490int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3491{
3492 return VM_FAULT_SIGBUS;
3493}
3494
1fe779f8
CO		 3495static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3496{
3497 int ret;
3498
3499 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3500 return -EINVAL;
1fe779f8
CO		 3501 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3502 return ret;
3503}
3504
b927a3ce
SY		 3505static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3506 u64 ident_addr)
3507{
3508 kvm->arch.ept_identity_map_addr = ident_addr;
3509 return 0;
3510}
3511
1fe779f8
CO		 3512static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3513 u32 kvm_nr_mmu_pages)
3514{
3515 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3516 return -EINVAL;
3517
79fac95e 3518 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3519
3520 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3521 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3522
79fac95e 3523 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3524 return 0;
3525}
3526
3527static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3528{
39de71ec 3529 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3530}
3531
1fe779f8
CO		 3532static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3533{
3534 int r;
3535
3536 r = 0;
3537 switch (chip->chip_id) {
3538 case KVM_IRQCHIP_PIC_MASTER:
3539 memcpy(&chip->chip.pic,
3540 &pic_irqchip(kvm)->pics[0],
3541 sizeof(struct kvm_pic_state));
3542 break;
3543 case KVM_IRQCHIP_PIC_SLAVE:
3544 memcpy(&chip->chip.pic,
3545 &pic_irqchip(kvm)->pics[1],
3546 sizeof(struct kvm_pic_state));
3547 break;
3548 case KVM_IRQCHIP_IOAPIC:
eba0226b 3549 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3550 break;
3551 default:
3552 r = -EINVAL;
3553 break;
3554 }
3555 return r;
3556}
3557
3558static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3559{
3560 int r;
3561
3562 r = 0;
3563 switch (chip->chip_id) {
3564 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3565 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3566 memcpy(&pic_irqchip(kvm)->pics[0],
3567 &chip->chip.pic,
3568 sizeof(struct kvm_pic_state));
f4f51050 3569 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3570 break;
3571 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3572 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3573 memcpy(&pic_irqchip(kvm)->pics[1],
3574 &chip->chip.pic,
3575 sizeof(struct kvm_pic_state));
f4f51050 3576 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3577 break;
3578 case KVM_IRQCHIP_IOAPIC:
eba0226b 3579 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3580 break;
3581 default:
3582 r = -EINVAL;
3583 break;
3584 }
3585 kvm_pic_update_irq(pic_irqchip(kvm));
3586 return r;
3587}
3588
e0f63cb9
SY		 3589static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3590{
3591 int r = 0;
3592
894a9c55 3593 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3594 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3595 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3596 return r;
3597}
3598
3599static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3600{
3601 int r = 0;
3602
894a9c55 3603 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3604 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3605 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3606 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3607 return r;
3608}
3609
3610static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3611{
3612 int r = 0;
3613
3614 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3615 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3616 sizeof(ps->channels));
3617 ps->flags = kvm->arch.vpit->pit_state.flags;
3618 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3619 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3620 return r;
3621}
3622
3623static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3624{
3625 int r = 0, start = 0;
3626 u32 prev_legacy, cur_legacy;
3627 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3628 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3629 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3630 if (!prev_legacy && cur_legacy)
3631 start = 1;
3632 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3633 sizeof(kvm->arch.vpit->pit_state.channels));
3634 kvm->arch.vpit->pit_state.flags = ps->flags;
3635 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3636 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3637 return r;
3638}
3639
52d939a0
MT		 3640static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3641 struct kvm_reinject_control *control)
3642{
3643 if (!kvm->arch.vpit)
3644 return -ENXIO;
894a9c55 3645 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3646 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3647 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3648 return 0;
3649}
3650
95d4c16c 3651/**
60c34612
TY		 3652 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3653 * @kvm: kvm instance
3654 * @log: slot id and address to which we copy the log
95d4c16c 3655 *
60c34612
TY		 3656 * We need to keep it in mind that VCPU threads can write to the bitmap
3657 * concurrently. So, to avoid losing data, we keep the following order for
3658 * each bit:
95d4c16c 3659 *
60c34612
TY		 3660 * 1. Take a snapshot of the bit and clear it if needed.
3661 * 2. Write protect the corresponding page.
3662 * 3. Flush TLB's if needed.
3663 * 4. Copy the snapshot to the userspace.
95d4c16c 3664 *
60c34612
TY		 3665 * Between 2 and 3, the guest may write to the page using the remaining TLB
3666 * entry. This is not a problem because the page will be reported dirty at
3667 * step 4 using the snapshot taken before and step 3 ensures that successive
3668 * writes will be logged for the next call.
5bb064dc 3669 */
60c34612 3670int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3671{
7850ac54 3672 int r;
5bb064dc 3673 struct kvm_memory_slot *memslot;
60c34612
TY		 3674 unsigned long n, i;
3675 unsigned long *dirty_bitmap;
3676 unsigned long *dirty_bitmap_buffer;
3677 bool is_dirty = false;
5bb064dc 3678
79fac95e 3679 mutex_lock(&kvm->slots_lock);
5bb064dc 3680
b050b015 3681 r = -EINVAL;
bbacc0c1 3682 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3683 goto out;
3684
28a37544 3685 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3686
3687 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3688 r = -ENOENT;
60c34612 3689 if (!dirty_bitmap)
b050b015
MT		 3690 goto out;
3691
87bf6e7d 3692 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3693
60c34612
TY		 3694 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3695 memset(dirty_bitmap_buffer, 0, n);
b050b015 3696
60c34612 3697 spin_lock(&kvm->mmu_lock);
b050b015 3698
60c34612
TY		 3699 for (i = 0; i < n / sizeof(long); i++) {
3700 unsigned long mask;
3701 gfn_t offset;
cdfca7b3 3702
60c34612
TY		 3703 if (!dirty_bitmap[i])
3704 continue;
b050b015 3705
60c34612 3706 is_dirty = true;
914ebccd 3707
60c34612
TY		 3708 mask = xchg(&dirty_bitmap[i], 0);
3709 dirty_bitmap_buffer[i] = mask;
edde99ce 3710
60c34612
TY		 3711 offset = i * BITS_PER_LONG;
3712 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3713 }
60c34612
TY		 3714
3715 spin_unlock(&kvm->mmu_lock);
3716
198c74f4
XG		 3717 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3718 lockdep_assert_held(&kvm->slots_lock);
3719
3720 /*
3721 * All the TLBs can be flushed out of mmu lock, see the comments in
3722 * kvm_mmu_slot_remove_write_access().
3723 */
3724 if (is_dirty)
3725 kvm_flush_remote_tlbs(kvm);
3726
60c34612
TY		 3727 r = -EFAULT;
3728 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3729 goto out;
b050b015 3730
5bb064dc
ZX		 3731 r = 0;
3732out:
79fac95e 3733 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3734 return r;
3735}
3736
aa2fbe6d
YZ		 3737int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3738 bool line_status)
23d43cf9
CD		 3739{
3740 if (!irqchip_in_kernel(kvm))
3741 return -ENXIO;
3742
3743 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3744 irq_event->irq, irq_event->level,
3745 line_status);
23d43cf9
CD		 3746 return 0;
3747}
3748
1fe779f8
CO		 3749long kvm_arch_vm_ioctl(struct file *filp,
3750 unsigned int ioctl, unsigned long arg)
3751{
3752 struct kvm *kvm = filp->private_data;
3753 void __user *argp = (void __user *)arg;
367e1319 3754 int r = -ENOTTY;
f0d66275
DH		 3755 /*
3756 * This union makes it completely explicit to gcc-3.x
3757 * that these two variables' stack usage should be
3758 * combined, not added together.
3759 */
3760 union {
3761 struct kvm_pit_state ps;
e9f42757 3762 struct kvm_pit_state2 ps2;
c5ff41ce 3763 struct kvm_pit_config pit_config;
f0d66275 3764 } u;
1fe779f8
CO		 3765
3766 switch (ioctl) {
3767 case KVM_SET_TSS_ADDR:
3768 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3769 break;
b927a3ce
SY		 3770 case KVM_SET_IDENTITY_MAP_ADDR: {
3771 u64 ident_addr;
3772
3773 r = -EFAULT;
3774 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3775 goto out;
3776 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3777 break;
3778 }
1fe779f8
CO		 3779 case KVM_SET_NR_MMU_PAGES:
3780 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3781 break;
3782 case KVM_GET_NR_MMU_PAGES:
3783 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3784 break;
3ddea128
MT		 3785 case KVM_CREATE_IRQCHIP: {
3786 struct kvm_pic *vpic;
3787
3788 mutex_lock(&kvm->lock);
3789 r = -EEXIST;
3790 if (kvm->arch.vpic)
3791 goto create_irqchip_unlock;
3e515705
AK		 3792 r = -EINVAL;
3793 if (atomic_read(&kvm->online_vcpus))
3794 goto create_irqchip_unlock;
1fe779f8 3795 r = -ENOMEM;
3ddea128
MT		 3796 vpic = kvm_create_pic(kvm);
3797 if (vpic) {
1fe779f8
CO		 3798 r = kvm_ioapic_init(kvm);
3799 if (r) {
175504cd 3800 mutex_lock(&kvm->slots_lock);
72bb2fcd 3801 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3802 &vpic->dev_master);
3803 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3804 &vpic->dev_slave);
3805 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3806 &vpic->dev_eclr);
175504cd 3807 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3808 kfree(vpic);
3809 goto create_irqchip_unlock;
1fe779f8
CO		 3810 }
3811 } else
3ddea128
MT		 3812 goto create_irqchip_unlock;
3813 smp_wmb();
3814 kvm->arch.vpic = vpic;
3815 smp_wmb();
399ec807
AK		 3816 r = kvm_setup_default_irq_routing(kvm);
3817 if (r) {
175504cd 3818 mutex_lock(&kvm->slots_lock);
3ddea128 3819 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3820 kvm_ioapic_destroy(kvm);
3821 kvm_destroy_pic(kvm);
3ddea128 3822 mutex_unlock(&kvm->irq_lock);
175504cd 3823 mutex_unlock(&kvm->slots_lock);
399ec807 3824 }
3ddea128
MT		 3825 create_irqchip_unlock:
3826 mutex_unlock(&kvm->lock);
1fe779f8 3827 break;
3ddea128 3828 }
7837699f 3829 case KVM_CREATE_PIT:
c5ff41ce
JK		 3830 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3831 goto create_pit;
3832 case KVM_CREATE_PIT2:
3833 r = -EFAULT;
3834 if (copy_from_user(&u.pit_config, argp,
3835 sizeof(struct kvm_pit_config)))
3836 goto out;
3837 create_pit:
79fac95e 3838 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3839 r = -EEXIST;
3840 if (kvm->arch.vpit)
3841 goto create_pit_unlock;
7837699f 3842 r = -ENOMEM;
c5ff41ce 3843 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3844 if (kvm->arch.vpit)
3845 r = 0;
269e05e4 3846 create_pit_unlock:
79fac95e 3847 mutex_unlock(&kvm->slots_lock);
7837699f 3848 break;
1fe779f8
CO		 3849 case KVM_GET_IRQCHIP: {
3850 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3851 struct kvm_irqchip *chip;
1fe779f8 3852
ff5c2c03
SL		 3853 chip = memdup_user(argp, sizeof(*chip));
3854 if (IS_ERR(chip)) {
3855 r = PTR_ERR(chip);
1fe779f8 3856 goto out;
ff5c2c03
SL		 3857 }
3858
1fe779f8
CO		 3859 r = -ENXIO;
3860 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3861 goto get_irqchip_out;
3862 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3863 if (r)
f0d66275 3864 goto get_irqchip_out;
1fe779f8 3865 r = -EFAULT;
f0d66275
DH		 3866 if (copy_to_user(argp, chip, sizeof *chip))
3867 goto get_irqchip_out;
1fe779f8 3868 r = 0;
f0d66275
DH		 3869 get_irqchip_out:
3870 kfree(chip);
1fe779f8
CO		 3871 break;
3872 }
3873 case KVM_SET_IRQCHIP: {
3874 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3875 struct kvm_irqchip *chip;
1fe779f8 3876
ff5c2c03
SL		 3877 chip = memdup_user(argp, sizeof(*chip));
3878 if (IS_ERR(chip)) {
3879 r = PTR_ERR(chip);
1fe779f8 3880 goto out;
ff5c2c03
SL		 3881 }
3882
1fe779f8
CO		 3883 r = -ENXIO;
3884 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3885 goto set_irqchip_out;
3886 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3887 if (r)
f0d66275 3888 goto set_irqchip_out;
1fe779f8 3889 r = 0;
f0d66275
DH		 3890 set_irqchip_out:
3891 kfree(chip);
1fe779f8
CO		 3892 break;
3893 }
e0f63cb9 3894 case KVM_GET_PIT: {
e0f63cb9 3895 r = -EFAULT;
f0d66275 3896 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3897 goto out;
3898 r = -ENXIO;
3899 if (!kvm->arch.vpit)
3900 goto out;
f0d66275 3901 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3902 if (r)
3903 goto out;
3904 r = -EFAULT;
f0d66275 3905 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3906 goto out;
3907 r = 0;
3908 break;
3909 }
3910 case KVM_SET_PIT: {
e0f63cb9 3911 r = -EFAULT;
f0d66275 3912 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3913 goto out;
3914 r = -ENXIO;
3915 if (!kvm->arch.vpit)
3916 goto out;
f0d66275 3917 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3918 break;
3919 }
e9f42757
BK		 3920 case KVM_GET_PIT2: {
3921 r = -ENXIO;
3922 if (!kvm->arch.vpit)
3923 goto out;
3924 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3925 if (r)
3926 goto out;
3927 r = -EFAULT;
3928 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3929 goto out;
3930 r = 0;
3931 break;
3932 }
3933 case KVM_SET_PIT2: {
3934 r = -EFAULT;
3935 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3936 goto out;
3937 r = -ENXIO;
3938 if (!kvm->arch.vpit)
3939 goto out;
3940 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3941 break;
3942 }
52d939a0
MT		 3943 case KVM_REINJECT_CONTROL: {
3944 struct kvm_reinject_control control;
3945 r = -EFAULT;
3946 if (copy_from_user(&control, argp, sizeof(control)))
3947 goto out;
3948 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3949 break;
3950 }
ffde22ac
ES		 3951 case KVM_XEN_HVM_CONFIG: {
3952 r = -EFAULT;
3953 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3954 sizeof(struct kvm_xen_hvm_config)))
3955 goto out;
3956 r = -EINVAL;
3957 if (kvm->arch.xen_hvm_config.flags)
3958 goto out;
3959 r = 0;
3960 break;
3961 }
afbcf7ab 3962 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3963 struct kvm_clock_data user_ns;
3964 u64 now_ns;
3965 s64 delta;
3966
3967 r = -EFAULT;
3968 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3969 goto out;
3970
3971 r = -EINVAL;
3972 if (user_ns.flags)
3973 goto out;
3974
3975 r = 0;
395c6b0a 3976 local_irq_disable();
759379dd 3977 now_ns = get_kernel_ns();
afbcf7ab 3978 delta = user_ns.clock - now_ns;
395c6b0a 3979 local_irq_enable();
afbcf7ab 3980 kvm->arch.kvmclock_offset = delta;
2e762ff7 3981 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3982 break;
3983 }
3984 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3985 struct kvm_clock_data user_ns;
3986 u64 now_ns;
3987
395c6b0a 3988 local_irq_disable();
759379dd 3989 now_ns = get_kernel_ns();
afbcf7ab 3990 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3991 local_irq_enable();
afbcf7ab 3992 user_ns.flags = 0;
97e69aa6 3993 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3994
3995 r = -EFAULT;
3996 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3997 goto out;
3998 r = 0;
3999 break;
4000 }
4001
1fe779f8
CO		 4002 default:
4003 ;
4004 }
4005out:
4006 return r;
4007}
4008
a16b043c 4009static void kvm_init_msr_list(void)
043405e1
CO		 4010{
4011 u32 dummy[2];
4012 unsigned i, j;
4013
e3267cbb
GC		 4014 /* skip the first msrs in the list. KVM-specific */
4015 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4016 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4017 continue;
93c4adc7
PB		 4018
4019 /*
4020 * Even MSRs that are valid in the host may not be exposed
4021 * to the guests in some cases. We could work around this
4022 * in VMX with the generic MSR save/load machinery, but it
4023 * is not really worthwhile since it will really only
4024 * happen with nested virtualization.
4025 */
4026 switch (msrs_to_save[i]) {
4027 case MSR_IA32_BNDCFGS:
4028 if (!kvm_x86_ops->mpx_supported())
4029 continue;
4030 break;
4031 default:
4032 break;
4033 }
4034
043405e1
CO		 4035 if (j < i)
4036 msrs_to_save[j] = msrs_to_save[i];
4037 j++;
4038 }
4039 num_msrs_to_save = j;
4040}
4041
bda9020e
MT		 4042static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4043 const void *v)
bbd9b64e 4044{
70252a10
AK		 4045 int handled = 0;
4046 int n;
4047
4048 do {
4049 n = min(len, 8);
4050 if (!(vcpu->arch.apic &&
4051 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4052 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4053 break;
4054 handled += n;
4055 addr += n;
4056 len -= n;
4057 v += n;
4058 } while (len);
bbd9b64e 4059
70252a10 4060 return handled;
bbd9b64e
CO		 4061}
4062
bda9020e 4063static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4064{
70252a10
AK		 4065 int handled = 0;
4066 int n;
4067
4068 do {
4069 n = min(len, 8);
4070 if (!(vcpu->arch.apic &&
4071 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4072 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4073 break;
4074 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4075 handled += n;
4076 addr += n;
4077 len -= n;
4078 v += n;
4079 } while (len);
bbd9b64e 4080
70252a10 4081 return handled;
bbd9b64e
CO		 4082}
4083
2dafc6c2
GN		 4084static void kvm_set_segment(struct kvm_vcpu *vcpu,
4085 struct kvm_segment *var, int seg)
4086{
4087 kvm_x86_ops->set_segment(vcpu, var, seg);
4088}
4089
4090void kvm_get_segment(struct kvm_vcpu *vcpu,
4091 struct kvm_segment *var, int seg)
4092{
4093 kvm_x86_ops->get_segment(vcpu, var, seg);
4094}
4095
54987b7a
PB		 4096gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4097 struct x86_exception *exception)
02f59dc9
JR		 4098{
4099 gpa_t t_gpa;
02f59dc9
JR		 4100
4101 BUG_ON(!mmu_is_nested(vcpu));
4102
4103 /* NPT walks are always user-walks */
4104 access |= PFERR_USER_MASK;
54987b7a 4105 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4106
4107 return t_gpa;
4108}
4109
ab9ae313
AK		 4110gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4111 struct x86_exception *exception)
1871c602
GN		 4112{
4113 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4114 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4115}
4116
ab9ae313
AK		 4117 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4118 struct x86_exception *exception)
1871c602
GN		 4119{
4120 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4121 access |= PFERR_FETCH_MASK;
ab9ae313 4122 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4123}
4124
ab9ae313
AK		 4125gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4126 struct x86_exception *exception)
1871c602
GN		 4127{
4128 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4129 access |= PFERR_WRITE_MASK;
ab9ae313 4130 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4131}
4132
4133/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4134gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4135 struct x86_exception *exception)
1871c602 4136{
ab9ae313 4137 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4138}
4139
4140static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4141 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4142 struct x86_exception *exception)
bbd9b64e
CO		 4143{
4144 void *data = val;
10589a46 4145 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4146
4147 while (bytes) {
14dfe855 4148 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4149 exception);
bbd9b64e 4150 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4151 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4152 int ret;
4153
bcc55cba 4154 if (gpa == UNMAPPED_GVA)
ab9ae313 4155 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4156 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4157 offset, toread);
10589a46 4158 if (ret < 0) {
c3cd7ffa 4159 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4160 goto out;
4161 }
bbd9b64e 4162
77c2002e
IE		 4163 bytes -= toread;
4164 data += toread;
4165 addr += toread;
bbd9b64e 4166 }
10589a46 4167out:
10589a46 4168 return r;
bbd9b64e 4169}
77c2002e 4170
1871c602 4171/* used for instruction fetching */
0f65dd70
AK		 4172static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4173 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4174 struct x86_exception *exception)
1871c602 4175{
0f65dd70 4176 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4177 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4178 unsigned offset;
4179 int ret;
0f65dd70 4180
44583cba
PB		 4181 /* Inline kvm_read_guest_virt_helper for speed. */
4182 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4183 exception);
4184 if (unlikely(gpa == UNMAPPED_GVA))
4185 return X86EMUL_PROPAGATE_FAULT;
4186
4187 offset = addr & (PAGE_SIZE-1);
4188 if (WARN_ON(offset + bytes > PAGE_SIZE))
4189 bytes = (unsigned)PAGE_SIZE - offset;
4190 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4191 offset, bytes);
4192 if (unlikely(ret < 0))
4193 return X86EMUL_IO_NEEDED;
4194
4195 return X86EMUL_CONTINUE;
1871c602
GN		 4196}
4197
064aea77 4198int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4199 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4200 struct x86_exception *exception)
1871c602 4201{
0f65dd70 4202 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4203 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4204
1871c602 4205 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4206 exception);
1871c602 4207}
064aea77 4208EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4209
0f65dd70
AK		 4210static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4211 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4212 struct x86_exception *exception)
1871c602 4213{
0f65dd70 4214 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4215 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4216}
4217
6a4d7550 4218int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4219 gva_t addr, void *val,
2dafc6c2 4220 unsigned int bytes,
bcc55cba 4221 struct x86_exception *exception)
77c2002e 4222{
0f65dd70 4223 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4224 void *data = val;
4225 int r = X86EMUL_CONTINUE;
4226
4227 while (bytes) {
14dfe855
JR		 4228 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4229 PFERR_WRITE_MASK,
ab9ae313 4230 exception);
77c2002e
IE		 4231 unsigned offset = addr & (PAGE_SIZE-1);
4232 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4233 int ret;
4234
bcc55cba 4235 if (gpa == UNMAPPED_GVA)
ab9ae313 4236 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4237 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4238 if (ret < 0) {
c3cd7ffa 4239 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4240 goto out;
4241 }
4242
4243 bytes -= towrite;
4244 data += towrite;
4245 addr += towrite;
4246 }
4247out:
4248 return r;
4249}
6a4d7550 4250EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4251
af7cc7d1
XG		 4252static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4253 gpa_t *gpa, struct x86_exception *exception,
4254 bool write)
4255{
97d64b78
AK		 4256 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4257 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4258
97d64b78 4259 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4260 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4261 vcpu->arch.access, access)) {
bebb106a
XG		 4262 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4263 (gva & (PAGE_SIZE - 1));
4f022648 4264 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4265 return 1;
4266 }
4267
af7cc7d1
XG		 4268 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4269
4270 if (*gpa == UNMAPPED_GVA)
4271 return -1;
4272
4273 /* For APIC access vmexit */
4274 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4275 return 1;
4276
4f022648
XG		 4277 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4278 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4279 return 1;
4f022648 4280 }
bebb106a 4281
af7cc7d1
XG		 4282 return 0;
4283}
4284
3200f405 4285int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4286 const void *val, int bytes)
bbd9b64e
CO		 4287{
4288 int ret;
4289
4290 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4291 if (ret < 0)
bbd9b64e 4292 return 0;
f57f2ef5 4293 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4294 return 1;
4295}
4296
77d197b2
XG		 4297struct read_write_emulator_ops {
4298 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4299 int bytes);
4300 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4301 void *val, int bytes);
4302 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4303 int bytes, void *val);
4304 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4305 void *val, int bytes);
4306 bool write;
4307};
4308
4309static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4310{
4311 if (vcpu->mmio_read_completed) {
77d197b2 4312 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4313 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4314 vcpu->mmio_read_completed = 0;
4315 return 1;
4316 }
4317
4318 return 0;
4319}
4320
4321static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4322 void *val, int bytes)
4323{
4324 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4325}
4326
4327static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4328 void *val, int bytes)
4329{
4330 return emulator_write_phys(vcpu, gpa, val, bytes);
4331}
4332
4333static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4334{
4335 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4336 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4337}
4338
4339static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4340 void *val, int bytes)
4341{
4342 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4343 return X86EMUL_IO_NEEDED;
4344}
4345
4346static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4347 void *val, int bytes)
4348{
f78146b0
AK		 4349 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4350
87da7e66 4351 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4352 return X86EMUL_CONTINUE;
4353}
4354
0fbe9b0b 4355static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4356 .read_write_prepare = read_prepare,
4357 .read_write_emulate = read_emulate,
4358 .read_write_mmio = vcpu_mmio_read,
4359 .read_write_exit_mmio = read_exit_mmio,
4360};
4361
0fbe9b0b 4362static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4363 .read_write_emulate = write_emulate,
4364 .read_write_mmio = write_mmio,
4365 .read_write_exit_mmio = write_exit_mmio,
4366 .write = true,
4367};
4368
22388a3c
XG		 4369static int emulator_read_write_onepage(unsigned long addr, void *val,
4370 unsigned int bytes,
4371 struct x86_exception *exception,
4372 struct kvm_vcpu *vcpu,
0fbe9b0b 4373 const struct read_write_emulator_ops *ops)
bbd9b64e 4374{
af7cc7d1
XG		 4375 gpa_t gpa;
4376 int handled, ret;
22388a3c 4377 bool write = ops->write;
f78146b0 4378 struct kvm_mmio_fragment *frag;
10589a46 4379
22388a3c 4380 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4381
af7cc7d1 4382 if (ret < 0)
bbd9b64e 4383 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4384
4385 /* For APIC access vmexit */
af7cc7d1 4386 if (ret)
bbd9b64e
CO		 4387 goto mmio;
4388
22388a3c 4389 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4390 return X86EMUL_CONTINUE;
4391
4392mmio:
4393 /*
4394 * Is this MMIO handled locally?
4395 */
22388a3c 4396 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4397 if (handled == bytes)
bbd9b64e 4398 return X86EMUL_CONTINUE;
bbd9b64e 4399
70252a10
AK		 4400 gpa += handled;
4401 bytes -= handled;
4402 val += handled;
4403
87da7e66
XG		 4404 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4405 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4406 frag->gpa = gpa;
4407 frag->data = val;
4408 frag->len = bytes;
f78146b0 4409 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4410}
4411
22388a3c
XG		 4412int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4413 void *val, unsigned int bytes,
4414 struct x86_exception *exception,
0fbe9b0b 4415 const struct read_write_emulator_ops *ops)
bbd9b64e 4416{
0f65dd70 4417 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4418 gpa_t gpa;
4419 int rc;
4420
4421 if (ops->read_write_prepare &&
4422 ops->read_write_prepare(vcpu, val, bytes))
4423 return X86EMUL_CONTINUE;
4424
4425 vcpu->mmio_nr_fragments = 0;
0f65dd70 4426
bbd9b64e
CO		 4427 /* Crossing a page boundary? */
4428 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4429 int now;
bbd9b64e
CO		 4430
4431 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4432 rc = emulator_read_write_onepage(addr, val, now, exception,
4433 vcpu, ops);
4434
bbd9b64e
CO		 4435 if (rc != X86EMUL_CONTINUE)
4436 return rc;
4437 addr += now;
4438 val += now;
4439 bytes -= now;
4440 }
22388a3c 4441
f78146b0
AK		 4442 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4443 vcpu, ops);
4444 if (rc != X86EMUL_CONTINUE)
4445 return rc;
4446
4447 if (!vcpu->mmio_nr_fragments)
4448 return rc;
4449
4450 gpa = vcpu->mmio_fragments[0].gpa;
4451
4452 vcpu->mmio_needed = 1;
4453 vcpu->mmio_cur_fragment = 0;
4454
87da7e66 4455 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4456 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4457 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4458 vcpu->run->mmio.phys_addr = gpa;
4459
4460 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4461}
4462
4463static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4464 unsigned long addr,
4465 void *val,
4466 unsigned int bytes,
4467 struct x86_exception *exception)
4468{
4469 return emulator_read_write(ctxt, addr, val, bytes,
4470 exception, &read_emultor);
4471}
4472
4473int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4474 unsigned long addr,
4475 const void *val,
4476 unsigned int bytes,
4477 struct x86_exception *exception)
4478{
4479 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4480 exception, &write_emultor);
bbd9b64e 4481}
bbd9b64e 4482
daea3e73
AK		 4483#define CMPXCHG_TYPE(t, ptr, old, new) \
4484 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4485
4486#ifdef CONFIG_X86_64
4487# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4488#else
4489# define CMPXCHG64(ptr, old, new) \
9749a6c0 4490 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4491#endif
4492
0f65dd70
AK		 4493static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4494 unsigned long addr,
bbd9b64e
CO		 4495 const void *old,
4496 const void *new,
4497 unsigned int bytes,
0f65dd70 4498 struct x86_exception *exception)
bbd9b64e 4499{
0f65dd70 4500 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4501 gpa_t gpa;
4502 struct page *page;
4503 char *kaddr;
4504 bool exchanged;
2bacc55c 4505
daea3e73
AK		 4506 /* guests cmpxchg8b have to be emulated atomically */
4507 if (bytes > 8 || (bytes & (bytes - 1)))
4508 goto emul_write;
10589a46 4509
daea3e73 4510 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4511
daea3e73
AK		 4512 if (gpa == UNMAPPED_GVA ||
4513 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4514 goto emul_write;
2bacc55c 4515
daea3e73
AK		 4516 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4517 goto emul_write;
72dc67a6 4518
daea3e73 4519 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4520 if (is_error_page(page))
c19b8bd6 4521 goto emul_write;
72dc67a6 4522
8fd75e12 4523 kaddr = kmap_atomic(page);
daea3e73
AK		 4524 kaddr += offset_in_page(gpa);
4525 switch (bytes) {
4526 case 1:
4527 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4528 break;
4529 case 2:
4530 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4531 break;
4532 case 4:
4533 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4534 break;
4535 case 8:
4536 exchanged = CMPXCHG64(kaddr, old, new);
4537 break;
4538 default:
4539 BUG();
2bacc55c 4540 }
8fd75e12 4541 kunmap_atomic(kaddr);
daea3e73
AK		 4542 kvm_release_page_dirty(page);
4543
4544 if (!exchanged)
4545 return X86EMUL_CMPXCHG_FAILED;
4546
d3714010 4547 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4548 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4549
4550 return X86EMUL_CONTINUE;
4a5f48f6 4551
3200f405 4552emul_write:
daea3e73 4553 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4554
0f65dd70 4555 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4556}
4557
cf8f70bf
GN		 4558static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4559{
4560 /* TODO: String I/O for in kernel device */
4561 int r;
4562
4563 if (vcpu->arch.pio.in)
4564 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4565 vcpu->arch.pio.size, pd);
4566 else
4567 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4568 vcpu->arch.pio.port, vcpu->arch.pio.size,
4569 pd);
4570 return r;
4571}
4572
6f6fbe98
XG		 4573static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4574 unsigned short port, void *val,
4575 unsigned int count, bool in)
cf8f70bf 4576{
cf8f70bf 4577 vcpu->arch.pio.port = port;
6f6fbe98 4578 vcpu->arch.pio.in = in;
7972995b 4579 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4580 vcpu->arch.pio.size = size;
4581
4582 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4583 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4584 return 1;
4585 }
4586
4587 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4588 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4589 vcpu->run->io.size = size;
4590 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4591 vcpu->run->io.count = count;
4592 vcpu->run->io.port = port;
4593
4594 return 0;
4595}
4596
6f6fbe98
XG		 4597static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4598 int size, unsigned short port, void *val,
4599 unsigned int count)
cf8f70bf 4600{
ca1d4a9e 4601 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4602 int ret;
ca1d4a9e 4603
6f6fbe98
XG		 4604 if (vcpu->arch.pio.count)
4605 goto data_avail;
cf8f70bf 4606
6f6fbe98
XG		 4607 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4608 if (ret) {
4609data_avail:
4610 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4611 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4612 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4613 return 1;
4614 }
4615
cf8f70bf
GN		 4616 return 0;
4617}
4618
6f6fbe98
XG		 4619static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4620 int size, unsigned short port,
4621 const void *val, unsigned int count)
4622{
4623 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4624
4625 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4626 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4627 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4628}
4629
bbd9b64e
CO		 4630static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4631{
4632 return kvm_x86_ops->get_segment_base(vcpu, seg);
4633}
4634
3cb16fe7 4635static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4636{
3cb16fe7 4637 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4638}
4639
f5f48ee1
SY		 4640int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4641{
4642 if (!need_emulate_wbinvd(vcpu))
4643 return X86EMUL_CONTINUE;
4644
4645 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4646 int cpu = get_cpu();
4647
4648 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4649 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4650 wbinvd_ipi, NULL, 1);
2eec7343 4651 put_cpu();
f5f48ee1 4652 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4653 } else
4654 wbinvd();
f5f48ee1
SY		 4655 return X86EMUL_CONTINUE;
4656}
4657EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4658
bcaf5cc5
AK		 4659static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4660{
4661 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4662}
4663
717746e3 4664int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4665{
16f8a6f9 4666 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4667}
4668
717746e3 4669int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4670{
338dbc97 4671
717746e3 4672 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4673}
4674
52a46617 4675static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4676{
52a46617 4677 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4678}
4679
717746e3 4680static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4681{
717746e3 4682 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4683 unsigned long value;
4684
4685 switch (cr) {
4686 case 0:
4687 value = kvm_read_cr0(vcpu);
4688 break;
4689 case 2:
4690 value = vcpu->arch.cr2;
4691 break;
4692 case 3:
9f8fe504 4693 value = kvm_read_cr3(vcpu);
52a46617
GN		 4694 break;
4695 case 4:
4696 value = kvm_read_cr4(vcpu);
4697 break;
4698 case 8:
4699 value = kvm_get_cr8(vcpu);
4700 break;
4701 default:
a737f256 4702 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4703 return 0;
4704 }
4705
4706 return value;
4707}
4708
717746e3 4709static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4710{
717746e3 4711 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4712 int res = 0;
4713
52a46617
GN		 4714 switch (cr) {
4715 case 0:
49a9b07e 4716 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4717 break;
4718 case 2:
4719 vcpu->arch.cr2 = val;
4720 break;
4721 case 3:
2390218b 4722 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4723 break;
4724 case 4:
a83b29c6 4725 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4726 break;
4727 case 8:
eea1cff9 4728 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4729 break;
4730 default:
a737f256 4731 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4732 res = -1;
52a46617 4733 }
0f12244f
GN		 4734
4735 return res;
52a46617
GN		 4736}
4737
717746e3 4738static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4739{
717746e3 4740 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4741}
4742
4bff1e86 4743static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4744{
4bff1e86 4745 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4746}
4747
4bff1e86 4748static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4749{
4bff1e86 4750 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4751}
4752
1ac9d0cf
AK		 4753static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4754{
4755 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4756}
4757
4758static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4759{
4760 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4761}
4762
4bff1e86
AK		 4763static unsigned long emulator_get_cached_segment_base(
4764 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4765{
4bff1e86 4766 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4767}
4768
1aa36616
AK		 4769static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4770 struct desc_struct *desc, u32 *base3,
4771 int seg)
2dafc6c2
GN		 4772{
4773 struct kvm_segment var;
4774
4bff1e86 4775 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4776 *selector = var.selector;
2dafc6c2 4777
378a8b09
GN		 4778 if (var.unusable) {
4779 memset(desc, 0, sizeof(*desc));
2dafc6c2 4780 return false;
378a8b09 4781 }
2dafc6c2
GN		 4782
4783 if (var.g)
4784 var.limit >>= 12;
4785 set_desc_limit(desc, var.limit);
4786 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4787#ifdef CONFIG_X86_64
4788 if (base3)
4789 *base3 = var.base >> 32;
4790#endif
2dafc6c2
GN		 4791 desc->type = var.type;
4792 desc->s = var.s;
4793 desc->dpl = var.dpl;
4794 desc->p = var.present;
4795 desc->avl = var.avl;
4796 desc->l = var.l;
4797 desc->d = var.db;
4798 desc->g = var.g;
4799
4800 return true;
4801}
4802
1aa36616
AK		 4803static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4804 struct desc_struct *desc, u32 base3,
4805 int seg)
2dafc6c2 4806{
4bff1e86 4807 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4808 struct kvm_segment var;
4809
1aa36616 4810 var.selector = selector;
2dafc6c2 4811 var.base = get_desc_base(desc);
5601d05b
GN		 4812#ifdef CONFIG_X86_64
4813 var.base |= ((u64)base3) << 32;
4814#endif
2dafc6c2
GN		 4815 var.limit = get_desc_limit(desc);
4816 if (desc->g)
4817 var.limit = (var.limit << 12) | 0xfff;
4818 var.type = desc->type;
2dafc6c2
GN		 4819 var.dpl = desc->dpl;
4820 var.db = desc->d;
4821 var.s = desc->s;
4822 var.l = desc->l;
4823 var.g = desc->g;
4824 var.avl = desc->avl;
4825 var.present = desc->p;
4826 var.unusable = !var.present;
4827 var.padding = 0;
4828
4829 kvm_set_segment(vcpu, &var, seg);
4830 return;
4831}
4832
717746e3
AK		 4833static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4834 u32 msr_index, u64 *pdata)
4835{
4836 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4837}
4838
4839static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4840 u32 msr_index, u64 data)
4841{
8fe8ab46
WA		 4842 struct msr_data msr;
4843
4844 msr.data = data;
4845 msr.index = msr_index;
4846 msr.host_initiated = false;
4847 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4848}
4849
67f4d428
NA		 4850static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4851 u32 pmc)
4852{
4853 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4854}
4855
222d21aa
AK		 4856static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4857 u32 pmc, u64 *pdata)
4858{
4859 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4860}
4861
6c3287f7
AK		 4862static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4863{
4864 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4865}
4866
5037f6f3
AK		 4867static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4868{
4869 preempt_disable();
5197b808 4870 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4871 /*
4872 * CR0.TS may reference the host fpu state, not the guest fpu state,
4873 * so it may be clear at this point.
4874 */
4875 clts();
4876}
4877
4878static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4879{
4880 preempt_enable();
4881}
4882
2953538e 4883static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4884 struct x86_instruction_info *info,
c4f035c6
AK		 4885 enum x86_intercept_stage stage)
4886{
2953538e 4887 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4888}
4889
0017f93a 4890static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4891 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4892{
0017f93a 4893 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4894}
4895
dd856efa
AK		 4896static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4897{
4898 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4899}
4900
4901static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4902{
4903 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4904}
4905
0225fb50 4906static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4907 .read_gpr = emulator_read_gpr,
4908 .write_gpr = emulator_write_gpr,
1871c602 4909 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4910 .write_std = kvm_write_guest_virt_system,
1871c602 4911 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4912 .read_emulated = emulator_read_emulated,
4913 .write_emulated = emulator_write_emulated,
4914 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4915 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4916 .pio_in_emulated = emulator_pio_in_emulated,
4917 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4918 .get_segment = emulator_get_segment,
4919 .set_segment = emulator_set_segment,
5951c442 4920 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4921 .get_gdt = emulator_get_gdt,
160ce1f1 4922 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4923 .set_gdt = emulator_set_gdt,
4924 .set_idt = emulator_set_idt,
52a46617
GN		 4925 .get_cr = emulator_get_cr,
4926 .set_cr = emulator_set_cr,
9c537244 4927 .cpl = emulator_get_cpl,
35aa5375
GN		 4928 .get_dr = emulator_get_dr,
4929 .set_dr = emulator_set_dr,
717746e3
AK		 4930 .set_msr = emulator_set_msr,
4931 .get_msr = emulator_get_msr,
67f4d428 4932 .check_pmc = emulator_check_pmc,
222d21aa 4933 .read_pmc = emulator_read_pmc,
6c3287f7 4934 .halt = emulator_halt,
bcaf5cc5 4935 .wbinvd = emulator_wbinvd,
d6aa1000 4936 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4937 .get_fpu = emulator_get_fpu,
4938 .put_fpu = emulator_put_fpu,
c4f035c6 4939 .intercept = emulator_intercept,
bdb42f5a 4940 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4941};
4942
95cb2295
GN		 4943static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4944{
37ccdcbe 4945 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4946 /*
4947 * an sti; sti; sequence only disable interrupts for the first
4948 * instruction. So, if the last instruction, be it emulated or
4949 * not, left the system with the INT_STI flag enabled, it
4950 * means that the last instruction is an sti. We should not
4951 * leave the flag on in this case. The same goes for mov ss
4952 */
37ccdcbe
PB		 4953 if (int_shadow & mask)
4954 mask = 0;
6addfc42 4955 if (unlikely(int_shadow || mask)) {
95cb2295 4956 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4957 if (!mask)
4958 kvm_make_request(KVM_REQ_EVENT, vcpu);
4959 }
95cb2295
GN		 4960}
4961
ef54bcfe 4962static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 4963{
4964 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4965 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 4966 return kvm_propagate_fault(vcpu, &ctxt->exception);
4967
4968 if (ctxt->exception.error_code_valid)
da9cb575
AK		 4969 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4970 ctxt->exception.error_code);
54b8486f 4971 else
da9cb575 4972 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 4973 return false;
54b8486f
GN		 4974}
4975
8ec4722d
MG		 4976static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4977{
adf52235 4978 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4979 int cs_db, cs_l;
4980
8ec4722d
MG		 4981 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4982
adf52235
TY		 4983 ctxt->eflags = kvm_get_rflags(vcpu);
4984 ctxt->eip = kvm_rip_read(vcpu);
4985 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4986 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4987 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4988 cs_db ? X86EMUL_MODE_PROT32 :
4989 X86EMUL_MODE_PROT16;
4990 ctxt->guest_mode = is_guest_mode(vcpu);
4991
dd856efa 4992 init_decode_cache(ctxt);
7ae441ea 4993 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4994}
4995
71f9833b 4996int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4997{
9d74191a 4998 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4999 int ret;
5000
5001 init_emulate_ctxt(vcpu);
5002
9dac77fa
AK		 5003 ctxt->op_bytes = 2;
5004 ctxt->ad_bytes = 2;
5005 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5006 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5007
5008 if (ret != X86EMUL_CONTINUE)
5009 return EMULATE_FAIL;
5010
9dac77fa 5011 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5012 kvm_rip_write(vcpu, ctxt->eip);
5013 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5014
5015 if (irq == NMI_VECTOR)
7460fb4a 5016 vcpu->arch.nmi_pending = 0;
63995653
MG		 5017 else
5018 vcpu->arch.interrupt.pending = false;
5019
5020 return EMULATE_DONE;
5021}
5022EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5023
6d77dbfc
GN		 5024static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5025{
fc3a9157
JR		 5026 int r = EMULATE_DONE;
5027
6d77dbfc
GN		 5028 ++vcpu->stat.insn_emulation_fail;
5029 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5030 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5031 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5032 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5033 vcpu->run->internal.ndata = 0;
5034 r = EMULATE_FAIL;
5035 }
6d77dbfc 5036 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5037
5038 return r;
6d77dbfc
GN		 5039}
5040
93c05d3e 5041static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5042 bool write_fault_to_shadow_pgtable,
5043 int emulation_type)
a6f177ef 5044{
95b3cf69 5045 gpa_t gpa = cr2;
8e3d9d06 5046 pfn_t pfn;
a6f177ef 5047
991eebf9
GN		 5048 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5049 return false;
5050
95b3cf69
XG		 5051 if (!vcpu->arch.mmu.direct_map) {
5052 /*
5053 * Write permission should be allowed since only
5054 * write access need to be emulated.
5055 */
5056 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5057
95b3cf69
XG		 5058 /*
5059 * If the mapping is invalid in guest, let cpu retry
5060 * it to generate fault.
5061 */
5062 if (gpa == UNMAPPED_GVA)
5063 return true;
5064 }
a6f177ef 5065
8e3d9d06
XG		 5066 /*
5067 * Do not retry the unhandleable instruction if it faults on the
5068 * readonly host memory, otherwise it will goto a infinite loop:
5069 * retry instruction -> write #PF -> emulation fail -> retry
5070 * instruction -> ...
5071 */
5072 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5073
5074 /*
5075 * If the instruction failed on the error pfn, it can not be fixed,
5076 * report the error to userspace.
5077 */
5078 if (is_error_noslot_pfn(pfn))
5079 return false;
5080
5081 kvm_release_pfn_clean(pfn);
5082
5083 /* The instructions are well-emulated on direct mmu. */
5084 if (vcpu->arch.mmu.direct_map) {
5085 unsigned int indirect_shadow_pages;
5086
5087 spin_lock(&vcpu->kvm->mmu_lock);
5088 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5089 spin_unlock(&vcpu->kvm->mmu_lock);
5090
5091 if (indirect_shadow_pages)
5092 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5093
a6f177ef 5094 return true;
8e3d9d06 5095 }
a6f177ef 5096
95b3cf69
XG		 5097 /*
5098 * if emulation was due to access to shadowed page table
5099 * and it failed try to unshadow page and re-enter the
5100 * guest to let CPU execute the instruction.
5101 */
5102 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5103
5104 /*
5105 * If the access faults on its page table, it can not
5106 * be fixed by unprotecting shadow page and it should
5107 * be reported to userspace.
5108 */
5109 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5110}
5111
1cb3f3ae
XG		 5112static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5113 unsigned long cr2, int emulation_type)
5114{
5115 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5116 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5117
5118 last_retry_eip = vcpu->arch.last_retry_eip;
5119 last_retry_addr = vcpu->arch.last_retry_addr;
5120
5121 /*
5122 * If the emulation is caused by #PF and it is non-page_table
5123 * writing instruction, it means the VM-EXIT is caused by shadow
5124 * page protected, we can zap the shadow page and retry this
5125 * instruction directly.
5126 *
5127 * Note: if the guest uses a non-page-table modifying instruction
5128 * on the PDE that points to the instruction, then we will unmap
5129 * the instruction and go to an infinite loop. So, we cache the
5130 * last retried eip and the last fault address, if we meet the eip
5131 * and the address again, we can break out of the potential infinite
5132 * loop.
5133 */
5134 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5135
5136 if (!(emulation_type & EMULTYPE_RETRY))
5137 return false;
5138
5139 if (x86_page_table_writing_insn(ctxt))
5140 return false;
5141
5142 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5143 return false;
5144
5145 vcpu->arch.last_retry_eip = ctxt->eip;
5146 vcpu->arch.last_retry_addr = cr2;
5147
5148 if (!vcpu->arch.mmu.direct_map)
5149 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5150
22368028 5151 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5152
5153 return true;
5154}
5155
716d51ab
GN		 5156static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5157static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5158
4a1e10d5
PB		 5159static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5160 unsigned long *db)
5161{
5162 u32 dr6 = 0;
5163 int i;
5164 u32 enable, rwlen;
5165
5166 enable = dr7;
5167 rwlen = dr7 >> 16;
5168 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5169 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5170 dr6 |= (1 << i);
5171 return dr6;
5172}
5173
6addfc42 5174static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5175{
5176 struct kvm_run *kvm_run = vcpu->run;
5177
5178 /*
6addfc42
PB		 5179 * rflags is the old, "raw" value of the flags. The new value has
5180 * not been saved yet.
663f4c61
PB		 5181 *
5182 * This is correct even for TF set by the guest, because "the
5183 * processor will not generate this exception after the instruction
5184 * that sets the TF flag".
5185 */
663f4c61
PB		 5186 if (unlikely(rflags & X86_EFLAGS_TF)) {
5187 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5188 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5189 DR6_RTM;
663f4c61
PB		 5190 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5191 kvm_run->debug.arch.exception = DB_VECTOR;
5192 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5193 *r = EMULATE_USER_EXIT;
5194 } else {
5195 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5196 /*
5197 * "Certain debug exceptions may clear bit 0-3. The
5198 * remaining contents of the DR6 register are never
5199 * cleared by the processor".
5200 */
5201 vcpu->arch.dr6 &= ~15;
6f43ed01 5202 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5203 kvm_queue_exception(vcpu, DB_VECTOR);
5204 }
5205 }
5206}
5207
4a1e10d5
PB		 5208static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5209{
5210 struct kvm_run *kvm_run = vcpu->run;
5211 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5212 u32 dr6 = 0;
5213
5214 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5215 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5216 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5217 vcpu->arch.guest_debug_dr7,
5218 vcpu->arch.eff_db);
5219
5220 if (dr6 != 0) {
6f43ed01 5221 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
4a1e10d5
PB		 5222 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5223 get_segment_base(vcpu, VCPU_SREG_CS);
5224
5225 kvm_run->debug.arch.exception = DB_VECTOR;
5226 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5227 *r = EMULATE_USER_EXIT;
5228 return true;
5229 }
5230 }
5231
4161a569
NA		 5232 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5233 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
4a1e10d5
PB		 5234 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5235 vcpu->arch.dr7,
5236 vcpu->arch.db);
5237
5238 if (dr6 != 0) {
5239 vcpu->arch.dr6 &= ~15;
6f43ed01 5240 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5241 kvm_queue_exception(vcpu, DB_VECTOR);
5242 *r = EMULATE_DONE;
5243 return true;
5244 }
5245 }
5246
5247 return false;
5248}
5249
51d8b661
AP		 5250int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5251 unsigned long cr2,
dc25e89e
AP		 5252 int emulation_type,
5253 void *insn,
5254 int insn_len)
bbd9b64e 5255{
95cb2295 5256 int r;
9d74191a 5257 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5258 bool writeback = true;
93c05d3e 5259 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5260
93c05d3e
XG		 5261 /*
5262 * Clear write_fault_to_shadow_pgtable here to ensure it is
5263 * never reused.
5264 */
5265 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5266 kvm_clear_exception_queue(vcpu);
8d7d8102 5267
571008da 5268 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5269 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5270
5271 /*
5272 * We will reenter on the same instruction since
5273 * we do not set complete_userspace_io. This does not
5274 * handle watchpoints yet, those would be handled in
5275 * the emulate_ops.
5276 */
5277 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5278 return r;
5279
9d74191a
TY		 5280 ctxt->interruptibility = 0;
5281 ctxt->have_exception = false;
e0ad0b47 5282 ctxt->exception.vector = -1;
9d74191a 5283 ctxt->perm_ok = false;
bbd9b64e 5284
b51e974f 5285 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5286
9d74191a 5287 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5288
e46479f8 5289 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5290 ++vcpu->stat.insn_emulation;
1d2887e2 5291 if (r != EMULATION_OK) {
4005996e
AK		 5292 if (emulation_type & EMULTYPE_TRAP_UD)
5293 return EMULATE_FAIL;
991eebf9
GN		 5294 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5295 emulation_type))
bbd9b64e 5296 return EMULATE_DONE;
6d77dbfc
GN		 5297 if (emulation_type & EMULTYPE_SKIP)
5298 return EMULATE_FAIL;
5299 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5300 }
5301 }
5302
ba8afb6b 5303 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5304 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5305 if (ctxt->eflags & X86_EFLAGS_RF)
5306 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5307 return EMULATE_DONE;
5308 }
5309
1cb3f3ae
XG		 5310 if (retry_instruction(ctxt, cr2, emulation_type))
5311 return EMULATE_DONE;
5312
7ae441ea 5313 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5314 changes registers values during IO operation */
7ae441ea
GN		 5315 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5316 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5317 emulator_invalidate_register_cache(ctxt);
7ae441ea 5318 }
4d2179e1 5319
5cd21917 5320restart:
9d74191a 5321 r = x86_emulate_insn(ctxt);
bbd9b64e 5322
775fde86
JR		 5323 if (r == EMULATION_INTERCEPTED)
5324 return EMULATE_DONE;
5325
d2ddd1c4 5326 if (r == EMULATION_FAILED) {
991eebf9
GN		 5327 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5328 emulation_type))
c3cd7ffa
GN		 5329 return EMULATE_DONE;
5330
6d77dbfc 5331 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5332 }
5333
9d74191a 5334 if (ctxt->have_exception) {
d2ddd1c4 5335 r = EMULATE_DONE;
ef54bcfe
PB		 5336 if (inject_emulated_exception(vcpu))
5337 return r;
d2ddd1c4 5338 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5339 if (!vcpu->arch.pio.in) {
5340 /* FIXME: return into emulator if single-stepping. */
3457e419 5341 vcpu->arch.pio.count = 0;
0912c977 5342 } else {
7ae441ea 5343 writeback = false;
716d51ab
GN		 5344 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5345 }
ac0a48c3 5346 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5347 } else if (vcpu->mmio_needed) {
5348 if (!vcpu->mmio_is_write)
5349 writeback = false;
ac0a48c3 5350 r = EMULATE_USER_EXIT;
716d51ab 5351 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5352 } else if (r == EMULATION_RESTART)
5cd21917 5353 goto restart;
d2ddd1c4
GN		 5354 else
5355 r = EMULATE_DONE;
f850e2e6 5356
7ae441ea 5357 if (writeback) {
6addfc42 5358 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5359 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5360 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5361 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5362 if (r == EMULATE_DONE)
6addfc42
PB		 5363 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5364 __kvm_set_rflags(vcpu, ctxt->eflags);
5365
5366 /*
5367 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5368 * do nothing, and it will be requested again as soon as
5369 * the shadow expires. But we still need to check here,
5370 * because POPF has no interrupt shadow.
5371 */
5372 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5373 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5374 } else
5375 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5376
5377 return r;
de7d789a 5378}
51d8b661 5379EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5380
cf8f70bf 5381int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5382{
cf8f70bf 5383 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5384 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5385 size, port, &val, 1);
cf8f70bf 5386 /* do not return to emulator after return from userspace */
7972995b 5387 vcpu->arch.pio.count = 0;
de7d789a
CO		 5388 return ret;
5389}
cf8f70bf 5390EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5391
8cfdc000
ZA		 5392static void tsc_bad(void *info)
5393{
0a3aee0d 5394 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5395}
5396
5397static void tsc_khz_changed(void *data)
c8076604 5398{
8cfdc000
ZA		 5399 struct cpufreq_freqs *freq = data;
5400 unsigned long khz = 0;
5401
5402 if (data)
5403 khz = freq->new;
5404 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5405 khz = cpufreq_quick_get(raw_smp_processor_id());
5406 if (!khz)
5407 khz = tsc_khz;
0a3aee0d 5408 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5409}
5410
c8076604
GH		 5411static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5412 void *data)
5413{
5414 struct cpufreq_freqs *freq = data;
5415 struct kvm *kvm;
5416 struct kvm_vcpu *vcpu;
5417 int i, send_ipi = 0;
5418
8cfdc000
ZA		 5419 /*
5420 * We allow guests to temporarily run on slowing clocks,
5421 * provided we notify them after, or to run on accelerating
5422 * clocks, provided we notify them before. Thus time never
5423 * goes backwards.
5424 *
5425 * However, we have a problem. We can't atomically update
5426 * the frequency of a given CPU from this function; it is
5427 * merely a notifier, which can be called from any CPU.
5428 * Changing the TSC frequency at arbitrary points in time
5429 * requires a recomputation of local variables related to
5430 * the TSC for each VCPU. We must flag these local variables
5431 * to be updated and be sure the update takes place with the
5432 * new frequency before any guests proceed.
5433 *
5434 * Unfortunately, the combination of hotplug CPU and frequency
5435 * change creates an intractable locking scenario; the order
5436 * of when these callouts happen is undefined with respect to
5437 * CPU hotplug, and they can race with each other. As such,
5438 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5439 * undefined; you can actually have a CPU frequency change take
5440 * place in between the computation of X and the setting of the
5441 * variable. To protect against this problem, all updates of
5442 * the per_cpu tsc_khz variable are done in an interrupt
5443 * protected IPI, and all callers wishing to update the value
5444 * must wait for a synchronous IPI to complete (which is trivial
5445 * if the caller is on the CPU already). This establishes the
5446 * necessary total order on variable updates.
5447 *
5448 * Note that because a guest time update may take place
5449 * anytime after the setting of the VCPU's request bit, the
5450 * correct TSC value must be set before the request. However,
5451 * to ensure the update actually makes it to any guest which
5452 * starts running in hardware virtualization between the set
5453 * and the acquisition of the spinlock, we must also ping the
5454 * CPU after setting the request bit.
5455 *
5456 */
5457
c8076604
GH		 5458 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5459 return 0;
5460 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5461 return 0;
8cfdc000
ZA		 5462
5463 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5464
2f303b74 5465 spin_lock(&kvm_lock);
c8076604 5466 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5467 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5468 if (vcpu->cpu != freq->cpu)
5469 continue;
c285545f 5470 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5471 if (vcpu->cpu != smp_processor_id())
8cfdc000 5472 send_ipi = 1;
c8076604
GH		 5473 }
5474 }
2f303b74 5475 spin_unlock(&kvm_lock);
c8076604
GH		 5476
5477 if (freq->old < freq->new && send_ipi) {
5478 /*
5479 * We upscale the frequency. Must make the guest
5480 * doesn't see old kvmclock values while running with
5481 * the new frequency, otherwise we risk the guest sees
5482 * time go backwards.
5483 *
5484 * In case we update the frequency for another cpu
5485 * (which might be in guest context) send an interrupt
5486 * to kick the cpu out of guest context. Next time
5487 * guest context is entered kvmclock will be updated,
5488 * so the guest will not see stale values.
5489 */
8cfdc000 5490 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5491 }
5492 return 0;
5493}
5494
5495static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5496 .notifier_call = kvmclock_cpufreq_notifier
5497};
5498
5499static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5500 unsigned long action, void *hcpu)
5501{
5502 unsigned int cpu = (unsigned long)hcpu;
5503
5504 switch (action) {
5505 case CPU_ONLINE:
5506 case CPU_DOWN_FAILED:
5507 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5508 break;
5509 case CPU_DOWN_PREPARE:
5510 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5511 break;
5512 }
5513 return NOTIFY_OK;
5514}
5515
5516static struct notifier_block kvmclock_cpu_notifier_block = {
5517 .notifier_call = kvmclock_cpu_notifier,
5518 .priority = -INT_MAX
c8076604
GH		 5519};
5520
b820cc0c
ZA		 5521static void kvm_timer_init(void)
5522{
5523 int cpu;
5524
c285545f 5525 max_tsc_khz = tsc_khz;
460dd42e
SB		 5526
5527 cpu_notifier_register_begin();
b820cc0c 5528 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5529#ifdef CONFIG_CPU_FREQ
5530 struct cpufreq_policy policy;
5531 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5532 cpu = get_cpu();
5533 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5534 if (policy.cpuinfo.max_freq)
5535 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5536 put_cpu();
c285545f 5537#endif
b820cc0c
ZA		 5538 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5539 CPUFREQ_TRANSITION_NOTIFIER);
5540 }
c285545f 5541 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5542 for_each_online_cpu(cpu)
5543 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5544
5545 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5546 cpu_notifier_register_done();
5547
b820cc0c
ZA		 5548}
5549
ff9d07a0
ZY		 5550static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5551
f5132b01 5552int kvm_is_in_guest(void)
ff9d07a0 5553{
086c9855 5554 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5555}
5556
5557static int kvm_is_user_mode(void)
5558{
5559 int user_mode = 3;
dcf46b94 5560
086c9855
AS		 5561 if (__this_cpu_read(current_vcpu))
5562 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5563
ff9d07a0
ZY		 5564 return user_mode != 0;
5565}
5566
5567static unsigned long kvm_get_guest_ip(void)
5568{
5569 unsigned long ip = 0;
dcf46b94 5570
086c9855
AS		 5571 if (__this_cpu_read(current_vcpu))
5572 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5573
ff9d07a0
ZY		 5574 return ip;
5575}
5576
5577static struct perf_guest_info_callbacks kvm_guest_cbs = {
5578 .is_in_guest = kvm_is_in_guest,
5579 .is_user_mode = kvm_is_user_mode,
5580 .get_guest_ip = kvm_get_guest_ip,
5581};
5582
5583void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5584{
086c9855 5585 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5586}
5587EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5588
5589void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5590{
086c9855 5591 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5592}
5593EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5594
ce88decf
XG		 5595static void kvm_set_mmio_spte_mask(void)
5596{
5597 u64 mask;
5598 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5599
5600 /*
5601 * Set the reserved bits and the present bit of an paging-structure
5602 * entry to generate page fault with PFER.RSV = 1.
5603 */
885032b9 5604 /* Mask the reserved physical address bits. */
d1431483 5605 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5606
5607 /* Bit 62 is always reserved for 32bit host. */
5608 mask |= 0x3ull << 62;
5609
5610 /* Set the present bit. */
ce88decf
XG		 5611 mask |= 1ull;
5612
5613#ifdef CONFIG_X86_64
5614 /*
5615 * If reserved bit is not supported, clear the present bit to disable
5616 * mmio page fault.
5617 */
5618 if (maxphyaddr == 52)
5619 mask &= ~1ull;
5620#endif
5621
5622 kvm_mmu_set_mmio_spte_mask(mask);
5623}
5624
16e8d74d
MT		 5625#ifdef CONFIG_X86_64
5626static void pvclock_gtod_update_fn(struct work_struct *work)
5627{
d828199e
MT		 5628 struct kvm *kvm;
5629
5630 struct kvm_vcpu *vcpu;
5631 int i;
5632
2f303b74 5633 spin_lock(&kvm_lock);
d828199e
MT		 5634 list_for_each_entry(kvm, &vm_list, vm_list)
5635 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5636 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5637 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5638 spin_unlock(&kvm_lock);
16e8d74d
MT		 5639}
5640
5641static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5642
5643/*
5644 * Notification about pvclock gtod data update.
5645 */
5646static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5647 void *priv)
5648{
5649 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5650 struct timekeeper *tk = priv;
5651
5652 update_pvclock_gtod(tk);
5653
5654 /* disable master clock if host does not trust, or does not
5655 * use, TSC clocksource
5656 */
5657 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5658 atomic_read(&kvm_guest_has_master_clock) != 0)
5659 queue_work(system_long_wq, &pvclock_gtod_work);
5660
5661 return 0;
5662}
5663
5664static struct notifier_block pvclock_gtod_notifier = {
5665 .notifier_call = pvclock_gtod_notify,
5666};
5667#endif
5668
f8c16bba 5669int kvm_arch_init(void *opaque)
043405e1 5670{
b820cc0c 5671 int r;
6b61edf7 5672 struct kvm_x86_ops *ops = opaque;
f8c16bba 5673
f8c16bba
ZX		 5674 if (kvm_x86_ops) {
5675 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5676 r = -EEXIST;
5677 goto out;
f8c16bba
ZX		 5678 }
5679
5680 if (!ops->cpu_has_kvm_support()) {
5681 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5682 r = -EOPNOTSUPP;
5683 goto out;
f8c16bba
ZX		 5684 }
5685 if (ops->disabled_by_bios()) {
5686 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5687 r = -EOPNOTSUPP;
5688 goto out;
f8c16bba
ZX		 5689 }
5690
013f6a5d
MT		 5691 r = -ENOMEM;
5692 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5693 if (!shared_msrs) {
5694 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5695 goto out;
5696 }
5697
97db56ce
AK		 5698 r = kvm_mmu_module_init();
5699 if (r)
013f6a5d 5700 goto out_free_percpu;
97db56ce 5701
ce88decf 5702 kvm_set_mmio_spte_mask();
97db56ce 5703
f8c16bba 5704 kvm_x86_ops = ops;
920c8377
PB		 5705 kvm_init_msr_list();
5706
7b52345e 5707 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5708 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5709
b820cc0c 5710 kvm_timer_init();
c8076604 5711
ff9d07a0
ZY		 5712 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5713
2acf923e
DC		 5714 if (cpu_has_xsave)
5715 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5716
c5cc421b 5717 kvm_lapic_init();
16e8d74d
MT		 5718#ifdef CONFIG_X86_64
5719 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5720#endif
5721
f8c16bba 5722 return 0;
56c6d28a 5723
013f6a5d
MT		 5724out_free_percpu:
5725 free_percpu(shared_msrs);
56c6d28a 5726out:
56c6d28a 5727 return r;
043405e1 5728}
8776e519 5729
f8c16bba
ZX		 5730void kvm_arch_exit(void)
5731{
ff9d07a0
ZY		 5732 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5733
888d256e
JK		 5734 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5735 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5736 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5737 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5738#ifdef CONFIG_X86_64
5739 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5740#endif
f8c16bba 5741 kvm_x86_ops = NULL;
56c6d28a 5742 kvm_mmu_module_exit();
013f6a5d 5743 free_percpu(shared_msrs);
56c6d28a 5744}
f8c16bba 5745
8776e519
HB		 5746int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5747{
5748 ++vcpu->stat.halt_exits;
5749 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5750 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5751 return 1;
5752 } else {
5753 vcpu->run->exit_reason = KVM_EXIT_HLT;
5754 return 0;
5755 }
5756}
5757EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5758
55cd8e5a
GN		 5759int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5760{
5761 u64 param, ingpa, outgpa, ret;
5762 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5763 bool fast, longmode;
55cd8e5a
GN		 5764
5765 /*
5766 * hypercall generates UD from non zero cpl and real mode
5767 * per HYPER-V spec
5768 */
3eeb3288 5769 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5770 kvm_queue_exception(vcpu, UD_VECTOR);
5771 return 0;
5772 }
5773
a449c7aa 5774 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5775
5776 if (!longmode) {
ccd46936
GN		 5777 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5778 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5779 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5780 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5781 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5782 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5783 }
5784#ifdef CONFIG_X86_64
5785 else {
5786 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5787 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5788 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5789 }
5790#endif
5791
5792 code = param & 0xffff;
5793 fast = (param >> 16) & 0x1;
5794 rep_cnt = (param >> 32) & 0xfff;
5795 rep_idx = (param >> 48) & 0xfff;
5796
5797 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5798
c25bc163
GN		 5799 switch (code) {
5800 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5801 kvm_vcpu_on_spin(vcpu);
5802 break;
5803 default:
5804 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5805 break;
5806 }
55cd8e5a
GN		 5807
5808 ret = res | (((u64)rep_done & 0xfff) << 32);
5809 if (longmode) {
5810 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5811 } else {
5812 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5813 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5814 }
5815
5816 return 1;
5817}
5818
6aef266c
SV		 5819/*
5820 * kvm_pv_kick_cpu_op: Kick a vcpu.
5821 *
5822 * @apicid - apicid of vcpu to be kicked.
5823 */
5824static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5825{
24d2166b 5826 struct kvm_lapic_irq lapic_irq;
6aef266c 5827
24d2166b
R		 5828 lapic_irq.shorthand = 0;
5829 lapic_irq.dest_mode = 0;
5830 lapic_irq.dest_id = apicid;
6aef266c 5831
24d2166b
R		 5832 lapic_irq.delivery_mode = APIC_DM_REMRD;
5833 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5834}
5835
8776e519
HB		 5836int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5837{
5838 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5839 int op_64_bit, r = 1;
8776e519 5840
55cd8e5a
GN		 5841 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5842 return kvm_hv_hypercall(vcpu);
5843
5fdbf976
MT		 5844 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5845 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5846 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5847 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5848 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5849
229456fc 5850 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5851
a449c7aa
NA		 5852 op_64_bit = is_64_bit_mode(vcpu);
5853 if (!op_64_bit) {
8776e519
HB		 5854 nr &= 0xFFFFFFFF;
5855 a0 &= 0xFFFFFFFF;
5856 a1 &= 0xFFFFFFFF;
5857 a2 &= 0xFFFFFFFF;
5858 a3 &= 0xFFFFFFFF;
5859 }
5860
07708c4a
JK		 5861 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5862 ret = -KVM_EPERM;
5863 goto out;
5864 }
5865
8776e519 5866 switch (nr) {
b93463aa
AK		 5867 case KVM_HC_VAPIC_POLL_IRQ:
5868 ret = 0;
5869 break;
6aef266c
SV		 5870 case KVM_HC_KICK_CPU:
5871 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5872 ret = 0;
5873 break;
8776e519
HB		 5874 default:
5875 ret = -KVM_ENOSYS;
5876 break;
5877 }
07708c4a 5878out:
a449c7aa
NA		 5879 if (!op_64_bit)
5880 ret = (u32)ret;
5fdbf976 5881 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5882 ++vcpu->stat.hypercalls;
2f333bcb 5883 return r;
8776e519
HB		 5884}
5885EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5886
b6785def 5887static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5888{
d6aa1000 5889 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5890 char instruction[3];
5fdbf976 5891 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5892
8776e519 5893 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5894
9d74191a 5895 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5896}
5897
b6c7a5dc
HB		 5898/*
5899 * Check if userspace requested an interrupt window, and that the
5900 * interrupt window is open.
5901 *
5902 * No need to exit to userspace if we already have an interrupt queued.
5903 */
851ba692 5904static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5905{
8061823a 5906 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5907 vcpu->run->request_interrupt_window &&
5df56646 5908 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5909}
5910
851ba692 5911static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5912{
851ba692
AK		 5913 struct kvm_run *kvm_run = vcpu->run;
5914
91586a3b 5915 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5916 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5917 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5918 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5919 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5920 else
b6c7a5dc 5921 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5922 kvm_arch_interrupt_allowed(vcpu) &&
5923 !kvm_cpu_has_interrupt(vcpu) &&
5924 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5925}
5926
95ba8273
GN		 5927static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5928{
5929 int max_irr, tpr;
5930
5931 if (!kvm_x86_ops->update_cr8_intercept)
5932 return;
5933
88c808fd
AK		 5934 if (!vcpu->arch.apic)
5935 return;
5936
8db3baa2
GN		 5937 if (!vcpu->arch.apic->vapic_addr)
5938 max_irr = kvm_lapic_find_highest_irr(vcpu);
5939 else
5940 max_irr = -1;
95ba8273
GN		 5941
5942 if (max_irr != -1)
5943 max_irr >>= 4;
5944
5945 tpr = kvm_lapic_get_cr8(vcpu);
5946
5947 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5948}
5949
b6b8a145 5950static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5951{
b6b8a145
JK		 5952 int r;
5953
95ba8273 5954 /* try to reinject previous events if any */
b59bb7bd 5955 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5956 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5957 vcpu->arch.exception.has_error_code,
5958 vcpu->arch.exception.error_code);
d6e8c854
NA		 5959
5960 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5961 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5962 X86_EFLAGS_RF);
5963
6bdf0662
NA		 5964 if (vcpu->arch.exception.nr == DB_VECTOR &&
5965 (vcpu->arch.dr7 & DR7_GD)) {
5966 vcpu->arch.dr7 &= ~DR7_GD;
5967 kvm_update_dr7(vcpu);
5968 }
5969
b59bb7bd
GN		 5970 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5971 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5972 vcpu->arch.exception.error_code,
5973 vcpu->arch.exception.reinject);
b6b8a145 5974 return 0;
b59bb7bd
GN		 5975 }
5976
95ba8273
GN		 5977 if (vcpu->arch.nmi_injected) {
5978 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5979 return 0;
95ba8273
GN		 5980 }
5981
5982 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5983 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5984 return 0;
5985 }
5986
5987 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5988 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5989 if (r != 0)
5990 return r;
95ba8273
GN		 5991 }
5992
5993 /* try to inject new event if pending */
5994 if (vcpu->arch.nmi_pending) {
5995 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5996 --vcpu->arch.nmi_pending;
95ba8273
GN		 5997 vcpu->arch.nmi_injected = true;
5998 kvm_x86_ops->set_nmi(vcpu);
5999 }
c7c9c56c 6000 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6001 /*
6002 * Because interrupts can be injected asynchronously, we are
6003 * calling check_nested_events again here to avoid a race condition.
6004 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6005 * proposal and current concerns. Perhaps we should be setting
6006 * KVM_REQ_EVENT only on certain events and not unconditionally?
6007 */
6008 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6009 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6010 if (r != 0)
6011 return r;
6012 }
95ba8273 6013 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6014 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6015 false);
6016 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6017 }
6018 }
b6b8a145 6019 return 0;
95ba8273
GN		 6020}
6021
7460fb4a
AK		 6022static void process_nmi(struct kvm_vcpu *vcpu)
6023{
6024 unsigned limit = 2;
6025
6026 /*
6027 * x86 is limited to one NMI running, and one NMI pending after it.
6028 * If an NMI is already in progress, limit further NMIs to just one.
6029 * Otherwise, allow two (and we'll inject the first one immediately).
6030 */
6031 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6032 limit = 1;
6033
6034 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6035 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6036 kvm_make_request(KVM_REQ_EVENT, vcpu);
6037}
6038
3d81bc7e 6039static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6040{
6041 u64 eoi_exit_bitmap[4];
cf9e65b7 6042 u32 tmr[8];
c7c9c56c 6043
3d81bc7e
YZ		 6044 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6045 return;
c7c9c56c
YZ		 6046
6047 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6048 memset(tmr, 0, 32);
c7c9c56c 6049
cf9e65b7 6050 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6051 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6052 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6053}
6054
a70656b6
RK		 6055static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6056{
6057 ++vcpu->stat.tlb_flush;
6058 kvm_x86_ops->tlb_flush(vcpu);
6059}
6060
4256f43f
TC		 6061void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6062{
c24ae0dc
TC		 6063 struct page *page = NULL;
6064
f439ed27
PB		 6065 if (!irqchip_in_kernel(vcpu->kvm))
6066 return;
6067
4256f43f
TC		 6068 if (!kvm_x86_ops->set_apic_access_page_addr)
6069 return;
6070
c24ae0dc
TC		 6071 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6072 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6073
6074 /*
6075 * Do not pin apic access page in memory, the MMU notifier
6076 * will call us again if it is migrated or swapped out.
6077 */
6078 put_page(page);
4256f43f
TC		 6079}
6080EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6081
fe71557a
TC		 6082void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6083 unsigned long address)
6084{
c24ae0dc
TC		 6085 /*
6086 * The physical address of apic access page is stored in the VMCS.
6087 * Update it when it becomes invalid.
6088 */
6089 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6090 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6091}
6092
9357d939
TY		 6093/*
6094 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6095 * exiting to the userspace. Otherwise, the value will be returned to the
6096 * userspace.
6097 */
851ba692 6098static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6099{
6100 int r;
6a8b1d13 6101 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6102 vcpu->run->request_interrupt_window;
730dca42 6103 bool req_immediate_exit = false;
b6c7a5dc 6104
3e007509 6105 if (vcpu->requests) {
a8eeb04a 6106 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6107 kvm_mmu_unload(vcpu);
a8eeb04a 6108 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6109 __kvm_migrate_timers(vcpu);
d828199e
MT		 6110 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6111 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6112 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6113 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6114 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6115 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6116 if (unlikely(r))
6117 goto out;
6118 }
a8eeb04a 6119 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6120 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6121 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6122 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6123 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6124 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6125 r = 0;
6126 goto out;
6127 }
a8eeb04a 6128 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6129 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6130 r = 0;
6131 goto out;
6132 }
a8eeb04a 6133 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6134 vcpu->fpu_active = 0;
6135 kvm_x86_ops->fpu_deactivate(vcpu);
6136 }
af585b92
GN		 6137 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6138 /* Page is swapped out. Do synthetic halt */
6139 vcpu->arch.apf.halted = true;
6140 r = 1;
6141 goto out;
6142 }
c9aaa895
GC		 6143 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6144 record_steal_time(vcpu);
7460fb4a
AK		 6145 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6146 process_nmi(vcpu);
f5132b01
GN		 6147 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6148 kvm_handle_pmu_event(vcpu);
6149 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6150 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6151 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6152 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6153 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6154 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6155 }
b93463aa 6156
b463a6f7 6157 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6158 kvm_apic_accept_events(vcpu);
6159 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6160 r = 1;
6161 goto out;
6162 }
6163
b6b8a145
JK		 6164 if (inject_pending_event(vcpu, req_int_win) != 0)
6165 req_immediate_exit = true;
b463a6f7 6166 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6167 else if (vcpu->arch.nmi_pending)
c9a7953f 6168 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6169 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6170 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6171
6172 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6173 /*
6174 * Update architecture specific hints for APIC
6175 * virtual interrupt delivery.
6176 */
6177 if (kvm_x86_ops->hwapic_irr_update)
6178 kvm_x86_ops->hwapic_irr_update(vcpu,
6179 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6180 update_cr8_intercept(vcpu);
6181 kvm_lapic_sync_to_vapic(vcpu);
6182 }
6183 }
6184
d8368af8
AK		 6185 r = kvm_mmu_reload(vcpu);
6186 if (unlikely(r)) {
d905c069 6187 goto cancel_injection;
d8368af8
AK		 6188 }
6189
b6c7a5dc
HB		 6190 preempt_disable();
6191
6192 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6193 if (vcpu->fpu_active)
6194 kvm_load_guest_fpu(vcpu);
2acf923e 6195 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6196
6b7e2d09
XG		 6197 vcpu->mode = IN_GUEST_MODE;
6198
01b71917
MT		 6199 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6200
6b7e2d09
XG		 6201 /* We should set ->mode before check ->requests,
6202 * see the comment in make_all_cpus_request.
6203 */
01b71917 6204 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6205
d94e1dc9 6206 local_irq_disable();
32f88400 6207
6b7e2d09 6208 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6209 || need_resched() || signal_pending(current)) {
6b7e2d09 6210 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6211 smp_wmb();
6c142801
AK		 6212 local_irq_enable();
6213 preempt_enable();
01b71917 6214 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6215 r = 1;
d905c069 6216 goto cancel_injection;
6c142801
AK		 6217 }
6218
d6185f20
NHE		 6219 if (req_immediate_exit)
6220 smp_send_reschedule(vcpu->cpu);
6221
b6c7a5dc
HB		 6222 kvm_guest_enter();
6223
42dbaa5a 6224 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6225 set_debugreg(0, 7);
6226 set_debugreg(vcpu->arch.eff_db[0], 0);
6227 set_debugreg(vcpu->arch.eff_db[1], 1);
6228 set_debugreg(vcpu->arch.eff_db[2], 2);
6229 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6230 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6231 }
b6c7a5dc 6232
229456fc 6233 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6234 kvm_x86_ops->run(vcpu);
b6c7a5dc 6235
c77fb5fe
PB		 6236 /*
6237 * Do this here before restoring debug registers on the host. And
6238 * since we do this before handling the vmexit, a DR access vmexit
6239 * can (a) read the correct value of the debug registers, (b) set
6240 * KVM_DEBUGREG_WONT_EXIT again.
6241 */
6242 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6243 int i;
6244
6245 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6246 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6247 for (i = 0; i < KVM_NR_DB_REGS; i++)
6248 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6249 }
6250
24f1e32c
FW		 6251 /*
6252 * If the guest has used debug registers, at least dr7
6253 * will be disabled while returning to the host.
6254 * If we don't have active breakpoints in the host, we don't
6255 * care about the messed up debug address registers. But if
6256 * we have some of them active, restore the old state.
6257 */
59d8eb53 6258 if (hw_breakpoint_active())
24f1e32c 6259 hw_breakpoint_restore();
42dbaa5a 6260
886b470c
MT		 6261 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6262 native_read_tsc());
1d5f066e 6263
6b7e2d09 6264 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6265 smp_wmb();
a547c6db
YZ		 6266
6267 /* Interrupt is enabled by handle_external_intr() */
6268 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6269
6270 ++vcpu->stat.exits;
6271
6272 /*
6273 * We must have an instruction between local_irq_enable() and
6274 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6275 * the interrupt shadow. The stat.exits increment will do nicely.
6276 * But we need to prevent reordering, hence this barrier():
6277 */
6278 barrier();
6279
6280 kvm_guest_exit();
6281
6282 preempt_enable();
6283
f656ce01 6284 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6285
b6c7a5dc
HB		 6286 /*
6287 * Profile KVM exit RIPs:
6288 */
6289 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6290 unsigned long rip = kvm_rip_read(vcpu);
6291 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6292 }
6293
cc578287
ZA		 6294 if (unlikely(vcpu->arch.tsc_always_catchup))
6295 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6296
5cfb1d5a
MT		 6297 if (vcpu->arch.apic_attention)
6298 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6299
851ba692 6300 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6301 return r;
6302
6303cancel_injection:
6304 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6305 if (unlikely(vcpu->arch.apic_attention))
6306 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6307out:
6308 return r;
6309}
b6c7a5dc 6310
09cec754 6311
851ba692 6312static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6313{
6314 int r;
f656ce01 6315 struct kvm *kvm = vcpu->kvm;
d7690175 6316
f656ce01 6317 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6318
6319 r = 1;
6320 while (r > 0) {
af585b92
GN		 6321 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6322 !vcpu->arch.apf.halted)
851ba692 6323 r = vcpu_enter_guest(vcpu);
d7690175 6324 else {
f656ce01 6325 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6326 kvm_vcpu_block(vcpu);
f656ce01 6327 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6328 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6329 kvm_apic_accept_events(vcpu);
09cec754
GN		 6330 switch(vcpu->arch.mp_state) {
6331 case KVM_MP_STATE_HALTED:
6aef266c 6332 vcpu->arch.pv.pv_unhalted = false;
d7690175 6333 vcpu->arch.mp_state =
09cec754
GN		 6334 KVM_MP_STATE_RUNNABLE;
6335 case KVM_MP_STATE_RUNNABLE:
af585b92 6336 vcpu->arch.apf.halted = false;
09cec754 6337 break;
66450a21
JK		 6338 case KVM_MP_STATE_INIT_RECEIVED:
6339 break;
09cec754
GN		 6340 default:
6341 r = -EINTR;
6342 break;
6343 }
6344 }
d7690175
MT		 6345 }
6346
09cec754
GN		 6347 if (r <= 0)
6348 break;
6349
6350 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6351 if (kvm_cpu_has_pending_timer(vcpu))
6352 kvm_inject_pending_timer_irqs(vcpu);
6353
851ba692 6354 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6355 r = -EINTR;
851ba692 6356 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6357 ++vcpu->stat.request_irq_exits;
6358 }
af585b92
GN		 6359
6360 kvm_check_async_pf_completion(vcpu);
6361
09cec754
GN		 6362 if (signal_pending(current)) {
6363 r = -EINTR;
851ba692 6364 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6365 ++vcpu->stat.signal_exits;
6366 }
6367 if (need_resched()) {
f656ce01 6368 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6369 cond_resched();
f656ce01 6370 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6371 }
b6c7a5dc
HB		 6372 }
6373
f656ce01 6374 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6375
6376 return r;
6377}
6378
716d51ab
GN		 6379static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6380{
6381 int r;
6382 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6383 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6384 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6385 if (r != EMULATE_DONE)
6386 return 0;
6387 return 1;
6388}
6389
6390static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6391{
6392 BUG_ON(!vcpu->arch.pio.count);
6393
6394 return complete_emulated_io(vcpu);
6395}
6396
f78146b0
AK		 6397/*
6398 * Implements the following, as a state machine:
6399 *
6400 * read:
6401 * for each fragment
87da7e66
XG		 6402 * for each mmio piece in the fragment
6403 * write gpa, len
6404 * exit
6405 * copy data
f78146b0
AK		 6406 * execute insn
6407 *
6408 * write:
6409 * for each fragment
87da7e66
XG		 6410 * for each mmio piece in the fragment
6411 * write gpa, len
6412 * copy data
6413 * exit
f78146b0 6414 */
716d51ab 6415static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6416{
6417 struct kvm_run *run = vcpu->run;
f78146b0 6418 struct kvm_mmio_fragment *frag;
87da7e66 6419 unsigned len;
5287f194 6420
716d51ab 6421 BUG_ON(!vcpu->mmio_needed);
5287f194 6422
716d51ab 6423 /* Complete previous fragment */
87da7e66
XG		 6424 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6425 len = min(8u, frag->len);
716d51ab 6426 if (!vcpu->mmio_is_write)
87da7e66
XG		 6427 memcpy(frag->data, run->mmio.data, len);
6428
6429 if (frag->len <= 8) {
6430 /* Switch to the next fragment. */
6431 frag++;
6432 vcpu->mmio_cur_fragment++;
6433 } else {
6434 /* Go forward to the next mmio piece. */
6435 frag->data += len;
6436 frag->gpa += len;
6437 frag->len -= len;
6438 }
6439
a08d3b3b 6440 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6441 vcpu->mmio_needed = 0;
0912c977
PB		 6442
6443 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6444 if (vcpu->mmio_is_write)
716d51ab
GN		 6445 return 1;
6446 vcpu->mmio_read_completed = 1;
6447 return complete_emulated_io(vcpu);
6448 }
87da7e66 6449
716d51ab
GN		 6450 run->exit_reason = KVM_EXIT_MMIO;
6451 run->mmio.phys_addr = frag->gpa;
6452 if (vcpu->mmio_is_write)
87da7e66
XG		 6453 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6454 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6455 run->mmio.is_write = vcpu->mmio_is_write;
6456 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6457 return 0;
5287f194
AK		 6458}
6459
716d51ab 6460
b6c7a5dc
HB		 6461int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6462{
6463 int r;
6464 sigset_t sigsaved;
6465
e5c30142
AK		 6466 if (!tsk_used_math(current) && init_fpu(current))
6467 return -ENOMEM;
6468
ac9f6dc0
AK		 6469 if (vcpu->sigset_active)
6470 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6471
a4535290 6472 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6473 kvm_vcpu_block(vcpu);
66450a21 6474 kvm_apic_accept_events(vcpu);
d7690175 6475 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6476 r = -EAGAIN;
6477 goto out;
b6c7a5dc
HB		 6478 }
6479
b6c7a5dc 6480 /* re-sync apic's tpr */
eea1cff9
AP		 6481 if (!irqchip_in_kernel(vcpu->kvm)) {
6482 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6483 r = -EINVAL;
6484 goto out;
6485 }
6486 }
b6c7a5dc 6487
716d51ab
GN		 6488 if (unlikely(vcpu->arch.complete_userspace_io)) {
6489 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6490 vcpu->arch.complete_userspace_io = NULL;
6491 r = cui(vcpu);
6492 if (r <= 0)
6493 goto out;
6494 } else
6495 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6496
851ba692 6497 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6498
6499out:
f1d86e46 6500 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6501 if (vcpu->sigset_active)
6502 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6503
b6c7a5dc
HB		 6504 return r;
6505}
6506
6507int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6508{
7ae441ea
GN		 6509 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6510 /*
6511 * We are here if userspace calls get_regs() in the middle of
6512 * instruction emulation. Registers state needs to be copied
4a969980 6513 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6514 * that usually, but some bad designed PV devices (vmware
6515 * backdoor interface) need this to work
6516 */
dd856efa 6517 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6518 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6519 }
5fdbf976
MT		 6520 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6521 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6522 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6523 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6524 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6525 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6526 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6527 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6528#ifdef CONFIG_X86_64
5fdbf976
MT		 6529 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6530 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6531 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6532 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6533 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6534 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6535 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6536 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6537#endif
6538
5fdbf976 6539 regs->rip = kvm_rip_read(vcpu);
91586a3b 6540 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6541
b6c7a5dc
HB		 6542 return 0;
6543}
6544
6545int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6546{
7ae441ea
GN		 6547 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6548 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6549
5fdbf976
MT		 6550 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6551 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6552 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6553 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6554 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6555 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6556 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6557 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6558#ifdef CONFIG_X86_64
5fdbf976
MT		 6559 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6560 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6561 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6562 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6563 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6564 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6565 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6566 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6567#endif
6568
5fdbf976 6569 kvm_rip_write(vcpu, regs->rip);
91586a3b 6570 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6571
b4f14abd
JK		 6572 vcpu->arch.exception.pending = false;
6573
3842d135
AK		 6574 kvm_make_request(KVM_REQ_EVENT, vcpu);
6575
b6c7a5dc
HB		 6576 return 0;
6577}
6578
b6c7a5dc
HB		 6579void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6580{
6581 struct kvm_segment cs;
6582
3e6e0aab 6583 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6584 *db = cs.db;
6585 *l = cs.l;
6586}
6587EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6588
6589int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6590 struct kvm_sregs *sregs)
6591{
89a27f4d 6592 struct desc_ptr dt;
b6c7a5dc 6593
3e6e0aab
GT		 6594 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6595 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6596 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6597 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6598 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6599 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6600
3e6e0aab
GT		 6601 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6602 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6603
6604 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6605 sregs->idt.limit = dt.size;
6606 sregs->idt.base = dt.address;
b6c7a5dc 6607 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6608 sregs->gdt.limit = dt.size;
6609 sregs->gdt.base = dt.address;
b6c7a5dc 6610
4d4ec087 6611 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6612 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6613 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6614 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6615 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6616 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6617 sregs->apic_base = kvm_get_apic_base(vcpu);
6618
923c61bb 6619 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6620
36752c9b 6621 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6622 set_bit(vcpu->arch.interrupt.nr,
6623 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6624
b6c7a5dc
HB		 6625 return 0;
6626}
6627
62d9f0db
MT		 6628int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6629 struct kvm_mp_state *mp_state)
6630{
66450a21 6631 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6632 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6633 vcpu->arch.pv.pv_unhalted)
6634 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6635 else
6636 mp_state->mp_state = vcpu->arch.mp_state;
6637
62d9f0db
MT		 6638 return 0;
6639}
6640
6641int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6642 struct kvm_mp_state *mp_state)
6643{
66450a21
JK		 6644 if (!kvm_vcpu_has_lapic(vcpu) &&
6645 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6646 return -EINVAL;
6647
6648 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6649 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6650 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6651 } else
6652 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6653 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6654 return 0;
6655}
6656
7f3d35fd
KW		 6657int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6658 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6659{
9d74191a 6660 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6661 int ret;
e01c2426 6662
8ec4722d 6663 init_emulate_ctxt(vcpu);
c697518a 6664
7f3d35fd 6665 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6666 has_error_code, error_code);
c697518a 6667
c697518a 6668 if (ret)
19d04437 6669 return EMULATE_FAIL;
37817f29 6670
9d74191a
TY		 6671 kvm_rip_write(vcpu, ctxt->eip);
6672 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6673 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6674 return EMULATE_DONE;
37817f29
IE		 6675}
6676EXPORT_SYMBOL_GPL(kvm_task_switch);
6677
b6c7a5dc
HB		 6678int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6679 struct kvm_sregs *sregs)
6680{
58cb628d 6681 struct msr_data apic_base_msr;
b6c7a5dc 6682 int mmu_reset_needed = 0;
63f42e02 6683 int pending_vec, max_bits, idx;
89a27f4d 6684 struct desc_ptr dt;
b6c7a5dc 6685
6d1068b3
PM		 6686 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6687 return -EINVAL;
6688
89a27f4d
GN		 6689 dt.size = sregs->idt.limit;
6690 dt.address = sregs->idt.base;
b6c7a5dc 6691 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6692 dt.size = sregs->gdt.limit;
6693 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6694 kvm_x86_ops->set_gdt(vcpu, &dt);
6695
ad312c7c 6696 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6697 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6698 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6699 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6700
2d3ad1f4 6701 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6702
f6801dff 6703 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6704 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6705 apic_base_msr.data = sregs->apic_base;
6706 apic_base_msr.host_initiated = true;
6707 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6708
4d4ec087 6709 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6710 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6711 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6712
fc78f519 6713 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6714 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6715 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6716 kvm_update_cpuid(vcpu);
63f42e02
XG		 6717
6718 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6719 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6720 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6721 mmu_reset_needed = 1;
6722 }
63f42e02 6723 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6724
6725 if (mmu_reset_needed)
6726 kvm_mmu_reset_context(vcpu);
6727
a50abc3b 6728 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6729 pending_vec = find_first_bit(
6730 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6731 if (pending_vec < max_bits) {
66fd3f7f 6732 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6733 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6734 }
6735
3e6e0aab
GT		 6736 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6737 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6738 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6739 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6740 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6741 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6742
3e6e0aab
GT		 6743 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6744 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6745
5f0269f5
ME		 6746 update_cr8_intercept(vcpu);
6747
9c3e4aab 6748 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6749 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6750 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6751 !is_protmode(vcpu))
9c3e4aab
MT		 6752 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6753
3842d135
AK		 6754 kvm_make_request(KVM_REQ_EVENT, vcpu);
6755
b6c7a5dc
HB		 6756 return 0;
6757}
6758
d0bfb940
JK		 6759int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6760 struct kvm_guest_debug *dbg)
b6c7a5dc 6761{
355be0b9 6762 unsigned long rflags;
ae675ef0 6763 int i, r;
b6c7a5dc 6764
4f926bf2
JK		 6765 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6766 r = -EBUSY;
6767 if (vcpu->arch.exception.pending)
2122ff5e 6768 goto out;
4f926bf2
JK		 6769 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6770 kvm_queue_exception(vcpu, DB_VECTOR);
6771 else
6772 kvm_queue_exception(vcpu, BP_VECTOR);
6773 }
6774
91586a3b
JK		 6775 /*
6776 * Read rflags as long as potentially injected trace flags are still
6777 * filtered out.
6778 */
6779 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6780
6781 vcpu->guest_debug = dbg->control;
6782 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6783 vcpu->guest_debug = 0;
6784
6785 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6786 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6787 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6788 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6789 } else {
6790 for (i = 0; i < KVM_NR_DB_REGS; i++)
6791 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6792 }
c8639010 6793 kvm_update_dr7(vcpu);
ae675ef0 6794
f92653ee
JK		 6795 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6796 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6797 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6798
91586a3b
JK		 6799 /*
6800 * Trigger an rflags update that will inject or remove the trace
6801 * flags.
6802 */
6803 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6804
c8639010 6805 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6806
4f926bf2 6807 r = 0;
d0bfb940 6808
2122ff5e 6809out:
b6c7a5dc
HB		 6810
6811 return r;
6812}
6813
8b006791
ZX		 6814/*
6815 * Translate a guest virtual address to a guest physical address.
6816 */
6817int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6818 struct kvm_translation *tr)
6819{
6820 unsigned long vaddr = tr->linear_address;
6821 gpa_t gpa;
f656ce01 6822 int idx;
8b006791 6823
f656ce01 6824 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6825 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6826 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6827 tr->physical_address = gpa;
6828 tr->valid = gpa != UNMAPPED_GVA;
6829 tr->writeable = 1;
6830 tr->usermode = 0;
8b006791
ZX		 6831
6832 return 0;
6833}
6834
d0752060
HB		 6835int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6836{
98918833
SY		 6837 struct i387_fxsave_struct *fxsave =
6838 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6839
d0752060
HB		 6840 memcpy(fpu->fpr, fxsave->st_space, 128);
6841 fpu->fcw = fxsave->cwd;
6842 fpu->fsw = fxsave->swd;
6843 fpu->ftwx = fxsave->twd;
6844 fpu->last_opcode = fxsave->fop;
6845 fpu->last_ip = fxsave->rip;
6846 fpu->last_dp = fxsave->rdp;
6847 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6848
d0752060
HB		 6849 return 0;
6850}
6851
6852int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6853{
98918833
SY		 6854 struct i387_fxsave_struct *fxsave =
6855 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6856
d0752060
HB		 6857 memcpy(fxsave->st_space, fpu->fpr, 128);
6858 fxsave->cwd = fpu->fcw;
6859 fxsave->swd = fpu->fsw;
6860 fxsave->twd = fpu->ftwx;
6861 fxsave->fop = fpu->last_opcode;
6862 fxsave->rip = fpu->last_ip;
6863 fxsave->rdp = fpu->last_dp;
6864 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6865
d0752060
HB		 6866 return 0;
6867}
6868
10ab25cd 6869int fx_init(struct kvm_vcpu *vcpu)
d0752060 6870{
10ab25cd
JK		 6871 int err;
6872
6873 err = fpu_alloc(&vcpu->arch.guest_fpu);
6874 if (err)
6875 return err;
6876
98918833 6877 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6878
2acf923e
DC		 6879 /*
6880 * Ensure guest xcr0 is valid for loading
6881 */
6882 vcpu->arch.xcr0 = XSTATE_FP;
6883
ad312c7c 6884 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6885
6886 return 0;
d0752060
HB		 6887}
6888EXPORT_SYMBOL_GPL(fx_init);
6889
98918833
SY		 6890static void fx_free(struct kvm_vcpu *vcpu)
6891{
6892 fpu_free(&vcpu->arch.guest_fpu);
6893}
6894
d0752060
HB		 6895void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6896{
2608d7a1 6897 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6898 return;
6899
2acf923e
DC		 6900 /*
6901 * Restore all possible states in the guest,
6902 * and assume host would use all available bits.
6903 * Guest xcr0 would be loaded later.
6904 */
6905 kvm_put_guest_xcr0(vcpu);
d0752060 6906 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6907 __kernel_fpu_begin();
98918833 6908 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6909 trace_kvm_fpu(1);
d0752060 6910}
d0752060
HB		 6911
6912void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6913{
2acf923e
DC		 6914 kvm_put_guest_xcr0(vcpu);
6915
d0752060
HB		 6916 if (!vcpu->guest_fpu_loaded)
6917 return;
6918
6919 vcpu->guest_fpu_loaded = 0;
98918833 6920 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6921 __kernel_fpu_end();
f096ed85 6922 ++vcpu->stat.fpu_reload;
a8eeb04a 6923 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6924 trace_kvm_fpu(0);
d0752060 6925}
e9b11c17
ZX		 6926
6927void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6928{
12f9a48f 6929 kvmclock_reset(vcpu);
7f1ea208 6930
f5f48ee1 6931 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6932 fx_free(vcpu);
e9b11c17
ZX		 6933 kvm_x86_ops->vcpu_free(vcpu);
6934}
6935
6936struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6937 unsigned int id)
6938{
6755bae8
ZA		 6939 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6940 printk_once(KERN_WARNING
6941 "kvm: SMP vm created on host with unstable TSC; "
6942 "guest TSC will not be reliable\n");
26e5215f
AK		 6943 return kvm_x86_ops->vcpu_create(kvm, id);
6944}
e9b11c17 6945
26e5215f
AK		 6946int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6947{
6948 int r;
e9b11c17 6949
0bed3b56 6950 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6951 r = vcpu_load(vcpu);
6952 if (r)
6953 return r;
57f252f2 6954 kvm_vcpu_reset(vcpu);
8a3c1a33 6955 kvm_mmu_setup(vcpu);
e9b11c17 6956 vcpu_put(vcpu);
e9b11c17 6957
26e5215f 6958 return r;
e9b11c17
ZX		 6959}
6960
42897d86
MT		 6961int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6962{
6963 int r;
8fe8ab46 6964 struct msr_data msr;
332967a3 6965 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6966
6967 r = vcpu_load(vcpu);
6968 if (r)
6969 return r;
8fe8ab46
WA		 6970 msr.data = 0x0;
6971 msr.index = MSR_IA32_TSC;
6972 msr.host_initiated = true;
6973 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6974 vcpu_put(vcpu);
6975
332967a3
AJ		 6976 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6977 KVMCLOCK_SYNC_PERIOD);
6978
42897d86
MT		 6979 return r;
6980}
6981
d40ccc62 6982void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6983{
9fc77441 6984 int r;
344d9588
GN		 6985 vcpu->arch.apf.msr_val = 0;
6986
9fc77441
MT		 6987 r = vcpu_load(vcpu);
6988 BUG_ON(r);
e9b11c17
ZX		 6989 kvm_mmu_unload(vcpu);
6990 vcpu_put(vcpu);
6991
98918833 6992 fx_free(vcpu);
e9b11c17
ZX		 6993 kvm_x86_ops->vcpu_free(vcpu);
6994}
6995
66450a21 6996void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6997{
7460fb4a
AK		 6998 atomic_set(&vcpu->arch.nmi_queued, 0);
6999 vcpu->arch.nmi_pending = 0;
448fa4a9 7000 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7001 kvm_clear_interrupt_queue(vcpu);
7002 kvm_clear_exception_queue(vcpu);
448fa4a9 7003
42dbaa5a 7004 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6f43ed01 7005 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7006 kvm_update_dr6(vcpu);
42dbaa5a 7007 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7008 kvm_update_dr7(vcpu);
42dbaa5a 7009
3842d135 7010 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7011 vcpu->arch.apf.msr_val = 0;
c9aaa895 7012 vcpu->arch.st.msr_val = 0;
3842d135 7013
12f9a48f
GC		 7014 kvmclock_reset(vcpu);
7015
af585b92
GN		 7016 kvm_clear_async_pf_completion_queue(vcpu);
7017 kvm_async_pf_hash_reset(vcpu);
7018 vcpu->arch.apf.halted = false;
3842d135 7019
f5132b01
GN		 7020 kvm_pmu_reset(vcpu);
7021
66f7b72e
JS		 7022 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7023 vcpu->arch.regs_avail = ~0;
7024 vcpu->arch.regs_dirty = ~0;
7025
57f252f2 7026 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 7027}
7028
66450a21
JK		 7029void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
7030{
7031 struct kvm_segment cs;
7032
7033 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7034 cs.selector = vector << 8;
7035 cs.base = vector << 12;
7036 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7037 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7038}
7039
13a34e06 7040int kvm_arch_hardware_enable(void)
e9b11c17 7041{
ca84d1a2
ZA		 7042 struct kvm *kvm;
7043 struct kvm_vcpu *vcpu;
7044 int i;
0dd6a6ed
ZA		 7045 int ret;
7046 u64 local_tsc;
7047 u64 max_tsc = 0;
7048 bool stable, backwards_tsc = false;
18863bdd
AK		 7049
7050 kvm_shared_msr_cpu_online();
13a34e06 7051 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7052 if (ret != 0)
7053 return ret;
7054
7055 local_tsc = native_read_tsc();
7056 stable = !check_tsc_unstable();
7057 list_for_each_entry(kvm, &vm_list, vm_list) {
7058 kvm_for_each_vcpu(i, vcpu, kvm) {
7059 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7060 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7061 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7062 backwards_tsc = true;
7063 if (vcpu->arch.last_host_tsc > max_tsc)
7064 max_tsc = vcpu->arch.last_host_tsc;
7065 }
7066 }
7067 }
7068
7069 /*
7070 * Sometimes, even reliable TSCs go backwards. This happens on
7071 * platforms that reset TSC during suspend or hibernate actions, but
7072 * maintain synchronization. We must compensate. Fortunately, we can
7073 * detect that condition here, which happens early in CPU bringup,
7074 * before any KVM threads can be running. Unfortunately, we can't
7075 * bring the TSCs fully up to date with real time, as we aren't yet far
7076 * enough into CPU bringup that we know how much real time has actually
7077 * elapsed; our helper function, get_kernel_ns() will be using boot
7078 * variables that haven't been updated yet.
7079 *
7080 * So we simply find the maximum observed TSC above, then record the
7081 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7082 * the adjustment will be applied. Note that we accumulate
7083 * adjustments, in case multiple suspend cycles happen before some VCPU
7084 * gets a chance to run again. In the event that no KVM threads get a
7085 * chance to run, we will miss the entire elapsed period, as we'll have
7086 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7087 * loose cycle time. This isn't too big a deal, since the loss will be
7088 * uniform across all VCPUs (not to mention the scenario is extremely
7089 * unlikely). It is possible that a second hibernate recovery happens
7090 * much faster than a first, causing the observed TSC here to be
7091 * smaller; this would require additional padding adjustment, which is
7092 * why we set last_host_tsc to the local tsc observed here.
7093 *
7094 * N.B. - this code below runs only on platforms with reliable TSC,
7095 * as that is the only way backwards_tsc is set above. Also note
7096 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7097 * have the same delta_cyc adjustment applied if backwards_tsc
7098 * is detected. Note further, this adjustment is only done once,
7099 * as we reset last_host_tsc on all VCPUs to stop this from being
7100 * called multiple times (one for each physical CPU bringup).
7101 *
4a969980 7102 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7103 * will be compensated by the logic in vcpu_load, which sets the TSC to
7104 * catchup mode. This will catchup all VCPUs to real time, but cannot
7105 * guarantee that they stay in perfect synchronization.
7106 */
7107 if (backwards_tsc) {
7108 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7109 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7110 list_for_each_entry(kvm, &vm_list, vm_list) {
7111 kvm_for_each_vcpu(i, vcpu, kvm) {
7112 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7113 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7114 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7115 }
7116
7117 /*
7118 * We have to disable TSC offset matching.. if you were
7119 * booting a VM while issuing an S4 host suspend....
7120 * you may have some problem. Solving this issue is
7121 * left as an exercise to the reader.
7122 */
7123 kvm->arch.last_tsc_nsec = 0;
7124 kvm->arch.last_tsc_write = 0;
7125 }
7126
7127 }
7128 return 0;
e9b11c17
ZX		 7129}
7130
13a34e06 7131void kvm_arch_hardware_disable(void)
e9b11c17 7132{
13a34e06
RK		 7133 kvm_x86_ops->hardware_disable();
7134 drop_user_return_notifiers();
e9b11c17
ZX		 7135}
7136
7137int kvm_arch_hardware_setup(void)
7138{
7139 return kvm_x86_ops->hardware_setup();
7140}
7141
7142void kvm_arch_hardware_unsetup(void)
7143{
7144 kvm_x86_ops->hardware_unsetup();
7145}
7146
7147void kvm_arch_check_processor_compat(void *rtn)
7148{
7149 kvm_x86_ops->check_processor_compatibility(rtn);
7150}
7151
3e515705
AK		 7152bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7153{
7154 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7155}
7156
54e9818f
GN		 7157struct static_key kvm_no_apic_vcpu __read_mostly;
7158
e9b11c17
ZX		 7159int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7160{
7161 struct page *page;
7162 struct kvm *kvm;
7163 int r;
7164
7165 BUG_ON(vcpu->kvm == NULL);
7166 kvm = vcpu->kvm;
7167
6aef266c 7168 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7169 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7170 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7171 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7172 else
a4535290 7173 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7174
7175 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7176 if (!page) {
7177 r = -ENOMEM;
7178 goto fail;
7179 }
ad312c7c 7180 vcpu->arch.pio_data = page_address(page);
e9b11c17 7181
cc578287 7182 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7183
e9b11c17
ZX		 7184 r = kvm_mmu_create(vcpu);
7185 if (r < 0)
7186 goto fail_free_pio_data;
7187
7188 if (irqchip_in_kernel(kvm)) {
7189 r = kvm_create_lapic(vcpu);
7190 if (r < 0)
7191 goto fail_mmu_destroy;
54e9818f
GN		 7192 } else
7193 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7194
890ca9ae
HY		 7195 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7196 GFP_KERNEL);
7197 if (!vcpu->arch.mce_banks) {
7198 r = -ENOMEM;
443c39bc 7199 goto fail_free_lapic;
890ca9ae
HY		 7200 }
7201 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7202
f1797359
WY		 7203 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7204 r = -ENOMEM;
f5f48ee1 7205 goto fail_free_mce_banks;
f1797359 7206 }
f5f48ee1 7207
66f7b72e
JS		 7208 r = fx_init(vcpu);
7209 if (r)
7210 goto fail_free_wbinvd_dirty_mask;
7211
ba904635 7212 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7213 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7214
7215 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7216 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7217
af585b92 7218 kvm_async_pf_hash_reset(vcpu);
f5132b01 7219 kvm_pmu_init(vcpu);
af585b92 7220
e9b11c17 7221 return 0;
66f7b72e
JS		 7222fail_free_wbinvd_dirty_mask:
7223 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7224fail_free_mce_banks:
7225 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7226fail_free_lapic:
7227 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7228fail_mmu_destroy:
7229 kvm_mmu_destroy(vcpu);
7230fail_free_pio_data:
ad312c7c 7231 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7232fail:
7233 return r;
7234}
7235
7236void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7237{
f656ce01
MT		 7238 int idx;
7239
f5132b01 7240 kvm_pmu_destroy(vcpu);
36cb93fd 7241 kfree(vcpu->arch.mce_banks);
e9b11c17 7242 kvm_free_lapic(vcpu);
f656ce01 7243 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7244 kvm_mmu_destroy(vcpu);
f656ce01 7245 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7246 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7247 if (!irqchip_in_kernel(vcpu->kvm))
7248 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7249}
d19a9cd2 7250
e790d9ef
RK		 7251void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7252{
ae97a3b8 7253 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7254}
7255
e08b9637 7256int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7257{
e08b9637
CO		 7258 if (type)
7259 return -EINVAL;
7260
f05e70ac 7261 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7262 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7263 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7264 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7265
5550af4d
SY		 7266 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7267 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7268 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7269 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7270 &kvm->arch.irq_sources_bitmap);
5550af4d 7271
038f8c11 7272 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7273 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7274 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7275
7276 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7277
7e44e449 7278 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7279 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7280
d89f5eff 7281 return 0;
d19a9cd2
ZX		 7282}
7283
7284static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7285{
9fc77441
MT		 7286 int r;
7287 r = vcpu_load(vcpu);
7288 BUG_ON(r);
d19a9cd2
ZX		 7289 kvm_mmu_unload(vcpu);
7290 vcpu_put(vcpu);
7291}
7292
7293static void kvm_free_vcpus(struct kvm *kvm)
7294{
7295 unsigned int i;
988a2cae 7296 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7297
7298 /*
7299 * Unpin any mmu pages first.
7300 */
af585b92
GN		 7301 kvm_for_each_vcpu(i, vcpu, kvm) {
7302 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7303 kvm_unload_vcpu_mmu(vcpu);
af585b92 7304 }
988a2cae
GN		 7305 kvm_for_each_vcpu(i, vcpu, kvm)
7306 kvm_arch_vcpu_free(vcpu);
7307
7308 mutex_lock(&kvm->lock);
7309 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7310 kvm->vcpus[i] = NULL;
d19a9cd2 7311
988a2cae
GN		 7312 atomic_set(&kvm->online_vcpus, 0);
7313 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7314}
7315
ad8ba2cd
SY		 7316void kvm_arch_sync_events(struct kvm *kvm)
7317{
332967a3 7318 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7319 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7320 kvm_free_all_assigned_devices(kvm);
aea924f6 7321 kvm_free_pit(kvm);
ad8ba2cd
SY		 7322}
7323
d19a9cd2
ZX		 7324void kvm_arch_destroy_vm(struct kvm *kvm)
7325{
27469d29
AH		 7326 if (current->mm == kvm->mm) {
7327 /*
7328 * Free memory regions allocated on behalf of userspace,
7329 * unless the the memory map has changed due to process exit
7330 * or fd copying.
7331 */
7332 struct kvm_userspace_memory_region mem;
7333 memset(&mem, 0, sizeof(mem));
7334 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7335 kvm_set_memory_region(kvm, &mem);
7336
7337 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7338 kvm_set_memory_region(kvm, &mem);
7339
7340 mem.slot = TSS_PRIVATE_MEMSLOT;
7341 kvm_set_memory_region(kvm, &mem);
7342 }
6eb55818 7343 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7344 kfree(kvm->arch.vpic);
7345 kfree(kvm->arch.vioapic);
d19a9cd2 7346 kvm_free_vcpus(kvm);
1e08ec4a 7347 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7348}
0de10343 7349
5587027c 7350void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7351 struct kvm_memory_slot *dont)
7352{
7353 int i;
7354
d89cc617
TY		 7355 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7356 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7357 kvm_kvfree(free->arch.rmap[i]);
7358 free->arch.rmap[i] = NULL;
77d11309 7359 }
d89cc617
TY		 7360 if (i == 0)
7361 continue;
7362
7363 if (!dont || free->arch.lpage_info[i - 1] !=
7364 dont->arch.lpage_info[i - 1]) {
7365 kvm_kvfree(free->arch.lpage_info[i - 1]);
7366 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7367 }
7368 }
7369}
7370
5587027c
AK		 7371int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7372 unsigned long npages)
db3fe4eb
TY		 7373{
7374 int i;
7375
d89cc617 7376 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7377 unsigned long ugfn;
7378 int lpages;
d89cc617 7379 int level = i + 1;
db3fe4eb
TY		 7380
7381 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7382 slot->base_gfn, level) + 1;
7383
d89cc617
TY		 7384 slot->arch.rmap[i] =
7385 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7386 if (!slot->arch.rmap[i])
77d11309 7387 goto out_free;
d89cc617
TY		 7388 if (i == 0)
7389 continue;
77d11309 7390
d89cc617
TY		 7391 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7392 sizeof(*slot->arch.lpage_info[i - 1]));
7393 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7394 goto out_free;
7395
7396 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7397 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7398 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7399 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7400 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7401 /*
7402 * If the gfn and userspace address are not aligned wrt each
7403 * other, or if explicitly asked to, disable large page
7404 * support for this slot
7405 */
7406 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7407 !kvm_largepages_enabled()) {
7408 unsigned long j;
7409
7410 for (j = 0; j < lpages; ++j)
d89cc617 7411 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7412 }
7413 }
7414
7415 return 0;
7416
7417out_free:
d89cc617
TY		 7418 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7419 kvm_kvfree(slot->arch.rmap[i]);
7420 slot->arch.rmap[i] = NULL;
7421 if (i == 0)
7422 continue;
7423
7424 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7425 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7426 }
7427 return -ENOMEM;
7428}
7429
e59dbe09
TY		 7430void kvm_arch_memslots_updated(struct kvm *kvm)
7431{
e6dff7d1
TY		 7432 /*
7433 * memslots->generation has been incremented.
7434 * mmio generation may have reached its maximum value.
7435 */
7436 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7437}
7438
f7784b8e
MT		 7439int kvm_arch_prepare_memory_region(struct kvm *kvm,
7440 struct kvm_memory_slot *memslot,
f7784b8e 7441 struct kvm_userspace_memory_region *mem,
7b6195a9 7442 enum kvm_mr_change change)
0de10343 7443{
7a905b14
TY		 7444 /*
7445 * Only private memory slots need to be mapped here since
7446 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7447 */
7b6195a9 7448 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7449 unsigned long userspace_addr;
604b38ac 7450
7a905b14
TY		 7451 /*
7452 * MAP_SHARED to prevent internal slot pages from being moved
7453 * by fork()/COW.
7454 */
7b6195a9 7455 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7456 PROT_READ | PROT_WRITE,
7457 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7458
7a905b14
TY		 7459 if (IS_ERR((void *)userspace_addr))
7460 return PTR_ERR((void *)userspace_addr);
604b38ac 7461
7a905b14 7462 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7463 }
7464
f7784b8e
MT		 7465 return 0;
7466}
7467
7468void kvm_arch_commit_memory_region(struct kvm *kvm,
7469 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7470 const struct kvm_memory_slot *old,
7471 enum kvm_mr_change change)
f7784b8e
MT		 7472{
7473
8482644a 7474 int nr_mmu_pages = 0;
f7784b8e 7475
8482644a 7476 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7477 int ret;
7478
8482644a
TY		 7479 ret = vm_munmap(old->userspace_addr,
7480 old->npages * PAGE_SIZE);
f7784b8e
MT		 7481 if (ret < 0)
7482 printk(KERN_WARNING
7483 "kvm_vm_ioctl_set_memory_region: "
7484 "failed to munmap memory\n");
7485 }
7486
48c0e4e9
XG		 7487 if (!kvm->arch.n_requested_mmu_pages)
7488 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7489
48c0e4e9 7490 if (nr_mmu_pages)
0de10343 7491 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7492 /*
7493 * Write protect all pages for dirty logging.
c126d94f
XG		 7494 *
7495 * All the sptes including the large sptes which point to this
7496 * slot are set to readonly. We can not create any new large
7497 * spte on this slot until the end of the logging.
7498 *
7499 * See the comments in fast_page_fault().
c972f3b1 7500 */
8482644a 7501 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7502 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7503}
1d737c8a 7504
2df72e9b 7505void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7506{
6ca18b69 7507 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7508}
7509
2df72e9b
MT		 7510void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7511 struct kvm_memory_slot *slot)
7512{
6ca18b69 7513 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7514}
7515
1d737c8a
ZX		 7516int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7517{
b6b8a145
JK		 7518 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7519 kvm_x86_ops->check_nested_events(vcpu, false);
7520
af585b92
GN		 7521 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7522 !vcpu->arch.apf.halted)
7523 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7524 || kvm_apic_has_events(vcpu)
6aef266c 7525 || vcpu->arch.pv.pv_unhalted
7460fb4a 7526 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7527 (kvm_arch_interrupt_allowed(vcpu) &&
7528 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7529}
5736199a 7530
b6d33834 7531int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7532{
b6d33834 7533 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7534}
78646121
GN		 7535
7536int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7537{
7538 return kvm_x86_ops->interrupt_allowed(vcpu);
7539}
229456fc 7540
f92653ee
JK		 7541bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7542{
7543 unsigned long current_rip = kvm_rip_read(vcpu) +
7544 get_segment_base(vcpu, VCPU_SREG_CS);
7545
7546 return current_rip == linear_rip;
7547}
7548EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7549
94fe45da
JK		 7550unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7551{
7552 unsigned long rflags;
7553
7554 rflags = kvm_x86_ops->get_rflags(vcpu);
7555 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7556 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7557 return rflags;
7558}
7559EXPORT_SYMBOL_GPL(kvm_get_rflags);
7560
6addfc42 7561static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7562{
7563 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7564 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7565 rflags |= X86_EFLAGS_TF;
94fe45da 7566 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7567}
7568
7569void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7570{
7571 __kvm_set_rflags(vcpu, rflags);
3842d135 7572 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7573}
7574EXPORT_SYMBOL_GPL(kvm_set_rflags);
7575
56028d08
GN		 7576void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7577{
7578 int r;
7579
fb67e14f 7580 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7581 work->wakeup_all)
56028d08
GN		 7582 return;
7583
7584 r = kvm_mmu_reload(vcpu);
7585 if (unlikely(r))
7586 return;
7587
fb67e14f
XG		 7588 if (!vcpu->arch.mmu.direct_map &&
7589 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7590 return;
7591
56028d08
GN		 7592 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7593}
7594
af585b92
GN		 7595static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7596{
7597 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7598}
7599
7600static inline u32 kvm_async_pf_next_probe(u32 key)
7601{
7602 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7603}
7604
7605static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7606{
7607 u32 key = kvm_async_pf_hash_fn(gfn);
7608
7609 while (vcpu->arch.apf.gfns[key] != ~0)
7610 key = kvm_async_pf_next_probe(key);
7611
7612 vcpu->arch.apf.gfns[key] = gfn;
7613}
7614
7615static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7616{
7617 int i;
7618 u32 key = kvm_async_pf_hash_fn(gfn);
7619
7620 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7621 (vcpu->arch.apf.gfns[key] != gfn &&
7622 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7623 key = kvm_async_pf_next_probe(key);
7624
7625 return key;
7626}
7627
7628bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7629{
7630 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7631}
7632
7633static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7634{
7635 u32 i, j, k;
7636
7637 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7638 while (true) {
7639 vcpu->arch.apf.gfns[i] = ~0;
7640 do {
7641 j = kvm_async_pf_next_probe(j);
7642 if (vcpu->arch.apf.gfns[j] == ~0)
7643 return;
7644 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7645 /*
7646 * k lies cyclically in ]i,j]
7647 * | i.k.j |
7648 * |....j i.k.| or |.k..j i...|
7649 */
7650 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7651 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7652 i = j;
7653 }
7654}
7655
7c90705b
GN		 7656static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7657{
7658
7659 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7660 sizeof(val));
7661}
7662
af585b92
GN		 7663void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7664 struct kvm_async_pf *work)
7665{
6389ee94
AK		 7666 struct x86_exception fault;
7667
7c90705b 7668 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7669 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7670
7671 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7672 (vcpu->arch.apf.send_user_only &&
7673 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7674 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7675 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7676 fault.vector = PF_VECTOR;
7677 fault.error_code_valid = true;
7678 fault.error_code = 0;
7679 fault.nested_page_fault = false;
7680 fault.address = work->arch.token;
7681 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7682 }
af585b92
GN		 7683}
7684
7685void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7686 struct kvm_async_pf *work)
7687{
6389ee94
AK		 7688 struct x86_exception fault;
7689
7c90705b 7690 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7691 if (work->wakeup_all)
7c90705b
GN		 7692 work->arch.token = ~0; /* broadcast wakeup */
7693 else
7694 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7695
7696 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7697 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7698 fault.vector = PF_VECTOR;
7699 fault.error_code_valid = true;
7700 fault.error_code = 0;
7701 fault.nested_page_fault = false;
7702 fault.address = work->arch.token;
7703 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7704 }
e6d53e3b 7705 vcpu->arch.apf.halted = false;
a4fa1635 7706 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7707}
7708
7709bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7710{
7711 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7712 return true;
7713 else
7714 return !kvm_event_needs_reinjection(vcpu) &&
7715 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7716}
7717
e0f0bbc5
AW		 7718void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7719{
7720 atomic_inc(&kvm->arch.noncoherent_dma_count);
7721}
7722EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7723
7724void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7725{
7726 atomic_dec(&kvm->arch.noncoherent_dma_count);
7727}
7728EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7729
7730bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7731{
7732 return atomic_read(&kvm->arch.noncoherent_dma_count);
7733}
7734EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7735
229456fc
MT		 7736EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7737EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7738EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7739EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7740EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7741EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7742EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7743EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7744EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7745EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7746EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7747EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7748EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 7749EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
Linux 6.x block layer and io_uring tree(s)