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KVM: x86: Do not re-{try,execute} after failed emulation in L2
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
4c27625b 117unsigned int min_timer_period_us = 200;
9ed96e87
MT		 118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
c5ce8235 141EXPORT_SYMBOL_GPL(lapic_timer_advance_ns);
d0659d94 142
52004014
FW		 143static bool __read_mostly vector_hashing = true;
144module_param(vector_hashing, bool, S_IRUGO);
145
c4ae60e4
LA		 146bool __read_mostly enable_vmware_backdoor = false;
147module_param(enable_vmware_backdoor, bool, S_IRUGO);
148EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
149
6c86eedc
WL		 150static bool __read_mostly force_emulation_prefix = false;
151module_param(force_emulation_prefix, bool, S_IRUGO);
152
18863bdd
AK		 153#define KVM_NR_SHARED_MSRS 16
154
155struct kvm_shared_msrs_global {
156 int nr;
2bf78fa7 157 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 158};
159
160struct kvm_shared_msrs {
161 struct user_return_notifier urn;
162 bool registered;
2bf78fa7
SY		 163 struct kvm_shared_msr_values {
164 u64 host;
165 u64 curr;
166 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 167};
168
169static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 170static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 171
417bc304 172struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 173 { "pf_fixed", VCPU_STAT(pf_fixed) },
174 { "pf_guest", VCPU_STAT(pf_guest) },
175 { "tlb_flush", VCPU_STAT(tlb_flush) },
176 { "invlpg", VCPU_STAT(invlpg) },
177 { "exits", VCPU_STAT(exits) },
178 { "io_exits", VCPU_STAT(io_exits) },
179 { "mmio_exits", VCPU_STAT(mmio_exits) },
180 { "signal_exits", VCPU_STAT(signal_exits) },
181 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 182 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 183 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 184 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 185 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 186 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 187 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 188 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 189 { "request_irq", VCPU_STAT(request_irq_exits) },
190 { "irq_exits", VCPU_STAT(irq_exits) },
191 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 192 { "fpu_reload", VCPU_STAT(fpu_reload) },
193 { "insn_emulation", VCPU_STAT(insn_emulation) },
194 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 195 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 196 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 197 { "req_event", VCPU_STAT(req_event) },
c595ceee 198 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 199 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
200 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
201 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
202 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
203 { "mmu_flooded", VM_STAT(mmu_flooded) },
204 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 205 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 206 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 207 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 208 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 209 { "max_mmu_page_hash_collisions",
210 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 211 { NULL }
212};
213
2acf923e
DC		 214u64 __read_mostly host_xcr0;
215
b6785def 216static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 217
af585b92
GN		 218static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
219{
220 int i;
221 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
222 vcpu->arch.apf.gfns[i] = ~0;
223}
224
18863bdd
AK		 225static void kvm_on_user_return(struct user_return_notifier *urn)
226{
227 unsigned slot;
18863bdd
AK		 228 struct kvm_shared_msrs *locals
229 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 230 struct kvm_shared_msr_values *values;
1650b4eb
IA		 231 unsigned long flags;
232
233 /*
234 * Disabling irqs at this point since the following code could be
235 * interrupted and executed through kvm_arch_hardware_disable()
236 */
237 local_irq_save(flags);
238 if (locals->registered) {
239 locals->registered = false;
240 user_return_notifier_unregister(urn);
241 }
242 local_irq_restore(flags);
18863bdd 243 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 244 values = &locals->values[slot];
245 if (values->host != values->curr) {
246 wrmsrl(shared_msrs_global.msrs[slot], values->host);
247 values->curr = values->host;
18863bdd
AK		 248 }
249 }
18863bdd
AK		 250}
251
2bf78fa7 252static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 253{
18863bdd 254 u64 value;
013f6a5d
MT		 255 unsigned int cpu = smp_processor_id();
256 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 257
2bf78fa7
SY		 258 /* only read, and nobody should modify it at this time,
259 * so don't need lock */
260 if (slot >= shared_msrs_global.nr) {
261 printk(KERN_ERR "kvm: invalid MSR slot!");
262 return;
263 }
264 rdmsrl_safe(msr, &value);
265 smsr->values[slot].host = value;
266 smsr->values[slot].curr = value;
267}
268
269void kvm_define_shared_msr(unsigned slot, u32 msr)
270{
0123be42 271 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 272 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 273 if (slot >= shared_msrs_global.nr)
274 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 275}
276EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
277
278static void kvm_shared_msr_cpu_online(void)
279{
280 unsigned i;
18863bdd
AK		 281
282 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 283 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 284}
285
8b3c3104 286int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 287{
013f6a5d
MT		 288 unsigned int cpu = smp_processor_id();
289 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 290 int err;
18863bdd 291
2bf78fa7 292 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 293 return 0;
2bf78fa7 294 smsr->values[slot].curr = value;
8b3c3104
AH		 295 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
296 if (err)
297 return 1;
298
18863bdd
AK		 299 if (!smsr->registered) {
300 smsr->urn.on_user_return = kvm_on_user_return;
301 user_return_notifier_register(&smsr->urn);
302 smsr->registered = true;
303 }
8b3c3104 304 return 0;
18863bdd
AK		 305}
306EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
307
13a34e06 308static void drop_user_return_notifiers(void)
3548bab5 309{
013f6a5d
MT		 310 unsigned int cpu = smp_processor_id();
311 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 312
313 if (smsr->registered)
314 kvm_on_user_return(&smsr->urn);
315}
316
6866b83e
CO		 317u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
318{
8a5a87d9 319 return vcpu->arch.apic_base;
6866b83e
CO		 320}
321EXPORT_SYMBOL_GPL(kvm_get_apic_base);
322
58871649
JM		 323enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
324{
325 return kvm_apic_mode(kvm_get_apic_base(vcpu));
326}
327EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
328
58cb628d
JK		 329int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
330{
58871649
JM		 331 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
332 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 333 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
334 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 335
58871649 336 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 337 return 1;
58871649
JM		 338 if (!msr_info->host_initiated) {
339 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
340 return 1;
341 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
342 return 1;
343 }
58cb628d
JK		 344
345 kvm_lapic_set_base(vcpu, msr_info->data);
346 return 0;
6866b83e
CO		 347}
348EXPORT_SYMBOL_GPL(kvm_set_apic_base);
349
2605fc21 350asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 351{
352 /* Fault while not rebooting. We want the trace. */
353 BUG();
354}
355EXPORT_SYMBOL_GPL(kvm_spurious_fault);
356
3fd28fce
ED		 357#define EXCPT_BENIGN 0
358#define EXCPT_CONTRIBUTORY 1
359#define EXCPT_PF 2
360
361static int exception_class(int vector)
362{
363 switch (vector) {
364 case PF_VECTOR:
365 return EXCPT_PF;
366 case DE_VECTOR:
367 case TS_VECTOR:
368 case NP_VECTOR:
369 case SS_VECTOR:
370 case GP_VECTOR:
371 return EXCPT_CONTRIBUTORY;
372 default:
373 break;
374 }
375 return EXCPT_BENIGN;
376}
377
d6e8c854
NA		 378#define EXCPT_FAULT 0
379#define EXCPT_TRAP 1
380#define EXCPT_ABORT 2
381#define EXCPT_INTERRUPT 3
382
383static int exception_type(int vector)
384{
385 unsigned int mask;
386
387 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
388 return EXCPT_INTERRUPT;
389
390 mask = 1 << vector;
391
392 /* #DB is trap, as instruction watchpoints are handled elsewhere */
393 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
394 return EXCPT_TRAP;
395
396 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
397 return EXCPT_ABORT;
398
399 /* Reserved exceptions will result in fault */
400 return EXCPT_FAULT;
401}
402
3fd28fce 403static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 404 unsigned nr, bool has_error, u32 error_code,
405 bool reinject)
3fd28fce
ED		 406{
407 u32 prev_nr;
408 int class1, class2;
409
3842d135
AK		 410 kvm_make_request(KVM_REQ_EVENT, vcpu);
411
664f8e26 412 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 413 queue:
3ffb2468
NA		 414 if (has_error && !is_protmode(vcpu))
415 has_error = false;
664f8e26
WL		 416 if (reinject) {
417 /*
418 * On vmentry, vcpu->arch.exception.pending is only
419 * true if an event injection was blocked by
420 * nested_run_pending. In that case, however,
421 * vcpu_enter_guest requests an immediate exit,
422 * and the guest shouldn't proceed far enough to
423 * need reinjection.
424 */
425 WARN_ON_ONCE(vcpu->arch.exception.pending);
426 vcpu->arch.exception.injected = true;
427 } else {
428 vcpu->arch.exception.pending = true;
429 vcpu->arch.exception.injected = false;
430 }
3fd28fce
ED		 431 vcpu->arch.exception.has_error_code = has_error;
432 vcpu->arch.exception.nr = nr;
433 vcpu->arch.exception.error_code = error_code;
434 return;
435 }
436
437 /* to check exception */
438 prev_nr = vcpu->arch.exception.nr;
439 if (prev_nr == DF_VECTOR) {
440 /* triple fault -> shutdown */
a8eeb04a 441 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 442 return;
443 }
444 class1 = exception_class(prev_nr);
445 class2 = exception_class(nr);
446 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
447 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 448 /*
449 * Generate double fault per SDM Table 5-5. Set
450 * exception.pending = true so that the double fault
451 * can trigger a nested vmexit.
452 */
3fd28fce 453 vcpu->arch.exception.pending = true;
664f8e26 454 vcpu->arch.exception.injected = false;
3fd28fce
ED		 455 vcpu->arch.exception.has_error_code = true;
456 vcpu->arch.exception.nr = DF_VECTOR;
457 vcpu->arch.exception.error_code = 0;
458 } else
459 /* replace previous exception with a new one in a hope
460 that instruction re-execution will regenerate lost
461 exception */
462 goto queue;
463}
464
298101da
AK		 465void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
466{
ce7ddec4 467 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 468}
469EXPORT_SYMBOL_GPL(kvm_queue_exception);
470
ce7ddec4
JR		 471void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
472{
473 kvm_multiple_exception(vcpu, nr, false, 0, true);
474}
475EXPORT_SYMBOL_GPL(kvm_requeue_exception);
476
6affcbed 477int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 478{
db8fcefa
AP		 479 if (err)
480 kvm_inject_gp(vcpu, 0);
481 else
6affcbed
KH		 482 return kvm_skip_emulated_instruction(vcpu);
483
484 return 1;
db8fcefa
AP		 485}
486EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 487
6389ee94 488void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 489{
490 ++vcpu->stat.pf_guest;
adfe20fb
WL		 491 vcpu->arch.exception.nested_apf =
492 is_guest_mode(vcpu) && fault->async_page_fault;
493 if (vcpu->arch.exception.nested_apf)
494 vcpu->arch.apf.nested_apf_token = fault->address;
495 else
496 vcpu->arch.cr2 = fault->address;
6389ee94 497 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 498}
27d6c865 499EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 500
ef54bcfe 501static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 502{
6389ee94
AK		 503 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
504 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 505 else
6389ee94 506 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 507
508 return fault->nested_page_fault;
d4f8cf66
JR		 509}
510
3419ffc8
SY		 511void kvm_inject_nmi(struct kvm_vcpu *vcpu)
512{
7460fb4a
AK		 513 atomic_inc(&vcpu->arch.nmi_queued);
514 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 515}
516EXPORT_SYMBOL_GPL(kvm_inject_nmi);
517
298101da
AK		 518void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
519{
ce7ddec4 520 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 521}
522EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
523
ce7ddec4
JR		 524void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
525{
526 kvm_multiple_exception(vcpu, nr, true, error_code, true);
527}
528EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
529
0a79b009
AK		 530/*
531 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
532 * a #GP and return false.
533 */
534bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 535{
0a79b009
AK		 536 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
537 return true;
538 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
539 return false;
298101da 540}
0a79b009 541EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 542
16f8a6f9
NA		 543bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
544{
545 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
546 return true;
547
548 kvm_queue_exception(vcpu, UD_VECTOR);
549 return false;
550}
551EXPORT_SYMBOL_GPL(kvm_require_dr);
552
ec92fe44
JR		 553/*
554 * This function will be used to read from the physical memory of the currently
54bf36aa 555 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 556 * can read from guest physical or from the guest's guest physical memory.
557 */
558int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
559 gfn_t ngfn, void *data, int offset, int len,
560 u32 access)
561{
54987b7a 562 struct x86_exception exception;
ec92fe44
JR		 563 gfn_t real_gfn;
564 gpa_t ngpa;
565
566 ngpa = gfn_to_gpa(ngfn);
54987b7a 567 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 568 if (real_gfn == UNMAPPED_GVA)
569 return -EFAULT;
570
571 real_gfn = gpa_to_gfn(real_gfn);
572
54bf36aa 573 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 574}
575EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
576
69b0049a 577static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 578 void *data, int offset, int len, u32 access)
579{
580 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
581 data, offset, len, access);
582}
583
a03490ed
CO		 584/*
585 * Load the pae pdptrs. Return true is they are all valid.
586 */
ff03a073 587int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 588{
589 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
590 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
591 int i;
592 int ret;
ff03a073 593 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 594
ff03a073
JR		 595 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
596 offset * sizeof(u64), sizeof(pdpte),
597 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 598 if (ret < 0) {
599 ret = 0;
600 goto out;
601 }
602 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 603 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 604 (pdpte[i] &
605 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 606 ret = 0;
607 goto out;
608 }
609 }
610 ret = 1;
611
ff03a073 612 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 613 __set_bit(VCPU_EXREG_PDPTR,
614 (unsigned long *)&vcpu->arch.regs_avail);
615 __set_bit(VCPU_EXREG_PDPTR,
616 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 617out:
a03490ed
CO		 618
619 return ret;
620}
cc4b6871 621EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 622
9ed38ffa 623bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 624{
ff03a073 625 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 626 bool changed = true;
3d06b8bf
JR		 627 int offset;
628 gfn_t gfn;
d835dfec
AK		 629 int r;
630
631 if (is_long_mode(vcpu) || !is_pae(vcpu))
632 return false;
633
6de4f3ad
AK		 634 if (!test_bit(VCPU_EXREG_PDPTR,
635 (unsigned long *)&vcpu->arch.regs_avail))
636 return true;
637
a512177e
PB		 638 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
639 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 640 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
641 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 642 if (r < 0)
643 goto out;
ff03a073 644 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 645out:
d835dfec
AK		 646
647 return changed;
648}
9ed38ffa 649EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 650
49a9b07e 651int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 652{
aad82703 653 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 654 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 655
f9a48e6a
AK		 656 cr0 |= X86_CR0_ET;
657
ab344828 658#ifdef CONFIG_X86_64
0f12244f
GN		 659 if (cr0 & 0xffffffff00000000UL)
660 return 1;
ab344828
GN		 661#endif
662
663 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 664
0f12244f
GN		 665 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
666 return 1;
a03490ed 667
0f12244f
GN		 668 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
669 return 1;
a03490ed
CO		 670
671 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
672#ifdef CONFIG_X86_64
f6801dff 673 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 674 int cs_db, cs_l;
675
0f12244f
GN		 676 if (!is_pae(vcpu))
677 return 1;
a03490ed 678 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 679 if (cs_l)
680 return 1;
a03490ed
CO		 681 } else
682#endif
ff03a073 683 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 684 kvm_read_cr3(vcpu)))
0f12244f 685 return 1;
a03490ed
CO		 686 }
687
ad756a16
MJ		 688 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
689 return 1;
690
a03490ed 691 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 692
d170c419 693 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 694 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 695 kvm_async_pf_hash_reset(vcpu);
696 }
e5f3f027 697
aad82703
SY		 698 if ((cr0 ^ old_cr0) & update_bits)
699 kvm_mmu_reset_context(vcpu);
b18d5431 700
879ae188
LE		 701 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
702 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
703 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 704 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
705
0f12244f
GN		 706 return 0;
707}
2d3ad1f4 708EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 709
2d3ad1f4 710void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 711{
49a9b07e 712 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 713}
2d3ad1f4 714EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 715
42bdf991
MT		 716static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
717{
718 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
719 !vcpu->guest_xcr0_loaded) {
720 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 721 if (vcpu->arch.xcr0 != host_xcr0)
722 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 723 vcpu->guest_xcr0_loaded = 1;
724 }
725}
726
727static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
728{
729 if (vcpu->guest_xcr0_loaded) {
730 if (vcpu->arch.xcr0 != host_xcr0)
731 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
732 vcpu->guest_xcr0_loaded = 0;
733 }
734}
735
69b0049a 736static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 737{
56c103ec
LJ		 738 u64 xcr0 = xcr;
739 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 740 u64 valid_bits;
2acf923e
DC		 741
742 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
743 if (index != XCR_XFEATURE_ENABLED_MASK)
744 return 1;
d91cab78 745 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 746 return 1;
d91cab78 747 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 748 return 1;
46c34cb0
PB		 749
750 /*
751 * Do not allow the guest to set bits that we do not support
752 * saving. However, xcr0 bit 0 is always set, even if the
753 * emulated CPU does not support XSAVE (see fx_init).
754 */
d91cab78 755 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 756 if (xcr0 & ~valid_bits)
2acf923e 757 return 1;
46c34cb0 758
d91cab78
DH		 759 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
760 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 761 return 1;
762
d91cab78
DH		 763 if (xcr0 & XFEATURE_MASK_AVX512) {
764 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 765 return 1;
d91cab78 766 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 767 return 1;
768 }
2acf923e 769 vcpu->arch.xcr0 = xcr0;
56c103ec 770
d91cab78 771 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 772 kvm_update_cpuid(vcpu);
2acf923e
DC		 773 return 0;
774}
775
776int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
777{
764bcbc5
Z		 778 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
779 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 780 kvm_inject_gp(vcpu, 0);
781 return 1;
782 }
783 return 0;
784}
785EXPORT_SYMBOL_GPL(kvm_set_xcr);
786
a83b29c6 787int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 788{
fc78f519 789 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 790 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 791 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 792
0f12244f
GN		 793 if (cr4 & CR4_RESERVED_BITS)
794 return 1;
a03490ed 795
d6321d49 796 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 797 return 1;
798
d6321d49 799 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 800 return 1;
801
d6321d49 802 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 803 return 1;
804
d6321d49 805 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 806 return 1;
807
d6321d49 808 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 809 return 1;
810
fd8cb433 811 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 812 return 1;
813
ae3e61e1
PB		 814 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
815 return 1;
816
a03490ed 817 if (is_long_mode(vcpu)) {
0f12244f
GN		 818 if (!(cr4 & X86_CR4_PAE))
819 return 1;
a2edf57f
AK		 820 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
821 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 822 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
823 kvm_read_cr3(vcpu)))
0f12244f
GN		 824 return 1;
825
ad756a16 826 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 827 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 828 return 1;
829
830 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
831 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
832 return 1;
833 }
834
5e1746d6 835 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 836 return 1;
a03490ed 837
ad756a16
MJ		 838 if (((cr4 ^ old_cr4) & pdptr_bits) ||
839 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 840 kvm_mmu_reset_context(vcpu);
0f12244f 841
b9baba86 842 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 843 kvm_update_cpuid(vcpu);
2acf923e 844
0f12244f
GN		 845 return 0;
846}
2d3ad1f4 847EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 848
2390218b 849int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 850{
ade61e28 851 bool skip_tlb_flush = false;
ac146235 852#ifdef CONFIG_X86_64
c19986fe
JS		 853 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
854
ade61e28 855 if (pcid_enabled) {
208320ba
JS		 856 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
857 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 858 }
ac146235 859#endif
9d88fca7 860
9f8fe504 861 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 862 if (!skip_tlb_flush) {
863 kvm_mmu_sync_roots(vcpu);
ade61e28 864 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 865 }
0f12244f 866 return 0;
d835dfec
AK		 867 }
868
d1cd3ce9 869 if (is_long_mode(vcpu) &&
a780a3ea 870 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9
YZ		 871 return 1;
872 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 873 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 874 return 1;
a03490ed 875
ade61e28 876 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 877 vcpu->arch.cr3 = cr3;
aff48baa 878 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
7c390d35 879
0f12244f
GN		 880 return 0;
881}
2d3ad1f4 882EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 883
eea1cff9 884int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 885{
0f12244f
GN		 886 if (cr8 & CR8_RESERVED_BITS)
887 return 1;
35754c98 888 if (lapic_in_kernel(vcpu))
a03490ed
CO		 889 kvm_lapic_set_tpr(vcpu, cr8);
890 else
ad312c7c 891 vcpu->arch.cr8 = cr8;
0f12244f
GN		 892 return 0;
893}
2d3ad1f4 894EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 895
2d3ad1f4 896unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 897{
35754c98 898 if (lapic_in_kernel(vcpu))
a03490ed
CO		 899 return kvm_lapic_get_cr8(vcpu);
900 else
ad312c7c 901 return vcpu->arch.cr8;
a03490ed 902}
2d3ad1f4 903EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 904
ae561ede
NA		 905static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
906{
907 int i;
908
909 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
910 for (i = 0; i < KVM_NR_DB_REGS; i++)
911 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
912 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
913 }
914}
915
73aaf249
JK		 916static void kvm_update_dr6(struct kvm_vcpu *vcpu)
917{
918 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
919 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
920}
921
c8639010
JK		 922static void kvm_update_dr7(struct kvm_vcpu *vcpu)
923{
924 unsigned long dr7;
925
926 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
927 dr7 = vcpu->arch.guest_debug_dr7;
928 else
929 dr7 = vcpu->arch.dr7;
930 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 931 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
932 if (dr7 & DR7_BP_EN_MASK)
933 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 934}
935
6f43ed01
NA		 936static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
937{
938 u64 fixed = DR6_FIXED_1;
939
d6321d49 940 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 941 fixed |= DR6_RTM;
942 return fixed;
943}
944
338dbc97 945static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 946{
947 switch (dr) {
948 case 0 ... 3:
949 vcpu->arch.db[dr] = val;
950 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
951 vcpu->arch.eff_db[dr] = val;
952 break;
953 case 4:
020df079
GN		 954 /* fall through */
955 case 6:
338dbc97
GN		 956 if (val & 0xffffffff00000000ULL)
957 return -1; /* #GP */
6f43ed01 958 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 959 kvm_update_dr6(vcpu);
020df079
GN		 960 break;
961 case 5:
020df079
GN		 962 /* fall through */
963 default: /* 7 */
338dbc97
GN		 964 if (val & 0xffffffff00000000ULL)
965 return -1; /* #GP */
020df079 966 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 967 kvm_update_dr7(vcpu);
020df079
GN		 968 break;
969 }
970
971 return 0;
972}
338dbc97
GN		 973
974int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
975{
16f8a6f9 976 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 977 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 978 return 1;
979 }
980 return 0;
338dbc97 981}
020df079
GN		 982EXPORT_SYMBOL_GPL(kvm_set_dr);
983
16f8a6f9 984int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 985{
986 switch (dr) {
987 case 0 ... 3:
988 *val = vcpu->arch.db[dr];
989 break;
990 case 4:
020df079
GN		 991 /* fall through */
992 case 6:
73aaf249
JK		 993 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
994 *val = vcpu->arch.dr6;
995 else
996 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 997 break;
998 case 5:
020df079
GN		 999 /* fall through */
1000 default: /* 7 */
1001 *val = vcpu->arch.dr7;
1002 break;
1003 }
338dbc97
GN		 1004 return 0;
1005}
020df079
GN		 1006EXPORT_SYMBOL_GPL(kvm_get_dr);
1007
022cd0e8
AK		 1008bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1009{
1010 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
1011 u64 data;
1012 int err;
1013
c6702c9d 1014 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1015 if (err)
1016 return err;
1017 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
1018 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
1019 return err;
1020}
1021EXPORT_SYMBOL_GPL(kvm_rdpmc);
1022
043405e1
CO		 1023/*
1024 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1025 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1026 *
1027 * This list is modified at module load time to reflect the
e3267cbb 1028 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1029 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1030 * may depend on host virtualization features rather than host cpu features.
043405e1 1031 */
e3267cbb 1032
043405e1
CO		 1033static u32 msrs_to_save[] = {
1034 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1035 MSR_STAR,
043405e1
CO		 1036#ifdef CONFIG_X86_64
1037 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1038#endif
b3897a49 1039 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1040 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1041 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1042};
1043
1044static unsigned num_msrs_to_save;
1045
62ef68bb
PB		 1046static u32 emulated_msrs[] = {
1047 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1048 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1049 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1050 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1051 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1052 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1053 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1054 HV_X64_MSR_RESET,
11c4b1ca 1055 HV_X64_MSR_VP_INDEX,
9eec50b8 1056 HV_X64_MSR_VP_RUNTIME,
5c919412 1057 HV_X64_MSR_SCONTROL,
1f4b34f8 1058 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1059 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1060 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1061 HV_X64_MSR_TSC_EMULATION_STATUS,
1062
1063 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1064 MSR_KVM_PV_EOI_EN,
1065
ba904635 1066 MSR_IA32_TSC_ADJUST,
a3e06bbe 1067 MSR_IA32_TSCDEADLINE,
043405e1 1068 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1069 MSR_IA32_MCG_STATUS,
1070 MSR_IA32_MCG_CTL,
c45dcc71 1071 MSR_IA32_MCG_EXT_CTL,
64d60670 1072 MSR_IA32_SMBASE,
52797bf9 1073 MSR_SMI_COUNT,
db2336a8
KH		 1074 MSR_PLATFORM_INFO,
1075 MSR_MISC_FEATURES_ENABLES,
bc226f07 1076 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO		 1077};
1078
62ef68bb
PB		 1079static unsigned num_emulated_msrs;
1080
801e459a
TL		 1081/*
1082 * List of msr numbers which are used to expose MSR-based features that
1083 * can be used by a hypervisor to validate requested CPU features.
1084 */
1085static u32 msr_based_features[] = {
1389309c
PB		 1086 MSR_IA32_VMX_BASIC,
1087 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1088 MSR_IA32_VMX_PINBASED_CTLS,
1089 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1090 MSR_IA32_VMX_PROCBASED_CTLS,
1091 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1092 MSR_IA32_VMX_EXIT_CTLS,
1093 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1094 MSR_IA32_VMX_ENTRY_CTLS,
1095 MSR_IA32_VMX_MISC,
1096 MSR_IA32_VMX_CR0_FIXED0,
1097 MSR_IA32_VMX_CR0_FIXED1,
1098 MSR_IA32_VMX_CR4_FIXED0,
1099 MSR_IA32_VMX_CR4_FIXED1,
1100 MSR_IA32_VMX_VMCS_ENUM,
1101 MSR_IA32_VMX_PROCBASED_CTLS2,
1102 MSR_IA32_VMX_EPT_VPID_CAP,
1103 MSR_IA32_VMX_VMFUNC,
1104
d1d93fa9 1105 MSR_F10H_DECFG,
518e7b94 1106 MSR_IA32_UCODE_REV,
cd283252 1107 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1108};
1109
1110static unsigned int num_msr_based_features;
1111
5b76a3cf
PB		 1112u64 kvm_get_arch_capabilities(void)
1113{
1114 u64 data;
1115
1116 rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, &data);
1117
1118 /*
1119 * If we're doing cache flushes (either "always" or "cond")
1120 * we will do one whenever the guest does a vmlaunch/vmresume.
1121 * If an outer hypervisor is doing the cache flush for us
1122 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1123 * capability to the guest too, and if EPT is disabled we're not
1124 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1125 * require a nested hypervisor to do a flush of its own.
1126 */
1127 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1128 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1129
1130 return data;
1131}
1132EXPORT_SYMBOL_GPL(kvm_get_arch_capabilities);
1133
66421c1e
WL		 1134static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1135{
1136 switch (msr->index) {
cd283252 1137 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1138 msr->data = kvm_get_arch_capabilities();
1139 break;
1140 case MSR_IA32_UCODE_REV:
cd283252 1141 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1142 break;
66421c1e
WL		 1143 default:
1144 if (kvm_x86_ops->get_msr_feature(msr))
1145 return 1;
1146 }
1147 return 0;
1148}
1149
801e459a
TL		 1150static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1151{
1152 struct kvm_msr_entry msr;
66421c1e 1153 int r;
801e459a
TL		 1154
1155 msr.index = index;
66421c1e
WL		 1156 r = kvm_get_msr_feature(&msr);
1157 if (r)
1158 return r;
801e459a
TL		 1159
1160 *data = msr.data;
1161
1162 return 0;
1163}
1164
384bb783 1165bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1166{
b69e8cae 1167 if (efer & efer_reserved_bits)
384bb783 1168 return false;
15c4a640 1169
1b4d56b8 1170 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1171 return false;
1b2fd70c 1172
1b4d56b8 1173 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1174 return false;
d8017474 1175
384bb783
JK		 1176 return true;
1177}
1178EXPORT_SYMBOL_GPL(kvm_valid_efer);
1179
1180static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1181{
1182 u64 old_efer = vcpu->arch.efer;
1183
1184 if (!kvm_valid_efer(vcpu, efer))
1185 return 1;
1186
1187 if (is_paging(vcpu)
1188 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1189 return 1;
1190
15c4a640 1191 efer &= ~EFER_LMA;
f6801dff 1192 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1193
a3d204e2
SY		 1194 kvm_x86_ops->set_efer(vcpu, efer);
1195
aad82703
SY		 1196 /* Update reserved bits */
1197 if ((efer ^ old_efer) & EFER_NX)
1198 kvm_mmu_reset_context(vcpu);
1199
b69e8cae 1200 return 0;
15c4a640
CO		 1201}
1202
f2b4b7dd
JR		 1203void kvm_enable_efer_bits(u64 mask)
1204{
1205 efer_reserved_bits &= ~mask;
1206}
1207EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1208
15c4a640
CO		 1209/*
1210 * Writes msr value into into the appropriate "register".
1211 * Returns 0 on success, non-0 otherwise.
1212 * Assumes vcpu_load() was already called.
1213 */
8fe8ab46 1214int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1215{
854e8bb1
NA		 1216 switch (msr->index) {
1217 case MSR_FS_BASE:
1218 case MSR_GS_BASE:
1219 case MSR_KERNEL_GS_BASE:
1220 case MSR_CSTAR:
1221 case MSR_LSTAR:
fd8cb433 1222 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1223 return 1;
1224 break;
1225 case MSR_IA32_SYSENTER_EIP:
1226 case MSR_IA32_SYSENTER_ESP:
1227 /*
1228 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1229 * non-canonical address is written on Intel but not on
1230 * AMD (which ignores the top 32-bits, because it does
1231 * not implement 64-bit SYSENTER).
1232 *
1233 * 64-bit code should hence be able to write a non-canonical
1234 * value on AMD. Making the address canonical ensures that
1235 * vmentry does not fail on Intel after writing a non-canonical
1236 * value, and that something deterministic happens if the guest
1237 * invokes 64-bit SYSENTER.
1238 */
fd8cb433 1239 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1240 }
8fe8ab46 1241 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1242}
854e8bb1 1243EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1244
313a3dc7
CO		 1245/*
1246 * Adapt set_msr() to msr_io()'s calling convention
1247 */
609e36d3
PB		 1248static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1249{
1250 struct msr_data msr;
1251 int r;
1252
1253 msr.index = index;
1254 msr.host_initiated = true;
1255 r = kvm_get_msr(vcpu, &msr);
1256 if (r)
1257 return r;
1258
1259 *data = msr.data;
1260 return 0;
1261}
1262
313a3dc7
CO		 1263static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1264{
8fe8ab46
WA		 1265 struct msr_data msr;
1266
1267 msr.data = *data;
1268 msr.index = index;
1269 msr.host_initiated = true;
1270 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1271}
1272
16e8d74d
MT		 1273#ifdef CONFIG_X86_64
1274struct pvclock_gtod_data {
1275 seqcount_t seq;
1276
1277 struct { /* extract of a clocksource struct */
1278 int vclock_mode;
a5a1d1c2
TG		 1279 u64 cycle_last;
1280 u64 mask;
16e8d74d
MT		 1281 u32 mult;
1282 u32 shift;
1283 } clock;
1284
cbcf2dd3
TG		 1285 u64 boot_ns;
1286 u64 nsec_base;
55dd00a7 1287 u64 wall_time_sec;
16e8d74d
MT		 1288};
1289
1290static struct pvclock_gtod_data pvclock_gtod_data;
1291
1292static void update_pvclock_gtod(struct timekeeper *tk)
1293{
1294 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1295 u64 boot_ns;
1296
876e7881 1297 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1298
1299 write_seqcount_begin(&vdata->seq);
1300
1301 /* copy pvclock gtod data */
876e7881
PZ		 1302 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1303 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1304 vdata->clock.mask = tk->tkr_mono.mask;
1305 vdata->clock.mult = tk->tkr_mono.mult;
1306 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1307
cbcf2dd3 1308 vdata->boot_ns = boot_ns;
876e7881 1309 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1310
55dd00a7
MT		 1311 vdata->wall_time_sec = tk->xtime_sec;
1312
16e8d74d
MT		 1313 write_seqcount_end(&vdata->seq);
1314}
1315#endif
1316
bab5bb39
NK		 1317void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1318{
1319 /*
1320 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1321 * vcpu_enter_guest. This function is only called from
1322 * the physical CPU that is running vcpu.
1323 */
1324 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1325}
16e8d74d 1326
18068523
GOC		 1327static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1328{
9ed3c444
AK		 1329 int version;
1330 int r;
50d0a0f9 1331 struct pvclock_wall_clock wc;
87aeb54f 1332 struct timespec64 boot;
18068523
GOC		 1333
1334 if (!wall_clock)
1335 return;
1336
9ed3c444
AK		 1337 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1338 if (r)
1339 return;
1340
1341 if (version & 1)
1342 ++version; /* first time write, random junk */
1343
1344 ++version;
18068523 1345
1dab1345
NK		 1346 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1347 return;
18068523 1348
50d0a0f9
GH		 1349 /*
1350 * The guest calculates current wall clock time by adding
34c238a1 1351 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1352 * wall clock specified here. guest system time equals host
1353 * system time for us, thus we must fill in host boot time here.
1354 */
87aeb54f 1355 getboottime64(&boot);
50d0a0f9 1356
4b648665 1357 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1358 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1359 boot = timespec64_sub(boot, ts);
4b648665 1360 }
87aeb54f 1361 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1362 wc.nsec = boot.tv_nsec;
1363 wc.version = version;
18068523
GOC		 1364
1365 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1366
1367 version++;
1368 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1369}
1370
50d0a0f9
GH		 1371static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1372{
b51012de
PB		 1373 do_shl32_div32(dividend, divisor);
1374 return dividend;
50d0a0f9
GH		 1375}
1376
3ae13faa 1377static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1378 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1379{
5f4e3f88 1380 uint64_t scaled64;
50d0a0f9
GH		 1381 int32_t shift = 0;
1382 uint64_t tps64;
1383 uint32_t tps32;
1384
3ae13faa
PB		 1385 tps64 = base_hz;
1386 scaled64 = scaled_hz;
50933623 1387 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1388 tps64 >>= 1;
1389 shift--;
1390 }
1391
1392 tps32 = (uint32_t)tps64;
50933623
JK		 1393 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1394 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1395 scaled64 >>= 1;
1396 else
1397 tps32 <<= 1;
50d0a0f9
GH		 1398 shift++;
1399 }
1400
5f4e3f88
ZA		 1401 *pshift = shift;
1402 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1403
3ae13faa
PB		 1404 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1405 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1406}
1407
d828199e 1408#ifdef CONFIG_X86_64
16e8d74d 1409static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1410#endif
16e8d74d 1411
c8076604 1412static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1413static unsigned long max_tsc_khz;
c8076604 1414
cc578287 1415static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1416{
cc578287
ZA		 1417 u64 v = (u64)khz * (1000000 + ppm);
1418 do_div(v, 1000000);
1419 return v;
1e993611
JR		 1420}
1421
381d585c
HZ		 1422static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1423{
1424 u64 ratio;
1425
1426 /* Guest TSC same frequency as host TSC? */
1427 if (!scale) {
1428 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1429 return 0;
1430 }
1431
1432 /* TSC scaling supported? */
1433 if (!kvm_has_tsc_control) {
1434 if (user_tsc_khz > tsc_khz) {
1435 vcpu->arch.tsc_catchup = 1;
1436 vcpu->arch.tsc_always_catchup = 1;
1437 return 0;
1438 } else {
1439 WARN(1, "user requested TSC rate below hardware speed\n");
1440 return -1;
1441 }
1442 }
1443
1444 /* TSC scaling required - calculate ratio */
1445 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1446 user_tsc_khz, tsc_khz);
1447
1448 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1449 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1450 user_tsc_khz);
1451 return -1;
1452 }
1453
1454 vcpu->arch.tsc_scaling_ratio = ratio;
1455 return 0;
1456}
1457
4941b8cb 1458static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1459{
cc578287
ZA		 1460 u32 thresh_lo, thresh_hi;
1461 int use_scaling = 0;
217fc9cf 1462
03ba32ca 1463 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1464 if (user_tsc_khz == 0) {
ad721883
HZ		 1465 /* set tsc_scaling_ratio to a safe value */
1466 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1467 return -1;
ad721883 1468 }
03ba32ca 1469
c285545f 1470 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1471 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1472 &vcpu->arch.virtual_tsc_shift,
1473 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1474 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1475
1476 /*
1477 * Compute the variation in TSC rate which is acceptable
1478 * within the range of tolerance and decide if the
1479 * rate being applied is within that bounds of the hardware
1480 * rate. If so, no scaling or compensation need be done.
1481 */
1482 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1483 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1484 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1485 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1486 use_scaling = 1;
1487 }
4941b8cb 1488 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1489}
1490
1491static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1492{
e26101b1 1493 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1494 vcpu->arch.virtual_tsc_mult,
1495 vcpu->arch.virtual_tsc_shift);
e26101b1 1496 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1497 return tsc;
1498}
1499
b0c39dc6
VK		 1500static inline int gtod_is_based_on_tsc(int mode)
1501{
1502 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1503}
1504
69b0049a 1505static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1506{
1507#ifdef CONFIG_X86_64
1508 bool vcpus_matched;
b48aa97e
MT		 1509 struct kvm_arch *ka = &vcpu->kvm->arch;
1510 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1511
1512 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1513 atomic_read(&vcpu->kvm->online_vcpus));
1514
7f187922
MT		 1515 /*
1516 * Once the masterclock is enabled, always perform request in
1517 * order to update it.
1518 *
1519 * In order to enable masterclock, the host clocksource must be TSC
1520 * and the vcpus need to have matched TSCs. When that happens,
1521 * perform request to enable masterclock.
1522 */
1523 if (ka->use_master_clock ||
b0c39dc6 1524 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1525 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1526
1527 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1528 atomic_read(&vcpu->kvm->online_vcpus),
1529 ka->use_master_clock, gtod->clock.vclock_mode);
1530#endif
1531}
1532
ba904635
WA		 1533static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1534{
e79f245d 1535 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1536 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1537}
1538
35181e86
HZ		 1539/*
1540 * Multiply tsc by a fixed point number represented by ratio.
1541 *
1542 * The most significant 64-N bits (mult) of ratio represent the
1543 * integral part of the fixed point number; the remaining N bits
1544 * (frac) represent the fractional part, ie. ratio represents a fixed
1545 * point number (mult + frac * 2^(-N)).
1546 *
1547 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1548 */
1549static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1550{
1551 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1552}
1553
1554u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1555{
1556 u64 _tsc = tsc;
1557 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1558
1559 if (ratio != kvm_default_tsc_scaling_ratio)
1560 _tsc = __scale_tsc(ratio, tsc);
1561
1562 return _tsc;
1563}
1564EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1565
07c1419a
HZ		 1566static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1567{
1568 u64 tsc;
1569
1570 tsc = kvm_scale_tsc(vcpu, rdtsc());
1571
1572 return target_tsc - tsc;
1573}
1574
4ba76538
HZ		 1575u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1576{
e79f245d
KA		 1577 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1578
1579 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1580}
1581EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1582
a545ab6a
LC		 1583static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1584{
1585 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1586 vcpu->arch.tsc_offset = offset;
1587}
1588
b0c39dc6
VK		 1589static inline bool kvm_check_tsc_unstable(void)
1590{
1591#ifdef CONFIG_X86_64
1592 /*
1593 * TSC is marked unstable when we're running on Hyper-V,
1594 * 'TSC page' clocksource is good.
1595 */
1596 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1597 return false;
1598#endif
1599 return check_tsc_unstable();
1600}
1601
8fe8ab46 1602void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1603{
1604 struct kvm *kvm = vcpu->kvm;
f38e098f 1605 u64 offset, ns, elapsed;
99e3e30a 1606 unsigned long flags;
b48aa97e 1607 bool matched;
0d3da0d2 1608 bool already_matched;
8fe8ab46 1609 u64 data = msr->data;
c5e8ec8e 1610 bool synchronizing = false;
99e3e30a 1611
038f8c11 1612 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1613 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1614 ns = ktime_get_boot_ns();
f38e098f 1615 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1616
03ba32ca 1617 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1618 if (data == 0 && msr->host_initiated) {
1619 /*
1620 * detection of vcpu initialization -- need to sync
1621 * with other vCPUs. This particularly helps to keep
1622 * kvm_clock stable after CPU hotplug
1623 */
1624 synchronizing = true;
1625 } else {
1626 u64 tsc_exp = kvm->arch.last_tsc_write +
1627 nsec_to_cycles(vcpu, elapsed);
1628 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1629 /*
1630 * Special case: TSC write with a small delta (1 second)
1631 * of virtual cycle time against real time is
1632 * interpreted as an attempt to synchronize the CPU.
1633 */
1634 synchronizing = data < tsc_exp + tsc_hz &&
1635 data + tsc_hz > tsc_exp;
1636 }
c5e8ec8e 1637 }
f38e098f
ZA		 1638
1639 /*
5d3cb0f6
ZA		 1640 * For a reliable TSC, we can match TSC offsets, and for an unstable
1641 * TSC, we add elapsed time in this computation. We could let the
1642 * compensation code attempt to catch up if we fall behind, but
1643 * it's better to try to match offsets from the beginning.
1644 */
c5e8ec8e 1645 if (synchronizing &&
5d3cb0f6 1646 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1647 if (!kvm_check_tsc_unstable()) {
e26101b1 1648 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1649 pr_debug("kvm: matched tsc offset for %llu\n", data);
1650 } else {
857e4099 1651 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1652 data += delta;
07c1419a 1653 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1654 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1655 }
b48aa97e 1656 matched = true;
0d3da0d2 1657 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1658 } else {
1659 /*
1660 * We split periods of matched TSC writes into generations.
1661 * For each generation, we track the original measured
1662 * nanosecond time, offset, and write, so if TSCs are in
1663 * sync, we can match exact offset, and if not, we can match
4a969980 1664 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1665 *
1666 * These values are tracked in kvm->arch.cur_xxx variables.
1667 */
1668 kvm->arch.cur_tsc_generation++;
1669 kvm->arch.cur_tsc_nsec = ns;
1670 kvm->arch.cur_tsc_write = data;
1671 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1672 matched = false;
0d3da0d2 1673 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1674 kvm->arch.cur_tsc_generation, data);
f38e098f 1675 }
e26101b1
ZA		 1676
1677 /*
1678 * We also track th most recent recorded KHZ, write and time to
1679 * allow the matching interval to be extended at each write.
1680 */
f38e098f
ZA		 1681 kvm->arch.last_tsc_nsec = ns;
1682 kvm->arch.last_tsc_write = data;
5d3cb0f6 1683 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1684
b183aa58 1685 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1686
1687 /* Keep track of which generation this VCPU has synchronized to */
1688 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1689 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1690 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1691
d6321d49 1692 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1693 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1694
a545ab6a 1695 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1696 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1697
1698 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1699 if (!matched) {
b48aa97e 1700 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1701 } else if (!already_matched) {
1702 kvm->arch.nr_vcpus_matched_tsc++;
1703 }
b48aa97e
MT		 1704
1705 kvm_track_tsc_matching(vcpu);
1706 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1707}
e26101b1 1708
99e3e30a
ZA		 1709EXPORT_SYMBOL_GPL(kvm_write_tsc);
1710
58ea6767
HZ		 1711static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1712 s64 adjustment)
1713{
ea26e4ec 1714 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1715}
1716
1717static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1718{
1719 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1720 WARN_ON(adjustment < 0);
1721 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1722 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1723}
1724
d828199e
MT		 1725#ifdef CONFIG_X86_64
1726
a5a1d1c2 1727static u64 read_tsc(void)
d828199e 1728{
a5a1d1c2 1729 u64 ret = (u64)rdtsc_ordered();
03b9730b 1730 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1731
1732 if (likely(ret >= last))
1733 return ret;
1734
1735 /*
1736 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1737 * predictable (it's just a function of time and the likely is
d828199e
MT		 1738 * very likely) and there's a data dependence, so force GCC
1739 * to generate a branch instead. I don't barrier() because
1740 * we don't actually need a barrier, and if this function
1741 * ever gets inlined it will generate worse code.
1742 */
1743 asm volatile ("");
1744 return last;
1745}
1746
b0c39dc6 1747static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1748{
1749 long v;
1750 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1751 u64 tsc_pg_val;
1752
1753 switch (gtod->clock.vclock_mode) {
1754 case VCLOCK_HVCLOCK:
1755 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1756 tsc_timestamp);
1757 if (tsc_pg_val != U64_MAX) {
1758 /* TSC page valid */
1759 *mode = VCLOCK_HVCLOCK;
1760 v = (tsc_pg_val - gtod->clock.cycle_last) &
1761 gtod->clock.mask;
1762 } else {
1763 /* TSC page invalid */
1764 *mode = VCLOCK_NONE;
1765 }
1766 break;
1767 case VCLOCK_TSC:
1768 *mode = VCLOCK_TSC;
1769 *tsc_timestamp = read_tsc();
1770 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1771 gtod->clock.mask;
1772 break;
1773 default:
1774 *mode = VCLOCK_NONE;
1775 }
d828199e 1776
b0c39dc6
VK		 1777 if (*mode == VCLOCK_NONE)
1778 *tsc_timestamp = v = 0;
d828199e 1779
d828199e
MT		 1780 return v * gtod->clock.mult;
1781}
1782
b0c39dc6 1783static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1784{
cbcf2dd3 1785 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1786 unsigned long seq;
d828199e 1787 int mode;
cbcf2dd3 1788 u64 ns;
d828199e 1789
d828199e
MT		 1790 do {
1791 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1792 ns = gtod->nsec_base;
b0c39dc6 1793 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1794 ns >>= gtod->clock.shift;
cbcf2dd3 1795 ns += gtod->boot_ns;
d828199e 1796 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1797 *t = ns;
d828199e
MT		 1798
1799 return mode;
1800}
1801
899a31f5 1802static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1803{
1804 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1805 unsigned long seq;
1806 int mode;
1807 u64 ns;
1808
1809 do {
1810 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1811 ts->tv_sec = gtod->wall_time_sec;
1812 ns = gtod->nsec_base;
b0c39dc6 1813 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1814 ns >>= gtod->clock.shift;
1815 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1816
1817 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1818 ts->tv_nsec = ns;
1819
1820 return mode;
1821}
1822
b0c39dc6
VK		 1823/* returns true if host is using TSC based clocksource */
1824static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1825{
d828199e 1826 /* checked again under seqlock below */
b0c39dc6 1827 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1828 return false;
1829
b0c39dc6
VK		 1830 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1831 tsc_timestamp));
d828199e 1832}
55dd00a7 1833
b0c39dc6 1834/* returns true if host is using TSC based clocksource */
899a31f5 1835static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 1836 u64 *tsc_timestamp)
55dd00a7
MT		 1837{
1838 /* checked again under seqlock below */
b0c39dc6 1839 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1840 return false;
1841
b0c39dc6 1842 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1843}
d828199e
MT		 1844#endif
1845
1846/*
1847 *
b48aa97e
MT		 1848 * Assuming a stable TSC across physical CPUS, and a stable TSC
1849 * across virtual CPUs, the following condition is possible.
1850 * Each numbered line represents an event visible to both
d828199e
MT		 1851 * CPUs at the next numbered event.
1852 *
1853 * "timespecX" represents host monotonic time. "tscX" represents
1854 * RDTSC value.
1855 *
1856 * VCPU0 on CPU0 | VCPU1 on CPU1
1857 *
1858 * 1. read timespec0,tsc0
1859 * 2. | timespec1 = timespec0 + N
1860 * | tsc1 = tsc0 + M
1861 * 3. transition to guest | transition to guest
1862 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1863 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1864 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1865 *
1866 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1867 *
1868 * - ret0 < ret1
1869 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1870 * ...
1871 * - 0 < N - M => M < N
1872 *
1873 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1874 * always the case (the difference between two distinct xtime instances
1875 * might be smaller then the difference between corresponding TSC reads,
1876 * when updating guest vcpus pvclock areas).
1877 *
1878 * To avoid that problem, do not allow visibility of distinct
1879 * system_timestamp/tsc_timestamp values simultaneously: use a master
1880 * copy of host monotonic time values. Update that master copy
1881 * in lockstep.
1882 *
b48aa97e 1883 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1884 *
1885 */
1886
1887static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1888{
1889#ifdef CONFIG_X86_64
1890 struct kvm_arch *ka = &kvm->arch;
1891 int vclock_mode;
b48aa97e
MT		 1892 bool host_tsc_clocksource, vcpus_matched;
1893
1894 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1895 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1896
1897 /*
1898 * If the host uses TSC clock, then passthrough TSC as stable
1899 * to the guest.
1900 */
b48aa97e 1901 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1902 &ka->master_kernel_ns,
1903 &ka->master_cycle_now);
1904
16a96021 1905 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1906 && !ka->backwards_tsc_observed
54750f2c 1907 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1908
d828199e
MT		 1909 if (ka->use_master_clock)
1910 atomic_set(&kvm_guest_has_master_clock, 1);
1911
1912 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1913 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1914 vcpus_matched);
d828199e
MT		 1915#endif
1916}
1917
2860c4b1
PB		 1918void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1919{
1920 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1921}
1922
2e762ff7
MT		 1923static void kvm_gen_update_masterclock(struct kvm *kvm)
1924{
1925#ifdef CONFIG_X86_64
1926 int i;
1927 struct kvm_vcpu *vcpu;
1928 struct kvm_arch *ka = &kvm->arch;
1929
1930 spin_lock(&ka->pvclock_gtod_sync_lock);
1931 kvm_make_mclock_inprogress_request(kvm);
1932 /* no guest entries from this point */
1933 pvclock_update_vm_gtod_copy(kvm);
1934
1935 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1936 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1937
1938 /* guest entries allowed */
1939 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1940 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1941
1942 spin_unlock(&ka->pvclock_gtod_sync_lock);
1943#endif
1944}
1945
e891a32e 1946u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1947{
108b249c 1948 struct kvm_arch *ka = &kvm->arch;
8b953440 1949 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1950 u64 ret;
108b249c 1951
8b953440
PB		 1952 spin_lock(&ka->pvclock_gtod_sync_lock);
1953 if (!ka->use_master_clock) {
1954 spin_unlock(&ka->pvclock_gtod_sync_lock);
1955 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1956 }
1957
8b953440
PB		 1958 hv_clock.tsc_timestamp = ka->master_cycle_now;
1959 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1960 spin_unlock(&ka->pvclock_gtod_sync_lock);
1961
e2c2206a
WL		 1962 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1963 get_cpu();
1964
e70b57a6
WL		 1965 if (__this_cpu_read(cpu_tsc_khz)) {
1966 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1967 &hv_clock.tsc_shift,
1968 &hv_clock.tsc_to_system_mul);
1969 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1970 } else
1971 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1972
1973 put_cpu();
1974
1975 return ret;
108b249c
PB		 1976}
1977
0d6dd2ff
PB		 1978static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1979{
1980 struct kvm_vcpu_arch *vcpu = &v->arch;
1981 struct pvclock_vcpu_time_info guest_hv_clock;
1982
4e335d9e 1983 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1984 &guest_hv_clock, sizeof(guest_hv_clock))))
1985 return;
1986
1987 /* This VCPU is paused, but it's legal for a guest to read another
1988 * VCPU's kvmclock, so we really have to follow the specification where
1989 * it says that version is odd if data is being modified, and even after
1990 * it is consistent.
1991 *
1992 * Version field updates must be kept separate. This is because
1993 * kvm_write_guest_cached might use a "rep movs" instruction, and
1994 * writes within a string instruction are weakly ordered. So there
1995 * are three writes overall.
1996 *
1997 * As a small optimization, only write the version field in the first
1998 * and third write. The vcpu->pv_time cache is still valid, because the
1999 * version field is the first in the struct.
2000 */
2001 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2002
51c4b8bb
LA		 2003 if (guest_hv_clock.version & 1)
2004 ++guest_hv_clock.version; /* first time write, random junk */
2005
0d6dd2ff 2006 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2007 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2008 &vcpu->hv_clock,
2009 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2010
2011 smp_wmb();
2012
2013 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2014 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2015
2016 if (vcpu->pvclock_set_guest_stopped_request) {
2017 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2018 vcpu->pvclock_set_guest_stopped_request = false;
2019 }
2020
2021 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2022
4e335d9e
PB		 2023 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2024 &vcpu->hv_clock,
2025 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2026
2027 smp_wmb();
2028
2029 vcpu->hv_clock.version++;
4e335d9e
PB		 2030 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2031 &vcpu->hv_clock,
2032 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2033}
2034
34c238a1 2035static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2036{
78db6a50 2037 unsigned long flags, tgt_tsc_khz;
18068523 2038 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2039 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2040 s64 kernel_ns;
d828199e 2041 u64 tsc_timestamp, host_tsc;
51d59c6b 2042 u8 pvclock_flags;
d828199e
MT		 2043 bool use_master_clock;
2044
2045 kernel_ns = 0;
2046 host_tsc = 0;
18068523 2047
d828199e
MT		 2048 /*
2049 * If the host uses TSC clock, then passthrough TSC as stable
2050 * to the guest.
2051 */
2052 spin_lock(&ka->pvclock_gtod_sync_lock);
2053 use_master_clock = ka->use_master_clock;
2054 if (use_master_clock) {
2055 host_tsc = ka->master_cycle_now;
2056 kernel_ns = ka->master_kernel_ns;
2057 }
2058 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2059
2060 /* Keep irq disabled to prevent changes to the clock */
2061 local_irq_save(flags);
78db6a50
PB		 2062 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2063 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2064 local_irq_restore(flags);
2065 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2066 return 1;
2067 }
d828199e 2068 if (!use_master_clock) {
4ea1636b 2069 host_tsc = rdtsc();
108b249c 2070 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 2071 }
2072
4ba76538 2073 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2074
c285545f
ZA		 2075 /*
2076 * We may have to catch up the TSC to match elapsed wall clock
2077 * time for two reasons, even if kvmclock is used.
2078 * 1) CPU could have been running below the maximum TSC rate
2079 * 2) Broken TSC compensation resets the base at each VCPU
2080 * entry to avoid unknown leaps of TSC even when running
2081 * again on the same CPU. This may cause apparent elapsed
2082 * time to disappear, and the guest to stand still or run
2083 * very slowly.
2084 */
2085 if (vcpu->tsc_catchup) {
2086 u64 tsc = compute_guest_tsc(v, kernel_ns);
2087 if (tsc > tsc_timestamp) {
f1e2b260 2088 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2089 tsc_timestamp = tsc;
2090 }
50d0a0f9
GH		 2091 }
2092
18068523
GOC		 2093 local_irq_restore(flags);
2094
0d6dd2ff 2095 /* With all the info we got, fill in the values */
18068523 2096
78db6a50
PB		 2097 if (kvm_has_tsc_control)
2098 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2099
2100 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2101 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2102 &vcpu->hv_clock.tsc_shift,
2103 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2104 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2105 }
2106
1d5f066e 2107 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2108 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2109 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2110
d828199e 2111 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2112 pvclock_flags = 0;
d828199e
MT		 2113 if (use_master_clock)
2114 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2115
78c0337a
MT		 2116 vcpu->hv_clock.flags = pvclock_flags;
2117
095cf55d
PB		 2118 if (vcpu->pv_time_enabled)
2119 kvm_setup_pvclock_page(v);
2120 if (v == kvm_get_vcpu(v->kvm, 0))
2121 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2122 return 0;
c8076604
GH		 2123}
2124
0061d53d
MT		 2125/*
2126 * kvmclock updates which are isolated to a given vcpu, such as
2127 * vcpu->cpu migration, should not allow system_timestamp from
2128 * the rest of the vcpus to remain static. Otherwise ntp frequency
2129 * correction applies to one vcpu's system_timestamp but not
2130 * the others.
2131 *
2132 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2133 * We need to rate-limit these requests though, as they can
2134 * considerably slow guests that have a large number of vcpus.
2135 * The time for a remote vcpu to update its kvmclock is bound
2136 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2137 */
2138
7e44e449
AJ		 2139#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2140
2141static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2142{
2143 int i;
7e44e449
AJ		 2144 struct delayed_work *dwork = to_delayed_work(work);
2145 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2146 kvmclock_update_work);
2147 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2148 struct kvm_vcpu *vcpu;
2149
2150 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2151 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2152 kvm_vcpu_kick(vcpu);
2153 }
2154}
2155
7e44e449
AJ		 2156static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2157{
2158 struct kvm *kvm = v->kvm;
2159
105b21bb 2160 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2161 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2162 KVMCLOCK_UPDATE_DELAY);
2163}
2164
332967a3
AJ		 2165#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2166
2167static void kvmclock_sync_fn(struct work_struct *work)
2168{
2169 struct delayed_work *dwork = to_delayed_work(work);
2170 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2171 kvmclock_sync_work);
2172 struct kvm *kvm = container_of(ka, struct kvm, arch);
2173
630994b3
MT		 2174 if (!kvmclock_periodic_sync)
2175 return;
2176
332967a3
AJ		 2177 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2178 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2179 KVMCLOCK_SYNC_PERIOD);
2180}
2181
9ffd986c 2182static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2183{
890ca9ae
HY		 2184 u64 mcg_cap = vcpu->arch.mcg_cap;
2185 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2186 u32 msr = msr_info->index;
2187 u64 data = msr_info->data;
890ca9ae 2188
15c4a640 2189 switch (msr) {
15c4a640 2190 case MSR_IA32_MCG_STATUS:
890ca9ae 2191 vcpu->arch.mcg_status = data;
15c4a640 2192 break;
c7ac679c 2193 case MSR_IA32_MCG_CTL:
44883f01
PB		 2194 if (!(mcg_cap & MCG_CTL_P) &&
2195 (data || !msr_info->host_initiated))
890ca9ae
HY		 2196 return 1;
2197 if (data != 0 && data != ~(u64)0)
44883f01 2198 return 1;
890ca9ae
HY		 2199 vcpu->arch.mcg_ctl = data;
2200 break;
2201 default:
2202 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2203 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2204 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2205 /* only 0 or all 1s can be written to IA32_MCi_CTL
2206 * some Linux kernels though clear bit 10 in bank 4 to
2207 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2208 * this to avoid an uncatched #GP in the guest
2209 */
890ca9ae 2210 if ((offset & 0x3) == 0 &&
114be429 2211 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2212 return -1;
9ffd986c
WL		 2213 if (!msr_info->host_initiated &&
2214 (offset & 0x3) == 1 && data != 0)
2215 return -1;
890ca9ae
HY		 2216 vcpu->arch.mce_banks[offset] = data;
2217 break;
2218 }
2219 return 1;
2220 }
2221 return 0;
2222}
2223
ffde22ac
ES		 2224static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2225{
2226 struct kvm *kvm = vcpu->kvm;
2227 int lm = is_long_mode(vcpu);
2228 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2229 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2230 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2231 : kvm->arch.xen_hvm_config.blob_size_32;
2232 u32 page_num = data & ~PAGE_MASK;
2233 u64 page_addr = data & PAGE_MASK;
2234 u8 *page;
2235 int r;
2236
2237 r = -E2BIG;
2238 if (page_num >= blob_size)
2239 goto out;
2240 r = -ENOMEM;
ff5c2c03
SL		 2241 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2242 if (IS_ERR(page)) {
2243 r = PTR_ERR(page);
ffde22ac 2244 goto out;
ff5c2c03 2245 }
54bf36aa 2246 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2247 goto out_free;
2248 r = 0;
2249out_free:
2250 kfree(page);
2251out:
2252 return r;
2253}
2254
344d9588
GN		 2255static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2256{
2257 gpa_t gpa = data & ~0x3f;
2258
52a5c155
WL		 2259 /* Bits 3:5 are reserved, Should be zero */
2260 if (data & 0x38)
344d9588
GN		 2261 return 1;
2262
2263 vcpu->arch.apf.msr_val = data;
2264
2265 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2266 kvm_clear_async_pf_completion_queue(vcpu);
2267 kvm_async_pf_hash_reset(vcpu);
2268 return 0;
2269 }
2270
4e335d9e 2271 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2272 sizeof(u32)))
344d9588
GN		 2273 return 1;
2274
6adba527 2275 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2276 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2277 kvm_async_pf_wakeup_all(vcpu);
2278 return 0;
2279}
2280
12f9a48f
GC		 2281static void kvmclock_reset(struct kvm_vcpu *vcpu)
2282{
0b79459b 2283 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2284}
2285
f38a7b75
WL		 2286static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2287{
2288 ++vcpu->stat.tlb_flush;
2289 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2290}
2291
c9aaa895
GC		 2292static void record_steal_time(struct kvm_vcpu *vcpu)
2293{
2294 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2295 return;
2296
4e335d9e 2297 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2298 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2299 return;
2300
f38a7b75
WL		 2301 /*
2302 * Doing a TLB flush here, on the guest's behalf, can avoid
2303 * expensive IPIs.
2304 */
2305 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2306 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2307
35f3fae1
WL		 2308 if (vcpu->arch.st.steal.version & 1)
2309 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2310
2311 vcpu->arch.st.steal.version += 1;
2312
4e335d9e 2313 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2314 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2315
2316 smp_wmb();
2317
c54cdf14
LC		 2318 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2319 vcpu->arch.st.last_steal;
2320 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2321
4e335d9e 2322 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2323 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2324
2325 smp_wmb();
2326
2327 vcpu->arch.st.steal.version += 1;
c9aaa895 2328
4e335d9e 2329 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2330 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2331}
2332
8fe8ab46 2333int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2334{
5753785f 2335 bool pr = false;
8fe8ab46
WA		 2336 u32 msr = msr_info->index;
2337 u64 data = msr_info->data;
5753785f 2338
15c4a640 2339 switch (msr) {
2e32b719 2340 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2341 case MSR_IA32_UCODE_WRITE:
2342 case MSR_VM_HSAVE_PA:
2343 case MSR_AMD64_PATCH_LOADER:
2344 case MSR_AMD64_BU_CFG2:
405a353a 2345 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2346 break;
2347
518e7b94
WL		 2348 case MSR_IA32_UCODE_REV:
2349 if (msr_info->host_initiated)
2350 vcpu->arch.microcode_version = data;
2351 break;
15c4a640 2352 case MSR_EFER:
b69e8cae 2353 return set_efer(vcpu, data);
8f1589d9
AP		 2354 case MSR_K7_HWCR:
2355 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2356 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2357 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2358 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2359 if (data != 0) {
a737f256
CD		 2360 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2361 data);
8f1589d9
AP		 2362 return 1;
2363 }
15c4a640 2364 break;
f7c6d140
AP		 2365 case MSR_FAM10H_MMIO_CONF_BASE:
2366 if (data != 0) {
a737f256
CD		 2367 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2368 "0x%llx\n", data);
f7c6d140
AP		 2369 return 1;
2370 }
15c4a640 2371 break;
b5e2fec0
AG		 2372 case MSR_IA32_DEBUGCTLMSR:
2373 if (!data) {
2374 /* We support the non-activated case already */
2375 break;
2376 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2377 /* Values other than LBR and BTF are vendor-specific,
2378 thus reserved and should throw a #GP */
2379 return 1;
2380 }
a737f256
CD		 2381 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2382 __func__, data);
b5e2fec0 2383 break;
9ba075a6 2384 case 0x200 ... 0x2ff:
ff53604b 2385 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2386 case MSR_IA32_APICBASE:
58cb628d 2387 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2388 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2389 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2390 case MSR_IA32_TSCDEADLINE:
2391 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2392 break;
ba904635 2393 case MSR_IA32_TSC_ADJUST:
d6321d49 2394 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2395 if (!msr_info->host_initiated) {
d913b904 2396 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2397 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2398 }
2399 vcpu->arch.ia32_tsc_adjust_msr = data;
2400 }
2401 break;
15c4a640 2402 case MSR_IA32_MISC_ENABLE:
ad312c7c 2403 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2404 break;
64d60670
PB		 2405 case MSR_IA32_SMBASE:
2406 if (!msr_info->host_initiated)
2407 return 1;
2408 vcpu->arch.smbase = data;
2409 break;
dd259935
PB		 2410 case MSR_IA32_TSC:
2411 kvm_write_tsc(vcpu, msr_info);
2412 break;
52797bf9
LA		 2413 case MSR_SMI_COUNT:
2414 if (!msr_info->host_initiated)
2415 return 1;
2416 vcpu->arch.smi_count = data;
2417 break;
11c6bffa 2418 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2419 case MSR_KVM_WALL_CLOCK:
2420 vcpu->kvm->arch.wall_clock = data;
2421 kvm_write_wall_clock(vcpu->kvm, data);
2422 break;
11c6bffa 2423 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2424 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2425 struct kvm_arch *ka = &vcpu->kvm->arch;
2426
12f9a48f 2427 kvmclock_reset(vcpu);
18068523 2428
54750f2c
MT		 2429 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2430 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2431
2432 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2433 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2434
2435 ka->boot_vcpu_runs_old_kvmclock = tmp;
2436 }
2437
18068523 2438 vcpu->arch.time = data;
0061d53d 2439 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2440
2441 /* we verify if the enable bit is set... */
2442 if (!(data & 1))
2443 break;
2444
4e335d9e 2445 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2446 &vcpu->arch.pv_time, data & ~1ULL,
2447 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2448 vcpu->arch.pv_time_enabled = false;
2449 else
2450 vcpu->arch.pv_time_enabled = true;
32cad84f 2451
18068523
GOC		 2452 break;
2453 }
344d9588
GN		 2454 case MSR_KVM_ASYNC_PF_EN:
2455 if (kvm_pv_enable_async_pf(vcpu, data))
2456 return 1;
2457 break;
c9aaa895
GC		 2458 case MSR_KVM_STEAL_TIME:
2459
2460 if (unlikely(!sched_info_on()))
2461 return 1;
2462
2463 if (data & KVM_STEAL_RESERVED_MASK)
2464 return 1;
2465
4e335d9e 2466 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2467 data & KVM_STEAL_VALID_BITS,
2468 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2469 return 1;
2470
2471 vcpu->arch.st.msr_val = data;
2472
2473 if (!(data & KVM_MSR_ENABLED))
2474 break;
2475
c9aaa895
GC		 2476 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2477
2478 break;
ae7a2a3f
MT		 2479 case MSR_KVM_PV_EOI_EN:
2480 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2481 return 1;
2482 break;
c9aaa895 2483
890ca9ae
HY		 2484 case MSR_IA32_MCG_CTL:
2485 case MSR_IA32_MCG_STATUS:
81760dcc 2486 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2487 return set_msr_mce(vcpu, msr_info);
71db6023 2488
6912ac32
WH		 2489 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2490 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2491 pr = true; /* fall through */
2492 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2493 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2494 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2495 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2496
2497 if (pr || data != 0)
a737f256
CD		 2498 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2499 "0x%x data 0x%llx\n", msr, data);
5753785f 2500 break;
84e0cefa
JS		 2501 case MSR_K7_CLK_CTL:
2502 /*
2503 * Ignore all writes to this no longer documented MSR.
2504 * Writes are only relevant for old K7 processors,
2505 * all pre-dating SVM, but a recommended workaround from
4a969980 2506 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2507 * affected processor models on the command line, hence
2508 * the need to ignore the workaround.
2509 */
2510 break;
55cd8e5a 2511 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2512 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2513 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2514 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2515 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2516 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2517 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2518 return kvm_hv_set_msr_common(vcpu, msr, data,
2519 msr_info->host_initiated);
91c9c3ed 2520 case MSR_IA32_BBL_CR_CTL3:
2521 /* Drop writes to this legacy MSR -- see rdmsr
2522 * counterpart for further detail.
2523 */
fab0aa3b
EM		 2524 if (report_ignored_msrs)
2525 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2526 msr, data);
91c9c3ed 2527 break;
2b036c6b 2528 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2529 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2530 return 1;
2531 vcpu->arch.osvw.length = data;
2532 break;
2533 case MSR_AMD64_OSVW_STATUS:
d6321d49 2534 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2535 return 1;
2536 vcpu->arch.osvw.status = data;
2537 break;
db2336a8
KH		 2538 case MSR_PLATFORM_INFO:
2539 if (!msr_info->host_initiated ||
2540 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2541 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2542 cpuid_fault_enabled(vcpu)))
2543 return 1;
2544 vcpu->arch.msr_platform_info = data;
2545 break;
2546 case MSR_MISC_FEATURES_ENABLES:
2547 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2548 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2549 !supports_cpuid_fault(vcpu)))
2550 return 1;
2551 vcpu->arch.msr_misc_features_enables = data;
2552 break;
15c4a640 2553 default:
ffde22ac
ES		 2554 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2555 return xen_hvm_config(vcpu, data);
c6702c9d 2556 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2557 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2558 if (!ignore_msrs) {
ae0f5499 2559 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2560 msr, data);
ed85c068
AP		 2561 return 1;
2562 } else {
fab0aa3b
EM		 2563 if (report_ignored_msrs)
2564 vcpu_unimpl(vcpu,
2565 "ignored wrmsr: 0x%x data 0x%llx\n",
2566 msr, data);
ed85c068
AP		 2567 break;
2568 }
15c4a640
CO		 2569 }
2570 return 0;
2571}
2572EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2573
2574
2575/*
2576 * Reads an msr value (of 'msr_index') into 'pdata'.
2577 * Returns 0 on success, non-0 otherwise.
2578 * Assumes vcpu_load() was already called.
2579 */
609e36d3 2580int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2581{
609e36d3 2582 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2583}
ff651cb6 2584EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2585
44883f01 2586static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2587{
2588 u64 data;
890ca9ae
HY		 2589 u64 mcg_cap = vcpu->arch.mcg_cap;
2590 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2591
2592 switch (msr) {
15c4a640
CO		 2593 case MSR_IA32_P5_MC_ADDR:
2594 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2595 data = 0;
2596 break;
15c4a640 2597 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2598 data = vcpu->arch.mcg_cap;
2599 break;
c7ac679c 2600 case MSR_IA32_MCG_CTL:
44883f01 2601 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2602 return 1;
2603 data = vcpu->arch.mcg_ctl;
2604 break;
2605 case MSR_IA32_MCG_STATUS:
2606 data = vcpu->arch.mcg_status;
2607 break;
2608 default:
2609 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2610 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2611 u32 offset = msr - MSR_IA32_MC0_CTL;
2612 data = vcpu->arch.mce_banks[offset];
2613 break;
2614 }
2615 return 1;
2616 }
2617 *pdata = data;
2618 return 0;
2619}
2620
609e36d3 2621int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2622{
609e36d3 2623 switch (msr_info->index) {
890ca9ae 2624 case MSR_IA32_PLATFORM_ID:
15c4a640 2625 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2626 case MSR_IA32_DEBUGCTLMSR:
2627 case MSR_IA32_LASTBRANCHFROMIP:
2628 case MSR_IA32_LASTBRANCHTOIP:
2629 case MSR_IA32_LASTINTFROMIP:
2630 case MSR_IA32_LASTINTTOIP:
60af2ecd 2631 case MSR_K8_SYSCFG:
3afb1121
PB		 2632 case MSR_K8_TSEG_ADDR:
2633 case MSR_K8_TSEG_MASK:
60af2ecd 2634 case MSR_K7_HWCR:
61a6bd67 2635 case MSR_VM_HSAVE_PA:
1fdbd48c 2636 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2637 case MSR_AMD64_NB_CFG:
f7c6d140 2638 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2639 case MSR_AMD64_BU_CFG2:
0c2df2a1 2640 case MSR_IA32_PERF_CTL:
405a353a 2641 case MSR_AMD64_DC_CFG:
609e36d3 2642 msr_info->data = 0;
15c4a640 2643 break;
c51eb52b 2644 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 2645 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2646 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2647 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2648 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2649 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2650 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2651 msr_info->data = 0;
5753785f 2652 break;
742bc670 2653 case MSR_IA32_UCODE_REV:
518e7b94 2654 msr_info->data = vcpu->arch.microcode_version;
742bc670 2655 break;
dd259935
PB		 2656 case MSR_IA32_TSC:
2657 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
2658 break;
9ba075a6 2659 case MSR_MTRRcap:
9ba075a6 2660 case 0x200 ... 0x2ff:
ff53604b 2661 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2662 case 0xcd: /* fsb frequency */
609e36d3 2663 msr_info->data = 3;
15c4a640 2664 break;
7b914098
JS		 2665 /*
2666 * MSR_EBC_FREQUENCY_ID
2667 * Conservative value valid for even the basic CPU models.
2668 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2669 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2670 * and 266MHz for model 3, or 4. Set Core Clock
2671 * Frequency to System Bus Frequency Ratio to 1 (bits
2672 * 31:24) even though these are only valid for CPU
2673 * models > 2, however guests may end up dividing or
2674 * multiplying by zero otherwise.
2675 */
2676 case MSR_EBC_FREQUENCY_ID:
609e36d3 2677 msr_info->data = 1 << 24;
7b914098 2678 break;
15c4a640 2679 case MSR_IA32_APICBASE:
609e36d3 2680 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2681 break;
0105d1a5 2682 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2683 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2684 break;
a3e06bbe 2685 case MSR_IA32_TSCDEADLINE:
609e36d3 2686 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2687 break;
ba904635 2688 case MSR_IA32_TSC_ADJUST:
609e36d3 2689 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2690 break;
15c4a640 2691 case MSR_IA32_MISC_ENABLE:
609e36d3 2692 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2693 break;
64d60670
PB		 2694 case MSR_IA32_SMBASE:
2695 if (!msr_info->host_initiated)
2696 return 1;
2697 msr_info->data = vcpu->arch.smbase;
15c4a640 2698 break;
52797bf9
LA		 2699 case MSR_SMI_COUNT:
2700 msr_info->data = vcpu->arch.smi_count;
2701 break;
847f0ad8
AG		 2702 case MSR_IA32_PERF_STATUS:
2703 /* TSC increment by tick */
609e36d3 2704 msr_info->data = 1000ULL;
847f0ad8 2705 /* CPU multiplier */
b0996ae4 2706 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2707 break;
15c4a640 2708 case MSR_EFER:
609e36d3 2709 msr_info->data = vcpu->arch.efer;
15c4a640 2710 break;
18068523 2711 case MSR_KVM_WALL_CLOCK:
11c6bffa 2712 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2713 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2714 break;
2715 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2716 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2717 msr_info->data = vcpu->arch.time;
18068523 2718 break;
344d9588 2719 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2720 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2721 break;
c9aaa895 2722 case MSR_KVM_STEAL_TIME:
609e36d3 2723 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2724 break;
1d92128f 2725 case MSR_KVM_PV_EOI_EN:
609e36d3 2726 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2727 break;
890ca9ae
HY		 2728 case MSR_IA32_P5_MC_ADDR:
2729 case MSR_IA32_P5_MC_TYPE:
2730 case MSR_IA32_MCG_CAP:
2731 case MSR_IA32_MCG_CTL:
2732 case MSR_IA32_MCG_STATUS:
81760dcc 2733 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 2734 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
2735 msr_info->host_initiated);
84e0cefa
JS		 2736 case MSR_K7_CLK_CTL:
2737 /*
2738 * Provide expected ramp-up count for K7. All other
2739 * are set to zero, indicating minimum divisors for
2740 * every field.
2741 *
2742 * This prevents guest kernels on AMD host with CPU
2743 * type 6, model 8 and higher from exploding due to
2744 * the rdmsr failing.
2745 */
609e36d3 2746 msr_info->data = 0x20000000;
84e0cefa 2747 break;
55cd8e5a 2748 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2749 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2750 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2751 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2752 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2753 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2754 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 2755 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 2756 msr_info->index, &msr_info->data,
2757 msr_info->host_initiated);
55cd8e5a 2758 break;
91c9c3ed 2759 case MSR_IA32_BBL_CR_CTL3:
2760 /* This legacy MSR exists but isn't fully documented in current
2761 * silicon. It is however accessed by winxp in very narrow
2762 * scenarios where it sets bit #19, itself documented as
2763 * a "reserved" bit. Best effort attempt to source coherent
2764 * read data here should the balance of the register be
2765 * interpreted by the guest:
2766 *
2767 * L2 cache control register 3: 64GB range, 256KB size,
2768 * enabled, latency 0x1, configured
2769 */
609e36d3 2770 msr_info->data = 0xbe702111;
91c9c3ed 2771 break;
2b036c6b 2772 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2773 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2774 return 1;
609e36d3 2775 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2776 break;
2777 case MSR_AMD64_OSVW_STATUS:
d6321d49 2778 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2779 return 1;
609e36d3 2780 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2781 break;
db2336a8
KH		 2782 case MSR_PLATFORM_INFO:
2783 msr_info->data = vcpu->arch.msr_platform_info;
2784 break;
2785 case MSR_MISC_FEATURES_ENABLES:
2786 msr_info->data = vcpu->arch.msr_misc_features_enables;
2787 break;
15c4a640 2788 default:
c6702c9d 2789 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2790 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2791 if (!ignore_msrs) {
ae0f5499
BD		 2792 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2793 msr_info->index);
ed85c068
AP		 2794 return 1;
2795 } else {
fab0aa3b
EM		 2796 if (report_ignored_msrs)
2797 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2798 msr_info->index);
609e36d3 2799 msr_info->data = 0;
ed85c068
AP		 2800 }
2801 break;
15c4a640 2802 }
15c4a640
CO		 2803 return 0;
2804}
2805EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2806
313a3dc7
CO		 2807/*
2808 * Read or write a bunch of msrs. All parameters are kernel addresses.
2809 *
2810 * @return number of msrs set successfully.
2811 */
2812static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2813 struct kvm_msr_entry *entries,
2814 int (*do_msr)(struct kvm_vcpu *vcpu,
2815 unsigned index, u64 *data))
2816{
801e459a 2817 int i;
313a3dc7 2818
313a3dc7
CO		 2819 for (i = 0; i < msrs->nmsrs; ++i)
2820 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2821 break;
2822
313a3dc7
CO		 2823 return i;
2824}
2825
2826/*
2827 * Read or write a bunch of msrs. Parameters are user addresses.
2828 *
2829 * @return number of msrs set successfully.
2830 */
2831static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2832 int (*do_msr)(struct kvm_vcpu *vcpu,
2833 unsigned index, u64 *data),
2834 int writeback)
2835{
2836 struct kvm_msrs msrs;
2837 struct kvm_msr_entry *entries;
2838 int r, n;
2839 unsigned size;
2840
2841 r = -EFAULT;
2842 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2843 goto out;
2844
2845 r = -E2BIG;
2846 if (msrs.nmsrs >= MAX_IO_MSRS)
2847 goto out;
2848
313a3dc7 2849 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2850 entries = memdup_user(user_msrs->entries, size);
2851 if (IS_ERR(entries)) {
2852 r = PTR_ERR(entries);
313a3dc7 2853 goto out;
ff5c2c03 2854 }
313a3dc7
CO		 2855
2856 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2857 if (r < 0)
2858 goto out_free;
2859
2860 r = -EFAULT;
2861 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2862 goto out_free;
2863
2864 r = n;
2865
2866out_free:
7a73c028 2867 kfree(entries);
313a3dc7
CO		 2868out:
2869 return r;
2870}
2871
4d5422ce
WL		 2872static inline bool kvm_can_mwait_in_guest(void)
2873{
2874 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 2875 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
2876 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 2877}
2878
784aa3d7 2879int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 2880{
4d5422ce 2881 int r = 0;
018d00d2
ZX		 2882
2883 switch (ext) {
2884 case KVM_CAP_IRQCHIP:
2885 case KVM_CAP_HLT:
2886 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2887 case KVM_CAP_SET_TSS_ADDR:
07716717 2888 case KVM_CAP_EXT_CPUID:
9c15bb1d 2889 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2890 case KVM_CAP_CLOCKSOURCE:
7837699f 2891 case KVM_CAP_PIT:
a28e4f5a 2892 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2893 case KVM_CAP_MP_STATE:
ed848624 2894 case KVM_CAP_SYNC_MMU:
a355c85c 2895 case KVM_CAP_USER_NMI:
52d939a0 2896 case KVM_CAP_REINJECT_CONTROL:
4925663a 2897 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2898 case KVM_CAP_IOEVENTFD:
f848a5a8 2899 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2900 case KVM_CAP_PIT2:
e9f42757 2901 case KVM_CAP_PIT_STATE2:
b927a3ce 2902 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2903 case KVM_CAP_XEN_HVM:
3cfc3092 2904 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2905 case KVM_CAP_HYPERV:
10388a07 2906 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2907 case KVM_CAP_HYPERV_SPIN:
5c919412 2908 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2909 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2910 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2911 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 2912 case KVM_CAP_HYPERV_TLBFLUSH:
ab9f4ecb 2913 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2914 case KVM_CAP_DEBUGREGS:
d2be1651 2915 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2916 case KVM_CAP_XSAVE:
344d9588 2917 case KVM_CAP_ASYNC_PF:
92a1f12d 2918 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2919 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2920 case KVM_CAP_READONLY_MEM:
5f66b620 2921 case KVM_CAP_HYPERV_TIME:
100943c5 2922 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2923 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2924 case KVM_CAP_ENABLE_CAP_VM:
2925 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2926 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2927 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2928 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2929 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2930 r = 1;
2931 break;
01643c51
KH		 2932 case KVM_CAP_SYNC_REGS:
2933 r = KVM_SYNC_X86_VALID_FIELDS;
2934 break;
e3fd9a93
PB		 2935 case KVM_CAP_ADJUST_CLOCK:
2936 r = KVM_CLOCK_TSC_STABLE;
2937 break;
4d5422ce 2938 case KVM_CAP_X86_DISABLE_EXITS:
766d3571 2939 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE;
4d5422ce
WL		 2940 if(kvm_can_mwait_in_guest())
2941 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 2942 break;
6d396b55
PB		 2943 case KVM_CAP_X86_SMM:
2944 /* SMBASE is usually relocated above 1M on modern chipsets,
2945 * and SMM handlers might indeed rely on 4G segment limits,
2946 * so do not report SMM to be available if real mode is
2947 * emulated via vm86 mode. Still, do not go to great lengths
2948 * to avoid userspace's usage of the feature, because it is a
2949 * fringe case that is not enabled except via specific settings
2950 * of the module parameters.
2951 */
bc226f07 2952 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 2953 break;
774ead3a
AK		 2954 case KVM_CAP_VAPIC:
2955 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2956 break;
f725230a 2957 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2958 r = KVM_SOFT_MAX_VCPUS;
2959 break;
2960 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2961 r = KVM_MAX_VCPUS;
2962 break;
a988b910 2963 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2964 r = KVM_USER_MEM_SLOTS;
a988b910 2965 break;
a68a6a72
MT		 2966 case KVM_CAP_PV_MMU: /* obsolete */
2967 r = 0;
2f333bcb 2968 break;
890ca9ae
HY		 2969 case KVM_CAP_MCE:
2970 r = KVM_MAX_MCE_BANKS;
2971 break;
2d5b5a66 2972 case KVM_CAP_XCRS:
d366bf7e 2973 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2974 break;
92a1f12d
JR		 2975 case KVM_CAP_TSC_CONTROL:
2976 r = kvm_has_tsc_control;
2977 break;
37131313
RK		 2978 case KVM_CAP_X2APIC_API:
2979 r = KVM_X2APIC_API_VALID_FLAGS;
2980 break;
8fcc4b59
JM		 2981 case KVM_CAP_NESTED_STATE:
2982 r = kvm_x86_ops->get_nested_state ?
2983 kvm_x86_ops->get_nested_state(NULL, 0, 0) : 0;
2984 break;
018d00d2 2985 default:
018d00d2
ZX		 2986 break;
2987 }
2988 return r;
2989
2990}
2991
043405e1
CO		 2992long kvm_arch_dev_ioctl(struct file *filp,
2993 unsigned int ioctl, unsigned long arg)
2994{
2995 void __user *argp = (void __user *)arg;
2996 long r;
2997
2998 switch (ioctl) {
2999 case KVM_GET_MSR_INDEX_LIST: {
3000 struct kvm_msr_list __user *user_msr_list = argp;
3001 struct kvm_msr_list msr_list;
3002 unsigned n;
3003
3004 r = -EFAULT;
3005 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
3006 goto out;
3007 n = msr_list.nmsrs;
62ef68bb 3008 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 3009 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
3010 goto out;
3011 r = -E2BIG;
e125e7b6 3012 if (n < msr_list.nmsrs)
043405e1
CO		 3013 goto out;
3014 r = -EFAULT;
3015 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3016 num_msrs_to_save * sizeof(u32)))
3017 goto out;
e125e7b6 3018 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3019 &emulated_msrs,
62ef68bb 3020 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3021 goto out;
3022 r = 0;
3023 break;
3024 }
9c15bb1d
BP		 3025 case KVM_GET_SUPPORTED_CPUID:
3026 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3027 struct kvm_cpuid2 __user *cpuid_arg = argp;
3028 struct kvm_cpuid2 cpuid;
3029
3030 r = -EFAULT;
3031 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3032 goto out;
9c15bb1d
BP		 3033
3034 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3035 ioctl);
674eea0f
AK		 3036 if (r)
3037 goto out;
3038
3039 r = -EFAULT;
3040 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3041 goto out;
3042 r = 0;
3043 break;
3044 }
890ca9ae 3045 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3046 r = -EFAULT;
c45dcc71
AR		 3047 if (copy_to_user(argp, &kvm_mce_cap_supported,
3048 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3049 goto out;
3050 r = 0;
3051 break;
801e459a
TL		 3052 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3053 struct kvm_msr_list __user *user_msr_list = argp;
3054 struct kvm_msr_list msr_list;
3055 unsigned int n;
3056
3057 r = -EFAULT;
3058 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3059 goto out;
3060 n = msr_list.nmsrs;
3061 msr_list.nmsrs = num_msr_based_features;
3062 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3063 goto out;
3064 r = -E2BIG;
3065 if (n < msr_list.nmsrs)
3066 goto out;
3067 r = -EFAULT;
3068 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3069 num_msr_based_features * sizeof(u32)))
3070 goto out;
3071 r = 0;
3072 break;
3073 }
3074 case KVM_GET_MSRS:
3075 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3076 break;
890ca9ae 3077 }
043405e1
CO		 3078 default:
3079 r = -EINVAL;
3080 }
3081out:
3082 return r;
3083}
3084
f5f48ee1
SY		 3085static void wbinvd_ipi(void *garbage)
3086{
3087 wbinvd();
3088}
3089
3090static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3091{
e0f0bbc5 3092 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3093}
3094
313a3dc7
CO		 3095void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3096{
f5f48ee1
SY		 3097 /* Address WBINVD may be executed by guest */
3098 if (need_emulate_wbinvd(vcpu)) {
3099 if (kvm_x86_ops->has_wbinvd_exit())
3100 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3101 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3102 smp_call_function_single(vcpu->cpu,
3103 wbinvd_ipi, NULL, 1);
3104 }
3105
313a3dc7 3106 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3107
0dd6a6ed
ZA		 3108 /* Apply any externally detected TSC adjustments (due to suspend) */
3109 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3110 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3111 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3112 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3113 }
8f6055cb 3114
b0c39dc6 3115 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3116 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3117 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3118 if (tsc_delta < 0)
3119 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3120
b0c39dc6 3121 if (kvm_check_tsc_unstable()) {
07c1419a 3122 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3123 vcpu->arch.last_guest_tsc);
a545ab6a 3124 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3125 vcpu->arch.tsc_catchup = 1;
c285545f 3126 }
a749e247
PB		 3127
3128 if (kvm_lapic_hv_timer_in_use(vcpu))
3129 kvm_lapic_restart_hv_timer(vcpu);
3130
d98d07ca
MT		 3131 /*
3132 * On a host with synchronized TSC, there is no need to update
3133 * kvmclock on vcpu->cpu migration
3134 */
3135 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3136 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3137 if (vcpu->cpu != cpu)
1bd2009e 3138 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3139 vcpu->cpu = cpu;
6b7d7e76 3140 }
c9aaa895 3141
c9aaa895 3142 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3143}
3144
0b9f6c46
PX		 3145static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3146{
3147 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3148 return;
3149
fa55eedd 3150 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3151
4e335d9e 3152 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3153 &vcpu->arch.st.steal.preempted,
3154 offsetof(struct kvm_steal_time, preempted),
3155 sizeof(vcpu->arch.st.steal.preempted));
3156}
3157
313a3dc7
CO		 3158void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3159{
cc0d907c 3160 int idx;
de63ad4c
LM		 3161
3162 if (vcpu->preempted)
3163 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3164
931f261b
AA		 3165 /*
3166 * Disable page faults because we're in atomic context here.
3167 * kvm_write_guest_offset_cached() would call might_fault()
3168 * that relies on pagefault_disable() to tell if there's a
3169 * bug. NOTE: the write to guest memory may not go through if
3170 * during postcopy live migration or if there's heavy guest
3171 * paging.
3172 */
3173 pagefault_disable();
cc0d907c
AA		 3174 /*
3175 * kvm_memslots() will be called by
3176 * kvm_write_guest_offset_cached() so take the srcu lock.
3177 */
3178 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3179 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3180 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3181 pagefault_enable();
02daab21 3182 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3183 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3184 /*
3185 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3186 * on every vmexit, but if not, we might have a stale dr6 from the
3187 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3188 */
3189 set_debugreg(0, 6);
313a3dc7
CO		 3190}
3191
313a3dc7
CO		 3192static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3193 struct kvm_lapic_state *s)
3194{
fa59cc00 3195 if (vcpu->arch.apicv_active)
d62caabb
AS		 3196 kvm_x86_ops->sync_pir_to_irr(vcpu);
3197
a92e2543 3198 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3199}
3200
3201static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3202 struct kvm_lapic_state *s)
3203{
a92e2543
RK		 3204 int r;
3205
3206 r = kvm_apic_set_state(vcpu, s);
3207 if (r)
3208 return r;
cb142eb7 3209 update_cr8_intercept(vcpu);
313a3dc7
CO		 3210
3211 return 0;
3212}
3213
127a457a
MG		 3214static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3215{
3216 return (!lapic_in_kernel(vcpu) ||
3217 kvm_apic_accept_pic_intr(vcpu));
3218}
3219
782d422b
MG		 3220/*
3221 * if userspace requested an interrupt window, check that the
3222 * interrupt window is open.
3223 *
3224 * No need to exit to userspace if we already have an interrupt queued.
3225 */
3226static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3227{
3228 return kvm_arch_interrupt_allowed(vcpu) &&
3229 !kvm_cpu_has_interrupt(vcpu) &&
3230 !kvm_event_needs_reinjection(vcpu) &&
3231 kvm_cpu_accept_dm_intr(vcpu);
3232}
3233
f77bc6a4
ZX		 3234static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3235 struct kvm_interrupt *irq)
3236{
02cdb50f 3237 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3238 return -EINVAL;
1c1a9ce9
SR		 3239
3240 if (!irqchip_in_kernel(vcpu->kvm)) {
3241 kvm_queue_interrupt(vcpu, irq->irq, false);
3242 kvm_make_request(KVM_REQ_EVENT, vcpu);
3243 return 0;
3244 }
3245
3246 /*
3247 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3248 * fail for in-kernel 8259.
3249 */
3250 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3251 return -ENXIO;
f77bc6a4 3252
1c1a9ce9
SR		 3253 if (vcpu->arch.pending_external_vector != -1)
3254 return -EEXIST;
f77bc6a4 3255
1c1a9ce9 3256 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3257 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3258 return 0;
3259}
3260
c4abb7c9
JK		 3261static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3262{
c4abb7c9 3263 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3264
3265 return 0;
3266}
3267
f077825a
PB		 3268static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3269{
64d60670
PB		 3270 kvm_make_request(KVM_REQ_SMI, vcpu);
3271
f077825a
PB		 3272 return 0;
3273}
3274
b209749f
AK		 3275static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3276 struct kvm_tpr_access_ctl *tac)
3277{
3278 if (tac->flags)
3279 return -EINVAL;
3280 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3281 return 0;
3282}
3283
890ca9ae
HY		 3284static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3285 u64 mcg_cap)
3286{
3287 int r;
3288 unsigned bank_num = mcg_cap & 0xff, bank;
3289
3290 r = -EINVAL;
a9e38c3e 3291 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3292 goto out;
c45dcc71 3293 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3294 goto out;
3295 r = 0;
3296 vcpu->arch.mcg_cap = mcg_cap;
3297 /* Init IA32_MCG_CTL to all 1s */
3298 if (mcg_cap & MCG_CTL_P)
3299 vcpu->arch.mcg_ctl = ~(u64)0;
3300 /* Init IA32_MCi_CTL to all 1s */
3301 for (bank = 0; bank < bank_num; bank++)
3302 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3303
3304 if (kvm_x86_ops->setup_mce)
3305 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3306out:
3307 return r;
3308}
3309
3310static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3311 struct kvm_x86_mce *mce)
3312{
3313 u64 mcg_cap = vcpu->arch.mcg_cap;
3314 unsigned bank_num = mcg_cap & 0xff;
3315 u64 *banks = vcpu->arch.mce_banks;
3316
3317 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3318 return -EINVAL;
3319 /*
3320 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3321 * reporting is disabled
3322 */
3323 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3324 vcpu->arch.mcg_ctl != ~(u64)0)
3325 return 0;
3326 banks += 4 * mce->bank;
3327 /*
3328 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3329 * reporting is disabled for the bank
3330 */
3331 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3332 return 0;
3333 if (mce->status & MCI_STATUS_UC) {
3334 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3335 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3336 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3337 return 0;
3338 }
3339 if (banks[1] & MCI_STATUS_VAL)
3340 mce->status |= MCI_STATUS_OVER;
3341 banks[2] = mce->addr;
3342 banks[3] = mce->misc;
3343 vcpu->arch.mcg_status = mce->mcg_status;
3344 banks[1] = mce->status;
3345 kvm_queue_exception(vcpu, MC_VECTOR);
3346 } else if (!(banks[1] & MCI_STATUS_VAL)
3347 || !(banks[1] & MCI_STATUS_UC)) {
3348 if (banks[1] & MCI_STATUS_VAL)
3349 mce->status |= MCI_STATUS_OVER;
3350 banks[2] = mce->addr;
3351 banks[3] = mce->misc;
3352 banks[1] = mce->status;
3353 } else
3354 banks[1] |= MCI_STATUS_OVER;
3355 return 0;
3356}
3357
3cfc3092
JK		 3358static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3359 struct kvm_vcpu_events *events)
3360{
7460fb4a 3361 process_nmi(vcpu);
664f8e26
WL		 3362 /*
3363 * FIXME: pass injected and pending separately. This is only
3364 * needed for nested virtualization, whose state cannot be
3365 * migrated yet. For now we can combine them.
3366 */
03b82a30 3367 events->exception.injected =
664f8e26
WL		 3368 (vcpu->arch.exception.pending ||
3369 vcpu->arch.exception.injected) &&
03b82a30 3370 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3371 events->exception.nr = vcpu->arch.exception.nr;
3372 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3373 events->exception.pad = 0;
3cfc3092
JK		 3374 events->exception.error_code = vcpu->arch.exception.error_code;
3375
03b82a30 3376 events->interrupt.injected =
04140b41 3377 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3378 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3379 events->interrupt.soft = 0;
37ccdcbe 3380 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3381
3382 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3383 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3384 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3385 events->nmi.pad = 0;
3cfc3092 3386
66450a21 3387 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3388
f077825a
PB		 3389 events->smi.smm = is_smm(vcpu);
3390 events->smi.pending = vcpu->arch.smi_pending;
3391 events->smi.smm_inside_nmi =
3392 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3393 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3394
dab4b911 3395 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3396 | KVM_VCPUEVENT_VALID_SHADOW
3397 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3398 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3399}
3400
6ef4e07e
XG		 3401static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3402
3cfc3092
JK		 3403static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3404 struct kvm_vcpu_events *events)
3405{
dab4b911 3406 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3407 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3408 | KVM_VCPUEVENT_VALID_SHADOW
3409 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3410 return -EINVAL;
3411
78e546c8 3412 if (events->exception.injected &&
28d06353
JM		 3413 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3414 is_guest_mode(vcpu)))
78e546c8
PB		 3415 return -EINVAL;
3416
28bf2888
DH		 3417 /* INITs are latched while in SMM */
3418 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3419 (events->smi.smm || events->smi.pending) &&
3420 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3421 return -EINVAL;
3422
7460fb4a 3423 process_nmi(vcpu);
664f8e26 3424 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3425 vcpu->arch.exception.pending = events->exception.injected;
3426 vcpu->arch.exception.nr = events->exception.nr;
3427 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3428 vcpu->arch.exception.error_code = events->exception.error_code;
3429
04140b41 3430 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3431 vcpu->arch.interrupt.nr = events->interrupt.nr;
3432 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3433 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3434 kvm_x86_ops->set_interrupt_shadow(vcpu,
3435 events->interrupt.shadow);
3cfc3092
JK		 3436
3437 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3438 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3439 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3440 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3441
66450a21 3442 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3443 lapic_in_kernel(vcpu))
66450a21 3444 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3445
f077825a 3446 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3447 u32 hflags = vcpu->arch.hflags;
f077825a 3448 if (events->smi.smm)
6ef4e07e 3449 hflags |= HF_SMM_MASK;
f077825a 3450 else
6ef4e07e
XG		 3451 hflags &= ~HF_SMM_MASK;
3452 kvm_set_hflags(vcpu, hflags);
3453
f077825a 3454 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3455
3456 if (events->smi.smm) {
3457 if (events->smi.smm_inside_nmi)
3458 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3459 else
f4ef1910
WL		 3460 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3461 if (lapic_in_kernel(vcpu)) {
3462 if (events->smi.latched_init)
3463 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3464 else
3465 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3466 }
f077825a
PB		 3467 }
3468 }
3469
3842d135
AK		 3470 kvm_make_request(KVM_REQ_EVENT, vcpu);
3471
3cfc3092
JK		 3472 return 0;
3473}
3474
a1efbe77
JK		 3475static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3476 struct kvm_debugregs *dbgregs)
3477{
73aaf249
JK		 3478 unsigned long val;
3479
a1efbe77 3480 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3481 kvm_get_dr(vcpu, 6, &val);
73aaf249 3482 dbgregs->dr6 = val;
a1efbe77
JK		 3483 dbgregs->dr7 = vcpu->arch.dr7;
3484 dbgregs->flags = 0;
97e69aa6 3485 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3486}
3487
3488static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3489 struct kvm_debugregs *dbgregs)
3490{
3491 if (dbgregs->flags)
3492 return -EINVAL;
3493
d14bdb55
PB		 3494 if (dbgregs->dr6 & ~0xffffffffull)
3495 return -EINVAL;
3496 if (dbgregs->dr7 & ~0xffffffffull)
3497 return -EINVAL;
3498
a1efbe77 3499 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3500 kvm_update_dr0123(vcpu);
a1efbe77 3501 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3502 kvm_update_dr6(vcpu);
a1efbe77 3503 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3504 kvm_update_dr7(vcpu);
a1efbe77 3505
a1efbe77
JK		 3506 return 0;
3507}
3508
df1daba7
PB		 3509#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3510
3511static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3512{
c47ada30 3513 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3514 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3515 u64 valid;
3516
3517 /*
3518 * Copy legacy XSAVE area, to avoid complications with CPUID
3519 * leaves 0 and 1 in the loop below.
3520 */
3521 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3522
3523 /* Set XSTATE_BV */
00c87e9a 3524 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3525 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3526
3527 /*
3528 * Copy each region from the possibly compacted offset to the
3529 * non-compacted offset.
3530 */
d91cab78 3531 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3532 while (valid) {
3533 u64 feature = valid & -valid;
3534 int index = fls64(feature) - 1;
3535 void *src = get_xsave_addr(xsave, feature);
3536
3537 if (src) {
3538 u32 size, offset, ecx, edx;
3539 cpuid_count(XSTATE_CPUID, index,
3540 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3541 if (feature == XFEATURE_MASK_PKRU)
3542 memcpy(dest + offset, &vcpu->arch.pkru,
3543 sizeof(vcpu->arch.pkru));
3544 else
3545 memcpy(dest + offset, src, size);
3546
df1daba7
PB		 3547 }
3548
3549 valid -= feature;
3550 }
3551}
3552
3553static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3554{
c47ada30 3555 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3556 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3557 u64 valid;
3558
3559 /*
3560 * Copy legacy XSAVE area, to avoid complications with CPUID
3561 * leaves 0 and 1 in the loop below.
3562 */
3563 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3564
3565 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3566 xsave->header.xfeatures = xstate_bv;
782511b0 3567 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3568 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3569
3570 /*
3571 * Copy each region from the non-compacted offset to the
3572 * possibly compacted offset.
3573 */
d91cab78 3574 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3575 while (valid) {
3576 u64 feature = valid & -valid;
3577 int index = fls64(feature) - 1;
3578 void *dest = get_xsave_addr(xsave, feature);
3579
3580 if (dest) {
3581 u32 size, offset, ecx, edx;
3582 cpuid_count(XSTATE_CPUID, index,
3583 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3584 if (feature == XFEATURE_MASK_PKRU)
3585 memcpy(&vcpu->arch.pkru, src + offset,
3586 sizeof(vcpu->arch.pkru));
3587 else
3588 memcpy(dest, src + offset, size);
ee4100da 3589 }
df1daba7
PB		 3590
3591 valid -= feature;
3592 }
3593}
3594
2d5b5a66
SY		 3595static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3596 struct kvm_xsave *guest_xsave)
3597{
d366bf7e 3598 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3599 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3600 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3601 } else {
2d5b5a66 3602 memcpy(guest_xsave->region,
7366ed77 3603 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3604 sizeof(struct fxregs_state));
2d5b5a66 3605 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3606 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3607 }
3608}
3609
a575813b
WL		 3610#define XSAVE_MXCSR_OFFSET 24
3611
2d5b5a66
SY		 3612static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3613 struct kvm_xsave *guest_xsave)
3614{
3615 u64 xstate_bv =
3616 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3617 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3618
d366bf7e 3619 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3620 /*
3621 * Here we allow setting states that are not present in
3622 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3623 * with old userspace.
3624 */
a575813b
WL		 3625 if (xstate_bv & ~kvm_supported_xcr0() ||
3626 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3627 return -EINVAL;
df1daba7 3628 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3629 } else {
a575813b
WL		 3630 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3631 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3632 return -EINVAL;
7366ed77 3633 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3634 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3635 }
3636 return 0;
3637}
3638
3639static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3640 struct kvm_xcrs *guest_xcrs)
3641{
d366bf7e 3642 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3643 guest_xcrs->nr_xcrs = 0;
3644 return;
3645 }
3646
3647 guest_xcrs->nr_xcrs = 1;
3648 guest_xcrs->flags = 0;
3649 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3650 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3651}
3652
3653static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3654 struct kvm_xcrs *guest_xcrs)
3655{
3656 int i, r = 0;
3657
d366bf7e 3658 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3659 return -EINVAL;
3660
3661 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3662 return -EINVAL;
3663
3664 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3665 /* Only support XCR0 currently */
c67a04cb 3666 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3667 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3668 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3669 break;
3670 }
3671 if (r)
3672 r = -EINVAL;
3673 return r;
3674}
3675
1c0b28c2
EM		 3676/*
3677 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3678 * stopped by the hypervisor. This function will be called from the host only.
3679 * EINVAL is returned when the host attempts to set the flag for a guest that
3680 * does not support pv clocks.
3681 */
3682static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3683{
0b79459b 3684 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3685 return -EINVAL;
51d59c6b 3686 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3687 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3688 return 0;
3689}
3690
5c919412
AS		 3691static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3692 struct kvm_enable_cap *cap)
3693{
3694 if (cap->flags)
3695 return -EINVAL;
3696
3697 switch (cap->cap) {
efc479e6
RK		 3698 case KVM_CAP_HYPERV_SYNIC2:
3699 if (cap->args[0])
3700 return -EINVAL;
5c919412 3701 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3702 if (!irqchip_in_kernel(vcpu->kvm))
3703 return -EINVAL;
efc479e6
RK		 3704 return kvm_hv_activate_synic(vcpu, cap->cap ==
3705 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3706 default:
3707 return -EINVAL;
3708 }
3709}
3710
313a3dc7
CO		 3711long kvm_arch_vcpu_ioctl(struct file *filp,
3712 unsigned int ioctl, unsigned long arg)
3713{
3714 struct kvm_vcpu *vcpu = filp->private_data;
3715 void __user *argp = (void __user *)arg;
3716 int r;
d1ac91d8
AK		 3717 union {
3718 struct kvm_lapic_state *lapic;
3719 struct kvm_xsave *xsave;
3720 struct kvm_xcrs *xcrs;
3721 void *buffer;
3722 } u;
3723
9b062471
CD		 3724 vcpu_load(vcpu);
3725
d1ac91d8 3726 u.buffer = NULL;
313a3dc7
CO		 3727 switch (ioctl) {
3728 case KVM_GET_LAPIC: {
2204ae3c 3729 r = -EINVAL;
bce87cce 3730 if (!lapic_in_kernel(vcpu))
2204ae3c 3731 goto out;
d1ac91d8 3732 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3733
b772ff36 3734 r = -ENOMEM;
d1ac91d8 3735 if (!u.lapic)
b772ff36 3736 goto out;
d1ac91d8 3737 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3738 if (r)
3739 goto out;
3740 r = -EFAULT;
d1ac91d8 3741 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3742 goto out;
3743 r = 0;
3744 break;
3745 }
3746 case KVM_SET_LAPIC: {
2204ae3c 3747 r = -EINVAL;
bce87cce 3748 if (!lapic_in_kernel(vcpu))
2204ae3c 3749 goto out;
ff5c2c03 3750 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3751 if (IS_ERR(u.lapic)) {
3752 r = PTR_ERR(u.lapic);
3753 goto out_nofree;
3754 }
ff5c2c03 3755
d1ac91d8 3756 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3757 break;
3758 }
f77bc6a4
ZX		 3759 case KVM_INTERRUPT: {
3760 struct kvm_interrupt irq;
3761
3762 r = -EFAULT;
3763 if (copy_from_user(&irq, argp, sizeof irq))
3764 goto out;
3765 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3766 break;
3767 }
c4abb7c9
JK		 3768 case KVM_NMI: {
3769 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3770 break;
3771 }
f077825a
PB		 3772 case KVM_SMI: {
3773 r = kvm_vcpu_ioctl_smi(vcpu);
3774 break;
3775 }
313a3dc7
CO		 3776 case KVM_SET_CPUID: {
3777 struct kvm_cpuid __user *cpuid_arg = argp;
3778 struct kvm_cpuid cpuid;
3779
3780 r = -EFAULT;
3781 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3782 goto out;
3783 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3784 break;
3785 }
07716717
DK		 3786 case KVM_SET_CPUID2: {
3787 struct kvm_cpuid2 __user *cpuid_arg = argp;
3788 struct kvm_cpuid2 cpuid;
3789
3790 r = -EFAULT;
3791 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3792 goto out;
3793 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3794 cpuid_arg->entries);
07716717
DK		 3795 break;
3796 }
3797 case KVM_GET_CPUID2: {
3798 struct kvm_cpuid2 __user *cpuid_arg = argp;
3799 struct kvm_cpuid2 cpuid;
3800
3801 r = -EFAULT;
3802 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3803 goto out;
3804 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3805 cpuid_arg->entries);
07716717
DK		 3806 if (r)
3807 goto out;
3808 r = -EFAULT;
3809 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3810 goto out;
3811 r = 0;
3812 break;
3813 }
801e459a
TL		 3814 case KVM_GET_MSRS: {
3815 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3816 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3817 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3818 break;
801e459a
TL		 3819 }
3820 case KVM_SET_MSRS: {
3821 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3822 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3823 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3824 break;
801e459a 3825 }
b209749f
AK		 3826 case KVM_TPR_ACCESS_REPORTING: {
3827 struct kvm_tpr_access_ctl tac;
3828
3829 r = -EFAULT;
3830 if (copy_from_user(&tac, argp, sizeof tac))
3831 goto out;
3832 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3833 if (r)
3834 goto out;
3835 r = -EFAULT;
3836 if (copy_to_user(argp, &tac, sizeof tac))
3837 goto out;
3838 r = 0;
3839 break;
3840 };
b93463aa
AK		 3841 case KVM_SET_VAPIC_ADDR: {
3842 struct kvm_vapic_addr va;
7301d6ab 3843 int idx;
b93463aa
AK		 3844
3845 r = -EINVAL;
35754c98 3846 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3847 goto out;
3848 r = -EFAULT;
3849 if (copy_from_user(&va, argp, sizeof va))
3850 goto out;
7301d6ab 3851 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3852 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3853 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3854 break;
3855 }
890ca9ae
HY		 3856 case KVM_X86_SETUP_MCE: {
3857 u64 mcg_cap;
3858
3859 r = -EFAULT;
3860 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3861 goto out;
3862 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3863 break;
3864 }
3865 case KVM_X86_SET_MCE: {
3866 struct kvm_x86_mce mce;
3867
3868 r = -EFAULT;
3869 if (copy_from_user(&mce, argp, sizeof mce))
3870 goto out;
3871 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3872 break;
3873 }
3cfc3092
JK		 3874 case KVM_GET_VCPU_EVENTS: {
3875 struct kvm_vcpu_events events;
3876
3877 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3878
3879 r = -EFAULT;
3880 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3881 break;
3882 r = 0;
3883 break;
3884 }
3885 case KVM_SET_VCPU_EVENTS: {
3886 struct kvm_vcpu_events events;
3887
3888 r = -EFAULT;
3889 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3890 break;
3891
3892 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3893 break;
3894 }
a1efbe77
JK		 3895 case KVM_GET_DEBUGREGS: {
3896 struct kvm_debugregs dbgregs;
3897
3898 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3899
3900 r = -EFAULT;
3901 if (copy_to_user(argp, &dbgregs,
3902 sizeof(struct kvm_debugregs)))
3903 break;
3904 r = 0;
3905 break;
3906 }
3907 case KVM_SET_DEBUGREGS: {
3908 struct kvm_debugregs dbgregs;
3909
3910 r = -EFAULT;
3911 if (copy_from_user(&dbgregs, argp,
3912 sizeof(struct kvm_debugregs)))
3913 break;
3914
3915 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3916 break;
3917 }
2d5b5a66 3918 case KVM_GET_XSAVE: {
d1ac91d8 3919 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3920 r = -ENOMEM;
d1ac91d8 3921 if (!u.xsave)
2d5b5a66
SY		 3922 break;
3923
d1ac91d8 3924 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3925
3926 r = -EFAULT;
d1ac91d8 3927 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3928 break;
3929 r = 0;
3930 break;
3931 }
3932 case KVM_SET_XSAVE: {
ff5c2c03 3933 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3934 if (IS_ERR(u.xsave)) {
3935 r = PTR_ERR(u.xsave);
3936 goto out_nofree;
3937 }
2d5b5a66 3938
d1ac91d8 3939 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3940 break;
3941 }
3942 case KVM_GET_XCRS: {
d1ac91d8 3943 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3944 r = -ENOMEM;
d1ac91d8 3945 if (!u.xcrs)
2d5b5a66
SY		 3946 break;
3947
d1ac91d8 3948 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3949
3950 r = -EFAULT;
d1ac91d8 3951 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3952 sizeof(struct kvm_xcrs)))
3953 break;
3954 r = 0;
3955 break;
3956 }
3957 case KVM_SET_XCRS: {
ff5c2c03 3958 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3959 if (IS_ERR(u.xcrs)) {
3960 r = PTR_ERR(u.xcrs);
3961 goto out_nofree;
3962 }
2d5b5a66 3963
d1ac91d8 3964 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3965 break;
3966 }
92a1f12d
JR		 3967 case KVM_SET_TSC_KHZ: {
3968 u32 user_tsc_khz;
3969
3970 r = -EINVAL;
92a1f12d
JR		 3971 user_tsc_khz = (u32)arg;
3972
3973 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3974 goto out;
3975
cc578287
ZA		 3976 if (user_tsc_khz == 0)
3977 user_tsc_khz = tsc_khz;
3978
381d585c
HZ		 3979 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3980 r = 0;
92a1f12d 3981
92a1f12d
JR		 3982 goto out;
3983 }
3984 case KVM_GET_TSC_KHZ: {
cc578287 3985 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3986 goto out;
3987 }
1c0b28c2
EM		 3988 case KVM_KVMCLOCK_CTRL: {
3989 r = kvm_set_guest_paused(vcpu);
3990 goto out;
3991 }
5c919412
AS		 3992 case KVM_ENABLE_CAP: {
3993 struct kvm_enable_cap cap;
3994
3995 r = -EFAULT;
3996 if (copy_from_user(&cap, argp, sizeof(cap)))
3997 goto out;
3998 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3999 break;
4000 }
8fcc4b59
JM		 4001 case KVM_GET_NESTED_STATE: {
4002 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4003 u32 user_data_size;
4004
4005 r = -EINVAL;
4006 if (!kvm_x86_ops->get_nested_state)
4007 break;
4008
4009 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
4010 if (get_user(user_data_size, &user_kvm_nested_state->size))
4011 return -EFAULT;
4012
4013 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4014 user_data_size);
4015 if (r < 0)
4016 return r;
4017
4018 if (r > user_data_size) {
4019 if (put_user(r, &user_kvm_nested_state->size))
4020 return -EFAULT;
4021 return -E2BIG;
4022 }
4023 r = 0;
4024 break;
4025 }
4026 case KVM_SET_NESTED_STATE: {
4027 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4028 struct kvm_nested_state kvm_state;
4029
4030 r = -EINVAL;
4031 if (!kvm_x86_ops->set_nested_state)
4032 break;
4033
4034 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
4035 return -EFAULT;
4036
4037 if (kvm_state.size < sizeof(kvm_state))
4038 return -EINVAL;
4039
4040 if (kvm_state.flags &
4041 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE))
4042 return -EINVAL;
4043
4044 /* nested_run_pending implies guest_mode. */
4045 if (kvm_state.flags == KVM_STATE_NESTED_RUN_PENDING)
4046 return -EINVAL;
4047
4048 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
4049 break;
4050 }
313a3dc7
CO		 4051 default:
4052 r = -EINVAL;
4053 }
4054out:
d1ac91d8 4055 kfree(u.buffer);
9b062471
CD		 4056out_nofree:
4057 vcpu_put(vcpu);
313a3dc7
CO		 4058 return r;
4059}
4060
1499fa80 4061vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4062{
4063 return VM_FAULT_SIGBUS;
4064}
4065
1fe779f8
CO		 4066static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4067{
4068 int ret;
4069
4070 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4071 return -EINVAL;
1fe779f8
CO		 4072 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4073 return ret;
4074}
4075
b927a3ce
SY		 4076static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4077 u64 ident_addr)
4078{
2ac52ab8 4079 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4080}
4081
1fe779f8
CO		 4082static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
4083 u32 kvm_nr_mmu_pages)
4084{
4085 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4086 return -EINVAL;
4087
79fac95e 4088 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4089
4090 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4091 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4092
79fac95e 4093 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4094 return 0;
4095}
4096
4097static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
4098{
39de71ec 4099 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4100}
4101
1fe779f8
CO		 4102static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4103{
90bca052 4104 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4105 int r;
4106
4107 r = 0;
4108 switch (chip->chip_id) {
4109 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4110 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4111 sizeof(struct kvm_pic_state));
4112 break;
4113 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4114 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4115 sizeof(struct kvm_pic_state));
4116 break;
4117 case KVM_IRQCHIP_IOAPIC:
33392b49 4118 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4119 break;
4120 default:
4121 r = -EINVAL;
4122 break;
4123 }
4124 return r;
4125}
4126
4127static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4128{
90bca052 4129 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4130 int r;
4131
4132 r = 0;
4133 switch (chip->chip_id) {
4134 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4135 spin_lock(&pic->lock);
4136 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4137 sizeof(struct kvm_pic_state));
90bca052 4138 spin_unlock(&pic->lock);
1fe779f8
CO		 4139 break;
4140 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4141 spin_lock(&pic->lock);
4142 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4143 sizeof(struct kvm_pic_state));
90bca052 4144 spin_unlock(&pic->lock);
1fe779f8
CO		 4145 break;
4146 case KVM_IRQCHIP_IOAPIC:
33392b49 4147 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4148 break;
4149 default:
4150 r = -EINVAL;
4151 break;
4152 }
90bca052 4153 kvm_pic_update_irq(pic);
1fe779f8
CO		 4154 return r;
4155}
4156
e0f63cb9
SY		 4157static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4158{
34f3941c
RK		 4159 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4160
4161 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4162
4163 mutex_lock(&kps->lock);
4164 memcpy(ps, &kps->channels, sizeof(*ps));
4165 mutex_unlock(&kps->lock);
2da29bcc 4166 return 0;
e0f63cb9
SY		 4167}
4168
4169static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4170{
0185604c 4171 int i;
09edea72
RK		 4172 struct kvm_pit *pit = kvm->arch.vpit;
4173
4174 mutex_lock(&pit->pit_state.lock);
34f3941c 4175 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4176 for (i = 0; i < 3; i++)
09edea72
RK		 4177 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4178 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4179 return 0;
e9f42757
BK		 4180}
4181
4182static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4183{
e9f42757
BK		 4184 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4185 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4186 sizeof(ps->channels));
4187 ps->flags = kvm->arch.vpit->pit_state.flags;
4188 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4189 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4190 return 0;
e9f42757
BK		 4191}
4192
4193static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4194{
2da29bcc 4195 int start = 0;
0185604c 4196 int i;
e9f42757 4197 u32 prev_legacy, cur_legacy;
09edea72
RK		 4198 struct kvm_pit *pit = kvm->arch.vpit;
4199
4200 mutex_lock(&pit->pit_state.lock);
4201 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4202 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4203 if (!prev_legacy && cur_legacy)
4204 start = 1;
09edea72
RK		 4205 memcpy(&pit->pit_state.channels, &ps->channels,
4206 sizeof(pit->pit_state.channels));
4207 pit->pit_state.flags = ps->flags;
0185604c 4208 for (i = 0; i < 3; i++)
09edea72 4209 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4210 start && i == 0);
09edea72 4211 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4212 return 0;
e0f63cb9
SY		 4213}
4214
52d939a0
MT		 4215static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4216 struct kvm_reinject_control *control)
4217{
71474e2f
RK		 4218 struct kvm_pit *pit = kvm->arch.vpit;
4219
4220 if (!pit)
52d939a0 4221 return -ENXIO;
b39c90b6 4222
71474e2f
RK		 4223 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4224 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4225 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4226 */
4227 mutex_lock(&pit->pit_state.lock);
4228 kvm_pit_set_reinject(pit, control->pit_reinject);
4229 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4230
52d939a0
MT		 4231 return 0;
4232}
4233
95d4c16c 4234/**
60c34612
TY		 4235 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4236 * @kvm: kvm instance
4237 * @log: slot id and address to which we copy the log
95d4c16c 4238 *
e108ff2f
PB		 4239 * Steps 1-4 below provide general overview of dirty page logging. See
4240 * kvm_get_dirty_log_protect() function description for additional details.
4241 *
4242 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4243 * always flush the TLB (step 4) even if previous step failed and the dirty
4244 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4245 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4246 * writes will be marked dirty for next log read.
95d4c16c 4247 *
60c34612
TY		 4248 * 1. Take a snapshot of the bit and clear it if needed.
4249 * 2. Write protect the corresponding page.
e108ff2f
PB		 4250 * 3. Copy the snapshot to the userspace.
4251 * 4. Flush TLB's if needed.
5bb064dc 4252 */
60c34612 4253int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4254{
60c34612 4255 bool is_dirty = false;
e108ff2f 4256 int r;
5bb064dc 4257
79fac95e 4258 mutex_lock(&kvm->slots_lock);
5bb064dc 4259
88178fd4
KH		 4260 /*
4261 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4262 */
4263 if (kvm_x86_ops->flush_log_dirty)
4264 kvm_x86_ops->flush_log_dirty(kvm);
4265
e108ff2f 4266 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4267
4268 /*
4269 * All the TLBs can be flushed out of mmu lock, see the comments in
4270 * kvm_mmu_slot_remove_write_access().
4271 */
e108ff2f 4272 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4273 if (is_dirty)
4274 kvm_flush_remote_tlbs(kvm);
4275
79fac95e 4276 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4277 return r;
4278}
4279
aa2fbe6d
YZ		 4280int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4281 bool line_status)
23d43cf9
CD		 4282{
4283 if (!irqchip_in_kernel(kvm))
4284 return -ENXIO;
4285
4286 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4287 irq_event->irq, irq_event->level,
4288 line_status);
23d43cf9
CD		 4289 return 0;
4290}
4291
90de4a18
NA		 4292static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4293 struct kvm_enable_cap *cap)
4294{
4295 int r;
4296
4297 if (cap->flags)
4298 return -EINVAL;
4299
4300 switch (cap->cap) {
4301 case KVM_CAP_DISABLE_QUIRKS:
4302 kvm->arch.disabled_quirks = cap->args[0];
4303 r = 0;
4304 break;
49df6397
SR		 4305 case KVM_CAP_SPLIT_IRQCHIP: {
4306 mutex_lock(&kvm->lock);
b053b2ae
SR		 4307 r = -EINVAL;
4308 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4309 goto split_irqchip_unlock;
49df6397
SR		 4310 r = -EEXIST;
4311 if (irqchip_in_kernel(kvm))
4312 goto split_irqchip_unlock;
557abc40 4313 if (kvm->created_vcpus)
49df6397
SR		 4314 goto split_irqchip_unlock;
4315 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4316 if (r)
49df6397
SR		 4317 goto split_irqchip_unlock;
4318 /* Pairs with irqchip_in_kernel. */
4319 smp_wmb();
49776faf 4320 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4321 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4322 r = 0;
4323split_irqchip_unlock:
4324 mutex_unlock(&kvm->lock);
4325 break;
4326 }
37131313
RK		 4327 case KVM_CAP_X2APIC_API:
4328 r = -EINVAL;
4329 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4330 break;
4331
4332 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4333 kvm->arch.x2apic_format = true;
c519265f
RK		 4334 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4335 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4336
4337 r = 0;
4338 break;
4d5422ce
WL		 4339 case KVM_CAP_X86_DISABLE_EXITS:
4340 r = -EINVAL;
4341 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4342 break;
4343
4344 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4345 kvm_can_mwait_in_guest())
4346 kvm->arch.mwait_in_guest = true;
766d3571 4347 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4348 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4349 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4350 kvm->arch.pause_in_guest = true;
4d5422ce
WL		 4351 r = 0;
4352 break;
90de4a18
NA		 4353 default:
4354 r = -EINVAL;
4355 break;
4356 }
4357 return r;
4358}
4359
1fe779f8
CO		 4360long kvm_arch_vm_ioctl(struct file *filp,
4361 unsigned int ioctl, unsigned long arg)
4362{
4363 struct kvm *kvm = filp->private_data;
4364 void __user *argp = (void __user *)arg;
367e1319 4365 int r = -ENOTTY;
f0d66275
DH		 4366 /*
4367 * This union makes it completely explicit to gcc-3.x
4368 * that these two variables' stack usage should be
4369 * combined, not added together.
4370 */
4371 union {
4372 struct kvm_pit_state ps;
e9f42757 4373 struct kvm_pit_state2 ps2;
c5ff41ce 4374 struct kvm_pit_config pit_config;
f0d66275 4375 } u;
1fe779f8
CO		 4376
4377 switch (ioctl) {
4378 case KVM_SET_TSS_ADDR:
4379 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4380 break;
b927a3ce
SY		 4381 case KVM_SET_IDENTITY_MAP_ADDR: {
4382 u64 ident_addr;
4383
1af1ac91
DH		 4384 mutex_lock(&kvm->lock);
4385 r = -EINVAL;
4386 if (kvm->created_vcpus)
4387 goto set_identity_unlock;
b927a3ce
SY		 4388 r = -EFAULT;
4389 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4390 goto set_identity_unlock;
b927a3ce 4391 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4392set_identity_unlock:
4393 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4394 break;
4395 }
1fe779f8
CO		 4396 case KVM_SET_NR_MMU_PAGES:
4397 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4398 break;
4399 case KVM_GET_NR_MMU_PAGES:
4400 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4401 break;
3ddea128 4402 case KVM_CREATE_IRQCHIP: {
3ddea128 4403 mutex_lock(&kvm->lock);
09941366 4404
3ddea128 4405 r = -EEXIST;
35e6eaa3 4406 if (irqchip_in_kernel(kvm))
3ddea128 4407 goto create_irqchip_unlock;
09941366 4408
3e515705 4409 r = -EINVAL;
557abc40 4410 if (kvm->created_vcpus)
3e515705 4411 goto create_irqchip_unlock;
09941366
RK		 4412
4413 r = kvm_pic_init(kvm);
4414 if (r)
3ddea128 4415 goto create_irqchip_unlock;
09941366
RK		 4416
4417 r = kvm_ioapic_init(kvm);
4418 if (r) {
09941366 4419 kvm_pic_destroy(kvm);
3ddea128 4420 goto create_irqchip_unlock;
09941366
RK		 4421 }
4422
399ec807
AK		 4423 r = kvm_setup_default_irq_routing(kvm);
4424 if (r) {
72bb2fcd 4425 kvm_ioapic_destroy(kvm);
09941366 4426 kvm_pic_destroy(kvm);
71ba994c 4427 goto create_irqchip_unlock;
399ec807 4428 }
49776faf 4429 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4430 smp_wmb();
49776faf 4431 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4432 create_irqchip_unlock:
4433 mutex_unlock(&kvm->lock);
1fe779f8 4434 break;
3ddea128 4435 }
7837699f 4436 case KVM_CREATE_PIT:
c5ff41ce
JK		 4437 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4438 goto create_pit;
4439 case KVM_CREATE_PIT2:
4440 r = -EFAULT;
4441 if (copy_from_user(&u.pit_config, argp,
4442 sizeof(struct kvm_pit_config)))
4443 goto out;
4444 create_pit:
250715a6 4445 mutex_lock(&kvm->lock);
269e05e4
AK		 4446 r = -EEXIST;
4447 if (kvm->arch.vpit)
4448 goto create_pit_unlock;
7837699f 4449 r = -ENOMEM;
c5ff41ce 4450 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4451 if (kvm->arch.vpit)
4452 r = 0;
269e05e4 4453 create_pit_unlock:
250715a6 4454 mutex_unlock(&kvm->lock);
7837699f 4455 break;
1fe779f8
CO		 4456 case KVM_GET_IRQCHIP: {
4457 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4458 struct kvm_irqchip *chip;
1fe779f8 4459
ff5c2c03
SL		 4460 chip = memdup_user(argp, sizeof(*chip));
4461 if (IS_ERR(chip)) {
4462 r = PTR_ERR(chip);
1fe779f8 4463 goto out;
ff5c2c03
SL		 4464 }
4465
1fe779f8 4466 r = -ENXIO;
826da321 4467 if (!irqchip_kernel(kvm))
f0d66275
DH		 4468 goto get_irqchip_out;
4469 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4470 if (r)
f0d66275 4471 goto get_irqchip_out;
1fe779f8 4472 r = -EFAULT;
f0d66275
DH		 4473 if (copy_to_user(argp, chip, sizeof *chip))
4474 goto get_irqchip_out;
1fe779f8 4475 r = 0;
f0d66275
DH		 4476 get_irqchip_out:
4477 kfree(chip);
1fe779f8
CO		 4478 break;
4479 }
4480 case KVM_SET_IRQCHIP: {
4481 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4482 struct kvm_irqchip *chip;
1fe779f8 4483
ff5c2c03
SL		 4484 chip = memdup_user(argp, sizeof(*chip));
4485 if (IS_ERR(chip)) {
4486 r = PTR_ERR(chip);
1fe779f8 4487 goto out;
ff5c2c03
SL		 4488 }
4489
1fe779f8 4490 r = -ENXIO;
826da321 4491 if (!irqchip_kernel(kvm))
f0d66275
DH		 4492 goto set_irqchip_out;
4493 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4494 if (r)
f0d66275 4495 goto set_irqchip_out;
1fe779f8 4496 r = 0;
f0d66275
DH		 4497 set_irqchip_out:
4498 kfree(chip);
1fe779f8
CO		 4499 break;
4500 }
e0f63cb9 4501 case KVM_GET_PIT: {
e0f63cb9 4502 r = -EFAULT;
f0d66275 4503 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4504 goto out;
4505 r = -ENXIO;
4506 if (!kvm->arch.vpit)
4507 goto out;
f0d66275 4508 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4509 if (r)
4510 goto out;
4511 r = -EFAULT;
f0d66275 4512 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4513 goto out;
4514 r = 0;
4515 break;
4516 }
4517 case KVM_SET_PIT: {
e0f63cb9 4518 r = -EFAULT;
f0d66275 4519 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4520 goto out;
4521 r = -ENXIO;
4522 if (!kvm->arch.vpit)
4523 goto out;
f0d66275 4524 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4525 break;
4526 }
e9f42757
BK		 4527 case KVM_GET_PIT2: {
4528 r = -ENXIO;
4529 if (!kvm->arch.vpit)
4530 goto out;
4531 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4532 if (r)
4533 goto out;
4534 r = -EFAULT;
4535 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4536 goto out;
4537 r = 0;
4538 break;
4539 }
4540 case KVM_SET_PIT2: {
4541 r = -EFAULT;
4542 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4543 goto out;
4544 r = -ENXIO;
4545 if (!kvm->arch.vpit)
4546 goto out;
4547 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4548 break;
4549 }
52d939a0
MT		 4550 case KVM_REINJECT_CONTROL: {
4551 struct kvm_reinject_control control;
4552 r = -EFAULT;
4553 if (copy_from_user(&control, argp, sizeof(control)))
4554 goto out;
4555 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4556 break;
4557 }
d71ba788
PB		 4558 case KVM_SET_BOOT_CPU_ID:
4559 r = 0;
4560 mutex_lock(&kvm->lock);
557abc40 4561 if (kvm->created_vcpus)
d71ba788
PB		 4562 r = -EBUSY;
4563 else
4564 kvm->arch.bsp_vcpu_id = arg;
4565 mutex_unlock(&kvm->lock);
4566 break;
ffde22ac 4567 case KVM_XEN_HVM_CONFIG: {
51776043 4568 struct kvm_xen_hvm_config xhc;
ffde22ac 4569 r = -EFAULT;
51776043 4570 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4571 goto out;
4572 r = -EINVAL;
51776043 4573 if (xhc.flags)
ffde22ac 4574 goto out;
51776043 4575 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4576 r = 0;
4577 break;
4578 }
afbcf7ab 4579 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4580 struct kvm_clock_data user_ns;
4581 u64 now_ns;
afbcf7ab
GC		 4582
4583 r = -EFAULT;
4584 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4585 goto out;
4586
4587 r = -EINVAL;
4588 if (user_ns.flags)
4589 goto out;
4590
4591 r = 0;
0bc48bea
RK		 4592 /*
4593 * TODO: userspace has to take care of races with VCPU_RUN, so
4594 * kvm_gen_update_masterclock() can be cut down to locked
4595 * pvclock_update_vm_gtod_copy().
4596 */
4597 kvm_gen_update_masterclock(kvm);
e891a32e 4598 now_ns = get_kvmclock_ns(kvm);
108b249c 4599 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4600 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4601 break;
4602 }
4603 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4604 struct kvm_clock_data user_ns;
4605 u64 now_ns;
4606
e891a32e 4607 now_ns = get_kvmclock_ns(kvm);
108b249c 4608 user_ns.clock = now_ns;
e3fd9a93 4609 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4610 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4611
4612 r = -EFAULT;
4613 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4614 goto out;
4615 r = 0;
4616 break;
4617 }
90de4a18
NA		 4618 case KVM_ENABLE_CAP: {
4619 struct kvm_enable_cap cap;
afbcf7ab 4620
90de4a18
NA		 4621 r = -EFAULT;
4622 if (copy_from_user(&cap, argp, sizeof(cap)))
4623 goto out;
4624 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4625 break;
4626 }
5acc5c06
BS		 4627 case KVM_MEMORY_ENCRYPT_OP: {
4628 r = -ENOTTY;
4629 if (kvm_x86_ops->mem_enc_op)
4630 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4631 break;
4632 }
69eaedee
BS		 4633 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4634 struct kvm_enc_region region;
4635
4636 r = -EFAULT;
4637 if (copy_from_user(&region, argp, sizeof(region)))
4638 goto out;
4639
4640 r = -ENOTTY;
4641 if (kvm_x86_ops->mem_enc_reg_region)
4642 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4643 break;
4644 }
4645 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4646 struct kvm_enc_region region;
4647
4648 r = -EFAULT;
4649 if (copy_from_user(&region, argp, sizeof(region)))
4650 goto out;
4651
4652 r = -ENOTTY;
4653 if (kvm_x86_ops->mem_enc_unreg_region)
4654 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4655 break;
4656 }
faeb7833
RK		 4657 case KVM_HYPERV_EVENTFD: {
4658 struct kvm_hyperv_eventfd hvevfd;
4659
4660 r = -EFAULT;
4661 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4662 goto out;
4663 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4664 break;
4665 }
1fe779f8 4666 default:
ad6260da 4667 r = -ENOTTY;
1fe779f8
CO		 4668 }
4669out:
4670 return r;
4671}
4672
a16b043c 4673static void kvm_init_msr_list(void)
043405e1
CO		 4674{
4675 u32 dummy[2];
4676 unsigned i, j;
4677
62ef68bb 4678 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4679 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4680 continue;
93c4adc7
PB		 4681
4682 /*
4683 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4684 * to the guests in some cases.
93c4adc7
PB		 4685 */
4686 switch (msrs_to_save[i]) {
4687 case MSR_IA32_BNDCFGS:
4688 if (!kvm_x86_ops->mpx_supported())
4689 continue;
4690 break;
9dbe6cf9
PB		 4691 case MSR_TSC_AUX:
4692 if (!kvm_x86_ops->rdtscp_supported())
4693 continue;
4694 break;
93c4adc7
PB		 4695 default:
4696 break;
4697 }
4698
043405e1
CO		 4699 if (j < i)
4700 msrs_to_save[j] = msrs_to_save[i];
4701 j++;
4702 }
4703 num_msrs_to_save = j;
62ef68bb
PB		 4704
4705 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
bc226f07
TL		 4706 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4707 continue;
62ef68bb
PB		 4708
4709 if (j < i)
4710 emulated_msrs[j] = emulated_msrs[i];
4711 j++;
4712 }
4713 num_emulated_msrs = j;
801e459a
TL		 4714
4715 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4716 struct kvm_msr_entry msr;
4717
4718 msr.index = msr_based_features[i];
66421c1e 4719 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4720 continue;
4721
4722 if (j < i)
4723 msr_based_features[j] = msr_based_features[i];
4724 j++;
4725 }
4726 num_msr_based_features = j;
043405e1
CO		 4727}
4728
bda9020e
MT		 4729static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4730 const void *v)
bbd9b64e 4731{
70252a10
AK		 4732 int handled = 0;
4733 int n;
4734
4735 do {
4736 n = min(len, 8);
bce87cce 4737 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4738 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4739 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4740 break;
4741 handled += n;
4742 addr += n;
4743 len -= n;
4744 v += n;
4745 } while (len);
bbd9b64e 4746
70252a10 4747 return handled;
bbd9b64e
CO		 4748}
4749
bda9020e 4750static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4751{
70252a10
AK		 4752 int handled = 0;
4753 int n;
4754
4755 do {
4756 n = min(len, 8);
bce87cce 4757 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4758 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4759 addr, n, v))
4760 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4761 break;
e39d200f 4762 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4763 handled += n;
4764 addr += n;
4765 len -= n;
4766 v += n;
4767 } while (len);
bbd9b64e 4768
70252a10 4769 return handled;
bbd9b64e
CO		 4770}
4771
2dafc6c2
GN		 4772static void kvm_set_segment(struct kvm_vcpu *vcpu,
4773 struct kvm_segment *var, int seg)
4774{
4775 kvm_x86_ops->set_segment(vcpu, var, seg);
4776}
4777
4778void kvm_get_segment(struct kvm_vcpu *vcpu,
4779 struct kvm_segment *var, int seg)
4780{
4781 kvm_x86_ops->get_segment(vcpu, var, seg);
4782}
4783
54987b7a
PB		 4784gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4785 struct x86_exception *exception)
02f59dc9
JR		 4786{
4787 gpa_t t_gpa;
02f59dc9
JR		 4788
4789 BUG_ON(!mmu_is_nested(vcpu));
4790
4791 /* NPT walks are always user-walks */
4792 access |= PFERR_USER_MASK;
54987b7a 4793 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4794
4795 return t_gpa;
4796}
4797
ab9ae313
AK		 4798gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4799 struct x86_exception *exception)
1871c602
GN		 4800{
4801 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4802 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4803}
4804
ab9ae313
AK		 4805 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4806 struct x86_exception *exception)
1871c602
GN		 4807{
4808 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4809 access |= PFERR_FETCH_MASK;
ab9ae313 4810 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4811}
4812
ab9ae313
AK		 4813gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4814 struct x86_exception *exception)
1871c602
GN		 4815{
4816 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4817 access |= PFERR_WRITE_MASK;
ab9ae313 4818 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4819}
4820
4821/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4822gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4823 struct x86_exception *exception)
1871c602 4824{
ab9ae313 4825 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4826}
4827
4828static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4829 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4830 struct x86_exception *exception)
bbd9b64e
CO		 4831{
4832 void *data = val;
10589a46 4833 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4834
4835 while (bytes) {
14dfe855 4836 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4837 exception);
bbd9b64e 4838 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4839 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4840 int ret;
4841
bcc55cba 4842 if (gpa == UNMAPPED_GVA)
ab9ae313 4843 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4844 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4845 offset, toread);
10589a46 4846 if (ret < 0) {
c3cd7ffa 4847 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4848 goto out;
4849 }
bbd9b64e 4850
77c2002e
IE		 4851 bytes -= toread;
4852 data += toread;
4853 addr += toread;
bbd9b64e 4854 }
10589a46 4855out:
10589a46 4856 return r;
bbd9b64e 4857}
77c2002e 4858
1871c602 4859/* used for instruction fetching */
0f65dd70
AK		 4860static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4861 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4862 struct x86_exception *exception)
1871c602 4863{
0f65dd70 4864 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4865 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4866 unsigned offset;
4867 int ret;
0f65dd70 4868
44583cba
PB		 4869 /* Inline kvm_read_guest_virt_helper for speed. */
4870 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4871 exception);
4872 if (unlikely(gpa == UNMAPPED_GVA))
4873 return X86EMUL_PROPAGATE_FAULT;
4874
4875 offset = addr & (PAGE_SIZE-1);
4876 if (WARN_ON(offset + bytes > PAGE_SIZE))
4877 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4878 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4879 offset, bytes);
44583cba
PB		 4880 if (unlikely(ret < 0))
4881 return X86EMUL_IO_NEEDED;
4882
4883 return X86EMUL_CONTINUE;
1871c602
GN		 4884}
4885
ce14e868 4886int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 4887 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4888 struct x86_exception *exception)
1871c602
GN		 4889{
4890 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4891
1871c602 4892 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4893 exception);
1871c602 4894}
064aea77 4895EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4896
ce14e868
PB		 4897static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
4898 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 4899 struct x86_exception *exception, bool system)
1871c602 4900{
0f65dd70 4901 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 4902 u32 access = 0;
4903
4904 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4905 access |= PFERR_USER_MASK;
4906
4907 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 4908}
4909
7a036a6f
RK		 4910static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4911 unsigned long addr, void *val, unsigned int bytes)
4912{
4913 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4914 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4915
4916 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4917}
4918
ce14e868
PB		 4919static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4920 struct kvm_vcpu *vcpu, u32 access,
4921 struct x86_exception *exception)
77c2002e
IE		 4922{
4923 void *data = val;
4924 int r = X86EMUL_CONTINUE;
4925
4926 while (bytes) {
14dfe855 4927 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 4928 access,
ab9ae313 4929 exception);
77c2002e
IE		 4930 unsigned offset = addr & (PAGE_SIZE-1);
4931 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4932 int ret;
4933
bcc55cba 4934 if (gpa == UNMAPPED_GVA)
ab9ae313 4935 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4936 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4937 if (ret < 0) {
c3cd7ffa 4938 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4939 goto out;
4940 }
4941
4942 bytes -= towrite;
4943 data += towrite;
4944 addr += towrite;
4945 }
4946out:
4947 return r;
4948}
ce14e868
PB		 4949
4950static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 4951 unsigned int bytes, struct x86_exception *exception,
4952 bool system)
ce14e868
PB		 4953{
4954 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 4955 u32 access = PFERR_WRITE_MASK;
4956
4957 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
4958 access |= PFERR_USER_MASK;
ce14e868
PB		 4959
4960 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 4961 access, exception);
ce14e868
PB		 4962}
4963
4964int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
4965 unsigned int bytes, struct x86_exception *exception)
4966{
c595ceee
PB		 4967 /* kvm_write_guest_virt_system can pull in tons of pages. */
4968 vcpu->arch.l1tf_flush_l1d = true;
4969
ce14e868
PB		 4970 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
4971 PFERR_WRITE_MASK, exception);
4972}
6a4d7550 4973EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4974
082d06ed
WL		 4975int handle_ud(struct kvm_vcpu *vcpu)
4976{
6c86eedc 4977 int emul_type = EMULTYPE_TRAP_UD;
082d06ed 4978 enum emulation_result er;
6c86eedc
WL		 4979 char sig[5]; /* ud2; .ascii "kvm" */
4980 struct x86_exception e;
4981
4982 if (force_emulation_prefix &&
3c9fa24c
PB		 4983 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
4984 sig, sizeof(sig), &e) == 0 &&
6c86eedc
WL		 4985 memcmp(sig, "\xf\xbkvm", sizeof(sig)) == 0) {
4986 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
4987 emul_type = 0;
4988 }
082d06ed 4989
6c86eedc 4990 er = emulate_instruction(vcpu, emul_type);
082d06ed
WL		 4991 if (er == EMULATE_USER_EXIT)
4992 return 0;
4993 if (er != EMULATE_DONE)
4994 kvm_queue_exception(vcpu, UD_VECTOR);
4995 return 1;
4996}
4997EXPORT_SYMBOL_GPL(handle_ud);
4998
0f89b207
TL		 4999static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5000 gpa_t gpa, bool write)
5001{
5002 /* For APIC access vmexit */
5003 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5004 return 1;
5005
5006 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5007 trace_vcpu_match_mmio(gva, gpa, write, true);
5008 return 1;
5009 }
5010
5011 return 0;
5012}
5013
af7cc7d1
XG		 5014static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5015 gpa_t *gpa, struct x86_exception *exception,
5016 bool write)
5017{
97d64b78
AK		 5018 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5019 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5020
be94f6b7
HH		 5021 /*
5022 * currently PKRU is only applied to ept enabled guest so
5023 * there is no pkey in EPT page table for L1 guest or EPT
5024 * shadow page table for L2 guest.
5025 */
97d64b78 5026 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5027 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 5028 vcpu->arch.access, 0, access)) {
bebb106a
XG		 5029 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5030 (gva & (PAGE_SIZE - 1));
4f022648 5031 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5032 return 1;
5033 }
5034
af7cc7d1
XG		 5035 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5036
5037 if (*gpa == UNMAPPED_GVA)
5038 return -1;
5039
0f89b207 5040 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5041}
5042
3200f405 5043int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5044 const void *val, int bytes)
bbd9b64e
CO		 5045{
5046 int ret;
5047
54bf36aa 5048 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5049 if (ret < 0)
bbd9b64e 5050 return 0;
0eb05bf2 5051 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5052 return 1;
5053}
5054
77d197b2
XG		 5055struct read_write_emulator_ops {
5056 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5057 int bytes);
5058 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5059 void *val, int bytes);
5060 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5061 int bytes, void *val);
5062 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5063 void *val, int bytes);
5064 bool write;
5065};
5066
5067static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5068{
5069 if (vcpu->mmio_read_completed) {
77d197b2 5070 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5071 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5072 vcpu->mmio_read_completed = 0;
5073 return 1;
5074 }
5075
5076 return 0;
5077}
5078
5079static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5080 void *val, int bytes)
5081{
54bf36aa 5082 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5083}
5084
5085static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5086 void *val, int bytes)
5087{
5088 return emulator_write_phys(vcpu, gpa, val, bytes);
5089}
5090
5091static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5092{
e39d200f 5093 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5094 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5095}
5096
5097static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5098 void *val, int bytes)
5099{
e39d200f 5100 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5101 return X86EMUL_IO_NEEDED;
5102}
5103
5104static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5105 void *val, int bytes)
5106{
f78146b0
AK		 5107 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5108
87da7e66 5109 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5110 return X86EMUL_CONTINUE;
5111}
5112
0fbe9b0b 5113static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5114 .read_write_prepare = read_prepare,
5115 .read_write_emulate = read_emulate,
5116 .read_write_mmio = vcpu_mmio_read,
5117 .read_write_exit_mmio = read_exit_mmio,
5118};
5119
0fbe9b0b 5120static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5121 .read_write_emulate = write_emulate,
5122 .read_write_mmio = write_mmio,
5123 .read_write_exit_mmio = write_exit_mmio,
5124 .write = true,
5125};
5126
22388a3c
XG		 5127static int emulator_read_write_onepage(unsigned long addr, void *val,
5128 unsigned int bytes,
5129 struct x86_exception *exception,
5130 struct kvm_vcpu *vcpu,
0fbe9b0b 5131 const struct read_write_emulator_ops *ops)
bbd9b64e 5132{
af7cc7d1
XG		 5133 gpa_t gpa;
5134 int handled, ret;
22388a3c 5135 bool write = ops->write;
f78146b0 5136 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5137 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5138
5139 /*
5140 * If the exit was due to a NPF we may already have a GPA.
5141 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5142 * Note, this cannot be used on string operations since string
5143 * operation using rep will only have the initial GPA from the NPF
5144 * occurred.
5145 */
5146 if (vcpu->arch.gpa_available &&
5147 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5148 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5149 gpa = vcpu->arch.gpa_val;
5150 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5151 } else {
5152 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5153 if (ret < 0)
5154 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5155 }
10589a46 5156
618232e2 5157 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5158 return X86EMUL_CONTINUE;
5159
bbd9b64e
CO		 5160 /*
5161 * Is this MMIO handled locally?
5162 */
22388a3c 5163 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5164 if (handled == bytes)
bbd9b64e 5165 return X86EMUL_CONTINUE;
bbd9b64e 5166
70252a10
AK		 5167 gpa += handled;
5168 bytes -= handled;
5169 val += handled;
5170
87da7e66
XG		 5171 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5172 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5173 frag->gpa = gpa;
5174 frag->data = val;
5175 frag->len = bytes;
f78146b0 5176 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5177}
5178
52eb5a6d
XL		 5179static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5180 unsigned long addr,
22388a3c
XG		 5181 void *val, unsigned int bytes,
5182 struct x86_exception *exception,
0fbe9b0b 5183 const struct read_write_emulator_ops *ops)
bbd9b64e 5184{
0f65dd70 5185 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5186 gpa_t gpa;
5187 int rc;
5188
5189 if (ops->read_write_prepare &&
5190 ops->read_write_prepare(vcpu, val, bytes))
5191 return X86EMUL_CONTINUE;
5192
5193 vcpu->mmio_nr_fragments = 0;
0f65dd70 5194
bbd9b64e
CO		 5195 /* Crossing a page boundary? */
5196 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5197 int now;
bbd9b64e
CO		 5198
5199 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5200 rc = emulator_read_write_onepage(addr, val, now, exception,
5201 vcpu, ops);
5202
bbd9b64e
CO		 5203 if (rc != X86EMUL_CONTINUE)
5204 return rc;
5205 addr += now;
bac15531
NA		 5206 if (ctxt->mode != X86EMUL_MODE_PROT64)
5207 addr = (u32)addr;
bbd9b64e
CO		 5208 val += now;
5209 bytes -= now;
5210 }
22388a3c 5211
f78146b0
AK		 5212 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5213 vcpu, ops);
5214 if (rc != X86EMUL_CONTINUE)
5215 return rc;
5216
5217 if (!vcpu->mmio_nr_fragments)
5218 return rc;
5219
5220 gpa = vcpu->mmio_fragments[0].gpa;
5221
5222 vcpu->mmio_needed = 1;
5223 vcpu->mmio_cur_fragment = 0;
5224
87da7e66 5225 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5226 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5227 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5228 vcpu->run->mmio.phys_addr = gpa;
5229
5230 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5231}
5232
5233static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5234 unsigned long addr,
5235 void *val,
5236 unsigned int bytes,
5237 struct x86_exception *exception)
5238{
5239 return emulator_read_write(ctxt, addr, val, bytes,
5240 exception, &read_emultor);
5241}
5242
52eb5a6d 5243static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5244 unsigned long addr,
5245 const void *val,
5246 unsigned int bytes,
5247 struct x86_exception *exception)
5248{
5249 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5250 exception, &write_emultor);
bbd9b64e 5251}
bbd9b64e 5252
daea3e73
AK		 5253#define CMPXCHG_TYPE(t, ptr, old, new) \
5254 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5255
5256#ifdef CONFIG_X86_64
5257# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5258#else
5259# define CMPXCHG64(ptr, old, new) \
9749a6c0 5260 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5261#endif
5262
0f65dd70
AK		 5263static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5264 unsigned long addr,
bbd9b64e
CO		 5265 const void *old,
5266 const void *new,
5267 unsigned int bytes,
0f65dd70 5268 struct x86_exception *exception)
bbd9b64e 5269{
0f65dd70 5270 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5271 gpa_t gpa;
5272 struct page *page;
5273 char *kaddr;
5274 bool exchanged;
2bacc55c 5275
daea3e73
AK		 5276 /* guests cmpxchg8b have to be emulated atomically */
5277 if (bytes > 8 || (bytes & (bytes - 1)))
5278 goto emul_write;
10589a46 5279
daea3e73 5280 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5281
daea3e73
AK		 5282 if (gpa == UNMAPPED_GVA ||
5283 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5284 goto emul_write;
2bacc55c 5285
daea3e73
AK		 5286 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5287 goto emul_write;
72dc67a6 5288
54bf36aa 5289 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5290 if (is_error_page(page))
c19b8bd6 5291 goto emul_write;
72dc67a6 5292
8fd75e12 5293 kaddr = kmap_atomic(page);
daea3e73
AK		 5294 kaddr += offset_in_page(gpa);
5295 switch (bytes) {
5296 case 1:
5297 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5298 break;
5299 case 2:
5300 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5301 break;
5302 case 4:
5303 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5304 break;
5305 case 8:
5306 exchanged = CMPXCHG64(kaddr, old, new);
5307 break;
5308 default:
5309 BUG();
2bacc55c 5310 }
8fd75e12 5311 kunmap_atomic(kaddr);
daea3e73
AK		 5312 kvm_release_page_dirty(page);
5313
5314 if (!exchanged)
5315 return X86EMUL_CMPXCHG_FAILED;
5316
54bf36aa 5317 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5318 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5319
5320 return X86EMUL_CONTINUE;
4a5f48f6 5321
3200f405 5322emul_write:
daea3e73 5323 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5324
0f65dd70 5325 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5326}
5327
cf8f70bf
GN		 5328static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5329{
cbfc6c91 5330 int r = 0, i;
cf8f70bf 5331
cbfc6c91
WL		 5332 for (i = 0; i < vcpu->arch.pio.count; i++) {
5333 if (vcpu->arch.pio.in)
5334 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5335 vcpu->arch.pio.size, pd);
5336 else
5337 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5338 vcpu->arch.pio.port, vcpu->arch.pio.size,
5339 pd);
5340 if (r)
5341 break;
5342 pd += vcpu->arch.pio.size;
5343 }
cf8f70bf
GN		 5344 return r;
5345}
5346
6f6fbe98
XG		 5347static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5348 unsigned short port, void *val,
5349 unsigned int count, bool in)
cf8f70bf 5350{
cf8f70bf 5351 vcpu->arch.pio.port = port;
6f6fbe98 5352 vcpu->arch.pio.in = in;
7972995b 5353 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5354 vcpu->arch.pio.size = size;
5355
5356 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5357 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5358 return 1;
5359 }
5360
5361 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5362 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5363 vcpu->run->io.size = size;
5364 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5365 vcpu->run->io.count = count;
5366 vcpu->run->io.port = port;
5367
5368 return 0;
5369}
5370
6f6fbe98
XG		 5371static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5372 int size, unsigned short port, void *val,
5373 unsigned int count)
cf8f70bf 5374{
ca1d4a9e 5375 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5376 int ret;
ca1d4a9e 5377
6f6fbe98
XG		 5378 if (vcpu->arch.pio.count)
5379 goto data_avail;
cf8f70bf 5380
cbfc6c91
WL		 5381 memset(vcpu->arch.pio_data, 0, size * count);
5382
6f6fbe98
XG		 5383 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5384 if (ret) {
5385data_avail:
5386 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5387 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5388 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5389 return 1;
5390 }
5391
cf8f70bf
GN		 5392 return 0;
5393}
5394
6f6fbe98
XG		 5395static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5396 int size, unsigned short port,
5397 const void *val, unsigned int count)
5398{
5399 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5400
5401 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5402 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5403 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5404}
5405
bbd9b64e
CO		 5406static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5407{
5408 return kvm_x86_ops->get_segment_base(vcpu, seg);
5409}
5410
3cb16fe7 5411static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5412{
3cb16fe7 5413 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5414}
5415
ae6a2375 5416static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5417{
5418 if (!need_emulate_wbinvd(vcpu))
5419 return X86EMUL_CONTINUE;
5420
5421 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5422 int cpu = get_cpu();
5423
5424 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5425 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5426 wbinvd_ipi, NULL, 1);
2eec7343 5427 put_cpu();
f5f48ee1 5428 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5429 } else
5430 wbinvd();
f5f48ee1
SY		 5431 return X86EMUL_CONTINUE;
5432}
5cb56059
JS		 5433
5434int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5435{
6affcbed
KH		 5436 kvm_emulate_wbinvd_noskip(vcpu);
5437 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5438}
f5f48ee1
SY		 5439EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5440
5cb56059
JS		 5441
5442
bcaf5cc5
AK		 5443static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5444{
5cb56059 5445 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5446}
5447
52eb5a6d
XL		 5448static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5449 unsigned long *dest)
bbd9b64e 5450{
16f8a6f9 5451 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5452}
5453
52eb5a6d
XL		 5454static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5455 unsigned long value)
bbd9b64e 5456{
338dbc97 5457
717746e3 5458 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5459}
5460
52a46617 5461static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5462{
52a46617 5463 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5464}
5465
717746e3 5466static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5467{
717746e3 5468 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5469 unsigned long value;
5470
5471 switch (cr) {
5472 case 0:
5473 value = kvm_read_cr0(vcpu);
5474 break;
5475 case 2:
5476 value = vcpu->arch.cr2;
5477 break;
5478 case 3:
9f8fe504 5479 value = kvm_read_cr3(vcpu);
52a46617
GN		 5480 break;
5481 case 4:
5482 value = kvm_read_cr4(vcpu);
5483 break;
5484 case 8:
5485 value = kvm_get_cr8(vcpu);
5486 break;
5487 default:
a737f256 5488 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5489 return 0;
5490 }
5491
5492 return value;
5493}
5494
717746e3 5495static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5496{
717746e3 5497 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5498 int res = 0;
5499
52a46617
GN		 5500 switch (cr) {
5501 case 0:
49a9b07e 5502 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5503 break;
5504 case 2:
5505 vcpu->arch.cr2 = val;
5506 break;
5507 case 3:
2390218b 5508 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5509 break;
5510 case 4:
a83b29c6 5511 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5512 break;
5513 case 8:
eea1cff9 5514 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5515 break;
5516 default:
a737f256 5517 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5518 res = -1;
52a46617 5519 }
0f12244f
GN		 5520
5521 return res;
52a46617
GN		 5522}
5523
717746e3 5524static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5525{
717746e3 5526 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5527}
5528
4bff1e86 5529static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5530{
4bff1e86 5531 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5532}
5533
4bff1e86 5534static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5535{
4bff1e86 5536 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5537}
5538
1ac9d0cf
AK		 5539static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5540{
5541 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5542}
5543
5544static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5545{
5546 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5547}
5548
4bff1e86
AK		 5549static unsigned long emulator_get_cached_segment_base(
5550 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5551{
4bff1e86 5552 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5553}
5554
1aa36616
AK		 5555static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5556 struct desc_struct *desc, u32 *base3,
5557 int seg)
2dafc6c2
GN		 5558{
5559 struct kvm_segment var;
5560
4bff1e86 5561 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5562 *selector = var.selector;
2dafc6c2 5563
378a8b09
GN		 5564 if (var.unusable) {
5565 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5566 if (base3)
5567 *base3 = 0;
2dafc6c2 5568 return false;
378a8b09 5569 }
2dafc6c2
GN		 5570
5571 if (var.g)
5572 var.limit >>= 12;
5573 set_desc_limit(desc, var.limit);
5574 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5575#ifdef CONFIG_X86_64
5576 if (base3)
5577 *base3 = var.base >> 32;
5578#endif
2dafc6c2
GN		 5579 desc->type = var.type;
5580 desc->s = var.s;
5581 desc->dpl = var.dpl;
5582 desc->p = var.present;
5583 desc->avl = var.avl;
5584 desc->l = var.l;
5585 desc->d = var.db;
5586 desc->g = var.g;
5587
5588 return true;
5589}
5590
1aa36616
AK		 5591static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5592 struct desc_struct *desc, u32 base3,
5593 int seg)
2dafc6c2 5594{
4bff1e86 5595 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5596 struct kvm_segment var;
5597
1aa36616 5598 var.selector = selector;
2dafc6c2 5599 var.base = get_desc_base(desc);
5601d05b
GN		 5600#ifdef CONFIG_X86_64
5601 var.base |= ((u64)base3) << 32;
5602#endif
2dafc6c2
GN		 5603 var.limit = get_desc_limit(desc);
5604 if (desc->g)
5605 var.limit = (var.limit << 12) | 0xfff;
5606 var.type = desc->type;
2dafc6c2
GN		 5607 var.dpl = desc->dpl;
5608 var.db = desc->d;
5609 var.s = desc->s;
5610 var.l = desc->l;
5611 var.g = desc->g;
5612 var.avl = desc->avl;
5613 var.present = desc->p;
5614 var.unusable = !var.present;
5615 var.padding = 0;
5616
5617 kvm_set_segment(vcpu, &var, seg);
5618 return;
5619}
5620
717746e3
AK		 5621static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5622 u32 msr_index, u64 *pdata)
5623{
609e36d3
PB		 5624 struct msr_data msr;
5625 int r;
5626
5627 msr.index = msr_index;
5628 msr.host_initiated = false;
5629 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5630 if (r)
5631 return r;
5632
5633 *pdata = msr.data;
5634 return 0;
717746e3
AK		 5635}
5636
5637static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5638 u32 msr_index, u64 data)
5639{
8fe8ab46
WA		 5640 struct msr_data msr;
5641
5642 msr.data = data;
5643 msr.index = msr_index;
5644 msr.host_initiated = false;
5645 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5646}
5647
64d60670
PB		 5648static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5649{
5650 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5651
5652 return vcpu->arch.smbase;
5653}
5654
5655static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5656{
5657 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5658
5659 vcpu->arch.smbase = smbase;
5660}
5661
67f4d428
NA		 5662static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5663 u32 pmc)
5664{
c6702c9d 5665 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5666}
5667
222d21aa
AK		 5668static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5669 u32 pmc, u64 *pdata)
5670{
c6702c9d 5671 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5672}
5673
6c3287f7
AK		 5674static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5675{
5676 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5677}
5678
2953538e 5679static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5680 struct x86_instruction_info *info,
c4f035c6
AK		 5681 enum x86_intercept_stage stage)
5682{
2953538e 5683 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5684}
5685
e911eb3b
YZ		 5686static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5687 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5688{
e911eb3b 5689 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5690}
5691
dd856efa
AK		 5692static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5693{
5694 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5695}
5696
5697static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5698{
5699 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5700}
5701
801806d9
NA		 5702static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5703{
5704 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5705}
5706
6ed071f0
LP		 5707static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5708{
5709 return emul_to_vcpu(ctxt)->arch.hflags;
5710}
5711
5712static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5713{
5714 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5715}
5716
0234bf88
LP		 5717static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5718{
5719 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5720}
5721
0225fb50 5722static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5723 .read_gpr = emulator_read_gpr,
5724 .write_gpr = emulator_write_gpr,
ce14e868
PB		 5725 .read_std = emulator_read_std,
5726 .write_std = emulator_write_std,
7a036a6f 5727 .read_phys = kvm_read_guest_phys_system,
1871c602 5728 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5729 .read_emulated = emulator_read_emulated,
5730 .write_emulated = emulator_write_emulated,
5731 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5732 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5733 .pio_in_emulated = emulator_pio_in_emulated,
5734 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5735 .get_segment = emulator_get_segment,
5736 .set_segment = emulator_set_segment,
5951c442 5737 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5738 .get_gdt = emulator_get_gdt,
160ce1f1 5739 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5740 .set_gdt = emulator_set_gdt,
5741 .set_idt = emulator_set_idt,
52a46617
GN		 5742 .get_cr = emulator_get_cr,
5743 .set_cr = emulator_set_cr,
9c537244 5744 .cpl = emulator_get_cpl,
35aa5375
GN		 5745 .get_dr = emulator_get_dr,
5746 .set_dr = emulator_set_dr,
64d60670
PB		 5747 .get_smbase = emulator_get_smbase,
5748 .set_smbase = emulator_set_smbase,
717746e3
AK		 5749 .set_msr = emulator_set_msr,
5750 .get_msr = emulator_get_msr,
67f4d428 5751 .check_pmc = emulator_check_pmc,
222d21aa 5752 .read_pmc = emulator_read_pmc,
6c3287f7 5753 .halt = emulator_halt,
bcaf5cc5 5754 .wbinvd = emulator_wbinvd,
d6aa1000 5755 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5756 .intercept = emulator_intercept,
bdb42f5a 5757 .get_cpuid = emulator_get_cpuid,
801806d9 5758 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5759 .get_hflags = emulator_get_hflags,
5760 .set_hflags = emulator_set_hflags,
0234bf88 5761 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5762};
5763
95cb2295
GN		 5764static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5765{
37ccdcbe 5766 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5767 /*
5768 * an sti; sti; sequence only disable interrupts for the first
5769 * instruction. So, if the last instruction, be it emulated or
5770 * not, left the system with the INT_STI flag enabled, it
5771 * means that the last instruction is an sti. We should not
5772 * leave the flag on in this case. The same goes for mov ss
5773 */
37ccdcbe
PB		 5774 if (int_shadow & mask)
5775 mask = 0;
6addfc42 5776 if (unlikely(int_shadow || mask)) {
95cb2295 5777 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5778 if (!mask)
5779 kvm_make_request(KVM_REQ_EVENT, vcpu);
5780 }
95cb2295
GN		 5781}
5782
ef54bcfe 5783static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5784{
5785 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5786 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5787 return kvm_propagate_fault(vcpu, &ctxt->exception);
5788
5789 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5790 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5791 ctxt->exception.error_code);
54b8486f 5792 else
da9cb575 5793 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5794 return false;
54b8486f
GN		 5795}
5796
8ec4722d
MG		 5797static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5798{
adf52235 5799 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5800 int cs_db, cs_l;
5801
8ec4722d
MG		 5802 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5803
adf52235 5804 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5805 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5806
adf52235
TY		 5807 ctxt->eip = kvm_rip_read(vcpu);
5808 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5809 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5810 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5811 cs_db ? X86EMUL_MODE_PROT32 :
5812 X86EMUL_MODE_PROT16;
a584539b 5813 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5814 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5815 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5816
dd856efa 5817 init_decode_cache(ctxt);
7ae441ea 5818 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5819}
5820
71f9833b 5821int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5822{
9d74191a 5823 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5824 int ret;
5825
5826 init_emulate_ctxt(vcpu);
5827
9dac77fa
AK		 5828 ctxt->op_bytes = 2;
5829 ctxt->ad_bytes = 2;
5830 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5831 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5832
5833 if (ret != X86EMUL_CONTINUE)
5834 return EMULATE_FAIL;
5835
9dac77fa 5836 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5837 kvm_rip_write(vcpu, ctxt->eip);
5838 kvm_set_rflags(vcpu, ctxt->eflags);
63995653 5839
63995653
MG		 5840 return EMULATE_DONE;
5841}
5842EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5843
e2366171 5844static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 5845{
fc3a9157
JR		 5846 int r = EMULATE_DONE;
5847
6d77dbfc
GN		 5848 ++vcpu->stat.insn_emulation_fail;
5849 trace_kvm_emulate_insn_failed(vcpu);
e2366171
LA		 5850
5851 if (emulation_type & EMULTYPE_NO_UD_ON_FAIL)
5852 return EMULATE_FAIL;
5853
a2b9e6c1 5854 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5855 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5856 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5857 vcpu->run->internal.ndata = 0;
1f4dcb3b 5858 r = EMULATE_USER_EXIT;
fc3a9157 5859 }
e2366171 5860
6d77dbfc 5861 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5862
5863 return r;
6d77dbfc
GN		 5864}
5865
93c05d3e 5866static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5867 bool write_fault_to_shadow_pgtable,
5868 int emulation_type)
a6f177ef 5869{
95b3cf69 5870 gpa_t gpa = cr2;
ba049e93 5871 kvm_pfn_t pfn;
a6f177ef 5872
384bf221 5873 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 5874 return false;
5875
6c3dfeb6
SC		 5876 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
5877 return false;
5878
95b3cf69
XG		 5879 if (!vcpu->arch.mmu.direct_map) {
5880 /*
5881 * Write permission should be allowed since only
5882 * write access need to be emulated.
5883 */
5884 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5885
95b3cf69
XG		 5886 /*
5887 * If the mapping is invalid in guest, let cpu retry
5888 * it to generate fault.
5889 */
5890 if (gpa == UNMAPPED_GVA)
5891 return true;
5892 }
a6f177ef 5893
8e3d9d06
XG		 5894 /*
5895 * Do not retry the unhandleable instruction if it faults on the
5896 * readonly host memory, otherwise it will goto a infinite loop:
5897 * retry instruction -> write #PF -> emulation fail -> retry
5898 * instruction -> ...
5899 */
5900 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5901
5902 /*
5903 * If the instruction failed on the error pfn, it can not be fixed,
5904 * report the error to userspace.
5905 */
5906 if (is_error_noslot_pfn(pfn))
5907 return false;
5908
5909 kvm_release_pfn_clean(pfn);
5910
5911 /* The instructions are well-emulated on direct mmu. */
5912 if (vcpu->arch.mmu.direct_map) {
5913 unsigned int indirect_shadow_pages;
5914
5915 spin_lock(&vcpu->kvm->mmu_lock);
5916 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5917 spin_unlock(&vcpu->kvm->mmu_lock);
5918
5919 if (indirect_shadow_pages)
5920 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5921
a6f177ef 5922 return true;
8e3d9d06 5923 }
a6f177ef 5924
95b3cf69
XG		 5925 /*
5926 * if emulation was due to access to shadowed page table
5927 * and it failed try to unshadow page and re-enter the
5928 * guest to let CPU execute the instruction.
5929 */
5930 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5931
5932 /*
5933 * If the access faults on its page table, it can not
5934 * be fixed by unprotecting shadow page and it should
5935 * be reported to userspace.
5936 */
5937 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5938}
5939
1cb3f3ae
XG		 5940static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5941 unsigned long cr2, int emulation_type)
5942{
5943 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5944 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5945
5946 last_retry_eip = vcpu->arch.last_retry_eip;
5947 last_retry_addr = vcpu->arch.last_retry_addr;
5948
5949 /*
5950 * If the emulation is caused by #PF and it is non-page_table
5951 * writing instruction, it means the VM-EXIT is caused by shadow
5952 * page protected, we can zap the shadow page and retry this
5953 * instruction directly.
5954 *
5955 * Note: if the guest uses a non-page-table modifying instruction
5956 * on the PDE that points to the instruction, then we will unmap
5957 * the instruction and go to an infinite loop. So, we cache the
5958 * last retried eip and the last fault address, if we meet the eip
5959 * and the address again, we can break out of the potential infinite
5960 * loop.
5961 */
5962 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5963
384bf221 5964 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 5965 return false;
5966
6c3dfeb6
SC		 5967 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
5968 return false;
5969
1cb3f3ae
XG		 5970 if (x86_page_table_writing_insn(ctxt))
5971 return false;
5972
5973 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5974 return false;
5975
5976 vcpu->arch.last_retry_eip = ctxt->eip;
5977 vcpu->arch.last_retry_addr = cr2;
5978
5979 if (!vcpu->arch.mmu.direct_map)
5980 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5981
22368028 5982 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5983
5984 return true;
5985}
5986
716d51ab
GN		 5987static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5988static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5989
64d60670 5990static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5991{
64d60670 5992 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5993 /* This is a good place to trace that we are exiting SMM. */
5994 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5995
c43203ca
PB		 5996 /* Process a latched INIT or SMI, if any. */
5997 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5998 }
699023e2
PB		 5999
6000 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6001}
6002
6003static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
6004{
6005 unsigned changed = vcpu->arch.hflags ^ emul_flags;
6006
a584539b 6007 vcpu->arch.hflags = emul_flags;
64d60670
PB		 6008
6009 if (changed & HF_SMM_MASK)
6010 kvm_smm_changed(vcpu);
a584539b
PB		 6011}
6012
4a1e10d5
PB		 6013static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6014 unsigned long *db)
6015{
6016 u32 dr6 = 0;
6017 int i;
6018 u32 enable, rwlen;
6019
6020 enable = dr7;
6021 rwlen = dr7 >> 16;
6022 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6023 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6024 dr6 |= (1 << i);
6025 return dr6;
6026}
6027
c8401dda 6028static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 6029{
6030 struct kvm_run *kvm_run = vcpu->run;
6031
c8401dda
PB		 6032 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6033 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6034 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6035 kvm_run->debug.arch.exception = DB_VECTOR;
6036 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6037 *r = EMULATE_USER_EXIT;
6038 } else {
6039 /*
6040 * "Certain debug exceptions may clear bit 0-3. The
6041 * remaining contents of the DR6 register are never
6042 * cleared by the processor".
6043 */
6044 vcpu->arch.dr6 &= ~15;
6045 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
6046 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 6047 }
6048}
6049
6affcbed
KH		 6050int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6051{
6052 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
6053 int r = EMULATE_DONE;
6054
6055 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 6056
6057 /*
6058 * rflags is the old, "raw" value of the flags. The new value has
6059 * not been saved yet.
6060 *
6061 * This is correct even for TF set by the guest, because "the
6062 * processor will not generate this exception after the instruction
6063 * that sets the TF flag".
6064 */
6065 if (unlikely(rflags & X86_EFLAGS_TF))
6066 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 6067 return r == EMULATE_DONE;
6068}
6069EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6070
4a1e10d5
PB		 6071static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6072{
4a1e10d5
PB		 6073 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6074 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6075 struct kvm_run *kvm_run = vcpu->run;
6076 unsigned long eip = kvm_get_linear_rip(vcpu);
6077 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6078 vcpu->arch.guest_debug_dr7,
6079 vcpu->arch.eff_db);
6080
6081 if (dr6 != 0) {
6f43ed01 6082 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6083 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6084 kvm_run->debug.arch.exception = DB_VECTOR;
6085 kvm_run->exit_reason = KVM_EXIT_DEBUG;
6086 *r = EMULATE_USER_EXIT;
6087 return true;
6088 }
6089 }
6090
4161a569
NA		 6091 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6092 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6093 unsigned long eip = kvm_get_linear_rip(vcpu);
6094 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6095 vcpu->arch.dr7,
6096 vcpu->arch.db);
6097
6098 if (dr6 != 0) {
6099 vcpu->arch.dr6 &= ~15;
6f43ed01 6100 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 6101 kvm_queue_exception(vcpu, DB_VECTOR);
6102 *r = EMULATE_DONE;
6103 return true;
6104 }
6105 }
6106
6107 return false;
6108}
6109
04789b66
LA		 6110static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6111{
2d7921c4
AM		 6112 switch (ctxt->opcode_len) {
6113 case 1:
6114 switch (ctxt->b) {
6115 case 0xe4: /* IN */
6116 case 0xe5:
6117 case 0xec:
6118 case 0xed:
6119 case 0xe6: /* OUT */
6120 case 0xe7:
6121 case 0xee:
6122 case 0xef:
6123 case 0x6c: /* INS */
6124 case 0x6d:
6125 case 0x6e: /* OUTS */
6126 case 0x6f:
6127 return true;
6128 }
6129 break;
6130 case 2:
6131 switch (ctxt->b) {
6132 case 0x33: /* RDPMC */
6133 return true;
6134 }
6135 break;
04789b66
LA		 6136 }
6137
6138 return false;
6139}
6140
51d8b661
AP		 6141int x86_emulate_instruction(struct kvm_vcpu *vcpu,
6142 unsigned long cr2,
dc25e89e
AP		 6143 int emulation_type,
6144 void *insn,
6145 int insn_len)
bbd9b64e 6146{
95cb2295 6147 int r;
9d74191a 6148 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6149 bool writeback = true;
93c05d3e 6150 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6151
c595ceee
PB		 6152 vcpu->arch.l1tf_flush_l1d = true;
6153
93c05d3e
XG		 6154 /*
6155 * Clear write_fault_to_shadow_pgtable here to ensure it is
6156 * never reused.
6157 */
6158 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6159 kvm_clear_exception_queue(vcpu);
8d7d8102 6160
571008da 6161 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6162 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6163
6164 /*
6165 * We will reenter on the same instruction since
6166 * we do not set complete_userspace_io. This does not
6167 * handle watchpoints yet, those would be handled in
6168 * the emulate_ops.
6169 */
d391f120
VK		 6170 if (!(emulation_type & EMULTYPE_SKIP) &&
6171 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6172 return r;
6173
9d74191a
TY		 6174 ctxt->interruptibility = 0;
6175 ctxt->have_exception = false;
e0ad0b47 6176 ctxt->exception.vector = -1;
9d74191a 6177 ctxt->perm_ok = false;
bbd9b64e 6178
b51e974f 6179 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6180
9d74191a 6181 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6182
e46479f8 6183 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6184 ++vcpu->stat.insn_emulation;
1d2887e2 6185 if (r != EMULATION_OK) {
4005996e
AK		 6186 if (emulation_type & EMULTYPE_TRAP_UD)
6187 return EMULATE_FAIL;
991eebf9
GN		 6188 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6189 emulation_type))
bbd9b64e 6190 return EMULATE_DONE;
6ea6e843
PB		 6191 if (ctxt->have_exception && inject_emulated_exception(vcpu))
6192 return EMULATE_DONE;
6d77dbfc
GN		 6193 if (emulation_type & EMULTYPE_SKIP)
6194 return EMULATE_FAIL;
e2366171 6195 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6196 }
6197 }
6198
04789b66
LA		 6199 if ((emulation_type & EMULTYPE_VMWARE) &&
6200 !is_vmware_backdoor_opcode(ctxt))
6201 return EMULATE_FAIL;
6202
ba8afb6b 6203 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6204 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6205 if (ctxt->eflags & X86_EFLAGS_RF)
6206 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 6207 return EMULATE_DONE;
6208 }
6209
1cb3f3ae
XG		 6210 if (retry_instruction(ctxt, cr2, emulation_type))
6211 return EMULATE_DONE;
6212
7ae441ea 6213 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6214 changes registers values during IO operation */
7ae441ea
GN		 6215 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6216 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6217 emulator_invalidate_register_cache(ctxt);
7ae441ea 6218 }
4d2179e1 6219
5cd21917 6220restart:
0f89b207
TL		 6221 /* Save the faulting GPA (cr2) in the address field */
6222 ctxt->exception.address = cr2;
6223
9d74191a 6224 r = x86_emulate_insn(ctxt);
bbd9b64e 6225
775fde86
JR		 6226 if (r == EMULATION_INTERCEPTED)
6227 return EMULATE_DONE;
6228
d2ddd1c4 6229 if (r == EMULATION_FAILED) {
991eebf9
GN		 6230 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
6231 emulation_type))
c3cd7ffa
GN		 6232 return EMULATE_DONE;
6233
e2366171 6234 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6235 }
6236
9d74191a 6237 if (ctxt->have_exception) {
d2ddd1c4 6238 r = EMULATE_DONE;
ef54bcfe
PB		 6239 if (inject_emulated_exception(vcpu))
6240 return r;
d2ddd1c4 6241 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6242 if (!vcpu->arch.pio.in) {
6243 /* FIXME: return into emulator if single-stepping. */
3457e419 6244 vcpu->arch.pio.count = 0;
0912c977 6245 } else {
7ae441ea 6246 writeback = false;
716d51ab
GN		 6247 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6248 }
ac0a48c3 6249 r = EMULATE_USER_EXIT;
7ae441ea
GN		 6250 } else if (vcpu->mmio_needed) {
6251 if (!vcpu->mmio_is_write)
6252 writeback = false;
ac0a48c3 6253 r = EMULATE_USER_EXIT;
716d51ab 6254 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6255 } else if (r == EMULATION_RESTART)
5cd21917 6256 goto restart;
d2ddd1c4
GN		 6257 else
6258 r = EMULATE_DONE;
f850e2e6 6259
7ae441ea 6260 if (writeback) {
6addfc42 6261 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6262 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6263 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6264 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6265 if (r == EMULATE_DONE &&
6266 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6267 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6268 if (!ctxt->have_exception ||
6269 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6270 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6271
6272 /*
6273 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6274 * do nothing, and it will be requested again as soon as
6275 * the shadow expires. But we still need to check here,
6276 * because POPF has no interrupt shadow.
6277 */
6278 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6279 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6280 } else
6281 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6282
6283 return r;
de7d789a 6284}
51d8b661 6285EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6286
dca7f128
SC		 6287static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6288 unsigned short port)
de7d789a 6289{
cf8f70bf 6290 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6291 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6292 size, port, &val, 1);
cf8f70bf 6293 /* do not return to emulator after return from userspace */
7972995b 6294 vcpu->arch.pio.count = 0;
de7d789a
CO		 6295 return ret;
6296}
de7d789a 6297
8370c3d0
TL		 6298static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6299{
6300 unsigned long val;
6301
6302 /* We should only ever be called with arch.pio.count equal to 1 */
6303 BUG_ON(vcpu->arch.pio.count != 1);
6304
6305 /* For size less than 4 we merge, else we zero extend */
6306 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6307 : 0;
6308
6309 /*
6310 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6311 * the copy and tracing
6312 */
6313 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6314 vcpu->arch.pio.port, &val, 1);
6315 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6316
6317 return 1;
6318}
6319
dca7f128
SC		 6320static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6321 unsigned short port)
8370c3d0
TL		 6322{
6323 unsigned long val;
6324 int ret;
6325
6326 /* For size less than 4 we merge, else we zero extend */
6327 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6328
6329 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6330 &val, 1);
6331 if (ret) {
6332 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6333 return ret;
6334 }
6335
6336 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6337
6338 return 0;
6339}
dca7f128
SC		 6340
6341int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6342{
6343 int ret = kvm_skip_emulated_instruction(vcpu);
6344
6345 /*
6346 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6347 * KVM_EXIT_DEBUG here.
6348 */
6349 if (in)
6350 return kvm_fast_pio_in(vcpu, size, port) && ret;
6351 else
6352 return kvm_fast_pio_out(vcpu, size, port) && ret;
6353}
6354EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 6355
251a5fd6 6356static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6357{
0a3aee0d 6358 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6359 return 0;
8cfdc000
ZA		 6360}
6361
6362static void tsc_khz_changed(void *data)
c8076604 6363{
8cfdc000
ZA		 6364 struct cpufreq_freqs *freq = data;
6365 unsigned long khz = 0;
6366
6367 if (data)
6368 khz = freq->new;
6369 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6370 khz = cpufreq_quick_get(raw_smp_processor_id());
6371 if (!khz)
6372 khz = tsc_khz;
0a3aee0d 6373 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6374}
6375
5fa4ec9c 6376#ifdef CONFIG_X86_64
0092e434
VK		 6377static void kvm_hyperv_tsc_notifier(void)
6378{
0092e434
VK		 6379 struct kvm *kvm;
6380 struct kvm_vcpu *vcpu;
6381 int cpu;
6382
6383 spin_lock(&kvm_lock);
6384 list_for_each_entry(kvm, &vm_list, vm_list)
6385 kvm_make_mclock_inprogress_request(kvm);
6386
6387 hyperv_stop_tsc_emulation();
6388
6389 /* TSC frequency always matches when on Hyper-V */
6390 for_each_present_cpu(cpu)
6391 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6392 kvm_max_guest_tsc_khz = tsc_khz;
6393
6394 list_for_each_entry(kvm, &vm_list, vm_list) {
6395 struct kvm_arch *ka = &kvm->arch;
6396
6397 spin_lock(&ka->pvclock_gtod_sync_lock);
6398
6399 pvclock_update_vm_gtod_copy(kvm);
6400
6401 kvm_for_each_vcpu(cpu, vcpu, kvm)
6402 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6403
6404 kvm_for_each_vcpu(cpu, vcpu, kvm)
6405 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6406
6407 spin_unlock(&ka->pvclock_gtod_sync_lock);
6408 }
6409 spin_unlock(&kvm_lock);
0092e434 6410}
5fa4ec9c 6411#endif
0092e434 6412
c8076604
GH		 6413static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6414 void *data)
6415{
6416 struct cpufreq_freqs *freq = data;
6417 struct kvm *kvm;
6418 struct kvm_vcpu *vcpu;
6419 int i, send_ipi = 0;
6420
8cfdc000
ZA		 6421 /*
6422 * We allow guests to temporarily run on slowing clocks,
6423 * provided we notify them after, or to run on accelerating
6424 * clocks, provided we notify them before. Thus time never
6425 * goes backwards.
6426 *
6427 * However, we have a problem. We can't atomically update
6428 * the frequency of a given CPU from this function; it is
6429 * merely a notifier, which can be called from any CPU.
6430 * Changing the TSC frequency at arbitrary points in time
6431 * requires a recomputation of local variables related to
6432 * the TSC for each VCPU. We must flag these local variables
6433 * to be updated and be sure the update takes place with the
6434 * new frequency before any guests proceed.
6435 *
6436 * Unfortunately, the combination of hotplug CPU and frequency
6437 * change creates an intractable locking scenario; the order
6438 * of when these callouts happen is undefined with respect to
6439 * CPU hotplug, and they can race with each other. As such,
6440 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6441 * undefined; you can actually have a CPU frequency change take
6442 * place in between the computation of X and the setting of the
6443 * variable. To protect against this problem, all updates of
6444 * the per_cpu tsc_khz variable are done in an interrupt
6445 * protected IPI, and all callers wishing to update the value
6446 * must wait for a synchronous IPI to complete (which is trivial
6447 * if the caller is on the CPU already). This establishes the
6448 * necessary total order on variable updates.
6449 *
6450 * Note that because a guest time update may take place
6451 * anytime after the setting of the VCPU's request bit, the
6452 * correct TSC value must be set before the request. However,
6453 * to ensure the update actually makes it to any guest which
6454 * starts running in hardware virtualization between the set
6455 * and the acquisition of the spinlock, we must also ping the
6456 * CPU after setting the request bit.
6457 *
6458 */
6459
c8076604
GH		 6460 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6461 return 0;
6462 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6463 return 0;
8cfdc000
ZA		 6464
6465 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6466
2f303b74 6467 spin_lock(&kvm_lock);
c8076604 6468 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6469 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6470 if (vcpu->cpu != freq->cpu)
6471 continue;
c285545f 6472 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6473 if (vcpu->cpu != smp_processor_id())
8cfdc000 6474 send_ipi = 1;
c8076604
GH		 6475 }
6476 }
2f303b74 6477 spin_unlock(&kvm_lock);
c8076604
GH		 6478
6479 if (freq->old < freq->new && send_ipi) {
6480 /*
6481 * We upscale the frequency. Must make the guest
6482 * doesn't see old kvmclock values while running with
6483 * the new frequency, otherwise we risk the guest sees
6484 * time go backwards.
6485 *
6486 * In case we update the frequency for another cpu
6487 * (which might be in guest context) send an interrupt
6488 * to kick the cpu out of guest context. Next time
6489 * guest context is entered kvmclock will be updated,
6490 * so the guest will not see stale values.
6491 */
8cfdc000 6492 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6493 }
6494 return 0;
6495}
6496
6497static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6498 .notifier_call = kvmclock_cpufreq_notifier
6499};
6500
251a5fd6 6501static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6502{
251a5fd6
SAS		 6503 tsc_khz_changed(NULL);
6504 return 0;
8cfdc000
ZA		 6505}
6506
b820cc0c
ZA		 6507static void kvm_timer_init(void)
6508{
c285545f 6509 max_tsc_khz = tsc_khz;
460dd42e 6510
b820cc0c 6511 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6512#ifdef CONFIG_CPU_FREQ
6513 struct cpufreq_policy policy;
758f588d
BP		 6514 int cpu;
6515
c285545f 6516 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6517 cpu = get_cpu();
6518 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6519 if (policy.cpuinfo.max_freq)
6520 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6521 put_cpu();
c285545f 6522#endif
b820cc0c
ZA		 6523 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6524 CPUFREQ_TRANSITION_NOTIFIER);
6525 }
c285545f 6526 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6527
73c1b41e 6528 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6529 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6530}
6531
dd60d217
AK		 6532DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6533EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 6534
f5132b01 6535int kvm_is_in_guest(void)
ff9d07a0 6536{
086c9855 6537 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6538}
6539
6540static int kvm_is_user_mode(void)
6541{
6542 int user_mode = 3;
dcf46b94 6543
086c9855
AS		 6544 if (__this_cpu_read(current_vcpu))
6545 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6546
ff9d07a0
ZY		 6547 return user_mode != 0;
6548}
6549
6550static unsigned long kvm_get_guest_ip(void)
6551{
6552 unsigned long ip = 0;
dcf46b94 6553
086c9855
AS		 6554 if (__this_cpu_read(current_vcpu))
6555 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6556
ff9d07a0
ZY		 6557 return ip;
6558}
6559
6560static struct perf_guest_info_callbacks kvm_guest_cbs = {
6561 .is_in_guest = kvm_is_in_guest,
6562 .is_user_mode = kvm_is_user_mode,
6563 .get_guest_ip = kvm_get_guest_ip,
6564};
6565
ce88decf
XG		 6566static void kvm_set_mmio_spte_mask(void)
6567{
6568 u64 mask;
6569 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6570
6571 /*
6572 * Set the reserved bits and the present bit of an paging-structure
6573 * entry to generate page fault with PFER.RSV = 1.
6574 */
28a1f3ac
JS		 6575
6576 /*
6577 * Mask the uppermost physical address bit, which would be reserved as
6578 * long as the supported physical address width is less than 52.
6579 */
6580 mask = 1ull << 51;
885032b9 6581
885032b9 6582 /* Set the present bit. */
ce88decf
XG		 6583 mask |= 1ull;
6584
ce88decf
XG		 6585 /*
6586 * If reserved bit is not supported, clear the present bit to disable
6587 * mmio page fault.
6588 */
7288bde1 6589 if (IS_ENABLED(CONFIG_X86_64) && maxphyaddr == 52)
ce88decf 6590 mask &= ~1ull;
ce88decf 6591
dcdca5fe 6592 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6593}
6594
16e8d74d
MT		 6595#ifdef CONFIG_X86_64
6596static void pvclock_gtod_update_fn(struct work_struct *work)
6597{
d828199e
MT		 6598 struct kvm *kvm;
6599
6600 struct kvm_vcpu *vcpu;
6601 int i;
6602
2f303b74 6603 spin_lock(&kvm_lock);
d828199e
MT		 6604 list_for_each_entry(kvm, &vm_list, vm_list)
6605 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6606 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6607 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6608 spin_unlock(&kvm_lock);
16e8d74d
MT		 6609}
6610
6611static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6612
6613/*
6614 * Notification about pvclock gtod data update.
6615 */
6616static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6617 void *priv)
6618{
6619 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6620 struct timekeeper *tk = priv;
6621
6622 update_pvclock_gtod(tk);
6623
6624 /* disable master clock if host does not trust, or does not
b0c39dc6 6625 * use, TSC based clocksource.
16e8d74d 6626 */
b0c39dc6 6627 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6628 atomic_read(&kvm_guest_has_master_clock) != 0)
6629 queue_work(system_long_wq, &pvclock_gtod_work);
6630
6631 return 0;
6632}
6633
6634static struct notifier_block pvclock_gtod_notifier = {
6635 .notifier_call = pvclock_gtod_notify,
6636};
6637#endif
6638
f8c16bba 6639int kvm_arch_init(void *opaque)
043405e1 6640{
b820cc0c 6641 int r;
6b61edf7 6642 struct kvm_x86_ops *ops = opaque;
f8c16bba 6643
f8c16bba
ZX		 6644 if (kvm_x86_ops) {
6645 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6646 r = -EEXIST;
6647 goto out;
f8c16bba
ZX		 6648 }
6649
6650 if (!ops->cpu_has_kvm_support()) {
6651 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6652 r = -EOPNOTSUPP;
6653 goto out;
f8c16bba
ZX		 6654 }
6655 if (ops->disabled_by_bios()) {
6656 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6657 r = -EOPNOTSUPP;
6658 goto out;
f8c16bba
ZX		 6659 }
6660
013f6a5d
MT		 6661 r = -ENOMEM;
6662 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6663 if (!shared_msrs) {
6664 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6665 goto out;
6666 }
6667
97db56ce
AK		 6668 r = kvm_mmu_module_init();
6669 if (r)
013f6a5d 6670 goto out_free_percpu;
97db56ce 6671
ce88decf 6672 kvm_set_mmio_spte_mask();
97db56ce 6673
f8c16bba 6674 kvm_x86_ops = ops;
920c8377 6675
7b52345e 6676 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6677 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6678 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6679 kvm_timer_init();
c8076604 6680
ff9d07a0
ZY		 6681 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6682
d366bf7e 6683 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6684 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6685
c5cc421b 6686 kvm_lapic_init();
16e8d74d
MT		 6687#ifdef CONFIG_X86_64
6688 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6689
5fa4ec9c 6690 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6691 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6692#endif
6693
f8c16bba 6694 return 0;
56c6d28a 6695
013f6a5d
MT		 6696out_free_percpu:
6697 free_percpu(shared_msrs);
56c6d28a 6698out:
56c6d28a 6699 return r;
043405e1 6700}
8776e519 6701
f8c16bba
ZX		 6702void kvm_arch_exit(void)
6703{
0092e434 6704#ifdef CONFIG_X86_64
5fa4ec9c 6705 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6706 clear_hv_tscchange_cb();
6707#endif
cef84c30 6708 kvm_lapic_exit();
ff9d07a0
ZY		 6709 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6710
888d256e
JK		 6711 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6712 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6713 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6714 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6715#ifdef CONFIG_X86_64
6716 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6717#endif
f8c16bba 6718 kvm_x86_ops = NULL;
56c6d28a 6719 kvm_mmu_module_exit();
013f6a5d 6720 free_percpu(shared_msrs);
56c6d28a 6721}
f8c16bba 6722
5cb56059 6723int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6724{
6725 ++vcpu->stat.halt_exits;
35754c98 6726 if (lapic_in_kernel(vcpu)) {
a4535290 6727 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6728 return 1;
6729 } else {
6730 vcpu->run->exit_reason = KVM_EXIT_HLT;
6731 return 0;
6732 }
6733}
5cb56059
JS		 6734EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6735
6736int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6737{
6affcbed
KH		 6738 int ret = kvm_skip_emulated_instruction(vcpu);
6739 /*
6740 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6741 * KVM_EXIT_DEBUG here.
6742 */
6743 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6744}
8776e519
HB		 6745EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6746
8ef81a9a 6747#ifdef CONFIG_X86_64
55dd00a7
MT		 6748static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6749 unsigned long clock_type)
6750{
6751 struct kvm_clock_pairing clock_pairing;
899a31f5 6752 struct timespec64 ts;
80fbd89c 6753 u64 cycle;
55dd00a7
MT		 6754 int ret;
6755
6756 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6757 return -KVM_EOPNOTSUPP;
6758
6759 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6760 return -KVM_EOPNOTSUPP;
6761
6762 clock_pairing.sec = ts.tv_sec;
6763 clock_pairing.nsec = ts.tv_nsec;
6764 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6765 clock_pairing.flags = 0;
6766
6767 ret = 0;
6768 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6769 sizeof(struct kvm_clock_pairing)))
6770 ret = -KVM_EFAULT;
6771
6772 return ret;
6773}
8ef81a9a 6774#endif
55dd00a7 6775
6aef266c
SV		 6776/*
6777 * kvm_pv_kick_cpu_op: Kick a vcpu.
6778 *
6779 * @apicid - apicid of vcpu to be kicked.
6780 */
6781static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6782{
24d2166b 6783 struct kvm_lapic_irq lapic_irq;
6aef266c 6784
24d2166b
R		 6785 lapic_irq.shorthand = 0;
6786 lapic_irq.dest_mode = 0;
ebd28fcb 6787 lapic_irq.level = 0;
24d2166b 6788 lapic_irq.dest_id = apicid;
93bbf0b8 6789 lapic_irq.msi_redir_hint = false;
6aef266c 6790
24d2166b 6791 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6792 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6793}
6794
d62caabb
AS		 6795void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6796{
6797 vcpu->arch.apicv_active = false;
6798 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6799}
6800
8776e519
HB		 6801int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6802{
6803 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 6804 int op_64_bit;
8776e519 6805
696ca779
RK		 6806 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6807 return kvm_hv_hypercall(vcpu);
55cd8e5a 6808
5fdbf976
MT		 6809 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6810 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6811 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6812 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6813 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6814
229456fc 6815 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6816
a449c7aa
NA		 6817 op_64_bit = is_64_bit_mode(vcpu);
6818 if (!op_64_bit) {
8776e519
HB		 6819 nr &= 0xFFFFFFFF;
6820 a0 &= 0xFFFFFFFF;
6821 a1 &= 0xFFFFFFFF;
6822 a2 &= 0xFFFFFFFF;
6823 a3 &= 0xFFFFFFFF;
6824 }
6825
07708c4a
JK		 6826 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6827 ret = -KVM_EPERM;
696ca779 6828 goto out;
07708c4a
JK		 6829 }
6830
8776e519 6831 switch (nr) {
b93463aa
AK		 6832 case KVM_HC_VAPIC_POLL_IRQ:
6833 ret = 0;
6834 break;
6aef266c
SV		 6835 case KVM_HC_KICK_CPU:
6836 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6837 ret = 0;
6838 break;
8ef81a9a 6839#ifdef CONFIG_X86_64
55dd00a7
MT		 6840 case KVM_HC_CLOCK_PAIRING:
6841 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6842 break;
4180bf1b
WL		 6843 case KVM_HC_SEND_IPI:
6844 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
6845 break;
8ef81a9a 6846#endif
8776e519
HB		 6847 default:
6848 ret = -KVM_ENOSYS;
6849 break;
6850 }
696ca779 6851out:
a449c7aa
NA		 6852 if (!op_64_bit)
6853 ret = (u32)ret;
5fdbf976 6854 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
6356ee0c 6855
f11c3a8d 6856 ++vcpu->stat.hypercalls;
6356ee0c 6857 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 6858}
6859EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6860
b6785def 6861static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6862{
d6aa1000 6863 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6864 char instruction[3];
5fdbf976 6865 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6866
8776e519 6867 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6868
ce2e852e
DV		 6869 return emulator_write_emulated(ctxt, rip, instruction, 3,
6870 &ctxt->exception);
8776e519
HB		 6871}
6872
851ba692 6873static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6874{
782d422b
MG		 6875 return vcpu->run->request_interrupt_window &&
6876 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6877}
6878
851ba692 6879static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6880{
851ba692
AK		 6881 struct kvm_run *kvm_run = vcpu->run;
6882
91586a3b 6883 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6884 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6885 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6886 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6887 kvm_run->ready_for_interrupt_injection =
6888 pic_in_kernel(vcpu->kvm) ||
782d422b 6889 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6890}
6891
95ba8273
GN		 6892static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6893{
6894 int max_irr, tpr;
6895
6896 if (!kvm_x86_ops->update_cr8_intercept)
6897 return;
6898
bce87cce 6899 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6900 return;
6901
d62caabb
AS		 6902 if (vcpu->arch.apicv_active)
6903 return;
6904
8db3baa2
GN		 6905 if (!vcpu->arch.apic->vapic_addr)
6906 max_irr = kvm_lapic_find_highest_irr(vcpu);
6907 else
6908 max_irr = -1;
95ba8273
GN		 6909
6910 if (max_irr != -1)
6911 max_irr >>= 4;
6912
6913 tpr = kvm_lapic_get_cr8(vcpu);
6914
6915 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6916}
6917
b6b8a145 6918static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6919{
b6b8a145
JK		 6920 int r;
6921
95ba8273 6922 /* try to reinject previous events if any */
664f8e26 6923
1a680e35
LA		 6924 if (vcpu->arch.exception.injected)
6925 kvm_x86_ops->queue_exception(vcpu);
664f8e26 6926 /*
a042c26f
LA		 6927 * Do not inject an NMI or interrupt if there is a pending
6928 * exception. Exceptions and interrupts are recognized at
6929 * instruction boundaries, i.e. the start of an instruction.
6930 * Trap-like exceptions, e.g. #DB, have higher priority than
6931 * NMIs and interrupts, i.e. traps are recognized before an
6932 * NMI/interrupt that's pending on the same instruction.
6933 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
6934 * priority, but are only generated (pended) during instruction
6935 * execution, i.e. a pending fault-like exception means the
6936 * fault occurred on the *previous* instruction and must be
6937 * serviced prior to recognizing any new events in order to
6938 * fully complete the previous instruction.
664f8e26 6939 */
1a680e35
LA		 6940 else if (!vcpu->arch.exception.pending) {
6941 if (vcpu->arch.nmi_injected)
664f8e26 6942 kvm_x86_ops->set_nmi(vcpu);
1a680e35 6943 else if (vcpu->arch.interrupt.injected)
664f8e26 6944 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 6945 }
6946
1a680e35
LA		 6947 /*
6948 * Call check_nested_events() even if we reinjected a previous event
6949 * in order for caller to determine if it should require immediate-exit
6950 * from L2 to L1 due to pending L1 events which require exit
6951 * from L2 to L1.
6952 */
664f8e26
WL		 6953 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6954 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6955 if (r != 0)
6956 return r;
6957 }
6958
6959 /* try to inject new event if pending */
b59bb7bd 6960 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6961 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6962 vcpu->arch.exception.has_error_code,
6963 vcpu->arch.exception.error_code);
d6e8c854 6964
1a680e35 6965 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 6966 vcpu->arch.exception.pending = false;
6967 vcpu->arch.exception.injected = true;
6968
d6e8c854
NA		 6969 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6970 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6971 X86_EFLAGS_RF);
6972
6bdf0662
NA		 6973 if (vcpu->arch.exception.nr == DB_VECTOR &&
6974 (vcpu->arch.dr7 & DR7_GD)) {
6975 vcpu->arch.dr7 &= ~DR7_GD;
6976 kvm_update_dr7(vcpu);
6977 }
6978
cfcd20e5 6979 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 6980 }
6981
6982 /* Don't consider new event if we re-injected an event */
6983 if (kvm_event_needs_reinjection(vcpu))
6984 return 0;
6985
6986 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
6987 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6988 vcpu->arch.smi_pending = false;
52797bf9 6989 ++vcpu->arch.smi_count;
ee2cd4b7 6990 enter_smm(vcpu);
c43203ca 6991 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6992 --vcpu->arch.nmi_pending;
6993 vcpu->arch.nmi_injected = true;
6994 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6995 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6996 /*
6997 * Because interrupts can be injected asynchronously, we are
6998 * calling check_nested_events again here to avoid a race condition.
6999 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7000 * proposal and current concerns. Perhaps we should be setting
7001 * KVM_REQ_EVENT only on certain events and not unconditionally?
7002 */
7003 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7004 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7005 if (r != 0)
7006 return r;
7007 }
95ba8273 7008 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7009 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7010 false);
7011 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7012 }
7013 }
ee2cd4b7 7014
b6b8a145 7015 return 0;
95ba8273
GN		 7016}
7017
7460fb4a
AK		 7018static void process_nmi(struct kvm_vcpu *vcpu)
7019{
7020 unsigned limit = 2;
7021
7022 /*
7023 * x86 is limited to one NMI running, and one NMI pending after it.
7024 * If an NMI is already in progress, limit further NMIs to just one.
7025 * Otherwise, allow two (and we'll inject the first one immediately).
7026 */
7027 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7028 limit = 1;
7029
7030 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7031 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7032 kvm_make_request(KVM_REQ_EVENT, vcpu);
7033}
7034
ee2cd4b7 7035static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7036{
7037 u32 flags = 0;
7038 flags |= seg->g << 23;
7039 flags |= seg->db << 22;
7040 flags |= seg->l << 21;
7041 flags |= seg->avl << 20;
7042 flags |= seg->present << 15;
7043 flags |= seg->dpl << 13;
7044 flags |= seg->s << 12;
7045 flags |= seg->type << 8;
7046 return flags;
7047}
7048
ee2cd4b7 7049static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7050{
7051 struct kvm_segment seg;
7052 int offset;
7053
7054 kvm_get_segment(vcpu, &seg, n);
7055 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7056
7057 if (n < 3)
7058 offset = 0x7f84 + n * 12;
7059 else
7060 offset = 0x7f2c + (n - 3) * 12;
7061
7062 put_smstate(u32, buf, offset + 8, seg.base);
7063 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7064 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7065}
7066
efbb288a 7067#ifdef CONFIG_X86_64
ee2cd4b7 7068static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7069{
7070 struct kvm_segment seg;
7071 int offset;
7072 u16 flags;
7073
7074 kvm_get_segment(vcpu, &seg, n);
7075 offset = 0x7e00 + n * 16;
7076
ee2cd4b7 7077 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7078 put_smstate(u16, buf, offset, seg.selector);
7079 put_smstate(u16, buf, offset + 2, flags);
7080 put_smstate(u32, buf, offset + 4, seg.limit);
7081 put_smstate(u64, buf, offset + 8, seg.base);
7082}
efbb288a 7083#endif
660a5d51 7084
ee2cd4b7 7085static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7086{
7087 struct desc_ptr dt;
7088 struct kvm_segment seg;
7089 unsigned long val;
7090 int i;
7091
7092 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7093 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7094 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7095 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7096
7097 for (i = 0; i < 8; i++)
7098 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7099
7100 kvm_get_dr(vcpu, 6, &val);
7101 put_smstate(u32, buf, 0x7fcc, (u32)val);
7102 kvm_get_dr(vcpu, 7, &val);
7103 put_smstate(u32, buf, 0x7fc8, (u32)val);
7104
7105 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7106 put_smstate(u32, buf, 0x7fc4, seg.selector);
7107 put_smstate(u32, buf, 0x7f64, seg.base);
7108 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7109 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7110
7111 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7112 put_smstate(u32, buf, 0x7fc0, seg.selector);
7113 put_smstate(u32, buf, 0x7f80, seg.base);
7114 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7115 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7116
7117 kvm_x86_ops->get_gdt(vcpu, &dt);
7118 put_smstate(u32, buf, 0x7f74, dt.address);
7119 put_smstate(u32, buf, 0x7f70, dt.size);
7120
7121 kvm_x86_ops->get_idt(vcpu, &dt);
7122 put_smstate(u32, buf, 0x7f58, dt.address);
7123 put_smstate(u32, buf, 0x7f54, dt.size);
7124
7125 for (i = 0; i < 6; i++)
ee2cd4b7 7126 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7127
7128 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7129
7130 /* revision id */
7131 put_smstate(u32, buf, 0x7efc, 0x00020000);
7132 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7133}
7134
ee2cd4b7 7135static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7136{
7137#ifdef CONFIG_X86_64
7138 struct desc_ptr dt;
7139 struct kvm_segment seg;
7140 unsigned long val;
7141 int i;
7142
7143 for (i = 0; i < 16; i++)
7144 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7145
7146 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7147 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7148
7149 kvm_get_dr(vcpu, 6, &val);
7150 put_smstate(u64, buf, 0x7f68, val);
7151 kvm_get_dr(vcpu, 7, &val);
7152 put_smstate(u64, buf, 0x7f60, val);
7153
7154 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7155 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7156 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7157
7158 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7159
7160 /* revision id */
7161 put_smstate(u32, buf, 0x7efc, 0x00020064);
7162
7163 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7164
7165 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7166 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7167 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7168 put_smstate(u32, buf, 0x7e94, seg.limit);
7169 put_smstate(u64, buf, 0x7e98, seg.base);
7170
7171 kvm_x86_ops->get_idt(vcpu, &dt);
7172 put_smstate(u32, buf, 0x7e84, dt.size);
7173 put_smstate(u64, buf, 0x7e88, dt.address);
7174
7175 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7176 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7177 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7178 put_smstate(u32, buf, 0x7e74, seg.limit);
7179 put_smstate(u64, buf, 0x7e78, seg.base);
7180
7181 kvm_x86_ops->get_gdt(vcpu, &dt);
7182 put_smstate(u32, buf, 0x7e64, dt.size);
7183 put_smstate(u64, buf, 0x7e68, dt.address);
7184
7185 for (i = 0; i < 6; i++)
ee2cd4b7 7186 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 7187#else
7188 WARN_ON_ONCE(1);
7189#endif
7190}
7191
ee2cd4b7 7192static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7193{
660a5d51 7194 struct kvm_segment cs, ds;
18c3626e 7195 struct desc_ptr dt;
660a5d51
PB		 7196 char buf[512];
7197 u32 cr0;
7198
660a5d51 7199 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7200 memset(buf, 0, 512);
d6321d49 7201 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7202 enter_smm_save_state_64(vcpu, buf);
660a5d51 7203 else
ee2cd4b7 7204 enter_smm_save_state_32(vcpu, buf);
660a5d51 7205
0234bf88
LP		 7206 /*
7207 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7208 * vCPU state (e.g. leave guest mode) after we've saved the state into
7209 * the SMM state-save area.
7210 */
7211 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7212
7213 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7214 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7215
7216 if (kvm_x86_ops->get_nmi_mask(vcpu))
7217 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7218 else
7219 kvm_x86_ops->set_nmi_mask(vcpu, true);
7220
7221 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7222 kvm_rip_write(vcpu, 0x8000);
7223
7224 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7225 kvm_x86_ops->set_cr0(vcpu, cr0);
7226 vcpu->arch.cr0 = cr0;
7227
7228 kvm_x86_ops->set_cr4(vcpu, 0);
7229
18c3626e
PB		 7230 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7231 dt.address = dt.size = 0;
7232 kvm_x86_ops->set_idt(vcpu, &dt);
7233
660a5d51
PB		 7234 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7235
7236 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7237 cs.base = vcpu->arch.smbase;
7238
7239 ds.selector = 0;
7240 ds.base = 0;
7241
7242 cs.limit = ds.limit = 0xffffffff;
7243 cs.type = ds.type = 0x3;
7244 cs.dpl = ds.dpl = 0;
7245 cs.db = ds.db = 0;
7246 cs.s = ds.s = 1;
7247 cs.l = ds.l = 0;
7248 cs.g = ds.g = 1;
7249 cs.avl = ds.avl = 0;
7250 cs.present = ds.present = 1;
7251 cs.unusable = ds.unusable = 0;
7252 cs.padding = ds.padding = 0;
7253
7254 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7255 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7256 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7257 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7258 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7259 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7260
d6321d49 7261 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 7262 kvm_x86_ops->set_efer(vcpu, 0);
7263
7264 kvm_update_cpuid(vcpu);
7265 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7266}
7267
ee2cd4b7 7268static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7269{
7270 vcpu->arch.smi_pending = true;
7271 kvm_make_request(KVM_REQ_EVENT, vcpu);
7272}
7273
2860c4b1
PB		 7274void kvm_make_scan_ioapic_request(struct kvm *kvm)
7275{
7276 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
7277}
7278
3d81bc7e 7279static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7280{
3d81bc7e
YZ		 7281 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7282 return;
c7c9c56c 7283
6308630b 7284 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7285
b053b2ae 7286 if (irqchip_split(vcpu->kvm))
6308630b 7287 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7288 else {
fa59cc00 7289 if (vcpu->arch.apicv_active)
d62caabb 7290 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7291 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7292 }
e40ff1d6
LA		 7293
7294 if (is_guest_mode(vcpu))
7295 vcpu->arch.load_eoi_exitmap_pending = true;
7296 else
7297 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
7298}
7299
7300static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
7301{
7302 u64 eoi_exit_bitmap[4];
7303
7304 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7305 return;
7306
5c919412
AS		 7307 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7308 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7309 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7310}
7311
93065ac7
MH		 7312int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7313 unsigned long start, unsigned long end,
7314 bool blockable)
b1394e74
RK		 7315{
7316 unsigned long apic_address;
7317
7318 /*
7319 * The physical address of apic access page is stored in the VMCS.
7320 * Update it when it becomes invalid.
7321 */
7322 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7323 if (start <= apic_address && apic_address < end)
7324 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 7325
7326 return 0;
b1394e74
RK		 7327}
7328
4256f43f
TC		 7329void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7330{
c24ae0dc
TC		 7331 struct page *page = NULL;
7332
35754c98 7333 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7334 return;
7335
4256f43f
TC		 7336 if (!kvm_x86_ops->set_apic_access_page_addr)
7337 return;
7338
c24ae0dc 7339 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7340 if (is_error_page(page))
7341 return;
c24ae0dc
TC		 7342 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7343
7344 /*
7345 * Do not pin apic access page in memory, the MMU notifier
7346 * will call us again if it is migrated or swapped out.
7347 */
7348 put_page(page);
4256f43f
TC		 7349}
7350EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7351
9357d939 7352/*
362c698f 7353 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7354 * exiting to the userspace. Otherwise, the value will be returned to the
7355 * userspace.
7356 */
851ba692 7357static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7358{
7359 int r;
62a193ed
MG		 7360 bool req_int_win =
7361 dm_request_for_irq_injection(vcpu) &&
7362 kvm_cpu_accept_dm_intr(vcpu);
7363
730dca42 7364 bool req_immediate_exit = false;
b6c7a5dc 7365
2fa6e1e1 7366 if (kvm_request_pending(vcpu)) {
7f7f1ba3
PB		 7367 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu))
7368 kvm_x86_ops->get_vmcs12_pages(vcpu);
a8eeb04a 7369 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7370 kvm_mmu_unload(vcpu);
a8eeb04a 7371 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7372 __kvm_migrate_timers(vcpu);
d828199e
MT		 7373 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7374 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7375 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7376 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7377 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7378 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7379 if (unlikely(r))
7380 goto out;
7381 }
a8eeb04a 7382 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7383 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 7384 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
7385 kvm_mmu_load_cr3(vcpu);
a8eeb04a 7386 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7387 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7388 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7389 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7390 r = 0;
7391 goto out;
7392 }
a8eeb04a 7393 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7394 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7395 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7396 r = 0;
7397 goto out;
7398 }
af585b92
GN		 7399 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7400 /* Page is swapped out. Do synthetic halt */
7401 vcpu->arch.apf.halted = true;
7402 r = 1;
7403 goto out;
7404 }
c9aaa895
GC		 7405 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7406 record_steal_time(vcpu);
64d60670
PB		 7407 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7408 process_smi(vcpu);
7460fb4a
AK		 7409 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7410 process_nmi(vcpu);
f5132b01 7411 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7412 kvm_pmu_handle_event(vcpu);
f5132b01 7413 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7414 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7415 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7416 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7417 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7418 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7419 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7420 vcpu->run->eoi.vector =
7421 vcpu->arch.pending_ioapic_eoi;
7422 r = 0;
7423 goto out;
7424 }
7425 }
3d81bc7e
YZ		 7426 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7427 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 7428 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
7429 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 7430 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7431 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7432 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7433 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7434 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7435 r = 0;
7436 goto out;
7437 }
e516cebb
AS		 7438 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7439 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7440 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7441 r = 0;
7442 goto out;
7443 }
db397571
AS		 7444 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7445 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7446 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7447 r = 0;
7448 goto out;
7449 }
f3b138c5
AS		 7450
7451 /*
7452 * KVM_REQ_HV_STIMER has to be processed after
7453 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7454 * depend on the guest clock being up-to-date
7455 */
1f4b34f8
AS		 7456 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7457 kvm_hv_process_stimers(vcpu);
2f52d58c 7458 }
b93463aa 7459
b463a6f7 7460 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7461 ++vcpu->stat.req_event;
66450a21
JK		 7462 kvm_apic_accept_events(vcpu);
7463 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7464 r = 1;
7465 goto out;
7466 }
7467
b6b8a145
JK		 7468 if (inject_pending_event(vcpu, req_int_win) != 0)
7469 req_immediate_exit = true;
321c5658 7470 else {
cc3d967f 7471 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7472 *
cc3d967f
LP		 7473 * SMIs have three cases:
7474 * 1) They can be nested, and then there is nothing to
7475 * do here because RSM will cause a vmexit anyway.
7476 * 2) There is an ISA-specific reason why SMI cannot be
7477 * injected, and the moment when this changes can be
7478 * intercepted.
7479 * 3) Or the SMI can be pending because
7480 * inject_pending_event has completed the injection
7481 * of an IRQ or NMI from the previous vmexit, and
7482 * then we request an immediate exit to inject the
7483 * SMI.
c43203ca
PB		 7484 */
7485 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7486 if (!kvm_x86_ops->enable_smi_window(vcpu))
7487 req_immediate_exit = true;
321c5658
YS		 7488 if (vcpu->arch.nmi_pending)
7489 kvm_x86_ops->enable_nmi_window(vcpu);
7490 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7491 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7492 WARN_ON(vcpu->arch.exception.pending);
321c5658 7493 }
b463a6f7
AK		 7494
7495 if (kvm_lapic_enabled(vcpu)) {
7496 update_cr8_intercept(vcpu);
7497 kvm_lapic_sync_to_vapic(vcpu);
7498 }
7499 }
7500
d8368af8
AK		 7501 r = kvm_mmu_reload(vcpu);
7502 if (unlikely(r)) {
d905c069 7503 goto cancel_injection;
d8368af8
AK		 7504 }
7505
b6c7a5dc
HB		 7506 preempt_disable();
7507
7508 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7509
7510 /*
7511 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7512 * IPI are then delayed after guest entry, which ensures that they
7513 * result in virtual interrupt delivery.
7514 */
7515 local_irq_disable();
6b7e2d09
XG		 7516 vcpu->mode = IN_GUEST_MODE;
7517
01b71917
MT		 7518 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7519
0f127d12 7520 /*
b95234c8 7521 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7522 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7523 *
7524 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7525 * pairs with the memory barrier implicit in pi_test_and_set_on
7526 * (see vmx_deliver_posted_interrupt).
7527 *
7528 * 3) This also orders the write to mode from any reads to the page
7529 * tables done while the VCPU is running. Please see the comment
7530 * in kvm_flush_remote_tlbs.
6b7e2d09 7531 */
01b71917 7532 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7533
b95234c8
PB		 7534 /*
7535 * This handles the case where a posted interrupt was
7536 * notified with kvm_vcpu_kick.
7537 */
fa59cc00
LA		 7538 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7539 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7540
2fa6e1e1 7541 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7542 || need_resched() || signal_pending(current)) {
6b7e2d09 7543 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7544 smp_wmb();
6c142801
AK		 7545 local_irq_enable();
7546 preempt_enable();
01b71917 7547 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7548 r = 1;
d905c069 7549 goto cancel_injection;
6c142801
AK		 7550 }
7551
fc5b7f3b
DM		 7552 kvm_load_guest_xcr0(vcpu);
7553
c43203ca
PB		 7554 if (req_immediate_exit) {
7555 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7556 smp_send_reschedule(vcpu->cpu);
c43203ca 7557 }
d6185f20 7558
8b89fe1f 7559 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7560 if (lapic_timer_advance_ns)
7561 wait_lapic_expire(vcpu);
6edaa530 7562 guest_enter_irqoff();
b6c7a5dc 7563
42dbaa5a 7564 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7565 set_debugreg(0, 7);
7566 set_debugreg(vcpu->arch.eff_db[0], 0);
7567 set_debugreg(vcpu->arch.eff_db[1], 1);
7568 set_debugreg(vcpu->arch.eff_db[2], 2);
7569 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7570 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7571 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7572 }
b6c7a5dc 7573
851ba692 7574 kvm_x86_ops->run(vcpu);
b6c7a5dc 7575
c77fb5fe
PB		 7576 /*
7577 * Do this here before restoring debug registers on the host. And
7578 * since we do this before handling the vmexit, a DR access vmexit
7579 * can (a) read the correct value of the debug registers, (b) set
7580 * KVM_DEBUGREG_WONT_EXIT again.
7581 */
7582 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7583 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7584 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7585 kvm_update_dr0123(vcpu);
7586 kvm_update_dr6(vcpu);
7587 kvm_update_dr7(vcpu);
7588 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7589 }
7590
24f1e32c
FW		 7591 /*
7592 * If the guest has used debug registers, at least dr7
7593 * will be disabled while returning to the host.
7594 * If we don't have active breakpoints in the host, we don't
7595 * care about the messed up debug address registers. But if
7596 * we have some of them active, restore the old state.
7597 */
59d8eb53 7598 if (hw_breakpoint_active())
24f1e32c 7599 hw_breakpoint_restore();
42dbaa5a 7600
4ba76538 7601 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7602
6b7e2d09 7603 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7604 smp_wmb();
a547c6db 7605
fc5b7f3b
DM		 7606 kvm_put_guest_xcr0(vcpu);
7607
dd60d217 7608 kvm_before_interrupt(vcpu);
a547c6db 7609 kvm_x86_ops->handle_external_intr(vcpu);
dd60d217 7610 kvm_after_interrupt(vcpu);
b6c7a5dc
HB		 7611
7612 ++vcpu->stat.exits;
7613
f2485b3e 7614 guest_exit_irqoff();
b6c7a5dc 7615
f2485b3e 7616 local_irq_enable();
b6c7a5dc
HB		 7617 preempt_enable();
7618
f656ce01 7619 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7620
b6c7a5dc
HB		 7621 /*
7622 * Profile KVM exit RIPs:
7623 */
7624 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7625 unsigned long rip = kvm_rip_read(vcpu);
7626 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7627 }
7628
cc578287
ZA		 7629 if (unlikely(vcpu->arch.tsc_always_catchup))
7630 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7631
5cfb1d5a
MT		 7632 if (vcpu->arch.apic_attention)
7633 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7634
618232e2 7635 vcpu->arch.gpa_available = false;
851ba692 7636 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7637 return r;
7638
7639cancel_injection:
7640 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7641 if (unlikely(vcpu->arch.apic_attention))
7642 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7643out:
7644 return r;
7645}
b6c7a5dc 7646
362c698f
PB		 7647static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7648{
bf9f6ac8
FW		 7649 if (!kvm_arch_vcpu_runnable(vcpu) &&
7650 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7651 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7652 kvm_vcpu_block(vcpu);
7653 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7654
7655 if (kvm_x86_ops->post_block)
7656 kvm_x86_ops->post_block(vcpu);
7657
9c8fd1ba
PB		 7658 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7659 return 1;
7660 }
362c698f
PB		 7661
7662 kvm_apic_accept_events(vcpu);
7663 switch(vcpu->arch.mp_state) {
7664 case KVM_MP_STATE_HALTED:
7665 vcpu->arch.pv.pv_unhalted = false;
7666 vcpu->arch.mp_state =
7667 KVM_MP_STATE_RUNNABLE;
7668 case KVM_MP_STATE_RUNNABLE:
7669 vcpu->arch.apf.halted = false;
7670 break;
7671 case KVM_MP_STATE_INIT_RECEIVED:
7672 break;
7673 default:
7674 return -EINTR;
7675 break;
7676 }
7677 return 1;
7678}
09cec754 7679
5d9bc648
PB		 7680static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7681{
0ad3bed6
PB		 7682 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7683 kvm_x86_ops->check_nested_events(vcpu, false);
7684
5d9bc648
PB		 7685 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7686 !vcpu->arch.apf.halted);
7687}
7688
362c698f 7689static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7690{
7691 int r;
f656ce01 7692 struct kvm *kvm = vcpu->kvm;
d7690175 7693
f656ce01 7694 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 7695 vcpu->arch.l1tf_flush_l1d = true;
d7690175 7696
362c698f 7697 for (;;) {
58f800d5 7698 if (kvm_vcpu_running(vcpu)) {
851ba692 7699 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7700 } else {
362c698f 7701 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7702 }
7703
09cec754
GN		 7704 if (r <= 0)
7705 break;
7706
72875d8a 7707 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7708 if (kvm_cpu_has_pending_timer(vcpu))
7709 kvm_inject_pending_timer_irqs(vcpu);
7710
782d422b
MG		 7711 if (dm_request_for_irq_injection(vcpu) &&
7712 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7713 r = 0;
7714 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7715 ++vcpu->stat.request_irq_exits;
362c698f 7716 break;
09cec754 7717 }
af585b92
GN		 7718
7719 kvm_check_async_pf_completion(vcpu);
7720
09cec754
GN		 7721 if (signal_pending(current)) {
7722 r = -EINTR;
851ba692 7723 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7724 ++vcpu->stat.signal_exits;
362c698f 7725 break;
09cec754
GN		 7726 }
7727 if (need_resched()) {
f656ce01 7728 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7729 cond_resched();
f656ce01 7730 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7731 }
b6c7a5dc
HB		 7732 }
7733
f656ce01 7734 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7735
7736 return r;
7737}
7738
716d51ab
GN		 7739static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7740{
7741 int r;
7742 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7743 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7744 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7745 if (r != EMULATE_DONE)
7746 return 0;
7747 return 1;
7748}
7749
7750static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7751{
7752 BUG_ON(!vcpu->arch.pio.count);
7753
7754 return complete_emulated_io(vcpu);
7755}
7756
f78146b0
AK		 7757/*
7758 * Implements the following, as a state machine:
7759 *
7760 * read:
7761 * for each fragment
87da7e66
XG		 7762 * for each mmio piece in the fragment
7763 * write gpa, len
7764 * exit
7765 * copy data
f78146b0
AK		 7766 * execute insn
7767 *
7768 * write:
7769 * for each fragment
87da7e66
XG		 7770 * for each mmio piece in the fragment
7771 * write gpa, len
7772 * copy data
7773 * exit
f78146b0 7774 */
716d51ab 7775static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7776{
7777 struct kvm_run *run = vcpu->run;
f78146b0 7778 struct kvm_mmio_fragment *frag;
87da7e66 7779 unsigned len;
5287f194 7780
716d51ab 7781 BUG_ON(!vcpu->mmio_needed);
5287f194 7782
716d51ab 7783 /* Complete previous fragment */
87da7e66
XG		 7784 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7785 len = min(8u, frag->len);
716d51ab 7786 if (!vcpu->mmio_is_write)
87da7e66
XG		 7787 memcpy(frag->data, run->mmio.data, len);
7788
7789 if (frag->len <= 8) {
7790 /* Switch to the next fragment. */
7791 frag++;
7792 vcpu->mmio_cur_fragment++;
7793 } else {
7794 /* Go forward to the next mmio piece. */
7795 frag->data += len;
7796 frag->gpa += len;
7797 frag->len -= len;
7798 }
7799
a08d3b3b 7800 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7801 vcpu->mmio_needed = 0;
0912c977
PB		 7802
7803 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7804 if (vcpu->mmio_is_write)
716d51ab
GN		 7805 return 1;
7806 vcpu->mmio_read_completed = 1;
7807 return complete_emulated_io(vcpu);
7808 }
87da7e66 7809
716d51ab
GN		 7810 run->exit_reason = KVM_EXIT_MMIO;
7811 run->mmio.phys_addr = frag->gpa;
7812 if (vcpu->mmio_is_write)
87da7e66
XG		 7813 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7814 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7815 run->mmio.is_write = vcpu->mmio_is_write;
7816 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7817 return 0;
5287f194
AK		 7818}
7819
b6c7a5dc
HB		 7820int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7821{
7822 int r;
b6c7a5dc 7823
accb757d 7824 vcpu_load(vcpu);
20b7035c 7825 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7826 kvm_load_guest_fpu(vcpu);
7827
a4535290 7828 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7829 if (kvm_run->immediate_exit) {
7830 r = -EINTR;
7831 goto out;
7832 }
b6c7a5dc 7833 kvm_vcpu_block(vcpu);
66450a21 7834 kvm_apic_accept_events(vcpu);
72875d8a 7835 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7836 r = -EAGAIN;
a0595000
JS		 7837 if (signal_pending(current)) {
7838 r = -EINTR;
7839 vcpu->run->exit_reason = KVM_EXIT_INTR;
7840 ++vcpu->stat.signal_exits;
7841 }
ac9f6dc0 7842 goto out;
b6c7a5dc
HB		 7843 }
7844
01643c51
KH		 7845 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7846 r = -EINVAL;
7847 goto out;
7848 }
7849
7850 if (vcpu->run->kvm_dirty_regs) {
7851 r = sync_regs(vcpu);
7852 if (r != 0)
7853 goto out;
7854 }
7855
b6c7a5dc 7856 /* re-sync apic's tpr */
35754c98 7857 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7858 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7859 r = -EINVAL;
7860 goto out;
7861 }
7862 }
b6c7a5dc 7863
716d51ab
GN		 7864 if (unlikely(vcpu->arch.complete_userspace_io)) {
7865 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7866 vcpu->arch.complete_userspace_io = NULL;
7867 r = cui(vcpu);
7868 if (r <= 0)
5663d8f9 7869 goto out;
716d51ab
GN		 7870 } else
7871 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7872
460df4c1
PB		 7873 if (kvm_run->immediate_exit)
7874 r = -EINTR;
7875 else
7876 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7877
7878out:
5663d8f9 7879 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7880 if (vcpu->run->kvm_valid_regs)
7881 store_regs(vcpu);
f1d86e46 7882 post_kvm_run_save(vcpu);
20b7035c 7883 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7884
accb757d 7885 vcpu_put(vcpu);
b6c7a5dc
HB		 7886 return r;
7887}
7888
01643c51 7889static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7890{
7ae441ea
GN		 7891 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7892 /*
7893 * We are here if userspace calls get_regs() in the middle of
7894 * instruction emulation. Registers state needs to be copied
4a969980 7895 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7896 * that usually, but some bad designed PV devices (vmware
7897 * backdoor interface) need this to work
7898 */
dd856efa 7899 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7900 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7901 }
5fdbf976
MT		 7902 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7903 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7904 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7905 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7906 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7907 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7908 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7909 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7910#ifdef CONFIG_X86_64
5fdbf976
MT		 7911 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7912 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7913 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7914 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7915 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7916 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7917 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7918 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7919#endif
7920
5fdbf976 7921 regs->rip = kvm_rip_read(vcpu);
91586a3b 7922 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7923}
b6c7a5dc 7924
01643c51
KH		 7925int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7926{
7927 vcpu_load(vcpu);
7928 __get_regs(vcpu, regs);
1fc9b76b 7929 vcpu_put(vcpu);
b6c7a5dc
HB		 7930 return 0;
7931}
7932
01643c51 7933static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7934{
7ae441ea
GN		 7935 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7936 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7937
5fdbf976
MT		 7938 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7939 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7940 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7941 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7942 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7943 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7944 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7945 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7946#ifdef CONFIG_X86_64
5fdbf976
MT		 7947 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7948 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7949 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7950 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7951 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7952 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7953 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7954 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7955#endif
7956
5fdbf976 7957 kvm_rip_write(vcpu, regs->rip);
d73235d1 7958 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7959
b4f14abd
JK		 7960 vcpu->arch.exception.pending = false;
7961
3842d135 7962 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7963}
3842d135 7964
01643c51
KH		 7965int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7966{
7967 vcpu_load(vcpu);
7968 __set_regs(vcpu, regs);
875656fe 7969 vcpu_put(vcpu);
b6c7a5dc
HB		 7970 return 0;
7971}
7972
b6c7a5dc
HB		 7973void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7974{
7975 struct kvm_segment cs;
7976
3e6e0aab 7977 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7978 *db = cs.db;
7979 *l = cs.l;
7980}
7981EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7982
01643c51 7983static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7984{
89a27f4d 7985 struct desc_ptr dt;
b6c7a5dc 7986
3e6e0aab
GT		 7987 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7988 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7989 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7990 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7991 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7992 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7993
3e6e0aab
GT		 7994 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7995 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7996
7997 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7998 sregs->idt.limit = dt.size;
7999 sregs->idt.base = dt.address;
b6c7a5dc 8000 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8001 sregs->gdt.limit = dt.size;
8002 sregs->gdt.base = dt.address;
b6c7a5dc 8003
4d4ec087 8004 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8005 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8006 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8007 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8008 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8009 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8010 sregs->apic_base = kvm_get_apic_base(vcpu);
8011
923c61bb 8012 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 8013
04140b41 8014 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8015 set_bit(vcpu->arch.interrupt.nr,
8016 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8017}
16d7a191 8018
01643c51
KH		 8019int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8020 struct kvm_sregs *sregs)
8021{
8022 vcpu_load(vcpu);
8023 __get_sregs(vcpu, sregs);
bcdec41c 8024 vcpu_put(vcpu);
b6c7a5dc
HB		 8025 return 0;
8026}
8027
62d9f0db
MT		 8028int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8029 struct kvm_mp_state *mp_state)
8030{
fd232561
CD		 8031 vcpu_load(vcpu);
8032
66450a21 8033 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8034 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8035 vcpu->arch.pv.pv_unhalted)
8036 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8037 else
8038 mp_state->mp_state = vcpu->arch.mp_state;
8039
fd232561 8040 vcpu_put(vcpu);
62d9f0db
MT		 8041 return 0;
8042}
8043
8044int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8045 struct kvm_mp_state *mp_state)
8046{
e83dff5e
CD		 8047 int ret = -EINVAL;
8048
8049 vcpu_load(vcpu);
8050
bce87cce 8051 if (!lapic_in_kernel(vcpu) &&
66450a21 8052 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8053 goto out;
66450a21 8054
28bf2888
DH		 8055 /* INITs are latched while in SMM */
8056 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
8057 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8058 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8059 goto out;
28bf2888 8060
66450a21
JK		 8061 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8062 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8063 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8064 } else
8065 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8066 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8067
8068 ret = 0;
8069out:
8070 vcpu_put(vcpu);
8071 return ret;
62d9f0db
MT		 8072}
8073
7f3d35fd
KW		 8074int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8075 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8076{
9d74191a 8077 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8078 int ret;
e01c2426 8079
8ec4722d 8080 init_emulate_ctxt(vcpu);
c697518a 8081
7f3d35fd 8082 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8083 has_error_code, error_code);
c697518a 8084
c697518a 8085 if (ret)
19d04437 8086 return EMULATE_FAIL;
37817f29 8087
9d74191a
TY		 8088 kvm_rip_write(vcpu, ctxt->eip);
8089 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8090 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 8091 return EMULATE_DONE;
37817f29
IE		 8092}
8093EXPORT_SYMBOL_GPL(kvm_task_switch);
8094
3140c156 8095static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8096{
74fec5b9
TL		 8097 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
8098 (sregs->cr4 & X86_CR4_OSXSAVE))
8099 return -EINVAL;
8100
37b95951 8101 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8102 /*
8103 * When EFER.LME and CR0.PG are set, the processor is in
8104 * 64-bit mode (though maybe in a 32-bit code segment).
8105 * CR4.PAE and EFER.LMA must be set.
8106 */
37b95951 8107 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8108 || !(sregs->efer & EFER_LMA))
8109 return -EINVAL;
8110 } else {
8111 /*
8112 * Not in 64-bit mode: EFER.LMA is clear and the code
8113 * segment cannot be 64-bit.
8114 */
8115 if (sregs->efer & EFER_LMA || sregs->cs.l)
8116 return -EINVAL;
8117 }
8118
8119 return 0;
8120}
8121
01643c51 8122static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8123{
58cb628d 8124 struct msr_data apic_base_msr;
b6c7a5dc 8125 int mmu_reset_needed = 0;
c4d21882 8126 int cpuid_update_needed = 0;
63f42e02 8127 int pending_vec, max_bits, idx;
89a27f4d 8128 struct desc_ptr dt;
b4ef9d4e
CD		 8129 int ret = -EINVAL;
8130
f2981033 8131 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8132 goto out;
f2981033 8133
d3802286
JM		 8134 apic_base_msr.data = sregs->apic_base;
8135 apic_base_msr.host_initiated = true;
8136 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8137 goto out;
6d1068b3 8138
89a27f4d
GN		 8139 dt.size = sregs->idt.limit;
8140 dt.address = sregs->idt.base;
b6c7a5dc 8141 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8142 dt.size = sregs->gdt.limit;
8143 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8144 kvm_x86_ops->set_gdt(vcpu, &dt);
8145
ad312c7c 8146 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8147 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8148 vcpu->arch.cr3 = sregs->cr3;
aff48baa 8149 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 8150
2d3ad1f4 8151 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8152
f6801dff 8153 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8154 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8155
4d4ec087 8156 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8157 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8158 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8159
fc78f519 8160 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8161 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8162 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8163 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8164 if (cpuid_update_needed)
00b27a3e 8165 kvm_update_cpuid(vcpu);
63f42e02
XG		 8166
8167 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 8168 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 8169 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8170 mmu_reset_needed = 1;
8171 }
63f42e02 8172 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8173
8174 if (mmu_reset_needed)
8175 kvm_mmu_reset_context(vcpu);
8176
a50abc3b 8177 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8178 pending_vec = find_first_bit(
8179 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8180 if (pending_vec < max_bits) {
66fd3f7f 8181 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8182 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8183 }
8184
3e6e0aab
GT		 8185 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8186 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8187 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8188 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8189 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8190 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8191
3e6e0aab
GT		 8192 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8193 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 8194
5f0269f5
ME		 8195 update_cr8_intercept(vcpu);
8196
9c3e4aab 8197 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 8198 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 8199 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 8200 !is_protmode(vcpu))
9c3e4aab
MT		 8201 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
8202
3842d135
AK		 8203 kvm_make_request(KVM_REQ_EVENT, vcpu);
8204
b4ef9d4e
CD		 8205 ret = 0;
8206out:
01643c51
KH		 8207 return ret;
8208}
8209
8210int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
8211 struct kvm_sregs *sregs)
8212{
8213 int ret;
8214
8215 vcpu_load(vcpu);
8216 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 8217 vcpu_put(vcpu);
8218 return ret;
b6c7a5dc
HB		 8219}
8220
d0bfb940
JK		 8221int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
8222 struct kvm_guest_debug *dbg)
b6c7a5dc 8223{
355be0b9 8224 unsigned long rflags;
ae675ef0 8225 int i, r;
b6c7a5dc 8226
66b56562
CD		 8227 vcpu_load(vcpu);
8228
4f926bf2
JK		 8229 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
8230 r = -EBUSY;
8231 if (vcpu->arch.exception.pending)
2122ff5e 8232 goto out;
4f926bf2
JK		 8233 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
8234 kvm_queue_exception(vcpu, DB_VECTOR);
8235 else
8236 kvm_queue_exception(vcpu, BP_VECTOR);
8237 }
8238
91586a3b
JK		 8239 /*
8240 * Read rflags as long as potentially injected trace flags are still
8241 * filtered out.
8242 */
8243 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 8244
8245 vcpu->guest_debug = dbg->control;
8246 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
8247 vcpu->guest_debug = 0;
8248
8249 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 8250 for (i = 0; i < KVM_NR_DB_REGS; ++i)
8251 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 8252 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 8253 } else {
8254 for (i = 0; i < KVM_NR_DB_REGS; i++)
8255 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 8256 }
c8639010 8257 kvm_update_dr7(vcpu);
ae675ef0 8258
f92653ee
JK		 8259 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8260 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
8261 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 8262
91586a3b
JK		 8263 /*
8264 * Trigger an rflags update that will inject or remove the trace
8265 * flags.
8266 */
8267 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 8268
a96036b8 8269 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 8270
4f926bf2 8271 r = 0;
d0bfb940 8272
2122ff5e 8273out:
66b56562 8274 vcpu_put(vcpu);
b6c7a5dc
HB		 8275 return r;
8276}
8277
8b006791
ZX		 8278/*
8279 * Translate a guest virtual address to a guest physical address.
8280 */
8281int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
8282 struct kvm_translation *tr)
8283{
8284 unsigned long vaddr = tr->linear_address;
8285 gpa_t gpa;
f656ce01 8286 int idx;
8b006791 8287
1da5b61d
CD		 8288 vcpu_load(vcpu);
8289
f656ce01 8290 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 8291 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 8292 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 8293 tr->physical_address = gpa;
8294 tr->valid = gpa != UNMAPPED_GVA;
8295 tr->writeable = 1;
8296 tr->usermode = 0;
8b006791 8297
1da5b61d 8298 vcpu_put(vcpu);
8b006791
ZX		 8299 return 0;
8300}
8301
d0752060
HB		 8302int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8303{
1393123e 8304 struct fxregs_state *fxsave;
d0752060 8305
1393123e 8306 vcpu_load(vcpu);
d0752060 8307
1393123e 8308 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8309 memcpy(fpu->fpr, fxsave->st_space, 128);
8310 fpu->fcw = fxsave->cwd;
8311 fpu->fsw = fxsave->swd;
8312 fpu->ftwx = fxsave->twd;
8313 fpu->last_opcode = fxsave->fop;
8314 fpu->last_ip = fxsave->rip;
8315 fpu->last_dp = fxsave->rdp;
8316 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8317
1393123e 8318 vcpu_put(vcpu);
d0752060
HB		 8319 return 0;
8320}
8321
8322int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8323{
6a96bc7f
CD		 8324 struct fxregs_state *fxsave;
8325
8326 vcpu_load(vcpu);
8327
8328 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8329
d0752060
HB		 8330 memcpy(fxsave->st_space, fpu->fpr, 128);
8331 fxsave->cwd = fpu->fcw;
8332 fxsave->swd = fpu->fsw;
8333 fxsave->twd = fpu->ftwx;
8334 fxsave->fop = fpu->last_opcode;
8335 fxsave->rip = fpu->last_ip;
8336 fxsave->rdp = fpu->last_dp;
8337 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8338
6a96bc7f 8339 vcpu_put(vcpu);
d0752060
HB		 8340 return 0;
8341}
8342
01643c51
KH		 8343static void store_regs(struct kvm_vcpu *vcpu)
8344{
8345 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8346
8347 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8348 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8349
8350 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8351 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8352
8353 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8354 kvm_vcpu_ioctl_x86_get_vcpu_events(
8355 vcpu, &vcpu->run->s.regs.events);
8356}
8357
8358static int sync_regs(struct kvm_vcpu *vcpu)
8359{
8360 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8361 return -EINVAL;
8362
8363 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8364 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8365 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8366 }
8367 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8368 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8369 return -EINVAL;
8370 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8371 }
8372 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8373 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8374 vcpu, &vcpu->run->s.regs.events))
8375 return -EINVAL;
8376 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8377 }
8378
8379 return 0;
8380}
8381
0ee6a517 8382static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8383{
bf935b0b 8384 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8385 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8386 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8387 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8388
2acf923e
DC		 8389 /*
8390 * Ensure guest xcr0 is valid for loading
8391 */
d91cab78 8392 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8393
ad312c7c 8394 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8395}
d0752060 8396
f775b13e 8397/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8398void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8399{
f775b13e
RR		 8400 preempt_disable();
8401 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8402 /* PKRU is separately restored in kvm_x86_ops->run. */
8403 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8404 ~XFEATURE_MASK_PKRU);
f775b13e 8405 preempt_enable();
0c04851c 8406 trace_kvm_fpu(1);
d0752060 8407}
d0752060 8408
f775b13e 8409/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8410void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8411{
f775b13e 8412 preempt_disable();
4f836347 8413 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8414 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8415 preempt_enable();
f096ed85 8416 ++vcpu->stat.fpu_reload;
0c04851c 8417 trace_kvm_fpu(0);
d0752060 8418}
e9b11c17
ZX		 8419
8420void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8421{
bd768e14
IY		 8422 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8423
12f9a48f 8424 kvmclock_reset(vcpu);
7f1ea208 8425
e9b11c17 8426 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8427 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8428}
8429
8430struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8431 unsigned int id)
8432{
c447e76b
LL		 8433 struct kvm_vcpu *vcpu;
8434
b0c39dc6 8435 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8436 printk_once(KERN_WARNING
8437 "kvm: SMP vm created on host with unstable TSC; "
8438 "guest TSC will not be reliable\n");
c447e76b
LL		 8439
8440 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8441
c447e76b 8442 return vcpu;
26e5215f 8443}
e9b11c17 8444
26e5215f
AK		 8445int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8446{
19efffa2 8447 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8448 vcpu_load(vcpu);
d28bc9dd 8449 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8450 kvm_mmu_setup(vcpu);
e9b11c17 8451 vcpu_put(vcpu);
ec7660cc 8452 return 0;
e9b11c17
ZX		 8453}
8454
31928aa5 8455void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8456{
8fe8ab46 8457 struct msr_data msr;
332967a3 8458 struct kvm *kvm = vcpu->kvm;
42897d86 8459
d3457c87
RK		 8460 kvm_hv_vcpu_postcreate(vcpu);
8461
ec7660cc 8462 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8463 return;
ec7660cc 8464 vcpu_load(vcpu);
8fe8ab46
WA		 8465 msr.data = 0x0;
8466 msr.index = MSR_IA32_TSC;
8467 msr.host_initiated = true;
8468 kvm_write_tsc(vcpu, &msr);
42897d86 8469 vcpu_put(vcpu);
ec7660cc 8470 mutex_unlock(&vcpu->mutex);
42897d86 8471
630994b3
MT		 8472 if (!kvmclock_periodic_sync)
8473 return;
8474
332967a3
AJ		 8475 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8476 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8477}
8478
d40ccc62 8479void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8480{
344d9588
GN		 8481 vcpu->arch.apf.msr_val = 0;
8482
ec7660cc 8483 vcpu_load(vcpu);
e9b11c17
ZX		 8484 kvm_mmu_unload(vcpu);
8485 vcpu_put(vcpu);
8486
8487 kvm_x86_ops->vcpu_free(vcpu);
8488}
8489
d28bc9dd 8490void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8491{
b7e31be3
RK		 8492 kvm_lapic_reset(vcpu, init_event);
8493
e69fab5d
PB		 8494 vcpu->arch.hflags = 0;
8495
c43203ca 8496 vcpu->arch.smi_pending = 0;
52797bf9 8497 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8498 atomic_set(&vcpu->arch.nmi_queued, 0);
8499 vcpu->arch.nmi_pending = 0;
448fa4a9 8500 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8501 kvm_clear_interrupt_queue(vcpu);
8502 kvm_clear_exception_queue(vcpu);
664f8e26 8503 vcpu->arch.exception.pending = false;
448fa4a9 8504
42dbaa5a 8505 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8506 kvm_update_dr0123(vcpu);
6f43ed01 8507 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8508 kvm_update_dr6(vcpu);
42dbaa5a 8509 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8510 kvm_update_dr7(vcpu);
42dbaa5a 8511
1119022c
NA		 8512 vcpu->arch.cr2 = 0;
8513
3842d135 8514 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8515 vcpu->arch.apf.msr_val = 0;
c9aaa895 8516 vcpu->arch.st.msr_val = 0;
3842d135 8517
12f9a48f
GC		 8518 kvmclock_reset(vcpu);
8519
af585b92
GN		 8520 kvm_clear_async_pf_completion_queue(vcpu);
8521 kvm_async_pf_hash_reset(vcpu);
8522 vcpu->arch.apf.halted = false;
3842d135 8523
a554d207
WL		 8524 if (kvm_mpx_supported()) {
8525 void *mpx_state_buffer;
8526
8527 /*
8528 * To avoid have the INIT path from kvm_apic_has_events() that be
8529 * called with loaded FPU and does not let userspace fix the state.
8530 */
f775b13e
RR		 8531 if (init_event)
8532 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8533 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8534 XFEATURE_MASK_BNDREGS);
8535 if (mpx_state_buffer)
8536 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8537 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8538 XFEATURE_MASK_BNDCSR);
8539 if (mpx_state_buffer)
8540 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8541 if (init_event)
8542 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8543 }
8544
64d60670 8545 if (!init_event) {
d28bc9dd 8546 kvm_pmu_reset(vcpu);
64d60670 8547 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8548
8549 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8550 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8551
8552 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8553 }
f5132b01 8554
66f7b72e
JS		 8555 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8556 vcpu->arch.regs_avail = ~0;
8557 vcpu->arch.regs_dirty = ~0;
8558
a554d207
WL		 8559 vcpu->arch.ia32_xss = 0;
8560
d28bc9dd 8561 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8562}
8563
2b4a273b 8564void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8565{
8566 struct kvm_segment cs;
8567
8568 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8569 cs.selector = vector << 8;
8570 cs.base = vector << 12;
8571 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8572 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8573}
8574
13a34e06 8575int kvm_arch_hardware_enable(void)
e9b11c17 8576{
ca84d1a2
ZA		 8577 struct kvm *kvm;
8578 struct kvm_vcpu *vcpu;
8579 int i;
0dd6a6ed
ZA		 8580 int ret;
8581 u64 local_tsc;
8582 u64 max_tsc = 0;
8583 bool stable, backwards_tsc = false;
18863bdd
AK		 8584
8585 kvm_shared_msr_cpu_online();
13a34e06 8586 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8587 if (ret != 0)
8588 return ret;
8589
4ea1636b 8590 local_tsc = rdtsc();
b0c39dc6 8591 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8592 list_for_each_entry(kvm, &vm_list, vm_list) {
8593 kvm_for_each_vcpu(i, vcpu, kvm) {
8594 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8595 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8596 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8597 backwards_tsc = true;
8598 if (vcpu->arch.last_host_tsc > max_tsc)
8599 max_tsc = vcpu->arch.last_host_tsc;
8600 }
8601 }
8602 }
8603
8604 /*
8605 * Sometimes, even reliable TSCs go backwards. This happens on
8606 * platforms that reset TSC during suspend or hibernate actions, but
8607 * maintain synchronization. We must compensate. Fortunately, we can
8608 * detect that condition here, which happens early in CPU bringup,
8609 * before any KVM threads can be running. Unfortunately, we can't
8610 * bring the TSCs fully up to date with real time, as we aren't yet far
8611 * enough into CPU bringup that we know how much real time has actually
108b249c 8612 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8613 * variables that haven't been updated yet.
8614 *
8615 * So we simply find the maximum observed TSC above, then record the
8616 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8617 * the adjustment will be applied. Note that we accumulate
8618 * adjustments, in case multiple suspend cycles happen before some VCPU
8619 * gets a chance to run again. In the event that no KVM threads get a
8620 * chance to run, we will miss the entire elapsed period, as we'll have
8621 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8622 * loose cycle time. This isn't too big a deal, since the loss will be
8623 * uniform across all VCPUs (not to mention the scenario is extremely
8624 * unlikely). It is possible that a second hibernate recovery happens
8625 * much faster than a first, causing the observed TSC here to be
8626 * smaller; this would require additional padding adjustment, which is
8627 * why we set last_host_tsc to the local tsc observed here.
8628 *
8629 * N.B. - this code below runs only on platforms with reliable TSC,
8630 * as that is the only way backwards_tsc is set above. Also note
8631 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8632 * have the same delta_cyc adjustment applied if backwards_tsc
8633 * is detected. Note further, this adjustment is only done once,
8634 * as we reset last_host_tsc on all VCPUs to stop this from being
8635 * called multiple times (one for each physical CPU bringup).
8636 *
4a969980 8637 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8638 * will be compensated by the logic in vcpu_load, which sets the TSC to
8639 * catchup mode. This will catchup all VCPUs to real time, but cannot
8640 * guarantee that they stay in perfect synchronization.
8641 */
8642 if (backwards_tsc) {
8643 u64 delta_cyc = max_tsc - local_tsc;
8644 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8645 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8646 kvm_for_each_vcpu(i, vcpu, kvm) {
8647 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8648 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8649 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8650 }
8651
8652 /*
8653 * We have to disable TSC offset matching.. if you were
8654 * booting a VM while issuing an S4 host suspend....
8655 * you may have some problem. Solving this issue is
8656 * left as an exercise to the reader.
8657 */
8658 kvm->arch.last_tsc_nsec = 0;
8659 kvm->arch.last_tsc_write = 0;
8660 }
8661
8662 }
8663 return 0;
e9b11c17
ZX		 8664}
8665
13a34e06 8666void kvm_arch_hardware_disable(void)
e9b11c17 8667{
13a34e06
RK		 8668 kvm_x86_ops->hardware_disable();
8669 drop_user_return_notifiers();
e9b11c17
ZX		 8670}
8671
8672int kvm_arch_hardware_setup(void)
8673{
9e9c3fe4
NA		 8674 int r;
8675
8676 r = kvm_x86_ops->hardware_setup();
8677 if (r != 0)
8678 return r;
8679
35181e86
HZ		 8680 if (kvm_has_tsc_control) {
8681 /*
8682 * Make sure the user can only configure tsc_khz values that
8683 * fit into a signed integer.
273ba457 8684 * A min value is not calculated because it will always
35181e86
HZ		 8685 * be 1 on all machines.
8686 */
8687 u64 max = min(0x7fffffffULL,
8688 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8689 kvm_max_guest_tsc_khz = max;
8690
ad721883 8691 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8692 }
ad721883 8693
9e9c3fe4
NA		 8694 kvm_init_msr_list();
8695 return 0;
e9b11c17
ZX		 8696}
8697
8698void kvm_arch_hardware_unsetup(void)
8699{
8700 kvm_x86_ops->hardware_unsetup();
8701}
8702
8703void kvm_arch_check_processor_compat(void *rtn)
8704{
8705 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8706}
8707
8708bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8709{
8710 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8711}
8712EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8713
8714bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8715{
8716 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8717}
8718
54e9818f 8719struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8720EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8721
e9b11c17
ZX		 8722int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8723{
8724 struct page *page;
e9b11c17
ZX		 8725 int r;
8726
b2a05fef 8727 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8728 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8729 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8730 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8731 else
a4535290 8732 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8733
8734 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8735 if (!page) {
8736 r = -ENOMEM;
8737 goto fail;
8738 }
ad312c7c 8739 vcpu->arch.pio_data = page_address(page);
e9b11c17 8740
cc578287 8741 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8742
e9b11c17
ZX		 8743 r = kvm_mmu_create(vcpu);
8744 if (r < 0)
8745 goto fail_free_pio_data;
8746
26de7988 8747 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8748 r = kvm_create_lapic(vcpu);
8749 if (r < 0)
8750 goto fail_mmu_destroy;
54e9818f
GN		 8751 } else
8752 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8753
890ca9ae
HY		 8754 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8755 GFP_KERNEL);
8756 if (!vcpu->arch.mce_banks) {
8757 r = -ENOMEM;
443c39bc 8758 goto fail_free_lapic;
890ca9ae
HY		 8759 }
8760 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8761
f1797359
WY		 8762 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8763 r = -ENOMEM;
f5f48ee1 8764 goto fail_free_mce_banks;
f1797359 8765 }
f5f48ee1 8766
0ee6a517 8767 fx_init(vcpu);
66f7b72e 8768
4344ee98 8769 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8770
5a4f55cd
EK		 8771 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8772
74545705
RK		 8773 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8774
af585b92 8775 kvm_async_pf_hash_reset(vcpu);
f5132b01 8776 kvm_pmu_init(vcpu);
af585b92 8777
1c1a9ce9 8778 vcpu->arch.pending_external_vector = -1;
de63ad4c 8779 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8780
5c919412
AS		 8781 kvm_hv_vcpu_init(vcpu);
8782
e9b11c17 8783 return 0;
0ee6a517 8784
f5f48ee1
SY		 8785fail_free_mce_banks:
8786 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8787fail_free_lapic:
8788 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8789fail_mmu_destroy:
8790 kvm_mmu_destroy(vcpu);
8791fail_free_pio_data:
ad312c7c 8792 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8793fail:
8794 return r;
8795}
8796
8797void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8798{
f656ce01
MT		 8799 int idx;
8800
1f4b34f8 8801 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8802 kvm_pmu_destroy(vcpu);
36cb93fd 8803 kfree(vcpu->arch.mce_banks);
e9b11c17 8804 kvm_free_lapic(vcpu);
f656ce01 8805 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8806 kvm_mmu_destroy(vcpu);
f656ce01 8807 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8808 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8809 if (!lapic_in_kernel(vcpu))
54e9818f 8810 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8811}
d19a9cd2 8812
e790d9ef
RK		 8813void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8814{
c595ceee 8815 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 8816 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8817}
8818
e08b9637 8819int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8820{
e08b9637
CO		 8821 if (type)
8822 return -EINVAL;
8823
6ef768fa 8824 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8825 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8826 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8827 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8828 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8829
5550af4d
SY		 8830 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8831 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8832 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8833 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8834 &kvm->arch.irq_sources_bitmap);
5550af4d 8835
038f8c11 8836 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8837 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8838 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8839
108b249c 8840 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8841 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8842
7e44e449 8843 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8844 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8845
cbc0236a 8846 kvm_hv_init_vm(kvm);
0eb05bf2 8847 kvm_page_track_init(kvm);
13d268ca 8848 kvm_mmu_init_vm(kvm);
0eb05bf2 8849
03543133
SS		 8850 if (kvm_x86_ops->vm_init)
8851 return kvm_x86_ops->vm_init(kvm);
8852
d89f5eff 8853 return 0;
d19a9cd2
ZX		 8854}
8855
8856static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8857{
ec7660cc 8858 vcpu_load(vcpu);
d19a9cd2
ZX		 8859 kvm_mmu_unload(vcpu);
8860 vcpu_put(vcpu);
8861}
8862
8863static void kvm_free_vcpus(struct kvm *kvm)
8864{
8865 unsigned int i;
988a2cae 8866 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8867
8868 /*
8869 * Unpin any mmu pages first.
8870 */
af585b92
GN		 8871 kvm_for_each_vcpu(i, vcpu, kvm) {
8872 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8873 kvm_unload_vcpu_mmu(vcpu);
af585b92 8874 }
988a2cae
GN		 8875 kvm_for_each_vcpu(i, vcpu, kvm)
8876 kvm_arch_vcpu_free(vcpu);
8877
8878 mutex_lock(&kvm->lock);
8879 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8880 kvm->vcpus[i] = NULL;
d19a9cd2 8881
988a2cae
GN		 8882 atomic_set(&kvm->online_vcpus, 0);
8883 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8884}
8885
ad8ba2cd
SY		 8886void kvm_arch_sync_events(struct kvm *kvm)
8887{
332967a3 8888 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8889 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8890 kvm_free_pit(kvm);
ad8ba2cd
SY		 8891}
8892
1d8007bd 8893int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8894{
8895 int i, r;
25188b99 8896 unsigned long hva;
f0d648bd
PB		 8897 struct kvm_memslots *slots = kvm_memslots(kvm);
8898 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8899
8900 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8901 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8902 return -EINVAL;
9da0e4d5 8903
f0d648bd
PB		 8904 slot = id_to_memslot(slots, id);
8905 if (size) {
b21629da 8906 if (slot->npages)
f0d648bd
PB		 8907 return -EEXIST;
8908
8909 /*
8910 * MAP_SHARED to prevent internal slot pages from being moved
8911 * by fork()/COW.
8912 */
8913 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8914 MAP_SHARED | MAP_ANONYMOUS, 0);
8915 if (IS_ERR((void *)hva))
8916 return PTR_ERR((void *)hva);
8917 } else {
8918 if (!slot->npages)
8919 return 0;
8920
8921 hva = 0;
8922 }
8923
8924 old = *slot;
9da0e4d5 8925 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8926 struct kvm_userspace_memory_region m;
9da0e4d5 8927
1d8007bd
PB		 8928 m.slot = id | (i << 16);
8929 m.flags = 0;
8930 m.guest_phys_addr = gpa;
f0d648bd 8931 m.userspace_addr = hva;
1d8007bd 8932 m.memory_size = size;
9da0e4d5
PB		 8933 r = __kvm_set_memory_region(kvm, &m);
8934 if (r < 0)
8935 return r;
8936 }
8937
103c763c
EB		 8938 if (!size)
8939 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8940
9da0e4d5
PB		 8941 return 0;
8942}
8943EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8944
1d8007bd 8945int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8946{
8947 int r;
8948
8949 mutex_lock(&kvm->slots_lock);
1d8007bd 8950 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8951 mutex_unlock(&kvm->slots_lock);
8952
8953 return r;
8954}
8955EXPORT_SYMBOL_GPL(x86_set_memory_region);
8956
d19a9cd2
ZX		 8957void kvm_arch_destroy_vm(struct kvm *kvm)
8958{
27469d29
AH		 8959 if (current->mm == kvm->mm) {
8960 /*
8961 * Free memory regions allocated on behalf of userspace,
8962 * unless the the memory map has changed due to process exit
8963 * or fd copying.
8964 */
1d8007bd
PB		 8965 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8966 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8967 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8968 }
03543133
SS		 8969 if (kvm_x86_ops->vm_destroy)
8970 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8971 kvm_pic_destroy(kvm);
8972 kvm_ioapic_destroy(kvm);
d19a9cd2 8973 kvm_free_vcpus(kvm);
af1bae54 8974 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8975 kvm_mmu_uninit_vm(kvm);
2beb6dad 8976 kvm_page_track_cleanup(kvm);
cbc0236a 8977 kvm_hv_destroy_vm(kvm);
d19a9cd2 8978}
0de10343 8979
5587027c 8980void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8981 struct kvm_memory_slot *dont)
8982{
8983 int i;
8984
d89cc617
TY		 8985 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8986 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8987 kvfree(free->arch.rmap[i]);
d89cc617 8988 free->arch.rmap[i] = NULL;
77d11309 8989 }
d89cc617
TY		 8990 if (i == 0)
8991 continue;
8992
8993 if (!dont || free->arch.lpage_info[i - 1] !=
8994 dont->arch.lpage_info[i - 1]) {
548ef284 8995 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8996 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8997 }
8998 }
21ebbeda
XG		 8999
9000 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9001}
9002
5587027c
AK		 9003int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9004 unsigned long npages)
db3fe4eb
TY		 9005{
9006 int i;
9007
d89cc617 9008 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9009 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9010 unsigned long ugfn;
9011 int lpages;
d89cc617 9012 int level = i + 1;
db3fe4eb
TY		 9013
9014 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9015 slot->base_gfn, level) + 1;
9016
d89cc617 9017 slot->arch.rmap[i] =
778e1cdd
KC		 9018 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
9019 GFP_KERNEL);
d89cc617 9020 if (!slot->arch.rmap[i])
77d11309 9021 goto out_free;
d89cc617
TY		 9022 if (i == 0)
9023 continue;
77d11309 9024
778e1cdd 9025 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL);
92f94f1e 9026 if (!linfo)
db3fe4eb
TY		 9027 goto out_free;
9028
92f94f1e
XG		 9029 slot->arch.lpage_info[i - 1] = linfo;
9030
db3fe4eb 9031 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9032 linfo[0].disallow_lpage = 1;
db3fe4eb 9033 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9034 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9035 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9036 /*
9037 * If the gfn and userspace address are not aligned wrt each
9038 * other, or if explicitly asked to, disable large page
9039 * support for this slot
9040 */
9041 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9042 !kvm_largepages_enabled()) {
9043 unsigned long j;
9044
9045 for (j = 0; j < lpages; ++j)
92f94f1e 9046 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9047 }
9048 }
9049
21ebbeda
XG		 9050 if (kvm_page_track_create_memslot(slot, npages))
9051 goto out_free;
9052
db3fe4eb
TY		 9053 return 0;
9054
9055out_free:
d89cc617 9056 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9057 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9058 slot->arch.rmap[i] = NULL;
9059 if (i == 0)
9060 continue;
9061
548ef284 9062 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9063 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9064 }
9065 return -ENOMEM;
9066}
9067
15f46015 9068void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 9069{
e6dff7d1
TY		 9070 /*
9071 * memslots->generation has been incremented.
9072 * mmio generation may have reached its maximum value.
9073 */
54bf36aa 9074 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 9075}
9076
f7784b8e
MT		 9077int kvm_arch_prepare_memory_region(struct kvm *kvm,
9078 struct kvm_memory_slot *memslot,
09170a49 9079 const struct kvm_userspace_memory_region *mem,
7b6195a9 9080 enum kvm_mr_change change)
0de10343 9081{
f7784b8e
MT		 9082 return 0;
9083}
9084
88178fd4
KH		 9085static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9086 struct kvm_memory_slot *new)
9087{
9088 /* Still write protect RO slot */
9089 if (new->flags & KVM_MEM_READONLY) {
9090 kvm_mmu_slot_remove_write_access(kvm, new);
9091 return;
9092 }
9093
9094 /*
9095 * Call kvm_x86_ops dirty logging hooks when they are valid.
9096 *
9097 * kvm_x86_ops->slot_disable_log_dirty is called when:
9098 *
9099 * - KVM_MR_CREATE with dirty logging is disabled
9100 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9101 *
9102 * The reason is, in case of PML, we need to set D-bit for any slots
9103 * with dirty logging disabled in order to eliminate unnecessary GPA
9104 * logging in PML buffer (and potential PML buffer full VMEXT). This
9105 * guarantees leaving PML enabled during guest's lifetime won't have
9106 * any additonal overhead from PML when guest is running with dirty
9107 * logging disabled for memory slots.
9108 *
9109 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9110 * to dirty logging mode.
9111 *
9112 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9113 *
9114 * In case of write protect:
9115 *
9116 * Write protect all pages for dirty logging.
9117 *
9118 * All the sptes including the large sptes which point to this
9119 * slot are set to readonly. We can not create any new large
9120 * spte on this slot until the end of the logging.
9121 *
9122 * See the comments in fast_page_fault().
9123 */
9124 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9125 if (kvm_x86_ops->slot_enable_log_dirty)
9126 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9127 else
9128 kvm_mmu_slot_remove_write_access(kvm, new);
9129 } else {
9130 if (kvm_x86_ops->slot_disable_log_dirty)
9131 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9132 }
9133}
9134
f7784b8e 9135void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9136 const struct kvm_userspace_memory_region *mem,
8482644a 9137 const struct kvm_memory_slot *old,
f36f3f28 9138 const struct kvm_memory_slot *new,
8482644a 9139 enum kvm_mr_change change)
f7784b8e 9140{
8482644a 9141 int nr_mmu_pages = 0;
f7784b8e 9142
48c0e4e9
XG		 9143 if (!kvm->arch.n_requested_mmu_pages)
9144 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
9145
48c0e4e9 9146 if (nr_mmu_pages)
0de10343 9147 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 9148
3ea3b7fa
WL		 9149 /*
9150 * Dirty logging tracks sptes in 4k granularity, meaning that large
9151 * sptes have to be split. If live migration is successful, the guest
9152 * in the source machine will be destroyed and large sptes will be
9153 * created in the destination. However, if the guest continues to run
9154 * in the source machine (for example if live migration fails), small
9155 * sptes will remain around and cause bad performance.
9156 *
9157 * Scan sptes if dirty logging has been stopped, dropping those
9158 * which can be collapsed into a single large-page spte. Later
9159 * page faults will create the large-page sptes.
9160 */
9161 if ((change != KVM_MR_DELETE) &&
9162 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9163 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9164 kvm_mmu_zap_collapsible_sptes(kvm, new);
9165
c972f3b1 9166 /*
88178fd4 9167 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9168 *
88178fd4
KH		 9169 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9170 * been zapped so no dirty logging staff is needed for old slot. For
9171 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9172 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9173 *
9174 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9175 */
88178fd4 9176 if (change != KVM_MR_DELETE)
f36f3f28 9177 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 9178}
1d737c8a 9179
2df72e9b 9180void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 9181{
6ca18b69 9182 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 9183}
9184
2df72e9b
MT		 9185void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
9186 struct kvm_memory_slot *slot)
9187{
ae7cd873 9188 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 9189}
9190
5d9bc648
PB		 9191static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
9192{
9193 if (!list_empty_careful(&vcpu->async_pf.done))
9194 return true;
9195
9196 if (kvm_apic_has_events(vcpu))
9197 return true;
9198
9199 if (vcpu->arch.pv.pv_unhalted)
9200 return true;
9201
a5f01f8e
WL		 9202 if (vcpu->arch.exception.pending)
9203 return true;
9204
47a66eed
Z		 9205 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
9206 (vcpu->arch.nmi_pending &&
9207 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 9208 return true;
9209
47a66eed
Z		 9210 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
9211 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 9212 return true;
9213
5d9bc648
PB		 9214 if (kvm_arch_interrupt_allowed(vcpu) &&
9215 kvm_cpu_has_interrupt(vcpu))
9216 return true;
9217
1f4b34f8
AS		 9218 if (kvm_hv_has_stimer_pending(vcpu))
9219 return true;
9220
5d9bc648
PB		 9221 return false;
9222}
9223
1d737c8a
ZX		 9224int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
9225{
5d9bc648 9226 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 9227}
5736199a 9228
199b5763
LM		 9229bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
9230{
de63ad4c 9231 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 9232}
9233
b6d33834 9234int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 9235{
b6d33834 9236 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 9237}
78646121
GN		 9238
9239int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
9240{
9241 return kvm_x86_ops->interrupt_allowed(vcpu);
9242}
229456fc 9243
82b32774 9244unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 9245{
82b32774
NA		 9246 if (is_64_bit_mode(vcpu))
9247 return kvm_rip_read(vcpu);
9248 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
9249 kvm_rip_read(vcpu));
9250}
9251EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 9252
82b32774
NA		 9253bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
9254{
9255 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 9256}
9257EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
9258
94fe45da
JK		 9259unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
9260{
9261 unsigned long rflags;
9262
9263 rflags = kvm_x86_ops->get_rflags(vcpu);
9264 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 9265 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 9266 return rflags;
9267}
9268EXPORT_SYMBOL_GPL(kvm_get_rflags);
9269
6addfc42 9270static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 9271{
9272 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 9273 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 9274 rflags |= X86_EFLAGS_TF;
94fe45da 9275 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 9276}
9277
9278void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
9279{
9280 __kvm_set_rflags(vcpu, rflags);
3842d135 9281 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 9282}
9283EXPORT_SYMBOL_GPL(kvm_set_rflags);
9284
56028d08
GN		 9285void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
9286{
9287 int r;
9288
fb67e14f 9289 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 9290 work->wakeup_all)
56028d08
GN		 9291 return;
9292
9293 r = kvm_mmu_reload(vcpu);
9294 if (unlikely(r))
9295 return;
9296
fb67e14f
XG		 9297 if (!vcpu->arch.mmu.direct_map &&
9298 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
9299 return;
9300
56028d08
GN		 9301 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
9302}
9303
af585b92
GN		 9304static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
9305{
9306 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9307}
9308
9309static inline u32 kvm_async_pf_next_probe(u32 key)
9310{
9311 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9312}
9313
9314static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9315{
9316 u32 key = kvm_async_pf_hash_fn(gfn);
9317
9318 while (vcpu->arch.apf.gfns[key] != ~0)
9319 key = kvm_async_pf_next_probe(key);
9320
9321 vcpu->arch.apf.gfns[key] = gfn;
9322}
9323
9324static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9325{
9326 int i;
9327 u32 key = kvm_async_pf_hash_fn(gfn);
9328
9329 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9330 (vcpu->arch.apf.gfns[key] != gfn &&
9331 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9332 key = kvm_async_pf_next_probe(key);
9333
9334 return key;
9335}
9336
9337bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9338{
9339 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9340}
9341
9342static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9343{
9344 u32 i, j, k;
9345
9346 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9347 while (true) {
9348 vcpu->arch.apf.gfns[i] = ~0;
9349 do {
9350 j = kvm_async_pf_next_probe(j);
9351 if (vcpu->arch.apf.gfns[j] == ~0)
9352 return;
9353 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9354 /*
9355 * k lies cyclically in ]i,j]
9356 * | i.k.j |
9357 * |....j i.k.| or |.k..j i...|
9358 */
9359 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9360 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9361 i = j;
9362 }
9363}
9364
7c90705b
GN		 9365static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9366{
4e335d9e
PB		 9367
9368 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9369 sizeof(val));
7c90705b
GN		 9370}
9371
9a6e7c39
WL		 9372static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9373{
9374
9375 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9376 sizeof(u32));
9377}
9378
af585b92
GN		 9379void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9380 struct kvm_async_pf *work)
9381{
6389ee94
AK		 9382 struct x86_exception fault;
9383
7c90705b 9384 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9385 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9386
9387 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9388 (vcpu->arch.apf.send_user_only &&
9389 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9390 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9391 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9392 fault.vector = PF_VECTOR;
9393 fault.error_code_valid = true;
9394 fault.error_code = 0;
9395 fault.nested_page_fault = false;
9396 fault.address = work->arch.token;
adfe20fb 9397 fault.async_page_fault = true;
6389ee94 9398 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9399 }
af585b92
GN		 9400}
9401
9402void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9403 struct kvm_async_pf *work)
9404{
6389ee94 9405 struct x86_exception fault;
9a6e7c39 9406 u32 val;
6389ee94 9407
f2e10669 9408 if (work->wakeup_all)
7c90705b
GN		 9409 work->arch.token = ~0; /* broadcast wakeup */
9410 else
9411 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9412 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9413
9a6e7c39
WL		 9414 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9415 !apf_get_user(vcpu, &val)) {
9416 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9417 vcpu->arch.exception.pending &&
9418 vcpu->arch.exception.nr == PF_VECTOR &&
9419 !apf_put_user(vcpu, 0)) {
9420 vcpu->arch.exception.injected = false;
9421 vcpu->arch.exception.pending = false;
9422 vcpu->arch.exception.nr = 0;
9423 vcpu->arch.exception.has_error_code = false;
9424 vcpu->arch.exception.error_code = 0;
9425 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9426 fault.vector = PF_VECTOR;
9427 fault.error_code_valid = true;
9428 fault.error_code = 0;
9429 fault.nested_page_fault = false;
9430 fault.address = work->arch.token;
9431 fault.async_page_fault = true;
9432 kvm_inject_page_fault(vcpu, &fault);
9433 }
7c90705b 9434 }
e6d53e3b 9435 vcpu->arch.apf.halted = false;
a4fa1635 9436 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9437}
9438
9439bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9440{
9441 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9442 return true;
9443 else
9bc1f09f 9444 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9445}
9446
5544eb9b
PB		 9447void kvm_arch_start_assignment(struct kvm *kvm)
9448{
9449 atomic_inc(&kvm->arch.assigned_device_count);
9450}
9451EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9452
9453void kvm_arch_end_assignment(struct kvm *kvm)
9454{
9455 atomic_dec(&kvm->arch.assigned_device_count);
9456}
9457EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9458
9459bool kvm_arch_has_assigned_device(struct kvm *kvm)
9460{
9461 return atomic_read(&kvm->arch.assigned_device_count);
9462}
9463EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9464
e0f0bbc5
AW		 9465void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9466{
9467 atomic_inc(&kvm->arch.noncoherent_dma_count);
9468}
9469EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9470
9471void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9472{
9473 atomic_dec(&kvm->arch.noncoherent_dma_count);
9474}
9475EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9476
9477bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9478{
9479 return atomic_read(&kvm->arch.noncoherent_dma_count);
9480}
9481EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9482
14717e20
AW		 9483bool kvm_arch_has_irq_bypass(void)
9484{
9485 return kvm_x86_ops->update_pi_irte != NULL;
9486}
9487
87276880
FW		 9488int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9489 struct irq_bypass_producer *prod)
9490{
9491 struct kvm_kernel_irqfd *irqfd =
9492 container_of(cons, struct kvm_kernel_irqfd, consumer);
9493
14717e20 9494 irqfd->producer = prod;
87276880 9495
14717e20
AW		 9496 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9497 prod->irq, irqfd->gsi, 1);
87276880
FW		 9498}
9499
9500void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9501 struct irq_bypass_producer *prod)
9502{
9503 int ret;
9504 struct kvm_kernel_irqfd *irqfd =
9505 container_of(cons, struct kvm_kernel_irqfd, consumer);
9506
87276880
FW		 9507 WARN_ON(irqfd->producer != prod);
9508 irqfd->producer = NULL;
9509
9510 /*
9511 * When producer of consumer is unregistered, we change back to
9512 * remapped mode, so we can re-use the current implementation
bb3541f1 9513 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9514 * int this case doesn't want to receive the interrupts.
9515 */
9516 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9517 if (ret)
9518 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9519 " fails: %d\n", irqfd->consumer.token, ret);
9520}
9521
9522int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9523 uint32_t guest_irq, bool set)
9524{
9525 if (!kvm_x86_ops->update_pi_irte)
9526 return -EINVAL;
9527
9528 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9529}
9530
52004014
FW		 9531bool kvm_vector_hashing_enabled(void)
9532{
9533 return vector_hashing;
9534}
9535EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9536
229456fc 9537EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9538EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9539EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9540EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9541EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9542EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9543EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9544EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9545EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9546EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9547EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9548EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9549EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9550EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9551EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9552EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9553EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9554EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9555EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)