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Merge tag 'vfio-v4.4-rc5' of git://github.com/awilliam/linux-vfio
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
893590c7 126static bool __read_mostly backwards_tsc_observed = false;
16a96021 127
18863bdd
AK		 128#define KVM_NR_SHARED_MSRS 16
129
130struct kvm_shared_msrs_global {
131 int nr;
2bf78fa7 132 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 133};
134
135struct kvm_shared_msrs {
136 struct user_return_notifier urn;
137 bool registered;
2bf78fa7
SY		 138 struct kvm_shared_msr_values {
139 u64 host;
140 u64 curr;
141 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 142};
143
144static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 145static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 146
417bc304 147struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 148 { "pf_fixed", VCPU_STAT(pf_fixed) },
149 { "pf_guest", VCPU_STAT(pf_guest) },
150 { "tlb_flush", VCPU_STAT(tlb_flush) },
151 { "invlpg", VCPU_STAT(invlpg) },
152 { "exits", VCPU_STAT(exits) },
153 { "io_exits", VCPU_STAT(io_exits) },
154 { "mmio_exits", VCPU_STAT(mmio_exits) },
155 { "signal_exits", VCPU_STAT(signal_exits) },
156 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 157 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 158 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 159 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 160 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 161 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 162 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 163 { "request_irq", VCPU_STAT(request_irq_exits) },
164 { "irq_exits", VCPU_STAT(irq_exits) },
165 { "host_state_reload", VCPU_STAT(host_state_reload) },
166 { "efer_reload", VCPU_STAT(efer_reload) },
167 { "fpu_reload", VCPU_STAT(fpu_reload) },
168 { "insn_emulation", VCPU_STAT(insn_emulation) },
169 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 170 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 171 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 172 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
173 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
174 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
175 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
176 { "mmu_flooded", VM_STAT(mmu_flooded) },
177 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 178 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 179 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 180 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 181 { "largepages", VM_STAT(lpages) },
417bc304
HB		 182 { NULL }
183};
184
2acf923e
DC		 185u64 __read_mostly host_xcr0;
186
b6785def 187static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 188
af585b92
GN		 189static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
190{
191 int i;
192 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
193 vcpu->arch.apf.gfns[i] = ~0;
194}
195
18863bdd
AK		 196static void kvm_on_user_return(struct user_return_notifier *urn)
197{
198 unsigned slot;
18863bdd
AK		 199 struct kvm_shared_msrs *locals
200 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 201 struct kvm_shared_msr_values *values;
18863bdd
AK		 202
203 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 204 values = &locals->values[slot];
205 if (values->host != values->curr) {
206 wrmsrl(shared_msrs_global.msrs[slot], values->host);
207 values->curr = values->host;
18863bdd
AK		 208 }
209 }
210 locals->registered = false;
211 user_return_notifier_unregister(urn);
212}
213
2bf78fa7 214static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 215{
18863bdd 216 u64 value;
013f6a5d
MT		 217 unsigned int cpu = smp_processor_id();
218 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 219
2bf78fa7
SY		 220 /* only read, and nobody should modify it at this time,
221 * so don't need lock */
222 if (slot >= shared_msrs_global.nr) {
223 printk(KERN_ERR "kvm: invalid MSR slot!");
224 return;
225 }
226 rdmsrl_safe(msr, &value);
227 smsr->values[slot].host = value;
228 smsr->values[slot].curr = value;
229}
230
231void kvm_define_shared_msr(unsigned slot, u32 msr)
232{
0123be42 233 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 234 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 235 if (slot >= shared_msrs_global.nr)
236 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 237}
238EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
239
240static void kvm_shared_msr_cpu_online(void)
241{
242 unsigned i;
18863bdd
AK		 243
244 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 245 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 246}
247
8b3c3104 248int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 249{
013f6a5d
MT		 250 unsigned int cpu = smp_processor_id();
251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 252 int err;
18863bdd 253
2bf78fa7 254 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 255 return 0;
2bf78fa7 256 smsr->values[slot].curr = value;
8b3c3104
AH		 257 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
258 if (err)
259 return 1;
260
18863bdd
AK		 261 if (!smsr->registered) {
262 smsr->urn.on_user_return = kvm_on_user_return;
263 user_return_notifier_register(&smsr->urn);
264 smsr->registered = true;
265 }
8b3c3104 266 return 0;
18863bdd
AK		 267}
268EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
269
13a34e06 270static void drop_user_return_notifiers(void)
3548bab5 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 274
275 if (smsr->registered)
276 kvm_on_user_return(&smsr->urn);
277}
278
6866b83e
CO		 279u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
280{
8a5a87d9 281 return vcpu->arch.apic_base;
6866b83e
CO		 282}
283EXPORT_SYMBOL_GPL(kvm_get_apic_base);
284
58cb628d
JK		 285int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
286{
287 u64 old_state = vcpu->arch.apic_base &
288 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
289 u64 new_state = msr_info->data &
290 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
291 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
292 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
293
294 if (!msr_info->host_initiated &&
295 ((msr_info->data & reserved_bits) != 0 ||
296 new_state == X2APIC_ENABLE ||
297 (new_state == MSR_IA32_APICBASE_ENABLE &&
298 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
299 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
300 old_state == 0)))
301 return 1;
302
303 kvm_lapic_set_base(vcpu, msr_info->data);
304 return 0;
6866b83e
CO		 305}
306EXPORT_SYMBOL_GPL(kvm_set_apic_base);
307
2605fc21 308asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 309{
310 /* Fault while not rebooting. We want the trace. */
311 BUG();
312}
313EXPORT_SYMBOL_GPL(kvm_spurious_fault);
314
3fd28fce
ED		 315#define EXCPT_BENIGN 0
316#define EXCPT_CONTRIBUTORY 1
317#define EXCPT_PF 2
318
319static int exception_class(int vector)
320{
321 switch (vector) {
322 case PF_VECTOR:
323 return EXCPT_PF;
324 case DE_VECTOR:
325 case TS_VECTOR:
326 case NP_VECTOR:
327 case SS_VECTOR:
328 case GP_VECTOR:
329 return EXCPT_CONTRIBUTORY;
330 default:
331 break;
332 }
333 return EXCPT_BENIGN;
334}
335
d6e8c854
NA		 336#define EXCPT_FAULT 0
337#define EXCPT_TRAP 1
338#define EXCPT_ABORT 2
339#define EXCPT_INTERRUPT 3
340
341static int exception_type(int vector)
342{
343 unsigned int mask;
344
345 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
346 return EXCPT_INTERRUPT;
347
348 mask = 1 << vector;
349
350 /* #DB is trap, as instruction watchpoints are handled elsewhere */
351 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
352 return EXCPT_TRAP;
353
354 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
355 return EXCPT_ABORT;
356
357 /* Reserved exceptions will result in fault */
358 return EXCPT_FAULT;
359}
360
3fd28fce 361static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 362 unsigned nr, bool has_error, u32 error_code,
363 bool reinject)
3fd28fce
ED		 364{
365 u32 prev_nr;
366 int class1, class2;
367
3842d135
AK		 368 kvm_make_request(KVM_REQ_EVENT, vcpu);
369
3fd28fce
ED		 370 if (!vcpu->arch.exception.pending) {
371 queue:
3ffb2468
NA		 372 if (has_error && !is_protmode(vcpu))
373 has_error = false;
3fd28fce
ED		 374 vcpu->arch.exception.pending = true;
375 vcpu->arch.exception.has_error_code = has_error;
376 vcpu->arch.exception.nr = nr;
377 vcpu->arch.exception.error_code = error_code;
3f0fd292 378 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 379 return;
380 }
381
382 /* to check exception */
383 prev_nr = vcpu->arch.exception.nr;
384 if (prev_nr == DF_VECTOR) {
385 /* triple fault -> shutdown */
a8eeb04a 386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 387 return;
388 }
389 class1 = exception_class(prev_nr);
390 class2 = exception_class(nr);
391 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
392 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
393 /* generate double fault per SDM Table 5-5 */
394 vcpu->arch.exception.pending = true;
395 vcpu->arch.exception.has_error_code = true;
396 vcpu->arch.exception.nr = DF_VECTOR;
397 vcpu->arch.exception.error_code = 0;
398 } else
399 /* replace previous exception with a new one in a hope
400 that instruction re-execution will regenerate lost
401 exception */
402 goto queue;
403}
404
298101da
AK		 405void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
406{
ce7ddec4 407 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 408}
409EXPORT_SYMBOL_GPL(kvm_queue_exception);
410
ce7ddec4
JR		 411void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
412{
413 kvm_multiple_exception(vcpu, nr, false, 0, true);
414}
415EXPORT_SYMBOL_GPL(kvm_requeue_exception);
416
db8fcefa 417void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 418{
db8fcefa
AP		 419 if (err)
420 kvm_inject_gp(vcpu, 0);
421 else
422 kvm_x86_ops->skip_emulated_instruction(vcpu);
423}
424EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 425
6389ee94 426void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 427{
428 ++vcpu->stat.pf_guest;
6389ee94
AK		 429 vcpu->arch.cr2 = fault->address;
430 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 431}
27d6c865 432EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 433
ef54bcfe 434static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 435{
6389ee94
AK		 436 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
437 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 438 else
6389ee94 439 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 440
441 return fault->nested_page_fault;
d4f8cf66
JR		 442}
443
3419ffc8
SY		 444void kvm_inject_nmi(struct kvm_vcpu *vcpu)
445{
7460fb4a
AK		 446 atomic_inc(&vcpu->arch.nmi_queued);
447 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 448}
449EXPORT_SYMBOL_GPL(kvm_inject_nmi);
450
298101da
AK		 451void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
452{
ce7ddec4 453 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 454}
455EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
456
ce7ddec4
JR		 457void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
458{
459 kvm_multiple_exception(vcpu, nr, true, error_code, true);
460}
461EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
462
0a79b009
AK		 463/*
464 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
465 * a #GP and return false.
466 */
467bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 468{
0a79b009
AK		 469 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
470 return true;
471 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
472 return false;
298101da 473}
0a79b009 474EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 475
16f8a6f9
NA		 476bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
477{
478 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
479 return true;
480
481 kvm_queue_exception(vcpu, UD_VECTOR);
482 return false;
483}
484EXPORT_SYMBOL_GPL(kvm_require_dr);
485
ec92fe44
JR		 486/*
487 * This function will be used to read from the physical memory of the currently
54bf36aa 488 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 489 * can read from guest physical or from the guest's guest physical memory.
490 */
491int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
492 gfn_t ngfn, void *data, int offset, int len,
493 u32 access)
494{
54987b7a 495 struct x86_exception exception;
ec92fe44
JR		 496 gfn_t real_gfn;
497 gpa_t ngpa;
498
499 ngpa = gfn_to_gpa(ngfn);
54987b7a 500 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 501 if (real_gfn == UNMAPPED_GVA)
502 return -EFAULT;
503
504 real_gfn = gpa_to_gfn(real_gfn);
505
54bf36aa 506 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 507}
508EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
509
69b0049a 510static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 511 void *data, int offset, int len, u32 access)
512{
513 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
514 data, offset, len, access);
515}
516
a03490ed
CO		 517/*
518 * Load the pae pdptrs. Return true is they are all valid.
519 */
ff03a073 520int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 521{
522 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
523 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
524 int i;
525 int ret;
ff03a073 526 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 527
ff03a073
JR		 528 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
529 offset * sizeof(u64), sizeof(pdpte),
530 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 531 if (ret < 0) {
532 ret = 0;
533 goto out;
534 }
535 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 536 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 537 (pdpte[i] &
538 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 539 ret = 0;
540 goto out;
541 }
542 }
543 ret = 1;
544
ff03a073 545 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 546 __set_bit(VCPU_EXREG_PDPTR,
547 (unsigned long *)&vcpu->arch.regs_avail);
548 __set_bit(VCPU_EXREG_PDPTR,
549 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 550out:
a03490ed
CO		 551
552 return ret;
553}
cc4b6871 554EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 555
d835dfec
AK		 556static bool pdptrs_changed(struct kvm_vcpu *vcpu)
557{
ff03a073 558 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 559 bool changed = true;
3d06b8bf
JR		 560 int offset;
561 gfn_t gfn;
d835dfec
AK		 562 int r;
563
564 if (is_long_mode(vcpu) || !is_pae(vcpu))
565 return false;
566
6de4f3ad
AK		 567 if (!test_bit(VCPU_EXREG_PDPTR,
568 (unsigned long *)&vcpu->arch.regs_avail))
569 return true;
570
9f8fe504
AK		 571 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
572 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 573 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
574 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 575 if (r < 0)
576 goto out;
ff03a073 577 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 578out:
d835dfec
AK		 579
580 return changed;
581}
582
49a9b07e 583int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 584{
aad82703 585 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 586 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 587
f9a48e6a
AK		 588 cr0 |= X86_CR0_ET;
589
ab344828 590#ifdef CONFIG_X86_64
0f12244f
GN		 591 if (cr0 & 0xffffffff00000000UL)
592 return 1;
ab344828
GN		 593#endif
594
595 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 596
0f12244f
GN		 597 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
598 return 1;
a03490ed 599
0f12244f
GN		 600 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
601 return 1;
a03490ed
CO		 602
603 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
604#ifdef CONFIG_X86_64
f6801dff 605 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 606 int cs_db, cs_l;
607
0f12244f
GN		 608 if (!is_pae(vcpu))
609 return 1;
a03490ed 610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 611 if (cs_l)
612 return 1;
a03490ed
CO		 613 } else
614#endif
ff03a073 615 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 616 kvm_read_cr3(vcpu)))
0f12244f 617 return 1;
a03490ed
CO		 618 }
619
ad756a16
MJ		 620 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
621 return 1;
622
a03490ed 623 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 624
d170c419 625 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 626 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 627 kvm_async_pf_hash_reset(vcpu);
628 }
e5f3f027 629
aad82703
SY		 630 if ((cr0 ^ old_cr0) & update_bits)
631 kvm_mmu_reset_context(vcpu);
b18d5431 632
879ae188
LE		 633 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
634 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
635 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 636 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
637
0f12244f
GN		 638 return 0;
639}
2d3ad1f4 640EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 641
2d3ad1f4 642void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 643{
49a9b07e 644 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 645}
2d3ad1f4 646EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 647
42bdf991
MT		 648static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
649{
650 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
651 !vcpu->guest_xcr0_loaded) {
652 /* kvm_set_xcr() also depends on this */
653 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
654 vcpu->guest_xcr0_loaded = 1;
655 }
656}
657
658static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
659{
660 if (vcpu->guest_xcr0_loaded) {
661 if (vcpu->arch.xcr0 != host_xcr0)
662 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
663 vcpu->guest_xcr0_loaded = 0;
664 }
665}
666
69b0049a 667static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 668{
56c103ec
LJ		 669 u64 xcr0 = xcr;
670 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 671 u64 valid_bits;
2acf923e
DC		 672
673 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
674 if (index != XCR_XFEATURE_ENABLED_MASK)
675 return 1;
d91cab78 676 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 677 return 1;
d91cab78 678 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 679 return 1;
46c34cb0
PB		 680
681 /*
682 * Do not allow the guest to set bits that we do not support
683 * saving. However, xcr0 bit 0 is always set, even if the
684 * emulated CPU does not support XSAVE (see fx_init).
685 */
d91cab78 686 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 687 if (xcr0 & ~valid_bits)
2acf923e 688 return 1;
46c34cb0 689
d91cab78
DH		 690 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
691 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 692 return 1;
693
d91cab78
DH		 694 if (xcr0 & XFEATURE_MASK_AVX512) {
695 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 696 return 1;
d91cab78 697 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 698 return 1;
699 }
42bdf991 700 kvm_put_guest_xcr0(vcpu);
2acf923e 701 vcpu->arch.xcr0 = xcr0;
56c103ec 702
d91cab78 703 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 704 kvm_update_cpuid(vcpu);
2acf923e
DC		 705 return 0;
706}
707
708int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
709{
764bcbc5
Z		 710 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
711 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 712 kvm_inject_gp(vcpu, 0);
713 return 1;
714 }
715 return 0;
716}
717EXPORT_SYMBOL_GPL(kvm_set_xcr);
718
a83b29c6 719int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 720{
fc78f519 721 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 722 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
723 X86_CR4_SMEP | X86_CR4_SMAP;
724
0f12244f
GN		 725 if (cr4 & CR4_RESERVED_BITS)
726 return 1;
a03490ed 727
2acf923e
DC		 728 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
729 return 1;
730
c68b734f
YW		 731 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
732 return 1;
733
97ec8c06
FW		 734 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
735 return 1;
736
afcbf13f 737 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 738 return 1;
739
a03490ed 740 if (is_long_mode(vcpu)) {
0f12244f
GN		 741 if (!(cr4 & X86_CR4_PAE))
742 return 1;
a2edf57f
AK		 743 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
744 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 745 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
746 kvm_read_cr3(vcpu)))
0f12244f
GN		 747 return 1;
748
ad756a16
MJ		 749 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
750 if (!guest_cpuid_has_pcid(vcpu))
751 return 1;
752
753 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
754 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
755 return 1;
756 }
757
5e1746d6 758 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 759 return 1;
a03490ed 760
ad756a16
MJ		 761 if (((cr4 ^ old_cr4) & pdptr_bits) ||
762 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 763 kvm_mmu_reset_context(vcpu);
0f12244f 764
2acf923e 765 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 766 kvm_update_cpuid(vcpu);
2acf923e 767
0f12244f
GN		 768 return 0;
769}
2d3ad1f4 770EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 771
2390218b 772int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 773{
ac146235 774#ifdef CONFIG_X86_64
9d88fca7 775 cr3 &= ~CR3_PCID_INVD;
ac146235 776#endif
9d88fca7 777
9f8fe504 778 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 779 kvm_mmu_sync_roots(vcpu);
77c3913b 780 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 781 return 0;
d835dfec
AK		 782 }
783
a03490ed 784 if (is_long_mode(vcpu)) {
d9f89b88
JK		 785 if (cr3 & CR3_L_MODE_RESERVED_BITS)
786 return 1;
787 } else if (is_pae(vcpu) && is_paging(vcpu) &&
788 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 789 return 1;
a03490ed 790
0f12244f 791 vcpu->arch.cr3 = cr3;
aff48baa 792 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 793 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 794 return 0;
795}
2d3ad1f4 796EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 797
eea1cff9 798int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 799{
0f12244f
GN		 800 if (cr8 & CR8_RESERVED_BITS)
801 return 1;
35754c98 802 if (lapic_in_kernel(vcpu))
a03490ed
CO		 803 kvm_lapic_set_tpr(vcpu, cr8);
804 else
ad312c7c 805 vcpu->arch.cr8 = cr8;
0f12244f
GN		 806 return 0;
807}
2d3ad1f4 808EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 809
2d3ad1f4 810unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 811{
35754c98 812 if (lapic_in_kernel(vcpu))
a03490ed
CO		 813 return kvm_lapic_get_cr8(vcpu);
814 else
ad312c7c 815 return vcpu->arch.cr8;
a03490ed 816}
2d3ad1f4 817EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 818
ae561ede
NA		 819static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
820{
821 int i;
822
823 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
824 for (i = 0; i < KVM_NR_DB_REGS; i++)
825 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
826 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
827 }
828}
829
73aaf249
JK		 830static void kvm_update_dr6(struct kvm_vcpu *vcpu)
831{
832 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
833 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
834}
835
c8639010
JK		 836static void kvm_update_dr7(struct kvm_vcpu *vcpu)
837{
838 unsigned long dr7;
839
840 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
841 dr7 = vcpu->arch.guest_debug_dr7;
842 else
843 dr7 = vcpu->arch.dr7;
844 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 845 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
846 if (dr7 & DR7_BP_EN_MASK)
847 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 848}
849
6f43ed01
NA		 850static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
851{
852 u64 fixed = DR6_FIXED_1;
853
854 if (!guest_cpuid_has_rtm(vcpu))
855 fixed |= DR6_RTM;
856 return fixed;
857}
858
338dbc97 859static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 860{
861 switch (dr) {
862 case 0 ... 3:
863 vcpu->arch.db[dr] = val;
864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 vcpu->arch.eff_db[dr] = val;
866 break;
867 case 4:
020df079
GN		 868 /* fall through */
869 case 6:
338dbc97
GN		 870 if (val & 0xffffffff00000000ULL)
871 return -1; /* #GP */
6f43ed01 872 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 873 kvm_update_dr6(vcpu);
020df079
GN		 874 break;
875 case 5:
020df079
GN		 876 /* fall through */
877 default: /* 7 */
338dbc97
GN		 878 if (val & 0xffffffff00000000ULL)
879 return -1; /* #GP */
020df079 880 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 881 kvm_update_dr7(vcpu);
020df079
GN		 882 break;
883 }
884
885 return 0;
886}
338dbc97
GN		 887
888int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
889{
16f8a6f9 890 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 891 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 892 return 1;
893 }
894 return 0;
338dbc97 895}
020df079
GN		 896EXPORT_SYMBOL_GPL(kvm_set_dr);
897
16f8a6f9 898int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 899{
900 switch (dr) {
901 case 0 ... 3:
902 *val = vcpu->arch.db[dr];
903 break;
904 case 4:
020df079
GN		 905 /* fall through */
906 case 6:
73aaf249
JK		 907 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
908 *val = vcpu->arch.dr6;
909 else
910 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 911 break;
912 case 5:
020df079
GN		 913 /* fall through */
914 default: /* 7 */
915 *val = vcpu->arch.dr7;
916 break;
917 }
338dbc97
GN		 918 return 0;
919}
020df079
GN		 920EXPORT_SYMBOL_GPL(kvm_get_dr);
921
022cd0e8
AK		 922bool kvm_rdpmc(struct kvm_vcpu *vcpu)
923{
924 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
925 u64 data;
926 int err;
927
c6702c9d 928 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 929 if (err)
930 return err;
931 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
932 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
933 return err;
934}
935EXPORT_SYMBOL_GPL(kvm_rdpmc);
936
043405e1
CO		 937/*
938 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
939 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
940 *
941 * This list is modified at module load time to reflect the
e3267cbb 942 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 943 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
944 * may depend on host virtualization features rather than host cpu features.
043405e1 945 */
e3267cbb 946
043405e1
CO		 947static u32 msrs_to_save[] = {
948 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 949 MSR_STAR,
043405e1
CO		 950#ifdef CONFIG_X86_64
951 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
952#endif
b3897a49 953 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 954 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 955};
956
957static unsigned num_msrs_to_save;
958
62ef68bb
PB		 959static u32 emulated_msrs[] = {
960 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
961 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
962 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
963 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 964 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
965 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 966 HV_X64_MSR_RESET,
11c4b1ca 967 HV_X64_MSR_VP_INDEX,
9eec50b8 968 HV_X64_MSR_VP_RUNTIME,
62ef68bb
PB		 969 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
970 MSR_KVM_PV_EOI_EN,
971
ba904635 972 MSR_IA32_TSC_ADJUST,
a3e06bbe 973 MSR_IA32_TSCDEADLINE,
043405e1 974 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 975 MSR_IA32_MCG_STATUS,
976 MSR_IA32_MCG_CTL,
64d60670 977 MSR_IA32_SMBASE,
043405e1
CO		 978};
979
62ef68bb
PB		 980static unsigned num_emulated_msrs;
981
384bb783 982bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 983{
b69e8cae 984 if (efer & efer_reserved_bits)
384bb783 985 return false;
15c4a640 986
1b2fd70c
AG		 987 if (efer & EFER_FFXSR) {
988 struct kvm_cpuid_entry2 *feat;
989
990 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 991 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 992 return false;
1b2fd70c
AG		 993 }
994
d8017474
AG		 995 if (efer & EFER_SVME) {
996 struct kvm_cpuid_entry2 *feat;
997
998 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 999 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1000 return false;
d8017474
AG		 1001 }
1002
384bb783
JK		 1003 return true;
1004}
1005EXPORT_SYMBOL_GPL(kvm_valid_efer);
1006
1007static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1008{
1009 u64 old_efer = vcpu->arch.efer;
1010
1011 if (!kvm_valid_efer(vcpu, efer))
1012 return 1;
1013
1014 if (is_paging(vcpu)
1015 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1016 return 1;
1017
15c4a640 1018 efer &= ~EFER_LMA;
f6801dff 1019 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1020
a3d204e2
SY		 1021 kvm_x86_ops->set_efer(vcpu, efer);
1022
aad82703
SY		 1023 /* Update reserved bits */
1024 if ((efer ^ old_efer) & EFER_NX)
1025 kvm_mmu_reset_context(vcpu);
1026
b69e8cae 1027 return 0;
15c4a640
CO		 1028}
1029
f2b4b7dd
JR		 1030void kvm_enable_efer_bits(u64 mask)
1031{
1032 efer_reserved_bits &= ~mask;
1033}
1034EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1035
15c4a640
CO		 1036/*
1037 * Writes msr value into into the appropriate "register".
1038 * Returns 0 on success, non-0 otherwise.
1039 * Assumes vcpu_load() was already called.
1040 */
8fe8ab46 1041int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1042{
854e8bb1
NA		 1043 switch (msr->index) {
1044 case MSR_FS_BASE:
1045 case MSR_GS_BASE:
1046 case MSR_KERNEL_GS_BASE:
1047 case MSR_CSTAR:
1048 case MSR_LSTAR:
1049 if (is_noncanonical_address(msr->data))
1050 return 1;
1051 break;
1052 case MSR_IA32_SYSENTER_EIP:
1053 case MSR_IA32_SYSENTER_ESP:
1054 /*
1055 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1056 * non-canonical address is written on Intel but not on
1057 * AMD (which ignores the top 32-bits, because it does
1058 * not implement 64-bit SYSENTER).
1059 *
1060 * 64-bit code should hence be able to write a non-canonical
1061 * value on AMD. Making the address canonical ensures that
1062 * vmentry does not fail on Intel after writing a non-canonical
1063 * value, and that something deterministic happens if the guest
1064 * invokes 64-bit SYSENTER.
1065 */
1066 msr->data = get_canonical(msr->data);
1067 }
8fe8ab46 1068 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1069}
854e8bb1 1070EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1071
313a3dc7
CO		 1072/*
1073 * Adapt set_msr() to msr_io()'s calling convention
1074 */
609e36d3
PB		 1075static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1076{
1077 struct msr_data msr;
1078 int r;
1079
1080 msr.index = index;
1081 msr.host_initiated = true;
1082 r = kvm_get_msr(vcpu, &msr);
1083 if (r)
1084 return r;
1085
1086 *data = msr.data;
1087 return 0;
1088}
1089
313a3dc7
CO		 1090static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1091{
8fe8ab46
WA		 1092 struct msr_data msr;
1093
1094 msr.data = *data;
1095 msr.index = index;
1096 msr.host_initiated = true;
1097 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1098}
1099
16e8d74d
MT		 1100#ifdef CONFIG_X86_64
1101struct pvclock_gtod_data {
1102 seqcount_t seq;
1103
1104 struct { /* extract of a clocksource struct */
1105 int vclock_mode;
1106 cycle_t cycle_last;
1107 cycle_t mask;
1108 u32 mult;
1109 u32 shift;
1110 } clock;
1111
cbcf2dd3
TG		 1112 u64 boot_ns;
1113 u64 nsec_base;
16e8d74d
MT		 1114};
1115
1116static struct pvclock_gtod_data pvclock_gtod_data;
1117
1118static void update_pvclock_gtod(struct timekeeper *tk)
1119{
1120 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1121 u64 boot_ns;
1122
876e7881 1123 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1124
1125 write_seqcount_begin(&vdata->seq);
1126
1127 /* copy pvclock gtod data */
876e7881
PZ		 1128 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1129 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1130 vdata->clock.mask = tk->tkr_mono.mask;
1131 vdata->clock.mult = tk->tkr_mono.mult;
1132 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1133
cbcf2dd3 1134 vdata->boot_ns = boot_ns;
876e7881 1135 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1136
1137 write_seqcount_end(&vdata->seq);
1138}
1139#endif
1140
bab5bb39
NK		 1141void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1142{
1143 /*
1144 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1145 * vcpu_enter_guest. This function is only called from
1146 * the physical CPU that is running vcpu.
1147 */
1148 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1149}
16e8d74d 1150
18068523
GOC		 1151static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1152{
9ed3c444
AK		 1153 int version;
1154 int r;
50d0a0f9 1155 struct pvclock_wall_clock wc;
923de3cf 1156 struct timespec boot;
18068523
GOC		 1157
1158 if (!wall_clock)
1159 return;
1160
9ed3c444
AK		 1161 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1162 if (r)
1163 return;
1164
1165 if (version & 1)
1166 ++version; /* first time write, random junk */
1167
1168 ++version;
18068523 1169
18068523
GOC		 1170 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1171
50d0a0f9
GH		 1172 /*
1173 * The guest calculates current wall clock time by adding
34c238a1 1174 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1175 * wall clock specified here. guest system time equals host
1176 * system time for us, thus we must fill in host boot time here.
1177 */
923de3cf 1178 getboottime(&boot);
50d0a0f9 1179
4b648665
BR		 1180 if (kvm->arch.kvmclock_offset) {
1181 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1182 boot = timespec_sub(boot, ts);
1183 }
50d0a0f9
GH		 1184 wc.sec = boot.tv_sec;
1185 wc.nsec = boot.tv_nsec;
1186 wc.version = version;
18068523
GOC		 1187
1188 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1189
1190 version++;
1191 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1192}
1193
50d0a0f9
GH		 1194static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1195{
1196 uint32_t quotient, remainder;
1197
1198 /* Don't try to replace with do_div(), this one calculates
1199 * "(dividend << 32) / divisor" */
1200 __asm__ ( "divl %4"
1201 : "=a" (quotient), "=d" (remainder)
1202 : "0" (0), "1" (dividend), "r" (divisor) );
1203 return quotient;
1204}
1205
5f4e3f88
ZA		 1206static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1207 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1208{
5f4e3f88 1209 uint64_t scaled64;
50d0a0f9
GH		 1210 int32_t shift = 0;
1211 uint64_t tps64;
1212 uint32_t tps32;
1213
5f4e3f88
ZA		 1214 tps64 = base_khz * 1000LL;
1215 scaled64 = scaled_khz * 1000LL;
50933623 1216 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1217 tps64 >>= 1;
1218 shift--;
1219 }
1220
1221 tps32 = (uint32_t)tps64;
50933623
JK		 1222 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1223 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1224 scaled64 >>= 1;
1225 else
1226 tps32 <<= 1;
50d0a0f9
GH		 1227 shift++;
1228 }
1229
5f4e3f88
ZA		 1230 *pshift = shift;
1231 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1232
5f4e3f88
ZA		 1233 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1234 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1235}
1236
d828199e 1237#ifdef CONFIG_X86_64
16e8d74d 1238static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1239#endif
16e8d74d 1240
c8076604 1241static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1242static unsigned long max_tsc_khz;
c8076604 1243
cc578287 1244static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1245{
cc578287
ZA		 1246 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1247 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1248}
1249
cc578287 1250static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1251{
cc578287
ZA		 1252 u64 v = (u64)khz * (1000000 + ppm);
1253 do_div(v, 1000000);
1254 return v;
1e993611
JR		 1255}
1256
381d585c
HZ		 1257static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1258{
1259 u64 ratio;
1260
1261 /* Guest TSC same frequency as host TSC? */
1262 if (!scale) {
1263 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1264 return 0;
1265 }
1266
1267 /* TSC scaling supported? */
1268 if (!kvm_has_tsc_control) {
1269 if (user_tsc_khz > tsc_khz) {
1270 vcpu->arch.tsc_catchup = 1;
1271 vcpu->arch.tsc_always_catchup = 1;
1272 return 0;
1273 } else {
1274 WARN(1, "user requested TSC rate below hardware speed\n");
1275 return -1;
1276 }
1277 }
1278
1279 /* TSC scaling required - calculate ratio */
1280 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1281 user_tsc_khz, tsc_khz);
1282
1283 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1284 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1285 user_tsc_khz);
1286 return -1;
1287 }
1288
1289 vcpu->arch.tsc_scaling_ratio = ratio;
1290 return 0;
1291}
1292
1293static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1294{
cc578287
ZA		 1295 u32 thresh_lo, thresh_hi;
1296 int use_scaling = 0;
217fc9cf 1297
03ba32ca 1298 /* tsc_khz can be zero if TSC calibration fails */
ad721883
HZ		 1299 if (this_tsc_khz == 0) {
1300 /* set tsc_scaling_ratio to a safe value */
1301 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1302 return -1;
ad721883 1303 }
03ba32ca 1304
c285545f
ZA		 1305 /* Compute a scale to convert nanoseconds in TSC cycles */
1306 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1307 &vcpu->arch.virtual_tsc_shift,
1308 &vcpu->arch.virtual_tsc_mult);
1309 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1310
1311 /*
1312 * Compute the variation in TSC rate which is acceptable
1313 * within the range of tolerance and decide if the
1314 * rate being applied is within that bounds of the hardware
1315 * rate. If so, no scaling or compensation need be done.
1316 */
1317 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1318 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1319 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1320 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1321 use_scaling = 1;
1322 }
381d585c 1323 return set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1324}
1325
1326static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1327{
e26101b1 1328 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1329 vcpu->arch.virtual_tsc_mult,
1330 vcpu->arch.virtual_tsc_shift);
e26101b1 1331 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1332 return tsc;
1333}
1334
69b0049a 1335static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1336{
1337#ifdef CONFIG_X86_64
1338 bool vcpus_matched;
b48aa97e
MT		 1339 struct kvm_arch *ka = &vcpu->kvm->arch;
1340 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1341
1342 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1343 atomic_read(&vcpu->kvm->online_vcpus));
1344
7f187922
MT		 1345 /*
1346 * Once the masterclock is enabled, always perform request in
1347 * order to update it.
1348 *
1349 * In order to enable masterclock, the host clocksource must be TSC
1350 * and the vcpus need to have matched TSCs. When that happens,
1351 * perform request to enable masterclock.
1352 */
1353 if (ka->use_master_clock ||
1354 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1355 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1356
1357 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1358 atomic_read(&vcpu->kvm->online_vcpus),
1359 ka->use_master_clock, gtod->clock.vclock_mode);
1360#endif
1361}
1362
ba904635
WA		 1363static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1364{
1365 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1366 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1367}
1368
35181e86
HZ		 1369/*
1370 * Multiply tsc by a fixed point number represented by ratio.
1371 *
1372 * The most significant 64-N bits (mult) of ratio represent the
1373 * integral part of the fixed point number; the remaining N bits
1374 * (frac) represent the fractional part, ie. ratio represents a fixed
1375 * point number (mult + frac * 2^(-N)).
1376 *
1377 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1378 */
1379static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1380{
1381 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1382}
1383
1384u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1385{
1386 u64 _tsc = tsc;
1387 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1388
1389 if (ratio != kvm_default_tsc_scaling_ratio)
1390 _tsc = __scale_tsc(ratio, tsc);
1391
1392 return _tsc;
1393}
1394EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1395
07c1419a
HZ		 1396static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1397{
1398 u64 tsc;
1399
1400 tsc = kvm_scale_tsc(vcpu, rdtsc());
1401
1402 return target_tsc - tsc;
1403}
1404
4ba76538
HZ		 1405u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1406{
1407 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1408}
1409EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1410
8fe8ab46 1411void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1412{
1413 struct kvm *kvm = vcpu->kvm;
f38e098f 1414 u64 offset, ns, elapsed;
99e3e30a 1415 unsigned long flags;
02626b6a 1416 s64 usdiff;
b48aa97e 1417 bool matched;
0d3da0d2 1418 bool already_matched;
8fe8ab46 1419 u64 data = msr->data;
99e3e30a 1420
038f8c11 1421 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1422 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1423 ns = get_kernel_ns();
f38e098f 1424 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1425
03ba32ca 1426 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1427 int faulted = 0;
1428
03ba32ca
MT		 1429 /* n.b - signed multiplication and division required */
1430 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1431#ifdef CONFIG_X86_64
03ba32ca 1432 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1433#else
03ba32ca 1434 /* do_div() only does unsigned */
8915aa27
MT		 1435 asm("1: idivl %[divisor]\n"
1436 "2: xor %%edx, %%edx\n"
1437 " movl $0, %[faulted]\n"
1438 "3:\n"
1439 ".section .fixup,\"ax\"\n"
1440 "4: movl $1, %[faulted]\n"
1441 " jmp 3b\n"
1442 ".previous\n"
1443
1444 _ASM_EXTABLE(1b, 4b)
1445
1446 : "=A"(usdiff), [faulted] "=r" (faulted)
1447 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1448
5d3cb0f6 1449#endif
03ba32ca
MT		 1450 do_div(elapsed, 1000);
1451 usdiff -= elapsed;
1452 if (usdiff < 0)
1453 usdiff = -usdiff;
8915aa27
MT		 1454
1455 /* idivl overflow => difference is larger than USEC_PER_SEC */
1456 if (faulted)
1457 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1458 } else
1459 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1460
1461 /*
5d3cb0f6
ZA		 1462 * Special case: TSC write with a small delta (1 second) of virtual
1463 * cycle time against real time is interpreted as an attempt to
1464 * synchronize the CPU.
1465 *
1466 * For a reliable TSC, we can match TSC offsets, and for an unstable
1467 * TSC, we add elapsed time in this computation. We could let the
1468 * compensation code attempt to catch up if we fall behind, but
1469 * it's better to try to match offsets from the beginning.
1470 */
02626b6a 1471 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1472 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1473 if (!check_tsc_unstable()) {
e26101b1 1474 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1475 pr_debug("kvm: matched tsc offset for %llu\n", data);
1476 } else {
857e4099 1477 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1478 data += delta;
07c1419a 1479 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1480 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1481 }
b48aa97e 1482 matched = true;
0d3da0d2 1483 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1484 } else {
1485 /*
1486 * We split periods of matched TSC writes into generations.
1487 * For each generation, we track the original measured
1488 * nanosecond time, offset, and write, so if TSCs are in
1489 * sync, we can match exact offset, and if not, we can match
4a969980 1490 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1491 *
1492 * These values are tracked in kvm->arch.cur_xxx variables.
1493 */
1494 kvm->arch.cur_tsc_generation++;
1495 kvm->arch.cur_tsc_nsec = ns;
1496 kvm->arch.cur_tsc_write = data;
1497 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1498 matched = false;
0d3da0d2 1499 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1500 kvm->arch.cur_tsc_generation, data);
f38e098f 1501 }
e26101b1
ZA		 1502
1503 /*
1504 * We also track th most recent recorded KHZ, write and time to
1505 * allow the matching interval to be extended at each write.
1506 */
f38e098f
ZA		 1507 kvm->arch.last_tsc_nsec = ns;
1508 kvm->arch.last_tsc_write = data;
5d3cb0f6 1509 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1510
b183aa58 1511 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1512
1513 /* Keep track of which generation this VCPU has synchronized to */
1514 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1515 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1516 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1517
ba904635
WA		 1518 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1519 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1520 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1521 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1522
1523 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1524 if (!matched) {
b48aa97e 1525 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1526 } else if (!already_matched) {
1527 kvm->arch.nr_vcpus_matched_tsc++;
1528 }
b48aa97e
MT		 1529
1530 kvm_track_tsc_matching(vcpu);
1531 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1532}
e26101b1 1533
99e3e30a
ZA		 1534EXPORT_SYMBOL_GPL(kvm_write_tsc);
1535
58ea6767
HZ		 1536static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1537 s64 adjustment)
1538{
1539 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1540}
1541
1542static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1543{
1544 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1545 WARN_ON(adjustment < 0);
1546 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1547 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1548}
1549
d828199e
MT		 1550#ifdef CONFIG_X86_64
1551
1552static cycle_t read_tsc(void)
1553{
03b9730b
AL		 1554 cycle_t ret = (cycle_t)rdtsc_ordered();
1555 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1556
1557 if (likely(ret >= last))
1558 return ret;
1559
1560 /*
1561 * GCC likes to generate cmov here, but this branch is extremely
1562 * predictable (it's just a funciton of time and the likely is
1563 * very likely) and there's a data dependence, so force GCC
1564 * to generate a branch instead. I don't barrier() because
1565 * we don't actually need a barrier, and if this function
1566 * ever gets inlined it will generate worse code.
1567 */
1568 asm volatile ("");
1569 return last;
1570}
1571
1572static inline u64 vgettsc(cycle_t *cycle_now)
1573{
1574 long v;
1575 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1576
1577 *cycle_now = read_tsc();
1578
1579 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1580 return v * gtod->clock.mult;
1581}
1582
cbcf2dd3 1583static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1584{
cbcf2dd3 1585 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1586 unsigned long seq;
d828199e 1587 int mode;
cbcf2dd3 1588 u64 ns;
d828199e 1589
d828199e
MT		 1590 do {
1591 seq = read_seqcount_begin(&gtod->seq);
1592 mode = gtod->clock.vclock_mode;
cbcf2dd3 1593 ns = gtod->nsec_base;
d828199e
MT		 1594 ns += vgettsc(cycle_now);
1595 ns >>= gtod->clock.shift;
cbcf2dd3 1596 ns += gtod->boot_ns;
d828199e 1597 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1598 *t = ns;
d828199e
MT		 1599
1600 return mode;
1601}
1602
1603/* returns true if host is using tsc clocksource */
1604static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1605{
d828199e
MT		 1606 /* checked again under seqlock below */
1607 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1608 return false;
1609
cbcf2dd3 1610 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1611}
1612#endif
1613
1614/*
1615 *
b48aa97e
MT		 1616 * Assuming a stable TSC across physical CPUS, and a stable TSC
1617 * across virtual CPUs, the following condition is possible.
1618 * Each numbered line represents an event visible to both
d828199e
MT		 1619 * CPUs at the next numbered event.
1620 *
1621 * "timespecX" represents host monotonic time. "tscX" represents
1622 * RDTSC value.
1623 *
1624 * VCPU0 on CPU0 | VCPU1 on CPU1
1625 *
1626 * 1. read timespec0,tsc0
1627 * 2. | timespec1 = timespec0 + N
1628 * | tsc1 = tsc0 + M
1629 * 3. transition to guest | transition to guest
1630 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1631 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1632 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1633 *
1634 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1635 *
1636 * - ret0 < ret1
1637 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1638 * ...
1639 * - 0 < N - M => M < N
1640 *
1641 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1642 * always the case (the difference between two distinct xtime instances
1643 * might be smaller then the difference between corresponding TSC reads,
1644 * when updating guest vcpus pvclock areas).
1645 *
1646 * To avoid that problem, do not allow visibility of distinct
1647 * system_timestamp/tsc_timestamp values simultaneously: use a master
1648 * copy of host monotonic time values. Update that master copy
1649 * in lockstep.
1650 *
b48aa97e 1651 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1652 *
1653 */
1654
1655static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1656{
1657#ifdef CONFIG_X86_64
1658 struct kvm_arch *ka = &kvm->arch;
1659 int vclock_mode;
b48aa97e
MT		 1660 bool host_tsc_clocksource, vcpus_matched;
1661
1662 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1663 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1664
1665 /*
1666 * If the host uses TSC clock, then passthrough TSC as stable
1667 * to the guest.
1668 */
b48aa97e 1669 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1670 &ka->master_kernel_ns,
1671 &ka->master_cycle_now);
1672
16a96021 1673 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1674 && !backwards_tsc_observed
1675 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1676
d828199e
MT		 1677 if (ka->use_master_clock)
1678 atomic_set(&kvm_guest_has_master_clock, 1);
1679
1680 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1681 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1682 vcpus_matched);
d828199e
MT		 1683#endif
1684}
1685
2e762ff7
MT		 1686static void kvm_gen_update_masterclock(struct kvm *kvm)
1687{
1688#ifdef CONFIG_X86_64
1689 int i;
1690 struct kvm_vcpu *vcpu;
1691 struct kvm_arch *ka = &kvm->arch;
1692
1693 spin_lock(&ka->pvclock_gtod_sync_lock);
1694 kvm_make_mclock_inprogress_request(kvm);
1695 /* no guest entries from this point */
1696 pvclock_update_vm_gtod_copy(kvm);
1697
1698 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1699 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1700
1701 /* guest entries allowed */
1702 kvm_for_each_vcpu(i, vcpu, kvm)
1703 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1704
1705 spin_unlock(&ka->pvclock_gtod_sync_lock);
1706#endif
1707}
1708
34c238a1 1709static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1710{
27cca94e 1711 unsigned long flags, this_tsc_khz, tgt_tsc_khz;
18068523 1712 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1713 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1714 s64 kernel_ns;
d828199e 1715 u64 tsc_timestamp, host_tsc;
0b79459b 1716 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1717 u8 pvclock_flags;
d828199e
MT		 1718 bool use_master_clock;
1719
1720 kernel_ns = 0;
1721 host_tsc = 0;
18068523 1722
d828199e
MT		 1723 /*
1724 * If the host uses TSC clock, then passthrough TSC as stable
1725 * to the guest.
1726 */
1727 spin_lock(&ka->pvclock_gtod_sync_lock);
1728 use_master_clock = ka->use_master_clock;
1729 if (use_master_clock) {
1730 host_tsc = ka->master_cycle_now;
1731 kernel_ns = ka->master_kernel_ns;
1732 }
1733 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1734
1735 /* Keep irq disabled to prevent changes to the clock */
1736 local_irq_save(flags);
89cbc767 1737 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1738 if (unlikely(this_tsc_khz == 0)) {
1739 local_irq_restore(flags);
1740 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1741 return 1;
1742 }
d828199e 1743 if (!use_master_clock) {
4ea1636b 1744 host_tsc = rdtsc();
d828199e
MT		 1745 kernel_ns = get_kernel_ns();
1746 }
1747
4ba76538 1748 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1749
c285545f
ZA		 1750 /*
1751 * We may have to catch up the TSC to match elapsed wall clock
1752 * time for two reasons, even if kvmclock is used.
1753 * 1) CPU could have been running below the maximum TSC rate
1754 * 2) Broken TSC compensation resets the base at each VCPU
1755 * entry to avoid unknown leaps of TSC even when running
1756 * again on the same CPU. This may cause apparent elapsed
1757 * time to disappear, and the guest to stand still or run
1758 * very slowly.
1759 */
1760 if (vcpu->tsc_catchup) {
1761 u64 tsc = compute_guest_tsc(v, kernel_ns);
1762 if (tsc > tsc_timestamp) {
f1e2b260 1763 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1764 tsc_timestamp = tsc;
1765 }
50d0a0f9
GH		 1766 }
1767
18068523
GOC		 1768 local_irq_restore(flags);
1769
0b79459b 1770 if (!vcpu->pv_time_enabled)
c285545f 1771 return 0;
18068523 1772
e48672fa 1773 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
27cca94e
HZ		 1774 tgt_tsc_khz = kvm_has_tsc_control ?
1775 vcpu->virtual_tsc_khz : this_tsc_khz;
1776 kvm_get_time_scale(NSEC_PER_SEC / 1000, tgt_tsc_khz,
5f4e3f88
ZA		 1777 &vcpu->hv_clock.tsc_shift,
1778 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1779 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1780 }
1781
1782 /* With all the info we got, fill in the values */
1d5f066e 1783 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1784 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1785 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1786
09a0c3f1
OH		 1787 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1788 &guest_hv_clock, sizeof(guest_hv_clock))))
1789 return 0;
1790
5dca0d91
RK		 1791 /* This VCPU is paused, but it's legal for a guest to read another
1792 * VCPU's kvmclock, so we really have to follow the specification where
1793 * it says that version is odd if data is being modified, and even after
1794 * it is consistent.
1795 *
1796 * Version field updates must be kept separate. This is because
1797 * kvm_write_guest_cached might use a "rep movs" instruction, and
1798 * writes within a string instruction are weakly ordered. So there
1799 * are three writes overall.
1800 *
1801 * As a small optimization, only write the version field in the first
1802 * and third write. The vcpu->pv_time cache is still valid, because the
1803 * version field is the first in the struct.
18068523 1804 */
5dca0d91
RK		 1805 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1806
1807 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1808 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1809 &vcpu->hv_clock,
1810 sizeof(vcpu->hv_clock.version));
1811
1812 smp_wmb();
78c0337a
MT		 1813
1814 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1815 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1816
1817 if (vcpu->pvclock_set_guest_stopped_request) {
1818 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1819 vcpu->pvclock_set_guest_stopped_request = false;
1820 }
1821
d828199e
MT		 1822 /* If the host uses TSC clocksource, then it is stable */
1823 if (use_master_clock)
1824 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1825
78c0337a
MT		 1826 vcpu->hv_clock.flags = pvclock_flags;
1827
ce1a5e60
DM		 1828 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1829
0b79459b
AH		 1830 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1831 &vcpu->hv_clock,
1832 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1833
1834 smp_wmb();
1835
1836 vcpu->hv_clock.version++;
1837 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1838 &vcpu->hv_clock,
1839 sizeof(vcpu->hv_clock.version));
8cfdc000 1840 return 0;
c8076604
GH		 1841}
1842
0061d53d
MT		 1843/*
1844 * kvmclock updates which are isolated to a given vcpu, such as
1845 * vcpu->cpu migration, should not allow system_timestamp from
1846 * the rest of the vcpus to remain static. Otherwise ntp frequency
1847 * correction applies to one vcpu's system_timestamp but not
1848 * the others.
1849 *
1850 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1851 * We need to rate-limit these requests though, as they can
1852 * considerably slow guests that have a large number of vcpus.
1853 * The time for a remote vcpu to update its kvmclock is bound
1854 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1855 */
1856
7e44e449
AJ		 1857#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1858
1859static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1860{
1861 int i;
7e44e449
AJ		 1862 struct delayed_work *dwork = to_delayed_work(work);
1863 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1864 kvmclock_update_work);
1865 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1866 struct kvm_vcpu *vcpu;
1867
1868 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1869 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1870 kvm_vcpu_kick(vcpu);
1871 }
1872}
1873
7e44e449
AJ		 1874static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1875{
1876 struct kvm *kvm = v->kvm;
1877
105b21bb 1878 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1879 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1880 KVMCLOCK_UPDATE_DELAY);
1881}
1882
332967a3
AJ		 1883#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1884
1885static void kvmclock_sync_fn(struct work_struct *work)
1886{
1887 struct delayed_work *dwork = to_delayed_work(work);
1888 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1889 kvmclock_sync_work);
1890 struct kvm *kvm = container_of(ka, struct kvm, arch);
1891
630994b3
MT		 1892 if (!kvmclock_periodic_sync)
1893 return;
1894
332967a3
AJ		 1895 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1896 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1897 KVMCLOCK_SYNC_PERIOD);
1898}
1899
890ca9ae 1900static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1901{
890ca9ae
HY		 1902 u64 mcg_cap = vcpu->arch.mcg_cap;
1903 unsigned bank_num = mcg_cap & 0xff;
1904
15c4a640 1905 switch (msr) {
15c4a640 1906 case MSR_IA32_MCG_STATUS:
890ca9ae 1907 vcpu->arch.mcg_status = data;
15c4a640 1908 break;
c7ac679c 1909 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1910 if (!(mcg_cap & MCG_CTL_P))
1911 return 1;
1912 if (data != 0 && data != ~(u64)0)
1913 return -1;
1914 vcpu->arch.mcg_ctl = data;
1915 break;
1916 default:
1917 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1918 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1919 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1920 /* only 0 or all 1s can be written to IA32_MCi_CTL
1921 * some Linux kernels though clear bit 10 in bank 4 to
1922 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1923 * this to avoid an uncatched #GP in the guest
1924 */
890ca9ae 1925 if ((offset & 0x3) == 0 &&
114be429 1926 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1927 return -1;
1928 vcpu->arch.mce_banks[offset] = data;
1929 break;
1930 }
1931 return 1;
1932 }
1933 return 0;
1934}
1935
ffde22ac
ES		 1936static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1937{
1938 struct kvm *kvm = vcpu->kvm;
1939 int lm = is_long_mode(vcpu);
1940 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1941 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1942 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1943 : kvm->arch.xen_hvm_config.blob_size_32;
1944 u32 page_num = data & ~PAGE_MASK;
1945 u64 page_addr = data & PAGE_MASK;
1946 u8 *page;
1947 int r;
1948
1949 r = -E2BIG;
1950 if (page_num >= blob_size)
1951 goto out;
1952 r = -ENOMEM;
ff5c2c03
SL		 1953 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1954 if (IS_ERR(page)) {
1955 r = PTR_ERR(page);
ffde22ac 1956 goto out;
ff5c2c03 1957 }
54bf36aa 1958 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1959 goto out_free;
1960 r = 0;
1961out_free:
1962 kfree(page);
1963out:
1964 return r;
1965}
1966
344d9588
GN		 1967static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1968{
1969 gpa_t gpa = data & ~0x3f;
1970
4a969980 1971 /* Bits 2:5 are reserved, Should be zero */
6adba527 1972 if (data & 0x3c)
344d9588
GN		 1973 return 1;
1974
1975 vcpu->arch.apf.msr_val = data;
1976
1977 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1978 kvm_clear_async_pf_completion_queue(vcpu);
1979 kvm_async_pf_hash_reset(vcpu);
1980 return 0;
1981 }
1982
8f964525
AH		 1983 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1984 sizeof(u32)))
344d9588
GN		 1985 return 1;
1986
6adba527 1987 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1988 kvm_async_pf_wakeup_all(vcpu);
1989 return 0;
1990}
1991
12f9a48f
GC		 1992static void kvmclock_reset(struct kvm_vcpu *vcpu)
1993{
0b79459b 1994 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1995}
1996
c9aaa895
GC		 1997static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1998{
1999 u64 delta;
2000
2001 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2002 return;
2003
2004 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2005 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2006 vcpu->arch.st.accum_steal = delta;
2007}
2008
2009static void record_steal_time(struct kvm_vcpu *vcpu)
2010{
7cae2bed
MT		 2011 accumulate_steal_time(vcpu);
2012
c9aaa895
GC		 2013 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2014 return;
2015
2016 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2017 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2018 return;
2019
2020 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2021 vcpu->arch.st.steal.version += 2;
2022 vcpu->arch.st.accum_steal = 0;
2023
2024 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2025 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2026}
2027
8fe8ab46 2028int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2029{
5753785f 2030 bool pr = false;
8fe8ab46
WA		 2031 u32 msr = msr_info->index;
2032 u64 data = msr_info->data;
5753785f 2033
15c4a640 2034 switch (msr) {
2e32b719
BP		 2035 case MSR_AMD64_NB_CFG:
2036 case MSR_IA32_UCODE_REV:
2037 case MSR_IA32_UCODE_WRITE:
2038 case MSR_VM_HSAVE_PA:
2039 case MSR_AMD64_PATCH_LOADER:
2040 case MSR_AMD64_BU_CFG2:
2041 break;
2042
15c4a640 2043 case MSR_EFER:
b69e8cae 2044 return set_efer(vcpu, data);
8f1589d9
AP		 2045 case MSR_K7_HWCR:
2046 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2047 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2048 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2049 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2050 if (data != 0) {
a737f256
CD		 2051 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2052 data);
8f1589d9
AP		 2053 return 1;
2054 }
15c4a640 2055 break;
f7c6d140
AP		 2056 case MSR_FAM10H_MMIO_CONF_BASE:
2057 if (data != 0) {
a737f256
CD		 2058 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2059 "0x%llx\n", data);
f7c6d140
AP		 2060 return 1;
2061 }
15c4a640 2062 break;
b5e2fec0
AG		 2063 case MSR_IA32_DEBUGCTLMSR:
2064 if (!data) {
2065 /* We support the non-activated case already */
2066 break;
2067 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2068 /* Values other than LBR and BTF are vendor-specific,
2069 thus reserved and should throw a #GP */
2070 return 1;
2071 }
a737f256
CD		 2072 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2073 __func__, data);
b5e2fec0 2074 break;
9ba075a6 2075 case 0x200 ... 0x2ff:
ff53604b 2076 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2077 case MSR_IA32_APICBASE:
58cb628d 2078 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2079 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2080 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2081 case MSR_IA32_TSCDEADLINE:
2082 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2083 break;
ba904635
WA		 2084 case MSR_IA32_TSC_ADJUST:
2085 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2086 if (!msr_info->host_initiated) {
d913b904 2087 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2088 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2089 }
2090 vcpu->arch.ia32_tsc_adjust_msr = data;
2091 }
2092 break;
15c4a640 2093 case MSR_IA32_MISC_ENABLE:
ad312c7c 2094 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2095 break;
64d60670
PB		 2096 case MSR_IA32_SMBASE:
2097 if (!msr_info->host_initiated)
2098 return 1;
2099 vcpu->arch.smbase = data;
2100 break;
11c6bffa 2101 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2102 case MSR_KVM_WALL_CLOCK:
2103 vcpu->kvm->arch.wall_clock = data;
2104 kvm_write_wall_clock(vcpu->kvm, data);
2105 break;
11c6bffa 2106 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2107 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2108 u64 gpa_offset;
54750f2c
MT		 2109 struct kvm_arch *ka = &vcpu->kvm->arch;
2110
12f9a48f 2111 kvmclock_reset(vcpu);
18068523 2112
54750f2c
MT		 2113 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2114 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2115
2116 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2117 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2118 &vcpu->requests);
2119
2120 ka->boot_vcpu_runs_old_kvmclock = tmp;
2121 }
2122
18068523 2123 vcpu->arch.time = data;
0061d53d 2124 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2125
2126 /* we verify if the enable bit is set... */
2127 if (!(data & 1))
2128 break;
2129
0b79459b 2130 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2131
0b79459b 2132 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2133 &vcpu->arch.pv_time, data & ~1ULL,
2134 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2135 vcpu->arch.pv_time_enabled = false;
2136 else
2137 vcpu->arch.pv_time_enabled = true;
32cad84f 2138
18068523
GOC		 2139 break;
2140 }
344d9588
GN		 2141 case MSR_KVM_ASYNC_PF_EN:
2142 if (kvm_pv_enable_async_pf(vcpu, data))
2143 return 1;
2144 break;
c9aaa895
GC		 2145 case MSR_KVM_STEAL_TIME:
2146
2147 if (unlikely(!sched_info_on()))
2148 return 1;
2149
2150 if (data & KVM_STEAL_RESERVED_MASK)
2151 return 1;
2152
2153 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2154 data & KVM_STEAL_VALID_BITS,
2155 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2156 return 1;
2157
2158 vcpu->arch.st.msr_val = data;
2159
2160 if (!(data & KVM_MSR_ENABLED))
2161 break;
2162
c9aaa895
GC		 2163 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2164
2165 break;
ae7a2a3f
MT		 2166 case MSR_KVM_PV_EOI_EN:
2167 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2168 return 1;
2169 break;
c9aaa895 2170
890ca9ae
HY		 2171 case MSR_IA32_MCG_CTL:
2172 case MSR_IA32_MCG_STATUS:
81760dcc 2173 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2174 return set_msr_mce(vcpu, msr, data);
71db6023 2175
6912ac32
WH		 2176 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2177 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2178 pr = true; /* fall through */
2179 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2180 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2181 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2182 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2183
2184 if (pr || data != 0)
a737f256
CD		 2185 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2186 "0x%x data 0x%llx\n", msr, data);
5753785f 2187 break;
84e0cefa
JS		 2188 case MSR_K7_CLK_CTL:
2189 /*
2190 * Ignore all writes to this no longer documented MSR.
2191 * Writes are only relevant for old K7 processors,
2192 * all pre-dating SVM, but a recommended workaround from
4a969980 2193 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2194 * affected processor models on the command line, hence
2195 * the need to ignore the workaround.
2196 */
2197 break;
55cd8e5a 2198 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2199 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2200 case HV_X64_MSR_CRASH_CTL:
2201 return kvm_hv_set_msr_common(vcpu, msr, data,
2202 msr_info->host_initiated);
91c9c3ed 2203 case MSR_IA32_BBL_CR_CTL3:
2204 /* Drop writes to this legacy MSR -- see rdmsr
2205 * counterpart for further detail.
2206 */
a737f256 2207 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2208 break;
2b036c6b
BO		 2209 case MSR_AMD64_OSVW_ID_LENGTH:
2210 if (!guest_cpuid_has_osvw(vcpu))
2211 return 1;
2212 vcpu->arch.osvw.length = data;
2213 break;
2214 case MSR_AMD64_OSVW_STATUS:
2215 if (!guest_cpuid_has_osvw(vcpu))
2216 return 1;
2217 vcpu->arch.osvw.status = data;
2218 break;
15c4a640 2219 default:
ffde22ac
ES		 2220 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2221 return xen_hvm_config(vcpu, data);
c6702c9d 2222 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2223 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2224 if (!ignore_msrs) {
a737f256
CD		 2225 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2226 msr, data);
ed85c068
AP		 2227 return 1;
2228 } else {
a737f256
CD		 2229 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2230 msr, data);
ed85c068
AP		 2231 break;
2232 }
15c4a640
CO		 2233 }
2234 return 0;
2235}
2236EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2237
2238
2239/*
2240 * Reads an msr value (of 'msr_index') into 'pdata'.
2241 * Returns 0 on success, non-0 otherwise.
2242 * Assumes vcpu_load() was already called.
2243 */
609e36d3 2244int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2245{
609e36d3 2246 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2247}
ff651cb6 2248EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2249
890ca9ae 2250static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2251{
2252 u64 data;
890ca9ae
HY		 2253 u64 mcg_cap = vcpu->arch.mcg_cap;
2254 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2255
2256 switch (msr) {
15c4a640
CO		 2257 case MSR_IA32_P5_MC_ADDR:
2258 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2259 data = 0;
2260 break;
15c4a640 2261 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2262 data = vcpu->arch.mcg_cap;
2263 break;
c7ac679c 2264 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2265 if (!(mcg_cap & MCG_CTL_P))
2266 return 1;
2267 data = vcpu->arch.mcg_ctl;
2268 break;
2269 case MSR_IA32_MCG_STATUS:
2270 data = vcpu->arch.mcg_status;
2271 break;
2272 default:
2273 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2274 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2275 u32 offset = msr - MSR_IA32_MC0_CTL;
2276 data = vcpu->arch.mce_banks[offset];
2277 break;
2278 }
2279 return 1;
2280 }
2281 *pdata = data;
2282 return 0;
2283}
2284
609e36d3 2285int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2286{
609e36d3 2287 switch (msr_info->index) {
890ca9ae 2288 case MSR_IA32_PLATFORM_ID:
15c4a640 2289 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2290 case MSR_IA32_DEBUGCTLMSR:
2291 case MSR_IA32_LASTBRANCHFROMIP:
2292 case MSR_IA32_LASTBRANCHTOIP:
2293 case MSR_IA32_LASTINTFROMIP:
2294 case MSR_IA32_LASTINTTOIP:
60af2ecd 2295 case MSR_K8_SYSCFG:
3afb1121
PB		 2296 case MSR_K8_TSEG_ADDR:
2297 case MSR_K8_TSEG_MASK:
60af2ecd 2298 case MSR_K7_HWCR:
61a6bd67 2299 case MSR_VM_HSAVE_PA:
1fdbd48c 2300 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2301 case MSR_AMD64_NB_CFG:
f7c6d140 2302 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2303 case MSR_AMD64_BU_CFG2:
609e36d3 2304 msr_info->data = 0;
15c4a640 2305 break;
6912ac32
WH		 2306 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2307 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2308 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2309 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2310 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2311 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2312 msr_info->data = 0;
5753785f 2313 break;
742bc670 2314 case MSR_IA32_UCODE_REV:
609e36d3 2315 msr_info->data = 0x100000000ULL;
742bc670 2316 break;
9ba075a6 2317 case MSR_MTRRcap:
9ba075a6 2318 case 0x200 ... 0x2ff:
ff53604b 2319 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2320 case 0xcd: /* fsb frequency */
609e36d3 2321 msr_info->data = 3;
15c4a640 2322 break;
7b914098
JS		 2323 /*
2324 * MSR_EBC_FREQUENCY_ID
2325 * Conservative value valid for even the basic CPU models.
2326 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2327 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2328 * and 266MHz for model 3, or 4. Set Core Clock
2329 * Frequency to System Bus Frequency Ratio to 1 (bits
2330 * 31:24) even though these are only valid for CPU
2331 * models > 2, however guests may end up dividing or
2332 * multiplying by zero otherwise.
2333 */
2334 case MSR_EBC_FREQUENCY_ID:
609e36d3 2335 msr_info->data = 1 << 24;
7b914098 2336 break;
15c4a640 2337 case MSR_IA32_APICBASE:
609e36d3 2338 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2339 break;
0105d1a5 2340 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2341 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2342 break;
a3e06bbe 2343 case MSR_IA32_TSCDEADLINE:
609e36d3 2344 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2345 break;
ba904635 2346 case MSR_IA32_TSC_ADJUST:
609e36d3 2347 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2348 break;
15c4a640 2349 case MSR_IA32_MISC_ENABLE:
609e36d3 2350 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2351 break;
64d60670
PB		 2352 case MSR_IA32_SMBASE:
2353 if (!msr_info->host_initiated)
2354 return 1;
2355 msr_info->data = vcpu->arch.smbase;
15c4a640 2356 break;
847f0ad8
AG		 2357 case MSR_IA32_PERF_STATUS:
2358 /* TSC increment by tick */
609e36d3 2359 msr_info->data = 1000ULL;
847f0ad8 2360 /* CPU multiplier */
b0996ae4 2361 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2362 break;
15c4a640 2363 case MSR_EFER:
609e36d3 2364 msr_info->data = vcpu->arch.efer;
15c4a640 2365 break;
18068523 2366 case MSR_KVM_WALL_CLOCK:
11c6bffa 2367 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2368 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2369 break;
2370 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2371 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2372 msr_info->data = vcpu->arch.time;
18068523 2373 break;
344d9588 2374 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2375 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2376 break;
c9aaa895 2377 case MSR_KVM_STEAL_TIME:
609e36d3 2378 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2379 break;
1d92128f 2380 case MSR_KVM_PV_EOI_EN:
609e36d3 2381 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2382 break;
890ca9ae
HY		 2383 case MSR_IA32_P5_MC_ADDR:
2384 case MSR_IA32_P5_MC_TYPE:
2385 case MSR_IA32_MCG_CAP:
2386 case MSR_IA32_MCG_CTL:
2387 case MSR_IA32_MCG_STATUS:
81760dcc 2388 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2389 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2390 case MSR_K7_CLK_CTL:
2391 /*
2392 * Provide expected ramp-up count for K7. All other
2393 * are set to zero, indicating minimum divisors for
2394 * every field.
2395 *
2396 * This prevents guest kernels on AMD host with CPU
2397 * type 6, model 8 and higher from exploding due to
2398 * the rdmsr failing.
2399 */
609e36d3 2400 msr_info->data = 0x20000000;
84e0cefa 2401 break;
55cd8e5a 2402 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2403 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2404 case HV_X64_MSR_CRASH_CTL:
e83d5887
AS		 2405 return kvm_hv_get_msr_common(vcpu,
2406 msr_info->index, &msr_info->data);
55cd8e5a 2407 break;
91c9c3ed 2408 case MSR_IA32_BBL_CR_CTL3:
2409 /* This legacy MSR exists but isn't fully documented in current
2410 * silicon. It is however accessed by winxp in very narrow
2411 * scenarios where it sets bit #19, itself documented as
2412 * a "reserved" bit. Best effort attempt to source coherent
2413 * read data here should the balance of the register be
2414 * interpreted by the guest:
2415 *
2416 * L2 cache control register 3: 64GB range, 256KB size,
2417 * enabled, latency 0x1, configured
2418 */
609e36d3 2419 msr_info->data = 0xbe702111;
91c9c3ed 2420 break;
2b036c6b
BO		 2421 case MSR_AMD64_OSVW_ID_LENGTH:
2422 if (!guest_cpuid_has_osvw(vcpu))
2423 return 1;
609e36d3 2424 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2425 break;
2426 case MSR_AMD64_OSVW_STATUS:
2427 if (!guest_cpuid_has_osvw(vcpu))
2428 return 1;
609e36d3 2429 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2430 break;
15c4a640 2431 default:
c6702c9d 2432 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2433 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2434 if (!ignore_msrs) {
609e36d3 2435 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2436 return 1;
2437 } else {
609e36d3
PB		 2438 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2439 msr_info->data = 0;
ed85c068
AP		 2440 }
2441 break;
15c4a640 2442 }
15c4a640
CO		 2443 return 0;
2444}
2445EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2446
313a3dc7
CO		 2447/*
2448 * Read or write a bunch of msrs. All parameters are kernel addresses.
2449 *
2450 * @return number of msrs set successfully.
2451 */
2452static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2453 struct kvm_msr_entry *entries,
2454 int (*do_msr)(struct kvm_vcpu *vcpu,
2455 unsigned index, u64 *data))
2456{
f656ce01 2457 int i, idx;
313a3dc7 2458
f656ce01 2459 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2460 for (i = 0; i < msrs->nmsrs; ++i)
2461 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2462 break;
f656ce01 2463 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2464
313a3dc7
CO		 2465 return i;
2466}
2467
2468/*
2469 * Read or write a bunch of msrs. Parameters are user addresses.
2470 *
2471 * @return number of msrs set successfully.
2472 */
2473static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2474 int (*do_msr)(struct kvm_vcpu *vcpu,
2475 unsigned index, u64 *data),
2476 int writeback)
2477{
2478 struct kvm_msrs msrs;
2479 struct kvm_msr_entry *entries;
2480 int r, n;
2481 unsigned size;
2482
2483 r = -EFAULT;
2484 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2485 goto out;
2486
2487 r = -E2BIG;
2488 if (msrs.nmsrs >= MAX_IO_MSRS)
2489 goto out;
2490
313a3dc7 2491 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2492 entries = memdup_user(user_msrs->entries, size);
2493 if (IS_ERR(entries)) {
2494 r = PTR_ERR(entries);
313a3dc7 2495 goto out;
ff5c2c03 2496 }
313a3dc7
CO		 2497
2498 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2499 if (r < 0)
2500 goto out_free;
2501
2502 r = -EFAULT;
2503 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2504 goto out_free;
2505
2506 r = n;
2507
2508out_free:
7a73c028 2509 kfree(entries);
313a3dc7
CO		 2510out:
2511 return r;
2512}
2513
784aa3d7 2514int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2515{
2516 int r;
2517
2518 switch (ext) {
2519 case KVM_CAP_IRQCHIP:
2520 case KVM_CAP_HLT:
2521 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2522 case KVM_CAP_SET_TSS_ADDR:
07716717 2523 case KVM_CAP_EXT_CPUID:
9c15bb1d 2524 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2525 case KVM_CAP_CLOCKSOURCE:
7837699f 2526 case KVM_CAP_PIT:
a28e4f5a 2527 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2528 case KVM_CAP_MP_STATE:
ed848624 2529 case KVM_CAP_SYNC_MMU:
a355c85c 2530 case KVM_CAP_USER_NMI:
52d939a0 2531 case KVM_CAP_REINJECT_CONTROL:
4925663a 2532 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2533 case KVM_CAP_IOEVENTFD:
f848a5a8 2534 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2535 case KVM_CAP_PIT2:
e9f42757 2536 case KVM_CAP_PIT_STATE2:
b927a3ce 2537 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2538 case KVM_CAP_XEN_HVM:
afbcf7ab 2539 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2540 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2541 case KVM_CAP_HYPERV:
10388a07 2542 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2543 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2544 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2545 case KVM_CAP_DEBUGREGS:
d2be1651 2546 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2547 case KVM_CAP_XSAVE:
344d9588 2548 case KVM_CAP_ASYNC_PF:
92a1f12d 2549 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2550 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2551 case KVM_CAP_READONLY_MEM:
5f66b620 2552 case KVM_CAP_HYPERV_TIME:
100943c5 2553 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2554 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2555 case KVM_CAP_ENABLE_CAP_VM:
2556 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2557 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2558 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2559#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2560 case KVM_CAP_ASSIGN_DEV_IRQ:
2561 case KVM_CAP_PCI_2_3:
2562#endif
018d00d2
ZX		 2563 r = 1;
2564 break;
6d396b55
PB		 2565 case KVM_CAP_X86_SMM:
2566 /* SMBASE is usually relocated above 1M on modern chipsets,
2567 * and SMM handlers might indeed rely on 4G segment limits,
2568 * so do not report SMM to be available if real mode is
2569 * emulated via vm86 mode. Still, do not go to great lengths
2570 * to avoid userspace's usage of the feature, because it is a
2571 * fringe case that is not enabled except via specific settings
2572 * of the module parameters.
2573 */
2574 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2575 break;
542472b5
LV		 2576 case KVM_CAP_COALESCED_MMIO:
2577 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2578 break;
774ead3a
AK		 2579 case KVM_CAP_VAPIC:
2580 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2581 break;
f725230a 2582 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2583 r = KVM_SOFT_MAX_VCPUS;
2584 break;
2585 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2586 r = KVM_MAX_VCPUS;
2587 break;
a988b910 2588 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2589 r = KVM_USER_MEM_SLOTS;
a988b910 2590 break;
a68a6a72
MT		 2591 case KVM_CAP_PV_MMU: /* obsolete */
2592 r = 0;
2f333bcb 2593 break;
4cee4b72 2594#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2595 case KVM_CAP_IOMMU:
a1b60c1c 2596 r = iommu_present(&pci_bus_type);
62c476c7 2597 break;
4cee4b72 2598#endif
890ca9ae
HY		 2599 case KVM_CAP_MCE:
2600 r = KVM_MAX_MCE_BANKS;
2601 break;
2d5b5a66
SY		 2602 case KVM_CAP_XCRS:
2603 r = cpu_has_xsave;
2604 break;
92a1f12d
JR		 2605 case KVM_CAP_TSC_CONTROL:
2606 r = kvm_has_tsc_control;
2607 break;
018d00d2
ZX		 2608 default:
2609 r = 0;
2610 break;
2611 }
2612 return r;
2613
2614}
2615
043405e1
CO		 2616long kvm_arch_dev_ioctl(struct file *filp,
2617 unsigned int ioctl, unsigned long arg)
2618{
2619 void __user *argp = (void __user *)arg;
2620 long r;
2621
2622 switch (ioctl) {
2623 case KVM_GET_MSR_INDEX_LIST: {
2624 struct kvm_msr_list __user *user_msr_list = argp;
2625 struct kvm_msr_list msr_list;
2626 unsigned n;
2627
2628 r = -EFAULT;
2629 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2630 goto out;
2631 n = msr_list.nmsrs;
62ef68bb 2632 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2633 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2634 goto out;
2635 r = -E2BIG;
e125e7b6 2636 if (n < msr_list.nmsrs)
043405e1
CO		 2637 goto out;
2638 r = -EFAULT;
2639 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2640 num_msrs_to_save * sizeof(u32)))
2641 goto out;
e125e7b6 2642 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2643 &emulated_msrs,
62ef68bb 2644 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2645 goto out;
2646 r = 0;
2647 break;
2648 }
9c15bb1d
BP		 2649 case KVM_GET_SUPPORTED_CPUID:
2650 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2651 struct kvm_cpuid2 __user *cpuid_arg = argp;
2652 struct kvm_cpuid2 cpuid;
2653
2654 r = -EFAULT;
2655 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2656 goto out;
9c15bb1d
BP		 2657
2658 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2659 ioctl);
674eea0f
AK		 2660 if (r)
2661 goto out;
2662
2663 r = -EFAULT;
2664 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2665 goto out;
2666 r = 0;
2667 break;
2668 }
890ca9ae
HY		 2669 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2670 u64 mce_cap;
2671
2672 mce_cap = KVM_MCE_CAP_SUPPORTED;
2673 r = -EFAULT;
2674 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2675 goto out;
2676 r = 0;
2677 break;
2678 }
043405e1
CO		 2679 default:
2680 r = -EINVAL;
2681 }
2682out:
2683 return r;
2684}
2685
f5f48ee1
SY		 2686static void wbinvd_ipi(void *garbage)
2687{
2688 wbinvd();
2689}
2690
2691static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2692{
e0f0bbc5 2693 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2694}
2695
313a3dc7
CO		 2696void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2697{
f5f48ee1
SY		 2698 /* Address WBINVD may be executed by guest */
2699 if (need_emulate_wbinvd(vcpu)) {
2700 if (kvm_x86_ops->has_wbinvd_exit())
2701 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2702 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2703 smp_call_function_single(vcpu->cpu,
2704 wbinvd_ipi, NULL, 1);
2705 }
2706
313a3dc7 2707 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2708
0dd6a6ed
ZA		 2709 /* Apply any externally detected TSC adjustments (due to suspend) */
2710 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2711 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2712 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2713 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2714 }
8f6055cb 2715
48434c20 2716 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2717 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2718 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2719 if (tsc_delta < 0)
2720 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2721 if (check_tsc_unstable()) {
07c1419a 2722 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2723 vcpu->arch.last_guest_tsc);
2724 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2725 vcpu->arch.tsc_catchup = 1;
c285545f 2726 }
d98d07ca
MT		 2727 /*
2728 * On a host with synchronized TSC, there is no need to update
2729 * kvmclock on vcpu->cpu migration
2730 */
2731 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2732 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2733 if (vcpu->cpu != cpu)
2734 kvm_migrate_timers(vcpu);
e48672fa 2735 vcpu->cpu = cpu;
6b7d7e76 2736 }
c9aaa895 2737
c9aaa895 2738 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2739}
2740
2741void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2742{
02daab21 2743 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2744 kvm_put_guest_fpu(vcpu);
4ea1636b 2745 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2746}
2747
313a3dc7
CO		 2748static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2749 struct kvm_lapic_state *s)
2750{
5a71785d 2751 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2752 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2753
2754 return 0;
2755}
2756
2757static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2758 struct kvm_lapic_state *s)
2759{
64eb0620 2760 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2761 update_cr8_intercept(vcpu);
313a3dc7
CO		 2762
2763 return 0;
2764}
2765
127a457a
MG		 2766static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2767{
2768 return (!lapic_in_kernel(vcpu) ||
2769 kvm_apic_accept_pic_intr(vcpu));
2770}
2771
782d422b
MG		 2772/*
2773 * if userspace requested an interrupt window, check that the
2774 * interrupt window is open.
2775 *
2776 * No need to exit to userspace if we already have an interrupt queued.
2777 */
2778static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2779{
2780 return kvm_arch_interrupt_allowed(vcpu) &&
2781 !kvm_cpu_has_interrupt(vcpu) &&
2782 !kvm_event_needs_reinjection(vcpu) &&
2783 kvm_cpu_accept_dm_intr(vcpu);
2784}
2785
f77bc6a4
ZX		 2786static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2787 struct kvm_interrupt *irq)
2788{
02cdb50f 2789 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2790 return -EINVAL;
1c1a9ce9
SR		 2791
2792 if (!irqchip_in_kernel(vcpu->kvm)) {
2793 kvm_queue_interrupt(vcpu, irq->irq, false);
2794 kvm_make_request(KVM_REQ_EVENT, vcpu);
2795 return 0;
2796 }
2797
2798 /*
2799 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2800 * fail for in-kernel 8259.
2801 */
2802 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2803 return -ENXIO;
f77bc6a4 2804
1c1a9ce9
SR		 2805 if (vcpu->arch.pending_external_vector != -1)
2806 return -EEXIST;
f77bc6a4 2807
1c1a9ce9 2808 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2809 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2810 return 0;
2811}
2812
c4abb7c9
JK		 2813static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2814{
c4abb7c9 2815 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2816
2817 return 0;
2818}
2819
f077825a
PB		 2820static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2821{
64d60670
PB		 2822 kvm_make_request(KVM_REQ_SMI, vcpu);
2823
f077825a
PB		 2824 return 0;
2825}
2826
b209749f
AK		 2827static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2828 struct kvm_tpr_access_ctl *tac)
2829{
2830 if (tac->flags)
2831 return -EINVAL;
2832 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2833 return 0;
2834}
2835
890ca9ae
HY		 2836static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2837 u64 mcg_cap)
2838{
2839 int r;
2840 unsigned bank_num = mcg_cap & 0xff, bank;
2841
2842 r = -EINVAL;
a9e38c3e 2843 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2844 goto out;
2845 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2846 goto out;
2847 r = 0;
2848 vcpu->arch.mcg_cap = mcg_cap;
2849 /* Init IA32_MCG_CTL to all 1s */
2850 if (mcg_cap & MCG_CTL_P)
2851 vcpu->arch.mcg_ctl = ~(u64)0;
2852 /* Init IA32_MCi_CTL to all 1s */
2853 for (bank = 0; bank < bank_num; bank++)
2854 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2855out:
2856 return r;
2857}
2858
2859static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2860 struct kvm_x86_mce *mce)
2861{
2862 u64 mcg_cap = vcpu->arch.mcg_cap;
2863 unsigned bank_num = mcg_cap & 0xff;
2864 u64 *banks = vcpu->arch.mce_banks;
2865
2866 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2867 return -EINVAL;
2868 /*
2869 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2870 * reporting is disabled
2871 */
2872 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2873 vcpu->arch.mcg_ctl != ~(u64)0)
2874 return 0;
2875 banks += 4 * mce->bank;
2876 /*
2877 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2878 * reporting is disabled for the bank
2879 */
2880 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2881 return 0;
2882 if (mce->status & MCI_STATUS_UC) {
2883 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2884 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2885 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2886 return 0;
2887 }
2888 if (banks[1] & MCI_STATUS_VAL)
2889 mce->status |= MCI_STATUS_OVER;
2890 banks[2] = mce->addr;
2891 banks[3] = mce->misc;
2892 vcpu->arch.mcg_status = mce->mcg_status;
2893 banks[1] = mce->status;
2894 kvm_queue_exception(vcpu, MC_VECTOR);
2895 } else if (!(banks[1] & MCI_STATUS_VAL)
2896 || !(banks[1] & MCI_STATUS_UC)) {
2897 if (banks[1] & MCI_STATUS_VAL)
2898 mce->status |= MCI_STATUS_OVER;
2899 banks[2] = mce->addr;
2900 banks[3] = mce->misc;
2901 banks[1] = mce->status;
2902 } else
2903 banks[1] |= MCI_STATUS_OVER;
2904 return 0;
2905}
2906
3cfc3092
JK		 2907static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2908 struct kvm_vcpu_events *events)
2909{
7460fb4a 2910 process_nmi(vcpu);
03b82a30
JK		 2911 events->exception.injected =
2912 vcpu->arch.exception.pending &&
2913 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2914 events->exception.nr = vcpu->arch.exception.nr;
2915 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2916 events->exception.pad = 0;
3cfc3092
JK		 2917 events->exception.error_code = vcpu->arch.exception.error_code;
2918
03b82a30
JK		 2919 events->interrupt.injected =
2920 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2921 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2922 events->interrupt.soft = 0;
37ccdcbe 2923 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2924
2925 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2926 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2927 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2928 events->nmi.pad = 0;
3cfc3092 2929
66450a21 2930 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2931
f077825a
PB		 2932 events->smi.smm = is_smm(vcpu);
2933 events->smi.pending = vcpu->arch.smi_pending;
2934 events->smi.smm_inside_nmi =
2935 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2936 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2937
dab4b911 2938 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2939 | KVM_VCPUEVENT_VALID_SHADOW
2940 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2941 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2942}
2943
2944static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2945 struct kvm_vcpu_events *events)
2946{
dab4b911 2947 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2948 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2949 | KVM_VCPUEVENT_VALID_SHADOW
2950 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2951 return -EINVAL;
2952
7460fb4a 2953 process_nmi(vcpu);
3cfc3092
JK		 2954 vcpu->arch.exception.pending = events->exception.injected;
2955 vcpu->arch.exception.nr = events->exception.nr;
2956 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2957 vcpu->arch.exception.error_code = events->exception.error_code;
2958
2959 vcpu->arch.interrupt.pending = events->interrupt.injected;
2960 vcpu->arch.interrupt.nr = events->interrupt.nr;
2961 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2962 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2963 kvm_x86_ops->set_interrupt_shadow(vcpu,
2964 events->interrupt.shadow);
3cfc3092
JK		 2965
2966 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2967 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2968 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2969 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2970
66450a21
JK		 2971 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2972 kvm_vcpu_has_lapic(vcpu))
2973 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2974
f077825a
PB		 2975 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2976 if (events->smi.smm)
2977 vcpu->arch.hflags |= HF_SMM_MASK;
2978 else
2979 vcpu->arch.hflags &= ~HF_SMM_MASK;
2980 vcpu->arch.smi_pending = events->smi.pending;
2981 if (events->smi.smm_inside_nmi)
2982 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2983 else
2984 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2985 if (kvm_vcpu_has_lapic(vcpu)) {
2986 if (events->smi.latched_init)
2987 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2988 else
2989 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2990 }
2991 }
2992
3842d135
AK		 2993 kvm_make_request(KVM_REQ_EVENT, vcpu);
2994
3cfc3092
JK		 2995 return 0;
2996}
2997
a1efbe77
JK		 2998static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2999 struct kvm_debugregs *dbgregs)
3000{
73aaf249
JK		 3001 unsigned long val;
3002
a1efbe77 3003 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3004 kvm_get_dr(vcpu, 6, &val);
73aaf249 3005 dbgregs->dr6 = val;
a1efbe77
JK		 3006 dbgregs->dr7 = vcpu->arch.dr7;
3007 dbgregs->flags = 0;
97e69aa6 3008 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3009}
3010
3011static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3012 struct kvm_debugregs *dbgregs)
3013{
3014 if (dbgregs->flags)
3015 return -EINVAL;
3016
a1efbe77 3017 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3018 kvm_update_dr0123(vcpu);
a1efbe77 3019 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3020 kvm_update_dr6(vcpu);
a1efbe77 3021 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3022 kvm_update_dr7(vcpu);
a1efbe77 3023
a1efbe77
JK		 3024 return 0;
3025}
3026
df1daba7
PB		 3027#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3028
3029static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3030{
c47ada30 3031 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3032 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3033 u64 valid;
3034
3035 /*
3036 * Copy legacy XSAVE area, to avoid complications with CPUID
3037 * leaves 0 and 1 in the loop below.
3038 */
3039 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3040
3041 /* Set XSTATE_BV */
3042 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3043
3044 /*
3045 * Copy each region from the possibly compacted offset to the
3046 * non-compacted offset.
3047 */
d91cab78 3048 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3049 while (valid) {
3050 u64 feature = valid & -valid;
3051 int index = fls64(feature) - 1;
3052 void *src = get_xsave_addr(xsave, feature);
3053
3054 if (src) {
3055 u32 size, offset, ecx, edx;
3056 cpuid_count(XSTATE_CPUID, index,
3057 &size, &offset, &ecx, &edx);
3058 memcpy(dest + offset, src, size);
3059 }
3060
3061 valid -= feature;
3062 }
3063}
3064
3065static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3066{
c47ada30 3067 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3068 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3069 u64 valid;
3070
3071 /*
3072 * Copy legacy XSAVE area, to avoid complications with CPUID
3073 * leaves 0 and 1 in the loop below.
3074 */
3075 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3076
3077 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3078 xsave->header.xfeatures = xstate_bv;
df1daba7 3079 if (cpu_has_xsaves)
3a54450b 3080 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3081
3082 /*
3083 * Copy each region from the non-compacted offset to the
3084 * possibly compacted offset.
3085 */
d91cab78 3086 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3087 while (valid) {
3088 u64 feature = valid & -valid;
3089 int index = fls64(feature) - 1;
3090 void *dest = get_xsave_addr(xsave, feature);
3091
3092 if (dest) {
3093 u32 size, offset, ecx, edx;
3094 cpuid_count(XSTATE_CPUID, index,
3095 &size, &offset, &ecx, &edx);
3096 memcpy(dest, src + offset, size);
ee4100da 3097 }
df1daba7
PB		 3098
3099 valid -= feature;
3100 }
3101}
3102
2d5b5a66
SY		 3103static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3104 struct kvm_xsave *guest_xsave)
3105{
4344ee98 3106 if (cpu_has_xsave) {
df1daba7
PB		 3107 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3108 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3109 } else {
2d5b5a66 3110 memcpy(guest_xsave->region,
7366ed77 3111 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3112 sizeof(struct fxregs_state));
2d5b5a66 3113 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3114 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3115 }
3116}
3117
3118static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3119 struct kvm_xsave *guest_xsave)
3120{
3121 u64 xstate_bv =
3122 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3123
d7876f1b
PB		 3124 if (cpu_has_xsave) {
3125 /*
3126 * Here we allow setting states that are not present in
3127 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3128 * with old userspace.
3129 */
4ff41732 3130 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3131 return -EINVAL;
df1daba7 3132 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3133 } else {
d91cab78 3134 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3135 return -EINVAL;
7366ed77 3136 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3137 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3138 }
3139 return 0;
3140}
3141
3142static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3143 struct kvm_xcrs *guest_xcrs)
3144{
3145 if (!cpu_has_xsave) {
3146 guest_xcrs->nr_xcrs = 0;
3147 return;
3148 }
3149
3150 guest_xcrs->nr_xcrs = 1;
3151 guest_xcrs->flags = 0;
3152 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3153 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3154}
3155
3156static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3157 struct kvm_xcrs *guest_xcrs)
3158{
3159 int i, r = 0;
3160
3161 if (!cpu_has_xsave)
3162 return -EINVAL;
3163
3164 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3165 return -EINVAL;
3166
3167 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3168 /* Only support XCR0 currently */
c67a04cb 3169 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3170 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3171 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3172 break;
3173 }
3174 if (r)
3175 r = -EINVAL;
3176 return r;
3177}
3178
1c0b28c2
EM		 3179/*
3180 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3181 * stopped by the hypervisor. This function will be called from the host only.
3182 * EINVAL is returned when the host attempts to set the flag for a guest that
3183 * does not support pv clocks.
3184 */
3185static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3186{
0b79459b 3187 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3188 return -EINVAL;
51d59c6b 3189 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3190 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3191 return 0;
3192}
3193
313a3dc7
CO		 3194long kvm_arch_vcpu_ioctl(struct file *filp,
3195 unsigned int ioctl, unsigned long arg)
3196{
3197 struct kvm_vcpu *vcpu = filp->private_data;
3198 void __user *argp = (void __user *)arg;
3199 int r;
d1ac91d8
AK		 3200 union {
3201 struct kvm_lapic_state *lapic;
3202 struct kvm_xsave *xsave;
3203 struct kvm_xcrs *xcrs;
3204 void *buffer;
3205 } u;
3206
3207 u.buffer = NULL;
313a3dc7
CO		 3208 switch (ioctl) {
3209 case KVM_GET_LAPIC: {
2204ae3c
MT		 3210 r = -EINVAL;
3211 if (!vcpu->arch.apic)
3212 goto out;
d1ac91d8 3213 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3214
b772ff36 3215 r = -ENOMEM;
d1ac91d8 3216 if (!u.lapic)
b772ff36 3217 goto out;
d1ac91d8 3218 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3219 if (r)
3220 goto out;
3221 r = -EFAULT;
d1ac91d8 3222 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3223 goto out;
3224 r = 0;
3225 break;
3226 }
3227 case KVM_SET_LAPIC: {
2204ae3c
MT		 3228 r = -EINVAL;
3229 if (!vcpu->arch.apic)
3230 goto out;
ff5c2c03 3231 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3232 if (IS_ERR(u.lapic))
3233 return PTR_ERR(u.lapic);
ff5c2c03 3234
d1ac91d8 3235 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3236 break;
3237 }
f77bc6a4
ZX		 3238 case KVM_INTERRUPT: {
3239 struct kvm_interrupt irq;
3240
3241 r = -EFAULT;
3242 if (copy_from_user(&irq, argp, sizeof irq))
3243 goto out;
3244 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3245 break;
3246 }
c4abb7c9
JK		 3247 case KVM_NMI: {
3248 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3249 break;
3250 }
f077825a
PB		 3251 case KVM_SMI: {
3252 r = kvm_vcpu_ioctl_smi(vcpu);
3253 break;
3254 }
313a3dc7
CO		 3255 case KVM_SET_CPUID: {
3256 struct kvm_cpuid __user *cpuid_arg = argp;
3257 struct kvm_cpuid cpuid;
3258
3259 r = -EFAULT;
3260 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3261 goto out;
3262 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3263 break;
3264 }
07716717
DK		 3265 case KVM_SET_CPUID2: {
3266 struct kvm_cpuid2 __user *cpuid_arg = argp;
3267 struct kvm_cpuid2 cpuid;
3268
3269 r = -EFAULT;
3270 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3271 goto out;
3272 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3273 cpuid_arg->entries);
07716717
DK		 3274 break;
3275 }
3276 case KVM_GET_CPUID2: {
3277 struct kvm_cpuid2 __user *cpuid_arg = argp;
3278 struct kvm_cpuid2 cpuid;
3279
3280 r = -EFAULT;
3281 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3282 goto out;
3283 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3284 cpuid_arg->entries);
07716717
DK		 3285 if (r)
3286 goto out;
3287 r = -EFAULT;
3288 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3289 goto out;
3290 r = 0;
3291 break;
3292 }
313a3dc7 3293 case KVM_GET_MSRS:
609e36d3 3294 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3295 break;
3296 case KVM_SET_MSRS:
3297 r = msr_io(vcpu, argp, do_set_msr, 0);
3298 break;
b209749f
AK		 3299 case KVM_TPR_ACCESS_REPORTING: {
3300 struct kvm_tpr_access_ctl tac;
3301
3302 r = -EFAULT;
3303 if (copy_from_user(&tac, argp, sizeof tac))
3304 goto out;
3305 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3306 if (r)
3307 goto out;
3308 r = -EFAULT;
3309 if (copy_to_user(argp, &tac, sizeof tac))
3310 goto out;
3311 r = 0;
3312 break;
3313 };
b93463aa
AK		 3314 case KVM_SET_VAPIC_ADDR: {
3315 struct kvm_vapic_addr va;
3316
3317 r = -EINVAL;
35754c98 3318 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3319 goto out;
3320 r = -EFAULT;
3321 if (copy_from_user(&va, argp, sizeof va))
3322 goto out;
fda4e2e8 3323 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3324 break;
3325 }
890ca9ae
HY		 3326 case KVM_X86_SETUP_MCE: {
3327 u64 mcg_cap;
3328
3329 r = -EFAULT;
3330 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3331 goto out;
3332 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3333 break;
3334 }
3335 case KVM_X86_SET_MCE: {
3336 struct kvm_x86_mce mce;
3337
3338 r = -EFAULT;
3339 if (copy_from_user(&mce, argp, sizeof mce))
3340 goto out;
3341 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3342 break;
3343 }
3cfc3092
JK		 3344 case KVM_GET_VCPU_EVENTS: {
3345 struct kvm_vcpu_events events;
3346
3347 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3348
3349 r = -EFAULT;
3350 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3351 break;
3352 r = 0;
3353 break;
3354 }
3355 case KVM_SET_VCPU_EVENTS: {
3356 struct kvm_vcpu_events events;
3357
3358 r = -EFAULT;
3359 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3360 break;
3361
3362 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3363 break;
3364 }
a1efbe77
JK		 3365 case KVM_GET_DEBUGREGS: {
3366 struct kvm_debugregs dbgregs;
3367
3368 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3369
3370 r = -EFAULT;
3371 if (copy_to_user(argp, &dbgregs,
3372 sizeof(struct kvm_debugregs)))
3373 break;
3374 r = 0;
3375 break;
3376 }
3377 case KVM_SET_DEBUGREGS: {
3378 struct kvm_debugregs dbgregs;
3379
3380 r = -EFAULT;
3381 if (copy_from_user(&dbgregs, argp,
3382 sizeof(struct kvm_debugregs)))
3383 break;
3384
3385 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3386 break;
3387 }
2d5b5a66 3388 case KVM_GET_XSAVE: {
d1ac91d8 3389 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3390 r = -ENOMEM;
d1ac91d8 3391 if (!u.xsave)
2d5b5a66
SY		 3392 break;
3393
d1ac91d8 3394 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3395
3396 r = -EFAULT;
d1ac91d8 3397 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3398 break;
3399 r = 0;
3400 break;
3401 }
3402 case KVM_SET_XSAVE: {
ff5c2c03 3403 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3404 if (IS_ERR(u.xsave))
3405 return PTR_ERR(u.xsave);
2d5b5a66 3406
d1ac91d8 3407 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3408 break;
3409 }
3410 case KVM_GET_XCRS: {
d1ac91d8 3411 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3412 r = -ENOMEM;
d1ac91d8 3413 if (!u.xcrs)
2d5b5a66
SY		 3414 break;
3415
d1ac91d8 3416 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3417
3418 r = -EFAULT;
d1ac91d8 3419 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3420 sizeof(struct kvm_xcrs)))
3421 break;
3422 r = 0;
3423 break;
3424 }
3425 case KVM_SET_XCRS: {
ff5c2c03 3426 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3427 if (IS_ERR(u.xcrs))
3428 return PTR_ERR(u.xcrs);
2d5b5a66 3429
d1ac91d8 3430 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3431 break;
3432 }
92a1f12d
JR		 3433 case KVM_SET_TSC_KHZ: {
3434 u32 user_tsc_khz;
3435
3436 r = -EINVAL;
92a1f12d
JR		 3437 user_tsc_khz = (u32)arg;
3438
3439 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3440 goto out;
3441
cc578287
ZA		 3442 if (user_tsc_khz == 0)
3443 user_tsc_khz = tsc_khz;
3444
381d585c
HZ		 3445 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3446 r = 0;
92a1f12d 3447
92a1f12d
JR		 3448 goto out;
3449 }
3450 case KVM_GET_TSC_KHZ: {
cc578287 3451 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3452 goto out;
3453 }
1c0b28c2
EM		 3454 case KVM_KVMCLOCK_CTRL: {
3455 r = kvm_set_guest_paused(vcpu);
3456 goto out;
3457 }
313a3dc7
CO		 3458 default:
3459 r = -EINVAL;
3460 }
3461out:
d1ac91d8 3462 kfree(u.buffer);
313a3dc7
CO		 3463 return r;
3464}
3465
5b1c1493
CO		 3466int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3467{
3468 return VM_FAULT_SIGBUS;
3469}
3470
1fe779f8
CO		 3471static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3472{
3473 int ret;
3474
3475 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3476 return -EINVAL;
1fe779f8
CO		 3477 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3478 return ret;
3479}
3480
b927a3ce
SY		 3481static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3482 u64 ident_addr)
3483{
3484 kvm->arch.ept_identity_map_addr = ident_addr;
3485 return 0;
3486}
3487
1fe779f8
CO		 3488static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3489 u32 kvm_nr_mmu_pages)
3490{
3491 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3492 return -EINVAL;
3493
79fac95e 3494 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3495
3496 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3497 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3498
79fac95e 3499 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3500 return 0;
3501}
3502
3503static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3504{
39de71ec 3505 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3506}
3507
1fe779f8
CO		 3508static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3509{
3510 int r;
3511
3512 r = 0;
3513 switch (chip->chip_id) {
3514 case KVM_IRQCHIP_PIC_MASTER:
3515 memcpy(&chip->chip.pic,
3516 &pic_irqchip(kvm)->pics[0],
3517 sizeof(struct kvm_pic_state));
3518 break;
3519 case KVM_IRQCHIP_PIC_SLAVE:
3520 memcpy(&chip->chip.pic,
3521 &pic_irqchip(kvm)->pics[1],
3522 sizeof(struct kvm_pic_state));
3523 break;
3524 case KVM_IRQCHIP_IOAPIC:
eba0226b 3525 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3526 break;
3527 default:
3528 r = -EINVAL;
3529 break;
3530 }
3531 return r;
3532}
3533
3534static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3535{
3536 int r;
3537
3538 r = 0;
3539 switch (chip->chip_id) {
3540 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3541 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3542 memcpy(&pic_irqchip(kvm)->pics[0],
3543 &chip->chip.pic,
3544 sizeof(struct kvm_pic_state));
f4f51050 3545 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3546 break;
3547 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3548 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3549 memcpy(&pic_irqchip(kvm)->pics[1],
3550 &chip->chip.pic,
3551 sizeof(struct kvm_pic_state));
f4f51050 3552 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3553 break;
3554 case KVM_IRQCHIP_IOAPIC:
eba0226b 3555 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3556 break;
3557 default:
3558 r = -EINVAL;
3559 break;
3560 }
3561 kvm_pic_update_irq(pic_irqchip(kvm));
3562 return r;
3563}
3564
e0f63cb9
SY		 3565static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3566{
894a9c55 3567 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3568 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3569 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3570 return 0;
e0f63cb9
SY		 3571}
3572
3573static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3574{
894a9c55 3575 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3576 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3577 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3578 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3579 return 0;
e9f42757
BK		 3580}
3581
3582static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3583{
e9f42757
BK		 3584 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3585 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3586 sizeof(ps->channels));
3587 ps->flags = kvm->arch.vpit->pit_state.flags;
3588 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3589 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3590 return 0;
e9f42757
BK		 3591}
3592
3593static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3594{
2da29bcc 3595 int start = 0;
e9f42757
BK		 3596 u32 prev_legacy, cur_legacy;
3597 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3598 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3599 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3600 if (!prev_legacy && cur_legacy)
3601 start = 1;
3602 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3603 sizeof(kvm->arch.vpit->pit_state.channels));
3604 kvm->arch.vpit->pit_state.flags = ps->flags;
3605 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3606 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3607 return 0;
e0f63cb9
SY		 3608}
3609
52d939a0
MT		 3610static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3611 struct kvm_reinject_control *control)
3612{
3613 if (!kvm->arch.vpit)
3614 return -ENXIO;
894a9c55 3615 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3616 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3617 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3618 return 0;
3619}
3620
95d4c16c 3621/**
60c34612
TY		 3622 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3623 * @kvm: kvm instance
3624 * @log: slot id and address to which we copy the log
95d4c16c 3625 *
e108ff2f
PB		 3626 * Steps 1-4 below provide general overview of dirty page logging. See
3627 * kvm_get_dirty_log_protect() function description for additional details.
3628 *
3629 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3630 * always flush the TLB (step 4) even if previous step failed and the dirty
3631 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3632 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3633 * writes will be marked dirty for next log read.
95d4c16c 3634 *
60c34612
TY		 3635 * 1. Take a snapshot of the bit and clear it if needed.
3636 * 2. Write protect the corresponding page.
e108ff2f
PB		 3637 * 3. Copy the snapshot to the userspace.
3638 * 4. Flush TLB's if needed.
5bb064dc 3639 */
60c34612 3640int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3641{
60c34612 3642 bool is_dirty = false;
e108ff2f 3643 int r;
5bb064dc 3644
79fac95e 3645 mutex_lock(&kvm->slots_lock);
5bb064dc 3646
88178fd4
KH		 3647 /*
3648 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3649 */
3650 if (kvm_x86_ops->flush_log_dirty)
3651 kvm_x86_ops->flush_log_dirty(kvm);
3652
e108ff2f 3653 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3654
3655 /*
3656 * All the TLBs can be flushed out of mmu lock, see the comments in
3657 * kvm_mmu_slot_remove_write_access().
3658 */
e108ff2f 3659 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3660 if (is_dirty)
3661 kvm_flush_remote_tlbs(kvm);
3662
79fac95e 3663 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3664 return r;
3665}
3666
aa2fbe6d
YZ		 3667int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3668 bool line_status)
23d43cf9
CD		 3669{
3670 if (!irqchip_in_kernel(kvm))
3671 return -ENXIO;
3672
3673 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3674 irq_event->irq, irq_event->level,
3675 line_status);
23d43cf9
CD		 3676 return 0;
3677}
3678
90de4a18
NA		 3679static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3680 struct kvm_enable_cap *cap)
3681{
3682 int r;
3683
3684 if (cap->flags)
3685 return -EINVAL;
3686
3687 switch (cap->cap) {
3688 case KVM_CAP_DISABLE_QUIRKS:
3689 kvm->arch.disabled_quirks = cap->args[0];
3690 r = 0;
3691 break;
49df6397
SR		 3692 case KVM_CAP_SPLIT_IRQCHIP: {
3693 mutex_lock(&kvm->lock);
b053b2ae
SR		 3694 r = -EINVAL;
3695 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3696 goto split_irqchip_unlock;
49df6397
SR		 3697 r = -EEXIST;
3698 if (irqchip_in_kernel(kvm))
3699 goto split_irqchip_unlock;
3700 if (atomic_read(&kvm->online_vcpus))
3701 goto split_irqchip_unlock;
3702 r = kvm_setup_empty_irq_routing(kvm);
3703 if (r)
3704 goto split_irqchip_unlock;
3705 /* Pairs with irqchip_in_kernel. */
3706 smp_wmb();
3707 kvm->arch.irqchip_split = true;
b053b2ae 3708 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3709 r = 0;
3710split_irqchip_unlock:
3711 mutex_unlock(&kvm->lock);
3712 break;
3713 }
90de4a18
NA		 3714 default:
3715 r = -EINVAL;
3716 break;
3717 }
3718 return r;
3719}
3720
1fe779f8
CO		 3721long kvm_arch_vm_ioctl(struct file *filp,
3722 unsigned int ioctl, unsigned long arg)
3723{
3724 struct kvm *kvm = filp->private_data;
3725 void __user *argp = (void __user *)arg;
367e1319 3726 int r = -ENOTTY;
f0d66275
DH		 3727 /*
3728 * This union makes it completely explicit to gcc-3.x
3729 * that these two variables' stack usage should be
3730 * combined, not added together.
3731 */
3732 union {
3733 struct kvm_pit_state ps;
e9f42757 3734 struct kvm_pit_state2 ps2;
c5ff41ce 3735 struct kvm_pit_config pit_config;
f0d66275 3736 } u;
1fe779f8
CO		 3737
3738 switch (ioctl) {
3739 case KVM_SET_TSS_ADDR:
3740 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3741 break;
b927a3ce
SY		 3742 case KVM_SET_IDENTITY_MAP_ADDR: {
3743 u64 ident_addr;
3744
3745 r = -EFAULT;
3746 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3747 goto out;
3748 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3749 break;
3750 }
1fe779f8
CO		 3751 case KVM_SET_NR_MMU_PAGES:
3752 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3753 break;
3754 case KVM_GET_NR_MMU_PAGES:
3755 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3756 break;
3ddea128
MT		 3757 case KVM_CREATE_IRQCHIP: {
3758 struct kvm_pic *vpic;
3759
3760 mutex_lock(&kvm->lock);
3761 r = -EEXIST;
3762 if (kvm->arch.vpic)
3763 goto create_irqchip_unlock;
3e515705
AK		 3764 r = -EINVAL;
3765 if (atomic_read(&kvm->online_vcpus))
3766 goto create_irqchip_unlock;
1fe779f8 3767 r = -ENOMEM;
3ddea128
MT		 3768 vpic = kvm_create_pic(kvm);
3769 if (vpic) {
1fe779f8
CO		 3770 r = kvm_ioapic_init(kvm);
3771 if (r) {
175504cd 3772 mutex_lock(&kvm->slots_lock);
71ba994c 3773 kvm_destroy_pic(vpic);
175504cd 3774 mutex_unlock(&kvm->slots_lock);
3ddea128 3775 goto create_irqchip_unlock;
1fe779f8
CO		 3776 }
3777 } else
3ddea128 3778 goto create_irqchip_unlock;
399ec807
AK		 3779 r = kvm_setup_default_irq_routing(kvm);
3780 if (r) {
175504cd 3781 mutex_lock(&kvm->slots_lock);
3ddea128 3782 mutex_lock(&kvm->irq_lock);
72bb2fcd 3783 kvm_ioapic_destroy(kvm);
71ba994c 3784 kvm_destroy_pic(vpic);
3ddea128 3785 mutex_unlock(&kvm->irq_lock);
175504cd 3786 mutex_unlock(&kvm->slots_lock);
71ba994c 3787 goto create_irqchip_unlock;
399ec807 3788 }
71ba994c
PB		 3789 /* Write kvm->irq_routing before kvm->arch.vpic. */
3790 smp_wmb();
3791 kvm->arch.vpic = vpic;
3ddea128
MT		 3792 create_irqchip_unlock:
3793 mutex_unlock(&kvm->lock);
1fe779f8 3794 break;
3ddea128 3795 }
7837699f 3796 case KVM_CREATE_PIT:
c5ff41ce
JK		 3797 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3798 goto create_pit;
3799 case KVM_CREATE_PIT2:
3800 r = -EFAULT;
3801 if (copy_from_user(&u.pit_config, argp,
3802 sizeof(struct kvm_pit_config)))
3803 goto out;
3804 create_pit:
79fac95e 3805 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3806 r = -EEXIST;
3807 if (kvm->arch.vpit)
3808 goto create_pit_unlock;
7837699f 3809 r = -ENOMEM;
c5ff41ce 3810 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3811 if (kvm->arch.vpit)
3812 r = 0;
269e05e4 3813 create_pit_unlock:
79fac95e 3814 mutex_unlock(&kvm->slots_lock);
7837699f 3815 break;
1fe779f8
CO		 3816 case KVM_GET_IRQCHIP: {
3817 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3818 struct kvm_irqchip *chip;
1fe779f8 3819
ff5c2c03
SL		 3820 chip = memdup_user(argp, sizeof(*chip));
3821 if (IS_ERR(chip)) {
3822 r = PTR_ERR(chip);
1fe779f8 3823 goto out;
ff5c2c03
SL		 3824 }
3825
1fe779f8 3826 r = -ENXIO;
49df6397 3827 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3828 goto get_irqchip_out;
3829 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3830 if (r)
f0d66275 3831 goto get_irqchip_out;
1fe779f8 3832 r = -EFAULT;
f0d66275
DH		 3833 if (copy_to_user(argp, chip, sizeof *chip))
3834 goto get_irqchip_out;
1fe779f8 3835 r = 0;
f0d66275
DH		 3836 get_irqchip_out:
3837 kfree(chip);
1fe779f8
CO		 3838 break;
3839 }
3840 case KVM_SET_IRQCHIP: {
3841 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3842 struct kvm_irqchip *chip;
1fe779f8 3843
ff5c2c03
SL		 3844 chip = memdup_user(argp, sizeof(*chip));
3845 if (IS_ERR(chip)) {
3846 r = PTR_ERR(chip);
1fe779f8 3847 goto out;
ff5c2c03
SL		 3848 }
3849
1fe779f8 3850 r = -ENXIO;
49df6397 3851 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3852 goto set_irqchip_out;
3853 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3854 if (r)
f0d66275 3855 goto set_irqchip_out;
1fe779f8 3856 r = 0;
f0d66275
DH		 3857 set_irqchip_out:
3858 kfree(chip);
1fe779f8
CO		 3859 break;
3860 }
e0f63cb9 3861 case KVM_GET_PIT: {
e0f63cb9 3862 r = -EFAULT;
f0d66275 3863 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3864 goto out;
3865 r = -ENXIO;
3866 if (!kvm->arch.vpit)
3867 goto out;
f0d66275 3868 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3869 if (r)
3870 goto out;
3871 r = -EFAULT;
f0d66275 3872 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3873 goto out;
3874 r = 0;
3875 break;
3876 }
3877 case KVM_SET_PIT: {
e0f63cb9 3878 r = -EFAULT;
f0d66275 3879 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3880 goto out;
3881 r = -ENXIO;
3882 if (!kvm->arch.vpit)
3883 goto out;
f0d66275 3884 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3885 break;
3886 }
e9f42757
BK		 3887 case KVM_GET_PIT2: {
3888 r = -ENXIO;
3889 if (!kvm->arch.vpit)
3890 goto out;
3891 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3892 if (r)
3893 goto out;
3894 r = -EFAULT;
3895 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3896 goto out;
3897 r = 0;
3898 break;
3899 }
3900 case KVM_SET_PIT2: {
3901 r = -EFAULT;
3902 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3903 goto out;
3904 r = -ENXIO;
3905 if (!kvm->arch.vpit)
3906 goto out;
3907 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3908 break;
3909 }
52d939a0
MT		 3910 case KVM_REINJECT_CONTROL: {
3911 struct kvm_reinject_control control;
3912 r = -EFAULT;
3913 if (copy_from_user(&control, argp, sizeof(control)))
3914 goto out;
3915 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3916 break;
3917 }
d71ba788
PB		 3918 case KVM_SET_BOOT_CPU_ID:
3919 r = 0;
3920 mutex_lock(&kvm->lock);
3921 if (atomic_read(&kvm->online_vcpus) != 0)
3922 r = -EBUSY;
3923 else
3924 kvm->arch.bsp_vcpu_id = arg;
3925 mutex_unlock(&kvm->lock);
3926 break;
ffde22ac
ES		 3927 case KVM_XEN_HVM_CONFIG: {
3928 r = -EFAULT;
3929 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3930 sizeof(struct kvm_xen_hvm_config)))
3931 goto out;
3932 r = -EINVAL;
3933 if (kvm->arch.xen_hvm_config.flags)
3934 goto out;
3935 r = 0;
3936 break;
3937 }
afbcf7ab 3938 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3939 struct kvm_clock_data user_ns;
3940 u64 now_ns;
3941 s64 delta;
3942
3943 r = -EFAULT;
3944 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3945 goto out;
3946
3947 r = -EINVAL;
3948 if (user_ns.flags)
3949 goto out;
3950
3951 r = 0;
395c6b0a 3952 local_irq_disable();
759379dd 3953 now_ns = get_kernel_ns();
afbcf7ab 3954 delta = user_ns.clock - now_ns;
395c6b0a 3955 local_irq_enable();
afbcf7ab 3956 kvm->arch.kvmclock_offset = delta;
2e762ff7 3957 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3958 break;
3959 }
3960 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3961 struct kvm_clock_data user_ns;
3962 u64 now_ns;
3963
395c6b0a 3964 local_irq_disable();
759379dd 3965 now_ns = get_kernel_ns();
afbcf7ab 3966 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3967 local_irq_enable();
afbcf7ab 3968 user_ns.flags = 0;
97e69aa6 3969 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3970
3971 r = -EFAULT;
3972 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3973 goto out;
3974 r = 0;
3975 break;
3976 }
90de4a18
NA		 3977 case KVM_ENABLE_CAP: {
3978 struct kvm_enable_cap cap;
afbcf7ab 3979
90de4a18
NA		 3980 r = -EFAULT;
3981 if (copy_from_user(&cap, argp, sizeof(cap)))
3982 goto out;
3983 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
3984 break;
3985 }
1fe779f8 3986 default:
c274e03a 3987 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 3988 }
3989out:
3990 return r;
3991}
3992
a16b043c 3993static void kvm_init_msr_list(void)
043405e1
CO		 3994{
3995 u32 dummy[2];
3996 unsigned i, j;
3997
62ef68bb 3998 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3999 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4000 continue;
93c4adc7
PB		 4001
4002 /*
4003 * Even MSRs that are valid in the host may not be exposed
4004 * to the guests in some cases. We could work around this
4005 * in VMX with the generic MSR save/load machinery, but it
4006 * is not really worthwhile since it will really only
4007 * happen with nested virtualization.
4008 */
4009 switch (msrs_to_save[i]) {
4010 case MSR_IA32_BNDCFGS:
4011 if (!kvm_x86_ops->mpx_supported())
4012 continue;
4013 break;
4014 default:
4015 break;
4016 }
4017
043405e1
CO		 4018 if (j < i)
4019 msrs_to_save[j] = msrs_to_save[i];
4020 j++;
4021 }
4022 num_msrs_to_save = j;
62ef68bb
PB		 4023
4024 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4025 switch (emulated_msrs[i]) {
6d396b55
PB		 4026 case MSR_IA32_SMBASE:
4027 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4028 continue;
4029 break;
62ef68bb
PB		 4030 default:
4031 break;
4032 }
4033
4034 if (j < i)
4035 emulated_msrs[j] = emulated_msrs[i];
4036 j++;
4037 }
4038 num_emulated_msrs = j;
043405e1
CO		 4039}
4040
bda9020e
MT		 4041static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4042 const void *v)
bbd9b64e 4043{
70252a10
AK		 4044 int handled = 0;
4045 int n;
4046
4047 do {
4048 n = min(len, 8);
4049 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4050 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4051 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4052 break;
4053 handled += n;
4054 addr += n;
4055 len -= n;
4056 v += n;
4057 } while (len);
bbd9b64e 4058
70252a10 4059 return handled;
bbd9b64e
CO		 4060}
4061
bda9020e 4062static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4063{
70252a10
AK		 4064 int handled = 0;
4065 int n;
4066
4067 do {
4068 n = min(len, 8);
4069 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4070 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4071 addr, n, v))
4072 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4073 break;
4074 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4075 handled += n;
4076 addr += n;
4077 len -= n;
4078 v += n;
4079 } while (len);
bbd9b64e 4080
70252a10 4081 return handled;
bbd9b64e
CO		 4082}
4083
2dafc6c2
GN		 4084static void kvm_set_segment(struct kvm_vcpu *vcpu,
4085 struct kvm_segment *var, int seg)
4086{
4087 kvm_x86_ops->set_segment(vcpu, var, seg);
4088}
4089
4090void kvm_get_segment(struct kvm_vcpu *vcpu,
4091 struct kvm_segment *var, int seg)
4092{
4093 kvm_x86_ops->get_segment(vcpu, var, seg);
4094}
4095
54987b7a
PB		 4096gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4097 struct x86_exception *exception)
02f59dc9
JR		 4098{
4099 gpa_t t_gpa;
02f59dc9
JR		 4100
4101 BUG_ON(!mmu_is_nested(vcpu));
4102
4103 /* NPT walks are always user-walks */
4104 access |= PFERR_USER_MASK;
54987b7a 4105 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4106
4107 return t_gpa;
4108}
4109
ab9ae313
AK		 4110gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4111 struct x86_exception *exception)
1871c602
GN		 4112{
4113 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4114 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4115}
4116
ab9ae313
AK		 4117 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4118 struct x86_exception *exception)
1871c602
GN		 4119{
4120 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4121 access |= PFERR_FETCH_MASK;
ab9ae313 4122 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4123}
4124
ab9ae313
AK		 4125gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4126 struct x86_exception *exception)
1871c602
GN		 4127{
4128 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4129 access |= PFERR_WRITE_MASK;
ab9ae313 4130 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4131}
4132
4133/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4134gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4135 struct x86_exception *exception)
1871c602 4136{
ab9ae313 4137 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4138}
4139
4140static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4141 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4142 struct x86_exception *exception)
bbd9b64e
CO		 4143{
4144 void *data = val;
10589a46 4145 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4146
4147 while (bytes) {
14dfe855 4148 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4149 exception);
bbd9b64e 4150 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4151 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4152 int ret;
4153
bcc55cba 4154 if (gpa == UNMAPPED_GVA)
ab9ae313 4155 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4156 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4157 offset, toread);
10589a46 4158 if (ret < 0) {
c3cd7ffa 4159 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4160 goto out;
4161 }
bbd9b64e 4162
77c2002e
IE		 4163 bytes -= toread;
4164 data += toread;
4165 addr += toread;
bbd9b64e 4166 }
10589a46 4167out:
10589a46 4168 return r;
bbd9b64e 4169}
77c2002e 4170
1871c602 4171/* used for instruction fetching */
0f65dd70
AK		 4172static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4173 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4174 struct x86_exception *exception)
1871c602 4175{
0f65dd70 4176 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4177 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4178 unsigned offset;
4179 int ret;
0f65dd70 4180
44583cba
PB		 4181 /* Inline kvm_read_guest_virt_helper for speed. */
4182 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4183 exception);
4184 if (unlikely(gpa == UNMAPPED_GVA))
4185 return X86EMUL_PROPAGATE_FAULT;
4186
4187 offset = addr & (PAGE_SIZE-1);
4188 if (WARN_ON(offset + bytes > PAGE_SIZE))
4189 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4190 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4191 offset, bytes);
44583cba
PB		 4192 if (unlikely(ret < 0))
4193 return X86EMUL_IO_NEEDED;
4194
4195 return X86EMUL_CONTINUE;
1871c602
GN		 4196}
4197
064aea77 4198int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4199 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4200 struct x86_exception *exception)
1871c602 4201{
0f65dd70 4202 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4203 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4204
1871c602 4205 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4206 exception);
1871c602 4207}
064aea77 4208EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4209
0f65dd70
AK		 4210static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4211 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4212 struct x86_exception *exception)
1871c602 4213{
0f65dd70 4214 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4215 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4216}
4217
7a036a6f
RK		 4218static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4219 unsigned long addr, void *val, unsigned int bytes)
4220{
4221 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4222 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4223
4224 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4225}
4226
6a4d7550 4227int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4228 gva_t addr, void *val,
2dafc6c2 4229 unsigned int bytes,
bcc55cba 4230 struct x86_exception *exception)
77c2002e 4231{
0f65dd70 4232 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4233 void *data = val;
4234 int r = X86EMUL_CONTINUE;
4235
4236 while (bytes) {
14dfe855
JR		 4237 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4238 PFERR_WRITE_MASK,
ab9ae313 4239 exception);
77c2002e
IE		 4240 unsigned offset = addr & (PAGE_SIZE-1);
4241 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4242 int ret;
4243
bcc55cba 4244 if (gpa == UNMAPPED_GVA)
ab9ae313 4245 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4246 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4247 if (ret < 0) {
c3cd7ffa 4248 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4249 goto out;
4250 }
4251
4252 bytes -= towrite;
4253 data += towrite;
4254 addr += towrite;
4255 }
4256out:
4257 return r;
4258}
6a4d7550 4259EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4260
af7cc7d1
XG		 4261static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4262 gpa_t *gpa, struct x86_exception *exception,
4263 bool write)
4264{
97d64b78
AK		 4265 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4266 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4267
97d64b78 4268 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4269 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4270 vcpu->arch.access, access)) {
bebb106a
XG		 4271 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4272 (gva & (PAGE_SIZE - 1));
4f022648 4273 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4274 return 1;
4275 }
4276
af7cc7d1
XG		 4277 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4278
4279 if (*gpa == UNMAPPED_GVA)
4280 return -1;
4281
4282 /* For APIC access vmexit */
4283 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4284 return 1;
4285
4f022648
XG		 4286 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4287 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4288 return 1;
4f022648 4289 }
bebb106a 4290
af7cc7d1
XG		 4291 return 0;
4292}
4293
3200f405 4294int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4295 const void *val, int bytes)
bbd9b64e
CO		 4296{
4297 int ret;
4298
54bf36aa 4299 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4300 if (ret < 0)
bbd9b64e 4301 return 0;
f57f2ef5 4302 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4303 return 1;
4304}
4305
77d197b2
XG		 4306struct read_write_emulator_ops {
4307 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4308 int bytes);
4309 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4310 void *val, int bytes);
4311 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4312 int bytes, void *val);
4313 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4314 void *val, int bytes);
4315 bool write;
4316};
4317
4318static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4319{
4320 if (vcpu->mmio_read_completed) {
77d197b2 4321 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4322 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4323 vcpu->mmio_read_completed = 0;
4324 return 1;
4325 }
4326
4327 return 0;
4328}
4329
4330static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4331 void *val, int bytes)
4332{
54bf36aa 4333 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4334}
4335
4336static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4337 void *val, int bytes)
4338{
4339 return emulator_write_phys(vcpu, gpa, val, bytes);
4340}
4341
4342static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4343{
4344 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4345 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4346}
4347
4348static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4349 void *val, int bytes)
4350{
4351 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4352 return X86EMUL_IO_NEEDED;
4353}
4354
4355static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4356 void *val, int bytes)
4357{
f78146b0
AK		 4358 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4359
87da7e66 4360 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4361 return X86EMUL_CONTINUE;
4362}
4363
0fbe9b0b 4364static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4365 .read_write_prepare = read_prepare,
4366 .read_write_emulate = read_emulate,
4367 .read_write_mmio = vcpu_mmio_read,
4368 .read_write_exit_mmio = read_exit_mmio,
4369};
4370
0fbe9b0b 4371static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4372 .read_write_emulate = write_emulate,
4373 .read_write_mmio = write_mmio,
4374 .read_write_exit_mmio = write_exit_mmio,
4375 .write = true,
4376};
4377
22388a3c
XG		 4378static int emulator_read_write_onepage(unsigned long addr, void *val,
4379 unsigned int bytes,
4380 struct x86_exception *exception,
4381 struct kvm_vcpu *vcpu,
0fbe9b0b 4382 const struct read_write_emulator_ops *ops)
bbd9b64e 4383{
af7cc7d1
XG		 4384 gpa_t gpa;
4385 int handled, ret;
22388a3c 4386 bool write = ops->write;
f78146b0 4387 struct kvm_mmio_fragment *frag;
10589a46 4388
22388a3c 4389 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4390
af7cc7d1 4391 if (ret < 0)
bbd9b64e 4392 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4393
4394 /* For APIC access vmexit */
af7cc7d1 4395 if (ret)
bbd9b64e
CO		 4396 goto mmio;
4397
22388a3c 4398 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4399 return X86EMUL_CONTINUE;
4400
4401mmio:
4402 /*
4403 * Is this MMIO handled locally?
4404 */
22388a3c 4405 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4406 if (handled == bytes)
bbd9b64e 4407 return X86EMUL_CONTINUE;
bbd9b64e 4408
70252a10
AK		 4409 gpa += handled;
4410 bytes -= handled;
4411 val += handled;
4412
87da7e66
XG		 4413 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4414 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4415 frag->gpa = gpa;
4416 frag->data = val;
4417 frag->len = bytes;
f78146b0 4418 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4419}
4420
52eb5a6d
XL		 4421static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4422 unsigned long addr,
22388a3c
XG		 4423 void *val, unsigned int bytes,
4424 struct x86_exception *exception,
0fbe9b0b 4425 const struct read_write_emulator_ops *ops)
bbd9b64e 4426{
0f65dd70 4427 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4428 gpa_t gpa;
4429 int rc;
4430
4431 if (ops->read_write_prepare &&
4432 ops->read_write_prepare(vcpu, val, bytes))
4433 return X86EMUL_CONTINUE;
4434
4435 vcpu->mmio_nr_fragments = 0;
0f65dd70 4436
bbd9b64e
CO		 4437 /* Crossing a page boundary? */
4438 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4439 int now;
bbd9b64e
CO		 4440
4441 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4442 rc = emulator_read_write_onepage(addr, val, now, exception,
4443 vcpu, ops);
4444
bbd9b64e
CO		 4445 if (rc != X86EMUL_CONTINUE)
4446 return rc;
4447 addr += now;
bac15531
NA		 4448 if (ctxt->mode != X86EMUL_MODE_PROT64)
4449 addr = (u32)addr;
bbd9b64e
CO		 4450 val += now;
4451 bytes -= now;
4452 }
22388a3c 4453
f78146b0
AK		 4454 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4455 vcpu, ops);
4456 if (rc != X86EMUL_CONTINUE)
4457 return rc;
4458
4459 if (!vcpu->mmio_nr_fragments)
4460 return rc;
4461
4462 gpa = vcpu->mmio_fragments[0].gpa;
4463
4464 vcpu->mmio_needed = 1;
4465 vcpu->mmio_cur_fragment = 0;
4466
87da7e66 4467 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4468 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4469 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4470 vcpu->run->mmio.phys_addr = gpa;
4471
4472 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4473}
4474
4475static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4476 unsigned long addr,
4477 void *val,
4478 unsigned int bytes,
4479 struct x86_exception *exception)
4480{
4481 return emulator_read_write(ctxt, addr, val, bytes,
4482 exception, &read_emultor);
4483}
4484
52eb5a6d 4485static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4486 unsigned long addr,
4487 const void *val,
4488 unsigned int bytes,
4489 struct x86_exception *exception)
4490{
4491 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4492 exception, &write_emultor);
bbd9b64e 4493}
bbd9b64e 4494
daea3e73
AK		 4495#define CMPXCHG_TYPE(t, ptr, old, new) \
4496 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4497
4498#ifdef CONFIG_X86_64
4499# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4500#else
4501# define CMPXCHG64(ptr, old, new) \
9749a6c0 4502 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4503#endif
4504
0f65dd70
AK		 4505static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4506 unsigned long addr,
bbd9b64e
CO		 4507 const void *old,
4508 const void *new,
4509 unsigned int bytes,
0f65dd70 4510 struct x86_exception *exception)
bbd9b64e 4511{
0f65dd70 4512 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4513 gpa_t gpa;
4514 struct page *page;
4515 char *kaddr;
4516 bool exchanged;
2bacc55c 4517
daea3e73
AK		 4518 /* guests cmpxchg8b have to be emulated atomically */
4519 if (bytes > 8 || (bytes & (bytes - 1)))
4520 goto emul_write;
10589a46 4521
daea3e73 4522 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4523
daea3e73
AK		 4524 if (gpa == UNMAPPED_GVA ||
4525 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4526 goto emul_write;
2bacc55c 4527
daea3e73
AK		 4528 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4529 goto emul_write;
72dc67a6 4530
54bf36aa 4531 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4532 if (is_error_page(page))
c19b8bd6 4533 goto emul_write;
72dc67a6 4534
8fd75e12 4535 kaddr = kmap_atomic(page);
daea3e73
AK		 4536 kaddr += offset_in_page(gpa);
4537 switch (bytes) {
4538 case 1:
4539 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4540 break;
4541 case 2:
4542 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4543 break;
4544 case 4:
4545 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4546 break;
4547 case 8:
4548 exchanged = CMPXCHG64(kaddr, old, new);
4549 break;
4550 default:
4551 BUG();
2bacc55c 4552 }
8fd75e12 4553 kunmap_atomic(kaddr);
daea3e73
AK		 4554 kvm_release_page_dirty(page);
4555
4556 if (!exchanged)
4557 return X86EMUL_CMPXCHG_FAILED;
4558
54bf36aa 4559 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4560 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4561
4562 return X86EMUL_CONTINUE;
4a5f48f6 4563
3200f405 4564emul_write:
daea3e73 4565 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4566
0f65dd70 4567 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4568}
4569
cf8f70bf
GN		 4570static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4571{
4572 /* TODO: String I/O for in kernel device */
4573 int r;
4574
4575 if (vcpu->arch.pio.in)
e32edf4f 4576 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4577 vcpu->arch.pio.size, pd);
4578 else
e32edf4f 4579 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4580 vcpu->arch.pio.port, vcpu->arch.pio.size,
4581 pd);
4582 return r;
4583}
4584
6f6fbe98
XG		 4585static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4586 unsigned short port, void *val,
4587 unsigned int count, bool in)
cf8f70bf 4588{
cf8f70bf 4589 vcpu->arch.pio.port = port;
6f6fbe98 4590 vcpu->arch.pio.in = in;
7972995b 4591 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4592 vcpu->arch.pio.size = size;
4593
4594 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4595 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4596 return 1;
4597 }
4598
4599 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4600 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4601 vcpu->run->io.size = size;
4602 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4603 vcpu->run->io.count = count;
4604 vcpu->run->io.port = port;
4605
4606 return 0;
4607}
4608
6f6fbe98
XG		 4609static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4610 int size, unsigned short port, void *val,
4611 unsigned int count)
cf8f70bf 4612{
ca1d4a9e 4613 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4614 int ret;
ca1d4a9e 4615
6f6fbe98
XG		 4616 if (vcpu->arch.pio.count)
4617 goto data_avail;
cf8f70bf 4618
6f6fbe98
XG		 4619 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4620 if (ret) {
4621data_avail:
4622 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4623 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4624 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4625 return 1;
4626 }
4627
cf8f70bf
GN		 4628 return 0;
4629}
4630
6f6fbe98
XG		 4631static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4632 int size, unsigned short port,
4633 const void *val, unsigned int count)
4634{
4635 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4636
4637 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4638 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4639 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4640}
4641
bbd9b64e
CO		 4642static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4643{
4644 return kvm_x86_ops->get_segment_base(vcpu, seg);
4645}
4646
3cb16fe7 4647static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4648{
3cb16fe7 4649 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4650}
4651
5cb56059 4652int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4653{
4654 if (!need_emulate_wbinvd(vcpu))
4655 return X86EMUL_CONTINUE;
4656
4657 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4658 int cpu = get_cpu();
4659
4660 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4661 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4662 wbinvd_ipi, NULL, 1);
2eec7343 4663 put_cpu();
f5f48ee1 4664 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4665 } else
4666 wbinvd();
f5f48ee1
SY		 4667 return X86EMUL_CONTINUE;
4668}
5cb56059
JS		 4669
4670int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4671{
4672 kvm_x86_ops->skip_emulated_instruction(vcpu);
4673 return kvm_emulate_wbinvd_noskip(vcpu);
4674}
f5f48ee1
SY		 4675EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4676
5cb56059
JS		 4677
4678
bcaf5cc5
AK		 4679static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4680{
5cb56059 4681 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4682}
4683
52eb5a6d
XL		 4684static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4685 unsigned long *dest)
bbd9b64e 4686{
16f8a6f9 4687 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4688}
4689
52eb5a6d
XL		 4690static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4691 unsigned long value)
bbd9b64e 4692{
338dbc97 4693
717746e3 4694 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4695}
4696
52a46617 4697static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4698{
52a46617 4699 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4700}
4701
717746e3 4702static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4703{
717746e3 4704 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4705 unsigned long value;
4706
4707 switch (cr) {
4708 case 0:
4709 value = kvm_read_cr0(vcpu);
4710 break;
4711 case 2:
4712 value = vcpu->arch.cr2;
4713 break;
4714 case 3:
9f8fe504 4715 value = kvm_read_cr3(vcpu);
52a46617
GN		 4716 break;
4717 case 4:
4718 value = kvm_read_cr4(vcpu);
4719 break;
4720 case 8:
4721 value = kvm_get_cr8(vcpu);
4722 break;
4723 default:
a737f256 4724 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4725 return 0;
4726 }
4727
4728 return value;
4729}
4730
717746e3 4731static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4732{
717746e3 4733 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4734 int res = 0;
4735
52a46617
GN		 4736 switch (cr) {
4737 case 0:
49a9b07e 4738 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4739 break;
4740 case 2:
4741 vcpu->arch.cr2 = val;
4742 break;
4743 case 3:
2390218b 4744 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4745 break;
4746 case 4:
a83b29c6 4747 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4748 break;
4749 case 8:
eea1cff9 4750 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4751 break;
4752 default:
a737f256 4753 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4754 res = -1;
52a46617 4755 }
0f12244f
GN		 4756
4757 return res;
52a46617
GN		 4758}
4759
717746e3 4760static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4761{
717746e3 4762 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4763}
4764
4bff1e86 4765static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4766{
4bff1e86 4767 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4768}
4769
4bff1e86 4770static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4771{
4bff1e86 4772 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4773}
4774
1ac9d0cf
AK		 4775static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4776{
4777 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4778}
4779
4780static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4781{
4782 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4783}
4784
4bff1e86
AK		 4785static unsigned long emulator_get_cached_segment_base(
4786 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4787{
4bff1e86 4788 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4789}
4790
1aa36616
AK		 4791static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4792 struct desc_struct *desc, u32 *base3,
4793 int seg)
2dafc6c2
GN		 4794{
4795 struct kvm_segment var;
4796
4bff1e86 4797 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4798 *selector = var.selector;
2dafc6c2 4799
378a8b09
GN		 4800 if (var.unusable) {
4801 memset(desc, 0, sizeof(*desc));
2dafc6c2 4802 return false;
378a8b09 4803 }
2dafc6c2
GN		 4804
4805 if (var.g)
4806 var.limit >>= 12;
4807 set_desc_limit(desc, var.limit);
4808 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4809#ifdef CONFIG_X86_64
4810 if (base3)
4811 *base3 = var.base >> 32;
4812#endif
2dafc6c2
GN		 4813 desc->type = var.type;
4814 desc->s = var.s;
4815 desc->dpl = var.dpl;
4816 desc->p = var.present;
4817 desc->avl = var.avl;
4818 desc->l = var.l;
4819 desc->d = var.db;
4820 desc->g = var.g;
4821
4822 return true;
4823}
4824
1aa36616
AK		 4825static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4826 struct desc_struct *desc, u32 base3,
4827 int seg)
2dafc6c2 4828{
4bff1e86 4829 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4830 struct kvm_segment var;
4831
1aa36616 4832 var.selector = selector;
2dafc6c2 4833 var.base = get_desc_base(desc);
5601d05b
GN		 4834#ifdef CONFIG_X86_64
4835 var.base |= ((u64)base3) << 32;
4836#endif
2dafc6c2
GN		 4837 var.limit = get_desc_limit(desc);
4838 if (desc->g)
4839 var.limit = (var.limit << 12) | 0xfff;
4840 var.type = desc->type;
2dafc6c2
GN		 4841 var.dpl = desc->dpl;
4842 var.db = desc->d;
4843 var.s = desc->s;
4844 var.l = desc->l;
4845 var.g = desc->g;
4846 var.avl = desc->avl;
4847 var.present = desc->p;
4848 var.unusable = !var.present;
4849 var.padding = 0;
4850
4851 kvm_set_segment(vcpu, &var, seg);
4852 return;
4853}
4854
717746e3
AK		 4855static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4856 u32 msr_index, u64 *pdata)
4857{
609e36d3
PB		 4858 struct msr_data msr;
4859 int r;
4860
4861 msr.index = msr_index;
4862 msr.host_initiated = false;
4863 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4864 if (r)
4865 return r;
4866
4867 *pdata = msr.data;
4868 return 0;
717746e3
AK		 4869}
4870
4871static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4872 u32 msr_index, u64 data)
4873{
8fe8ab46
WA		 4874 struct msr_data msr;
4875
4876 msr.data = data;
4877 msr.index = msr_index;
4878 msr.host_initiated = false;
4879 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4880}
4881
64d60670
PB		 4882static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4883{
4884 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4885
4886 return vcpu->arch.smbase;
4887}
4888
4889static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4890{
4891 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4892
4893 vcpu->arch.smbase = smbase;
4894}
4895
67f4d428
NA		 4896static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4897 u32 pmc)
4898{
c6702c9d 4899 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4900}
4901
222d21aa
AK		 4902static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4903 u32 pmc, u64 *pdata)
4904{
c6702c9d 4905 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4906}
4907
6c3287f7
AK		 4908static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4909{
4910 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4911}
4912
5037f6f3
AK		 4913static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4914{
4915 preempt_disable();
5197b808 4916 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4917 /*
4918 * CR0.TS may reference the host fpu state, not the guest fpu state,
4919 * so it may be clear at this point.
4920 */
4921 clts();
4922}
4923
4924static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4925{
4926 preempt_enable();
4927}
4928
2953538e 4929static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4930 struct x86_instruction_info *info,
c4f035c6
AK		 4931 enum x86_intercept_stage stage)
4932{
2953538e 4933 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4934}
4935
0017f93a 4936static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4937 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4938{
0017f93a 4939 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4940}
4941
dd856efa
AK		 4942static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4943{
4944 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4945}
4946
4947static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4948{
4949 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4950}
4951
801806d9
NA		 4952static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4953{
4954 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4955}
4956
0225fb50 4957static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4958 .read_gpr = emulator_read_gpr,
4959 .write_gpr = emulator_write_gpr,
1871c602 4960 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4961 .write_std = kvm_write_guest_virt_system,
7a036a6f 4962 .read_phys = kvm_read_guest_phys_system,
1871c602 4963 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4964 .read_emulated = emulator_read_emulated,
4965 .write_emulated = emulator_write_emulated,
4966 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4967 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4968 .pio_in_emulated = emulator_pio_in_emulated,
4969 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4970 .get_segment = emulator_get_segment,
4971 .set_segment = emulator_set_segment,
5951c442 4972 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4973 .get_gdt = emulator_get_gdt,
160ce1f1 4974 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4975 .set_gdt = emulator_set_gdt,
4976 .set_idt = emulator_set_idt,
52a46617
GN		 4977 .get_cr = emulator_get_cr,
4978 .set_cr = emulator_set_cr,
9c537244 4979 .cpl = emulator_get_cpl,
35aa5375
GN		 4980 .get_dr = emulator_get_dr,
4981 .set_dr = emulator_set_dr,
64d60670
PB		 4982 .get_smbase = emulator_get_smbase,
4983 .set_smbase = emulator_set_smbase,
717746e3
AK		 4984 .set_msr = emulator_set_msr,
4985 .get_msr = emulator_get_msr,
67f4d428 4986 .check_pmc = emulator_check_pmc,
222d21aa 4987 .read_pmc = emulator_read_pmc,
6c3287f7 4988 .halt = emulator_halt,
bcaf5cc5 4989 .wbinvd = emulator_wbinvd,
d6aa1000 4990 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4991 .get_fpu = emulator_get_fpu,
4992 .put_fpu = emulator_put_fpu,
c4f035c6 4993 .intercept = emulator_intercept,
bdb42f5a 4994 .get_cpuid = emulator_get_cpuid,
801806d9 4995 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 4996};
4997
95cb2295
GN		 4998static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4999{
37ccdcbe 5000 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5001 /*
5002 * an sti; sti; sequence only disable interrupts for the first
5003 * instruction. So, if the last instruction, be it emulated or
5004 * not, left the system with the INT_STI flag enabled, it
5005 * means that the last instruction is an sti. We should not
5006 * leave the flag on in this case. The same goes for mov ss
5007 */
37ccdcbe
PB		 5008 if (int_shadow & mask)
5009 mask = 0;
6addfc42 5010 if (unlikely(int_shadow || mask)) {
95cb2295 5011 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5012 if (!mask)
5013 kvm_make_request(KVM_REQ_EVENT, vcpu);
5014 }
95cb2295
GN		 5015}
5016
ef54bcfe 5017static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5018{
5019 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5020 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5021 return kvm_propagate_fault(vcpu, &ctxt->exception);
5022
5023 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5024 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5025 ctxt->exception.error_code);
54b8486f 5026 else
da9cb575 5027 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5028 return false;
54b8486f
GN		 5029}
5030
8ec4722d
MG		 5031static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5032{
adf52235 5033 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5034 int cs_db, cs_l;
5035
8ec4722d
MG		 5036 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5037
adf52235
TY		 5038 ctxt->eflags = kvm_get_rflags(vcpu);
5039 ctxt->eip = kvm_rip_read(vcpu);
5040 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5041 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5042 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5043 cs_db ? X86EMUL_MODE_PROT32 :
5044 X86EMUL_MODE_PROT16;
a584539b 5045 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5046 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5047 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5048 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5049
dd856efa 5050 init_decode_cache(ctxt);
7ae441ea 5051 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5052}
5053
71f9833b 5054int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5055{
9d74191a 5056 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5057 int ret;
5058
5059 init_emulate_ctxt(vcpu);
5060
9dac77fa
AK		 5061 ctxt->op_bytes = 2;
5062 ctxt->ad_bytes = 2;
5063 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5064 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5065
5066 if (ret != X86EMUL_CONTINUE)
5067 return EMULATE_FAIL;
5068
9dac77fa 5069 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5070 kvm_rip_write(vcpu, ctxt->eip);
5071 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5072
5073 if (irq == NMI_VECTOR)
7460fb4a 5074 vcpu->arch.nmi_pending = 0;
63995653
MG		 5075 else
5076 vcpu->arch.interrupt.pending = false;
5077
5078 return EMULATE_DONE;
5079}
5080EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5081
6d77dbfc
GN		 5082static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5083{
fc3a9157
JR		 5084 int r = EMULATE_DONE;
5085
6d77dbfc
GN		 5086 ++vcpu->stat.insn_emulation_fail;
5087 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5088 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5089 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5090 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5091 vcpu->run->internal.ndata = 0;
5092 r = EMULATE_FAIL;
5093 }
6d77dbfc 5094 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5095
5096 return r;
6d77dbfc
GN		 5097}
5098
93c05d3e 5099static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5100 bool write_fault_to_shadow_pgtable,
5101 int emulation_type)
a6f177ef 5102{
95b3cf69 5103 gpa_t gpa = cr2;
8e3d9d06 5104 pfn_t pfn;
a6f177ef 5105
991eebf9
GN		 5106 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5107 return false;
5108
95b3cf69
XG		 5109 if (!vcpu->arch.mmu.direct_map) {
5110 /*
5111 * Write permission should be allowed since only
5112 * write access need to be emulated.
5113 */
5114 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5115
95b3cf69
XG		 5116 /*
5117 * If the mapping is invalid in guest, let cpu retry
5118 * it to generate fault.
5119 */
5120 if (gpa == UNMAPPED_GVA)
5121 return true;
5122 }
a6f177ef 5123
8e3d9d06
XG		 5124 /*
5125 * Do not retry the unhandleable instruction if it faults on the
5126 * readonly host memory, otherwise it will goto a infinite loop:
5127 * retry instruction -> write #PF -> emulation fail -> retry
5128 * instruction -> ...
5129 */
5130 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5131
5132 /*
5133 * If the instruction failed on the error pfn, it can not be fixed,
5134 * report the error to userspace.
5135 */
5136 if (is_error_noslot_pfn(pfn))
5137 return false;
5138
5139 kvm_release_pfn_clean(pfn);
5140
5141 /* The instructions are well-emulated on direct mmu. */
5142 if (vcpu->arch.mmu.direct_map) {
5143 unsigned int indirect_shadow_pages;
5144
5145 spin_lock(&vcpu->kvm->mmu_lock);
5146 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5147 spin_unlock(&vcpu->kvm->mmu_lock);
5148
5149 if (indirect_shadow_pages)
5150 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5151
a6f177ef 5152 return true;
8e3d9d06 5153 }
a6f177ef 5154
95b3cf69
XG		 5155 /*
5156 * if emulation was due to access to shadowed page table
5157 * and it failed try to unshadow page and re-enter the
5158 * guest to let CPU execute the instruction.
5159 */
5160 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5161
5162 /*
5163 * If the access faults on its page table, it can not
5164 * be fixed by unprotecting shadow page and it should
5165 * be reported to userspace.
5166 */
5167 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5168}
5169
1cb3f3ae
XG		 5170static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5171 unsigned long cr2, int emulation_type)
5172{
5173 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5174 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5175
5176 last_retry_eip = vcpu->arch.last_retry_eip;
5177 last_retry_addr = vcpu->arch.last_retry_addr;
5178
5179 /*
5180 * If the emulation is caused by #PF and it is non-page_table
5181 * writing instruction, it means the VM-EXIT is caused by shadow
5182 * page protected, we can zap the shadow page and retry this
5183 * instruction directly.
5184 *
5185 * Note: if the guest uses a non-page-table modifying instruction
5186 * on the PDE that points to the instruction, then we will unmap
5187 * the instruction and go to an infinite loop. So, we cache the
5188 * last retried eip and the last fault address, if we meet the eip
5189 * and the address again, we can break out of the potential infinite
5190 * loop.
5191 */
5192 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5193
5194 if (!(emulation_type & EMULTYPE_RETRY))
5195 return false;
5196
5197 if (x86_page_table_writing_insn(ctxt))
5198 return false;
5199
5200 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5201 return false;
5202
5203 vcpu->arch.last_retry_eip = ctxt->eip;
5204 vcpu->arch.last_retry_addr = cr2;
5205
5206 if (!vcpu->arch.mmu.direct_map)
5207 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5208
22368028 5209 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5210
5211 return true;
5212}
5213
716d51ab
GN		 5214static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5215static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5216
64d60670 5217static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5218{
64d60670 5219 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5220 /* This is a good place to trace that we are exiting SMM. */
5221 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5222
64d60670
PB		 5223 if (unlikely(vcpu->arch.smi_pending)) {
5224 kvm_make_request(KVM_REQ_SMI, vcpu);
5225 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5226 } else {
5227 /* Process a latched INIT, if any. */
5228 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5229 }
5230 }
699023e2
PB		 5231
5232 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5233}
5234
5235static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5236{
5237 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5238
a584539b 5239 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5240
5241 if (changed & HF_SMM_MASK)
5242 kvm_smm_changed(vcpu);
a584539b
PB		 5243}
5244
4a1e10d5
PB		 5245static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5246 unsigned long *db)
5247{
5248 u32 dr6 = 0;
5249 int i;
5250 u32 enable, rwlen;
5251
5252 enable = dr7;
5253 rwlen = dr7 >> 16;
5254 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5255 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5256 dr6 |= (1 << i);
5257 return dr6;
5258}
5259
6addfc42 5260static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5261{
5262 struct kvm_run *kvm_run = vcpu->run;
5263
5264 /*
6addfc42
PB		 5265 * rflags is the old, "raw" value of the flags. The new value has
5266 * not been saved yet.
663f4c61
PB		 5267 *
5268 * This is correct even for TF set by the guest, because "the
5269 * processor will not generate this exception after the instruction
5270 * that sets the TF flag".
5271 */
663f4c61
PB		 5272 if (unlikely(rflags & X86_EFLAGS_TF)) {
5273 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5274 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5275 DR6_RTM;
663f4c61
PB		 5276 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5277 kvm_run->debug.arch.exception = DB_VECTOR;
5278 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5279 *r = EMULATE_USER_EXIT;
5280 } else {
5281 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5282 /*
5283 * "Certain debug exceptions may clear bit 0-3. The
5284 * remaining contents of the DR6 register are never
5285 * cleared by the processor".
5286 */
5287 vcpu->arch.dr6 &= ~15;
6f43ed01 5288 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5289 kvm_queue_exception(vcpu, DB_VECTOR);
5290 }
5291 }
5292}
5293
4a1e10d5
PB		 5294static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5295{
4a1e10d5
PB		 5296 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5297 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5298 struct kvm_run *kvm_run = vcpu->run;
5299 unsigned long eip = kvm_get_linear_rip(vcpu);
5300 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5301 vcpu->arch.guest_debug_dr7,
5302 vcpu->arch.eff_db);
5303
5304 if (dr6 != 0) {
6f43ed01 5305 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5306 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5307 kvm_run->debug.arch.exception = DB_VECTOR;
5308 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5309 *r = EMULATE_USER_EXIT;
5310 return true;
5311 }
5312 }
5313
4161a569
NA		 5314 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5315 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5316 unsigned long eip = kvm_get_linear_rip(vcpu);
5317 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5318 vcpu->arch.dr7,
5319 vcpu->arch.db);
5320
5321 if (dr6 != 0) {
5322 vcpu->arch.dr6 &= ~15;
6f43ed01 5323 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5324 kvm_queue_exception(vcpu, DB_VECTOR);
5325 *r = EMULATE_DONE;
5326 return true;
5327 }
5328 }
5329
5330 return false;
5331}
5332
51d8b661
AP		 5333int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5334 unsigned long cr2,
dc25e89e
AP		 5335 int emulation_type,
5336 void *insn,
5337 int insn_len)
bbd9b64e 5338{
95cb2295 5339 int r;
9d74191a 5340 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5341 bool writeback = true;
93c05d3e 5342 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5343
93c05d3e
XG		 5344 /*
5345 * Clear write_fault_to_shadow_pgtable here to ensure it is
5346 * never reused.
5347 */
5348 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5349 kvm_clear_exception_queue(vcpu);
8d7d8102 5350
571008da 5351 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5352 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5353
5354 /*
5355 * We will reenter on the same instruction since
5356 * we do not set complete_userspace_io. This does not
5357 * handle watchpoints yet, those would be handled in
5358 * the emulate_ops.
5359 */
5360 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5361 return r;
5362
9d74191a
TY		 5363 ctxt->interruptibility = 0;
5364 ctxt->have_exception = false;
e0ad0b47 5365 ctxt->exception.vector = -1;
9d74191a 5366 ctxt->perm_ok = false;
bbd9b64e 5367
b51e974f 5368 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5369
9d74191a 5370 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5371
e46479f8 5372 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5373 ++vcpu->stat.insn_emulation;
1d2887e2 5374 if (r != EMULATION_OK) {
4005996e
AK		 5375 if (emulation_type & EMULTYPE_TRAP_UD)
5376 return EMULATE_FAIL;
991eebf9
GN		 5377 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5378 emulation_type))
bbd9b64e 5379 return EMULATE_DONE;
6d77dbfc
GN		 5380 if (emulation_type & EMULTYPE_SKIP)
5381 return EMULATE_FAIL;
5382 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5383 }
5384 }
5385
ba8afb6b 5386 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5387 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5388 if (ctxt->eflags & X86_EFLAGS_RF)
5389 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5390 return EMULATE_DONE;
5391 }
5392
1cb3f3ae
XG		 5393 if (retry_instruction(ctxt, cr2, emulation_type))
5394 return EMULATE_DONE;
5395
7ae441ea 5396 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5397 changes registers values during IO operation */
7ae441ea
GN		 5398 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5399 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5400 emulator_invalidate_register_cache(ctxt);
7ae441ea 5401 }
4d2179e1 5402
5cd21917 5403restart:
9d74191a 5404 r = x86_emulate_insn(ctxt);
bbd9b64e 5405
775fde86
JR		 5406 if (r == EMULATION_INTERCEPTED)
5407 return EMULATE_DONE;
5408
d2ddd1c4 5409 if (r == EMULATION_FAILED) {
991eebf9
GN		 5410 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5411 emulation_type))
c3cd7ffa
GN		 5412 return EMULATE_DONE;
5413
6d77dbfc 5414 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5415 }
5416
9d74191a 5417 if (ctxt->have_exception) {
d2ddd1c4 5418 r = EMULATE_DONE;
ef54bcfe
PB		 5419 if (inject_emulated_exception(vcpu))
5420 return r;
d2ddd1c4 5421 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5422 if (!vcpu->arch.pio.in) {
5423 /* FIXME: return into emulator if single-stepping. */
3457e419 5424 vcpu->arch.pio.count = 0;
0912c977 5425 } else {
7ae441ea 5426 writeback = false;
716d51ab
GN		 5427 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5428 }
ac0a48c3 5429 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5430 } else if (vcpu->mmio_needed) {
5431 if (!vcpu->mmio_is_write)
5432 writeback = false;
ac0a48c3 5433 r = EMULATE_USER_EXIT;
716d51ab 5434 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5435 } else if (r == EMULATION_RESTART)
5cd21917 5436 goto restart;
d2ddd1c4
GN		 5437 else
5438 r = EMULATE_DONE;
f850e2e6 5439
7ae441ea 5440 if (writeback) {
6addfc42 5441 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5442 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5443 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5444 if (vcpu->arch.hflags != ctxt->emul_flags)
5445 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5446 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5447 if (r == EMULATE_DONE)
6addfc42 5448 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5449 if (!ctxt->have_exception ||
5450 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5451 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5452
5453 /*
5454 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5455 * do nothing, and it will be requested again as soon as
5456 * the shadow expires. But we still need to check here,
5457 * because POPF has no interrupt shadow.
5458 */
5459 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5460 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5461 } else
5462 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5463
5464 return r;
de7d789a 5465}
51d8b661 5466EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5467
cf8f70bf 5468int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5469{
cf8f70bf 5470 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5471 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5472 size, port, &val, 1);
cf8f70bf 5473 /* do not return to emulator after return from userspace */
7972995b 5474 vcpu->arch.pio.count = 0;
de7d789a
CO		 5475 return ret;
5476}
cf8f70bf 5477EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5478
8cfdc000
ZA		 5479static void tsc_bad(void *info)
5480{
0a3aee0d 5481 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5482}
5483
5484static void tsc_khz_changed(void *data)
c8076604 5485{
8cfdc000
ZA		 5486 struct cpufreq_freqs *freq = data;
5487 unsigned long khz = 0;
5488
5489 if (data)
5490 khz = freq->new;
5491 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5492 khz = cpufreq_quick_get(raw_smp_processor_id());
5493 if (!khz)
5494 khz = tsc_khz;
0a3aee0d 5495 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5496}
5497
c8076604
GH		 5498static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5499 void *data)
5500{
5501 struct cpufreq_freqs *freq = data;
5502 struct kvm *kvm;
5503 struct kvm_vcpu *vcpu;
5504 int i, send_ipi = 0;
5505
8cfdc000
ZA		 5506 /*
5507 * We allow guests to temporarily run on slowing clocks,
5508 * provided we notify them after, or to run on accelerating
5509 * clocks, provided we notify them before. Thus time never
5510 * goes backwards.
5511 *
5512 * However, we have a problem. We can't atomically update
5513 * the frequency of a given CPU from this function; it is
5514 * merely a notifier, which can be called from any CPU.
5515 * Changing the TSC frequency at arbitrary points in time
5516 * requires a recomputation of local variables related to
5517 * the TSC for each VCPU. We must flag these local variables
5518 * to be updated and be sure the update takes place with the
5519 * new frequency before any guests proceed.
5520 *
5521 * Unfortunately, the combination of hotplug CPU and frequency
5522 * change creates an intractable locking scenario; the order
5523 * of when these callouts happen is undefined with respect to
5524 * CPU hotplug, and they can race with each other. As such,
5525 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5526 * undefined; you can actually have a CPU frequency change take
5527 * place in between the computation of X and the setting of the
5528 * variable. To protect against this problem, all updates of
5529 * the per_cpu tsc_khz variable are done in an interrupt
5530 * protected IPI, and all callers wishing to update the value
5531 * must wait for a synchronous IPI to complete (which is trivial
5532 * if the caller is on the CPU already). This establishes the
5533 * necessary total order on variable updates.
5534 *
5535 * Note that because a guest time update may take place
5536 * anytime after the setting of the VCPU's request bit, the
5537 * correct TSC value must be set before the request. However,
5538 * to ensure the update actually makes it to any guest which
5539 * starts running in hardware virtualization between the set
5540 * and the acquisition of the spinlock, we must also ping the
5541 * CPU after setting the request bit.
5542 *
5543 */
5544
c8076604
GH		 5545 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5546 return 0;
5547 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5548 return 0;
8cfdc000
ZA		 5549
5550 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5551
2f303b74 5552 spin_lock(&kvm_lock);
c8076604 5553 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5554 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5555 if (vcpu->cpu != freq->cpu)
5556 continue;
c285545f 5557 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5558 if (vcpu->cpu != smp_processor_id())
8cfdc000 5559 send_ipi = 1;
c8076604
GH		 5560 }
5561 }
2f303b74 5562 spin_unlock(&kvm_lock);
c8076604
GH		 5563
5564 if (freq->old < freq->new && send_ipi) {
5565 /*
5566 * We upscale the frequency. Must make the guest
5567 * doesn't see old kvmclock values while running with
5568 * the new frequency, otherwise we risk the guest sees
5569 * time go backwards.
5570 *
5571 * In case we update the frequency for another cpu
5572 * (which might be in guest context) send an interrupt
5573 * to kick the cpu out of guest context. Next time
5574 * guest context is entered kvmclock will be updated,
5575 * so the guest will not see stale values.
5576 */
8cfdc000 5577 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5578 }
5579 return 0;
5580}
5581
5582static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5583 .notifier_call = kvmclock_cpufreq_notifier
5584};
5585
5586static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5587 unsigned long action, void *hcpu)
5588{
5589 unsigned int cpu = (unsigned long)hcpu;
5590
5591 switch (action) {
5592 case CPU_ONLINE:
5593 case CPU_DOWN_FAILED:
5594 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5595 break;
5596 case CPU_DOWN_PREPARE:
5597 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5598 break;
5599 }
5600 return NOTIFY_OK;
5601}
5602
5603static struct notifier_block kvmclock_cpu_notifier_block = {
5604 .notifier_call = kvmclock_cpu_notifier,
5605 .priority = -INT_MAX
c8076604
GH		 5606};
5607
b820cc0c
ZA		 5608static void kvm_timer_init(void)
5609{
5610 int cpu;
5611
c285545f 5612 max_tsc_khz = tsc_khz;
460dd42e
SB		 5613
5614 cpu_notifier_register_begin();
b820cc0c 5615 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5616#ifdef CONFIG_CPU_FREQ
5617 struct cpufreq_policy policy;
5618 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5619 cpu = get_cpu();
5620 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5621 if (policy.cpuinfo.max_freq)
5622 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5623 put_cpu();
c285545f 5624#endif
b820cc0c
ZA		 5625 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5626 CPUFREQ_TRANSITION_NOTIFIER);
5627 }
c285545f 5628 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5629 for_each_online_cpu(cpu)
5630 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5631
5632 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5633 cpu_notifier_register_done();
5634
b820cc0c
ZA		 5635}
5636
ff9d07a0
ZY		 5637static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5638
f5132b01 5639int kvm_is_in_guest(void)
ff9d07a0 5640{
086c9855 5641 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5642}
5643
5644static int kvm_is_user_mode(void)
5645{
5646 int user_mode = 3;
dcf46b94 5647
086c9855
AS		 5648 if (__this_cpu_read(current_vcpu))
5649 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5650
ff9d07a0
ZY		 5651 return user_mode != 0;
5652}
5653
5654static unsigned long kvm_get_guest_ip(void)
5655{
5656 unsigned long ip = 0;
dcf46b94 5657
086c9855
AS		 5658 if (__this_cpu_read(current_vcpu))
5659 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5660
ff9d07a0
ZY		 5661 return ip;
5662}
5663
5664static struct perf_guest_info_callbacks kvm_guest_cbs = {
5665 .is_in_guest = kvm_is_in_guest,
5666 .is_user_mode = kvm_is_user_mode,
5667 .get_guest_ip = kvm_get_guest_ip,
5668};
5669
5670void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5671{
086c9855 5672 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5673}
5674EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5675
5676void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5677{
086c9855 5678 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5679}
5680EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5681
ce88decf
XG		 5682static void kvm_set_mmio_spte_mask(void)
5683{
5684 u64 mask;
5685 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5686
5687 /*
5688 * Set the reserved bits and the present bit of an paging-structure
5689 * entry to generate page fault with PFER.RSV = 1.
5690 */
885032b9 5691 /* Mask the reserved physical address bits. */
d1431483 5692 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5693
5694 /* Bit 62 is always reserved for 32bit host. */
5695 mask |= 0x3ull << 62;
5696
5697 /* Set the present bit. */
ce88decf
XG		 5698 mask |= 1ull;
5699
5700#ifdef CONFIG_X86_64
5701 /*
5702 * If reserved bit is not supported, clear the present bit to disable
5703 * mmio page fault.
5704 */
5705 if (maxphyaddr == 52)
5706 mask &= ~1ull;
5707#endif
5708
5709 kvm_mmu_set_mmio_spte_mask(mask);
5710}
5711
16e8d74d
MT		 5712#ifdef CONFIG_X86_64
5713static void pvclock_gtod_update_fn(struct work_struct *work)
5714{
d828199e
MT		 5715 struct kvm *kvm;
5716
5717 struct kvm_vcpu *vcpu;
5718 int i;
5719
2f303b74 5720 spin_lock(&kvm_lock);
d828199e
MT		 5721 list_for_each_entry(kvm, &vm_list, vm_list)
5722 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5723 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5724 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5725 spin_unlock(&kvm_lock);
16e8d74d
MT		 5726}
5727
5728static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5729
5730/*
5731 * Notification about pvclock gtod data update.
5732 */
5733static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5734 void *priv)
5735{
5736 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5737 struct timekeeper *tk = priv;
5738
5739 update_pvclock_gtod(tk);
5740
5741 /* disable master clock if host does not trust, or does not
5742 * use, TSC clocksource
5743 */
5744 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5745 atomic_read(&kvm_guest_has_master_clock) != 0)
5746 queue_work(system_long_wq, &pvclock_gtod_work);
5747
5748 return 0;
5749}
5750
5751static struct notifier_block pvclock_gtod_notifier = {
5752 .notifier_call = pvclock_gtod_notify,
5753};
5754#endif
5755
f8c16bba 5756int kvm_arch_init(void *opaque)
043405e1 5757{
b820cc0c 5758 int r;
6b61edf7 5759 struct kvm_x86_ops *ops = opaque;
f8c16bba 5760
f8c16bba
ZX		 5761 if (kvm_x86_ops) {
5762 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5763 r = -EEXIST;
5764 goto out;
f8c16bba
ZX		 5765 }
5766
5767 if (!ops->cpu_has_kvm_support()) {
5768 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5769 r = -EOPNOTSUPP;
5770 goto out;
f8c16bba
ZX		 5771 }
5772 if (ops->disabled_by_bios()) {
5773 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5774 r = -EOPNOTSUPP;
5775 goto out;
f8c16bba
ZX		 5776 }
5777
013f6a5d
MT		 5778 r = -ENOMEM;
5779 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5780 if (!shared_msrs) {
5781 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5782 goto out;
5783 }
5784
97db56ce
AK		 5785 r = kvm_mmu_module_init();
5786 if (r)
013f6a5d 5787 goto out_free_percpu;
97db56ce 5788
ce88decf 5789 kvm_set_mmio_spte_mask();
97db56ce 5790
f8c16bba 5791 kvm_x86_ops = ops;
920c8377 5792
7b52345e 5793 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5794 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5795
b820cc0c 5796 kvm_timer_init();
c8076604 5797
ff9d07a0
ZY		 5798 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5799
2acf923e
DC		 5800 if (cpu_has_xsave)
5801 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5802
c5cc421b 5803 kvm_lapic_init();
16e8d74d
MT		 5804#ifdef CONFIG_X86_64
5805 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5806#endif
5807
f8c16bba 5808 return 0;
56c6d28a 5809
013f6a5d
MT		 5810out_free_percpu:
5811 free_percpu(shared_msrs);
56c6d28a 5812out:
56c6d28a 5813 return r;
043405e1 5814}
8776e519 5815
f8c16bba
ZX		 5816void kvm_arch_exit(void)
5817{
ff9d07a0
ZY		 5818 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5819
888d256e
JK		 5820 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5821 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5822 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5823 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5824#ifdef CONFIG_X86_64
5825 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5826#endif
f8c16bba 5827 kvm_x86_ops = NULL;
56c6d28a 5828 kvm_mmu_module_exit();
013f6a5d 5829 free_percpu(shared_msrs);
56c6d28a 5830}
f8c16bba 5831
5cb56059 5832int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5833{
5834 ++vcpu->stat.halt_exits;
35754c98 5835 if (lapic_in_kernel(vcpu)) {
a4535290 5836 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5837 return 1;
5838 } else {
5839 vcpu->run->exit_reason = KVM_EXIT_HLT;
5840 return 0;
5841 }
5842}
5cb56059
JS		 5843EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5844
5845int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5846{
5847 kvm_x86_ops->skip_emulated_instruction(vcpu);
5848 return kvm_vcpu_halt(vcpu);
5849}
8776e519
HB		 5850EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5851
6aef266c
SV		 5852/*
5853 * kvm_pv_kick_cpu_op: Kick a vcpu.
5854 *
5855 * @apicid - apicid of vcpu to be kicked.
5856 */
5857static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5858{
24d2166b 5859 struct kvm_lapic_irq lapic_irq;
6aef266c 5860
24d2166b
R		 5861 lapic_irq.shorthand = 0;
5862 lapic_irq.dest_mode = 0;
5863 lapic_irq.dest_id = apicid;
93bbf0b8 5864 lapic_irq.msi_redir_hint = false;
6aef266c 5865
24d2166b 5866 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5867 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5868}
5869
8776e519
HB		 5870int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5871{
5872 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5873 int op_64_bit, r = 1;
8776e519 5874
5cb56059
JS		 5875 kvm_x86_ops->skip_emulated_instruction(vcpu);
5876
55cd8e5a
GN		 5877 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5878 return kvm_hv_hypercall(vcpu);
5879
5fdbf976
MT		 5880 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5881 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5882 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5883 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5884 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5885
229456fc 5886 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5887
a449c7aa
NA		 5888 op_64_bit = is_64_bit_mode(vcpu);
5889 if (!op_64_bit) {
8776e519
HB		 5890 nr &= 0xFFFFFFFF;
5891 a0 &= 0xFFFFFFFF;
5892 a1 &= 0xFFFFFFFF;
5893 a2 &= 0xFFFFFFFF;
5894 a3 &= 0xFFFFFFFF;
5895 }
5896
07708c4a
JK		 5897 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5898 ret = -KVM_EPERM;
5899 goto out;
5900 }
5901
8776e519 5902 switch (nr) {
b93463aa
AK		 5903 case KVM_HC_VAPIC_POLL_IRQ:
5904 ret = 0;
5905 break;
6aef266c
SV		 5906 case KVM_HC_KICK_CPU:
5907 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5908 ret = 0;
5909 break;
8776e519
HB		 5910 default:
5911 ret = -KVM_ENOSYS;
5912 break;
5913 }
07708c4a 5914out:
a449c7aa
NA		 5915 if (!op_64_bit)
5916 ret = (u32)ret;
5fdbf976 5917 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5918 ++vcpu->stat.hypercalls;
2f333bcb 5919 return r;
8776e519
HB		 5920}
5921EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5922
b6785def 5923static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5924{
d6aa1000 5925 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5926 char instruction[3];
5fdbf976 5927 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5928
8776e519 5929 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5930
9d74191a 5931 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5932}
5933
851ba692 5934static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5935{
782d422b
MG		 5936 return vcpu->run->request_interrupt_window &&
5937 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 5938}
5939
851ba692 5940static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5941{
851ba692
AK		 5942 struct kvm_run *kvm_run = vcpu->run;
5943
91586a3b 5944 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5945 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5946 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5947 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 5948 kvm_run->ready_for_interrupt_injection =
5949 pic_in_kernel(vcpu->kvm) ||
782d422b 5950 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 5951}
5952
95ba8273
GN		 5953static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5954{
5955 int max_irr, tpr;
5956
5957 if (!kvm_x86_ops->update_cr8_intercept)
5958 return;
5959
88c808fd
AK		 5960 if (!vcpu->arch.apic)
5961 return;
5962
8db3baa2
GN		 5963 if (!vcpu->arch.apic->vapic_addr)
5964 max_irr = kvm_lapic_find_highest_irr(vcpu);
5965 else
5966 max_irr = -1;
95ba8273
GN		 5967
5968 if (max_irr != -1)
5969 max_irr >>= 4;
5970
5971 tpr = kvm_lapic_get_cr8(vcpu);
5972
5973 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5974}
5975
b6b8a145 5976static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5977{
b6b8a145
JK		 5978 int r;
5979
95ba8273 5980 /* try to reinject previous events if any */
b59bb7bd 5981 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5982 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5983 vcpu->arch.exception.has_error_code,
5984 vcpu->arch.exception.error_code);
d6e8c854
NA		 5985
5986 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5987 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5988 X86_EFLAGS_RF);
5989
6bdf0662
NA		 5990 if (vcpu->arch.exception.nr == DB_VECTOR &&
5991 (vcpu->arch.dr7 & DR7_GD)) {
5992 vcpu->arch.dr7 &= ~DR7_GD;
5993 kvm_update_dr7(vcpu);
5994 }
5995
b59bb7bd
GN		 5996 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5997 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5998 vcpu->arch.exception.error_code,
5999 vcpu->arch.exception.reinject);
b6b8a145 6000 return 0;
b59bb7bd
GN		 6001 }
6002
95ba8273
GN		 6003 if (vcpu->arch.nmi_injected) {
6004 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6005 return 0;
95ba8273
GN		 6006 }
6007
6008 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6009 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6010 return 0;
6011 }
6012
6013 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6014 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6015 if (r != 0)
6016 return r;
95ba8273
GN		 6017 }
6018
6019 /* try to inject new event if pending */
6020 if (vcpu->arch.nmi_pending) {
6021 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6022 --vcpu->arch.nmi_pending;
95ba8273
GN		 6023 vcpu->arch.nmi_injected = true;
6024 kvm_x86_ops->set_nmi(vcpu);
6025 }
c7c9c56c 6026 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6027 /*
6028 * Because interrupts can be injected asynchronously, we are
6029 * calling check_nested_events again here to avoid a race condition.
6030 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6031 * proposal and current concerns. Perhaps we should be setting
6032 * KVM_REQ_EVENT only on certain events and not unconditionally?
6033 */
6034 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6035 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6036 if (r != 0)
6037 return r;
6038 }
95ba8273 6039 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6040 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6041 false);
6042 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6043 }
6044 }
b6b8a145 6045 return 0;
95ba8273
GN		 6046}
6047
7460fb4a
AK		 6048static void process_nmi(struct kvm_vcpu *vcpu)
6049{
6050 unsigned limit = 2;
6051
6052 /*
6053 * x86 is limited to one NMI running, and one NMI pending after it.
6054 * If an NMI is already in progress, limit further NMIs to just one.
6055 * Otherwise, allow two (and we'll inject the first one immediately).
6056 */
6057 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6058 limit = 1;
6059
6060 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6061 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6062 kvm_make_request(KVM_REQ_EVENT, vcpu);
6063}
6064
660a5d51
PB		 6065#define put_smstate(type, buf, offset, val) \
6066 *(type *)((buf) + (offset) - 0x7e00) = val
6067
6068static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6069{
6070 u32 flags = 0;
6071 flags |= seg->g << 23;
6072 flags |= seg->db << 22;
6073 flags |= seg->l << 21;
6074 flags |= seg->avl << 20;
6075 flags |= seg->present << 15;
6076 flags |= seg->dpl << 13;
6077 flags |= seg->s << 12;
6078 flags |= seg->type << 8;
6079 return flags;
6080}
6081
6082static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6083{
6084 struct kvm_segment seg;
6085 int offset;
6086
6087 kvm_get_segment(vcpu, &seg, n);
6088 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6089
6090 if (n < 3)
6091 offset = 0x7f84 + n * 12;
6092 else
6093 offset = 0x7f2c + (n - 3) * 12;
6094
6095 put_smstate(u32, buf, offset + 8, seg.base);
6096 put_smstate(u32, buf, offset + 4, seg.limit);
6097 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6098}
6099
efbb288a 6100#ifdef CONFIG_X86_64
660a5d51
PB		 6101static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6102{
6103 struct kvm_segment seg;
6104 int offset;
6105 u16 flags;
6106
6107 kvm_get_segment(vcpu, &seg, n);
6108 offset = 0x7e00 + n * 16;
6109
6110 flags = process_smi_get_segment_flags(&seg) >> 8;
6111 put_smstate(u16, buf, offset, seg.selector);
6112 put_smstate(u16, buf, offset + 2, flags);
6113 put_smstate(u32, buf, offset + 4, seg.limit);
6114 put_smstate(u64, buf, offset + 8, seg.base);
6115}
efbb288a 6116#endif
660a5d51
PB		 6117
6118static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6119{
6120 struct desc_ptr dt;
6121 struct kvm_segment seg;
6122 unsigned long val;
6123 int i;
6124
6125 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6126 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6127 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6128 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6129
6130 for (i = 0; i < 8; i++)
6131 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6132
6133 kvm_get_dr(vcpu, 6, &val);
6134 put_smstate(u32, buf, 0x7fcc, (u32)val);
6135 kvm_get_dr(vcpu, 7, &val);
6136 put_smstate(u32, buf, 0x7fc8, (u32)val);
6137
6138 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6139 put_smstate(u32, buf, 0x7fc4, seg.selector);
6140 put_smstate(u32, buf, 0x7f64, seg.base);
6141 put_smstate(u32, buf, 0x7f60, seg.limit);
6142 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6143
6144 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6145 put_smstate(u32, buf, 0x7fc0, seg.selector);
6146 put_smstate(u32, buf, 0x7f80, seg.base);
6147 put_smstate(u32, buf, 0x7f7c, seg.limit);
6148 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6149
6150 kvm_x86_ops->get_gdt(vcpu, &dt);
6151 put_smstate(u32, buf, 0x7f74, dt.address);
6152 put_smstate(u32, buf, 0x7f70, dt.size);
6153
6154 kvm_x86_ops->get_idt(vcpu, &dt);
6155 put_smstate(u32, buf, 0x7f58, dt.address);
6156 put_smstate(u32, buf, 0x7f54, dt.size);
6157
6158 for (i = 0; i < 6; i++)
6159 process_smi_save_seg_32(vcpu, buf, i);
6160
6161 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6162
6163 /* revision id */
6164 put_smstate(u32, buf, 0x7efc, 0x00020000);
6165 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6166}
6167
6168static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6169{
6170#ifdef CONFIG_X86_64
6171 struct desc_ptr dt;
6172 struct kvm_segment seg;
6173 unsigned long val;
6174 int i;
6175
6176 for (i = 0; i < 16; i++)
6177 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6178
6179 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6180 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6181
6182 kvm_get_dr(vcpu, 6, &val);
6183 put_smstate(u64, buf, 0x7f68, val);
6184 kvm_get_dr(vcpu, 7, &val);
6185 put_smstate(u64, buf, 0x7f60, val);
6186
6187 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6188 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6189 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6190
6191 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6192
6193 /* revision id */
6194 put_smstate(u32, buf, 0x7efc, 0x00020064);
6195
6196 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6197
6198 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6199 put_smstate(u16, buf, 0x7e90, seg.selector);
6200 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6201 put_smstate(u32, buf, 0x7e94, seg.limit);
6202 put_smstate(u64, buf, 0x7e98, seg.base);
6203
6204 kvm_x86_ops->get_idt(vcpu, &dt);
6205 put_smstate(u32, buf, 0x7e84, dt.size);
6206 put_smstate(u64, buf, 0x7e88, dt.address);
6207
6208 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6209 put_smstate(u16, buf, 0x7e70, seg.selector);
6210 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6211 put_smstate(u32, buf, 0x7e74, seg.limit);
6212 put_smstate(u64, buf, 0x7e78, seg.base);
6213
6214 kvm_x86_ops->get_gdt(vcpu, &dt);
6215 put_smstate(u32, buf, 0x7e64, dt.size);
6216 put_smstate(u64, buf, 0x7e68, dt.address);
6217
6218 for (i = 0; i < 6; i++)
6219 process_smi_save_seg_64(vcpu, buf, i);
6220#else
6221 WARN_ON_ONCE(1);
6222#endif
6223}
6224
64d60670
PB		 6225static void process_smi(struct kvm_vcpu *vcpu)
6226{
660a5d51 6227 struct kvm_segment cs, ds;
18c3626e 6228 struct desc_ptr dt;
660a5d51
PB		 6229 char buf[512];
6230 u32 cr0;
6231
64d60670
PB		 6232 if (is_smm(vcpu)) {
6233 vcpu->arch.smi_pending = true;
6234 return;
6235 }
6236
660a5d51
PB		 6237 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6238 vcpu->arch.hflags |= HF_SMM_MASK;
6239 memset(buf, 0, 512);
6240 if (guest_cpuid_has_longmode(vcpu))
6241 process_smi_save_state_64(vcpu, buf);
6242 else
6243 process_smi_save_state_32(vcpu, buf);
6244
54bf36aa 6245 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6246
6247 if (kvm_x86_ops->get_nmi_mask(vcpu))
6248 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6249 else
6250 kvm_x86_ops->set_nmi_mask(vcpu, true);
6251
6252 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6253 kvm_rip_write(vcpu, 0x8000);
6254
6255 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6256 kvm_x86_ops->set_cr0(vcpu, cr0);
6257 vcpu->arch.cr0 = cr0;
6258
6259 kvm_x86_ops->set_cr4(vcpu, 0);
6260
18c3626e
PB		 6261 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6262 dt.address = dt.size = 0;
6263 kvm_x86_ops->set_idt(vcpu, &dt);
6264
660a5d51
PB		 6265 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6266
6267 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6268 cs.base = vcpu->arch.smbase;
6269
6270 ds.selector = 0;
6271 ds.base = 0;
6272
6273 cs.limit = ds.limit = 0xffffffff;
6274 cs.type = ds.type = 0x3;
6275 cs.dpl = ds.dpl = 0;
6276 cs.db = ds.db = 0;
6277 cs.s = ds.s = 1;
6278 cs.l = ds.l = 0;
6279 cs.g = ds.g = 1;
6280 cs.avl = ds.avl = 0;
6281 cs.present = ds.present = 1;
6282 cs.unusable = ds.unusable = 0;
6283 cs.padding = ds.padding = 0;
6284
6285 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6286 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6287 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6288 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6289 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6290 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6291
6292 if (guest_cpuid_has_longmode(vcpu))
6293 kvm_x86_ops->set_efer(vcpu, 0);
6294
6295 kvm_update_cpuid(vcpu);
6296 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6297}
6298
3d81bc7e 6299static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6300{
3d81bc7e
YZ		 6301 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6302 return;
c7c9c56c 6303
3bb345f3 6304 memset(vcpu->arch.eoi_exit_bitmap, 0, 256 / 8);
c7c9c56c 6305
b053b2ae
SR		 6306 if (irqchip_split(vcpu->kvm))
6307 kvm_scan_ioapic_routes(vcpu, vcpu->arch.eoi_exit_bitmap);
db2bdcbb
RK		 6308 else {
6309 kvm_x86_ops->sync_pir_to_irr(vcpu);
b053b2ae 6310 kvm_ioapic_scan_entry(vcpu, vcpu->arch.eoi_exit_bitmap);
db2bdcbb 6311 }
3bb345f3 6312 kvm_x86_ops->load_eoi_exitmap(vcpu);
c7c9c56c
YZ		 6313}
6314
a70656b6
RK		 6315static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6316{
6317 ++vcpu->stat.tlb_flush;
6318 kvm_x86_ops->tlb_flush(vcpu);
6319}
6320
4256f43f
TC		 6321void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6322{
c24ae0dc
TC		 6323 struct page *page = NULL;
6324
35754c98 6325 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6326 return;
6327
4256f43f
TC		 6328 if (!kvm_x86_ops->set_apic_access_page_addr)
6329 return;
6330
c24ae0dc 6331 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6332 if (is_error_page(page))
6333 return;
c24ae0dc
TC		 6334 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6335
6336 /*
6337 * Do not pin apic access page in memory, the MMU notifier
6338 * will call us again if it is migrated or swapped out.
6339 */
6340 put_page(page);
4256f43f
TC		 6341}
6342EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6343
fe71557a
TC		 6344void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6345 unsigned long address)
6346{
c24ae0dc
TC		 6347 /*
6348 * The physical address of apic access page is stored in the VMCS.
6349 * Update it when it becomes invalid.
6350 */
6351 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6352 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6353}
6354
9357d939 6355/*
362c698f 6356 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6357 * exiting to the userspace. Otherwise, the value will be returned to the
6358 * userspace.
6359 */
851ba692 6360static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6361{
6362 int r;
62a193ed
MG		 6363 bool req_int_win =
6364 dm_request_for_irq_injection(vcpu) &&
6365 kvm_cpu_accept_dm_intr(vcpu);
6366
730dca42 6367 bool req_immediate_exit = false;
b6c7a5dc 6368
3e007509 6369 if (vcpu->requests) {
a8eeb04a 6370 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6371 kvm_mmu_unload(vcpu);
a8eeb04a 6372 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6373 __kvm_migrate_timers(vcpu);
d828199e
MT		 6374 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6375 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6376 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6377 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6378 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6379 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6380 if (unlikely(r))
6381 goto out;
6382 }
a8eeb04a 6383 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6384 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6385 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6386 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6387 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6388 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6389 r = 0;
6390 goto out;
6391 }
a8eeb04a 6392 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6393 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6394 r = 0;
6395 goto out;
6396 }
a8eeb04a 6397 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6398 vcpu->fpu_active = 0;
6399 kvm_x86_ops->fpu_deactivate(vcpu);
6400 }
af585b92
GN		 6401 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6402 /* Page is swapped out. Do synthetic halt */
6403 vcpu->arch.apf.halted = true;
6404 r = 1;
6405 goto out;
6406 }
c9aaa895
GC		 6407 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6408 record_steal_time(vcpu);
64d60670
PB		 6409 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6410 process_smi(vcpu);
7460fb4a
AK		 6411 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6412 process_nmi(vcpu);
f5132b01 6413 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6414 kvm_pmu_handle_event(vcpu);
f5132b01 6415 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6416 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6417 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6418 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6419 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6420 (void *) vcpu->arch.eoi_exit_bitmap)) {
6421 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6422 vcpu->run->eoi.vector =
6423 vcpu->arch.pending_ioapic_eoi;
6424 r = 0;
6425 goto out;
6426 }
6427 }
3d81bc7e
YZ		 6428 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6429 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6430 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6431 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6432 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6433 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6434 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6435 r = 0;
6436 goto out;
6437 }
e516cebb
AS		 6438 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6439 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6440 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6441 r = 0;
6442 goto out;
6443 }
2f52d58c 6444 }
b93463aa 6445
bf9f6ac8
FW		 6446 /*
6447 * KVM_REQ_EVENT is not set when posted interrupts are set by
6448 * VT-d hardware, so we have to update RVI unconditionally.
6449 */
6450 if (kvm_lapic_enabled(vcpu)) {
6451 /*
6452 * Update architecture specific hints for APIC
6453 * virtual interrupt delivery.
6454 */
6455 if (kvm_x86_ops->hwapic_irr_update)
6456 kvm_x86_ops->hwapic_irr_update(vcpu,
6457 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6458 }
b93463aa 6459
b463a6f7 6460 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6461 kvm_apic_accept_events(vcpu);
6462 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6463 r = 1;
6464 goto out;
6465 }
6466
b6b8a145
JK		 6467 if (inject_pending_event(vcpu, req_int_win) != 0)
6468 req_immediate_exit = true;
b463a6f7 6469 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6470 else if (vcpu->arch.nmi_pending)
c9a7953f 6471 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6472 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6473 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6474
6475 if (kvm_lapic_enabled(vcpu)) {
6476 update_cr8_intercept(vcpu);
6477 kvm_lapic_sync_to_vapic(vcpu);
6478 }
6479 }
6480
d8368af8
AK		 6481 r = kvm_mmu_reload(vcpu);
6482 if (unlikely(r)) {
d905c069 6483 goto cancel_injection;
d8368af8
AK		 6484 }
6485
b6c7a5dc
HB		 6486 preempt_disable();
6487
6488 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6489 if (vcpu->fpu_active)
6490 kvm_load_guest_fpu(vcpu);
2acf923e 6491 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6492
6b7e2d09
XG		 6493 vcpu->mode = IN_GUEST_MODE;
6494
01b71917
MT		 6495 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6496
6b7e2d09
XG		 6497 /* We should set ->mode before check ->requests,
6498 * see the comment in make_all_cpus_request.
6499 */
01b71917 6500 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6501
d94e1dc9 6502 local_irq_disable();
32f88400 6503
6b7e2d09 6504 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6505 || need_resched() || signal_pending(current)) {
6b7e2d09 6506 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6507 smp_wmb();
6c142801
AK		 6508 local_irq_enable();
6509 preempt_enable();
01b71917 6510 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6511 r = 1;
d905c069 6512 goto cancel_injection;
6c142801
AK		 6513 }
6514
d6185f20
NHE		 6515 if (req_immediate_exit)
6516 smp_send_reschedule(vcpu->cpu);
6517
ccf73aaf 6518 __kvm_guest_enter();
b6c7a5dc 6519
42dbaa5a 6520 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6521 set_debugreg(0, 7);
6522 set_debugreg(vcpu->arch.eff_db[0], 0);
6523 set_debugreg(vcpu->arch.eff_db[1], 1);
6524 set_debugreg(vcpu->arch.eff_db[2], 2);
6525 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6526 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6527 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6528 }
b6c7a5dc 6529
229456fc 6530 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6531 wait_lapic_expire(vcpu);
851ba692 6532 kvm_x86_ops->run(vcpu);
b6c7a5dc 6533
c77fb5fe
PB		 6534 /*
6535 * Do this here before restoring debug registers on the host. And
6536 * since we do this before handling the vmexit, a DR access vmexit
6537 * can (a) read the correct value of the debug registers, (b) set
6538 * KVM_DEBUGREG_WONT_EXIT again.
6539 */
6540 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6541 int i;
6542
6543 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6544 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6545 for (i = 0; i < KVM_NR_DB_REGS; i++)
6546 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6547 }
6548
24f1e32c
FW		 6549 /*
6550 * If the guest has used debug registers, at least dr7
6551 * will be disabled while returning to the host.
6552 * If we don't have active breakpoints in the host, we don't
6553 * care about the messed up debug address registers. But if
6554 * we have some of them active, restore the old state.
6555 */
59d8eb53 6556 if (hw_breakpoint_active())
24f1e32c 6557 hw_breakpoint_restore();
42dbaa5a 6558
4ba76538 6559 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6560
6b7e2d09 6561 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6562 smp_wmb();
a547c6db
YZ		 6563
6564 /* Interrupt is enabled by handle_external_intr() */
6565 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6566
6567 ++vcpu->stat.exits;
6568
6569 /*
6570 * We must have an instruction between local_irq_enable() and
6571 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6572 * the interrupt shadow. The stat.exits increment will do nicely.
6573 * But we need to prevent reordering, hence this barrier():
6574 */
6575 barrier();
6576
6577 kvm_guest_exit();
6578
6579 preempt_enable();
6580
f656ce01 6581 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6582
b6c7a5dc
HB		 6583 /*
6584 * Profile KVM exit RIPs:
6585 */
6586 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6587 unsigned long rip = kvm_rip_read(vcpu);
6588 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6589 }
6590
cc578287
ZA		 6591 if (unlikely(vcpu->arch.tsc_always_catchup))
6592 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6593
5cfb1d5a
MT		 6594 if (vcpu->arch.apic_attention)
6595 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6596
851ba692 6597 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6598 return r;
6599
6600cancel_injection:
6601 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6602 if (unlikely(vcpu->arch.apic_attention))
6603 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6604out:
6605 return r;
6606}
b6c7a5dc 6607
362c698f
PB		 6608static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6609{
bf9f6ac8
FW		 6610 if (!kvm_arch_vcpu_runnable(vcpu) &&
6611 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6612 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6613 kvm_vcpu_block(vcpu);
6614 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6615
6616 if (kvm_x86_ops->post_block)
6617 kvm_x86_ops->post_block(vcpu);
6618
9c8fd1ba
PB		 6619 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6620 return 1;
6621 }
362c698f
PB		 6622
6623 kvm_apic_accept_events(vcpu);
6624 switch(vcpu->arch.mp_state) {
6625 case KVM_MP_STATE_HALTED:
6626 vcpu->arch.pv.pv_unhalted = false;
6627 vcpu->arch.mp_state =
6628 KVM_MP_STATE_RUNNABLE;
6629 case KVM_MP_STATE_RUNNABLE:
6630 vcpu->arch.apf.halted = false;
6631 break;
6632 case KVM_MP_STATE_INIT_RECEIVED:
6633 break;
6634 default:
6635 return -EINTR;
6636 break;
6637 }
6638 return 1;
6639}
09cec754 6640
5d9bc648
PB		 6641static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6642{
6643 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6644 !vcpu->arch.apf.halted);
6645}
6646
362c698f 6647static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6648{
6649 int r;
f656ce01 6650 struct kvm *kvm = vcpu->kvm;
d7690175 6651
f656ce01 6652 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6653
362c698f 6654 for (;;) {
58f800d5 6655 if (kvm_vcpu_running(vcpu)) {
851ba692 6656 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6657 } else {
362c698f 6658 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6659 }
6660
09cec754
GN		 6661 if (r <= 0)
6662 break;
6663
6664 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6665 if (kvm_cpu_has_pending_timer(vcpu))
6666 kvm_inject_pending_timer_irqs(vcpu);
6667
782d422b
MG		 6668 if (dm_request_for_irq_injection(vcpu) &&
6669 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6670 r = 0;
6671 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6672 ++vcpu->stat.request_irq_exits;
362c698f 6673 break;
09cec754 6674 }
af585b92
GN		 6675
6676 kvm_check_async_pf_completion(vcpu);
6677
09cec754
GN		 6678 if (signal_pending(current)) {
6679 r = -EINTR;
851ba692 6680 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6681 ++vcpu->stat.signal_exits;
362c698f 6682 break;
09cec754
GN		 6683 }
6684 if (need_resched()) {
f656ce01 6685 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6686 cond_resched();
f656ce01 6687 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6688 }
b6c7a5dc
HB		 6689 }
6690
f656ce01 6691 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6692
6693 return r;
6694}
6695
716d51ab
GN		 6696static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6697{
6698 int r;
6699 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6700 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6701 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6702 if (r != EMULATE_DONE)
6703 return 0;
6704 return 1;
6705}
6706
6707static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6708{
6709 BUG_ON(!vcpu->arch.pio.count);
6710
6711 return complete_emulated_io(vcpu);
6712}
6713
f78146b0
AK		 6714/*
6715 * Implements the following, as a state machine:
6716 *
6717 * read:
6718 * for each fragment
87da7e66
XG		 6719 * for each mmio piece in the fragment
6720 * write gpa, len
6721 * exit
6722 * copy data
f78146b0
AK		 6723 * execute insn
6724 *
6725 * write:
6726 * for each fragment
87da7e66
XG		 6727 * for each mmio piece in the fragment
6728 * write gpa, len
6729 * copy data
6730 * exit
f78146b0 6731 */
716d51ab 6732static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6733{
6734 struct kvm_run *run = vcpu->run;
f78146b0 6735 struct kvm_mmio_fragment *frag;
87da7e66 6736 unsigned len;
5287f194 6737
716d51ab 6738 BUG_ON(!vcpu->mmio_needed);
5287f194 6739
716d51ab 6740 /* Complete previous fragment */
87da7e66
XG		 6741 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6742 len = min(8u, frag->len);
716d51ab 6743 if (!vcpu->mmio_is_write)
87da7e66
XG		 6744 memcpy(frag->data, run->mmio.data, len);
6745
6746 if (frag->len <= 8) {
6747 /* Switch to the next fragment. */
6748 frag++;
6749 vcpu->mmio_cur_fragment++;
6750 } else {
6751 /* Go forward to the next mmio piece. */
6752 frag->data += len;
6753 frag->gpa += len;
6754 frag->len -= len;
6755 }
6756
a08d3b3b 6757 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6758 vcpu->mmio_needed = 0;
0912c977
PB		 6759
6760 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6761 if (vcpu->mmio_is_write)
716d51ab
GN		 6762 return 1;
6763 vcpu->mmio_read_completed = 1;
6764 return complete_emulated_io(vcpu);
6765 }
87da7e66 6766
716d51ab
GN		 6767 run->exit_reason = KVM_EXIT_MMIO;
6768 run->mmio.phys_addr = frag->gpa;
6769 if (vcpu->mmio_is_write)
87da7e66
XG		 6770 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6771 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6772 run->mmio.is_write = vcpu->mmio_is_write;
6773 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6774 return 0;
5287f194
AK		 6775}
6776
716d51ab 6777
b6c7a5dc
HB		 6778int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6779{
c5bedc68 6780 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6781 int r;
6782 sigset_t sigsaved;
6783
c4d72e2d 6784 fpu__activate_curr(fpu);
e5c30142 6785
ac9f6dc0
AK		 6786 if (vcpu->sigset_active)
6787 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6788
a4535290 6789 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6790 kvm_vcpu_block(vcpu);
66450a21 6791 kvm_apic_accept_events(vcpu);
d7690175 6792 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6793 r = -EAGAIN;
6794 goto out;
b6c7a5dc
HB		 6795 }
6796
b6c7a5dc 6797 /* re-sync apic's tpr */
35754c98 6798 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6799 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6800 r = -EINVAL;
6801 goto out;
6802 }
6803 }
b6c7a5dc 6804
716d51ab
GN		 6805 if (unlikely(vcpu->arch.complete_userspace_io)) {
6806 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6807 vcpu->arch.complete_userspace_io = NULL;
6808 r = cui(vcpu);
6809 if (r <= 0)
6810 goto out;
6811 } else
6812 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6813
362c698f 6814 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6815
6816out:
f1d86e46 6817 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6818 if (vcpu->sigset_active)
6819 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6820
b6c7a5dc
HB		 6821 return r;
6822}
6823
6824int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6825{
7ae441ea
GN		 6826 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6827 /*
6828 * We are here if userspace calls get_regs() in the middle of
6829 * instruction emulation. Registers state needs to be copied
4a969980 6830 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6831 * that usually, but some bad designed PV devices (vmware
6832 * backdoor interface) need this to work
6833 */
dd856efa 6834 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6835 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6836 }
5fdbf976
MT		 6837 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6838 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6839 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6840 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6841 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6842 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6843 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6844 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6845#ifdef CONFIG_X86_64
5fdbf976
MT		 6846 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6847 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6848 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6849 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6850 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6851 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6852 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6853 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6854#endif
6855
5fdbf976 6856 regs->rip = kvm_rip_read(vcpu);
91586a3b 6857 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6858
b6c7a5dc
HB		 6859 return 0;
6860}
6861
6862int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6863{
7ae441ea
GN		 6864 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6865 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6866
5fdbf976
MT		 6867 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6868 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6869 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6870 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6871 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6872 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6873 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6874 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6875#ifdef CONFIG_X86_64
5fdbf976
MT		 6876 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6877 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6878 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6879 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6880 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6881 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6882 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6883 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6884#endif
6885
5fdbf976 6886 kvm_rip_write(vcpu, regs->rip);
91586a3b 6887 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6888
b4f14abd
JK		 6889 vcpu->arch.exception.pending = false;
6890
3842d135
AK		 6891 kvm_make_request(KVM_REQ_EVENT, vcpu);
6892
b6c7a5dc
HB		 6893 return 0;
6894}
6895
b6c7a5dc
HB		 6896void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6897{
6898 struct kvm_segment cs;
6899
3e6e0aab 6900 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6901 *db = cs.db;
6902 *l = cs.l;
6903}
6904EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6905
6906int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6907 struct kvm_sregs *sregs)
6908{
89a27f4d 6909 struct desc_ptr dt;
b6c7a5dc 6910
3e6e0aab
GT		 6911 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6912 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6913 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6914 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6915 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6916 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6917
3e6e0aab
GT		 6918 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6919 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6920
6921 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6922 sregs->idt.limit = dt.size;
6923 sregs->idt.base = dt.address;
b6c7a5dc 6924 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6925 sregs->gdt.limit = dt.size;
6926 sregs->gdt.base = dt.address;
b6c7a5dc 6927
4d4ec087 6928 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6929 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6930 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6931 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6932 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6933 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6934 sregs->apic_base = kvm_get_apic_base(vcpu);
6935
923c61bb 6936 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6937
36752c9b 6938 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6939 set_bit(vcpu->arch.interrupt.nr,
6940 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6941
b6c7a5dc
HB		 6942 return 0;
6943}
6944
62d9f0db
MT		 6945int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6946 struct kvm_mp_state *mp_state)
6947{
66450a21 6948 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6949 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6950 vcpu->arch.pv.pv_unhalted)
6951 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6952 else
6953 mp_state->mp_state = vcpu->arch.mp_state;
6954
62d9f0db
MT		 6955 return 0;
6956}
6957
6958int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6959 struct kvm_mp_state *mp_state)
6960{
66450a21
JK		 6961 if (!kvm_vcpu_has_lapic(vcpu) &&
6962 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6963 return -EINVAL;
6964
6965 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6966 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6967 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6968 } else
6969 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6970 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6971 return 0;
6972}
6973
7f3d35fd
KW		 6974int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6975 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6976{
9d74191a 6977 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6978 int ret;
e01c2426 6979
8ec4722d 6980 init_emulate_ctxt(vcpu);
c697518a 6981
7f3d35fd 6982 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6983 has_error_code, error_code);
c697518a 6984
c697518a 6985 if (ret)
19d04437 6986 return EMULATE_FAIL;
37817f29 6987
9d74191a
TY		 6988 kvm_rip_write(vcpu, ctxt->eip);
6989 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6990 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6991 return EMULATE_DONE;
37817f29
IE		 6992}
6993EXPORT_SYMBOL_GPL(kvm_task_switch);
6994
b6c7a5dc
HB		 6995int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6996 struct kvm_sregs *sregs)
6997{
58cb628d 6998 struct msr_data apic_base_msr;
b6c7a5dc 6999 int mmu_reset_needed = 0;
63f42e02 7000 int pending_vec, max_bits, idx;
89a27f4d 7001 struct desc_ptr dt;
b6c7a5dc 7002
6d1068b3
PM		 7003 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7004 return -EINVAL;
7005
89a27f4d
GN		 7006 dt.size = sregs->idt.limit;
7007 dt.address = sregs->idt.base;
b6c7a5dc 7008 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7009 dt.size = sregs->gdt.limit;
7010 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7011 kvm_x86_ops->set_gdt(vcpu, &dt);
7012
ad312c7c 7013 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7014 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7015 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7016 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7017
2d3ad1f4 7018 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7019
f6801dff 7020 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7021 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7022 apic_base_msr.data = sregs->apic_base;
7023 apic_base_msr.host_initiated = true;
7024 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7025
4d4ec087 7026 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7027 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7028 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7029
fc78f519 7030 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7031 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 7032 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 7033 kvm_update_cpuid(vcpu);
63f42e02
XG		 7034
7035 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7036 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7037 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7038 mmu_reset_needed = 1;
7039 }
63f42e02 7040 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7041
7042 if (mmu_reset_needed)
7043 kvm_mmu_reset_context(vcpu);
7044
a50abc3b 7045 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7046 pending_vec = find_first_bit(
7047 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7048 if (pending_vec < max_bits) {
66fd3f7f 7049 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7050 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7051 }
7052
3e6e0aab
GT		 7053 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7054 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7055 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7056 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7057 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7058 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7059
3e6e0aab
GT		 7060 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7061 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7062
5f0269f5
ME		 7063 update_cr8_intercept(vcpu);
7064
9c3e4aab 7065 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7066 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7067 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7068 !is_protmode(vcpu))
9c3e4aab
MT		 7069 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7070
3842d135
AK		 7071 kvm_make_request(KVM_REQ_EVENT, vcpu);
7072
b6c7a5dc
HB		 7073 return 0;
7074}
7075
d0bfb940
JK		 7076int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7077 struct kvm_guest_debug *dbg)
b6c7a5dc 7078{
355be0b9 7079 unsigned long rflags;
ae675ef0 7080 int i, r;
b6c7a5dc 7081
4f926bf2
JK		 7082 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7083 r = -EBUSY;
7084 if (vcpu->arch.exception.pending)
2122ff5e 7085 goto out;
4f926bf2
JK		 7086 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7087 kvm_queue_exception(vcpu, DB_VECTOR);
7088 else
7089 kvm_queue_exception(vcpu, BP_VECTOR);
7090 }
7091
91586a3b
JK		 7092 /*
7093 * Read rflags as long as potentially injected trace flags are still
7094 * filtered out.
7095 */
7096 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7097
7098 vcpu->guest_debug = dbg->control;
7099 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7100 vcpu->guest_debug = 0;
7101
7102 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7103 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7104 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7105 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7106 } else {
7107 for (i = 0; i < KVM_NR_DB_REGS; i++)
7108 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7109 }
c8639010 7110 kvm_update_dr7(vcpu);
ae675ef0 7111
f92653ee
JK		 7112 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7113 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7114 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7115
91586a3b
JK		 7116 /*
7117 * Trigger an rflags update that will inject or remove the trace
7118 * flags.
7119 */
7120 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7121
a96036b8 7122 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7123
4f926bf2 7124 r = 0;
d0bfb940 7125
2122ff5e 7126out:
b6c7a5dc
HB		 7127
7128 return r;
7129}
7130
8b006791
ZX		 7131/*
7132 * Translate a guest virtual address to a guest physical address.
7133 */
7134int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7135 struct kvm_translation *tr)
7136{
7137 unsigned long vaddr = tr->linear_address;
7138 gpa_t gpa;
f656ce01 7139 int idx;
8b006791 7140
f656ce01 7141 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7142 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7143 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7144 tr->physical_address = gpa;
7145 tr->valid = gpa != UNMAPPED_GVA;
7146 tr->writeable = 1;
7147 tr->usermode = 0;
8b006791
ZX		 7148
7149 return 0;
7150}
7151
d0752060
HB		 7152int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7153{
c47ada30 7154 struct fxregs_state *fxsave =
7366ed77 7155 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7156
d0752060
HB		 7157 memcpy(fpu->fpr, fxsave->st_space, 128);
7158 fpu->fcw = fxsave->cwd;
7159 fpu->fsw = fxsave->swd;
7160 fpu->ftwx = fxsave->twd;
7161 fpu->last_opcode = fxsave->fop;
7162 fpu->last_ip = fxsave->rip;
7163 fpu->last_dp = fxsave->rdp;
7164 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7165
d0752060
HB		 7166 return 0;
7167}
7168
7169int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7170{
c47ada30 7171 struct fxregs_state *fxsave =
7366ed77 7172 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7173
d0752060
HB		 7174 memcpy(fxsave->st_space, fpu->fpr, 128);
7175 fxsave->cwd = fpu->fcw;
7176 fxsave->swd = fpu->fsw;
7177 fxsave->twd = fpu->ftwx;
7178 fxsave->fop = fpu->last_opcode;
7179 fxsave->rip = fpu->last_ip;
7180 fxsave->rdp = fpu->last_dp;
7181 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7182
d0752060
HB		 7183 return 0;
7184}
7185
0ee6a517 7186static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7187{
bf935b0b 7188 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7189 if (cpu_has_xsaves)
7366ed77 7190 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7191 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7192
2acf923e
DC		 7193 /*
7194 * Ensure guest xcr0 is valid for loading
7195 */
d91cab78 7196 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7197
ad312c7c 7198 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7199}
d0752060
HB		 7200
7201void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7202{
2608d7a1 7203 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7204 return;
7205
2acf923e
DC		 7206 /*
7207 * Restore all possible states in the guest,
7208 * and assume host would use all available bits.
7209 * Guest xcr0 would be loaded later.
7210 */
7211 kvm_put_guest_xcr0(vcpu);
d0752060 7212 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7213 __kernel_fpu_begin();
003e2e8b 7214 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7215 trace_kvm_fpu(1);
d0752060 7216}
d0752060
HB		 7217
7218void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7219{
2acf923e
DC		 7220 kvm_put_guest_xcr0(vcpu);
7221
653f52c3
RR		 7222 if (!vcpu->guest_fpu_loaded) {
7223 vcpu->fpu_counter = 0;
d0752060 7224 return;
653f52c3 7225 }
d0752060
HB		 7226
7227 vcpu->guest_fpu_loaded = 0;
4f836347 7228 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7229 __kernel_fpu_end();
f096ed85 7230 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7231 /*
7232 * If using eager FPU mode, or if the guest is a frequent user
7233 * of the FPU, just leave the FPU active for next time.
7234 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7235 * the FPU in bursts will revert to loading it on demand.
7236 */
a9b4fb7e 7237 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7238 if (++vcpu->fpu_counter < 5)
7239 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7240 }
0c04851c 7241 trace_kvm_fpu(0);
d0752060 7242}
e9b11c17
ZX		 7243
7244void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7245{
12f9a48f 7246 kvmclock_reset(vcpu);
7f1ea208 7247
f5f48ee1 7248 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7249 kvm_x86_ops->vcpu_free(vcpu);
7250}
7251
7252struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7253 unsigned int id)
7254{
c447e76b
LL		 7255 struct kvm_vcpu *vcpu;
7256
6755bae8
ZA		 7257 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7258 printk_once(KERN_WARNING
7259 "kvm: SMP vm created on host with unstable TSC; "
7260 "guest TSC will not be reliable\n");
c447e76b
LL		 7261
7262 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7263
c447e76b 7264 return vcpu;
26e5215f 7265}
e9b11c17 7266
26e5215f
AK		 7267int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7268{
7269 int r;
e9b11c17 7270
19efffa2 7271 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7272 r = vcpu_load(vcpu);
7273 if (r)
7274 return r;
d28bc9dd 7275 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7276 kvm_mmu_setup(vcpu);
e9b11c17 7277 vcpu_put(vcpu);
26e5215f 7278 return r;
e9b11c17
ZX		 7279}
7280
31928aa5 7281void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7282{
8fe8ab46 7283 struct msr_data msr;
332967a3 7284 struct kvm *kvm = vcpu->kvm;
42897d86 7285
31928aa5
DD		 7286 if (vcpu_load(vcpu))
7287 return;
8fe8ab46
WA		 7288 msr.data = 0x0;
7289 msr.index = MSR_IA32_TSC;
7290 msr.host_initiated = true;
7291 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7292 vcpu_put(vcpu);
7293
630994b3
MT		 7294 if (!kvmclock_periodic_sync)
7295 return;
7296
332967a3
AJ		 7297 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7298 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7299}
7300
d40ccc62 7301void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7302{
9fc77441 7303 int r;
344d9588
GN		 7304 vcpu->arch.apf.msr_val = 0;
7305
9fc77441
MT		 7306 r = vcpu_load(vcpu);
7307 BUG_ON(r);
e9b11c17
ZX		 7308 kvm_mmu_unload(vcpu);
7309 vcpu_put(vcpu);
7310
7311 kvm_x86_ops->vcpu_free(vcpu);
7312}
7313
d28bc9dd 7314void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7315{
e69fab5d
PB		 7316 vcpu->arch.hflags = 0;
7317
7460fb4a
AK		 7318 atomic_set(&vcpu->arch.nmi_queued, 0);
7319 vcpu->arch.nmi_pending = 0;
448fa4a9 7320 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7321 kvm_clear_interrupt_queue(vcpu);
7322 kvm_clear_exception_queue(vcpu);
448fa4a9 7323
42dbaa5a 7324 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7325 kvm_update_dr0123(vcpu);
6f43ed01 7326 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7327 kvm_update_dr6(vcpu);
42dbaa5a 7328 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7329 kvm_update_dr7(vcpu);
42dbaa5a 7330
1119022c
NA		 7331 vcpu->arch.cr2 = 0;
7332
3842d135 7333 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7334 vcpu->arch.apf.msr_val = 0;
c9aaa895 7335 vcpu->arch.st.msr_val = 0;
3842d135 7336
12f9a48f
GC		 7337 kvmclock_reset(vcpu);
7338
af585b92
GN		 7339 kvm_clear_async_pf_completion_queue(vcpu);
7340 kvm_async_pf_hash_reset(vcpu);
7341 vcpu->arch.apf.halted = false;
3842d135 7342
64d60670 7343 if (!init_event) {
d28bc9dd 7344 kvm_pmu_reset(vcpu);
64d60670
PB		 7345 vcpu->arch.smbase = 0x30000;
7346 }
f5132b01 7347
66f7b72e
JS		 7348 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7349 vcpu->arch.regs_avail = ~0;
7350 vcpu->arch.regs_dirty = ~0;
7351
d28bc9dd 7352 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7353}
7354
2b4a273b 7355void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7356{
7357 struct kvm_segment cs;
7358
7359 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7360 cs.selector = vector << 8;
7361 cs.base = vector << 12;
7362 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7363 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7364}
7365
13a34e06 7366int kvm_arch_hardware_enable(void)
e9b11c17 7367{
ca84d1a2
ZA		 7368 struct kvm *kvm;
7369 struct kvm_vcpu *vcpu;
7370 int i;
0dd6a6ed
ZA		 7371 int ret;
7372 u64 local_tsc;
7373 u64 max_tsc = 0;
7374 bool stable, backwards_tsc = false;
18863bdd
AK		 7375
7376 kvm_shared_msr_cpu_online();
13a34e06 7377 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7378 if (ret != 0)
7379 return ret;
7380
4ea1636b 7381 local_tsc = rdtsc();
0dd6a6ed
ZA		 7382 stable = !check_tsc_unstable();
7383 list_for_each_entry(kvm, &vm_list, vm_list) {
7384 kvm_for_each_vcpu(i, vcpu, kvm) {
7385 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7386 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7387 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7388 backwards_tsc = true;
7389 if (vcpu->arch.last_host_tsc > max_tsc)
7390 max_tsc = vcpu->arch.last_host_tsc;
7391 }
7392 }
7393 }
7394
7395 /*
7396 * Sometimes, even reliable TSCs go backwards. This happens on
7397 * platforms that reset TSC during suspend or hibernate actions, but
7398 * maintain synchronization. We must compensate. Fortunately, we can
7399 * detect that condition here, which happens early in CPU bringup,
7400 * before any KVM threads can be running. Unfortunately, we can't
7401 * bring the TSCs fully up to date with real time, as we aren't yet far
7402 * enough into CPU bringup that we know how much real time has actually
7403 * elapsed; our helper function, get_kernel_ns() will be using boot
7404 * variables that haven't been updated yet.
7405 *
7406 * So we simply find the maximum observed TSC above, then record the
7407 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7408 * the adjustment will be applied. Note that we accumulate
7409 * adjustments, in case multiple suspend cycles happen before some VCPU
7410 * gets a chance to run again. In the event that no KVM threads get a
7411 * chance to run, we will miss the entire elapsed period, as we'll have
7412 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7413 * loose cycle time. This isn't too big a deal, since the loss will be
7414 * uniform across all VCPUs (not to mention the scenario is extremely
7415 * unlikely). It is possible that a second hibernate recovery happens
7416 * much faster than a first, causing the observed TSC here to be
7417 * smaller; this would require additional padding adjustment, which is
7418 * why we set last_host_tsc to the local tsc observed here.
7419 *
7420 * N.B. - this code below runs only on platforms with reliable TSC,
7421 * as that is the only way backwards_tsc is set above. Also note
7422 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7423 * have the same delta_cyc adjustment applied if backwards_tsc
7424 * is detected. Note further, this adjustment is only done once,
7425 * as we reset last_host_tsc on all VCPUs to stop this from being
7426 * called multiple times (one for each physical CPU bringup).
7427 *
4a969980 7428 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7429 * will be compensated by the logic in vcpu_load, which sets the TSC to
7430 * catchup mode. This will catchup all VCPUs to real time, but cannot
7431 * guarantee that they stay in perfect synchronization.
7432 */
7433 if (backwards_tsc) {
7434 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7435 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7436 list_for_each_entry(kvm, &vm_list, vm_list) {
7437 kvm_for_each_vcpu(i, vcpu, kvm) {
7438 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7439 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7440 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7441 }
7442
7443 /*
7444 * We have to disable TSC offset matching.. if you were
7445 * booting a VM while issuing an S4 host suspend....
7446 * you may have some problem. Solving this issue is
7447 * left as an exercise to the reader.
7448 */
7449 kvm->arch.last_tsc_nsec = 0;
7450 kvm->arch.last_tsc_write = 0;
7451 }
7452
7453 }
7454 return 0;
e9b11c17
ZX		 7455}
7456
13a34e06 7457void kvm_arch_hardware_disable(void)
e9b11c17 7458{
13a34e06
RK		 7459 kvm_x86_ops->hardware_disable();
7460 drop_user_return_notifiers();
e9b11c17
ZX		 7461}
7462
7463int kvm_arch_hardware_setup(void)
7464{
9e9c3fe4
NA		 7465 int r;
7466
7467 r = kvm_x86_ops->hardware_setup();
7468 if (r != 0)
7469 return r;
7470
35181e86
HZ		 7471 if (kvm_has_tsc_control) {
7472 /*
7473 * Make sure the user can only configure tsc_khz values that
7474 * fit into a signed integer.
7475 * A min value is not calculated needed because it will always
7476 * be 1 on all machines.
7477 */
7478 u64 max = min(0x7fffffffULL,
7479 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7480 kvm_max_guest_tsc_khz = max;
7481
ad721883 7482 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7483 }
ad721883 7484
9e9c3fe4
NA		 7485 kvm_init_msr_list();
7486 return 0;
e9b11c17
ZX		 7487}
7488
7489void kvm_arch_hardware_unsetup(void)
7490{
7491 kvm_x86_ops->hardware_unsetup();
7492}
7493
7494void kvm_arch_check_processor_compat(void *rtn)
7495{
7496 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7497}
7498
7499bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7500{
7501 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7502}
7503EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7504
7505bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7506{
7507 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7508}
7509
3e515705
AK		 7510bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7511{
35754c98 7512 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7513}
7514
54e9818f
GN		 7515struct static_key kvm_no_apic_vcpu __read_mostly;
7516
e9b11c17
ZX		 7517int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7518{
7519 struct page *page;
7520 struct kvm *kvm;
7521 int r;
7522
7523 BUG_ON(vcpu->kvm == NULL);
7524 kvm = vcpu->kvm;
7525
6aef266c 7526 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7527 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7528 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7529 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7530 else
a4535290 7531 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7532
7533 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7534 if (!page) {
7535 r = -ENOMEM;
7536 goto fail;
7537 }
ad312c7c 7538 vcpu->arch.pio_data = page_address(page);
e9b11c17 7539
cc578287 7540 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7541
e9b11c17
ZX		 7542 r = kvm_mmu_create(vcpu);
7543 if (r < 0)
7544 goto fail_free_pio_data;
7545
7546 if (irqchip_in_kernel(kvm)) {
7547 r = kvm_create_lapic(vcpu);
7548 if (r < 0)
7549 goto fail_mmu_destroy;
54e9818f
GN		 7550 } else
7551 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7552
890ca9ae
HY		 7553 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7554 GFP_KERNEL);
7555 if (!vcpu->arch.mce_banks) {
7556 r = -ENOMEM;
443c39bc 7557 goto fail_free_lapic;
890ca9ae
HY		 7558 }
7559 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7560
f1797359
WY		 7561 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7562 r = -ENOMEM;
f5f48ee1 7563 goto fail_free_mce_banks;
f1797359 7564 }
f5f48ee1 7565
0ee6a517 7566 fx_init(vcpu);
66f7b72e 7567
ba904635 7568 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7569 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7570
7571 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7572 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7573
5a4f55cd
EK		 7574 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7575
74545705
RK		 7576 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7577
af585b92 7578 kvm_async_pf_hash_reset(vcpu);
f5132b01 7579 kvm_pmu_init(vcpu);
af585b92 7580
1c1a9ce9
SR		 7581 vcpu->arch.pending_external_vector = -1;
7582
e9b11c17 7583 return 0;
0ee6a517 7584
f5f48ee1
SY		 7585fail_free_mce_banks:
7586 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7587fail_free_lapic:
7588 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7589fail_mmu_destroy:
7590 kvm_mmu_destroy(vcpu);
7591fail_free_pio_data:
ad312c7c 7592 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7593fail:
7594 return r;
7595}
7596
7597void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7598{
f656ce01
MT		 7599 int idx;
7600
f5132b01 7601 kvm_pmu_destroy(vcpu);
36cb93fd 7602 kfree(vcpu->arch.mce_banks);
e9b11c17 7603 kvm_free_lapic(vcpu);
f656ce01 7604 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7605 kvm_mmu_destroy(vcpu);
f656ce01 7606 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7607 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7608 if (!lapic_in_kernel(vcpu))
54e9818f 7609 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7610}
d19a9cd2 7611
e790d9ef
RK		 7612void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7613{
ae97a3b8 7614 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7615}
7616
e08b9637 7617int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7618{
e08b9637
CO		 7619 if (type)
7620 return -EINVAL;
7621
6ef768fa 7622 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7623 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7624 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7625 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7626 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7627
5550af4d
SY		 7628 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7629 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7630 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7631 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7632 &kvm->arch.irq_sources_bitmap);
5550af4d 7633
038f8c11 7634 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7635 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7636 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7637
7638 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7639
7e44e449 7640 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7641 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7642
d89f5eff 7643 return 0;
d19a9cd2
ZX		 7644}
7645
7646static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7647{
9fc77441
MT		 7648 int r;
7649 r = vcpu_load(vcpu);
7650 BUG_ON(r);
d19a9cd2
ZX		 7651 kvm_mmu_unload(vcpu);
7652 vcpu_put(vcpu);
7653}
7654
7655static void kvm_free_vcpus(struct kvm *kvm)
7656{
7657 unsigned int i;
988a2cae 7658 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7659
7660 /*
7661 * Unpin any mmu pages first.
7662 */
af585b92
GN		 7663 kvm_for_each_vcpu(i, vcpu, kvm) {
7664 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7665 kvm_unload_vcpu_mmu(vcpu);
af585b92 7666 }
988a2cae
GN		 7667 kvm_for_each_vcpu(i, vcpu, kvm)
7668 kvm_arch_vcpu_free(vcpu);
7669
7670 mutex_lock(&kvm->lock);
7671 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7672 kvm->vcpus[i] = NULL;
d19a9cd2 7673
988a2cae
GN		 7674 atomic_set(&kvm->online_vcpus, 0);
7675 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7676}
7677
ad8ba2cd
SY		 7678void kvm_arch_sync_events(struct kvm *kvm)
7679{
332967a3 7680 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7681 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7682 kvm_free_all_assigned_devices(kvm);
aea924f6 7683 kvm_free_pit(kvm);
ad8ba2cd
SY		 7684}
7685
1d8007bd 7686int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7687{
7688 int i, r;
25188b99 7689 unsigned long hva;
f0d648bd
PB		 7690 struct kvm_memslots *slots = kvm_memslots(kvm);
7691 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7692
7693 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7694 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7695 return -EINVAL;
9da0e4d5 7696
f0d648bd
PB		 7697 slot = id_to_memslot(slots, id);
7698 if (size) {
7699 if (WARN_ON(slot->npages))
7700 return -EEXIST;
7701
7702 /*
7703 * MAP_SHARED to prevent internal slot pages from being moved
7704 * by fork()/COW.
7705 */
7706 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7707 MAP_SHARED | MAP_ANONYMOUS, 0);
7708 if (IS_ERR((void *)hva))
7709 return PTR_ERR((void *)hva);
7710 } else {
7711 if (!slot->npages)
7712 return 0;
7713
7714 hva = 0;
7715 }
7716
7717 old = *slot;
9da0e4d5 7718 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7719 struct kvm_userspace_memory_region m;
9da0e4d5 7720
1d8007bd
PB		 7721 m.slot = id | (i << 16);
7722 m.flags = 0;
7723 m.guest_phys_addr = gpa;
f0d648bd 7724 m.userspace_addr = hva;
1d8007bd 7725 m.memory_size = size;
9da0e4d5
PB		 7726 r = __kvm_set_memory_region(kvm, &m);
7727 if (r < 0)
7728 return r;
7729 }
7730
f0d648bd
PB		 7731 if (!size) {
7732 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7733 WARN_ON(r < 0);
7734 }
7735
9da0e4d5
PB		 7736 return 0;
7737}
7738EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7739
1d8007bd 7740int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7741{
7742 int r;
7743
7744 mutex_lock(&kvm->slots_lock);
1d8007bd 7745 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7746 mutex_unlock(&kvm->slots_lock);
7747
7748 return r;
7749}
7750EXPORT_SYMBOL_GPL(x86_set_memory_region);
7751
d19a9cd2
ZX		 7752void kvm_arch_destroy_vm(struct kvm *kvm)
7753{
27469d29
AH		 7754 if (current->mm == kvm->mm) {
7755 /*
7756 * Free memory regions allocated on behalf of userspace,
7757 * unless the the memory map has changed due to process exit
7758 * or fd copying.
7759 */
1d8007bd
PB		 7760 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7761 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7762 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7763 }
6eb55818 7764 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7765 kfree(kvm->arch.vpic);
7766 kfree(kvm->arch.vioapic);
d19a9cd2 7767 kvm_free_vcpus(kvm);
1e08ec4a 7768 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7769}
0de10343 7770
5587027c 7771void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7772 struct kvm_memory_slot *dont)
7773{
7774 int i;
7775
d89cc617
TY		 7776 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7777 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7778 kvfree(free->arch.rmap[i]);
d89cc617 7779 free->arch.rmap[i] = NULL;
77d11309 7780 }
d89cc617
TY		 7781 if (i == 0)
7782 continue;
7783
7784 if (!dont || free->arch.lpage_info[i - 1] !=
7785 dont->arch.lpage_info[i - 1]) {
548ef284 7786 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7787 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7788 }
7789 }
7790}
7791
5587027c
AK		 7792int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7793 unsigned long npages)
db3fe4eb
TY		 7794{
7795 int i;
7796
d89cc617 7797 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7798 unsigned long ugfn;
7799 int lpages;
d89cc617 7800 int level = i + 1;
db3fe4eb
TY		 7801
7802 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7803 slot->base_gfn, level) + 1;
7804
d89cc617
TY		 7805 slot->arch.rmap[i] =
7806 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7807 if (!slot->arch.rmap[i])
77d11309 7808 goto out_free;
d89cc617
TY		 7809 if (i == 0)
7810 continue;
77d11309 7811
d89cc617
TY		 7812 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7813 sizeof(*slot->arch.lpage_info[i - 1]));
7814 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7815 goto out_free;
7816
7817 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7818 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7819 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7820 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7821 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7822 /*
7823 * If the gfn and userspace address are not aligned wrt each
7824 * other, or if explicitly asked to, disable large page
7825 * support for this slot
7826 */
7827 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7828 !kvm_largepages_enabled()) {
7829 unsigned long j;
7830
7831 for (j = 0; j < lpages; ++j)
d89cc617 7832 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7833 }
7834 }
7835
7836 return 0;
7837
7838out_free:
d89cc617 7839 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7840 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7841 slot->arch.rmap[i] = NULL;
7842 if (i == 0)
7843 continue;
7844
548ef284 7845 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7846 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7847 }
7848 return -ENOMEM;
7849}
7850
15f46015 7851void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7852{
e6dff7d1
TY		 7853 /*
7854 * memslots->generation has been incremented.
7855 * mmio generation may have reached its maximum value.
7856 */
54bf36aa 7857 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7858}
7859
f7784b8e
MT		 7860int kvm_arch_prepare_memory_region(struct kvm *kvm,
7861 struct kvm_memory_slot *memslot,
09170a49 7862 const struct kvm_userspace_memory_region *mem,
7b6195a9 7863 enum kvm_mr_change change)
0de10343 7864{
f7784b8e
MT		 7865 return 0;
7866}
7867
88178fd4
KH		 7868static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7869 struct kvm_memory_slot *new)
7870{
7871 /* Still write protect RO slot */
7872 if (new->flags & KVM_MEM_READONLY) {
7873 kvm_mmu_slot_remove_write_access(kvm, new);
7874 return;
7875 }
7876
7877 /*
7878 * Call kvm_x86_ops dirty logging hooks when they are valid.
7879 *
7880 * kvm_x86_ops->slot_disable_log_dirty is called when:
7881 *
7882 * - KVM_MR_CREATE with dirty logging is disabled
7883 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7884 *
7885 * The reason is, in case of PML, we need to set D-bit for any slots
7886 * with dirty logging disabled in order to eliminate unnecessary GPA
7887 * logging in PML buffer (and potential PML buffer full VMEXT). This
7888 * guarantees leaving PML enabled during guest's lifetime won't have
7889 * any additonal overhead from PML when guest is running with dirty
7890 * logging disabled for memory slots.
7891 *
7892 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7893 * to dirty logging mode.
7894 *
7895 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7896 *
7897 * In case of write protect:
7898 *
7899 * Write protect all pages for dirty logging.
7900 *
7901 * All the sptes including the large sptes which point to this
7902 * slot are set to readonly. We can not create any new large
7903 * spte on this slot until the end of the logging.
7904 *
7905 * See the comments in fast_page_fault().
7906 */
7907 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7908 if (kvm_x86_ops->slot_enable_log_dirty)
7909 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7910 else
7911 kvm_mmu_slot_remove_write_access(kvm, new);
7912 } else {
7913 if (kvm_x86_ops->slot_disable_log_dirty)
7914 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7915 }
7916}
7917
f7784b8e 7918void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7919 const struct kvm_userspace_memory_region *mem,
8482644a 7920 const struct kvm_memory_slot *old,
f36f3f28 7921 const struct kvm_memory_slot *new,
8482644a 7922 enum kvm_mr_change change)
f7784b8e 7923{
8482644a 7924 int nr_mmu_pages = 0;
f7784b8e 7925
48c0e4e9
XG		 7926 if (!kvm->arch.n_requested_mmu_pages)
7927 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7928
48c0e4e9 7929 if (nr_mmu_pages)
0de10343 7930 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7931
3ea3b7fa
WL		 7932 /*
7933 * Dirty logging tracks sptes in 4k granularity, meaning that large
7934 * sptes have to be split. If live migration is successful, the guest
7935 * in the source machine will be destroyed and large sptes will be
7936 * created in the destination. However, if the guest continues to run
7937 * in the source machine (for example if live migration fails), small
7938 * sptes will remain around and cause bad performance.
7939 *
7940 * Scan sptes if dirty logging has been stopped, dropping those
7941 * which can be collapsed into a single large-page spte. Later
7942 * page faults will create the large-page sptes.
7943 */
7944 if ((change != KVM_MR_DELETE) &&
7945 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
7946 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
7947 kvm_mmu_zap_collapsible_sptes(kvm, new);
7948
c972f3b1 7949 /*
88178fd4 7950 * Set up write protection and/or dirty logging for the new slot.
c126d94f 7951 *
88178fd4
KH		 7952 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
7953 * been zapped so no dirty logging staff is needed for old slot. For
7954 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
7955 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 7956 *
7957 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 7958 */
88178fd4 7959 if (change != KVM_MR_DELETE)
f36f3f28 7960 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 7961}
1d737c8a 7962
2df72e9b 7963void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7964{
6ca18b69 7965 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7966}
7967
2df72e9b
MT		 7968void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7969 struct kvm_memory_slot *slot)
7970{
6ca18b69 7971 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7972}
7973
5d9bc648
PB		 7974static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
7975{
7976 if (!list_empty_careful(&vcpu->async_pf.done))
7977 return true;
7978
7979 if (kvm_apic_has_events(vcpu))
7980 return true;
7981
7982 if (vcpu->arch.pv.pv_unhalted)
7983 return true;
7984
7985 if (atomic_read(&vcpu->arch.nmi_queued))
7986 return true;
7987
73917739
PB		 7988 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
7989 return true;
7990
5d9bc648
PB		 7991 if (kvm_arch_interrupt_allowed(vcpu) &&
7992 kvm_cpu_has_interrupt(vcpu))
7993 return true;
7994
7995 return false;
7996}
7997
1d737c8a
ZX		 7998int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7999{
b6b8a145
JK		 8000 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8001 kvm_x86_ops->check_nested_events(vcpu, false);
8002
5d9bc648 8003 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8004}
5736199a 8005
b6d33834 8006int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8007{
b6d33834 8008 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8009}
78646121
GN		 8010
8011int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8012{
8013 return kvm_x86_ops->interrupt_allowed(vcpu);
8014}
229456fc 8015
82b32774 8016unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8017{
82b32774
NA		 8018 if (is_64_bit_mode(vcpu))
8019 return kvm_rip_read(vcpu);
8020 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8021 kvm_rip_read(vcpu));
8022}
8023EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8024
82b32774
NA		 8025bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8026{
8027 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8028}
8029EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8030
94fe45da
JK		 8031unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8032{
8033 unsigned long rflags;
8034
8035 rflags = kvm_x86_ops->get_rflags(vcpu);
8036 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8037 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8038 return rflags;
8039}
8040EXPORT_SYMBOL_GPL(kvm_get_rflags);
8041
6addfc42 8042static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8043{
8044 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8045 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8046 rflags |= X86_EFLAGS_TF;
94fe45da 8047 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8048}
8049
8050void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8051{
8052 __kvm_set_rflags(vcpu, rflags);
3842d135 8053 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8054}
8055EXPORT_SYMBOL_GPL(kvm_set_rflags);
8056
56028d08
GN		 8057void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8058{
8059 int r;
8060
fb67e14f 8061 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8062 work->wakeup_all)
56028d08
GN		 8063 return;
8064
8065 r = kvm_mmu_reload(vcpu);
8066 if (unlikely(r))
8067 return;
8068
fb67e14f
XG		 8069 if (!vcpu->arch.mmu.direct_map &&
8070 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8071 return;
8072
56028d08
GN		 8073 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8074}
8075
af585b92
GN		 8076static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8077{
8078 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8079}
8080
8081static inline u32 kvm_async_pf_next_probe(u32 key)
8082{
8083 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8084}
8085
8086static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8087{
8088 u32 key = kvm_async_pf_hash_fn(gfn);
8089
8090 while (vcpu->arch.apf.gfns[key] != ~0)
8091 key = kvm_async_pf_next_probe(key);
8092
8093 vcpu->arch.apf.gfns[key] = gfn;
8094}
8095
8096static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8097{
8098 int i;
8099 u32 key = kvm_async_pf_hash_fn(gfn);
8100
8101 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8102 (vcpu->arch.apf.gfns[key] != gfn &&
8103 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8104 key = kvm_async_pf_next_probe(key);
8105
8106 return key;
8107}
8108
8109bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8110{
8111 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8112}
8113
8114static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8115{
8116 u32 i, j, k;
8117
8118 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8119 while (true) {
8120 vcpu->arch.apf.gfns[i] = ~0;
8121 do {
8122 j = kvm_async_pf_next_probe(j);
8123 if (vcpu->arch.apf.gfns[j] == ~0)
8124 return;
8125 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8126 /*
8127 * k lies cyclically in ]i,j]
8128 * | i.k.j |
8129 * |....j i.k.| or |.k..j i...|
8130 */
8131 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8132 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8133 i = j;
8134 }
8135}
8136
7c90705b
GN		 8137static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8138{
8139
8140 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8141 sizeof(val));
8142}
8143
af585b92
GN		 8144void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8145 struct kvm_async_pf *work)
8146{
6389ee94
AK		 8147 struct x86_exception fault;
8148
7c90705b 8149 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8150 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8151
8152 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8153 (vcpu->arch.apf.send_user_only &&
8154 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8155 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8156 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8157 fault.vector = PF_VECTOR;
8158 fault.error_code_valid = true;
8159 fault.error_code = 0;
8160 fault.nested_page_fault = false;
8161 fault.address = work->arch.token;
8162 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8163 }
af585b92
GN		 8164}
8165
8166void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8167 struct kvm_async_pf *work)
8168{
6389ee94
AK		 8169 struct x86_exception fault;
8170
7c90705b 8171 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8172 if (work->wakeup_all)
7c90705b
GN		 8173 work->arch.token = ~0; /* broadcast wakeup */
8174 else
8175 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8176
8177 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8178 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8179 fault.vector = PF_VECTOR;
8180 fault.error_code_valid = true;
8181 fault.error_code = 0;
8182 fault.nested_page_fault = false;
8183 fault.address = work->arch.token;
8184 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8185 }
e6d53e3b 8186 vcpu->arch.apf.halted = false;
a4fa1635 8187 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8188}
8189
8190bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8191{
8192 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8193 return true;
8194 else
8195 return !kvm_event_needs_reinjection(vcpu) &&
8196 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8197}
8198
5544eb9b
PB		 8199void kvm_arch_start_assignment(struct kvm *kvm)
8200{
8201 atomic_inc(&kvm->arch.assigned_device_count);
8202}
8203EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8204
8205void kvm_arch_end_assignment(struct kvm *kvm)
8206{
8207 atomic_dec(&kvm->arch.assigned_device_count);
8208}
8209EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8210
8211bool kvm_arch_has_assigned_device(struct kvm *kvm)
8212{
8213 return atomic_read(&kvm->arch.assigned_device_count);
8214}
8215EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8216
e0f0bbc5
AW		 8217void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8218{
8219 atomic_inc(&kvm->arch.noncoherent_dma_count);
8220}
8221EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8222
8223void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8224{
8225 atomic_dec(&kvm->arch.noncoherent_dma_count);
8226}
8227EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8228
8229bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8230{
8231 return atomic_read(&kvm->arch.noncoherent_dma_count);
8232}
8233EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8234
87276880
FW		 8235int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8236 struct irq_bypass_producer *prod)
8237{
8238 struct kvm_kernel_irqfd *irqfd =
8239 container_of(cons, struct kvm_kernel_irqfd, consumer);
8240
8241 if (kvm_x86_ops->update_pi_irte) {
8242 irqfd->producer = prod;
8243 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8244 prod->irq, irqfd->gsi, 1);
8245 }
8246
8247 return -EINVAL;
8248}
8249
8250void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8251 struct irq_bypass_producer *prod)
8252{
8253 int ret;
8254 struct kvm_kernel_irqfd *irqfd =
8255 container_of(cons, struct kvm_kernel_irqfd, consumer);
8256
8257 if (!kvm_x86_ops->update_pi_irte) {
8258 WARN_ON(irqfd->producer != NULL);
8259 return;
8260 }
8261
8262 WARN_ON(irqfd->producer != prod);
8263 irqfd->producer = NULL;
8264
8265 /*
8266 * When producer of consumer is unregistered, we change back to
8267 * remapped mode, so we can re-use the current implementation
8268 * when the irq is masked/disabed or the consumer side (KVM
8269 * int this case doesn't want to receive the interrupts.
8270 */
8271 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8272 if (ret)
8273 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8274 " fails: %d\n", irqfd->consumer.token, ret);
8275}
8276
8277int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8278 uint32_t guest_irq, bool set)
8279{
8280 if (!kvm_x86_ops->update_pi_irte)
8281 return -EINVAL;
8282
8283 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8284}
8285
229456fc 8286EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8287EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8288EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8289EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8290EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8291EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8292EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8293EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8294EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8295EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8296EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8297EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8298EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8299EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8300EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8301EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8302EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
Linux 6.x block layer and io_uring tree(s)