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KVM: nVMX: introduce struct nested_vmx_msrs
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
b0c39dc6 70#include <asm/mshyperv.h>
0092e434 71#include <asm/hypervisor.h>
043405e1 72
d1898b73
DH		 73#define CREATE_TRACE_POINTS
74#include "trace.h"
75
313a3dc7 76#define MAX_IO_MSRS 256
890ca9ae 77#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 78u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
79EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 80
0f65dd70
AK		 81#define emul_to_vcpu(ctxt) \
82 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
83
50a37eb4
JR		 84/* EFER defaults:
85 * - enable syscall per default because its emulated by KVM
86 * - enable LME and LMA per default on 64 bit KVM
87 */
88#ifdef CONFIG_X86_64
1260edbe
LJ		 89static
90u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 91#else
1260edbe 92static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 93#endif
313a3dc7 94
ba1389b7
AK		 95#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
96#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 97
c519265f
RK		 98#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
99 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 100
cb142eb7 101static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 102static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 103static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 104static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 105static void store_regs(struct kvm_vcpu *vcpu);
106static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 107
893590c7 108struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 109EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 110
893590c7 111static bool __read_mostly ignore_msrs = 0;
476bc001 112module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 113
fab0aa3b
EM		 114static bool __read_mostly report_ignored_msrs = true;
115module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
116
9ed96e87
MT		 117unsigned int min_timer_period_us = 500;
118module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
119
630994b3
MT		 120static bool __read_mostly kvmclock_periodic_sync = true;
121module_param(kvmclock_periodic_sync, bool, S_IRUGO);
122
893590c7 123bool __read_mostly kvm_has_tsc_control;
92a1f12d 124EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 125u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 126EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 127u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
128EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
129u64 __read_mostly kvm_max_tsc_scaling_ratio;
130EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 131u64 __read_mostly kvm_default_tsc_scaling_ratio;
132EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 133
cc578287 134/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 135static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 136module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
137
d0659d94 138/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 139unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 140module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
141
52004014
FW		 142static bool __read_mostly vector_hashing = true;
143module_param(vector_hashing, bool, S_IRUGO);
144
18863bdd
AK		 145#define KVM_NR_SHARED_MSRS 16
146
147struct kvm_shared_msrs_global {
148 int nr;
2bf78fa7 149 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 150};
151
152struct kvm_shared_msrs {
153 struct user_return_notifier urn;
154 bool registered;
2bf78fa7
SY		 155 struct kvm_shared_msr_values {
156 u64 host;
157 u64 curr;
158 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 159};
160
161static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 162static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 163
417bc304 164struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 165 { "pf_fixed", VCPU_STAT(pf_fixed) },
166 { "pf_guest", VCPU_STAT(pf_guest) },
167 { "tlb_flush", VCPU_STAT(tlb_flush) },
168 { "invlpg", VCPU_STAT(invlpg) },
169 { "exits", VCPU_STAT(exits) },
170 { "io_exits", VCPU_STAT(io_exits) },
171 { "mmio_exits", VCPU_STAT(mmio_exits) },
172 { "signal_exits", VCPU_STAT(signal_exits) },
173 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 174 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 175 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 176 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 177 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 178 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 179 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 180 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 181 { "request_irq", VCPU_STAT(request_irq_exits) },
182 { "irq_exits", VCPU_STAT(irq_exits) },
183 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 184 { "fpu_reload", VCPU_STAT(fpu_reload) },
185 { "insn_emulation", VCPU_STAT(insn_emulation) },
186 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 187 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 188 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 189 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 190 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
191 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
192 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
193 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
194 { "mmu_flooded", VM_STAT(mmu_flooded) },
195 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 196 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 197 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 198 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 199 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 200 { "max_mmu_page_hash_collisions",
201 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 202 { NULL }
203};
204
2acf923e
DC		 205u64 __read_mostly host_xcr0;
206
b6785def 207static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 208
af585b92
GN		 209static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
210{
211 int i;
212 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
213 vcpu->arch.apf.gfns[i] = ~0;
214}
215
18863bdd
AK		 216static void kvm_on_user_return(struct user_return_notifier *urn)
217{
218 unsigned slot;
18863bdd
AK		 219 struct kvm_shared_msrs *locals
220 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 221 struct kvm_shared_msr_values *values;
1650b4eb
IA		 222 unsigned long flags;
223
224 /*
225 * Disabling irqs at this point since the following code could be
226 * interrupted and executed through kvm_arch_hardware_disable()
227 */
228 local_irq_save(flags);
229 if (locals->registered) {
230 locals->registered = false;
231 user_return_notifier_unregister(urn);
232 }
233 local_irq_restore(flags);
18863bdd 234 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 235 values = &locals->values[slot];
236 if (values->host != values->curr) {
237 wrmsrl(shared_msrs_global.msrs[slot], values->host);
238 values->curr = values->host;
18863bdd
AK		 239 }
240 }
18863bdd
AK		 241}
242
2bf78fa7 243static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 244{
18863bdd 245 u64 value;
013f6a5d
MT		 246 unsigned int cpu = smp_processor_id();
247 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 248
2bf78fa7
SY		 249 /* only read, and nobody should modify it at this time,
250 * so don't need lock */
251 if (slot >= shared_msrs_global.nr) {
252 printk(KERN_ERR "kvm: invalid MSR slot!");
253 return;
254 }
255 rdmsrl_safe(msr, &value);
256 smsr->values[slot].host = value;
257 smsr->values[slot].curr = value;
258}
259
260void kvm_define_shared_msr(unsigned slot, u32 msr)
261{
0123be42 262 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 263 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 264 if (slot >= shared_msrs_global.nr)
265 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 266}
267EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
268
269static void kvm_shared_msr_cpu_online(void)
270{
271 unsigned i;
18863bdd
AK		 272
273 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 274 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 275}
276
8b3c3104 277int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 278{
013f6a5d
MT		 279 unsigned int cpu = smp_processor_id();
280 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 281 int err;
18863bdd 282
2bf78fa7 283 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 284 return 0;
2bf78fa7 285 smsr->values[slot].curr = value;
8b3c3104
AH		 286 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
287 if (err)
288 return 1;
289
18863bdd
AK		 290 if (!smsr->registered) {
291 smsr->urn.on_user_return = kvm_on_user_return;
292 user_return_notifier_register(&smsr->urn);
293 smsr->registered = true;
294 }
8b3c3104 295 return 0;
18863bdd
AK		 296}
297EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
298
13a34e06 299static void drop_user_return_notifiers(void)
3548bab5 300{
013f6a5d
MT		 301 unsigned int cpu = smp_processor_id();
302 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 303
304 if (smsr->registered)
305 kvm_on_user_return(&smsr->urn);
306}
307
6866b83e
CO		 308u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
309{
8a5a87d9 310 return vcpu->arch.apic_base;
6866b83e
CO		 311}
312EXPORT_SYMBOL_GPL(kvm_get_apic_base);
313
58cb628d
JK		 314int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
315{
316 u64 old_state = vcpu->arch.apic_base &
317 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
318 u64 new_state = msr_info->data &
319 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK		 320 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
321 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 322
d3802286
JM		 323 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
324 return 1;
58cb628d 325 if (!msr_info->host_initiated &&
d3802286 326 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK		 327 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
328 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
329 old_state == 0)))
330 return 1;
331
332 kvm_lapic_set_base(vcpu, msr_info->data);
333 return 0;
6866b83e
CO		 334}
335EXPORT_SYMBOL_GPL(kvm_set_apic_base);
336
2605fc21 337asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 338{
339 /* Fault while not rebooting. We want the trace. */
340 BUG();
341}
342EXPORT_SYMBOL_GPL(kvm_spurious_fault);
343
3fd28fce
ED		 344#define EXCPT_BENIGN 0
345#define EXCPT_CONTRIBUTORY 1
346#define EXCPT_PF 2
347
348static int exception_class(int vector)
349{
350 switch (vector) {
351 case PF_VECTOR:
352 return EXCPT_PF;
353 case DE_VECTOR:
354 case TS_VECTOR:
355 case NP_VECTOR:
356 case SS_VECTOR:
357 case GP_VECTOR:
358 return EXCPT_CONTRIBUTORY;
359 default:
360 break;
361 }
362 return EXCPT_BENIGN;
363}
364
d6e8c854
NA		 365#define EXCPT_FAULT 0
366#define EXCPT_TRAP 1
367#define EXCPT_ABORT 2
368#define EXCPT_INTERRUPT 3
369
370static int exception_type(int vector)
371{
372 unsigned int mask;
373
374 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
375 return EXCPT_INTERRUPT;
376
377 mask = 1 << vector;
378
379 /* #DB is trap, as instruction watchpoints are handled elsewhere */
380 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
381 return EXCPT_TRAP;
382
383 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
384 return EXCPT_ABORT;
385
386 /* Reserved exceptions will result in fault */
387 return EXCPT_FAULT;
388}
389
3fd28fce 390static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 391 unsigned nr, bool has_error, u32 error_code,
392 bool reinject)
3fd28fce
ED		 393{
394 u32 prev_nr;
395 int class1, class2;
396
3842d135
AK		 397 kvm_make_request(KVM_REQ_EVENT, vcpu);
398
664f8e26 399 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 400 queue:
3ffb2468
NA		 401 if (has_error && !is_protmode(vcpu))
402 has_error = false;
664f8e26
WL		 403 if (reinject) {
404 /*
405 * On vmentry, vcpu->arch.exception.pending is only
406 * true if an event injection was blocked by
407 * nested_run_pending. In that case, however,
408 * vcpu_enter_guest requests an immediate exit,
409 * and the guest shouldn't proceed far enough to
410 * need reinjection.
411 */
412 WARN_ON_ONCE(vcpu->arch.exception.pending);
413 vcpu->arch.exception.injected = true;
414 } else {
415 vcpu->arch.exception.pending = true;
416 vcpu->arch.exception.injected = false;
417 }
3fd28fce
ED		 418 vcpu->arch.exception.has_error_code = has_error;
419 vcpu->arch.exception.nr = nr;
420 vcpu->arch.exception.error_code = error_code;
421 return;
422 }
423
424 /* to check exception */
425 prev_nr = vcpu->arch.exception.nr;
426 if (prev_nr == DF_VECTOR) {
427 /* triple fault -> shutdown */
a8eeb04a 428 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 429 return;
430 }
431 class1 = exception_class(prev_nr);
432 class2 = exception_class(nr);
433 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
434 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 435 /*
436 * Generate double fault per SDM Table 5-5. Set
437 * exception.pending = true so that the double fault
438 * can trigger a nested vmexit.
439 */
3fd28fce 440 vcpu->arch.exception.pending = true;
664f8e26 441 vcpu->arch.exception.injected = false;
3fd28fce
ED		 442 vcpu->arch.exception.has_error_code = true;
443 vcpu->arch.exception.nr = DF_VECTOR;
444 vcpu->arch.exception.error_code = 0;
445 } else
446 /* replace previous exception with a new one in a hope
447 that instruction re-execution will regenerate lost
448 exception */
449 goto queue;
450}
451
298101da
AK		 452void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
453{
ce7ddec4 454 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 455}
456EXPORT_SYMBOL_GPL(kvm_queue_exception);
457
ce7ddec4
JR		 458void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
459{
460 kvm_multiple_exception(vcpu, nr, false, 0, true);
461}
462EXPORT_SYMBOL_GPL(kvm_requeue_exception);
463
6affcbed 464int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 465{
db8fcefa
AP		 466 if (err)
467 kvm_inject_gp(vcpu, 0);
468 else
6affcbed
KH		 469 return kvm_skip_emulated_instruction(vcpu);
470
471 return 1;
db8fcefa
AP		 472}
473EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 474
6389ee94 475void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 476{
477 ++vcpu->stat.pf_guest;
adfe20fb
WL		 478 vcpu->arch.exception.nested_apf =
479 is_guest_mode(vcpu) && fault->async_page_fault;
480 if (vcpu->arch.exception.nested_apf)
481 vcpu->arch.apf.nested_apf_token = fault->address;
482 else
483 vcpu->arch.cr2 = fault->address;
6389ee94 484 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 485}
27d6c865 486EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 487
ef54bcfe 488static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 489{
6389ee94
AK		 490 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
491 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 492 else
6389ee94 493 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 494
495 return fault->nested_page_fault;
d4f8cf66
JR		 496}
497
3419ffc8
SY		 498void kvm_inject_nmi(struct kvm_vcpu *vcpu)
499{
7460fb4a
AK		 500 atomic_inc(&vcpu->arch.nmi_queued);
501 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 502}
503EXPORT_SYMBOL_GPL(kvm_inject_nmi);
504
298101da
AK		 505void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
506{
ce7ddec4 507 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 508}
509EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
510
ce7ddec4
JR		 511void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
512{
513 kvm_multiple_exception(vcpu, nr, true, error_code, true);
514}
515EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
516
0a79b009
AK		 517/*
518 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
519 * a #GP and return false.
520 */
521bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 522{
0a79b009
AK		 523 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
524 return true;
525 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
526 return false;
298101da 527}
0a79b009 528EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 529
16f8a6f9
NA		 530bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
531{
532 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
533 return true;
534
535 kvm_queue_exception(vcpu, UD_VECTOR);
536 return false;
537}
538EXPORT_SYMBOL_GPL(kvm_require_dr);
539
ec92fe44
JR		 540/*
541 * This function will be used to read from the physical memory of the currently
54bf36aa 542 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 543 * can read from guest physical or from the guest's guest physical memory.
544 */
545int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
546 gfn_t ngfn, void *data, int offset, int len,
547 u32 access)
548{
54987b7a 549 struct x86_exception exception;
ec92fe44
JR		 550 gfn_t real_gfn;
551 gpa_t ngpa;
552
553 ngpa = gfn_to_gpa(ngfn);
54987b7a 554 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 555 if (real_gfn == UNMAPPED_GVA)
556 return -EFAULT;
557
558 real_gfn = gpa_to_gfn(real_gfn);
559
54bf36aa 560 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 561}
562EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
563
69b0049a 564static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 565 void *data, int offset, int len, u32 access)
566{
567 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
568 data, offset, len, access);
569}
570
a03490ed
CO		 571/*
572 * Load the pae pdptrs. Return true is they are all valid.
573 */
ff03a073 574int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 575{
576 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
577 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
578 int i;
579 int ret;
ff03a073 580 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 581
ff03a073
JR		 582 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
583 offset * sizeof(u64), sizeof(pdpte),
584 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 585 if (ret < 0) {
586 ret = 0;
587 goto out;
588 }
589 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 590 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 591 (pdpte[i] &
592 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 593 ret = 0;
594 goto out;
595 }
596 }
597 ret = 1;
598
ff03a073 599 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 600 __set_bit(VCPU_EXREG_PDPTR,
601 (unsigned long *)&vcpu->arch.regs_avail);
602 __set_bit(VCPU_EXREG_PDPTR,
603 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 604out:
a03490ed
CO		 605
606 return ret;
607}
cc4b6871 608EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 609
9ed38ffa 610bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 611{
ff03a073 612 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 613 bool changed = true;
3d06b8bf
JR		 614 int offset;
615 gfn_t gfn;
d835dfec
AK		 616 int r;
617
618 if (is_long_mode(vcpu) || !is_pae(vcpu))
619 return false;
620
6de4f3ad
AK		 621 if (!test_bit(VCPU_EXREG_PDPTR,
622 (unsigned long *)&vcpu->arch.regs_avail))
623 return true;
624
a512177e
PB		 625 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
626 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 627 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
628 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 629 if (r < 0)
630 goto out;
ff03a073 631 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 632out:
d835dfec
AK		 633
634 return changed;
635}
9ed38ffa 636EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 637
49a9b07e 638int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 639{
aad82703 640 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 641 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 642
f9a48e6a
AK		 643 cr0 |= X86_CR0_ET;
644
ab344828 645#ifdef CONFIG_X86_64
0f12244f
GN		 646 if (cr0 & 0xffffffff00000000UL)
647 return 1;
ab344828
GN		 648#endif
649
650 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 651
0f12244f
GN		 652 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
653 return 1;
a03490ed 654
0f12244f
GN		 655 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
656 return 1;
a03490ed
CO		 657
658 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
659#ifdef CONFIG_X86_64
f6801dff 660 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 661 int cs_db, cs_l;
662
0f12244f
GN		 663 if (!is_pae(vcpu))
664 return 1;
a03490ed 665 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 666 if (cs_l)
667 return 1;
a03490ed
CO		 668 } else
669#endif
ff03a073 670 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 671 kvm_read_cr3(vcpu)))
0f12244f 672 return 1;
a03490ed
CO		 673 }
674
ad756a16
MJ		 675 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
676 return 1;
677
a03490ed 678 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 679
d170c419 680 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 681 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 682 kvm_async_pf_hash_reset(vcpu);
683 }
e5f3f027 684
aad82703
SY		 685 if ((cr0 ^ old_cr0) & update_bits)
686 kvm_mmu_reset_context(vcpu);
b18d5431 687
879ae188
LE		 688 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
689 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
690 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 691 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
692
0f12244f
GN		 693 return 0;
694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 696
2d3ad1f4 697void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 698{
49a9b07e 699 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 700}
2d3ad1f4 701EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 702
42bdf991
MT		 703static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
704{
705 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
706 !vcpu->guest_xcr0_loaded) {
707 /* kvm_set_xcr() also depends on this */
476b7ada
PB		 708 if (vcpu->arch.xcr0 != host_xcr0)
709 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
42bdf991
MT		 710 vcpu->guest_xcr0_loaded = 1;
711 }
712}
713
714static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
715{
716 if (vcpu->guest_xcr0_loaded) {
717 if (vcpu->arch.xcr0 != host_xcr0)
718 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
719 vcpu->guest_xcr0_loaded = 0;
720 }
721}
722
69b0049a 723static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 724{
56c103ec
LJ		 725 u64 xcr0 = xcr;
726 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 727 u64 valid_bits;
2acf923e
DC		 728
729 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
730 if (index != XCR_XFEATURE_ENABLED_MASK)
731 return 1;
d91cab78 732 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 733 return 1;
d91cab78 734 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 735 return 1;
46c34cb0
PB		 736
737 /*
738 * Do not allow the guest to set bits that we do not support
739 * saving. However, xcr0 bit 0 is always set, even if the
740 * emulated CPU does not support XSAVE (see fx_init).
741 */
d91cab78 742 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 743 if (xcr0 & ~valid_bits)
2acf923e 744 return 1;
46c34cb0 745
d91cab78
DH		 746 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
747 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 748 return 1;
749
d91cab78
DH		 750 if (xcr0 & XFEATURE_MASK_AVX512) {
751 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 752 return 1;
d91cab78 753 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 754 return 1;
755 }
2acf923e 756 vcpu->arch.xcr0 = xcr0;
56c103ec 757
d91cab78 758 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 759 kvm_update_cpuid(vcpu);
2acf923e
DC		 760 return 0;
761}
762
763int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
764{
764bcbc5
Z		 765 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
766 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 767 kvm_inject_gp(vcpu, 0);
768 return 1;
769 }
770 return 0;
771}
772EXPORT_SYMBOL_GPL(kvm_set_xcr);
773
a83b29c6 774int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 775{
fc78f519 776 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 777 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 778 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 779
0f12244f
GN		 780 if (cr4 & CR4_RESERVED_BITS)
781 return 1;
a03490ed 782
d6321d49 783 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC		 784 return 1;
785
d6321d49 786 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC		 787 return 1;
788
d6321d49 789 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW		 790 return 1;
791
d6321d49 792 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW		 793 return 1;
794
d6321d49 795 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW		 796 return 1;
797
fd8cb433 798 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH		 799 return 1;
800
ae3e61e1
PB		 801 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
802 return 1;
803
a03490ed 804 if (is_long_mode(vcpu)) {
0f12244f
GN		 805 if (!(cr4 & X86_CR4_PAE))
806 return 1;
a2edf57f
AK		 807 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
808 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 809 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
810 kvm_read_cr3(vcpu)))
0f12244f
GN		 811 return 1;
812
ad756a16 813 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 814 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 815 return 1;
816
817 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
818 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
819 return 1;
820 }
821
5e1746d6 822 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 823 return 1;
a03490ed 824
ad756a16
MJ		 825 if (((cr4 ^ old_cr4) & pdptr_bits) ||
826 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 827 kvm_mmu_reset_context(vcpu);
0f12244f 828
b9baba86 829 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 830 kvm_update_cpuid(vcpu);
2acf923e 831
0f12244f
GN		 832 return 0;
833}
2d3ad1f4 834EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 835
2390218b 836int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 837{
ac146235 838#ifdef CONFIG_X86_64
9d88fca7 839 cr3 &= ~CR3_PCID_INVD;
ac146235 840#endif
9d88fca7 841
9f8fe504 842 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 843 kvm_mmu_sync_roots(vcpu);
77c3913b 844 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 845 return 0;
d835dfec
AK		 846 }
847
d1cd3ce9
YZ		 848 if (is_long_mode(vcpu) &&
849 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
850 return 1;
851 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 852 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 853 return 1;
a03490ed 854
0f12244f 855 vcpu->arch.cr3 = cr3;
aff48baa 856 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 857 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 858 return 0;
859}
2d3ad1f4 860EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 861
eea1cff9 862int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 863{
0f12244f
GN		 864 if (cr8 & CR8_RESERVED_BITS)
865 return 1;
35754c98 866 if (lapic_in_kernel(vcpu))
a03490ed
CO		 867 kvm_lapic_set_tpr(vcpu, cr8);
868 else
ad312c7c 869 vcpu->arch.cr8 = cr8;
0f12244f
GN		 870 return 0;
871}
2d3ad1f4 872EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 873
2d3ad1f4 874unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 875{
35754c98 876 if (lapic_in_kernel(vcpu))
a03490ed
CO		 877 return kvm_lapic_get_cr8(vcpu);
878 else
ad312c7c 879 return vcpu->arch.cr8;
a03490ed 880}
2d3ad1f4 881EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 882
ae561ede
NA		 883static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
884{
885 int i;
886
887 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
888 for (i = 0; i < KVM_NR_DB_REGS; i++)
889 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
890 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
891 }
892}
893
73aaf249
JK		 894static void kvm_update_dr6(struct kvm_vcpu *vcpu)
895{
896 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
897 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
898}
899
c8639010
JK		 900static void kvm_update_dr7(struct kvm_vcpu *vcpu)
901{
902 unsigned long dr7;
903
904 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
905 dr7 = vcpu->arch.guest_debug_dr7;
906 else
907 dr7 = vcpu->arch.dr7;
908 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 909 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
910 if (dr7 & DR7_BP_EN_MASK)
911 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 912}
913
6f43ed01
NA		 914static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
915{
916 u64 fixed = DR6_FIXED_1;
917
d6321d49 918 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 919 fixed |= DR6_RTM;
920 return fixed;
921}
922
338dbc97 923static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 924{
925 switch (dr) {
926 case 0 ... 3:
927 vcpu->arch.db[dr] = val;
928 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
929 vcpu->arch.eff_db[dr] = val;
930 break;
931 case 4:
020df079
GN		 932 /* fall through */
933 case 6:
338dbc97
GN		 934 if (val & 0xffffffff00000000ULL)
935 return -1; /* #GP */
6f43ed01 936 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 937 kvm_update_dr6(vcpu);
020df079
GN		 938 break;
939 case 5:
020df079
GN		 940 /* fall through */
941 default: /* 7 */
338dbc97
GN		 942 if (val & 0xffffffff00000000ULL)
943 return -1; /* #GP */
020df079 944 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 945 kvm_update_dr7(vcpu);
020df079
GN		 946 break;
947 }
948
949 return 0;
950}
338dbc97
GN		 951
952int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
953{
16f8a6f9 954 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 955 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 956 return 1;
957 }
958 return 0;
338dbc97 959}
020df079
GN		 960EXPORT_SYMBOL_GPL(kvm_set_dr);
961
16f8a6f9 962int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 963{
964 switch (dr) {
965 case 0 ... 3:
966 *val = vcpu->arch.db[dr];
967 break;
968 case 4:
020df079
GN		 969 /* fall through */
970 case 6:
73aaf249
JK		 971 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
972 *val = vcpu->arch.dr6;
973 else
974 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 975 break;
976 case 5:
020df079
GN		 977 /* fall through */
978 default: /* 7 */
979 *val = vcpu->arch.dr7;
980 break;
981 }
338dbc97
GN		 982 return 0;
983}
020df079
GN		 984EXPORT_SYMBOL_GPL(kvm_get_dr);
985
022cd0e8
AK		 986bool kvm_rdpmc(struct kvm_vcpu *vcpu)
987{
988 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
989 u64 data;
990 int err;
991
c6702c9d 992 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 993 if (err)
994 return err;
995 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
996 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
997 return err;
998}
999EXPORT_SYMBOL_GPL(kvm_rdpmc);
1000
043405e1
CO		 1001/*
1002 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1003 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1004 *
1005 * This list is modified at module load time to reflect the
e3267cbb 1006 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 1007 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1008 * may depend on host virtualization features rather than host cpu features.
043405e1 1009 */
e3267cbb 1010
043405e1
CO		 1011static u32 msrs_to_save[] = {
1012 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1013 MSR_STAR,
043405e1
CO		 1014#ifdef CONFIG_X86_64
1015 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1016#endif
b3897a49 1017 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1018 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
d28b387f 1019 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO		 1020};
1021
1022static unsigned num_msrs_to_save;
1023
62ef68bb
PB		 1024static u32 emulated_msrs[] = {
1025 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1026 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1027 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1028 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1029 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1030 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1031 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1032 HV_X64_MSR_RESET,
11c4b1ca 1033 HV_X64_MSR_VP_INDEX,
9eec50b8 1034 HV_X64_MSR_VP_RUNTIME,
5c919412 1035 HV_X64_MSR_SCONTROL,
1f4b34f8 1036 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1037 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1038 MSR_KVM_PV_EOI_EN,
1039
ba904635 1040 MSR_IA32_TSC_ADJUST,
a3e06bbe 1041 MSR_IA32_TSCDEADLINE,
043405e1 1042 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1043 MSR_IA32_MCG_STATUS,
1044 MSR_IA32_MCG_CTL,
c45dcc71 1045 MSR_IA32_MCG_EXT_CTL,
64d60670 1046 MSR_IA32_SMBASE,
52797bf9 1047 MSR_SMI_COUNT,
db2336a8
KH		 1048 MSR_PLATFORM_INFO,
1049 MSR_MISC_FEATURES_ENABLES,
043405e1
CO		 1050};
1051
62ef68bb
PB		 1052static unsigned num_emulated_msrs;
1053
801e459a
TL		 1054/*
1055 * List of msr numbers which are used to expose MSR-based features that
1056 * can be used by a hypervisor to validate requested CPU features.
1057 */
1058static u32 msr_based_features[] = {
d1d93fa9 1059 MSR_F10H_DECFG,
518e7b94 1060 MSR_IA32_UCODE_REV,
801e459a
TL		 1061};
1062
1063static unsigned int num_msr_based_features;
1064
66421c1e
WL		 1065static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1066{
1067 switch (msr->index) {
518e7b94
WL		 1068 case MSR_IA32_UCODE_REV:
1069 rdmsrl(msr->index, msr->data);
1070 break;
66421c1e
WL		 1071 default:
1072 if (kvm_x86_ops->get_msr_feature(msr))
1073 return 1;
1074 }
1075 return 0;
1076}
1077
801e459a
TL		 1078static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1079{
1080 struct kvm_msr_entry msr;
66421c1e 1081 int r;
801e459a
TL		 1082
1083 msr.index = index;
66421c1e
WL		 1084 r = kvm_get_msr_feature(&msr);
1085 if (r)
1086 return r;
801e459a
TL		 1087
1088 *data = msr.data;
1089
1090 return 0;
1091}
1092
384bb783 1093bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1094{
b69e8cae 1095 if (efer & efer_reserved_bits)
384bb783 1096 return false;
15c4a640 1097
1b4d56b8 1098 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1099 return false;
1b2fd70c 1100
1b4d56b8 1101 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1102 return false;
d8017474 1103
384bb783
JK		 1104 return true;
1105}
1106EXPORT_SYMBOL_GPL(kvm_valid_efer);
1107
1108static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1109{
1110 u64 old_efer = vcpu->arch.efer;
1111
1112 if (!kvm_valid_efer(vcpu, efer))
1113 return 1;
1114
1115 if (is_paging(vcpu)
1116 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1117 return 1;
1118
15c4a640 1119 efer &= ~EFER_LMA;
f6801dff 1120 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1121
a3d204e2
SY		 1122 kvm_x86_ops->set_efer(vcpu, efer);
1123
aad82703
SY		 1124 /* Update reserved bits */
1125 if ((efer ^ old_efer) & EFER_NX)
1126 kvm_mmu_reset_context(vcpu);
1127
b69e8cae 1128 return 0;
15c4a640
CO		 1129}
1130
f2b4b7dd
JR		 1131void kvm_enable_efer_bits(u64 mask)
1132{
1133 efer_reserved_bits &= ~mask;
1134}
1135EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1136
15c4a640
CO		 1137/*
1138 * Writes msr value into into the appropriate "register".
1139 * Returns 0 on success, non-0 otherwise.
1140 * Assumes vcpu_load() was already called.
1141 */
8fe8ab46 1142int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1143{
854e8bb1
NA		 1144 switch (msr->index) {
1145 case MSR_FS_BASE:
1146 case MSR_GS_BASE:
1147 case MSR_KERNEL_GS_BASE:
1148 case MSR_CSTAR:
1149 case MSR_LSTAR:
fd8cb433 1150 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA		 1151 return 1;
1152 break;
1153 case MSR_IA32_SYSENTER_EIP:
1154 case MSR_IA32_SYSENTER_ESP:
1155 /*
1156 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1157 * non-canonical address is written on Intel but not on
1158 * AMD (which ignores the top 32-bits, because it does
1159 * not implement 64-bit SYSENTER).
1160 *
1161 * 64-bit code should hence be able to write a non-canonical
1162 * value on AMD. Making the address canonical ensures that
1163 * vmentry does not fail on Intel after writing a non-canonical
1164 * value, and that something deterministic happens if the guest
1165 * invokes 64-bit SYSENTER.
1166 */
fd8cb433 1167 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1168 }
8fe8ab46 1169 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1170}
854e8bb1 1171EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1172
313a3dc7
CO		 1173/*
1174 * Adapt set_msr() to msr_io()'s calling convention
1175 */
609e36d3
PB		 1176static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1177{
1178 struct msr_data msr;
1179 int r;
1180
1181 msr.index = index;
1182 msr.host_initiated = true;
1183 r = kvm_get_msr(vcpu, &msr);
1184 if (r)
1185 return r;
1186
1187 *data = msr.data;
1188 return 0;
1189}
1190
313a3dc7
CO		 1191static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1192{
8fe8ab46
WA		 1193 struct msr_data msr;
1194
1195 msr.data = *data;
1196 msr.index = index;
1197 msr.host_initiated = true;
1198 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1199}
1200
16e8d74d
MT		 1201#ifdef CONFIG_X86_64
1202struct pvclock_gtod_data {
1203 seqcount_t seq;
1204
1205 struct { /* extract of a clocksource struct */
1206 int vclock_mode;
a5a1d1c2
TG		 1207 u64 cycle_last;
1208 u64 mask;
16e8d74d
MT		 1209 u32 mult;
1210 u32 shift;
1211 } clock;
1212
cbcf2dd3
TG		 1213 u64 boot_ns;
1214 u64 nsec_base;
55dd00a7 1215 u64 wall_time_sec;
16e8d74d
MT		 1216};
1217
1218static struct pvclock_gtod_data pvclock_gtod_data;
1219
1220static void update_pvclock_gtod(struct timekeeper *tk)
1221{
1222 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1223 u64 boot_ns;
1224
876e7881 1225 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1226
1227 write_seqcount_begin(&vdata->seq);
1228
1229 /* copy pvclock gtod data */
876e7881
PZ		 1230 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1231 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1232 vdata->clock.mask = tk->tkr_mono.mask;
1233 vdata->clock.mult = tk->tkr_mono.mult;
1234 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1235
cbcf2dd3 1236 vdata->boot_ns = boot_ns;
876e7881 1237 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1238
55dd00a7
MT		 1239 vdata->wall_time_sec = tk->xtime_sec;
1240
16e8d74d
MT		 1241 write_seqcount_end(&vdata->seq);
1242}
1243#endif
1244
bab5bb39
NK		 1245void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1246{
1247 /*
1248 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1249 * vcpu_enter_guest. This function is only called from
1250 * the physical CPU that is running vcpu.
1251 */
1252 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1253}
16e8d74d 1254
18068523
GOC		 1255static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1256{
9ed3c444
AK		 1257 int version;
1258 int r;
50d0a0f9 1259 struct pvclock_wall_clock wc;
87aeb54f 1260 struct timespec64 boot;
18068523
GOC		 1261
1262 if (!wall_clock)
1263 return;
1264
9ed3c444
AK		 1265 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1266 if (r)
1267 return;
1268
1269 if (version & 1)
1270 ++version; /* first time write, random junk */
1271
1272 ++version;
18068523 1273
1dab1345
NK		 1274 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1275 return;
18068523 1276
50d0a0f9
GH		 1277 /*
1278 * The guest calculates current wall clock time by adding
34c238a1 1279 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1280 * wall clock specified here. guest system time equals host
1281 * system time for us, thus we must fill in host boot time here.
1282 */
87aeb54f 1283 getboottime64(&boot);
50d0a0f9 1284
4b648665 1285 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1286 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1287 boot = timespec64_sub(boot, ts);
4b648665 1288 }
87aeb54f 1289 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1290 wc.nsec = boot.tv_nsec;
1291 wc.version = version;
18068523
GOC		 1292
1293 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1294
1295 version++;
1296 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1297}
1298
50d0a0f9
GH		 1299static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1300{
b51012de
PB		 1301 do_shl32_div32(dividend, divisor);
1302 return dividend;
50d0a0f9
GH		 1303}
1304
3ae13faa 1305static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1306 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1307{
5f4e3f88 1308 uint64_t scaled64;
50d0a0f9
GH		 1309 int32_t shift = 0;
1310 uint64_t tps64;
1311 uint32_t tps32;
1312
3ae13faa
PB		 1313 tps64 = base_hz;
1314 scaled64 = scaled_hz;
50933623 1315 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1316 tps64 >>= 1;
1317 shift--;
1318 }
1319
1320 tps32 = (uint32_t)tps64;
50933623
JK		 1321 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1322 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1323 scaled64 >>= 1;
1324 else
1325 tps32 <<= 1;
50d0a0f9
GH		 1326 shift++;
1327 }
1328
5f4e3f88
ZA		 1329 *pshift = shift;
1330 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1331
3ae13faa
PB		 1332 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1333 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1334}
1335
d828199e 1336#ifdef CONFIG_X86_64
16e8d74d 1337static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1338#endif
16e8d74d 1339
c8076604 1340static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1341static unsigned long max_tsc_khz;
c8076604 1342
cc578287 1343static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1344{
cc578287
ZA		 1345 u64 v = (u64)khz * (1000000 + ppm);
1346 do_div(v, 1000000);
1347 return v;
1e993611
JR		 1348}
1349
381d585c
HZ		 1350static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1351{
1352 u64 ratio;
1353
1354 /* Guest TSC same frequency as host TSC? */
1355 if (!scale) {
1356 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1357 return 0;
1358 }
1359
1360 /* TSC scaling supported? */
1361 if (!kvm_has_tsc_control) {
1362 if (user_tsc_khz > tsc_khz) {
1363 vcpu->arch.tsc_catchup = 1;
1364 vcpu->arch.tsc_always_catchup = 1;
1365 return 0;
1366 } else {
1367 WARN(1, "user requested TSC rate below hardware speed\n");
1368 return -1;
1369 }
1370 }
1371
1372 /* TSC scaling required - calculate ratio */
1373 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1374 user_tsc_khz, tsc_khz);
1375
1376 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1377 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1378 user_tsc_khz);
1379 return -1;
1380 }
1381
1382 vcpu->arch.tsc_scaling_ratio = ratio;
1383 return 0;
1384}
1385
4941b8cb 1386static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1387{
cc578287
ZA		 1388 u32 thresh_lo, thresh_hi;
1389 int use_scaling = 0;
217fc9cf 1390
03ba32ca 1391 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1392 if (user_tsc_khz == 0) {
ad721883
HZ		 1393 /* set tsc_scaling_ratio to a safe value */
1394 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1395 return -1;
ad721883 1396 }
03ba32ca 1397
c285545f 1398 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1399 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1400 &vcpu->arch.virtual_tsc_shift,
1401 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1402 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1403
1404 /*
1405 * Compute the variation in TSC rate which is acceptable
1406 * within the range of tolerance and decide if the
1407 * rate being applied is within that bounds of the hardware
1408 * rate. If so, no scaling or compensation need be done.
1409 */
1410 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1411 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1412 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1413 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1414 use_scaling = 1;
1415 }
4941b8cb 1416 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1417}
1418
1419static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1420{
e26101b1 1421 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1422 vcpu->arch.virtual_tsc_mult,
1423 vcpu->arch.virtual_tsc_shift);
e26101b1 1424 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1425 return tsc;
1426}
1427
b0c39dc6
VK		 1428static inline int gtod_is_based_on_tsc(int mode)
1429{
1430 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1431}
1432
69b0049a 1433static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1434{
1435#ifdef CONFIG_X86_64
1436 bool vcpus_matched;
b48aa97e
MT		 1437 struct kvm_arch *ka = &vcpu->kvm->arch;
1438 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1439
1440 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1441 atomic_read(&vcpu->kvm->online_vcpus));
1442
7f187922
MT		 1443 /*
1444 * Once the masterclock is enabled, always perform request in
1445 * order to update it.
1446 *
1447 * In order to enable masterclock, the host clocksource must be TSC
1448 * and the vcpus need to have matched TSCs. When that happens,
1449 * perform request to enable masterclock.
1450 */
1451 if (ka->use_master_clock ||
b0c39dc6 1452 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1453 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1454
1455 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1456 atomic_read(&vcpu->kvm->online_vcpus),
1457 ka->use_master_clock, gtod->clock.vclock_mode);
1458#endif
1459}
1460
ba904635
WA		 1461static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1462{
3e3f5026 1463 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1464 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1465}
1466
35181e86
HZ		 1467/*
1468 * Multiply tsc by a fixed point number represented by ratio.
1469 *
1470 * The most significant 64-N bits (mult) of ratio represent the
1471 * integral part of the fixed point number; the remaining N bits
1472 * (frac) represent the fractional part, ie. ratio represents a fixed
1473 * point number (mult + frac * 2^(-N)).
1474 *
1475 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1476 */
1477static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1478{
1479 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1480}
1481
1482u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1483{
1484 u64 _tsc = tsc;
1485 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1486
1487 if (ratio != kvm_default_tsc_scaling_ratio)
1488 _tsc = __scale_tsc(ratio, tsc);
1489
1490 return _tsc;
1491}
1492EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1493
07c1419a
HZ		 1494static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1495{
1496 u64 tsc;
1497
1498 tsc = kvm_scale_tsc(vcpu, rdtsc());
1499
1500 return target_tsc - tsc;
1501}
1502
4ba76538
HZ		 1503u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1504{
ea26e4ec 1505 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1506}
1507EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1508
a545ab6a
LC		 1509static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1510{
1511 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1512 vcpu->arch.tsc_offset = offset;
1513}
1514
b0c39dc6
VK		 1515static inline bool kvm_check_tsc_unstable(void)
1516{
1517#ifdef CONFIG_X86_64
1518 /*
1519 * TSC is marked unstable when we're running on Hyper-V,
1520 * 'TSC page' clocksource is good.
1521 */
1522 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1523 return false;
1524#endif
1525 return check_tsc_unstable();
1526}
1527
8fe8ab46 1528void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1529{
1530 struct kvm *kvm = vcpu->kvm;
f38e098f 1531 u64 offset, ns, elapsed;
99e3e30a 1532 unsigned long flags;
b48aa97e 1533 bool matched;
0d3da0d2 1534 bool already_matched;
8fe8ab46 1535 u64 data = msr->data;
c5e8ec8e 1536 bool synchronizing = false;
99e3e30a 1537
038f8c11 1538 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1539 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1540 ns = ktime_get_boot_ns();
f38e098f 1541 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1542
03ba32ca 1543 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1544 if (data == 0 && msr->host_initiated) {
1545 /*
1546 * detection of vcpu initialization -- need to sync
1547 * with other vCPUs. This particularly helps to keep
1548 * kvm_clock stable after CPU hotplug
1549 */
1550 synchronizing = true;
1551 } else {
1552 u64 tsc_exp = kvm->arch.last_tsc_write +
1553 nsec_to_cycles(vcpu, elapsed);
1554 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1555 /*
1556 * Special case: TSC write with a small delta (1 second)
1557 * of virtual cycle time against real time is
1558 * interpreted as an attempt to synchronize the CPU.
1559 */
1560 synchronizing = data < tsc_exp + tsc_hz &&
1561 data + tsc_hz > tsc_exp;
1562 }
c5e8ec8e 1563 }
f38e098f
ZA		 1564
1565 /*
5d3cb0f6
ZA		 1566 * For a reliable TSC, we can match TSC offsets, and for an unstable
1567 * TSC, we add elapsed time in this computation. We could let the
1568 * compensation code attempt to catch up if we fall behind, but
1569 * it's better to try to match offsets from the beginning.
1570 */
c5e8ec8e 1571 if (synchronizing &&
5d3cb0f6 1572 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1573 if (!kvm_check_tsc_unstable()) {
e26101b1 1574 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1575 pr_debug("kvm: matched tsc offset for %llu\n", data);
1576 } else {
857e4099 1577 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1578 data += delta;
07c1419a 1579 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1580 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1581 }
b48aa97e 1582 matched = true;
0d3da0d2 1583 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1584 } else {
1585 /*
1586 * We split periods of matched TSC writes into generations.
1587 * For each generation, we track the original measured
1588 * nanosecond time, offset, and write, so if TSCs are in
1589 * sync, we can match exact offset, and if not, we can match
4a969980 1590 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1591 *
1592 * These values are tracked in kvm->arch.cur_xxx variables.
1593 */
1594 kvm->arch.cur_tsc_generation++;
1595 kvm->arch.cur_tsc_nsec = ns;
1596 kvm->arch.cur_tsc_write = data;
1597 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1598 matched = false;
0d3da0d2 1599 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1600 kvm->arch.cur_tsc_generation, data);
f38e098f 1601 }
e26101b1
ZA		 1602
1603 /*
1604 * We also track th most recent recorded KHZ, write and time to
1605 * allow the matching interval to be extended at each write.
1606 */
f38e098f
ZA		 1607 kvm->arch.last_tsc_nsec = ns;
1608 kvm->arch.last_tsc_write = data;
5d3cb0f6 1609 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1610
b183aa58 1611 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1612
1613 /* Keep track of which generation this VCPU has synchronized to */
1614 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1615 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1616 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1617
d6321d49 1618 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1619 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1620
a545ab6a 1621 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1622 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1623
1624 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1625 if (!matched) {
b48aa97e 1626 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1627 } else if (!already_matched) {
1628 kvm->arch.nr_vcpus_matched_tsc++;
1629 }
b48aa97e
MT		 1630
1631 kvm_track_tsc_matching(vcpu);
1632 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1633}
e26101b1 1634
99e3e30a
ZA		 1635EXPORT_SYMBOL_GPL(kvm_write_tsc);
1636
58ea6767
HZ		 1637static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1638 s64 adjustment)
1639{
ea26e4ec 1640 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1641}
1642
1643static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1644{
1645 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1646 WARN_ON(adjustment < 0);
1647 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1648 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1649}
1650
d828199e
MT		 1651#ifdef CONFIG_X86_64
1652
a5a1d1c2 1653static u64 read_tsc(void)
d828199e 1654{
a5a1d1c2 1655 u64 ret = (u64)rdtsc_ordered();
03b9730b 1656 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1657
1658 if (likely(ret >= last))
1659 return ret;
1660
1661 /*
1662 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1663 * predictable (it's just a function of time and the likely is
d828199e
MT		 1664 * very likely) and there's a data dependence, so force GCC
1665 * to generate a branch instead. I don't barrier() because
1666 * we don't actually need a barrier, and if this function
1667 * ever gets inlined it will generate worse code.
1668 */
1669 asm volatile ("");
1670 return last;
1671}
1672
b0c39dc6 1673static inline u64 vgettsc(u64 *tsc_timestamp, int *mode)
d828199e
MT		 1674{
1675 long v;
1676 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
b0c39dc6
VK		 1677 u64 tsc_pg_val;
1678
1679 switch (gtod->clock.vclock_mode) {
1680 case VCLOCK_HVCLOCK:
1681 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
1682 tsc_timestamp);
1683 if (tsc_pg_val != U64_MAX) {
1684 /* TSC page valid */
1685 *mode = VCLOCK_HVCLOCK;
1686 v = (tsc_pg_val - gtod->clock.cycle_last) &
1687 gtod->clock.mask;
1688 } else {
1689 /* TSC page invalid */
1690 *mode = VCLOCK_NONE;
1691 }
1692 break;
1693 case VCLOCK_TSC:
1694 *mode = VCLOCK_TSC;
1695 *tsc_timestamp = read_tsc();
1696 v = (*tsc_timestamp - gtod->clock.cycle_last) &
1697 gtod->clock.mask;
1698 break;
1699 default:
1700 *mode = VCLOCK_NONE;
1701 }
d828199e 1702
b0c39dc6
VK		 1703 if (*mode == VCLOCK_NONE)
1704 *tsc_timestamp = v = 0;
d828199e 1705
d828199e
MT		 1706 return v * gtod->clock.mult;
1707}
1708
b0c39dc6 1709static int do_monotonic_boot(s64 *t, u64 *tsc_timestamp)
d828199e 1710{
cbcf2dd3 1711 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1712 unsigned long seq;
d828199e 1713 int mode;
cbcf2dd3 1714 u64 ns;
d828199e 1715
d828199e
MT		 1716 do {
1717 seq = read_seqcount_begin(&gtod->seq);
cbcf2dd3 1718 ns = gtod->nsec_base;
b0c39dc6 1719 ns += vgettsc(tsc_timestamp, &mode);
d828199e 1720 ns >>= gtod->clock.shift;
cbcf2dd3 1721 ns += gtod->boot_ns;
d828199e 1722 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1723 *t = ns;
d828199e
MT		 1724
1725 return mode;
1726}
1727
b0c39dc6 1728static int do_realtime(struct timespec *ts, u64 *tsc_timestamp)
55dd00a7
MT		 1729{
1730 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1731 unsigned long seq;
1732 int mode;
1733 u64 ns;
1734
1735 do {
1736 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 1737 ts->tv_sec = gtod->wall_time_sec;
1738 ns = gtod->nsec_base;
b0c39dc6 1739 ns += vgettsc(tsc_timestamp, &mode);
55dd00a7
MT		 1740 ns >>= gtod->clock.shift;
1741 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1742
1743 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1744 ts->tv_nsec = ns;
1745
1746 return mode;
1747}
1748
b0c39dc6
VK		 1749/* returns true if host is using TSC based clocksource */
1750static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 1751{
d828199e 1752 /* checked again under seqlock below */
b0c39dc6 1753 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 1754 return false;
1755
b0c39dc6
VK		 1756 return gtod_is_based_on_tsc(do_monotonic_boot(kernel_ns,
1757 tsc_timestamp));
d828199e 1758}
55dd00a7 1759
b0c39dc6 1760/* returns true if host is using TSC based clocksource */
55dd00a7 1761static bool kvm_get_walltime_and_clockread(struct timespec *ts,
b0c39dc6 1762 u64 *tsc_timestamp)
55dd00a7
MT		 1763{
1764 /* checked again under seqlock below */
b0c39dc6 1765 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 1766 return false;
1767
b0c39dc6 1768 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 1769}
d828199e
MT		 1770#endif
1771
1772/*
1773 *
b48aa97e
MT		 1774 * Assuming a stable TSC across physical CPUS, and a stable TSC
1775 * across virtual CPUs, the following condition is possible.
1776 * Each numbered line represents an event visible to both
d828199e
MT		 1777 * CPUs at the next numbered event.
1778 *
1779 * "timespecX" represents host monotonic time. "tscX" represents
1780 * RDTSC value.
1781 *
1782 * VCPU0 on CPU0 | VCPU1 on CPU1
1783 *
1784 * 1. read timespec0,tsc0
1785 * 2. | timespec1 = timespec0 + N
1786 * | tsc1 = tsc0 + M
1787 * 3. transition to guest | transition to guest
1788 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1789 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1790 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1791 *
1792 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1793 *
1794 * - ret0 < ret1
1795 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1796 * ...
1797 * - 0 < N - M => M < N
1798 *
1799 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1800 * always the case (the difference between two distinct xtime instances
1801 * might be smaller then the difference between corresponding TSC reads,
1802 * when updating guest vcpus pvclock areas).
1803 *
1804 * To avoid that problem, do not allow visibility of distinct
1805 * system_timestamp/tsc_timestamp values simultaneously: use a master
1806 * copy of host monotonic time values. Update that master copy
1807 * in lockstep.
1808 *
b48aa97e 1809 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1810 *
1811 */
1812
1813static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1814{
1815#ifdef CONFIG_X86_64
1816 struct kvm_arch *ka = &kvm->arch;
1817 int vclock_mode;
b48aa97e
MT		 1818 bool host_tsc_clocksource, vcpus_matched;
1819
1820 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1821 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1822
1823 /*
1824 * If the host uses TSC clock, then passthrough TSC as stable
1825 * to the guest.
1826 */
b48aa97e 1827 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1828 &ka->master_kernel_ns,
1829 &ka->master_cycle_now);
1830
16a96021 1831 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1832 && !ka->backwards_tsc_observed
54750f2c 1833 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1834
d828199e
MT		 1835 if (ka->use_master_clock)
1836 atomic_set(&kvm_guest_has_master_clock, 1);
1837
1838 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1839 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1840 vcpus_matched);
d828199e
MT		 1841#endif
1842}
1843
2860c4b1
PB		 1844void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1845{
1846 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1847}
1848
2e762ff7
MT		 1849static void kvm_gen_update_masterclock(struct kvm *kvm)
1850{
1851#ifdef CONFIG_X86_64
1852 int i;
1853 struct kvm_vcpu *vcpu;
1854 struct kvm_arch *ka = &kvm->arch;
1855
1856 spin_lock(&ka->pvclock_gtod_sync_lock);
1857 kvm_make_mclock_inprogress_request(kvm);
1858 /* no guest entries from this point */
1859 pvclock_update_vm_gtod_copy(kvm);
1860
1861 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1862 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1863
1864 /* guest entries allowed */
1865 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1866 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 1867
1868 spin_unlock(&ka->pvclock_gtod_sync_lock);
1869#endif
1870}
1871
e891a32e 1872u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1873{
108b249c 1874 struct kvm_arch *ka = &kvm->arch;
8b953440 1875 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1876 u64 ret;
108b249c 1877
8b953440
PB		 1878 spin_lock(&ka->pvclock_gtod_sync_lock);
1879 if (!ka->use_master_clock) {
1880 spin_unlock(&ka->pvclock_gtod_sync_lock);
1881 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1882 }
1883
8b953440
PB		 1884 hv_clock.tsc_timestamp = ka->master_cycle_now;
1885 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1886 spin_unlock(&ka->pvclock_gtod_sync_lock);
1887
e2c2206a
WL		 1888 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1889 get_cpu();
1890
e70b57a6
WL		 1891 if (__this_cpu_read(cpu_tsc_khz)) {
1892 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1893 &hv_clock.tsc_shift,
1894 &hv_clock.tsc_to_system_mul);
1895 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1896 } else
1897 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL		 1898
1899 put_cpu();
1900
1901 return ret;
108b249c
PB		 1902}
1903
0d6dd2ff
PB		 1904static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1905{
1906 struct kvm_vcpu_arch *vcpu = &v->arch;
1907 struct pvclock_vcpu_time_info guest_hv_clock;
1908
4e335d9e 1909 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 1910 &guest_hv_clock, sizeof(guest_hv_clock))))
1911 return;
1912
1913 /* This VCPU is paused, but it's legal for a guest to read another
1914 * VCPU's kvmclock, so we really have to follow the specification where
1915 * it says that version is odd if data is being modified, and even after
1916 * it is consistent.
1917 *
1918 * Version field updates must be kept separate. This is because
1919 * kvm_write_guest_cached might use a "rep movs" instruction, and
1920 * writes within a string instruction are weakly ordered. So there
1921 * are three writes overall.
1922 *
1923 * As a small optimization, only write the version field in the first
1924 * and third write. The vcpu->pv_time cache is still valid, because the
1925 * version field is the first in the struct.
1926 */
1927 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1928
51c4b8bb
LA		 1929 if (guest_hv_clock.version & 1)
1930 ++guest_hv_clock.version; /* first time write, random junk */
1931
0d6dd2ff 1932 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 1933 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1934 &vcpu->hv_clock,
1935 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1936
1937 smp_wmb();
1938
1939 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1940 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1941
1942 if (vcpu->pvclock_set_guest_stopped_request) {
1943 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1944 vcpu->pvclock_set_guest_stopped_request = false;
1945 }
1946
1947 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1948
4e335d9e
PB		 1949 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1950 &vcpu->hv_clock,
1951 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1952
1953 smp_wmb();
1954
1955 vcpu->hv_clock.version++;
4e335d9e
PB		 1956 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1957 &vcpu->hv_clock,
1958 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1959}
1960
34c238a1 1961static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1962{
78db6a50 1963 unsigned long flags, tgt_tsc_khz;
18068523 1964 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1965 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1966 s64 kernel_ns;
d828199e 1967 u64 tsc_timestamp, host_tsc;
51d59c6b 1968 u8 pvclock_flags;
d828199e
MT		 1969 bool use_master_clock;
1970
1971 kernel_ns = 0;
1972 host_tsc = 0;
18068523 1973
d828199e
MT		 1974 /*
1975 * If the host uses TSC clock, then passthrough TSC as stable
1976 * to the guest.
1977 */
1978 spin_lock(&ka->pvclock_gtod_sync_lock);
1979 use_master_clock = ka->use_master_clock;
1980 if (use_master_clock) {
1981 host_tsc = ka->master_cycle_now;
1982 kernel_ns = ka->master_kernel_ns;
1983 }
1984 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1985
1986 /* Keep irq disabled to prevent changes to the clock */
1987 local_irq_save(flags);
78db6a50
PB		 1988 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1989 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1990 local_irq_restore(flags);
1991 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1992 return 1;
1993 }
d828199e 1994 if (!use_master_clock) {
4ea1636b 1995 host_tsc = rdtsc();
108b249c 1996 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1997 }
1998
4ba76538 1999 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2000
c285545f
ZA		 2001 /*
2002 * We may have to catch up the TSC to match elapsed wall clock
2003 * time for two reasons, even if kvmclock is used.
2004 * 1) CPU could have been running below the maximum TSC rate
2005 * 2) Broken TSC compensation resets the base at each VCPU
2006 * entry to avoid unknown leaps of TSC even when running
2007 * again on the same CPU. This may cause apparent elapsed
2008 * time to disappear, and the guest to stand still or run
2009 * very slowly.
2010 */
2011 if (vcpu->tsc_catchup) {
2012 u64 tsc = compute_guest_tsc(v, kernel_ns);
2013 if (tsc > tsc_timestamp) {
f1e2b260 2014 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2015 tsc_timestamp = tsc;
2016 }
50d0a0f9
GH		 2017 }
2018
18068523
GOC		 2019 local_irq_restore(flags);
2020
0d6dd2ff 2021 /* With all the info we got, fill in the values */
18068523 2022
78db6a50
PB		 2023 if (kvm_has_tsc_control)
2024 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2025
2026 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2027 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2028 &vcpu->hv_clock.tsc_shift,
2029 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2030 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2031 }
2032
1d5f066e 2033 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2034 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2035 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2036
d828199e 2037 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2038 pvclock_flags = 0;
d828199e
MT		 2039 if (use_master_clock)
2040 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2041
78c0337a
MT		 2042 vcpu->hv_clock.flags = pvclock_flags;
2043
095cf55d
PB		 2044 if (vcpu->pv_time_enabled)
2045 kvm_setup_pvclock_page(v);
2046 if (v == kvm_get_vcpu(v->kvm, 0))
2047 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2048 return 0;
c8076604
GH		 2049}
2050
0061d53d
MT		 2051/*
2052 * kvmclock updates which are isolated to a given vcpu, such as
2053 * vcpu->cpu migration, should not allow system_timestamp from
2054 * the rest of the vcpus to remain static. Otherwise ntp frequency
2055 * correction applies to one vcpu's system_timestamp but not
2056 * the others.
2057 *
2058 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2059 * We need to rate-limit these requests though, as they can
2060 * considerably slow guests that have a large number of vcpus.
2061 * The time for a remote vcpu to update its kvmclock is bound
2062 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2063 */
2064
7e44e449
AJ		 2065#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2066
2067static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2068{
2069 int i;
7e44e449
AJ		 2070 struct delayed_work *dwork = to_delayed_work(work);
2071 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2072 kvmclock_update_work);
2073 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2074 struct kvm_vcpu *vcpu;
2075
2076 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2077 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2078 kvm_vcpu_kick(vcpu);
2079 }
2080}
2081
7e44e449
AJ		 2082static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2083{
2084 struct kvm *kvm = v->kvm;
2085
105b21bb 2086 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2087 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2088 KVMCLOCK_UPDATE_DELAY);
2089}
2090
332967a3
AJ		 2091#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2092
2093static void kvmclock_sync_fn(struct work_struct *work)
2094{
2095 struct delayed_work *dwork = to_delayed_work(work);
2096 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2097 kvmclock_sync_work);
2098 struct kvm *kvm = container_of(ka, struct kvm, arch);
2099
630994b3
MT		 2100 if (!kvmclock_periodic_sync)
2101 return;
2102
332967a3
AJ		 2103 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2104 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2105 KVMCLOCK_SYNC_PERIOD);
2106}
2107
9ffd986c 2108static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2109{
890ca9ae
HY		 2110 u64 mcg_cap = vcpu->arch.mcg_cap;
2111 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2112 u32 msr = msr_info->index;
2113 u64 data = msr_info->data;
890ca9ae 2114
15c4a640 2115 switch (msr) {
15c4a640 2116 case MSR_IA32_MCG_STATUS:
890ca9ae 2117 vcpu->arch.mcg_status = data;
15c4a640 2118 break;
c7ac679c 2119 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2120 if (!(mcg_cap & MCG_CTL_P))
2121 return 1;
2122 if (data != 0 && data != ~(u64)0)
2123 return -1;
2124 vcpu->arch.mcg_ctl = data;
2125 break;
2126 default:
2127 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2128 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2129 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2130 /* only 0 or all 1s can be written to IA32_MCi_CTL
2131 * some Linux kernels though clear bit 10 in bank 4 to
2132 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2133 * this to avoid an uncatched #GP in the guest
2134 */
890ca9ae 2135 if ((offset & 0x3) == 0 &&
114be429 2136 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2137 return -1;
9ffd986c
WL		 2138 if (!msr_info->host_initiated &&
2139 (offset & 0x3) == 1 && data != 0)
2140 return -1;
890ca9ae
HY		 2141 vcpu->arch.mce_banks[offset] = data;
2142 break;
2143 }
2144 return 1;
2145 }
2146 return 0;
2147}
2148
ffde22ac
ES		 2149static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2150{
2151 struct kvm *kvm = vcpu->kvm;
2152 int lm = is_long_mode(vcpu);
2153 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2154 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2155 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2156 : kvm->arch.xen_hvm_config.blob_size_32;
2157 u32 page_num = data & ~PAGE_MASK;
2158 u64 page_addr = data & PAGE_MASK;
2159 u8 *page;
2160 int r;
2161
2162 r = -E2BIG;
2163 if (page_num >= blob_size)
2164 goto out;
2165 r = -ENOMEM;
ff5c2c03
SL		 2166 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2167 if (IS_ERR(page)) {
2168 r = PTR_ERR(page);
ffde22ac 2169 goto out;
ff5c2c03 2170 }
54bf36aa 2171 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2172 goto out_free;
2173 r = 0;
2174out_free:
2175 kfree(page);
2176out:
2177 return r;
2178}
2179
344d9588
GN		 2180static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2181{
2182 gpa_t gpa = data & ~0x3f;
2183
52a5c155
WL		 2184 /* Bits 3:5 are reserved, Should be zero */
2185 if (data & 0x38)
344d9588
GN		 2186 return 1;
2187
2188 vcpu->arch.apf.msr_val = data;
2189
2190 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2191 kvm_clear_async_pf_completion_queue(vcpu);
2192 kvm_async_pf_hash_reset(vcpu);
2193 return 0;
2194 }
2195
4e335d9e 2196 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2197 sizeof(u32)))
344d9588
GN		 2198 return 1;
2199
6adba527 2200 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2201 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2202 kvm_async_pf_wakeup_all(vcpu);
2203 return 0;
2204}
2205
12f9a48f
GC		 2206static void kvmclock_reset(struct kvm_vcpu *vcpu)
2207{
0b79459b 2208 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2209}
2210
f38a7b75
WL		 2211static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2212{
2213 ++vcpu->stat.tlb_flush;
2214 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2215}
2216
c9aaa895
GC		 2217static void record_steal_time(struct kvm_vcpu *vcpu)
2218{
2219 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2220 return;
2221
4e335d9e 2222 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2223 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2224 return;
2225
f38a7b75
WL		 2226 /*
2227 * Doing a TLB flush here, on the guest's behalf, can avoid
2228 * expensive IPIs.
2229 */
2230 if (xchg(&vcpu->arch.st.steal.preempted, 0) & KVM_VCPU_FLUSH_TLB)
2231 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2232
35f3fae1
WL		 2233 if (vcpu->arch.st.steal.version & 1)
2234 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2235
2236 vcpu->arch.st.steal.version += 1;
2237
4e335d9e 2238 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2239 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2240
2241 smp_wmb();
2242
c54cdf14
LC		 2243 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2244 vcpu->arch.st.last_steal;
2245 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2246
4e335d9e 2247 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL		 2248 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2249
2250 smp_wmb();
2251
2252 vcpu->arch.st.steal.version += 1;
c9aaa895 2253
4e335d9e 2254 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC		 2255 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2256}
2257
8fe8ab46 2258int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2259{
5753785f 2260 bool pr = false;
8fe8ab46
WA		 2261 u32 msr = msr_info->index;
2262 u64 data = msr_info->data;
5753785f 2263
15c4a640 2264 switch (msr) {
2e32b719 2265 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2266 case MSR_IA32_UCODE_WRITE:
2267 case MSR_VM_HSAVE_PA:
2268 case MSR_AMD64_PATCH_LOADER:
2269 case MSR_AMD64_BU_CFG2:
405a353a 2270 case MSR_AMD64_DC_CFG:
2e32b719
BP		 2271 break;
2272
518e7b94
WL		 2273 case MSR_IA32_UCODE_REV:
2274 if (msr_info->host_initiated)
2275 vcpu->arch.microcode_version = data;
2276 break;
15c4a640 2277 case MSR_EFER:
b69e8cae 2278 return set_efer(vcpu, data);
8f1589d9
AP		 2279 case MSR_K7_HWCR:
2280 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2281 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2282 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2283 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2284 if (data != 0) {
a737f256
CD		 2285 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2286 data);
8f1589d9
AP		 2287 return 1;
2288 }
15c4a640 2289 break;
f7c6d140
AP		 2290 case MSR_FAM10H_MMIO_CONF_BASE:
2291 if (data != 0) {
a737f256
CD		 2292 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2293 "0x%llx\n", data);
f7c6d140
AP		 2294 return 1;
2295 }
15c4a640 2296 break;
b5e2fec0
AG		 2297 case MSR_IA32_DEBUGCTLMSR:
2298 if (!data) {
2299 /* We support the non-activated case already */
2300 break;
2301 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2302 /* Values other than LBR and BTF are vendor-specific,
2303 thus reserved and should throw a #GP */
2304 return 1;
2305 }
a737f256
CD		 2306 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2307 __func__, data);
b5e2fec0 2308 break;
9ba075a6 2309 case 0x200 ... 0x2ff:
ff53604b 2310 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2311 case MSR_IA32_APICBASE:
58cb628d 2312 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2313 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2314 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2315 case MSR_IA32_TSCDEADLINE:
2316 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2317 break;
ba904635 2318 case MSR_IA32_TSC_ADJUST:
d6321d49 2319 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2320 if (!msr_info->host_initiated) {
d913b904 2321 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2322 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2323 }
2324 vcpu->arch.ia32_tsc_adjust_msr = data;
2325 }
2326 break;
15c4a640 2327 case MSR_IA32_MISC_ENABLE:
ad312c7c 2328 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2329 break;
64d60670
PB		 2330 case MSR_IA32_SMBASE:
2331 if (!msr_info->host_initiated)
2332 return 1;
2333 vcpu->arch.smbase = data;
2334 break;
52797bf9
LA		 2335 case MSR_SMI_COUNT:
2336 if (!msr_info->host_initiated)
2337 return 1;
2338 vcpu->arch.smi_count = data;
2339 break;
11c6bffa 2340 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2341 case MSR_KVM_WALL_CLOCK:
2342 vcpu->kvm->arch.wall_clock = data;
2343 kvm_write_wall_clock(vcpu->kvm, data);
2344 break;
11c6bffa 2345 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2346 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2347 struct kvm_arch *ka = &vcpu->kvm->arch;
2348
12f9a48f 2349 kvmclock_reset(vcpu);
18068523 2350
54750f2c
MT		 2351 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2352 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2353
2354 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2355 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2356
2357 ka->boot_vcpu_runs_old_kvmclock = tmp;
2358 }
2359
18068523 2360 vcpu->arch.time = data;
0061d53d 2361 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2362
2363 /* we verify if the enable bit is set... */
2364 if (!(data & 1))
2365 break;
2366
4e335d9e 2367 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2368 &vcpu->arch.pv_time, data & ~1ULL,
2369 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2370 vcpu->arch.pv_time_enabled = false;
2371 else
2372 vcpu->arch.pv_time_enabled = true;
32cad84f 2373
18068523
GOC		 2374 break;
2375 }
344d9588
GN		 2376 case MSR_KVM_ASYNC_PF_EN:
2377 if (kvm_pv_enable_async_pf(vcpu, data))
2378 return 1;
2379 break;
c9aaa895
GC		 2380 case MSR_KVM_STEAL_TIME:
2381
2382 if (unlikely(!sched_info_on()))
2383 return 1;
2384
2385 if (data & KVM_STEAL_RESERVED_MASK)
2386 return 1;
2387
4e335d9e 2388 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2389 data & KVM_STEAL_VALID_BITS,
2390 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2391 return 1;
2392
2393 vcpu->arch.st.msr_val = data;
2394
2395 if (!(data & KVM_MSR_ENABLED))
2396 break;
2397
c9aaa895
GC		 2398 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2399
2400 break;
ae7a2a3f
MT		 2401 case MSR_KVM_PV_EOI_EN:
2402 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2403 return 1;
2404 break;
c9aaa895 2405
890ca9ae
HY		 2406 case MSR_IA32_MCG_CTL:
2407 case MSR_IA32_MCG_STATUS:
81760dcc 2408 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2409 return set_msr_mce(vcpu, msr_info);
71db6023 2410
6912ac32
WH		 2411 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2412 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2413 pr = true; /* fall through */
2414 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2415 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2416 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2417 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2418
2419 if (pr || data != 0)
a737f256
CD		 2420 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2421 "0x%x data 0x%llx\n", msr, data);
5753785f 2422 break;
84e0cefa
JS		 2423 case MSR_K7_CLK_CTL:
2424 /*
2425 * Ignore all writes to this no longer documented MSR.
2426 * Writes are only relevant for old K7 processors,
2427 * all pre-dating SVM, but a recommended workaround from
4a969980 2428 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2429 * affected processor models on the command line, hence
2430 * the need to ignore the workaround.
2431 */
2432 break;
55cd8e5a 2433 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2434 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2435 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2436 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2437 return kvm_hv_set_msr_common(vcpu, msr, data,
2438 msr_info->host_initiated);
91c9c3ed 2439 case MSR_IA32_BBL_CR_CTL3:
2440 /* Drop writes to this legacy MSR -- see rdmsr
2441 * counterpart for further detail.
2442 */
fab0aa3b
EM		 2443 if (report_ignored_msrs)
2444 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2445 msr, data);
91c9c3ed 2446 break;
2b036c6b 2447 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2448 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2449 return 1;
2450 vcpu->arch.osvw.length = data;
2451 break;
2452 case MSR_AMD64_OSVW_STATUS:
d6321d49 2453 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2454 return 1;
2455 vcpu->arch.osvw.status = data;
2456 break;
db2336a8
KH		 2457 case MSR_PLATFORM_INFO:
2458 if (!msr_info->host_initiated ||
2459 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2460 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2461 cpuid_fault_enabled(vcpu)))
2462 return 1;
2463 vcpu->arch.msr_platform_info = data;
2464 break;
2465 case MSR_MISC_FEATURES_ENABLES:
2466 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2467 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2468 !supports_cpuid_fault(vcpu)))
2469 return 1;
2470 vcpu->arch.msr_misc_features_enables = data;
2471 break;
15c4a640 2472 default:
ffde22ac
ES		 2473 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2474 return xen_hvm_config(vcpu, data);
c6702c9d 2475 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2476 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2477 if (!ignore_msrs) {
ae0f5499 2478 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2479 msr, data);
ed85c068
AP		 2480 return 1;
2481 } else {
fab0aa3b
EM		 2482 if (report_ignored_msrs)
2483 vcpu_unimpl(vcpu,
2484 "ignored wrmsr: 0x%x data 0x%llx\n",
2485 msr, data);
ed85c068
AP		 2486 break;
2487 }
15c4a640
CO		 2488 }
2489 return 0;
2490}
2491EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2492
2493
2494/*
2495 * Reads an msr value (of 'msr_index') into 'pdata'.
2496 * Returns 0 on success, non-0 otherwise.
2497 * Assumes vcpu_load() was already called.
2498 */
609e36d3 2499int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2500{
609e36d3 2501 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2502}
ff651cb6 2503EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2504
890ca9ae 2505static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2506{
2507 u64 data;
890ca9ae
HY		 2508 u64 mcg_cap = vcpu->arch.mcg_cap;
2509 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2510
2511 switch (msr) {
15c4a640
CO		 2512 case MSR_IA32_P5_MC_ADDR:
2513 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2514 data = 0;
2515 break;
15c4a640 2516 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2517 data = vcpu->arch.mcg_cap;
2518 break;
c7ac679c 2519 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2520 if (!(mcg_cap & MCG_CTL_P))
2521 return 1;
2522 data = vcpu->arch.mcg_ctl;
2523 break;
2524 case MSR_IA32_MCG_STATUS:
2525 data = vcpu->arch.mcg_status;
2526 break;
2527 default:
2528 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2529 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2530 u32 offset = msr - MSR_IA32_MC0_CTL;
2531 data = vcpu->arch.mce_banks[offset];
2532 break;
2533 }
2534 return 1;
2535 }
2536 *pdata = data;
2537 return 0;
2538}
2539
609e36d3 2540int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2541{
609e36d3 2542 switch (msr_info->index) {
890ca9ae 2543 case MSR_IA32_PLATFORM_ID:
15c4a640 2544 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2545 case MSR_IA32_DEBUGCTLMSR:
2546 case MSR_IA32_LASTBRANCHFROMIP:
2547 case MSR_IA32_LASTBRANCHTOIP:
2548 case MSR_IA32_LASTINTFROMIP:
2549 case MSR_IA32_LASTINTTOIP:
60af2ecd 2550 case MSR_K8_SYSCFG:
3afb1121
PB		 2551 case MSR_K8_TSEG_ADDR:
2552 case MSR_K8_TSEG_MASK:
60af2ecd 2553 case MSR_K7_HWCR:
61a6bd67 2554 case MSR_VM_HSAVE_PA:
1fdbd48c 2555 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2556 case MSR_AMD64_NB_CFG:
f7c6d140 2557 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2558 case MSR_AMD64_BU_CFG2:
0c2df2a1 2559 case MSR_IA32_PERF_CTL:
405a353a 2560 case MSR_AMD64_DC_CFG:
609e36d3 2561 msr_info->data = 0;
15c4a640 2562 break;
6912ac32
WH		 2563 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2564 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2565 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2566 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2567 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2568 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2569 msr_info->data = 0;
5753785f 2570 break;
742bc670 2571 case MSR_IA32_UCODE_REV:
518e7b94 2572 msr_info->data = vcpu->arch.microcode_version;
742bc670 2573 break;
9ba075a6 2574 case MSR_MTRRcap:
9ba075a6 2575 case 0x200 ... 0x2ff:
ff53604b 2576 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2577 case 0xcd: /* fsb frequency */
609e36d3 2578 msr_info->data = 3;
15c4a640 2579 break;
7b914098
JS		 2580 /*
2581 * MSR_EBC_FREQUENCY_ID
2582 * Conservative value valid for even the basic CPU models.
2583 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2584 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2585 * and 266MHz for model 3, or 4. Set Core Clock
2586 * Frequency to System Bus Frequency Ratio to 1 (bits
2587 * 31:24) even though these are only valid for CPU
2588 * models > 2, however guests may end up dividing or
2589 * multiplying by zero otherwise.
2590 */
2591 case MSR_EBC_FREQUENCY_ID:
609e36d3 2592 msr_info->data = 1 << 24;
7b914098 2593 break;
15c4a640 2594 case MSR_IA32_APICBASE:
609e36d3 2595 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2596 break;
0105d1a5 2597 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2598 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2599 break;
a3e06bbe 2600 case MSR_IA32_TSCDEADLINE:
609e36d3 2601 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2602 break;
ba904635 2603 case MSR_IA32_TSC_ADJUST:
609e36d3 2604 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2605 break;
15c4a640 2606 case MSR_IA32_MISC_ENABLE:
609e36d3 2607 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2608 break;
64d60670
PB		 2609 case MSR_IA32_SMBASE:
2610 if (!msr_info->host_initiated)
2611 return 1;
2612 msr_info->data = vcpu->arch.smbase;
15c4a640 2613 break;
52797bf9
LA		 2614 case MSR_SMI_COUNT:
2615 msr_info->data = vcpu->arch.smi_count;
2616 break;
847f0ad8
AG		 2617 case MSR_IA32_PERF_STATUS:
2618 /* TSC increment by tick */
609e36d3 2619 msr_info->data = 1000ULL;
847f0ad8 2620 /* CPU multiplier */
b0996ae4 2621 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2622 break;
15c4a640 2623 case MSR_EFER:
609e36d3 2624 msr_info->data = vcpu->arch.efer;
15c4a640 2625 break;
18068523 2626 case MSR_KVM_WALL_CLOCK:
11c6bffa 2627 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2628 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2629 break;
2630 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2631 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2632 msr_info->data = vcpu->arch.time;
18068523 2633 break;
344d9588 2634 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2635 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2636 break;
c9aaa895 2637 case MSR_KVM_STEAL_TIME:
609e36d3 2638 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2639 break;
1d92128f 2640 case MSR_KVM_PV_EOI_EN:
609e36d3 2641 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2642 break;
890ca9ae
HY		 2643 case MSR_IA32_P5_MC_ADDR:
2644 case MSR_IA32_P5_MC_TYPE:
2645 case MSR_IA32_MCG_CAP:
2646 case MSR_IA32_MCG_CTL:
2647 case MSR_IA32_MCG_STATUS:
81760dcc 2648 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2649 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2650 case MSR_K7_CLK_CTL:
2651 /*
2652 * Provide expected ramp-up count for K7. All other
2653 * are set to zero, indicating minimum divisors for
2654 * every field.
2655 *
2656 * This prevents guest kernels on AMD host with CPU
2657 * type 6, model 8 and higher from exploding due to
2658 * the rdmsr failing.
2659 */
609e36d3 2660 msr_info->data = 0x20000000;
84e0cefa 2661 break;
55cd8e5a 2662 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2663 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2664 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2665 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2666 return kvm_hv_get_msr_common(vcpu,
2667 msr_info->index, &msr_info->data);
55cd8e5a 2668 break;
91c9c3ed 2669 case MSR_IA32_BBL_CR_CTL3:
2670 /* This legacy MSR exists but isn't fully documented in current
2671 * silicon. It is however accessed by winxp in very narrow
2672 * scenarios where it sets bit #19, itself documented as
2673 * a "reserved" bit. Best effort attempt to source coherent
2674 * read data here should the balance of the register be
2675 * interpreted by the guest:
2676 *
2677 * L2 cache control register 3: 64GB range, 256KB size,
2678 * enabled, latency 0x1, configured
2679 */
609e36d3 2680 msr_info->data = 0xbe702111;
91c9c3ed 2681 break;
2b036c6b 2682 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2683 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2684 return 1;
609e36d3 2685 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2686 break;
2687 case MSR_AMD64_OSVW_STATUS:
d6321d49 2688 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2689 return 1;
609e36d3 2690 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2691 break;
db2336a8
KH		 2692 case MSR_PLATFORM_INFO:
2693 msr_info->data = vcpu->arch.msr_platform_info;
2694 break;
2695 case MSR_MISC_FEATURES_ENABLES:
2696 msr_info->data = vcpu->arch.msr_misc_features_enables;
2697 break;
15c4a640 2698 default:
c6702c9d 2699 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2700 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2701 if (!ignore_msrs) {
ae0f5499
BD		 2702 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2703 msr_info->index);
ed85c068
AP		 2704 return 1;
2705 } else {
fab0aa3b
EM		 2706 if (report_ignored_msrs)
2707 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2708 msr_info->index);
609e36d3 2709 msr_info->data = 0;
ed85c068
AP		 2710 }
2711 break;
15c4a640 2712 }
15c4a640
CO		 2713 return 0;
2714}
2715EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2716
313a3dc7
CO		 2717/*
2718 * Read or write a bunch of msrs. All parameters are kernel addresses.
2719 *
2720 * @return number of msrs set successfully.
2721 */
2722static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2723 struct kvm_msr_entry *entries,
2724 int (*do_msr)(struct kvm_vcpu *vcpu,
2725 unsigned index, u64 *data))
2726{
801e459a 2727 int i;
313a3dc7 2728
313a3dc7
CO		 2729 for (i = 0; i < msrs->nmsrs; ++i)
2730 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2731 break;
2732
313a3dc7
CO		 2733 return i;
2734}
2735
2736/*
2737 * Read or write a bunch of msrs. Parameters are user addresses.
2738 *
2739 * @return number of msrs set successfully.
2740 */
2741static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2742 int (*do_msr)(struct kvm_vcpu *vcpu,
2743 unsigned index, u64 *data),
2744 int writeback)
2745{
2746 struct kvm_msrs msrs;
2747 struct kvm_msr_entry *entries;
2748 int r, n;
2749 unsigned size;
2750
2751 r = -EFAULT;
2752 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2753 goto out;
2754
2755 r = -E2BIG;
2756 if (msrs.nmsrs >= MAX_IO_MSRS)
2757 goto out;
2758
313a3dc7 2759 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2760 entries = memdup_user(user_msrs->entries, size);
2761 if (IS_ERR(entries)) {
2762 r = PTR_ERR(entries);
313a3dc7 2763 goto out;
ff5c2c03 2764 }
313a3dc7
CO		 2765
2766 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2767 if (r < 0)
2768 goto out_free;
2769
2770 r = -EFAULT;
2771 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2772 goto out_free;
2773
2774 r = n;
2775
2776out_free:
7a73c028 2777 kfree(entries);
313a3dc7
CO		 2778out:
2779 return r;
2780}
2781
784aa3d7 2782int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2783{
2784 int r;
2785
2786 switch (ext) {
2787 case KVM_CAP_IRQCHIP:
2788 case KVM_CAP_HLT:
2789 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2790 case KVM_CAP_SET_TSS_ADDR:
07716717 2791 case KVM_CAP_EXT_CPUID:
9c15bb1d 2792 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2793 case KVM_CAP_CLOCKSOURCE:
7837699f 2794 case KVM_CAP_PIT:
a28e4f5a 2795 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2796 case KVM_CAP_MP_STATE:
ed848624 2797 case KVM_CAP_SYNC_MMU:
a355c85c 2798 case KVM_CAP_USER_NMI:
52d939a0 2799 case KVM_CAP_REINJECT_CONTROL:
4925663a 2800 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2801 case KVM_CAP_IOEVENTFD:
f848a5a8 2802 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2803 case KVM_CAP_PIT2:
e9f42757 2804 case KVM_CAP_PIT_STATE2:
b927a3ce 2805 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2806 case KVM_CAP_XEN_HVM:
3cfc3092 2807 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2808 case KVM_CAP_HYPERV:
10388a07 2809 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2810 case KVM_CAP_HYPERV_SPIN:
5c919412 2811 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2812 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2813 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 2814 case KVM_CAP_HYPERV_EVENTFD:
ab9f4ecb 2815 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2816 case KVM_CAP_DEBUGREGS:
d2be1651 2817 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2818 case KVM_CAP_XSAVE:
344d9588 2819 case KVM_CAP_ASYNC_PF:
92a1f12d 2820 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2821 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2822 case KVM_CAP_READONLY_MEM:
5f66b620 2823 case KVM_CAP_HYPERV_TIME:
100943c5 2824 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2825 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2826 case KVM_CAP_ENABLE_CAP_VM:
2827 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2828 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2829 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2830 case KVM_CAP_IMMEDIATE_EXIT:
801e459a 2831 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX		 2832 r = 1;
2833 break;
01643c51
KH		 2834 case KVM_CAP_SYNC_REGS:
2835 r = KVM_SYNC_X86_VALID_FIELDS;
2836 break;
e3fd9a93
PB		 2837 case KVM_CAP_ADJUST_CLOCK:
2838 r = KVM_CLOCK_TSC_STABLE;
2839 break;
668fffa3
MT		 2840 case KVM_CAP_X86_GUEST_MWAIT:
2841 r = kvm_mwait_in_guest();
2842 break;
6d396b55
PB		 2843 case KVM_CAP_X86_SMM:
2844 /* SMBASE is usually relocated above 1M on modern chipsets,
2845 * and SMM handlers might indeed rely on 4G segment limits,
2846 * so do not report SMM to be available if real mode is
2847 * emulated via vm86 mode. Still, do not go to great lengths
2848 * to avoid userspace's usage of the feature, because it is a
2849 * fringe case that is not enabled except via specific settings
2850 * of the module parameters.
2851 */
2852 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2853 break;
774ead3a
AK		 2854 case KVM_CAP_VAPIC:
2855 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2856 break;
f725230a 2857 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2858 r = KVM_SOFT_MAX_VCPUS;
2859 break;
2860 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2861 r = KVM_MAX_VCPUS;
2862 break;
a988b910 2863 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2864 r = KVM_USER_MEM_SLOTS;
a988b910 2865 break;
a68a6a72
MT		 2866 case KVM_CAP_PV_MMU: /* obsolete */
2867 r = 0;
2f333bcb 2868 break;
890ca9ae
HY		 2869 case KVM_CAP_MCE:
2870 r = KVM_MAX_MCE_BANKS;
2871 break;
2d5b5a66 2872 case KVM_CAP_XCRS:
d366bf7e 2873 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2874 break;
92a1f12d
JR		 2875 case KVM_CAP_TSC_CONTROL:
2876 r = kvm_has_tsc_control;
2877 break;
37131313
RK		 2878 case KVM_CAP_X2APIC_API:
2879 r = KVM_X2APIC_API_VALID_FLAGS;
2880 break;
018d00d2
ZX		 2881 default:
2882 r = 0;
2883 break;
2884 }
2885 return r;
2886
2887}
2888
043405e1
CO		 2889long kvm_arch_dev_ioctl(struct file *filp,
2890 unsigned int ioctl, unsigned long arg)
2891{
2892 void __user *argp = (void __user *)arg;
2893 long r;
2894
2895 switch (ioctl) {
2896 case KVM_GET_MSR_INDEX_LIST: {
2897 struct kvm_msr_list __user *user_msr_list = argp;
2898 struct kvm_msr_list msr_list;
2899 unsigned n;
2900
2901 r = -EFAULT;
2902 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2903 goto out;
2904 n = msr_list.nmsrs;
62ef68bb 2905 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2906 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2907 goto out;
2908 r = -E2BIG;
e125e7b6 2909 if (n < msr_list.nmsrs)
043405e1
CO		 2910 goto out;
2911 r = -EFAULT;
2912 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2913 num_msrs_to_save * sizeof(u32)))
2914 goto out;
e125e7b6 2915 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2916 &emulated_msrs,
62ef68bb 2917 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2918 goto out;
2919 r = 0;
2920 break;
2921 }
9c15bb1d
BP		 2922 case KVM_GET_SUPPORTED_CPUID:
2923 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2924 struct kvm_cpuid2 __user *cpuid_arg = argp;
2925 struct kvm_cpuid2 cpuid;
2926
2927 r = -EFAULT;
2928 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2929 goto out;
9c15bb1d
BP		 2930
2931 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2932 ioctl);
674eea0f
AK		 2933 if (r)
2934 goto out;
2935
2936 r = -EFAULT;
2937 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2938 goto out;
2939 r = 0;
2940 break;
2941 }
890ca9ae 2942 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2943 r = -EFAULT;
c45dcc71
AR		 2944 if (copy_to_user(argp, &kvm_mce_cap_supported,
2945 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2946 goto out;
2947 r = 0;
2948 break;
801e459a
TL		 2949 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
2950 struct kvm_msr_list __user *user_msr_list = argp;
2951 struct kvm_msr_list msr_list;
2952 unsigned int n;
2953
2954 r = -EFAULT;
2955 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
2956 goto out;
2957 n = msr_list.nmsrs;
2958 msr_list.nmsrs = num_msr_based_features;
2959 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
2960 goto out;
2961 r = -E2BIG;
2962 if (n < msr_list.nmsrs)
2963 goto out;
2964 r = -EFAULT;
2965 if (copy_to_user(user_msr_list->indices, &msr_based_features,
2966 num_msr_based_features * sizeof(u32)))
2967 goto out;
2968 r = 0;
2969 break;
2970 }
2971 case KVM_GET_MSRS:
2972 r = msr_io(NULL, argp, do_get_msr_feature, 1);
2973 break;
890ca9ae 2974 }
043405e1
CO		 2975 default:
2976 r = -EINVAL;
2977 }
2978out:
2979 return r;
2980}
2981
f5f48ee1
SY		 2982static void wbinvd_ipi(void *garbage)
2983{
2984 wbinvd();
2985}
2986
2987static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2988{
e0f0bbc5 2989 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2990}
2991
313a3dc7
CO		 2992void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2993{
f5f48ee1
SY		 2994 /* Address WBINVD may be executed by guest */
2995 if (need_emulate_wbinvd(vcpu)) {
2996 if (kvm_x86_ops->has_wbinvd_exit())
2997 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2998 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2999 smp_call_function_single(vcpu->cpu,
3000 wbinvd_ipi, NULL, 1);
3001 }
3002
313a3dc7 3003 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3004
0dd6a6ed
ZA		 3005 /* Apply any externally detected TSC adjustments (due to suspend) */
3006 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3007 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3008 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3009 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3010 }
8f6055cb 3011
b0c39dc6 3012 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3013 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3014 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3015 if (tsc_delta < 0)
3016 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3017
b0c39dc6 3018 if (kvm_check_tsc_unstable()) {
07c1419a 3019 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3020 vcpu->arch.last_guest_tsc);
a545ab6a 3021 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3022 vcpu->arch.tsc_catchup = 1;
c285545f 3023 }
a749e247
PB		 3024
3025 if (kvm_lapic_hv_timer_in_use(vcpu))
3026 kvm_lapic_restart_hv_timer(vcpu);
3027
d98d07ca
MT		 3028 /*
3029 * On a host with synchronized TSC, there is no need to update
3030 * kvmclock on vcpu->cpu migration
3031 */
3032 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3033 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3034 if (vcpu->cpu != cpu)
1bd2009e 3035 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3036 vcpu->cpu = cpu;
6b7d7e76 3037 }
c9aaa895 3038
c9aaa895 3039 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3040}
3041
0b9f6c46
PX		 3042static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3043{
3044 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3045 return;
3046
fa55eedd 3047 vcpu->arch.st.steal.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3048
4e335d9e 3049 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX		 3050 &vcpu->arch.st.steal.preempted,
3051 offsetof(struct kvm_steal_time, preempted),
3052 sizeof(vcpu->arch.st.steal.preempted));
3053}
3054
313a3dc7
CO		 3055void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3056{
cc0d907c 3057 int idx;
de63ad4c
LM		 3058
3059 if (vcpu->preempted)
3060 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3061
931f261b
AA		 3062 /*
3063 * Disable page faults because we're in atomic context here.
3064 * kvm_write_guest_offset_cached() would call might_fault()
3065 * that relies on pagefault_disable() to tell if there's a
3066 * bug. NOTE: the write to guest memory may not go through if
3067 * during postcopy live migration or if there's heavy guest
3068 * paging.
3069 */
3070 pagefault_disable();
cc0d907c
AA		 3071 /*
3072 * kvm_memslots() will be called by
3073 * kvm_write_guest_offset_cached() so take the srcu lock.
3074 */
3075 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3076 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3077 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3078 pagefault_enable();
02daab21 3079 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3080 vcpu->arch.last_host_tsc = rdtsc();
efdab992
WL		 3081 /*
3082 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3083 * on every vmexit, but if not, we might have a stale dr6 from the
3084 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3085 */
3086 set_debugreg(0, 6);
313a3dc7
CO		 3087}
3088
313a3dc7
CO		 3089static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3090 struct kvm_lapic_state *s)
3091{
fa59cc00 3092 if (vcpu->arch.apicv_active)
d62caabb
AS		 3093 kvm_x86_ops->sync_pir_to_irr(vcpu);
3094
a92e2543 3095 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3096}
3097
3098static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3099 struct kvm_lapic_state *s)
3100{
a92e2543
RK		 3101 int r;
3102
3103 r = kvm_apic_set_state(vcpu, s);
3104 if (r)
3105 return r;
cb142eb7 3106 update_cr8_intercept(vcpu);
313a3dc7
CO		 3107
3108 return 0;
3109}
3110
127a457a
MG		 3111static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3112{
3113 return (!lapic_in_kernel(vcpu) ||
3114 kvm_apic_accept_pic_intr(vcpu));
3115}
3116
782d422b
MG		 3117/*
3118 * if userspace requested an interrupt window, check that the
3119 * interrupt window is open.
3120 *
3121 * No need to exit to userspace if we already have an interrupt queued.
3122 */
3123static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3124{
3125 return kvm_arch_interrupt_allowed(vcpu) &&
3126 !kvm_cpu_has_interrupt(vcpu) &&
3127 !kvm_event_needs_reinjection(vcpu) &&
3128 kvm_cpu_accept_dm_intr(vcpu);
3129}
3130
f77bc6a4
ZX		 3131static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3132 struct kvm_interrupt *irq)
3133{
02cdb50f 3134 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3135 return -EINVAL;
1c1a9ce9
SR		 3136
3137 if (!irqchip_in_kernel(vcpu->kvm)) {
3138 kvm_queue_interrupt(vcpu, irq->irq, false);
3139 kvm_make_request(KVM_REQ_EVENT, vcpu);
3140 return 0;
3141 }
3142
3143 /*
3144 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3145 * fail for in-kernel 8259.
3146 */
3147 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3148 return -ENXIO;
f77bc6a4 3149
1c1a9ce9
SR		 3150 if (vcpu->arch.pending_external_vector != -1)
3151 return -EEXIST;
f77bc6a4 3152
1c1a9ce9 3153 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3154 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3155 return 0;
3156}
3157
c4abb7c9
JK		 3158static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3159{
c4abb7c9 3160 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3161
3162 return 0;
3163}
3164
f077825a
PB		 3165static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3166{
64d60670
PB		 3167 kvm_make_request(KVM_REQ_SMI, vcpu);
3168
f077825a
PB		 3169 return 0;
3170}
3171
b209749f
AK		 3172static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3173 struct kvm_tpr_access_ctl *tac)
3174{
3175 if (tac->flags)
3176 return -EINVAL;
3177 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3178 return 0;
3179}
3180
890ca9ae
HY		 3181static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3182 u64 mcg_cap)
3183{
3184 int r;
3185 unsigned bank_num = mcg_cap & 0xff, bank;
3186
3187 r = -EINVAL;
a9e38c3e 3188 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3189 goto out;
c45dcc71 3190 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3191 goto out;
3192 r = 0;
3193 vcpu->arch.mcg_cap = mcg_cap;
3194 /* Init IA32_MCG_CTL to all 1s */
3195 if (mcg_cap & MCG_CTL_P)
3196 vcpu->arch.mcg_ctl = ~(u64)0;
3197 /* Init IA32_MCi_CTL to all 1s */
3198 for (bank = 0; bank < bank_num; bank++)
3199 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 3200
3201 if (kvm_x86_ops->setup_mce)
3202 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3203out:
3204 return r;
3205}
3206
3207static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3208 struct kvm_x86_mce *mce)
3209{
3210 u64 mcg_cap = vcpu->arch.mcg_cap;
3211 unsigned bank_num = mcg_cap & 0xff;
3212 u64 *banks = vcpu->arch.mce_banks;
3213
3214 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3215 return -EINVAL;
3216 /*
3217 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3218 * reporting is disabled
3219 */
3220 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3221 vcpu->arch.mcg_ctl != ~(u64)0)
3222 return 0;
3223 banks += 4 * mce->bank;
3224 /*
3225 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3226 * reporting is disabled for the bank
3227 */
3228 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3229 return 0;
3230 if (mce->status & MCI_STATUS_UC) {
3231 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3232 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3233 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3234 return 0;
3235 }
3236 if (banks[1] & MCI_STATUS_VAL)
3237 mce->status |= MCI_STATUS_OVER;
3238 banks[2] = mce->addr;
3239 banks[3] = mce->misc;
3240 vcpu->arch.mcg_status = mce->mcg_status;
3241 banks[1] = mce->status;
3242 kvm_queue_exception(vcpu, MC_VECTOR);
3243 } else if (!(banks[1] & MCI_STATUS_VAL)
3244 || !(banks[1] & MCI_STATUS_UC)) {
3245 if (banks[1] & MCI_STATUS_VAL)
3246 mce->status |= MCI_STATUS_OVER;
3247 banks[2] = mce->addr;
3248 banks[3] = mce->misc;
3249 banks[1] = mce->status;
3250 } else
3251 banks[1] |= MCI_STATUS_OVER;
3252 return 0;
3253}
3254
3cfc3092
JK		 3255static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3256 struct kvm_vcpu_events *events)
3257{
7460fb4a 3258 process_nmi(vcpu);
664f8e26
WL		 3259 /*
3260 * FIXME: pass injected and pending separately. This is only
3261 * needed for nested virtualization, whose state cannot be
3262 * migrated yet. For now we can combine them.
3263 */
03b82a30 3264 events->exception.injected =
664f8e26
WL		 3265 (vcpu->arch.exception.pending ||
3266 vcpu->arch.exception.injected) &&
03b82a30 3267 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3268 events->exception.nr = vcpu->arch.exception.nr;
3269 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3270 events->exception.pad = 0;
3cfc3092
JK		 3271 events->exception.error_code = vcpu->arch.exception.error_code;
3272
03b82a30
JK		 3273 events->interrupt.injected =
3274 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3275 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3276 events->interrupt.soft = 0;
37ccdcbe 3277 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3278
3279 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3280 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3281 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3282 events->nmi.pad = 0;
3cfc3092 3283
66450a21 3284 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3285
f077825a
PB		 3286 events->smi.smm = is_smm(vcpu);
3287 events->smi.pending = vcpu->arch.smi_pending;
3288 events->smi.smm_inside_nmi =
3289 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3290 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3291
dab4b911 3292 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3293 | KVM_VCPUEVENT_VALID_SHADOW
3294 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3295 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3296}
3297
6ef4e07e
XG		 3298static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3299
3cfc3092
JK		 3300static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3301 struct kvm_vcpu_events *events)
3302{
dab4b911 3303 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3304 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3305 | KVM_VCPUEVENT_VALID_SHADOW
3306 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3307 return -EINVAL;
3308
78e546c8 3309 if (events->exception.injected &&
28d06353
JM		 3310 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3311 is_guest_mode(vcpu)))
78e546c8
PB		 3312 return -EINVAL;
3313
28bf2888
DH		 3314 /* INITs are latched while in SMM */
3315 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3316 (events->smi.smm || events->smi.pending) &&
3317 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3318 return -EINVAL;
3319
7460fb4a 3320 process_nmi(vcpu);
664f8e26 3321 vcpu->arch.exception.injected = false;
3cfc3092
JK		 3322 vcpu->arch.exception.pending = events->exception.injected;
3323 vcpu->arch.exception.nr = events->exception.nr;
3324 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3325 vcpu->arch.exception.error_code = events->exception.error_code;
3326
3327 vcpu->arch.interrupt.pending = events->interrupt.injected;
3328 vcpu->arch.interrupt.nr = events->interrupt.nr;
3329 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3330 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3331 kvm_x86_ops->set_interrupt_shadow(vcpu,
3332 events->interrupt.shadow);
3cfc3092
JK		 3333
3334 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3335 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3336 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3337 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3338
66450a21 3339 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3340 lapic_in_kernel(vcpu))
66450a21 3341 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3342
f077825a 3343 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3344 u32 hflags = vcpu->arch.hflags;
f077825a 3345 if (events->smi.smm)
6ef4e07e 3346 hflags |= HF_SMM_MASK;
f077825a 3347 else
6ef4e07e
XG		 3348 hflags &= ~HF_SMM_MASK;
3349 kvm_set_hflags(vcpu, hflags);
3350
f077825a 3351 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3352
3353 if (events->smi.smm) {
3354 if (events->smi.smm_inside_nmi)
3355 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3356 else
f4ef1910
WL		 3357 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3358 if (lapic_in_kernel(vcpu)) {
3359 if (events->smi.latched_init)
3360 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3361 else
3362 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3363 }
f077825a
PB		 3364 }
3365 }
3366
3842d135
AK		 3367 kvm_make_request(KVM_REQ_EVENT, vcpu);
3368
3cfc3092
JK		 3369 return 0;
3370}
3371
a1efbe77
JK		 3372static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3373 struct kvm_debugregs *dbgregs)
3374{
73aaf249
JK		 3375 unsigned long val;
3376
a1efbe77 3377 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3378 kvm_get_dr(vcpu, 6, &val);
73aaf249 3379 dbgregs->dr6 = val;
a1efbe77
JK		 3380 dbgregs->dr7 = vcpu->arch.dr7;
3381 dbgregs->flags = 0;
97e69aa6 3382 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3383}
3384
3385static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3386 struct kvm_debugregs *dbgregs)
3387{
3388 if (dbgregs->flags)
3389 return -EINVAL;
3390
d14bdb55
PB		 3391 if (dbgregs->dr6 & ~0xffffffffull)
3392 return -EINVAL;
3393 if (dbgregs->dr7 & ~0xffffffffull)
3394 return -EINVAL;
3395
a1efbe77 3396 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3397 kvm_update_dr0123(vcpu);
a1efbe77 3398 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3399 kvm_update_dr6(vcpu);
a1efbe77 3400 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3401 kvm_update_dr7(vcpu);
a1efbe77 3402
a1efbe77
JK		 3403 return 0;
3404}
3405
df1daba7
PB		 3406#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3407
3408static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3409{
c47ada30 3410 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3411 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3412 u64 valid;
3413
3414 /*
3415 * Copy legacy XSAVE area, to avoid complications with CPUID
3416 * leaves 0 and 1 in the loop below.
3417 */
3418 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3419
3420 /* Set XSTATE_BV */
00c87e9a 3421 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3422 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3423
3424 /*
3425 * Copy each region from the possibly compacted offset to the
3426 * non-compacted offset.
3427 */
d91cab78 3428 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3429 while (valid) {
3430 u64 feature = valid & -valid;
3431 int index = fls64(feature) - 1;
3432 void *src = get_xsave_addr(xsave, feature);
3433
3434 if (src) {
3435 u32 size, offset, ecx, edx;
3436 cpuid_count(XSTATE_CPUID, index,
3437 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3438 if (feature == XFEATURE_MASK_PKRU)
3439 memcpy(dest + offset, &vcpu->arch.pkru,
3440 sizeof(vcpu->arch.pkru));
3441 else
3442 memcpy(dest + offset, src, size);
3443
df1daba7
PB		 3444 }
3445
3446 valid -= feature;
3447 }
3448}
3449
3450static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3451{
c47ada30 3452 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3453 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3454 u64 valid;
3455
3456 /*
3457 * Copy legacy XSAVE area, to avoid complications with CPUID
3458 * leaves 0 and 1 in the loop below.
3459 */
3460 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3461
3462 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3463 xsave->header.xfeatures = xstate_bv;
782511b0 3464 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3465 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3466
3467 /*
3468 * Copy each region from the non-compacted offset to the
3469 * possibly compacted offset.
3470 */
d91cab78 3471 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3472 while (valid) {
3473 u64 feature = valid & -valid;
3474 int index = fls64(feature) - 1;
3475 void *dest = get_xsave_addr(xsave, feature);
3476
3477 if (dest) {
3478 u32 size, offset, ecx, edx;
3479 cpuid_count(XSTATE_CPUID, index,
3480 &size, &offset, &ecx, &edx);
38cfd5e3
PB		 3481 if (feature == XFEATURE_MASK_PKRU)
3482 memcpy(&vcpu->arch.pkru, src + offset,
3483 sizeof(vcpu->arch.pkru));
3484 else
3485 memcpy(dest, src + offset, size);
ee4100da 3486 }
df1daba7
PB		 3487
3488 valid -= feature;
3489 }
3490}
3491
2d5b5a66
SY		 3492static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3493 struct kvm_xsave *guest_xsave)
3494{
d366bf7e 3495 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3496 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3497 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3498 } else {
2d5b5a66 3499 memcpy(guest_xsave->region,
7366ed77 3500 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3501 sizeof(struct fxregs_state));
2d5b5a66 3502 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3503 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3504 }
3505}
3506
a575813b
WL		 3507#define XSAVE_MXCSR_OFFSET 24
3508
2d5b5a66
SY		 3509static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3510 struct kvm_xsave *guest_xsave)
3511{
3512 u64 xstate_bv =
3513 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3514 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3515
d366bf7e 3516 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3517 /*
3518 * Here we allow setting states that are not present in
3519 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3520 * with old userspace.
3521 */
a575813b
WL		 3522 if (xstate_bv & ~kvm_supported_xcr0() ||
3523 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3524 return -EINVAL;
df1daba7 3525 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3526 } else {
a575813b
WL		 3527 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3528 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3529 return -EINVAL;
7366ed77 3530 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3531 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3532 }
3533 return 0;
3534}
3535
3536static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3537 struct kvm_xcrs *guest_xcrs)
3538{
d366bf7e 3539 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3540 guest_xcrs->nr_xcrs = 0;
3541 return;
3542 }
3543
3544 guest_xcrs->nr_xcrs = 1;
3545 guest_xcrs->flags = 0;
3546 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3547 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3548}
3549
3550static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3551 struct kvm_xcrs *guest_xcrs)
3552{
3553 int i, r = 0;
3554
d366bf7e 3555 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3556 return -EINVAL;
3557
3558 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3559 return -EINVAL;
3560
3561 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3562 /* Only support XCR0 currently */
c67a04cb 3563 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3564 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3565 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3566 break;
3567 }
3568 if (r)
3569 r = -EINVAL;
3570 return r;
3571}
3572
1c0b28c2
EM		 3573/*
3574 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3575 * stopped by the hypervisor. This function will be called from the host only.
3576 * EINVAL is returned when the host attempts to set the flag for a guest that
3577 * does not support pv clocks.
3578 */
3579static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3580{
0b79459b 3581 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3582 return -EINVAL;
51d59c6b 3583 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3584 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3585 return 0;
3586}
3587
5c919412
AS		 3588static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3589 struct kvm_enable_cap *cap)
3590{
3591 if (cap->flags)
3592 return -EINVAL;
3593
3594 switch (cap->cap) {
efc479e6
RK		 3595 case KVM_CAP_HYPERV_SYNIC2:
3596 if (cap->args[0])
3597 return -EINVAL;
5c919412 3598 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3599 if (!irqchip_in_kernel(vcpu->kvm))
3600 return -EINVAL;
efc479e6
RK		 3601 return kvm_hv_activate_synic(vcpu, cap->cap ==
3602 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS		 3603 default:
3604 return -EINVAL;
3605 }
3606}
3607
313a3dc7
CO		 3608long kvm_arch_vcpu_ioctl(struct file *filp,
3609 unsigned int ioctl, unsigned long arg)
3610{
3611 struct kvm_vcpu *vcpu = filp->private_data;
3612 void __user *argp = (void __user *)arg;
3613 int r;
d1ac91d8
AK		 3614 union {
3615 struct kvm_lapic_state *lapic;
3616 struct kvm_xsave *xsave;
3617 struct kvm_xcrs *xcrs;
3618 void *buffer;
3619 } u;
3620
9b062471
CD		 3621 vcpu_load(vcpu);
3622
d1ac91d8 3623 u.buffer = NULL;
313a3dc7
CO		 3624 switch (ioctl) {
3625 case KVM_GET_LAPIC: {
2204ae3c 3626 r = -EINVAL;
bce87cce 3627 if (!lapic_in_kernel(vcpu))
2204ae3c 3628 goto out;
d1ac91d8 3629 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3630
b772ff36 3631 r = -ENOMEM;
d1ac91d8 3632 if (!u.lapic)
b772ff36 3633 goto out;
d1ac91d8 3634 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3635 if (r)
3636 goto out;
3637 r = -EFAULT;
d1ac91d8 3638 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3639 goto out;
3640 r = 0;
3641 break;
3642 }
3643 case KVM_SET_LAPIC: {
2204ae3c 3644 r = -EINVAL;
bce87cce 3645 if (!lapic_in_kernel(vcpu))
2204ae3c 3646 goto out;
ff5c2c03 3647 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 3648 if (IS_ERR(u.lapic)) {
3649 r = PTR_ERR(u.lapic);
3650 goto out_nofree;
3651 }
ff5c2c03 3652
d1ac91d8 3653 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3654 break;
3655 }
f77bc6a4
ZX		 3656 case KVM_INTERRUPT: {
3657 struct kvm_interrupt irq;
3658
3659 r = -EFAULT;
3660 if (copy_from_user(&irq, argp, sizeof irq))
3661 goto out;
3662 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3663 break;
3664 }
c4abb7c9
JK		 3665 case KVM_NMI: {
3666 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3667 break;
3668 }
f077825a
PB		 3669 case KVM_SMI: {
3670 r = kvm_vcpu_ioctl_smi(vcpu);
3671 break;
3672 }
313a3dc7
CO		 3673 case KVM_SET_CPUID: {
3674 struct kvm_cpuid __user *cpuid_arg = argp;
3675 struct kvm_cpuid cpuid;
3676
3677 r = -EFAULT;
3678 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3679 goto out;
3680 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3681 break;
3682 }
07716717
DK		 3683 case KVM_SET_CPUID2: {
3684 struct kvm_cpuid2 __user *cpuid_arg = argp;
3685 struct kvm_cpuid2 cpuid;
3686
3687 r = -EFAULT;
3688 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3689 goto out;
3690 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3691 cpuid_arg->entries);
07716717
DK		 3692 break;
3693 }
3694 case KVM_GET_CPUID2: {
3695 struct kvm_cpuid2 __user *cpuid_arg = argp;
3696 struct kvm_cpuid2 cpuid;
3697
3698 r = -EFAULT;
3699 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3700 goto out;
3701 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3702 cpuid_arg->entries);
07716717
DK		 3703 if (r)
3704 goto out;
3705 r = -EFAULT;
3706 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3707 goto out;
3708 r = 0;
3709 break;
3710 }
801e459a
TL		 3711 case KVM_GET_MSRS: {
3712 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3713 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 3714 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3715 break;
801e459a
TL		 3716 }
3717 case KVM_SET_MSRS: {
3718 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3719 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 3720 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3721 break;
801e459a 3722 }
b209749f
AK		 3723 case KVM_TPR_ACCESS_REPORTING: {
3724 struct kvm_tpr_access_ctl tac;
3725
3726 r = -EFAULT;
3727 if (copy_from_user(&tac, argp, sizeof tac))
3728 goto out;
3729 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3730 if (r)
3731 goto out;
3732 r = -EFAULT;
3733 if (copy_to_user(argp, &tac, sizeof tac))
3734 goto out;
3735 r = 0;
3736 break;
3737 };
b93463aa
AK		 3738 case KVM_SET_VAPIC_ADDR: {
3739 struct kvm_vapic_addr va;
7301d6ab 3740 int idx;
b93463aa
AK		 3741
3742 r = -EINVAL;
35754c98 3743 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3744 goto out;
3745 r = -EFAULT;
3746 if (copy_from_user(&va, argp, sizeof va))
3747 goto out;
7301d6ab 3748 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3749 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3750 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3751 break;
3752 }
890ca9ae
HY		 3753 case KVM_X86_SETUP_MCE: {
3754 u64 mcg_cap;
3755
3756 r = -EFAULT;
3757 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3758 goto out;
3759 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3760 break;
3761 }
3762 case KVM_X86_SET_MCE: {
3763 struct kvm_x86_mce mce;
3764
3765 r = -EFAULT;
3766 if (copy_from_user(&mce, argp, sizeof mce))
3767 goto out;
3768 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3769 break;
3770 }
3cfc3092
JK		 3771 case KVM_GET_VCPU_EVENTS: {
3772 struct kvm_vcpu_events events;
3773
3774 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3775
3776 r = -EFAULT;
3777 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3778 break;
3779 r = 0;
3780 break;
3781 }
3782 case KVM_SET_VCPU_EVENTS: {
3783 struct kvm_vcpu_events events;
3784
3785 r = -EFAULT;
3786 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3787 break;
3788
3789 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3790 break;
3791 }
a1efbe77
JK		 3792 case KVM_GET_DEBUGREGS: {
3793 struct kvm_debugregs dbgregs;
3794
3795 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3796
3797 r = -EFAULT;
3798 if (copy_to_user(argp, &dbgregs,
3799 sizeof(struct kvm_debugregs)))
3800 break;
3801 r = 0;
3802 break;
3803 }
3804 case KVM_SET_DEBUGREGS: {
3805 struct kvm_debugregs dbgregs;
3806
3807 r = -EFAULT;
3808 if (copy_from_user(&dbgregs, argp,
3809 sizeof(struct kvm_debugregs)))
3810 break;
3811
3812 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3813 break;
3814 }
2d5b5a66 3815 case KVM_GET_XSAVE: {
d1ac91d8 3816 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3817 r = -ENOMEM;
d1ac91d8 3818 if (!u.xsave)
2d5b5a66
SY		 3819 break;
3820
d1ac91d8 3821 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3822
3823 r = -EFAULT;
d1ac91d8 3824 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3825 break;
3826 r = 0;
3827 break;
3828 }
3829 case KVM_SET_XSAVE: {
ff5c2c03 3830 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 3831 if (IS_ERR(u.xsave)) {
3832 r = PTR_ERR(u.xsave);
3833 goto out_nofree;
3834 }
2d5b5a66 3835
d1ac91d8 3836 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3837 break;
3838 }
3839 case KVM_GET_XCRS: {
d1ac91d8 3840 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3841 r = -ENOMEM;
d1ac91d8 3842 if (!u.xcrs)
2d5b5a66
SY		 3843 break;
3844
d1ac91d8 3845 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3846
3847 r = -EFAULT;
d1ac91d8 3848 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3849 sizeof(struct kvm_xcrs)))
3850 break;
3851 r = 0;
3852 break;
3853 }
3854 case KVM_SET_XCRS: {
ff5c2c03 3855 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 3856 if (IS_ERR(u.xcrs)) {
3857 r = PTR_ERR(u.xcrs);
3858 goto out_nofree;
3859 }
2d5b5a66 3860
d1ac91d8 3861 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3862 break;
3863 }
92a1f12d
JR		 3864 case KVM_SET_TSC_KHZ: {
3865 u32 user_tsc_khz;
3866
3867 r = -EINVAL;
92a1f12d
JR		 3868 user_tsc_khz = (u32)arg;
3869
3870 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3871 goto out;
3872
cc578287
ZA		 3873 if (user_tsc_khz == 0)
3874 user_tsc_khz = tsc_khz;
3875
381d585c
HZ		 3876 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3877 r = 0;
92a1f12d 3878
92a1f12d
JR		 3879 goto out;
3880 }
3881 case KVM_GET_TSC_KHZ: {
cc578287 3882 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3883 goto out;
3884 }
1c0b28c2
EM		 3885 case KVM_KVMCLOCK_CTRL: {
3886 r = kvm_set_guest_paused(vcpu);
3887 goto out;
3888 }
5c919412
AS		 3889 case KVM_ENABLE_CAP: {
3890 struct kvm_enable_cap cap;
3891
3892 r = -EFAULT;
3893 if (copy_from_user(&cap, argp, sizeof(cap)))
3894 goto out;
3895 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3896 break;
3897 }
313a3dc7
CO		 3898 default:
3899 r = -EINVAL;
3900 }
3901out:
d1ac91d8 3902 kfree(u.buffer);
9b062471
CD		 3903out_nofree:
3904 vcpu_put(vcpu);
313a3dc7
CO		 3905 return r;
3906}
3907
5b1c1493
CO		 3908int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3909{
3910 return VM_FAULT_SIGBUS;
3911}
3912
1fe779f8
CO		 3913static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3914{
3915 int ret;
3916
3917 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3918 return -EINVAL;
1fe779f8
CO		 3919 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3920 return ret;
3921}
3922
b927a3ce
SY		 3923static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3924 u64 ident_addr)
3925{
3926 kvm->arch.ept_identity_map_addr = ident_addr;
3927 return 0;
3928}
3929
1fe779f8
CO		 3930static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3931 u32 kvm_nr_mmu_pages)
3932{
3933 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3934 return -EINVAL;
3935
79fac95e 3936 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3937
3938 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3939 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3940
79fac95e 3941 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3942 return 0;
3943}
3944
3945static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3946{
39de71ec 3947 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3948}
3949
1fe779f8
CO		 3950static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3951{
90bca052 3952 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3953 int r;
3954
3955 r = 0;
3956 switch (chip->chip_id) {
3957 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3958 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3959 sizeof(struct kvm_pic_state));
3960 break;
3961 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3962 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3963 sizeof(struct kvm_pic_state));
3964 break;
3965 case KVM_IRQCHIP_IOAPIC:
33392b49 3966 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3967 break;
3968 default:
3969 r = -EINVAL;
3970 break;
3971 }
3972 return r;
3973}
3974
3975static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3976{
90bca052 3977 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3978 int r;
3979
3980 r = 0;
3981 switch (chip->chip_id) {
3982 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3983 spin_lock(&pic->lock);
3984 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3985 sizeof(struct kvm_pic_state));
90bca052 3986 spin_unlock(&pic->lock);
1fe779f8
CO		 3987 break;
3988 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3989 spin_lock(&pic->lock);
3990 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3991 sizeof(struct kvm_pic_state));
90bca052 3992 spin_unlock(&pic->lock);
1fe779f8
CO		 3993 break;
3994 case KVM_IRQCHIP_IOAPIC:
33392b49 3995 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3996 break;
3997 default:
3998 r = -EINVAL;
3999 break;
4000 }
90bca052 4001 kvm_pic_update_irq(pic);
1fe779f8
CO		 4002 return r;
4003}
4004
e0f63cb9
SY		 4005static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4006{
34f3941c
RK		 4007 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4008
4009 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4010
4011 mutex_lock(&kps->lock);
4012 memcpy(ps, &kps->channels, sizeof(*ps));
4013 mutex_unlock(&kps->lock);
2da29bcc 4014 return 0;
e0f63cb9
SY		 4015}
4016
4017static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4018{
0185604c 4019 int i;
09edea72
RK		 4020 struct kvm_pit *pit = kvm->arch.vpit;
4021
4022 mutex_lock(&pit->pit_state.lock);
34f3941c 4023 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4024 for (i = 0; i < 3; i++)
09edea72
RK		 4025 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4026 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4027 return 0;
e9f42757
BK		 4028}
4029
4030static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4031{
e9f42757
BK		 4032 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4033 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4034 sizeof(ps->channels));
4035 ps->flags = kvm->arch.vpit->pit_state.flags;
4036 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4037 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4038 return 0;
e9f42757
BK		 4039}
4040
4041static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4042{
2da29bcc 4043 int start = 0;
0185604c 4044 int i;
e9f42757 4045 u32 prev_legacy, cur_legacy;
09edea72
RK		 4046 struct kvm_pit *pit = kvm->arch.vpit;
4047
4048 mutex_lock(&pit->pit_state.lock);
4049 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4050 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4051 if (!prev_legacy && cur_legacy)
4052 start = 1;
09edea72
RK		 4053 memcpy(&pit->pit_state.channels, &ps->channels,
4054 sizeof(pit->pit_state.channels));
4055 pit->pit_state.flags = ps->flags;
0185604c 4056 for (i = 0; i < 3; i++)
09edea72 4057 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4058 start && i == 0);
09edea72 4059 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4060 return 0;
e0f63cb9
SY		 4061}
4062
52d939a0
MT		 4063static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4064 struct kvm_reinject_control *control)
4065{
71474e2f
RK		 4066 struct kvm_pit *pit = kvm->arch.vpit;
4067
4068 if (!pit)
52d939a0 4069 return -ENXIO;
b39c90b6 4070
71474e2f
RK		 4071 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4072 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4073 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4074 */
4075 mutex_lock(&pit->pit_state.lock);
4076 kvm_pit_set_reinject(pit, control->pit_reinject);
4077 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4078
52d939a0
MT		 4079 return 0;
4080}
4081
95d4c16c 4082/**
60c34612
TY		 4083 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4084 * @kvm: kvm instance
4085 * @log: slot id and address to which we copy the log
95d4c16c 4086 *
e108ff2f
PB		 4087 * Steps 1-4 below provide general overview of dirty page logging. See
4088 * kvm_get_dirty_log_protect() function description for additional details.
4089 *
4090 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4091 * always flush the TLB (step 4) even if previous step failed and the dirty
4092 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4093 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4094 * writes will be marked dirty for next log read.
95d4c16c 4095 *
60c34612
TY		 4096 * 1. Take a snapshot of the bit and clear it if needed.
4097 * 2. Write protect the corresponding page.
e108ff2f
PB		 4098 * 3. Copy the snapshot to the userspace.
4099 * 4. Flush TLB's if needed.
5bb064dc 4100 */
60c34612 4101int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4102{
60c34612 4103 bool is_dirty = false;
e108ff2f 4104 int r;
5bb064dc 4105
79fac95e 4106 mutex_lock(&kvm->slots_lock);
5bb064dc 4107
88178fd4
KH		 4108 /*
4109 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4110 */
4111 if (kvm_x86_ops->flush_log_dirty)
4112 kvm_x86_ops->flush_log_dirty(kvm);
4113
e108ff2f 4114 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 4115
4116 /*
4117 * All the TLBs can be flushed out of mmu lock, see the comments in
4118 * kvm_mmu_slot_remove_write_access().
4119 */
e108ff2f 4120 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 4121 if (is_dirty)
4122 kvm_flush_remote_tlbs(kvm);
4123
79fac95e 4124 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4125 return r;
4126}
4127
aa2fbe6d
YZ		 4128int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4129 bool line_status)
23d43cf9
CD		 4130{
4131 if (!irqchip_in_kernel(kvm))
4132 return -ENXIO;
4133
4134 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4135 irq_event->irq, irq_event->level,
4136 line_status);
23d43cf9
CD		 4137 return 0;
4138}
4139
90de4a18
NA		 4140static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4141 struct kvm_enable_cap *cap)
4142{
4143 int r;
4144
4145 if (cap->flags)
4146 return -EINVAL;
4147
4148 switch (cap->cap) {
4149 case KVM_CAP_DISABLE_QUIRKS:
4150 kvm->arch.disabled_quirks = cap->args[0];
4151 r = 0;
4152 break;
49df6397
SR		 4153 case KVM_CAP_SPLIT_IRQCHIP: {
4154 mutex_lock(&kvm->lock);
b053b2ae
SR		 4155 r = -EINVAL;
4156 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4157 goto split_irqchip_unlock;
49df6397
SR		 4158 r = -EEXIST;
4159 if (irqchip_in_kernel(kvm))
4160 goto split_irqchip_unlock;
557abc40 4161 if (kvm->created_vcpus)
49df6397
SR		 4162 goto split_irqchip_unlock;
4163 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4164 if (r)
49df6397
SR		 4165 goto split_irqchip_unlock;
4166 /* Pairs with irqchip_in_kernel. */
4167 smp_wmb();
49776faf 4168 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4169 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4170 r = 0;
4171split_irqchip_unlock:
4172 mutex_unlock(&kvm->lock);
4173 break;
4174 }
37131313
RK		 4175 case KVM_CAP_X2APIC_API:
4176 r = -EINVAL;
4177 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4178 break;
4179
4180 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4181 kvm->arch.x2apic_format = true;
c519265f
RK		 4182 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4183 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4184
4185 r = 0;
4186 break;
90de4a18
NA		 4187 default:
4188 r = -EINVAL;
4189 break;
4190 }
4191 return r;
4192}
4193
1fe779f8
CO		 4194long kvm_arch_vm_ioctl(struct file *filp,
4195 unsigned int ioctl, unsigned long arg)
4196{
4197 struct kvm *kvm = filp->private_data;
4198 void __user *argp = (void __user *)arg;
367e1319 4199 int r = -ENOTTY;
f0d66275
DH		 4200 /*
4201 * This union makes it completely explicit to gcc-3.x
4202 * that these two variables' stack usage should be
4203 * combined, not added together.
4204 */
4205 union {
4206 struct kvm_pit_state ps;
e9f42757 4207 struct kvm_pit_state2 ps2;
c5ff41ce 4208 struct kvm_pit_config pit_config;
f0d66275 4209 } u;
1fe779f8
CO		 4210
4211 switch (ioctl) {
4212 case KVM_SET_TSS_ADDR:
4213 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4214 break;
b927a3ce
SY		 4215 case KVM_SET_IDENTITY_MAP_ADDR: {
4216 u64 ident_addr;
4217
1af1ac91
DH		 4218 mutex_lock(&kvm->lock);
4219 r = -EINVAL;
4220 if (kvm->created_vcpus)
4221 goto set_identity_unlock;
b927a3ce
SY		 4222 r = -EFAULT;
4223 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4224 goto set_identity_unlock;
b927a3ce 4225 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4226set_identity_unlock:
4227 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4228 break;
4229 }
1fe779f8
CO		 4230 case KVM_SET_NR_MMU_PAGES:
4231 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4232 break;
4233 case KVM_GET_NR_MMU_PAGES:
4234 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4235 break;
3ddea128 4236 case KVM_CREATE_IRQCHIP: {
3ddea128 4237 mutex_lock(&kvm->lock);
09941366 4238
3ddea128 4239 r = -EEXIST;
35e6eaa3 4240 if (irqchip_in_kernel(kvm))
3ddea128 4241 goto create_irqchip_unlock;
09941366 4242
3e515705 4243 r = -EINVAL;
557abc40 4244 if (kvm->created_vcpus)
3e515705 4245 goto create_irqchip_unlock;
09941366
RK		 4246
4247 r = kvm_pic_init(kvm);
4248 if (r)
3ddea128 4249 goto create_irqchip_unlock;
09941366
RK		 4250
4251 r = kvm_ioapic_init(kvm);
4252 if (r) {
09941366 4253 kvm_pic_destroy(kvm);
3ddea128 4254 goto create_irqchip_unlock;
09941366
RK		 4255 }
4256
399ec807
AK		 4257 r = kvm_setup_default_irq_routing(kvm);
4258 if (r) {
72bb2fcd 4259 kvm_ioapic_destroy(kvm);
09941366 4260 kvm_pic_destroy(kvm);
71ba994c 4261 goto create_irqchip_unlock;
399ec807 4262 }
49776faf 4263 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4264 smp_wmb();
49776faf 4265 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4266 create_irqchip_unlock:
4267 mutex_unlock(&kvm->lock);
1fe779f8 4268 break;
3ddea128 4269 }
7837699f 4270 case KVM_CREATE_PIT:
c5ff41ce
JK		 4271 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4272 goto create_pit;
4273 case KVM_CREATE_PIT2:
4274 r = -EFAULT;
4275 if (copy_from_user(&u.pit_config, argp,
4276 sizeof(struct kvm_pit_config)))
4277 goto out;
4278 create_pit:
250715a6 4279 mutex_lock(&kvm->lock);
269e05e4
AK		 4280 r = -EEXIST;
4281 if (kvm->arch.vpit)
4282 goto create_pit_unlock;
7837699f 4283 r = -ENOMEM;
c5ff41ce 4284 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4285 if (kvm->arch.vpit)
4286 r = 0;
269e05e4 4287 create_pit_unlock:
250715a6 4288 mutex_unlock(&kvm->lock);
7837699f 4289 break;
1fe779f8
CO		 4290 case KVM_GET_IRQCHIP: {
4291 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4292 struct kvm_irqchip *chip;
1fe779f8 4293
ff5c2c03
SL		 4294 chip = memdup_user(argp, sizeof(*chip));
4295 if (IS_ERR(chip)) {
4296 r = PTR_ERR(chip);
1fe779f8 4297 goto out;
ff5c2c03
SL		 4298 }
4299
1fe779f8 4300 r = -ENXIO;
826da321 4301 if (!irqchip_kernel(kvm))
f0d66275
DH		 4302 goto get_irqchip_out;
4303 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4304 if (r)
f0d66275 4305 goto get_irqchip_out;
1fe779f8 4306 r = -EFAULT;
f0d66275
DH		 4307 if (copy_to_user(argp, chip, sizeof *chip))
4308 goto get_irqchip_out;
1fe779f8 4309 r = 0;
f0d66275
DH		 4310 get_irqchip_out:
4311 kfree(chip);
1fe779f8
CO		 4312 break;
4313 }
4314 case KVM_SET_IRQCHIP: {
4315 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4316 struct kvm_irqchip *chip;
1fe779f8 4317
ff5c2c03
SL		 4318 chip = memdup_user(argp, sizeof(*chip));
4319 if (IS_ERR(chip)) {
4320 r = PTR_ERR(chip);
1fe779f8 4321 goto out;
ff5c2c03
SL		 4322 }
4323
1fe779f8 4324 r = -ENXIO;
826da321 4325 if (!irqchip_kernel(kvm))
f0d66275
DH		 4326 goto set_irqchip_out;
4327 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4328 if (r)
f0d66275 4329 goto set_irqchip_out;
1fe779f8 4330 r = 0;
f0d66275
DH		 4331 set_irqchip_out:
4332 kfree(chip);
1fe779f8
CO		 4333 break;
4334 }
e0f63cb9 4335 case KVM_GET_PIT: {
e0f63cb9 4336 r = -EFAULT;
f0d66275 4337 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4338 goto out;
4339 r = -ENXIO;
4340 if (!kvm->arch.vpit)
4341 goto out;
f0d66275 4342 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4343 if (r)
4344 goto out;
4345 r = -EFAULT;
f0d66275 4346 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4347 goto out;
4348 r = 0;
4349 break;
4350 }
4351 case KVM_SET_PIT: {
e0f63cb9 4352 r = -EFAULT;
f0d66275 4353 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4354 goto out;
4355 r = -ENXIO;
4356 if (!kvm->arch.vpit)
4357 goto out;
f0d66275 4358 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4359 break;
4360 }
e9f42757
BK		 4361 case KVM_GET_PIT2: {
4362 r = -ENXIO;
4363 if (!kvm->arch.vpit)
4364 goto out;
4365 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4366 if (r)
4367 goto out;
4368 r = -EFAULT;
4369 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4370 goto out;
4371 r = 0;
4372 break;
4373 }
4374 case KVM_SET_PIT2: {
4375 r = -EFAULT;
4376 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4377 goto out;
4378 r = -ENXIO;
4379 if (!kvm->arch.vpit)
4380 goto out;
4381 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4382 break;
4383 }
52d939a0
MT		 4384 case KVM_REINJECT_CONTROL: {
4385 struct kvm_reinject_control control;
4386 r = -EFAULT;
4387 if (copy_from_user(&control, argp, sizeof(control)))
4388 goto out;
4389 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4390 break;
4391 }
d71ba788
PB		 4392 case KVM_SET_BOOT_CPU_ID:
4393 r = 0;
4394 mutex_lock(&kvm->lock);
557abc40 4395 if (kvm->created_vcpus)
d71ba788
PB		 4396 r = -EBUSY;
4397 else
4398 kvm->arch.bsp_vcpu_id = arg;
4399 mutex_unlock(&kvm->lock);
4400 break;
ffde22ac 4401 case KVM_XEN_HVM_CONFIG: {
51776043 4402 struct kvm_xen_hvm_config xhc;
ffde22ac 4403 r = -EFAULT;
51776043 4404 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 4405 goto out;
4406 r = -EINVAL;
51776043 4407 if (xhc.flags)
ffde22ac 4408 goto out;
51776043 4409 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 4410 r = 0;
4411 break;
4412 }
afbcf7ab 4413 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4414 struct kvm_clock_data user_ns;
4415 u64 now_ns;
afbcf7ab
GC		 4416
4417 r = -EFAULT;
4418 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4419 goto out;
4420
4421 r = -EINVAL;
4422 if (user_ns.flags)
4423 goto out;
4424
4425 r = 0;
0bc48bea
RK		 4426 /*
4427 * TODO: userspace has to take care of races with VCPU_RUN, so
4428 * kvm_gen_update_masterclock() can be cut down to locked
4429 * pvclock_update_vm_gtod_copy().
4430 */
4431 kvm_gen_update_masterclock(kvm);
e891a32e 4432 now_ns = get_kvmclock_ns(kvm);
108b249c 4433 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4434 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 4435 break;
4436 }
4437 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4438 struct kvm_clock_data user_ns;
4439 u64 now_ns;
4440
e891a32e 4441 now_ns = get_kvmclock_ns(kvm);
108b249c 4442 user_ns.clock = now_ns;
e3fd9a93 4443 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4444 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4445
4446 r = -EFAULT;
4447 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4448 goto out;
4449 r = 0;
4450 break;
4451 }
90de4a18
NA		 4452 case KVM_ENABLE_CAP: {
4453 struct kvm_enable_cap cap;
afbcf7ab 4454
90de4a18
NA		 4455 r = -EFAULT;
4456 if (copy_from_user(&cap, argp, sizeof(cap)))
4457 goto out;
4458 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4459 break;
4460 }
5acc5c06
BS		 4461 case KVM_MEMORY_ENCRYPT_OP: {
4462 r = -ENOTTY;
4463 if (kvm_x86_ops->mem_enc_op)
4464 r = kvm_x86_ops->mem_enc_op(kvm, argp);
4465 break;
4466 }
69eaedee
BS		 4467 case KVM_MEMORY_ENCRYPT_REG_REGION: {
4468 struct kvm_enc_region region;
4469
4470 r = -EFAULT;
4471 if (copy_from_user(&region, argp, sizeof(region)))
4472 goto out;
4473
4474 r = -ENOTTY;
4475 if (kvm_x86_ops->mem_enc_reg_region)
4476 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
4477 break;
4478 }
4479 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
4480 struct kvm_enc_region region;
4481
4482 r = -EFAULT;
4483 if (copy_from_user(&region, argp, sizeof(region)))
4484 goto out;
4485
4486 r = -ENOTTY;
4487 if (kvm_x86_ops->mem_enc_unreg_region)
4488 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
4489 break;
4490 }
faeb7833
RK		 4491 case KVM_HYPERV_EVENTFD: {
4492 struct kvm_hyperv_eventfd hvevfd;
4493
4494 r = -EFAULT;
4495 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
4496 goto out;
4497 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
4498 break;
4499 }
1fe779f8 4500 default:
ad6260da 4501 r = -ENOTTY;
1fe779f8
CO		 4502 }
4503out:
4504 return r;
4505}
4506
a16b043c 4507static void kvm_init_msr_list(void)
043405e1
CO		 4508{
4509 u32 dummy[2];
4510 unsigned i, j;
4511
62ef68bb 4512 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4513 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4514 continue;
93c4adc7
PB		 4515
4516 /*
4517 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4518 * to the guests in some cases.
93c4adc7
PB		 4519 */
4520 switch (msrs_to_save[i]) {
4521 case MSR_IA32_BNDCFGS:
4522 if (!kvm_x86_ops->mpx_supported())
4523 continue;
4524 break;
9dbe6cf9
PB		 4525 case MSR_TSC_AUX:
4526 if (!kvm_x86_ops->rdtscp_supported())
4527 continue;
4528 break;
93c4adc7
PB		 4529 default:
4530 break;
4531 }
4532
043405e1
CO		 4533 if (j < i)
4534 msrs_to_save[j] = msrs_to_save[i];
4535 j++;
4536 }
4537 num_msrs_to_save = j;
62ef68bb
PB		 4538
4539 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4540 switch (emulated_msrs[i]) {
6d396b55
PB		 4541 case MSR_IA32_SMBASE:
4542 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4543 continue;
4544 break;
62ef68bb
PB		 4545 default:
4546 break;
4547 }
4548
4549 if (j < i)
4550 emulated_msrs[j] = emulated_msrs[i];
4551 j++;
4552 }
4553 num_emulated_msrs = j;
801e459a
TL		 4554
4555 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4556 struct kvm_msr_entry msr;
4557
4558 msr.index = msr_based_features[i];
66421c1e 4559 if (kvm_get_msr_feature(&msr))
801e459a
TL		 4560 continue;
4561
4562 if (j < i)
4563 msr_based_features[j] = msr_based_features[i];
4564 j++;
4565 }
4566 num_msr_based_features = j;
043405e1
CO		 4567}
4568
bda9020e
MT		 4569static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4570 const void *v)
bbd9b64e 4571{
70252a10
AK		 4572 int handled = 0;
4573 int n;
4574
4575 do {
4576 n = min(len, 8);
bce87cce 4577 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4578 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4579 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4580 break;
4581 handled += n;
4582 addr += n;
4583 len -= n;
4584 v += n;
4585 } while (len);
bbd9b64e 4586
70252a10 4587 return handled;
bbd9b64e
CO		 4588}
4589
bda9020e 4590static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4591{
70252a10
AK		 4592 int handled = 0;
4593 int n;
4594
4595 do {
4596 n = min(len, 8);
bce87cce 4597 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4598 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4599 addr, n, v))
4600 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4601 break;
e39d200f 4602 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 4603 handled += n;
4604 addr += n;
4605 len -= n;
4606 v += n;
4607 } while (len);
bbd9b64e 4608
70252a10 4609 return handled;
bbd9b64e
CO		 4610}
4611
2dafc6c2
GN		 4612static void kvm_set_segment(struct kvm_vcpu *vcpu,
4613 struct kvm_segment *var, int seg)
4614{
4615 kvm_x86_ops->set_segment(vcpu, var, seg);
4616}
4617
4618void kvm_get_segment(struct kvm_vcpu *vcpu,
4619 struct kvm_segment *var, int seg)
4620{
4621 kvm_x86_ops->get_segment(vcpu, var, seg);
4622}
4623
54987b7a
PB		 4624gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4625 struct x86_exception *exception)
02f59dc9
JR		 4626{
4627 gpa_t t_gpa;
02f59dc9
JR		 4628
4629 BUG_ON(!mmu_is_nested(vcpu));
4630
4631 /* NPT walks are always user-walks */
4632 access |= PFERR_USER_MASK;
54987b7a 4633 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4634
4635 return t_gpa;
4636}
4637
ab9ae313
AK		 4638gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4639 struct x86_exception *exception)
1871c602
GN		 4640{
4641 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4642 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4643}
4644
ab9ae313
AK		 4645 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4646 struct x86_exception *exception)
1871c602
GN		 4647{
4648 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4649 access |= PFERR_FETCH_MASK;
ab9ae313 4650 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4651}
4652
ab9ae313
AK		 4653gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4654 struct x86_exception *exception)
1871c602
GN		 4655{
4656 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4657 access |= PFERR_WRITE_MASK;
ab9ae313 4658 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4659}
4660
4661/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4662gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4663 struct x86_exception *exception)
1871c602 4664{
ab9ae313 4665 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4666}
4667
4668static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4669 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4670 struct x86_exception *exception)
bbd9b64e
CO		 4671{
4672 void *data = val;
10589a46 4673 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4674
4675 while (bytes) {
14dfe855 4676 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4677 exception);
bbd9b64e 4678 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4679 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4680 int ret;
4681
bcc55cba 4682 if (gpa == UNMAPPED_GVA)
ab9ae313 4683 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4684 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4685 offset, toread);
10589a46 4686 if (ret < 0) {
c3cd7ffa 4687 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4688 goto out;
4689 }
bbd9b64e 4690
77c2002e
IE		 4691 bytes -= toread;
4692 data += toread;
4693 addr += toread;
bbd9b64e 4694 }
10589a46 4695out:
10589a46 4696 return r;
bbd9b64e 4697}
77c2002e 4698
1871c602 4699/* used for instruction fetching */
0f65dd70
AK		 4700static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4701 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4702 struct x86_exception *exception)
1871c602 4703{
0f65dd70 4704 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4705 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4706 unsigned offset;
4707 int ret;
0f65dd70 4708
44583cba
PB		 4709 /* Inline kvm_read_guest_virt_helper for speed. */
4710 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4711 exception);
4712 if (unlikely(gpa == UNMAPPED_GVA))
4713 return X86EMUL_PROPAGATE_FAULT;
4714
4715 offset = addr & (PAGE_SIZE-1);
4716 if (WARN_ON(offset + bytes > PAGE_SIZE))
4717 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4718 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4719 offset, bytes);
44583cba
PB		 4720 if (unlikely(ret < 0))
4721 return X86EMUL_IO_NEEDED;
4722
4723 return X86EMUL_CONTINUE;
1871c602
GN		 4724}
4725
064aea77 4726int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4727 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4728 struct x86_exception *exception)
1871c602 4729{
0f65dd70 4730 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4731 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4732
1871c602 4733 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4734 exception);
1871c602 4735}
064aea77 4736EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4737
0f65dd70
AK		 4738static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4739 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4740 struct x86_exception *exception)
1871c602 4741{
0f65dd70 4742 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4743 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4744}
4745
7a036a6f
RK		 4746static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4747 unsigned long addr, void *val, unsigned int bytes)
4748{
4749 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4750 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4751
4752 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4753}
4754
6a4d7550 4755int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4756 gva_t addr, void *val,
2dafc6c2 4757 unsigned int bytes,
bcc55cba 4758 struct x86_exception *exception)
77c2002e 4759{
0f65dd70 4760 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4761 void *data = val;
4762 int r = X86EMUL_CONTINUE;
4763
4764 while (bytes) {
14dfe855
JR		 4765 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4766 PFERR_WRITE_MASK,
ab9ae313 4767 exception);
77c2002e
IE		 4768 unsigned offset = addr & (PAGE_SIZE-1);
4769 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4770 int ret;
4771
bcc55cba 4772 if (gpa == UNMAPPED_GVA)
ab9ae313 4773 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4774 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4775 if (ret < 0) {
c3cd7ffa 4776 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4777 goto out;
4778 }
4779
4780 bytes -= towrite;
4781 data += towrite;
4782 addr += towrite;
4783 }
4784out:
4785 return r;
4786}
6a4d7550 4787EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4788
0f89b207
TL		 4789static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4790 gpa_t gpa, bool write)
4791{
4792 /* For APIC access vmexit */
4793 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4794 return 1;
4795
4796 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4797 trace_vcpu_match_mmio(gva, gpa, write, true);
4798 return 1;
4799 }
4800
4801 return 0;
4802}
4803
af7cc7d1
XG		 4804static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4805 gpa_t *gpa, struct x86_exception *exception,
4806 bool write)
4807{
97d64b78
AK		 4808 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4809 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4810
be94f6b7
HH		 4811 /*
4812 * currently PKRU is only applied to ept enabled guest so
4813 * there is no pkey in EPT page table for L1 guest or EPT
4814 * shadow page table for L2 guest.
4815 */
97d64b78 4816 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4817 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4818 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4819 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4820 (gva & (PAGE_SIZE - 1));
4f022648 4821 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4822 return 1;
4823 }
4824
af7cc7d1
XG		 4825 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4826
4827 if (*gpa == UNMAPPED_GVA)
4828 return -1;
4829
0f89b207 4830 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4831}
4832
3200f405 4833int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4834 const void *val, int bytes)
bbd9b64e
CO		 4835{
4836 int ret;
4837
54bf36aa 4838 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4839 if (ret < 0)
bbd9b64e 4840 return 0;
0eb05bf2 4841 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4842 return 1;
4843}
4844
77d197b2
XG		 4845struct read_write_emulator_ops {
4846 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4847 int bytes);
4848 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4849 void *val, int bytes);
4850 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4851 int bytes, void *val);
4852 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4853 void *val, int bytes);
4854 bool write;
4855};
4856
4857static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4858{
4859 if (vcpu->mmio_read_completed) {
77d197b2 4860 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4861 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 4862 vcpu->mmio_read_completed = 0;
4863 return 1;
4864 }
4865
4866 return 0;
4867}
4868
4869static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4870 void *val, int bytes)
4871{
54bf36aa 4872 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4873}
4874
4875static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4876 void *val, int bytes)
4877{
4878 return emulator_write_phys(vcpu, gpa, val, bytes);
4879}
4880
4881static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4882{
e39d200f 4883 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 4884 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4885}
4886
4887static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4888 void *val, int bytes)
4889{
e39d200f 4890 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 4891 return X86EMUL_IO_NEEDED;
4892}
4893
4894static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4895 void *val, int bytes)
4896{
f78146b0
AK		 4897 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4898
87da7e66 4899 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4900 return X86EMUL_CONTINUE;
4901}
4902
0fbe9b0b 4903static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4904 .read_write_prepare = read_prepare,
4905 .read_write_emulate = read_emulate,
4906 .read_write_mmio = vcpu_mmio_read,
4907 .read_write_exit_mmio = read_exit_mmio,
4908};
4909
0fbe9b0b 4910static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4911 .read_write_emulate = write_emulate,
4912 .read_write_mmio = write_mmio,
4913 .read_write_exit_mmio = write_exit_mmio,
4914 .write = true,
4915};
4916
22388a3c
XG		 4917static int emulator_read_write_onepage(unsigned long addr, void *val,
4918 unsigned int bytes,
4919 struct x86_exception *exception,
4920 struct kvm_vcpu *vcpu,
0fbe9b0b 4921 const struct read_write_emulator_ops *ops)
bbd9b64e 4922{
af7cc7d1
XG		 4923 gpa_t gpa;
4924 int handled, ret;
22388a3c 4925 bool write = ops->write;
f78146b0 4926 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4927 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4928
4929 /*
4930 * If the exit was due to a NPF we may already have a GPA.
4931 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4932 * Note, this cannot be used on string operations since string
4933 * operation using rep will only have the initial GPA from the NPF
4934 * occurred.
4935 */
4936 if (vcpu->arch.gpa_available &&
4937 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 4938 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4939 gpa = vcpu->arch.gpa_val;
4940 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4941 } else {
4942 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4943 if (ret < 0)
4944 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4945 }
10589a46 4946
618232e2 4947 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4948 return X86EMUL_CONTINUE;
4949
bbd9b64e
CO		 4950 /*
4951 * Is this MMIO handled locally?
4952 */
22388a3c 4953 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4954 if (handled == bytes)
bbd9b64e 4955 return X86EMUL_CONTINUE;
bbd9b64e 4956
70252a10
AK		 4957 gpa += handled;
4958 bytes -= handled;
4959 val += handled;
4960
87da7e66
XG		 4961 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4962 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4963 frag->gpa = gpa;
4964 frag->data = val;
4965 frag->len = bytes;
f78146b0 4966 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4967}
4968
52eb5a6d
XL		 4969static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4970 unsigned long addr,
22388a3c
XG		 4971 void *val, unsigned int bytes,
4972 struct x86_exception *exception,
0fbe9b0b 4973 const struct read_write_emulator_ops *ops)
bbd9b64e 4974{
0f65dd70 4975 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4976 gpa_t gpa;
4977 int rc;
4978
4979 if (ops->read_write_prepare &&
4980 ops->read_write_prepare(vcpu, val, bytes))
4981 return X86EMUL_CONTINUE;
4982
4983 vcpu->mmio_nr_fragments = 0;
0f65dd70 4984
bbd9b64e
CO		 4985 /* Crossing a page boundary? */
4986 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4987 int now;
bbd9b64e
CO		 4988
4989 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4990 rc = emulator_read_write_onepage(addr, val, now, exception,
4991 vcpu, ops);
4992
bbd9b64e
CO		 4993 if (rc != X86EMUL_CONTINUE)
4994 return rc;
4995 addr += now;
bac15531
NA		 4996 if (ctxt->mode != X86EMUL_MODE_PROT64)
4997 addr = (u32)addr;
bbd9b64e
CO		 4998 val += now;
4999 bytes -= now;
5000 }
22388a3c 5001
f78146b0
AK		 5002 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5003 vcpu, ops);
5004 if (rc != X86EMUL_CONTINUE)
5005 return rc;
5006
5007 if (!vcpu->mmio_nr_fragments)
5008 return rc;
5009
5010 gpa = vcpu->mmio_fragments[0].gpa;
5011
5012 vcpu->mmio_needed = 1;
5013 vcpu->mmio_cur_fragment = 0;
5014
87da7e66 5015 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5016 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5017 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5018 vcpu->run->mmio.phys_addr = gpa;
5019
5020 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5021}
5022
5023static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5024 unsigned long addr,
5025 void *val,
5026 unsigned int bytes,
5027 struct x86_exception *exception)
5028{
5029 return emulator_read_write(ctxt, addr, val, bytes,
5030 exception, &read_emultor);
5031}
5032
52eb5a6d 5033static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5034 unsigned long addr,
5035 const void *val,
5036 unsigned int bytes,
5037 struct x86_exception *exception)
5038{
5039 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5040 exception, &write_emultor);
bbd9b64e 5041}
bbd9b64e 5042
daea3e73
AK		 5043#define CMPXCHG_TYPE(t, ptr, old, new) \
5044 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5045
5046#ifdef CONFIG_X86_64
5047# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5048#else
5049# define CMPXCHG64(ptr, old, new) \
9749a6c0 5050 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5051#endif
5052
0f65dd70
AK		 5053static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5054 unsigned long addr,
bbd9b64e
CO		 5055 const void *old,
5056 const void *new,
5057 unsigned int bytes,
0f65dd70 5058 struct x86_exception *exception)
bbd9b64e 5059{
0f65dd70 5060 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 5061 gpa_t gpa;
5062 struct page *page;
5063 char *kaddr;
5064 bool exchanged;
2bacc55c 5065
daea3e73
AK		 5066 /* guests cmpxchg8b have to be emulated atomically */
5067 if (bytes > 8 || (bytes & (bytes - 1)))
5068 goto emul_write;
10589a46 5069
daea3e73 5070 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5071
daea3e73
AK		 5072 if (gpa == UNMAPPED_GVA ||
5073 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5074 goto emul_write;
2bacc55c 5075
daea3e73
AK		 5076 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5077 goto emul_write;
72dc67a6 5078
54bf36aa 5079 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 5080 if (is_error_page(page))
c19b8bd6 5081 goto emul_write;
72dc67a6 5082
8fd75e12 5083 kaddr = kmap_atomic(page);
daea3e73
AK		 5084 kaddr += offset_in_page(gpa);
5085 switch (bytes) {
5086 case 1:
5087 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5088 break;
5089 case 2:
5090 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5091 break;
5092 case 4:
5093 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5094 break;
5095 case 8:
5096 exchanged = CMPXCHG64(kaddr, old, new);
5097 break;
5098 default:
5099 BUG();
2bacc55c 5100 }
8fd75e12 5101 kunmap_atomic(kaddr);
daea3e73
AK		 5102 kvm_release_page_dirty(page);
5103
5104 if (!exchanged)
5105 return X86EMUL_CMPXCHG_FAILED;
5106
54bf36aa 5107 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 5108 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5109
5110 return X86EMUL_CONTINUE;
4a5f48f6 5111
3200f405 5112emul_write:
daea3e73 5113 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5114
0f65dd70 5115 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5116}
5117
cf8f70bf
GN		 5118static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5119{
cbfc6c91 5120 int r = 0, i;
cf8f70bf 5121
cbfc6c91
WL		 5122 for (i = 0; i < vcpu->arch.pio.count; i++) {
5123 if (vcpu->arch.pio.in)
5124 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5125 vcpu->arch.pio.size, pd);
5126 else
5127 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5128 vcpu->arch.pio.port, vcpu->arch.pio.size,
5129 pd);
5130 if (r)
5131 break;
5132 pd += vcpu->arch.pio.size;
5133 }
cf8f70bf
GN		 5134 return r;
5135}
5136
6f6fbe98
XG		 5137static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5138 unsigned short port, void *val,
5139 unsigned int count, bool in)
cf8f70bf 5140{
cf8f70bf 5141 vcpu->arch.pio.port = port;
6f6fbe98 5142 vcpu->arch.pio.in = in;
7972995b 5143 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5144 vcpu->arch.pio.size = size;
5145
5146 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5147 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5148 return 1;
5149 }
5150
5151 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5152 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5153 vcpu->run->io.size = size;
5154 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5155 vcpu->run->io.count = count;
5156 vcpu->run->io.port = port;
5157
5158 return 0;
5159}
5160
6f6fbe98
XG		 5161static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5162 int size, unsigned short port, void *val,
5163 unsigned int count)
cf8f70bf 5164{
ca1d4a9e 5165 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5166 int ret;
ca1d4a9e 5167
6f6fbe98
XG		 5168 if (vcpu->arch.pio.count)
5169 goto data_avail;
cf8f70bf 5170
cbfc6c91
WL		 5171 memset(vcpu->arch.pio_data, 0, size * count);
5172
6f6fbe98
XG		 5173 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5174 if (ret) {
5175data_avail:
5176 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5177 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5178 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5179 return 1;
5180 }
5181
cf8f70bf
GN		 5182 return 0;
5183}
5184
6f6fbe98
XG		 5185static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5186 int size, unsigned short port,
5187 const void *val, unsigned int count)
5188{
5189 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5190
5191 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5192 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5193 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5194}
5195
bbd9b64e
CO		 5196static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5197{
5198 return kvm_x86_ops->get_segment_base(vcpu, seg);
5199}
5200
3cb16fe7 5201static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5202{
3cb16fe7 5203 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5204}
5205
ae6a2375 5206static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 5207{
5208 if (!need_emulate_wbinvd(vcpu))
5209 return X86EMUL_CONTINUE;
5210
5211 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 5212 int cpu = get_cpu();
5213
5214 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 5215 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5216 wbinvd_ipi, NULL, 1);
2eec7343 5217 put_cpu();
f5f48ee1 5218 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 5219 } else
5220 wbinvd();
f5f48ee1
SY		 5221 return X86EMUL_CONTINUE;
5222}
5cb56059
JS		 5223
5224int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5225{
6affcbed
KH		 5226 kvm_emulate_wbinvd_noskip(vcpu);
5227 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5228}
f5f48ee1
SY		 5229EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5230
5cb56059
JS		 5231
5232
bcaf5cc5
AK		 5233static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5234{
5cb56059 5235 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 5236}
5237
52eb5a6d
XL		 5238static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5239 unsigned long *dest)
bbd9b64e 5240{
16f8a6f9 5241 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 5242}
5243
52eb5a6d
XL		 5244static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5245 unsigned long value)
bbd9b64e 5246{
338dbc97 5247
717746e3 5248 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 5249}
5250
52a46617 5251static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5252{
52a46617 5253 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 5254}
5255
717746e3 5256static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5257{
717746e3 5258 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 5259 unsigned long value;
5260
5261 switch (cr) {
5262 case 0:
5263 value = kvm_read_cr0(vcpu);
5264 break;
5265 case 2:
5266 value = vcpu->arch.cr2;
5267 break;
5268 case 3:
9f8fe504 5269 value = kvm_read_cr3(vcpu);
52a46617
GN		 5270 break;
5271 case 4:
5272 value = kvm_read_cr4(vcpu);
5273 break;
5274 case 8:
5275 value = kvm_get_cr8(vcpu);
5276 break;
5277 default:
a737f256 5278 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 5279 return 0;
5280 }
5281
5282 return value;
5283}
5284
717746e3 5285static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5286{
717746e3 5287 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 5288 int res = 0;
5289
52a46617
GN		 5290 switch (cr) {
5291 case 0:
49a9b07e 5292 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 5293 break;
5294 case 2:
5295 vcpu->arch.cr2 = val;
5296 break;
5297 case 3:
2390218b 5298 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 5299 break;
5300 case 4:
a83b29c6 5301 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5302 break;
5303 case 8:
eea1cff9 5304 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5305 break;
5306 default:
a737f256 5307 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5308 res = -1;
52a46617 5309 }
0f12244f
GN		 5310
5311 return res;
52a46617
GN		 5312}
5313
717746e3 5314static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5315{
717746e3 5316 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5317}
5318
4bff1e86 5319static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5320{
4bff1e86 5321 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5322}
5323
4bff1e86 5324static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5325{
4bff1e86 5326 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5327}
5328
1ac9d0cf
AK		 5329static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5330{
5331 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5332}
5333
5334static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5335{
5336 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5337}
5338
4bff1e86
AK		 5339static unsigned long emulator_get_cached_segment_base(
5340 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5341{
4bff1e86 5342 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5343}
5344
1aa36616
AK		 5345static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5346 struct desc_struct *desc, u32 *base3,
5347 int seg)
2dafc6c2
GN		 5348{
5349 struct kvm_segment var;
5350
4bff1e86 5351 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5352 *selector = var.selector;
2dafc6c2 5353
378a8b09
GN		 5354 if (var.unusable) {
5355 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 5356 if (base3)
5357 *base3 = 0;
2dafc6c2 5358 return false;
378a8b09 5359 }
2dafc6c2
GN		 5360
5361 if (var.g)
5362 var.limit >>= 12;
5363 set_desc_limit(desc, var.limit);
5364 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5365#ifdef CONFIG_X86_64
5366 if (base3)
5367 *base3 = var.base >> 32;
5368#endif
2dafc6c2
GN		 5369 desc->type = var.type;
5370 desc->s = var.s;
5371 desc->dpl = var.dpl;
5372 desc->p = var.present;
5373 desc->avl = var.avl;
5374 desc->l = var.l;
5375 desc->d = var.db;
5376 desc->g = var.g;
5377
5378 return true;
5379}
5380
1aa36616
AK		 5381static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5382 struct desc_struct *desc, u32 base3,
5383 int seg)
2dafc6c2 5384{
4bff1e86 5385 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5386 struct kvm_segment var;
5387
1aa36616 5388 var.selector = selector;
2dafc6c2 5389 var.base = get_desc_base(desc);
5601d05b
GN		 5390#ifdef CONFIG_X86_64
5391 var.base |= ((u64)base3) << 32;
5392#endif
2dafc6c2
GN		 5393 var.limit = get_desc_limit(desc);
5394 if (desc->g)
5395 var.limit = (var.limit << 12) | 0xfff;
5396 var.type = desc->type;
2dafc6c2
GN		 5397 var.dpl = desc->dpl;
5398 var.db = desc->d;
5399 var.s = desc->s;
5400 var.l = desc->l;
5401 var.g = desc->g;
5402 var.avl = desc->avl;
5403 var.present = desc->p;
5404 var.unusable = !var.present;
5405 var.padding = 0;
5406
5407 kvm_set_segment(vcpu, &var, seg);
5408 return;
5409}
5410
717746e3
AK		 5411static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5412 u32 msr_index, u64 *pdata)
5413{
609e36d3
PB		 5414 struct msr_data msr;
5415 int r;
5416
5417 msr.index = msr_index;
5418 msr.host_initiated = false;
5419 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5420 if (r)
5421 return r;
5422
5423 *pdata = msr.data;
5424 return 0;
717746e3
AK		 5425}
5426
5427static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5428 u32 msr_index, u64 data)
5429{
8fe8ab46
WA		 5430 struct msr_data msr;
5431
5432 msr.data = data;
5433 msr.index = msr_index;
5434 msr.host_initiated = false;
5435 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5436}
5437
64d60670
PB		 5438static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5439{
5440 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5441
5442 return vcpu->arch.smbase;
5443}
5444
5445static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5446{
5447 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5448
5449 vcpu->arch.smbase = smbase;
5450}
5451
67f4d428
NA		 5452static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5453 u32 pmc)
5454{
c6702c9d 5455 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5456}
5457
222d21aa
AK		 5458static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5459 u32 pmc, u64 *pdata)
5460{
c6702c9d 5461 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5462}
5463
6c3287f7
AK		 5464static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5465{
5466 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5467}
5468
2953538e 5469static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5470 struct x86_instruction_info *info,
c4f035c6
AK		 5471 enum x86_intercept_stage stage)
5472{
2953538e 5473 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5474}
5475
e911eb3b
YZ		 5476static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5477 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5478{
e911eb3b 5479 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 5480}
5481
dd856efa
AK		 5482static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5483{
5484 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5485}
5486
5487static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5488{
5489 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5490}
5491
801806d9
NA		 5492static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5493{
5494 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5495}
5496
6ed071f0
LP		 5497static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5498{
5499 return emul_to_vcpu(ctxt)->arch.hflags;
5500}
5501
5502static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5503{
5504 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5505}
5506
0234bf88
LP		 5507static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5508{
5509 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5510}
5511
0225fb50 5512static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5513 .read_gpr = emulator_read_gpr,
5514 .write_gpr = emulator_write_gpr,
1871c602 5515 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5516 .write_std = kvm_write_guest_virt_system,
7a036a6f 5517 .read_phys = kvm_read_guest_phys_system,
1871c602 5518 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5519 .read_emulated = emulator_read_emulated,
5520 .write_emulated = emulator_write_emulated,
5521 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5522 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5523 .pio_in_emulated = emulator_pio_in_emulated,
5524 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5525 .get_segment = emulator_get_segment,
5526 .set_segment = emulator_set_segment,
5951c442 5527 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5528 .get_gdt = emulator_get_gdt,
160ce1f1 5529 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5530 .set_gdt = emulator_set_gdt,
5531 .set_idt = emulator_set_idt,
52a46617
GN		 5532 .get_cr = emulator_get_cr,
5533 .set_cr = emulator_set_cr,
9c537244 5534 .cpl = emulator_get_cpl,
35aa5375
GN		 5535 .get_dr = emulator_get_dr,
5536 .set_dr = emulator_set_dr,
64d60670
PB		 5537 .get_smbase = emulator_get_smbase,
5538 .set_smbase = emulator_set_smbase,
717746e3
AK		 5539 .set_msr = emulator_set_msr,
5540 .get_msr = emulator_get_msr,
67f4d428 5541 .check_pmc = emulator_check_pmc,
222d21aa 5542 .read_pmc = emulator_read_pmc,
6c3287f7 5543 .halt = emulator_halt,
bcaf5cc5 5544 .wbinvd = emulator_wbinvd,
d6aa1000 5545 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5546 .intercept = emulator_intercept,
bdb42f5a 5547 .get_cpuid = emulator_get_cpuid,
801806d9 5548 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 5549 .get_hflags = emulator_get_hflags,
5550 .set_hflags = emulator_set_hflags,
0234bf88 5551 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO		 5552};
5553
95cb2295
GN		 5554static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5555{
37ccdcbe 5556 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5557 /*
5558 * an sti; sti; sequence only disable interrupts for the first
5559 * instruction. So, if the last instruction, be it emulated or
5560 * not, left the system with the INT_STI flag enabled, it
5561 * means that the last instruction is an sti. We should not
5562 * leave the flag on in this case. The same goes for mov ss
5563 */
37ccdcbe
PB		 5564 if (int_shadow & mask)
5565 mask = 0;
6addfc42 5566 if (unlikely(int_shadow || mask)) {
95cb2295 5567 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5568 if (!mask)
5569 kvm_make_request(KVM_REQ_EVENT, vcpu);
5570 }
95cb2295
GN		 5571}
5572
ef54bcfe 5573static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5574{
5575 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5576 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5577 return kvm_propagate_fault(vcpu, &ctxt->exception);
5578
5579 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5580 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5581 ctxt->exception.error_code);
54b8486f 5582 else
da9cb575 5583 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5584 return false;
54b8486f
GN		 5585}
5586
8ec4722d
MG		 5587static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5588{
adf52235 5589 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5590 int cs_db, cs_l;
5591
8ec4722d
MG		 5592 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5593
adf52235 5594 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 5595 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5596
adf52235
TY		 5597 ctxt->eip = kvm_rip_read(vcpu);
5598 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5599 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5600 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5601 cs_db ? X86EMUL_MODE_PROT32 :
5602 X86EMUL_MODE_PROT16;
a584539b 5603 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5604 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5605 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5606
dd856efa 5607 init_decode_cache(ctxt);
7ae441ea 5608 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5609}
5610
71f9833b 5611int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5612{
9d74191a 5613 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5614 int ret;
5615
5616 init_emulate_ctxt(vcpu);
5617
9dac77fa
AK		 5618 ctxt->op_bytes = 2;
5619 ctxt->ad_bytes = 2;
5620 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5621 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5622
5623 if (ret != X86EMUL_CONTINUE)
5624 return EMULATE_FAIL;
5625
9dac77fa 5626 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5627 kvm_rip_write(vcpu, ctxt->eip);
5628 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5629
5630 if (irq == NMI_VECTOR)
7460fb4a 5631 vcpu->arch.nmi_pending = 0;
63995653
MG		 5632 else
5633 vcpu->arch.interrupt.pending = false;
5634
5635 return EMULATE_DONE;
5636}
5637EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5638
6d77dbfc
GN		 5639static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5640{
fc3a9157
JR		 5641 int r = EMULATE_DONE;
5642
6d77dbfc
GN		 5643 ++vcpu->stat.insn_emulation_fail;
5644 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5645 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5646 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5647 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5648 vcpu->run->internal.ndata = 0;
1f4dcb3b 5649 r = EMULATE_USER_EXIT;
fc3a9157 5650 }
6d77dbfc 5651 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5652
5653 return r;
6d77dbfc
GN		 5654}
5655
93c05d3e 5656static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5657 bool write_fault_to_shadow_pgtable,
5658 int emulation_type)
a6f177ef 5659{
95b3cf69 5660 gpa_t gpa = cr2;
ba049e93 5661 kvm_pfn_t pfn;
a6f177ef 5662
991eebf9
GN		 5663 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5664 return false;
5665
95b3cf69
XG		 5666 if (!vcpu->arch.mmu.direct_map) {
5667 /*
5668 * Write permission should be allowed since only
5669 * write access need to be emulated.
5670 */
5671 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5672
95b3cf69
XG		 5673 /*
5674 * If the mapping is invalid in guest, let cpu retry
5675 * it to generate fault.
5676 */
5677 if (gpa == UNMAPPED_GVA)
5678 return true;
5679 }
a6f177ef 5680
8e3d9d06
XG		 5681 /*
5682 * Do not retry the unhandleable instruction if it faults on the
5683 * readonly host memory, otherwise it will goto a infinite loop:
5684 * retry instruction -> write #PF -> emulation fail -> retry
5685 * instruction -> ...
5686 */
5687 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5688
5689 /*
5690 * If the instruction failed on the error pfn, it can not be fixed,
5691 * report the error to userspace.
5692 */
5693 if (is_error_noslot_pfn(pfn))
5694 return false;
5695
5696 kvm_release_pfn_clean(pfn);
5697
5698 /* The instructions are well-emulated on direct mmu. */
5699 if (vcpu->arch.mmu.direct_map) {
5700 unsigned int indirect_shadow_pages;
5701
5702 spin_lock(&vcpu->kvm->mmu_lock);
5703 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5704 spin_unlock(&vcpu->kvm->mmu_lock);
5705
5706 if (indirect_shadow_pages)
5707 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5708
a6f177ef 5709 return true;
8e3d9d06 5710 }
a6f177ef 5711
95b3cf69
XG		 5712 /*
5713 * if emulation was due to access to shadowed page table
5714 * and it failed try to unshadow page and re-enter the
5715 * guest to let CPU execute the instruction.
5716 */
5717 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5718
5719 /*
5720 * If the access faults on its page table, it can not
5721 * be fixed by unprotecting shadow page and it should
5722 * be reported to userspace.
5723 */
5724 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5725}
5726
1cb3f3ae
XG		 5727static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5728 unsigned long cr2, int emulation_type)
5729{
5730 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5731 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5732
5733 last_retry_eip = vcpu->arch.last_retry_eip;
5734 last_retry_addr = vcpu->arch.last_retry_addr;
5735
5736 /*
5737 * If the emulation is caused by #PF and it is non-page_table
5738 * writing instruction, it means the VM-EXIT is caused by shadow
5739 * page protected, we can zap the shadow page and retry this
5740 * instruction directly.
5741 *
5742 * Note: if the guest uses a non-page-table modifying instruction
5743 * on the PDE that points to the instruction, then we will unmap
5744 * the instruction and go to an infinite loop. So, we cache the
5745 * last retried eip and the last fault address, if we meet the eip
5746 * and the address again, we can break out of the potential infinite
5747 * loop.
5748 */
5749 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5750
5751 if (!(emulation_type & EMULTYPE_RETRY))
5752 return false;
5753
5754 if (x86_page_table_writing_insn(ctxt))
5755 return false;
5756
5757 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5758 return false;
5759
5760 vcpu->arch.last_retry_eip = ctxt->eip;
5761 vcpu->arch.last_retry_addr = cr2;
5762
5763 if (!vcpu->arch.mmu.direct_map)
5764 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5765
22368028 5766 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5767
5768 return true;
5769}
5770
716d51ab
GN		 5771static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5772static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5773
64d60670 5774static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5775{
64d60670 5776 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5777 /* This is a good place to trace that we are exiting SMM. */
5778 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5779
c43203ca
PB		 5780 /* Process a latched INIT or SMI, if any. */
5781 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5782 }
699023e2
PB		 5783
5784 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5785}
5786
5787static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5788{
5789 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5790
a584539b 5791 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5792
5793 if (changed & HF_SMM_MASK)
5794 kvm_smm_changed(vcpu);
a584539b
PB		 5795}
5796
4a1e10d5
PB		 5797static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5798 unsigned long *db)
5799{
5800 u32 dr6 = 0;
5801 int i;
5802 u32 enable, rwlen;
5803
5804 enable = dr7;
5805 rwlen = dr7 >> 16;
5806 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5807 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5808 dr6 |= (1 << i);
5809 return dr6;
5810}
5811
c8401dda 5812static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB		 5813{
5814 struct kvm_run *kvm_run = vcpu->run;
5815
c8401dda
PB		 5816 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5817 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5818 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5819 kvm_run->debug.arch.exception = DB_VECTOR;
5820 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5821 *r = EMULATE_USER_EXIT;
5822 } else {
5823 /*
5824 * "Certain debug exceptions may clear bit 0-3. The
5825 * remaining contents of the DR6 register are never
5826 * cleared by the processor".
5827 */
5828 vcpu->arch.dr6 &= ~15;
5829 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5830 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB		 5831 }
5832}
5833
6affcbed
KH		 5834int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5835{
5836 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5837 int r = EMULATE_DONE;
5838
5839 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB		 5840
5841 /*
5842 * rflags is the old, "raw" value of the flags. The new value has
5843 * not been saved yet.
5844 *
5845 * This is correct even for TF set by the guest, because "the
5846 * processor will not generate this exception after the instruction
5847 * that sets the TF flag".
5848 */
5849 if (unlikely(rflags & X86_EFLAGS_TF))
5850 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH		 5851 return r == EMULATE_DONE;
5852}
5853EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5854
4a1e10d5
PB		 5855static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5856{
4a1e10d5
PB		 5857 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5858 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5859 struct kvm_run *kvm_run = vcpu->run;
5860 unsigned long eip = kvm_get_linear_rip(vcpu);
5861 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5862 vcpu->arch.guest_debug_dr7,
5863 vcpu->arch.eff_db);
5864
5865 if (dr6 != 0) {
6f43ed01 5866 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5867 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5868 kvm_run->debug.arch.exception = DB_VECTOR;
5869 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5870 *r = EMULATE_USER_EXIT;
5871 return true;
5872 }
5873 }
5874
4161a569
NA		 5875 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5876 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5877 unsigned long eip = kvm_get_linear_rip(vcpu);
5878 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5879 vcpu->arch.dr7,
5880 vcpu->arch.db);
5881
5882 if (dr6 != 0) {
5883 vcpu->arch.dr6 &= ~15;
6f43ed01 5884 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5885 kvm_queue_exception(vcpu, DB_VECTOR);
5886 *r = EMULATE_DONE;
5887 return true;
5888 }
5889 }
5890
5891 return false;
5892}
5893
51d8b661
AP		 5894int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5895 unsigned long cr2,
dc25e89e
AP		 5896 int emulation_type,
5897 void *insn,
5898 int insn_len)
bbd9b64e 5899{
95cb2295 5900 int r;
9d74191a 5901 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5902 bool writeback = true;
93c05d3e 5903 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5904
93c05d3e
XG		 5905 /*
5906 * Clear write_fault_to_shadow_pgtable here to ensure it is
5907 * never reused.
5908 */
5909 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5910 kvm_clear_exception_queue(vcpu);
8d7d8102 5911
571008da 5912 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5913 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5914
5915 /*
5916 * We will reenter on the same instruction since
5917 * we do not set complete_userspace_io. This does not
5918 * handle watchpoints yet, those would be handled in
5919 * the emulate_ops.
5920 */
d391f120
VK		 5921 if (!(emulation_type & EMULTYPE_SKIP) &&
5922 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 5923 return r;
5924
9d74191a
TY		 5925 ctxt->interruptibility = 0;
5926 ctxt->have_exception = false;
e0ad0b47 5927 ctxt->exception.vector = -1;
9d74191a 5928 ctxt->perm_ok = false;
bbd9b64e 5929
b51e974f 5930 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5931
9d74191a 5932 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5933
e46479f8 5934 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5935 ++vcpu->stat.insn_emulation;
1d2887e2 5936 if (r != EMULATION_OK) {
4005996e
AK		 5937 if (emulation_type & EMULTYPE_TRAP_UD)
5938 return EMULATE_FAIL;
991eebf9
GN		 5939 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5940 emulation_type))
bbd9b64e 5941 return EMULATE_DONE;
6ea6e843
PB		 5942 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5943 return EMULATE_DONE;
6d77dbfc
GN		 5944 if (emulation_type & EMULTYPE_SKIP)
5945 return EMULATE_FAIL;
5946 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5947 }
5948 }
5949
ba8afb6b 5950 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5951 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5952 if (ctxt->eflags & X86_EFLAGS_RF)
5953 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5954 return EMULATE_DONE;
5955 }
5956
1cb3f3ae
XG		 5957 if (retry_instruction(ctxt, cr2, emulation_type))
5958 return EMULATE_DONE;
5959
7ae441ea 5960 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5961 changes registers values during IO operation */
7ae441ea
GN		 5962 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5963 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5964 emulator_invalidate_register_cache(ctxt);
7ae441ea 5965 }
4d2179e1 5966
5cd21917 5967restart:
0f89b207
TL		 5968 /* Save the faulting GPA (cr2) in the address field */
5969 ctxt->exception.address = cr2;
5970
9d74191a 5971 r = x86_emulate_insn(ctxt);
bbd9b64e 5972
775fde86
JR		 5973 if (r == EMULATION_INTERCEPTED)
5974 return EMULATE_DONE;
5975
d2ddd1c4 5976 if (r == EMULATION_FAILED) {
991eebf9
GN		 5977 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5978 emulation_type))
c3cd7ffa
GN		 5979 return EMULATE_DONE;
5980
6d77dbfc 5981 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5982 }
5983
9d74191a 5984 if (ctxt->have_exception) {
d2ddd1c4 5985 r = EMULATE_DONE;
ef54bcfe
PB		 5986 if (inject_emulated_exception(vcpu))
5987 return r;
d2ddd1c4 5988 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5989 if (!vcpu->arch.pio.in) {
5990 /* FIXME: return into emulator if single-stepping. */
3457e419 5991 vcpu->arch.pio.count = 0;
0912c977 5992 } else {
7ae441ea 5993 writeback = false;
716d51ab
GN		 5994 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5995 }
ac0a48c3 5996 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5997 } else if (vcpu->mmio_needed) {
5998 if (!vcpu->mmio_is_write)
5999 writeback = false;
ac0a48c3 6000 r = EMULATE_USER_EXIT;
716d51ab 6001 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6002 } else if (r == EMULATION_RESTART)
5cd21917 6003 goto restart;
d2ddd1c4
GN		 6004 else
6005 r = EMULATE_DONE;
f850e2e6 6006
7ae441ea 6007 if (writeback) {
6addfc42 6008 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6009 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6010 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 6011 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB		 6012 if (r == EMULATE_DONE &&
6013 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
6014 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA		 6015 if (!ctxt->have_exception ||
6016 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
6017 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 6018
6019 /*
6020 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6021 * do nothing, and it will be requested again as soon as
6022 * the shadow expires. But we still need to check here,
6023 * because POPF has no interrupt shadow.
6024 */
6025 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6026 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6027 } else
6028 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6029
6030 return r;
de7d789a 6031}
51d8b661 6032EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 6033
cf8f70bf 6034int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 6035{
cf8f70bf 6036 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 6037 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6038 size, port, &val, 1);
cf8f70bf 6039 /* do not return to emulator after return from userspace */
7972995b 6040 vcpu->arch.pio.count = 0;
de7d789a
CO		 6041 return ret;
6042}
cf8f70bf 6043EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 6044
8370c3d0
TL		 6045static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6046{
6047 unsigned long val;
6048
6049 /* We should only ever be called with arch.pio.count equal to 1 */
6050 BUG_ON(vcpu->arch.pio.count != 1);
6051
6052 /* For size less than 4 we merge, else we zero extend */
6053 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
6054 : 0;
6055
6056 /*
6057 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6058 * the copy and tracing
6059 */
6060 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6061 vcpu->arch.pio.port, &val, 1);
6062 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6063
6064 return 1;
6065}
6066
6067int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
6068{
6069 unsigned long val;
6070 int ret;
6071
6072 /* For size less than 4 we merge, else we zero extend */
6073 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
6074
6075 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6076 &val, 1);
6077 if (ret) {
6078 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
6079 return ret;
6080 }
6081
6082 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6083
6084 return 0;
6085}
6086EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
6087
251a5fd6 6088static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 6089{
0a3aee0d 6090 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 6091 return 0;
8cfdc000
ZA		 6092}
6093
6094static void tsc_khz_changed(void *data)
c8076604 6095{
8cfdc000
ZA		 6096 struct cpufreq_freqs *freq = data;
6097 unsigned long khz = 0;
6098
6099 if (data)
6100 khz = freq->new;
6101 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6102 khz = cpufreq_quick_get(raw_smp_processor_id());
6103 if (!khz)
6104 khz = tsc_khz;
0a3aee0d 6105 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 6106}
6107
5fa4ec9c 6108#ifdef CONFIG_X86_64
0092e434
VK		 6109static void kvm_hyperv_tsc_notifier(void)
6110{
0092e434
VK		 6111 struct kvm *kvm;
6112 struct kvm_vcpu *vcpu;
6113 int cpu;
6114
6115 spin_lock(&kvm_lock);
6116 list_for_each_entry(kvm, &vm_list, vm_list)
6117 kvm_make_mclock_inprogress_request(kvm);
6118
6119 hyperv_stop_tsc_emulation();
6120
6121 /* TSC frequency always matches when on Hyper-V */
6122 for_each_present_cpu(cpu)
6123 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
6124 kvm_max_guest_tsc_khz = tsc_khz;
6125
6126 list_for_each_entry(kvm, &vm_list, vm_list) {
6127 struct kvm_arch *ka = &kvm->arch;
6128
6129 spin_lock(&ka->pvclock_gtod_sync_lock);
6130
6131 pvclock_update_vm_gtod_copy(kvm);
6132
6133 kvm_for_each_vcpu(cpu, vcpu, kvm)
6134 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
6135
6136 kvm_for_each_vcpu(cpu, vcpu, kvm)
6137 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
6138
6139 spin_unlock(&ka->pvclock_gtod_sync_lock);
6140 }
6141 spin_unlock(&kvm_lock);
0092e434 6142}
5fa4ec9c 6143#endif
0092e434 6144
c8076604
GH		 6145static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
6146 void *data)
6147{
6148 struct cpufreq_freqs *freq = data;
6149 struct kvm *kvm;
6150 struct kvm_vcpu *vcpu;
6151 int i, send_ipi = 0;
6152
8cfdc000
ZA		 6153 /*
6154 * We allow guests to temporarily run on slowing clocks,
6155 * provided we notify them after, or to run on accelerating
6156 * clocks, provided we notify them before. Thus time never
6157 * goes backwards.
6158 *
6159 * However, we have a problem. We can't atomically update
6160 * the frequency of a given CPU from this function; it is
6161 * merely a notifier, which can be called from any CPU.
6162 * Changing the TSC frequency at arbitrary points in time
6163 * requires a recomputation of local variables related to
6164 * the TSC for each VCPU. We must flag these local variables
6165 * to be updated and be sure the update takes place with the
6166 * new frequency before any guests proceed.
6167 *
6168 * Unfortunately, the combination of hotplug CPU and frequency
6169 * change creates an intractable locking scenario; the order
6170 * of when these callouts happen is undefined with respect to
6171 * CPU hotplug, and they can race with each other. As such,
6172 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6173 * undefined; you can actually have a CPU frequency change take
6174 * place in between the computation of X and the setting of the
6175 * variable. To protect against this problem, all updates of
6176 * the per_cpu tsc_khz variable are done in an interrupt
6177 * protected IPI, and all callers wishing to update the value
6178 * must wait for a synchronous IPI to complete (which is trivial
6179 * if the caller is on the CPU already). This establishes the
6180 * necessary total order on variable updates.
6181 *
6182 * Note that because a guest time update may take place
6183 * anytime after the setting of the VCPU's request bit, the
6184 * correct TSC value must be set before the request. However,
6185 * to ensure the update actually makes it to any guest which
6186 * starts running in hardware virtualization between the set
6187 * and the acquisition of the spinlock, we must also ping the
6188 * CPU after setting the request bit.
6189 *
6190 */
6191
c8076604
GH		 6192 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6193 return 0;
6194 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6195 return 0;
8cfdc000
ZA		 6196
6197 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6198
2f303b74 6199 spin_lock(&kvm_lock);
c8076604 6200 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6201 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 6202 if (vcpu->cpu != freq->cpu)
6203 continue;
c285545f 6204 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6205 if (vcpu->cpu != smp_processor_id())
8cfdc000 6206 send_ipi = 1;
c8076604
GH		 6207 }
6208 }
2f303b74 6209 spin_unlock(&kvm_lock);
c8076604
GH		 6210
6211 if (freq->old < freq->new && send_ipi) {
6212 /*
6213 * We upscale the frequency. Must make the guest
6214 * doesn't see old kvmclock values while running with
6215 * the new frequency, otherwise we risk the guest sees
6216 * time go backwards.
6217 *
6218 * In case we update the frequency for another cpu
6219 * (which might be in guest context) send an interrupt
6220 * to kick the cpu out of guest context. Next time
6221 * guest context is entered kvmclock will be updated,
6222 * so the guest will not see stale values.
6223 */
8cfdc000 6224 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 6225 }
6226 return 0;
6227}
6228
6229static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 6230 .notifier_call = kvmclock_cpufreq_notifier
6231};
6232
251a5fd6 6233static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6234{
251a5fd6
SAS		 6235 tsc_khz_changed(NULL);
6236 return 0;
8cfdc000
ZA		 6237}
6238
b820cc0c
ZA		 6239static void kvm_timer_init(void)
6240{
c285545f 6241 max_tsc_khz = tsc_khz;
460dd42e 6242
b820cc0c 6243 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 6244#ifdef CONFIG_CPU_FREQ
6245 struct cpufreq_policy policy;
758f588d
BP		 6246 int cpu;
6247
c285545f 6248 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 6249 cpu = get_cpu();
6250 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 6251 if (policy.cpuinfo.max_freq)
6252 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6253 put_cpu();
c285545f 6254#endif
b820cc0c
ZA		 6255 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6256 CPUFREQ_TRANSITION_NOTIFIER);
6257 }
c285545f 6258 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6259
73c1b41e 6260 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6261 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 6262}
6263
ff9d07a0
ZY		 6264static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6265
f5132b01 6266int kvm_is_in_guest(void)
ff9d07a0 6267{
086c9855 6268 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 6269}
6270
6271static int kvm_is_user_mode(void)
6272{
6273 int user_mode = 3;
dcf46b94 6274
086c9855
AS		 6275 if (__this_cpu_read(current_vcpu))
6276 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6277
ff9d07a0
ZY		 6278 return user_mode != 0;
6279}
6280
6281static unsigned long kvm_get_guest_ip(void)
6282{
6283 unsigned long ip = 0;
dcf46b94 6284
086c9855
AS		 6285 if (__this_cpu_read(current_vcpu))
6286 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6287
ff9d07a0
ZY		 6288 return ip;
6289}
6290
6291static struct perf_guest_info_callbacks kvm_guest_cbs = {
6292 .is_in_guest = kvm_is_in_guest,
6293 .is_user_mode = kvm_is_user_mode,
6294 .get_guest_ip = kvm_get_guest_ip,
6295};
6296
6297void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6298{
086c9855 6299 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 6300}
6301EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6302
6303void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6304{
086c9855 6305 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 6306}
6307EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6308
ce88decf
XG		 6309static void kvm_set_mmio_spte_mask(void)
6310{
6311 u64 mask;
6312 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6313
6314 /*
6315 * Set the reserved bits and the present bit of an paging-structure
6316 * entry to generate page fault with PFER.RSV = 1.
6317 */
885032b9 6318 /* Mask the reserved physical address bits. */
d1431483 6319 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6320
885032b9 6321 /* Set the present bit. */
ce88decf
XG		 6322 mask |= 1ull;
6323
6324#ifdef CONFIG_X86_64
6325 /*
6326 * If reserved bit is not supported, clear the present bit to disable
6327 * mmio page fault.
6328 */
6329 if (maxphyaddr == 52)
6330 mask &= ~1ull;
6331#endif
6332
dcdca5fe 6333 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG		 6334}
6335
16e8d74d
MT		 6336#ifdef CONFIG_X86_64
6337static void pvclock_gtod_update_fn(struct work_struct *work)
6338{
d828199e
MT		 6339 struct kvm *kvm;
6340
6341 struct kvm_vcpu *vcpu;
6342 int i;
6343
2f303b74 6344 spin_lock(&kvm_lock);
d828199e
MT		 6345 list_for_each_entry(kvm, &vm_list, vm_list)
6346 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6347 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6348 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6349 spin_unlock(&kvm_lock);
16e8d74d
MT		 6350}
6351
6352static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6353
6354/*
6355 * Notification about pvclock gtod data update.
6356 */
6357static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6358 void *priv)
6359{
6360 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6361 struct timekeeper *tk = priv;
6362
6363 update_pvclock_gtod(tk);
6364
6365 /* disable master clock if host does not trust, or does not
b0c39dc6 6366 * use, TSC based clocksource.
16e8d74d 6367 */
b0c39dc6 6368 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 6369 atomic_read(&kvm_guest_has_master_clock) != 0)
6370 queue_work(system_long_wq, &pvclock_gtod_work);
6371
6372 return 0;
6373}
6374
6375static struct notifier_block pvclock_gtod_notifier = {
6376 .notifier_call = pvclock_gtod_notify,
6377};
6378#endif
6379
f8c16bba 6380int kvm_arch_init(void *opaque)
043405e1 6381{
b820cc0c 6382 int r;
6b61edf7 6383 struct kvm_x86_ops *ops = opaque;
f8c16bba 6384
f8c16bba
ZX		 6385 if (kvm_x86_ops) {
6386 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6387 r = -EEXIST;
6388 goto out;
f8c16bba
ZX		 6389 }
6390
6391 if (!ops->cpu_has_kvm_support()) {
6392 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6393 r = -EOPNOTSUPP;
6394 goto out;
f8c16bba
ZX		 6395 }
6396 if (ops->disabled_by_bios()) {
6397 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6398 r = -EOPNOTSUPP;
6399 goto out;
f8c16bba
ZX		 6400 }
6401
013f6a5d
MT		 6402 r = -ENOMEM;
6403 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6404 if (!shared_msrs) {
6405 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6406 goto out;
6407 }
6408
97db56ce
AK		 6409 r = kvm_mmu_module_init();
6410 if (r)
013f6a5d 6411 goto out_free_percpu;
97db56ce 6412
ce88decf 6413 kvm_set_mmio_spte_mask();
97db56ce 6414
f8c16bba 6415 kvm_x86_ops = ops;
920c8377 6416
7b52345e 6417 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6418 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6419 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6420 kvm_timer_init();
c8076604 6421
ff9d07a0
ZY		 6422 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6423
d366bf7e 6424 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6425 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6426
c5cc421b 6427 kvm_lapic_init();
16e8d74d
MT		 6428#ifdef CONFIG_X86_64
6429 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 6430
5fa4ec9c 6431 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 6432 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 6433#endif
6434
f8c16bba 6435 return 0;
56c6d28a 6436
013f6a5d
MT		 6437out_free_percpu:
6438 free_percpu(shared_msrs);
56c6d28a 6439out:
56c6d28a 6440 return r;
043405e1 6441}
8776e519 6442
f8c16bba
ZX		 6443void kvm_arch_exit(void)
6444{
0092e434 6445#ifdef CONFIG_X86_64
5fa4ec9c 6446 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 6447 clear_hv_tscchange_cb();
6448#endif
cef84c30 6449 kvm_lapic_exit();
ff9d07a0
ZY		 6450 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6451
888d256e
JK		 6452 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6453 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6454 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6455 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6456#ifdef CONFIG_X86_64
6457 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6458#endif
f8c16bba 6459 kvm_x86_ops = NULL;
56c6d28a 6460 kvm_mmu_module_exit();
013f6a5d 6461 free_percpu(shared_msrs);
56c6d28a 6462}
f8c16bba 6463
5cb56059 6464int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6465{
6466 ++vcpu->stat.halt_exits;
35754c98 6467 if (lapic_in_kernel(vcpu)) {
a4535290 6468 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6469 return 1;
6470 } else {
6471 vcpu->run->exit_reason = KVM_EXIT_HLT;
6472 return 0;
6473 }
6474}
5cb56059
JS		 6475EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6476
6477int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6478{
6affcbed
KH		 6479 int ret = kvm_skip_emulated_instruction(vcpu);
6480 /*
6481 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6482 * KVM_EXIT_DEBUG here.
6483 */
6484 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6485}
8776e519
HB		 6486EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6487
8ef81a9a 6488#ifdef CONFIG_X86_64
55dd00a7
MT		 6489static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6490 unsigned long clock_type)
6491{
6492 struct kvm_clock_pairing clock_pairing;
6493 struct timespec ts;
80fbd89c 6494 u64 cycle;
55dd00a7
MT		 6495 int ret;
6496
6497 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6498 return -KVM_EOPNOTSUPP;
6499
6500 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6501 return -KVM_EOPNOTSUPP;
6502
6503 clock_pairing.sec = ts.tv_sec;
6504 clock_pairing.nsec = ts.tv_nsec;
6505 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6506 clock_pairing.flags = 0;
6507
6508 ret = 0;
6509 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6510 sizeof(struct kvm_clock_pairing)))
6511 ret = -KVM_EFAULT;
6512
6513 return ret;
6514}
8ef81a9a 6515#endif
55dd00a7 6516
6aef266c
SV		 6517/*
6518 * kvm_pv_kick_cpu_op: Kick a vcpu.
6519 *
6520 * @apicid - apicid of vcpu to be kicked.
6521 */
6522static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6523{
24d2166b 6524 struct kvm_lapic_irq lapic_irq;
6aef266c 6525
24d2166b
R		 6526 lapic_irq.shorthand = 0;
6527 lapic_irq.dest_mode = 0;
ebd28fcb 6528 lapic_irq.level = 0;
24d2166b 6529 lapic_irq.dest_id = apicid;
93bbf0b8 6530 lapic_irq.msi_redir_hint = false;
6aef266c 6531
24d2166b 6532 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6533 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6534}
6535
d62caabb
AS		 6536void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6537{
6538 vcpu->arch.apicv_active = false;
6539 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6540}
6541
8776e519
HB		 6542int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6543{
6544 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6545 int op_64_bit, r;
8776e519 6546
6affcbed 6547 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6548
55cd8e5a
GN		 6549 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6550 return kvm_hv_hypercall(vcpu);
6551
5fdbf976
MT		 6552 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6553 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6554 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6555 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6556 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6557
229456fc 6558 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6559
a449c7aa
NA		 6560 op_64_bit = is_64_bit_mode(vcpu);
6561 if (!op_64_bit) {
8776e519
HB		 6562 nr &= 0xFFFFFFFF;
6563 a0 &= 0xFFFFFFFF;
6564 a1 &= 0xFFFFFFFF;
6565 a2 &= 0xFFFFFFFF;
6566 a3 &= 0xFFFFFFFF;
6567 }
6568
07708c4a
JK		 6569 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6570 ret = -KVM_EPERM;
6571 goto out;
6572 }
6573
8776e519 6574 switch (nr) {
b93463aa
AK		 6575 case KVM_HC_VAPIC_POLL_IRQ:
6576 ret = 0;
6577 break;
6aef266c
SV		 6578 case KVM_HC_KICK_CPU:
6579 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6580 ret = 0;
6581 break;
8ef81a9a 6582#ifdef CONFIG_X86_64
55dd00a7
MT		 6583 case KVM_HC_CLOCK_PAIRING:
6584 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6585 break;
8ef81a9a 6586#endif
8776e519
HB		 6587 default:
6588 ret = -KVM_ENOSYS;
6589 break;
6590 }
07708c4a 6591out:
a449c7aa
NA		 6592 if (!op_64_bit)
6593 ret = (u32)ret;
5fdbf976 6594 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6595 ++vcpu->stat.hypercalls;
2f333bcb 6596 return r;
8776e519
HB		 6597}
6598EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6599
b6785def 6600static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6601{
d6aa1000 6602 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6603 char instruction[3];
5fdbf976 6604 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6605
8776e519 6606 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6607
ce2e852e
DV		 6608 return emulator_write_emulated(ctxt, rip, instruction, 3,
6609 &ctxt->exception);
8776e519
HB		 6610}
6611
851ba692 6612static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6613{
782d422b
MG		 6614 return vcpu->run->request_interrupt_window &&
6615 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6616}
6617
851ba692 6618static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6619{
851ba692
AK		 6620 struct kvm_run *kvm_run = vcpu->run;
6621
91586a3b 6622 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6623 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6624 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6625 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6626 kvm_run->ready_for_interrupt_injection =
6627 pic_in_kernel(vcpu->kvm) ||
782d422b 6628 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6629}
6630
95ba8273
GN		 6631static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6632{
6633 int max_irr, tpr;
6634
6635 if (!kvm_x86_ops->update_cr8_intercept)
6636 return;
6637
bce87cce 6638 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6639 return;
6640
d62caabb
AS		 6641 if (vcpu->arch.apicv_active)
6642 return;
6643
8db3baa2
GN		 6644 if (!vcpu->arch.apic->vapic_addr)
6645 max_irr = kvm_lapic_find_highest_irr(vcpu);
6646 else
6647 max_irr = -1;
95ba8273
GN		 6648
6649 if (max_irr != -1)
6650 max_irr >>= 4;
6651
6652 tpr = kvm_lapic_get_cr8(vcpu);
6653
6654 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6655}
6656
b6b8a145 6657static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6658{
b6b8a145
JK		 6659 int r;
6660
95ba8273 6661 /* try to reinject previous events if any */
664f8e26
WL		 6662 if (vcpu->arch.exception.injected) {
6663 kvm_x86_ops->queue_exception(vcpu);
6664 return 0;
6665 }
6666
6667 /*
6668 * Exceptions must be injected immediately, or the exception
6669 * frame will have the address of the NMI or interrupt handler.
6670 */
6671 if (!vcpu->arch.exception.pending) {
6672 if (vcpu->arch.nmi_injected) {
6673 kvm_x86_ops->set_nmi(vcpu);
6674 return 0;
6675 }
6676
6677 if (vcpu->arch.interrupt.pending) {
6678 kvm_x86_ops->set_irq(vcpu);
6679 return 0;
6680 }
6681 }
6682
6683 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6684 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6685 if (r != 0)
6686 return r;
6687 }
6688
6689 /* try to inject new event if pending */
b59bb7bd 6690 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6691 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6692 vcpu->arch.exception.has_error_code,
6693 vcpu->arch.exception.error_code);
d6e8c854 6694
664f8e26
WL		 6695 vcpu->arch.exception.pending = false;
6696 vcpu->arch.exception.injected = true;
6697
d6e8c854
NA		 6698 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6699 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6700 X86_EFLAGS_RF);
6701
6bdf0662
NA		 6702 if (vcpu->arch.exception.nr == DB_VECTOR &&
6703 (vcpu->arch.dr7 & DR7_GD)) {
6704 vcpu->arch.dr7 &= ~DR7_GD;
6705 kvm_update_dr7(vcpu);
6706 }
6707
cfcd20e5 6708 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6709 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6710 vcpu->arch.smi_pending = false;
52797bf9 6711 ++vcpu->arch.smi_count;
ee2cd4b7 6712 enter_smm(vcpu);
c43203ca 6713 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6714 --vcpu->arch.nmi_pending;
6715 vcpu->arch.nmi_injected = true;
6716 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6717 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6718 /*
6719 * Because interrupts can be injected asynchronously, we are
6720 * calling check_nested_events again here to avoid a race condition.
6721 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6722 * proposal and current concerns. Perhaps we should be setting
6723 * KVM_REQ_EVENT only on certain events and not unconditionally?
6724 */
6725 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6726 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6727 if (r != 0)
6728 return r;
6729 }
95ba8273 6730 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6731 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6732 false);
6733 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6734 }
6735 }
ee2cd4b7 6736
b6b8a145 6737 return 0;
95ba8273
GN		 6738}
6739
7460fb4a
AK		 6740static void process_nmi(struct kvm_vcpu *vcpu)
6741{
6742 unsigned limit = 2;
6743
6744 /*
6745 * x86 is limited to one NMI running, and one NMI pending after it.
6746 * If an NMI is already in progress, limit further NMIs to just one.
6747 * Otherwise, allow two (and we'll inject the first one immediately).
6748 */
6749 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6750 limit = 1;
6751
6752 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6753 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6754 kvm_make_request(KVM_REQ_EVENT, vcpu);
6755}
6756
ee2cd4b7 6757static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6758{
6759 u32 flags = 0;
6760 flags |= seg->g << 23;
6761 flags |= seg->db << 22;
6762 flags |= seg->l << 21;
6763 flags |= seg->avl << 20;
6764 flags |= seg->present << 15;
6765 flags |= seg->dpl << 13;
6766 flags |= seg->s << 12;
6767 flags |= seg->type << 8;
6768 return flags;
6769}
6770
ee2cd4b7 6771static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6772{
6773 struct kvm_segment seg;
6774 int offset;
6775
6776 kvm_get_segment(vcpu, &seg, n);
6777 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6778
6779 if (n < 3)
6780 offset = 0x7f84 + n * 12;
6781 else
6782 offset = 0x7f2c + (n - 3) * 12;
6783
6784 put_smstate(u32, buf, offset + 8, seg.base);
6785 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6786 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6787}
6788
efbb288a 6789#ifdef CONFIG_X86_64
ee2cd4b7 6790static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6791{
6792 struct kvm_segment seg;
6793 int offset;
6794 u16 flags;
6795
6796 kvm_get_segment(vcpu, &seg, n);
6797 offset = 0x7e00 + n * 16;
6798
ee2cd4b7 6799 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6800 put_smstate(u16, buf, offset, seg.selector);
6801 put_smstate(u16, buf, offset + 2, flags);
6802 put_smstate(u32, buf, offset + 4, seg.limit);
6803 put_smstate(u64, buf, offset + 8, seg.base);
6804}
efbb288a 6805#endif
660a5d51 6806
ee2cd4b7 6807static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6808{
6809 struct desc_ptr dt;
6810 struct kvm_segment seg;
6811 unsigned long val;
6812 int i;
6813
6814 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6815 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6816 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6817 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6818
6819 for (i = 0; i < 8; i++)
6820 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6821
6822 kvm_get_dr(vcpu, 6, &val);
6823 put_smstate(u32, buf, 0x7fcc, (u32)val);
6824 kvm_get_dr(vcpu, 7, &val);
6825 put_smstate(u32, buf, 0x7fc8, (u32)val);
6826
6827 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6828 put_smstate(u32, buf, 0x7fc4, seg.selector);
6829 put_smstate(u32, buf, 0x7f64, seg.base);
6830 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6831 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6832
6833 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6834 put_smstate(u32, buf, 0x7fc0, seg.selector);
6835 put_smstate(u32, buf, 0x7f80, seg.base);
6836 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6837 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6838
6839 kvm_x86_ops->get_gdt(vcpu, &dt);
6840 put_smstate(u32, buf, 0x7f74, dt.address);
6841 put_smstate(u32, buf, 0x7f70, dt.size);
6842
6843 kvm_x86_ops->get_idt(vcpu, &dt);
6844 put_smstate(u32, buf, 0x7f58, dt.address);
6845 put_smstate(u32, buf, 0x7f54, dt.size);
6846
6847 for (i = 0; i < 6; i++)
ee2cd4b7 6848 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6849
6850 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6851
6852 /* revision id */
6853 put_smstate(u32, buf, 0x7efc, 0x00020000);
6854 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6855}
6856
ee2cd4b7 6857static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6858{
6859#ifdef CONFIG_X86_64
6860 struct desc_ptr dt;
6861 struct kvm_segment seg;
6862 unsigned long val;
6863 int i;
6864
6865 for (i = 0; i < 16; i++)
6866 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6867
6868 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6869 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6870
6871 kvm_get_dr(vcpu, 6, &val);
6872 put_smstate(u64, buf, 0x7f68, val);
6873 kvm_get_dr(vcpu, 7, &val);
6874 put_smstate(u64, buf, 0x7f60, val);
6875
6876 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6877 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6878 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6879
6880 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6881
6882 /* revision id */
6883 put_smstate(u32, buf, 0x7efc, 0x00020064);
6884
6885 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6886
6887 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6888 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6889 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6890 put_smstate(u32, buf, 0x7e94, seg.limit);
6891 put_smstate(u64, buf, 0x7e98, seg.base);
6892
6893 kvm_x86_ops->get_idt(vcpu, &dt);
6894 put_smstate(u32, buf, 0x7e84, dt.size);
6895 put_smstate(u64, buf, 0x7e88, dt.address);
6896
6897 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6898 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6899 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6900 put_smstate(u32, buf, 0x7e74, seg.limit);
6901 put_smstate(u64, buf, 0x7e78, seg.base);
6902
6903 kvm_x86_ops->get_gdt(vcpu, &dt);
6904 put_smstate(u32, buf, 0x7e64, dt.size);
6905 put_smstate(u64, buf, 0x7e68, dt.address);
6906
6907 for (i = 0; i < 6; i++)
ee2cd4b7 6908 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6909#else
6910 WARN_ON_ONCE(1);
6911#endif
6912}
6913
ee2cd4b7 6914static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6915{
660a5d51 6916 struct kvm_segment cs, ds;
18c3626e 6917 struct desc_ptr dt;
660a5d51
PB		 6918 char buf[512];
6919 u32 cr0;
6920
660a5d51 6921 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6922 memset(buf, 0, 512);
d6321d49 6923 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6924 enter_smm_save_state_64(vcpu, buf);
660a5d51 6925 else
ee2cd4b7 6926 enter_smm_save_state_32(vcpu, buf);
660a5d51 6927
0234bf88
LP		 6928 /*
6929 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6930 * vCPU state (e.g. leave guest mode) after we've saved the state into
6931 * the SMM state-save area.
6932 */
6933 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6934
6935 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6936 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6937
6938 if (kvm_x86_ops->get_nmi_mask(vcpu))
6939 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6940 else
6941 kvm_x86_ops->set_nmi_mask(vcpu, true);
6942
6943 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6944 kvm_rip_write(vcpu, 0x8000);
6945
6946 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6947 kvm_x86_ops->set_cr0(vcpu, cr0);
6948 vcpu->arch.cr0 = cr0;
6949
6950 kvm_x86_ops->set_cr4(vcpu, 0);
6951
18c3626e
PB		 6952 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6953 dt.address = dt.size = 0;
6954 kvm_x86_ops->set_idt(vcpu, &dt);
6955
660a5d51
PB		 6956 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6957
6958 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6959 cs.base = vcpu->arch.smbase;
6960
6961 ds.selector = 0;
6962 ds.base = 0;
6963
6964 cs.limit = ds.limit = 0xffffffff;
6965 cs.type = ds.type = 0x3;
6966 cs.dpl = ds.dpl = 0;
6967 cs.db = ds.db = 0;
6968 cs.s = ds.s = 1;
6969 cs.l = ds.l = 0;
6970 cs.g = ds.g = 1;
6971 cs.avl = ds.avl = 0;
6972 cs.present = ds.present = 1;
6973 cs.unusable = ds.unusable = 0;
6974 cs.padding = ds.padding = 0;
6975
6976 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6977 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6978 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6979 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6980 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6981 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6982
d6321d49 6983 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB		 6984 kvm_x86_ops->set_efer(vcpu, 0);
6985
6986 kvm_update_cpuid(vcpu);
6987 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6988}
6989
ee2cd4b7 6990static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6991{
6992 vcpu->arch.smi_pending = true;
6993 kvm_make_request(KVM_REQ_EVENT, vcpu);
6994}
6995
2860c4b1
PB		 6996void kvm_make_scan_ioapic_request(struct kvm *kvm)
6997{
6998 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6999}
7000
3d81bc7e 7001static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 7002{
5c919412
AS		 7003 u64 eoi_exit_bitmap[4];
7004
3d81bc7e
YZ		 7005 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
7006 return;
c7c9c56c 7007
6308630b 7008 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 7009
b053b2ae 7010 if (irqchip_split(vcpu->kvm))
6308630b 7011 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7012 else {
fa59cc00 7013 if (vcpu->arch.apicv_active)
d62caabb 7014 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 7015 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 7016 }
5c919412
AS		 7017 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
7018 vcpu_to_synic(vcpu)->vec_bitmap, 256);
7019 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 7020}
7021
b1394e74
RK		 7022void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
7023 unsigned long start, unsigned long end)
7024{
7025 unsigned long apic_address;
7026
7027 /*
7028 * The physical address of apic access page is stored in the VMCS.
7029 * Update it when it becomes invalid.
7030 */
7031 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
7032 if (start <= apic_address && apic_address < end)
7033 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
7034}
7035
4256f43f
TC		 7036void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
7037{
c24ae0dc
TC		 7038 struct page *page = NULL;
7039
35754c98 7040 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 7041 return;
7042
4256f43f
TC		 7043 if (!kvm_x86_ops->set_apic_access_page_addr)
7044 return;
7045
c24ae0dc 7046 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 7047 if (is_error_page(page))
7048 return;
c24ae0dc
TC		 7049 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
7050
7051 /*
7052 * Do not pin apic access page in memory, the MMU notifier
7053 * will call us again if it is migrated or swapped out.
7054 */
7055 put_page(page);
4256f43f
TC		 7056}
7057EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
7058
9357d939 7059/*
362c698f 7060 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 7061 * exiting to the userspace. Otherwise, the value will be returned to the
7062 * userspace.
7063 */
851ba692 7064static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 7065{
7066 int r;
62a193ed
MG		 7067 bool req_int_win =
7068 dm_request_for_irq_injection(vcpu) &&
7069 kvm_cpu_accept_dm_intr(vcpu);
7070
730dca42 7071 bool req_immediate_exit = false;
b6c7a5dc 7072
2fa6e1e1 7073 if (kvm_request_pending(vcpu)) {
a8eeb04a 7074 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 7075 kvm_mmu_unload(vcpu);
a8eeb04a 7076 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 7077 __kvm_migrate_timers(vcpu);
d828199e
MT		 7078 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
7079 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 7080 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
7081 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 7082 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
7083 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 7084 if (unlikely(r))
7085 goto out;
7086 }
a8eeb04a 7087 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 7088 kvm_mmu_sync_roots(vcpu);
a8eeb04a 7089 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 7090 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 7091 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 7092 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 7093 r = 0;
7094 goto out;
7095 }
a8eeb04a 7096 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 7097 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 7098 vcpu->mmio_needed = 0;
71c4dfaf
JR		 7099 r = 0;
7100 goto out;
7101 }
af585b92
GN		 7102 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
7103 /* Page is swapped out. Do synthetic halt */
7104 vcpu->arch.apf.halted = true;
7105 r = 1;
7106 goto out;
7107 }
c9aaa895
GC		 7108 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
7109 record_steal_time(vcpu);
64d60670
PB		 7110 if (kvm_check_request(KVM_REQ_SMI, vcpu))
7111 process_smi(vcpu);
7460fb4a
AK		 7112 if (kvm_check_request(KVM_REQ_NMI, vcpu))
7113 process_nmi(vcpu);
f5132b01 7114 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 7115 kvm_pmu_handle_event(vcpu);
f5132b01 7116 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 7117 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 7118 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
7119 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
7120 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 7121 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 7122 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
7123 vcpu->run->eoi.vector =
7124 vcpu->arch.pending_ioapic_eoi;
7125 r = 0;
7126 goto out;
7127 }
7128 }
3d81bc7e
YZ		 7129 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
7130 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 7131 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
7132 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 7133 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
7134 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7135 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
7136 r = 0;
7137 goto out;
7138 }
e516cebb
AS		 7139 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
7140 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
7141 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
7142 r = 0;
7143 goto out;
7144 }
db397571
AS		 7145 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
7146 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
7147 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
7148 r = 0;
7149 goto out;
7150 }
f3b138c5
AS		 7151
7152 /*
7153 * KVM_REQ_HV_STIMER has to be processed after
7154 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
7155 * depend on the guest clock being up-to-date
7156 */
1f4b34f8
AS		 7157 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
7158 kvm_hv_process_stimers(vcpu);
2f52d58c 7159 }
b93463aa 7160
b463a6f7 7161 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7162 ++vcpu->stat.req_event;
66450a21
JK		 7163 kvm_apic_accept_events(vcpu);
7164 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7165 r = 1;
7166 goto out;
7167 }
7168
b6b8a145
JK		 7169 if (inject_pending_event(vcpu, req_int_win) != 0)
7170 req_immediate_exit = true;
321c5658 7171 else {
cc3d967f 7172 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7173 *
cc3d967f
LP		 7174 * SMIs have three cases:
7175 * 1) They can be nested, and then there is nothing to
7176 * do here because RSM will cause a vmexit anyway.
7177 * 2) There is an ISA-specific reason why SMI cannot be
7178 * injected, and the moment when this changes can be
7179 * intercepted.
7180 * 3) Or the SMI can be pending because
7181 * inject_pending_event has completed the injection
7182 * of an IRQ or NMI from the previous vmexit, and
7183 * then we request an immediate exit to inject the
7184 * SMI.
c43203ca
PB		 7185 */
7186 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 7187 if (!kvm_x86_ops->enable_smi_window(vcpu))
7188 req_immediate_exit = true;
321c5658
YS		 7189 if (vcpu->arch.nmi_pending)
7190 kvm_x86_ops->enable_nmi_window(vcpu);
7191 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7192 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7193 WARN_ON(vcpu->arch.exception.pending);
321c5658 7194 }
b463a6f7
AK		 7195
7196 if (kvm_lapic_enabled(vcpu)) {
7197 update_cr8_intercept(vcpu);
7198 kvm_lapic_sync_to_vapic(vcpu);
7199 }
7200 }
7201
d8368af8
AK		 7202 r = kvm_mmu_reload(vcpu);
7203 if (unlikely(r)) {
d905c069 7204 goto cancel_injection;
d8368af8
AK		 7205 }
7206
b6c7a5dc
HB		 7207 preempt_disable();
7208
7209 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 7210
7211 /*
7212 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7213 * IPI are then delayed after guest entry, which ensures that they
7214 * result in virtual interrupt delivery.
7215 */
7216 local_irq_disable();
6b7e2d09
XG		 7217 vcpu->mode = IN_GUEST_MODE;
7218
01b71917
MT		 7219 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7220
0f127d12 7221 /*
b95234c8 7222 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7223 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB		 7224 *
7225 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7226 * pairs with the memory barrier implicit in pi_test_and_set_on
7227 * (see vmx_deliver_posted_interrupt).
7228 *
7229 * 3) This also orders the write to mode from any reads to the page
7230 * tables done while the VCPU is running. Please see the comment
7231 * in kvm_flush_remote_tlbs.
6b7e2d09 7232 */
01b71917 7233 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7234
b95234c8
PB		 7235 /*
7236 * This handles the case where a posted interrupt was
7237 * notified with kvm_vcpu_kick.
7238 */
fa59cc00
LA		 7239 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
7240 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 7241
2fa6e1e1 7242 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7243 || need_resched() || signal_pending(current)) {
6b7e2d09 7244 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7245 smp_wmb();
6c142801
AK		 7246 local_irq_enable();
7247 preempt_enable();
01b71917 7248 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7249 r = 1;
d905c069 7250 goto cancel_injection;
6c142801
AK		 7251 }
7252
fc5b7f3b
DM		 7253 kvm_load_guest_xcr0(vcpu);
7254
c43203ca
PB		 7255 if (req_immediate_exit) {
7256 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7257 smp_send_reschedule(vcpu->cpu);
c43203ca 7258 }
d6185f20 7259
8b89fe1f 7260 trace_kvm_entry(vcpu->vcpu_id);
9c48d517
WL		 7261 if (lapic_timer_advance_ns)
7262 wait_lapic_expire(vcpu);
6edaa530 7263 guest_enter_irqoff();
b6c7a5dc 7264
42dbaa5a 7265 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 7266 set_debugreg(0, 7);
7267 set_debugreg(vcpu->arch.eff_db[0], 0);
7268 set_debugreg(vcpu->arch.eff_db[1], 1);
7269 set_debugreg(vcpu->arch.eff_db[2], 2);
7270 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7271 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7272 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7273 }
b6c7a5dc 7274
851ba692 7275 kvm_x86_ops->run(vcpu);
b6c7a5dc 7276
c77fb5fe
PB		 7277 /*
7278 * Do this here before restoring debug registers on the host. And
7279 * since we do this before handling the vmexit, a DR access vmexit
7280 * can (a) read the correct value of the debug registers, (b) set
7281 * KVM_DEBUGREG_WONT_EXIT again.
7282 */
7283 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 7284 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7285 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 7286 kvm_update_dr0123(vcpu);
7287 kvm_update_dr6(vcpu);
7288 kvm_update_dr7(vcpu);
7289 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 7290 }
7291
24f1e32c
FW		 7292 /*
7293 * If the guest has used debug registers, at least dr7
7294 * will be disabled while returning to the host.
7295 * If we don't have active breakpoints in the host, we don't
7296 * care about the messed up debug address registers. But if
7297 * we have some of them active, restore the old state.
7298 */
59d8eb53 7299 if (hw_breakpoint_active())
24f1e32c 7300 hw_breakpoint_restore();
42dbaa5a 7301
4ba76538 7302 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7303
6b7e2d09 7304 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7305 smp_wmb();
a547c6db 7306
fc5b7f3b
DM		 7307 kvm_put_guest_xcr0(vcpu);
7308
a547c6db 7309 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 7310
7311 ++vcpu->stat.exits;
7312
f2485b3e 7313 guest_exit_irqoff();
b6c7a5dc 7314
f2485b3e 7315 local_irq_enable();
b6c7a5dc
HB		 7316 preempt_enable();
7317
f656ce01 7318 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7319
b6c7a5dc
HB		 7320 /*
7321 * Profile KVM exit RIPs:
7322 */
7323 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 7324 unsigned long rip = kvm_rip_read(vcpu);
7325 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 7326 }
7327
cc578287
ZA		 7328 if (unlikely(vcpu->arch.tsc_always_catchup))
7329 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7330
5cfb1d5a
MT		 7331 if (vcpu->arch.apic_attention)
7332 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7333
618232e2 7334 vcpu->arch.gpa_available = false;
851ba692 7335 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 7336 return r;
7337
7338cancel_injection:
7339 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 7340 if (unlikely(vcpu->arch.apic_attention))
7341 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 7342out:
7343 return r;
7344}
b6c7a5dc 7345
362c698f
PB		 7346static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7347{
bf9f6ac8
FW		 7348 if (!kvm_arch_vcpu_runnable(vcpu) &&
7349 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 7350 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7351 kvm_vcpu_block(vcpu);
7352 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 7353
7354 if (kvm_x86_ops->post_block)
7355 kvm_x86_ops->post_block(vcpu);
7356
9c8fd1ba
PB		 7357 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7358 return 1;
7359 }
362c698f
PB		 7360
7361 kvm_apic_accept_events(vcpu);
7362 switch(vcpu->arch.mp_state) {
7363 case KVM_MP_STATE_HALTED:
7364 vcpu->arch.pv.pv_unhalted = false;
7365 vcpu->arch.mp_state =
7366 KVM_MP_STATE_RUNNABLE;
7367 case KVM_MP_STATE_RUNNABLE:
7368 vcpu->arch.apf.halted = false;
7369 break;
7370 case KVM_MP_STATE_INIT_RECEIVED:
7371 break;
7372 default:
7373 return -EINTR;
7374 break;
7375 }
7376 return 1;
7377}
09cec754 7378
5d9bc648
PB		 7379static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7380{
0ad3bed6
PB		 7381 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7382 kvm_x86_ops->check_nested_events(vcpu, false);
7383
5d9bc648
PB		 7384 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7385 !vcpu->arch.apf.halted);
7386}
7387
362c698f 7388static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7389{
7390 int r;
f656ce01 7391 struct kvm *kvm = vcpu->kvm;
d7690175 7392
f656ce01 7393 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7394
362c698f 7395 for (;;) {
58f800d5 7396 if (kvm_vcpu_running(vcpu)) {
851ba692 7397 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7398 } else {
362c698f 7399 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7400 }
7401
09cec754
GN		 7402 if (r <= 0)
7403 break;
7404
72875d8a 7405 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 7406 if (kvm_cpu_has_pending_timer(vcpu))
7407 kvm_inject_pending_timer_irqs(vcpu);
7408
782d422b
MG		 7409 if (dm_request_for_irq_injection(vcpu) &&
7410 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7411 r = 0;
7412 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7413 ++vcpu->stat.request_irq_exits;
362c698f 7414 break;
09cec754 7415 }
af585b92
GN		 7416
7417 kvm_check_async_pf_completion(vcpu);
7418
09cec754
GN		 7419 if (signal_pending(current)) {
7420 r = -EINTR;
851ba692 7421 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7422 ++vcpu->stat.signal_exits;
362c698f 7423 break;
09cec754
GN		 7424 }
7425 if (need_resched()) {
f656ce01 7426 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7427 cond_resched();
f656ce01 7428 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7429 }
b6c7a5dc
HB		 7430 }
7431
f656ce01 7432 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7433
7434 return r;
7435}
7436
716d51ab
GN		 7437static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7438{
7439 int r;
7440 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7441 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7442 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7443 if (r != EMULATE_DONE)
7444 return 0;
7445 return 1;
7446}
7447
7448static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7449{
7450 BUG_ON(!vcpu->arch.pio.count);
7451
7452 return complete_emulated_io(vcpu);
7453}
7454
f78146b0
AK		 7455/*
7456 * Implements the following, as a state machine:
7457 *
7458 * read:
7459 * for each fragment
87da7e66
XG		 7460 * for each mmio piece in the fragment
7461 * write gpa, len
7462 * exit
7463 * copy data
f78146b0
AK		 7464 * execute insn
7465 *
7466 * write:
7467 * for each fragment
87da7e66
XG		 7468 * for each mmio piece in the fragment
7469 * write gpa, len
7470 * copy data
7471 * exit
f78146b0 7472 */
716d51ab 7473static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7474{
7475 struct kvm_run *run = vcpu->run;
f78146b0 7476 struct kvm_mmio_fragment *frag;
87da7e66 7477 unsigned len;
5287f194 7478
716d51ab 7479 BUG_ON(!vcpu->mmio_needed);
5287f194 7480
716d51ab 7481 /* Complete previous fragment */
87da7e66
XG		 7482 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7483 len = min(8u, frag->len);
716d51ab 7484 if (!vcpu->mmio_is_write)
87da7e66
XG		 7485 memcpy(frag->data, run->mmio.data, len);
7486
7487 if (frag->len <= 8) {
7488 /* Switch to the next fragment. */
7489 frag++;
7490 vcpu->mmio_cur_fragment++;
7491 } else {
7492 /* Go forward to the next mmio piece. */
7493 frag->data += len;
7494 frag->gpa += len;
7495 frag->len -= len;
7496 }
7497
a08d3b3b 7498 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7499 vcpu->mmio_needed = 0;
0912c977
PB		 7500
7501 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7502 if (vcpu->mmio_is_write)
716d51ab
GN		 7503 return 1;
7504 vcpu->mmio_read_completed = 1;
7505 return complete_emulated_io(vcpu);
7506 }
87da7e66 7507
716d51ab
GN		 7508 run->exit_reason = KVM_EXIT_MMIO;
7509 run->mmio.phys_addr = frag->gpa;
7510 if (vcpu->mmio_is_write)
87da7e66
XG		 7511 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7512 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7513 run->mmio.is_write = vcpu->mmio_is_write;
7514 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7515 return 0;
5287f194
AK		 7516}
7517
b6c7a5dc
HB		 7518int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7519{
7520 int r;
b6c7a5dc 7521
accb757d 7522 vcpu_load(vcpu);
20b7035c 7523 kvm_sigset_activate(vcpu);
5663d8f9
PX		 7524 kvm_load_guest_fpu(vcpu);
7525
a4535290 7526 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 7527 if (kvm_run->immediate_exit) {
7528 r = -EINTR;
7529 goto out;
7530 }
b6c7a5dc 7531 kvm_vcpu_block(vcpu);
66450a21 7532 kvm_apic_accept_events(vcpu);
72875d8a 7533 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7534 r = -EAGAIN;
a0595000
JS		 7535 if (signal_pending(current)) {
7536 r = -EINTR;
7537 vcpu->run->exit_reason = KVM_EXIT_INTR;
7538 ++vcpu->stat.signal_exits;
7539 }
ac9f6dc0 7540 goto out;
b6c7a5dc
HB		 7541 }
7542
01643c51
KH		 7543 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
7544 r = -EINVAL;
7545 goto out;
7546 }
7547
7548 if (vcpu->run->kvm_dirty_regs) {
7549 r = sync_regs(vcpu);
7550 if (r != 0)
7551 goto out;
7552 }
7553
b6c7a5dc 7554 /* re-sync apic's tpr */
35754c98 7555 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7556 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7557 r = -EINVAL;
7558 goto out;
7559 }
7560 }
b6c7a5dc 7561
716d51ab
GN		 7562 if (unlikely(vcpu->arch.complete_userspace_io)) {
7563 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7564 vcpu->arch.complete_userspace_io = NULL;
7565 r = cui(vcpu);
7566 if (r <= 0)
5663d8f9 7567 goto out;
716d51ab
GN		 7568 } else
7569 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7570
460df4c1
PB		 7571 if (kvm_run->immediate_exit)
7572 r = -EINTR;
7573 else
7574 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7575
7576out:
5663d8f9 7577 kvm_put_guest_fpu(vcpu);
01643c51
KH		 7578 if (vcpu->run->kvm_valid_regs)
7579 store_regs(vcpu);
f1d86e46 7580 post_kvm_run_save(vcpu);
20b7035c 7581 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7582
accb757d 7583 vcpu_put(vcpu);
b6c7a5dc
HB		 7584 return r;
7585}
7586
01643c51 7587static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7588{
7ae441ea
GN		 7589 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7590 /*
7591 * We are here if userspace calls get_regs() in the middle of
7592 * instruction emulation. Registers state needs to be copied
4a969980 7593 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7594 * that usually, but some bad designed PV devices (vmware
7595 * backdoor interface) need this to work
7596 */
dd856efa 7597 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7598 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7599 }
5fdbf976
MT		 7600 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7601 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7602 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7603 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7604 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7605 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7606 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7607 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7608#ifdef CONFIG_X86_64
5fdbf976
MT		 7609 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7610 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7611 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7612 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7613 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7614 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7615 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7616 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7617#endif
7618
5fdbf976 7619 regs->rip = kvm_rip_read(vcpu);
91586a3b 7620 regs->rflags = kvm_get_rflags(vcpu);
01643c51 7621}
b6c7a5dc 7622
01643c51
KH		 7623int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7624{
7625 vcpu_load(vcpu);
7626 __get_regs(vcpu, regs);
1fc9b76b 7627 vcpu_put(vcpu);
b6c7a5dc
HB		 7628 return 0;
7629}
7630
01643c51 7631static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 7632{
7ae441ea
GN		 7633 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7634 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7635
5fdbf976
MT		 7636 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7637 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7638 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7639 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7640 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7641 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7642 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7643 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7644#ifdef CONFIG_X86_64
5fdbf976
MT		 7645 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7646 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7647 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7648 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7649 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7650 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7651 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7652 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7653#endif
7654
5fdbf976 7655 kvm_rip_write(vcpu, regs->rip);
d73235d1 7656 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7657
b4f14abd
JK		 7658 vcpu->arch.exception.pending = false;
7659
3842d135 7660 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 7661}
3842d135 7662
01643c51
KH		 7663int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7664{
7665 vcpu_load(vcpu);
7666 __set_regs(vcpu, regs);
875656fe 7667 vcpu_put(vcpu);
b6c7a5dc
HB		 7668 return 0;
7669}
7670
b6c7a5dc
HB		 7671void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7672{
7673 struct kvm_segment cs;
7674
3e6e0aab 7675 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7676 *db = cs.db;
7677 *l = cs.l;
7678}
7679EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7680
01643c51 7681static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7682{
89a27f4d 7683 struct desc_ptr dt;
b6c7a5dc 7684
3e6e0aab
GT		 7685 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7686 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7687 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7688 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7689 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7690 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7691
3e6e0aab
GT		 7692 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7693 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7694
7695 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7696 sregs->idt.limit = dt.size;
7697 sregs->idt.base = dt.address;
b6c7a5dc 7698 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7699 sregs->gdt.limit = dt.size;
7700 sregs->gdt.base = dt.address;
b6c7a5dc 7701
4d4ec087 7702 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7703 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7704 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7705 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7706 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7707 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7708 sregs->apic_base = kvm_get_apic_base(vcpu);
7709
923c61bb 7710 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7711
36752c9b 7712 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7713 set_bit(vcpu->arch.interrupt.nr,
7714 (unsigned long *)sregs->interrupt_bitmap);
01643c51 7715}
16d7a191 7716
01643c51
KH		 7717int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7718 struct kvm_sregs *sregs)
7719{
7720 vcpu_load(vcpu);
7721 __get_sregs(vcpu, sregs);
bcdec41c 7722 vcpu_put(vcpu);
b6c7a5dc
HB		 7723 return 0;
7724}
7725
62d9f0db
MT		 7726int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7727 struct kvm_mp_state *mp_state)
7728{
fd232561
CD		 7729 vcpu_load(vcpu);
7730
66450a21 7731 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7732 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7733 vcpu->arch.pv.pv_unhalted)
7734 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7735 else
7736 mp_state->mp_state = vcpu->arch.mp_state;
7737
fd232561 7738 vcpu_put(vcpu);
62d9f0db
MT		 7739 return 0;
7740}
7741
7742int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7743 struct kvm_mp_state *mp_state)
7744{
e83dff5e
CD		 7745 int ret = -EINVAL;
7746
7747 vcpu_load(vcpu);
7748
bce87cce 7749 if (!lapic_in_kernel(vcpu) &&
66450a21 7750 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 7751 goto out;
66450a21 7752
28bf2888
DH		 7753 /* INITs are latched while in SMM */
7754 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7755 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7756 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 7757 goto out;
28bf2888 7758
66450a21
JK		 7759 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7760 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7761 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7762 } else
7763 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7764 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 7765
7766 ret = 0;
7767out:
7768 vcpu_put(vcpu);
7769 return ret;
62d9f0db
MT		 7770}
7771
7f3d35fd
KW		 7772int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7773 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7774{
9d74191a 7775 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7776 int ret;
e01c2426 7777
8ec4722d 7778 init_emulate_ctxt(vcpu);
c697518a 7779
7f3d35fd 7780 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7781 has_error_code, error_code);
c697518a 7782
c697518a 7783 if (ret)
19d04437 7784 return EMULATE_FAIL;
37817f29 7785
9d74191a
TY		 7786 kvm_rip_write(vcpu, ctxt->eip);
7787 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7788 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7789 return EMULATE_DONE;
37817f29
IE		 7790}
7791EXPORT_SYMBOL_GPL(kvm_task_switch);
7792
f2981033
LT		 7793int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7794{
37b95951 7795 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 7796 /*
7797 * When EFER.LME and CR0.PG are set, the processor is in
7798 * 64-bit mode (though maybe in a 32-bit code segment).
7799 * CR4.PAE and EFER.LMA must be set.
7800 */
37b95951 7801 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 7802 || !(sregs->efer & EFER_LMA))
7803 return -EINVAL;
7804 } else {
7805 /*
7806 * Not in 64-bit mode: EFER.LMA is clear and the code
7807 * segment cannot be 64-bit.
7808 */
7809 if (sregs->efer & EFER_LMA || sregs->cs.l)
7810 return -EINVAL;
7811 }
7812
7813 return 0;
7814}
7815
01643c51 7816static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 7817{
58cb628d 7818 struct msr_data apic_base_msr;
b6c7a5dc 7819 int mmu_reset_needed = 0;
63f42e02 7820 int pending_vec, max_bits, idx;
89a27f4d 7821 struct desc_ptr dt;
b4ef9d4e
CD		 7822 int ret = -EINVAL;
7823
d6321d49
RK		 7824 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7825 (sregs->cr4 & X86_CR4_OSXSAVE))
b4ef9d4e 7826 goto out;
6d1068b3 7827
f2981033 7828 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 7829 goto out;
f2981033 7830
d3802286
JM		 7831 apic_base_msr.data = sregs->apic_base;
7832 apic_base_msr.host_initiated = true;
7833 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 7834 goto out;
6d1068b3 7835
89a27f4d
GN		 7836 dt.size = sregs->idt.limit;
7837 dt.address = sregs->idt.base;
b6c7a5dc 7838 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7839 dt.size = sregs->gdt.limit;
7840 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7841 kvm_x86_ops->set_gdt(vcpu, &dt);
7842
ad312c7c 7843 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7844 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7845 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7846 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7847
2d3ad1f4 7848 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7849
f6801dff 7850 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7851 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7852
4d4ec087 7853 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7854 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7855 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7856
fc78f519 7857 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7858 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7859 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7860 kvm_update_cpuid(vcpu);
63f42e02
XG		 7861
7862 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7863 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7864 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7865 mmu_reset_needed = 1;
7866 }
63f42e02 7867 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7868
7869 if (mmu_reset_needed)
7870 kvm_mmu_reset_context(vcpu);
7871
a50abc3b 7872 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7873 pending_vec = find_first_bit(
7874 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7875 if (pending_vec < max_bits) {
66fd3f7f 7876 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7877 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7878 }
7879
3e6e0aab
GT		 7880 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7881 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7882 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7883 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7884 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7885 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7886
3e6e0aab
GT		 7887 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7888 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7889
5f0269f5
ME		 7890 update_cr8_intercept(vcpu);
7891
9c3e4aab 7892 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7893 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7894 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7895 !is_protmode(vcpu))
9c3e4aab
MT		 7896 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7897
3842d135
AK		 7898 kvm_make_request(KVM_REQ_EVENT, vcpu);
7899
b4ef9d4e
CD		 7900 ret = 0;
7901out:
01643c51
KH		 7902 return ret;
7903}
7904
7905int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7906 struct kvm_sregs *sregs)
7907{
7908 int ret;
7909
7910 vcpu_load(vcpu);
7911 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 7912 vcpu_put(vcpu);
7913 return ret;
b6c7a5dc
HB		 7914}
7915
d0bfb940
JK		 7916int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7917 struct kvm_guest_debug *dbg)
b6c7a5dc 7918{
355be0b9 7919 unsigned long rflags;
ae675ef0 7920 int i, r;
b6c7a5dc 7921
66b56562
CD		 7922 vcpu_load(vcpu);
7923
4f926bf2
JK		 7924 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7925 r = -EBUSY;
7926 if (vcpu->arch.exception.pending)
2122ff5e 7927 goto out;
4f926bf2
JK		 7928 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7929 kvm_queue_exception(vcpu, DB_VECTOR);
7930 else
7931 kvm_queue_exception(vcpu, BP_VECTOR);
7932 }
7933
91586a3b
JK		 7934 /*
7935 * Read rflags as long as potentially injected trace flags are still
7936 * filtered out.
7937 */
7938 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7939
7940 vcpu->guest_debug = dbg->control;
7941 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7942 vcpu->guest_debug = 0;
7943
7944 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7945 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7946 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7947 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7948 } else {
7949 for (i = 0; i < KVM_NR_DB_REGS; i++)
7950 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7951 }
c8639010 7952 kvm_update_dr7(vcpu);
ae675ef0 7953
f92653ee
JK		 7954 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7955 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7956 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7957
91586a3b
JK		 7958 /*
7959 * Trigger an rflags update that will inject or remove the trace
7960 * flags.
7961 */
7962 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7963
a96036b8 7964 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7965
4f926bf2 7966 r = 0;
d0bfb940 7967
2122ff5e 7968out:
66b56562 7969 vcpu_put(vcpu);
b6c7a5dc
HB		 7970 return r;
7971}
7972
8b006791
ZX		 7973/*
7974 * Translate a guest virtual address to a guest physical address.
7975 */
7976int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7977 struct kvm_translation *tr)
7978{
7979 unsigned long vaddr = tr->linear_address;
7980 gpa_t gpa;
f656ce01 7981 int idx;
8b006791 7982
1da5b61d
CD		 7983 vcpu_load(vcpu);
7984
f656ce01 7985 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7986 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7987 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7988 tr->physical_address = gpa;
7989 tr->valid = gpa != UNMAPPED_GVA;
7990 tr->writeable = 1;
7991 tr->usermode = 0;
8b006791 7992
1da5b61d 7993 vcpu_put(vcpu);
8b006791
ZX		 7994 return 0;
7995}
7996
d0752060
HB		 7997int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7998{
1393123e 7999 struct fxregs_state *fxsave;
d0752060 8000
1393123e 8001 vcpu_load(vcpu);
d0752060 8002
1393123e 8003 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060
HB		 8004 memcpy(fpu->fpr, fxsave->st_space, 128);
8005 fpu->fcw = fxsave->cwd;
8006 fpu->fsw = fxsave->swd;
8007 fpu->ftwx = fxsave->twd;
8008 fpu->last_opcode = fxsave->fop;
8009 fpu->last_ip = fxsave->rip;
8010 fpu->last_dp = fxsave->rdp;
8011 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
8012
1393123e 8013 vcpu_put(vcpu);
d0752060
HB		 8014 return 0;
8015}
8016
8017int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
8018{
6a96bc7f
CD		 8019 struct fxregs_state *fxsave;
8020
8021 vcpu_load(vcpu);
8022
8023 fxsave = &vcpu->arch.guest_fpu.state.fxsave;
d0752060 8024
d0752060
HB		 8025 memcpy(fxsave->st_space, fpu->fpr, 128);
8026 fxsave->cwd = fpu->fcw;
8027 fxsave->swd = fpu->fsw;
8028 fxsave->twd = fpu->ftwx;
8029 fxsave->fop = fpu->last_opcode;
8030 fxsave->rip = fpu->last_ip;
8031 fxsave->rdp = fpu->last_dp;
8032 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
8033
6a96bc7f 8034 vcpu_put(vcpu);
d0752060
HB		 8035 return 0;
8036}
8037
01643c51
KH		 8038static void store_regs(struct kvm_vcpu *vcpu)
8039{
8040 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
8041
8042 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
8043 __get_regs(vcpu, &vcpu->run->s.regs.regs);
8044
8045 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
8046 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
8047
8048 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
8049 kvm_vcpu_ioctl_x86_get_vcpu_events(
8050 vcpu, &vcpu->run->s.regs.events);
8051}
8052
8053static int sync_regs(struct kvm_vcpu *vcpu)
8054{
8055 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
8056 return -EINVAL;
8057
8058 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
8059 __set_regs(vcpu, &vcpu->run->s.regs.regs);
8060 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
8061 }
8062 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
8063 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
8064 return -EINVAL;
8065 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
8066 }
8067 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
8068 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
8069 vcpu, &vcpu->run->s.regs.events))
8070 return -EINVAL;
8071 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
8072 }
8073
8074 return 0;
8075}
8076
0ee6a517 8077static void fx_init(struct kvm_vcpu *vcpu)
d0752060 8078{
bf935b0b 8079 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 8080 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 8081 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 8082 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 8083
2acf923e
DC		 8084 /*
8085 * Ensure guest xcr0 is valid for loading
8086 */
d91cab78 8087 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 8088
ad312c7c 8089 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 8090}
d0752060 8091
f775b13e 8092/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB		 8093void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8094{
f775b13e
RR		 8095 preempt_disable();
8096 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB		 8097 /* PKRU is separately restored in kvm_x86_ops->run. */
8098 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
8099 ~XFEATURE_MASK_PKRU);
f775b13e 8100 preempt_enable();
0c04851c 8101 trace_kvm_fpu(1);
d0752060 8102}
d0752060 8103
f775b13e 8104/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB		 8105void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8106{
f775b13e 8107 preempt_disable();
4f836347 8108 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR		 8109 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
8110 preempt_enable();
f096ed85 8111 ++vcpu->stat.fpu_reload;
0c04851c 8112 trace_kvm_fpu(0);
d0752060 8113}
e9b11c17
ZX		 8114
8115void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
8116{
bd768e14
IY		 8117 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
8118
12f9a48f 8119 kvmclock_reset(vcpu);
7f1ea208 8120
e9b11c17 8121 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 8122 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 8123}
8124
8125struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
8126 unsigned int id)
8127{
c447e76b
LL		 8128 struct kvm_vcpu *vcpu;
8129
b0c39dc6 8130 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6755bae8
ZA		 8131 printk_once(KERN_WARNING
8132 "kvm: SMP vm created on host with unstable TSC; "
8133 "guest TSC will not be reliable\n");
c447e76b
LL		 8134
8135 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
8136
c447e76b 8137 return vcpu;
26e5215f 8138}
e9b11c17 8139
26e5215f
AK		 8140int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
8141{
19efffa2 8142 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 8143 vcpu_load(vcpu);
d28bc9dd 8144 kvm_vcpu_reset(vcpu, false);
8a3c1a33 8145 kvm_mmu_setup(vcpu);
e9b11c17 8146 vcpu_put(vcpu);
ec7660cc 8147 return 0;
e9b11c17
ZX		 8148}
8149
31928aa5 8150void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 8151{
8fe8ab46 8152 struct msr_data msr;
332967a3 8153 struct kvm *kvm = vcpu->kvm;
42897d86 8154
d3457c87
RK		 8155 kvm_hv_vcpu_postcreate(vcpu);
8156
ec7660cc 8157 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 8158 return;
ec7660cc 8159 vcpu_load(vcpu);
8fe8ab46
WA		 8160 msr.data = 0x0;
8161 msr.index = MSR_IA32_TSC;
8162 msr.host_initiated = true;
8163 kvm_write_tsc(vcpu, &msr);
42897d86 8164 vcpu_put(vcpu);
ec7660cc 8165 mutex_unlock(&vcpu->mutex);
42897d86 8166
630994b3
MT		 8167 if (!kvmclock_periodic_sync)
8168 return;
8169
332967a3
AJ		 8170 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
8171 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 8172}
8173
d40ccc62 8174void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 8175{
344d9588
GN		 8176 vcpu->arch.apf.msr_val = 0;
8177
ec7660cc 8178 vcpu_load(vcpu);
e9b11c17
ZX		 8179 kvm_mmu_unload(vcpu);
8180 vcpu_put(vcpu);
8181
8182 kvm_x86_ops->vcpu_free(vcpu);
8183}
8184
d28bc9dd 8185void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 8186{
b7e31be3
RK		 8187 kvm_lapic_reset(vcpu, init_event);
8188
e69fab5d
PB		 8189 vcpu->arch.hflags = 0;
8190
c43203ca 8191 vcpu->arch.smi_pending = 0;
52797bf9 8192 vcpu->arch.smi_count = 0;
7460fb4a
AK		 8193 atomic_set(&vcpu->arch.nmi_queued, 0);
8194 vcpu->arch.nmi_pending = 0;
448fa4a9 8195 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 8196 kvm_clear_interrupt_queue(vcpu);
8197 kvm_clear_exception_queue(vcpu);
664f8e26 8198 vcpu->arch.exception.pending = false;
448fa4a9 8199
42dbaa5a 8200 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 8201 kvm_update_dr0123(vcpu);
6f43ed01 8202 vcpu->arch.dr6 = DR6_INIT;
73aaf249 8203 kvm_update_dr6(vcpu);
42dbaa5a 8204 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 8205 kvm_update_dr7(vcpu);
42dbaa5a 8206
1119022c
NA		 8207 vcpu->arch.cr2 = 0;
8208
3842d135 8209 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 8210 vcpu->arch.apf.msr_val = 0;
c9aaa895 8211 vcpu->arch.st.msr_val = 0;
3842d135 8212
12f9a48f
GC		 8213 kvmclock_reset(vcpu);
8214
af585b92
GN		 8215 kvm_clear_async_pf_completion_queue(vcpu);
8216 kvm_async_pf_hash_reset(vcpu);
8217 vcpu->arch.apf.halted = false;
3842d135 8218
a554d207
WL		 8219 if (kvm_mpx_supported()) {
8220 void *mpx_state_buffer;
8221
8222 /*
8223 * To avoid have the INIT path from kvm_apic_has_events() that be
8224 * called with loaded FPU and does not let userspace fix the state.
8225 */
f775b13e
RR		 8226 if (init_event)
8227 kvm_put_guest_fpu(vcpu);
a554d207
WL		 8228 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8229 XFEATURE_MASK_BNDREGS);
8230 if (mpx_state_buffer)
8231 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
8232 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
8233 XFEATURE_MASK_BNDCSR);
8234 if (mpx_state_buffer)
8235 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 8236 if (init_event)
8237 kvm_load_guest_fpu(vcpu);
a554d207
WL		 8238 }
8239
64d60670 8240 if (!init_event) {
d28bc9dd 8241 kvm_pmu_reset(vcpu);
64d60670 8242 vcpu->arch.smbase = 0x30000;
db2336a8
KH		 8243
8244 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
8245 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 8246
8247 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 8248 }
f5132b01 8249
66f7b72e
JS		 8250 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
8251 vcpu->arch.regs_avail = ~0;
8252 vcpu->arch.regs_dirty = ~0;
8253
a554d207
WL		 8254 vcpu->arch.ia32_xss = 0;
8255
d28bc9dd 8256 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 8257}
8258
2b4a273b 8259void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 8260{
8261 struct kvm_segment cs;
8262
8263 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8264 cs.selector = vector << 8;
8265 cs.base = vector << 12;
8266 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8267 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 8268}
8269
13a34e06 8270int kvm_arch_hardware_enable(void)
e9b11c17 8271{
ca84d1a2
ZA		 8272 struct kvm *kvm;
8273 struct kvm_vcpu *vcpu;
8274 int i;
0dd6a6ed
ZA		 8275 int ret;
8276 u64 local_tsc;
8277 u64 max_tsc = 0;
8278 bool stable, backwards_tsc = false;
18863bdd
AK		 8279
8280 kvm_shared_msr_cpu_online();
13a34e06 8281 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 8282 if (ret != 0)
8283 return ret;
8284
4ea1636b 8285 local_tsc = rdtsc();
b0c39dc6 8286 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 8287 list_for_each_entry(kvm, &vm_list, vm_list) {
8288 kvm_for_each_vcpu(i, vcpu, kvm) {
8289 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8290 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8291 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8292 backwards_tsc = true;
8293 if (vcpu->arch.last_host_tsc > max_tsc)
8294 max_tsc = vcpu->arch.last_host_tsc;
8295 }
8296 }
8297 }
8298
8299 /*
8300 * Sometimes, even reliable TSCs go backwards. This happens on
8301 * platforms that reset TSC during suspend or hibernate actions, but
8302 * maintain synchronization. We must compensate. Fortunately, we can
8303 * detect that condition here, which happens early in CPU bringup,
8304 * before any KVM threads can be running. Unfortunately, we can't
8305 * bring the TSCs fully up to date with real time, as we aren't yet far
8306 * enough into CPU bringup that we know how much real time has actually
108b249c 8307 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 8308 * variables that haven't been updated yet.
8309 *
8310 * So we simply find the maximum observed TSC above, then record the
8311 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8312 * the adjustment will be applied. Note that we accumulate
8313 * adjustments, in case multiple suspend cycles happen before some VCPU
8314 * gets a chance to run again. In the event that no KVM threads get a
8315 * chance to run, we will miss the entire elapsed period, as we'll have
8316 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8317 * loose cycle time. This isn't too big a deal, since the loss will be
8318 * uniform across all VCPUs (not to mention the scenario is extremely
8319 * unlikely). It is possible that a second hibernate recovery happens
8320 * much faster than a first, causing the observed TSC here to be
8321 * smaller; this would require additional padding adjustment, which is
8322 * why we set last_host_tsc to the local tsc observed here.
8323 *
8324 * N.B. - this code below runs only on platforms with reliable TSC,
8325 * as that is the only way backwards_tsc is set above. Also note
8326 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8327 * have the same delta_cyc adjustment applied if backwards_tsc
8328 * is detected. Note further, this adjustment is only done once,
8329 * as we reset last_host_tsc on all VCPUs to stop this from being
8330 * called multiple times (one for each physical CPU bringup).
8331 *
4a969980 8332 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 8333 * will be compensated by the logic in vcpu_load, which sets the TSC to
8334 * catchup mode. This will catchup all VCPUs to real time, but cannot
8335 * guarantee that they stay in perfect synchronization.
8336 */
8337 if (backwards_tsc) {
8338 u64 delta_cyc = max_tsc - local_tsc;
8339 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8340 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 8341 kvm_for_each_vcpu(i, vcpu, kvm) {
8342 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8343 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8344 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 8345 }
8346
8347 /*
8348 * We have to disable TSC offset matching.. if you were
8349 * booting a VM while issuing an S4 host suspend....
8350 * you may have some problem. Solving this issue is
8351 * left as an exercise to the reader.
8352 */
8353 kvm->arch.last_tsc_nsec = 0;
8354 kvm->arch.last_tsc_write = 0;
8355 }
8356
8357 }
8358 return 0;
e9b11c17
ZX		 8359}
8360
13a34e06 8361void kvm_arch_hardware_disable(void)
e9b11c17 8362{
13a34e06
RK		 8363 kvm_x86_ops->hardware_disable();
8364 drop_user_return_notifiers();
e9b11c17
ZX		 8365}
8366
8367int kvm_arch_hardware_setup(void)
8368{
9e9c3fe4
NA		 8369 int r;
8370
8371 r = kvm_x86_ops->hardware_setup();
8372 if (r != 0)
8373 return r;
8374
35181e86
HZ		 8375 if (kvm_has_tsc_control) {
8376 /*
8377 * Make sure the user can only configure tsc_khz values that
8378 * fit into a signed integer.
8379 * A min value is not calculated needed because it will always
8380 * be 1 on all machines.
8381 */
8382 u64 max = min(0x7fffffffULL,
8383 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8384 kvm_max_guest_tsc_khz = max;
8385
ad721883 8386 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8387 }
ad721883 8388
9e9c3fe4
NA		 8389 kvm_init_msr_list();
8390 return 0;
e9b11c17
ZX		 8391}
8392
8393void kvm_arch_hardware_unsetup(void)
8394{
8395 kvm_x86_ops->hardware_unsetup();
8396}
8397
8398void kvm_arch_check_processor_compat(void *rtn)
8399{
8400 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 8401}
8402
8403bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8404{
8405 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8406}
8407EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8408
8409bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8410{
8411 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 8412}
8413
54e9818f 8414struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8415EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8416
e9b11c17
ZX		 8417int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8418{
8419 struct page *page;
e9b11c17
ZX		 8420 int r;
8421
b2a05fef 8422 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8423 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8424 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8425 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8426 else
a4535290 8427 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 8428
8429 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8430 if (!page) {
8431 r = -ENOMEM;
8432 goto fail;
8433 }
ad312c7c 8434 vcpu->arch.pio_data = page_address(page);
e9b11c17 8435
cc578287 8436 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8437
e9b11c17
ZX		 8438 r = kvm_mmu_create(vcpu);
8439 if (r < 0)
8440 goto fail_free_pio_data;
8441
26de7988 8442 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX		 8443 r = kvm_create_lapic(vcpu);
8444 if (r < 0)
8445 goto fail_mmu_destroy;
54e9818f
GN		 8446 } else
8447 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8448
890ca9ae
HY		 8449 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8450 GFP_KERNEL);
8451 if (!vcpu->arch.mce_banks) {
8452 r = -ENOMEM;
443c39bc 8453 goto fail_free_lapic;
890ca9ae
HY		 8454 }
8455 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8456
f1797359
WY		 8457 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8458 r = -ENOMEM;
f5f48ee1 8459 goto fail_free_mce_banks;
f1797359 8460 }
f5f48ee1 8461
0ee6a517 8462 fx_init(vcpu);
66f7b72e 8463
4344ee98 8464 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8465
5a4f55cd
EK		 8466 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8467
74545705
RK		 8468 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8469
af585b92 8470 kvm_async_pf_hash_reset(vcpu);
f5132b01 8471 kvm_pmu_init(vcpu);
af585b92 8472
1c1a9ce9 8473 vcpu->arch.pending_external_vector = -1;
de63ad4c 8474 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8475
5c919412
AS		 8476 kvm_hv_vcpu_init(vcpu);
8477
e9b11c17 8478 return 0;
0ee6a517 8479
f5f48ee1
SY		 8480fail_free_mce_banks:
8481 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 8482fail_free_lapic:
8483 kvm_free_lapic(vcpu);
e9b11c17
ZX		 8484fail_mmu_destroy:
8485 kvm_mmu_destroy(vcpu);
8486fail_free_pio_data:
ad312c7c 8487 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 8488fail:
8489 return r;
8490}
8491
8492void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8493{
f656ce01
MT		 8494 int idx;
8495
1f4b34f8 8496 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8497 kvm_pmu_destroy(vcpu);
36cb93fd 8498 kfree(vcpu->arch.mce_banks);
e9b11c17 8499 kvm_free_lapic(vcpu);
f656ce01 8500 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8501 kvm_mmu_destroy(vcpu);
f656ce01 8502 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8503 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8504 if (!lapic_in_kernel(vcpu))
54e9818f 8505 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8506}
d19a9cd2 8507
e790d9ef
RK		 8508void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8509{
ae97a3b8 8510 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 8511}
8512
e08b9637 8513int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8514{
e08b9637
CO		 8515 if (type)
8516 return -EINVAL;
8517
6ef768fa 8518 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8519 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8520 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8521 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8522 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8523
5550af4d
SY		 8524 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8525 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 8526 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8527 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8528 &kvm->arch.irq_sources_bitmap);
5550af4d 8529
038f8c11 8530 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8531 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 8532 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8533
108b249c 8534 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8535 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8536
7e44e449 8537 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8538 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8539
cbc0236a 8540 kvm_hv_init_vm(kvm);
0eb05bf2 8541 kvm_page_track_init(kvm);
13d268ca 8542 kvm_mmu_init_vm(kvm);
0eb05bf2 8543
03543133
SS		 8544 if (kvm_x86_ops->vm_init)
8545 return kvm_x86_ops->vm_init(kvm);
8546
d89f5eff 8547 return 0;
d19a9cd2
ZX		 8548}
8549
8550static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8551{
ec7660cc 8552 vcpu_load(vcpu);
d19a9cd2
ZX		 8553 kvm_mmu_unload(vcpu);
8554 vcpu_put(vcpu);
8555}
8556
8557static void kvm_free_vcpus(struct kvm *kvm)
8558{
8559 unsigned int i;
988a2cae 8560 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8561
8562 /*
8563 * Unpin any mmu pages first.
8564 */
af585b92
GN		 8565 kvm_for_each_vcpu(i, vcpu, kvm) {
8566 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8567 kvm_unload_vcpu_mmu(vcpu);
af585b92 8568 }
988a2cae
GN		 8569 kvm_for_each_vcpu(i, vcpu, kvm)
8570 kvm_arch_vcpu_free(vcpu);
8571
8572 mutex_lock(&kvm->lock);
8573 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8574 kvm->vcpus[i] = NULL;
d19a9cd2 8575
988a2cae
GN		 8576 atomic_set(&kvm->online_vcpus, 0);
8577 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8578}
8579
ad8ba2cd
SY		 8580void kvm_arch_sync_events(struct kvm *kvm)
8581{
332967a3 8582 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8583 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8584 kvm_free_pit(kvm);
ad8ba2cd
SY		 8585}
8586
1d8007bd 8587int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8588{
8589 int i, r;
25188b99 8590 unsigned long hva;
f0d648bd
PB		 8591 struct kvm_memslots *slots = kvm_memslots(kvm);
8592 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8593
8594 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8595 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8596 return -EINVAL;
9da0e4d5 8597
f0d648bd
PB		 8598 slot = id_to_memslot(slots, id);
8599 if (size) {
b21629da 8600 if (slot->npages)
f0d648bd
PB		 8601 return -EEXIST;
8602
8603 /*
8604 * MAP_SHARED to prevent internal slot pages from being moved
8605 * by fork()/COW.
8606 */
8607 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8608 MAP_SHARED | MAP_ANONYMOUS, 0);
8609 if (IS_ERR((void *)hva))
8610 return PTR_ERR((void *)hva);
8611 } else {
8612 if (!slot->npages)
8613 return 0;
8614
8615 hva = 0;
8616 }
8617
8618 old = *slot;
9da0e4d5 8619 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8620 struct kvm_userspace_memory_region m;
9da0e4d5 8621
1d8007bd
PB		 8622 m.slot = id | (i << 16);
8623 m.flags = 0;
8624 m.guest_phys_addr = gpa;
f0d648bd 8625 m.userspace_addr = hva;
1d8007bd 8626 m.memory_size = size;
9da0e4d5
PB		 8627 r = __kvm_set_memory_region(kvm, &m);
8628 if (r < 0)
8629 return r;
8630 }
8631
103c763c
EB		 8632 if (!size)
8633 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8634
9da0e4d5
PB		 8635 return 0;
8636}
8637EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8638
1d8007bd 8639int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8640{
8641 int r;
8642
8643 mutex_lock(&kvm->slots_lock);
1d8007bd 8644 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8645 mutex_unlock(&kvm->slots_lock);
8646
8647 return r;
8648}
8649EXPORT_SYMBOL_GPL(x86_set_memory_region);
8650
d19a9cd2
ZX		 8651void kvm_arch_destroy_vm(struct kvm *kvm)
8652{
27469d29
AH		 8653 if (current->mm == kvm->mm) {
8654 /*
8655 * Free memory regions allocated on behalf of userspace,
8656 * unless the the memory map has changed due to process exit
8657 * or fd copying.
8658 */
1d8007bd
PB		 8659 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8660 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8661 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8662 }
03543133
SS		 8663 if (kvm_x86_ops->vm_destroy)
8664 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8665 kvm_pic_destroy(kvm);
8666 kvm_ioapic_destroy(kvm);
d19a9cd2 8667 kvm_free_vcpus(kvm);
af1bae54 8668 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8669 kvm_mmu_uninit_vm(kvm);
2beb6dad 8670 kvm_page_track_cleanup(kvm);
cbc0236a 8671 kvm_hv_destroy_vm(kvm);
d19a9cd2 8672}
0de10343 8673
5587027c 8674void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8675 struct kvm_memory_slot *dont)
8676{
8677 int i;
8678
d89cc617
TY		 8679 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8680 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8681 kvfree(free->arch.rmap[i]);
d89cc617 8682 free->arch.rmap[i] = NULL;
77d11309 8683 }
d89cc617
TY		 8684 if (i == 0)
8685 continue;
8686
8687 if (!dont || free->arch.lpage_info[i - 1] !=
8688 dont->arch.lpage_info[i - 1]) {
548ef284 8689 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8690 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8691 }
8692 }
21ebbeda
XG		 8693
8694 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8695}
8696
5587027c
AK		 8697int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8698 unsigned long npages)
db3fe4eb
TY		 8699{
8700 int i;
8701
d89cc617 8702 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8703 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8704 unsigned long ugfn;
8705 int lpages;
d89cc617 8706 int level = i + 1;
db3fe4eb
TY		 8707
8708 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8709 slot->base_gfn, level) + 1;
8710
d89cc617 8711 slot->arch.rmap[i] =
a7c3e901 8712 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8713 if (!slot->arch.rmap[i])
77d11309 8714 goto out_free;
d89cc617
TY		 8715 if (i == 0)
8716 continue;
77d11309 8717
a7c3e901 8718 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8719 if (!linfo)
db3fe4eb
TY		 8720 goto out_free;
8721
92f94f1e
XG		 8722 slot->arch.lpage_info[i - 1] = linfo;
8723
db3fe4eb 8724 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8725 linfo[0].disallow_lpage = 1;
db3fe4eb 8726 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8727 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8728 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8729 /*
8730 * If the gfn and userspace address are not aligned wrt each
8731 * other, or if explicitly asked to, disable large page
8732 * support for this slot
8733 */
8734 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8735 !kvm_largepages_enabled()) {
8736 unsigned long j;
8737
8738 for (j = 0; j < lpages; ++j)
92f94f1e 8739 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8740 }
8741 }
8742
21ebbeda
XG		 8743 if (kvm_page_track_create_memslot(slot, npages))
8744 goto out_free;
8745
db3fe4eb
TY		 8746 return 0;
8747
8748out_free:
d89cc617 8749 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8750 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8751 slot->arch.rmap[i] = NULL;
8752 if (i == 0)
8753 continue;
8754
548ef284 8755 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8756 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8757 }
8758 return -ENOMEM;
8759}
8760
15f46015 8761void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8762{
e6dff7d1
TY		 8763 /*
8764 * memslots->generation has been incremented.
8765 * mmio generation may have reached its maximum value.
8766 */
54bf36aa 8767 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8768}
8769
f7784b8e
MT		 8770int kvm_arch_prepare_memory_region(struct kvm *kvm,
8771 struct kvm_memory_slot *memslot,
09170a49 8772 const struct kvm_userspace_memory_region *mem,
7b6195a9 8773 enum kvm_mr_change change)
0de10343 8774{
f7784b8e
MT		 8775 return 0;
8776}
8777
88178fd4
KH		 8778static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8779 struct kvm_memory_slot *new)
8780{
8781 /* Still write protect RO slot */
8782 if (new->flags & KVM_MEM_READONLY) {
8783 kvm_mmu_slot_remove_write_access(kvm, new);
8784 return;
8785 }
8786
8787 /*
8788 * Call kvm_x86_ops dirty logging hooks when they are valid.
8789 *
8790 * kvm_x86_ops->slot_disable_log_dirty is called when:
8791 *
8792 * - KVM_MR_CREATE with dirty logging is disabled
8793 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8794 *
8795 * The reason is, in case of PML, we need to set D-bit for any slots
8796 * with dirty logging disabled in order to eliminate unnecessary GPA
8797 * logging in PML buffer (and potential PML buffer full VMEXT). This
8798 * guarantees leaving PML enabled during guest's lifetime won't have
8799 * any additonal overhead from PML when guest is running with dirty
8800 * logging disabled for memory slots.
8801 *
8802 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8803 * to dirty logging mode.
8804 *
8805 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8806 *
8807 * In case of write protect:
8808 *
8809 * Write protect all pages for dirty logging.
8810 *
8811 * All the sptes including the large sptes which point to this
8812 * slot are set to readonly. We can not create any new large
8813 * spte on this slot until the end of the logging.
8814 *
8815 * See the comments in fast_page_fault().
8816 */
8817 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8818 if (kvm_x86_ops->slot_enable_log_dirty)
8819 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8820 else
8821 kvm_mmu_slot_remove_write_access(kvm, new);
8822 } else {
8823 if (kvm_x86_ops->slot_disable_log_dirty)
8824 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8825 }
8826}
8827
f7784b8e 8828void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8829 const struct kvm_userspace_memory_region *mem,
8482644a 8830 const struct kvm_memory_slot *old,
f36f3f28 8831 const struct kvm_memory_slot *new,
8482644a 8832 enum kvm_mr_change change)
f7784b8e 8833{
8482644a 8834 int nr_mmu_pages = 0;
f7784b8e 8835
48c0e4e9
XG		 8836 if (!kvm->arch.n_requested_mmu_pages)
8837 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8838
48c0e4e9 8839 if (nr_mmu_pages)
0de10343 8840 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8841
3ea3b7fa
WL		 8842 /*
8843 * Dirty logging tracks sptes in 4k granularity, meaning that large
8844 * sptes have to be split. If live migration is successful, the guest
8845 * in the source machine will be destroyed and large sptes will be
8846 * created in the destination. However, if the guest continues to run
8847 * in the source machine (for example if live migration fails), small
8848 * sptes will remain around and cause bad performance.
8849 *
8850 * Scan sptes if dirty logging has been stopped, dropping those
8851 * which can be collapsed into a single large-page spte. Later
8852 * page faults will create the large-page sptes.
8853 */
8854 if ((change != KVM_MR_DELETE) &&
8855 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8856 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8857 kvm_mmu_zap_collapsible_sptes(kvm, new);
8858
c972f3b1 8859 /*
88178fd4 8860 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8861 *
88178fd4
KH		 8862 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8863 * been zapped so no dirty logging staff is needed for old slot. For
8864 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8865 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8866 *
8867 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8868 */
88178fd4 8869 if (change != KVM_MR_DELETE)
f36f3f28 8870 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8871}
1d737c8a 8872
2df72e9b 8873void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8874{
6ca18b69 8875 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8876}
8877
2df72e9b
MT		 8878void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8879 struct kvm_memory_slot *slot)
8880{
ae7cd873 8881 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8882}
8883
5d9bc648
PB		 8884static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8885{
8886 if (!list_empty_careful(&vcpu->async_pf.done))
8887 return true;
8888
8889 if (kvm_apic_has_events(vcpu))
8890 return true;
8891
8892 if (vcpu->arch.pv.pv_unhalted)
8893 return true;
8894
a5f01f8e
WL		 8895 if (vcpu->arch.exception.pending)
8896 return true;
8897
47a66eed
Z		 8898 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8899 (vcpu->arch.nmi_pending &&
8900 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 8901 return true;
8902
47a66eed
Z		 8903 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8904 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 8905 return true;
8906
5d9bc648
PB		 8907 if (kvm_arch_interrupt_allowed(vcpu) &&
8908 kvm_cpu_has_interrupt(vcpu))
8909 return true;
8910
1f4b34f8
AS		 8911 if (kvm_hv_has_stimer_pending(vcpu))
8912 return true;
8913
5d9bc648
PB		 8914 return false;
8915}
8916
1d737c8a
ZX		 8917int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8918{
5d9bc648 8919 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8920}
5736199a 8921
199b5763
LM		 8922bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8923{
de63ad4c 8924 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 8925}
8926
b6d33834 8927int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8928{
b6d33834 8929 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8930}
78646121
GN		 8931
8932int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8933{
8934 return kvm_x86_ops->interrupt_allowed(vcpu);
8935}
229456fc 8936
82b32774 8937unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8938{
82b32774
NA		 8939 if (is_64_bit_mode(vcpu))
8940 return kvm_rip_read(vcpu);
8941 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8942 kvm_rip_read(vcpu));
8943}
8944EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8945
82b32774
NA		 8946bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8947{
8948 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8949}
8950EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8951
94fe45da
JK		 8952unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8953{
8954 unsigned long rflags;
8955
8956 rflags = kvm_x86_ops->get_rflags(vcpu);
8957 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8958 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8959 return rflags;
8960}
8961EXPORT_SYMBOL_GPL(kvm_get_rflags);
8962
6addfc42 8963static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8964{
8965 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8966 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8967 rflags |= X86_EFLAGS_TF;
94fe45da 8968 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8969}
8970
8971void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8972{
8973 __kvm_set_rflags(vcpu, rflags);
3842d135 8974 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8975}
8976EXPORT_SYMBOL_GPL(kvm_set_rflags);
8977
56028d08
GN		 8978void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8979{
8980 int r;
8981
fb67e14f 8982 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8983 work->wakeup_all)
56028d08
GN		 8984 return;
8985
8986 r = kvm_mmu_reload(vcpu);
8987 if (unlikely(r))
8988 return;
8989
fb67e14f
XG		 8990 if (!vcpu->arch.mmu.direct_map &&
8991 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8992 return;
8993
56028d08
GN		 8994 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8995}
8996
af585b92
GN		 8997static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8998{
8999 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
9000}
9001
9002static inline u32 kvm_async_pf_next_probe(u32 key)
9003{
9004 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
9005}
9006
9007static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9008{
9009 u32 key = kvm_async_pf_hash_fn(gfn);
9010
9011 while (vcpu->arch.apf.gfns[key] != ~0)
9012 key = kvm_async_pf_next_probe(key);
9013
9014 vcpu->arch.apf.gfns[key] = gfn;
9015}
9016
9017static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
9018{
9019 int i;
9020 u32 key = kvm_async_pf_hash_fn(gfn);
9021
9022 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 9023 (vcpu->arch.apf.gfns[key] != gfn &&
9024 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 9025 key = kvm_async_pf_next_probe(key);
9026
9027 return key;
9028}
9029
9030bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9031{
9032 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
9033}
9034
9035static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
9036{
9037 u32 i, j, k;
9038
9039 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
9040 while (true) {
9041 vcpu->arch.apf.gfns[i] = ~0;
9042 do {
9043 j = kvm_async_pf_next_probe(j);
9044 if (vcpu->arch.apf.gfns[j] == ~0)
9045 return;
9046 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
9047 /*
9048 * k lies cyclically in ]i,j]
9049 * | i.k.j |
9050 * |....j i.k.| or |.k..j i...|
9051 */
9052 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
9053 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
9054 i = j;
9055 }
9056}
9057
7c90705b
GN		 9058static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
9059{
4e335d9e
PB		 9060
9061 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
9062 sizeof(val));
7c90705b
GN		 9063}
9064
9a6e7c39
WL		 9065static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
9066{
9067
9068 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
9069 sizeof(u32));
9070}
9071
af585b92
GN		 9072void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
9073 struct kvm_async_pf *work)
9074{
6389ee94
AK		 9075 struct x86_exception fault;
9076
7c90705b 9077 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 9078 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 9079
9080 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 9081 (vcpu->arch.apf.send_user_only &&
9082 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 9083 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
9084 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 9085 fault.vector = PF_VECTOR;
9086 fault.error_code_valid = true;
9087 fault.error_code = 0;
9088 fault.nested_page_fault = false;
9089 fault.address = work->arch.token;
adfe20fb 9090 fault.async_page_fault = true;
6389ee94 9091 kvm_inject_page_fault(vcpu, &fault);
7c90705b 9092 }
af585b92
GN		 9093}
9094
9095void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
9096 struct kvm_async_pf *work)
9097{
6389ee94 9098 struct x86_exception fault;
9a6e7c39 9099 u32 val;
6389ee94 9100
f2e10669 9101 if (work->wakeup_all)
7c90705b
GN		 9102 work->arch.token = ~0; /* broadcast wakeup */
9103 else
9104 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 9105 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 9106
9a6e7c39
WL		 9107 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
9108 !apf_get_user(vcpu, &val)) {
9109 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
9110 vcpu->arch.exception.pending &&
9111 vcpu->arch.exception.nr == PF_VECTOR &&
9112 !apf_put_user(vcpu, 0)) {
9113 vcpu->arch.exception.injected = false;
9114 vcpu->arch.exception.pending = false;
9115 vcpu->arch.exception.nr = 0;
9116 vcpu->arch.exception.has_error_code = false;
9117 vcpu->arch.exception.error_code = 0;
9118 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
9119 fault.vector = PF_VECTOR;
9120 fault.error_code_valid = true;
9121 fault.error_code = 0;
9122 fault.nested_page_fault = false;
9123 fault.address = work->arch.token;
9124 fault.async_page_fault = true;
9125 kvm_inject_page_fault(vcpu, &fault);
9126 }
7c90705b 9127 }
e6d53e3b 9128 vcpu->arch.apf.halted = false;
a4fa1635 9129 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 9130}
9131
9132bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
9133{
9134 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
9135 return true;
9136 else
9bc1f09f 9137 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 9138}
9139
5544eb9b
PB		 9140void kvm_arch_start_assignment(struct kvm *kvm)
9141{
9142 atomic_inc(&kvm->arch.assigned_device_count);
9143}
9144EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
9145
9146void kvm_arch_end_assignment(struct kvm *kvm)
9147{
9148 atomic_dec(&kvm->arch.assigned_device_count);
9149}
9150EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
9151
9152bool kvm_arch_has_assigned_device(struct kvm *kvm)
9153{
9154 return atomic_read(&kvm->arch.assigned_device_count);
9155}
9156EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
9157
e0f0bbc5
AW		 9158void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
9159{
9160 atomic_inc(&kvm->arch.noncoherent_dma_count);
9161}
9162EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
9163
9164void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
9165{
9166 atomic_dec(&kvm->arch.noncoherent_dma_count);
9167}
9168EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
9169
9170bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
9171{
9172 return atomic_read(&kvm->arch.noncoherent_dma_count);
9173}
9174EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
9175
14717e20
AW		 9176bool kvm_arch_has_irq_bypass(void)
9177{
9178 return kvm_x86_ops->update_pi_irte != NULL;
9179}
9180
87276880
FW		 9181int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
9182 struct irq_bypass_producer *prod)
9183{
9184 struct kvm_kernel_irqfd *irqfd =
9185 container_of(cons, struct kvm_kernel_irqfd, consumer);
9186
14717e20 9187 irqfd->producer = prod;
87276880 9188
14717e20
AW		 9189 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
9190 prod->irq, irqfd->gsi, 1);
87276880
FW		 9191}
9192
9193void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
9194 struct irq_bypass_producer *prod)
9195{
9196 int ret;
9197 struct kvm_kernel_irqfd *irqfd =
9198 container_of(cons, struct kvm_kernel_irqfd, consumer);
9199
87276880
FW		 9200 WARN_ON(irqfd->producer != prod);
9201 irqfd->producer = NULL;
9202
9203 /*
9204 * When producer of consumer is unregistered, we change back to
9205 * remapped mode, so we can re-use the current implementation
bb3541f1 9206 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 9207 * int this case doesn't want to receive the interrupts.
9208 */
9209 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
9210 if (ret)
9211 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
9212 " fails: %d\n", irqfd->consumer.token, ret);
9213}
9214
9215int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
9216 uint32_t guest_irq, bool set)
9217{
9218 if (!kvm_x86_ops->update_pi_irte)
9219 return -EINVAL;
9220
9221 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
9222}
9223
52004014
FW		 9224bool kvm_vector_hashing_enabled(void)
9225{
9226 return vector_hashing;
9227}
9228EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
9229
229456fc 9230EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 9231EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 9232EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
9233EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
9234EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
9235EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 9236EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 9237EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 9238EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 9239EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 9240EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 9241EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 9242EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 9243EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 9244EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 9245EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 9246EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 9247EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
9248EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)