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KVM: renumber vcpu->request bits
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
474a5bb9 31#include "pmu.h"
e83d5887 32#include "hyperv.h"
313a3dc7 33
18068523 34#include <linux/clocksource.h>
4d5c5d0f 35#include <linux/interrupt.h>
313a3dc7
CO		 36#include <linux/kvm.h>
37#include <linux/fs.h>
38#include <linux/vmalloc.h>
5fb76f9b 39#include <linux/module.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
aec51dc4 56#include <trace/events/kvm.h>
2ed152af 57
229456fc
MT		 58#define CREATE_TRACE_POINTS
59#include "trace.h"
043405e1 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
313a3dc7 71#define MAX_IO_MSRS 256
890ca9ae 72#define KVM_MAX_MCE_BANKS 32
5854dbca 73#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 74
0f65dd70
AK		 75#define emul_to_vcpu(ctxt) \
76 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
1260edbe
LJ		 83static
84u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 85#else
1260edbe 86static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 87#endif
313a3dc7 88
ba1389b7
AK		 89#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
90#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 91
cb142eb7 92static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 93static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 94static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 95
893590c7 96struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 97EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 98
893590c7 99static bool __read_mostly ignore_msrs = 0;
476bc001 100module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 101
9ed96e87
MT		 102unsigned int min_timer_period_us = 500;
103module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
104
630994b3
MT		 105static bool __read_mostly kvmclock_periodic_sync = true;
106module_param(kvmclock_periodic_sync, bool, S_IRUGO);
107
893590c7 108bool __read_mostly kvm_has_tsc_control;
92a1f12d 109EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 110u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 111EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 112u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
113EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
114u64 __read_mostly kvm_max_tsc_scaling_ratio;
115EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
ad721883 116static u64 __read_mostly kvm_default_tsc_scaling_ratio;
92a1f12d 117
cc578287 118/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 119static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 120module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
121
d0659d94 122/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 123unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 124module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
125
893590c7 126static bool __read_mostly backwards_tsc_observed = false;
16a96021 127
18863bdd
AK		 128#define KVM_NR_SHARED_MSRS 16
129
130struct kvm_shared_msrs_global {
131 int nr;
2bf78fa7 132 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 133};
134
135struct kvm_shared_msrs {
136 struct user_return_notifier urn;
137 bool registered;
2bf78fa7
SY		 138 struct kvm_shared_msr_values {
139 u64 host;
140 u64 curr;
141 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 142};
143
144static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 145static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 146
417bc304 147struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 148 { "pf_fixed", VCPU_STAT(pf_fixed) },
149 { "pf_guest", VCPU_STAT(pf_guest) },
150 { "tlb_flush", VCPU_STAT(tlb_flush) },
151 { "invlpg", VCPU_STAT(invlpg) },
152 { "exits", VCPU_STAT(exits) },
153 { "io_exits", VCPU_STAT(io_exits) },
154 { "mmio_exits", VCPU_STAT(mmio_exits) },
155 { "signal_exits", VCPU_STAT(signal_exits) },
156 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 157 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 158 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 159 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 160 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
ba1389b7 161 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 162 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 163 { "request_irq", VCPU_STAT(request_irq_exits) },
164 { "irq_exits", VCPU_STAT(irq_exits) },
165 { "host_state_reload", VCPU_STAT(host_state_reload) },
166 { "efer_reload", VCPU_STAT(efer_reload) },
167 { "fpu_reload", VCPU_STAT(fpu_reload) },
168 { "insn_emulation", VCPU_STAT(insn_emulation) },
169 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 170 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 171 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 172 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
173 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
174 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
175 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
176 { "mmu_flooded", VM_STAT(mmu_flooded) },
177 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 178 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 179 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 180 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 181 { "largepages", VM_STAT(lpages) },
417bc304
HB		 182 { NULL }
183};
184
2acf923e
DC		 185u64 __read_mostly host_xcr0;
186
b6785def 187static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 188
af585b92
GN		 189static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
190{
191 int i;
192 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
193 vcpu->arch.apf.gfns[i] = ~0;
194}
195
18863bdd
AK		 196static void kvm_on_user_return(struct user_return_notifier *urn)
197{
198 unsigned slot;
18863bdd
AK		 199 struct kvm_shared_msrs *locals
200 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 201 struct kvm_shared_msr_values *values;
18863bdd
AK		 202
203 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 204 values = &locals->values[slot];
205 if (values->host != values->curr) {
206 wrmsrl(shared_msrs_global.msrs[slot], values->host);
207 values->curr = values->host;
18863bdd
AK		 208 }
209 }
210 locals->registered = false;
211 user_return_notifier_unregister(urn);
212}
213
2bf78fa7 214static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 215{
18863bdd 216 u64 value;
013f6a5d
MT		 217 unsigned int cpu = smp_processor_id();
218 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 219
2bf78fa7
SY		 220 /* only read, and nobody should modify it at this time,
221 * so don't need lock */
222 if (slot >= shared_msrs_global.nr) {
223 printk(KERN_ERR "kvm: invalid MSR slot!");
224 return;
225 }
226 rdmsrl_safe(msr, &value);
227 smsr->values[slot].host = value;
228 smsr->values[slot].curr = value;
229}
230
231void kvm_define_shared_msr(unsigned slot, u32 msr)
232{
0123be42 233 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 234 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 235 if (slot >= shared_msrs_global.nr)
236 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 237}
238EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
239
240static void kvm_shared_msr_cpu_online(void)
241{
242 unsigned i;
18863bdd
AK		 243
244 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 245 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 246}
247
8b3c3104 248int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 249{
013f6a5d
MT		 250 unsigned int cpu = smp_processor_id();
251 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 252 int err;
18863bdd 253
2bf78fa7 254 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 255 return 0;
2bf78fa7 256 smsr->values[slot].curr = value;
8b3c3104
AH		 257 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
258 if (err)
259 return 1;
260
18863bdd
AK		 261 if (!smsr->registered) {
262 smsr->urn.on_user_return = kvm_on_user_return;
263 user_return_notifier_register(&smsr->urn);
264 smsr->registered = true;
265 }
8b3c3104 266 return 0;
18863bdd
AK		 267}
268EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
269
13a34e06 270static void drop_user_return_notifiers(void)
3548bab5 271{
013f6a5d
MT		 272 unsigned int cpu = smp_processor_id();
273 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 274
275 if (smsr->registered)
276 kvm_on_user_return(&smsr->urn);
277}
278
6866b83e
CO		 279u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
280{
8a5a87d9 281 return vcpu->arch.apic_base;
6866b83e
CO		 282}
283EXPORT_SYMBOL_GPL(kvm_get_apic_base);
284
58cb628d
JK		 285int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
286{
287 u64 old_state = vcpu->arch.apic_base &
288 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
289 u64 new_state = msr_info->data &
290 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
291 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
292 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
293
294 if (!msr_info->host_initiated &&
295 ((msr_info->data & reserved_bits) != 0 ||
296 new_state == X2APIC_ENABLE ||
297 (new_state == MSR_IA32_APICBASE_ENABLE &&
298 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
299 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
300 old_state == 0)))
301 return 1;
302
303 kvm_lapic_set_base(vcpu, msr_info->data);
304 return 0;
6866b83e
CO		 305}
306EXPORT_SYMBOL_GPL(kvm_set_apic_base);
307
2605fc21 308asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 309{
310 /* Fault while not rebooting. We want the trace. */
311 BUG();
312}
313EXPORT_SYMBOL_GPL(kvm_spurious_fault);
314
3fd28fce
ED		 315#define EXCPT_BENIGN 0
316#define EXCPT_CONTRIBUTORY 1
317#define EXCPT_PF 2
318
319static int exception_class(int vector)
320{
321 switch (vector) {
322 case PF_VECTOR:
323 return EXCPT_PF;
324 case DE_VECTOR:
325 case TS_VECTOR:
326 case NP_VECTOR:
327 case SS_VECTOR:
328 case GP_VECTOR:
329 return EXCPT_CONTRIBUTORY;
330 default:
331 break;
332 }
333 return EXCPT_BENIGN;
334}
335
d6e8c854
NA		 336#define EXCPT_FAULT 0
337#define EXCPT_TRAP 1
338#define EXCPT_ABORT 2
339#define EXCPT_INTERRUPT 3
340
341static int exception_type(int vector)
342{
343 unsigned int mask;
344
345 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
346 return EXCPT_INTERRUPT;
347
348 mask = 1 << vector;
349
350 /* #DB is trap, as instruction watchpoints are handled elsewhere */
351 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
352 return EXCPT_TRAP;
353
354 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
355 return EXCPT_ABORT;
356
357 /* Reserved exceptions will result in fault */
358 return EXCPT_FAULT;
359}
360
3fd28fce 361static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 362 unsigned nr, bool has_error, u32 error_code,
363 bool reinject)
3fd28fce
ED		 364{
365 u32 prev_nr;
366 int class1, class2;
367
3842d135
AK		 368 kvm_make_request(KVM_REQ_EVENT, vcpu);
369
3fd28fce
ED		 370 if (!vcpu->arch.exception.pending) {
371 queue:
3ffb2468
NA		 372 if (has_error && !is_protmode(vcpu))
373 has_error = false;
3fd28fce
ED		 374 vcpu->arch.exception.pending = true;
375 vcpu->arch.exception.has_error_code = has_error;
376 vcpu->arch.exception.nr = nr;
377 vcpu->arch.exception.error_code = error_code;
3f0fd292 378 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 379 return;
380 }
381
382 /* to check exception */
383 prev_nr = vcpu->arch.exception.nr;
384 if (prev_nr == DF_VECTOR) {
385 /* triple fault -> shutdown */
a8eeb04a 386 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 387 return;
388 }
389 class1 = exception_class(prev_nr);
390 class2 = exception_class(nr);
391 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
392 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
393 /* generate double fault per SDM Table 5-5 */
394 vcpu->arch.exception.pending = true;
395 vcpu->arch.exception.has_error_code = true;
396 vcpu->arch.exception.nr = DF_VECTOR;
397 vcpu->arch.exception.error_code = 0;
398 } else
399 /* replace previous exception with a new one in a hope
400 that instruction re-execution will regenerate lost
401 exception */
402 goto queue;
403}
404
298101da
AK		 405void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
406{
ce7ddec4 407 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 408}
409EXPORT_SYMBOL_GPL(kvm_queue_exception);
410
ce7ddec4
JR		 411void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
412{
413 kvm_multiple_exception(vcpu, nr, false, 0, true);
414}
415EXPORT_SYMBOL_GPL(kvm_requeue_exception);
416
db8fcefa 417void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 418{
db8fcefa
AP		 419 if (err)
420 kvm_inject_gp(vcpu, 0);
421 else
422 kvm_x86_ops->skip_emulated_instruction(vcpu);
423}
424EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 425
6389ee94 426void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 427{
428 ++vcpu->stat.pf_guest;
6389ee94
AK		 429 vcpu->arch.cr2 = fault->address;
430 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 431}
27d6c865 432EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 433
ef54bcfe 434static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 435{
6389ee94
AK		 436 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
437 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 438 else
6389ee94 439 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 440
441 return fault->nested_page_fault;
d4f8cf66
JR		 442}
443
3419ffc8
SY		 444void kvm_inject_nmi(struct kvm_vcpu *vcpu)
445{
7460fb4a
AK		 446 atomic_inc(&vcpu->arch.nmi_queued);
447 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 448}
449EXPORT_SYMBOL_GPL(kvm_inject_nmi);
450
298101da
AK		 451void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
452{
ce7ddec4 453 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 454}
455EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
456
ce7ddec4
JR		 457void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
458{
459 kvm_multiple_exception(vcpu, nr, true, error_code, true);
460}
461EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
462
0a79b009
AK		 463/*
464 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
465 * a #GP and return false.
466 */
467bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 468{
0a79b009
AK		 469 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
470 return true;
471 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
472 return false;
298101da 473}
0a79b009 474EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 475
16f8a6f9
NA		 476bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
477{
478 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
479 return true;
480
481 kvm_queue_exception(vcpu, UD_VECTOR);
482 return false;
483}
484EXPORT_SYMBOL_GPL(kvm_require_dr);
485
ec92fe44
JR		 486/*
487 * This function will be used to read from the physical memory of the currently
54bf36aa 488 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 489 * can read from guest physical or from the guest's guest physical memory.
490 */
491int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
492 gfn_t ngfn, void *data, int offset, int len,
493 u32 access)
494{
54987b7a 495 struct x86_exception exception;
ec92fe44
JR		 496 gfn_t real_gfn;
497 gpa_t ngpa;
498
499 ngpa = gfn_to_gpa(ngfn);
54987b7a 500 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 501 if (real_gfn == UNMAPPED_GVA)
502 return -EFAULT;
503
504 real_gfn = gpa_to_gfn(real_gfn);
505
54bf36aa 506 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 507}
508EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
509
69b0049a 510static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 511 void *data, int offset, int len, u32 access)
512{
513 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
514 data, offset, len, access);
515}
516
a03490ed
CO		 517/*
518 * Load the pae pdptrs. Return true is they are all valid.
519 */
ff03a073 520int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 521{
522 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
523 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
524 int i;
525 int ret;
ff03a073 526 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 527
ff03a073
JR		 528 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
529 offset * sizeof(u64), sizeof(pdpte),
530 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 531 if (ret < 0) {
532 ret = 0;
533 goto out;
534 }
535 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 536 if (is_present_gpte(pdpte[i]) &&
a0a64f50
XG		 537 (pdpte[i] &
538 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 539 ret = 0;
540 goto out;
541 }
542 }
543 ret = 1;
544
ff03a073 545 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 546 __set_bit(VCPU_EXREG_PDPTR,
547 (unsigned long *)&vcpu->arch.regs_avail);
548 __set_bit(VCPU_EXREG_PDPTR,
549 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 550out:
a03490ed
CO		 551
552 return ret;
553}
cc4b6871 554EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 555
d835dfec
AK		 556static bool pdptrs_changed(struct kvm_vcpu *vcpu)
557{
ff03a073 558 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 559 bool changed = true;
3d06b8bf
JR		 560 int offset;
561 gfn_t gfn;
d835dfec
AK		 562 int r;
563
564 if (is_long_mode(vcpu) || !is_pae(vcpu))
565 return false;
566
6de4f3ad
AK		 567 if (!test_bit(VCPU_EXREG_PDPTR,
568 (unsigned long *)&vcpu->arch.regs_avail))
569 return true;
570
9f8fe504
AK		 571 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
572 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 573 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
574 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 575 if (r < 0)
576 goto out;
ff03a073 577 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 578out:
d835dfec
AK		 579
580 return changed;
581}
582
49a9b07e 583int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 584{
aad82703 585 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 586 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 587
f9a48e6a
AK		 588 cr0 |= X86_CR0_ET;
589
ab344828 590#ifdef CONFIG_X86_64
0f12244f
GN		 591 if (cr0 & 0xffffffff00000000UL)
592 return 1;
ab344828
GN		 593#endif
594
595 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 596
0f12244f
GN		 597 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
598 return 1;
a03490ed 599
0f12244f
GN		 600 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
601 return 1;
a03490ed
CO		 602
603 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
604#ifdef CONFIG_X86_64
f6801dff 605 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 606 int cs_db, cs_l;
607
0f12244f
GN		 608 if (!is_pae(vcpu))
609 return 1;
a03490ed 610 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 611 if (cs_l)
612 return 1;
a03490ed
CO		 613 } else
614#endif
ff03a073 615 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 616 kvm_read_cr3(vcpu)))
0f12244f 617 return 1;
a03490ed
CO		 618 }
619
ad756a16
MJ		 620 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
621 return 1;
622
a03490ed 623 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 624
d170c419 625 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 626 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 627 kvm_async_pf_hash_reset(vcpu);
628 }
e5f3f027 629
aad82703
SY		 630 if ((cr0 ^ old_cr0) & update_bits)
631 kvm_mmu_reset_context(vcpu);
b18d5431 632
879ae188
LE		 633 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
634 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
635 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 636 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
637
0f12244f
GN		 638 return 0;
639}
2d3ad1f4 640EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 641
2d3ad1f4 642void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 643{
49a9b07e 644 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 645}
2d3ad1f4 646EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 647
42bdf991
MT		 648static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
649{
650 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
651 !vcpu->guest_xcr0_loaded) {
652 /* kvm_set_xcr() also depends on this */
653 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
654 vcpu->guest_xcr0_loaded = 1;
655 }
656}
657
658static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
659{
660 if (vcpu->guest_xcr0_loaded) {
661 if (vcpu->arch.xcr0 != host_xcr0)
662 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
663 vcpu->guest_xcr0_loaded = 0;
664 }
665}
666
69b0049a 667static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 668{
56c103ec
LJ		 669 u64 xcr0 = xcr;
670 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 671 u64 valid_bits;
2acf923e
DC		 672
673 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
674 if (index != XCR_XFEATURE_ENABLED_MASK)
675 return 1;
d91cab78 676 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 677 return 1;
d91cab78 678 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 679 return 1;
46c34cb0
PB		 680
681 /*
682 * Do not allow the guest to set bits that we do not support
683 * saving. However, xcr0 bit 0 is always set, even if the
684 * emulated CPU does not support XSAVE (see fx_init).
685 */
d91cab78 686 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 687 if (xcr0 & ~valid_bits)
2acf923e 688 return 1;
46c34cb0 689
d91cab78
DH		 690 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
691 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 692 return 1;
693
d91cab78
DH		 694 if (xcr0 & XFEATURE_MASK_AVX512) {
695 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 696 return 1;
d91cab78 697 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 698 return 1;
699 }
42bdf991 700 kvm_put_guest_xcr0(vcpu);
2acf923e 701 vcpu->arch.xcr0 = xcr0;
56c103ec 702
d91cab78 703 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 704 kvm_update_cpuid(vcpu);
2acf923e
DC		 705 return 0;
706}
707
708int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
709{
764bcbc5
Z		 710 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
711 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 712 kvm_inject_gp(vcpu, 0);
713 return 1;
714 }
715 return 0;
716}
717EXPORT_SYMBOL_GPL(kvm_set_xcr);
718
a83b29c6 719int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 720{
fc78f519 721 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f
XG		 722 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
723 X86_CR4_SMEP | X86_CR4_SMAP;
724
0f12244f
GN		 725 if (cr4 & CR4_RESERVED_BITS)
726 return 1;
a03490ed 727
2acf923e
DC		 728 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
729 return 1;
730
c68b734f
YW		 731 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
732 return 1;
733
97ec8c06
FW		 734 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
735 return 1;
736
afcbf13f 737 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 738 return 1;
739
a03490ed 740 if (is_long_mode(vcpu)) {
0f12244f
GN		 741 if (!(cr4 & X86_CR4_PAE))
742 return 1;
a2edf57f
AK		 743 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
744 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 745 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
746 kvm_read_cr3(vcpu)))
0f12244f
GN		 747 return 1;
748
ad756a16
MJ		 749 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
750 if (!guest_cpuid_has_pcid(vcpu))
751 return 1;
752
753 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
754 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
755 return 1;
756 }
757
5e1746d6 758 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 759 return 1;
a03490ed 760
ad756a16
MJ		 761 if (((cr4 ^ old_cr4) & pdptr_bits) ||
762 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 763 kvm_mmu_reset_context(vcpu);
0f12244f 764
2acf923e 765 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 766 kvm_update_cpuid(vcpu);
2acf923e 767
0f12244f
GN		 768 return 0;
769}
2d3ad1f4 770EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 771
2390218b 772int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 773{
ac146235 774#ifdef CONFIG_X86_64
9d88fca7 775 cr3 &= ~CR3_PCID_INVD;
ac146235 776#endif
9d88fca7 777
9f8fe504 778 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 779 kvm_mmu_sync_roots(vcpu);
77c3913b 780 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 781 return 0;
d835dfec
AK		 782 }
783
a03490ed 784 if (is_long_mode(vcpu)) {
d9f89b88
JK		 785 if (cr3 & CR3_L_MODE_RESERVED_BITS)
786 return 1;
787 } else if (is_pae(vcpu) && is_paging(vcpu) &&
788 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 789 return 1;
a03490ed 790
0f12244f 791 vcpu->arch.cr3 = cr3;
aff48baa 792 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 793 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 794 return 0;
795}
2d3ad1f4 796EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 797
eea1cff9 798int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 799{
0f12244f
GN		 800 if (cr8 & CR8_RESERVED_BITS)
801 return 1;
35754c98 802 if (lapic_in_kernel(vcpu))
a03490ed
CO		 803 kvm_lapic_set_tpr(vcpu, cr8);
804 else
ad312c7c 805 vcpu->arch.cr8 = cr8;
0f12244f
GN		 806 return 0;
807}
2d3ad1f4 808EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 809
2d3ad1f4 810unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 811{
35754c98 812 if (lapic_in_kernel(vcpu))
a03490ed
CO		 813 return kvm_lapic_get_cr8(vcpu);
814 else
ad312c7c 815 return vcpu->arch.cr8;
a03490ed 816}
2d3ad1f4 817EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 818
ae561ede
NA		 819static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
820{
821 int i;
822
823 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
824 for (i = 0; i < KVM_NR_DB_REGS; i++)
825 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
826 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
827 }
828}
829
73aaf249
JK		 830static void kvm_update_dr6(struct kvm_vcpu *vcpu)
831{
832 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
833 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
834}
835
c8639010
JK		 836static void kvm_update_dr7(struct kvm_vcpu *vcpu)
837{
838 unsigned long dr7;
839
840 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
841 dr7 = vcpu->arch.guest_debug_dr7;
842 else
843 dr7 = vcpu->arch.dr7;
844 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 845 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
846 if (dr7 & DR7_BP_EN_MASK)
847 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 848}
849
6f43ed01
NA		 850static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
851{
852 u64 fixed = DR6_FIXED_1;
853
854 if (!guest_cpuid_has_rtm(vcpu))
855 fixed |= DR6_RTM;
856 return fixed;
857}
858
338dbc97 859static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 860{
861 switch (dr) {
862 case 0 ... 3:
863 vcpu->arch.db[dr] = val;
864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
865 vcpu->arch.eff_db[dr] = val;
866 break;
867 case 4:
020df079
GN		 868 /* fall through */
869 case 6:
338dbc97
GN		 870 if (val & 0xffffffff00000000ULL)
871 return -1; /* #GP */
6f43ed01 872 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 873 kvm_update_dr6(vcpu);
020df079
GN		 874 break;
875 case 5:
020df079
GN		 876 /* fall through */
877 default: /* 7 */
338dbc97
GN		 878 if (val & 0xffffffff00000000ULL)
879 return -1; /* #GP */
020df079 880 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 881 kvm_update_dr7(vcpu);
020df079
GN		 882 break;
883 }
884
885 return 0;
886}
338dbc97
GN		 887
888int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
889{
16f8a6f9 890 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 891 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 892 return 1;
893 }
894 return 0;
338dbc97 895}
020df079
GN		 896EXPORT_SYMBOL_GPL(kvm_set_dr);
897
16f8a6f9 898int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 899{
900 switch (dr) {
901 case 0 ... 3:
902 *val = vcpu->arch.db[dr];
903 break;
904 case 4:
020df079
GN		 905 /* fall through */
906 case 6:
73aaf249
JK		 907 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
908 *val = vcpu->arch.dr6;
909 else
910 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 911 break;
912 case 5:
020df079
GN		 913 /* fall through */
914 default: /* 7 */
915 *val = vcpu->arch.dr7;
916 break;
917 }
338dbc97
GN		 918 return 0;
919}
020df079
GN		 920EXPORT_SYMBOL_GPL(kvm_get_dr);
921
022cd0e8
AK		 922bool kvm_rdpmc(struct kvm_vcpu *vcpu)
923{
924 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
925 u64 data;
926 int err;
927
c6702c9d 928 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 929 if (err)
930 return err;
931 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
932 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
933 return err;
934}
935EXPORT_SYMBOL_GPL(kvm_rdpmc);
936
043405e1
CO		 937/*
938 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
939 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
940 *
941 * This list is modified at module load time to reflect the
e3267cbb 942 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 943 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
944 * may depend on host virtualization features rather than host cpu features.
043405e1 945 */
e3267cbb 946
043405e1
CO		 947static u32 msrs_to_save[] = {
948 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 949 MSR_STAR,
043405e1
CO		 950#ifdef CONFIG_X86_64
951 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
952#endif
b3897a49 953 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 954 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 955};
956
957static unsigned num_msrs_to_save;
958
62ef68bb
PB		 959static u32 emulated_msrs[] = {
960 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
961 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
962 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
963 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 964 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
965 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 966 HV_X64_MSR_RESET,
11c4b1ca 967 HV_X64_MSR_VP_INDEX,
9eec50b8 968 HV_X64_MSR_VP_RUNTIME,
5c919412 969 HV_X64_MSR_SCONTROL,
1f4b34f8 970 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 971 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
972 MSR_KVM_PV_EOI_EN,
973
ba904635 974 MSR_IA32_TSC_ADJUST,
a3e06bbe 975 MSR_IA32_TSCDEADLINE,
043405e1 976 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 977 MSR_IA32_MCG_STATUS,
978 MSR_IA32_MCG_CTL,
64d60670 979 MSR_IA32_SMBASE,
043405e1
CO		 980};
981
62ef68bb
PB		 982static unsigned num_emulated_msrs;
983
384bb783 984bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 985{
b69e8cae 986 if (efer & efer_reserved_bits)
384bb783 987 return false;
15c4a640 988
1b2fd70c
AG		 989 if (efer & EFER_FFXSR) {
990 struct kvm_cpuid_entry2 *feat;
991
992 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 993 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 994 return false;
1b2fd70c
AG		 995 }
996
d8017474
AG		 997 if (efer & EFER_SVME) {
998 struct kvm_cpuid_entry2 *feat;
999
1000 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1001 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1002 return false;
d8017474
AG		 1003 }
1004
384bb783
JK		 1005 return true;
1006}
1007EXPORT_SYMBOL_GPL(kvm_valid_efer);
1008
1009static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1010{
1011 u64 old_efer = vcpu->arch.efer;
1012
1013 if (!kvm_valid_efer(vcpu, efer))
1014 return 1;
1015
1016 if (is_paging(vcpu)
1017 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1018 return 1;
1019
15c4a640 1020 efer &= ~EFER_LMA;
f6801dff 1021 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1022
a3d204e2
SY		 1023 kvm_x86_ops->set_efer(vcpu, efer);
1024
aad82703
SY		 1025 /* Update reserved bits */
1026 if ((efer ^ old_efer) & EFER_NX)
1027 kvm_mmu_reset_context(vcpu);
1028
b69e8cae 1029 return 0;
15c4a640
CO		 1030}
1031
f2b4b7dd
JR		 1032void kvm_enable_efer_bits(u64 mask)
1033{
1034 efer_reserved_bits &= ~mask;
1035}
1036EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1037
15c4a640
CO		 1038/*
1039 * Writes msr value into into the appropriate "register".
1040 * Returns 0 on success, non-0 otherwise.
1041 * Assumes vcpu_load() was already called.
1042 */
8fe8ab46 1043int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1044{
854e8bb1
NA		 1045 switch (msr->index) {
1046 case MSR_FS_BASE:
1047 case MSR_GS_BASE:
1048 case MSR_KERNEL_GS_BASE:
1049 case MSR_CSTAR:
1050 case MSR_LSTAR:
1051 if (is_noncanonical_address(msr->data))
1052 return 1;
1053 break;
1054 case MSR_IA32_SYSENTER_EIP:
1055 case MSR_IA32_SYSENTER_ESP:
1056 /*
1057 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1058 * non-canonical address is written on Intel but not on
1059 * AMD (which ignores the top 32-bits, because it does
1060 * not implement 64-bit SYSENTER).
1061 *
1062 * 64-bit code should hence be able to write a non-canonical
1063 * value on AMD. Making the address canonical ensures that
1064 * vmentry does not fail on Intel after writing a non-canonical
1065 * value, and that something deterministic happens if the guest
1066 * invokes 64-bit SYSENTER.
1067 */
1068 msr->data = get_canonical(msr->data);
1069 }
8fe8ab46 1070 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1071}
854e8bb1 1072EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1073
313a3dc7
CO		 1074/*
1075 * Adapt set_msr() to msr_io()'s calling convention
1076 */
609e36d3
PB		 1077static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1078{
1079 struct msr_data msr;
1080 int r;
1081
1082 msr.index = index;
1083 msr.host_initiated = true;
1084 r = kvm_get_msr(vcpu, &msr);
1085 if (r)
1086 return r;
1087
1088 *data = msr.data;
1089 return 0;
1090}
1091
313a3dc7
CO		 1092static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1093{
8fe8ab46
WA		 1094 struct msr_data msr;
1095
1096 msr.data = *data;
1097 msr.index = index;
1098 msr.host_initiated = true;
1099 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1100}
1101
16e8d74d
MT		 1102#ifdef CONFIG_X86_64
1103struct pvclock_gtod_data {
1104 seqcount_t seq;
1105
1106 struct { /* extract of a clocksource struct */
1107 int vclock_mode;
1108 cycle_t cycle_last;
1109 cycle_t mask;
1110 u32 mult;
1111 u32 shift;
1112 } clock;
1113
cbcf2dd3
TG		 1114 u64 boot_ns;
1115 u64 nsec_base;
16e8d74d
MT		 1116};
1117
1118static struct pvclock_gtod_data pvclock_gtod_data;
1119
1120static void update_pvclock_gtod(struct timekeeper *tk)
1121{
1122 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1123 u64 boot_ns;
1124
876e7881 1125 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1126
1127 write_seqcount_begin(&vdata->seq);
1128
1129 /* copy pvclock gtod data */
876e7881
PZ		 1130 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1131 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1132 vdata->clock.mask = tk->tkr_mono.mask;
1133 vdata->clock.mult = tk->tkr_mono.mult;
1134 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1135
cbcf2dd3 1136 vdata->boot_ns = boot_ns;
876e7881 1137 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1138
1139 write_seqcount_end(&vdata->seq);
1140}
1141#endif
1142
bab5bb39
NK		 1143void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1144{
1145 /*
1146 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1147 * vcpu_enter_guest. This function is only called from
1148 * the physical CPU that is running vcpu.
1149 */
1150 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1151}
16e8d74d 1152
18068523
GOC		 1153static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1154{
9ed3c444
AK		 1155 int version;
1156 int r;
50d0a0f9 1157 struct pvclock_wall_clock wc;
923de3cf 1158 struct timespec boot;
18068523
GOC		 1159
1160 if (!wall_clock)
1161 return;
1162
9ed3c444
AK		 1163 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1164 if (r)
1165 return;
1166
1167 if (version & 1)
1168 ++version; /* first time write, random junk */
1169
1170 ++version;
18068523 1171
1dab1345
NK		 1172 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1173 return;
18068523 1174
50d0a0f9
GH		 1175 /*
1176 * The guest calculates current wall clock time by adding
34c238a1 1177 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1178 * wall clock specified here. guest system time equals host
1179 * system time for us, thus we must fill in host boot time here.
1180 */
923de3cf 1181 getboottime(&boot);
50d0a0f9 1182
4b648665
BR		 1183 if (kvm->arch.kvmclock_offset) {
1184 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1185 boot = timespec_sub(boot, ts);
1186 }
50d0a0f9
GH		 1187 wc.sec = boot.tv_sec;
1188 wc.nsec = boot.tv_nsec;
1189 wc.version = version;
18068523
GOC		 1190
1191 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1192
1193 version++;
1194 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1195}
1196
50d0a0f9
GH		 1197static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1198{
1199 uint32_t quotient, remainder;
1200
1201 /* Don't try to replace with do_div(), this one calculates
1202 * "(dividend << 32) / divisor" */
1203 __asm__ ( "divl %4"
1204 : "=a" (quotient), "=d" (remainder)
1205 : "0" (0), "1" (dividend), "r" (divisor) );
1206 return quotient;
1207}
1208
5f4e3f88
ZA		 1209static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1210 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1211{
5f4e3f88 1212 uint64_t scaled64;
50d0a0f9
GH		 1213 int32_t shift = 0;
1214 uint64_t tps64;
1215 uint32_t tps32;
1216
5f4e3f88
ZA		 1217 tps64 = base_khz * 1000LL;
1218 scaled64 = scaled_khz * 1000LL;
50933623 1219 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1220 tps64 >>= 1;
1221 shift--;
1222 }
1223
1224 tps32 = (uint32_t)tps64;
50933623
JK		 1225 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1226 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1227 scaled64 >>= 1;
1228 else
1229 tps32 <<= 1;
50d0a0f9
GH		 1230 shift++;
1231 }
1232
5f4e3f88
ZA		 1233 *pshift = shift;
1234 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1235
5f4e3f88
ZA		 1236 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1237 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1238}
1239
d828199e 1240#ifdef CONFIG_X86_64
16e8d74d 1241static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1242#endif
16e8d74d 1243
c8076604 1244static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1245static unsigned long max_tsc_khz;
c8076604 1246
cc578287 1247static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1248{
cc578287
ZA		 1249 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1250 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1251}
1252
cc578287 1253static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1254{
cc578287
ZA		 1255 u64 v = (u64)khz * (1000000 + ppm);
1256 do_div(v, 1000000);
1257 return v;
1e993611
JR		 1258}
1259
381d585c
HZ		 1260static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1261{
1262 u64 ratio;
1263
1264 /* Guest TSC same frequency as host TSC? */
1265 if (!scale) {
1266 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1267 return 0;
1268 }
1269
1270 /* TSC scaling supported? */
1271 if (!kvm_has_tsc_control) {
1272 if (user_tsc_khz > tsc_khz) {
1273 vcpu->arch.tsc_catchup = 1;
1274 vcpu->arch.tsc_always_catchup = 1;
1275 return 0;
1276 } else {
1277 WARN(1, "user requested TSC rate below hardware speed\n");
1278 return -1;
1279 }
1280 }
1281
1282 /* TSC scaling required - calculate ratio */
1283 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1284 user_tsc_khz, tsc_khz);
1285
1286 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1287 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1288 user_tsc_khz);
1289 return -1;
1290 }
1291
1292 vcpu->arch.tsc_scaling_ratio = ratio;
1293 return 0;
1294}
1295
1296static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1297{
cc578287
ZA		 1298 u32 thresh_lo, thresh_hi;
1299 int use_scaling = 0;
217fc9cf 1300
03ba32ca 1301 /* tsc_khz can be zero if TSC calibration fails */
ad721883
HZ		 1302 if (this_tsc_khz == 0) {
1303 /* set tsc_scaling_ratio to a safe value */
1304 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1305 return -1;
ad721883 1306 }
03ba32ca 1307
c285545f
ZA		 1308 /* Compute a scale to convert nanoseconds in TSC cycles */
1309 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1310 &vcpu->arch.virtual_tsc_shift,
1311 &vcpu->arch.virtual_tsc_mult);
1312 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1313
1314 /*
1315 * Compute the variation in TSC rate which is acceptable
1316 * within the range of tolerance and decide if the
1317 * rate being applied is within that bounds of the hardware
1318 * rate. If so, no scaling or compensation need be done.
1319 */
1320 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1321 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1322 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1323 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1324 use_scaling = 1;
1325 }
381d585c 1326 return set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1327}
1328
1329static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1330{
e26101b1 1331 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1332 vcpu->arch.virtual_tsc_mult,
1333 vcpu->arch.virtual_tsc_shift);
e26101b1 1334 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1335 return tsc;
1336}
1337
69b0049a 1338static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1339{
1340#ifdef CONFIG_X86_64
1341 bool vcpus_matched;
b48aa97e
MT		 1342 struct kvm_arch *ka = &vcpu->kvm->arch;
1343 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1344
1345 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1346 atomic_read(&vcpu->kvm->online_vcpus));
1347
7f187922
MT		 1348 /*
1349 * Once the masterclock is enabled, always perform request in
1350 * order to update it.
1351 *
1352 * In order to enable masterclock, the host clocksource must be TSC
1353 * and the vcpus need to have matched TSCs. When that happens,
1354 * perform request to enable masterclock.
1355 */
1356 if (ka->use_master_clock ||
1357 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1358 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1359
1360 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1361 atomic_read(&vcpu->kvm->online_vcpus),
1362 ka->use_master_clock, gtod->clock.vclock_mode);
1363#endif
1364}
1365
ba904635
WA		 1366static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1367{
1368 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1369 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1370}
1371
35181e86
HZ		 1372/*
1373 * Multiply tsc by a fixed point number represented by ratio.
1374 *
1375 * The most significant 64-N bits (mult) of ratio represent the
1376 * integral part of the fixed point number; the remaining N bits
1377 * (frac) represent the fractional part, ie. ratio represents a fixed
1378 * point number (mult + frac * 2^(-N)).
1379 *
1380 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1381 */
1382static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1383{
1384 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1385}
1386
1387u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1388{
1389 u64 _tsc = tsc;
1390 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1391
1392 if (ratio != kvm_default_tsc_scaling_ratio)
1393 _tsc = __scale_tsc(ratio, tsc);
1394
1395 return _tsc;
1396}
1397EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1398
07c1419a
HZ		 1399static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1400{
1401 u64 tsc;
1402
1403 tsc = kvm_scale_tsc(vcpu, rdtsc());
1404
1405 return target_tsc - tsc;
1406}
1407
4ba76538
HZ		 1408u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1409{
1410 return kvm_x86_ops->read_l1_tsc(vcpu, kvm_scale_tsc(vcpu, host_tsc));
1411}
1412EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1413
8fe8ab46 1414void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1415{
1416 struct kvm *kvm = vcpu->kvm;
f38e098f 1417 u64 offset, ns, elapsed;
99e3e30a 1418 unsigned long flags;
02626b6a 1419 s64 usdiff;
b48aa97e 1420 bool matched;
0d3da0d2 1421 bool already_matched;
8fe8ab46 1422 u64 data = msr->data;
99e3e30a 1423
038f8c11 1424 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1425 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1426 ns = get_kernel_ns();
f38e098f 1427 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1428
03ba32ca 1429 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1430 int faulted = 0;
1431
03ba32ca
MT		 1432 /* n.b - signed multiplication and division required */
1433 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1434#ifdef CONFIG_X86_64
03ba32ca 1435 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1436#else
03ba32ca 1437 /* do_div() only does unsigned */
8915aa27
MT		 1438 asm("1: idivl %[divisor]\n"
1439 "2: xor %%edx, %%edx\n"
1440 " movl $0, %[faulted]\n"
1441 "3:\n"
1442 ".section .fixup,\"ax\"\n"
1443 "4: movl $1, %[faulted]\n"
1444 " jmp 3b\n"
1445 ".previous\n"
1446
1447 _ASM_EXTABLE(1b, 4b)
1448
1449 : "=A"(usdiff), [faulted] "=r" (faulted)
1450 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1451
5d3cb0f6 1452#endif
03ba32ca
MT		 1453 do_div(elapsed, 1000);
1454 usdiff -= elapsed;
1455 if (usdiff < 0)
1456 usdiff = -usdiff;
8915aa27
MT		 1457
1458 /* idivl overflow => difference is larger than USEC_PER_SEC */
1459 if (faulted)
1460 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1461 } else
1462 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1463
1464 /*
5d3cb0f6
ZA		 1465 * Special case: TSC write with a small delta (1 second) of virtual
1466 * cycle time against real time is interpreted as an attempt to
1467 * synchronize the CPU.
1468 *
1469 * For a reliable TSC, we can match TSC offsets, and for an unstable
1470 * TSC, we add elapsed time in this computation. We could let the
1471 * compensation code attempt to catch up if we fall behind, but
1472 * it's better to try to match offsets from the beginning.
1473 */
02626b6a 1474 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1475 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1476 if (!check_tsc_unstable()) {
e26101b1 1477 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1478 pr_debug("kvm: matched tsc offset for %llu\n", data);
1479 } else {
857e4099 1480 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1481 data += delta;
07c1419a 1482 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1483 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1484 }
b48aa97e 1485 matched = true;
0d3da0d2 1486 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1487 } else {
1488 /*
1489 * We split periods of matched TSC writes into generations.
1490 * For each generation, we track the original measured
1491 * nanosecond time, offset, and write, so if TSCs are in
1492 * sync, we can match exact offset, and if not, we can match
4a969980 1493 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1494 *
1495 * These values are tracked in kvm->arch.cur_xxx variables.
1496 */
1497 kvm->arch.cur_tsc_generation++;
1498 kvm->arch.cur_tsc_nsec = ns;
1499 kvm->arch.cur_tsc_write = data;
1500 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1501 matched = false;
0d3da0d2 1502 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1503 kvm->arch.cur_tsc_generation, data);
f38e098f 1504 }
e26101b1
ZA		 1505
1506 /*
1507 * We also track th most recent recorded KHZ, write and time to
1508 * allow the matching interval to be extended at each write.
1509 */
f38e098f
ZA		 1510 kvm->arch.last_tsc_nsec = ns;
1511 kvm->arch.last_tsc_write = data;
5d3cb0f6 1512 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1513
b183aa58 1514 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1515
1516 /* Keep track of which generation this VCPU has synchronized to */
1517 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1518 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1519 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1520
ba904635
WA		 1521 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1522 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1523 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1524 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1525
1526 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1527 if (!matched) {
b48aa97e 1528 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1529 } else if (!already_matched) {
1530 kvm->arch.nr_vcpus_matched_tsc++;
1531 }
b48aa97e
MT		 1532
1533 kvm_track_tsc_matching(vcpu);
1534 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1535}
e26101b1 1536
99e3e30a
ZA		 1537EXPORT_SYMBOL_GPL(kvm_write_tsc);
1538
58ea6767
HZ		 1539static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1540 s64 adjustment)
1541{
1542 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1543}
1544
1545static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1546{
1547 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1548 WARN_ON(adjustment < 0);
1549 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
1550 kvm_x86_ops->adjust_tsc_offset_guest(vcpu, adjustment);
1551}
1552
d828199e
MT		 1553#ifdef CONFIG_X86_64
1554
1555static cycle_t read_tsc(void)
1556{
03b9730b
AL		 1557 cycle_t ret = (cycle_t)rdtsc_ordered();
1558 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1559
1560 if (likely(ret >= last))
1561 return ret;
1562
1563 /*
1564 * GCC likes to generate cmov here, but this branch is extremely
1565 * predictable (it's just a funciton of time and the likely is
1566 * very likely) and there's a data dependence, so force GCC
1567 * to generate a branch instead. I don't barrier() because
1568 * we don't actually need a barrier, and if this function
1569 * ever gets inlined it will generate worse code.
1570 */
1571 asm volatile ("");
1572 return last;
1573}
1574
1575static inline u64 vgettsc(cycle_t *cycle_now)
1576{
1577 long v;
1578 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1579
1580 *cycle_now = read_tsc();
1581
1582 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1583 return v * gtod->clock.mult;
1584}
1585
cbcf2dd3 1586static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1587{
cbcf2dd3 1588 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1589 unsigned long seq;
d828199e 1590 int mode;
cbcf2dd3 1591 u64 ns;
d828199e 1592
d828199e
MT		 1593 do {
1594 seq = read_seqcount_begin(&gtod->seq);
1595 mode = gtod->clock.vclock_mode;
cbcf2dd3 1596 ns = gtod->nsec_base;
d828199e
MT		 1597 ns += vgettsc(cycle_now);
1598 ns >>= gtod->clock.shift;
cbcf2dd3 1599 ns += gtod->boot_ns;
d828199e 1600 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1601 *t = ns;
d828199e
MT		 1602
1603 return mode;
1604}
1605
1606/* returns true if host is using tsc clocksource */
1607static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1608{
d828199e
MT		 1609 /* checked again under seqlock below */
1610 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1611 return false;
1612
cbcf2dd3 1613 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1614}
1615#endif
1616
1617/*
1618 *
b48aa97e
MT		 1619 * Assuming a stable TSC across physical CPUS, and a stable TSC
1620 * across virtual CPUs, the following condition is possible.
1621 * Each numbered line represents an event visible to both
d828199e
MT		 1622 * CPUs at the next numbered event.
1623 *
1624 * "timespecX" represents host monotonic time. "tscX" represents
1625 * RDTSC value.
1626 *
1627 * VCPU0 on CPU0 | VCPU1 on CPU1
1628 *
1629 * 1. read timespec0,tsc0
1630 * 2. | timespec1 = timespec0 + N
1631 * | tsc1 = tsc0 + M
1632 * 3. transition to guest | transition to guest
1633 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1634 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1635 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1636 *
1637 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1638 *
1639 * - ret0 < ret1
1640 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1641 * ...
1642 * - 0 < N - M => M < N
1643 *
1644 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1645 * always the case (the difference between two distinct xtime instances
1646 * might be smaller then the difference between corresponding TSC reads,
1647 * when updating guest vcpus pvclock areas).
1648 *
1649 * To avoid that problem, do not allow visibility of distinct
1650 * system_timestamp/tsc_timestamp values simultaneously: use a master
1651 * copy of host monotonic time values. Update that master copy
1652 * in lockstep.
1653 *
b48aa97e 1654 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1655 *
1656 */
1657
1658static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1659{
1660#ifdef CONFIG_X86_64
1661 struct kvm_arch *ka = &kvm->arch;
1662 int vclock_mode;
b48aa97e
MT		 1663 bool host_tsc_clocksource, vcpus_matched;
1664
1665 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1666 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1667
1668 /*
1669 * If the host uses TSC clock, then passthrough TSC as stable
1670 * to the guest.
1671 */
b48aa97e 1672 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1673 &ka->master_kernel_ns,
1674 &ka->master_cycle_now);
1675
16a96021 1676 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1677 && !backwards_tsc_observed
1678 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1679
d828199e
MT		 1680 if (ka->use_master_clock)
1681 atomic_set(&kvm_guest_has_master_clock, 1);
1682
1683 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1684 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1685 vcpus_matched);
d828199e
MT		 1686#endif
1687}
1688
2e762ff7
MT		 1689static void kvm_gen_update_masterclock(struct kvm *kvm)
1690{
1691#ifdef CONFIG_X86_64
1692 int i;
1693 struct kvm_vcpu *vcpu;
1694 struct kvm_arch *ka = &kvm->arch;
1695
1696 spin_lock(&ka->pvclock_gtod_sync_lock);
1697 kvm_make_mclock_inprogress_request(kvm);
1698 /* no guest entries from this point */
1699 pvclock_update_vm_gtod_copy(kvm);
1700
1701 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1702 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1703
1704 /* guest entries allowed */
1705 kvm_for_each_vcpu(i, vcpu, kvm)
1706 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1707
1708 spin_unlock(&ka->pvclock_gtod_sync_lock);
1709#endif
1710}
1711
34c238a1 1712static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1713{
27cca94e 1714 unsigned long flags, this_tsc_khz, tgt_tsc_khz;
18068523 1715 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1716 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1717 s64 kernel_ns;
d828199e 1718 u64 tsc_timestamp, host_tsc;
0b79459b 1719 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1720 u8 pvclock_flags;
d828199e
MT		 1721 bool use_master_clock;
1722
1723 kernel_ns = 0;
1724 host_tsc = 0;
18068523 1725
d828199e
MT		 1726 /*
1727 * If the host uses TSC clock, then passthrough TSC as stable
1728 * to the guest.
1729 */
1730 spin_lock(&ka->pvclock_gtod_sync_lock);
1731 use_master_clock = ka->use_master_clock;
1732 if (use_master_clock) {
1733 host_tsc = ka->master_cycle_now;
1734 kernel_ns = ka->master_kernel_ns;
1735 }
1736 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1737
1738 /* Keep irq disabled to prevent changes to the clock */
1739 local_irq_save(flags);
89cbc767 1740 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1741 if (unlikely(this_tsc_khz == 0)) {
1742 local_irq_restore(flags);
1743 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1744 return 1;
1745 }
d828199e 1746 if (!use_master_clock) {
4ea1636b 1747 host_tsc = rdtsc();
d828199e
MT		 1748 kernel_ns = get_kernel_ns();
1749 }
1750
4ba76538 1751 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1752
c285545f
ZA		 1753 /*
1754 * We may have to catch up the TSC to match elapsed wall clock
1755 * time for two reasons, even if kvmclock is used.
1756 * 1) CPU could have been running below the maximum TSC rate
1757 * 2) Broken TSC compensation resets the base at each VCPU
1758 * entry to avoid unknown leaps of TSC even when running
1759 * again on the same CPU. This may cause apparent elapsed
1760 * time to disappear, and the guest to stand still or run
1761 * very slowly.
1762 */
1763 if (vcpu->tsc_catchup) {
1764 u64 tsc = compute_guest_tsc(v, kernel_ns);
1765 if (tsc > tsc_timestamp) {
f1e2b260 1766 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1767 tsc_timestamp = tsc;
1768 }
50d0a0f9
GH		 1769 }
1770
18068523
GOC		 1771 local_irq_restore(flags);
1772
0b79459b 1773 if (!vcpu->pv_time_enabled)
c285545f 1774 return 0;
18068523 1775
e48672fa 1776 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
27cca94e
HZ		 1777 tgt_tsc_khz = kvm_has_tsc_control ?
1778 vcpu->virtual_tsc_khz : this_tsc_khz;
1779 kvm_get_time_scale(NSEC_PER_SEC / 1000, tgt_tsc_khz,
5f4e3f88
ZA		 1780 &vcpu->hv_clock.tsc_shift,
1781 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1782 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1783 }
1784
1785 /* With all the info we got, fill in the values */
1d5f066e 1786 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1787 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1788 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1789
09a0c3f1
OH		 1790 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1791 &guest_hv_clock, sizeof(guest_hv_clock))))
1792 return 0;
1793
5dca0d91
RK		 1794 /* This VCPU is paused, but it's legal for a guest to read another
1795 * VCPU's kvmclock, so we really have to follow the specification where
1796 * it says that version is odd if data is being modified, and even after
1797 * it is consistent.
1798 *
1799 * Version field updates must be kept separate. This is because
1800 * kvm_write_guest_cached might use a "rep movs" instruction, and
1801 * writes within a string instruction are weakly ordered. So there
1802 * are three writes overall.
1803 *
1804 * As a small optimization, only write the version field in the first
1805 * and third write. The vcpu->pv_time cache is still valid, because the
1806 * version field is the first in the struct.
18068523 1807 */
5dca0d91
RK		 1808 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1809
1810 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1811 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1812 &vcpu->hv_clock,
1813 sizeof(vcpu->hv_clock.version));
1814
1815 smp_wmb();
78c0337a
MT		 1816
1817 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1818 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1819
1820 if (vcpu->pvclock_set_guest_stopped_request) {
1821 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1822 vcpu->pvclock_set_guest_stopped_request = false;
1823 }
1824
d828199e
MT		 1825 /* If the host uses TSC clocksource, then it is stable */
1826 if (use_master_clock)
1827 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1828
78c0337a
MT		 1829 vcpu->hv_clock.flags = pvclock_flags;
1830
ce1a5e60
DM		 1831 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1832
0b79459b
AH		 1833 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1834 &vcpu->hv_clock,
1835 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1836
1837 smp_wmb();
1838
1839 vcpu->hv_clock.version++;
1840 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1841 &vcpu->hv_clock,
1842 sizeof(vcpu->hv_clock.version));
8cfdc000 1843 return 0;
c8076604
GH		 1844}
1845
0061d53d
MT		 1846/*
1847 * kvmclock updates which are isolated to a given vcpu, such as
1848 * vcpu->cpu migration, should not allow system_timestamp from
1849 * the rest of the vcpus to remain static. Otherwise ntp frequency
1850 * correction applies to one vcpu's system_timestamp but not
1851 * the others.
1852 *
1853 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1854 * We need to rate-limit these requests though, as they can
1855 * considerably slow guests that have a large number of vcpus.
1856 * The time for a remote vcpu to update its kvmclock is bound
1857 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1858 */
1859
7e44e449
AJ		 1860#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1861
1862static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1863{
1864 int i;
7e44e449
AJ		 1865 struct delayed_work *dwork = to_delayed_work(work);
1866 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1867 kvmclock_update_work);
1868 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1869 struct kvm_vcpu *vcpu;
1870
1871 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1872 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1873 kvm_vcpu_kick(vcpu);
1874 }
1875}
1876
7e44e449
AJ		 1877static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1878{
1879 struct kvm *kvm = v->kvm;
1880
105b21bb 1881 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1882 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1883 KVMCLOCK_UPDATE_DELAY);
1884}
1885
332967a3
AJ		 1886#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1887
1888static void kvmclock_sync_fn(struct work_struct *work)
1889{
1890 struct delayed_work *dwork = to_delayed_work(work);
1891 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1892 kvmclock_sync_work);
1893 struct kvm *kvm = container_of(ka, struct kvm, arch);
1894
630994b3
MT		 1895 if (!kvmclock_periodic_sync)
1896 return;
1897
332967a3
AJ		 1898 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1899 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1900 KVMCLOCK_SYNC_PERIOD);
1901}
1902
890ca9ae 1903static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1904{
890ca9ae
HY		 1905 u64 mcg_cap = vcpu->arch.mcg_cap;
1906 unsigned bank_num = mcg_cap & 0xff;
1907
15c4a640 1908 switch (msr) {
15c4a640 1909 case MSR_IA32_MCG_STATUS:
890ca9ae 1910 vcpu->arch.mcg_status = data;
15c4a640 1911 break;
c7ac679c 1912 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1913 if (!(mcg_cap & MCG_CTL_P))
1914 return 1;
1915 if (data != 0 && data != ~(u64)0)
1916 return -1;
1917 vcpu->arch.mcg_ctl = data;
1918 break;
1919 default:
1920 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1921 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1922 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1923 /* only 0 or all 1s can be written to IA32_MCi_CTL
1924 * some Linux kernels though clear bit 10 in bank 4 to
1925 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1926 * this to avoid an uncatched #GP in the guest
1927 */
890ca9ae 1928 if ((offset & 0x3) == 0 &&
114be429 1929 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1930 return -1;
1931 vcpu->arch.mce_banks[offset] = data;
1932 break;
1933 }
1934 return 1;
1935 }
1936 return 0;
1937}
1938
ffde22ac
ES		 1939static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1940{
1941 struct kvm *kvm = vcpu->kvm;
1942 int lm = is_long_mode(vcpu);
1943 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1944 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1945 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1946 : kvm->arch.xen_hvm_config.blob_size_32;
1947 u32 page_num = data & ~PAGE_MASK;
1948 u64 page_addr = data & PAGE_MASK;
1949 u8 *page;
1950 int r;
1951
1952 r = -E2BIG;
1953 if (page_num >= blob_size)
1954 goto out;
1955 r = -ENOMEM;
ff5c2c03
SL		 1956 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1957 if (IS_ERR(page)) {
1958 r = PTR_ERR(page);
ffde22ac 1959 goto out;
ff5c2c03 1960 }
54bf36aa 1961 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1962 goto out_free;
1963 r = 0;
1964out_free:
1965 kfree(page);
1966out:
1967 return r;
1968}
1969
344d9588
GN		 1970static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1971{
1972 gpa_t gpa = data & ~0x3f;
1973
4a969980 1974 /* Bits 2:5 are reserved, Should be zero */
6adba527 1975 if (data & 0x3c)
344d9588
GN		 1976 return 1;
1977
1978 vcpu->arch.apf.msr_val = data;
1979
1980 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1981 kvm_clear_async_pf_completion_queue(vcpu);
1982 kvm_async_pf_hash_reset(vcpu);
1983 return 0;
1984 }
1985
8f964525
AH		 1986 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1987 sizeof(u32)))
344d9588
GN		 1988 return 1;
1989
6adba527 1990 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1991 kvm_async_pf_wakeup_all(vcpu);
1992 return 0;
1993}
1994
12f9a48f
GC		 1995static void kvmclock_reset(struct kvm_vcpu *vcpu)
1996{
0b79459b 1997 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1998}
1999
c9aaa895
GC		 2000static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2001{
2002 u64 delta;
2003
2004 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2005 return;
2006
2007 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2008 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2009 vcpu->arch.st.accum_steal = delta;
2010}
2011
2012static void record_steal_time(struct kvm_vcpu *vcpu)
2013{
7cae2bed
MT		 2014 accumulate_steal_time(vcpu);
2015
c9aaa895
GC		 2016 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2017 return;
2018
2019 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2020 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2021 return;
2022
2023 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2024 vcpu->arch.st.steal.version += 2;
2025 vcpu->arch.st.accum_steal = 0;
2026
2027 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2028 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2029}
2030
8fe8ab46 2031int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2032{
5753785f 2033 bool pr = false;
8fe8ab46
WA		 2034 u32 msr = msr_info->index;
2035 u64 data = msr_info->data;
5753785f 2036
15c4a640 2037 switch (msr) {
2e32b719
BP		 2038 case MSR_AMD64_NB_CFG:
2039 case MSR_IA32_UCODE_REV:
2040 case MSR_IA32_UCODE_WRITE:
2041 case MSR_VM_HSAVE_PA:
2042 case MSR_AMD64_PATCH_LOADER:
2043 case MSR_AMD64_BU_CFG2:
2044 break;
2045
15c4a640 2046 case MSR_EFER:
b69e8cae 2047 return set_efer(vcpu, data);
8f1589d9
AP		 2048 case MSR_K7_HWCR:
2049 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2050 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2051 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2052 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2053 if (data != 0) {
a737f256
CD		 2054 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2055 data);
8f1589d9
AP		 2056 return 1;
2057 }
15c4a640 2058 break;
f7c6d140
AP		 2059 case MSR_FAM10H_MMIO_CONF_BASE:
2060 if (data != 0) {
a737f256
CD		 2061 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2062 "0x%llx\n", data);
f7c6d140
AP		 2063 return 1;
2064 }
15c4a640 2065 break;
b5e2fec0
AG		 2066 case MSR_IA32_DEBUGCTLMSR:
2067 if (!data) {
2068 /* We support the non-activated case already */
2069 break;
2070 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2071 /* Values other than LBR and BTF are vendor-specific,
2072 thus reserved and should throw a #GP */
2073 return 1;
2074 }
a737f256
CD		 2075 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2076 __func__, data);
b5e2fec0 2077 break;
9ba075a6 2078 case 0x200 ... 0x2ff:
ff53604b 2079 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2080 case MSR_IA32_APICBASE:
58cb628d 2081 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2082 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2083 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2084 case MSR_IA32_TSCDEADLINE:
2085 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2086 break;
ba904635
WA		 2087 case MSR_IA32_TSC_ADJUST:
2088 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2089 if (!msr_info->host_initiated) {
d913b904 2090 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2091 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2092 }
2093 vcpu->arch.ia32_tsc_adjust_msr = data;
2094 }
2095 break;
15c4a640 2096 case MSR_IA32_MISC_ENABLE:
ad312c7c 2097 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2098 break;
64d60670
PB		 2099 case MSR_IA32_SMBASE:
2100 if (!msr_info->host_initiated)
2101 return 1;
2102 vcpu->arch.smbase = data;
2103 break;
11c6bffa 2104 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2105 case MSR_KVM_WALL_CLOCK:
2106 vcpu->kvm->arch.wall_clock = data;
2107 kvm_write_wall_clock(vcpu->kvm, data);
2108 break;
11c6bffa 2109 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2110 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2111 u64 gpa_offset;
54750f2c
MT		 2112 struct kvm_arch *ka = &vcpu->kvm->arch;
2113
12f9a48f 2114 kvmclock_reset(vcpu);
18068523 2115
54750f2c
MT		 2116 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2117 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2118
2119 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2120 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2121 &vcpu->requests);
2122
2123 ka->boot_vcpu_runs_old_kvmclock = tmp;
2124 }
2125
18068523 2126 vcpu->arch.time = data;
0061d53d 2127 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2128
2129 /* we verify if the enable bit is set... */
2130 if (!(data & 1))
2131 break;
2132
0b79459b 2133 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2134
0b79459b 2135 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2136 &vcpu->arch.pv_time, data & ~1ULL,
2137 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2138 vcpu->arch.pv_time_enabled = false;
2139 else
2140 vcpu->arch.pv_time_enabled = true;
32cad84f 2141
18068523
GOC		 2142 break;
2143 }
344d9588
GN		 2144 case MSR_KVM_ASYNC_PF_EN:
2145 if (kvm_pv_enable_async_pf(vcpu, data))
2146 return 1;
2147 break;
c9aaa895
GC		 2148 case MSR_KVM_STEAL_TIME:
2149
2150 if (unlikely(!sched_info_on()))
2151 return 1;
2152
2153 if (data & KVM_STEAL_RESERVED_MASK)
2154 return 1;
2155
2156 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2157 data & KVM_STEAL_VALID_BITS,
2158 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2159 return 1;
2160
2161 vcpu->arch.st.msr_val = data;
2162
2163 if (!(data & KVM_MSR_ENABLED))
2164 break;
2165
c9aaa895
GC		 2166 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2167
2168 break;
ae7a2a3f
MT		 2169 case MSR_KVM_PV_EOI_EN:
2170 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2171 return 1;
2172 break;
c9aaa895 2173
890ca9ae
HY		 2174 case MSR_IA32_MCG_CTL:
2175 case MSR_IA32_MCG_STATUS:
81760dcc 2176 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2177 return set_msr_mce(vcpu, msr, data);
71db6023 2178
6912ac32
WH		 2179 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2180 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2181 pr = true; /* fall through */
2182 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2183 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2184 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2185 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2186
2187 if (pr || data != 0)
a737f256
CD		 2188 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2189 "0x%x data 0x%llx\n", msr, data);
5753785f 2190 break;
84e0cefa
JS		 2191 case MSR_K7_CLK_CTL:
2192 /*
2193 * Ignore all writes to this no longer documented MSR.
2194 * Writes are only relevant for old K7 processors,
2195 * all pre-dating SVM, but a recommended workaround from
4a969980 2196 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2197 * affected processor models on the command line, hence
2198 * the need to ignore the workaround.
2199 */
2200 break;
55cd8e5a 2201 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2202 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2203 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2204 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2205 return kvm_hv_set_msr_common(vcpu, msr, data,
2206 msr_info->host_initiated);
91c9c3ed 2207 case MSR_IA32_BBL_CR_CTL3:
2208 /* Drop writes to this legacy MSR -- see rdmsr
2209 * counterpart for further detail.
2210 */
a737f256 2211 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2212 break;
2b036c6b
BO		 2213 case MSR_AMD64_OSVW_ID_LENGTH:
2214 if (!guest_cpuid_has_osvw(vcpu))
2215 return 1;
2216 vcpu->arch.osvw.length = data;
2217 break;
2218 case MSR_AMD64_OSVW_STATUS:
2219 if (!guest_cpuid_has_osvw(vcpu))
2220 return 1;
2221 vcpu->arch.osvw.status = data;
2222 break;
15c4a640 2223 default:
ffde22ac
ES		 2224 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2225 return xen_hvm_config(vcpu, data);
c6702c9d 2226 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2227 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2228 if (!ignore_msrs) {
a737f256
CD		 2229 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2230 msr, data);
ed85c068
AP		 2231 return 1;
2232 } else {
a737f256
CD		 2233 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2234 msr, data);
ed85c068
AP		 2235 break;
2236 }
15c4a640
CO		 2237 }
2238 return 0;
2239}
2240EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2241
2242
2243/*
2244 * Reads an msr value (of 'msr_index') into 'pdata'.
2245 * Returns 0 on success, non-0 otherwise.
2246 * Assumes vcpu_load() was already called.
2247 */
609e36d3 2248int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2249{
609e36d3 2250 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2251}
ff651cb6 2252EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2253
890ca9ae 2254static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2255{
2256 u64 data;
890ca9ae
HY		 2257 u64 mcg_cap = vcpu->arch.mcg_cap;
2258 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2259
2260 switch (msr) {
15c4a640
CO		 2261 case MSR_IA32_P5_MC_ADDR:
2262 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2263 data = 0;
2264 break;
15c4a640 2265 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2266 data = vcpu->arch.mcg_cap;
2267 break;
c7ac679c 2268 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2269 if (!(mcg_cap & MCG_CTL_P))
2270 return 1;
2271 data = vcpu->arch.mcg_ctl;
2272 break;
2273 case MSR_IA32_MCG_STATUS:
2274 data = vcpu->arch.mcg_status;
2275 break;
2276 default:
2277 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2278 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2279 u32 offset = msr - MSR_IA32_MC0_CTL;
2280 data = vcpu->arch.mce_banks[offset];
2281 break;
2282 }
2283 return 1;
2284 }
2285 *pdata = data;
2286 return 0;
2287}
2288
609e36d3 2289int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2290{
609e36d3 2291 switch (msr_info->index) {
890ca9ae 2292 case MSR_IA32_PLATFORM_ID:
15c4a640 2293 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2294 case MSR_IA32_DEBUGCTLMSR:
2295 case MSR_IA32_LASTBRANCHFROMIP:
2296 case MSR_IA32_LASTBRANCHTOIP:
2297 case MSR_IA32_LASTINTFROMIP:
2298 case MSR_IA32_LASTINTTOIP:
60af2ecd 2299 case MSR_K8_SYSCFG:
3afb1121
PB		 2300 case MSR_K8_TSEG_ADDR:
2301 case MSR_K8_TSEG_MASK:
60af2ecd 2302 case MSR_K7_HWCR:
61a6bd67 2303 case MSR_VM_HSAVE_PA:
1fdbd48c 2304 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2305 case MSR_AMD64_NB_CFG:
f7c6d140 2306 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2307 case MSR_AMD64_BU_CFG2:
609e36d3 2308 msr_info->data = 0;
15c4a640 2309 break;
6912ac32
WH		 2310 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2311 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2312 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2313 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2314 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2315 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2316 msr_info->data = 0;
5753785f 2317 break;
742bc670 2318 case MSR_IA32_UCODE_REV:
609e36d3 2319 msr_info->data = 0x100000000ULL;
742bc670 2320 break;
9ba075a6 2321 case MSR_MTRRcap:
9ba075a6 2322 case 0x200 ... 0x2ff:
ff53604b 2323 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2324 case 0xcd: /* fsb frequency */
609e36d3 2325 msr_info->data = 3;
15c4a640 2326 break;
7b914098
JS		 2327 /*
2328 * MSR_EBC_FREQUENCY_ID
2329 * Conservative value valid for even the basic CPU models.
2330 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2331 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2332 * and 266MHz for model 3, or 4. Set Core Clock
2333 * Frequency to System Bus Frequency Ratio to 1 (bits
2334 * 31:24) even though these are only valid for CPU
2335 * models > 2, however guests may end up dividing or
2336 * multiplying by zero otherwise.
2337 */
2338 case MSR_EBC_FREQUENCY_ID:
609e36d3 2339 msr_info->data = 1 << 24;
7b914098 2340 break;
15c4a640 2341 case MSR_IA32_APICBASE:
609e36d3 2342 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2343 break;
0105d1a5 2344 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2345 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2346 break;
a3e06bbe 2347 case MSR_IA32_TSCDEADLINE:
609e36d3 2348 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2349 break;
ba904635 2350 case MSR_IA32_TSC_ADJUST:
609e36d3 2351 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2352 break;
15c4a640 2353 case MSR_IA32_MISC_ENABLE:
609e36d3 2354 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2355 break;
64d60670
PB		 2356 case MSR_IA32_SMBASE:
2357 if (!msr_info->host_initiated)
2358 return 1;
2359 msr_info->data = vcpu->arch.smbase;
15c4a640 2360 break;
847f0ad8
AG		 2361 case MSR_IA32_PERF_STATUS:
2362 /* TSC increment by tick */
609e36d3 2363 msr_info->data = 1000ULL;
847f0ad8 2364 /* CPU multiplier */
b0996ae4 2365 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2366 break;
15c4a640 2367 case MSR_EFER:
609e36d3 2368 msr_info->data = vcpu->arch.efer;
15c4a640 2369 break;
18068523 2370 case MSR_KVM_WALL_CLOCK:
11c6bffa 2371 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2372 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2373 break;
2374 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2375 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2376 msr_info->data = vcpu->arch.time;
18068523 2377 break;
344d9588 2378 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2379 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2380 break;
c9aaa895 2381 case MSR_KVM_STEAL_TIME:
609e36d3 2382 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2383 break;
1d92128f 2384 case MSR_KVM_PV_EOI_EN:
609e36d3 2385 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2386 break;
890ca9ae
HY		 2387 case MSR_IA32_P5_MC_ADDR:
2388 case MSR_IA32_P5_MC_TYPE:
2389 case MSR_IA32_MCG_CAP:
2390 case MSR_IA32_MCG_CTL:
2391 case MSR_IA32_MCG_STATUS:
81760dcc 2392 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2393 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2394 case MSR_K7_CLK_CTL:
2395 /*
2396 * Provide expected ramp-up count for K7. All other
2397 * are set to zero, indicating minimum divisors for
2398 * every field.
2399 *
2400 * This prevents guest kernels on AMD host with CPU
2401 * type 6, model 8 and higher from exploding due to
2402 * the rdmsr failing.
2403 */
609e36d3 2404 msr_info->data = 0x20000000;
84e0cefa 2405 break;
55cd8e5a 2406 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2407 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2408 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2409 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2410 return kvm_hv_get_msr_common(vcpu,
2411 msr_info->index, &msr_info->data);
55cd8e5a 2412 break;
91c9c3ed 2413 case MSR_IA32_BBL_CR_CTL3:
2414 /* This legacy MSR exists but isn't fully documented in current
2415 * silicon. It is however accessed by winxp in very narrow
2416 * scenarios where it sets bit #19, itself documented as
2417 * a "reserved" bit. Best effort attempt to source coherent
2418 * read data here should the balance of the register be
2419 * interpreted by the guest:
2420 *
2421 * L2 cache control register 3: 64GB range, 256KB size,
2422 * enabled, latency 0x1, configured
2423 */
609e36d3 2424 msr_info->data = 0xbe702111;
91c9c3ed 2425 break;
2b036c6b
BO		 2426 case MSR_AMD64_OSVW_ID_LENGTH:
2427 if (!guest_cpuid_has_osvw(vcpu))
2428 return 1;
609e36d3 2429 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2430 break;
2431 case MSR_AMD64_OSVW_STATUS:
2432 if (!guest_cpuid_has_osvw(vcpu))
2433 return 1;
609e36d3 2434 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2435 break;
15c4a640 2436 default:
c6702c9d 2437 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2438 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2439 if (!ignore_msrs) {
609e36d3 2440 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2441 return 1;
2442 } else {
609e36d3
PB		 2443 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2444 msr_info->data = 0;
ed85c068
AP		 2445 }
2446 break;
15c4a640 2447 }
15c4a640
CO		 2448 return 0;
2449}
2450EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2451
313a3dc7
CO		 2452/*
2453 * Read or write a bunch of msrs. All parameters are kernel addresses.
2454 *
2455 * @return number of msrs set successfully.
2456 */
2457static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2458 struct kvm_msr_entry *entries,
2459 int (*do_msr)(struct kvm_vcpu *vcpu,
2460 unsigned index, u64 *data))
2461{
f656ce01 2462 int i, idx;
313a3dc7 2463
f656ce01 2464 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2465 for (i = 0; i < msrs->nmsrs; ++i)
2466 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2467 break;
f656ce01 2468 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2469
313a3dc7
CO		 2470 return i;
2471}
2472
2473/*
2474 * Read or write a bunch of msrs. Parameters are user addresses.
2475 *
2476 * @return number of msrs set successfully.
2477 */
2478static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2479 int (*do_msr)(struct kvm_vcpu *vcpu,
2480 unsigned index, u64 *data),
2481 int writeback)
2482{
2483 struct kvm_msrs msrs;
2484 struct kvm_msr_entry *entries;
2485 int r, n;
2486 unsigned size;
2487
2488 r = -EFAULT;
2489 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2490 goto out;
2491
2492 r = -E2BIG;
2493 if (msrs.nmsrs >= MAX_IO_MSRS)
2494 goto out;
2495
313a3dc7 2496 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2497 entries = memdup_user(user_msrs->entries, size);
2498 if (IS_ERR(entries)) {
2499 r = PTR_ERR(entries);
313a3dc7 2500 goto out;
ff5c2c03 2501 }
313a3dc7
CO		 2502
2503 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2504 if (r < 0)
2505 goto out_free;
2506
2507 r = -EFAULT;
2508 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2509 goto out_free;
2510
2511 r = n;
2512
2513out_free:
7a73c028 2514 kfree(entries);
313a3dc7
CO		 2515out:
2516 return r;
2517}
2518
784aa3d7 2519int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2520{
2521 int r;
2522
2523 switch (ext) {
2524 case KVM_CAP_IRQCHIP:
2525 case KVM_CAP_HLT:
2526 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2527 case KVM_CAP_SET_TSS_ADDR:
07716717 2528 case KVM_CAP_EXT_CPUID:
9c15bb1d 2529 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2530 case KVM_CAP_CLOCKSOURCE:
7837699f 2531 case KVM_CAP_PIT:
a28e4f5a 2532 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2533 case KVM_CAP_MP_STATE:
ed848624 2534 case KVM_CAP_SYNC_MMU:
a355c85c 2535 case KVM_CAP_USER_NMI:
52d939a0 2536 case KVM_CAP_REINJECT_CONTROL:
4925663a 2537 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2538 case KVM_CAP_IOEVENTFD:
f848a5a8 2539 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2540 case KVM_CAP_PIT2:
e9f42757 2541 case KVM_CAP_PIT_STATE2:
b927a3ce 2542 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2543 case KVM_CAP_XEN_HVM:
afbcf7ab 2544 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2545 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2546 case KVM_CAP_HYPERV:
10388a07 2547 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2548 case KVM_CAP_HYPERV_SPIN:
5c919412 2549 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2550 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2551 case KVM_CAP_DEBUGREGS:
d2be1651 2552 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2553 case KVM_CAP_XSAVE:
344d9588 2554 case KVM_CAP_ASYNC_PF:
92a1f12d 2555 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2556 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2557 case KVM_CAP_READONLY_MEM:
5f66b620 2558 case KVM_CAP_HYPERV_TIME:
100943c5 2559 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2560 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2561 case KVM_CAP_ENABLE_CAP_VM:
2562 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2563 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2564 case KVM_CAP_SPLIT_IRQCHIP:
2a5bab10
AW		 2565#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2566 case KVM_CAP_ASSIGN_DEV_IRQ:
2567 case KVM_CAP_PCI_2_3:
2568#endif
018d00d2
ZX		 2569 r = 1;
2570 break;
6d396b55
PB		 2571 case KVM_CAP_X86_SMM:
2572 /* SMBASE is usually relocated above 1M on modern chipsets,
2573 * and SMM handlers might indeed rely on 4G segment limits,
2574 * so do not report SMM to be available if real mode is
2575 * emulated via vm86 mode. Still, do not go to great lengths
2576 * to avoid userspace's usage of the feature, because it is a
2577 * fringe case that is not enabled except via specific settings
2578 * of the module parameters.
2579 */
2580 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2581 break;
542472b5
LV		 2582 case KVM_CAP_COALESCED_MMIO:
2583 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2584 break;
774ead3a
AK		 2585 case KVM_CAP_VAPIC:
2586 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2587 break;
f725230a 2588 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2589 r = KVM_SOFT_MAX_VCPUS;
2590 break;
2591 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2592 r = KVM_MAX_VCPUS;
2593 break;
a988b910 2594 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2595 r = KVM_USER_MEM_SLOTS;
a988b910 2596 break;
a68a6a72
MT		 2597 case KVM_CAP_PV_MMU: /* obsolete */
2598 r = 0;
2f333bcb 2599 break;
4cee4b72 2600#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2601 case KVM_CAP_IOMMU:
a1b60c1c 2602 r = iommu_present(&pci_bus_type);
62c476c7 2603 break;
4cee4b72 2604#endif
890ca9ae
HY		 2605 case KVM_CAP_MCE:
2606 r = KVM_MAX_MCE_BANKS;
2607 break;
2d5b5a66
SY		 2608 case KVM_CAP_XCRS:
2609 r = cpu_has_xsave;
2610 break;
92a1f12d
JR		 2611 case KVM_CAP_TSC_CONTROL:
2612 r = kvm_has_tsc_control;
2613 break;
018d00d2
ZX		 2614 default:
2615 r = 0;
2616 break;
2617 }
2618 return r;
2619
2620}
2621
043405e1
CO		 2622long kvm_arch_dev_ioctl(struct file *filp,
2623 unsigned int ioctl, unsigned long arg)
2624{
2625 void __user *argp = (void __user *)arg;
2626 long r;
2627
2628 switch (ioctl) {
2629 case KVM_GET_MSR_INDEX_LIST: {
2630 struct kvm_msr_list __user *user_msr_list = argp;
2631 struct kvm_msr_list msr_list;
2632 unsigned n;
2633
2634 r = -EFAULT;
2635 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2636 goto out;
2637 n = msr_list.nmsrs;
62ef68bb 2638 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2639 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2640 goto out;
2641 r = -E2BIG;
e125e7b6 2642 if (n < msr_list.nmsrs)
043405e1
CO		 2643 goto out;
2644 r = -EFAULT;
2645 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2646 num_msrs_to_save * sizeof(u32)))
2647 goto out;
e125e7b6 2648 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2649 &emulated_msrs,
62ef68bb 2650 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2651 goto out;
2652 r = 0;
2653 break;
2654 }
9c15bb1d
BP		 2655 case KVM_GET_SUPPORTED_CPUID:
2656 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2657 struct kvm_cpuid2 __user *cpuid_arg = argp;
2658 struct kvm_cpuid2 cpuid;
2659
2660 r = -EFAULT;
2661 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2662 goto out;
9c15bb1d
BP		 2663
2664 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2665 ioctl);
674eea0f
AK		 2666 if (r)
2667 goto out;
2668
2669 r = -EFAULT;
2670 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2671 goto out;
2672 r = 0;
2673 break;
2674 }
890ca9ae
HY		 2675 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2676 u64 mce_cap;
2677
2678 mce_cap = KVM_MCE_CAP_SUPPORTED;
2679 r = -EFAULT;
2680 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2681 goto out;
2682 r = 0;
2683 break;
2684 }
043405e1
CO		 2685 default:
2686 r = -EINVAL;
2687 }
2688out:
2689 return r;
2690}
2691
f5f48ee1
SY		 2692static void wbinvd_ipi(void *garbage)
2693{
2694 wbinvd();
2695}
2696
2697static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2698{
e0f0bbc5 2699 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2700}
2701
313a3dc7
CO		 2702void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2703{
f5f48ee1
SY		 2704 /* Address WBINVD may be executed by guest */
2705 if (need_emulate_wbinvd(vcpu)) {
2706 if (kvm_x86_ops->has_wbinvd_exit())
2707 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2708 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2709 smp_call_function_single(vcpu->cpu,
2710 wbinvd_ipi, NULL, 1);
2711 }
2712
313a3dc7 2713 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2714
0dd6a6ed
ZA		 2715 /* Apply any externally detected TSC adjustments (due to suspend) */
2716 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2717 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2718 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2719 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2720 }
8f6055cb 2721
48434c20 2722 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2723 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2724 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2725 if (tsc_delta < 0)
2726 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2727 if (check_tsc_unstable()) {
07c1419a 2728 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58
ZA		 2729 vcpu->arch.last_guest_tsc);
2730 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2731 vcpu->arch.tsc_catchup = 1;
c285545f 2732 }
d98d07ca
MT		 2733 /*
2734 * On a host with synchronized TSC, there is no need to update
2735 * kvmclock on vcpu->cpu migration
2736 */
2737 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2738 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2739 if (vcpu->cpu != cpu)
2740 kvm_migrate_timers(vcpu);
e48672fa 2741 vcpu->cpu = cpu;
6b7d7e76 2742 }
c9aaa895 2743
c9aaa895 2744 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2745}
2746
2747void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2748{
02daab21 2749 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2750 kvm_put_guest_fpu(vcpu);
4ea1636b 2751 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2752}
2753
313a3dc7
CO		 2754static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2755 struct kvm_lapic_state *s)
2756{
d62caabb
AS		 2757 if (vcpu->arch.apicv_active)
2758 kvm_x86_ops->sync_pir_to_irr(vcpu);
2759
ad312c7c 2760 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2761
2762 return 0;
2763}
2764
2765static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2766 struct kvm_lapic_state *s)
2767{
64eb0620 2768 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2769 update_cr8_intercept(vcpu);
313a3dc7
CO		 2770
2771 return 0;
2772}
2773
127a457a
MG		 2774static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2775{
2776 return (!lapic_in_kernel(vcpu) ||
2777 kvm_apic_accept_pic_intr(vcpu));
2778}
2779
782d422b
MG		 2780/*
2781 * if userspace requested an interrupt window, check that the
2782 * interrupt window is open.
2783 *
2784 * No need to exit to userspace if we already have an interrupt queued.
2785 */
2786static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2787{
2788 return kvm_arch_interrupt_allowed(vcpu) &&
2789 !kvm_cpu_has_interrupt(vcpu) &&
2790 !kvm_event_needs_reinjection(vcpu) &&
2791 kvm_cpu_accept_dm_intr(vcpu);
2792}
2793
f77bc6a4
ZX		 2794static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2795 struct kvm_interrupt *irq)
2796{
02cdb50f 2797 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2798 return -EINVAL;
1c1a9ce9
SR		 2799
2800 if (!irqchip_in_kernel(vcpu->kvm)) {
2801 kvm_queue_interrupt(vcpu, irq->irq, false);
2802 kvm_make_request(KVM_REQ_EVENT, vcpu);
2803 return 0;
2804 }
2805
2806 /*
2807 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2808 * fail for in-kernel 8259.
2809 */
2810 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2811 return -ENXIO;
f77bc6a4 2812
1c1a9ce9
SR		 2813 if (vcpu->arch.pending_external_vector != -1)
2814 return -EEXIST;
f77bc6a4 2815
1c1a9ce9 2816 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2817 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2818 return 0;
2819}
2820
c4abb7c9
JK		 2821static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2822{
c4abb7c9 2823 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2824
2825 return 0;
2826}
2827
f077825a
PB		 2828static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2829{
64d60670
PB		 2830 kvm_make_request(KVM_REQ_SMI, vcpu);
2831
f077825a
PB		 2832 return 0;
2833}
2834
b209749f
AK		 2835static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2836 struct kvm_tpr_access_ctl *tac)
2837{
2838 if (tac->flags)
2839 return -EINVAL;
2840 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2841 return 0;
2842}
2843
890ca9ae
HY		 2844static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2845 u64 mcg_cap)
2846{
2847 int r;
2848 unsigned bank_num = mcg_cap & 0xff, bank;
2849
2850 r = -EINVAL;
a9e38c3e 2851 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2852 goto out;
2853 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2854 goto out;
2855 r = 0;
2856 vcpu->arch.mcg_cap = mcg_cap;
2857 /* Init IA32_MCG_CTL to all 1s */
2858 if (mcg_cap & MCG_CTL_P)
2859 vcpu->arch.mcg_ctl = ~(u64)0;
2860 /* Init IA32_MCi_CTL to all 1s */
2861 for (bank = 0; bank < bank_num; bank++)
2862 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2863out:
2864 return r;
2865}
2866
2867static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2868 struct kvm_x86_mce *mce)
2869{
2870 u64 mcg_cap = vcpu->arch.mcg_cap;
2871 unsigned bank_num = mcg_cap & 0xff;
2872 u64 *banks = vcpu->arch.mce_banks;
2873
2874 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2875 return -EINVAL;
2876 /*
2877 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2878 * reporting is disabled
2879 */
2880 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2881 vcpu->arch.mcg_ctl != ~(u64)0)
2882 return 0;
2883 banks += 4 * mce->bank;
2884 /*
2885 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2886 * reporting is disabled for the bank
2887 */
2888 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2889 return 0;
2890 if (mce->status & MCI_STATUS_UC) {
2891 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2892 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2893 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2894 return 0;
2895 }
2896 if (banks[1] & MCI_STATUS_VAL)
2897 mce->status |= MCI_STATUS_OVER;
2898 banks[2] = mce->addr;
2899 banks[3] = mce->misc;
2900 vcpu->arch.mcg_status = mce->mcg_status;
2901 banks[1] = mce->status;
2902 kvm_queue_exception(vcpu, MC_VECTOR);
2903 } else if (!(banks[1] & MCI_STATUS_VAL)
2904 || !(banks[1] & MCI_STATUS_UC)) {
2905 if (banks[1] & MCI_STATUS_VAL)
2906 mce->status |= MCI_STATUS_OVER;
2907 banks[2] = mce->addr;
2908 banks[3] = mce->misc;
2909 banks[1] = mce->status;
2910 } else
2911 banks[1] |= MCI_STATUS_OVER;
2912 return 0;
2913}
2914
3cfc3092
JK		 2915static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2916 struct kvm_vcpu_events *events)
2917{
7460fb4a 2918 process_nmi(vcpu);
03b82a30
JK		 2919 events->exception.injected =
2920 vcpu->arch.exception.pending &&
2921 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2922 events->exception.nr = vcpu->arch.exception.nr;
2923 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2924 events->exception.pad = 0;
3cfc3092
JK		 2925 events->exception.error_code = vcpu->arch.exception.error_code;
2926
03b82a30
JK		 2927 events->interrupt.injected =
2928 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2929 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2930 events->interrupt.soft = 0;
37ccdcbe 2931 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 2932
2933 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2934 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2935 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2936 events->nmi.pad = 0;
3cfc3092 2937
66450a21 2938 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2939
f077825a
PB		 2940 events->smi.smm = is_smm(vcpu);
2941 events->smi.pending = vcpu->arch.smi_pending;
2942 events->smi.smm_inside_nmi =
2943 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
2944 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
2945
dab4b911 2946 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 2947 | KVM_VCPUEVENT_VALID_SHADOW
2948 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 2949 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2950}
2951
2952static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2953 struct kvm_vcpu_events *events)
2954{
dab4b911 2955 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2956 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 2957 | KVM_VCPUEVENT_VALID_SHADOW
2958 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 2959 return -EINVAL;
2960
7460fb4a 2961 process_nmi(vcpu);
3cfc3092
JK		 2962 vcpu->arch.exception.pending = events->exception.injected;
2963 vcpu->arch.exception.nr = events->exception.nr;
2964 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2965 vcpu->arch.exception.error_code = events->exception.error_code;
2966
2967 vcpu->arch.interrupt.pending = events->interrupt.injected;
2968 vcpu->arch.interrupt.nr = events->interrupt.nr;
2969 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2970 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2971 kvm_x86_ops->set_interrupt_shadow(vcpu,
2972 events->interrupt.shadow);
3cfc3092
JK		 2973
2974 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2975 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2976 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2977 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2978
66450a21
JK		 2979 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2980 kvm_vcpu_has_lapic(vcpu))
2981 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2982
f077825a
PB		 2983 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
2984 if (events->smi.smm)
2985 vcpu->arch.hflags |= HF_SMM_MASK;
2986 else
2987 vcpu->arch.hflags &= ~HF_SMM_MASK;
2988 vcpu->arch.smi_pending = events->smi.pending;
2989 if (events->smi.smm_inside_nmi)
2990 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
2991 else
2992 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
2993 if (kvm_vcpu_has_lapic(vcpu)) {
2994 if (events->smi.latched_init)
2995 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2996 else
2997 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
2998 }
2999 }
3000
3842d135
AK		 3001 kvm_make_request(KVM_REQ_EVENT, vcpu);
3002
3cfc3092
JK		 3003 return 0;
3004}
3005
a1efbe77
JK		 3006static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3007 struct kvm_debugregs *dbgregs)
3008{
73aaf249
JK		 3009 unsigned long val;
3010
a1efbe77 3011 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3012 kvm_get_dr(vcpu, 6, &val);
73aaf249 3013 dbgregs->dr6 = val;
a1efbe77
JK		 3014 dbgregs->dr7 = vcpu->arch.dr7;
3015 dbgregs->flags = 0;
97e69aa6 3016 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3017}
3018
3019static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3020 struct kvm_debugregs *dbgregs)
3021{
3022 if (dbgregs->flags)
3023 return -EINVAL;
3024
a1efbe77 3025 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3026 kvm_update_dr0123(vcpu);
a1efbe77 3027 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3028 kvm_update_dr6(vcpu);
a1efbe77 3029 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3030 kvm_update_dr7(vcpu);
a1efbe77 3031
a1efbe77
JK		 3032 return 0;
3033}
3034
df1daba7
PB		 3035#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3036
3037static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3038{
c47ada30 3039 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3040 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3041 u64 valid;
3042
3043 /*
3044 * Copy legacy XSAVE area, to avoid complications with CPUID
3045 * leaves 0 and 1 in the loop below.
3046 */
3047 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3048
3049 /* Set XSTATE_BV */
3050 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3051
3052 /*
3053 * Copy each region from the possibly compacted offset to the
3054 * non-compacted offset.
3055 */
d91cab78 3056 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3057 while (valid) {
3058 u64 feature = valid & -valid;
3059 int index = fls64(feature) - 1;
3060 void *src = get_xsave_addr(xsave, feature);
3061
3062 if (src) {
3063 u32 size, offset, ecx, edx;
3064 cpuid_count(XSTATE_CPUID, index,
3065 &size, &offset, &ecx, &edx);
3066 memcpy(dest + offset, src, size);
3067 }
3068
3069 valid -= feature;
3070 }
3071}
3072
3073static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3074{
c47ada30 3075 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3076 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3077 u64 valid;
3078
3079 /*
3080 * Copy legacy XSAVE area, to avoid complications with CPUID
3081 * leaves 0 and 1 in the loop below.
3082 */
3083 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3084
3085 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3086 xsave->header.xfeatures = xstate_bv;
df1daba7 3087 if (cpu_has_xsaves)
3a54450b 3088 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3089
3090 /*
3091 * Copy each region from the non-compacted offset to the
3092 * possibly compacted offset.
3093 */
d91cab78 3094 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3095 while (valid) {
3096 u64 feature = valid & -valid;
3097 int index = fls64(feature) - 1;
3098 void *dest = get_xsave_addr(xsave, feature);
3099
3100 if (dest) {
3101 u32 size, offset, ecx, edx;
3102 cpuid_count(XSTATE_CPUID, index,
3103 &size, &offset, &ecx, &edx);
3104 memcpy(dest, src + offset, size);
ee4100da 3105 }
df1daba7
PB		 3106
3107 valid -= feature;
3108 }
3109}
3110
2d5b5a66
SY		 3111static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3112 struct kvm_xsave *guest_xsave)
3113{
4344ee98 3114 if (cpu_has_xsave) {
df1daba7
PB		 3115 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3116 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3117 } else {
2d5b5a66 3118 memcpy(guest_xsave->region,
7366ed77 3119 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3120 sizeof(struct fxregs_state));
2d5b5a66 3121 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3122 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3123 }
3124}
3125
3126static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3127 struct kvm_xsave *guest_xsave)
3128{
3129 u64 xstate_bv =
3130 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3131
d7876f1b
PB		 3132 if (cpu_has_xsave) {
3133 /*
3134 * Here we allow setting states that are not present in
3135 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3136 * with old userspace.
3137 */
4ff41732 3138 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3139 return -EINVAL;
df1daba7 3140 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3141 } else {
d91cab78 3142 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3143 return -EINVAL;
7366ed77 3144 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3145 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3146 }
3147 return 0;
3148}
3149
3150static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3151 struct kvm_xcrs *guest_xcrs)
3152{
3153 if (!cpu_has_xsave) {
3154 guest_xcrs->nr_xcrs = 0;
3155 return;
3156 }
3157
3158 guest_xcrs->nr_xcrs = 1;
3159 guest_xcrs->flags = 0;
3160 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3161 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3162}
3163
3164static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3165 struct kvm_xcrs *guest_xcrs)
3166{
3167 int i, r = 0;
3168
3169 if (!cpu_has_xsave)
3170 return -EINVAL;
3171
3172 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3173 return -EINVAL;
3174
3175 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3176 /* Only support XCR0 currently */
c67a04cb 3177 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3178 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3179 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3180 break;
3181 }
3182 if (r)
3183 r = -EINVAL;
3184 return r;
3185}
3186
1c0b28c2
EM		 3187/*
3188 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3189 * stopped by the hypervisor. This function will be called from the host only.
3190 * EINVAL is returned when the host attempts to set the flag for a guest that
3191 * does not support pv clocks.
3192 */
3193static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3194{
0b79459b 3195 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3196 return -EINVAL;
51d59c6b 3197 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3198 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3199 return 0;
3200}
3201
5c919412
AS		 3202static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3203 struct kvm_enable_cap *cap)
3204{
3205 if (cap->flags)
3206 return -EINVAL;
3207
3208 switch (cap->cap) {
3209 case KVM_CAP_HYPERV_SYNIC:
3210 return kvm_hv_activate_synic(vcpu);
3211 default:
3212 return -EINVAL;
3213 }
3214}
3215
313a3dc7
CO		 3216long kvm_arch_vcpu_ioctl(struct file *filp,
3217 unsigned int ioctl, unsigned long arg)
3218{
3219 struct kvm_vcpu *vcpu = filp->private_data;
3220 void __user *argp = (void __user *)arg;
3221 int r;
d1ac91d8
AK		 3222 union {
3223 struct kvm_lapic_state *lapic;
3224 struct kvm_xsave *xsave;
3225 struct kvm_xcrs *xcrs;
3226 void *buffer;
3227 } u;
3228
3229 u.buffer = NULL;
313a3dc7
CO		 3230 switch (ioctl) {
3231 case KVM_GET_LAPIC: {
2204ae3c
MT		 3232 r = -EINVAL;
3233 if (!vcpu->arch.apic)
3234 goto out;
d1ac91d8 3235 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3236
b772ff36 3237 r = -ENOMEM;
d1ac91d8 3238 if (!u.lapic)
b772ff36 3239 goto out;
d1ac91d8 3240 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3241 if (r)
3242 goto out;
3243 r = -EFAULT;
d1ac91d8 3244 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3245 goto out;
3246 r = 0;
3247 break;
3248 }
3249 case KVM_SET_LAPIC: {
2204ae3c
MT		 3250 r = -EINVAL;
3251 if (!vcpu->arch.apic)
3252 goto out;
ff5c2c03 3253 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3254 if (IS_ERR(u.lapic))
3255 return PTR_ERR(u.lapic);
ff5c2c03 3256
d1ac91d8 3257 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3258 break;
3259 }
f77bc6a4
ZX		 3260 case KVM_INTERRUPT: {
3261 struct kvm_interrupt irq;
3262
3263 r = -EFAULT;
3264 if (copy_from_user(&irq, argp, sizeof irq))
3265 goto out;
3266 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3267 break;
3268 }
c4abb7c9
JK		 3269 case KVM_NMI: {
3270 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3271 break;
3272 }
f077825a
PB		 3273 case KVM_SMI: {
3274 r = kvm_vcpu_ioctl_smi(vcpu);
3275 break;
3276 }
313a3dc7
CO		 3277 case KVM_SET_CPUID: {
3278 struct kvm_cpuid __user *cpuid_arg = argp;
3279 struct kvm_cpuid cpuid;
3280
3281 r = -EFAULT;
3282 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3283 goto out;
3284 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3285 break;
3286 }
07716717
DK		 3287 case KVM_SET_CPUID2: {
3288 struct kvm_cpuid2 __user *cpuid_arg = argp;
3289 struct kvm_cpuid2 cpuid;
3290
3291 r = -EFAULT;
3292 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3293 goto out;
3294 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3295 cpuid_arg->entries);
07716717
DK		 3296 break;
3297 }
3298 case KVM_GET_CPUID2: {
3299 struct kvm_cpuid2 __user *cpuid_arg = argp;
3300 struct kvm_cpuid2 cpuid;
3301
3302 r = -EFAULT;
3303 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3304 goto out;
3305 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3306 cpuid_arg->entries);
07716717
DK		 3307 if (r)
3308 goto out;
3309 r = -EFAULT;
3310 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3311 goto out;
3312 r = 0;
3313 break;
3314 }
313a3dc7 3315 case KVM_GET_MSRS:
609e36d3 3316 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3317 break;
3318 case KVM_SET_MSRS:
3319 r = msr_io(vcpu, argp, do_set_msr, 0);
3320 break;
b209749f
AK		 3321 case KVM_TPR_ACCESS_REPORTING: {
3322 struct kvm_tpr_access_ctl tac;
3323
3324 r = -EFAULT;
3325 if (copy_from_user(&tac, argp, sizeof tac))
3326 goto out;
3327 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3328 if (r)
3329 goto out;
3330 r = -EFAULT;
3331 if (copy_to_user(argp, &tac, sizeof tac))
3332 goto out;
3333 r = 0;
3334 break;
3335 };
b93463aa
AK		 3336 case KVM_SET_VAPIC_ADDR: {
3337 struct kvm_vapic_addr va;
3338
3339 r = -EINVAL;
35754c98 3340 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3341 goto out;
3342 r = -EFAULT;
3343 if (copy_from_user(&va, argp, sizeof va))
3344 goto out;
fda4e2e8 3345 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3346 break;
3347 }
890ca9ae
HY		 3348 case KVM_X86_SETUP_MCE: {
3349 u64 mcg_cap;
3350
3351 r = -EFAULT;
3352 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3353 goto out;
3354 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3355 break;
3356 }
3357 case KVM_X86_SET_MCE: {
3358 struct kvm_x86_mce mce;
3359
3360 r = -EFAULT;
3361 if (copy_from_user(&mce, argp, sizeof mce))
3362 goto out;
3363 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3364 break;
3365 }
3cfc3092
JK		 3366 case KVM_GET_VCPU_EVENTS: {
3367 struct kvm_vcpu_events events;
3368
3369 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3370
3371 r = -EFAULT;
3372 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3373 break;
3374 r = 0;
3375 break;
3376 }
3377 case KVM_SET_VCPU_EVENTS: {
3378 struct kvm_vcpu_events events;
3379
3380 r = -EFAULT;
3381 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3382 break;
3383
3384 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3385 break;
3386 }
a1efbe77
JK		 3387 case KVM_GET_DEBUGREGS: {
3388 struct kvm_debugregs dbgregs;
3389
3390 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3391
3392 r = -EFAULT;
3393 if (copy_to_user(argp, &dbgregs,
3394 sizeof(struct kvm_debugregs)))
3395 break;
3396 r = 0;
3397 break;
3398 }
3399 case KVM_SET_DEBUGREGS: {
3400 struct kvm_debugregs dbgregs;
3401
3402 r = -EFAULT;
3403 if (copy_from_user(&dbgregs, argp,
3404 sizeof(struct kvm_debugregs)))
3405 break;
3406
3407 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3408 break;
3409 }
2d5b5a66 3410 case KVM_GET_XSAVE: {
d1ac91d8 3411 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3412 r = -ENOMEM;
d1ac91d8 3413 if (!u.xsave)
2d5b5a66
SY		 3414 break;
3415
d1ac91d8 3416 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3417
3418 r = -EFAULT;
d1ac91d8 3419 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3420 break;
3421 r = 0;
3422 break;
3423 }
3424 case KVM_SET_XSAVE: {
ff5c2c03 3425 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3426 if (IS_ERR(u.xsave))
3427 return PTR_ERR(u.xsave);
2d5b5a66 3428
d1ac91d8 3429 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3430 break;
3431 }
3432 case KVM_GET_XCRS: {
d1ac91d8 3433 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3434 r = -ENOMEM;
d1ac91d8 3435 if (!u.xcrs)
2d5b5a66
SY		 3436 break;
3437
d1ac91d8 3438 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3439
3440 r = -EFAULT;
d1ac91d8 3441 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3442 sizeof(struct kvm_xcrs)))
3443 break;
3444 r = 0;
3445 break;
3446 }
3447 case KVM_SET_XCRS: {
ff5c2c03 3448 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3449 if (IS_ERR(u.xcrs))
3450 return PTR_ERR(u.xcrs);
2d5b5a66 3451
d1ac91d8 3452 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3453 break;
3454 }
92a1f12d
JR		 3455 case KVM_SET_TSC_KHZ: {
3456 u32 user_tsc_khz;
3457
3458 r = -EINVAL;
92a1f12d
JR		 3459 user_tsc_khz = (u32)arg;
3460
3461 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3462 goto out;
3463
cc578287
ZA		 3464 if (user_tsc_khz == 0)
3465 user_tsc_khz = tsc_khz;
3466
381d585c
HZ		 3467 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3468 r = 0;
92a1f12d 3469
92a1f12d
JR		 3470 goto out;
3471 }
3472 case KVM_GET_TSC_KHZ: {
cc578287 3473 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3474 goto out;
3475 }
1c0b28c2
EM		 3476 case KVM_KVMCLOCK_CTRL: {
3477 r = kvm_set_guest_paused(vcpu);
3478 goto out;
3479 }
5c919412
AS		 3480 case KVM_ENABLE_CAP: {
3481 struct kvm_enable_cap cap;
3482
3483 r = -EFAULT;
3484 if (copy_from_user(&cap, argp, sizeof(cap)))
3485 goto out;
3486 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3487 break;
3488 }
313a3dc7
CO		 3489 default:
3490 r = -EINVAL;
3491 }
3492out:
d1ac91d8 3493 kfree(u.buffer);
313a3dc7
CO		 3494 return r;
3495}
3496
5b1c1493
CO		 3497int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3498{
3499 return VM_FAULT_SIGBUS;
3500}
3501
1fe779f8
CO		 3502static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3503{
3504 int ret;
3505
3506 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3507 return -EINVAL;
1fe779f8
CO		 3508 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3509 return ret;
3510}
3511
b927a3ce
SY		 3512static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3513 u64 ident_addr)
3514{
3515 kvm->arch.ept_identity_map_addr = ident_addr;
3516 return 0;
3517}
3518
1fe779f8
CO		 3519static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3520 u32 kvm_nr_mmu_pages)
3521{
3522 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3523 return -EINVAL;
3524
79fac95e 3525 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3526
3527 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3528 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3529
79fac95e 3530 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3531 return 0;
3532}
3533
3534static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3535{
39de71ec 3536 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3537}
3538
1fe779f8
CO		 3539static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3540{
3541 int r;
3542
3543 r = 0;
3544 switch (chip->chip_id) {
3545 case KVM_IRQCHIP_PIC_MASTER:
3546 memcpy(&chip->chip.pic,
3547 &pic_irqchip(kvm)->pics[0],
3548 sizeof(struct kvm_pic_state));
3549 break;
3550 case KVM_IRQCHIP_PIC_SLAVE:
3551 memcpy(&chip->chip.pic,
3552 &pic_irqchip(kvm)->pics[1],
3553 sizeof(struct kvm_pic_state));
3554 break;
3555 case KVM_IRQCHIP_IOAPIC:
eba0226b 3556 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3557 break;
3558 default:
3559 r = -EINVAL;
3560 break;
3561 }
3562 return r;
3563}
3564
3565static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3566{
3567 int r;
3568
3569 r = 0;
3570 switch (chip->chip_id) {
3571 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3572 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3573 memcpy(&pic_irqchip(kvm)->pics[0],
3574 &chip->chip.pic,
3575 sizeof(struct kvm_pic_state));
f4f51050 3576 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3577 break;
3578 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3579 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3580 memcpy(&pic_irqchip(kvm)->pics[1],
3581 &chip->chip.pic,
3582 sizeof(struct kvm_pic_state));
f4f51050 3583 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3584 break;
3585 case KVM_IRQCHIP_IOAPIC:
eba0226b 3586 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3587 break;
3588 default:
3589 r = -EINVAL;
3590 break;
3591 }
3592 kvm_pic_update_irq(pic_irqchip(kvm));
3593 return r;
3594}
3595
e0f63cb9
SY		 3596static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3597{
894a9c55 3598 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3599 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3600 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3601 return 0;
e0f63cb9
SY		 3602}
3603
3604static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3605{
894a9c55 3606 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3607 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3608 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3609 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3610 return 0;
e9f42757
BK		 3611}
3612
3613static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3614{
e9f42757
BK		 3615 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3616 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3617 sizeof(ps->channels));
3618 ps->flags = kvm->arch.vpit->pit_state.flags;
3619 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3620 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3621 return 0;
e9f42757
BK		 3622}
3623
3624static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3625{
2da29bcc 3626 int start = 0;
e9f42757
BK		 3627 u32 prev_legacy, cur_legacy;
3628 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3629 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3630 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3631 if (!prev_legacy && cur_legacy)
3632 start = 1;
3633 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3634 sizeof(kvm->arch.vpit->pit_state.channels));
3635 kvm->arch.vpit->pit_state.flags = ps->flags;
3636 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3637 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2da29bcc 3638 return 0;
e0f63cb9
SY		 3639}
3640
52d939a0
MT		 3641static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3642 struct kvm_reinject_control *control)
3643{
3644 if (!kvm->arch.vpit)
3645 return -ENXIO;
894a9c55 3646 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3647 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3648 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3649 return 0;
3650}
3651
95d4c16c 3652/**
60c34612
TY		 3653 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3654 * @kvm: kvm instance
3655 * @log: slot id and address to which we copy the log
95d4c16c 3656 *
e108ff2f
PB		 3657 * Steps 1-4 below provide general overview of dirty page logging. See
3658 * kvm_get_dirty_log_protect() function description for additional details.
3659 *
3660 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3661 * always flush the TLB (step 4) even if previous step failed and the dirty
3662 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3663 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3664 * writes will be marked dirty for next log read.
95d4c16c 3665 *
60c34612
TY		 3666 * 1. Take a snapshot of the bit and clear it if needed.
3667 * 2. Write protect the corresponding page.
e108ff2f
PB		 3668 * 3. Copy the snapshot to the userspace.
3669 * 4. Flush TLB's if needed.
5bb064dc 3670 */
60c34612 3671int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3672{
60c34612 3673 bool is_dirty = false;
e108ff2f 3674 int r;
5bb064dc 3675
79fac95e 3676 mutex_lock(&kvm->slots_lock);
5bb064dc 3677
88178fd4
KH		 3678 /*
3679 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3680 */
3681 if (kvm_x86_ops->flush_log_dirty)
3682 kvm_x86_ops->flush_log_dirty(kvm);
3683
e108ff2f 3684 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3685
3686 /*
3687 * All the TLBs can be flushed out of mmu lock, see the comments in
3688 * kvm_mmu_slot_remove_write_access().
3689 */
e108ff2f 3690 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3691 if (is_dirty)
3692 kvm_flush_remote_tlbs(kvm);
3693
79fac95e 3694 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3695 return r;
3696}
3697
aa2fbe6d
YZ		 3698int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3699 bool line_status)
23d43cf9
CD		 3700{
3701 if (!irqchip_in_kernel(kvm))
3702 return -ENXIO;
3703
3704 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3705 irq_event->irq, irq_event->level,
3706 line_status);
23d43cf9
CD		 3707 return 0;
3708}
3709
90de4a18
NA		 3710static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3711 struct kvm_enable_cap *cap)
3712{
3713 int r;
3714
3715 if (cap->flags)
3716 return -EINVAL;
3717
3718 switch (cap->cap) {
3719 case KVM_CAP_DISABLE_QUIRKS:
3720 kvm->arch.disabled_quirks = cap->args[0];
3721 r = 0;
3722 break;
49df6397
SR		 3723 case KVM_CAP_SPLIT_IRQCHIP: {
3724 mutex_lock(&kvm->lock);
b053b2ae
SR		 3725 r = -EINVAL;
3726 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3727 goto split_irqchip_unlock;
49df6397
SR		 3728 r = -EEXIST;
3729 if (irqchip_in_kernel(kvm))
3730 goto split_irqchip_unlock;
3731 if (atomic_read(&kvm->online_vcpus))
3732 goto split_irqchip_unlock;
3733 r = kvm_setup_empty_irq_routing(kvm);
3734 if (r)
3735 goto split_irqchip_unlock;
3736 /* Pairs with irqchip_in_kernel. */
3737 smp_wmb();
3738 kvm->arch.irqchip_split = true;
b053b2ae 3739 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3740 r = 0;
3741split_irqchip_unlock:
3742 mutex_unlock(&kvm->lock);
3743 break;
3744 }
90de4a18
NA		 3745 default:
3746 r = -EINVAL;
3747 break;
3748 }
3749 return r;
3750}
3751
1fe779f8
CO		 3752long kvm_arch_vm_ioctl(struct file *filp,
3753 unsigned int ioctl, unsigned long arg)
3754{
3755 struct kvm *kvm = filp->private_data;
3756 void __user *argp = (void __user *)arg;
367e1319 3757 int r = -ENOTTY;
f0d66275
DH		 3758 /*
3759 * This union makes it completely explicit to gcc-3.x
3760 * that these two variables' stack usage should be
3761 * combined, not added together.
3762 */
3763 union {
3764 struct kvm_pit_state ps;
e9f42757 3765 struct kvm_pit_state2 ps2;
c5ff41ce 3766 struct kvm_pit_config pit_config;
f0d66275 3767 } u;
1fe779f8
CO		 3768
3769 switch (ioctl) {
3770 case KVM_SET_TSS_ADDR:
3771 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3772 break;
b927a3ce
SY		 3773 case KVM_SET_IDENTITY_MAP_ADDR: {
3774 u64 ident_addr;
3775
3776 r = -EFAULT;
3777 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3778 goto out;
3779 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3780 break;
3781 }
1fe779f8
CO		 3782 case KVM_SET_NR_MMU_PAGES:
3783 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3784 break;
3785 case KVM_GET_NR_MMU_PAGES:
3786 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3787 break;
3ddea128
MT		 3788 case KVM_CREATE_IRQCHIP: {
3789 struct kvm_pic *vpic;
3790
3791 mutex_lock(&kvm->lock);
3792 r = -EEXIST;
3793 if (kvm->arch.vpic)
3794 goto create_irqchip_unlock;
3e515705
AK		 3795 r = -EINVAL;
3796 if (atomic_read(&kvm->online_vcpus))
3797 goto create_irqchip_unlock;
1fe779f8 3798 r = -ENOMEM;
3ddea128
MT		 3799 vpic = kvm_create_pic(kvm);
3800 if (vpic) {
1fe779f8
CO		 3801 r = kvm_ioapic_init(kvm);
3802 if (r) {
175504cd 3803 mutex_lock(&kvm->slots_lock);
71ba994c 3804 kvm_destroy_pic(vpic);
175504cd 3805 mutex_unlock(&kvm->slots_lock);
3ddea128 3806 goto create_irqchip_unlock;
1fe779f8
CO		 3807 }
3808 } else
3ddea128 3809 goto create_irqchip_unlock;
399ec807
AK		 3810 r = kvm_setup_default_irq_routing(kvm);
3811 if (r) {
175504cd 3812 mutex_lock(&kvm->slots_lock);
3ddea128 3813 mutex_lock(&kvm->irq_lock);
72bb2fcd 3814 kvm_ioapic_destroy(kvm);
71ba994c 3815 kvm_destroy_pic(vpic);
3ddea128 3816 mutex_unlock(&kvm->irq_lock);
175504cd 3817 mutex_unlock(&kvm->slots_lock);
71ba994c 3818 goto create_irqchip_unlock;
399ec807 3819 }
71ba994c
PB		 3820 /* Write kvm->irq_routing before kvm->arch.vpic. */
3821 smp_wmb();
3822 kvm->arch.vpic = vpic;
3ddea128
MT		 3823 create_irqchip_unlock:
3824 mutex_unlock(&kvm->lock);
1fe779f8 3825 break;
3ddea128 3826 }
7837699f 3827 case KVM_CREATE_PIT:
c5ff41ce
JK		 3828 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3829 goto create_pit;
3830 case KVM_CREATE_PIT2:
3831 r = -EFAULT;
3832 if (copy_from_user(&u.pit_config, argp,
3833 sizeof(struct kvm_pit_config)))
3834 goto out;
3835 create_pit:
79fac95e 3836 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3837 r = -EEXIST;
3838 if (kvm->arch.vpit)
3839 goto create_pit_unlock;
7837699f 3840 r = -ENOMEM;
c5ff41ce 3841 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3842 if (kvm->arch.vpit)
3843 r = 0;
269e05e4 3844 create_pit_unlock:
79fac95e 3845 mutex_unlock(&kvm->slots_lock);
7837699f 3846 break;
1fe779f8
CO		 3847 case KVM_GET_IRQCHIP: {
3848 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3849 struct kvm_irqchip *chip;
1fe779f8 3850
ff5c2c03
SL		 3851 chip = memdup_user(argp, sizeof(*chip));
3852 if (IS_ERR(chip)) {
3853 r = PTR_ERR(chip);
1fe779f8 3854 goto out;
ff5c2c03
SL		 3855 }
3856
1fe779f8 3857 r = -ENXIO;
49df6397 3858 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3859 goto get_irqchip_out;
3860 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3861 if (r)
f0d66275 3862 goto get_irqchip_out;
1fe779f8 3863 r = -EFAULT;
f0d66275
DH		 3864 if (copy_to_user(argp, chip, sizeof *chip))
3865 goto get_irqchip_out;
1fe779f8 3866 r = 0;
f0d66275
DH		 3867 get_irqchip_out:
3868 kfree(chip);
1fe779f8
CO		 3869 break;
3870 }
3871 case KVM_SET_IRQCHIP: {
3872 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3873 struct kvm_irqchip *chip;
1fe779f8 3874
ff5c2c03
SL		 3875 chip = memdup_user(argp, sizeof(*chip));
3876 if (IS_ERR(chip)) {
3877 r = PTR_ERR(chip);
1fe779f8 3878 goto out;
ff5c2c03
SL		 3879 }
3880
1fe779f8 3881 r = -ENXIO;
49df6397 3882 if (!irqchip_in_kernel(kvm) || irqchip_split(kvm))
f0d66275
DH		 3883 goto set_irqchip_out;
3884 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3885 if (r)
f0d66275 3886 goto set_irqchip_out;
1fe779f8 3887 r = 0;
f0d66275
DH		 3888 set_irqchip_out:
3889 kfree(chip);
1fe779f8
CO		 3890 break;
3891 }
e0f63cb9 3892 case KVM_GET_PIT: {
e0f63cb9 3893 r = -EFAULT;
f0d66275 3894 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3895 goto out;
3896 r = -ENXIO;
3897 if (!kvm->arch.vpit)
3898 goto out;
f0d66275 3899 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3900 if (r)
3901 goto out;
3902 r = -EFAULT;
f0d66275 3903 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3904 goto out;
3905 r = 0;
3906 break;
3907 }
3908 case KVM_SET_PIT: {
e0f63cb9 3909 r = -EFAULT;
f0d66275 3910 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3911 goto out;
3912 r = -ENXIO;
3913 if (!kvm->arch.vpit)
3914 goto out;
f0d66275 3915 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3916 break;
3917 }
e9f42757
BK		 3918 case KVM_GET_PIT2: {
3919 r = -ENXIO;
3920 if (!kvm->arch.vpit)
3921 goto out;
3922 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3923 if (r)
3924 goto out;
3925 r = -EFAULT;
3926 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3927 goto out;
3928 r = 0;
3929 break;
3930 }
3931 case KVM_SET_PIT2: {
3932 r = -EFAULT;
3933 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3934 goto out;
3935 r = -ENXIO;
3936 if (!kvm->arch.vpit)
3937 goto out;
3938 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3939 break;
3940 }
52d939a0
MT		 3941 case KVM_REINJECT_CONTROL: {
3942 struct kvm_reinject_control control;
3943 r = -EFAULT;
3944 if (copy_from_user(&control, argp, sizeof(control)))
3945 goto out;
3946 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3947 break;
3948 }
d71ba788
PB		 3949 case KVM_SET_BOOT_CPU_ID:
3950 r = 0;
3951 mutex_lock(&kvm->lock);
3952 if (atomic_read(&kvm->online_vcpus) != 0)
3953 r = -EBUSY;
3954 else
3955 kvm->arch.bsp_vcpu_id = arg;
3956 mutex_unlock(&kvm->lock);
3957 break;
ffde22ac
ES		 3958 case KVM_XEN_HVM_CONFIG: {
3959 r = -EFAULT;
3960 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3961 sizeof(struct kvm_xen_hvm_config)))
3962 goto out;
3963 r = -EINVAL;
3964 if (kvm->arch.xen_hvm_config.flags)
3965 goto out;
3966 r = 0;
3967 break;
3968 }
afbcf7ab 3969 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3970 struct kvm_clock_data user_ns;
3971 u64 now_ns;
3972 s64 delta;
3973
3974 r = -EFAULT;
3975 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3976 goto out;
3977
3978 r = -EINVAL;
3979 if (user_ns.flags)
3980 goto out;
3981
3982 r = 0;
395c6b0a 3983 local_irq_disable();
759379dd 3984 now_ns = get_kernel_ns();
afbcf7ab 3985 delta = user_ns.clock - now_ns;
395c6b0a 3986 local_irq_enable();
afbcf7ab 3987 kvm->arch.kvmclock_offset = delta;
2e762ff7 3988 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3989 break;
3990 }
3991 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3992 struct kvm_clock_data user_ns;
3993 u64 now_ns;
3994
395c6b0a 3995 local_irq_disable();
759379dd 3996 now_ns = get_kernel_ns();
afbcf7ab 3997 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3998 local_irq_enable();
afbcf7ab 3999 user_ns.flags = 0;
97e69aa6 4000 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4001
4002 r = -EFAULT;
4003 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4004 goto out;
4005 r = 0;
4006 break;
4007 }
90de4a18
NA		 4008 case KVM_ENABLE_CAP: {
4009 struct kvm_enable_cap cap;
afbcf7ab 4010
90de4a18
NA		 4011 r = -EFAULT;
4012 if (copy_from_user(&cap, argp, sizeof(cap)))
4013 goto out;
4014 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4015 break;
4016 }
1fe779f8 4017 default:
c274e03a 4018 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4019 }
4020out:
4021 return r;
4022}
4023
a16b043c 4024static void kvm_init_msr_list(void)
043405e1
CO		 4025{
4026 u32 dummy[2];
4027 unsigned i, j;
4028
62ef68bb 4029 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4030 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4031 continue;
93c4adc7
PB		 4032
4033 /*
4034 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4035 * to the guests in some cases.
93c4adc7
PB		 4036 */
4037 switch (msrs_to_save[i]) {
4038 case MSR_IA32_BNDCFGS:
4039 if (!kvm_x86_ops->mpx_supported())
4040 continue;
4041 break;
9dbe6cf9
PB		 4042 case MSR_TSC_AUX:
4043 if (!kvm_x86_ops->rdtscp_supported())
4044 continue;
4045 break;
93c4adc7
PB		 4046 default:
4047 break;
4048 }
4049
043405e1
CO		 4050 if (j < i)
4051 msrs_to_save[j] = msrs_to_save[i];
4052 j++;
4053 }
4054 num_msrs_to_save = j;
62ef68bb
PB		 4055
4056 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4057 switch (emulated_msrs[i]) {
6d396b55
PB		 4058 case MSR_IA32_SMBASE:
4059 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4060 continue;
4061 break;
62ef68bb
PB		 4062 default:
4063 break;
4064 }
4065
4066 if (j < i)
4067 emulated_msrs[j] = emulated_msrs[i];
4068 j++;
4069 }
4070 num_emulated_msrs = j;
043405e1
CO		 4071}
4072
bda9020e
MT		 4073static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4074 const void *v)
bbd9b64e 4075{
70252a10
AK		 4076 int handled = 0;
4077 int n;
4078
4079 do {
4080 n = min(len, 8);
4081 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4082 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4083 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4084 break;
4085 handled += n;
4086 addr += n;
4087 len -= n;
4088 v += n;
4089 } while (len);
bbd9b64e 4090
70252a10 4091 return handled;
bbd9b64e
CO		 4092}
4093
bda9020e 4094static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4095{
70252a10
AK		 4096 int handled = 0;
4097 int n;
4098
4099 do {
4100 n = min(len, 8);
4101 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4102 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4103 addr, n, v))
4104 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4105 break;
4106 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4107 handled += n;
4108 addr += n;
4109 len -= n;
4110 v += n;
4111 } while (len);
bbd9b64e 4112
70252a10 4113 return handled;
bbd9b64e
CO		 4114}
4115
2dafc6c2
GN		 4116static void kvm_set_segment(struct kvm_vcpu *vcpu,
4117 struct kvm_segment *var, int seg)
4118{
4119 kvm_x86_ops->set_segment(vcpu, var, seg);
4120}
4121
4122void kvm_get_segment(struct kvm_vcpu *vcpu,
4123 struct kvm_segment *var, int seg)
4124{
4125 kvm_x86_ops->get_segment(vcpu, var, seg);
4126}
4127
54987b7a
PB		 4128gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4129 struct x86_exception *exception)
02f59dc9
JR		 4130{
4131 gpa_t t_gpa;
02f59dc9
JR		 4132
4133 BUG_ON(!mmu_is_nested(vcpu));
4134
4135 /* NPT walks are always user-walks */
4136 access |= PFERR_USER_MASK;
54987b7a 4137 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4138
4139 return t_gpa;
4140}
4141
ab9ae313
AK		 4142gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4143 struct x86_exception *exception)
1871c602
GN		 4144{
4145 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4146 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4147}
4148
ab9ae313
AK		 4149 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4150 struct x86_exception *exception)
1871c602
GN		 4151{
4152 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4153 access |= PFERR_FETCH_MASK;
ab9ae313 4154 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4155}
4156
ab9ae313
AK		 4157gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4158 struct x86_exception *exception)
1871c602
GN		 4159{
4160 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4161 access |= PFERR_WRITE_MASK;
ab9ae313 4162 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4163}
4164
4165/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4166gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4167 struct x86_exception *exception)
1871c602 4168{
ab9ae313 4169 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4170}
4171
4172static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4173 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4174 struct x86_exception *exception)
bbd9b64e
CO		 4175{
4176 void *data = val;
10589a46 4177 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4178
4179 while (bytes) {
14dfe855 4180 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4181 exception);
bbd9b64e 4182 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4183 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4184 int ret;
4185
bcc55cba 4186 if (gpa == UNMAPPED_GVA)
ab9ae313 4187 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4188 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4189 offset, toread);
10589a46 4190 if (ret < 0) {
c3cd7ffa 4191 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4192 goto out;
4193 }
bbd9b64e 4194
77c2002e
IE		 4195 bytes -= toread;
4196 data += toread;
4197 addr += toread;
bbd9b64e 4198 }
10589a46 4199out:
10589a46 4200 return r;
bbd9b64e 4201}
77c2002e 4202
1871c602 4203/* used for instruction fetching */
0f65dd70
AK		 4204static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4205 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4206 struct x86_exception *exception)
1871c602 4207{
0f65dd70 4208 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4209 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4210 unsigned offset;
4211 int ret;
0f65dd70 4212
44583cba
PB		 4213 /* Inline kvm_read_guest_virt_helper for speed. */
4214 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4215 exception);
4216 if (unlikely(gpa == UNMAPPED_GVA))
4217 return X86EMUL_PROPAGATE_FAULT;
4218
4219 offset = addr & (PAGE_SIZE-1);
4220 if (WARN_ON(offset + bytes > PAGE_SIZE))
4221 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4222 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4223 offset, bytes);
44583cba
PB		 4224 if (unlikely(ret < 0))
4225 return X86EMUL_IO_NEEDED;
4226
4227 return X86EMUL_CONTINUE;
1871c602
GN		 4228}
4229
064aea77 4230int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4231 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4232 struct x86_exception *exception)
1871c602 4233{
0f65dd70 4234 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4235 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4236
1871c602 4237 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4238 exception);
1871c602 4239}
064aea77 4240EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4241
0f65dd70
AK		 4242static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4243 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4244 struct x86_exception *exception)
1871c602 4245{
0f65dd70 4246 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4247 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4248}
4249
7a036a6f
RK		 4250static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4251 unsigned long addr, void *val, unsigned int bytes)
4252{
4253 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4254 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4255
4256 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4257}
4258
6a4d7550 4259int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4260 gva_t addr, void *val,
2dafc6c2 4261 unsigned int bytes,
bcc55cba 4262 struct x86_exception *exception)
77c2002e 4263{
0f65dd70 4264 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4265 void *data = val;
4266 int r = X86EMUL_CONTINUE;
4267
4268 while (bytes) {
14dfe855
JR		 4269 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4270 PFERR_WRITE_MASK,
ab9ae313 4271 exception);
77c2002e
IE		 4272 unsigned offset = addr & (PAGE_SIZE-1);
4273 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4274 int ret;
4275
bcc55cba 4276 if (gpa == UNMAPPED_GVA)
ab9ae313 4277 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4278 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4279 if (ret < 0) {
c3cd7ffa 4280 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4281 goto out;
4282 }
4283
4284 bytes -= towrite;
4285 data += towrite;
4286 addr += towrite;
4287 }
4288out:
4289 return r;
4290}
6a4d7550 4291EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4292
af7cc7d1
XG		 4293static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4294 gpa_t *gpa, struct x86_exception *exception,
4295 bool write)
4296{
97d64b78
AK		 4297 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4298 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4299
97d64b78 4300 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4301 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4302 vcpu->arch.access, access)) {
bebb106a
XG		 4303 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4304 (gva & (PAGE_SIZE - 1));
4f022648 4305 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4306 return 1;
4307 }
4308
af7cc7d1
XG		 4309 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4310
4311 if (*gpa == UNMAPPED_GVA)
4312 return -1;
4313
4314 /* For APIC access vmexit */
4315 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4316 return 1;
4317
4f022648
XG		 4318 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4319 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4320 return 1;
4f022648 4321 }
bebb106a 4322
af7cc7d1
XG		 4323 return 0;
4324}
4325
3200f405 4326int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4327 const void *val, int bytes)
bbd9b64e
CO		 4328{
4329 int ret;
4330
54bf36aa 4331 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4332 if (ret < 0)
bbd9b64e 4333 return 0;
f57f2ef5 4334 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4335 return 1;
4336}
4337
77d197b2
XG		 4338struct read_write_emulator_ops {
4339 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4340 int bytes);
4341 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4342 void *val, int bytes);
4343 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4344 int bytes, void *val);
4345 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4346 void *val, int bytes);
4347 bool write;
4348};
4349
4350static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4351{
4352 if (vcpu->mmio_read_completed) {
77d197b2 4353 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4354 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4355 vcpu->mmio_read_completed = 0;
4356 return 1;
4357 }
4358
4359 return 0;
4360}
4361
4362static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4363 void *val, int bytes)
4364{
54bf36aa 4365 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4366}
4367
4368static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4369 void *val, int bytes)
4370{
4371 return emulator_write_phys(vcpu, gpa, val, bytes);
4372}
4373
4374static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4375{
4376 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4377 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4378}
4379
4380static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4381 void *val, int bytes)
4382{
4383 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4384 return X86EMUL_IO_NEEDED;
4385}
4386
4387static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4388 void *val, int bytes)
4389{
f78146b0
AK		 4390 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4391
87da7e66 4392 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4393 return X86EMUL_CONTINUE;
4394}
4395
0fbe9b0b 4396static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4397 .read_write_prepare = read_prepare,
4398 .read_write_emulate = read_emulate,
4399 .read_write_mmio = vcpu_mmio_read,
4400 .read_write_exit_mmio = read_exit_mmio,
4401};
4402
0fbe9b0b 4403static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4404 .read_write_emulate = write_emulate,
4405 .read_write_mmio = write_mmio,
4406 .read_write_exit_mmio = write_exit_mmio,
4407 .write = true,
4408};
4409
22388a3c
XG		 4410static int emulator_read_write_onepage(unsigned long addr, void *val,
4411 unsigned int bytes,
4412 struct x86_exception *exception,
4413 struct kvm_vcpu *vcpu,
0fbe9b0b 4414 const struct read_write_emulator_ops *ops)
bbd9b64e 4415{
af7cc7d1
XG		 4416 gpa_t gpa;
4417 int handled, ret;
22388a3c 4418 bool write = ops->write;
f78146b0 4419 struct kvm_mmio_fragment *frag;
10589a46 4420
22388a3c 4421 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4422
af7cc7d1 4423 if (ret < 0)
bbd9b64e 4424 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4425
4426 /* For APIC access vmexit */
af7cc7d1 4427 if (ret)
bbd9b64e
CO		 4428 goto mmio;
4429
22388a3c 4430 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4431 return X86EMUL_CONTINUE;
4432
4433mmio:
4434 /*
4435 * Is this MMIO handled locally?
4436 */
22388a3c 4437 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4438 if (handled == bytes)
bbd9b64e 4439 return X86EMUL_CONTINUE;
bbd9b64e 4440
70252a10
AK		 4441 gpa += handled;
4442 bytes -= handled;
4443 val += handled;
4444
87da7e66
XG		 4445 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4446 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4447 frag->gpa = gpa;
4448 frag->data = val;
4449 frag->len = bytes;
f78146b0 4450 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4451}
4452
52eb5a6d
XL		 4453static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4454 unsigned long addr,
22388a3c
XG		 4455 void *val, unsigned int bytes,
4456 struct x86_exception *exception,
0fbe9b0b 4457 const struct read_write_emulator_ops *ops)
bbd9b64e 4458{
0f65dd70 4459 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4460 gpa_t gpa;
4461 int rc;
4462
4463 if (ops->read_write_prepare &&
4464 ops->read_write_prepare(vcpu, val, bytes))
4465 return X86EMUL_CONTINUE;
4466
4467 vcpu->mmio_nr_fragments = 0;
0f65dd70 4468
bbd9b64e
CO		 4469 /* Crossing a page boundary? */
4470 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4471 int now;
bbd9b64e
CO		 4472
4473 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4474 rc = emulator_read_write_onepage(addr, val, now, exception,
4475 vcpu, ops);
4476
bbd9b64e
CO		 4477 if (rc != X86EMUL_CONTINUE)
4478 return rc;
4479 addr += now;
bac15531
NA		 4480 if (ctxt->mode != X86EMUL_MODE_PROT64)
4481 addr = (u32)addr;
bbd9b64e
CO		 4482 val += now;
4483 bytes -= now;
4484 }
22388a3c 4485
f78146b0
AK		 4486 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4487 vcpu, ops);
4488 if (rc != X86EMUL_CONTINUE)
4489 return rc;
4490
4491 if (!vcpu->mmio_nr_fragments)
4492 return rc;
4493
4494 gpa = vcpu->mmio_fragments[0].gpa;
4495
4496 vcpu->mmio_needed = 1;
4497 vcpu->mmio_cur_fragment = 0;
4498
87da7e66 4499 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4500 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4501 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4502 vcpu->run->mmio.phys_addr = gpa;
4503
4504 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4505}
4506
4507static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4508 unsigned long addr,
4509 void *val,
4510 unsigned int bytes,
4511 struct x86_exception *exception)
4512{
4513 return emulator_read_write(ctxt, addr, val, bytes,
4514 exception, &read_emultor);
4515}
4516
52eb5a6d 4517static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4518 unsigned long addr,
4519 const void *val,
4520 unsigned int bytes,
4521 struct x86_exception *exception)
4522{
4523 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4524 exception, &write_emultor);
bbd9b64e 4525}
bbd9b64e 4526
daea3e73
AK		 4527#define CMPXCHG_TYPE(t, ptr, old, new) \
4528 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4529
4530#ifdef CONFIG_X86_64
4531# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4532#else
4533# define CMPXCHG64(ptr, old, new) \
9749a6c0 4534 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4535#endif
4536
0f65dd70
AK		 4537static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4538 unsigned long addr,
bbd9b64e
CO		 4539 const void *old,
4540 const void *new,
4541 unsigned int bytes,
0f65dd70 4542 struct x86_exception *exception)
bbd9b64e 4543{
0f65dd70 4544 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4545 gpa_t gpa;
4546 struct page *page;
4547 char *kaddr;
4548 bool exchanged;
2bacc55c 4549
daea3e73
AK		 4550 /* guests cmpxchg8b have to be emulated atomically */
4551 if (bytes > 8 || (bytes & (bytes - 1)))
4552 goto emul_write;
10589a46 4553
daea3e73 4554 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4555
daea3e73
AK		 4556 if (gpa == UNMAPPED_GVA ||
4557 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4558 goto emul_write;
2bacc55c 4559
daea3e73
AK		 4560 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4561 goto emul_write;
72dc67a6 4562
54bf36aa 4563 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4564 if (is_error_page(page))
c19b8bd6 4565 goto emul_write;
72dc67a6 4566
8fd75e12 4567 kaddr = kmap_atomic(page);
daea3e73
AK		 4568 kaddr += offset_in_page(gpa);
4569 switch (bytes) {
4570 case 1:
4571 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4572 break;
4573 case 2:
4574 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4575 break;
4576 case 4:
4577 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4578 break;
4579 case 8:
4580 exchanged = CMPXCHG64(kaddr, old, new);
4581 break;
4582 default:
4583 BUG();
2bacc55c 4584 }
8fd75e12 4585 kunmap_atomic(kaddr);
daea3e73
AK		 4586 kvm_release_page_dirty(page);
4587
4588 if (!exchanged)
4589 return X86EMUL_CMPXCHG_FAILED;
4590
54bf36aa 4591 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4592 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4593
4594 return X86EMUL_CONTINUE;
4a5f48f6 4595
3200f405 4596emul_write:
daea3e73 4597 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4598
0f65dd70 4599 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4600}
4601
cf8f70bf
GN		 4602static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4603{
4604 /* TODO: String I/O for in kernel device */
4605 int r;
4606
4607 if (vcpu->arch.pio.in)
e32edf4f 4608 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4609 vcpu->arch.pio.size, pd);
4610 else
e32edf4f 4611 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4612 vcpu->arch.pio.port, vcpu->arch.pio.size,
4613 pd);
4614 return r;
4615}
4616
6f6fbe98
XG		 4617static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4618 unsigned short port, void *val,
4619 unsigned int count, bool in)
cf8f70bf 4620{
cf8f70bf 4621 vcpu->arch.pio.port = port;
6f6fbe98 4622 vcpu->arch.pio.in = in;
7972995b 4623 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4624 vcpu->arch.pio.size = size;
4625
4626 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4627 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4628 return 1;
4629 }
4630
4631 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4632 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4633 vcpu->run->io.size = size;
4634 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4635 vcpu->run->io.count = count;
4636 vcpu->run->io.port = port;
4637
4638 return 0;
4639}
4640
6f6fbe98
XG		 4641static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4642 int size, unsigned short port, void *val,
4643 unsigned int count)
cf8f70bf 4644{
ca1d4a9e 4645 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4646 int ret;
ca1d4a9e 4647
6f6fbe98
XG		 4648 if (vcpu->arch.pio.count)
4649 goto data_avail;
cf8f70bf 4650
6f6fbe98
XG		 4651 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4652 if (ret) {
4653data_avail:
4654 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4655 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4656 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4657 return 1;
4658 }
4659
cf8f70bf
GN		 4660 return 0;
4661}
4662
6f6fbe98
XG		 4663static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4664 int size, unsigned short port,
4665 const void *val, unsigned int count)
4666{
4667 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4668
4669 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4670 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4671 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4672}
4673
bbd9b64e
CO		 4674static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4675{
4676 return kvm_x86_ops->get_segment_base(vcpu, seg);
4677}
4678
3cb16fe7 4679static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4680{
3cb16fe7 4681 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4682}
4683
5cb56059 4684int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4685{
4686 if (!need_emulate_wbinvd(vcpu))
4687 return X86EMUL_CONTINUE;
4688
4689 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4690 int cpu = get_cpu();
4691
4692 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4693 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4694 wbinvd_ipi, NULL, 1);
2eec7343 4695 put_cpu();
f5f48ee1 4696 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4697 } else
4698 wbinvd();
f5f48ee1
SY		 4699 return X86EMUL_CONTINUE;
4700}
5cb56059
JS		 4701
4702int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4703{
4704 kvm_x86_ops->skip_emulated_instruction(vcpu);
4705 return kvm_emulate_wbinvd_noskip(vcpu);
4706}
f5f48ee1
SY		 4707EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4708
5cb56059
JS		 4709
4710
bcaf5cc5
AK		 4711static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4712{
5cb56059 4713 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4714}
4715
52eb5a6d
XL		 4716static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4717 unsigned long *dest)
bbd9b64e 4718{
16f8a6f9 4719 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4720}
4721
52eb5a6d
XL		 4722static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4723 unsigned long value)
bbd9b64e 4724{
338dbc97 4725
717746e3 4726 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4727}
4728
52a46617 4729static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4730{
52a46617 4731 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4732}
4733
717746e3 4734static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4735{
717746e3 4736 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4737 unsigned long value;
4738
4739 switch (cr) {
4740 case 0:
4741 value = kvm_read_cr0(vcpu);
4742 break;
4743 case 2:
4744 value = vcpu->arch.cr2;
4745 break;
4746 case 3:
9f8fe504 4747 value = kvm_read_cr3(vcpu);
52a46617
GN		 4748 break;
4749 case 4:
4750 value = kvm_read_cr4(vcpu);
4751 break;
4752 case 8:
4753 value = kvm_get_cr8(vcpu);
4754 break;
4755 default:
a737f256 4756 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4757 return 0;
4758 }
4759
4760 return value;
4761}
4762
717746e3 4763static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4764{
717746e3 4765 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4766 int res = 0;
4767
52a46617
GN		 4768 switch (cr) {
4769 case 0:
49a9b07e 4770 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4771 break;
4772 case 2:
4773 vcpu->arch.cr2 = val;
4774 break;
4775 case 3:
2390218b 4776 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4777 break;
4778 case 4:
a83b29c6 4779 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4780 break;
4781 case 8:
eea1cff9 4782 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4783 break;
4784 default:
a737f256 4785 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4786 res = -1;
52a46617 4787 }
0f12244f
GN		 4788
4789 return res;
52a46617
GN		 4790}
4791
717746e3 4792static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4793{
717746e3 4794 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4795}
4796
4bff1e86 4797static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4798{
4bff1e86 4799 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4800}
4801
4bff1e86 4802static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4803{
4bff1e86 4804 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4805}
4806
1ac9d0cf
AK		 4807static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4808{
4809 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4810}
4811
4812static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4813{
4814 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4815}
4816
4bff1e86
AK		 4817static unsigned long emulator_get_cached_segment_base(
4818 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4819{
4bff1e86 4820 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4821}
4822
1aa36616
AK		 4823static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4824 struct desc_struct *desc, u32 *base3,
4825 int seg)
2dafc6c2
GN		 4826{
4827 struct kvm_segment var;
4828
4bff1e86 4829 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4830 *selector = var.selector;
2dafc6c2 4831
378a8b09
GN		 4832 if (var.unusable) {
4833 memset(desc, 0, sizeof(*desc));
2dafc6c2 4834 return false;
378a8b09 4835 }
2dafc6c2
GN		 4836
4837 if (var.g)
4838 var.limit >>= 12;
4839 set_desc_limit(desc, var.limit);
4840 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4841#ifdef CONFIG_X86_64
4842 if (base3)
4843 *base3 = var.base >> 32;
4844#endif
2dafc6c2
GN		 4845 desc->type = var.type;
4846 desc->s = var.s;
4847 desc->dpl = var.dpl;
4848 desc->p = var.present;
4849 desc->avl = var.avl;
4850 desc->l = var.l;
4851 desc->d = var.db;
4852 desc->g = var.g;
4853
4854 return true;
4855}
4856
1aa36616
AK		 4857static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4858 struct desc_struct *desc, u32 base3,
4859 int seg)
2dafc6c2 4860{
4bff1e86 4861 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4862 struct kvm_segment var;
4863
1aa36616 4864 var.selector = selector;
2dafc6c2 4865 var.base = get_desc_base(desc);
5601d05b
GN		 4866#ifdef CONFIG_X86_64
4867 var.base |= ((u64)base3) << 32;
4868#endif
2dafc6c2
GN		 4869 var.limit = get_desc_limit(desc);
4870 if (desc->g)
4871 var.limit = (var.limit << 12) | 0xfff;
4872 var.type = desc->type;
2dafc6c2
GN		 4873 var.dpl = desc->dpl;
4874 var.db = desc->d;
4875 var.s = desc->s;
4876 var.l = desc->l;
4877 var.g = desc->g;
4878 var.avl = desc->avl;
4879 var.present = desc->p;
4880 var.unusable = !var.present;
4881 var.padding = 0;
4882
4883 kvm_set_segment(vcpu, &var, seg);
4884 return;
4885}
4886
717746e3
AK		 4887static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4888 u32 msr_index, u64 *pdata)
4889{
609e36d3
PB		 4890 struct msr_data msr;
4891 int r;
4892
4893 msr.index = msr_index;
4894 msr.host_initiated = false;
4895 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4896 if (r)
4897 return r;
4898
4899 *pdata = msr.data;
4900 return 0;
717746e3
AK		 4901}
4902
4903static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4904 u32 msr_index, u64 data)
4905{
8fe8ab46
WA		 4906 struct msr_data msr;
4907
4908 msr.data = data;
4909 msr.index = msr_index;
4910 msr.host_initiated = false;
4911 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4912}
4913
64d60670
PB		 4914static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4915{
4916 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4917
4918 return vcpu->arch.smbase;
4919}
4920
4921static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4922{
4923 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4924
4925 vcpu->arch.smbase = smbase;
4926}
4927
67f4d428
NA		 4928static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4929 u32 pmc)
4930{
c6702c9d 4931 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 4932}
4933
222d21aa
AK		 4934static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4935 u32 pmc, u64 *pdata)
4936{
c6702c9d 4937 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 4938}
4939
6c3287f7
AK		 4940static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4941{
4942 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4943}
4944
5037f6f3
AK		 4945static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4946{
4947 preempt_disable();
5197b808 4948 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4949 /*
4950 * CR0.TS may reference the host fpu state, not the guest fpu state,
4951 * so it may be clear at this point.
4952 */
4953 clts();
4954}
4955
4956static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4957{
4958 preempt_enable();
4959}
4960
2953538e 4961static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4962 struct x86_instruction_info *info,
c4f035c6
AK		 4963 enum x86_intercept_stage stage)
4964{
2953538e 4965 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4966}
4967
0017f93a 4968static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4969 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4970{
0017f93a 4971 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4972}
4973
dd856efa
AK		 4974static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4975{
4976 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4977}
4978
4979static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4980{
4981 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4982}
4983
801806d9
NA		 4984static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
4985{
4986 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
4987}
4988
0225fb50 4989static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4990 .read_gpr = emulator_read_gpr,
4991 .write_gpr = emulator_write_gpr,
1871c602 4992 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4993 .write_std = kvm_write_guest_virt_system,
7a036a6f 4994 .read_phys = kvm_read_guest_phys_system,
1871c602 4995 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4996 .read_emulated = emulator_read_emulated,
4997 .write_emulated = emulator_write_emulated,
4998 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4999 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5000 .pio_in_emulated = emulator_pio_in_emulated,
5001 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5002 .get_segment = emulator_get_segment,
5003 .set_segment = emulator_set_segment,
5951c442 5004 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5005 .get_gdt = emulator_get_gdt,
160ce1f1 5006 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5007 .set_gdt = emulator_set_gdt,
5008 .set_idt = emulator_set_idt,
52a46617
GN		 5009 .get_cr = emulator_get_cr,
5010 .set_cr = emulator_set_cr,
9c537244 5011 .cpl = emulator_get_cpl,
35aa5375
GN		 5012 .get_dr = emulator_get_dr,
5013 .set_dr = emulator_set_dr,
64d60670
PB		 5014 .get_smbase = emulator_get_smbase,
5015 .set_smbase = emulator_set_smbase,
717746e3
AK		 5016 .set_msr = emulator_set_msr,
5017 .get_msr = emulator_get_msr,
67f4d428 5018 .check_pmc = emulator_check_pmc,
222d21aa 5019 .read_pmc = emulator_read_pmc,
6c3287f7 5020 .halt = emulator_halt,
bcaf5cc5 5021 .wbinvd = emulator_wbinvd,
d6aa1000 5022 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5023 .get_fpu = emulator_get_fpu,
5024 .put_fpu = emulator_put_fpu,
c4f035c6 5025 .intercept = emulator_intercept,
bdb42f5a 5026 .get_cpuid = emulator_get_cpuid,
801806d9 5027 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5028};
5029
95cb2295
GN		 5030static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5031{
37ccdcbe 5032 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5033 /*
5034 * an sti; sti; sequence only disable interrupts for the first
5035 * instruction. So, if the last instruction, be it emulated or
5036 * not, left the system with the INT_STI flag enabled, it
5037 * means that the last instruction is an sti. We should not
5038 * leave the flag on in this case. The same goes for mov ss
5039 */
37ccdcbe
PB		 5040 if (int_shadow & mask)
5041 mask = 0;
6addfc42 5042 if (unlikely(int_shadow || mask)) {
95cb2295 5043 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5044 if (!mask)
5045 kvm_make_request(KVM_REQ_EVENT, vcpu);
5046 }
95cb2295
GN		 5047}
5048
ef54bcfe 5049static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5050{
5051 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5052 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5053 return kvm_propagate_fault(vcpu, &ctxt->exception);
5054
5055 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5056 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5057 ctxt->exception.error_code);
54b8486f 5058 else
da9cb575 5059 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5060 return false;
54b8486f
GN		 5061}
5062
8ec4722d
MG		 5063static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5064{
adf52235 5065 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5066 int cs_db, cs_l;
5067
8ec4722d
MG		 5068 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5069
adf52235
TY		 5070 ctxt->eflags = kvm_get_rflags(vcpu);
5071 ctxt->eip = kvm_rip_read(vcpu);
5072 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5073 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5074 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5075 cs_db ? X86EMUL_MODE_PROT32 :
5076 X86EMUL_MODE_PROT16;
a584539b 5077 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5078 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5079 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5080 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5081
dd856efa 5082 init_decode_cache(ctxt);
7ae441ea 5083 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5084}
5085
71f9833b 5086int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5087{
9d74191a 5088 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5089 int ret;
5090
5091 init_emulate_ctxt(vcpu);
5092
9dac77fa
AK		 5093 ctxt->op_bytes = 2;
5094 ctxt->ad_bytes = 2;
5095 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5096 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5097
5098 if (ret != X86EMUL_CONTINUE)
5099 return EMULATE_FAIL;
5100
9dac77fa 5101 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5102 kvm_rip_write(vcpu, ctxt->eip);
5103 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5104
5105 if (irq == NMI_VECTOR)
7460fb4a 5106 vcpu->arch.nmi_pending = 0;
63995653
MG		 5107 else
5108 vcpu->arch.interrupt.pending = false;
5109
5110 return EMULATE_DONE;
5111}
5112EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5113
6d77dbfc
GN		 5114static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5115{
fc3a9157
JR		 5116 int r = EMULATE_DONE;
5117
6d77dbfc
GN		 5118 ++vcpu->stat.insn_emulation_fail;
5119 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5120 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5121 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5122 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5123 vcpu->run->internal.ndata = 0;
5124 r = EMULATE_FAIL;
5125 }
6d77dbfc 5126 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5127
5128 return r;
6d77dbfc
GN		 5129}
5130
93c05d3e 5131static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5132 bool write_fault_to_shadow_pgtable,
5133 int emulation_type)
a6f177ef 5134{
95b3cf69 5135 gpa_t gpa = cr2;
8e3d9d06 5136 pfn_t pfn;
a6f177ef 5137
991eebf9
GN		 5138 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5139 return false;
5140
95b3cf69
XG		 5141 if (!vcpu->arch.mmu.direct_map) {
5142 /*
5143 * Write permission should be allowed since only
5144 * write access need to be emulated.
5145 */
5146 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5147
95b3cf69
XG		 5148 /*
5149 * If the mapping is invalid in guest, let cpu retry
5150 * it to generate fault.
5151 */
5152 if (gpa == UNMAPPED_GVA)
5153 return true;
5154 }
a6f177ef 5155
8e3d9d06
XG		 5156 /*
5157 * Do not retry the unhandleable instruction if it faults on the
5158 * readonly host memory, otherwise it will goto a infinite loop:
5159 * retry instruction -> write #PF -> emulation fail -> retry
5160 * instruction -> ...
5161 */
5162 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5163
5164 /*
5165 * If the instruction failed on the error pfn, it can not be fixed,
5166 * report the error to userspace.
5167 */
5168 if (is_error_noslot_pfn(pfn))
5169 return false;
5170
5171 kvm_release_pfn_clean(pfn);
5172
5173 /* The instructions are well-emulated on direct mmu. */
5174 if (vcpu->arch.mmu.direct_map) {
5175 unsigned int indirect_shadow_pages;
5176
5177 spin_lock(&vcpu->kvm->mmu_lock);
5178 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5179 spin_unlock(&vcpu->kvm->mmu_lock);
5180
5181 if (indirect_shadow_pages)
5182 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5183
a6f177ef 5184 return true;
8e3d9d06 5185 }
a6f177ef 5186
95b3cf69
XG		 5187 /*
5188 * if emulation was due to access to shadowed page table
5189 * and it failed try to unshadow page and re-enter the
5190 * guest to let CPU execute the instruction.
5191 */
5192 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5193
5194 /*
5195 * If the access faults on its page table, it can not
5196 * be fixed by unprotecting shadow page and it should
5197 * be reported to userspace.
5198 */
5199 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5200}
5201
1cb3f3ae
XG		 5202static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5203 unsigned long cr2, int emulation_type)
5204{
5205 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5206 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5207
5208 last_retry_eip = vcpu->arch.last_retry_eip;
5209 last_retry_addr = vcpu->arch.last_retry_addr;
5210
5211 /*
5212 * If the emulation is caused by #PF and it is non-page_table
5213 * writing instruction, it means the VM-EXIT is caused by shadow
5214 * page protected, we can zap the shadow page and retry this
5215 * instruction directly.
5216 *
5217 * Note: if the guest uses a non-page-table modifying instruction
5218 * on the PDE that points to the instruction, then we will unmap
5219 * the instruction and go to an infinite loop. So, we cache the
5220 * last retried eip and the last fault address, if we meet the eip
5221 * and the address again, we can break out of the potential infinite
5222 * loop.
5223 */
5224 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5225
5226 if (!(emulation_type & EMULTYPE_RETRY))
5227 return false;
5228
5229 if (x86_page_table_writing_insn(ctxt))
5230 return false;
5231
5232 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5233 return false;
5234
5235 vcpu->arch.last_retry_eip = ctxt->eip;
5236 vcpu->arch.last_retry_addr = cr2;
5237
5238 if (!vcpu->arch.mmu.direct_map)
5239 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5240
22368028 5241 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5242
5243 return true;
5244}
5245
716d51ab
GN		 5246static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5247static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5248
64d60670 5249static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5250{
64d60670 5251 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5252 /* This is a good place to trace that we are exiting SMM. */
5253 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5254
64d60670
PB		 5255 if (unlikely(vcpu->arch.smi_pending)) {
5256 kvm_make_request(KVM_REQ_SMI, vcpu);
5257 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5258 } else {
5259 /* Process a latched INIT, if any. */
5260 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5261 }
5262 }
699023e2
PB		 5263
5264 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5265}
5266
5267static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5268{
5269 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5270
a584539b 5271 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5272
5273 if (changed & HF_SMM_MASK)
5274 kvm_smm_changed(vcpu);
a584539b
PB		 5275}
5276
4a1e10d5
PB		 5277static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5278 unsigned long *db)
5279{
5280 u32 dr6 = 0;
5281 int i;
5282 u32 enable, rwlen;
5283
5284 enable = dr7;
5285 rwlen = dr7 >> 16;
5286 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5287 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5288 dr6 |= (1 << i);
5289 return dr6;
5290}
5291
6addfc42 5292static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5293{
5294 struct kvm_run *kvm_run = vcpu->run;
5295
5296 /*
6addfc42
PB		 5297 * rflags is the old, "raw" value of the flags. The new value has
5298 * not been saved yet.
663f4c61
PB		 5299 *
5300 * This is correct even for TF set by the guest, because "the
5301 * processor will not generate this exception after the instruction
5302 * that sets the TF flag".
5303 */
663f4c61
PB		 5304 if (unlikely(rflags & X86_EFLAGS_TF)) {
5305 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5306 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5307 DR6_RTM;
663f4c61
PB		 5308 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5309 kvm_run->debug.arch.exception = DB_VECTOR;
5310 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5311 *r = EMULATE_USER_EXIT;
5312 } else {
5313 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5314 /*
5315 * "Certain debug exceptions may clear bit 0-3. The
5316 * remaining contents of the DR6 register are never
5317 * cleared by the processor".
5318 */
5319 vcpu->arch.dr6 &= ~15;
6f43ed01 5320 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5321 kvm_queue_exception(vcpu, DB_VECTOR);
5322 }
5323 }
5324}
5325
4a1e10d5
PB		 5326static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5327{
4a1e10d5
PB		 5328 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5329 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5330 struct kvm_run *kvm_run = vcpu->run;
5331 unsigned long eip = kvm_get_linear_rip(vcpu);
5332 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5333 vcpu->arch.guest_debug_dr7,
5334 vcpu->arch.eff_db);
5335
5336 if (dr6 != 0) {
6f43ed01 5337 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5338 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5339 kvm_run->debug.arch.exception = DB_VECTOR;
5340 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5341 *r = EMULATE_USER_EXIT;
5342 return true;
5343 }
5344 }
5345
4161a569
NA		 5346 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5347 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5348 unsigned long eip = kvm_get_linear_rip(vcpu);
5349 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5350 vcpu->arch.dr7,
5351 vcpu->arch.db);
5352
5353 if (dr6 != 0) {
5354 vcpu->arch.dr6 &= ~15;
6f43ed01 5355 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5356 kvm_queue_exception(vcpu, DB_VECTOR);
5357 *r = EMULATE_DONE;
5358 return true;
5359 }
5360 }
5361
5362 return false;
5363}
5364
51d8b661
AP		 5365int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5366 unsigned long cr2,
dc25e89e
AP		 5367 int emulation_type,
5368 void *insn,
5369 int insn_len)
bbd9b64e 5370{
95cb2295 5371 int r;
9d74191a 5372 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5373 bool writeback = true;
93c05d3e 5374 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5375
93c05d3e
XG		 5376 /*
5377 * Clear write_fault_to_shadow_pgtable here to ensure it is
5378 * never reused.
5379 */
5380 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5381 kvm_clear_exception_queue(vcpu);
8d7d8102 5382
571008da 5383 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5384 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5385
5386 /*
5387 * We will reenter on the same instruction since
5388 * we do not set complete_userspace_io. This does not
5389 * handle watchpoints yet, those would be handled in
5390 * the emulate_ops.
5391 */
5392 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5393 return r;
5394
9d74191a
TY		 5395 ctxt->interruptibility = 0;
5396 ctxt->have_exception = false;
e0ad0b47 5397 ctxt->exception.vector = -1;
9d74191a 5398 ctxt->perm_ok = false;
bbd9b64e 5399
b51e974f 5400 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5401
9d74191a 5402 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5403
e46479f8 5404 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5405 ++vcpu->stat.insn_emulation;
1d2887e2 5406 if (r != EMULATION_OK) {
4005996e
AK		 5407 if (emulation_type & EMULTYPE_TRAP_UD)
5408 return EMULATE_FAIL;
991eebf9
GN		 5409 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5410 emulation_type))
bbd9b64e 5411 return EMULATE_DONE;
6d77dbfc
GN		 5412 if (emulation_type & EMULTYPE_SKIP)
5413 return EMULATE_FAIL;
5414 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5415 }
5416 }
5417
ba8afb6b 5418 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5419 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5420 if (ctxt->eflags & X86_EFLAGS_RF)
5421 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5422 return EMULATE_DONE;
5423 }
5424
1cb3f3ae
XG		 5425 if (retry_instruction(ctxt, cr2, emulation_type))
5426 return EMULATE_DONE;
5427
7ae441ea 5428 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5429 changes registers values during IO operation */
7ae441ea
GN		 5430 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5431 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5432 emulator_invalidate_register_cache(ctxt);
7ae441ea 5433 }
4d2179e1 5434
5cd21917 5435restart:
9d74191a 5436 r = x86_emulate_insn(ctxt);
bbd9b64e 5437
775fde86
JR		 5438 if (r == EMULATION_INTERCEPTED)
5439 return EMULATE_DONE;
5440
d2ddd1c4 5441 if (r == EMULATION_FAILED) {
991eebf9
GN		 5442 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5443 emulation_type))
c3cd7ffa
GN		 5444 return EMULATE_DONE;
5445
6d77dbfc 5446 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5447 }
5448
9d74191a 5449 if (ctxt->have_exception) {
d2ddd1c4 5450 r = EMULATE_DONE;
ef54bcfe
PB		 5451 if (inject_emulated_exception(vcpu))
5452 return r;
d2ddd1c4 5453 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5454 if (!vcpu->arch.pio.in) {
5455 /* FIXME: return into emulator if single-stepping. */
3457e419 5456 vcpu->arch.pio.count = 0;
0912c977 5457 } else {
7ae441ea 5458 writeback = false;
716d51ab
GN		 5459 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5460 }
ac0a48c3 5461 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5462 } else if (vcpu->mmio_needed) {
5463 if (!vcpu->mmio_is_write)
5464 writeback = false;
ac0a48c3 5465 r = EMULATE_USER_EXIT;
716d51ab 5466 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5467 } else if (r == EMULATION_RESTART)
5cd21917 5468 goto restart;
d2ddd1c4
GN		 5469 else
5470 r = EMULATE_DONE;
f850e2e6 5471
7ae441ea 5472 if (writeback) {
6addfc42 5473 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5474 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5475 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5476 if (vcpu->arch.hflags != ctxt->emul_flags)
5477 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5478 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5479 if (r == EMULATE_DONE)
6addfc42 5480 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5481 if (!ctxt->have_exception ||
5482 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5483 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5484
5485 /*
5486 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5487 * do nothing, and it will be requested again as soon as
5488 * the shadow expires. But we still need to check here,
5489 * because POPF has no interrupt shadow.
5490 */
5491 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5492 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5493 } else
5494 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5495
5496 return r;
de7d789a 5497}
51d8b661 5498EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5499
cf8f70bf 5500int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5501{
cf8f70bf 5502 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5503 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5504 size, port, &val, 1);
cf8f70bf 5505 /* do not return to emulator after return from userspace */
7972995b 5506 vcpu->arch.pio.count = 0;
de7d789a
CO		 5507 return ret;
5508}
cf8f70bf 5509EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5510
8cfdc000
ZA		 5511static void tsc_bad(void *info)
5512{
0a3aee0d 5513 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5514}
5515
5516static void tsc_khz_changed(void *data)
c8076604 5517{
8cfdc000
ZA		 5518 struct cpufreq_freqs *freq = data;
5519 unsigned long khz = 0;
5520
5521 if (data)
5522 khz = freq->new;
5523 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5524 khz = cpufreq_quick_get(raw_smp_processor_id());
5525 if (!khz)
5526 khz = tsc_khz;
0a3aee0d 5527 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5528}
5529
c8076604
GH		 5530static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5531 void *data)
5532{
5533 struct cpufreq_freqs *freq = data;
5534 struct kvm *kvm;
5535 struct kvm_vcpu *vcpu;
5536 int i, send_ipi = 0;
5537
8cfdc000
ZA		 5538 /*
5539 * We allow guests to temporarily run on slowing clocks,
5540 * provided we notify them after, or to run on accelerating
5541 * clocks, provided we notify them before. Thus time never
5542 * goes backwards.
5543 *
5544 * However, we have a problem. We can't atomically update
5545 * the frequency of a given CPU from this function; it is
5546 * merely a notifier, which can be called from any CPU.
5547 * Changing the TSC frequency at arbitrary points in time
5548 * requires a recomputation of local variables related to
5549 * the TSC for each VCPU. We must flag these local variables
5550 * to be updated and be sure the update takes place with the
5551 * new frequency before any guests proceed.
5552 *
5553 * Unfortunately, the combination of hotplug CPU and frequency
5554 * change creates an intractable locking scenario; the order
5555 * of when these callouts happen is undefined with respect to
5556 * CPU hotplug, and they can race with each other. As such,
5557 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5558 * undefined; you can actually have a CPU frequency change take
5559 * place in between the computation of X and the setting of the
5560 * variable. To protect against this problem, all updates of
5561 * the per_cpu tsc_khz variable are done in an interrupt
5562 * protected IPI, and all callers wishing to update the value
5563 * must wait for a synchronous IPI to complete (which is trivial
5564 * if the caller is on the CPU already). This establishes the
5565 * necessary total order on variable updates.
5566 *
5567 * Note that because a guest time update may take place
5568 * anytime after the setting of the VCPU's request bit, the
5569 * correct TSC value must be set before the request. However,
5570 * to ensure the update actually makes it to any guest which
5571 * starts running in hardware virtualization between the set
5572 * and the acquisition of the spinlock, we must also ping the
5573 * CPU after setting the request bit.
5574 *
5575 */
5576
c8076604
GH		 5577 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5578 return 0;
5579 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5580 return 0;
8cfdc000
ZA		 5581
5582 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5583
2f303b74 5584 spin_lock(&kvm_lock);
c8076604 5585 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5586 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5587 if (vcpu->cpu != freq->cpu)
5588 continue;
c285545f 5589 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5590 if (vcpu->cpu != smp_processor_id())
8cfdc000 5591 send_ipi = 1;
c8076604
GH		 5592 }
5593 }
2f303b74 5594 spin_unlock(&kvm_lock);
c8076604
GH		 5595
5596 if (freq->old < freq->new && send_ipi) {
5597 /*
5598 * We upscale the frequency. Must make the guest
5599 * doesn't see old kvmclock values while running with
5600 * the new frequency, otherwise we risk the guest sees
5601 * time go backwards.
5602 *
5603 * In case we update the frequency for another cpu
5604 * (which might be in guest context) send an interrupt
5605 * to kick the cpu out of guest context. Next time
5606 * guest context is entered kvmclock will be updated,
5607 * so the guest will not see stale values.
5608 */
8cfdc000 5609 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5610 }
5611 return 0;
5612}
5613
5614static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5615 .notifier_call = kvmclock_cpufreq_notifier
5616};
5617
5618static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5619 unsigned long action, void *hcpu)
5620{
5621 unsigned int cpu = (unsigned long)hcpu;
5622
5623 switch (action) {
5624 case CPU_ONLINE:
5625 case CPU_DOWN_FAILED:
5626 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5627 break;
5628 case CPU_DOWN_PREPARE:
5629 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5630 break;
5631 }
5632 return NOTIFY_OK;
5633}
5634
5635static struct notifier_block kvmclock_cpu_notifier_block = {
5636 .notifier_call = kvmclock_cpu_notifier,
5637 .priority = -INT_MAX
c8076604
GH		 5638};
5639
b820cc0c
ZA		 5640static void kvm_timer_init(void)
5641{
5642 int cpu;
5643
c285545f 5644 max_tsc_khz = tsc_khz;
460dd42e
SB		 5645
5646 cpu_notifier_register_begin();
b820cc0c 5647 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5648#ifdef CONFIG_CPU_FREQ
5649 struct cpufreq_policy policy;
5650 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5651 cpu = get_cpu();
5652 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5653 if (policy.cpuinfo.max_freq)
5654 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5655 put_cpu();
c285545f 5656#endif
b820cc0c
ZA		 5657 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5658 CPUFREQ_TRANSITION_NOTIFIER);
5659 }
c285545f 5660 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5661 for_each_online_cpu(cpu)
5662 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5663
5664 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5665 cpu_notifier_register_done();
5666
b820cc0c
ZA		 5667}
5668
ff9d07a0
ZY		 5669static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5670
f5132b01 5671int kvm_is_in_guest(void)
ff9d07a0 5672{
086c9855 5673 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5674}
5675
5676static int kvm_is_user_mode(void)
5677{
5678 int user_mode = 3;
dcf46b94 5679
086c9855
AS		 5680 if (__this_cpu_read(current_vcpu))
5681 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5682
ff9d07a0
ZY		 5683 return user_mode != 0;
5684}
5685
5686static unsigned long kvm_get_guest_ip(void)
5687{
5688 unsigned long ip = 0;
dcf46b94 5689
086c9855
AS		 5690 if (__this_cpu_read(current_vcpu))
5691 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5692
ff9d07a0
ZY		 5693 return ip;
5694}
5695
5696static struct perf_guest_info_callbacks kvm_guest_cbs = {
5697 .is_in_guest = kvm_is_in_guest,
5698 .is_user_mode = kvm_is_user_mode,
5699 .get_guest_ip = kvm_get_guest_ip,
5700};
5701
5702void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5703{
086c9855 5704 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5705}
5706EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5707
5708void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5709{
086c9855 5710 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5711}
5712EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5713
ce88decf
XG		 5714static void kvm_set_mmio_spte_mask(void)
5715{
5716 u64 mask;
5717 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5718
5719 /*
5720 * Set the reserved bits and the present bit of an paging-structure
5721 * entry to generate page fault with PFER.RSV = 1.
5722 */
885032b9 5723 /* Mask the reserved physical address bits. */
d1431483 5724 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5725
5726 /* Bit 62 is always reserved for 32bit host. */
5727 mask |= 0x3ull << 62;
5728
5729 /* Set the present bit. */
ce88decf
XG		 5730 mask |= 1ull;
5731
5732#ifdef CONFIG_X86_64
5733 /*
5734 * If reserved bit is not supported, clear the present bit to disable
5735 * mmio page fault.
5736 */
5737 if (maxphyaddr == 52)
5738 mask &= ~1ull;
5739#endif
5740
5741 kvm_mmu_set_mmio_spte_mask(mask);
5742}
5743
16e8d74d
MT		 5744#ifdef CONFIG_X86_64
5745static void pvclock_gtod_update_fn(struct work_struct *work)
5746{
d828199e
MT		 5747 struct kvm *kvm;
5748
5749 struct kvm_vcpu *vcpu;
5750 int i;
5751
2f303b74 5752 spin_lock(&kvm_lock);
d828199e
MT		 5753 list_for_each_entry(kvm, &vm_list, vm_list)
5754 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5755 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5756 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5757 spin_unlock(&kvm_lock);
16e8d74d
MT		 5758}
5759
5760static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5761
5762/*
5763 * Notification about pvclock gtod data update.
5764 */
5765static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5766 void *priv)
5767{
5768 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5769 struct timekeeper *tk = priv;
5770
5771 update_pvclock_gtod(tk);
5772
5773 /* disable master clock if host does not trust, or does not
5774 * use, TSC clocksource
5775 */
5776 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5777 atomic_read(&kvm_guest_has_master_clock) != 0)
5778 queue_work(system_long_wq, &pvclock_gtod_work);
5779
5780 return 0;
5781}
5782
5783static struct notifier_block pvclock_gtod_notifier = {
5784 .notifier_call = pvclock_gtod_notify,
5785};
5786#endif
5787
f8c16bba 5788int kvm_arch_init(void *opaque)
043405e1 5789{
b820cc0c 5790 int r;
6b61edf7 5791 struct kvm_x86_ops *ops = opaque;
f8c16bba 5792
f8c16bba
ZX		 5793 if (kvm_x86_ops) {
5794 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5795 r = -EEXIST;
5796 goto out;
f8c16bba
ZX		 5797 }
5798
5799 if (!ops->cpu_has_kvm_support()) {
5800 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5801 r = -EOPNOTSUPP;
5802 goto out;
f8c16bba
ZX		 5803 }
5804 if (ops->disabled_by_bios()) {
5805 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5806 r = -EOPNOTSUPP;
5807 goto out;
f8c16bba
ZX		 5808 }
5809
013f6a5d
MT		 5810 r = -ENOMEM;
5811 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5812 if (!shared_msrs) {
5813 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5814 goto out;
5815 }
5816
97db56ce
AK		 5817 r = kvm_mmu_module_init();
5818 if (r)
013f6a5d 5819 goto out_free_percpu;
97db56ce 5820
ce88decf 5821 kvm_set_mmio_spte_mask();
97db56ce 5822
f8c16bba 5823 kvm_x86_ops = ops;
920c8377 5824
7b52345e 5825 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5826 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5827
b820cc0c 5828 kvm_timer_init();
c8076604 5829
ff9d07a0
ZY		 5830 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5831
2acf923e
DC		 5832 if (cpu_has_xsave)
5833 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5834
c5cc421b 5835 kvm_lapic_init();
16e8d74d
MT		 5836#ifdef CONFIG_X86_64
5837 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5838#endif
5839
f8c16bba 5840 return 0;
56c6d28a 5841
013f6a5d
MT		 5842out_free_percpu:
5843 free_percpu(shared_msrs);
56c6d28a 5844out:
56c6d28a 5845 return r;
043405e1 5846}
8776e519 5847
f8c16bba
ZX		 5848void kvm_arch_exit(void)
5849{
ff9d07a0
ZY		 5850 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5851
888d256e
JK		 5852 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5853 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5854 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5855 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5856#ifdef CONFIG_X86_64
5857 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5858#endif
f8c16bba 5859 kvm_x86_ops = NULL;
56c6d28a 5860 kvm_mmu_module_exit();
013f6a5d 5861 free_percpu(shared_msrs);
56c6d28a 5862}
f8c16bba 5863
5cb56059 5864int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5865{
5866 ++vcpu->stat.halt_exits;
35754c98 5867 if (lapic_in_kernel(vcpu)) {
a4535290 5868 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5869 return 1;
5870 } else {
5871 vcpu->run->exit_reason = KVM_EXIT_HLT;
5872 return 0;
5873 }
5874}
5cb56059
JS		 5875EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5876
5877int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5878{
5879 kvm_x86_ops->skip_emulated_instruction(vcpu);
5880 return kvm_vcpu_halt(vcpu);
5881}
8776e519
HB		 5882EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5883
6aef266c
SV		 5884/*
5885 * kvm_pv_kick_cpu_op: Kick a vcpu.
5886 *
5887 * @apicid - apicid of vcpu to be kicked.
5888 */
5889static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5890{
24d2166b 5891 struct kvm_lapic_irq lapic_irq;
6aef266c 5892
24d2166b
R		 5893 lapic_irq.shorthand = 0;
5894 lapic_irq.dest_mode = 0;
5895 lapic_irq.dest_id = apicid;
93bbf0b8 5896 lapic_irq.msi_redir_hint = false;
6aef266c 5897
24d2166b 5898 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5899 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5900}
5901
d62caabb
AS		 5902void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
5903{
5904 vcpu->arch.apicv_active = false;
5905 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
5906}
5907
8776e519
HB		 5908int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5909{
5910 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5911 int op_64_bit, r = 1;
8776e519 5912
5cb56059
JS		 5913 kvm_x86_ops->skip_emulated_instruction(vcpu);
5914
55cd8e5a
GN		 5915 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5916 return kvm_hv_hypercall(vcpu);
5917
5fdbf976
MT		 5918 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5919 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5920 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5921 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5922 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5923
229456fc 5924 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5925
a449c7aa
NA		 5926 op_64_bit = is_64_bit_mode(vcpu);
5927 if (!op_64_bit) {
8776e519
HB		 5928 nr &= 0xFFFFFFFF;
5929 a0 &= 0xFFFFFFFF;
5930 a1 &= 0xFFFFFFFF;
5931 a2 &= 0xFFFFFFFF;
5932 a3 &= 0xFFFFFFFF;
5933 }
5934
07708c4a
JK		 5935 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5936 ret = -KVM_EPERM;
5937 goto out;
5938 }
5939
8776e519 5940 switch (nr) {
b93463aa
AK		 5941 case KVM_HC_VAPIC_POLL_IRQ:
5942 ret = 0;
5943 break;
6aef266c
SV		 5944 case KVM_HC_KICK_CPU:
5945 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5946 ret = 0;
5947 break;
8776e519
HB		 5948 default:
5949 ret = -KVM_ENOSYS;
5950 break;
5951 }
07708c4a 5952out:
a449c7aa
NA		 5953 if (!op_64_bit)
5954 ret = (u32)ret;
5fdbf976 5955 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5956 ++vcpu->stat.hypercalls;
2f333bcb 5957 return r;
8776e519
HB		 5958}
5959EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5960
b6785def 5961static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5962{
d6aa1000 5963 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5964 char instruction[3];
5fdbf976 5965 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5966
8776e519 5967 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5968
9d74191a 5969 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5970}
5971
851ba692 5972static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5973{
782d422b
MG		 5974 return vcpu->run->request_interrupt_window &&
5975 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 5976}
5977
851ba692 5978static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5979{
851ba692
AK		 5980 struct kvm_run *kvm_run = vcpu->run;
5981
91586a3b 5982 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 5983 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 5984 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5985 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 5986 kvm_run->ready_for_interrupt_injection =
5987 pic_in_kernel(vcpu->kvm) ||
782d422b 5988 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 5989}
5990
95ba8273
GN		 5991static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5992{
5993 int max_irr, tpr;
5994
5995 if (!kvm_x86_ops->update_cr8_intercept)
5996 return;
5997
88c808fd
AK		 5998 if (!vcpu->arch.apic)
5999 return;
6000
d62caabb
AS		 6001 if (vcpu->arch.apicv_active)
6002 return;
6003
8db3baa2
GN		 6004 if (!vcpu->arch.apic->vapic_addr)
6005 max_irr = kvm_lapic_find_highest_irr(vcpu);
6006 else
6007 max_irr = -1;
95ba8273
GN		 6008
6009 if (max_irr != -1)
6010 max_irr >>= 4;
6011
6012 tpr = kvm_lapic_get_cr8(vcpu);
6013
6014 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6015}
6016
b6b8a145 6017static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6018{
b6b8a145
JK		 6019 int r;
6020
95ba8273 6021 /* try to reinject previous events if any */
b59bb7bd 6022 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6023 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6024 vcpu->arch.exception.has_error_code,
6025 vcpu->arch.exception.error_code);
d6e8c854
NA		 6026
6027 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6028 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6029 X86_EFLAGS_RF);
6030
6bdf0662
NA		 6031 if (vcpu->arch.exception.nr == DB_VECTOR &&
6032 (vcpu->arch.dr7 & DR7_GD)) {
6033 vcpu->arch.dr7 &= ~DR7_GD;
6034 kvm_update_dr7(vcpu);
6035 }
6036
b59bb7bd
GN		 6037 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6038 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6039 vcpu->arch.exception.error_code,
6040 vcpu->arch.exception.reinject);
b6b8a145 6041 return 0;
b59bb7bd
GN		 6042 }
6043
95ba8273
GN		 6044 if (vcpu->arch.nmi_injected) {
6045 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6046 return 0;
95ba8273
GN		 6047 }
6048
6049 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6050 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6051 return 0;
6052 }
6053
6054 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6055 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6056 if (r != 0)
6057 return r;
95ba8273
GN		 6058 }
6059
6060 /* try to inject new event if pending */
6061 if (vcpu->arch.nmi_pending) {
6062 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6063 --vcpu->arch.nmi_pending;
95ba8273
GN		 6064 vcpu->arch.nmi_injected = true;
6065 kvm_x86_ops->set_nmi(vcpu);
6066 }
c7c9c56c 6067 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6068 /*
6069 * Because interrupts can be injected asynchronously, we are
6070 * calling check_nested_events again here to avoid a race condition.
6071 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6072 * proposal and current concerns. Perhaps we should be setting
6073 * KVM_REQ_EVENT only on certain events and not unconditionally?
6074 */
6075 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6076 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6077 if (r != 0)
6078 return r;
6079 }
95ba8273 6080 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6081 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6082 false);
6083 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6084 }
6085 }
b6b8a145 6086 return 0;
95ba8273
GN		 6087}
6088
7460fb4a
AK		 6089static void process_nmi(struct kvm_vcpu *vcpu)
6090{
6091 unsigned limit = 2;
6092
6093 /*
6094 * x86 is limited to one NMI running, and one NMI pending after it.
6095 * If an NMI is already in progress, limit further NMIs to just one.
6096 * Otherwise, allow two (and we'll inject the first one immediately).
6097 */
6098 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6099 limit = 1;
6100
6101 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6102 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6103 kvm_make_request(KVM_REQ_EVENT, vcpu);
6104}
6105
660a5d51
PB		 6106#define put_smstate(type, buf, offset, val) \
6107 *(type *)((buf) + (offset) - 0x7e00) = val
6108
6109static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6110{
6111 u32 flags = 0;
6112 flags |= seg->g << 23;
6113 flags |= seg->db << 22;
6114 flags |= seg->l << 21;
6115 flags |= seg->avl << 20;
6116 flags |= seg->present << 15;
6117 flags |= seg->dpl << 13;
6118 flags |= seg->s << 12;
6119 flags |= seg->type << 8;
6120 return flags;
6121}
6122
6123static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6124{
6125 struct kvm_segment seg;
6126 int offset;
6127
6128 kvm_get_segment(vcpu, &seg, n);
6129 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6130
6131 if (n < 3)
6132 offset = 0x7f84 + n * 12;
6133 else
6134 offset = 0x7f2c + (n - 3) * 12;
6135
6136 put_smstate(u32, buf, offset + 8, seg.base);
6137 put_smstate(u32, buf, offset + 4, seg.limit);
6138 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6139}
6140
efbb288a 6141#ifdef CONFIG_X86_64
660a5d51
PB		 6142static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6143{
6144 struct kvm_segment seg;
6145 int offset;
6146 u16 flags;
6147
6148 kvm_get_segment(vcpu, &seg, n);
6149 offset = 0x7e00 + n * 16;
6150
6151 flags = process_smi_get_segment_flags(&seg) >> 8;
6152 put_smstate(u16, buf, offset, seg.selector);
6153 put_smstate(u16, buf, offset + 2, flags);
6154 put_smstate(u32, buf, offset + 4, seg.limit);
6155 put_smstate(u64, buf, offset + 8, seg.base);
6156}
efbb288a 6157#endif
660a5d51
PB		 6158
6159static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6160{
6161 struct desc_ptr dt;
6162 struct kvm_segment seg;
6163 unsigned long val;
6164 int i;
6165
6166 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6167 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6168 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6169 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6170
6171 for (i = 0; i < 8; i++)
6172 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6173
6174 kvm_get_dr(vcpu, 6, &val);
6175 put_smstate(u32, buf, 0x7fcc, (u32)val);
6176 kvm_get_dr(vcpu, 7, &val);
6177 put_smstate(u32, buf, 0x7fc8, (u32)val);
6178
6179 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6180 put_smstate(u32, buf, 0x7fc4, seg.selector);
6181 put_smstate(u32, buf, 0x7f64, seg.base);
6182 put_smstate(u32, buf, 0x7f60, seg.limit);
6183 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6184
6185 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6186 put_smstate(u32, buf, 0x7fc0, seg.selector);
6187 put_smstate(u32, buf, 0x7f80, seg.base);
6188 put_smstate(u32, buf, 0x7f7c, seg.limit);
6189 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6190
6191 kvm_x86_ops->get_gdt(vcpu, &dt);
6192 put_smstate(u32, buf, 0x7f74, dt.address);
6193 put_smstate(u32, buf, 0x7f70, dt.size);
6194
6195 kvm_x86_ops->get_idt(vcpu, &dt);
6196 put_smstate(u32, buf, 0x7f58, dt.address);
6197 put_smstate(u32, buf, 0x7f54, dt.size);
6198
6199 for (i = 0; i < 6; i++)
6200 process_smi_save_seg_32(vcpu, buf, i);
6201
6202 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6203
6204 /* revision id */
6205 put_smstate(u32, buf, 0x7efc, 0x00020000);
6206 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6207}
6208
6209static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6210{
6211#ifdef CONFIG_X86_64
6212 struct desc_ptr dt;
6213 struct kvm_segment seg;
6214 unsigned long val;
6215 int i;
6216
6217 for (i = 0; i < 16; i++)
6218 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6219
6220 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6221 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6222
6223 kvm_get_dr(vcpu, 6, &val);
6224 put_smstate(u64, buf, 0x7f68, val);
6225 kvm_get_dr(vcpu, 7, &val);
6226 put_smstate(u64, buf, 0x7f60, val);
6227
6228 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6229 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6230 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6231
6232 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6233
6234 /* revision id */
6235 put_smstate(u32, buf, 0x7efc, 0x00020064);
6236
6237 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6238
6239 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6240 put_smstate(u16, buf, 0x7e90, seg.selector);
6241 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6242 put_smstate(u32, buf, 0x7e94, seg.limit);
6243 put_smstate(u64, buf, 0x7e98, seg.base);
6244
6245 kvm_x86_ops->get_idt(vcpu, &dt);
6246 put_smstate(u32, buf, 0x7e84, dt.size);
6247 put_smstate(u64, buf, 0x7e88, dt.address);
6248
6249 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6250 put_smstate(u16, buf, 0x7e70, seg.selector);
6251 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6252 put_smstate(u32, buf, 0x7e74, seg.limit);
6253 put_smstate(u64, buf, 0x7e78, seg.base);
6254
6255 kvm_x86_ops->get_gdt(vcpu, &dt);
6256 put_smstate(u32, buf, 0x7e64, dt.size);
6257 put_smstate(u64, buf, 0x7e68, dt.address);
6258
6259 for (i = 0; i < 6; i++)
6260 process_smi_save_seg_64(vcpu, buf, i);
6261#else
6262 WARN_ON_ONCE(1);
6263#endif
6264}
6265
64d60670
PB		 6266static void process_smi(struct kvm_vcpu *vcpu)
6267{
660a5d51 6268 struct kvm_segment cs, ds;
18c3626e 6269 struct desc_ptr dt;
660a5d51
PB		 6270 char buf[512];
6271 u32 cr0;
6272
64d60670
PB		 6273 if (is_smm(vcpu)) {
6274 vcpu->arch.smi_pending = true;
6275 return;
6276 }
6277
660a5d51
PB		 6278 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6279 vcpu->arch.hflags |= HF_SMM_MASK;
6280 memset(buf, 0, 512);
6281 if (guest_cpuid_has_longmode(vcpu))
6282 process_smi_save_state_64(vcpu, buf);
6283 else
6284 process_smi_save_state_32(vcpu, buf);
6285
54bf36aa 6286 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6287
6288 if (kvm_x86_ops->get_nmi_mask(vcpu))
6289 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6290 else
6291 kvm_x86_ops->set_nmi_mask(vcpu, true);
6292
6293 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6294 kvm_rip_write(vcpu, 0x8000);
6295
6296 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6297 kvm_x86_ops->set_cr0(vcpu, cr0);
6298 vcpu->arch.cr0 = cr0;
6299
6300 kvm_x86_ops->set_cr4(vcpu, 0);
6301
18c3626e
PB		 6302 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6303 dt.address = dt.size = 0;
6304 kvm_x86_ops->set_idt(vcpu, &dt);
6305
660a5d51
PB		 6306 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6307
6308 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6309 cs.base = vcpu->arch.smbase;
6310
6311 ds.selector = 0;
6312 ds.base = 0;
6313
6314 cs.limit = ds.limit = 0xffffffff;
6315 cs.type = ds.type = 0x3;
6316 cs.dpl = ds.dpl = 0;
6317 cs.db = ds.db = 0;
6318 cs.s = ds.s = 1;
6319 cs.l = ds.l = 0;
6320 cs.g = ds.g = 1;
6321 cs.avl = ds.avl = 0;
6322 cs.present = ds.present = 1;
6323 cs.unusable = ds.unusable = 0;
6324 cs.padding = ds.padding = 0;
6325
6326 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6327 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6328 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6329 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6330 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6331 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6332
6333 if (guest_cpuid_has_longmode(vcpu))
6334 kvm_x86_ops->set_efer(vcpu, 0);
6335
6336 kvm_update_cpuid(vcpu);
6337 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6338}
6339
3d81bc7e 6340static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6341{
5c919412
AS		 6342 u64 eoi_exit_bitmap[4];
6343
3d81bc7e
YZ		 6344 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6345 return;
c7c9c56c 6346
6308630b 6347 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6348
b053b2ae 6349 if (irqchip_split(vcpu->kvm))
6308630b 6350 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6351 else {
d62caabb
AS		 6352 if (vcpu->arch.apicv_active)
6353 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6354 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6355 }
5c919412
AS		 6356 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6357 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6358 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6359}
6360
a70656b6
RK		 6361static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6362{
6363 ++vcpu->stat.tlb_flush;
6364 kvm_x86_ops->tlb_flush(vcpu);
6365}
6366
4256f43f
TC		 6367void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6368{
c24ae0dc
TC		 6369 struct page *page = NULL;
6370
35754c98 6371 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6372 return;
6373
4256f43f
TC		 6374 if (!kvm_x86_ops->set_apic_access_page_addr)
6375 return;
6376
c24ae0dc 6377 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6378 if (is_error_page(page))
6379 return;
c24ae0dc
TC		 6380 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6381
6382 /*
6383 * Do not pin apic access page in memory, the MMU notifier
6384 * will call us again if it is migrated or swapped out.
6385 */
6386 put_page(page);
4256f43f
TC		 6387}
6388EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6389
fe71557a
TC		 6390void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6391 unsigned long address)
6392{
c24ae0dc
TC		 6393 /*
6394 * The physical address of apic access page is stored in the VMCS.
6395 * Update it when it becomes invalid.
6396 */
6397 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6398 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6399}
6400
9357d939 6401/*
362c698f 6402 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6403 * exiting to the userspace. Otherwise, the value will be returned to the
6404 * userspace.
6405 */
851ba692 6406static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6407{
6408 int r;
62a193ed
MG		 6409 bool req_int_win =
6410 dm_request_for_irq_injection(vcpu) &&
6411 kvm_cpu_accept_dm_intr(vcpu);
6412
730dca42 6413 bool req_immediate_exit = false;
b6c7a5dc 6414
3e007509 6415 if (vcpu->requests) {
a8eeb04a 6416 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6417 kvm_mmu_unload(vcpu);
a8eeb04a 6418 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6419 __kvm_migrate_timers(vcpu);
d828199e
MT		 6420 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6421 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6422 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6423 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6424 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6425 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6426 if (unlikely(r))
6427 goto out;
6428 }
a8eeb04a 6429 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6430 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6431 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6432 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6433 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6434 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6435 r = 0;
6436 goto out;
6437 }
a8eeb04a 6438 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6439 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6440 r = 0;
6441 goto out;
6442 }
a8eeb04a 6443 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6444 vcpu->fpu_active = 0;
6445 kvm_x86_ops->fpu_deactivate(vcpu);
6446 }
af585b92
GN		 6447 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6448 /* Page is swapped out. Do synthetic halt */
6449 vcpu->arch.apf.halted = true;
6450 r = 1;
6451 goto out;
6452 }
c9aaa895
GC		 6453 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6454 record_steal_time(vcpu);
64d60670
PB		 6455 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6456 process_smi(vcpu);
7460fb4a
AK		 6457 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6458 process_nmi(vcpu);
f5132b01 6459 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6460 kvm_pmu_handle_event(vcpu);
f5132b01 6461 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6462 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6463 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6464 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6465 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6466 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6467 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6468 vcpu->run->eoi.vector =
6469 vcpu->arch.pending_ioapic_eoi;
6470 r = 0;
6471 goto out;
6472 }
6473 }
3d81bc7e
YZ		 6474 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6475 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6476 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6477 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6478 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6479 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6480 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6481 r = 0;
6482 goto out;
6483 }
e516cebb
AS		 6484 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6485 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6486 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6487 r = 0;
6488 goto out;
6489 }
db397571
AS		 6490 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6491 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6492 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6493 r = 0;
6494 goto out;
6495 }
1f4b34f8
AS		 6496 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6497 kvm_hv_process_stimers(vcpu);
2f52d58c 6498 }
b93463aa 6499
bf9f6ac8
FW		 6500 /*
6501 * KVM_REQ_EVENT is not set when posted interrupts are set by
6502 * VT-d hardware, so we have to update RVI unconditionally.
6503 */
6504 if (kvm_lapic_enabled(vcpu)) {
6505 /*
6506 * Update architecture specific hints for APIC
6507 * virtual interrupt delivery.
6508 */
d62caabb 6509 if (vcpu->arch.apicv_active)
bf9f6ac8
FW		 6510 kvm_x86_ops->hwapic_irr_update(vcpu,
6511 kvm_lapic_find_highest_irr(vcpu));
2f52d58c 6512 }
b93463aa 6513
b463a6f7 6514 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6515 kvm_apic_accept_events(vcpu);
6516 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6517 r = 1;
6518 goto out;
6519 }
6520
b6b8a145
JK		 6521 if (inject_pending_event(vcpu, req_int_win) != 0)
6522 req_immediate_exit = true;
b463a6f7 6523 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6524 else if (vcpu->arch.nmi_pending)
c9a7953f 6525 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6526 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6527 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6528
6529 if (kvm_lapic_enabled(vcpu)) {
6530 update_cr8_intercept(vcpu);
6531 kvm_lapic_sync_to_vapic(vcpu);
6532 }
6533 }
6534
d8368af8
AK		 6535 r = kvm_mmu_reload(vcpu);
6536 if (unlikely(r)) {
d905c069 6537 goto cancel_injection;
d8368af8
AK		 6538 }
6539
b6c7a5dc
HB		 6540 preempt_disable();
6541
6542 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6543 if (vcpu->fpu_active)
6544 kvm_load_guest_fpu(vcpu);
2acf923e 6545 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6546
6b7e2d09
XG		 6547 vcpu->mode = IN_GUEST_MODE;
6548
01b71917
MT		 6549 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6550
6b7e2d09
XG		 6551 /* We should set ->mode before check ->requests,
6552 * see the comment in make_all_cpus_request.
6553 */
01b71917 6554 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6555
d94e1dc9 6556 local_irq_disable();
32f88400 6557
6b7e2d09 6558 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6559 || need_resched() || signal_pending(current)) {
6b7e2d09 6560 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6561 smp_wmb();
6c142801
AK		 6562 local_irq_enable();
6563 preempt_enable();
01b71917 6564 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6565 r = 1;
d905c069 6566 goto cancel_injection;
6c142801
AK		 6567 }
6568
d6185f20
NHE		 6569 if (req_immediate_exit)
6570 smp_send_reschedule(vcpu->cpu);
6571
ccf73aaf 6572 __kvm_guest_enter();
b6c7a5dc 6573
42dbaa5a 6574 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6575 set_debugreg(0, 7);
6576 set_debugreg(vcpu->arch.eff_db[0], 0);
6577 set_debugreg(vcpu->arch.eff_db[1], 1);
6578 set_debugreg(vcpu->arch.eff_db[2], 2);
6579 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6580 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6581 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6582 }
b6c7a5dc 6583
229456fc 6584 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6585 wait_lapic_expire(vcpu);
851ba692 6586 kvm_x86_ops->run(vcpu);
b6c7a5dc 6587
c77fb5fe
PB		 6588 /*
6589 * Do this here before restoring debug registers on the host. And
6590 * since we do this before handling the vmexit, a DR access vmexit
6591 * can (a) read the correct value of the debug registers, (b) set
6592 * KVM_DEBUGREG_WONT_EXIT again.
6593 */
6594 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6595 int i;
6596
6597 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6598 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6599 for (i = 0; i < KVM_NR_DB_REGS; i++)
6600 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6601 }
6602
24f1e32c
FW		 6603 /*
6604 * If the guest has used debug registers, at least dr7
6605 * will be disabled while returning to the host.
6606 * If we don't have active breakpoints in the host, we don't
6607 * care about the messed up debug address registers. But if
6608 * we have some of them active, restore the old state.
6609 */
59d8eb53 6610 if (hw_breakpoint_active())
24f1e32c 6611 hw_breakpoint_restore();
42dbaa5a 6612
4ba76538 6613 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6614
6b7e2d09 6615 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6616 smp_wmb();
a547c6db
YZ		 6617
6618 /* Interrupt is enabled by handle_external_intr() */
6619 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6620
6621 ++vcpu->stat.exits;
6622
6623 /*
6624 * We must have an instruction between local_irq_enable() and
6625 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6626 * the interrupt shadow. The stat.exits increment will do nicely.
6627 * But we need to prevent reordering, hence this barrier():
6628 */
6629 barrier();
6630
6631 kvm_guest_exit();
6632
6633 preempt_enable();
6634
f656ce01 6635 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6636
b6c7a5dc
HB		 6637 /*
6638 * Profile KVM exit RIPs:
6639 */
6640 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6641 unsigned long rip = kvm_rip_read(vcpu);
6642 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6643 }
6644
cc578287
ZA		 6645 if (unlikely(vcpu->arch.tsc_always_catchup))
6646 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6647
5cfb1d5a
MT		 6648 if (vcpu->arch.apic_attention)
6649 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6650
851ba692 6651 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6652 return r;
6653
6654cancel_injection:
6655 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6656 if (unlikely(vcpu->arch.apic_attention))
6657 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6658out:
6659 return r;
6660}
b6c7a5dc 6661
362c698f
PB		 6662static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6663{
bf9f6ac8
FW		 6664 if (!kvm_arch_vcpu_runnable(vcpu) &&
6665 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6666 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6667 kvm_vcpu_block(vcpu);
6668 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6669
6670 if (kvm_x86_ops->post_block)
6671 kvm_x86_ops->post_block(vcpu);
6672
9c8fd1ba
PB		 6673 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6674 return 1;
6675 }
362c698f
PB		 6676
6677 kvm_apic_accept_events(vcpu);
6678 switch(vcpu->arch.mp_state) {
6679 case KVM_MP_STATE_HALTED:
6680 vcpu->arch.pv.pv_unhalted = false;
6681 vcpu->arch.mp_state =
6682 KVM_MP_STATE_RUNNABLE;
6683 case KVM_MP_STATE_RUNNABLE:
6684 vcpu->arch.apf.halted = false;
6685 break;
6686 case KVM_MP_STATE_INIT_RECEIVED:
6687 break;
6688 default:
6689 return -EINTR;
6690 break;
6691 }
6692 return 1;
6693}
09cec754 6694
5d9bc648
PB		 6695static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
6696{
6697 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6698 !vcpu->arch.apf.halted);
6699}
6700
362c698f 6701static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6702{
6703 int r;
f656ce01 6704 struct kvm *kvm = vcpu->kvm;
d7690175 6705
f656ce01 6706 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6707
362c698f 6708 for (;;) {
58f800d5 6709 if (kvm_vcpu_running(vcpu)) {
851ba692 6710 r = vcpu_enter_guest(vcpu);
bf9f6ac8 6711 } else {
362c698f 6712 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 6713 }
6714
09cec754
GN		 6715 if (r <= 0)
6716 break;
6717
6718 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6719 if (kvm_cpu_has_pending_timer(vcpu))
6720 kvm_inject_pending_timer_irqs(vcpu);
6721
782d422b
MG		 6722 if (dm_request_for_irq_injection(vcpu) &&
6723 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 6724 r = 0;
6725 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 6726 ++vcpu->stat.request_irq_exits;
362c698f 6727 break;
09cec754 6728 }
af585b92
GN		 6729
6730 kvm_check_async_pf_completion(vcpu);
6731
09cec754
GN		 6732 if (signal_pending(current)) {
6733 r = -EINTR;
851ba692 6734 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6735 ++vcpu->stat.signal_exits;
362c698f 6736 break;
09cec754
GN		 6737 }
6738 if (need_resched()) {
f656ce01 6739 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6740 cond_resched();
f656ce01 6741 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6742 }
b6c7a5dc
HB		 6743 }
6744
f656ce01 6745 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6746
6747 return r;
6748}
6749
716d51ab
GN		 6750static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6751{
6752 int r;
6753 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6754 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6755 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6756 if (r != EMULATE_DONE)
6757 return 0;
6758 return 1;
6759}
6760
6761static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6762{
6763 BUG_ON(!vcpu->arch.pio.count);
6764
6765 return complete_emulated_io(vcpu);
6766}
6767
f78146b0
AK		 6768/*
6769 * Implements the following, as a state machine:
6770 *
6771 * read:
6772 * for each fragment
87da7e66
XG		 6773 * for each mmio piece in the fragment
6774 * write gpa, len
6775 * exit
6776 * copy data
f78146b0
AK		 6777 * execute insn
6778 *
6779 * write:
6780 * for each fragment
87da7e66
XG		 6781 * for each mmio piece in the fragment
6782 * write gpa, len
6783 * copy data
6784 * exit
f78146b0 6785 */
716d51ab 6786static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6787{
6788 struct kvm_run *run = vcpu->run;
f78146b0 6789 struct kvm_mmio_fragment *frag;
87da7e66 6790 unsigned len;
5287f194 6791
716d51ab 6792 BUG_ON(!vcpu->mmio_needed);
5287f194 6793
716d51ab 6794 /* Complete previous fragment */
87da7e66
XG		 6795 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6796 len = min(8u, frag->len);
716d51ab 6797 if (!vcpu->mmio_is_write)
87da7e66
XG		 6798 memcpy(frag->data, run->mmio.data, len);
6799
6800 if (frag->len <= 8) {
6801 /* Switch to the next fragment. */
6802 frag++;
6803 vcpu->mmio_cur_fragment++;
6804 } else {
6805 /* Go forward to the next mmio piece. */
6806 frag->data += len;
6807 frag->gpa += len;
6808 frag->len -= len;
6809 }
6810
a08d3b3b 6811 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6812 vcpu->mmio_needed = 0;
0912c977
PB		 6813
6814 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6815 if (vcpu->mmio_is_write)
716d51ab
GN		 6816 return 1;
6817 vcpu->mmio_read_completed = 1;
6818 return complete_emulated_io(vcpu);
6819 }
87da7e66 6820
716d51ab
GN		 6821 run->exit_reason = KVM_EXIT_MMIO;
6822 run->mmio.phys_addr = frag->gpa;
6823 if (vcpu->mmio_is_write)
87da7e66
XG		 6824 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6825 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6826 run->mmio.is_write = vcpu->mmio_is_write;
6827 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6828 return 0;
5287f194
AK		 6829}
6830
716d51ab 6831
b6c7a5dc
HB		 6832int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6833{
c5bedc68 6834 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 6835 int r;
6836 sigset_t sigsaved;
6837
c4d72e2d 6838 fpu__activate_curr(fpu);
e5c30142 6839
ac9f6dc0
AK		 6840 if (vcpu->sigset_active)
6841 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6842
a4535290 6843 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6844 kvm_vcpu_block(vcpu);
66450a21 6845 kvm_apic_accept_events(vcpu);
d7690175 6846 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6847 r = -EAGAIN;
6848 goto out;
b6c7a5dc
HB		 6849 }
6850
b6c7a5dc 6851 /* re-sync apic's tpr */
35754c98 6852 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 6853 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6854 r = -EINVAL;
6855 goto out;
6856 }
6857 }
b6c7a5dc 6858
716d51ab
GN		 6859 if (unlikely(vcpu->arch.complete_userspace_io)) {
6860 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6861 vcpu->arch.complete_userspace_io = NULL;
6862 r = cui(vcpu);
6863 if (r <= 0)
6864 goto out;
6865 } else
6866 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6867
362c698f 6868 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6869
6870out:
f1d86e46 6871 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6872 if (vcpu->sigset_active)
6873 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6874
b6c7a5dc
HB		 6875 return r;
6876}
6877
6878int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6879{
7ae441ea
GN		 6880 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6881 /*
6882 * We are here if userspace calls get_regs() in the middle of
6883 * instruction emulation. Registers state needs to be copied
4a969980 6884 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6885 * that usually, but some bad designed PV devices (vmware
6886 * backdoor interface) need this to work
6887 */
dd856efa 6888 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6889 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6890 }
5fdbf976
MT		 6891 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6892 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6893 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6894 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6895 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6896 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6897 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6898 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6899#ifdef CONFIG_X86_64
5fdbf976
MT		 6900 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6901 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6902 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6903 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6904 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6905 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6906 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6907 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6908#endif
6909
5fdbf976 6910 regs->rip = kvm_rip_read(vcpu);
91586a3b 6911 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6912
b6c7a5dc
HB		 6913 return 0;
6914}
6915
6916int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6917{
7ae441ea
GN		 6918 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6919 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6920
5fdbf976
MT		 6921 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6922 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6923 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6924 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6925 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6926 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6927 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6928 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6929#ifdef CONFIG_X86_64
5fdbf976
MT		 6930 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6931 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6932 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6933 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6934 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6935 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6936 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6937 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6938#endif
6939
5fdbf976 6940 kvm_rip_write(vcpu, regs->rip);
91586a3b 6941 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6942
b4f14abd
JK		 6943 vcpu->arch.exception.pending = false;
6944
3842d135
AK		 6945 kvm_make_request(KVM_REQ_EVENT, vcpu);
6946
b6c7a5dc
HB		 6947 return 0;
6948}
6949
b6c7a5dc
HB		 6950void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6951{
6952 struct kvm_segment cs;
6953
3e6e0aab 6954 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6955 *db = cs.db;
6956 *l = cs.l;
6957}
6958EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6959
6960int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6961 struct kvm_sregs *sregs)
6962{
89a27f4d 6963 struct desc_ptr dt;
b6c7a5dc 6964
3e6e0aab
GT		 6965 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6966 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6967 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6968 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6969 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6970 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6971
3e6e0aab
GT		 6972 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6973 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6974
6975 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6976 sregs->idt.limit = dt.size;
6977 sregs->idt.base = dt.address;
b6c7a5dc 6978 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6979 sregs->gdt.limit = dt.size;
6980 sregs->gdt.base = dt.address;
b6c7a5dc 6981
4d4ec087 6982 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6983 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6984 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6985 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6986 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6987 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6988 sregs->apic_base = kvm_get_apic_base(vcpu);
6989
923c61bb 6990 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6991
36752c9b 6992 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6993 set_bit(vcpu->arch.interrupt.nr,
6994 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6995
b6c7a5dc
HB		 6996 return 0;
6997}
6998
62d9f0db
MT		 6999int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7000 struct kvm_mp_state *mp_state)
7001{
66450a21 7002 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7003 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7004 vcpu->arch.pv.pv_unhalted)
7005 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7006 else
7007 mp_state->mp_state = vcpu->arch.mp_state;
7008
62d9f0db
MT		 7009 return 0;
7010}
7011
7012int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7013 struct kvm_mp_state *mp_state)
7014{
66450a21
JK		 7015 if (!kvm_vcpu_has_lapic(vcpu) &&
7016 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7017 return -EINVAL;
7018
7019 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7020 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7021 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7022 } else
7023 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7024 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7025 return 0;
7026}
7027
7f3d35fd
KW		 7028int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7029 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7030{
9d74191a 7031 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7032 int ret;
e01c2426 7033
8ec4722d 7034 init_emulate_ctxt(vcpu);
c697518a 7035
7f3d35fd 7036 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7037 has_error_code, error_code);
c697518a 7038
c697518a 7039 if (ret)
19d04437 7040 return EMULATE_FAIL;
37817f29 7041
9d74191a
TY		 7042 kvm_rip_write(vcpu, ctxt->eip);
7043 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7044 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7045 return EMULATE_DONE;
37817f29
IE		 7046}
7047EXPORT_SYMBOL_GPL(kvm_task_switch);
7048
b6c7a5dc
HB		 7049int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7050 struct kvm_sregs *sregs)
7051{
58cb628d 7052 struct msr_data apic_base_msr;
b6c7a5dc 7053 int mmu_reset_needed = 0;
63f42e02 7054 int pending_vec, max_bits, idx;
89a27f4d 7055 struct desc_ptr dt;
b6c7a5dc 7056
6d1068b3
PM		 7057 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7058 return -EINVAL;
7059
89a27f4d
GN		 7060 dt.size = sregs->idt.limit;
7061 dt.address = sregs->idt.base;
b6c7a5dc 7062 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7063 dt.size = sregs->gdt.limit;
7064 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7065 kvm_x86_ops->set_gdt(vcpu, &dt);
7066
ad312c7c 7067 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7068 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7069 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7070 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7071
2d3ad1f4 7072 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7073
f6801dff 7074 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7075 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7076 apic_base_msr.data = sregs->apic_base;
7077 apic_base_msr.host_initiated = true;
7078 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7079
4d4ec087 7080 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7081 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7082 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7083
fc78f519 7084 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7085 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 7086 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 7087 kvm_update_cpuid(vcpu);
63f42e02
XG		 7088
7089 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7090 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7091 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7092 mmu_reset_needed = 1;
7093 }
63f42e02 7094 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7095
7096 if (mmu_reset_needed)
7097 kvm_mmu_reset_context(vcpu);
7098
a50abc3b 7099 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7100 pending_vec = find_first_bit(
7101 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7102 if (pending_vec < max_bits) {
66fd3f7f 7103 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7104 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7105 }
7106
3e6e0aab
GT		 7107 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7108 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7109 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7110 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7111 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7112 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7113
3e6e0aab
GT		 7114 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7115 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7116
5f0269f5
ME		 7117 update_cr8_intercept(vcpu);
7118
9c3e4aab 7119 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7120 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7121 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7122 !is_protmode(vcpu))
9c3e4aab
MT		 7123 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7124
3842d135
AK		 7125 kvm_make_request(KVM_REQ_EVENT, vcpu);
7126
b6c7a5dc
HB		 7127 return 0;
7128}
7129
d0bfb940
JK		 7130int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7131 struct kvm_guest_debug *dbg)
b6c7a5dc 7132{
355be0b9 7133 unsigned long rflags;
ae675ef0 7134 int i, r;
b6c7a5dc 7135
4f926bf2
JK		 7136 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7137 r = -EBUSY;
7138 if (vcpu->arch.exception.pending)
2122ff5e 7139 goto out;
4f926bf2
JK		 7140 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7141 kvm_queue_exception(vcpu, DB_VECTOR);
7142 else
7143 kvm_queue_exception(vcpu, BP_VECTOR);
7144 }
7145
91586a3b
JK		 7146 /*
7147 * Read rflags as long as potentially injected trace flags are still
7148 * filtered out.
7149 */
7150 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7151
7152 vcpu->guest_debug = dbg->control;
7153 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7154 vcpu->guest_debug = 0;
7155
7156 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7157 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7158 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7159 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7160 } else {
7161 for (i = 0; i < KVM_NR_DB_REGS; i++)
7162 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7163 }
c8639010 7164 kvm_update_dr7(vcpu);
ae675ef0 7165
f92653ee
JK		 7166 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7167 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7168 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7169
91586a3b
JK		 7170 /*
7171 * Trigger an rflags update that will inject or remove the trace
7172 * flags.
7173 */
7174 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7175
a96036b8 7176 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7177
4f926bf2 7178 r = 0;
d0bfb940 7179
2122ff5e 7180out:
b6c7a5dc
HB		 7181
7182 return r;
7183}
7184
8b006791
ZX		 7185/*
7186 * Translate a guest virtual address to a guest physical address.
7187 */
7188int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7189 struct kvm_translation *tr)
7190{
7191 unsigned long vaddr = tr->linear_address;
7192 gpa_t gpa;
f656ce01 7193 int idx;
8b006791 7194
f656ce01 7195 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7196 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7197 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7198 tr->physical_address = gpa;
7199 tr->valid = gpa != UNMAPPED_GVA;
7200 tr->writeable = 1;
7201 tr->usermode = 0;
8b006791
ZX		 7202
7203 return 0;
7204}
7205
d0752060
HB		 7206int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7207{
c47ada30 7208 struct fxregs_state *fxsave =
7366ed77 7209 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7210
d0752060
HB		 7211 memcpy(fpu->fpr, fxsave->st_space, 128);
7212 fpu->fcw = fxsave->cwd;
7213 fpu->fsw = fxsave->swd;
7214 fpu->ftwx = fxsave->twd;
7215 fpu->last_opcode = fxsave->fop;
7216 fpu->last_ip = fxsave->rip;
7217 fpu->last_dp = fxsave->rdp;
7218 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7219
d0752060
HB		 7220 return 0;
7221}
7222
7223int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7224{
c47ada30 7225 struct fxregs_state *fxsave =
7366ed77 7226 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7227
d0752060
HB		 7228 memcpy(fxsave->st_space, fpu->fpr, 128);
7229 fxsave->cwd = fpu->fcw;
7230 fxsave->swd = fpu->fsw;
7231 fxsave->twd = fpu->ftwx;
7232 fxsave->fop = fpu->last_opcode;
7233 fxsave->rip = fpu->last_ip;
7234 fxsave->rdp = fpu->last_dp;
7235 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7236
d0752060
HB		 7237 return 0;
7238}
7239
0ee6a517 7240static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7241{
bf935b0b 7242 fpstate_init(&vcpu->arch.guest_fpu.state);
df1daba7 7243 if (cpu_has_xsaves)
7366ed77 7244 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7245 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7246
2acf923e
DC		 7247 /*
7248 * Ensure guest xcr0 is valid for loading
7249 */
d91cab78 7250 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7251
ad312c7c 7252 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7253}
d0752060
HB		 7254
7255void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7256{
2608d7a1 7257 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7258 return;
7259
2acf923e
DC		 7260 /*
7261 * Restore all possible states in the guest,
7262 * and assume host would use all available bits.
7263 * Guest xcr0 would be loaded later.
7264 */
7265 kvm_put_guest_xcr0(vcpu);
d0752060 7266 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7267 __kernel_fpu_begin();
003e2e8b 7268 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7269 trace_kvm_fpu(1);
d0752060 7270}
d0752060
HB		 7271
7272void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7273{
2acf923e
DC		 7274 kvm_put_guest_xcr0(vcpu);
7275
653f52c3
RR		 7276 if (!vcpu->guest_fpu_loaded) {
7277 vcpu->fpu_counter = 0;
d0752060 7278 return;
653f52c3 7279 }
d0752060
HB		 7280
7281 vcpu->guest_fpu_loaded = 0;
4f836347 7282 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7283 __kernel_fpu_end();
f096ed85 7284 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7285 /*
7286 * If using eager FPU mode, or if the guest is a frequent user
7287 * of the FPU, just leave the FPU active for next time.
7288 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7289 * the FPU in bursts will revert to loading it on demand.
7290 */
a9b4fb7e 7291 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7292 if (++vcpu->fpu_counter < 5)
7293 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7294 }
0c04851c 7295 trace_kvm_fpu(0);
d0752060 7296}
e9b11c17
ZX		 7297
7298void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7299{
12f9a48f 7300 kvmclock_reset(vcpu);
7f1ea208 7301
f5f48ee1 7302 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
e9b11c17
ZX		 7303 kvm_x86_ops->vcpu_free(vcpu);
7304}
7305
7306struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7307 unsigned int id)
7308{
c447e76b
LL		 7309 struct kvm_vcpu *vcpu;
7310
6755bae8
ZA		 7311 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7312 printk_once(KERN_WARNING
7313 "kvm: SMP vm created on host with unstable TSC; "
7314 "guest TSC will not be reliable\n");
c447e76b
LL		 7315
7316 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7317
c447e76b 7318 return vcpu;
26e5215f 7319}
e9b11c17 7320
26e5215f
AK		 7321int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7322{
7323 int r;
e9b11c17 7324
19efffa2 7325 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7326 r = vcpu_load(vcpu);
7327 if (r)
7328 return r;
d28bc9dd 7329 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7330 kvm_mmu_setup(vcpu);
e9b11c17 7331 vcpu_put(vcpu);
26e5215f 7332 return r;
e9b11c17
ZX		 7333}
7334
31928aa5 7335void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7336{
8fe8ab46 7337 struct msr_data msr;
332967a3 7338 struct kvm *kvm = vcpu->kvm;
42897d86 7339
31928aa5
DD		 7340 if (vcpu_load(vcpu))
7341 return;
8fe8ab46
WA		 7342 msr.data = 0x0;
7343 msr.index = MSR_IA32_TSC;
7344 msr.host_initiated = true;
7345 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7346 vcpu_put(vcpu);
7347
630994b3
MT		 7348 if (!kvmclock_periodic_sync)
7349 return;
7350
332967a3
AJ		 7351 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7352 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7353}
7354
d40ccc62 7355void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7356{
9fc77441 7357 int r;
344d9588
GN		 7358 vcpu->arch.apf.msr_val = 0;
7359
9fc77441
MT		 7360 r = vcpu_load(vcpu);
7361 BUG_ON(r);
e9b11c17
ZX		 7362 kvm_mmu_unload(vcpu);
7363 vcpu_put(vcpu);
7364
7365 kvm_x86_ops->vcpu_free(vcpu);
7366}
7367
d28bc9dd 7368void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7369{
e69fab5d
PB		 7370 vcpu->arch.hflags = 0;
7371
7460fb4a
AK		 7372 atomic_set(&vcpu->arch.nmi_queued, 0);
7373 vcpu->arch.nmi_pending = 0;
448fa4a9 7374 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7375 kvm_clear_interrupt_queue(vcpu);
7376 kvm_clear_exception_queue(vcpu);
448fa4a9 7377
42dbaa5a 7378 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7379 kvm_update_dr0123(vcpu);
6f43ed01 7380 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7381 kvm_update_dr6(vcpu);
42dbaa5a 7382 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7383 kvm_update_dr7(vcpu);
42dbaa5a 7384
1119022c
NA		 7385 vcpu->arch.cr2 = 0;
7386
3842d135 7387 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7388 vcpu->arch.apf.msr_val = 0;
c9aaa895 7389 vcpu->arch.st.msr_val = 0;
3842d135 7390
12f9a48f
GC		 7391 kvmclock_reset(vcpu);
7392
af585b92
GN		 7393 kvm_clear_async_pf_completion_queue(vcpu);
7394 kvm_async_pf_hash_reset(vcpu);
7395 vcpu->arch.apf.halted = false;
3842d135 7396
64d60670 7397 if (!init_event) {
d28bc9dd 7398 kvm_pmu_reset(vcpu);
64d60670
PB		 7399 vcpu->arch.smbase = 0x30000;
7400 }
f5132b01 7401
66f7b72e
JS		 7402 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7403 vcpu->arch.regs_avail = ~0;
7404 vcpu->arch.regs_dirty = ~0;
7405
d28bc9dd 7406 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7407}
7408
2b4a273b 7409void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7410{
7411 struct kvm_segment cs;
7412
7413 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7414 cs.selector = vector << 8;
7415 cs.base = vector << 12;
7416 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7417 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7418}
7419
13a34e06 7420int kvm_arch_hardware_enable(void)
e9b11c17 7421{
ca84d1a2
ZA		 7422 struct kvm *kvm;
7423 struct kvm_vcpu *vcpu;
7424 int i;
0dd6a6ed
ZA		 7425 int ret;
7426 u64 local_tsc;
7427 u64 max_tsc = 0;
7428 bool stable, backwards_tsc = false;
18863bdd
AK		 7429
7430 kvm_shared_msr_cpu_online();
13a34e06 7431 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7432 if (ret != 0)
7433 return ret;
7434
4ea1636b 7435 local_tsc = rdtsc();
0dd6a6ed
ZA		 7436 stable = !check_tsc_unstable();
7437 list_for_each_entry(kvm, &vm_list, vm_list) {
7438 kvm_for_each_vcpu(i, vcpu, kvm) {
7439 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7440 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7441 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7442 backwards_tsc = true;
7443 if (vcpu->arch.last_host_tsc > max_tsc)
7444 max_tsc = vcpu->arch.last_host_tsc;
7445 }
7446 }
7447 }
7448
7449 /*
7450 * Sometimes, even reliable TSCs go backwards. This happens on
7451 * platforms that reset TSC during suspend or hibernate actions, but
7452 * maintain synchronization. We must compensate. Fortunately, we can
7453 * detect that condition here, which happens early in CPU bringup,
7454 * before any KVM threads can be running. Unfortunately, we can't
7455 * bring the TSCs fully up to date with real time, as we aren't yet far
7456 * enough into CPU bringup that we know how much real time has actually
7457 * elapsed; our helper function, get_kernel_ns() will be using boot
7458 * variables that haven't been updated yet.
7459 *
7460 * So we simply find the maximum observed TSC above, then record the
7461 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7462 * the adjustment will be applied. Note that we accumulate
7463 * adjustments, in case multiple suspend cycles happen before some VCPU
7464 * gets a chance to run again. In the event that no KVM threads get a
7465 * chance to run, we will miss the entire elapsed period, as we'll have
7466 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7467 * loose cycle time. This isn't too big a deal, since the loss will be
7468 * uniform across all VCPUs (not to mention the scenario is extremely
7469 * unlikely). It is possible that a second hibernate recovery happens
7470 * much faster than a first, causing the observed TSC here to be
7471 * smaller; this would require additional padding adjustment, which is
7472 * why we set last_host_tsc to the local tsc observed here.
7473 *
7474 * N.B. - this code below runs only on platforms with reliable TSC,
7475 * as that is the only way backwards_tsc is set above. Also note
7476 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7477 * have the same delta_cyc adjustment applied if backwards_tsc
7478 * is detected. Note further, this adjustment is only done once,
7479 * as we reset last_host_tsc on all VCPUs to stop this from being
7480 * called multiple times (one for each physical CPU bringup).
7481 *
4a969980 7482 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7483 * will be compensated by the logic in vcpu_load, which sets the TSC to
7484 * catchup mode. This will catchup all VCPUs to real time, but cannot
7485 * guarantee that they stay in perfect synchronization.
7486 */
7487 if (backwards_tsc) {
7488 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7489 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7490 list_for_each_entry(kvm, &vm_list, vm_list) {
7491 kvm_for_each_vcpu(i, vcpu, kvm) {
7492 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7493 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7494 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7495 }
7496
7497 /*
7498 * We have to disable TSC offset matching.. if you were
7499 * booting a VM while issuing an S4 host suspend....
7500 * you may have some problem. Solving this issue is
7501 * left as an exercise to the reader.
7502 */
7503 kvm->arch.last_tsc_nsec = 0;
7504 kvm->arch.last_tsc_write = 0;
7505 }
7506
7507 }
7508 return 0;
e9b11c17
ZX		 7509}
7510
13a34e06 7511void kvm_arch_hardware_disable(void)
e9b11c17 7512{
13a34e06
RK		 7513 kvm_x86_ops->hardware_disable();
7514 drop_user_return_notifiers();
e9b11c17
ZX		 7515}
7516
7517int kvm_arch_hardware_setup(void)
7518{
9e9c3fe4
NA		 7519 int r;
7520
7521 r = kvm_x86_ops->hardware_setup();
7522 if (r != 0)
7523 return r;
7524
35181e86
HZ		 7525 if (kvm_has_tsc_control) {
7526 /*
7527 * Make sure the user can only configure tsc_khz values that
7528 * fit into a signed integer.
7529 * A min value is not calculated needed because it will always
7530 * be 1 on all machines.
7531 */
7532 u64 max = min(0x7fffffffULL,
7533 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7534 kvm_max_guest_tsc_khz = max;
7535
ad721883 7536 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7537 }
ad721883 7538
9e9c3fe4
NA		 7539 kvm_init_msr_list();
7540 return 0;
e9b11c17
ZX		 7541}
7542
7543void kvm_arch_hardware_unsetup(void)
7544{
7545 kvm_x86_ops->hardware_unsetup();
7546}
7547
7548void kvm_arch_check_processor_compat(void *rtn)
7549{
7550 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7551}
7552
7553bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7554{
7555 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7556}
7557EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7558
7559bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7560{
7561 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7562}
7563
3e515705
AK		 7564bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7565{
35754c98 7566 return irqchip_in_kernel(vcpu->kvm) == lapic_in_kernel(vcpu);
3e515705
AK		 7567}
7568
54e9818f
GN		 7569struct static_key kvm_no_apic_vcpu __read_mostly;
7570
e9b11c17
ZX		 7571int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7572{
7573 struct page *page;
7574 struct kvm *kvm;
7575 int r;
7576
7577 BUG_ON(vcpu->kvm == NULL);
7578 kvm = vcpu->kvm;
7579
d62caabb 7580 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7581 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7582 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7583 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7584 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7585 else
a4535290 7586 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7587
7588 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7589 if (!page) {
7590 r = -ENOMEM;
7591 goto fail;
7592 }
ad312c7c 7593 vcpu->arch.pio_data = page_address(page);
e9b11c17 7594
cc578287 7595 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7596
e9b11c17
ZX		 7597 r = kvm_mmu_create(vcpu);
7598 if (r < 0)
7599 goto fail_free_pio_data;
7600
7601 if (irqchip_in_kernel(kvm)) {
7602 r = kvm_create_lapic(vcpu);
7603 if (r < 0)
7604 goto fail_mmu_destroy;
54e9818f
GN		 7605 } else
7606 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7607
890ca9ae
HY		 7608 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7609 GFP_KERNEL);
7610 if (!vcpu->arch.mce_banks) {
7611 r = -ENOMEM;
443c39bc 7612 goto fail_free_lapic;
890ca9ae
HY		 7613 }
7614 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7615
f1797359
WY		 7616 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7617 r = -ENOMEM;
f5f48ee1 7618 goto fail_free_mce_banks;
f1797359 7619 }
f5f48ee1 7620
0ee6a517 7621 fx_init(vcpu);
66f7b72e 7622
ba904635 7623 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7624 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7625
7626 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7627 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7628
5a4f55cd
EK		 7629 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7630
74545705
RK		 7631 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7632
af585b92 7633 kvm_async_pf_hash_reset(vcpu);
f5132b01 7634 kvm_pmu_init(vcpu);
af585b92 7635
1c1a9ce9
SR		 7636 vcpu->arch.pending_external_vector = -1;
7637
5c919412
AS		 7638 kvm_hv_vcpu_init(vcpu);
7639
e9b11c17 7640 return 0;
0ee6a517 7641
f5f48ee1
SY		 7642fail_free_mce_banks:
7643 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7644fail_free_lapic:
7645 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7646fail_mmu_destroy:
7647 kvm_mmu_destroy(vcpu);
7648fail_free_pio_data:
ad312c7c 7649 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7650fail:
7651 return r;
7652}
7653
7654void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7655{
f656ce01
MT		 7656 int idx;
7657
1f4b34f8 7658 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7659 kvm_pmu_destroy(vcpu);
36cb93fd 7660 kfree(vcpu->arch.mce_banks);
e9b11c17 7661 kvm_free_lapic(vcpu);
f656ce01 7662 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7663 kvm_mmu_destroy(vcpu);
f656ce01 7664 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7665 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7666 if (!lapic_in_kernel(vcpu))
54e9818f 7667 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7668}
d19a9cd2 7669
e790d9ef
RK		 7670void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7671{
ae97a3b8 7672 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7673}
7674
e08b9637 7675int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7676{
e08b9637
CO		 7677 if (type)
7678 return -EINVAL;
7679
6ef768fa 7680 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7681 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7682 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7683 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7684 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7685
5550af4d
SY		 7686 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7687 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7688 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7689 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7690 &kvm->arch.irq_sources_bitmap);
5550af4d 7691
038f8c11 7692 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7693 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7694 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7695
7696 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7697
7e44e449 7698 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7699 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7700
d89f5eff 7701 return 0;
d19a9cd2
ZX		 7702}
7703
7704static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7705{
9fc77441
MT		 7706 int r;
7707 r = vcpu_load(vcpu);
7708 BUG_ON(r);
d19a9cd2
ZX		 7709 kvm_mmu_unload(vcpu);
7710 vcpu_put(vcpu);
7711}
7712
7713static void kvm_free_vcpus(struct kvm *kvm)
7714{
7715 unsigned int i;
988a2cae 7716 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7717
7718 /*
7719 * Unpin any mmu pages first.
7720 */
af585b92
GN		 7721 kvm_for_each_vcpu(i, vcpu, kvm) {
7722 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7723 kvm_unload_vcpu_mmu(vcpu);
af585b92 7724 }
988a2cae
GN		 7725 kvm_for_each_vcpu(i, vcpu, kvm)
7726 kvm_arch_vcpu_free(vcpu);
7727
7728 mutex_lock(&kvm->lock);
7729 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7730 kvm->vcpus[i] = NULL;
d19a9cd2 7731
988a2cae
GN		 7732 atomic_set(&kvm->online_vcpus, 0);
7733 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7734}
7735
ad8ba2cd
SY		 7736void kvm_arch_sync_events(struct kvm *kvm)
7737{
332967a3 7738 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7739 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7740 kvm_free_all_assigned_devices(kvm);
aea924f6 7741 kvm_free_pit(kvm);
ad8ba2cd
SY		 7742}
7743
1d8007bd 7744int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7745{
7746 int i, r;
25188b99 7747 unsigned long hva;
f0d648bd
PB		 7748 struct kvm_memslots *slots = kvm_memslots(kvm);
7749 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 7750
7751 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 7752 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
7753 return -EINVAL;
9da0e4d5 7754
f0d648bd
PB		 7755 slot = id_to_memslot(slots, id);
7756 if (size) {
7757 if (WARN_ON(slot->npages))
7758 return -EEXIST;
7759
7760 /*
7761 * MAP_SHARED to prevent internal slot pages from being moved
7762 * by fork()/COW.
7763 */
7764 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
7765 MAP_SHARED | MAP_ANONYMOUS, 0);
7766 if (IS_ERR((void *)hva))
7767 return PTR_ERR((void *)hva);
7768 } else {
7769 if (!slot->npages)
7770 return 0;
7771
7772 hva = 0;
7773 }
7774
7775 old = *slot;
9da0e4d5 7776 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 7777 struct kvm_userspace_memory_region m;
9da0e4d5 7778
1d8007bd
PB		 7779 m.slot = id | (i << 16);
7780 m.flags = 0;
7781 m.guest_phys_addr = gpa;
f0d648bd 7782 m.userspace_addr = hva;
1d8007bd 7783 m.memory_size = size;
9da0e4d5
PB		 7784 r = __kvm_set_memory_region(kvm, &m);
7785 if (r < 0)
7786 return r;
7787 }
7788
f0d648bd
PB		 7789 if (!size) {
7790 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
7791 WARN_ON(r < 0);
7792 }
7793
9da0e4d5
PB		 7794 return 0;
7795}
7796EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7797
1d8007bd 7798int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 7799{
7800 int r;
7801
7802 mutex_lock(&kvm->slots_lock);
1d8007bd 7803 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 7804 mutex_unlock(&kvm->slots_lock);
7805
7806 return r;
7807}
7808EXPORT_SYMBOL_GPL(x86_set_memory_region);
7809
d19a9cd2
ZX		 7810void kvm_arch_destroy_vm(struct kvm *kvm)
7811{
27469d29
AH		 7812 if (current->mm == kvm->mm) {
7813 /*
7814 * Free memory regions allocated on behalf of userspace,
7815 * unless the the memory map has changed due to process exit
7816 * or fd copying.
7817 */
1d8007bd
PB		 7818 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
7819 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
7820 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 7821 }
6eb55818 7822 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7823 kfree(kvm->arch.vpic);
7824 kfree(kvm->arch.vioapic);
d19a9cd2 7825 kvm_free_vcpus(kvm);
1e08ec4a 7826 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7827}
0de10343 7828
5587027c 7829void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7830 struct kvm_memory_slot *dont)
7831{
7832 int i;
7833
d89cc617
TY		 7834 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7835 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7836 kvfree(free->arch.rmap[i]);
d89cc617 7837 free->arch.rmap[i] = NULL;
77d11309 7838 }
d89cc617
TY		 7839 if (i == 0)
7840 continue;
7841
7842 if (!dont || free->arch.lpage_info[i - 1] !=
7843 dont->arch.lpage_info[i - 1]) {
548ef284 7844 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7845 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7846 }
7847 }
7848}
7849
5587027c
AK		 7850int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7851 unsigned long npages)
db3fe4eb
TY		 7852{
7853 int i;
7854
d89cc617 7855 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7856 unsigned long ugfn;
7857 int lpages;
d89cc617 7858 int level = i + 1;
db3fe4eb
TY		 7859
7860 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7861 slot->base_gfn, level) + 1;
7862
d89cc617
TY		 7863 slot->arch.rmap[i] =
7864 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7865 if (!slot->arch.rmap[i])
77d11309 7866 goto out_free;
d89cc617
TY		 7867 if (i == 0)
7868 continue;
77d11309 7869
d89cc617
TY		 7870 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7871 sizeof(*slot->arch.lpage_info[i - 1]));
7872 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7873 goto out_free;
7874
7875 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7876 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7877 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7878 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7879 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7880 /*
7881 * If the gfn and userspace address are not aligned wrt each
7882 * other, or if explicitly asked to, disable large page
7883 * support for this slot
7884 */
7885 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7886 !kvm_largepages_enabled()) {
7887 unsigned long j;
7888
7889 for (j = 0; j < lpages; ++j)
d89cc617 7890 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7891 }
7892 }
7893
7894 return 0;
7895
7896out_free:
d89cc617 7897 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7898 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7899 slot->arch.rmap[i] = NULL;
7900 if (i == 0)
7901 continue;
7902
548ef284 7903 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7904 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7905 }
7906 return -ENOMEM;
7907}
7908
15f46015 7909void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7910{
e6dff7d1
TY		 7911 /*
7912 * memslots->generation has been incremented.
7913 * mmio generation may have reached its maximum value.
7914 */
54bf36aa 7915 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7916}
7917
f7784b8e
MT		 7918int kvm_arch_prepare_memory_region(struct kvm *kvm,
7919 struct kvm_memory_slot *memslot,
09170a49 7920 const struct kvm_userspace_memory_region *mem,
7b6195a9 7921 enum kvm_mr_change change)
0de10343 7922{
f7784b8e
MT		 7923 return 0;
7924}
7925
88178fd4
KH		 7926static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7927 struct kvm_memory_slot *new)
7928{
7929 /* Still write protect RO slot */
7930 if (new->flags & KVM_MEM_READONLY) {
7931 kvm_mmu_slot_remove_write_access(kvm, new);
7932 return;
7933 }
7934
7935 /*
7936 * Call kvm_x86_ops dirty logging hooks when they are valid.
7937 *
7938 * kvm_x86_ops->slot_disable_log_dirty is called when:
7939 *
7940 * - KVM_MR_CREATE with dirty logging is disabled
7941 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7942 *
7943 * The reason is, in case of PML, we need to set D-bit for any slots
7944 * with dirty logging disabled in order to eliminate unnecessary GPA
7945 * logging in PML buffer (and potential PML buffer full VMEXT). This
7946 * guarantees leaving PML enabled during guest's lifetime won't have
7947 * any additonal overhead from PML when guest is running with dirty
7948 * logging disabled for memory slots.
7949 *
7950 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7951 * to dirty logging mode.
7952 *
7953 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7954 *
7955 * In case of write protect:
7956 *
7957 * Write protect all pages for dirty logging.
7958 *
7959 * All the sptes including the large sptes which point to this
7960 * slot are set to readonly. We can not create any new large
7961 * spte on this slot until the end of the logging.
7962 *
7963 * See the comments in fast_page_fault().
7964 */
7965 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7966 if (kvm_x86_ops->slot_enable_log_dirty)
7967 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7968 else
7969 kvm_mmu_slot_remove_write_access(kvm, new);
7970 } else {
7971 if (kvm_x86_ops->slot_disable_log_dirty)
7972 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
7973 }
7974}
7975
f7784b8e 7976void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 7977 const struct kvm_userspace_memory_region *mem,
8482644a 7978 const struct kvm_memory_slot *old,
f36f3f28 7979 const struct kvm_memory_slot *new,
8482644a 7980 enum kvm_mr_change change)
f7784b8e 7981{
8482644a 7982 int nr_mmu_pages = 0;
f7784b8e 7983
48c0e4e9
XG		 7984 if (!kvm->arch.n_requested_mmu_pages)
7985 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7986
48c0e4e9 7987 if (nr_mmu_pages)
0de10343 7988 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 7989
3ea3b7fa
WL		 7990 /*
7991 * Dirty logging tracks sptes in 4k granularity, meaning that large
7992 * sptes have to be split. If live migration is successful, the guest
7993 * in the source machine will be destroyed and large sptes will be
7994 * created in the destination. However, if the guest continues to run
7995 * in the source machine (for example if live migration fails), small
7996 * sptes will remain around and cause bad performance.
7997 *
7998 * Scan sptes if dirty logging has been stopped, dropping those
7999 * which can be collapsed into a single large-page spte. Later
8000 * page faults will create the large-page sptes.
8001 */
8002 if ((change != KVM_MR_DELETE) &&
8003 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8004 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8005 kvm_mmu_zap_collapsible_sptes(kvm, new);
8006
c972f3b1 8007 /*
88178fd4 8008 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8009 *
88178fd4
KH		 8010 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8011 * been zapped so no dirty logging staff is needed for old slot. For
8012 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8013 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8014 *
8015 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8016 */
88178fd4 8017 if (change != KVM_MR_DELETE)
f36f3f28 8018 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8019}
1d737c8a 8020
2df72e9b 8021void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8022{
6ca18b69 8023 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8024}
8025
2df72e9b
MT		 8026void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8027 struct kvm_memory_slot *slot)
8028{
6ca18b69 8029 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8030}
8031
5d9bc648
PB		 8032static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8033{
8034 if (!list_empty_careful(&vcpu->async_pf.done))
8035 return true;
8036
8037 if (kvm_apic_has_events(vcpu))
8038 return true;
8039
8040 if (vcpu->arch.pv.pv_unhalted)
8041 return true;
8042
8043 if (atomic_read(&vcpu->arch.nmi_queued))
8044 return true;
8045
73917739
PB		 8046 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8047 return true;
8048
5d9bc648
PB		 8049 if (kvm_arch_interrupt_allowed(vcpu) &&
8050 kvm_cpu_has_interrupt(vcpu))
8051 return true;
8052
1f4b34f8
AS		 8053 if (kvm_hv_has_stimer_pending(vcpu))
8054 return true;
8055
5d9bc648
PB		 8056 return false;
8057}
8058
1d737c8a
ZX		 8059int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8060{
b6b8a145
JK		 8061 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8062 kvm_x86_ops->check_nested_events(vcpu, false);
8063
5d9bc648 8064 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8065}
5736199a 8066
b6d33834 8067int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8068{
b6d33834 8069 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8070}
78646121
GN		 8071
8072int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8073{
8074 return kvm_x86_ops->interrupt_allowed(vcpu);
8075}
229456fc 8076
82b32774 8077unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8078{
82b32774
NA		 8079 if (is_64_bit_mode(vcpu))
8080 return kvm_rip_read(vcpu);
8081 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8082 kvm_rip_read(vcpu));
8083}
8084EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8085
82b32774
NA		 8086bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8087{
8088 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8089}
8090EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8091
94fe45da
JK		 8092unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8093{
8094 unsigned long rflags;
8095
8096 rflags = kvm_x86_ops->get_rflags(vcpu);
8097 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8098 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8099 return rflags;
8100}
8101EXPORT_SYMBOL_GPL(kvm_get_rflags);
8102
6addfc42 8103static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8104{
8105 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8106 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8107 rflags |= X86_EFLAGS_TF;
94fe45da 8108 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8109}
8110
8111void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8112{
8113 __kvm_set_rflags(vcpu, rflags);
3842d135 8114 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8115}
8116EXPORT_SYMBOL_GPL(kvm_set_rflags);
8117
56028d08
GN		 8118void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8119{
8120 int r;
8121
fb67e14f 8122 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8123 work->wakeup_all)
56028d08
GN		 8124 return;
8125
8126 r = kvm_mmu_reload(vcpu);
8127 if (unlikely(r))
8128 return;
8129
fb67e14f
XG		 8130 if (!vcpu->arch.mmu.direct_map &&
8131 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8132 return;
8133
56028d08
GN		 8134 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8135}
8136
af585b92
GN		 8137static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8138{
8139 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8140}
8141
8142static inline u32 kvm_async_pf_next_probe(u32 key)
8143{
8144 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8145}
8146
8147static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8148{
8149 u32 key = kvm_async_pf_hash_fn(gfn);
8150
8151 while (vcpu->arch.apf.gfns[key] != ~0)
8152 key = kvm_async_pf_next_probe(key);
8153
8154 vcpu->arch.apf.gfns[key] = gfn;
8155}
8156
8157static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8158{
8159 int i;
8160 u32 key = kvm_async_pf_hash_fn(gfn);
8161
8162 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8163 (vcpu->arch.apf.gfns[key] != gfn &&
8164 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8165 key = kvm_async_pf_next_probe(key);
8166
8167 return key;
8168}
8169
8170bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8171{
8172 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8173}
8174
8175static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8176{
8177 u32 i, j, k;
8178
8179 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8180 while (true) {
8181 vcpu->arch.apf.gfns[i] = ~0;
8182 do {
8183 j = kvm_async_pf_next_probe(j);
8184 if (vcpu->arch.apf.gfns[j] == ~0)
8185 return;
8186 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8187 /*
8188 * k lies cyclically in ]i,j]
8189 * | i.k.j |
8190 * |....j i.k.| or |.k..j i...|
8191 */
8192 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8193 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8194 i = j;
8195 }
8196}
8197
7c90705b
GN		 8198static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8199{
8200
8201 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8202 sizeof(val));
8203}
8204
af585b92
GN		 8205void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8206 struct kvm_async_pf *work)
8207{
6389ee94
AK		 8208 struct x86_exception fault;
8209
7c90705b 8210 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8211 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8212
8213 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8214 (vcpu->arch.apf.send_user_only &&
8215 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8216 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8217 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8218 fault.vector = PF_VECTOR;
8219 fault.error_code_valid = true;
8220 fault.error_code = 0;
8221 fault.nested_page_fault = false;
8222 fault.address = work->arch.token;
8223 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8224 }
af585b92
GN		 8225}
8226
8227void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8228 struct kvm_async_pf *work)
8229{
6389ee94
AK		 8230 struct x86_exception fault;
8231
7c90705b 8232 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8233 if (work->wakeup_all)
7c90705b
GN		 8234 work->arch.token = ~0; /* broadcast wakeup */
8235 else
8236 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8237
8238 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8239 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8240 fault.vector = PF_VECTOR;
8241 fault.error_code_valid = true;
8242 fault.error_code = 0;
8243 fault.nested_page_fault = false;
8244 fault.address = work->arch.token;
8245 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8246 }
e6d53e3b 8247 vcpu->arch.apf.halted = false;
a4fa1635 8248 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8249}
8250
8251bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8252{
8253 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8254 return true;
8255 else
8256 return !kvm_event_needs_reinjection(vcpu) &&
8257 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8258}
8259
5544eb9b
PB		 8260void kvm_arch_start_assignment(struct kvm *kvm)
8261{
8262 atomic_inc(&kvm->arch.assigned_device_count);
8263}
8264EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8265
8266void kvm_arch_end_assignment(struct kvm *kvm)
8267{
8268 atomic_dec(&kvm->arch.assigned_device_count);
8269}
8270EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8271
8272bool kvm_arch_has_assigned_device(struct kvm *kvm)
8273{
8274 return atomic_read(&kvm->arch.assigned_device_count);
8275}
8276EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8277
e0f0bbc5
AW		 8278void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8279{
8280 atomic_inc(&kvm->arch.noncoherent_dma_count);
8281}
8282EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8283
8284void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8285{
8286 atomic_dec(&kvm->arch.noncoherent_dma_count);
8287}
8288EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8289
8290bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8291{
8292 return atomic_read(&kvm->arch.noncoherent_dma_count);
8293}
8294EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8295
87276880
FW		 8296int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8297 struct irq_bypass_producer *prod)
8298{
8299 struct kvm_kernel_irqfd *irqfd =
8300 container_of(cons, struct kvm_kernel_irqfd, consumer);
8301
8302 if (kvm_x86_ops->update_pi_irte) {
8303 irqfd->producer = prod;
8304 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8305 prod->irq, irqfd->gsi, 1);
8306 }
8307
8308 return -EINVAL;
8309}
8310
8311void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8312 struct irq_bypass_producer *prod)
8313{
8314 int ret;
8315 struct kvm_kernel_irqfd *irqfd =
8316 container_of(cons, struct kvm_kernel_irqfd, consumer);
8317
8318 if (!kvm_x86_ops->update_pi_irte) {
8319 WARN_ON(irqfd->producer != NULL);
8320 return;
8321 }
8322
8323 WARN_ON(irqfd->producer != prod);
8324 irqfd->producer = NULL;
8325
8326 /*
8327 * When producer of consumer is unregistered, we change back to
8328 * remapped mode, so we can re-use the current implementation
8329 * when the irq is masked/disabed or the consumer side (KVM
8330 * int this case doesn't want to receive the interrupts.
8331 */
8332 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8333 if (ret)
8334 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8335 " fails: %d\n", irqfd->consumer.token, ret);
8336}
8337
8338int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8339 uint32_t guest_irq, bool set)
8340{
8341 if (!kvm_x86_ops->update_pi_irte)
8342 return -EINVAL;
8343
8344 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8345}
8346
229456fc 8347EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8348EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8349EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8350EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8351EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8352EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8353EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8354EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8355EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8356EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8357EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8358EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8359EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8360EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8361EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8362EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8363EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
Linux 6.x block layer and io_uring tree(s)