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KVM: limit the number of pages per memory slot
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
aec51dc4 43#include <trace/events/kvm.h>
2ed152af 44
229456fc
MT		 45#define CREATE_TRACE_POINTS
46#include "trace.h"
043405e1 47
24f1e32c 48#include <asm/debugreg.h>
043405e1 49#include <asm/uaccess.h>
d825ed0a 50#include <asm/msr.h>
a5f61300 51#include <asm/desc.h>
0bed3b56 52#include <asm/mtrr.h>
890ca9ae 53#include <asm/mce.h>
043405e1 54
313a3dc7 55#define MAX_IO_MSRS 256
a03490ed
CO		 56#define CR0_RESERVED_BITS \
57 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
58 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
59 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
60#define CR4_RESERVED_BITS \
61 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
62 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
63 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
64 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
65
66#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 67
68#define KVM_MAX_MCE_BANKS 32
69#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
70
50a37eb4
JR		 71/* EFER defaults:
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
74 */
75#ifdef CONFIG_X86_64
76static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
77#else
78static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
79#endif
313a3dc7 80
ba1389b7
AK		 81#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
82#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 83
cb142eb7 84static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 85static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
86 struct kvm_cpuid_entry2 __user *entries);
87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
ed85c068
AP		 91int ignore_msrs = 0;
92module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
93
18863bdd
AK		 94#define KVM_NR_SHARED_MSRS 16
95
96struct kvm_shared_msrs_global {
97 int nr;
2bf78fa7 98 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 99};
100
101struct kvm_shared_msrs {
102 struct user_return_notifier urn;
103 bool registered;
2bf78fa7
SY		 104 struct kvm_shared_msr_values {
105 u64 host;
106 u64 curr;
107 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 108};
109
110static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
111static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
112
417bc304 113struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 114 { "pf_fixed", VCPU_STAT(pf_fixed) },
115 { "pf_guest", VCPU_STAT(pf_guest) },
116 { "tlb_flush", VCPU_STAT(tlb_flush) },
117 { "invlpg", VCPU_STAT(invlpg) },
118 { "exits", VCPU_STAT(exits) },
119 { "io_exits", VCPU_STAT(io_exits) },
120 { "mmio_exits", VCPU_STAT(mmio_exits) },
121 { "signal_exits", VCPU_STAT(signal_exits) },
122 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 123 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 124 { "halt_exits", VCPU_STAT(halt_exits) },
125 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 126 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 127 { "request_irq", VCPU_STAT(request_irq_exits) },
128 { "irq_exits", VCPU_STAT(irq_exits) },
129 { "host_state_reload", VCPU_STAT(host_state_reload) },
130 { "efer_reload", VCPU_STAT(efer_reload) },
131 { "fpu_reload", VCPU_STAT(fpu_reload) },
132 { "insn_emulation", VCPU_STAT(insn_emulation) },
133 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 134 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 135 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 136 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
137 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
138 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
139 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
140 { "mmu_flooded", VM_STAT(mmu_flooded) },
141 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 142 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 143 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 144 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 145 { "largepages", VM_STAT(lpages) },
417bc304
HB		 146 { NULL }
147};
148
18863bdd
AK		 149static void kvm_on_user_return(struct user_return_notifier *urn)
150{
151 unsigned slot;
18863bdd
AK		 152 struct kvm_shared_msrs *locals
153 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 154 struct kvm_shared_msr_values *values;
18863bdd
AK		 155
156 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 157 values = &locals->values[slot];
158 if (values->host != values->curr) {
159 wrmsrl(shared_msrs_global.msrs[slot], values->host);
160 values->curr = values->host;
18863bdd
AK		 161 }
162 }
163 locals->registered = false;
164 user_return_notifier_unregister(urn);
165}
166
2bf78fa7 167static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 168{
2bf78fa7 169 struct kvm_shared_msrs *smsr;
18863bdd
AK		 170 u64 value;
171
2bf78fa7
SY		 172 smsr = &__get_cpu_var(shared_msrs);
173 /* only read, and nobody should modify it at this time,
174 * so don't need lock */
175 if (slot >= shared_msrs_global.nr) {
176 printk(KERN_ERR "kvm: invalid MSR slot!");
177 return;
178 }
179 rdmsrl_safe(msr, &value);
180 smsr->values[slot].host = value;
181 smsr->values[slot].curr = value;
182}
183
184void kvm_define_shared_msr(unsigned slot, u32 msr)
185{
18863bdd
AK		 186 if (slot >= shared_msrs_global.nr)
187 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 188 shared_msrs_global.msrs[slot] = msr;
189 /* we need ensured the shared_msr_global have been updated */
190 smp_wmb();
18863bdd
AK		 191}
192EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
193
194static void kvm_shared_msr_cpu_online(void)
195{
196 unsigned i;
18863bdd
AK		 197
198 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 199 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 200}
201
d5696725 202void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 203{
204 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
205
2bf78fa7 206 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 207 return;
2bf78fa7
SY		 208 smsr->values[slot].curr = value;
209 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 210 if (!smsr->registered) {
211 smsr->urn.on_user_return = kvm_on_user_return;
212 user_return_notifier_register(&smsr->urn);
213 smsr->registered = true;
214 }
215}
216EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
217
3548bab5
AK		 218static void drop_user_return_notifiers(void *ignore)
219{
220 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
221
222 if (smsr->registered)
223 kvm_on_user_return(&smsr->urn);
224}
225
6866b83e
CO		 226u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
227{
228 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 229 return vcpu->arch.apic_base;
6866b83e 230 else
ad312c7c 231 return vcpu->arch.apic_base;
6866b83e
CO		 232}
233EXPORT_SYMBOL_GPL(kvm_get_apic_base);
234
235void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
236{
237 /* TODO: reserve bits check */
238 if (irqchip_in_kernel(vcpu->kvm))
239 kvm_lapic_set_base(vcpu, data);
240 else
ad312c7c 241 vcpu->arch.apic_base = data;
6866b83e
CO		 242}
243EXPORT_SYMBOL_GPL(kvm_set_apic_base);
244
3fd28fce
ED		 245#define EXCPT_BENIGN 0
246#define EXCPT_CONTRIBUTORY 1
247#define EXCPT_PF 2
248
249static int exception_class(int vector)
250{
251 switch (vector) {
252 case PF_VECTOR:
253 return EXCPT_PF;
254 case DE_VECTOR:
255 case TS_VECTOR:
256 case NP_VECTOR:
257 case SS_VECTOR:
258 case GP_VECTOR:
259 return EXCPT_CONTRIBUTORY;
260 default:
261 break;
262 }
263 return EXCPT_BENIGN;
264}
265
266static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
267 unsigned nr, bool has_error, u32 error_code)
268{
269 u32 prev_nr;
270 int class1, class2;
271
272 if (!vcpu->arch.exception.pending) {
273 queue:
274 vcpu->arch.exception.pending = true;
275 vcpu->arch.exception.has_error_code = has_error;
276 vcpu->arch.exception.nr = nr;
277 vcpu->arch.exception.error_code = error_code;
278 return;
279 }
280
281 /* to check exception */
282 prev_nr = vcpu->arch.exception.nr;
283 if (prev_nr == DF_VECTOR) {
284 /* triple fault -> shutdown */
285 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
286 return;
287 }
288 class1 = exception_class(prev_nr);
289 class2 = exception_class(nr);
290 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
291 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
292 /* generate double fault per SDM Table 5-5 */
293 vcpu->arch.exception.pending = true;
294 vcpu->arch.exception.has_error_code = true;
295 vcpu->arch.exception.nr = DF_VECTOR;
296 vcpu->arch.exception.error_code = 0;
297 } else
298 /* replace previous exception with a new one in a hope
299 that instruction re-execution will regenerate lost
300 exception */
301 goto queue;
302}
303
298101da
AK		 304void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
305{
3fd28fce 306 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 307}
308EXPORT_SYMBOL_GPL(kvm_queue_exception);
309
c3c91fee
AK		 310void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
311 u32 error_code)
312{
313 ++vcpu->stat.pf_guest;
ad312c7c 314 vcpu->arch.cr2 = addr;
c3c91fee
AK		 315 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
316}
317
3419ffc8
SY		 318void kvm_inject_nmi(struct kvm_vcpu *vcpu)
319{
320 vcpu->arch.nmi_pending = 1;
321}
322EXPORT_SYMBOL_GPL(kvm_inject_nmi);
323
298101da
AK		 324void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
325{
3fd28fce 326 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 327}
328EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
329
0a79b009
AK		 330/*
331 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
332 * a #GP and return false.
333 */
334bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 335{
0a79b009
AK		 336 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
337 return true;
338 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
339 return false;
298101da 340}
0a79b009 341EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 342
a03490ed
CO		 343/*
344 * Load the pae pdptrs. Return true is they are all valid.
345 */
346int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
347{
348 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
349 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
350 int i;
351 int ret;
ad312c7c 352 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 353
a03490ed
CO		 354 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
355 offset * sizeof(u64), sizeof(pdpte));
356 if (ret < 0) {
357 ret = 0;
358 goto out;
359 }
360 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 361 if (is_present_gpte(pdpte[i]) &&
20c466b5 362 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 363 ret = 0;
364 goto out;
365 }
366 }
367 ret = 1;
368
ad312c7c 369 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 370 __set_bit(VCPU_EXREG_PDPTR,
371 (unsigned long *)&vcpu->arch.regs_avail);
372 __set_bit(VCPU_EXREG_PDPTR,
373 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 374out:
a03490ed
CO		 375
376 return ret;
377}
cc4b6871 378EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 379
d835dfec
AK		 380static bool pdptrs_changed(struct kvm_vcpu *vcpu)
381{
ad312c7c 382 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 383 bool changed = true;
384 int r;
385
386 if (is_long_mode(vcpu) || !is_pae(vcpu))
387 return false;
388
6de4f3ad
AK		 389 if (!test_bit(VCPU_EXREG_PDPTR,
390 (unsigned long *)&vcpu->arch.regs_avail))
391 return true;
392
ad312c7c 393 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 394 if (r < 0)
395 goto out;
ad312c7c 396 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 397out:
d835dfec
AK		 398
399 return changed;
400}
401
2d3ad1f4 402void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 403{
f9a48e6a
AK		 404 cr0 |= X86_CR0_ET;
405
ab344828
GN		 406#ifdef CONFIG_X86_64
407 if (cr0 & 0xffffffff00000000UL) {
c1a5d4f9 408 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 409 return;
410 }
ab344828
GN		 411#endif
412
413 cr0 &= ~CR0_RESERVED_BITS;
a03490ed
CO		 414
415 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
c1a5d4f9 416 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 417 return;
418 }
419
420 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
c1a5d4f9 421 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 422 return;
423 }
424
425 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
426#ifdef CONFIG_X86_64
f6801dff 427 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 428 int cs_db, cs_l;
429
430 if (!is_pae(vcpu)) {
c1a5d4f9 431 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 432 return;
433 }
434 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
435 if (cs_l) {
c1a5d4f9 436 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 437 return;
438
439 }
440 } else
441#endif
ad312c7c 442 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 443 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 444 return;
445 }
446
447 }
448
449 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 450
a03490ed 451 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 452 return;
453}
2d3ad1f4 454EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 455
2d3ad1f4 456void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 457{
4d4ec087 458 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f));
a03490ed 459}
2d3ad1f4 460EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 461
2d3ad1f4 462void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 463{
fc78f519 464 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 465 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
466
a03490ed 467 if (cr4 & CR4_RESERVED_BITS) {
c1a5d4f9 468 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 469 return;
470 }
471
472 if (is_long_mode(vcpu)) {
473 if (!(cr4 & X86_CR4_PAE)) {
c1a5d4f9 474 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 475 return;
476 }
a2edf57f
AK		 477 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
478 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 479 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 480 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 481 return;
482 }
483
484 if (cr4 & X86_CR4_VMXE) {
c1a5d4f9 485 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 486 return;
487 }
488 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 489 vcpu->arch.cr4 = cr4;
5a41accd 490 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 491 kvm_mmu_reset_context(vcpu);
a03490ed 492}
2d3ad1f4 493EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 494
2d3ad1f4 495void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 496{
ad312c7c 497 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 498 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 499 kvm_mmu_flush_tlb(vcpu);
500 return;
501 }
502
a03490ed
CO		 503 if (is_long_mode(vcpu)) {
504 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
c1a5d4f9 505 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 506 return;
507 }
508 } else {
509 if (is_pae(vcpu)) {
510 if (cr3 & CR3_PAE_RESERVED_BITS) {
c1a5d4f9 511 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 512 return;
513 }
514 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
c1a5d4f9 515 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 516 return;
517 }
518 }
519 /*
520 * We don't check reserved bits in nonpae mode, because
521 * this isn't enforced, and VMware depends on this.
522 */
523 }
524
a03490ed
CO		 525 /*
526 * Does the new cr3 value map to physical memory? (Note, we
527 * catch an invalid cr3 even in real-mode, because it would
528 * cause trouble later on when we turn on paging anyway.)
529 *
530 * A real CPU would silently accept an invalid cr3 and would
531 * attempt to use it - with largely undefined (and often hard
532 * to debug) behavior on the guest side.
533 */
534 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 535 kvm_inject_gp(vcpu, 0);
a03490ed 536 else {
ad312c7c
ZX		 537 vcpu->arch.cr3 = cr3;
538 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 539 }
a03490ed 540}
2d3ad1f4 541EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 542
2d3ad1f4 543void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 544{
545 if (cr8 & CR8_RESERVED_BITS) {
c1a5d4f9 546 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 547 return;
548 }
549 if (irqchip_in_kernel(vcpu->kvm))
550 kvm_lapic_set_tpr(vcpu, cr8);
551 else
ad312c7c 552 vcpu->arch.cr8 = cr8;
a03490ed 553}
2d3ad1f4 554EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 555
2d3ad1f4 556unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 557{
558 if (irqchip_in_kernel(vcpu->kvm))
559 return kvm_lapic_get_cr8(vcpu);
560 else
ad312c7c 561 return vcpu->arch.cr8;
a03490ed 562}
2d3ad1f4 563EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 564
020df079
GN		 565int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
566{
567 switch (dr) {
568 case 0 ... 3:
569 vcpu->arch.db[dr] = val;
570 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
571 vcpu->arch.eff_db[dr] = val;
572 break;
573 case 4:
574 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
575 kvm_queue_exception(vcpu, UD_VECTOR);
576 return 1;
577 }
578 /* fall through */
579 case 6:
580 if (val & 0xffffffff00000000ULL) {
581 kvm_inject_gp(vcpu, 0);
582 return 1;
583 }
584 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
585 break;
586 case 5:
587 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
588 kvm_queue_exception(vcpu, UD_VECTOR);
589 return 1;
590 }
591 /* fall through */
592 default: /* 7 */
593 if (val & 0xffffffff00000000ULL) {
594 kvm_inject_gp(vcpu, 0);
595 return 1;
596 }
597 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
598 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
599 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
600 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
601 }
602 break;
603 }
604
605 return 0;
606}
607EXPORT_SYMBOL_GPL(kvm_set_dr);
608
609int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
610{
611 switch (dr) {
612 case 0 ... 3:
613 *val = vcpu->arch.db[dr];
614 break;
615 case 4:
616 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
617 kvm_queue_exception(vcpu, UD_VECTOR);
618 return 1;
619 }
620 /* fall through */
621 case 6:
622 *val = vcpu->arch.dr6;
623 break;
624 case 5:
625 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
626 kvm_queue_exception(vcpu, UD_VECTOR);
627 return 1;
628 }
629 /* fall through */
630 default: /* 7 */
631 *val = vcpu->arch.dr7;
632 break;
633 }
634
635 return 0;
636}
637EXPORT_SYMBOL_GPL(kvm_get_dr);
638
d8017474
AG		 639static inline u32 bit(int bitno)
640{
641 return 1 << (bitno & 31);
642}
643
043405e1
CO		 644/*
645 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
646 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
647 *
648 * This list is modified at module load time to reflect the
e3267cbb
GC		 649 * capabilities of the host cpu. This capabilities test skips MSRs that are
650 * kvm-specific. Those are put in the beginning of the list.
043405e1 651 */
e3267cbb 652
10388a07 653#define KVM_SAVE_MSRS_BEGIN 5
043405e1 654static u32 msrs_to_save[] = {
e3267cbb 655 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
55cd8e5a 656 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 657 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 658 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
659 MSR_K6_STAR,
660#ifdef CONFIG_X86_64
661 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
662#endif
e3267cbb 663 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 664};
665
666static unsigned num_msrs_to_save;
667
668static u32 emulated_msrs[] = {
669 MSR_IA32_MISC_ENABLE,
670};
671
15c4a640
CO		 672static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
673{
f2b4b7dd 674 if (efer & efer_reserved_bits) {
c1a5d4f9 675 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 676 return;
677 }
678
679 if (is_paging(vcpu)
f6801dff 680 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) {
c1a5d4f9 681 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 682 return;
683 }
684
1b2fd70c
AG		 685 if (efer & EFER_FFXSR) {
686 struct kvm_cpuid_entry2 *feat;
687
688 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
689 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
1b2fd70c
AG		 690 kvm_inject_gp(vcpu, 0);
691 return;
692 }
693 }
694
d8017474
AG		 695 if (efer & EFER_SVME) {
696 struct kvm_cpuid_entry2 *feat;
697
698 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
699 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
d8017474
AG		 700 kvm_inject_gp(vcpu, 0);
701 return;
702 }
703 }
704
15c4a640
CO		 705 kvm_x86_ops->set_efer(vcpu, efer);
706
707 efer &= ~EFER_LMA;
f6801dff 708 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 709
f6801dff 710 vcpu->arch.efer = efer;
9645bb56
AK		 711
712 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
713 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 714}
715
f2b4b7dd
JR		 716void kvm_enable_efer_bits(u64 mask)
717{
718 efer_reserved_bits &= ~mask;
719}
720EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
721
722
15c4a640
CO		 723/*
724 * Writes msr value into into the appropriate "register".
725 * Returns 0 on success, non-0 otherwise.
726 * Assumes vcpu_load() was already called.
727 */
728int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
729{
730 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
731}
732
313a3dc7
CO		 733/*
734 * Adapt set_msr() to msr_io()'s calling convention
735 */
736static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
737{
738 return kvm_set_msr(vcpu, index, *data);
739}
740
18068523
GOC		 741static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
742{
743 static int version;
50d0a0f9 744 struct pvclock_wall_clock wc;
923de3cf 745 struct timespec boot;
18068523
GOC		 746
747 if (!wall_clock)
748 return;
749
750 version++;
751
18068523
GOC		 752 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
753
50d0a0f9
GH		 754 /*
755 * The guest calculates current wall clock time by adding
756 * system time (updated by kvm_write_guest_time below) to the
757 * wall clock specified here. guest system time equals host
758 * system time for us, thus we must fill in host boot time here.
759 */
923de3cf 760 getboottime(&boot);
50d0a0f9
GH		 761
762 wc.sec = boot.tv_sec;
763 wc.nsec = boot.tv_nsec;
764 wc.version = version;
18068523
GOC		 765
766 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
767
768 version++;
769 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 770}
771
50d0a0f9
GH		 772static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
773{
774 uint32_t quotient, remainder;
775
776 /* Don't try to replace with do_div(), this one calculates
777 * "(dividend << 32) / divisor" */
778 __asm__ ( "divl %4"
779 : "=a" (quotient), "=d" (remainder)
780 : "0" (0), "1" (dividend), "r" (divisor) );
781 return quotient;
782}
783
784static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
785{
786 uint64_t nsecs = 1000000000LL;
787 int32_t shift = 0;
788 uint64_t tps64;
789 uint32_t tps32;
790
791 tps64 = tsc_khz * 1000LL;
792 while (tps64 > nsecs*2) {
793 tps64 >>= 1;
794 shift--;
795 }
796
797 tps32 = (uint32_t)tps64;
798 while (tps32 <= (uint32_t)nsecs) {
799 tps32 <<= 1;
800 shift++;
801 }
802
803 hv_clock->tsc_shift = shift;
804 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
805
806 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 807 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 808 hv_clock->tsc_to_system_mul);
809}
810
c8076604
GH		 811static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
812
18068523
GOC		 813static void kvm_write_guest_time(struct kvm_vcpu *v)
814{
815 struct timespec ts;
816 unsigned long flags;
817 struct kvm_vcpu_arch *vcpu = &v->arch;
818 void *shared_kaddr;
463656c0 819 unsigned long this_tsc_khz;
18068523
GOC		 820
821 if ((!vcpu->time_page))
822 return;
823
463656c0
AK		 824 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
825 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
826 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
827 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 828 }
463656c0 829 put_cpu_var(cpu_tsc_khz);
50d0a0f9 830
18068523
GOC		 831 /* Keep irq disabled to prevent changes to the clock */
832 local_irq_save(flags);
af24a4e4 833 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 834 ktime_get_ts(&ts);
923de3cf 835 monotonic_to_bootbased(&ts);
18068523
GOC		 836 local_irq_restore(flags);
837
838 /* With all the info we got, fill in the values */
839
840 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 841 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
842
18068523
GOC		 843 /*
844 * The interface expects us to write an even number signaling that the
845 * update is finished. Since the guest won't see the intermediate
50d0a0f9 846 * state, we just increase by 2 at the end.
18068523 847 */
50d0a0f9 848 vcpu->hv_clock.version += 2;
18068523
GOC		 849
850 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
851
852 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 853 sizeof(vcpu->hv_clock));
18068523
GOC		 854
855 kunmap_atomic(shared_kaddr, KM_USER0);
856
857 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
858}
859
c8076604
GH		 860static int kvm_request_guest_time_update(struct kvm_vcpu *v)
861{
862 struct kvm_vcpu_arch *vcpu = &v->arch;
863
864 if (!vcpu->time_page)
865 return 0;
866 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
867 return 1;
868}
869
9ba075a6
AK		 870static bool msr_mtrr_valid(unsigned msr)
871{
872 switch (msr) {
873 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
874 case MSR_MTRRfix64K_00000:
875 case MSR_MTRRfix16K_80000:
876 case MSR_MTRRfix16K_A0000:
877 case MSR_MTRRfix4K_C0000:
878 case MSR_MTRRfix4K_C8000:
879 case MSR_MTRRfix4K_D0000:
880 case MSR_MTRRfix4K_D8000:
881 case MSR_MTRRfix4K_E0000:
882 case MSR_MTRRfix4K_E8000:
883 case MSR_MTRRfix4K_F0000:
884 case MSR_MTRRfix4K_F8000:
885 case MSR_MTRRdefType:
886 case MSR_IA32_CR_PAT:
887 return true;
888 case 0x2f8:
889 return true;
890 }
891 return false;
892}
893
d6289b93
MT		 894static bool valid_pat_type(unsigned t)
895{
896 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
897}
898
899static bool valid_mtrr_type(unsigned t)
900{
901 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
902}
903
904static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
905{
906 int i;
907
908 if (!msr_mtrr_valid(msr))
909 return false;
910
911 if (msr == MSR_IA32_CR_PAT) {
912 for (i = 0; i < 8; i++)
913 if (!valid_pat_type((data >> (i * 8)) & 0xff))
914 return false;
915 return true;
916 } else if (msr == MSR_MTRRdefType) {
917 if (data & ~0xcff)
918 return false;
919 return valid_mtrr_type(data & 0xff);
920 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
921 for (i = 0; i < 8 ; i++)
922 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
923 return false;
924 return true;
925 }
926
927 /* variable MTRRs */
928 return valid_mtrr_type(data & 0xff);
929}
930
9ba075a6
AK		 931static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
932{
0bed3b56
SY		 933 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
934
d6289b93 935 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 936 return 1;
937
0bed3b56
SY		 938 if (msr == MSR_MTRRdefType) {
939 vcpu->arch.mtrr_state.def_type = data;
940 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
941 } else if (msr == MSR_MTRRfix64K_00000)
942 p[0] = data;
943 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
944 p[1 + msr - MSR_MTRRfix16K_80000] = data;
945 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
946 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
947 else if (msr == MSR_IA32_CR_PAT)
948 vcpu->arch.pat = data;
949 else { /* Variable MTRRs */
950 int idx, is_mtrr_mask;
951 u64 *pt;
952
953 idx = (msr - 0x200) / 2;
954 is_mtrr_mask = msr - 0x200 - 2 * idx;
955 if (!is_mtrr_mask)
956 pt =
957 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
958 else
959 pt =
960 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
961 *pt = data;
962 }
963
964 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 965 return 0;
966}
15c4a640 967
890ca9ae 968static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 969{
890ca9ae
HY		 970 u64 mcg_cap = vcpu->arch.mcg_cap;
971 unsigned bank_num = mcg_cap & 0xff;
972
15c4a640 973 switch (msr) {
15c4a640 974 case MSR_IA32_MCG_STATUS:
890ca9ae 975 vcpu->arch.mcg_status = data;
15c4a640 976 break;
c7ac679c 977 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 978 if (!(mcg_cap & MCG_CTL_P))
979 return 1;
980 if (data != 0 && data != ~(u64)0)
981 return -1;
982 vcpu->arch.mcg_ctl = data;
983 break;
984 default:
985 if (msr >= MSR_IA32_MC0_CTL &&
986 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
987 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 988 /* only 0 or all 1s can be written to IA32_MCi_CTL
989 * some Linux kernels though clear bit 10 in bank 4 to
990 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
991 * this to avoid an uncatched #GP in the guest
992 */
890ca9ae 993 if ((offset & 0x3) == 0 &&
114be429 994 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 995 return -1;
996 vcpu->arch.mce_banks[offset] = data;
997 break;
998 }
999 return 1;
1000 }
1001 return 0;
1002}
1003
ffde22ac
ES		 1004static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1005{
1006 struct kvm *kvm = vcpu->kvm;
1007 int lm = is_long_mode(vcpu);
1008 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1009 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1010 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1011 : kvm->arch.xen_hvm_config.blob_size_32;
1012 u32 page_num = data & ~PAGE_MASK;
1013 u64 page_addr = data & PAGE_MASK;
1014 u8 *page;
1015 int r;
1016
1017 r = -E2BIG;
1018 if (page_num >= blob_size)
1019 goto out;
1020 r = -ENOMEM;
1021 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1022 if (!page)
1023 goto out;
1024 r = -EFAULT;
1025 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1026 goto out_free;
1027 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1028 goto out_free;
1029 r = 0;
1030out_free:
1031 kfree(page);
1032out:
1033 return r;
1034}
1035
55cd8e5a
GN		 1036static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1037{
1038 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1039}
1040
1041static bool kvm_hv_msr_partition_wide(u32 msr)
1042{
1043 bool r = false;
1044 switch (msr) {
1045 case HV_X64_MSR_GUEST_OS_ID:
1046 case HV_X64_MSR_HYPERCALL:
1047 r = true;
1048 break;
1049 }
1050
1051 return r;
1052}
1053
1054static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1055{
1056 struct kvm *kvm = vcpu->kvm;
1057
1058 switch (msr) {
1059 case HV_X64_MSR_GUEST_OS_ID:
1060 kvm->arch.hv_guest_os_id = data;
1061 /* setting guest os id to zero disables hypercall page */
1062 if (!kvm->arch.hv_guest_os_id)
1063 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1064 break;
1065 case HV_X64_MSR_HYPERCALL: {
1066 u64 gfn;
1067 unsigned long addr;
1068 u8 instructions[4];
1069
1070 /* if guest os id is not set hypercall should remain disabled */
1071 if (!kvm->arch.hv_guest_os_id)
1072 break;
1073 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1074 kvm->arch.hv_hypercall = data;
1075 break;
1076 }
1077 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1078 addr = gfn_to_hva(kvm, gfn);
1079 if (kvm_is_error_hva(addr))
1080 return 1;
1081 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1082 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1083 if (copy_to_user((void __user *)addr, instructions, 4))
1084 return 1;
1085 kvm->arch.hv_hypercall = data;
1086 break;
1087 }
1088 default:
1089 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1090 "data 0x%llx\n", msr, data);
1091 return 1;
1092 }
1093 return 0;
1094}
1095
1096static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1097{
10388a07
GN		 1098 switch (msr) {
1099 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1100 unsigned long addr;
55cd8e5a 1101
10388a07
GN		 1102 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1103 vcpu->arch.hv_vapic = data;
1104 break;
1105 }
1106 addr = gfn_to_hva(vcpu->kvm, data >>
1107 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1108 if (kvm_is_error_hva(addr))
1109 return 1;
1110 if (clear_user((void __user *)addr, PAGE_SIZE))
1111 return 1;
1112 vcpu->arch.hv_vapic = data;
1113 break;
1114 }
1115 case HV_X64_MSR_EOI:
1116 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1117 case HV_X64_MSR_ICR:
1118 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1119 case HV_X64_MSR_TPR:
1120 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1121 default:
1122 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1123 "data 0x%llx\n", msr, data);
1124 return 1;
1125 }
1126
1127 return 0;
55cd8e5a
GN		 1128}
1129
15c4a640
CO		 1130int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1131{
1132 switch (msr) {
15c4a640
CO		 1133 case MSR_EFER:
1134 set_efer(vcpu, data);
1135 break;
8f1589d9
AP		 1136 case MSR_K7_HWCR:
1137 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1138 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1139 if (data != 0) {
1140 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1141 data);
1142 return 1;
1143 }
15c4a640 1144 break;
f7c6d140
AP		 1145 case MSR_FAM10H_MMIO_CONF_BASE:
1146 if (data != 0) {
1147 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1148 "0x%llx\n", data);
1149 return 1;
1150 }
15c4a640 1151 break;
c323c0e5 1152 case MSR_AMD64_NB_CFG:
c7ac679c 1153 break;
b5e2fec0
AG		 1154 case MSR_IA32_DEBUGCTLMSR:
1155 if (!data) {
1156 /* We support the non-activated case already */
1157 break;
1158 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1159 /* Values other than LBR and BTF are vendor-specific,
1160 thus reserved and should throw a #GP */
1161 return 1;
1162 }
1163 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1164 __func__, data);
1165 break;
15c4a640
CO		 1166 case MSR_IA32_UCODE_REV:
1167 case MSR_IA32_UCODE_WRITE:
61a6bd67 1168 case MSR_VM_HSAVE_PA:
6098ca93 1169 case MSR_AMD64_PATCH_LOADER:
15c4a640 1170 break;
9ba075a6
AK		 1171 case 0x200 ... 0x2ff:
1172 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1173 case MSR_IA32_APICBASE:
1174 kvm_set_apic_base(vcpu, data);
1175 break;
0105d1a5
GN		 1176 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1177 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1178 case MSR_IA32_MISC_ENABLE:
ad312c7c 1179 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1180 break;
18068523
GOC		 1181 case MSR_KVM_WALL_CLOCK:
1182 vcpu->kvm->arch.wall_clock = data;
1183 kvm_write_wall_clock(vcpu->kvm, data);
1184 break;
1185 case MSR_KVM_SYSTEM_TIME: {
1186 if (vcpu->arch.time_page) {
1187 kvm_release_page_dirty(vcpu->arch.time_page);
1188 vcpu->arch.time_page = NULL;
1189 }
1190
1191 vcpu->arch.time = data;
1192
1193 /* we verify if the enable bit is set... */
1194 if (!(data & 1))
1195 break;
1196
1197 /* ...but clean it before doing the actual write */
1198 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1199
18068523
GOC		 1200 vcpu->arch.time_page =
1201 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1202
1203 if (is_error_page(vcpu->arch.time_page)) {
1204 kvm_release_page_clean(vcpu->arch.time_page);
1205 vcpu->arch.time_page = NULL;
1206 }
1207
c8076604 1208 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1209 break;
1210 }
890ca9ae
HY		 1211 case MSR_IA32_MCG_CTL:
1212 case MSR_IA32_MCG_STATUS:
1213 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1214 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1215
1216 /* Performance counters are not protected by a CPUID bit,
1217 * so we should check all of them in the generic path for the sake of
1218 * cross vendor migration.
1219 * Writing a zero into the event select MSRs disables them,
1220 * which we perfectly emulate ;-). Any other value should be at least
1221 * reported, some guests depend on them.
1222 */
1223 case MSR_P6_EVNTSEL0:
1224 case MSR_P6_EVNTSEL1:
1225 case MSR_K7_EVNTSEL0:
1226 case MSR_K7_EVNTSEL1:
1227 case MSR_K7_EVNTSEL2:
1228 case MSR_K7_EVNTSEL3:
1229 if (data != 0)
1230 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1231 "0x%x data 0x%llx\n", msr, data);
1232 break;
1233 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1234 * so we ignore writes to make it happy.
1235 */
1236 case MSR_P6_PERFCTR0:
1237 case MSR_P6_PERFCTR1:
1238 case MSR_K7_PERFCTR0:
1239 case MSR_K7_PERFCTR1:
1240 case MSR_K7_PERFCTR2:
1241 case MSR_K7_PERFCTR3:
1242 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1243 "0x%x data 0x%llx\n", msr, data);
1244 break;
55cd8e5a
GN		 1245 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1246 if (kvm_hv_msr_partition_wide(msr)) {
1247 int r;
1248 mutex_lock(&vcpu->kvm->lock);
1249 r = set_msr_hyperv_pw(vcpu, msr, data);
1250 mutex_unlock(&vcpu->kvm->lock);
1251 return r;
1252 } else
1253 return set_msr_hyperv(vcpu, msr, data);
1254 break;
15c4a640 1255 default:
ffde22ac
ES		 1256 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1257 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1258 if (!ignore_msrs) {
1259 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1260 msr, data);
1261 return 1;
1262 } else {
1263 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1264 msr, data);
1265 break;
1266 }
15c4a640
CO		 1267 }
1268 return 0;
1269}
1270EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1271
1272
1273/*
1274 * Reads an msr value (of 'msr_index') into 'pdata'.
1275 * Returns 0 on success, non-0 otherwise.
1276 * Assumes vcpu_load() was already called.
1277 */
1278int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1279{
1280 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1281}
1282
9ba075a6
AK		 1283static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1284{
0bed3b56
SY		 1285 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1286
9ba075a6
AK		 1287 if (!msr_mtrr_valid(msr))
1288 return 1;
1289
0bed3b56
SY		 1290 if (msr == MSR_MTRRdefType)
1291 *pdata = vcpu->arch.mtrr_state.def_type +
1292 (vcpu->arch.mtrr_state.enabled << 10);
1293 else if (msr == MSR_MTRRfix64K_00000)
1294 *pdata = p[0];
1295 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1296 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1297 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1298 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1299 else if (msr == MSR_IA32_CR_PAT)
1300 *pdata = vcpu->arch.pat;
1301 else { /* Variable MTRRs */
1302 int idx, is_mtrr_mask;
1303 u64 *pt;
1304
1305 idx = (msr - 0x200) / 2;
1306 is_mtrr_mask = msr - 0x200 - 2 * idx;
1307 if (!is_mtrr_mask)
1308 pt =
1309 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1310 else
1311 pt =
1312 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1313 *pdata = *pt;
1314 }
1315
9ba075a6
AK		 1316 return 0;
1317}
1318
890ca9ae 1319static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1320{
1321 u64 data;
890ca9ae
HY		 1322 u64 mcg_cap = vcpu->arch.mcg_cap;
1323 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1324
1325 switch (msr) {
15c4a640
CO		 1326 case MSR_IA32_P5_MC_ADDR:
1327 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1328 data = 0;
1329 break;
15c4a640 1330 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1331 data = vcpu->arch.mcg_cap;
1332 break;
c7ac679c 1333 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1334 if (!(mcg_cap & MCG_CTL_P))
1335 return 1;
1336 data = vcpu->arch.mcg_ctl;
1337 break;
1338 case MSR_IA32_MCG_STATUS:
1339 data = vcpu->arch.mcg_status;
1340 break;
1341 default:
1342 if (msr >= MSR_IA32_MC0_CTL &&
1343 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1344 u32 offset = msr - MSR_IA32_MC0_CTL;
1345 data = vcpu->arch.mce_banks[offset];
1346 break;
1347 }
1348 return 1;
1349 }
1350 *pdata = data;
1351 return 0;
1352}
1353
55cd8e5a
GN		 1354static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1355{
1356 u64 data = 0;
1357 struct kvm *kvm = vcpu->kvm;
1358
1359 switch (msr) {
1360 case HV_X64_MSR_GUEST_OS_ID:
1361 data = kvm->arch.hv_guest_os_id;
1362 break;
1363 case HV_X64_MSR_HYPERCALL:
1364 data = kvm->arch.hv_hypercall;
1365 break;
1366 default:
1367 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1368 return 1;
1369 }
1370
1371 *pdata = data;
1372 return 0;
1373}
1374
1375static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1376{
1377 u64 data = 0;
1378
1379 switch (msr) {
1380 case HV_X64_MSR_VP_INDEX: {
1381 int r;
1382 struct kvm_vcpu *v;
1383 kvm_for_each_vcpu(r, v, vcpu->kvm)
1384 if (v == vcpu)
1385 data = r;
1386 break;
1387 }
10388a07
GN		 1388 case HV_X64_MSR_EOI:
1389 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1390 case HV_X64_MSR_ICR:
1391 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1392 case HV_X64_MSR_TPR:
1393 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1394 default:
1395 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1396 return 1;
1397 }
1398 *pdata = data;
1399 return 0;
1400}
1401
890ca9ae
HY		 1402int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1403{
1404 u64 data;
1405
1406 switch (msr) {
890ca9ae 1407 case MSR_IA32_PLATFORM_ID:
15c4a640 1408 case MSR_IA32_UCODE_REV:
15c4a640 1409 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1410 case MSR_IA32_DEBUGCTLMSR:
1411 case MSR_IA32_LASTBRANCHFROMIP:
1412 case MSR_IA32_LASTBRANCHTOIP:
1413 case MSR_IA32_LASTINTFROMIP:
1414 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1415 case MSR_K8_SYSCFG:
1416 case MSR_K7_HWCR:
61a6bd67 1417 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1418 case MSR_P6_PERFCTR0:
1419 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1420 case MSR_P6_EVNTSEL0:
1421 case MSR_P6_EVNTSEL1:
9e699624 1422 case MSR_K7_EVNTSEL0:
1f3ee616 1423 case MSR_K7_PERFCTR0:
1fdbd48c 1424 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1425 case MSR_AMD64_NB_CFG:
f7c6d140 1426 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1427 data = 0;
1428 break;
9ba075a6
AK		 1429 case MSR_MTRRcap:
1430 data = 0x500 | KVM_NR_VAR_MTRR;
1431 break;
1432 case 0x200 ... 0x2ff:
1433 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1434 case 0xcd: /* fsb frequency */
1435 data = 3;
1436 break;
1437 case MSR_IA32_APICBASE:
1438 data = kvm_get_apic_base(vcpu);
1439 break;
0105d1a5
GN		 1440 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1441 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1442 break;
15c4a640 1443 case MSR_IA32_MISC_ENABLE:
ad312c7c 1444 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1445 break;
847f0ad8
AG		 1446 case MSR_IA32_PERF_STATUS:
1447 /* TSC increment by tick */
1448 data = 1000ULL;
1449 /* CPU multiplier */
1450 data |= (((uint64_t)4ULL) << 40);
1451 break;
15c4a640 1452 case MSR_EFER:
f6801dff 1453 data = vcpu->arch.efer;
15c4a640 1454 break;
18068523
GOC		 1455 case MSR_KVM_WALL_CLOCK:
1456 data = vcpu->kvm->arch.wall_clock;
1457 break;
1458 case MSR_KVM_SYSTEM_TIME:
1459 data = vcpu->arch.time;
1460 break;
890ca9ae
HY		 1461 case MSR_IA32_P5_MC_ADDR:
1462 case MSR_IA32_P5_MC_TYPE:
1463 case MSR_IA32_MCG_CAP:
1464 case MSR_IA32_MCG_CTL:
1465 case MSR_IA32_MCG_STATUS:
1466 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1467 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1468 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1469 if (kvm_hv_msr_partition_wide(msr)) {
1470 int r;
1471 mutex_lock(&vcpu->kvm->lock);
1472 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1473 mutex_unlock(&vcpu->kvm->lock);
1474 return r;
1475 } else
1476 return get_msr_hyperv(vcpu, msr, pdata);
1477 break;
15c4a640 1478 default:
ed85c068
AP		 1479 if (!ignore_msrs) {
1480 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1481 return 1;
1482 } else {
1483 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1484 data = 0;
1485 }
1486 break;
15c4a640
CO		 1487 }
1488 *pdata = data;
1489 return 0;
1490}
1491EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1492
313a3dc7
CO		 1493/*
1494 * Read or write a bunch of msrs. All parameters are kernel addresses.
1495 *
1496 * @return number of msrs set successfully.
1497 */
1498static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1499 struct kvm_msr_entry *entries,
1500 int (*do_msr)(struct kvm_vcpu *vcpu,
1501 unsigned index, u64 *data))
1502{
f656ce01 1503 int i, idx;
313a3dc7
CO		 1504
1505 vcpu_load(vcpu);
1506
f656ce01 1507 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1508 for (i = 0; i < msrs->nmsrs; ++i)
1509 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1510 break;
f656ce01 1511 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1512
1513 vcpu_put(vcpu);
1514
1515 return i;
1516}
1517
1518/*
1519 * Read or write a bunch of msrs. Parameters are user addresses.
1520 *
1521 * @return number of msrs set successfully.
1522 */
1523static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1524 int (*do_msr)(struct kvm_vcpu *vcpu,
1525 unsigned index, u64 *data),
1526 int writeback)
1527{
1528 struct kvm_msrs msrs;
1529 struct kvm_msr_entry *entries;
1530 int r, n;
1531 unsigned size;
1532
1533 r = -EFAULT;
1534 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1535 goto out;
1536
1537 r = -E2BIG;
1538 if (msrs.nmsrs >= MAX_IO_MSRS)
1539 goto out;
1540
1541 r = -ENOMEM;
1542 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1543 entries = vmalloc(size);
1544 if (!entries)
1545 goto out;
1546
1547 r = -EFAULT;
1548 if (copy_from_user(entries, user_msrs->entries, size))
1549 goto out_free;
1550
1551 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1552 if (r < 0)
1553 goto out_free;
1554
1555 r = -EFAULT;
1556 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1557 goto out_free;
1558
1559 r = n;
1560
1561out_free:
1562 vfree(entries);
1563out:
1564 return r;
1565}
1566
018d00d2
ZX		 1567int kvm_dev_ioctl_check_extension(long ext)
1568{
1569 int r;
1570
1571 switch (ext) {
1572 case KVM_CAP_IRQCHIP:
1573 case KVM_CAP_HLT:
1574 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1575 case KVM_CAP_SET_TSS_ADDR:
07716717 1576 case KVM_CAP_EXT_CPUID:
c8076604 1577 case KVM_CAP_CLOCKSOURCE:
7837699f 1578 case KVM_CAP_PIT:
a28e4f5a 1579 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1580 case KVM_CAP_MP_STATE:
ed848624 1581 case KVM_CAP_SYNC_MMU:
52d939a0 1582 case KVM_CAP_REINJECT_CONTROL:
4925663a 1583 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1584 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1585 case KVM_CAP_IRQFD:
d34e6b17 1586 case KVM_CAP_IOEVENTFD:
c5ff41ce 1587 case KVM_CAP_PIT2:
e9f42757 1588 case KVM_CAP_PIT_STATE2:
b927a3ce 1589 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1590 case KVM_CAP_XEN_HVM:
afbcf7ab 1591 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1592 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1593 case KVM_CAP_HYPERV:
10388a07 1594 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1595 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1596 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1597 case KVM_CAP_DEBUGREGS:
d2be1651 1598 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1599 r = 1;
1600 break;
542472b5
LV		 1601 case KVM_CAP_COALESCED_MMIO:
1602 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1603 break;
774ead3a
AK		 1604 case KVM_CAP_VAPIC:
1605 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1606 break;
f725230a
AK		 1607 case KVM_CAP_NR_VCPUS:
1608 r = KVM_MAX_VCPUS;
1609 break;
a988b910
AK		 1610 case KVM_CAP_NR_MEMSLOTS:
1611 r = KVM_MEMORY_SLOTS;
1612 break;
a68a6a72
MT		 1613 case KVM_CAP_PV_MMU: /* obsolete */
1614 r = 0;
2f333bcb 1615 break;
62c476c7 1616 case KVM_CAP_IOMMU:
19de40a8 1617 r = iommu_found();
62c476c7 1618 break;
890ca9ae
HY		 1619 case KVM_CAP_MCE:
1620 r = KVM_MAX_MCE_BANKS;
1621 break;
018d00d2
ZX		 1622 default:
1623 r = 0;
1624 break;
1625 }
1626 return r;
1627
1628}
1629
043405e1
CO		 1630long kvm_arch_dev_ioctl(struct file *filp,
1631 unsigned int ioctl, unsigned long arg)
1632{
1633 void __user *argp = (void __user *)arg;
1634 long r;
1635
1636 switch (ioctl) {
1637 case KVM_GET_MSR_INDEX_LIST: {
1638 struct kvm_msr_list __user *user_msr_list = argp;
1639 struct kvm_msr_list msr_list;
1640 unsigned n;
1641
1642 r = -EFAULT;
1643 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1644 goto out;
1645 n = msr_list.nmsrs;
1646 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1647 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1648 goto out;
1649 r = -E2BIG;
e125e7b6 1650 if (n < msr_list.nmsrs)
043405e1
CO		 1651 goto out;
1652 r = -EFAULT;
1653 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1654 num_msrs_to_save * sizeof(u32)))
1655 goto out;
e125e7b6 1656 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1657 &emulated_msrs,
1658 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1659 goto out;
1660 r = 0;
1661 break;
1662 }
674eea0f
AK		 1663 case KVM_GET_SUPPORTED_CPUID: {
1664 struct kvm_cpuid2 __user *cpuid_arg = argp;
1665 struct kvm_cpuid2 cpuid;
1666
1667 r = -EFAULT;
1668 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1669 goto out;
1670 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1671 cpuid_arg->entries);
674eea0f
AK		 1672 if (r)
1673 goto out;
1674
1675 r = -EFAULT;
1676 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1677 goto out;
1678 r = 0;
1679 break;
1680 }
890ca9ae
HY		 1681 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1682 u64 mce_cap;
1683
1684 mce_cap = KVM_MCE_CAP_SUPPORTED;
1685 r = -EFAULT;
1686 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1687 goto out;
1688 r = 0;
1689 break;
1690 }
043405e1
CO		 1691 default:
1692 r = -EINVAL;
1693 }
1694out:
1695 return r;
1696}
1697
313a3dc7
CO		 1698void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1699{
1700 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1701 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1702 unsigned long khz = cpufreq_quick_get(cpu);
1703 if (!khz)
1704 khz = tsc_khz;
1705 per_cpu(cpu_tsc_khz, cpu) = khz;
1706 }
c8076604 1707 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1708}
1709
1710void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1711{
9327fd11 1712 kvm_put_guest_fpu(vcpu);
02daab21 1713 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1714}
1715
07716717 1716static int is_efer_nx(void)
313a3dc7 1717{
e286e86e 1718 unsigned long long efer = 0;
313a3dc7 1719
e286e86e 1720 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1721 return efer & EFER_NX;
1722}
1723
1724static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1725{
1726 int i;
1727 struct kvm_cpuid_entry2 *e, *entry;
1728
313a3dc7 1729 entry = NULL;
ad312c7c
ZX		 1730 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1731 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1732 if (e->function == 0x80000001) {
1733 entry = e;
1734 break;
1735 }
1736 }
07716717 1737 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1738 entry->edx &= ~(1 << 20);
1739 printk(KERN_INFO "kvm: guest NX capability removed\n");
1740 }
1741}
1742
07716717 1743/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1744static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1745 struct kvm_cpuid *cpuid,
1746 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1747{
1748 int r, i;
1749 struct kvm_cpuid_entry *cpuid_entries;
1750
1751 r = -E2BIG;
1752 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1753 goto out;
1754 r = -ENOMEM;
1755 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1756 if (!cpuid_entries)
1757 goto out;
1758 r = -EFAULT;
1759 if (copy_from_user(cpuid_entries, entries,
1760 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1761 goto out_free;
1762 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1763 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1764 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1765 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1766 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1767 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1768 vcpu->arch.cpuid_entries[i].index = 0;
1769 vcpu->arch.cpuid_entries[i].flags = 0;
1770 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1771 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1772 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1773 }
1774 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1775 cpuid_fix_nx_cap(vcpu);
1776 r = 0;
fc61b800 1777 kvm_apic_set_version(vcpu);
0e851880 1778 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1779
1780out_free:
1781 vfree(cpuid_entries);
1782out:
1783 return r;
1784}
1785
1786static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1787 struct kvm_cpuid2 *cpuid,
1788 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1789{
1790 int r;
1791
1792 r = -E2BIG;
1793 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1794 goto out;
1795 r = -EFAULT;
ad312c7c 1796 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1797 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1798 goto out;
ad312c7c 1799 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1800 kvm_apic_set_version(vcpu);
0e851880 1801 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1802 return 0;
1803
1804out:
1805 return r;
1806}
1807
07716717 1808static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1809 struct kvm_cpuid2 *cpuid,
1810 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1811{
1812 int r;
1813
1814 r = -E2BIG;
ad312c7c 1815 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1816 goto out;
1817 r = -EFAULT;
ad312c7c 1818 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1819 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1820 goto out;
1821 return 0;
1822
1823out:
ad312c7c 1824 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1825 return r;
1826}
1827
07716717 1828static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1829 u32 index)
07716717
DK		 1830{
1831 entry->function = function;
1832 entry->index = index;
1833 cpuid_count(entry->function, entry->index,
19355475 1834 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1835 entry->flags = 0;
1836}
1837
7faa4ee1
AK		 1838#define F(x) bit(X86_FEATURE_##x)
1839
07716717
DK		 1840static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1841 u32 index, int *nent, int maxnent)
1842{
7faa4ee1 1843 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1844#ifdef CONFIG_X86_64
17cc3935
SY		 1845 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1846 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1847 unsigned f_lm = F(LM);
1848#else
17cc3935 1849 unsigned f_gbpages = 0;
7faa4ee1 1850 unsigned f_lm = 0;
07716717 1851#endif
4e47c7a6 1852 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1853
1854 /* cpuid 1.edx */
1855 const u32 kvm_supported_word0_x86_features =
1856 F(FPU) | F(VME) | F(DE) | F(PSE) |
1857 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1858 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1859 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1860 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1861 0 /* Reserved, DS, ACPI */ | F(MMX) |
1862 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1863 0 /* HTT, TM, Reserved, PBE */;
1864 /* cpuid 0x80000001.edx */
1865 const u32 kvm_supported_word1_x86_features =
1866 F(FPU) | F(VME) | F(DE) | F(PSE) |
1867 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1868 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1869 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1870 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1871 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1872 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1873 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1874 /* cpuid 1.ecx */
1875 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1876 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1877 0 /* DS-CPL, VMX, SMX, EST */ |
1878 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1879 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1880 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1881 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1882 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1883 /* cpuid 0x80000001.ecx */
07716717 1884 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1885 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1886 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1887 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1888 0 /* SKINIT */ | 0 /* WDT */;
07716717 1889
19355475 1890 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1891 get_cpu();
1892 do_cpuid_1_ent(entry, function, index);
1893 ++*nent;
1894
1895 switch (function) {
1896 case 0:
1897 entry->eax = min(entry->eax, (u32)0xb);
1898 break;
1899 case 1:
1900 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1901 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1902 /* we support x2apic emulation even if host does not support
1903 * it since we emulate x2apic in software */
1904 entry->ecx |= F(X2APIC);
07716717
DK		 1905 break;
1906 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1907 * may return different values. This forces us to get_cpu() before
1908 * issuing the first command, and also to emulate this annoying behavior
1909 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1910 case 2: {
1911 int t, times = entry->eax & 0xff;
1912
1913 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1914 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1915 for (t = 1; t < times && *nent < maxnent; ++t) {
1916 do_cpuid_1_ent(&entry[t], function, 0);
1917 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1918 ++*nent;
1919 }
1920 break;
1921 }
1922 /* function 4 and 0xb have additional index. */
1923 case 4: {
14af3f3c 1924 int i, cache_type;
07716717
DK		 1925
1926 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1927 /* read more entries until cache_type is zero */
14af3f3c
HH		 1928 for (i = 1; *nent < maxnent; ++i) {
1929 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1930 if (!cache_type)
1931 break;
14af3f3c
HH		 1932 do_cpuid_1_ent(&entry[i], function, i);
1933 entry[i].flags |=
07716717
DK		 1934 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1935 ++*nent;
1936 }
1937 break;
1938 }
1939 case 0xb: {
14af3f3c 1940 int i, level_type;
07716717
DK		 1941
1942 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1943 /* read more entries until level_type is zero */
14af3f3c 1944 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1945 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1946 if (!level_type)
1947 break;
14af3f3c
HH		 1948 do_cpuid_1_ent(&entry[i], function, i);
1949 entry[i].flags |=
07716717
DK		 1950 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1951 ++*nent;
1952 }
1953 break;
1954 }
1955 case 0x80000000:
1956 entry->eax = min(entry->eax, 0x8000001a);
1957 break;
1958 case 0x80000001:
1959 entry->edx &= kvm_supported_word1_x86_features;
1960 entry->ecx &= kvm_supported_word6_x86_features;
1961 break;
1962 }
1963 put_cpu();
1964}
1965
7faa4ee1
AK		 1966#undef F
1967
674eea0f 1968static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1969 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1970{
1971 struct kvm_cpuid_entry2 *cpuid_entries;
1972 int limit, nent = 0, r = -E2BIG;
1973 u32 func;
1974
1975 if (cpuid->nent < 1)
1976 goto out;
6a544355
AK		 1977 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1978 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1979 r = -ENOMEM;
1980 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1981 if (!cpuid_entries)
1982 goto out;
1983
1984 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1985 limit = cpuid_entries[0].eax;
1986 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1987 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1988 &nent, cpuid->nent);
07716717
DK		 1989 r = -E2BIG;
1990 if (nent >= cpuid->nent)
1991 goto out_free;
1992
1993 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1994 limit = cpuid_entries[nent - 1].eax;
1995 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1996 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1997 &nent, cpuid->nent);
cb007648
MM		 1998 r = -E2BIG;
1999 if (nent >= cpuid->nent)
2000 goto out_free;
2001
07716717
DK		 2002 r = -EFAULT;
2003 if (copy_to_user(entries, cpuid_entries,
19355475 2004 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2005 goto out_free;
2006 cpuid->nent = nent;
2007 r = 0;
2008
2009out_free:
2010 vfree(cpuid_entries);
2011out:
2012 return r;
2013}
2014
313a3dc7
CO		 2015static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2016 struct kvm_lapic_state *s)
2017{
2018 vcpu_load(vcpu);
ad312c7c 2019 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2020 vcpu_put(vcpu);
2021
2022 return 0;
2023}
2024
2025static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2026 struct kvm_lapic_state *s)
2027{
2028 vcpu_load(vcpu);
ad312c7c 2029 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2030 kvm_apic_post_state_restore(vcpu);
cb142eb7 2031 update_cr8_intercept(vcpu);
313a3dc7
CO		 2032 vcpu_put(vcpu);
2033
2034 return 0;
2035}
2036
f77bc6a4
ZX		 2037static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2038 struct kvm_interrupt *irq)
2039{
2040 if (irq->irq < 0 || irq->irq >= 256)
2041 return -EINVAL;
2042 if (irqchip_in_kernel(vcpu->kvm))
2043 return -ENXIO;
2044 vcpu_load(vcpu);
2045
66fd3f7f 2046 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2047
2048 vcpu_put(vcpu);
2049
2050 return 0;
2051}
2052
c4abb7c9
JK		 2053static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2054{
2055 vcpu_load(vcpu);
2056 kvm_inject_nmi(vcpu);
2057 vcpu_put(vcpu);
2058
2059 return 0;
2060}
2061
b209749f
AK		 2062static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2063 struct kvm_tpr_access_ctl *tac)
2064{
2065 if (tac->flags)
2066 return -EINVAL;
2067 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2068 return 0;
2069}
2070
890ca9ae
HY		 2071static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2072 u64 mcg_cap)
2073{
2074 int r;
2075 unsigned bank_num = mcg_cap & 0xff, bank;
2076
2077 r = -EINVAL;
a9e38c3e 2078 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2079 goto out;
2080 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2081 goto out;
2082 r = 0;
2083 vcpu->arch.mcg_cap = mcg_cap;
2084 /* Init IA32_MCG_CTL to all 1s */
2085 if (mcg_cap & MCG_CTL_P)
2086 vcpu->arch.mcg_ctl = ~(u64)0;
2087 /* Init IA32_MCi_CTL to all 1s */
2088 for (bank = 0; bank < bank_num; bank++)
2089 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2090out:
2091 return r;
2092}
2093
2094static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2095 struct kvm_x86_mce *mce)
2096{
2097 u64 mcg_cap = vcpu->arch.mcg_cap;
2098 unsigned bank_num = mcg_cap & 0xff;
2099 u64 *banks = vcpu->arch.mce_banks;
2100
2101 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2102 return -EINVAL;
2103 /*
2104 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2105 * reporting is disabled
2106 */
2107 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2108 vcpu->arch.mcg_ctl != ~(u64)0)
2109 return 0;
2110 banks += 4 * mce->bank;
2111 /*
2112 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2113 * reporting is disabled for the bank
2114 */
2115 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2116 return 0;
2117 if (mce->status & MCI_STATUS_UC) {
2118 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2119 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2120 printk(KERN_DEBUG "kvm: set_mce: "
2121 "injects mce exception while "
2122 "previous one is in progress!\n");
2123 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2124 return 0;
2125 }
2126 if (banks[1] & MCI_STATUS_VAL)
2127 mce->status |= MCI_STATUS_OVER;
2128 banks[2] = mce->addr;
2129 banks[3] = mce->misc;
2130 vcpu->arch.mcg_status = mce->mcg_status;
2131 banks[1] = mce->status;
2132 kvm_queue_exception(vcpu, MC_VECTOR);
2133 } else if (!(banks[1] & MCI_STATUS_VAL)
2134 || !(banks[1] & MCI_STATUS_UC)) {
2135 if (banks[1] & MCI_STATUS_VAL)
2136 mce->status |= MCI_STATUS_OVER;
2137 banks[2] = mce->addr;
2138 banks[3] = mce->misc;
2139 banks[1] = mce->status;
2140 } else
2141 banks[1] |= MCI_STATUS_OVER;
2142 return 0;
2143}
2144
3cfc3092
JK		 2145static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2146 struct kvm_vcpu_events *events)
2147{
2148 vcpu_load(vcpu);
2149
03b82a30
JK		 2150 events->exception.injected =
2151 vcpu->arch.exception.pending &&
2152 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2153 events->exception.nr = vcpu->arch.exception.nr;
2154 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2155 events->exception.error_code = vcpu->arch.exception.error_code;
2156
03b82a30
JK		 2157 events->interrupt.injected =
2158 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2159 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2160 events->interrupt.soft = 0;
48005f64
JK		 2161 events->interrupt.shadow =
2162 kvm_x86_ops->get_interrupt_shadow(vcpu,
2163 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2164
2165 events->nmi.injected = vcpu->arch.nmi_injected;
2166 events->nmi.pending = vcpu->arch.nmi_pending;
2167 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2168
2169 events->sipi_vector = vcpu->arch.sipi_vector;
2170
dab4b911 2171 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2172 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2173 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2174
2175 vcpu_put(vcpu);
2176}
2177
2178static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2179 struct kvm_vcpu_events *events)
2180{
dab4b911 2181 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2182 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2183 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2184 return -EINVAL;
2185
2186 vcpu_load(vcpu);
2187
2188 vcpu->arch.exception.pending = events->exception.injected;
2189 vcpu->arch.exception.nr = events->exception.nr;
2190 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2191 vcpu->arch.exception.error_code = events->exception.error_code;
2192
2193 vcpu->arch.interrupt.pending = events->interrupt.injected;
2194 vcpu->arch.interrupt.nr = events->interrupt.nr;
2195 vcpu->arch.interrupt.soft = events->interrupt.soft;
2196 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2197 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2198 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2199 kvm_x86_ops->set_interrupt_shadow(vcpu,
2200 events->interrupt.shadow);
3cfc3092
JK		 2201
2202 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2203 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2204 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2205 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2206
dab4b911
JK		 2207 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2208 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2209
2210 vcpu_put(vcpu);
2211
2212 return 0;
2213}
2214
a1efbe77
JK		 2215static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2216 struct kvm_debugregs *dbgregs)
2217{
2218 vcpu_load(vcpu);
2219
2220 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2221 dbgregs->dr6 = vcpu->arch.dr6;
2222 dbgregs->dr7 = vcpu->arch.dr7;
2223 dbgregs->flags = 0;
2224
2225 vcpu_put(vcpu);
2226}
2227
2228static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2229 struct kvm_debugregs *dbgregs)
2230{
2231 if (dbgregs->flags)
2232 return -EINVAL;
2233
2234 vcpu_load(vcpu);
2235
2236 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2237 vcpu->arch.dr6 = dbgregs->dr6;
2238 vcpu->arch.dr7 = dbgregs->dr7;
2239
2240 vcpu_put(vcpu);
2241
2242 return 0;
2243}
2244
313a3dc7
CO		 2245long kvm_arch_vcpu_ioctl(struct file *filp,
2246 unsigned int ioctl, unsigned long arg)
2247{
2248 struct kvm_vcpu *vcpu = filp->private_data;
2249 void __user *argp = (void __user *)arg;
2250 int r;
b772ff36 2251 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2252
2253 switch (ioctl) {
2254 case KVM_GET_LAPIC: {
2204ae3c
MT		 2255 r = -EINVAL;
2256 if (!vcpu->arch.apic)
2257 goto out;
b772ff36 2258 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2259
b772ff36
DH		 2260 r = -ENOMEM;
2261 if (!lapic)
2262 goto out;
2263 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2264 if (r)
2265 goto out;
2266 r = -EFAULT;
b772ff36 2267 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2268 goto out;
2269 r = 0;
2270 break;
2271 }
2272 case KVM_SET_LAPIC: {
2204ae3c
MT		 2273 r = -EINVAL;
2274 if (!vcpu->arch.apic)
2275 goto out;
b772ff36
DH		 2276 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2277 r = -ENOMEM;
2278 if (!lapic)
2279 goto out;
313a3dc7 2280 r = -EFAULT;
b772ff36 2281 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2282 goto out;
b772ff36 2283 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2284 if (r)
2285 goto out;
2286 r = 0;
2287 break;
2288 }
f77bc6a4
ZX		 2289 case KVM_INTERRUPT: {
2290 struct kvm_interrupt irq;
2291
2292 r = -EFAULT;
2293 if (copy_from_user(&irq, argp, sizeof irq))
2294 goto out;
2295 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2296 if (r)
2297 goto out;
2298 r = 0;
2299 break;
2300 }
c4abb7c9
JK		 2301 case KVM_NMI: {
2302 r = kvm_vcpu_ioctl_nmi(vcpu);
2303 if (r)
2304 goto out;
2305 r = 0;
2306 break;
2307 }
313a3dc7
CO		 2308 case KVM_SET_CPUID: {
2309 struct kvm_cpuid __user *cpuid_arg = argp;
2310 struct kvm_cpuid cpuid;
2311
2312 r = -EFAULT;
2313 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2314 goto out;
2315 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2316 if (r)
2317 goto out;
2318 break;
2319 }
07716717
DK		 2320 case KVM_SET_CPUID2: {
2321 struct kvm_cpuid2 __user *cpuid_arg = argp;
2322 struct kvm_cpuid2 cpuid;
2323
2324 r = -EFAULT;
2325 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2326 goto out;
2327 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2328 cpuid_arg->entries);
07716717
DK		 2329 if (r)
2330 goto out;
2331 break;
2332 }
2333 case KVM_GET_CPUID2: {
2334 struct kvm_cpuid2 __user *cpuid_arg = argp;
2335 struct kvm_cpuid2 cpuid;
2336
2337 r = -EFAULT;
2338 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2339 goto out;
2340 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2341 cpuid_arg->entries);
07716717
DK		 2342 if (r)
2343 goto out;
2344 r = -EFAULT;
2345 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2346 goto out;
2347 r = 0;
2348 break;
2349 }
313a3dc7
CO		 2350 case KVM_GET_MSRS:
2351 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2352 break;
2353 case KVM_SET_MSRS:
2354 r = msr_io(vcpu, argp, do_set_msr, 0);
2355 break;
b209749f
AK		 2356 case KVM_TPR_ACCESS_REPORTING: {
2357 struct kvm_tpr_access_ctl tac;
2358
2359 r = -EFAULT;
2360 if (copy_from_user(&tac, argp, sizeof tac))
2361 goto out;
2362 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2363 if (r)
2364 goto out;
2365 r = -EFAULT;
2366 if (copy_to_user(argp, &tac, sizeof tac))
2367 goto out;
2368 r = 0;
2369 break;
2370 };
b93463aa
AK		 2371 case KVM_SET_VAPIC_ADDR: {
2372 struct kvm_vapic_addr va;
2373
2374 r = -EINVAL;
2375 if (!irqchip_in_kernel(vcpu->kvm))
2376 goto out;
2377 r = -EFAULT;
2378 if (copy_from_user(&va, argp, sizeof va))
2379 goto out;
2380 r = 0;
2381 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2382 break;
2383 }
890ca9ae
HY		 2384 case KVM_X86_SETUP_MCE: {
2385 u64 mcg_cap;
2386
2387 r = -EFAULT;
2388 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2389 goto out;
2390 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2391 break;
2392 }
2393 case KVM_X86_SET_MCE: {
2394 struct kvm_x86_mce mce;
2395
2396 r = -EFAULT;
2397 if (copy_from_user(&mce, argp, sizeof mce))
2398 goto out;
2399 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2400 break;
2401 }
3cfc3092
JK		 2402 case KVM_GET_VCPU_EVENTS: {
2403 struct kvm_vcpu_events events;
2404
2405 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2406
2407 r = -EFAULT;
2408 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2409 break;
2410 r = 0;
2411 break;
2412 }
2413 case KVM_SET_VCPU_EVENTS: {
2414 struct kvm_vcpu_events events;
2415
2416 r = -EFAULT;
2417 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2418 break;
2419
2420 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2421 break;
2422 }
a1efbe77
JK		 2423 case KVM_GET_DEBUGREGS: {
2424 struct kvm_debugregs dbgregs;
2425
2426 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2427
2428 r = -EFAULT;
2429 if (copy_to_user(argp, &dbgregs,
2430 sizeof(struct kvm_debugregs)))
2431 break;
2432 r = 0;
2433 break;
2434 }
2435 case KVM_SET_DEBUGREGS: {
2436 struct kvm_debugregs dbgregs;
2437
2438 r = -EFAULT;
2439 if (copy_from_user(&dbgregs, argp,
2440 sizeof(struct kvm_debugregs)))
2441 break;
2442
2443 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2444 break;
2445 }
313a3dc7
CO		 2446 default:
2447 r = -EINVAL;
2448 }
2449out:
7a6ce84c 2450 kfree(lapic);
313a3dc7
CO		 2451 return r;
2452}
2453
1fe779f8
CO		 2454static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2455{
2456 int ret;
2457
2458 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2459 return -1;
2460 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2461 return ret;
2462}
2463
b927a3ce
SY		 2464static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2465 u64 ident_addr)
2466{
2467 kvm->arch.ept_identity_map_addr = ident_addr;
2468 return 0;
2469}
2470
1fe779f8
CO		 2471static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2472 u32 kvm_nr_mmu_pages)
2473{
2474 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2475 return -EINVAL;
2476
79fac95e 2477 mutex_lock(&kvm->slots_lock);
7c8a83b7 2478 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2479
2480 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2481 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2482
7c8a83b7 2483 spin_unlock(&kvm->mmu_lock);
79fac95e 2484 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2485 return 0;
2486}
2487
2488static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2489{
f05e70ac 2490 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2491}
2492
a983fb23
MT		 2493gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2494{
2495 int i;
2496 struct kvm_mem_alias *alias;
2497 struct kvm_mem_aliases *aliases;
2498
2499 aliases = rcu_dereference(kvm->arch.aliases);
2500
2501 for (i = 0; i < aliases->naliases; ++i) {
2502 alias = &aliases->aliases[i];
2503 if (alias->flags & KVM_ALIAS_INVALID)
2504 continue;
2505 if (gfn >= alias->base_gfn
2506 && gfn < alias->base_gfn + alias->npages)
2507 return alias->target_gfn + gfn - alias->base_gfn;
2508 }
2509 return gfn;
2510}
2511
e9f85cde
ZX		 2512gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2513{
2514 int i;
2515 struct kvm_mem_alias *alias;
a983fb23
MT		 2516 struct kvm_mem_aliases *aliases;
2517
2518 aliases = rcu_dereference(kvm->arch.aliases);
e9f85cde 2519
fef9cce0
MT		 2520 for (i = 0; i < aliases->naliases; ++i) {
2521 alias = &aliases->aliases[i];
e9f85cde
ZX		 2522 if (gfn >= alias->base_gfn
2523 && gfn < alias->base_gfn + alias->npages)
2524 return alias->target_gfn + gfn - alias->base_gfn;
2525 }
2526 return gfn;
2527}
2528
1fe779f8
CO		 2529/*
2530 * Set a new alias region. Aliases map a portion of physical memory into
2531 * another portion. This is useful for memory windows, for example the PC
2532 * VGA region.
2533 */
2534static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2535 struct kvm_memory_alias *alias)
2536{
2537 int r, n;
2538 struct kvm_mem_alias *p;
a983fb23 2539 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2540
2541 r = -EINVAL;
2542 /* General sanity checks */
2543 if (alias->memory_size & (PAGE_SIZE - 1))
2544 goto out;
2545 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2546 goto out;
2547 if (alias->slot >= KVM_ALIAS_SLOTS)
2548 goto out;
2549 if (alias->guest_phys_addr + alias->memory_size
2550 < alias->guest_phys_addr)
2551 goto out;
2552 if (alias->target_phys_addr + alias->memory_size
2553 < alias->target_phys_addr)
2554 goto out;
2555
a983fb23
MT		 2556 r = -ENOMEM;
2557 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2558 if (!aliases)
2559 goto out;
2560
79fac95e 2561 mutex_lock(&kvm->slots_lock);
1fe779f8 2562
a983fb23
MT		 2563 /* invalidate any gfn reference in case of deletion/shrinking */
2564 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2565 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2566 old_aliases = kvm->arch.aliases;
2567 rcu_assign_pointer(kvm->arch.aliases, aliases);
2568 synchronize_srcu_expedited(&kvm->srcu);
2569 kvm_mmu_zap_all(kvm);
2570 kfree(old_aliases);
2571
2572 r = -ENOMEM;
2573 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2574 if (!aliases)
2575 goto out_unlock;
2576
2577 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2578
2579 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2580 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2581 p->npages = alias->memory_size >> PAGE_SHIFT;
2582 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2583 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2584
2585 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2586 if (aliases->aliases[n - 1].npages)
1fe779f8 2587 break;
fef9cce0 2588 aliases->naliases = n;
1fe779f8 2589
a983fb23
MT		 2590 old_aliases = kvm->arch.aliases;
2591 rcu_assign_pointer(kvm->arch.aliases, aliases);
2592 synchronize_srcu_expedited(&kvm->srcu);
2593 kfree(old_aliases);
2594 r = 0;
1fe779f8 2595
a983fb23 2596out_unlock:
79fac95e 2597 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2598out:
2599 return r;
2600}
2601
2602static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2603{
2604 int r;
2605
2606 r = 0;
2607 switch (chip->chip_id) {
2608 case KVM_IRQCHIP_PIC_MASTER:
2609 memcpy(&chip->chip.pic,
2610 &pic_irqchip(kvm)->pics[0],
2611 sizeof(struct kvm_pic_state));
2612 break;
2613 case KVM_IRQCHIP_PIC_SLAVE:
2614 memcpy(&chip->chip.pic,
2615 &pic_irqchip(kvm)->pics[1],
2616 sizeof(struct kvm_pic_state));
2617 break;
2618 case KVM_IRQCHIP_IOAPIC:
eba0226b 2619 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2620 break;
2621 default:
2622 r = -EINVAL;
2623 break;
2624 }
2625 return r;
2626}
2627
2628static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2629{
2630 int r;
2631
2632 r = 0;
2633 switch (chip->chip_id) {
2634 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2635 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2636 memcpy(&pic_irqchip(kvm)->pics[0],
2637 &chip->chip.pic,
2638 sizeof(struct kvm_pic_state));
fa8273e9 2639 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2640 break;
2641 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2642 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2643 memcpy(&pic_irqchip(kvm)->pics[1],
2644 &chip->chip.pic,
2645 sizeof(struct kvm_pic_state));
fa8273e9 2646 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2647 break;
2648 case KVM_IRQCHIP_IOAPIC:
eba0226b 2649 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2650 break;
2651 default:
2652 r = -EINVAL;
2653 break;
2654 }
2655 kvm_pic_update_irq(pic_irqchip(kvm));
2656 return r;
2657}
2658
e0f63cb9
SY		 2659static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2660{
2661 int r = 0;
2662
894a9c55 2663 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2664 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2665 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2666 return r;
2667}
2668
2669static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2670{
2671 int r = 0;
2672
894a9c55 2673 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2674 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2675 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2676 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2677 return r;
2678}
2679
2680static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2681{
2682 int r = 0;
2683
2684 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2685 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2686 sizeof(ps->channels));
2687 ps->flags = kvm->arch.vpit->pit_state.flags;
2688 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2689 return r;
2690}
2691
2692static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2693{
2694 int r = 0, start = 0;
2695 u32 prev_legacy, cur_legacy;
2696 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2697 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2698 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2699 if (!prev_legacy && cur_legacy)
2700 start = 1;
2701 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2702 sizeof(kvm->arch.vpit->pit_state.channels));
2703 kvm->arch.vpit->pit_state.flags = ps->flags;
2704 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2705 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2706 return r;
2707}
2708
52d939a0
MT		 2709static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2710 struct kvm_reinject_control *control)
2711{
2712 if (!kvm->arch.vpit)
2713 return -ENXIO;
894a9c55 2714 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2715 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2716 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2717 return 0;
2718}
2719
5bb064dc
ZX		 2720/*
2721 * Get (and clear) the dirty memory log for a memory slot.
2722 */
2723int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2724 struct kvm_dirty_log *log)
2725{
87bf6e7d 2726 int r, i;
5bb064dc 2727 struct kvm_memory_slot *memslot;
87bf6e7d 2728 unsigned long n;
b050b015
MT		 2729 unsigned long is_dirty = 0;
2730 unsigned long *dirty_bitmap = NULL;
5bb064dc 2731
79fac95e 2732 mutex_lock(&kvm->slots_lock);
5bb064dc 2733
b050b015
MT		 2734 r = -EINVAL;
2735 if (log->slot >= KVM_MEMORY_SLOTS)
2736 goto out;
2737
2738 memslot = &kvm->memslots->memslots[log->slot];
2739 r = -ENOENT;
2740 if (!memslot->dirty_bitmap)
2741 goto out;
2742
87bf6e7d 2743 n = kvm_dirty_bitmap_bytes(memslot);
b050b015
MT		 2744
2745 r = -ENOMEM;
2746 dirty_bitmap = vmalloc(n);
2747 if (!dirty_bitmap)
5bb064dc 2748 goto out;
b050b015
MT		 2749 memset(dirty_bitmap, 0, n);
2750
2751 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2752 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2753
2754 /* If nothing is dirty, don't bother messing with page tables. */
2755 if (is_dirty) {
b050b015
MT		 2756 struct kvm_memslots *slots, *old_slots;
2757
7c8a83b7 2758 spin_lock(&kvm->mmu_lock);
5bb064dc 2759 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2760 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2761
2762 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2763 if (!slots)
2764 goto out_free;
2765
2766 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2767 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2768
2769 old_slots = kvm->memslots;
2770 rcu_assign_pointer(kvm->memslots, slots);
2771 synchronize_srcu_expedited(&kvm->srcu);
2772 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2773 kfree(old_slots);
5bb064dc 2774 }
b050b015 2775
5bb064dc 2776 r = 0;
b050b015
MT		 2777 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2778 r = -EFAULT;
2779out_free:
2780 vfree(dirty_bitmap);
5bb064dc 2781out:
79fac95e 2782 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2783 return r;
2784}
2785
1fe779f8
CO		 2786long kvm_arch_vm_ioctl(struct file *filp,
2787 unsigned int ioctl, unsigned long arg)
2788{
2789 struct kvm *kvm = filp->private_data;
2790 void __user *argp = (void __user *)arg;
367e1319 2791 int r = -ENOTTY;
f0d66275
DH		 2792 /*
2793 * This union makes it completely explicit to gcc-3.x
2794 * that these two variables' stack usage should be
2795 * combined, not added together.
2796 */
2797 union {
2798 struct kvm_pit_state ps;
e9f42757 2799 struct kvm_pit_state2 ps2;
f0d66275 2800 struct kvm_memory_alias alias;
c5ff41ce 2801 struct kvm_pit_config pit_config;
f0d66275 2802 } u;
1fe779f8
CO		 2803
2804 switch (ioctl) {
2805 case KVM_SET_TSS_ADDR:
2806 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2807 if (r < 0)
2808 goto out;
2809 break;
b927a3ce
SY		 2810 case KVM_SET_IDENTITY_MAP_ADDR: {
2811 u64 ident_addr;
2812
2813 r = -EFAULT;
2814 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2815 goto out;
2816 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2817 if (r < 0)
2818 goto out;
2819 break;
2820 }
1fe779f8
CO		 2821 case KVM_SET_MEMORY_REGION: {
2822 struct kvm_memory_region kvm_mem;
2823 struct kvm_userspace_memory_region kvm_userspace_mem;
2824
2825 r = -EFAULT;
2826 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2827 goto out;
2828 kvm_userspace_mem.slot = kvm_mem.slot;
2829 kvm_userspace_mem.flags = kvm_mem.flags;
2830 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2831 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2832 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2833 if (r)
2834 goto out;
2835 break;
2836 }
2837 case KVM_SET_NR_MMU_PAGES:
2838 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2839 if (r)
2840 goto out;
2841 break;
2842 case KVM_GET_NR_MMU_PAGES:
2843 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2844 break;
f0d66275 2845 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2846 r = -EFAULT;
f0d66275 2847 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2848 goto out;
f0d66275 2849 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2850 if (r)
2851 goto out;
2852 break;
3ddea128
MT		 2853 case KVM_CREATE_IRQCHIP: {
2854 struct kvm_pic *vpic;
2855
2856 mutex_lock(&kvm->lock);
2857 r = -EEXIST;
2858 if (kvm->arch.vpic)
2859 goto create_irqchip_unlock;
1fe779f8 2860 r = -ENOMEM;
3ddea128
MT		 2861 vpic = kvm_create_pic(kvm);
2862 if (vpic) {
1fe779f8
CO		 2863 r = kvm_ioapic_init(kvm);
2864 if (r) {
72bb2fcd
WY		 2865 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2866 &vpic->dev);
3ddea128
MT		 2867 kfree(vpic);
2868 goto create_irqchip_unlock;
1fe779f8
CO		 2869 }
2870 } else
3ddea128
MT		 2871 goto create_irqchip_unlock;
2872 smp_wmb();
2873 kvm->arch.vpic = vpic;
2874 smp_wmb();
399ec807
AK		 2875 r = kvm_setup_default_irq_routing(kvm);
2876 if (r) {
3ddea128 2877 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2878 kvm_ioapic_destroy(kvm);
2879 kvm_destroy_pic(kvm);
3ddea128 2880 mutex_unlock(&kvm->irq_lock);
399ec807 2881 }
3ddea128
MT		 2882 create_irqchip_unlock:
2883 mutex_unlock(&kvm->lock);
1fe779f8 2884 break;
3ddea128 2885 }
7837699f 2886 case KVM_CREATE_PIT:
c5ff41ce
JK		 2887 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2888 goto create_pit;
2889 case KVM_CREATE_PIT2:
2890 r = -EFAULT;
2891 if (copy_from_user(&u.pit_config, argp,
2892 sizeof(struct kvm_pit_config)))
2893 goto out;
2894 create_pit:
79fac95e 2895 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2896 r = -EEXIST;
2897 if (kvm->arch.vpit)
2898 goto create_pit_unlock;
7837699f 2899 r = -ENOMEM;
c5ff41ce 2900 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2901 if (kvm->arch.vpit)
2902 r = 0;
269e05e4 2903 create_pit_unlock:
79fac95e 2904 mutex_unlock(&kvm->slots_lock);
7837699f 2905 break;
4925663a 2906 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2907 case KVM_IRQ_LINE: {
2908 struct kvm_irq_level irq_event;
2909
2910 r = -EFAULT;
2911 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2912 goto out;
160d2f6c 2913 r = -ENXIO;
1fe779f8 2914 if (irqchip_in_kernel(kvm)) {
4925663a 2915 __s32 status;
4925663a
GN		 2916 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2917 irq_event.irq, irq_event.level);
4925663a 2918 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 2919 r = -EFAULT;
4925663a
GN		 2920 irq_event.status = status;
2921 if (copy_to_user(argp, &irq_event,
2922 sizeof irq_event))
2923 goto out;
2924 }
1fe779f8
CO		 2925 r = 0;
2926 }
2927 break;
2928 }
2929 case KVM_GET_IRQCHIP: {
2930 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2931 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2932
f0d66275
DH		 2933 r = -ENOMEM;
2934 if (!chip)
1fe779f8 2935 goto out;
f0d66275
DH		 2936 r = -EFAULT;
2937 if (copy_from_user(chip, argp, sizeof *chip))
2938 goto get_irqchip_out;
1fe779f8
CO		 2939 r = -ENXIO;
2940 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2941 goto get_irqchip_out;
2942 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2943 if (r)
f0d66275 2944 goto get_irqchip_out;
1fe779f8 2945 r = -EFAULT;
f0d66275
DH		 2946 if (copy_to_user(argp, chip, sizeof *chip))
2947 goto get_irqchip_out;
1fe779f8 2948 r = 0;
f0d66275
DH		 2949 get_irqchip_out:
2950 kfree(chip);
2951 if (r)
2952 goto out;
1fe779f8
CO		 2953 break;
2954 }
2955 case KVM_SET_IRQCHIP: {
2956 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2957 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2958
f0d66275
DH		 2959 r = -ENOMEM;
2960 if (!chip)
1fe779f8 2961 goto out;
f0d66275
DH		 2962 r = -EFAULT;
2963 if (copy_from_user(chip, argp, sizeof *chip))
2964 goto set_irqchip_out;
1fe779f8
CO		 2965 r = -ENXIO;
2966 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2967 goto set_irqchip_out;
2968 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2969 if (r)
f0d66275 2970 goto set_irqchip_out;
1fe779f8 2971 r = 0;
f0d66275
DH		 2972 set_irqchip_out:
2973 kfree(chip);
2974 if (r)
2975 goto out;
1fe779f8
CO		 2976 break;
2977 }
e0f63cb9 2978 case KVM_GET_PIT: {
e0f63cb9 2979 r = -EFAULT;
f0d66275 2980 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2981 goto out;
2982 r = -ENXIO;
2983 if (!kvm->arch.vpit)
2984 goto out;
f0d66275 2985 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2986 if (r)
2987 goto out;
2988 r = -EFAULT;
f0d66275 2989 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2990 goto out;
2991 r = 0;
2992 break;
2993 }
2994 case KVM_SET_PIT: {
e0f63cb9 2995 r = -EFAULT;
f0d66275 2996 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2997 goto out;
2998 r = -ENXIO;
2999 if (!kvm->arch.vpit)
3000 goto out;
f0d66275 3001 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3002 if (r)
3003 goto out;
3004 r = 0;
3005 break;
3006 }
e9f42757
BK		 3007 case KVM_GET_PIT2: {
3008 r = -ENXIO;
3009 if (!kvm->arch.vpit)
3010 goto out;
3011 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3012 if (r)
3013 goto out;
3014 r = -EFAULT;
3015 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3016 goto out;
3017 r = 0;
3018 break;
3019 }
3020 case KVM_SET_PIT2: {
3021 r = -EFAULT;
3022 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3023 goto out;
3024 r = -ENXIO;
3025 if (!kvm->arch.vpit)
3026 goto out;
3027 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3028 if (r)
3029 goto out;
3030 r = 0;
3031 break;
3032 }
52d939a0
MT		 3033 case KVM_REINJECT_CONTROL: {
3034 struct kvm_reinject_control control;
3035 r = -EFAULT;
3036 if (copy_from_user(&control, argp, sizeof(control)))
3037 goto out;
3038 r = kvm_vm_ioctl_reinject(kvm, &control);
3039 if (r)
3040 goto out;
3041 r = 0;
3042 break;
3043 }
ffde22ac
ES		 3044 case KVM_XEN_HVM_CONFIG: {
3045 r = -EFAULT;
3046 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3047 sizeof(struct kvm_xen_hvm_config)))
3048 goto out;
3049 r = -EINVAL;
3050 if (kvm->arch.xen_hvm_config.flags)
3051 goto out;
3052 r = 0;
3053 break;
3054 }
afbcf7ab
GC		 3055 case KVM_SET_CLOCK: {
3056 struct timespec now;
3057 struct kvm_clock_data user_ns;
3058 u64 now_ns;
3059 s64 delta;
3060
3061 r = -EFAULT;
3062 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3063 goto out;
3064
3065 r = -EINVAL;
3066 if (user_ns.flags)
3067 goto out;
3068
3069 r = 0;
3070 ktime_get_ts(&now);
3071 now_ns = timespec_to_ns(&now);
3072 delta = user_ns.clock - now_ns;
3073 kvm->arch.kvmclock_offset = delta;
3074 break;
3075 }
3076 case KVM_GET_CLOCK: {
3077 struct timespec now;
3078 struct kvm_clock_data user_ns;
3079 u64 now_ns;
3080
3081 ktime_get_ts(&now);
3082 now_ns = timespec_to_ns(&now);
3083 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3084 user_ns.flags = 0;
3085
3086 r = -EFAULT;
3087 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3088 goto out;
3089 r = 0;
3090 break;
3091 }
3092
1fe779f8
CO		 3093 default:
3094 ;
3095 }
3096out:
3097 return r;
3098}
3099
a16b043c 3100static void kvm_init_msr_list(void)
043405e1
CO		 3101{
3102 u32 dummy[2];
3103 unsigned i, j;
3104
e3267cbb
GC		 3105 /* skip the first msrs in the list. KVM-specific */
3106 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3107 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3108 continue;
3109 if (j < i)
3110 msrs_to_save[j] = msrs_to_save[i];
3111 j++;
3112 }
3113 num_msrs_to_save = j;
3114}
3115
bda9020e
MT		 3116static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3117 const void *v)
bbd9b64e 3118{
bda9020e
MT		 3119 if (vcpu->arch.apic &&
3120 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3121 return 0;
bbd9b64e 3122
e93f8a0f 3123 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3124}
3125
bda9020e 3126static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3127{
bda9020e
MT		 3128 if (vcpu->arch.apic &&
3129 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3130 return 0;
bbd9b64e 3131
e93f8a0f 3132 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3133}
3134
2dafc6c2
GN		 3135static void kvm_set_segment(struct kvm_vcpu *vcpu,
3136 struct kvm_segment *var, int seg)
3137{
3138 kvm_x86_ops->set_segment(vcpu, var, seg);
3139}
3140
3141void kvm_get_segment(struct kvm_vcpu *vcpu,
3142 struct kvm_segment *var, int seg)
3143{
3144 kvm_x86_ops->get_segment(vcpu, var, seg);
3145}
3146
1871c602
GN		 3147gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3148{
3149 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3150 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3151}
3152
3153 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3154{
3155 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3156 access |= PFERR_FETCH_MASK;
3157 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3158}
3159
3160gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3161{
3162 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3163 access |= PFERR_WRITE_MASK;
3164 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3165}
3166
3167/* uses this to access any guest's mapped memory without checking CPL */
3168gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3169{
3170 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3171}
3172
3173static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3174 struct kvm_vcpu *vcpu, u32 access,
3175 u32 *error)
bbd9b64e
CO		 3176{
3177 void *data = val;
10589a46 3178 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3179
3180 while (bytes) {
1871c602 3181 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3182 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3183 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3184 int ret;
3185
10589a46
MT		 3186 if (gpa == UNMAPPED_GVA) {
3187 r = X86EMUL_PROPAGATE_FAULT;
3188 goto out;
3189 }
77c2002e 3190 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3191 if (ret < 0) {
3192 r = X86EMUL_UNHANDLEABLE;
3193 goto out;
3194 }
bbd9b64e 3195
77c2002e
IE		 3196 bytes -= toread;
3197 data += toread;
3198 addr += toread;
bbd9b64e 3199 }
10589a46 3200out:
10589a46 3201 return r;
bbd9b64e 3202}
77c2002e 3203
1871c602
GN		 3204/* used for instruction fetching */
3205static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3206 struct kvm_vcpu *vcpu, u32 *error)
3207{
3208 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3209 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3210 access | PFERR_FETCH_MASK, error);
3211}
3212
3213static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3214 struct kvm_vcpu *vcpu, u32 *error)
3215{
3216 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3217 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3218 error);
3219}
3220
3221static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3222 struct kvm_vcpu *vcpu, u32 *error)
3223{
3224 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3225}
3226
7972995b 3227static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3228 unsigned int bytes,
7972995b 3229 struct kvm_vcpu *vcpu,
2dafc6c2 3230 u32 *error)
77c2002e
IE		 3231{
3232 void *data = val;
3233 int r = X86EMUL_CONTINUE;
3234
3235 while (bytes) {
7972995b
GN		 3236 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3237 PFERR_WRITE_MASK, error);
77c2002e
IE		 3238 unsigned offset = addr & (PAGE_SIZE-1);
3239 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3240 int ret;
3241
3242 if (gpa == UNMAPPED_GVA) {
3243 r = X86EMUL_PROPAGATE_FAULT;
3244 goto out;
3245 }
3246 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3247 if (ret < 0) {
3248 r = X86EMUL_UNHANDLEABLE;
3249 goto out;
3250 }
3251
3252 bytes -= towrite;
3253 data += towrite;
3254 addr += towrite;
3255 }
3256out:
3257 return r;
3258}
3259
bbd9b64e
CO		 3260static int emulator_read_emulated(unsigned long addr,
3261 void *val,
3262 unsigned int bytes,
3263 struct kvm_vcpu *vcpu)
3264{
bbd9b64e 3265 gpa_t gpa;
1871c602 3266 u32 error_code;
bbd9b64e
CO		 3267
3268 if (vcpu->mmio_read_completed) {
3269 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3270 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3271 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3272 vcpu->mmio_read_completed = 0;
3273 return X86EMUL_CONTINUE;
3274 }
3275
1871c602
GN		 3276 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3277
3278 if (gpa == UNMAPPED_GVA) {
3279 kvm_inject_page_fault(vcpu, addr, error_code);
3280 return X86EMUL_PROPAGATE_FAULT;
3281 }
bbd9b64e
CO		 3282
3283 /* For APIC access vmexit */
3284 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3285 goto mmio;
3286
1871c602 3287 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3288 == X86EMUL_CONTINUE)
bbd9b64e 3289 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3290
3291mmio:
3292 /*
3293 * Is this MMIO handled locally?
3294 */
aec51dc4
AK		 3295 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3296 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3297 return X86EMUL_CONTINUE;
3298 }
aec51dc4
AK		 3299
3300 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3301
3302 vcpu->mmio_needed = 1;
3303 vcpu->mmio_phys_addr = gpa;
3304 vcpu->mmio_size = bytes;
3305 vcpu->mmio_is_write = 0;
3306
3307 return X86EMUL_UNHANDLEABLE;
3308}
3309
3200f405 3310int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3311 const void *val, int bytes)
bbd9b64e
CO		 3312{
3313 int ret;
3314
3315 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3316 if (ret < 0)
bbd9b64e 3317 return 0;
ad218f85 3318 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3319 return 1;
3320}
3321
3322static int emulator_write_emulated_onepage(unsigned long addr,
3323 const void *val,
3324 unsigned int bytes,
4a5f48f6
AK		 3325 struct kvm_vcpu *vcpu,
3326 bool mmu_only)
bbd9b64e 3327{
10589a46 3328 gpa_t gpa;
1871c602 3329 u32 error_code;
10589a46 3330
1871c602 3331 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3332
3333 if (gpa == UNMAPPED_GVA) {
1871c602 3334 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3335 return X86EMUL_PROPAGATE_FAULT;
3336 }
3337
3338 /* For APIC access vmexit */
3339 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3340 goto mmio;
3341
4a5f48f6
AK		 3342 if (mmu_only) {
3343 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
3344 return X86EMUL_CONTINUE;
3345 }
bbd9b64e
CO		 3346 if (emulator_write_phys(vcpu, gpa, val, bytes))
3347 return X86EMUL_CONTINUE;
3348
3349mmio:
aec51dc4 3350 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3351 /*
3352 * Is this MMIO handled locally?
3353 */
bda9020e 3354 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3355 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3356
3357 vcpu->mmio_needed = 1;
3358 vcpu->mmio_phys_addr = gpa;
3359 vcpu->mmio_size = bytes;
3360 vcpu->mmio_is_write = 1;
3361 memcpy(vcpu->mmio_data, val, bytes);
3362
3363 return X86EMUL_CONTINUE;
3364}
3365
4a5f48f6 3366int __emulator_write_emulated(unsigned long addr,
bbd9b64e
CO		 3367 const void *val,
3368 unsigned int bytes,
4a5f48f6
AK		 3369 struct kvm_vcpu *vcpu,
3370 bool mmu_only)
bbd9b64e
CO		 3371{
3372 /* Crossing a page boundary? */
3373 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3374 int rc, now;
3375
3376 now = -addr & ~PAGE_MASK;
4a5f48f6
AK		 3377 rc = emulator_write_emulated_onepage(addr, val, now, vcpu,
3378 mmu_only);
bbd9b64e
CO		 3379 if (rc != X86EMUL_CONTINUE)
3380 return rc;
3381 addr += now;
3382 val += now;
3383 bytes -= now;
3384 }
4a5f48f6
AK		 3385 return emulator_write_emulated_onepage(addr, val, bytes, vcpu,
3386 mmu_only);
3387}
3388
3389int emulator_write_emulated(unsigned long addr,
3390 const void *val,
3391 unsigned int bytes,
3392 struct kvm_vcpu *vcpu)
3393{
3394 return __emulator_write_emulated(addr, val, bytes, vcpu, false);
bbd9b64e
CO		 3395}
3396EXPORT_SYMBOL_GPL(emulator_write_emulated);
3397
daea3e73
AK		 3398#define CMPXCHG_TYPE(t, ptr, old, new) \
3399 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3400
3401#ifdef CONFIG_X86_64
3402# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3403#else
3404# define CMPXCHG64(ptr, old, new) \
9749a6c0 3405 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3406#endif
3407
bbd9b64e
CO		 3408static int emulator_cmpxchg_emulated(unsigned long addr,
3409 const void *old,
3410 const void *new,
3411 unsigned int bytes,
3412 struct kvm_vcpu *vcpu)
3413{
daea3e73
AK		 3414 gpa_t gpa;
3415 struct page *page;
3416 char *kaddr;
3417 bool exchanged;
2bacc55c 3418
daea3e73
AK		 3419 /* guests cmpxchg8b have to be emulated atomically */
3420 if (bytes > 8 || (bytes & (bytes - 1)))
3421 goto emul_write;
10589a46 3422
daea3e73 3423 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3424
daea3e73
AK		 3425 if (gpa == UNMAPPED_GVA ||
3426 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3427 goto emul_write;
2bacc55c 3428
daea3e73
AK		 3429 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3430 goto emul_write;
72dc67a6 3431
daea3e73 3432 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3433
daea3e73
AK		 3434 kaddr = kmap_atomic(page, KM_USER0);
3435 kaddr += offset_in_page(gpa);
3436 switch (bytes) {
3437 case 1:
3438 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3439 break;
3440 case 2:
3441 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3442 break;
3443 case 4:
3444 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3445 break;
3446 case 8:
3447 exchanged = CMPXCHG64(kaddr, old, new);
3448 break;
3449 default:
3450 BUG();
2bacc55c 3451 }
daea3e73
AK		 3452 kunmap_atomic(kaddr, KM_USER0);
3453 kvm_release_page_dirty(page);
3454
3455 if (!exchanged)
3456 return X86EMUL_CMPXCHG_FAILED;
3457
4a5f48f6
AK		 3458 return __emulator_write_emulated(addr, new, bytes, vcpu, true);
3459
3200f405 3460emul_write:
daea3e73 3461 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3462
bbd9b64e
CO		 3463 return emulator_write_emulated(addr, new, bytes, vcpu);
3464}
3465
cf8f70bf
GN		 3466static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3467{
3468 /* TODO: String I/O for in kernel device */
3469 int r;
3470
3471 if (vcpu->arch.pio.in)
3472 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3473 vcpu->arch.pio.size, pd);
3474 else
3475 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3476 vcpu->arch.pio.port, vcpu->arch.pio.size,
3477 pd);
3478 return r;
3479}
3480
3481
3482static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3483 unsigned int count, struct kvm_vcpu *vcpu)
3484{
7972995b 3485 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3486 goto data_avail;
3487
3488 trace_kvm_pio(1, port, size, 1);
3489
3490 vcpu->arch.pio.port = port;
3491 vcpu->arch.pio.in = 1;
7972995b 3492 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3493 vcpu->arch.pio.size = size;
3494
3495 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3496 data_avail:
3497 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3498 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3499 return 1;
3500 }
3501
3502 vcpu->run->exit_reason = KVM_EXIT_IO;
3503 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3504 vcpu->run->io.size = size;
3505 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3506 vcpu->run->io.count = count;
3507 vcpu->run->io.port = port;
3508
3509 return 0;
3510}
3511
3512static int emulator_pio_out_emulated(int size, unsigned short port,
3513 const void *val, unsigned int count,
3514 struct kvm_vcpu *vcpu)
3515{
3516 trace_kvm_pio(0, port, size, 1);
3517
3518 vcpu->arch.pio.port = port;
3519 vcpu->arch.pio.in = 0;
7972995b 3520 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3521 vcpu->arch.pio.size = size;
3522
3523 memcpy(vcpu->arch.pio_data, val, size * count);
3524
3525 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3526 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3527 return 1;
3528 }
3529
3530 vcpu->run->exit_reason = KVM_EXIT_IO;
3531 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3532 vcpu->run->io.size = size;
3533 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3534 vcpu->run->io.count = count;
3535 vcpu->run->io.port = port;
3536
3537 return 0;
3538}
3539
bbd9b64e
CO		 3540static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3541{
3542 return kvm_x86_ops->get_segment_base(vcpu, seg);
3543}
3544
3545int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3546{
a7052897 3547 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3548 return X86EMUL_CONTINUE;
3549}
3550
3551int emulate_clts(struct kvm_vcpu *vcpu)
3552{
4d4ec087 3553 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3554 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3555 return X86EMUL_CONTINUE;
3556}
3557
3558int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3559{
020df079 3560 return kvm_get_dr(ctxt->vcpu, dr, dest);
bbd9b64e
CO		 3561}
3562
3563int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3564{
3565 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
bbd9b64e 3566
020df079 3567 return kvm_set_dr(ctxt->vcpu, dr, value & mask);
bbd9b64e
CO		 3568}
3569
3570void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3571{
bbd9b64e 3572 u8 opcodes[4];
5fdbf976 3573 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3574 unsigned long rip_linear;
3575
f76c710d 3576 if (!printk_ratelimit())
bbd9b64e
CO		 3577 return;
3578
25be4608
GC		 3579 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3580
1871c602 3581 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3582
3583 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3584 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3585}
3586EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3587
52a46617
GN		 3588static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3589{
3590 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3591}
3592
3593static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
3594{
3595 unsigned long value;
3596
3597 switch (cr) {
3598 case 0:
3599 value = kvm_read_cr0(vcpu);
3600 break;
3601 case 2:
3602 value = vcpu->arch.cr2;
3603 break;
3604 case 3:
3605 value = vcpu->arch.cr3;
3606 break;
3607 case 4:
3608 value = kvm_read_cr4(vcpu);
3609 break;
3610 case 8:
3611 value = kvm_get_cr8(vcpu);
3612 break;
3613 default:
3614 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3615 return 0;
3616 }
3617
3618 return value;
3619}
3620
3621static void emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
3622{
3623 switch (cr) {
3624 case 0:
3625 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
3626 break;
3627 case 2:
3628 vcpu->arch.cr2 = val;
3629 break;
3630 case 3:
3631 kvm_set_cr3(vcpu, val);
3632 break;
3633 case 4:
3634 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
3635 break;
3636 case 8:
3637 kvm_set_cr8(vcpu, val & 0xfUL);
3638 break;
3639 default:
3640 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3641 }
3642}
3643
9c537244
GN		 3644static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3645{
3646 return kvm_x86_ops->get_cpl(vcpu);
3647}
3648
2dafc6c2
GN		 3649static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3650{
3651 kvm_x86_ops->get_gdt(vcpu, dt);
3652}
3653
3654static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3655 struct kvm_vcpu *vcpu)
3656{
3657 struct kvm_segment var;
3658
3659 kvm_get_segment(vcpu, &var, seg);
3660
3661 if (var.unusable)
3662 return false;
3663
3664 if (var.g)
3665 var.limit >>= 12;
3666 set_desc_limit(desc, var.limit);
3667 set_desc_base(desc, (unsigned long)var.base);
3668 desc->type = var.type;
3669 desc->s = var.s;
3670 desc->dpl = var.dpl;
3671 desc->p = var.present;
3672 desc->avl = var.avl;
3673 desc->l = var.l;
3674 desc->d = var.db;
3675 desc->g = var.g;
3676
3677 return true;
3678}
3679
3680static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3681 struct kvm_vcpu *vcpu)
3682{
3683 struct kvm_segment var;
3684
3685 /* needed to preserve selector */
3686 kvm_get_segment(vcpu, &var, seg);
3687
3688 var.base = get_desc_base(desc);
3689 var.limit = get_desc_limit(desc);
3690 if (desc->g)
3691 var.limit = (var.limit << 12) | 0xfff;
3692 var.type = desc->type;
3693 var.present = desc->p;
3694 var.dpl = desc->dpl;
3695 var.db = desc->d;
3696 var.s = desc->s;
3697 var.l = desc->l;
3698 var.g = desc->g;
3699 var.avl = desc->avl;
3700 var.present = desc->p;
3701 var.unusable = !var.present;
3702 var.padding = 0;
3703
3704 kvm_set_segment(vcpu, &var, seg);
3705 return;
3706}
3707
3708static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3709{
3710 struct kvm_segment kvm_seg;
3711
3712 kvm_get_segment(vcpu, &kvm_seg, seg);
3713 return kvm_seg.selector;
3714}
3715
3716static void emulator_set_segment_selector(u16 sel, int seg,
3717 struct kvm_vcpu *vcpu)
3718{
3719 struct kvm_segment kvm_seg;
3720
3721 kvm_get_segment(vcpu, &kvm_seg, seg);
3722 kvm_seg.selector = sel;
3723 kvm_set_segment(vcpu, &kvm_seg, seg);
3724}
3725
482ac18a
GN		 3726static void emulator_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
3727{
3728 kvm_x86_ops->set_rflags(vcpu, rflags);
3729}
3730
14af3f3c 3731static struct x86_emulate_ops emulate_ops = {
1871c602 3732 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3733 .write_std = kvm_write_guest_virt_system,
1871c602 3734 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3735 .read_emulated = emulator_read_emulated,
3736 .write_emulated = emulator_write_emulated,
3737 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3738 .pio_in_emulated = emulator_pio_in_emulated,
3739 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 3740 .get_cached_descriptor = emulator_get_cached_descriptor,
3741 .set_cached_descriptor = emulator_set_cached_descriptor,
3742 .get_segment_selector = emulator_get_segment_selector,
3743 .set_segment_selector = emulator_set_segment_selector,
3744 .get_gdt = emulator_get_gdt,
52a46617
GN		 3745 .get_cr = emulator_get_cr,
3746 .set_cr = emulator_set_cr,
9c537244 3747 .cpl = emulator_get_cpl,
482ac18a 3748 .set_rflags = emulator_set_rflags,
bbd9b64e
CO		 3749};
3750
5fdbf976
MT		 3751static void cache_all_regs(struct kvm_vcpu *vcpu)
3752{
3753 kvm_register_read(vcpu, VCPU_REGS_RAX);
3754 kvm_register_read(vcpu, VCPU_REGS_RSP);
3755 kvm_register_read(vcpu, VCPU_REGS_RIP);
3756 vcpu->arch.regs_dirty = ~0;
3757}
3758
bbd9b64e 3759int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3760 unsigned long cr2,
3761 u16 error_code,
571008da 3762 int emulation_type)
bbd9b64e 3763{
310b5d30 3764 int r, shadow_mask;
571008da 3765 struct decode_cache *c;
851ba692 3766 struct kvm_run *run = vcpu->run;
bbd9b64e 3767
26eef70c 3768 kvm_clear_exception_queue(vcpu);
ad312c7c 3769 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3770 /*
56e82318 3771 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3772 * instead of direct ->regs accesses, can save hundred cycles
3773 * on Intel for instructions that don't read/change RSP, for
3774 * for example.
3775 */
3776 cache_all_regs(vcpu);
bbd9b64e
CO		 3777
3778 vcpu->mmio_is_write = 0;
bbd9b64e 3779
571008da 3780 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3781 int cs_db, cs_l;
3782 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3783
ad312c7c 3784 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3785 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
063db061 3786 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
ad312c7c 3787 vcpu->arch.emulate_ctxt.mode =
a0044755 3788 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3789 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3790 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3791 ? X86EMUL_MODE_PROT64 : cs_db
3792 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3793
ad312c7c 3794 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
e46479f8 3795 trace_kvm_emulate_insn_start(vcpu);
571008da 3796
0cb5762e
AP		 3797 /* Only allow emulation of specific instructions on #UD
3798 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3799 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3800 if (emulation_type & EMULTYPE_TRAP_UD) {
3801 if (!c->twobyte)
3802 return EMULATE_FAIL;
3803 switch (c->b) {
3804 case 0x01: /* VMMCALL */
3805 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3806 return EMULATE_FAIL;
3807 break;
3808 case 0x34: /* sysenter */
3809 case 0x35: /* sysexit */
3810 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3811 return EMULATE_FAIL;
3812 break;
3813 case 0x05: /* syscall */
3814 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3815 return EMULATE_FAIL;
3816 break;
3817 default:
3818 return EMULATE_FAIL;
3819 }
3820
3821 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3822 return EMULATE_FAIL;
3823 }
571008da 3824
f2b5756b 3825 ++vcpu->stat.insn_emulation;
bbd9b64e 3826 if (r) {
f2b5756b 3827 ++vcpu->stat.insn_emulation_fail;
e46479f8 3828 trace_kvm_emulate_insn_failed(vcpu);
bbd9b64e
CO		 3829 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3830 return EMULATE_DONE;
3831 return EMULATE_FAIL;
3832 }
3833 }
3834
ba8afb6b
GN		 3835 if (emulation_type & EMULTYPE_SKIP) {
3836 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3837 return EMULATE_DONE;
3838 }
3839
5cd21917 3840restart:
ad312c7c 3841 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3842 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3843
3844 if (r == 0)
3845 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3846
7972995b 3847 if (vcpu->arch.pio.count) {
cf8f70bf 3848 if (!vcpu->arch.pio.in)
7972995b 3849 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3850 return EMULATE_DO_MMIO;
3851 }
3852
112592da 3853 if (r || vcpu->mmio_is_write) {
bbd9b64e
CO		 3854 run->exit_reason = KVM_EXIT_MMIO;
3855 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3856 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3857 run->mmio.len = vcpu->mmio_size;
3858 run->mmio.is_write = vcpu->mmio_is_write;
3859 }
3860
3861 if (r) {
3862 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
5cd21917 3863 goto done;
bbd9b64e 3864 if (!vcpu->mmio_needed) {
e46479f8
AK		 3865 ++vcpu->stat.insn_emulation_fail;
3866 trace_kvm_emulate_insn_failed(vcpu);
bbd9b64e
CO		 3867 kvm_report_emulation_failure(vcpu, "mmio");
3868 return EMULATE_FAIL;
3869 }
3870 return EMULATE_DO_MMIO;
3871 }
3872
bbd9b64e
CO		 3873 if (vcpu->mmio_is_write) {
3874 vcpu->mmio_needed = 0;
3875 return EMULATE_DO_MMIO;
3876 }
3877
5cd21917
GN		 3878done:
3879 if (vcpu->arch.exception.pending)
3880 vcpu->arch.emulate_ctxt.restart = false;
3881
3882 if (vcpu->arch.emulate_ctxt.restart)
3883 goto restart;
3884
bbd9b64e
CO		 3885 return EMULATE_DONE;
3886}
3887EXPORT_SYMBOL_GPL(emulate_instruction);
3888
cf8f70bf
GN		 3889int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
3890{
3891 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3892 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
3893 /* do not return to emulator after return from userspace */
7972995b 3894 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3895 return ret;
3896}
3897EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
3898
c8076604
GH		 3899static void bounce_off(void *info)
3900{
3901 /* nothing */
3902}
3903
c8076604
GH		 3904static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3905 void *data)
3906{
3907 struct cpufreq_freqs *freq = data;
3908 struct kvm *kvm;
3909 struct kvm_vcpu *vcpu;
3910 int i, send_ipi = 0;
3911
c8076604
GH		 3912 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3913 return 0;
3914 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3915 return 0;
0cca7907 3916 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3917
3918 spin_lock(&kvm_lock);
3919 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3920 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3921 if (vcpu->cpu != freq->cpu)
3922 continue;
3923 if (!kvm_request_guest_time_update(vcpu))
3924 continue;
3925 if (vcpu->cpu != smp_processor_id())
3926 send_ipi++;
3927 }
3928 }
3929 spin_unlock(&kvm_lock);
3930
3931 if (freq->old < freq->new && send_ipi) {
3932 /*
3933 * We upscale the frequency. Must make the guest
3934 * doesn't see old kvmclock values while running with
3935 * the new frequency, otherwise we risk the guest sees
3936 * time go backwards.
3937 *
3938 * In case we update the frequency for another cpu
3939 * (which might be in guest context) send an interrupt
3940 * to kick the cpu out of guest context. Next time
3941 * guest context is entered kvmclock will be updated,
3942 * so the guest will not see stale values.
3943 */
3944 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3945 }
3946 return 0;
3947}
3948
3949static struct notifier_block kvmclock_cpufreq_notifier_block = {
3950 .notifier_call = kvmclock_cpufreq_notifier
3951};
3952
b820cc0c
ZA		 3953static void kvm_timer_init(void)
3954{
3955 int cpu;
3956
b820cc0c 3957 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3958 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3959 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3960 for_each_online_cpu(cpu) {
3961 unsigned long khz = cpufreq_get(cpu);
3962 if (!khz)
3963 khz = tsc_khz;
3964 per_cpu(cpu_tsc_khz, cpu) = khz;
3965 }
0cca7907
ZA		 3966 } else {
3967 for_each_possible_cpu(cpu)
3968 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3969 }
3970}
3971
f8c16bba 3972int kvm_arch_init(void *opaque)
043405e1 3973{
b820cc0c 3974 int r;
f8c16bba
ZX		 3975 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3976
f8c16bba
ZX		 3977 if (kvm_x86_ops) {
3978 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3979 r = -EEXIST;
3980 goto out;
f8c16bba
ZX		 3981 }
3982
3983 if (!ops->cpu_has_kvm_support()) {
3984 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3985 r = -EOPNOTSUPP;
3986 goto out;
f8c16bba
ZX		 3987 }
3988 if (ops->disabled_by_bios()) {
3989 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3990 r = -EOPNOTSUPP;
3991 goto out;
f8c16bba
ZX		 3992 }
3993
97db56ce
AK		 3994 r = kvm_mmu_module_init();
3995 if (r)
3996 goto out;
3997
3998 kvm_init_msr_list();
3999
f8c16bba 4000 kvm_x86_ops = ops;
56c6d28a 4001 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4002 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4003 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4004 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4005
b820cc0c 4006 kvm_timer_init();
c8076604 4007
f8c16bba 4008 return 0;
56c6d28a
ZX		 4009
4010out:
56c6d28a 4011 return r;
043405e1 4012}
8776e519 4013
f8c16bba
ZX		 4014void kvm_arch_exit(void)
4015{
888d256e
JK		 4016 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4017 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4018 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 4019 kvm_x86_ops = NULL;
56c6d28a
ZX		 4020 kvm_mmu_module_exit();
4021}
f8c16bba 4022
8776e519
HB		 4023int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4024{
4025 ++vcpu->stat.halt_exits;
4026 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4027 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4028 return 1;
4029 } else {
4030 vcpu->run->exit_reason = KVM_EXIT_HLT;
4031 return 0;
4032 }
4033}
4034EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4035
2f333bcb
MT		 4036static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4037 unsigned long a1)
4038{
4039 if (is_long_mode(vcpu))
4040 return a0;
4041 else
4042 return a0 | ((gpa_t)a1 << 32);
4043}
4044
55cd8e5a
GN		 4045int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4046{
4047 u64 param, ingpa, outgpa, ret;
4048 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4049 bool fast, longmode;
4050 int cs_db, cs_l;
4051
4052 /*
4053 * hypercall generates UD from non zero cpl and real mode
4054 * per HYPER-V spec
4055 */
3eeb3288 4056 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4057 kvm_queue_exception(vcpu, UD_VECTOR);
4058 return 0;
4059 }
4060
4061 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4062 longmode = is_long_mode(vcpu) && cs_l == 1;
4063
4064 if (!longmode) {
ccd46936
GN		 4065 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4066 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4067 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4068 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4069 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4070 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4071 }
4072#ifdef CONFIG_X86_64
4073 else {
4074 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4075 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4076 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4077 }
4078#endif
4079
4080 code = param & 0xffff;
4081 fast = (param >> 16) & 0x1;
4082 rep_cnt = (param >> 32) & 0xfff;
4083 rep_idx = (param >> 48) & 0xfff;
4084
4085 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4086
c25bc163
GN		 4087 switch (code) {
4088 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4089 kvm_vcpu_on_spin(vcpu);
4090 break;
4091 default:
4092 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4093 break;
4094 }
55cd8e5a
GN		 4095
4096 ret = res | (((u64)rep_done & 0xfff) << 32);
4097 if (longmode) {
4098 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4099 } else {
4100 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4101 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4102 }
4103
4104 return 1;
4105}
4106
8776e519
HB		 4107int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4108{
4109 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4110 int r = 1;
8776e519 4111
55cd8e5a
GN		 4112 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4113 return kvm_hv_hypercall(vcpu);
4114
5fdbf976
MT		 4115 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4116 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4117 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4118 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4119 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4120
229456fc 4121 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4122
8776e519
HB		 4123 if (!is_long_mode(vcpu)) {
4124 nr &= 0xFFFFFFFF;
4125 a0 &= 0xFFFFFFFF;
4126 a1 &= 0xFFFFFFFF;
4127 a2 &= 0xFFFFFFFF;
4128 a3 &= 0xFFFFFFFF;
4129 }
4130
07708c4a
JK		 4131 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4132 ret = -KVM_EPERM;
4133 goto out;
4134 }
4135
8776e519 4136 switch (nr) {
b93463aa
AK		 4137 case KVM_HC_VAPIC_POLL_IRQ:
4138 ret = 0;
4139 break;
2f333bcb
MT		 4140 case KVM_HC_MMU_OP:
4141 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4142 break;
8776e519
HB		 4143 default:
4144 ret = -KVM_ENOSYS;
4145 break;
4146 }
07708c4a 4147out:
5fdbf976 4148 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4149 ++vcpu->stat.hypercalls;
2f333bcb 4150 return r;
8776e519
HB		 4151}
4152EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4153
4154int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4155{
4156 char instruction[3];
5fdbf976 4157 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4158
8776e519
HB		 4159 /*
4160 * Blow out the MMU to ensure that no other VCPU has an active mapping
4161 * to ensure that the updated hypercall appears atomically across all
4162 * VCPUs.
4163 */
4164 kvm_mmu_zap_all(vcpu->kvm);
4165
8776e519 4166 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4167
4a5f48f6 4168 return __emulator_write_emulated(rip, instruction, 3, vcpu, false);
8776e519
HB		 4169}
4170
8776e519
HB		 4171void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4172{
89a27f4d 4173 struct desc_ptr dt = { limit, base };
8776e519
HB		 4174
4175 kvm_x86_ops->set_gdt(vcpu, &dt);
4176}
4177
4178void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4179{
89a27f4d 4180 struct desc_ptr dt = { limit, base };
8776e519
HB		 4181
4182 kvm_x86_ops->set_idt(vcpu, &dt);
4183}
4184
07716717
DK		 4185static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4186{
ad312c7c
ZX		 4187 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4188 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4189
4190 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4191 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4192 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4193 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4194 if (ej->function == e->function) {
4195 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4196 return j;
4197 }
4198 }
4199 return 0; /* silence gcc, even though control never reaches here */
4200}
4201
4202/* find an entry with matching function, matching index (if needed), and that
4203 * should be read next (if it's stateful) */
4204static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4205 u32 function, u32 index)
4206{
4207 if (e->function != function)
4208 return 0;
4209 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4210 return 0;
4211 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4212 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4213 return 0;
4214 return 1;
4215}
4216
d8017474
AG		 4217struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4218 u32 function, u32 index)
8776e519
HB		 4219{
4220 int i;
d8017474 4221 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4222
ad312c7c 4223 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4224 struct kvm_cpuid_entry2 *e;
4225
ad312c7c 4226 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4227 if (is_matching_cpuid_entry(e, function, index)) {
4228 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4229 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4230 best = e;
4231 break;
4232 }
4233 /*
4234 * Both basic or both extended?
4235 */
4236 if (((e->function ^ function) & 0x80000000) == 0)
4237 if (!best || e->function > best->function)
4238 best = e;
4239 }
d8017474
AG		 4240 return best;
4241}
0e851880 4242EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4243
82725b20
DE		 4244int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4245{
4246 struct kvm_cpuid_entry2 *best;
4247
f7a71197
AK		 4248 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4249 if (!best || best->eax < 0x80000008)
4250 goto not_found;
82725b20
DE		 4251 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4252 if (best)
4253 return best->eax & 0xff;
f7a71197 4254not_found:
82725b20
DE		 4255 return 36;
4256}
4257
d8017474
AG		 4258void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4259{
4260 u32 function, index;
4261 struct kvm_cpuid_entry2 *best;
4262
4263 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4264 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4265 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4266 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4267 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4268 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4269 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4270 if (best) {
5fdbf976
MT		 4271 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4272 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4273 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4274 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4275 }
8776e519 4276 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4277 trace_kvm_cpuid(function,
4278 kvm_register_read(vcpu, VCPU_REGS_RAX),
4279 kvm_register_read(vcpu, VCPU_REGS_RBX),
4280 kvm_register_read(vcpu, VCPU_REGS_RCX),
4281 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4282}
4283EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4284
b6c7a5dc
HB		 4285/*
4286 * Check if userspace requested an interrupt window, and that the
4287 * interrupt window is open.
4288 *
4289 * No need to exit to userspace if we already have an interrupt queued.
4290 */
851ba692 4291static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4292{
8061823a 4293 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4294 vcpu->run->request_interrupt_window &&
5df56646 4295 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4296}
4297
851ba692 4298static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4299{
851ba692
AK		 4300 struct kvm_run *kvm_run = vcpu->run;
4301
91586a3b 4302 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4303 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4304 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4305 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4306 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4307 else
b6c7a5dc 4308 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4309 kvm_arch_interrupt_allowed(vcpu) &&
4310 !kvm_cpu_has_interrupt(vcpu) &&
4311 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4312}
4313
b93463aa
AK		 4314static void vapic_enter(struct kvm_vcpu *vcpu)
4315{
4316 struct kvm_lapic *apic = vcpu->arch.apic;
4317 struct page *page;
4318
4319 if (!apic || !apic->vapic_addr)
4320 return;
4321
4322 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4323
4324 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4325}
4326
4327static void vapic_exit(struct kvm_vcpu *vcpu)
4328{
4329 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4330 int idx;
b93463aa
AK		 4331
4332 if (!apic || !apic->vapic_addr)
4333 return;
4334
f656ce01 4335 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4336 kvm_release_page_dirty(apic->vapic_page);
4337 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4338 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4339}
4340
95ba8273
GN		 4341static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4342{
4343 int max_irr, tpr;
4344
4345 if (!kvm_x86_ops->update_cr8_intercept)
4346 return;
4347
88c808fd
AK		 4348 if (!vcpu->arch.apic)
4349 return;
4350
8db3baa2
GN		 4351 if (!vcpu->arch.apic->vapic_addr)
4352 max_irr = kvm_lapic_find_highest_irr(vcpu);
4353 else
4354 max_irr = -1;
95ba8273
GN		 4355
4356 if (max_irr != -1)
4357 max_irr >>= 4;
4358
4359 tpr = kvm_lapic_get_cr8(vcpu);
4360
4361 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4362}
4363
851ba692 4364static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4365{
4366 /* try to reinject previous events if any */
b59bb7bd 4367 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4368 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4369 vcpu->arch.exception.has_error_code,
4370 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4371 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4372 vcpu->arch.exception.has_error_code,
4373 vcpu->arch.exception.error_code);
4374 return;
4375 }
4376
95ba8273
GN		 4377 if (vcpu->arch.nmi_injected) {
4378 kvm_x86_ops->set_nmi(vcpu);
4379 return;
4380 }
4381
4382 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4383 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4384 return;
4385 }
4386
4387 /* try to inject new event if pending */
4388 if (vcpu->arch.nmi_pending) {
4389 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4390 vcpu->arch.nmi_pending = false;
4391 vcpu->arch.nmi_injected = true;
4392 kvm_x86_ops->set_nmi(vcpu);
4393 }
4394 } else if (kvm_cpu_has_interrupt(vcpu)) {
4395 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4396 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4397 false);
4398 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4399 }
4400 }
4401}
4402
851ba692 4403static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4404{
4405 int r;
6a8b1d13 4406 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4407 vcpu->run->request_interrupt_window;
b6c7a5dc 4408
2e53d63a
MT		 4409 if (vcpu->requests)
4410 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4411 kvm_mmu_unload(vcpu);
4412
b6c7a5dc
HB		 4413 r = kvm_mmu_reload(vcpu);
4414 if (unlikely(r))
4415 goto out;
4416
2f52d58c
AK		 4417 if (vcpu->requests) {
4418 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4419 __kvm_migrate_timers(vcpu);
c8076604
GH		 4420 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4421 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4422 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4423 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4424 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4425 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4426 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4427 &vcpu->requests)) {
851ba692 4428 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4429 r = 0;
4430 goto out;
4431 }
71c4dfaf 4432 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4433 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4434 r = 0;
4435 goto out;
4436 }
02daab21
AK		 4437 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4438 vcpu->fpu_active = 0;
4439 kvm_x86_ops->fpu_deactivate(vcpu);
4440 }
2f52d58c 4441 }
b93463aa 4442
b6c7a5dc
HB		 4443 preempt_disable();
4444
4445 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4446 if (vcpu->fpu_active)
4447 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4448
4449 local_irq_disable();
4450
32f88400
MT		 4451 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4452 smp_mb__after_clear_bit();
4453
d7690175 4454 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4455 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4456 local_irq_enable();
4457 preempt_enable();
4458 r = 1;
4459 goto out;
4460 }
4461
851ba692 4462 inject_pending_event(vcpu);
b6c7a5dc 4463
6a8b1d13
GN		 4464 /* enable NMI/IRQ window open exits if needed */
4465 if (vcpu->arch.nmi_pending)
4466 kvm_x86_ops->enable_nmi_window(vcpu);
4467 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4468 kvm_x86_ops->enable_irq_window(vcpu);
4469
95ba8273 4470 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4471 update_cr8_intercept(vcpu);
4472 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4473 }
b93463aa 4474
f656ce01 4475 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4476
b6c7a5dc
HB		 4477 kvm_guest_enter();
4478
42dbaa5a 4479 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4480 set_debugreg(0, 7);
4481 set_debugreg(vcpu->arch.eff_db[0], 0);
4482 set_debugreg(vcpu->arch.eff_db[1], 1);
4483 set_debugreg(vcpu->arch.eff_db[2], 2);
4484 set_debugreg(vcpu->arch.eff_db[3], 3);
4485 }
b6c7a5dc 4486
229456fc 4487 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4488 kvm_x86_ops->run(vcpu);
b6c7a5dc 4489
24f1e32c
FW		 4490 /*
4491 * If the guest has used debug registers, at least dr7
4492 * will be disabled while returning to the host.
4493 * If we don't have active breakpoints in the host, we don't
4494 * care about the messed up debug address registers. But if
4495 * we have some of them active, restore the old state.
4496 */
59d8eb53 4497 if (hw_breakpoint_active())
24f1e32c 4498 hw_breakpoint_restore();
42dbaa5a 4499
32f88400 4500 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4501 local_irq_enable();
4502
4503 ++vcpu->stat.exits;
4504
4505 /*
4506 * We must have an instruction between local_irq_enable() and
4507 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4508 * the interrupt shadow. The stat.exits increment will do nicely.
4509 * But we need to prevent reordering, hence this barrier():
4510 */
4511 barrier();
4512
4513 kvm_guest_exit();
4514
4515 preempt_enable();
4516
f656ce01 4517 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4518
b6c7a5dc
HB		 4519 /*
4520 * Profile KVM exit RIPs:
4521 */
4522 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4523 unsigned long rip = kvm_rip_read(vcpu);
4524 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4525 }
4526
298101da 4527
b93463aa
AK		 4528 kvm_lapic_sync_from_vapic(vcpu);
4529
851ba692 4530 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4531out:
4532 return r;
4533}
b6c7a5dc 4534
09cec754 4535
851ba692 4536static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4537{
4538 int r;
f656ce01 4539 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4540
4541 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4542 pr_debug("vcpu %d received sipi with vector # %x\n",
4543 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4544 kvm_lapic_reset(vcpu);
5f179287 4545 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4546 if (r)
4547 return r;
4548 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4549 }
4550
f656ce01 4551 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4552 vapic_enter(vcpu);
4553
4554 r = 1;
4555 while (r > 0) {
af2152f5 4556 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4557 r = vcpu_enter_guest(vcpu);
d7690175 4558 else {
f656ce01 4559 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4560 kvm_vcpu_block(vcpu);
f656ce01 4561 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4562 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4563 {
4564 switch(vcpu->arch.mp_state) {
4565 case KVM_MP_STATE_HALTED:
d7690175 4566 vcpu->arch.mp_state =
09cec754
GN		 4567 KVM_MP_STATE_RUNNABLE;
4568 case KVM_MP_STATE_RUNNABLE:
4569 break;
4570 case KVM_MP_STATE_SIPI_RECEIVED:
4571 default:
4572 r = -EINTR;
4573 break;
4574 }
4575 }
d7690175
MT		 4576 }
4577
09cec754
GN		 4578 if (r <= 0)
4579 break;
4580
4581 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4582 if (kvm_cpu_has_pending_timer(vcpu))
4583 kvm_inject_pending_timer_irqs(vcpu);
4584
851ba692 4585 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4586 r = -EINTR;
851ba692 4587 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4588 ++vcpu->stat.request_irq_exits;
4589 }
4590 if (signal_pending(current)) {
4591 r = -EINTR;
851ba692 4592 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4593 ++vcpu->stat.signal_exits;
4594 }
4595 if (need_resched()) {
f656ce01 4596 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4597 kvm_resched(vcpu);
f656ce01 4598 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4599 }
b6c7a5dc
HB		 4600 }
4601
f656ce01 4602 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
851ba692 4603 post_kvm_run_save(vcpu);
b6c7a5dc 4604
b93463aa
AK		 4605 vapic_exit(vcpu);
4606
b6c7a5dc
HB		 4607 return r;
4608}
4609
4610int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4611{
4612 int r;
4613 sigset_t sigsaved;
4614
4615 vcpu_load(vcpu);
4616
ac9f6dc0
AK		 4617 if (vcpu->sigset_active)
4618 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4619
a4535290 4620 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4621 kvm_vcpu_block(vcpu);
d7690175 4622 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4623 r = -EAGAIN;
4624 goto out;
b6c7a5dc
HB		 4625 }
4626
b6c7a5dc
HB		 4627 /* re-sync apic's tpr */
4628 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4629 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4630
92bf9748
GN		 4631 if (vcpu->arch.pio.count || vcpu->mmio_needed ||
4632 vcpu->arch.emulate_ctxt.restart) {
4633 if (vcpu->mmio_needed) {
4634 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4635 vcpu->mmio_read_completed = 1;
4636 vcpu->mmio_needed = 0;
b6c7a5dc 4637 }
5cd21917
GN		 4638 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4639 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
4640 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4641 if (r == EMULATE_DO_MMIO) {
4642 r = 0;
4643 goto out;
4644 }
4645 }
5fdbf976
MT		 4646 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4647 kvm_register_write(vcpu, VCPU_REGS_RAX,
4648 kvm_run->hypercall.ret);
b6c7a5dc 4649
851ba692 4650 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4651
4652out:
4653 if (vcpu->sigset_active)
4654 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4655
4656 vcpu_put(vcpu);
4657 return r;
4658}
4659
4660int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4661{
4662 vcpu_load(vcpu);
4663
5fdbf976
MT		 4664 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4665 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4666 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4667 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4668 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4669 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4670 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4671 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4672#ifdef CONFIG_X86_64
5fdbf976
MT		 4673 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4674 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4675 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4676 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4677 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4678 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4679 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4680 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4681#endif
4682
5fdbf976 4683 regs->rip = kvm_rip_read(vcpu);
91586a3b 4684 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4685
4686 vcpu_put(vcpu);
4687
4688 return 0;
4689}
4690
4691int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4692{
4693 vcpu_load(vcpu);
4694
5fdbf976
MT		 4695 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4696 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4697 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4698 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4699 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4700 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4701 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4702 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4703#ifdef CONFIG_X86_64
5fdbf976
MT		 4704 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4705 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4706 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4707 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4708 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4709 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4710 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4711 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4712#endif
4713
5fdbf976 4714 kvm_rip_write(vcpu, regs->rip);
91586a3b 4715 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4716
b4f14abd
JK		 4717 vcpu->arch.exception.pending = false;
4718
b6c7a5dc
HB		 4719 vcpu_put(vcpu);
4720
4721 return 0;
4722}
4723
b6c7a5dc
HB		 4724void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4725{
4726 struct kvm_segment cs;
4727
3e6e0aab 4728 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4729 *db = cs.db;
4730 *l = cs.l;
4731}
4732EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4733
4734int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4735 struct kvm_sregs *sregs)
4736{
89a27f4d 4737 struct desc_ptr dt;
b6c7a5dc
HB		 4738
4739 vcpu_load(vcpu);
4740
3e6e0aab
GT		 4741 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4742 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4743 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4744 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4745 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4746 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4747
3e6e0aab
GT		 4748 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4749 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4750
4751 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4752 sregs->idt.limit = dt.size;
4753 sregs->idt.base = dt.address;
b6c7a5dc 4754 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4755 sregs->gdt.limit = dt.size;
4756 sregs->gdt.base = dt.address;
b6c7a5dc 4757
4d4ec087 4758 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4759 sregs->cr2 = vcpu->arch.cr2;
4760 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4761 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4762 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4763 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4764 sregs->apic_base = kvm_get_apic_base(vcpu);
4765
923c61bb 4766 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4767
36752c9b 4768 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4769 set_bit(vcpu->arch.interrupt.nr,
4770 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4771
b6c7a5dc
HB		 4772 vcpu_put(vcpu);
4773
4774 return 0;
4775}
4776
62d9f0db
MT		 4777int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4778 struct kvm_mp_state *mp_state)
4779{
4780 vcpu_load(vcpu);
4781 mp_state->mp_state = vcpu->arch.mp_state;
4782 vcpu_put(vcpu);
4783 return 0;
4784}
4785
4786int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4787 struct kvm_mp_state *mp_state)
4788{
4789 vcpu_load(vcpu);
4790 vcpu->arch.mp_state = mp_state->mp_state;
4791 vcpu_put(vcpu);
4792 return 0;
4793}
4794
37817f29
IE		 4795int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4796{
ceffb459
GN		 4797 int cs_db, cs_l, ret;
4798 cache_all_regs(vcpu);
37817f29 4799
ceffb459 4800 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
b237ac37 4801
ceffb459
GN		 4802 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4803 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4804 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4805 vcpu->arch.emulate_ctxt.mode =
4806 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4807 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4808 ? X86EMUL_MODE_VM86 : cs_l
4809 ? X86EMUL_MODE_PROT64 : cs_db
4810 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
37817f29 4811
ceffb459
GN		 4812 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
4813 tss_selector, reason);
37817f29 4814
ceffb459
GN		 4815 if (ret == X86EMUL_CONTINUE)
4816 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
37817f29 4817
ceffb459 4818 return (ret != X86EMUL_CONTINUE);
37817f29
IE		 4819}
4820EXPORT_SYMBOL_GPL(kvm_task_switch);
4821
b6c7a5dc
HB		 4822int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4823 struct kvm_sregs *sregs)
4824{
4825 int mmu_reset_needed = 0;
923c61bb 4826 int pending_vec, max_bits;
89a27f4d 4827 struct desc_ptr dt;
b6c7a5dc
HB		 4828
4829 vcpu_load(vcpu);
4830
89a27f4d
GN		 4831 dt.size = sregs->idt.limit;
4832 dt.address = sregs->idt.base;
b6c7a5dc 4833 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 4834 dt.size = sregs->gdt.limit;
4835 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 4836 kvm_x86_ops->set_gdt(vcpu, &dt);
4837
ad312c7c
ZX		 4838 vcpu->arch.cr2 = sregs->cr2;
4839 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4840 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4841
2d3ad1f4 4842 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4843
f6801dff 4844 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 4845 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4846 kvm_set_apic_base(vcpu, sregs->apic_base);
4847
4d4ec087 4848 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 4849 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4850 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4851
fc78f519 4852 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 4853 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 4854 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 4855 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 4856 mmu_reset_needed = 1;
4857 }
b6c7a5dc
HB		 4858
4859 if (mmu_reset_needed)
4860 kvm_mmu_reset_context(vcpu);
4861
923c61bb
GN		 4862 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4863 pending_vec = find_first_bit(
4864 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4865 if (pending_vec < max_bits) {
66fd3f7f 4866 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4867 pr_debug("Set back pending irq %d\n", pending_vec);
4868 if (irqchip_in_kernel(vcpu->kvm))
4869 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4870 }
4871
3e6e0aab
GT		 4872 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4873 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4874 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4875 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4876 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4877 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4878
3e6e0aab
GT		 4879 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4880 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4881
5f0269f5
ME		 4882 update_cr8_intercept(vcpu);
4883
9c3e4aab 4884 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4885 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 4886 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 4887 !is_protmode(vcpu))
9c3e4aab
MT		 4888 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4889
b6c7a5dc
HB		 4890 vcpu_put(vcpu);
4891
4892 return 0;
4893}
4894
d0bfb940
JK		 4895int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4896 struct kvm_guest_debug *dbg)
b6c7a5dc 4897{
355be0b9 4898 unsigned long rflags;
ae675ef0 4899 int i, r;
b6c7a5dc
HB		 4900
4901 vcpu_load(vcpu);
4902
4f926bf2
JK		 4903 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
4904 r = -EBUSY;
4905 if (vcpu->arch.exception.pending)
4906 goto unlock_out;
4907 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4908 kvm_queue_exception(vcpu, DB_VECTOR);
4909 else
4910 kvm_queue_exception(vcpu, BP_VECTOR);
4911 }
4912
91586a3b
JK		 4913 /*
4914 * Read rflags as long as potentially injected trace flags are still
4915 * filtered out.
4916 */
4917 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 4918
4919 vcpu->guest_debug = dbg->control;
4920 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
4921 vcpu->guest_debug = 0;
4922
4923 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 4924 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4925 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4926 vcpu->arch.switch_db_regs =
4927 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4928 } else {
4929 for (i = 0; i < KVM_NR_DB_REGS; i++)
4930 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4931 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4932 }
4933
f92653ee
JK		 4934 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4935 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
4936 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 4937
91586a3b
JK		 4938 /*
4939 * Trigger an rflags update that will inject or remove the trace
4940 * flags.
4941 */
4942 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 4943
355be0b9 4944 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 4945
4f926bf2 4946 r = 0;
d0bfb940 4947
4f926bf2 4948unlock_out:
b6c7a5dc
HB		 4949 vcpu_put(vcpu);
4950
4951 return r;
4952}
4953
d0752060
HB		 4954/*
4955 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4956 * we have asm/x86/processor.h
4957 */
4958struct fxsave {
4959 u16 cwd;
4960 u16 swd;
4961 u16 twd;
4962 u16 fop;
4963 u64 rip;
4964 u64 rdp;
4965 u32 mxcsr;
4966 u32 mxcsr_mask;
4967 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4968#ifdef CONFIG_X86_64
4969 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4970#else
4971 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4972#endif
4973};
4974
8b006791
ZX		 4975/*
4976 * Translate a guest virtual address to a guest physical address.
4977 */
4978int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4979 struct kvm_translation *tr)
4980{
4981 unsigned long vaddr = tr->linear_address;
4982 gpa_t gpa;
f656ce01 4983 int idx;
8b006791
ZX		 4984
4985 vcpu_load(vcpu);
f656ce01 4986 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 4987 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 4988 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 4989 tr->physical_address = gpa;
4990 tr->valid = gpa != UNMAPPED_GVA;
4991 tr->writeable = 1;
4992 tr->usermode = 0;
8b006791
ZX		 4993 vcpu_put(vcpu);
4994
4995 return 0;
4996}
4997
d0752060
HB		 4998int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4999{
ad312c7c 5000 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5001
5002 vcpu_load(vcpu);
5003
5004 memcpy(fpu->fpr, fxsave->st_space, 128);
5005 fpu->fcw = fxsave->cwd;
5006 fpu->fsw = fxsave->swd;
5007 fpu->ftwx = fxsave->twd;
5008 fpu->last_opcode = fxsave->fop;
5009 fpu->last_ip = fxsave->rip;
5010 fpu->last_dp = fxsave->rdp;
5011 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5012
5013 vcpu_put(vcpu);
5014
5015 return 0;
5016}
5017
5018int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5019{
ad312c7c 5020 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5021
5022 vcpu_load(vcpu);
5023
5024 memcpy(fxsave->st_space, fpu->fpr, 128);
5025 fxsave->cwd = fpu->fcw;
5026 fxsave->swd = fpu->fsw;
5027 fxsave->twd = fpu->ftwx;
5028 fxsave->fop = fpu->last_opcode;
5029 fxsave->rip = fpu->last_ip;
5030 fxsave->rdp = fpu->last_dp;
5031 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5032
5033 vcpu_put(vcpu);
5034
5035 return 0;
5036}
5037
5038void fx_init(struct kvm_vcpu *vcpu)
5039{
5040 unsigned after_mxcsr_mask;
5041
bc1a34f1
AA		 5042 /*
5043 * Touch the fpu the first time in non atomic context as if
5044 * this is the first fpu instruction the exception handler
5045 * will fire before the instruction returns and it'll have to
5046 * allocate ram with GFP_KERNEL.
5047 */
5048 if (!used_math())
d6e88aec 5049 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5050
d0752060
HB		 5051 /* Initialize guest FPU by resetting ours and saving into guest's */
5052 preempt_disable();
d6e88aec
AK		 5053 kvm_fx_save(&vcpu->arch.host_fx_image);
5054 kvm_fx_finit();
5055 kvm_fx_save(&vcpu->arch.guest_fx_image);
5056 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5057 preempt_enable();
5058
ad312c7c 5059 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5060 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5061 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5062 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5063 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5064}
5065EXPORT_SYMBOL_GPL(fx_init);
5066
5067void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5068{
2608d7a1 5069 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5070 return;
5071
5072 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5073 kvm_fx_save(&vcpu->arch.host_fx_image);
5074 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5075 trace_kvm_fpu(1);
d0752060 5076}
d0752060
HB		 5077
5078void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5079{
5080 if (!vcpu->guest_fpu_loaded)
5081 return;
5082
5083 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5084 kvm_fx_save(&vcpu->arch.guest_fx_image);
5085 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5086 ++vcpu->stat.fpu_reload;
02daab21 5087 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5088 trace_kvm_fpu(0);
d0752060 5089}
e9b11c17
ZX		 5090
5091void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5092{
7f1ea208
JR		 5093 if (vcpu->arch.time_page) {
5094 kvm_release_page_dirty(vcpu->arch.time_page);
5095 vcpu->arch.time_page = NULL;
5096 }
5097
e9b11c17
ZX		 5098 kvm_x86_ops->vcpu_free(vcpu);
5099}
5100
5101struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5102 unsigned int id)
5103{
26e5215f
AK		 5104 return kvm_x86_ops->vcpu_create(kvm, id);
5105}
e9b11c17 5106
26e5215f
AK		 5107int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5108{
5109 int r;
e9b11c17
ZX		 5110
5111 /* We do fxsave: this must be aligned. */
ad312c7c 5112 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5113
0bed3b56 5114 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5115 vcpu_load(vcpu);
5116 r = kvm_arch_vcpu_reset(vcpu);
5117 if (r == 0)
5118 r = kvm_mmu_setup(vcpu);
5119 vcpu_put(vcpu);
5120 if (r < 0)
5121 goto free_vcpu;
5122
26e5215f 5123 return 0;
e9b11c17
ZX		 5124free_vcpu:
5125 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5126 return r;
e9b11c17
ZX		 5127}
5128
d40ccc62 5129void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5130{
5131 vcpu_load(vcpu);
5132 kvm_mmu_unload(vcpu);
5133 vcpu_put(vcpu);
5134
5135 kvm_x86_ops->vcpu_free(vcpu);
5136}
5137
5138int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5139{
448fa4a9
JK		 5140 vcpu->arch.nmi_pending = false;
5141 vcpu->arch.nmi_injected = false;
5142
42dbaa5a
JK		 5143 vcpu->arch.switch_db_regs = 0;
5144 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5145 vcpu->arch.dr6 = DR6_FIXED_1;
5146 vcpu->arch.dr7 = DR7_FIXED_1;
5147
e9b11c17
ZX		 5148 return kvm_x86_ops->vcpu_reset(vcpu);
5149}
5150
10474ae8 5151int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5152{
0cca7907
ZA		 5153 /*
5154 * Since this may be called from a hotplug notifcation,
5155 * we can't get the CPU frequency directly.
5156 */
5157 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5158 int cpu = raw_smp_processor_id();
5159 per_cpu(cpu_tsc_khz, cpu) = 0;
5160 }
18863bdd
AK		 5161
5162 kvm_shared_msr_cpu_online();
5163
10474ae8 5164 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5165}
5166
5167void kvm_arch_hardware_disable(void *garbage)
5168{
5169 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5170 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5171}
5172
5173int kvm_arch_hardware_setup(void)
5174{
5175 return kvm_x86_ops->hardware_setup();
5176}
5177
5178void kvm_arch_hardware_unsetup(void)
5179{
5180 kvm_x86_ops->hardware_unsetup();
5181}
5182
5183void kvm_arch_check_processor_compat(void *rtn)
5184{
5185 kvm_x86_ops->check_processor_compatibility(rtn);
5186}
5187
5188int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5189{
5190 struct page *page;
5191 struct kvm *kvm;
5192 int r;
5193
5194 BUG_ON(vcpu->kvm == NULL);
5195 kvm = vcpu->kvm;
5196
ad312c7c 5197 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5198 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5199 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5200 else
a4535290 5201 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5202
5203 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5204 if (!page) {
5205 r = -ENOMEM;
5206 goto fail;
5207 }
ad312c7c 5208 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5209
5210 r = kvm_mmu_create(vcpu);
5211 if (r < 0)
5212 goto fail_free_pio_data;
5213
5214 if (irqchip_in_kernel(kvm)) {
5215 r = kvm_create_lapic(vcpu);
5216 if (r < 0)
5217 goto fail_mmu_destroy;
5218 }
5219
890ca9ae
HY		 5220 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5221 GFP_KERNEL);
5222 if (!vcpu->arch.mce_banks) {
5223 r = -ENOMEM;
443c39bc 5224 goto fail_free_lapic;
890ca9ae
HY		 5225 }
5226 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5227
e9b11c17 5228 return 0;
443c39bc
WY		 5229fail_free_lapic:
5230 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5231fail_mmu_destroy:
5232 kvm_mmu_destroy(vcpu);
5233fail_free_pio_data:
ad312c7c 5234 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5235fail:
5236 return r;
5237}
5238
5239void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5240{
f656ce01
MT		 5241 int idx;
5242
36cb93fd 5243 kfree(vcpu->arch.mce_banks);
e9b11c17 5244 kvm_free_lapic(vcpu);
f656ce01 5245 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5246 kvm_mmu_destroy(vcpu);
f656ce01 5247 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5248 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5249}
d19a9cd2
ZX		 5250
5251struct kvm *kvm_arch_create_vm(void)
5252{
5253 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5254
5255 if (!kvm)
5256 return ERR_PTR(-ENOMEM);
5257
fef9cce0
MT		 5258 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5259 if (!kvm->arch.aliases) {
5260 kfree(kvm);
5261 return ERR_PTR(-ENOMEM);
5262 }
5263
f05e70ac 5264 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5265 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5266
5550af4d
SY		 5267 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5268 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5269
53f658b3
MT		 5270 rdtscll(kvm->arch.vm_init_tsc);
5271
d19a9cd2
ZX		 5272 return kvm;
5273}
5274
5275static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5276{
5277 vcpu_load(vcpu);
5278 kvm_mmu_unload(vcpu);
5279 vcpu_put(vcpu);
5280}
5281
5282static void kvm_free_vcpus(struct kvm *kvm)
5283{
5284 unsigned int i;
988a2cae 5285 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5286
5287 /*
5288 * Unpin any mmu pages first.
5289 */
988a2cae
GN		 5290 kvm_for_each_vcpu(i, vcpu, kvm)
5291 kvm_unload_vcpu_mmu(vcpu);
5292 kvm_for_each_vcpu(i, vcpu, kvm)
5293 kvm_arch_vcpu_free(vcpu);
5294
5295 mutex_lock(&kvm->lock);
5296 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5297 kvm->vcpus[i] = NULL;
d19a9cd2 5298
988a2cae
GN		 5299 atomic_set(&kvm->online_vcpus, 0);
5300 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5301}
5302
ad8ba2cd
SY		 5303void kvm_arch_sync_events(struct kvm *kvm)
5304{
ba4cef31 5305 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5306}
5307
d19a9cd2
ZX		 5308void kvm_arch_destroy_vm(struct kvm *kvm)
5309{
6eb55818 5310 kvm_iommu_unmap_guest(kvm);
7837699f 5311 kvm_free_pit(kvm);
d7deeeb0
ZX		 5312 kfree(kvm->arch.vpic);
5313 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5314 kvm_free_vcpus(kvm);
5315 kvm_free_physmem(kvm);
3d45830c
AK		 5316 if (kvm->arch.apic_access_page)
5317 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5318 if (kvm->arch.ept_identity_pagetable)
5319 put_page(kvm->arch.ept_identity_pagetable);
64749204 5320 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5321 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5322 kfree(kvm);
5323}
0de10343 5324
f7784b8e
MT		 5325int kvm_arch_prepare_memory_region(struct kvm *kvm,
5326 struct kvm_memory_slot *memslot,
0de10343 5327 struct kvm_memory_slot old,
f7784b8e 5328 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5329 int user_alloc)
5330{
f7784b8e 5331 int npages = memslot->npages;
0de10343
ZX		 5332
5333 /*To keep backward compatibility with older userspace,
5334 *x86 needs to hanlde !user_alloc case.
5335 */
5336 if (!user_alloc) {
5337 if (npages && !old.rmap) {
604b38ac
AA		 5338 unsigned long userspace_addr;
5339
72dc67a6 5340 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5341 userspace_addr = do_mmap(NULL, 0,
5342 npages * PAGE_SIZE,
5343 PROT_READ | PROT_WRITE,
acee3c04 5344 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5345 0);
72dc67a6 5346 up_write(&current->mm->mmap_sem);
0de10343 5347
604b38ac
AA		 5348 if (IS_ERR((void *)userspace_addr))
5349 return PTR_ERR((void *)userspace_addr);
5350
604b38ac 5351 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5352 }
5353 }
5354
f7784b8e
MT		 5355
5356 return 0;
5357}
5358
5359void kvm_arch_commit_memory_region(struct kvm *kvm,
5360 struct kvm_userspace_memory_region *mem,
5361 struct kvm_memory_slot old,
5362 int user_alloc)
5363{
5364
5365 int npages = mem->memory_size >> PAGE_SHIFT;
5366
5367 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5368 int ret;
5369
5370 down_write(&current->mm->mmap_sem);
5371 ret = do_munmap(current->mm, old.userspace_addr,
5372 old.npages * PAGE_SIZE);
5373 up_write(&current->mm->mmap_sem);
5374 if (ret < 0)
5375 printk(KERN_WARNING
5376 "kvm_vm_ioctl_set_memory_region: "
5377 "failed to munmap memory\n");
5378 }
5379
7c8a83b7 5380 spin_lock(&kvm->mmu_lock);
f05e70ac 5381 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5382 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5383 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5384 }
5385
5386 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5387 spin_unlock(&kvm->mmu_lock);
0de10343 5388}
1d737c8a 5389
34d4cb8f
MT		 5390void kvm_arch_flush_shadow(struct kvm *kvm)
5391{
5392 kvm_mmu_zap_all(kvm);
8986ecc0 5393 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5394}
5395
1d737c8a
ZX		 5396int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5397{
a4535290 5398 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5399 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5400 || vcpu->arch.nmi_pending ||
5401 (kvm_arch_interrupt_allowed(vcpu) &&
5402 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5403}
5736199a 5404
5736199a
ZX		 5405void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5406{
32f88400
MT		 5407 int me;
5408 int cpu = vcpu->cpu;
5736199a
ZX		 5409
5410 if (waitqueue_active(&vcpu->wq)) {
5411 wake_up_interruptible(&vcpu->wq);
5412 ++vcpu->stat.halt_wakeup;
5413 }
32f88400
MT		 5414
5415 me = get_cpu();
5416 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5417 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5418 smp_send_reschedule(cpu);
e9571ed5 5419 put_cpu();
5736199a 5420}
78646121
GN		 5421
5422int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5423{
5424 return kvm_x86_ops->interrupt_allowed(vcpu);
5425}
229456fc 5426
f92653ee
JK		 5427bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5428{
5429 unsigned long current_rip = kvm_rip_read(vcpu) +
5430 get_segment_base(vcpu, VCPU_SREG_CS);
5431
5432 return current_rip == linear_rip;
5433}
5434EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5435
94fe45da
JK		 5436unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5437{
5438 unsigned long rflags;
5439
5440 rflags = kvm_x86_ops->get_rflags(vcpu);
5441 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5442 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5443 return rflags;
5444}
5445EXPORT_SYMBOL_GPL(kvm_get_rflags);
5446
5447void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5448{
5449 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5450 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5451 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5452 kvm_x86_ops->set_rflags(vcpu, rflags);
5453}
5454EXPORT_SYMBOL_GPL(kvm_set_rflags);
5455
229456fc
MT		 5456EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5457EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5458EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5459EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5460EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5461EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5462EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5463EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5464EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5465EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5466EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5467EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux 6.x block layer and io_uring tree(s)