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KVM: nSVM: propagate the NPF EXITINFO to the guest
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
92a1f12d
JR		 101bool kvm_has_tsc_control;
102EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
103u32 kvm_max_guest_tsc_khz;
104EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
105
cc578287
ZA		 106/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
107static u32 tsc_tolerance_ppm = 250;
108module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
109
16a96021
MT		 110static bool backwards_tsc_observed = false;
111
18863bdd
AK		 112#define KVM_NR_SHARED_MSRS 16
113
114struct kvm_shared_msrs_global {
115 int nr;
2bf78fa7 116 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 117};
118
119struct kvm_shared_msrs {
120 struct user_return_notifier urn;
121 bool registered;
2bf78fa7
SY		 122 struct kvm_shared_msr_values {
123 u64 host;
124 u64 curr;
125 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 126};
127
128static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 129static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 130
417bc304 131struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 132 { "pf_fixed", VCPU_STAT(pf_fixed) },
133 { "pf_guest", VCPU_STAT(pf_guest) },
134 { "tlb_flush", VCPU_STAT(tlb_flush) },
135 { "invlpg", VCPU_STAT(invlpg) },
136 { "exits", VCPU_STAT(exits) },
137 { "io_exits", VCPU_STAT(io_exits) },
138 { "mmio_exits", VCPU_STAT(mmio_exits) },
139 { "signal_exits", VCPU_STAT(signal_exits) },
140 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 141 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 142 { "halt_exits", VCPU_STAT(halt_exits) },
143 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 144 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 145 { "request_irq", VCPU_STAT(request_irq_exits) },
146 { "irq_exits", VCPU_STAT(irq_exits) },
147 { "host_state_reload", VCPU_STAT(host_state_reload) },
148 { "efer_reload", VCPU_STAT(efer_reload) },
149 { "fpu_reload", VCPU_STAT(fpu_reload) },
150 { "insn_emulation", VCPU_STAT(insn_emulation) },
151 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 152 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 153 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 154 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
155 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
156 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
157 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
158 { "mmu_flooded", VM_STAT(mmu_flooded) },
159 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 160 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 161 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 162 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 163 { "largepages", VM_STAT(lpages) },
417bc304
HB		 164 { NULL }
165};
166
2acf923e
DC		 167u64 __read_mostly host_xcr0;
168
b6785def 169static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 170
af585b92
GN		 171static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
172{
173 int i;
174 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
175 vcpu->arch.apf.gfns[i] = ~0;
176}
177
18863bdd
AK		 178static void kvm_on_user_return(struct user_return_notifier *urn)
179{
180 unsigned slot;
18863bdd
AK		 181 struct kvm_shared_msrs *locals
182 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 183 struct kvm_shared_msr_values *values;
18863bdd
AK		 184
185 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 186 values = &locals->values[slot];
187 if (values->host != values->curr) {
188 wrmsrl(shared_msrs_global.msrs[slot], values->host);
189 values->curr = values->host;
18863bdd
AK		 190 }
191 }
192 locals->registered = false;
193 user_return_notifier_unregister(urn);
194}
195
2bf78fa7 196static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 197{
18863bdd 198 u64 value;
013f6a5d
MT		 199 unsigned int cpu = smp_processor_id();
200 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 201
2bf78fa7
SY		 202 /* only read, and nobody should modify it at this time,
203 * so don't need lock */
204 if (slot >= shared_msrs_global.nr) {
205 printk(KERN_ERR "kvm: invalid MSR slot!");
206 return;
207 }
208 rdmsrl_safe(msr, &value);
209 smsr->values[slot].host = value;
210 smsr->values[slot].curr = value;
211}
212
213void kvm_define_shared_msr(unsigned slot, u32 msr)
214{
0123be42 215 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 216 if (slot >= shared_msrs_global.nr)
217 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 218 shared_msrs_global.msrs[slot] = msr;
219 /* we need ensured the shared_msr_global have been updated */
220 smp_wmb();
18863bdd
AK		 221}
222EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
223
224static void kvm_shared_msr_cpu_online(void)
225{
226 unsigned i;
18863bdd
AK		 227
228 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 229 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 230}
231
d5696725 232void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 233{
013f6a5d
MT		 234 unsigned int cpu = smp_processor_id();
235 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 236
2bf78fa7 237 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 238 return;
2bf78fa7
SY		 239 smsr->values[slot].curr = value;
240 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 241 if (!smsr->registered) {
242 smsr->urn.on_user_return = kvm_on_user_return;
243 user_return_notifier_register(&smsr->urn);
244 smsr->registered = true;
245 }
246}
247EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
248
13a34e06 249static void drop_user_return_notifiers(void)
3548bab5 250{
013f6a5d
MT		 251 unsigned int cpu = smp_processor_id();
252 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 253
254 if (smsr->registered)
255 kvm_on_user_return(&smsr->urn);
256}
257
6866b83e
CO		 258u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
259{
8a5a87d9 260 return vcpu->arch.apic_base;
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_get_apic_base);
263
58cb628d
JK		 264int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
265{
266 u64 old_state = vcpu->arch.apic_base &
267 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
268 u64 new_state = msr_info->data &
269 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
270 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
271 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
272
273 if (!msr_info->host_initiated &&
274 ((msr_info->data & reserved_bits) != 0 ||
275 new_state == X2APIC_ENABLE ||
276 (new_state == MSR_IA32_APICBASE_ENABLE &&
277 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
278 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
279 old_state == 0)))
280 return 1;
281
282 kvm_lapic_set_base(vcpu, msr_info->data);
283 return 0;
6866b83e
CO		 284}
285EXPORT_SYMBOL_GPL(kvm_set_apic_base);
286
2605fc21 287asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 288{
289 /* Fault while not rebooting. We want the trace. */
290 BUG();
291}
292EXPORT_SYMBOL_GPL(kvm_spurious_fault);
293
3fd28fce
ED		 294#define EXCPT_BENIGN 0
295#define EXCPT_CONTRIBUTORY 1
296#define EXCPT_PF 2
297
298static int exception_class(int vector)
299{
300 switch (vector) {
301 case PF_VECTOR:
302 return EXCPT_PF;
303 case DE_VECTOR:
304 case TS_VECTOR:
305 case NP_VECTOR:
306 case SS_VECTOR:
307 case GP_VECTOR:
308 return EXCPT_CONTRIBUTORY;
309 default:
310 break;
311 }
312 return EXCPT_BENIGN;
313}
314
d6e8c854
NA		 315#define EXCPT_FAULT 0
316#define EXCPT_TRAP 1
317#define EXCPT_ABORT 2
318#define EXCPT_INTERRUPT 3
319
320static int exception_type(int vector)
321{
322 unsigned int mask;
323
324 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
325 return EXCPT_INTERRUPT;
326
327 mask = 1 << vector;
328
329 /* #DB is trap, as instruction watchpoints are handled elsewhere */
330 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
331 return EXCPT_TRAP;
332
333 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
334 return EXCPT_ABORT;
335
336 /* Reserved exceptions will result in fault */
337 return EXCPT_FAULT;
338}
339
3fd28fce 340static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 341 unsigned nr, bool has_error, u32 error_code,
342 bool reinject)
3fd28fce
ED		 343{
344 u32 prev_nr;
345 int class1, class2;
346
3842d135
AK		 347 kvm_make_request(KVM_REQ_EVENT, vcpu);
348
3fd28fce
ED		 349 if (!vcpu->arch.exception.pending) {
350 queue:
351 vcpu->arch.exception.pending = true;
352 vcpu->arch.exception.has_error_code = has_error;
353 vcpu->arch.exception.nr = nr;
354 vcpu->arch.exception.error_code = error_code;
3f0fd292 355 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 356 return;
357 }
358
359 /* to check exception */
360 prev_nr = vcpu->arch.exception.nr;
361 if (prev_nr == DF_VECTOR) {
362 /* triple fault -> shutdown */
a8eeb04a 363 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 364 return;
365 }
366 class1 = exception_class(prev_nr);
367 class2 = exception_class(nr);
368 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
369 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
370 /* generate double fault per SDM Table 5-5 */
371 vcpu->arch.exception.pending = true;
372 vcpu->arch.exception.has_error_code = true;
373 vcpu->arch.exception.nr = DF_VECTOR;
374 vcpu->arch.exception.error_code = 0;
375 } else
376 /* replace previous exception with a new one in a hope
377 that instruction re-execution will regenerate lost
378 exception */
379 goto queue;
380}
381
298101da
AK		 382void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
383{
ce7ddec4 384 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 385}
386EXPORT_SYMBOL_GPL(kvm_queue_exception);
387
ce7ddec4
JR		 388void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
389{
390 kvm_multiple_exception(vcpu, nr, false, 0, true);
391}
392EXPORT_SYMBOL_GPL(kvm_requeue_exception);
393
db8fcefa 394void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 395{
db8fcefa
AP		 396 if (err)
397 kvm_inject_gp(vcpu, 0);
398 else
399 kvm_x86_ops->skip_emulated_instruction(vcpu);
400}
401EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 402
6389ee94 403void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 404{
405 ++vcpu->stat.pf_guest;
6389ee94
AK		 406 vcpu->arch.cr2 = fault->address;
407 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 408}
27d6c865 409EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 410
6389ee94 411void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 412{
6389ee94
AK		 413 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
414 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 415 else
6389ee94 416 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 417}
418
3419ffc8
SY		 419void kvm_inject_nmi(struct kvm_vcpu *vcpu)
420{
7460fb4a
AK		 421 atomic_inc(&vcpu->arch.nmi_queued);
422 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 423}
424EXPORT_SYMBOL_GPL(kvm_inject_nmi);
425
298101da
AK		 426void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
427{
ce7ddec4 428 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 429}
430EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
431
ce7ddec4
JR		 432void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
433{
434 kvm_multiple_exception(vcpu, nr, true, error_code, true);
435}
436EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
437
0a79b009
AK		 438/*
439 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
440 * a #GP and return false.
441 */
442bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 443{
0a79b009
AK		 444 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
445 return true;
446 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
447 return false;
298101da 448}
0a79b009 449EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 450
ec92fe44
JR		 451/*
452 * This function will be used to read from the physical memory of the currently
453 * running guest. The difference to kvm_read_guest_page is that this function
454 * can read from guest physical or from the guest's guest physical memory.
455 */
456int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
457 gfn_t ngfn, void *data, int offset, int len,
458 u32 access)
459{
460 gfn_t real_gfn;
461 gpa_t ngpa;
462
463 ngpa = gfn_to_gpa(ngfn);
464 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
465 if (real_gfn == UNMAPPED_GVA)
466 return -EFAULT;
467
468 real_gfn = gpa_to_gfn(real_gfn);
469
470 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
471}
472EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
473
3d06b8bf
JR		 474int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
475 void *data, int offset, int len, u32 access)
476{
477 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
478 data, offset, len, access);
479}
480
a03490ed
CO		 481/*
482 * Load the pae pdptrs. Return true is they are all valid.
483 */
ff03a073 484int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 485{
486 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
487 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
488 int i;
489 int ret;
ff03a073 490 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 491
ff03a073
JR		 492 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
493 offset * sizeof(u64), sizeof(pdpte),
494 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 495 if (ret < 0) {
496 ret = 0;
497 goto out;
498 }
499 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 500 if (is_present_gpte(pdpte[i]) &&
20c466b5 501 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 502 ret = 0;
503 goto out;
504 }
505 }
506 ret = 1;
507
ff03a073 508 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 509 __set_bit(VCPU_EXREG_PDPTR,
510 (unsigned long *)&vcpu->arch.regs_avail);
511 __set_bit(VCPU_EXREG_PDPTR,
512 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 513out:
a03490ed
CO		 514
515 return ret;
516}
cc4b6871 517EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 518
d835dfec
AK		 519static bool pdptrs_changed(struct kvm_vcpu *vcpu)
520{
ff03a073 521 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 522 bool changed = true;
3d06b8bf
JR		 523 int offset;
524 gfn_t gfn;
d835dfec
AK		 525 int r;
526
527 if (is_long_mode(vcpu) || !is_pae(vcpu))
528 return false;
529
6de4f3ad
AK		 530 if (!test_bit(VCPU_EXREG_PDPTR,
531 (unsigned long *)&vcpu->arch.regs_avail))
532 return true;
533
9f8fe504
AK		 534 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
535 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 536 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
537 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 538 if (r < 0)
539 goto out;
ff03a073 540 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 541out:
d835dfec
AK		 542
543 return changed;
544}
545
49a9b07e 546int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 547{
aad82703
SY		 548 unsigned long old_cr0 = kvm_read_cr0(vcpu);
549 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
550 X86_CR0_CD | X86_CR0_NW;
551
f9a48e6a
AK		 552 cr0 |= X86_CR0_ET;
553
ab344828 554#ifdef CONFIG_X86_64
0f12244f
GN		 555 if (cr0 & 0xffffffff00000000UL)
556 return 1;
ab344828
GN		 557#endif
558
559 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 560
0f12244f
GN		 561 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
562 return 1;
a03490ed 563
0f12244f
GN		 564 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
565 return 1;
a03490ed
CO		 566
567 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
568#ifdef CONFIG_X86_64
f6801dff 569 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 570 int cs_db, cs_l;
571
0f12244f
GN		 572 if (!is_pae(vcpu))
573 return 1;
a03490ed 574 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 575 if (cs_l)
576 return 1;
a03490ed
CO		 577 } else
578#endif
ff03a073 579 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 580 kvm_read_cr3(vcpu)))
0f12244f 581 return 1;
a03490ed
CO		 582 }
583
ad756a16
MJ		 584 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
585 return 1;
586
a03490ed 587 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 588
d170c419 589 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 590 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 591 kvm_async_pf_hash_reset(vcpu);
592 }
e5f3f027 593
aad82703
SY		 594 if ((cr0 ^ old_cr0) & update_bits)
595 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 596 return 0;
597}
2d3ad1f4 598EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 599
2d3ad1f4 600void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 601{
49a9b07e 602 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 603}
2d3ad1f4 604EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 605
42bdf991
MT		 606static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
607{
608 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
609 !vcpu->guest_xcr0_loaded) {
610 /* kvm_set_xcr() also depends on this */
611 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
612 vcpu->guest_xcr0_loaded = 1;
613 }
614}
615
616static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
617{
618 if (vcpu->guest_xcr0_loaded) {
619 if (vcpu->arch.xcr0 != host_xcr0)
620 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
621 vcpu->guest_xcr0_loaded = 0;
622 }
623}
624
2acf923e
DC		 625int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
626{
56c103ec
LJ		 627 u64 xcr0 = xcr;
628 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 629 u64 valid_bits;
2acf923e
DC		 630
631 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
632 if (index != XCR_XFEATURE_ENABLED_MASK)
633 return 1;
2acf923e
DC		 634 if (!(xcr0 & XSTATE_FP))
635 return 1;
636 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
637 return 1;
46c34cb0
PB		 638
639 /*
640 * Do not allow the guest to set bits that we do not support
641 * saving. However, xcr0 bit 0 is always set, even if the
642 * emulated CPU does not support XSAVE (see fx_init).
643 */
644 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
645 if (xcr0 & ~valid_bits)
2acf923e 646 return 1;
46c34cb0 647
390bd528
LJ		 648 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
649 return 1;
650
42bdf991 651 kvm_put_guest_xcr0(vcpu);
2acf923e 652 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 653
654 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
655 kvm_update_cpuid(vcpu);
2acf923e
DC		 656 return 0;
657}
658
659int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
660{
764bcbc5
Z		 661 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
662 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 663 kvm_inject_gp(vcpu, 0);
664 return 1;
665 }
666 return 0;
667}
668EXPORT_SYMBOL_GPL(kvm_set_xcr);
669
a83b29c6 670int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 671{
fc78f519 672 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 673 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
674 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 675 if (cr4 & CR4_RESERVED_BITS)
676 return 1;
a03490ed 677
2acf923e
DC		 678 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
679 return 1;
680
c68b734f
YW		 681 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
682 return 1;
683
97ec8c06
FW		 684 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
685 return 1;
686
afcbf13f 687 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 688 return 1;
689
a03490ed 690 if (is_long_mode(vcpu)) {
0f12244f
GN		 691 if (!(cr4 & X86_CR4_PAE))
692 return 1;
a2edf57f
AK		 693 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
694 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 695 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
696 kvm_read_cr3(vcpu)))
0f12244f
GN		 697 return 1;
698
ad756a16
MJ		 699 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
700 if (!guest_cpuid_has_pcid(vcpu))
701 return 1;
702
703 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
704 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
705 return 1;
706 }
707
5e1746d6 708 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 709 return 1;
a03490ed 710
ad756a16
MJ		 711 if (((cr4 ^ old_cr4) & pdptr_bits) ||
712 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 713 kvm_mmu_reset_context(vcpu);
0f12244f 714
97ec8c06
FW		 715 if ((cr4 ^ old_cr4) & X86_CR4_SMAP)
716 update_permission_bitmask(vcpu, vcpu->arch.walk_mmu, false);
717
2acf923e 718 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 719 kvm_update_cpuid(vcpu);
2acf923e 720
0f12244f
GN		 721 return 0;
722}
2d3ad1f4 723EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 724
2390218b 725int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 726{
9f8fe504 727 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 728 kvm_mmu_sync_roots(vcpu);
d835dfec 729 kvm_mmu_flush_tlb(vcpu);
0f12244f 730 return 0;
d835dfec
AK		 731 }
732
a03490ed 733 if (is_long_mode(vcpu)) {
d9f89b88
JK		 734 if (cr3 & CR3_L_MODE_RESERVED_BITS)
735 return 1;
736 } else if (is_pae(vcpu) && is_paging(vcpu) &&
737 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 738 return 1;
a03490ed 739
0f12244f 740 vcpu->arch.cr3 = cr3;
aff48baa 741 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 742 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 743 return 0;
744}
2d3ad1f4 745EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 746
eea1cff9 747int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 748{
0f12244f
GN		 749 if (cr8 & CR8_RESERVED_BITS)
750 return 1;
a03490ed
CO		 751 if (irqchip_in_kernel(vcpu->kvm))
752 kvm_lapic_set_tpr(vcpu, cr8);
753 else
ad312c7c 754 vcpu->arch.cr8 = cr8;
0f12244f
GN		 755 return 0;
756}
2d3ad1f4 757EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 758
2d3ad1f4 759unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 760{
761 if (irqchip_in_kernel(vcpu->kvm))
762 return kvm_lapic_get_cr8(vcpu);
763 else
ad312c7c 764 return vcpu->arch.cr8;
a03490ed 765}
2d3ad1f4 766EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 767
73aaf249
JK		 768static void kvm_update_dr6(struct kvm_vcpu *vcpu)
769{
770 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
771 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
772}
773
c8639010
JK		 774static void kvm_update_dr7(struct kvm_vcpu *vcpu)
775{
776 unsigned long dr7;
777
778 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
779 dr7 = vcpu->arch.guest_debug_dr7;
780 else
781 dr7 = vcpu->arch.dr7;
782 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 783 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
784 if (dr7 & DR7_BP_EN_MASK)
785 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 786}
787
6f43ed01
NA		 788static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
789{
790 u64 fixed = DR6_FIXED_1;
791
792 if (!guest_cpuid_has_rtm(vcpu))
793 fixed |= DR6_RTM;
794 return fixed;
795}
796
338dbc97 797static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 798{
799 switch (dr) {
800 case 0 ... 3:
801 vcpu->arch.db[dr] = val;
802 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
803 vcpu->arch.eff_db[dr] = val;
804 break;
805 case 4:
338dbc97
GN		 806 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
807 return 1; /* #UD */
020df079
GN		 808 /* fall through */
809 case 6:
338dbc97
GN		 810 if (val & 0xffffffff00000000ULL)
811 return -1; /* #GP */
6f43ed01 812 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 813 kvm_update_dr6(vcpu);
020df079
GN		 814 break;
815 case 5:
338dbc97
GN		 816 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
817 return 1; /* #UD */
020df079
GN		 818 /* fall through */
819 default: /* 7 */
338dbc97
GN		 820 if (val & 0xffffffff00000000ULL)
821 return -1; /* #GP */
020df079 822 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 823 kvm_update_dr7(vcpu);
020df079
GN		 824 break;
825 }
826
827 return 0;
828}
338dbc97
GN		 829
830int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
831{
832 int res;
833
834 res = __kvm_set_dr(vcpu, dr, val);
835 if (res > 0)
836 kvm_queue_exception(vcpu, UD_VECTOR);
837 else if (res < 0)
838 kvm_inject_gp(vcpu, 0);
839
840 return res;
841}
020df079
GN		 842EXPORT_SYMBOL_GPL(kvm_set_dr);
843
338dbc97 844static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 845{
846 switch (dr) {
847 case 0 ... 3:
848 *val = vcpu->arch.db[dr];
849 break;
850 case 4:
338dbc97 851 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 852 return 1;
020df079
GN		 853 /* fall through */
854 case 6:
73aaf249
JK		 855 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
856 *val = vcpu->arch.dr6;
857 else
858 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 859 break;
860 case 5:
338dbc97 861 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 862 return 1;
020df079
GN		 863 /* fall through */
864 default: /* 7 */
865 *val = vcpu->arch.dr7;
866 break;
867 }
868
869 return 0;
870}
338dbc97
GN		 871
872int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
873{
874 if (_kvm_get_dr(vcpu, dr, val)) {
875 kvm_queue_exception(vcpu, UD_VECTOR);
876 return 1;
877 }
878 return 0;
879}
020df079
GN		 880EXPORT_SYMBOL_GPL(kvm_get_dr);
881
022cd0e8
AK		 882bool kvm_rdpmc(struct kvm_vcpu *vcpu)
883{
884 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
885 u64 data;
886 int err;
887
888 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
889 if (err)
890 return err;
891 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
892 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
893 return err;
894}
895EXPORT_SYMBOL_GPL(kvm_rdpmc);
896
043405e1
CO		 897/*
898 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
899 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
900 *
901 * This list is modified at module load time to reflect the
e3267cbb
GC		 902 * capabilities of the host cpu. This capabilities test skips MSRs that are
903 * kvm-specific. Those are put in the beginning of the list.
043405e1 904 */
e3267cbb 905
e984097b 906#define KVM_SAVE_MSRS_BEGIN 12
043405e1 907static u32 msrs_to_save[] = {
e3267cbb 908 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 909 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 910 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 911 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 912 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 913 MSR_KVM_PV_EOI_EN,
043405e1 914 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 915 MSR_STAR,
043405e1
CO		 916#ifdef CONFIG_X86_64
917 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
918#endif
b3897a49 919 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 920 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 921};
922
923static unsigned num_msrs_to_save;
924
f1d24831 925static const u32 emulated_msrs[] = {
ba904635 926 MSR_IA32_TSC_ADJUST,
a3e06bbe 927 MSR_IA32_TSCDEADLINE,
043405e1 928 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 929 MSR_IA32_MCG_STATUS,
930 MSR_IA32_MCG_CTL,
043405e1
CO		 931};
932
384bb783 933bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 934{
b69e8cae 935 if (efer & efer_reserved_bits)
384bb783 936 return false;
15c4a640 937
1b2fd70c
AG		 938 if (efer & EFER_FFXSR) {
939 struct kvm_cpuid_entry2 *feat;
940
941 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 942 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 943 return false;
1b2fd70c
AG		 944 }
945
d8017474
AG		 946 if (efer & EFER_SVME) {
947 struct kvm_cpuid_entry2 *feat;
948
949 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 950 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 951 return false;
d8017474
AG		 952 }
953
384bb783
JK		 954 return true;
955}
956EXPORT_SYMBOL_GPL(kvm_valid_efer);
957
958static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
959{
960 u64 old_efer = vcpu->arch.efer;
961
962 if (!kvm_valid_efer(vcpu, efer))
963 return 1;
964
965 if (is_paging(vcpu)
966 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
967 return 1;
968
15c4a640 969 efer &= ~EFER_LMA;
f6801dff 970 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 971
a3d204e2
SY		 972 kvm_x86_ops->set_efer(vcpu, efer);
973
aad82703
SY		 974 /* Update reserved bits */
975 if ((efer ^ old_efer) & EFER_NX)
976 kvm_mmu_reset_context(vcpu);
977
b69e8cae 978 return 0;
15c4a640
CO		 979}
980
f2b4b7dd
JR		 981void kvm_enable_efer_bits(u64 mask)
982{
983 efer_reserved_bits &= ~mask;
984}
985EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
986
987
15c4a640
CO		 988/*
989 * Writes msr value into into the appropriate "register".
990 * Returns 0 on success, non-0 otherwise.
991 * Assumes vcpu_load() was already called.
992 */
8fe8ab46 993int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 994{
8fe8ab46 995 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 996}
997
313a3dc7
CO		 998/*
999 * Adapt set_msr() to msr_io()'s calling convention
1000 */
1001static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1002{
8fe8ab46
WA		 1003 struct msr_data msr;
1004
1005 msr.data = *data;
1006 msr.index = index;
1007 msr.host_initiated = true;
1008 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1009}
1010
16e8d74d
MT		 1011#ifdef CONFIG_X86_64
1012struct pvclock_gtod_data {
1013 seqcount_t seq;
1014
1015 struct { /* extract of a clocksource struct */
1016 int vclock_mode;
1017 cycle_t cycle_last;
1018 cycle_t mask;
1019 u32 mult;
1020 u32 shift;
1021 } clock;
1022
cbcf2dd3
TG		 1023 u64 boot_ns;
1024 u64 nsec_base;
16e8d74d
MT		 1025};
1026
1027static struct pvclock_gtod_data pvclock_gtod_data;
1028
1029static void update_pvclock_gtod(struct timekeeper *tk)
1030{
1031 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1032 u64 boot_ns;
1033
d28ede83 1034 boot_ns = ktime_to_ns(ktime_add(tk->tkr.base_mono, tk->offs_boot));
16e8d74d
MT		 1035
1036 write_seqcount_begin(&vdata->seq);
1037
1038 /* copy pvclock gtod data */
d28ede83
TG		 1039 vdata->clock.vclock_mode = tk->tkr.clock->archdata.vclock_mode;
1040 vdata->clock.cycle_last = tk->tkr.cycle_last;
1041 vdata->clock.mask = tk->tkr.mask;
1042 vdata->clock.mult = tk->tkr.mult;
1043 vdata->clock.shift = tk->tkr.shift;
16e8d74d 1044
cbcf2dd3 1045 vdata->boot_ns = boot_ns;
d28ede83 1046 vdata->nsec_base = tk->tkr.xtime_nsec;
16e8d74d
MT		 1047
1048 write_seqcount_end(&vdata->seq);
1049}
1050#endif
1051
1052
18068523
GOC		 1053static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1054{
9ed3c444
AK		 1055 int version;
1056 int r;
50d0a0f9 1057 struct pvclock_wall_clock wc;
923de3cf 1058 struct timespec boot;
18068523
GOC		 1059
1060 if (!wall_clock)
1061 return;
1062
9ed3c444
AK		 1063 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1064 if (r)
1065 return;
1066
1067 if (version & 1)
1068 ++version; /* first time write, random junk */
1069
1070 ++version;
18068523 1071
18068523
GOC		 1072 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1073
50d0a0f9
GH		 1074 /*
1075 * The guest calculates current wall clock time by adding
34c238a1 1076 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1077 * wall clock specified here. guest system time equals host
1078 * system time for us, thus we must fill in host boot time here.
1079 */
923de3cf 1080 getboottime(&boot);
50d0a0f9 1081
4b648665
BR		 1082 if (kvm->arch.kvmclock_offset) {
1083 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1084 boot = timespec_sub(boot, ts);
1085 }
50d0a0f9
GH		 1086 wc.sec = boot.tv_sec;
1087 wc.nsec = boot.tv_nsec;
1088 wc.version = version;
18068523
GOC		 1089
1090 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1091
1092 version++;
1093 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1094}
1095
50d0a0f9
GH		 1096static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1097{
1098 uint32_t quotient, remainder;
1099
1100 /* Don't try to replace with do_div(), this one calculates
1101 * "(dividend << 32) / divisor" */
1102 __asm__ ( "divl %4"
1103 : "=a" (quotient), "=d" (remainder)
1104 : "0" (0), "1" (dividend), "r" (divisor) );
1105 return quotient;
1106}
1107
5f4e3f88
ZA		 1108static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1109 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1110{
5f4e3f88 1111 uint64_t scaled64;
50d0a0f9
GH		 1112 int32_t shift = 0;
1113 uint64_t tps64;
1114 uint32_t tps32;
1115
5f4e3f88
ZA		 1116 tps64 = base_khz * 1000LL;
1117 scaled64 = scaled_khz * 1000LL;
50933623 1118 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1119 tps64 >>= 1;
1120 shift--;
1121 }
1122
1123 tps32 = (uint32_t)tps64;
50933623
JK		 1124 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1125 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1126 scaled64 >>= 1;
1127 else
1128 tps32 <<= 1;
50d0a0f9
GH		 1129 shift++;
1130 }
1131
5f4e3f88
ZA		 1132 *pshift = shift;
1133 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1134
5f4e3f88
ZA		 1135 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1136 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1137}
1138
759379dd
ZA		 1139static inline u64 get_kernel_ns(void)
1140{
bb0b5812 1141 return ktime_get_boot_ns();
50d0a0f9
GH		 1142}
1143
d828199e 1144#ifdef CONFIG_X86_64
16e8d74d 1145static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1146#endif
16e8d74d 1147
c8076604 1148static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1149unsigned long max_tsc_khz;
c8076604 1150
cc578287 1151static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1152{
cc578287
ZA		 1153 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1154 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1155}
1156
cc578287 1157static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1158{
cc578287
ZA		 1159 u64 v = (u64)khz * (1000000 + ppm);
1160 do_div(v, 1000000);
1161 return v;
1e993611
JR		 1162}
1163
cc578287 1164static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1165{
cc578287
ZA		 1166 u32 thresh_lo, thresh_hi;
1167 int use_scaling = 0;
217fc9cf 1168
03ba32ca
MT		 1169 /* tsc_khz can be zero if TSC calibration fails */
1170 if (this_tsc_khz == 0)
1171 return;
1172
c285545f
ZA		 1173 /* Compute a scale to convert nanoseconds in TSC cycles */
1174 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1175 &vcpu->arch.virtual_tsc_shift,
1176 &vcpu->arch.virtual_tsc_mult);
1177 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1178
1179 /*
1180 * Compute the variation in TSC rate which is acceptable
1181 * within the range of tolerance and decide if the
1182 * rate being applied is within that bounds of the hardware
1183 * rate. If so, no scaling or compensation need be done.
1184 */
1185 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1186 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1187 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1188 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1189 use_scaling = 1;
1190 }
1191 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1192}
1193
1194static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1195{
e26101b1 1196 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1197 vcpu->arch.virtual_tsc_mult,
1198 vcpu->arch.virtual_tsc_shift);
e26101b1 1199 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1200 return tsc;
1201}
1202
b48aa97e
MT		 1203void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1204{
1205#ifdef CONFIG_X86_64
1206 bool vcpus_matched;
1207 bool do_request = false;
1208 struct kvm_arch *ka = &vcpu->kvm->arch;
1209 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1210
1211 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1212 atomic_read(&vcpu->kvm->online_vcpus));
1213
1214 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1215 if (!ka->use_master_clock)
1216 do_request = 1;
1217
1218 if (!vcpus_matched && ka->use_master_clock)
1219 do_request = 1;
1220
1221 if (do_request)
1222 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1223
1224 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1225 atomic_read(&vcpu->kvm->online_vcpus),
1226 ka->use_master_clock, gtod->clock.vclock_mode);
1227#endif
1228}
1229
ba904635
WA		 1230static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1231{
1232 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1233 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1234}
1235
8fe8ab46 1236void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1237{
1238 struct kvm *kvm = vcpu->kvm;
f38e098f 1239 u64 offset, ns, elapsed;
99e3e30a 1240 unsigned long flags;
02626b6a 1241 s64 usdiff;
b48aa97e 1242 bool matched;
0d3da0d2 1243 bool already_matched;
8fe8ab46 1244 u64 data = msr->data;
99e3e30a 1245
038f8c11 1246 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1247 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1248 ns = get_kernel_ns();
f38e098f 1249 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1250
03ba32ca 1251 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1252 int faulted = 0;
1253
03ba32ca
MT		 1254 /* n.b - signed multiplication and division required */
1255 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1256#ifdef CONFIG_X86_64
03ba32ca 1257 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1258#else
03ba32ca 1259 /* do_div() only does unsigned */
8915aa27
MT		 1260 asm("1: idivl %[divisor]\n"
1261 "2: xor %%edx, %%edx\n"
1262 " movl $0, %[faulted]\n"
1263 "3:\n"
1264 ".section .fixup,\"ax\"\n"
1265 "4: movl $1, %[faulted]\n"
1266 " jmp 3b\n"
1267 ".previous\n"
1268
1269 _ASM_EXTABLE(1b, 4b)
1270
1271 : "=A"(usdiff), [faulted] "=r" (faulted)
1272 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1273
5d3cb0f6 1274#endif
03ba32ca
MT		 1275 do_div(elapsed, 1000);
1276 usdiff -= elapsed;
1277 if (usdiff < 0)
1278 usdiff = -usdiff;
8915aa27
MT		 1279
1280 /* idivl overflow => difference is larger than USEC_PER_SEC */
1281 if (faulted)
1282 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1283 } else
1284 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1285
1286 /*
5d3cb0f6
ZA		 1287 * Special case: TSC write with a small delta (1 second) of virtual
1288 * cycle time against real time is interpreted as an attempt to
1289 * synchronize the CPU.
1290 *
1291 * For a reliable TSC, we can match TSC offsets, and for an unstable
1292 * TSC, we add elapsed time in this computation. We could let the
1293 * compensation code attempt to catch up if we fall behind, but
1294 * it's better to try to match offsets from the beginning.
1295 */
02626b6a 1296 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1297 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1298 if (!check_tsc_unstable()) {
e26101b1 1299 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1300 pr_debug("kvm: matched tsc offset for %llu\n", data);
1301 } else {
857e4099 1302 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1303 data += delta;
1304 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1305 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1306 }
b48aa97e 1307 matched = true;
0d3da0d2 1308 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1309 } else {
1310 /*
1311 * We split periods of matched TSC writes into generations.
1312 * For each generation, we track the original measured
1313 * nanosecond time, offset, and write, so if TSCs are in
1314 * sync, we can match exact offset, and if not, we can match
4a969980 1315 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1316 *
1317 * These values are tracked in kvm->arch.cur_xxx variables.
1318 */
1319 kvm->arch.cur_tsc_generation++;
1320 kvm->arch.cur_tsc_nsec = ns;
1321 kvm->arch.cur_tsc_write = data;
1322 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1323 matched = false;
0d3da0d2 1324 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1325 kvm->arch.cur_tsc_generation, data);
f38e098f 1326 }
e26101b1
ZA		 1327
1328 /*
1329 * We also track th most recent recorded KHZ, write and time to
1330 * allow the matching interval to be extended at each write.
1331 */
f38e098f
ZA		 1332 kvm->arch.last_tsc_nsec = ns;
1333 kvm->arch.last_tsc_write = data;
5d3cb0f6 1334 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1335
b183aa58 1336 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1337
1338 /* Keep track of which generation this VCPU has synchronized to */
1339 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1340 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1341 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1342
ba904635
WA		 1343 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1344 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1345 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1346 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1347
1348 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1349 if (!matched) {
b48aa97e 1350 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1351 } else if (!already_matched) {
1352 kvm->arch.nr_vcpus_matched_tsc++;
1353 }
b48aa97e
MT		 1354
1355 kvm_track_tsc_matching(vcpu);
1356 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1357}
e26101b1 1358
99e3e30a
ZA		 1359EXPORT_SYMBOL_GPL(kvm_write_tsc);
1360
d828199e
MT		 1361#ifdef CONFIG_X86_64
1362
1363static cycle_t read_tsc(void)
1364{
1365 cycle_t ret;
1366 u64 last;
1367
1368 /*
1369 * Empirically, a fence (of type that depends on the CPU)
1370 * before rdtsc is enough to ensure that rdtsc is ordered
1371 * with respect to loads. The various CPU manuals are unclear
1372 * as to whether rdtsc can be reordered with later loads,
1373 * but no one has ever seen it happen.
1374 */
1375 rdtsc_barrier();
1376 ret = (cycle_t)vget_cycles();
1377
1378 last = pvclock_gtod_data.clock.cycle_last;
1379
1380 if (likely(ret >= last))
1381 return ret;
1382
1383 /*
1384 * GCC likes to generate cmov here, but this branch is extremely
1385 * predictable (it's just a funciton of time and the likely is
1386 * very likely) and there's a data dependence, so force GCC
1387 * to generate a branch instead. I don't barrier() because
1388 * we don't actually need a barrier, and if this function
1389 * ever gets inlined it will generate worse code.
1390 */
1391 asm volatile ("");
1392 return last;
1393}
1394
1395static inline u64 vgettsc(cycle_t *cycle_now)
1396{
1397 long v;
1398 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1399
1400 *cycle_now = read_tsc();
1401
1402 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1403 return v * gtod->clock.mult;
1404}
1405
cbcf2dd3 1406static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1407{
cbcf2dd3 1408 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1409 unsigned long seq;
d828199e 1410 int mode;
cbcf2dd3 1411 u64 ns;
d828199e 1412
d828199e
MT		 1413 do {
1414 seq = read_seqcount_begin(&gtod->seq);
1415 mode = gtod->clock.vclock_mode;
cbcf2dd3 1416 ns = gtod->nsec_base;
d828199e
MT		 1417 ns += vgettsc(cycle_now);
1418 ns >>= gtod->clock.shift;
cbcf2dd3 1419 ns += gtod->boot_ns;
d828199e 1420 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1421 *t = ns;
d828199e
MT		 1422
1423 return mode;
1424}
1425
1426/* returns true if host is using tsc clocksource */
1427static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1428{
d828199e
MT		 1429 /* checked again under seqlock below */
1430 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1431 return false;
1432
cbcf2dd3 1433 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1434}
1435#endif
1436
1437/*
1438 *
b48aa97e
MT		 1439 * Assuming a stable TSC across physical CPUS, and a stable TSC
1440 * across virtual CPUs, the following condition is possible.
1441 * Each numbered line represents an event visible to both
d828199e
MT		 1442 * CPUs at the next numbered event.
1443 *
1444 * "timespecX" represents host monotonic time. "tscX" represents
1445 * RDTSC value.
1446 *
1447 * VCPU0 on CPU0 | VCPU1 on CPU1
1448 *
1449 * 1. read timespec0,tsc0
1450 * 2. | timespec1 = timespec0 + N
1451 * | tsc1 = tsc0 + M
1452 * 3. transition to guest | transition to guest
1453 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1454 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1455 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1456 *
1457 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1458 *
1459 * - ret0 < ret1
1460 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1461 * ...
1462 * - 0 < N - M => M < N
1463 *
1464 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1465 * always the case (the difference between two distinct xtime instances
1466 * might be smaller then the difference between corresponding TSC reads,
1467 * when updating guest vcpus pvclock areas).
1468 *
1469 * To avoid that problem, do not allow visibility of distinct
1470 * system_timestamp/tsc_timestamp values simultaneously: use a master
1471 * copy of host monotonic time values. Update that master copy
1472 * in lockstep.
1473 *
b48aa97e 1474 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1475 *
1476 */
1477
1478static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1479{
1480#ifdef CONFIG_X86_64
1481 struct kvm_arch *ka = &kvm->arch;
1482 int vclock_mode;
b48aa97e
MT		 1483 bool host_tsc_clocksource, vcpus_matched;
1484
1485 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1486 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1487
1488 /*
1489 * If the host uses TSC clock, then passthrough TSC as stable
1490 * to the guest.
1491 */
b48aa97e 1492 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1493 &ka->master_kernel_ns,
1494 &ka->master_cycle_now);
1495
16a96021
MT		 1496 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
1497 && !backwards_tsc_observed;
b48aa97e 1498
d828199e
MT		 1499 if (ka->use_master_clock)
1500 atomic_set(&kvm_guest_has_master_clock, 1);
1501
1502 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1503 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1504 vcpus_matched);
d828199e
MT		 1505#endif
1506}
1507
2e762ff7
MT		 1508static void kvm_gen_update_masterclock(struct kvm *kvm)
1509{
1510#ifdef CONFIG_X86_64
1511 int i;
1512 struct kvm_vcpu *vcpu;
1513 struct kvm_arch *ka = &kvm->arch;
1514
1515 spin_lock(&ka->pvclock_gtod_sync_lock);
1516 kvm_make_mclock_inprogress_request(kvm);
1517 /* no guest entries from this point */
1518 pvclock_update_vm_gtod_copy(kvm);
1519
1520 kvm_for_each_vcpu(i, vcpu, kvm)
1521 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1522
1523 /* guest entries allowed */
1524 kvm_for_each_vcpu(i, vcpu, kvm)
1525 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1526
1527 spin_unlock(&ka->pvclock_gtod_sync_lock);
1528#endif
1529}
1530
34c238a1 1531static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1532{
d828199e 1533 unsigned long flags, this_tsc_khz;
18068523 1534 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1535 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1536 s64 kernel_ns;
d828199e 1537 u64 tsc_timestamp, host_tsc;
0b79459b 1538 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1539 u8 pvclock_flags;
d828199e
MT		 1540 bool use_master_clock;
1541
1542 kernel_ns = 0;
1543 host_tsc = 0;
18068523 1544
d828199e
MT		 1545 /*
1546 * If the host uses TSC clock, then passthrough TSC as stable
1547 * to the guest.
1548 */
1549 spin_lock(&ka->pvclock_gtod_sync_lock);
1550 use_master_clock = ka->use_master_clock;
1551 if (use_master_clock) {
1552 host_tsc = ka->master_cycle_now;
1553 kernel_ns = ka->master_kernel_ns;
1554 }
1555 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1556
1557 /* Keep irq disabled to prevent changes to the clock */
1558 local_irq_save(flags);
1559 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1560 if (unlikely(this_tsc_khz == 0)) {
1561 local_irq_restore(flags);
1562 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1563 return 1;
1564 }
d828199e
MT		 1565 if (!use_master_clock) {
1566 host_tsc = native_read_tsc();
1567 kernel_ns = get_kernel_ns();
1568 }
1569
1570 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1571
c285545f
ZA		 1572 /*
1573 * We may have to catch up the TSC to match elapsed wall clock
1574 * time for two reasons, even if kvmclock is used.
1575 * 1) CPU could have been running below the maximum TSC rate
1576 * 2) Broken TSC compensation resets the base at each VCPU
1577 * entry to avoid unknown leaps of TSC even when running
1578 * again on the same CPU. This may cause apparent elapsed
1579 * time to disappear, and the guest to stand still or run
1580 * very slowly.
1581 */
1582 if (vcpu->tsc_catchup) {
1583 u64 tsc = compute_guest_tsc(v, kernel_ns);
1584 if (tsc > tsc_timestamp) {
f1e2b260 1585 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1586 tsc_timestamp = tsc;
1587 }
50d0a0f9
GH		 1588 }
1589
18068523
GOC		 1590 local_irq_restore(flags);
1591
0b79459b 1592 if (!vcpu->pv_time_enabled)
c285545f 1593 return 0;
18068523 1594
e48672fa 1595 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1596 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1597 &vcpu->hv_clock.tsc_shift,
1598 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1599 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1600 }
1601
1602 /* With all the info we got, fill in the values */
1d5f066e 1603 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1604 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1605 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1606
18068523
GOC		 1607 /*
1608 * The interface expects us to write an even number signaling that the
1609 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1610 * state, we just increase by 2 at the end.
18068523 1611 */
50d0a0f9 1612 vcpu->hv_clock.version += 2;
18068523 1613
0b79459b
AH		 1614 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1615 &guest_hv_clock, sizeof(guest_hv_clock))))
1616 return 0;
78c0337a
MT		 1617
1618 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1619 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1620
1621 if (vcpu->pvclock_set_guest_stopped_request) {
1622 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1623 vcpu->pvclock_set_guest_stopped_request = false;
1624 }
1625
d828199e
MT		 1626 /* If the host uses TSC clocksource, then it is stable */
1627 if (use_master_clock)
1628 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1629
78c0337a
MT		 1630 vcpu->hv_clock.flags = pvclock_flags;
1631
0b79459b
AH		 1632 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1633 &vcpu->hv_clock,
1634 sizeof(vcpu->hv_clock));
8cfdc000 1635 return 0;
c8076604
GH		 1636}
1637
0061d53d
MT		 1638/*
1639 * kvmclock updates which are isolated to a given vcpu, such as
1640 * vcpu->cpu migration, should not allow system_timestamp from
1641 * the rest of the vcpus to remain static. Otherwise ntp frequency
1642 * correction applies to one vcpu's system_timestamp but not
1643 * the others.
1644 *
1645 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1646 * We need to rate-limit these requests though, as they can
1647 * considerably slow guests that have a large number of vcpus.
1648 * The time for a remote vcpu to update its kvmclock is bound
1649 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1650 */
1651
7e44e449
AJ		 1652#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1653
1654static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1655{
1656 int i;
7e44e449
AJ		 1657 struct delayed_work *dwork = to_delayed_work(work);
1658 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1659 kvmclock_update_work);
1660 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1661 struct kvm_vcpu *vcpu;
1662
1663 kvm_for_each_vcpu(i, vcpu, kvm) {
1664 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1665 kvm_vcpu_kick(vcpu);
1666 }
1667}
1668
7e44e449
AJ		 1669static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1670{
1671 struct kvm *kvm = v->kvm;
1672
1673 set_bit(KVM_REQ_CLOCK_UPDATE, &v->requests);
1674 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1675 KVMCLOCK_UPDATE_DELAY);
1676}
1677
332967a3
AJ		 1678#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1679
1680static void kvmclock_sync_fn(struct work_struct *work)
1681{
1682 struct delayed_work *dwork = to_delayed_work(work);
1683 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1684 kvmclock_sync_work);
1685 struct kvm *kvm = container_of(ka, struct kvm, arch);
1686
1687 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1688 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1689 KVMCLOCK_SYNC_PERIOD);
1690}
1691
9ba075a6
AK		 1692static bool msr_mtrr_valid(unsigned msr)
1693{
1694 switch (msr) {
1695 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1696 case MSR_MTRRfix64K_00000:
1697 case MSR_MTRRfix16K_80000:
1698 case MSR_MTRRfix16K_A0000:
1699 case MSR_MTRRfix4K_C0000:
1700 case MSR_MTRRfix4K_C8000:
1701 case MSR_MTRRfix4K_D0000:
1702 case MSR_MTRRfix4K_D8000:
1703 case MSR_MTRRfix4K_E0000:
1704 case MSR_MTRRfix4K_E8000:
1705 case MSR_MTRRfix4K_F0000:
1706 case MSR_MTRRfix4K_F8000:
1707 case MSR_MTRRdefType:
1708 case MSR_IA32_CR_PAT:
1709 return true;
1710 case 0x2f8:
1711 return true;
1712 }
1713 return false;
1714}
1715
d6289b93
MT		 1716static bool valid_pat_type(unsigned t)
1717{
1718 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1719}
1720
1721static bool valid_mtrr_type(unsigned t)
1722{
1723 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1724}
1725
1726static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1727{
1728 int i;
fd275235 1729 u64 mask;
d6289b93
MT		 1730
1731 if (!msr_mtrr_valid(msr))
1732 return false;
1733
1734 if (msr == MSR_IA32_CR_PAT) {
1735 for (i = 0; i < 8; i++)
1736 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1737 return false;
1738 return true;
1739 } else if (msr == MSR_MTRRdefType) {
1740 if (data & ~0xcff)
1741 return false;
1742 return valid_mtrr_type(data & 0xff);
1743 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1744 for (i = 0; i < 8 ; i++)
1745 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1746 return false;
1747 return true;
1748 }
1749
1750 /* variable MTRRs */
adfb5d27
WL		 1751 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
1752
fd275235 1753 mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
d7a2a246 1754 if ((msr & 1) == 0) {
adfb5d27 1755 /* MTRR base */
d7a2a246
WL		 1756 if (!valid_mtrr_type(data & 0xff))
1757 return false;
1758 mask |= 0xf00;
1759 } else
1760 /* MTRR mask */
1761 mask |= 0x7ff;
1762 if (data & mask) {
1763 kvm_inject_gp(vcpu, 0);
1764 return false;
1765 }
1766
adfb5d27 1767 return true;
d6289b93
MT		 1768}
1769
9ba075a6
AK		 1770static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1771{
0bed3b56
SY		 1772 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1773
d6289b93 1774 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1775 return 1;
1776
0bed3b56
SY		 1777 if (msr == MSR_MTRRdefType) {
1778 vcpu->arch.mtrr_state.def_type = data;
1779 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1780 } else if (msr == MSR_MTRRfix64K_00000)
1781 p[0] = data;
1782 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1783 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1784 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1785 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1786 else if (msr == MSR_IA32_CR_PAT)
1787 vcpu->arch.pat = data;
1788 else { /* Variable MTRRs */
1789 int idx, is_mtrr_mask;
1790 u64 *pt;
1791
1792 idx = (msr - 0x200) / 2;
1793 is_mtrr_mask = msr - 0x200 - 2 * idx;
1794 if (!is_mtrr_mask)
1795 pt =
1796 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1797 else
1798 pt =
1799 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1800 *pt = data;
1801 }
1802
1803 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1804 return 0;
1805}
15c4a640 1806
890ca9ae 1807static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1808{
890ca9ae
HY		 1809 u64 mcg_cap = vcpu->arch.mcg_cap;
1810 unsigned bank_num = mcg_cap & 0xff;
1811
15c4a640 1812 switch (msr) {
15c4a640 1813 case MSR_IA32_MCG_STATUS:
890ca9ae 1814 vcpu->arch.mcg_status = data;
15c4a640 1815 break;
c7ac679c 1816 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1817 if (!(mcg_cap & MCG_CTL_P))
1818 return 1;
1819 if (data != 0 && data != ~(u64)0)
1820 return -1;
1821 vcpu->arch.mcg_ctl = data;
1822 break;
1823 default:
1824 if (msr >= MSR_IA32_MC0_CTL &&
1825 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1826 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1827 /* only 0 or all 1s can be written to IA32_MCi_CTL
1828 * some Linux kernels though clear bit 10 in bank 4 to
1829 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1830 * this to avoid an uncatched #GP in the guest
1831 */
890ca9ae 1832 if ((offset & 0x3) == 0 &&
114be429 1833 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1834 return -1;
1835 vcpu->arch.mce_banks[offset] = data;
1836 break;
1837 }
1838 return 1;
1839 }
1840 return 0;
1841}
1842
ffde22ac
ES		 1843static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1844{
1845 struct kvm *kvm = vcpu->kvm;
1846 int lm = is_long_mode(vcpu);
1847 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1848 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1849 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1850 : kvm->arch.xen_hvm_config.blob_size_32;
1851 u32 page_num = data & ~PAGE_MASK;
1852 u64 page_addr = data & PAGE_MASK;
1853 u8 *page;
1854 int r;
1855
1856 r = -E2BIG;
1857 if (page_num >= blob_size)
1858 goto out;
1859 r = -ENOMEM;
ff5c2c03
SL		 1860 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1861 if (IS_ERR(page)) {
1862 r = PTR_ERR(page);
ffde22ac 1863 goto out;
ff5c2c03 1864 }
ffde22ac
ES		 1865 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1866 goto out_free;
1867 r = 0;
1868out_free:
1869 kfree(page);
1870out:
1871 return r;
1872}
1873
55cd8e5a
GN		 1874static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1875{
1876 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1877}
1878
1879static bool kvm_hv_msr_partition_wide(u32 msr)
1880{
1881 bool r = false;
1882 switch (msr) {
1883 case HV_X64_MSR_GUEST_OS_ID:
1884 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1885 case HV_X64_MSR_REFERENCE_TSC:
1886 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1887 r = true;
1888 break;
1889 }
1890
1891 return r;
1892}
1893
1894static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1895{
1896 struct kvm *kvm = vcpu->kvm;
1897
1898 switch (msr) {
1899 case HV_X64_MSR_GUEST_OS_ID:
1900 kvm->arch.hv_guest_os_id = data;
1901 /* setting guest os id to zero disables hypercall page */
1902 if (!kvm->arch.hv_guest_os_id)
1903 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1904 break;
1905 case HV_X64_MSR_HYPERCALL: {
1906 u64 gfn;
1907 unsigned long addr;
1908 u8 instructions[4];
1909
1910 /* if guest os id is not set hypercall should remain disabled */
1911 if (!kvm->arch.hv_guest_os_id)
1912 break;
1913 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1914 kvm->arch.hv_hypercall = data;
1915 break;
1916 }
1917 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1918 addr = gfn_to_hva(kvm, gfn);
1919 if (kvm_is_error_hva(addr))
1920 return 1;
1921 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1922 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1923 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1924 return 1;
1925 kvm->arch.hv_hypercall = data;
b94b64c9 1926 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1927 break;
1928 }
e984097b
VR		 1929 case HV_X64_MSR_REFERENCE_TSC: {
1930 u64 gfn;
1931 HV_REFERENCE_TSC_PAGE tsc_ref;
1932 memset(&tsc_ref, 0, sizeof(tsc_ref));
1933 kvm->arch.hv_tsc_page = data;
1934 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1935 break;
1936 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1937 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1938 &tsc_ref, sizeof(tsc_ref)))
1939 return 1;
1940 mark_page_dirty(kvm, gfn);
1941 break;
1942 }
55cd8e5a 1943 default:
a737f256
CD		 1944 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1945 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1946 return 1;
1947 }
1948 return 0;
1949}
1950
1951static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1952{
10388a07
GN		 1953 switch (msr) {
1954 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1955 u64 gfn;
10388a07 1956 unsigned long addr;
55cd8e5a 1957
10388a07
GN		 1958 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1959 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1960 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1961 return 1;
10388a07
GN		 1962 break;
1963 }
b3af1e88
VR		 1964 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1965 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1966 if (kvm_is_error_hva(addr))
1967 return 1;
8b0cedff 1968 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1969 return 1;
1970 vcpu->arch.hv_vapic = data;
b3af1e88 1971 mark_page_dirty(vcpu->kvm, gfn);
b63cf42f
MT		 1972 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1973 return 1;
10388a07
GN		 1974 break;
1975 }
1976 case HV_X64_MSR_EOI:
1977 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1978 case HV_X64_MSR_ICR:
1979 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1980 case HV_X64_MSR_TPR:
1981 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1982 default:
a737f256
CD		 1983 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1984 "data 0x%llx\n", msr, data);
10388a07
GN		 1985 return 1;
1986 }
1987
1988 return 0;
55cd8e5a
GN		 1989}
1990
344d9588
GN		 1991static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1992{
1993 gpa_t gpa = data & ~0x3f;
1994
4a969980 1995 /* Bits 2:5 are reserved, Should be zero */
6adba527 1996 if (data & 0x3c)
344d9588
GN		 1997 return 1;
1998
1999 vcpu->arch.apf.msr_val = data;
2000
2001 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2002 kvm_clear_async_pf_completion_queue(vcpu);
2003 kvm_async_pf_hash_reset(vcpu);
2004 return 0;
2005 }
2006
8f964525
AH		 2007 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2008 sizeof(u32)))
344d9588
GN		 2009 return 1;
2010
6adba527 2011 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2012 kvm_async_pf_wakeup_all(vcpu);
2013 return 0;
2014}
2015
12f9a48f
GC		 2016static void kvmclock_reset(struct kvm_vcpu *vcpu)
2017{
0b79459b 2018 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2019}
2020
c9aaa895
GC		 2021static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2022{
2023 u64 delta;
2024
2025 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2026 return;
2027
2028 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2029 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2030 vcpu->arch.st.accum_steal = delta;
2031}
2032
2033static void record_steal_time(struct kvm_vcpu *vcpu)
2034{
2035 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2036 return;
2037
2038 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2039 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2040 return;
2041
2042 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2043 vcpu->arch.st.steal.version += 2;
2044 vcpu->arch.st.accum_steal = 0;
2045
2046 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2047 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2048}
2049
8fe8ab46 2050int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2051{
5753785f 2052 bool pr = false;
8fe8ab46
WA		 2053 u32 msr = msr_info->index;
2054 u64 data = msr_info->data;
5753785f 2055
15c4a640 2056 switch (msr) {
2e32b719
BP		 2057 case MSR_AMD64_NB_CFG:
2058 case MSR_IA32_UCODE_REV:
2059 case MSR_IA32_UCODE_WRITE:
2060 case MSR_VM_HSAVE_PA:
2061 case MSR_AMD64_PATCH_LOADER:
2062 case MSR_AMD64_BU_CFG2:
2063 break;
2064
15c4a640 2065 case MSR_EFER:
b69e8cae 2066 return set_efer(vcpu, data);
8f1589d9
AP		 2067 case MSR_K7_HWCR:
2068 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2069 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2070 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2071 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2072 if (data != 0) {
a737f256
CD		 2073 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2074 data);
8f1589d9
AP		 2075 return 1;
2076 }
15c4a640 2077 break;
f7c6d140
AP		 2078 case MSR_FAM10H_MMIO_CONF_BASE:
2079 if (data != 0) {
a737f256
CD		 2080 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2081 "0x%llx\n", data);
f7c6d140
AP		 2082 return 1;
2083 }
15c4a640 2084 break;
b5e2fec0
AG		 2085 case MSR_IA32_DEBUGCTLMSR:
2086 if (!data) {
2087 /* We support the non-activated case already */
2088 break;
2089 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2090 /* Values other than LBR and BTF are vendor-specific,
2091 thus reserved and should throw a #GP */
2092 return 1;
2093 }
a737f256
CD		 2094 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2095 __func__, data);
b5e2fec0 2096 break;
9ba075a6
AK		 2097 case 0x200 ... 0x2ff:
2098 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2099 case MSR_IA32_APICBASE:
58cb628d 2100 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2101 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2102 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2103 case MSR_IA32_TSCDEADLINE:
2104 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2105 break;
ba904635
WA		 2106 case MSR_IA32_TSC_ADJUST:
2107 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2108 if (!msr_info->host_initiated) {
2109 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2110 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2111 }
2112 vcpu->arch.ia32_tsc_adjust_msr = data;
2113 }
2114 break;
15c4a640 2115 case MSR_IA32_MISC_ENABLE:
ad312c7c 2116 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2117 break;
11c6bffa 2118 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2119 case MSR_KVM_WALL_CLOCK:
2120 vcpu->kvm->arch.wall_clock = data;
2121 kvm_write_wall_clock(vcpu->kvm, data);
2122 break;
11c6bffa 2123 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2124 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2125 u64 gpa_offset;
12f9a48f 2126 kvmclock_reset(vcpu);
18068523
GOC		 2127
2128 vcpu->arch.time = data;
0061d53d 2129 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2130
2131 /* we verify if the enable bit is set... */
2132 if (!(data & 1))
2133 break;
2134
0b79459b 2135 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2136
0b79459b 2137 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2138 &vcpu->arch.pv_time, data & ~1ULL,
2139 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2140 vcpu->arch.pv_time_enabled = false;
2141 else
2142 vcpu->arch.pv_time_enabled = true;
32cad84f 2143
18068523
GOC		 2144 break;
2145 }
344d9588
GN		 2146 case MSR_KVM_ASYNC_PF_EN:
2147 if (kvm_pv_enable_async_pf(vcpu, data))
2148 return 1;
2149 break;
c9aaa895
GC		 2150 case MSR_KVM_STEAL_TIME:
2151
2152 if (unlikely(!sched_info_on()))
2153 return 1;
2154
2155 if (data & KVM_STEAL_RESERVED_MASK)
2156 return 1;
2157
2158 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2159 data & KVM_STEAL_VALID_BITS,
2160 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2161 return 1;
2162
2163 vcpu->arch.st.msr_val = data;
2164
2165 if (!(data & KVM_MSR_ENABLED))
2166 break;
2167
2168 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2169
2170 preempt_disable();
2171 accumulate_steal_time(vcpu);
2172 preempt_enable();
2173
2174 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2175
2176 break;
ae7a2a3f
MT		 2177 case MSR_KVM_PV_EOI_EN:
2178 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2179 return 1;
2180 break;
c9aaa895 2181
890ca9ae
HY		 2182 case MSR_IA32_MCG_CTL:
2183 case MSR_IA32_MCG_STATUS:
2184 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2185 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2186
2187 /* Performance counters are not protected by a CPUID bit,
2188 * so we should check all of them in the generic path for the sake of
2189 * cross vendor migration.
2190 * Writing a zero into the event select MSRs disables them,
2191 * which we perfectly emulate ;-). Any other value should be at least
2192 * reported, some guests depend on them.
2193 */
71db6023
AP		 2194 case MSR_K7_EVNTSEL0:
2195 case MSR_K7_EVNTSEL1:
2196 case MSR_K7_EVNTSEL2:
2197 case MSR_K7_EVNTSEL3:
2198 if (data != 0)
a737f256
CD		 2199 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2200 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2201 break;
2202 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2203 * so we ignore writes to make it happy.
2204 */
71db6023
AP		 2205 case MSR_K7_PERFCTR0:
2206 case MSR_K7_PERFCTR1:
2207 case MSR_K7_PERFCTR2:
2208 case MSR_K7_PERFCTR3:
a737f256
CD		 2209 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2210 "0x%x data 0x%llx\n", msr, data);
71db6023 2211 break;
5753785f
GN		 2212 case MSR_P6_PERFCTR0:
2213 case MSR_P6_PERFCTR1:
2214 pr = true;
2215 case MSR_P6_EVNTSEL0:
2216 case MSR_P6_EVNTSEL1:
2217 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2218 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2219
2220 if (pr || data != 0)
a737f256
CD		 2221 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2222 "0x%x data 0x%llx\n", msr, data);
5753785f 2223 break;
84e0cefa
JS		 2224 case MSR_K7_CLK_CTL:
2225 /*
2226 * Ignore all writes to this no longer documented MSR.
2227 * Writes are only relevant for old K7 processors,
2228 * all pre-dating SVM, but a recommended workaround from
4a969980 2229 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2230 * affected processor models on the command line, hence
2231 * the need to ignore the workaround.
2232 */
2233 break;
55cd8e5a
GN		 2234 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2235 if (kvm_hv_msr_partition_wide(msr)) {
2236 int r;
2237 mutex_lock(&vcpu->kvm->lock);
2238 r = set_msr_hyperv_pw(vcpu, msr, data);
2239 mutex_unlock(&vcpu->kvm->lock);
2240 return r;
2241 } else
2242 return set_msr_hyperv(vcpu, msr, data);
2243 break;
91c9c3ed 2244 case MSR_IA32_BBL_CR_CTL3:
2245 /* Drop writes to this legacy MSR -- see rdmsr
2246 * counterpart for further detail.
2247 */
a737f256 2248 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2249 break;
2b036c6b
BO		 2250 case MSR_AMD64_OSVW_ID_LENGTH:
2251 if (!guest_cpuid_has_osvw(vcpu))
2252 return 1;
2253 vcpu->arch.osvw.length = data;
2254 break;
2255 case MSR_AMD64_OSVW_STATUS:
2256 if (!guest_cpuid_has_osvw(vcpu))
2257 return 1;
2258 vcpu->arch.osvw.status = data;
2259 break;
15c4a640 2260 default:
ffde22ac
ES		 2261 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2262 return xen_hvm_config(vcpu, data);
f5132b01 2263 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2264 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2265 if (!ignore_msrs) {
a737f256
CD		 2266 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2267 msr, data);
ed85c068
AP		 2268 return 1;
2269 } else {
a737f256
CD		 2270 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2271 msr, data);
ed85c068
AP		 2272 break;
2273 }
15c4a640
CO		 2274 }
2275 return 0;
2276}
2277EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2278
2279
2280/*
2281 * Reads an msr value (of 'msr_index') into 'pdata'.
2282 * Returns 0 on success, non-0 otherwise.
2283 * Assumes vcpu_load() was already called.
2284 */
2285int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2286{
2287 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2288}
2289
9ba075a6
AK		 2290static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2291{
0bed3b56
SY		 2292 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2293
9ba075a6
AK		 2294 if (!msr_mtrr_valid(msr))
2295 return 1;
2296
0bed3b56
SY		 2297 if (msr == MSR_MTRRdefType)
2298 *pdata = vcpu->arch.mtrr_state.def_type +
2299 (vcpu->arch.mtrr_state.enabled << 10);
2300 else if (msr == MSR_MTRRfix64K_00000)
2301 *pdata = p[0];
2302 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2303 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2304 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2305 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2306 else if (msr == MSR_IA32_CR_PAT)
2307 *pdata = vcpu->arch.pat;
2308 else { /* Variable MTRRs */
2309 int idx, is_mtrr_mask;
2310 u64 *pt;
2311
2312 idx = (msr - 0x200) / 2;
2313 is_mtrr_mask = msr - 0x200 - 2 * idx;
2314 if (!is_mtrr_mask)
2315 pt =
2316 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2317 else
2318 pt =
2319 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2320 *pdata = *pt;
2321 }
2322
9ba075a6
AK		 2323 return 0;
2324}
2325
890ca9ae 2326static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2327{
2328 u64 data;
890ca9ae
HY		 2329 u64 mcg_cap = vcpu->arch.mcg_cap;
2330 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2331
2332 switch (msr) {
15c4a640
CO		 2333 case MSR_IA32_P5_MC_ADDR:
2334 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2335 data = 0;
2336 break;
15c4a640 2337 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2338 data = vcpu->arch.mcg_cap;
2339 break;
c7ac679c 2340 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2341 if (!(mcg_cap & MCG_CTL_P))
2342 return 1;
2343 data = vcpu->arch.mcg_ctl;
2344 break;
2345 case MSR_IA32_MCG_STATUS:
2346 data = vcpu->arch.mcg_status;
2347 break;
2348 default:
2349 if (msr >= MSR_IA32_MC0_CTL &&
2350 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2351 u32 offset = msr - MSR_IA32_MC0_CTL;
2352 data = vcpu->arch.mce_banks[offset];
2353 break;
2354 }
2355 return 1;
2356 }
2357 *pdata = data;
2358 return 0;
2359}
2360
55cd8e5a
GN		 2361static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2362{
2363 u64 data = 0;
2364 struct kvm *kvm = vcpu->kvm;
2365
2366 switch (msr) {
2367 case HV_X64_MSR_GUEST_OS_ID:
2368 data = kvm->arch.hv_guest_os_id;
2369 break;
2370 case HV_X64_MSR_HYPERCALL:
2371 data = kvm->arch.hv_hypercall;
2372 break;
e984097b
VR		 2373 case HV_X64_MSR_TIME_REF_COUNT: {
2374 data =
2375 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2376 break;
2377 }
2378 case HV_X64_MSR_REFERENCE_TSC:
2379 data = kvm->arch.hv_tsc_page;
2380 break;
55cd8e5a 2381 default:
a737f256 2382 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2383 return 1;
2384 }
2385
2386 *pdata = data;
2387 return 0;
2388}
2389
2390static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2391{
2392 u64 data = 0;
2393
2394 switch (msr) {
2395 case HV_X64_MSR_VP_INDEX: {
2396 int r;
2397 struct kvm_vcpu *v;
684851a1
TY		 2398 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2399 if (v == vcpu) {
55cd8e5a 2400 data = r;
684851a1
TY		 2401 break;
2402 }
2403 }
55cd8e5a
GN		 2404 break;
2405 }
10388a07
GN		 2406 case HV_X64_MSR_EOI:
2407 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2408 case HV_X64_MSR_ICR:
2409 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2410 case HV_X64_MSR_TPR:
2411 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2412 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2413 data = vcpu->arch.hv_vapic;
2414 break;
55cd8e5a 2415 default:
a737f256 2416 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2417 return 1;
2418 }
2419 *pdata = data;
2420 return 0;
2421}
2422
890ca9ae
HY		 2423int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2424{
2425 u64 data;
2426
2427 switch (msr) {
890ca9ae 2428 case MSR_IA32_PLATFORM_ID:
15c4a640 2429 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2430 case MSR_IA32_DEBUGCTLMSR:
2431 case MSR_IA32_LASTBRANCHFROMIP:
2432 case MSR_IA32_LASTBRANCHTOIP:
2433 case MSR_IA32_LASTINTFROMIP:
2434 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2435 case MSR_K8_SYSCFG:
2436 case MSR_K7_HWCR:
61a6bd67 2437 case MSR_VM_HSAVE_PA:
9e699624 2438 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2439 case MSR_K7_EVNTSEL1:
2440 case MSR_K7_EVNTSEL2:
2441 case MSR_K7_EVNTSEL3:
1f3ee616 2442 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2443 case MSR_K7_PERFCTR1:
2444 case MSR_K7_PERFCTR2:
2445 case MSR_K7_PERFCTR3:
1fdbd48c 2446 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2447 case MSR_AMD64_NB_CFG:
f7c6d140 2448 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2449 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2450 data = 0;
2451 break;
5753785f
GN		 2452 case MSR_P6_PERFCTR0:
2453 case MSR_P6_PERFCTR1:
2454 case MSR_P6_EVNTSEL0:
2455 case MSR_P6_EVNTSEL1:
2456 if (kvm_pmu_msr(vcpu, msr))
2457 return kvm_pmu_get_msr(vcpu, msr, pdata);
2458 data = 0;
2459 break;
742bc670
MT		 2460 case MSR_IA32_UCODE_REV:
2461 data = 0x100000000ULL;
2462 break;
9ba075a6
AK		 2463 case MSR_MTRRcap:
2464 data = 0x500 | KVM_NR_VAR_MTRR;
2465 break;
2466 case 0x200 ... 0x2ff:
2467 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2468 case 0xcd: /* fsb frequency */
2469 data = 3;
2470 break;
7b914098
JS		 2471 /*
2472 * MSR_EBC_FREQUENCY_ID
2473 * Conservative value valid for even the basic CPU models.
2474 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2475 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2476 * and 266MHz for model 3, or 4. Set Core Clock
2477 * Frequency to System Bus Frequency Ratio to 1 (bits
2478 * 31:24) even though these are only valid for CPU
2479 * models > 2, however guests may end up dividing or
2480 * multiplying by zero otherwise.
2481 */
2482 case MSR_EBC_FREQUENCY_ID:
2483 data = 1 << 24;
2484 break;
15c4a640
CO		 2485 case MSR_IA32_APICBASE:
2486 data = kvm_get_apic_base(vcpu);
2487 break;
0105d1a5
GN		 2488 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2489 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2490 break;
a3e06bbe
LJ		 2491 case MSR_IA32_TSCDEADLINE:
2492 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2493 break;
ba904635
WA		 2494 case MSR_IA32_TSC_ADJUST:
2495 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2496 break;
15c4a640 2497 case MSR_IA32_MISC_ENABLE:
ad312c7c 2498 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2499 break;
847f0ad8
AG		 2500 case MSR_IA32_PERF_STATUS:
2501 /* TSC increment by tick */
2502 data = 1000ULL;
2503 /* CPU multiplier */
2504 data |= (((uint64_t)4ULL) << 40);
2505 break;
15c4a640 2506 case MSR_EFER:
f6801dff 2507 data = vcpu->arch.efer;
15c4a640 2508 break;
18068523 2509 case MSR_KVM_WALL_CLOCK:
11c6bffa 2510 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2511 data = vcpu->kvm->arch.wall_clock;
2512 break;
2513 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2514 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2515 data = vcpu->arch.time;
2516 break;
344d9588
GN		 2517 case MSR_KVM_ASYNC_PF_EN:
2518 data = vcpu->arch.apf.msr_val;
2519 break;
c9aaa895
GC		 2520 case MSR_KVM_STEAL_TIME:
2521 data = vcpu->arch.st.msr_val;
2522 break;
1d92128f
MT		 2523 case MSR_KVM_PV_EOI_EN:
2524 data = vcpu->arch.pv_eoi.msr_val;
2525 break;
890ca9ae
HY		 2526 case MSR_IA32_P5_MC_ADDR:
2527 case MSR_IA32_P5_MC_TYPE:
2528 case MSR_IA32_MCG_CAP:
2529 case MSR_IA32_MCG_CTL:
2530 case MSR_IA32_MCG_STATUS:
2531 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2532 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2533 case MSR_K7_CLK_CTL:
2534 /*
2535 * Provide expected ramp-up count for K7. All other
2536 * are set to zero, indicating minimum divisors for
2537 * every field.
2538 *
2539 * This prevents guest kernels on AMD host with CPU
2540 * type 6, model 8 and higher from exploding due to
2541 * the rdmsr failing.
2542 */
2543 data = 0x20000000;
2544 break;
55cd8e5a
GN		 2545 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2546 if (kvm_hv_msr_partition_wide(msr)) {
2547 int r;
2548 mutex_lock(&vcpu->kvm->lock);
2549 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2550 mutex_unlock(&vcpu->kvm->lock);
2551 return r;
2552 } else
2553 return get_msr_hyperv(vcpu, msr, pdata);
2554 break;
91c9c3ed 2555 case MSR_IA32_BBL_CR_CTL3:
2556 /* This legacy MSR exists but isn't fully documented in current
2557 * silicon. It is however accessed by winxp in very narrow
2558 * scenarios where it sets bit #19, itself documented as
2559 * a "reserved" bit. Best effort attempt to source coherent
2560 * read data here should the balance of the register be
2561 * interpreted by the guest:
2562 *
2563 * L2 cache control register 3: 64GB range, 256KB size,
2564 * enabled, latency 0x1, configured
2565 */
2566 data = 0xbe702111;
2567 break;
2b036c6b
BO		 2568 case MSR_AMD64_OSVW_ID_LENGTH:
2569 if (!guest_cpuid_has_osvw(vcpu))
2570 return 1;
2571 data = vcpu->arch.osvw.length;
2572 break;
2573 case MSR_AMD64_OSVW_STATUS:
2574 if (!guest_cpuid_has_osvw(vcpu))
2575 return 1;
2576 data = vcpu->arch.osvw.status;
2577 break;
15c4a640 2578 default:
f5132b01
GN		 2579 if (kvm_pmu_msr(vcpu, msr))
2580 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2581 if (!ignore_msrs) {
a737f256 2582 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2583 return 1;
2584 } else {
a737f256 2585 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2586 data = 0;
2587 }
2588 break;
15c4a640
CO		 2589 }
2590 *pdata = data;
2591 return 0;
2592}
2593EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2594
313a3dc7
CO		 2595/*
2596 * Read or write a bunch of msrs. All parameters are kernel addresses.
2597 *
2598 * @return number of msrs set successfully.
2599 */
2600static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2601 struct kvm_msr_entry *entries,
2602 int (*do_msr)(struct kvm_vcpu *vcpu,
2603 unsigned index, u64 *data))
2604{
f656ce01 2605 int i, idx;
313a3dc7 2606
f656ce01 2607 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2608 for (i = 0; i < msrs->nmsrs; ++i)
2609 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2610 break;
f656ce01 2611 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2612
313a3dc7
CO		 2613 return i;
2614}
2615
2616/*
2617 * Read or write a bunch of msrs. Parameters are user addresses.
2618 *
2619 * @return number of msrs set successfully.
2620 */
2621static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2622 int (*do_msr)(struct kvm_vcpu *vcpu,
2623 unsigned index, u64 *data),
2624 int writeback)
2625{
2626 struct kvm_msrs msrs;
2627 struct kvm_msr_entry *entries;
2628 int r, n;
2629 unsigned size;
2630
2631 r = -EFAULT;
2632 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2633 goto out;
2634
2635 r = -E2BIG;
2636 if (msrs.nmsrs >= MAX_IO_MSRS)
2637 goto out;
2638
313a3dc7 2639 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2640 entries = memdup_user(user_msrs->entries, size);
2641 if (IS_ERR(entries)) {
2642 r = PTR_ERR(entries);
313a3dc7 2643 goto out;
ff5c2c03 2644 }
313a3dc7
CO		 2645
2646 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2647 if (r < 0)
2648 goto out_free;
2649
2650 r = -EFAULT;
2651 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2652 goto out_free;
2653
2654 r = n;
2655
2656out_free:
7a73c028 2657 kfree(entries);
313a3dc7
CO		 2658out:
2659 return r;
2660}
2661
784aa3d7 2662int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2663{
2664 int r;
2665
2666 switch (ext) {
2667 case KVM_CAP_IRQCHIP:
2668 case KVM_CAP_HLT:
2669 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2670 case KVM_CAP_SET_TSS_ADDR:
07716717 2671 case KVM_CAP_EXT_CPUID:
9c15bb1d 2672 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2673 case KVM_CAP_CLOCKSOURCE:
7837699f 2674 case KVM_CAP_PIT:
a28e4f5a 2675 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2676 case KVM_CAP_MP_STATE:
ed848624 2677 case KVM_CAP_SYNC_MMU:
a355c85c 2678 case KVM_CAP_USER_NMI:
52d939a0 2679 case KVM_CAP_REINJECT_CONTROL:
4925663a 2680 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2681 case KVM_CAP_IRQFD:
d34e6b17 2682 case KVM_CAP_IOEVENTFD:
f848a5a8 2683 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2684 case KVM_CAP_PIT2:
e9f42757 2685 case KVM_CAP_PIT_STATE2:
b927a3ce 2686 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2687 case KVM_CAP_XEN_HVM:
afbcf7ab 2688 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2689 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2690 case KVM_CAP_HYPERV:
10388a07 2691 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2692 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2693 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2694 case KVM_CAP_DEBUGREGS:
d2be1651 2695 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2696 case KVM_CAP_XSAVE:
344d9588 2697 case KVM_CAP_ASYNC_PF:
92a1f12d 2698 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2699 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2700 case KVM_CAP_READONLY_MEM:
5f66b620 2701 case KVM_CAP_HYPERV_TIME:
100943c5 2702 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
2a5bab10
AW		 2703#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2704 case KVM_CAP_ASSIGN_DEV_IRQ:
2705 case KVM_CAP_PCI_2_3:
2706#endif
018d00d2
ZX		 2707 r = 1;
2708 break;
542472b5
LV		 2709 case KVM_CAP_COALESCED_MMIO:
2710 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2711 break;
774ead3a
AK		 2712 case KVM_CAP_VAPIC:
2713 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2714 break;
f725230a 2715 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2716 r = KVM_SOFT_MAX_VCPUS;
2717 break;
2718 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2719 r = KVM_MAX_VCPUS;
2720 break;
a988b910 2721 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2722 r = KVM_USER_MEM_SLOTS;
a988b910 2723 break;
a68a6a72
MT		 2724 case KVM_CAP_PV_MMU: /* obsolete */
2725 r = 0;
2f333bcb 2726 break;
4cee4b72 2727#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2728 case KVM_CAP_IOMMU:
a1b60c1c 2729 r = iommu_present(&pci_bus_type);
62c476c7 2730 break;
4cee4b72 2731#endif
890ca9ae
HY		 2732 case KVM_CAP_MCE:
2733 r = KVM_MAX_MCE_BANKS;
2734 break;
2d5b5a66
SY		 2735 case KVM_CAP_XCRS:
2736 r = cpu_has_xsave;
2737 break;
92a1f12d
JR		 2738 case KVM_CAP_TSC_CONTROL:
2739 r = kvm_has_tsc_control;
2740 break;
4d25a066
JK		 2741 case KVM_CAP_TSC_DEADLINE_TIMER:
2742 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2743 break;
018d00d2
ZX		 2744 default:
2745 r = 0;
2746 break;
2747 }
2748 return r;
2749
2750}
2751
043405e1
CO		 2752long kvm_arch_dev_ioctl(struct file *filp,
2753 unsigned int ioctl, unsigned long arg)
2754{
2755 void __user *argp = (void __user *)arg;
2756 long r;
2757
2758 switch (ioctl) {
2759 case KVM_GET_MSR_INDEX_LIST: {
2760 struct kvm_msr_list __user *user_msr_list = argp;
2761 struct kvm_msr_list msr_list;
2762 unsigned n;
2763
2764 r = -EFAULT;
2765 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2766 goto out;
2767 n = msr_list.nmsrs;
2768 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2769 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2770 goto out;
2771 r = -E2BIG;
e125e7b6 2772 if (n < msr_list.nmsrs)
043405e1
CO		 2773 goto out;
2774 r = -EFAULT;
2775 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2776 num_msrs_to_save * sizeof(u32)))
2777 goto out;
e125e7b6 2778 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2779 &emulated_msrs,
2780 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2781 goto out;
2782 r = 0;
2783 break;
2784 }
9c15bb1d
BP		 2785 case KVM_GET_SUPPORTED_CPUID:
2786 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2787 struct kvm_cpuid2 __user *cpuid_arg = argp;
2788 struct kvm_cpuid2 cpuid;
2789
2790 r = -EFAULT;
2791 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2792 goto out;
9c15bb1d
BP		 2793
2794 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2795 ioctl);
674eea0f
AK		 2796 if (r)
2797 goto out;
2798
2799 r = -EFAULT;
2800 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2801 goto out;
2802 r = 0;
2803 break;
2804 }
890ca9ae
HY		 2805 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2806 u64 mce_cap;
2807
2808 mce_cap = KVM_MCE_CAP_SUPPORTED;
2809 r = -EFAULT;
2810 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2811 goto out;
2812 r = 0;
2813 break;
2814 }
043405e1
CO		 2815 default:
2816 r = -EINVAL;
2817 }
2818out:
2819 return r;
2820}
2821
f5f48ee1
SY		 2822static void wbinvd_ipi(void *garbage)
2823{
2824 wbinvd();
2825}
2826
2827static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2828{
e0f0bbc5 2829 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2830}
2831
313a3dc7
CO		 2832void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2833{
f5f48ee1
SY		 2834 /* Address WBINVD may be executed by guest */
2835 if (need_emulate_wbinvd(vcpu)) {
2836 if (kvm_x86_ops->has_wbinvd_exit())
2837 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2838 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2839 smp_call_function_single(vcpu->cpu,
2840 wbinvd_ipi, NULL, 1);
2841 }
2842
313a3dc7 2843 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2844
0dd6a6ed
ZA		 2845 /* Apply any externally detected TSC adjustments (due to suspend) */
2846 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2847 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2848 vcpu->arch.tsc_offset_adjustment = 0;
2849 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2850 }
8f6055cb 2851
48434c20 2852 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2853 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2854 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2855 if (tsc_delta < 0)
2856 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2857 if (check_tsc_unstable()) {
b183aa58
ZA		 2858 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2859 vcpu->arch.last_guest_tsc);
2860 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2861 vcpu->arch.tsc_catchup = 1;
c285545f 2862 }
d98d07ca
MT		 2863 /*
2864 * On a host with synchronized TSC, there is no need to update
2865 * kvmclock on vcpu->cpu migration
2866 */
2867 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2868 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2869 if (vcpu->cpu != cpu)
2870 kvm_migrate_timers(vcpu);
e48672fa 2871 vcpu->cpu = cpu;
6b7d7e76 2872 }
c9aaa895
GC		 2873
2874 accumulate_steal_time(vcpu);
2875 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2876}
2877
2878void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2879{
02daab21 2880 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2881 kvm_put_guest_fpu(vcpu);
6f526ec5 2882 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2883}
2884
313a3dc7
CO		 2885static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2886 struct kvm_lapic_state *s)
2887{
5a71785d 2888 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2889 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2890
2891 return 0;
2892}
2893
2894static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2895 struct kvm_lapic_state *s)
2896{
64eb0620 2897 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2898 update_cr8_intercept(vcpu);
313a3dc7
CO		 2899
2900 return 0;
2901}
2902
f77bc6a4
ZX		 2903static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2904 struct kvm_interrupt *irq)
2905{
02cdb50f 2906 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2907 return -EINVAL;
2908 if (irqchip_in_kernel(vcpu->kvm))
2909 return -ENXIO;
f77bc6a4 2910
66fd3f7f 2911 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2912 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2913
f77bc6a4
ZX		 2914 return 0;
2915}
2916
c4abb7c9
JK		 2917static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2918{
c4abb7c9 2919 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2920
2921 return 0;
2922}
2923
b209749f
AK		 2924static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2925 struct kvm_tpr_access_ctl *tac)
2926{
2927 if (tac->flags)
2928 return -EINVAL;
2929 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2930 return 0;
2931}
2932
890ca9ae
HY		 2933static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2934 u64 mcg_cap)
2935{
2936 int r;
2937 unsigned bank_num = mcg_cap & 0xff, bank;
2938
2939 r = -EINVAL;
a9e38c3e 2940 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2941 goto out;
2942 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2943 goto out;
2944 r = 0;
2945 vcpu->arch.mcg_cap = mcg_cap;
2946 /* Init IA32_MCG_CTL to all 1s */
2947 if (mcg_cap & MCG_CTL_P)
2948 vcpu->arch.mcg_ctl = ~(u64)0;
2949 /* Init IA32_MCi_CTL to all 1s */
2950 for (bank = 0; bank < bank_num; bank++)
2951 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2952out:
2953 return r;
2954}
2955
2956static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2957 struct kvm_x86_mce *mce)
2958{
2959 u64 mcg_cap = vcpu->arch.mcg_cap;
2960 unsigned bank_num = mcg_cap & 0xff;
2961 u64 *banks = vcpu->arch.mce_banks;
2962
2963 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2964 return -EINVAL;
2965 /*
2966 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2967 * reporting is disabled
2968 */
2969 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2970 vcpu->arch.mcg_ctl != ~(u64)0)
2971 return 0;
2972 banks += 4 * mce->bank;
2973 /*
2974 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2975 * reporting is disabled for the bank
2976 */
2977 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2978 return 0;
2979 if (mce->status & MCI_STATUS_UC) {
2980 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2981 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2982 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2983 return 0;
2984 }
2985 if (banks[1] & MCI_STATUS_VAL)
2986 mce->status |= MCI_STATUS_OVER;
2987 banks[2] = mce->addr;
2988 banks[3] = mce->misc;
2989 vcpu->arch.mcg_status = mce->mcg_status;
2990 banks[1] = mce->status;
2991 kvm_queue_exception(vcpu, MC_VECTOR);
2992 } else if (!(banks[1] & MCI_STATUS_VAL)
2993 || !(banks[1] & MCI_STATUS_UC)) {
2994 if (banks[1] & MCI_STATUS_VAL)
2995 mce->status |= MCI_STATUS_OVER;
2996 banks[2] = mce->addr;
2997 banks[3] = mce->misc;
2998 banks[1] = mce->status;
2999 } else
3000 banks[1] |= MCI_STATUS_OVER;
3001 return 0;
3002}
3003
3cfc3092
JK		 3004static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3005 struct kvm_vcpu_events *events)
3006{
7460fb4a 3007 process_nmi(vcpu);
03b82a30
JK		 3008 events->exception.injected =
3009 vcpu->arch.exception.pending &&
3010 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3011 events->exception.nr = vcpu->arch.exception.nr;
3012 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3013 events->exception.pad = 0;
3cfc3092
JK		 3014 events->exception.error_code = vcpu->arch.exception.error_code;
3015
03b82a30
JK		 3016 events->interrupt.injected =
3017 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3018 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3019 events->interrupt.soft = 0;
37ccdcbe 3020 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3021
3022 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3023 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3024 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3025 events->nmi.pad = 0;
3cfc3092 3026
66450a21 3027 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3028
dab4b911 3029 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3030 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 3031 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3032}
3033
3034static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3035 struct kvm_vcpu_events *events)
3036{
dab4b911 3037 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 3038 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
3039 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 3040 return -EINVAL;
3041
7460fb4a 3042 process_nmi(vcpu);
3cfc3092
JK		 3043 vcpu->arch.exception.pending = events->exception.injected;
3044 vcpu->arch.exception.nr = events->exception.nr;
3045 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3046 vcpu->arch.exception.error_code = events->exception.error_code;
3047
3048 vcpu->arch.interrupt.pending = events->interrupt.injected;
3049 vcpu->arch.interrupt.nr = events->interrupt.nr;
3050 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3051 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3052 kvm_x86_ops->set_interrupt_shadow(vcpu,
3053 events->interrupt.shadow);
3cfc3092
JK		 3054
3055 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3056 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3057 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3058 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3059
66450a21
JK		 3060 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3061 kvm_vcpu_has_lapic(vcpu))
3062 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3063
3842d135
AK		 3064 kvm_make_request(KVM_REQ_EVENT, vcpu);
3065
3cfc3092
JK		 3066 return 0;
3067}
3068
a1efbe77
JK		 3069static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3070 struct kvm_debugregs *dbgregs)
3071{
73aaf249
JK		 3072 unsigned long val;
3073
a1efbe77 3074 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 3075 _kvm_get_dr(vcpu, 6, &val);
3076 dbgregs->dr6 = val;
a1efbe77
JK		 3077 dbgregs->dr7 = vcpu->arch.dr7;
3078 dbgregs->flags = 0;
97e69aa6 3079 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3080}
3081
3082static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3083 struct kvm_debugregs *dbgregs)
3084{
3085 if (dbgregs->flags)
3086 return -EINVAL;
3087
a1efbe77
JK		 3088 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3089 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3090 kvm_update_dr6(vcpu);
a1efbe77 3091 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3092 kvm_update_dr7(vcpu);
a1efbe77 3093
a1efbe77
JK		 3094 return 0;
3095}
3096
2d5b5a66
SY		 3097static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3098 struct kvm_xsave *guest_xsave)
3099{
4344ee98 3100 if (cpu_has_xsave) {
2d5b5a66
SY		 3101 memcpy(guest_xsave->region,
3102 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3103 vcpu->arch.guest_xstate_size);
3104 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3105 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3106 } else {
2d5b5a66
SY		 3107 memcpy(guest_xsave->region,
3108 &vcpu->arch.guest_fpu.state->fxsave,
3109 sizeof(struct i387_fxsave_struct));
3110 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3111 XSTATE_FPSSE;
3112 }
3113}
3114
3115static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3116 struct kvm_xsave *guest_xsave)
3117{
3118 u64 xstate_bv =
3119 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3120
d7876f1b
PB		 3121 if (cpu_has_xsave) {
3122 /*
3123 * Here we allow setting states that are not present in
3124 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3125 * with old userspace.
3126 */
4ff41732 3127 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3128 return -EINVAL;
2d5b5a66 3129 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3130 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3131 } else {
2d5b5a66
SY		 3132 if (xstate_bv & ~XSTATE_FPSSE)
3133 return -EINVAL;
3134 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3135 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3136 }
3137 return 0;
3138}
3139
3140static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3141 struct kvm_xcrs *guest_xcrs)
3142{
3143 if (!cpu_has_xsave) {
3144 guest_xcrs->nr_xcrs = 0;
3145 return;
3146 }
3147
3148 guest_xcrs->nr_xcrs = 1;
3149 guest_xcrs->flags = 0;
3150 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3151 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3152}
3153
3154static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3155 struct kvm_xcrs *guest_xcrs)
3156{
3157 int i, r = 0;
3158
3159 if (!cpu_has_xsave)
3160 return -EINVAL;
3161
3162 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3163 return -EINVAL;
3164
3165 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3166 /* Only support XCR0 currently */
c67a04cb 3167 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3168 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3169 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3170 break;
3171 }
3172 if (r)
3173 r = -EINVAL;
3174 return r;
3175}
3176
1c0b28c2
EM		 3177/*
3178 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3179 * stopped by the hypervisor. This function will be called from the host only.
3180 * EINVAL is returned when the host attempts to set the flag for a guest that
3181 * does not support pv clocks.
3182 */
3183static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3184{
0b79459b 3185 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3186 return -EINVAL;
51d59c6b 3187 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3188 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3189 return 0;
3190}
3191
313a3dc7
CO		 3192long kvm_arch_vcpu_ioctl(struct file *filp,
3193 unsigned int ioctl, unsigned long arg)
3194{
3195 struct kvm_vcpu *vcpu = filp->private_data;
3196 void __user *argp = (void __user *)arg;
3197 int r;
d1ac91d8
AK		 3198 union {
3199 struct kvm_lapic_state *lapic;
3200 struct kvm_xsave *xsave;
3201 struct kvm_xcrs *xcrs;
3202 void *buffer;
3203 } u;
3204
3205 u.buffer = NULL;
313a3dc7
CO		 3206 switch (ioctl) {
3207 case KVM_GET_LAPIC: {
2204ae3c
MT		 3208 r = -EINVAL;
3209 if (!vcpu->arch.apic)
3210 goto out;
d1ac91d8 3211 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3212
b772ff36 3213 r = -ENOMEM;
d1ac91d8 3214 if (!u.lapic)
b772ff36 3215 goto out;
d1ac91d8 3216 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3217 if (r)
3218 goto out;
3219 r = -EFAULT;
d1ac91d8 3220 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3221 goto out;
3222 r = 0;
3223 break;
3224 }
3225 case KVM_SET_LAPIC: {
2204ae3c
MT		 3226 r = -EINVAL;
3227 if (!vcpu->arch.apic)
3228 goto out;
ff5c2c03 3229 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3230 if (IS_ERR(u.lapic))
3231 return PTR_ERR(u.lapic);
ff5c2c03 3232
d1ac91d8 3233 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3234 break;
3235 }
f77bc6a4
ZX		 3236 case KVM_INTERRUPT: {
3237 struct kvm_interrupt irq;
3238
3239 r = -EFAULT;
3240 if (copy_from_user(&irq, argp, sizeof irq))
3241 goto out;
3242 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3243 break;
3244 }
c4abb7c9
JK		 3245 case KVM_NMI: {
3246 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3247 break;
3248 }
313a3dc7
CO		 3249 case KVM_SET_CPUID: {
3250 struct kvm_cpuid __user *cpuid_arg = argp;
3251 struct kvm_cpuid cpuid;
3252
3253 r = -EFAULT;
3254 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3255 goto out;
3256 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3257 break;
3258 }
07716717
DK		 3259 case KVM_SET_CPUID2: {
3260 struct kvm_cpuid2 __user *cpuid_arg = argp;
3261 struct kvm_cpuid2 cpuid;
3262
3263 r = -EFAULT;
3264 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3265 goto out;
3266 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3267 cpuid_arg->entries);
07716717
DK		 3268 break;
3269 }
3270 case KVM_GET_CPUID2: {
3271 struct kvm_cpuid2 __user *cpuid_arg = argp;
3272 struct kvm_cpuid2 cpuid;
3273
3274 r = -EFAULT;
3275 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3276 goto out;
3277 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3278 cpuid_arg->entries);
07716717
DK		 3279 if (r)
3280 goto out;
3281 r = -EFAULT;
3282 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3283 goto out;
3284 r = 0;
3285 break;
3286 }
313a3dc7
CO		 3287 case KVM_GET_MSRS:
3288 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3289 break;
3290 case KVM_SET_MSRS:
3291 r = msr_io(vcpu, argp, do_set_msr, 0);
3292 break;
b209749f
AK		 3293 case KVM_TPR_ACCESS_REPORTING: {
3294 struct kvm_tpr_access_ctl tac;
3295
3296 r = -EFAULT;
3297 if (copy_from_user(&tac, argp, sizeof tac))
3298 goto out;
3299 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3300 if (r)
3301 goto out;
3302 r = -EFAULT;
3303 if (copy_to_user(argp, &tac, sizeof tac))
3304 goto out;
3305 r = 0;
3306 break;
3307 };
b93463aa
AK		 3308 case KVM_SET_VAPIC_ADDR: {
3309 struct kvm_vapic_addr va;
3310
3311 r = -EINVAL;
3312 if (!irqchip_in_kernel(vcpu->kvm))
3313 goto out;
3314 r = -EFAULT;
3315 if (copy_from_user(&va, argp, sizeof va))
3316 goto out;
fda4e2e8 3317 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3318 break;
3319 }
890ca9ae
HY		 3320 case KVM_X86_SETUP_MCE: {
3321 u64 mcg_cap;
3322
3323 r = -EFAULT;
3324 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3325 goto out;
3326 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3327 break;
3328 }
3329 case KVM_X86_SET_MCE: {
3330 struct kvm_x86_mce mce;
3331
3332 r = -EFAULT;
3333 if (copy_from_user(&mce, argp, sizeof mce))
3334 goto out;
3335 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3336 break;
3337 }
3cfc3092
JK		 3338 case KVM_GET_VCPU_EVENTS: {
3339 struct kvm_vcpu_events events;
3340
3341 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3342
3343 r = -EFAULT;
3344 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3345 break;
3346 r = 0;
3347 break;
3348 }
3349 case KVM_SET_VCPU_EVENTS: {
3350 struct kvm_vcpu_events events;
3351
3352 r = -EFAULT;
3353 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3354 break;
3355
3356 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3357 break;
3358 }
a1efbe77
JK		 3359 case KVM_GET_DEBUGREGS: {
3360 struct kvm_debugregs dbgregs;
3361
3362 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3363
3364 r = -EFAULT;
3365 if (copy_to_user(argp, &dbgregs,
3366 sizeof(struct kvm_debugregs)))
3367 break;
3368 r = 0;
3369 break;
3370 }
3371 case KVM_SET_DEBUGREGS: {
3372 struct kvm_debugregs dbgregs;
3373
3374 r = -EFAULT;
3375 if (copy_from_user(&dbgregs, argp,
3376 sizeof(struct kvm_debugregs)))
3377 break;
3378
3379 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3380 break;
3381 }
2d5b5a66 3382 case KVM_GET_XSAVE: {
d1ac91d8 3383 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3384 r = -ENOMEM;
d1ac91d8 3385 if (!u.xsave)
2d5b5a66
SY		 3386 break;
3387
d1ac91d8 3388 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3389
3390 r = -EFAULT;
d1ac91d8 3391 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3392 break;
3393 r = 0;
3394 break;
3395 }
3396 case KVM_SET_XSAVE: {
ff5c2c03 3397 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3398 if (IS_ERR(u.xsave))
3399 return PTR_ERR(u.xsave);
2d5b5a66 3400
d1ac91d8 3401 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3402 break;
3403 }
3404 case KVM_GET_XCRS: {
d1ac91d8 3405 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3406 r = -ENOMEM;
d1ac91d8 3407 if (!u.xcrs)
2d5b5a66
SY		 3408 break;
3409
d1ac91d8 3410 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3411
3412 r = -EFAULT;
d1ac91d8 3413 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3414 sizeof(struct kvm_xcrs)))
3415 break;
3416 r = 0;
3417 break;
3418 }
3419 case KVM_SET_XCRS: {
ff5c2c03 3420 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3421 if (IS_ERR(u.xcrs))
3422 return PTR_ERR(u.xcrs);
2d5b5a66 3423
d1ac91d8 3424 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3425 break;
3426 }
92a1f12d
JR		 3427 case KVM_SET_TSC_KHZ: {
3428 u32 user_tsc_khz;
3429
3430 r = -EINVAL;
92a1f12d
JR		 3431 user_tsc_khz = (u32)arg;
3432
3433 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3434 goto out;
3435
cc578287
ZA		 3436 if (user_tsc_khz == 0)
3437 user_tsc_khz = tsc_khz;
3438
3439 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3440
3441 r = 0;
3442 goto out;
3443 }
3444 case KVM_GET_TSC_KHZ: {
cc578287 3445 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3446 goto out;
3447 }
1c0b28c2
EM		 3448 case KVM_KVMCLOCK_CTRL: {
3449 r = kvm_set_guest_paused(vcpu);
3450 goto out;
3451 }
313a3dc7
CO		 3452 default:
3453 r = -EINVAL;
3454 }
3455out:
d1ac91d8 3456 kfree(u.buffer);
313a3dc7
CO		 3457 return r;
3458}
3459
5b1c1493
CO		 3460int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3461{
3462 return VM_FAULT_SIGBUS;
3463}
3464
1fe779f8
CO		 3465static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3466{
3467 int ret;
3468
3469 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3470 return -EINVAL;
1fe779f8
CO		 3471 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3472 return ret;
3473}
3474
b927a3ce
SY		 3475static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3476 u64 ident_addr)
3477{
3478 kvm->arch.ept_identity_map_addr = ident_addr;
3479 return 0;
3480}
3481
1fe779f8
CO		 3482static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3483 u32 kvm_nr_mmu_pages)
3484{
3485 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3486 return -EINVAL;
3487
79fac95e 3488 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3489
3490 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3491 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3492
79fac95e 3493 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3494 return 0;
3495}
3496
3497static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3498{
39de71ec 3499 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3500}
3501
1fe779f8
CO		 3502static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3503{
3504 int r;
3505
3506 r = 0;
3507 switch (chip->chip_id) {
3508 case KVM_IRQCHIP_PIC_MASTER:
3509 memcpy(&chip->chip.pic,
3510 &pic_irqchip(kvm)->pics[0],
3511 sizeof(struct kvm_pic_state));
3512 break;
3513 case KVM_IRQCHIP_PIC_SLAVE:
3514 memcpy(&chip->chip.pic,
3515 &pic_irqchip(kvm)->pics[1],
3516 sizeof(struct kvm_pic_state));
3517 break;
3518 case KVM_IRQCHIP_IOAPIC:
eba0226b 3519 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3520 break;
3521 default:
3522 r = -EINVAL;
3523 break;
3524 }
3525 return r;
3526}
3527
3528static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3529{
3530 int r;
3531
3532 r = 0;
3533 switch (chip->chip_id) {
3534 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3535 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3536 memcpy(&pic_irqchip(kvm)->pics[0],
3537 &chip->chip.pic,
3538 sizeof(struct kvm_pic_state));
f4f51050 3539 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3540 break;
3541 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3542 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3543 memcpy(&pic_irqchip(kvm)->pics[1],
3544 &chip->chip.pic,
3545 sizeof(struct kvm_pic_state));
f4f51050 3546 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3547 break;
3548 case KVM_IRQCHIP_IOAPIC:
eba0226b 3549 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3550 break;
3551 default:
3552 r = -EINVAL;
3553 break;
3554 }
3555 kvm_pic_update_irq(pic_irqchip(kvm));
3556 return r;
3557}
3558
e0f63cb9
SY		 3559static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3560{
3561 int r = 0;
3562
894a9c55 3563 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3564 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3565 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3566 return r;
3567}
3568
3569static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3570{
3571 int r = 0;
3572
894a9c55 3573 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3574 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3575 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3576 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3577 return r;
3578}
3579
3580static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3581{
3582 int r = 0;
3583
3584 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3585 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3586 sizeof(ps->channels));
3587 ps->flags = kvm->arch.vpit->pit_state.flags;
3588 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3589 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3590 return r;
3591}
3592
3593static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3594{
3595 int r = 0, start = 0;
3596 u32 prev_legacy, cur_legacy;
3597 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3598 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3599 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3600 if (!prev_legacy && cur_legacy)
3601 start = 1;
3602 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3603 sizeof(kvm->arch.vpit->pit_state.channels));
3604 kvm->arch.vpit->pit_state.flags = ps->flags;
3605 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3606 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3607 return r;
3608}
3609
52d939a0
MT		 3610static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3611 struct kvm_reinject_control *control)
3612{
3613 if (!kvm->arch.vpit)
3614 return -ENXIO;
894a9c55 3615 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3616 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3617 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3618 return 0;
3619}
3620
95d4c16c 3621/**
60c34612
TY		 3622 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3623 * @kvm: kvm instance
3624 * @log: slot id and address to which we copy the log
95d4c16c 3625 *
60c34612
TY		 3626 * We need to keep it in mind that VCPU threads can write to the bitmap
3627 * concurrently. So, to avoid losing data, we keep the following order for
3628 * each bit:
95d4c16c 3629 *
60c34612
TY		 3630 * 1. Take a snapshot of the bit and clear it if needed.
3631 * 2. Write protect the corresponding page.
3632 * 3. Flush TLB's if needed.
3633 * 4. Copy the snapshot to the userspace.
95d4c16c 3634 *
60c34612
TY		 3635 * Between 2 and 3, the guest may write to the page using the remaining TLB
3636 * entry. This is not a problem because the page will be reported dirty at
3637 * step 4 using the snapshot taken before and step 3 ensures that successive
3638 * writes will be logged for the next call.
5bb064dc 3639 */
60c34612 3640int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3641{
7850ac54 3642 int r;
5bb064dc 3643 struct kvm_memory_slot *memslot;
60c34612
TY		 3644 unsigned long n, i;
3645 unsigned long *dirty_bitmap;
3646 unsigned long *dirty_bitmap_buffer;
3647 bool is_dirty = false;
5bb064dc 3648
79fac95e 3649 mutex_lock(&kvm->slots_lock);
5bb064dc 3650
b050b015 3651 r = -EINVAL;
bbacc0c1 3652 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3653 goto out;
3654
28a37544 3655 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3656
3657 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3658 r = -ENOENT;
60c34612 3659 if (!dirty_bitmap)
b050b015
MT		 3660 goto out;
3661
87bf6e7d 3662 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3663
60c34612
TY		 3664 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3665 memset(dirty_bitmap_buffer, 0, n);
b050b015 3666
60c34612 3667 spin_lock(&kvm->mmu_lock);
b050b015 3668
60c34612
TY		 3669 for (i = 0; i < n / sizeof(long); i++) {
3670 unsigned long mask;
3671 gfn_t offset;
cdfca7b3 3672
60c34612
TY		 3673 if (!dirty_bitmap[i])
3674 continue;
b050b015 3675
60c34612 3676 is_dirty = true;
914ebccd 3677
60c34612
TY		 3678 mask = xchg(&dirty_bitmap[i], 0);
3679 dirty_bitmap_buffer[i] = mask;
edde99ce 3680
60c34612
TY		 3681 offset = i * BITS_PER_LONG;
3682 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3683 }
60c34612
TY		 3684
3685 spin_unlock(&kvm->mmu_lock);
3686
198c74f4
XG		 3687 /* See the comments in kvm_mmu_slot_remove_write_access(). */
3688 lockdep_assert_held(&kvm->slots_lock);
3689
3690 /*
3691 * All the TLBs can be flushed out of mmu lock, see the comments in
3692 * kvm_mmu_slot_remove_write_access().
3693 */
3694 if (is_dirty)
3695 kvm_flush_remote_tlbs(kvm);
3696
60c34612
TY		 3697 r = -EFAULT;
3698 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3699 goto out;
b050b015 3700
5bb064dc
ZX		 3701 r = 0;
3702out:
79fac95e 3703 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3704 return r;
3705}
3706
aa2fbe6d
YZ		 3707int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3708 bool line_status)
23d43cf9
CD		 3709{
3710 if (!irqchip_in_kernel(kvm))
3711 return -ENXIO;
3712
3713 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3714 irq_event->irq, irq_event->level,
3715 line_status);
23d43cf9
CD		 3716 return 0;
3717}
3718
1fe779f8
CO		 3719long kvm_arch_vm_ioctl(struct file *filp,
3720 unsigned int ioctl, unsigned long arg)
3721{
3722 struct kvm *kvm = filp->private_data;
3723 void __user *argp = (void __user *)arg;
367e1319 3724 int r = -ENOTTY;
f0d66275
DH		 3725 /*
3726 * This union makes it completely explicit to gcc-3.x
3727 * that these two variables' stack usage should be
3728 * combined, not added together.
3729 */
3730 union {
3731 struct kvm_pit_state ps;
e9f42757 3732 struct kvm_pit_state2 ps2;
c5ff41ce 3733 struct kvm_pit_config pit_config;
f0d66275 3734 } u;
1fe779f8
CO		 3735
3736 switch (ioctl) {
3737 case KVM_SET_TSS_ADDR:
3738 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3739 break;
b927a3ce
SY		 3740 case KVM_SET_IDENTITY_MAP_ADDR: {
3741 u64 ident_addr;
3742
3743 r = -EFAULT;
3744 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3745 goto out;
3746 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3747 break;
3748 }
1fe779f8
CO		 3749 case KVM_SET_NR_MMU_PAGES:
3750 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3751 break;
3752 case KVM_GET_NR_MMU_PAGES:
3753 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3754 break;
3ddea128
MT		 3755 case KVM_CREATE_IRQCHIP: {
3756 struct kvm_pic *vpic;
3757
3758 mutex_lock(&kvm->lock);
3759 r = -EEXIST;
3760 if (kvm->arch.vpic)
3761 goto create_irqchip_unlock;
3e515705
AK		 3762 r = -EINVAL;
3763 if (atomic_read(&kvm->online_vcpus))
3764 goto create_irqchip_unlock;
1fe779f8 3765 r = -ENOMEM;
3ddea128
MT		 3766 vpic = kvm_create_pic(kvm);
3767 if (vpic) {
1fe779f8
CO		 3768 r = kvm_ioapic_init(kvm);
3769 if (r) {
175504cd 3770 mutex_lock(&kvm->slots_lock);
72bb2fcd 3771 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3772 &vpic->dev_master);
3773 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3774 &vpic->dev_slave);
3775 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3776 &vpic->dev_eclr);
175504cd 3777 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3778 kfree(vpic);
3779 goto create_irqchip_unlock;
1fe779f8
CO		 3780 }
3781 } else
3ddea128
MT		 3782 goto create_irqchip_unlock;
3783 smp_wmb();
3784 kvm->arch.vpic = vpic;
3785 smp_wmb();
399ec807
AK		 3786 r = kvm_setup_default_irq_routing(kvm);
3787 if (r) {
175504cd 3788 mutex_lock(&kvm->slots_lock);
3ddea128 3789 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3790 kvm_ioapic_destroy(kvm);
3791 kvm_destroy_pic(kvm);
3ddea128 3792 mutex_unlock(&kvm->irq_lock);
175504cd 3793 mutex_unlock(&kvm->slots_lock);
399ec807 3794 }
3ddea128
MT		 3795 create_irqchip_unlock:
3796 mutex_unlock(&kvm->lock);
1fe779f8 3797 break;
3ddea128 3798 }
7837699f 3799 case KVM_CREATE_PIT:
c5ff41ce
JK		 3800 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3801 goto create_pit;
3802 case KVM_CREATE_PIT2:
3803 r = -EFAULT;
3804 if (copy_from_user(&u.pit_config, argp,
3805 sizeof(struct kvm_pit_config)))
3806 goto out;
3807 create_pit:
79fac95e 3808 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3809 r = -EEXIST;
3810 if (kvm->arch.vpit)
3811 goto create_pit_unlock;
7837699f 3812 r = -ENOMEM;
c5ff41ce 3813 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3814 if (kvm->arch.vpit)
3815 r = 0;
269e05e4 3816 create_pit_unlock:
79fac95e 3817 mutex_unlock(&kvm->slots_lock);
7837699f 3818 break;
1fe779f8
CO		 3819 case KVM_GET_IRQCHIP: {
3820 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3821 struct kvm_irqchip *chip;
1fe779f8 3822
ff5c2c03
SL		 3823 chip = memdup_user(argp, sizeof(*chip));
3824 if (IS_ERR(chip)) {
3825 r = PTR_ERR(chip);
1fe779f8 3826 goto out;
ff5c2c03
SL		 3827 }
3828
1fe779f8
CO		 3829 r = -ENXIO;
3830 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3831 goto get_irqchip_out;
3832 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3833 if (r)
f0d66275 3834 goto get_irqchip_out;
1fe779f8 3835 r = -EFAULT;
f0d66275
DH		 3836 if (copy_to_user(argp, chip, sizeof *chip))
3837 goto get_irqchip_out;
1fe779f8 3838 r = 0;
f0d66275
DH		 3839 get_irqchip_out:
3840 kfree(chip);
1fe779f8
CO		 3841 break;
3842 }
3843 case KVM_SET_IRQCHIP: {
3844 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3845 struct kvm_irqchip *chip;
1fe779f8 3846
ff5c2c03
SL		 3847 chip = memdup_user(argp, sizeof(*chip));
3848 if (IS_ERR(chip)) {
3849 r = PTR_ERR(chip);
1fe779f8 3850 goto out;
ff5c2c03
SL		 3851 }
3852
1fe779f8
CO		 3853 r = -ENXIO;
3854 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3855 goto set_irqchip_out;
3856 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3857 if (r)
f0d66275 3858 goto set_irqchip_out;
1fe779f8 3859 r = 0;
f0d66275
DH		 3860 set_irqchip_out:
3861 kfree(chip);
1fe779f8
CO		 3862 break;
3863 }
e0f63cb9 3864 case KVM_GET_PIT: {
e0f63cb9 3865 r = -EFAULT;
f0d66275 3866 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3867 goto out;
3868 r = -ENXIO;
3869 if (!kvm->arch.vpit)
3870 goto out;
f0d66275 3871 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3872 if (r)
3873 goto out;
3874 r = -EFAULT;
f0d66275 3875 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3876 goto out;
3877 r = 0;
3878 break;
3879 }
3880 case KVM_SET_PIT: {
e0f63cb9 3881 r = -EFAULT;
f0d66275 3882 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3883 goto out;
3884 r = -ENXIO;
3885 if (!kvm->arch.vpit)
3886 goto out;
f0d66275 3887 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3888 break;
3889 }
e9f42757
BK		 3890 case KVM_GET_PIT2: {
3891 r = -ENXIO;
3892 if (!kvm->arch.vpit)
3893 goto out;
3894 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3895 if (r)
3896 goto out;
3897 r = -EFAULT;
3898 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3899 goto out;
3900 r = 0;
3901 break;
3902 }
3903 case KVM_SET_PIT2: {
3904 r = -EFAULT;
3905 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3906 goto out;
3907 r = -ENXIO;
3908 if (!kvm->arch.vpit)
3909 goto out;
3910 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3911 break;
3912 }
52d939a0
MT		 3913 case KVM_REINJECT_CONTROL: {
3914 struct kvm_reinject_control control;
3915 r = -EFAULT;
3916 if (copy_from_user(&control, argp, sizeof(control)))
3917 goto out;
3918 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3919 break;
3920 }
ffde22ac
ES		 3921 case KVM_XEN_HVM_CONFIG: {
3922 r = -EFAULT;
3923 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3924 sizeof(struct kvm_xen_hvm_config)))
3925 goto out;
3926 r = -EINVAL;
3927 if (kvm->arch.xen_hvm_config.flags)
3928 goto out;
3929 r = 0;
3930 break;
3931 }
afbcf7ab 3932 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3933 struct kvm_clock_data user_ns;
3934 u64 now_ns;
3935 s64 delta;
3936
3937 r = -EFAULT;
3938 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3939 goto out;
3940
3941 r = -EINVAL;
3942 if (user_ns.flags)
3943 goto out;
3944
3945 r = 0;
395c6b0a 3946 local_irq_disable();
759379dd 3947 now_ns = get_kernel_ns();
afbcf7ab 3948 delta = user_ns.clock - now_ns;
395c6b0a 3949 local_irq_enable();
afbcf7ab 3950 kvm->arch.kvmclock_offset = delta;
2e762ff7 3951 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3952 break;
3953 }
3954 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3955 struct kvm_clock_data user_ns;
3956 u64 now_ns;
3957
395c6b0a 3958 local_irq_disable();
759379dd 3959 now_ns = get_kernel_ns();
afbcf7ab 3960 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3961 local_irq_enable();
afbcf7ab 3962 user_ns.flags = 0;
97e69aa6 3963 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3964
3965 r = -EFAULT;
3966 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3967 goto out;
3968 r = 0;
3969 break;
3970 }
3971
1fe779f8
CO		 3972 default:
3973 ;
3974 }
3975out:
3976 return r;
3977}
3978
a16b043c 3979static void kvm_init_msr_list(void)
043405e1
CO		 3980{
3981 u32 dummy[2];
3982 unsigned i, j;
3983
e3267cbb
GC		 3984 /* skip the first msrs in the list. KVM-specific */
3985 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3986 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3987 continue;
93c4adc7
PB		 3988
3989 /*
3990 * Even MSRs that are valid in the host may not be exposed
3991 * to the guests in some cases. We could work around this
3992 * in VMX with the generic MSR save/load machinery, but it
3993 * is not really worthwhile since it will really only
3994 * happen with nested virtualization.
3995 */
3996 switch (msrs_to_save[i]) {
3997 case MSR_IA32_BNDCFGS:
3998 if (!kvm_x86_ops->mpx_supported())
3999 continue;
4000 break;
4001 default:
4002 break;
4003 }
4004
043405e1
CO		 4005 if (j < i)
4006 msrs_to_save[j] = msrs_to_save[i];
4007 j++;
4008 }
4009 num_msrs_to_save = j;
4010}
4011
bda9020e
MT		 4012static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4013 const void *v)
bbd9b64e 4014{
70252a10
AK		 4015 int handled = 0;
4016 int n;
4017
4018 do {
4019 n = min(len, 8);
4020 if (!(vcpu->arch.apic &&
4021 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
4022 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4023 break;
4024 handled += n;
4025 addr += n;
4026 len -= n;
4027 v += n;
4028 } while (len);
bbd9b64e 4029
70252a10 4030 return handled;
bbd9b64e
CO		 4031}
4032
bda9020e 4033static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4034{
70252a10
AK		 4035 int handled = 0;
4036 int n;
4037
4038 do {
4039 n = min(len, 8);
4040 if (!(vcpu->arch.apic &&
4041 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
4042 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
4043 break;
4044 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4045 handled += n;
4046 addr += n;
4047 len -= n;
4048 v += n;
4049 } while (len);
bbd9b64e 4050
70252a10 4051 return handled;
bbd9b64e
CO		 4052}
4053
2dafc6c2
GN		 4054static void kvm_set_segment(struct kvm_vcpu *vcpu,
4055 struct kvm_segment *var, int seg)
4056{
4057 kvm_x86_ops->set_segment(vcpu, var, seg);
4058}
4059
4060void kvm_get_segment(struct kvm_vcpu *vcpu,
4061 struct kvm_segment *var, int seg)
4062{
4063 kvm_x86_ops->get_segment(vcpu, var, seg);
4064}
4065
e459e322 4066gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 4067{
4068 gpa_t t_gpa;
ab9ae313 4069 struct x86_exception exception;
02f59dc9
JR		 4070
4071 BUG_ON(!mmu_is_nested(vcpu));
4072
4073 /* NPT walks are always user-walks */
4074 access |= PFERR_USER_MASK;
ab9ae313 4075 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 4076
4077 return t_gpa;
4078}
4079
ab9ae313
AK		 4080gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4081 struct x86_exception *exception)
1871c602
GN		 4082{
4083 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4084 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4085}
4086
ab9ae313
AK		 4087 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4088 struct x86_exception *exception)
1871c602
GN		 4089{
4090 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4091 access |= PFERR_FETCH_MASK;
ab9ae313 4092 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4093}
4094
ab9ae313
AK		 4095gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4096 struct x86_exception *exception)
1871c602
GN		 4097{
4098 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4099 access |= PFERR_WRITE_MASK;
ab9ae313 4100 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4101}
4102
4103/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4104gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4105 struct x86_exception *exception)
1871c602 4106{
ab9ae313 4107 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4108}
4109
4110static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4111 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4112 struct x86_exception *exception)
bbd9b64e
CO		 4113{
4114 void *data = val;
10589a46 4115 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4116
4117 while (bytes) {
14dfe855 4118 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4119 exception);
bbd9b64e 4120 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4121 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4122 int ret;
4123
bcc55cba 4124 if (gpa == UNMAPPED_GVA)
ab9ae313 4125 return X86EMUL_PROPAGATE_FAULT;
44583cba
PB		 4126 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, data,
4127 offset, toread);
10589a46 4128 if (ret < 0) {
c3cd7ffa 4129 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4130 goto out;
4131 }
bbd9b64e 4132
77c2002e
IE		 4133 bytes -= toread;
4134 data += toread;
4135 addr += toread;
bbd9b64e 4136 }
10589a46 4137out:
10589a46 4138 return r;
bbd9b64e 4139}
77c2002e 4140
1871c602 4141/* used for instruction fetching */
0f65dd70
AK		 4142static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4143 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4144 struct x86_exception *exception)
1871c602 4145{
0f65dd70 4146 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4147 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4148 unsigned offset;
4149 int ret;
0f65dd70 4150
44583cba
PB		 4151 /* Inline kvm_read_guest_virt_helper for speed. */
4152 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4153 exception);
4154 if (unlikely(gpa == UNMAPPED_GVA))
4155 return X86EMUL_PROPAGATE_FAULT;
4156
4157 offset = addr & (PAGE_SIZE-1);
4158 if (WARN_ON(offset + bytes > PAGE_SIZE))
4159 bytes = (unsigned)PAGE_SIZE - offset;
4160 ret = kvm_read_guest_page(vcpu->kvm, gpa >> PAGE_SHIFT, val,
4161 offset, bytes);
4162 if (unlikely(ret < 0))
4163 return X86EMUL_IO_NEEDED;
4164
4165 return X86EMUL_CONTINUE;
1871c602
GN		 4166}
4167
064aea77 4168int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4169 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4170 struct x86_exception *exception)
1871c602 4171{
0f65dd70 4172 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4173 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4174
1871c602 4175 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4176 exception);
1871c602 4177}
064aea77 4178EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4179
0f65dd70
AK		 4180static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4181 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4182 struct x86_exception *exception)
1871c602 4183{
0f65dd70 4184 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4185 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4186}
4187
6a4d7550 4188int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4189 gva_t addr, void *val,
2dafc6c2 4190 unsigned int bytes,
bcc55cba 4191 struct x86_exception *exception)
77c2002e 4192{
0f65dd70 4193 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4194 void *data = val;
4195 int r = X86EMUL_CONTINUE;
4196
4197 while (bytes) {
14dfe855
JR		 4198 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4199 PFERR_WRITE_MASK,
ab9ae313 4200 exception);
77c2002e
IE		 4201 unsigned offset = addr & (PAGE_SIZE-1);
4202 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4203 int ret;
4204
bcc55cba 4205 if (gpa == UNMAPPED_GVA)
ab9ae313 4206 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4207 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4208 if (ret < 0) {
c3cd7ffa 4209 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4210 goto out;
4211 }
4212
4213 bytes -= towrite;
4214 data += towrite;
4215 addr += towrite;
4216 }
4217out:
4218 return r;
4219}
6a4d7550 4220EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4221
af7cc7d1
XG		 4222static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4223 gpa_t *gpa, struct x86_exception *exception,
4224 bool write)
4225{
97d64b78
AK		 4226 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4227 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4228
97d64b78 4229 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4230 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4231 vcpu->arch.access, access)) {
bebb106a
XG		 4232 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4233 (gva & (PAGE_SIZE - 1));
4f022648 4234 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4235 return 1;
4236 }
4237
af7cc7d1
XG		 4238 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4239
4240 if (*gpa == UNMAPPED_GVA)
4241 return -1;
4242
4243 /* For APIC access vmexit */
4244 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4245 return 1;
4246
4f022648
XG		 4247 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4248 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4249 return 1;
4f022648 4250 }
bebb106a 4251
af7cc7d1
XG		 4252 return 0;
4253}
4254
3200f405 4255int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4256 const void *val, int bytes)
bbd9b64e
CO		 4257{
4258 int ret;
4259
4260 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4261 if (ret < 0)
bbd9b64e 4262 return 0;
f57f2ef5 4263 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4264 return 1;
4265}
4266
77d197b2
XG		 4267struct read_write_emulator_ops {
4268 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4269 int bytes);
4270 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4271 void *val, int bytes);
4272 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4273 int bytes, void *val);
4274 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4275 void *val, int bytes);
4276 bool write;
4277};
4278
4279static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4280{
4281 if (vcpu->mmio_read_completed) {
77d197b2 4282 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4283 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4284 vcpu->mmio_read_completed = 0;
4285 return 1;
4286 }
4287
4288 return 0;
4289}
4290
4291static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4292 void *val, int bytes)
4293{
4294 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4295}
4296
4297static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4298 void *val, int bytes)
4299{
4300 return emulator_write_phys(vcpu, gpa, val, bytes);
4301}
4302
4303static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4304{
4305 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4306 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4307}
4308
4309static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4310 void *val, int bytes)
4311{
4312 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4313 return X86EMUL_IO_NEEDED;
4314}
4315
4316static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4317 void *val, int bytes)
4318{
f78146b0
AK		 4319 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4320
87da7e66 4321 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4322 return X86EMUL_CONTINUE;
4323}
4324
0fbe9b0b 4325static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4326 .read_write_prepare = read_prepare,
4327 .read_write_emulate = read_emulate,
4328 .read_write_mmio = vcpu_mmio_read,
4329 .read_write_exit_mmio = read_exit_mmio,
4330};
4331
0fbe9b0b 4332static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4333 .read_write_emulate = write_emulate,
4334 .read_write_mmio = write_mmio,
4335 .read_write_exit_mmio = write_exit_mmio,
4336 .write = true,
4337};
4338
22388a3c
XG		 4339static int emulator_read_write_onepage(unsigned long addr, void *val,
4340 unsigned int bytes,
4341 struct x86_exception *exception,
4342 struct kvm_vcpu *vcpu,
0fbe9b0b 4343 const struct read_write_emulator_ops *ops)
bbd9b64e 4344{
af7cc7d1
XG		 4345 gpa_t gpa;
4346 int handled, ret;
22388a3c 4347 bool write = ops->write;
f78146b0 4348 struct kvm_mmio_fragment *frag;
10589a46 4349
22388a3c 4350 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4351
af7cc7d1 4352 if (ret < 0)
bbd9b64e 4353 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4354
4355 /* For APIC access vmexit */
af7cc7d1 4356 if (ret)
bbd9b64e
CO		 4357 goto mmio;
4358
22388a3c 4359 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4360 return X86EMUL_CONTINUE;
4361
4362mmio:
4363 /*
4364 * Is this MMIO handled locally?
4365 */
22388a3c 4366 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4367 if (handled == bytes)
bbd9b64e 4368 return X86EMUL_CONTINUE;
bbd9b64e 4369
70252a10
AK		 4370 gpa += handled;
4371 bytes -= handled;
4372 val += handled;
4373
87da7e66
XG		 4374 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4375 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4376 frag->gpa = gpa;
4377 frag->data = val;
4378 frag->len = bytes;
f78146b0 4379 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4380}
4381
22388a3c
XG		 4382int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4383 void *val, unsigned int bytes,
4384 struct x86_exception *exception,
0fbe9b0b 4385 const struct read_write_emulator_ops *ops)
bbd9b64e 4386{
0f65dd70 4387 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4388 gpa_t gpa;
4389 int rc;
4390
4391 if (ops->read_write_prepare &&
4392 ops->read_write_prepare(vcpu, val, bytes))
4393 return X86EMUL_CONTINUE;
4394
4395 vcpu->mmio_nr_fragments = 0;
0f65dd70 4396
bbd9b64e
CO		 4397 /* Crossing a page boundary? */
4398 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4399 int now;
bbd9b64e
CO		 4400
4401 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4402 rc = emulator_read_write_onepage(addr, val, now, exception,
4403 vcpu, ops);
4404
bbd9b64e
CO		 4405 if (rc != X86EMUL_CONTINUE)
4406 return rc;
4407 addr += now;
4408 val += now;
4409 bytes -= now;
4410 }
22388a3c 4411
f78146b0
AK		 4412 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4413 vcpu, ops);
4414 if (rc != X86EMUL_CONTINUE)
4415 return rc;
4416
4417 if (!vcpu->mmio_nr_fragments)
4418 return rc;
4419
4420 gpa = vcpu->mmio_fragments[0].gpa;
4421
4422 vcpu->mmio_needed = 1;
4423 vcpu->mmio_cur_fragment = 0;
4424
87da7e66 4425 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4426 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4427 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4428 vcpu->run->mmio.phys_addr = gpa;
4429
4430 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4431}
4432
4433static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4434 unsigned long addr,
4435 void *val,
4436 unsigned int bytes,
4437 struct x86_exception *exception)
4438{
4439 return emulator_read_write(ctxt, addr, val, bytes,
4440 exception, &read_emultor);
4441}
4442
4443int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4444 unsigned long addr,
4445 const void *val,
4446 unsigned int bytes,
4447 struct x86_exception *exception)
4448{
4449 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4450 exception, &write_emultor);
bbd9b64e 4451}
bbd9b64e 4452
daea3e73
AK		 4453#define CMPXCHG_TYPE(t, ptr, old, new) \
4454 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4455
4456#ifdef CONFIG_X86_64
4457# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4458#else
4459# define CMPXCHG64(ptr, old, new) \
9749a6c0 4460 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4461#endif
4462
0f65dd70
AK		 4463static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4464 unsigned long addr,
bbd9b64e
CO		 4465 const void *old,
4466 const void *new,
4467 unsigned int bytes,
0f65dd70 4468 struct x86_exception *exception)
bbd9b64e 4469{
0f65dd70 4470 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4471 gpa_t gpa;
4472 struct page *page;
4473 char *kaddr;
4474 bool exchanged;
2bacc55c 4475
daea3e73
AK		 4476 /* guests cmpxchg8b have to be emulated atomically */
4477 if (bytes > 8 || (bytes & (bytes - 1)))
4478 goto emul_write;
10589a46 4479
daea3e73 4480 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4481
daea3e73
AK		 4482 if (gpa == UNMAPPED_GVA ||
4483 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4484 goto emul_write;
2bacc55c 4485
daea3e73
AK		 4486 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4487 goto emul_write;
72dc67a6 4488
daea3e73 4489 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4490 if (is_error_page(page))
c19b8bd6 4491 goto emul_write;
72dc67a6 4492
8fd75e12 4493 kaddr = kmap_atomic(page);
daea3e73
AK		 4494 kaddr += offset_in_page(gpa);
4495 switch (bytes) {
4496 case 1:
4497 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4498 break;
4499 case 2:
4500 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4501 break;
4502 case 4:
4503 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4504 break;
4505 case 8:
4506 exchanged = CMPXCHG64(kaddr, old, new);
4507 break;
4508 default:
4509 BUG();
2bacc55c 4510 }
8fd75e12 4511 kunmap_atomic(kaddr);
daea3e73
AK		 4512 kvm_release_page_dirty(page);
4513
4514 if (!exchanged)
4515 return X86EMUL_CMPXCHG_FAILED;
4516
d3714010 4517 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4518 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4519
4520 return X86EMUL_CONTINUE;
4a5f48f6 4521
3200f405 4522emul_write:
daea3e73 4523 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4524
0f65dd70 4525 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4526}
4527
cf8f70bf
GN		 4528static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4529{
4530 /* TODO: String I/O for in kernel device */
4531 int r;
4532
4533 if (vcpu->arch.pio.in)
4534 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4535 vcpu->arch.pio.size, pd);
4536 else
4537 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4538 vcpu->arch.pio.port, vcpu->arch.pio.size,
4539 pd);
4540 return r;
4541}
4542
6f6fbe98
XG		 4543static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4544 unsigned short port, void *val,
4545 unsigned int count, bool in)
cf8f70bf 4546{
cf8f70bf 4547 vcpu->arch.pio.port = port;
6f6fbe98 4548 vcpu->arch.pio.in = in;
7972995b 4549 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4550 vcpu->arch.pio.size = size;
4551
4552 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4553 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4554 return 1;
4555 }
4556
4557 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4558 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4559 vcpu->run->io.size = size;
4560 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4561 vcpu->run->io.count = count;
4562 vcpu->run->io.port = port;
4563
4564 return 0;
4565}
4566
6f6fbe98
XG		 4567static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4568 int size, unsigned short port, void *val,
4569 unsigned int count)
cf8f70bf 4570{
ca1d4a9e 4571 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4572 int ret;
ca1d4a9e 4573
6f6fbe98
XG		 4574 if (vcpu->arch.pio.count)
4575 goto data_avail;
cf8f70bf 4576
6f6fbe98
XG		 4577 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4578 if (ret) {
4579data_avail:
4580 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4581 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4582 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4583 return 1;
4584 }
4585
cf8f70bf
GN		 4586 return 0;
4587}
4588
6f6fbe98
XG		 4589static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4590 int size, unsigned short port,
4591 const void *val, unsigned int count)
4592{
4593 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4594
4595 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4596 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4597 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4598}
4599
bbd9b64e
CO		 4600static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4601{
4602 return kvm_x86_ops->get_segment_base(vcpu, seg);
4603}
4604
3cb16fe7 4605static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4606{
3cb16fe7 4607 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4608}
4609
f5f48ee1
SY		 4610int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4611{
4612 if (!need_emulate_wbinvd(vcpu))
4613 return X86EMUL_CONTINUE;
4614
4615 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4616 int cpu = get_cpu();
4617
4618 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4619 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4620 wbinvd_ipi, NULL, 1);
2eec7343 4621 put_cpu();
f5f48ee1 4622 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4623 } else
4624 wbinvd();
f5f48ee1
SY		 4625 return X86EMUL_CONTINUE;
4626}
4627EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4628
bcaf5cc5
AK		 4629static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4630{
4631 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4632}
4633
717746e3 4634int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4635{
717746e3 4636 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4637}
4638
717746e3 4639int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4640{
338dbc97 4641
717746e3 4642 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4643}
4644
52a46617 4645static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4646{
52a46617 4647 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4648}
4649
717746e3 4650static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4651{
717746e3 4652 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4653 unsigned long value;
4654
4655 switch (cr) {
4656 case 0:
4657 value = kvm_read_cr0(vcpu);
4658 break;
4659 case 2:
4660 value = vcpu->arch.cr2;
4661 break;
4662 case 3:
9f8fe504 4663 value = kvm_read_cr3(vcpu);
52a46617
GN		 4664 break;
4665 case 4:
4666 value = kvm_read_cr4(vcpu);
4667 break;
4668 case 8:
4669 value = kvm_get_cr8(vcpu);
4670 break;
4671 default:
a737f256 4672 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4673 return 0;
4674 }
4675
4676 return value;
4677}
4678
717746e3 4679static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4680{
717746e3 4681 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4682 int res = 0;
4683
52a46617
GN		 4684 switch (cr) {
4685 case 0:
49a9b07e 4686 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4687 break;
4688 case 2:
4689 vcpu->arch.cr2 = val;
4690 break;
4691 case 3:
2390218b 4692 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4693 break;
4694 case 4:
a83b29c6 4695 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4696 break;
4697 case 8:
eea1cff9 4698 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4699 break;
4700 default:
a737f256 4701 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4702 res = -1;
52a46617 4703 }
0f12244f
GN		 4704
4705 return res;
52a46617
GN		 4706}
4707
717746e3 4708static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4709{
717746e3 4710 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4711}
4712
4bff1e86 4713static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4714{
4bff1e86 4715 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4716}
4717
4bff1e86 4718static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4719{
4bff1e86 4720 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4721}
4722
1ac9d0cf
AK		 4723static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4724{
4725 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4726}
4727
4728static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4729{
4730 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4731}
4732
4bff1e86
AK		 4733static unsigned long emulator_get_cached_segment_base(
4734 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4735{
4bff1e86 4736 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4737}
4738
1aa36616
AK		 4739static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4740 struct desc_struct *desc, u32 *base3,
4741 int seg)
2dafc6c2
GN		 4742{
4743 struct kvm_segment var;
4744
4bff1e86 4745 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4746 *selector = var.selector;
2dafc6c2 4747
378a8b09
GN		 4748 if (var.unusable) {
4749 memset(desc, 0, sizeof(*desc));
2dafc6c2 4750 return false;
378a8b09 4751 }
2dafc6c2
GN		 4752
4753 if (var.g)
4754 var.limit >>= 12;
4755 set_desc_limit(desc, var.limit);
4756 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4757#ifdef CONFIG_X86_64
4758 if (base3)
4759 *base3 = var.base >> 32;
4760#endif
2dafc6c2
GN		 4761 desc->type = var.type;
4762 desc->s = var.s;
4763 desc->dpl = var.dpl;
4764 desc->p = var.present;
4765 desc->avl = var.avl;
4766 desc->l = var.l;
4767 desc->d = var.db;
4768 desc->g = var.g;
4769
4770 return true;
4771}
4772
1aa36616
AK		 4773static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4774 struct desc_struct *desc, u32 base3,
4775 int seg)
2dafc6c2 4776{
4bff1e86 4777 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4778 struct kvm_segment var;
4779
1aa36616 4780 var.selector = selector;
2dafc6c2 4781 var.base = get_desc_base(desc);
5601d05b
GN		 4782#ifdef CONFIG_X86_64
4783 var.base |= ((u64)base3) << 32;
4784#endif
2dafc6c2
GN		 4785 var.limit = get_desc_limit(desc);
4786 if (desc->g)
4787 var.limit = (var.limit << 12) | 0xfff;
4788 var.type = desc->type;
2dafc6c2
GN		 4789 var.dpl = desc->dpl;
4790 var.db = desc->d;
4791 var.s = desc->s;
4792 var.l = desc->l;
4793 var.g = desc->g;
4794 var.avl = desc->avl;
4795 var.present = desc->p;
4796 var.unusable = !var.present;
4797 var.padding = 0;
4798
4799 kvm_set_segment(vcpu, &var, seg);
4800 return;
4801}
4802
717746e3
AK		 4803static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4804 u32 msr_index, u64 *pdata)
4805{
4806 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4807}
4808
4809static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4810 u32 msr_index, u64 data)
4811{
8fe8ab46
WA		 4812 struct msr_data msr;
4813
4814 msr.data = data;
4815 msr.index = msr_index;
4816 msr.host_initiated = false;
4817 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4818}
4819
67f4d428
NA		 4820static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4821 u32 pmc)
4822{
4823 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4824}
4825
222d21aa
AK		 4826static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4827 u32 pmc, u64 *pdata)
4828{
4829 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4830}
4831
6c3287f7
AK		 4832static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4833{
4834 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4835}
4836
5037f6f3
AK		 4837static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4838{
4839 preempt_disable();
5197b808 4840 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4841 /*
4842 * CR0.TS may reference the host fpu state, not the guest fpu state,
4843 * so it may be clear at this point.
4844 */
4845 clts();
4846}
4847
4848static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4849{
4850 preempt_enable();
4851}
4852
2953538e 4853static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4854 struct x86_instruction_info *info,
c4f035c6
AK		 4855 enum x86_intercept_stage stage)
4856{
2953538e 4857 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4858}
4859
0017f93a 4860static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4861 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4862{
0017f93a 4863 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4864}
4865
dd856efa
AK		 4866static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4867{
4868 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4869}
4870
4871static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4872{
4873 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4874}
4875
0225fb50 4876static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4877 .read_gpr = emulator_read_gpr,
4878 .write_gpr = emulator_write_gpr,
1871c602 4879 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4880 .write_std = kvm_write_guest_virt_system,
1871c602 4881 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4882 .read_emulated = emulator_read_emulated,
4883 .write_emulated = emulator_write_emulated,
4884 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4885 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4886 .pio_in_emulated = emulator_pio_in_emulated,
4887 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4888 .get_segment = emulator_get_segment,
4889 .set_segment = emulator_set_segment,
5951c442 4890 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4891 .get_gdt = emulator_get_gdt,
160ce1f1 4892 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4893 .set_gdt = emulator_set_gdt,
4894 .set_idt = emulator_set_idt,
52a46617
GN		 4895 .get_cr = emulator_get_cr,
4896 .set_cr = emulator_set_cr,
9c537244 4897 .cpl = emulator_get_cpl,
35aa5375
GN		 4898 .get_dr = emulator_get_dr,
4899 .set_dr = emulator_set_dr,
717746e3
AK		 4900 .set_msr = emulator_set_msr,
4901 .get_msr = emulator_get_msr,
67f4d428 4902 .check_pmc = emulator_check_pmc,
222d21aa 4903 .read_pmc = emulator_read_pmc,
6c3287f7 4904 .halt = emulator_halt,
bcaf5cc5 4905 .wbinvd = emulator_wbinvd,
d6aa1000 4906 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4907 .get_fpu = emulator_get_fpu,
4908 .put_fpu = emulator_put_fpu,
c4f035c6 4909 .intercept = emulator_intercept,
bdb42f5a 4910 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4911};
4912
95cb2295
GN		 4913static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4914{
37ccdcbe 4915 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 4916 /*
4917 * an sti; sti; sequence only disable interrupts for the first
4918 * instruction. So, if the last instruction, be it emulated or
4919 * not, left the system with the INT_STI flag enabled, it
4920 * means that the last instruction is an sti. We should not
4921 * leave the flag on in this case. The same goes for mov ss
4922 */
37ccdcbe
PB		 4923 if (int_shadow & mask)
4924 mask = 0;
6addfc42 4925 if (unlikely(int_shadow || mask)) {
95cb2295 4926 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 4927 if (!mask)
4928 kvm_make_request(KVM_REQ_EVENT, vcpu);
4929 }
95cb2295
GN		 4930}
4931
54b8486f
GN		 4932static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4933{
4934 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4935 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4936 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4937 else if (ctxt->exception.error_code_valid)
4938 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4939 ctxt->exception.error_code);
54b8486f 4940 else
da9cb575 4941 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4942}
4943
8ec4722d
MG		 4944static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4945{
adf52235 4946 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4947 int cs_db, cs_l;
4948
8ec4722d
MG		 4949 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4950
adf52235
TY		 4951 ctxt->eflags = kvm_get_rflags(vcpu);
4952 ctxt->eip = kvm_rip_read(vcpu);
4953 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4954 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 4955 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 4956 cs_db ? X86EMUL_MODE_PROT32 :
4957 X86EMUL_MODE_PROT16;
4958 ctxt->guest_mode = is_guest_mode(vcpu);
4959
dd856efa 4960 init_decode_cache(ctxt);
7ae441ea 4961 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4962}
4963
71f9833b 4964int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4965{
9d74191a 4966 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4967 int ret;
4968
4969 init_emulate_ctxt(vcpu);
4970
9dac77fa
AK		 4971 ctxt->op_bytes = 2;
4972 ctxt->ad_bytes = 2;
4973 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4974 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4975
4976 if (ret != X86EMUL_CONTINUE)
4977 return EMULATE_FAIL;
4978
9dac77fa 4979 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4980 kvm_rip_write(vcpu, ctxt->eip);
4981 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4982
4983 if (irq == NMI_VECTOR)
7460fb4a 4984 vcpu->arch.nmi_pending = 0;
63995653
MG		 4985 else
4986 vcpu->arch.interrupt.pending = false;
4987
4988 return EMULATE_DONE;
4989}
4990EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4991
6d77dbfc
GN		 4992static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4993{
fc3a9157
JR		 4994 int r = EMULATE_DONE;
4995
6d77dbfc
GN		 4996 ++vcpu->stat.insn_emulation_fail;
4997 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4998 if (!is_guest_mode(vcpu)) {
4999 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5000 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5001 vcpu->run->internal.ndata = 0;
5002 r = EMULATE_FAIL;
5003 }
6d77dbfc 5004 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5005
5006 return r;
6d77dbfc
GN		 5007}
5008
93c05d3e 5009static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5010 bool write_fault_to_shadow_pgtable,
5011 int emulation_type)
a6f177ef 5012{
95b3cf69 5013 gpa_t gpa = cr2;
8e3d9d06 5014 pfn_t pfn;
a6f177ef 5015
991eebf9
GN		 5016 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5017 return false;
5018
95b3cf69
XG		 5019 if (!vcpu->arch.mmu.direct_map) {
5020 /*
5021 * Write permission should be allowed since only
5022 * write access need to be emulated.
5023 */
5024 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5025
95b3cf69
XG		 5026 /*
5027 * If the mapping is invalid in guest, let cpu retry
5028 * it to generate fault.
5029 */
5030 if (gpa == UNMAPPED_GVA)
5031 return true;
5032 }
a6f177ef 5033
8e3d9d06
XG		 5034 /*
5035 * Do not retry the unhandleable instruction if it faults on the
5036 * readonly host memory, otherwise it will goto a infinite loop:
5037 * retry instruction -> write #PF -> emulation fail -> retry
5038 * instruction -> ...
5039 */
5040 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5041
5042 /*
5043 * If the instruction failed on the error pfn, it can not be fixed,
5044 * report the error to userspace.
5045 */
5046 if (is_error_noslot_pfn(pfn))
5047 return false;
5048
5049 kvm_release_pfn_clean(pfn);
5050
5051 /* The instructions are well-emulated on direct mmu. */
5052 if (vcpu->arch.mmu.direct_map) {
5053 unsigned int indirect_shadow_pages;
5054
5055 spin_lock(&vcpu->kvm->mmu_lock);
5056 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5057 spin_unlock(&vcpu->kvm->mmu_lock);
5058
5059 if (indirect_shadow_pages)
5060 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5061
a6f177ef 5062 return true;
8e3d9d06 5063 }
a6f177ef 5064
95b3cf69
XG		 5065 /*
5066 * if emulation was due to access to shadowed page table
5067 * and it failed try to unshadow page and re-enter the
5068 * guest to let CPU execute the instruction.
5069 */
5070 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5071
5072 /*
5073 * If the access faults on its page table, it can not
5074 * be fixed by unprotecting shadow page and it should
5075 * be reported to userspace.
5076 */
5077 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5078}
5079
1cb3f3ae
XG		 5080static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5081 unsigned long cr2, int emulation_type)
5082{
5083 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5084 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5085
5086 last_retry_eip = vcpu->arch.last_retry_eip;
5087 last_retry_addr = vcpu->arch.last_retry_addr;
5088
5089 /*
5090 * If the emulation is caused by #PF and it is non-page_table
5091 * writing instruction, it means the VM-EXIT is caused by shadow
5092 * page protected, we can zap the shadow page and retry this
5093 * instruction directly.
5094 *
5095 * Note: if the guest uses a non-page-table modifying instruction
5096 * on the PDE that points to the instruction, then we will unmap
5097 * the instruction and go to an infinite loop. So, we cache the
5098 * last retried eip and the last fault address, if we meet the eip
5099 * and the address again, we can break out of the potential infinite
5100 * loop.
5101 */
5102 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5103
5104 if (!(emulation_type & EMULTYPE_RETRY))
5105 return false;
5106
5107 if (x86_page_table_writing_insn(ctxt))
5108 return false;
5109
5110 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5111 return false;
5112
5113 vcpu->arch.last_retry_eip = ctxt->eip;
5114 vcpu->arch.last_retry_addr = cr2;
5115
5116 if (!vcpu->arch.mmu.direct_map)
5117 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5118
22368028 5119 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5120
5121 return true;
5122}
5123
716d51ab
GN		 5124static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5125static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5126
4a1e10d5
PB		 5127static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5128 unsigned long *db)
5129{
5130 u32 dr6 = 0;
5131 int i;
5132 u32 enable, rwlen;
5133
5134 enable = dr7;
5135 rwlen = dr7 >> 16;
5136 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5137 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5138 dr6 |= (1 << i);
5139 return dr6;
5140}
5141
6addfc42 5142static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5143{
5144 struct kvm_run *kvm_run = vcpu->run;
5145
5146 /*
6addfc42
PB		 5147 * rflags is the old, "raw" value of the flags. The new value has
5148 * not been saved yet.
663f4c61
PB		 5149 *
5150 * This is correct even for TF set by the guest, because "the
5151 * processor will not generate this exception after the instruction
5152 * that sets the TF flag".
5153 */
663f4c61
PB		 5154 if (unlikely(rflags & X86_EFLAGS_TF)) {
5155 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5156 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5157 DR6_RTM;
663f4c61
PB		 5158 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5159 kvm_run->debug.arch.exception = DB_VECTOR;
5160 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5161 *r = EMULATE_USER_EXIT;
5162 } else {
5163 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5164 /*
5165 * "Certain debug exceptions may clear bit 0-3. The
5166 * remaining contents of the DR6 register are never
5167 * cleared by the processor".
5168 */
5169 vcpu->arch.dr6 &= ~15;
6f43ed01 5170 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5171 kvm_queue_exception(vcpu, DB_VECTOR);
5172 }
5173 }
5174}
5175
4a1e10d5
PB		 5176static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5177{
5178 struct kvm_run *kvm_run = vcpu->run;
5179 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5180 u32 dr6 = 0;
5181
5182 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5183 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5184 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5185 vcpu->arch.guest_debug_dr7,
5186 vcpu->arch.eff_db);
5187
5188 if (dr6 != 0) {
6f43ed01 5189 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
4a1e10d5
PB		 5190 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5191 get_segment_base(vcpu, VCPU_SREG_CS);
5192
5193 kvm_run->debug.arch.exception = DB_VECTOR;
5194 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5195 *r = EMULATE_USER_EXIT;
5196 return true;
5197 }
5198 }
5199
4161a569
NA		 5200 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5201 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
4a1e10d5
PB		 5202 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5203 vcpu->arch.dr7,
5204 vcpu->arch.db);
5205
5206 if (dr6 != 0) {
5207 vcpu->arch.dr6 &= ~15;
6f43ed01 5208 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5209 kvm_queue_exception(vcpu, DB_VECTOR);
5210 *r = EMULATE_DONE;
5211 return true;
5212 }
5213 }
5214
5215 return false;
5216}
5217
51d8b661
AP		 5218int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5219 unsigned long cr2,
dc25e89e
AP		 5220 int emulation_type,
5221 void *insn,
5222 int insn_len)
bbd9b64e 5223{
95cb2295 5224 int r;
9d74191a 5225 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5226 bool writeback = true;
93c05d3e 5227 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5228
93c05d3e
XG		 5229 /*
5230 * Clear write_fault_to_shadow_pgtable here to ensure it is
5231 * never reused.
5232 */
5233 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5234 kvm_clear_exception_queue(vcpu);
8d7d8102 5235
571008da 5236 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5237 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5238
5239 /*
5240 * We will reenter on the same instruction since
5241 * we do not set complete_userspace_io. This does not
5242 * handle watchpoints yet, those would be handled in
5243 * the emulate_ops.
5244 */
5245 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5246 return r;
5247
9d74191a
TY		 5248 ctxt->interruptibility = 0;
5249 ctxt->have_exception = false;
e0ad0b47 5250 ctxt->exception.vector = -1;
9d74191a 5251 ctxt->perm_ok = false;
bbd9b64e 5252
b51e974f 5253 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5254
9d74191a 5255 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5256
e46479f8 5257 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5258 ++vcpu->stat.insn_emulation;
1d2887e2 5259 if (r != EMULATION_OK) {
4005996e
AK		 5260 if (emulation_type & EMULTYPE_TRAP_UD)
5261 return EMULATE_FAIL;
991eebf9
GN		 5262 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5263 emulation_type))
bbd9b64e 5264 return EMULATE_DONE;
6d77dbfc
GN		 5265 if (emulation_type & EMULTYPE_SKIP)
5266 return EMULATE_FAIL;
5267 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5268 }
5269 }
5270
ba8afb6b 5271 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5272 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5273 if (ctxt->eflags & X86_EFLAGS_RF)
5274 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5275 return EMULATE_DONE;
5276 }
5277
1cb3f3ae
XG		 5278 if (retry_instruction(ctxt, cr2, emulation_type))
5279 return EMULATE_DONE;
5280
7ae441ea 5281 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5282 changes registers values during IO operation */
7ae441ea
GN		 5283 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5284 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5285 emulator_invalidate_register_cache(ctxt);
7ae441ea 5286 }
4d2179e1 5287
5cd21917 5288restart:
9d74191a 5289 r = x86_emulate_insn(ctxt);
bbd9b64e 5290
775fde86
JR		 5291 if (r == EMULATION_INTERCEPTED)
5292 return EMULATE_DONE;
5293
d2ddd1c4 5294 if (r == EMULATION_FAILED) {
991eebf9
GN		 5295 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5296 emulation_type))
c3cd7ffa
GN		 5297 return EMULATE_DONE;
5298
6d77dbfc 5299 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5300 }
5301
9d74191a 5302 if (ctxt->have_exception) {
54b8486f 5303 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5304 r = EMULATE_DONE;
5305 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5306 if (!vcpu->arch.pio.in) {
5307 /* FIXME: return into emulator if single-stepping. */
3457e419 5308 vcpu->arch.pio.count = 0;
0912c977 5309 } else {
7ae441ea 5310 writeback = false;
716d51ab
GN		 5311 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5312 }
ac0a48c3 5313 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5314 } else if (vcpu->mmio_needed) {
5315 if (!vcpu->mmio_is_write)
5316 writeback = false;
ac0a48c3 5317 r = EMULATE_USER_EXIT;
716d51ab 5318 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5319 } else if (r == EMULATION_RESTART)
5cd21917 5320 goto restart;
d2ddd1c4
GN		 5321 else
5322 r = EMULATE_DONE;
f850e2e6 5323
7ae441ea 5324 if (writeback) {
6addfc42 5325 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5326 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5327 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5328 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5329 if (r == EMULATE_DONE)
6addfc42
PB		 5330 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5331 __kvm_set_rflags(vcpu, ctxt->eflags);
5332
5333 /*
5334 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5335 * do nothing, and it will be requested again as soon as
5336 * the shadow expires. But we still need to check here,
5337 * because POPF has no interrupt shadow.
5338 */
5339 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5340 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5341 } else
5342 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5343
5344 return r;
de7d789a 5345}
51d8b661 5346EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5347
cf8f70bf 5348int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5349{
cf8f70bf 5350 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5351 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5352 size, port, &val, 1);
cf8f70bf 5353 /* do not return to emulator after return from userspace */
7972995b 5354 vcpu->arch.pio.count = 0;
de7d789a
CO		 5355 return ret;
5356}
cf8f70bf 5357EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5358
8cfdc000
ZA		 5359static void tsc_bad(void *info)
5360{
0a3aee0d 5361 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5362}
5363
5364static void tsc_khz_changed(void *data)
c8076604 5365{
8cfdc000
ZA		 5366 struct cpufreq_freqs *freq = data;
5367 unsigned long khz = 0;
5368
5369 if (data)
5370 khz = freq->new;
5371 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5372 khz = cpufreq_quick_get(raw_smp_processor_id());
5373 if (!khz)
5374 khz = tsc_khz;
0a3aee0d 5375 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5376}
5377
c8076604
GH		 5378static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5379 void *data)
5380{
5381 struct cpufreq_freqs *freq = data;
5382 struct kvm *kvm;
5383 struct kvm_vcpu *vcpu;
5384 int i, send_ipi = 0;
5385
8cfdc000
ZA		 5386 /*
5387 * We allow guests to temporarily run on slowing clocks,
5388 * provided we notify them after, or to run on accelerating
5389 * clocks, provided we notify them before. Thus time never
5390 * goes backwards.
5391 *
5392 * However, we have a problem. We can't atomically update
5393 * the frequency of a given CPU from this function; it is
5394 * merely a notifier, which can be called from any CPU.
5395 * Changing the TSC frequency at arbitrary points in time
5396 * requires a recomputation of local variables related to
5397 * the TSC for each VCPU. We must flag these local variables
5398 * to be updated and be sure the update takes place with the
5399 * new frequency before any guests proceed.
5400 *
5401 * Unfortunately, the combination of hotplug CPU and frequency
5402 * change creates an intractable locking scenario; the order
5403 * of when these callouts happen is undefined with respect to
5404 * CPU hotplug, and they can race with each other. As such,
5405 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5406 * undefined; you can actually have a CPU frequency change take
5407 * place in between the computation of X and the setting of the
5408 * variable. To protect against this problem, all updates of
5409 * the per_cpu tsc_khz variable are done in an interrupt
5410 * protected IPI, and all callers wishing to update the value
5411 * must wait for a synchronous IPI to complete (which is trivial
5412 * if the caller is on the CPU already). This establishes the
5413 * necessary total order on variable updates.
5414 *
5415 * Note that because a guest time update may take place
5416 * anytime after the setting of the VCPU's request bit, the
5417 * correct TSC value must be set before the request. However,
5418 * to ensure the update actually makes it to any guest which
5419 * starts running in hardware virtualization between the set
5420 * and the acquisition of the spinlock, we must also ping the
5421 * CPU after setting the request bit.
5422 *
5423 */
5424
c8076604
GH		 5425 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5426 return 0;
5427 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5428 return 0;
8cfdc000
ZA		 5429
5430 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5431
2f303b74 5432 spin_lock(&kvm_lock);
c8076604 5433 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5434 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5435 if (vcpu->cpu != freq->cpu)
5436 continue;
c285545f 5437 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5438 if (vcpu->cpu != smp_processor_id())
8cfdc000 5439 send_ipi = 1;
c8076604
GH		 5440 }
5441 }
2f303b74 5442 spin_unlock(&kvm_lock);
c8076604
GH		 5443
5444 if (freq->old < freq->new && send_ipi) {
5445 /*
5446 * We upscale the frequency. Must make the guest
5447 * doesn't see old kvmclock values while running with
5448 * the new frequency, otherwise we risk the guest sees
5449 * time go backwards.
5450 *
5451 * In case we update the frequency for another cpu
5452 * (which might be in guest context) send an interrupt
5453 * to kick the cpu out of guest context. Next time
5454 * guest context is entered kvmclock will be updated,
5455 * so the guest will not see stale values.
5456 */
8cfdc000 5457 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5458 }
5459 return 0;
5460}
5461
5462static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5463 .notifier_call = kvmclock_cpufreq_notifier
5464};
5465
5466static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5467 unsigned long action, void *hcpu)
5468{
5469 unsigned int cpu = (unsigned long)hcpu;
5470
5471 switch (action) {
5472 case CPU_ONLINE:
5473 case CPU_DOWN_FAILED:
5474 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5475 break;
5476 case CPU_DOWN_PREPARE:
5477 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5478 break;
5479 }
5480 return NOTIFY_OK;
5481}
5482
5483static struct notifier_block kvmclock_cpu_notifier_block = {
5484 .notifier_call = kvmclock_cpu_notifier,
5485 .priority = -INT_MAX
c8076604
GH		 5486};
5487
b820cc0c
ZA		 5488static void kvm_timer_init(void)
5489{
5490 int cpu;
5491
c285545f 5492 max_tsc_khz = tsc_khz;
460dd42e
SB		 5493
5494 cpu_notifier_register_begin();
b820cc0c 5495 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5496#ifdef CONFIG_CPU_FREQ
5497 struct cpufreq_policy policy;
5498 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5499 cpu = get_cpu();
5500 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5501 if (policy.cpuinfo.max_freq)
5502 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5503 put_cpu();
c285545f 5504#endif
b820cc0c
ZA		 5505 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5506 CPUFREQ_TRANSITION_NOTIFIER);
5507 }
c285545f 5508 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5509 for_each_online_cpu(cpu)
5510 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5511
5512 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5513 cpu_notifier_register_done();
5514
b820cc0c
ZA		 5515}
5516
ff9d07a0
ZY		 5517static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5518
f5132b01 5519int kvm_is_in_guest(void)
ff9d07a0 5520{
086c9855 5521 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5522}
5523
5524static int kvm_is_user_mode(void)
5525{
5526 int user_mode = 3;
dcf46b94 5527
086c9855
AS		 5528 if (__this_cpu_read(current_vcpu))
5529 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5530
ff9d07a0
ZY		 5531 return user_mode != 0;
5532}
5533
5534static unsigned long kvm_get_guest_ip(void)
5535{
5536 unsigned long ip = 0;
dcf46b94 5537
086c9855
AS		 5538 if (__this_cpu_read(current_vcpu))
5539 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5540
ff9d07a0
ZY		 5541 return ip;
5542}
5543
5544static struct perf_guest_info_callbacks kvm_guest_cbs = {
5545 .is_in_guest = kvm_is_in_guest,
5546 .is_user_mode = kvm_is_user_mode,
5547 .get_guest_ip = kvm_get_guest_ip,
5548};
5549
5550void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5551{
086c9855 5552 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5553}
5554EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5555
5556void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5557{
086c9855 5558 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5559}
5560EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5561
ce88decf
XG		 5562static void kvm_set_mmio_spte_mask(void)
5563{
5564 u64 mask;
5565 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5566
5567 /*
5568 * Set the reserved bits and the present bit of an paging-structure
5569 * entry to generate page fault with PFER.RSV = 1.
5570 */
885032b9 5571 /* Mask the reserved physical address bits. */
d1431483 5572 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5573
5574 /* Bit 62 is always reserved for 32bit host. */
5575 mask |= 0x3ull << 62;
5576
5577 /* Set the present bit. */
ce88decf
XG		 5578 mask |= 1ull;
5579
5580#ifdef CONFIG_X86_64
5581 /*
5582 * If reserved bit is not supported, clear the present bit to disable
5583 * mmio page fault.
5584 */
5585 if (maxphyaddr == 52)
5586 mask &= ~1ull;
5587#endif
5588
5589 kvm_mmu_set_mmio_spte_mask(mask);
5590}
5591
16e8d74d
MT		 5592#ifdef CONFIG_X86_64
5593static void pvclock_gtod_update_fn(struct work_struct *work)
5594{
d828199e
MT		 5595 struct kvm *kvm;
5596
5597 struct kvm_vcpu *vcpu;
5598 int i;
5599
2f303b74 5600 spin_lock(&kvm_lock);
d828199e
MT		 5601 list_for_each_entry(kvm, &vm_list, vm_list)
5602 kvm_for_each_vcpu(i, vcpu, kvm)
5603 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5604 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5605 spin_unlock(&kvm_lock);
16e8d74d
MT		 5606}
5607
5608static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5609
5610/*
5611 * Notification about pvclock gtod data update.
5612 */
5613static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5614 void *priv)
5615{
5616 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5617 struct timekeeper *tk = priv;
5618
5619 update_pvclock_gtod(tk);
5620
5621 /* disable master clock if host does not trust, or does not
5622 * use, TSC clocksource
5623 */
5624 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5625 atomic_read(&kvm_guest_has_master_clock) != 0)
5626 queue_work(system_long_wq, &pvclock_gtod_work);
5627
5628 return 0;
5629}
5630
5631static struct notifier_block pvclock_gtod_notifier = {
5632 .notifier_call = pvclock_gtod_notify,
5633};
5634#endif
5635
f8c16bba 5636int kvm_arch_init(void *opaque)
043405e1 5637{
b820cc0c 5638 int r;
6b61edf7 5639 struct kvm_x86_ops *ops = opaque;
f8c16bba 5640
f8c16bba
ZX		 5641 if (kvm_x86_ops) {
5642 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5643 r = -EEXIST;
5644 goto out;
f8c16bba
ZX		 5645 }
5646
5647 if (!ops->cpu_has_kvm_support()) {
5648 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5649 r = -EOPNOTSUPP;
5650 goto out;
f8c16bba
ZX		 5651 }
5652 if (ops->disabled_by_bios()) {
5653 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5654 r = -EOPNOTSUPP;
5655 goto out;
f8c16bba
ZX		 5656 }
5657
013f6a5d
MT		 5658 r = -ENOMEM;
5659 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5660 if (!shared_msrs) {
5661 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5662 goto out;
5663 }
5664
97db56ce
AK		 5665 r = kvm_mmu_module_init();
5666 if (r)
013f6a5d 5667 goto out_free_percpu;
97db56ce 5668
ce88decf 5669 kvm_set_mmio_spte_mask();
97db56ce 5670
f8c16bba 5671 kvm_x86_ops = ops;
920c8377
PB		 5672 kvm_init_msr_list();
5673
7b52345e 5674 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5675 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5676
b820cc0c 5677 kvm_timer_init();
c8076604 5678
ff9d07a0
ZY		 5679 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5680
2acf923e
DC		 5681 if (cpu_has_xsave)
5682 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5683
c5cc421b 5684 kvm_lapic_init();
16e8d74d
MT		 5685#ifdef CONFIG_X86_64
5686 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5687#endif
5688
f8c16bba 5689 return 0;
56c6d28a 5690
013f6a5d
MT		 5691out_free_percpu:
5692 free_percpu(shared_msrs);
56c6d28a 5693out:
56c6d28a 5694 return r;
043405e1 5695}
8776e519 5696
f8c16bba
ZX		 5697void kvm_arch_exit(void)
5698{
ff9d07a0
ZY		 5699 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5700
888d256e
JK		 5701 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5702 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5703 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5704 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5705#ifdef CONFIG_X86_64
5706 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5707#endif
f8c16bba 5708 kvm_x86_ops = NULL;
56c6d28a 5709 kvm_mmu_module_exit();
013f6a5d 5710 free_percpu(shared_msrs);
56c6d28a 5711}
f8c16bba 5712
8776e519
HB		 5713int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5714{
5715 ++vcpu->stat.halt_exits;
5716 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5717 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5718 return 1;
5719 } else {
5720 vcpu->run->exit_reason = KVM_EXIT_HLT;
5721 return 0;
5722 }
5723}
5724EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5725
55cd8e5a
GN		 5726int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5727{
5728 u64 param, ingpa, outgpa, ret;
5729 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5730 bool fast, longmode;
55cd8e5a
GN		 5731
5732 /*
5733 * hypercall generates UD from non zero cpl and real mode
5734 * per HYPER-V spec
5735 */
3eeb3288 5736 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5737 kvm_queue_exception(vcpu, UD_VECTOR);
5738 return 0;
5739 }
5740
a449c7aa 5741 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5742
5743 if (!longmode) {
ccd46936
GN		 5744 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5745 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5746 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5747 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5748 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5749 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5750 }
5751#ifdef CONFIG_X86_64
5752 else {
5753 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5754 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5755 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5756 }
5757#endif
5758
5759 code = param & 0xffff;
5760 fast = (param >> 16) & 0x1;
5761 rep_cnt = (param >> 32) & 0xfff;
5762 rep_idx = (param >> 48) & 0xfff;
5763
5764 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5765
c25bc163
GN		 5766 switch (code) {
5767 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5768 kvm_vcpu_on_spin(vcpu);
5769 break;
5770 default:
5771 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5772 break;
5773 }
55cd8e5a
GN		 5774
5775 ret = res | (((u64)rep_done & 0xfff) << 32);
5776 if (longmode) {
5777 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5778 } else {
5779 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5780 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5781 }
5782
5783 return 1;
5784}
5785
6aef266c
SV		 5786/*
5787 * kvm_pv_kick_cpu_op: Kick a vcpu.
5788 *
5789 * @apicid - apicid of vcpu to be kicked.
5790 */
5791static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5792{
24d2166b 5793 struct kvm_lapic_irq lapic_irq;
6aef266c 5794
24d2166b
R		 5795 lapic_irq.shorthand = 0;
5796 lapic_irq.dest_mode = 0;
5797 lapic_irq.dest_id = apicid;
6aef266c 5798
24d2166b
R		 5799 lapic_irq.delivery_mode = APIC_DM_REMRD;
5800 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5801}
5802
8776e519
HB		 5803int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5804{
5805 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 5806 int op_64_bit, r = 1;
8776e519 5807
55cd8e5a
GN		 5808 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5809 return kvm_hv_hypercall(vcpu);
5810
5fdbf976
MT		 5811 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5812 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5813 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5814 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5815 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5816
229456fc 5817 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5818
a449c7aa
NA		 5819 op_64_bit = is_64_bit_mode(vcpu);
5820 if (!op_64_bit) {
8776e519
HB		 5821 nr &= 0xFFFFFFFF;
5822 a0 &= 0xFFFFFFFF;
5823 a1 &= 0xFFFFFFFF;
5824 a2 &= 0xFFFFFFFF;
5825 a3 &= 0xFFFFFFFF;
5826 }
5827
07708c4a
JK		 5828 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5829 ret = -KVM_EPERM;
5830 goto out;
5831 }
5832
8776e519 5833 switch (nr) {
b93463aa
AK		 5834 case KVM_HC_VAPIC_POLL_IRQ:
5835 ret = 0;
5836 break;
6aef266c
SV		 5837 case KVM_HC_KICK_CPU:
5838 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5839 ret = 0;
5840 break;
8776e519
HB		 5841 default:
5842 ret = -KVM_ENOSYS;
5843 break;
5844 }
07708c4a 5845out:
a449c7aa
NA		 5846 if (!op_64_bit)
5847 ret = (u32)ret;
5fdbf976 5848 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5849 ++vcpu->stat.hypercalls;
2f333bcb 5850 return r;
8776e519
HB		 5851}
5852EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5853
b6785def 5854static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5855{
d6aa1000 5856 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5857 char instruction[3];
5fdbf976 5858 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5859
8776e519 5860 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5861
9d74191a 5862 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5863}
5864
b6c7a5dc
HB		 5865/*
5866 * Check if userspace requested an interrupt window, and that the
5867 * interrupt window is open.
5868 *
5869 * No need to exit to userspace if we already have an interrupt queued.
5870 */
851ba692 5871static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5872{
8061823a 5873 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5874 vcpu->run->request_interrupt_window &&
5df56646 5875 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5876}
5877
851ba692 5878static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5879{
851ba692
AK		 5880 struct kvm_run *kvm_run = vcpu->run;
5881
91586a3b 5882 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5883 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5884 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5885 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5886 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5887 else
b6c7a5dc 5888 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5889 kvm_arch_interrupt_allowed(vcpu) &&
5890 !kvm_cpu_has_interrupt(vcpu) &&
5891 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5892}
5893
95ba8273
GN		 5894static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5895{
5896 int max_irr, tpr;
5897
5898 if (!kvm_x86_ops->update_cr8_intercept)
5899 return;
5900
88c808fd
AK		 5901 if (!vcpu->arch.apic)
5902 return;
5903
8db3baa2
GN		 5904 if (!vcpu->arch.apic->vapic_addr)
5905 max_irr = kvm_lapic_find_highest_irr(vcpu);
5906 else
5907 max_irr = -1;
95ba8273
GN		 5908
5909 if (max_irr != -1)
5910 max_irr >>= 4;
5911
5912 tpr = kvm_lapic_get_cr8(vcpu);
5913
5914 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5915}
5916
b6b8a145 5917static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 5918{
b6b8a145
JK		 5919 int r;
5920
95ba8273 5921 /* try to reinject previous events if any */
b59bb7bd 5922 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5923 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5924 vcpu->arch.exception.has_error_code,
5925 vcpu->arch.exception.error_code);
d6e8c854
NA		 5926
5927 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
5928 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
5929 X86_EFLAGS_RF);
5930
b59bb7bd
GN		 5931 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5932 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5933 vcpu->arch.exception.error_code,
5934 vcpu->arch.exception.reinject);
b6b8a145 5935 return 0;
b59bb7bd
GN		 5936 }
5937
95ba8273
GN		 5938 if (vcpu->arch.nmi_injected) {
5939 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 5940 return 0;
95ba8273
GN		 5941 }
5942
5943 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5944 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 5945 return 0;
5946 }
5947
5948 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5949 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5950 if (r != 0)
5951 return r;
95ba8273
GN		 5952 }
5953
5954 /* try to inject new event if pending */
5955 if (vcpu->arch.nmi_pending) {
5956 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5957 --vcpu->arch.nmi_pending;
95ba8273
GN		 5958 vcpu->arch.nmi_injected = true;
5959 kvm_x86_ops->set_nmi(vcpu);
5960 }
c7c9c56c 5961 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 5962 /*
5963 * Because interrupts can be injected asynchronously, we are
5964 * calling check_nested_events again here to avoid a race condition.
5965 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
5966 * proposal and current concerns. Perhaps we should be setting
5967 * KVM_REQ_EVENT only on certain events and not unconditionally?
5968 */
5969 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
5970 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
5971 if (r != 0)
5972 return r;
5973 }
95ba8273 5974 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5975 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5976 false);
5977 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5978 }
5979 }
b6b8a145 5980 return 0;
95ba8273
GN		 5981}
5982
7460fb4a
AK		 5983static void process_nmi(struct kvm_vcpu *vcpu)
5984{
5985 unsigned limit = 2;
5986
5987 /*
5988 * x86 is limited to one NMI running, and one NMI pending after it.
5989 * If an NMI is already in progress, limit further NMIs to just one.
5990 * Otherwise, allow two (and we'll inject the first one immediately).
5991 */
5992 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5993 limit = 1;
5994
5995 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5996 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5997 kvm_make_request(KVM_REQ_EVENT, vcpu);
5998}
5999
3d81bc7e 6000static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6001{
6002 u64 eoi_exit_bitmap[4];
cf9e65b7 6003 u32 tmr[8];
c7c9c56c 6004
3d81bc7e
YZ		 6005 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6006 return;
c7c9c56c
YZ		 6007
6008 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6009 memset(tmr, 0, 32);
c7c9c56c 6010
cf9e65b7 6011 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6012 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6013 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6014}
6015
9357d939
TY		 6016/*
6017 * Returns 1 to let __vcpu_run() continue the guest execution loop without
6018 * exiting to the userspace. Otherwise, the value will be returned to the
6019 * userspace.
6020 */
851ba692 6021static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6022{
6023 int r;
6a8b1d13 6024 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6025 vcpu->run->request_interrupt_window;
730dca42 6026 bool req_immediate_exit = false;
b6c7a5dc 6027
3e007509 6028 if (vcpu->requests) {
a8eeb04a 6029 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6030 kvm_mmu_unload(vcpu);
a8eeb04a 6031 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6032 __kvm_migrate_timers(vcpu);
d828199e
MT		 6033 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6034 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6035 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6036 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6037 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6038 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6039 if (unlikely(r))
6040 goto out;
6041 }
a8eeb04a 6042 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6043 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6044 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 6045 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 6046 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6047 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6048 r = 0;
6049 goto out;
6050 }
a8eeb04a 6051 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6052 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6053 r = 0;
6054 goto out;
6055 }
a8eeb04a 6056 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6057 vcpu->fpu_active = 0;
6058 kvm_x86_ops->fpu_deactivate(vcpu);
6059 }
af585b92
GN		 6060 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6061 /* Page is swapped out. Do synthetic halt */
6062 vcpu->arch.apf.halted = true;
6063 r = 1;
6064 goto out;
6065 }
c9aaa895
GC		 6066 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6067 record_steal_time(vcpu);
7460fb4a
AK		 6068 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6069 process_nmi(vcpu);
f5132b01
GN		 6070 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6071 kvm_handle_pmu_event(vcpu);
6072 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6073 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6074 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6075 vcpu_scan_ioapic(vcpu);
2f52d58c 6076 }
b93463aa 6077
b463a6f7 6078 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6079 kvm_apic_accept_events(vcpu);
6080 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6081 r = 1;
6082 goto out;
6083 }
6084
b6b8a145
JK		 6085 if (inject_pending_event(vcpu, req_int_win) != 0)
6086 req_immediate_exit = true;
b463a6f7 6087 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6088 else if (vcpu->arch.nmi_pending)
c9a7953f 6089 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6090 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6091 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6092
6093 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6094 /*
6095 * Update architecture specific hints for APIC
6096 * virtual interrupt delivery.
6097 */
6098 if (kvm_x86_ops->hwapic_irr_update)
6099 kvm_x86_ops->hwapic_irr_update(vcpu,
6100 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6101 update_cr8_intercept(vcpu);
6102 kvm_lapic_sync_to_vapic(vcpu);
6103 }
6104 }
6105
d8368af8
AK		 6106 r = kvm_mmu_reload(vcpu);
6107 if (unlikely(r)) {
d905c069 6108 goto cancel_injection;
d8368af8
AK		 6109 }
6110
b6c7a5dc
HB		 6111 preempt_disable();
6112
6113 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6114 if (vcpu->fpu_active)
6115 kvm_load_guest_fpu(vcpu);
2acf923e 6116 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6117
6b7e2d09
XG		 6118 vcpu->mode = IN_GUEST_MODE;
6119
01b71917
MT		 6120 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6121
6b7e2d09
XG		 6122 /* We should set ->mode before check ->requests,
6123 * see the comment in make_all_cpus_request.
6124 */
01b71917 6125 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6126
d94e1dc9 6127 local_irq_disable();
32f88400 6128
6b7e2d09 6129 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6130 || need_resched() || signal_pending(current)) {
6b7e2d09 6131 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6132 smp_wmb();
6c142801
AK		 6133 local_irq_enable();
6134 preempt_enable();
01b71917 6135 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6136 r = 1;
d905c069 6137 goto cancel_injection;
6c142801
AK		 6138 }
6139
d6185f20
NHE		 6140 if (req_immediate_exit)
6141 smp_send_reschedule(vcpu->cpu);
6142
b6c7a5dc
HB		 6143 kvm_guest_enter();
6144
42dbaa5a 6145 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6146 set_debugreg(0, 7);
6147 set_debugreg(vcpu->arch.eff_db[0], 0);
6148 set_debugreg(vcpu->arch.eff_db[1], 1);
6149 set_debugreg(vcpu->arch.eff_db[2], 2);
6150 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6151 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 6152 }
b6c7a5dc 6153
229456fc 6154 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6155 kvm_x86_ops->run(vcpu);
b6c7a5dc 6156
c77fb5fe
PB		 6157 /*
6158 * Do this here before restoring debug registers on the host. And
6159 * since we do this before handling the vmexit, a DR access vmexit
6160 * can (a) read the correct value of the debug registers, (b) set
6161 * KVM_DEBUGREG_WONT_EXIT again.
6162 */
6163 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6164 int i;
6165
6166 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6167 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6168 for (i = 0; i < KVM_NR_DB_REGS; i++)
6169 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6170 }
6171
24f1e32c
FW		 6172 /*
6173 * If the guest has used debug registers, at least dr7
6174 * will be disabled while returning to the host.
6175 * If we don't have active breakpoints in the host, we don't
6176 * care about the messed up debug address registers. But if
6177 * we have some of them active, restore the old state.
6178 */
59d8eb53 6179 if (hw_breakpoint_active())
24f1e32c 6180 hw_breakpoint_restore();
42dbaa5a 6181
886b470c
MT		 6182 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6183 native_read_tsc());
1d5f066e 6184
6b7e2d09 6185 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6186 smp_wmb();
a547c6db
YZ		 6187
6188 /* Interrupt is enabled by handle_external_intr() */
6189 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6190
6191 ++vcpu->stat.exits;
6192
6193 /*
6194 * We must have an instruction between local_irq_enable() and
6195 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6196 * the interrupt shadow. The stat.exits increment will do nicely.
6197 * But we need to prevent reordering, hence this barrier():
6198 */
6199 barrier();
6200
6201 kvm_guest_exit();
6202
6203 preempt_enable();
6204
f656ce01 6205 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6206
b6c7a5dc
HB		 6207 /*
6208 * Profile KVM exit RIPs:
6209 */
6210 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6211 unsigned long rip = kvm_rip_read(vcpu);
6212 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6213 }
6214
cc578287
ZA		 6215 if (unlikely(vcpu->arch.tsc_always_catchup))
6216 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6217
5cfb1d5a
MT		 6218 if (vcpu->arch.apic_attention)
6219 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6220
851ba692 6221 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6222 return r;
6223
6224cancel_injection:
6225 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6226 if (unlikely(vcpu->arch.apic_attention))
6227 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6228out:
6229 return r;
6230}
b6c7a5dc 6231
09cec754 6232
851ba692 6233static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6234{
6235 int r;
f656ce01 6236 struct kvm *kvm = vcpu->kvm;
d7690175 6237
f656ce01 6238 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6239
6240 r = 1;
6241 while (r > 0) {
af585b92
GN		 6242 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6243 !vcpu->arch.apf.halted)
851ba692 6244 r = vcpu_enter_guest(vcpu);
d7690175 6245 else {
f656ce01 6246 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6247 kvm_vcpu_block(vcpu);
f656ce01 6248 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6249 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6250 kvm_apic_accept_events(vcpu);
09cec754
GN		 6251 switch(vcpu->arch.mp_state) {
6252 case KVM_MP_STATE_HALTED:
6aef266c 6253 vcpu->arch.pv.pv_unhalted = false;
d7690175 6254 vcpu->arch.mp_state =
09cec754
GN		 6255 KVM_MP_STATE_RUNNABLE;
6256 case KVM_MP_STATE_RUNNABLE:
af585b92 6257 vcpu->arch.apf.halted = false;
09cec754 6258 break;
66450a21
JK		 6259 case KVM_MP_STATE_INIT_RECEIVED:
6260 break;
09cec754
GN		 6261 default:
6262 r = -EINTR;
6263 break;
6264 }
6265 }
d7690175
MT		 6266 }
6267
09cec754
GN		 6268 if (r <= 0)
6269 break;
6270
6271 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6272 if (kvm_cpu_has_pending_timer(vcpu))
6273 kvm_inject_pending_timer_irqs(vcpu);
6274
851ba692 6275 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6276 r = -EINTR;
851ba692 6277 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6278 ++vcpu->stat.request_irq_exits;
6279 }
af585b92
GN		 6280
6281 kvm_check_async_pf_completion(vcpu);
6282
09cec754
GN		 6283 if (signal_pending(current)) {
6284 r = -EINTR;
851ba692 6285 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6286 ++vcpu->stat.signal_exits;
6287 }
6288 if (need_resched()) {
f656ce01 6289 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6290 cond_resched();
f656ce01 6291 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6292 }
b6c7a5dc
HB		 6293 }
6294
f656ce01 6295 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6296
6297 return r;
6298}
6299
716d51ab
GN		 6300static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6301{
6302 int r;
6303 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6304 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6305 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6306 if (r != EMULATE_DONE)
6307 return 0;
6308 return 1;
6309}
6310
6311static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6312{
6313 BUG_ON(!vcpu->arch.pio.count);
6314
6315 return complete_emulated_io(vcpu);
6316}
6317
f78146b0
AK		 6318/*
6319 * Implements the following, as a state machine:
6320 *
6321 * read:
6322 * for each fragment
87da7e66
XG		 6323 * for each mmio piece in the fragment
6324 * write gpa, len
6325 * exit
6326 * copy data
f78146b0
AK		 6327 * execute insn
6328 *
6329 * write:
6330 * for each fragment
87da7e66
XG		 6331 * for each mmio piece in the fragment
6332 * write gpa, len
6333 * copy data
6334 * exit
f78146b0 6335 */
716d51ab 6336static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6337{
6338 struct kvm_run *run = vcpu->run;
f78146b0 6339 struct kvm_mmio_fragment *frag;
87da7e66 6340 unsigned len;
5287f194 6341
716d51ab 6342 BUG_ON(!vcpu->mmio_needed);
5287f194 6343
716d51ab 6344 /* Complete previous fragment */
87da7e66
XG		 6345 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6346 len = min(8u, frag->len);
716d51ab 6347 if (!vcpu->mmio_is_write)
87da7e66
XG		 6348 memcpy(frag->data, run->mmio.data, len);
6349
6350 if (frag->len <= 8) {
6351 /* Switch to the next fragment. */
6352 frag++;
6353 vcpu->mmio_cur_fragment++;
6354 } else {
6355 /* Go forward to the next mmio piece. */
6356 frag->data += len;
6357 frag->gpa += len;
6358 frag->len -= len;
6359 }
6360
a08d3b3b 6361 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6362 vcpu->mmio_needed = 0;
0912c977
PB		 6363
6364 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6365 if (vcpu->mmio_is_write)
716d51ab
GN		 6366 return 1;
6367 vcpu->mmio_read_completed = 1;
6368 return complete_emulated_io(vcpu);
6369 }
87da7e66 6370
716d51ab
GN		 6371 run->exit_reason = KVM_EXIT_MMIO;
6372 run->mmio.phys_addr = frag->gpa;
6373 if (vcpu->mmio_is_write)
87da7e66
XG		 6374 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6375 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6376 run->mmio.is_write = vcpu->mmio_is_write;
6377 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6378 return 0;
5287f194
AK		 6379}
6380
716d51ab 6381
b6c7a5dc
HB		 6382int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6383{
6384 int r;
6385 sigset_t sigsaved;
6386
e5c30142
AK		 6387 if (!tsk_used_math(current) && init_fpu(current))
6388 return -ENOMEM;
6389
ac9f6dc0
AK		 6390 if (vcpu->sigset_active)
6391 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6392
a4535290 6393 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6394 kvm_vcpu_block(vcpu);
66450a21 6395 kvm_apic_accept_events(vcpu);
d7690175 6396 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6397 r = -EAGAIN;
6398 goto out;
b6c7a5dc
HB		 6399 }
6400
b6c7a5dc 6401 /* re-sync apic's tpr */
eea1cff9
AP		 6402 if (!irqchip_in_kernel(vcpu->kvm)) {
6403 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6404 r = -EINVAL;
6405 goto out;
6406 }
6407 }
b6c7a5dc 6408
716d51ab
GN		 6409 if (unlikely(vcpu->arch.complete_userspace_io)) {
6410 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6411 vcpu->arch.complete_userspace_io = NULL;
6412 r = cui(vcpu);
6413 if (r <= 0)
6414 goto out;
6415 } else
6416 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6417
851ba692 6418 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6419
6420out:
f1d86e46 6421 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6422 if (vcpu->sigset_active)
6423 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6424
b6c7a5dc
HB		 6425 return r;
6426}
6427
6428int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6429{
7ae441ea
GN		 6430 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6431 /*
6432 * We are here if userspace calls get_regs() in the middle of
6433 * instruction emulation. Registers state needs to be copied
4a969980 6434 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6435 * that usually, but some bad designed PV devices (vmware
6436 * backdoor interface) need this to work
6437 */
dd856efa 6438 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6439 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6440 }
5fdbf976
MT		 6441 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6442 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6443 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6444 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6445 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6446 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6447 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6448 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6449#ifdef CONFIG_X86_64
5fdbf976
MT		 6450 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6451 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6452 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6453 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6454 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6455 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6456 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6457 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6458#endif
6459
5fdbf976 6460 regs->rip = kvm_rip_read(vcpu);
91586a3b 6461 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6462
b6c7a5dc
HB		 6463 return 0;
6464}
6465
6466int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6467{
7ae441ea
GN		 6468 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6469 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6470
5fdbf976
MT		 6471 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6472 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6473 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6474 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6475 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6476 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6477 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6478 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6479#ifdef CONFIG_X86_64
5fdbf976
MT		 6480 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6481 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6482 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6483 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6484 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6485 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6486 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6487 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6488#endif
6489
5fdbf976 6490 kvm_rip_write(vcpu, regs->rip);
91586a3b 6491 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6492
b4f14abd
JK		 6493 vcpu->arch.exception.pending = false;
6494
3842d135
AK		 6495 kvm_make_request(KVM_REQ_EVENT, vcpu);
6496
b6c7a5dc
HB		 6497 return 0;
6498}
6499
b6c7a5dc
HB		 6500void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6501{
6502 struct kvm_segment cs;
6503
3e6e0aab 6504 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6505 *db = cs.db;
6506 *l = cs.l;
6507}
6508EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6509
6510int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6511 struct kvm_sregs *sregs)
6512{
89a27f4d 6513 struct desc_ptr dt;
b6c7a5dc 6514
3e6e0aab
GT		 6515 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6516 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6517 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6518 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6519 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6520 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6521
3e6e0aab
GT		 6522 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6523 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6524
6525 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6526 sregs->idt.limit = dt.size;
6527 sregs->idt.base = dt.address;
b6c7a5dc 6528 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6529 sregs->gdt.limit = dt.size;
6530 sregs->gdt.base = dt.address;
b6c7a5dc 6531
4d4ec087 6532 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6533 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6534 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6535 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6536 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6537 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6538 sregs->apic_base = kvm_get_apic_base(vcpu);
6539
923c61bb 6540 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6541
36752c9b 6542 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6543 set_bit(vcpu->arch.interrupt.nr,
6544 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6545
b6c7a5dc
HB		 6546 return 0;
6547}
6548
62d9f0db
MT		 6549int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6550 struct kvm_mp_state *mp_state)
6551{
66450a21 6552 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6553 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6554 vcpu->arch.pv.pv_unhalted)
6555 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6556 else
6557 mp_state->mp_state = vcpu->arch.mp_state;
6558
62d9f0db
MT		 6559 return 0;
6560}
6561
6562int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6563 struct kvm_mp_state *mp_state)
6564{
66450a21
JK		 6565 if (!kvm_vcpu_has_lapic(vcpu) &&
6566 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6567 return -EINVAL;
6568
6569 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6570 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6571 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6572 } else
6573 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6574 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6575 return 0;
6576}
6577
7f3d35fd
KW		 6578int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6579 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6580{
9d74191a 6581 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6582 int ret;
e01c2426 6583
8ec4722d 6584 init_emulate_ctxt(vcpu);
c697518a 6585
7f3d35fd 6586 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6587 has_error_code, error_code);
c697518a 6588
c697518a 6589 if (ret)
19d04437 6590 return EMULATE_FAIL;
37817f29 6591
9d74191a
TY		 6592 kvm_rip_write(vcpu, ctxt->eip);
6593 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6594 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6595 return EMULATE_DONE;
37817f29
IE		 6596}
6597EXPORT_SYMBOL_GPL(kvm_task_switch);
6598
b6c7a5dc
HB		 6599int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6600 struct kvm_sregs *sregs)
6601{
58cb628d 6602 struct msr_data apic_base_msr;
b6c7a5dc 6603 int mmu_reset_needed = 0;
63f42e02 6604 int pending_vec, max_bits, idx;
89a27f4d 6605 struct desc_ptr dt;
b6c7a5dc 6606
6d1068b3
PM		 6607 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6608 return -EINVAL;
6609
89a27f4d
GN		 6610 dt.size = sregs->idt.limit;
6611 dt.address = sregs->idt.base;
b6c7a5dc 6612 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6613 dt.size = sregs->gdt.limit;
6614 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6615 kvm_x86_ops->set_gdt(vcpu, &dt);
6616
ad312c7c 6617 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6618 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6619 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6620 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6621
2d3ad1f4 6622 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6623
f6801dff 6624 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6625 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6626 apic_base_msr.data = sregs->apic_base;
6627 apic_base_msr.host_initiated = true;
6628 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6629
4d4ec087 6630 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6631 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6632 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6633
fc78f519 6634 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6635 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6636 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6637 kvm_update_cpuid(vcpu);
63f42e02
XG		 6638
6639 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6640 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6641 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6642 mmu_reset_needed = 1;
6643 }
63f42e02 6644 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6645
6646 if (mmu_reset_needed)
6647 kvm_mmu_reset_context(vcpu);
6648
a50abc3b 6649 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6650 pending_vec = find_first_bit(
6651 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6652 if (pending_vec < max_bits) {
66fd3f7f 6653 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6654 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6655 }
6656
3e6e0aab
GT		 6657 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6658 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6659 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6660 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6661 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6662 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6663
3e6e0aab
GT		 6664 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6665 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6666
5f0269f5
ME		 6667 update_cr8_intercept(vcpu);
6668
9c3e4aab 6669 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6670 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6671 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6672 !is_protmode(vcpu))
9c3e4aab
MT		 6673 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6674
3842d135
AK		 6675 kvm_make_request(KVM_REQ_EVENT, vcpu);
6676
b6c7a5dc
HB		 6677 return 0;
6678}
6679
d0bfb940
JK		 6680int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6681 struct kvm_guest_debug *dbg)
b6c7a5dc 6682{
355be0b9 6683 unsigned long rflags;
ae675ef0 6684 int i, r;
b6c7a5dc 6685
4f926bf2
JK		 6686 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6687 r = -EBUSY;
6688 if (vcpu->arch.exception.pending)
2122ff5e 6689 goto out;
4f926bf2
JK		 6690 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6691 kvm_queue_exception(vcpu, DB_VECTOR);
6692 else
6693 kvm_queue_exception(vcpu, BP_VECTOR);
6694 }
6695
91586a3b
JK		 6696 /*
6697 * Read rflags as long as potentially injected trace flags are still
6698 * filtered out.
6699 */
6700 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6701
6702 vcpu->guest_debug = dbg->control;
6703 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6704 vcpu->guest_debug = 0;
6705
6706 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6707 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6708 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6709 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6710 } else {
6711 for (i = 0; i < KVM_NR_DB_REGS; i++)
6712 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6713 }
c8639010 6714 kvm_update_dr7(vcpu);
ae675ef0 6715
f92653ee
JK		 6716 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6717 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6718 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6719
91586a3b
JK		 6720 /*
6721 * Trigger an rflags update that will inject or remove the trace
6722 * flags.
6723 */
6724 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6725
c8639010 6726 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6727
4f926bf2 6728 r = 0;
d0bfb940 6729
2122ff5e 6730out:
b6c7a5dc
HB		 6731
6732 return r;
6733}
6734
8b006791
ZX		 6735/*
6736 * Translate a guest virtual address to a guest physical address.
6737 */
6738int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6739 struct kvm_translation *tr)
6740{
6741 unsigned long vaddr = tr->linear_address;
6742 gpa_t gpa;
f656ce01 6743 int idx;
8b006791 6744
f656ce01 6745 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6746 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6747 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6748 tr->physical_address = gpa;
6749 tr->valid = gpa != UNMAPPED_GVA;
6750 tr->writeable = 1;
6751 tr->usermode = 0;
8b006791
ZX		 6752
6753 return 0;
6754}
6755
d0752060
HB		 6756int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6757{
98918833
SY		 6758 struct i387_fxsave_struct *fxsave =
6759 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6760
d0752060
HB		 6761 memcpy(fpu->fpr, fxsave->st_space, 128);
6762 fpu->fcw = fxsave->cwd;
6763 fpu->fsw = fxsave->swd;
6764 fpu->ftwx = fxsave->twd;
6765 fpu->last_opcode = fxsave->fop;
6766 fpu->last_ip = fxsave->rip;
6767 fpu->last_dp = fxsave->rdp;
6768 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6769
d0752060
HB		 6770 return 0;
6771}
6772
6773int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6774{
98918833
SY		 6775 struct i387_fxsave_struct *fxsave =
6776 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6777
d0752060
HB		 6778 memcpy(fxsave->st_space, fpu->fpr, 128);
6779 fxsave->cwd = fpu->fcw;
6780 fxsave->swd = fpu->fsw;
6781 fxsave->twd = fpu->ftwx;
6782 fxsave->fop = fpu->last_opcode;
6783 fxsave->rip = fpu->last_ip;
6784 fxsave->rdp = fpu->last_dp;
6785 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6786
d0752060
HB		 6787 return 0;
6788}
6789
10ab25cd 6790int fx_init(struct kvm_vcpu *vcpu)
d0752060 6791{
10ab25cd
JK		 6792 int err;
6793
6794 err = fpu_alloc(&vcpu->arch.guest_fpu);
6795 if (err)
6796 return err;
6797
98918833 6798 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6799
2acf923e
DC		 6800 /*
6801 * Ensure guest xcr0 is valid for loading
6802 */
6803 vcpu->arch.xcr0 = XSTATE_FP;
6804
ad312c7c 6805 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6806
6807 return 0;
d0752060
HB		 6808}
6809EXPORT_SYMBOL_GPL(fx_init);
6810
98918833
SY		 6811static void fx_free(struct kvm_vcpu *vcpu)
6812{
6813 fpu_free(&vcpu->arch.guest_fpu);
6814}
6815
d0752060
HB		 6816void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6817{
2608d7a1 6818 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6819 return;
6820
2acf923e
DC		 6821 /*
6822 * Restore all possible states in the guest,
6823 * and assume host would use all available bits.
6824 * Guest xcr0 would be loaded later.
6825 */
6826 kvm_put_guest_xcr0(vcpu);
d0752060 6827 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6828 __kernel_fpu_begin();
98918833 6829 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6830 trace_kvm_fpu(1);
d0752060 6831}
d0752060
HB		 6832
6833void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6834{
2acf923e
DC		 6835 kvm_put_guest_xcr0(vcpu);
6836
d0752060
HB		 6837 if (!vcpu->guest_fpu_loaded)
6838 return;
6839
6840 vcpu->guest_fpu_loaded = 0;
98918833 6841 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6842 __kernel_fpu_end();
f096ed85 6843 ++vcpu->stat.fpu_reload;
a8eeb04a 6844 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6845 trace_kvm_fpu(0);
d0752060 6846}
e9b11c17
ZX		 6847
6848void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6849{
12f9a48f 6850 kvmclock_reset(vcpu);
7f1ea208 6851
f5f48ee1 6852 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6853 fx_free(vcpu);
e9b11c17
ZX		 6854 kvm_x86_ops->vcpu_free(vcpu);
6855}
6856
6857struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6858 unsigned int id)
6859{
6755bae8
ZA		 6860 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6861 printk_once(KERN_WARNING
6862 "kvm: SMP vm created on host with unstable TSC; "
6863 "guest TSC will not be reliable\n");
26e5215f
AK		 6864 return kvm_x86_ops->vcpu_create(kvm, id);
6865}
e9b11c17 6866
26e5215f
AK		 6867int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6868{
6869 int r;
e9b11c17 6870
0bed3b56 6871 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6872 r = vcpu_load(vcpu);
6873 if (r)
6874 return r;
57f252f2 6875 kvm_vcpu_reset(vcpu);
8a3c1a33 6876 kvm_mmu_setup(vcpu);
e9b11c17 6877 vcpu_put(vcpu);
e9b11c17 6878
26e5215f 6879 return r;
e9b11c17
ZX		 6880}
6881
42897d86
MT		 6882int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6883{
6884 int r;
8fe8ab46 6885 struct msr_data msr;
332967a3 6886 struct kvm *kvm = vcpu->kvm;
42897d86
MT		 6887
6888 r = vcpu_load(vcpu);
6889 if (r)
6890 return r;
8fe8ab46
WA		 6891 msr.data = 0x0;
6892 msr.index = MSR_IA32_TSC;
6893 msr.host_initiated = true;
6894 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6895 vcpu_put(vcpu);
6896
332967a3
AJ		 6897 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
6898 KVMCLOCK_SYNC_PERIOD);
6899
42897d86
MT		 6900 return r;
6901}
6902
d40ccc62 6903void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6904{
9fc77441 6905 int r;
344d9588
GN		 6906 vcpu->arch.apf.msr_val = 0;
6907
9fc77441
MT		 6908 r = vcpu_load(vcpu);
6909 BUG_ON(r);
e9b11c17
ZX		 6910 kvm_mmu_unload(vcpu);
6911 vcpu_put(vcpu);
6912
98918833 6913 fx_free(vcpu);
e9b11c17
ZX		 6914 kvm_x86_ops->vcpu_free(vcpu);
6915}
6916
66450a21 6917void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6918{
7460fb4a
AK		 6919 atomic_set(&vcpu->arch.nmi_queued, 0);
6920 vcpu->arch.nmi_pending = 0;
448fa4a9 6921 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 6922 kvm_clear_interrupt_queue(vcpu);
6923 kvm_clear_exception_queue(vcpu);
448fa4a9 6924
42dbaa5a 6925 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6f43ed01 6926 vcpu->arch.dr6 = DR6_INIT;
73aaf249 6927 kvm_update_dr6(vcpu);
42dbaa5a 6928 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6929 kvm_update_dr7(vcpu);
42dbaa5a 6930
3842d135 6931 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6932 vcpu->arch.apf.msr_val = 0;
c9aaa895 6933 vcpu->arch.st.msr_val = 0;
3842d135 6934
12f9a48f
GC		 6935 kvmclock_reset(vcpu);
6936
af585b92
GN		 6937 kvm_clear_async_pf_completion_queue(vcpu);
6938 kvm_async_pf_hash_reset(vcpu);
6939 vcpu->arch.apf.halted = false;
3842d135 6940
f5132b01
GN		 6941 kvm_pmu_reset(vcpu);
6942
66f7b72e
JS		 6943 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6944 vcpu->arch.regs_avail = ~0;
6945 vcpu->arch.regs_dirty = ~0;
6946
57f252f2 6947 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6948}
6949
66450a21
JK		 6950void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6951{
6952 struct kvm_segment cs;
6953
6954 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6955 cs.selector = vector << 8;
6956 cs.base = vector << 12;
6957 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6958 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6959}
6960
13a34e06 6961int kvm_arch_hardware_enable(void)
e9b11c17 6962{
ca84d1a2
ZA		 6963 struct kvm *kvm;
6964 struct kvm_vcpu *vcpu;
6965 int i;
0dd6a6ed
ZA		 6966 int ret;
6967 u64 local_tsc;
6968 u64 max_tsc = 0;
6969 bool stable, backwards_tsc = false;
18863bdd
AK		 6970
6971 kvm_shared_msr_cpu_online();
13a34e06 6972 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 6973 if (ret != 0)
6974 return ret;
6975
6976 local_tsc = native_read_tsc();
6977 stable = !check_tsc_unstable();
6978 list_for_each_entry(kvm, &vm_list, vm_list) {
6979 kvm_for_each_vcpu(i, vcpu, kvm) {
6980 if (!stable && vcpu->cpu == smp_processor_id())
6981 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6982 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6983 backwards_tsc = true;
6984 if (vcpu->arch.last_host_tsc > max_tsc)
6985 max_tsc = vcpu->arch.last_host_tsc;
6986 }
6987 }
6988 }
6989
6990 /*
6991 * Sometimes, even reliable TSCs go backwards. This happens on
6992 * platforms that reset TSC during suspend or hibernate actions, but
6993 * maintain synchronization. We must compensate. Fortunately, we can
6994 * detect that condition here, which happens early in CPU bringup,
6995 * before any KVM threads can be running. Unfortunately, we can't
6996 * bring the TSCs fully up to date with real time, as we aren't yet far
6997 * enough into CPU bringup that we know how much real time has actually
6998 * elapsed; our helper function, get_kernel_ns() will be using boot
6999 * variables that haven't been updated yet.
7000 *
7001 * So we simply find the maximum observed TSC above, then record the
7002 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7003 * the adjustment will be applied. Note that we accumulate
7004 * adjustments, in case multiple suspend cycles happen before some VCPU
7005 * gets a chance to run again. In the event that no KVM threads get a
7006 * chance to run, we will miss the entire elapsed period, as we'll have
7007 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7008 * loose cycle time. This isn't too big a deal, since the loss will be
7009 * uniform across all VCPUs (not to mention the scenario is extremely
7010 * unlikely). It is possible that a second hibernate recovery happens
7011 * much faster than a first, causing the observed TSC here to be
7012 * smaller; this would require additional padding adjustment, which is
7013 * why we set last_host_tsc to the local tsc observed here.
7014 *
7015 * N.B. - this code below runs only on platforms with reliable TSC,
7016 * as that is the only way backwards_tsc is set above. Also note
7017 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7018 * have the same delta_cyc adjustment applied if backwards_tsc
7019 * is detected. Note further, this adjustment is only done once,
7020 * as we reset last_host_tsc on all VCPUs to stop this from being
7021 * called multiple times (one for each physical CPU bringup).
7022 *
4a969980 7023 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7024 * will be compensated by the logic in vcpu_load, which sets the TSC to
7025 * catchup mode. This will catchup all VCPUs to real time, but cannot
7026 * guarantee that they stay in perfect synchronization.
7027 */
7028 if (backwards_tsc) {
7029 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7030 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7031 list_for_each_entry(kvm, &vm_list, vm_list) {
7032 kvm_for_each_vcpu(i, vcpu, kvm) {
7033 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7034 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 7035 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
7036 &vcpu->requests);
0dd6a6ed
ZA		 7037 }
7038
7039 /*
7040 * We have to disable TSC offset matching.. if you were
7041 * booting a VM while issuing an S4 host suspend....
7042 * you may have some problem. Solving this issue is
7043 * left as an exercise to the reader.
7044 */
7045 kvm->arch.last_tsc_nsec = 0;
7046 kvm->arch.last_tsc_write = 0;
7047 }
7048
7049 }
7050 return 0;
e9b11c17
ZX		 7051}
7052
13a34e06 7053void kvm_arch_hardware_disable(void)
e9b11c17 7054{
13a34e06
RK		 7055 kvm_x86_ops->hardware_disable();
7056 drop_user_return_notifiers();
e9b11c17
ZX		 7057}
7058
7059int kvm_arch_hardware_setup(void)
7060{
7061 return kvm_x86_ops->hardware_setup();
7062}
7063
7064void kvm_arch_hardware_unsetup(void)
7065{
7066 kvm_x86_ops->hardware_unsetup();
7067}
7068
7069void kvm_arch_check_processor_compat(void *rtn)
7070{
7071 kvm_x86_ops->check_processor_compatibility(rtn);
7072}
7073
3e515705
AK		 7074bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7075{
7076 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7077}
7078
54e9818f
GN		 7079struct static_key kvm_no_apic_vcpu __read_mostly;
7080
e9b11c17
ZX		 7081int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7082{
7083 struct page *page;
7084 struct kvm *kvm;
7085 int r;
7086
7087 BUG_ON(vcpu->kvm == NULL);
7088 kvm = vcpu->kvm;
7089
6aef266c 7090 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7091 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 7092 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 7093 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7094 else
a4535290 7095 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7096
7097 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7098 if (!page) {
7099 r = -ENOMEM;
7100 goto fail;
7101 }
ad312c7c 7102 vcpu->arch.pio_data = page_address(page);
e9b11c17 7103
cc578287 7104 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7105
e9b11c17
ZX		 7106 r = kvm_mmu_create(vcpu);
7107 if (r < 0)
7108 goto fail_free_pio_data;
7109
7110 if (irqchip_in_kernel(kvm)) {
7111 r = kvm_create_lapic(vcpu);
7112 if (r < 0)
7113 goto fail_mmu_destroy;
54e9818f
GN		 7114 } else
7115 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7116
890ca9ae
HY		 7117 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7118 GFP_KERNEL);
7119 if (!vcpu->arch.mce_banks) {
7120 r = -ENOMEM;
443c39bc 7121 goto fail_free_lapic;
890ca9ae
HY		 7122 }
7123 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7124
f1797359
WY		 7125 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7126 r = -ENOMEM;
f5f48ee1 7127 goto fail_free_mce_banks;
f1797359 7128 }
f5f48ee1 7129
66f7b72e
JS		 7130 r = fx_init(vcpu);
7131 if (r)
7132 goto fail_free_wbinvd_dirty_mask;
7133
ba904635 7134 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7135 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7136
7137 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7138 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7139
af585b92 7140 kvm_async_pf_hash_reset(vcpu);
f5132b01 7141 kvm_pmu_init(vcpu);
af585b92 7142
e9b11c17 7143 return 0;
66f7b72e
JS		 7144fail_free_wbinvd_dirty_mask:
7145 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7146fail_free_mce_banks:
7147 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7148fail_free_lapic:
7149 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7150fail_mmu_destroy:
7151 kvm_mmu_destroy(vcpu);
7152fail_free_pio_data:
ad312c7c 7153 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7154fail:
7155 return r;
7156}
7157
7158void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7159{
f656ce01
MT		 7160 int idx;
7161
f5132b01 7162 kvm_pmu_destroy(vcpu);
36cb93fd 7163 kfree(vcpu->arch.mce_banks);
e9b11c17 7164 kvm_free_lapic(vcpu);
f656ce01 7165 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7166 kvm_mmu_destroy(vcpu);
f656ce01 7167 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7168 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7169 if (!irqchip_in_kernel(vcpu->kvm))
7170 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7171}
d19a9cd2 7172
e790d9ef
RK		 7173void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7174{
ae97a3b8 7175 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7176}
7177
e08b9637 7178int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7179{
e08b9637
CO		 7180 if (type)
7181 return -EINVAL;
7182
f05e70ac 7183 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7184 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7185 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7186 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7187
5550af4d
SY		 7188 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7189 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7190 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7191 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7192 &kvm->arch.irq_sources_bitmap);
5550af4d 7193
038f8c11 7194 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7195 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7196 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7197
7198 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7199
7e44e449 7200 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7201 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7202
d89f5eff 7203 return 0;
d19a9cd2
ZX		 7204}
7205
7206static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7207{
9fc77441
MT		 7208 int r;
7209 r = vcpu_load(vcpu);
7210 BUG_ON(r);
d19a9cd2
ZX		 7211 kvm_mmu_unload(vcpu);
7212 vcpu_put(vcpu);
7213}
7214
7215static void kvm_free_vcpus(struct kvm *kvm)
7216{
7217 unsigned int i;
988a2cae 7218 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7219
7220 /*
7221 * Unpin any mmu pages first.
7222 */
af585b92
GN		 7223 kvm_for_each_vcpu(i, vcpu, kvm) {
7224 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7225 kvm_unload_vcpu_mmu(vcpu);
af585b92 7226 }
988a2cae
GN		 7227 kvm_for_each_vcpu(i, vcpu, kvm)
7228 kvm_arch_vcpu_free(vcpu);
7229
7230 mutex_lock(&kvm->lock);
7231 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7232 kvm->vcpus[i] = NULL;
d19a9cd2 7233
988a2cae
GN		 7234 atomic_set(&kvm->online_vcpus, 0);
7235 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7236}
7237
ad8ba2cd
SY		 7238void kvm_arch_sync_events(struct kvm *kvm)
7239{
332967a3 7240 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7241 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7242 kvm_free_all_assigned_devices(kvm);
aea924f6 7243 kvm_free_pit(kvm);
ad8ba2cd
SY		 7244}
7245
d19a9cd2
ZX		 7246void kvm_arch_destroy_vm(struct kvm *kvm)
7247{
27469d29
AH		 7248 if (current->mm == kvm->mm) {
7249 /*
7250 * Free memory regions allocated on behalf of userspace,
7251 * unless the the memory map has changed due to process exit
7252 * or fd copying.
7253 */
7254 struct kvm_userspace_memory_region mem;
7255 memset(&mem, 0, sizeof(mem));
7256 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7257 kvm_set_memory_region(kvm, &mem);
7258
7259 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7260 kvm_set_memory_region(kvm, &mem);
7261
7262 mem.slot = TSS_PRIVATE_MEMSLOT;
7263 kvm_set_memory_region(kvm, &mem);
7264 }
6eb55818 7265 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7266 kfree(kvm->arch.vpic);
7267 kfree(kvm->arch.vioapic);
d19a9cd2 7268 kvm_free_vcpus(kvm);
3d45830c
AK		 7269 if (kvm->arch.apic_access_page)
7270 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7271 if (kvm->arch.ept_identity_pagetable)
7272 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7273 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7274}
0de10343 7275
5587027c 7276void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7277 struct kvm_memory_slot *dont)
7278{
7279 int i;
7280
d89cc617
TY		 7281 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7282 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7283 kvm_kvfree(free->arch.rmap[i]);
7284 free->arch.rmap[i] = NULL;
77d11309 7285 }
d89cc617
TY		 7286 if (i == 0)
7287 continue;
7288
7289 if (!dont || free->arch.lpage_info[i - 1] !=
7290 dont->arch.lpage_info[i - 1]) {
7291 kvm_kvfree(free->arch.lpage_info[i - 1]);
7292 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7293 }
7294 }
7295}
7296
5587027c
AK		 7297int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7298 unsigned long npages)
db3fe4eb
TY		 7299{
7300 int i;
7301
d89cc617 7302 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7303 unsigned long ugfn;
7304 int lpages;
d89cc617 7305 int level = i + 1;
db3fe4eb
TY		 7306
7307 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7308 slot->base_gfn, level) + 1;
7309
d89cc617
TY		 7310 slot->arch.rmap[i] =
7311 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7312 if (!slot->arch.rmap[i])
77d11309 7313 goto out_free;
d89cc617
TY		 7314 if (i == 0)
7315 continue;
77d11309 7316
d89cc617
TY		 7317 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7318 sizeof(*slot->arch.lpage_info[i - 1]));
7319 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7320 goto out_free;
7321
7322 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7323 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7324 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7325 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7326 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7327 /*
7328 * If the gfn and userspace address are not aligned wrt each
7329 * other, or if explicitly asked to, disable large page
7330 * support for this slot
7331 */
7332 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7333 !kvm_largepages_enabled()) {
7334 unsigned long j;
7335
7336 for (j = 0; j < lpages; ++j)
d89cc617 7337 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7338 }
7339 }
7340
7341 return 0;
7342
7343out_free:
d89cc617
TY		 7344 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7345 kvm_kvfree(slot->arch.rmap[i]);
7346 slot->arch.rmap[i] = NULL;
7347 if (i == 0)
7348 continue;
7349
7350 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7351 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7352 }
7353 return -ENOMEM;
7354}
7355
e59dbe09
TY		 7356void kvm_arch_memslots_updated(struct kvm *kvm)
7357{
e6dff7d1
TY		 7358 /*
7359 * memslots->generation has been incremented.
7360 * mmio generation may have reached its maximum value.
7361 */
7362 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7363}
7364
f7784b8e
MT		 7365int kvm_arch_prepare_memory_region(struct kvm *kvm,
7366 struct kvm_memory_slot *memslot,
f7784b8e 7367 struct kvm_userspace_memory_region *mem,
7b6195a9 7368 enum kvm_mr_change change)
0de10343 7369{
7a905b14
TY		 7370 /*
7371 * Only private memory slots need to be mapped here since
7372 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7373 */
7b6195a9 7374 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7375 unsigned long userspace_addr;
604b38ac 7376
7a905b14
TY		 7377 /*
7378 * MAP_SHARED to prevent internal slot pages from being moved
7379 * by fork()/COW.
7380 */
7b6195a9 7381 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7382 PROT_READ | PROT_WRITE,
7383 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7384
7a905b14
TY		 7385 if (IS_ERR((void *)userspace_addr))
7386 return PTR_ERR((void *)userspace_addr);
604b38ac 7387
7a905b14 7388 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7389 }
7390
f7784b8e
MT		 7391 return 0;
7392}
7393
7394void kvm_arch_commit_memory_region(struct kvm *kvm,
7395 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7396 const struct kvm_memory_slot *old,
7397 enum kvm_mr_change change)
f7784b8e
MT		 7398{
7399
8482644a 7400 int nr_mmu_pages = 0;
f7784b8e 7401
8482644a 7402 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7403 int ret;
7404
8482644a
TY		 7405 ret = vm_munmap(old->userspace_addr,
7406 old->npages * PAGE_SIZE);
f7784b8e
MT		 7407 if (ret < 0)
7408 printk(KERN_WARNING
7409 "kvm_vm_ioctl_set_memory_region: "
7410 "failed to munmap memory\n");
7411 }
7412
48c0e4e9
XG		 7413 if (!kvm->arch.n_requested_mmu_pages)
7414 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7415
48c0e4e9 7416 if (nr_mmu_pages)
0de10343 7417 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7418 /*
7419 * Write protect all pages for dirty logging.
c126d94f
XG		 7420 *
7421 * All the sptes including the large sptes which point to this
7422 * slot are set to readonly. We can not create any new large
7423 * spte on this slot until the end of the logging.
7424 *
7425 * See the comments in fast_page_fault().
c972f3b1 7426 */
8482644a 7427 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7428 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7429}
1d737c8a 7430
2df72e9b 7431void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7432{
6ca18b69 7433 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7434}
7435
2df72e9b
MT		 7436void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7437 struct kvm_memory_slot *slot)
7438{
6ca18b69 7439 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7440}
7441
1d737c8a
ZX		 7442int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7443{
b6b8a145
JK		 7444 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7445 kvm_x86_ops->check_nested_events(vcpu, false);
7446
af585b92
GN		 7447 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7448 !vcpu->arch.apf.halted)
7449 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7450 || kvm_apic_has_events(vcpu)
6aef266c 7451 || vcpu->arch.pv.pv_unhalted
7460fb4a 7452 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7453 (kvm_arch_interrupt_allowed(vcpu) &&
7454 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7455}
5736199a 7456
b6d33834 7457int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7458{
b6d33834 7459 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7460}
78646121
GN		 7461
7462int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7463{
7464 return kvm_x86_ops->interrupt_allowed(vcpu);
7465}
229456fc 7466
f92653ee
JK		 7467bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7468{
7469 unsigned long current_rip = kvm_rip_read(vcpu) +
7470 get_segment_base(vcpu, VCPU_SREG_CS);
7471
7472 return current_rip == linear_rip;
7473}
7474EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7475
94fe45da
JK		 7476unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7477{
7478 unsigned long rflags;
7479
7480 rflags = kvm_x86_ops->get_rflags(vcpu);
7481 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7482 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7483 return rflags;
7484}
7485EXPORT_SYMBOL_GPL(kvm_get_rflags);
7486
6addfc42 7487static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 7488{
7489 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7490 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7491 rflags |= X86_EFLAGS_TF;
94fe45da 7492 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 7493}
7494
7495void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7496{
7497 __kvm_set_rflags(vcpu, rflags);
3842d135 7498 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7499}
7500EXPORT_SYMBOL_GPL(kvm_set_rflags);
7501
56028d08
GN		 7502void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7503{
7504 int r;
7505
fb67e14f 7506 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7507 work->wakeup_all)
56028d08
GN		 7508 return;
7509
7510 r = kvm_mmu_reload(vcpu);
7511 if (unlikely(r))
7512 return;
7513
fb67e14f
XG		 7514 if (!vcpu->arch.mmu.direct_map &&
7515 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7516 return;
7517
56028d08
GN		 7518 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7519}
7520
af585b92
GN		 7521static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7522{
7523 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7524}
7525
7526static inline u32 kvm_async_pf_next_probe(u32 key)
7527{
7528 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7529}
7530
7531static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7532{
7533 u32 key = kvm_async_pf_hash_fn(gfn);
7534
7535 while (vcpu->arch.apf.gfns[key] != ~0)
7536 key = kvm_async_pf_next_probe(key);
7537
7538 vcpu->arch.apf.gfns[key] = gfn;
7539}
7540
7541static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7542{
7543 int i;
7544 u32 key = kvm_async_pf_hash_fn(gfn);
7545
7546 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7547 (vcpu->arch.apf.gfns[key] != gfn &&
7548 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7549 key = kvm_async_pf_next_probe(key);
7550
7551 return key;
7552}
7553
7554bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7555{
7556 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7557}
7558
7559static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7560{
7561 u32 i, j, k;
7562
7563 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7564 while (true) {
7565 vcpu->arch.apf.gfns[i] = ~0;
7566 do {
7567 j = kvm_async_pf_next_probe(j);
7568 if (vcpu->arch.apf.gfns[j] == ~0)
7569 return;
7570 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7571 /*
7572 * k lies cyclically in ]i,j]
7573 * | i.k.j |
7574 * |....j i.k.| or |.k..j i...|
7575 */
7576 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7577 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7578 i = j;
7579 }
7580}
7581
7c90705b
GN		 7582static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7583{
7584
7585 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7586 sizeof(val));
7587}
7588
af585b92
GN		 7589void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7590 struct kvm_async_pf *work)
7591{
6389ee94
AK		 7592 struct x86_exception fault;
7593
7c90705b 7594 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7595 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7596
7597 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7598 (vcpu->arch.apf.send_user_only &&
7599 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7600 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7601 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7602 fault.vector = PF_VECTOR;
7603 fault.error_code_valid = true;
7604 fault.error_code = 0;
7605 fault.nested_page_fault = false;
7606 fault.address = work->arch.token;
7607 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7608 }
af585b92
GN		 7609}
7610
7611void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7612 struct kvm_async_pf *work)
7613{
6389ee94
AK		 7614 struct x86_exception fault;
7615
7c90705b 7616 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7617 if (work->wakeup_all)
7c90705b
GN		 7618 work->arch.token = ~0; /* broadcast wakeup */
7619 else
7620 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7621
7622 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7623 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7624 fault.vector = PF_VECTOR;
7625 fault.error_code_valid = true;
7626 fault.error_code = 0;
7627 fault.nested_page_fault = false;
7628 fault.address = work->arch.token;
7629 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7630 }
e6d53e3b 7631 vcpu->arch.apf.halted = false;
a4fa1635 7632 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7633}
7634
7635bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7636{
7637 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7638 return true;
7639 else
7640 return !kvm_event_needs_reinjection(vcpu) &&
7641 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7642}
7643
e0f0bbc5
AW		 7644void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7645{
7646 atomic_inc(&kvm->arch.noncoherent_dma_count);
7647}
7648EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7649
7650void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7651{
7652 atomic_dec(&kvm->arch.noncoherent_dma_count);
7653}
7654EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7655
7656bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7657{
7658 return atomic_read(&kvm->arch.noncoherent_dma_count);
7659}
7660EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7661
229456fc
MT		 7662EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7663EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7664EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7665EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7666EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7667EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7668EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7669EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7670EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7671EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7672EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7673EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7674EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 7675EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
Linux 6.x block layer and io_uring tree(s)