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x86/kvm: virt_xxx memory barriers instead of mandatory barriers
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO		 35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG		 38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT		 52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW		 54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad
IM		 56#include <linux/sched/stat.h>
57
aec51dc4 58#include <trace/events/kvm.h>
2ed152af 59
24f1e32c 60#include <asm/debugreg.h>
d825ed0a 61#include <asm/msr.h>
a5f61300 62#include <asm/desc.h>
890ca9ae 63#include <asm/mce.h>
f89e32e0 64#include <linux/kernel_stat.h>
78f7f1e5 65#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 66#include <asm/pvclock.h>
217fc9cf 67#include <asm/div64.h>
efc64404 68#include <asm/irq_remapping.h>
043405e1 69
d1898b73
DH		 70#define CREATE_TRACE_POINTS
71#include "trace.h"
72
313a3dc7 73#define MAX_IO_MSRS 256
890ca9ae 74#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 75u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
76EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 77
0f65dd70
AK		 78#define emul_to_vcpu(ctxt) \
79 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
80
50a37eb4
JR		 81/* EFER defaults:
82 * - enable syscall per default because its emulated by KVM
83 * - enable LME and LMA per default on 64 bit KVM
84 */
85#ifdef CONFIG_X86_64
1260edbe
LJ		 86static
87u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 88#else
1260edbe 89static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 90#endif
313a3dc7 91
ba1389b7
AK		 92#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
93#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 94
c519265f
RK		 95#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
96 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 97
cb142eb7 98static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 99static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 100static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 101static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 102
893590c7 103struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 104EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 105
893590c7 106static bool __read_mostly ignore_msrs = 0;
476bc001 107module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 108
9ed96e87
MT		 109unsigned int min_timer_period_us = 500;
110module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
111
630994b3
MT		 112static bool __read_mostly kvmclock_periodic_sync = true;
113module_param(kvmclock_periodic_sync, bool, S_IRUGO);
114
893590c7 115bool __read_mostly kvm_has_tsc_control;
92a1f12d 116EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 117u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 118EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 119u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
120EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
121u64 __read_mostly kvm_max_tsc_scaling_ratio;
122EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 123u64 __read_mostly kvm_default_tsc_scaling_ratio;
124EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 125
cc578287 126/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 127static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 128module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
129
d0659d94 130/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 131unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT		 132module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
133
52004014
FW		 134static bool __read_mostly vector_hashing = true;
135module_param(vector_hashing, bool, S_IRUGO);
136
893590c7 137static bool __read_mostly backwards_tsc_observed = false;
16a96021 138
18863bdd
AK		 139#define KVM_NR_SHARED_MSRS 16
140
141struct kvm_shared_msrs_global {
142 int nr;
2bf78fa7 143 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 144};
145
146struct kvm_shared_msrs {
147 struct user_return_notifier urn;
148 bool registered;
2bf78fa7
SY		 149 struct kvm_shared_msr_values {
150 u64 host;
151 u64 curr;
152 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 153};
154
155static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 156static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 157
417bc304 158struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 159 { "pf_fixed", VCPU_STAT(pf_fixed) },
160 { "pf_guest", VCPU_STAT(pf_guest) },
161 { "tlb_flush", VCPU_STAT(tlb_flush) },
162 { "invlpg", VCPU_STAT(invlpg) },
163 { "exits", VCPU_STAT(exits) },
164 { "io_exits", VCPU_STAT(io_exits) },
165 { "mmio_exits", VCPU_STAT(mmio_exits) },
166 { "signal_exits", VCPU_STAT(signal_exits) },
167 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 168 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 169 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 170 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 171 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 172 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 173 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 174 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 175 { "request_irq", VCPU_STAT(request_irq_exits) },
176 { "irq_exits", VCPU_STAT(irq_exits) },
177 { "host_state_reload", VCPU_STAT(host_state_reload) },
178 { "efer_reload", VCPU_STAT(efer_reload) },
179 { "fpu_reload", VCPU_STAT(fpu_reload) },
180 { "insn_emulation", VCPU_STAT(insn_emulation) },
181 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 182 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 183 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 184 { "req_event", VCPU_STAT(req_event) },
4cee5764
AK		 185 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
186 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
187 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
188 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
189 { "mmu_flooded", VM_STAT(mmu_flooded) },
190 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 191 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 192 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 193 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 194 { "largepages", VM_STAT(lpages) },
f3414bc7
DM		 195 { "max_mmu_page_hash_collisions",
196 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 197 { NULL }
198};
199
2acf923e
DC		 200u64 __read_mostly host_xcr0;
201
b6785def 202static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 203
af585b92
GN		 204static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
205{
206 int i;
207 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
208 vcpu->arch.apf.gfns[i] = ~0;
209}
210
18863bdd
AK		 211static void kvm_on_user_return(struct user_return_notifier *urn)
212{
213 unsigned slot;
18863bdd
AK		 214 struct kvm_shared_msrs *locals
215 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 216 struct kvm_shared_msr_values *values;
1650b4eb
IA		 217 unsigned long flags;
218
219 /*
220 * Disabling irqs at this point since the following code could be
221 * interrupted and executed through kvm_arch_hardware_disable()
222 */
223 local_irq_save(flags);
224 if (locals->registered) {
225 locals->registered = false;
226 user_return_notifier_unregister(urn);
227 }
228 local_irq_restore(flags);
18863bdd 229 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 230 values = &locals->values[slot];
231 if (values->host != values->curr) {
232 wrmsrl(shared_msrs_global.msrs[slot], values->host);
233 values->curr = values->host;
18863bdd
AK		 234 }
235 }
18863bdd
AK		 236}
237
2bf78fa7 238static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 239{
18863bdd 240 u64 value;
013f6a5d
MT		 241 unsigned int cpu = smp_processor_id();
242 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 243
2bf78fa7
SY		 244 /* only read, and nobody should modify it at this time,
245 * so don't need lock */
246 if (slot >= shared_msrs_global.nr) {
247 printk(KERN_ERR "kvm: invalid MSR slot!");
248 return;
249 }
250 rdmsrl_safe(msr, &value);
251 smsr->values[slot].host = value;
252 smsr->values[slot].curr = value;
253}
254
255void kvm_define_shared_msr(unsigned slot, u32 msr)
256{
0123be42 257 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 258 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 259 if (slot >= shared_msrs_global.nr)
260 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 261}
262EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
263
264static void kvm_shared_msr_cpu_online(void)
265{
266 unsigned i;
18863bdd
AK		 267
268 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 269 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 270}
271
8b3c3104 272int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 273{
013f6a5d
MT		 274 unsigned int cpu = smp_processor_id();
275 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 276 int err;
18863bdd 277
2bf78fa7 278 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 279 return 0;
2bf78fa7 280 smsr->values[slot].curr = value;
8b3c3104
AH		 281 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
282 if (err)
283 return 1;
284
18863bdd
AK		 285 if (!smsr->registered) {
286 smsr->urn.on_user_return = kvm_on_user_return;
287 user_return_notifier_register(&smsr->urn);
288 smsr->registered = true;
289 }
8b3c3104 290 return 0;
18863bdd
AK		 291}
292EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
293
13a34e06 294static void drop_user_return_notifiers(void)
3548bab5 295{
013f6a5d
MT		 296 unsigned int cpu = smp_processor_id();
297 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 298
299 if (smsr->registered)
300 kvm_on_user_return(&smsr->urn);
301}
302
6866b83e
CO		 303u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
304{
8a5a87d9 305 return vcpu->arch.apic_base;
6866b83e
CO		 306}
307EXPORT_SYMBOL_GPL(kvm_get_apic_base);
308
58cb628d
JK		 309int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
310{
311 u64 old_state = vcpu->arch.apic_base &
312 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
313 u64 new_state = msr_info->data &
314 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
315 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
316 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
317
318 if (!msr_info->host_initiated &&
319 ((msr_info->data & reserved_bits) != 0 ||
320 new_state == X2APIC_ENABLE ||
321 (new_state == MSR_IA32_APICBASE_ENABLE &&
322 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
323 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
324 old_state == 0)))
325 return 1;
326
327 kvm_lapic_set_base(vcpu, msr_info->data);
328 return 0;
6866b83e
CO		 329}
330EXPORT_SYMBOL_GPL(kvm_set_apic_base);
331
2605fc21 332asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 333{
334 /* Fault while not rebooting. We want the trace. */
335 BUG();
336}
337EXPORT_SYMBOL_GPL(kvm_spurious_fault);
338
3fd28fce
ED		 339#define EXCPT_BENIGN 0
340#define EXCPT_CONTRIBUTORY 1
341#define EXCPT_PF 2
342
343static int exception_class(int vector)
344{
345 switch (vector) {
346 case PF_VECTOR:
347 return EXCPT_PF;
348 case DE_VECTOR:
349 case TS_VECTOR:
350 case NP_VECTOR:
351 case SS_VECTOR:
352 case GP_VECTOR:
353 return EXCPT_CONTRIBUTORY;
354 default:
355 break;
356 }
357 return EXCPT_BENIGN;
358}
359
d6e8c854
NA		 360#define EXCPT_FAULT 0
361#define EXCPT_TRAP 1
362#define EXCPT_ABORT 2
363#define EXCPT_INTERRUPT 3
364
365static int exception_type(int vector)
366{
367 unsigned int mask;
368
369 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
370 return EXCPT_INTERRUPT;
371
372 mask = 1 << vector;
373
374 /* #DB is trap, as instruction watchpoints are handled elsewhere */
375 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
376 return EXCPT_TRAP;
377
378 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
379 return EXCPT_ABORT;
380
381 /* Reserved exceptions will result in fault */
382 return EXCPT_FAULT;
383}
384
3fd28fce 385static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 386 unsigned nr, bool has_error, u32 error_code,
387 bool reinject)
3fd28fce
ED		 388{
389 u32 prev_nr;
390 int class1, class2;
391
3842d135
AK		 392 kvm_make_request(KVM_REQ_EVENT, vcpu);
393
3fd28fce
ED		 394 if (!vcpu->arch.exception.pending) {
395 queue:
3ffb2468
NA		 396 if (has_error && !is_protmode(vcpu))
397 has_error = false;
3fd28fce
ED		 398 vcpu->arch.exception.pending = true;
399 vcpu->arch.exception.has_error_code = has_error;
400 vcpu->arch.exception.nr = nr;
401 vcpu->arch.exception.error_code = error_code;
3f0fd292 402 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 403 return;
404 }
405
406 /* to check exception */
407 prev_nr = vcpu->arch.exception.nr;
408 if (prev_nr == DF_VECTOR) {
409 /* triple fault -> shutdown */
a8eeb04a 410 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 411 return;
412 }
413 class1 = exception_class(prev_nr);
414 class2 = exception_class(nr);
415 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
416 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
417 /* generate double fault per SDM Table 5-5 */
418 vcpu->arch.exception.pending = true;
419 vcpu->arch.exception.has_error_code = true;
420 vcpu->arch.exception.nr = DF_VECTOR;
421 vcpu->arch.exception.error_code = 0;
422 } else
423 /* replace previous exception with a new one in a hope
424 that instruction re-execution will regenerate lost
425 exception */
426 goto queue;
427}
428
298101da
AK		 429void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
430{
ce7ddec4 431 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 432}
433EXPORT_SYMBOL_GPL(kvm_queue_exception);
434
ce7ddec4
JR		 435void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
436{
437 kvm_multiple_exception(vcpu, nr, false, 0, true);
438}
439EXPORT_SYMBOL_GPL(kvm_requeue_exception);
440
6affcbed 441int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 442{
db8fcefa
AP		 443 if (err)
444 kvm_inject_gp(vcpu, 0);
445 else
6affcbed
KH		 446 return kvm_skip_emulated_instruction(vcpu);
447
448 return 1;
db8fcefa
AP		 449}
450EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 451
6389ee94 452void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 453{
454 ++vcpu->stat.pf_guest;
6389ee94
AK		 455 vcpu->arch.cr2 = fault->address;
456 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 457}
27d6c865 458EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 459
ef54bcfe 460static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 461{
6389ee94
AK		 462 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
463 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 464 else
6389ee94 465 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 466
467 return fault->nested_page_fault;
d4f8cf66
JR		 468}
469
3419ffc8
SY		 470void kvm_inject_nmi(struct kvm_vcpu *vcpu)
471{
7460fb4a
AK		 472 atomic_inc(&vcpu->arch.nmi_queued);
473 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 474}
475EXPORT_SYMBOL_GPL(kvm_inject_nmi);
476
298101da
AK		 477void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
478{
ce7ddec4 479 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 480}
481EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
482
ce7ddec4
JR		 483void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
484{
485 kvm_multiple_exception(vcpu, nr, true, error_code, true);
486}
487EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
488
0a79b009
AK		 489/*
490 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
491 * a #GP and return false.
492 */
493bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 494{
0a79b009
AK		 495 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
496 return true;
497 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
498 return false;
298101da 499}
0a79b009 500EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 501
16f8a6f9
NA		 502bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
503{
504 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
505 return true;
506
507 kvm_queue_exception(vcpu, UD_VECTOR);
508 return false;
509}
510EXPORT_SYMBOL_GPL(kvm_require_dr);
511
ec92fe44
JR		 512/*
513 * This function will be used to read from the physical memory of the currently
54bf36aa 514 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 515 * can read from guest physical or from the guest's guest physical memory.
516 */
517int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
518 gfn_t ngfn, void *data, int offset, int len,
519 u32 access)
520{
54987b7a 521 struct x86_exception exception;
ec92fe44
JR		 522 gfn_t real_gfn;
523 gpa_t ngpa;
524
525 ngpa = gfn_to_gpa(ngfn);
54987b7a 526 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 527 if (real_gfn == UNMAPPED_GVA)
528 return -EFAULT;
529
530 real_gfn = gpa_to_gfn(real_gfn);
531
54bf36aa 532 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 533}
534EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
535
69b0049a 536static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 537 void *data, int offset, int len, u32 access)
538{
539 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
540 data, offset, len, access);
541}
542
a03490ed
CO		 543/*
544 * Load the pae pdptrs. Return true is they are all valid.
545 */
ff03a073 546int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 547{
548 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
549 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
550 int i;
551 int ret;
ff03a073 552 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 553
ff03a073
JR		 554 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
555 offset * sizeof(u64), sizeof(pdpte),
556 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 557 if (ret < 0) {
558 ret = 0;
559 goto out;
560 }
561 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 562 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG		 563 (pdpte[i] &
564 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO		 565 ret = 0;
566 goto out;
567 }
568 }
569 ret = 1;
570
ff03a073 571 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 572 __set_bit(VCPU_EXREG_PDPTR,
573 (unsigned long *)&vcpu->arch.regs_avail);
574 __set_bit(VCPU_EXREG_PDPTR,
575 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 576out:
a03490ed
CO		 577
578 return ret;
579}
cc4b6871 580EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 581
9ed38ffa 582bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 583{
ff03a073 584 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 585 bool changed = true;
3d06b8bf
JR		 586 int offset;
587 gfn_t gfn;
d835dfec
AK		 588 int r;
589
590 if (is_long_mode(vcpu) || !is_pae(vcpu))
591 return false;
592
6de4f3ad
AK		 593 if (!test_bit(VCPU_EXREG_PDPTR,
594 (unsigned long *)&vcpu->arch.regs_avail))
595 return true;
596
9f8fe504
AK		 597 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
598 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 599 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
600 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 601 if (r < 0)
602 goto out;
ff03a073 603 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 604out:
d835dfec
AK		 605
606 return changed;
607}
9ed38ffa 608EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 609
49a9b07e 610int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 611{
aad82703 612 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 613 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 614
f9a48e6a
AK		 615 cr0 |= X86_CR0_ET;
616
ab344828 617#ifdef CONFIG_X86_64
0f12244f
GN		 618 if (cr0 & 0xffffffff00000000UL)
619 return 1;
ab344828
GN		 620#endif
621
622 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 623
0f12244f
GN		 624 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
625 return 1;
a03490ed 626
0f12244f
GN		 627 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
628 return 1;
a03490ed
CO		 629
630 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
631#ifdef CONFIG_X86_64
f6801dff 632 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 633 int cs_db, cs_l;
634
0f12244f
GN		 635 if (!is_pae(vcpu))
636 return 1;
a03490ed 637 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 638 if (cs_l)
639 return 1;
a03490ed
CO		 640 } else
641#endif
ff03a073 642 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 643 kvm_read_cr3(vcpu)))
0f12244f 644 return 1;
a03490ed
CO		 645 }
646
ad756a16
MJ		 647 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
648 return 1;
649
a03490ed 650 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 651
d170c419 652 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 653 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 654 kvm_async_pf_hash_reset(vcpu);
655 }
e5f3f027 656
aad82703
SY		 657 if ((cr0 ^ old_cr0) & update_bits)
658 kvm_mmu_reset_context(vcpu);
b18d5431 659
879ae188
LE		 660 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
661 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
662 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 663 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
664
0f12244f
GN		 665 return 0;
666}
2d3ad1f4 667EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 668
2d3ad1f4 669void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 670{
49a9b07e 671 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 672}
2d3ad1f4 673EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 674
42bdf991
MT		 675static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
676{
677 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
678 !vcpu->guest_xcr0_loaded) {
679 /* kvm_set_xcr() also depends on this */
680 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
681 vcpu->guest_xcr0_loaded = 1;
682 }
683}
684
685static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
686{
687 if (vcpu->guest_xcr0_loaded) {
688 if (vcpu->arch.xcr0 != host_xcr0)
689 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
690 vcpu->guest_xcr0_loaded = 0;
691 }
692}
693
69b0049a 694static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 695{
56c103ec
LJ		 696 u64 xcr0 = xcr;
697 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 698 u64 valid_bits;
2acf923e
DC		 699
700 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
701 if (index != XCR_XFEATURE_ENABLED_MASK)
702 return 1;
d91cab78 703 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 704 return 1;
d91cab78 705 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 706 return 1;
46c34cb0
PB		 707
708 /*
709 * Do not allow the guest to set bits that we do not support
710 * saving. However, xcr0 bit 0 is always set, even if the
711 * emulated CPU does not support XSAVE (see fx_init).
712 */
d91cab78 713 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 714 if (xcr0 & ~valid_bits)
2acf923e 715 return 1;
46c34cb0 716
d91cab78
DH		 717 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
718 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 719 return 1;
720
d91cab78
DH		 721 if (xcr0 & XFEATURE_MASK_AVX512) {
722 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 723 return 1;
d91cab78 724 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 725 return 1;
726 }
2acf923e 727 vcpu->arch.xcr0 = xcr0;
56c103ec 728
d91cab78 729 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 730 kvm_update_cpuid(vcpu);
2acf923e
DC		 731 return 0;
732}
733
734int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
735{
764bcbc5
Z		 736 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
737 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 738 kvm_inject_gp(vcpu, 0);
739 return 1;
740 }
741 return 0;
742}
743EXPORT_SYMBOL_GPL(kvm_set_xcr);
744
a83b29c6 745int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 746{
fc78f519 747 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 748 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 749 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 750
0f12244f
GN		 751 if (cr4 & CR4_RESERVED_BITS)
752 return 1;
a03490ed 753
2acf923e
DC		 754 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
755 return 1;
756
c68b734f
YW		 757 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
758 return 1;
759
97ec8c06
FW		 760 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
761 return 1;
762
afcbf13f 763 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 764 return 1;
765
b9baba86
HH		 766 if (!guest_cpuid_has_pku(vcpu) && (cr4 & X86_CR4_PKE))
767 return 1;
768
a03490ed 769 if (is_long_mode(vcpu)) {
0f12244f
GN		 770 if (!(cr4 & X86_CR4_PAE))
771 return 1;
a2edf57f
AK		 772 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
773 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 774 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
775 kvm_read_cr3(vcpu)))
0f12244f
GN		 776 return 1;
777
ad756a16
MJ		 778 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
779 if (!guest_cpuid_has_pcid(vcpu))
780 return 1;
781
782 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
783 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
784 return 1;
785 }
786
5e1746d6 787 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 788 return 1;
a03490ed 789
ad756a16
MJ		 790 if (((cr4 ^ old_cr4) & pdptr_bits) ||
791 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 792 kvm_mmu_reset_context(vcpu);
0f12244f 793
b9baba86 794 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 795 kvm_update_cpuid(vcpu);
2acf923e 796
0f12244f
GN		 797 return 0;
798}
2d3ad1f4 799EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 800
2390218b 801int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 802{
ac146235 803#ifdef CONFIG_X86_64
9d88fca7 804 cr3 &= ~CR3_PCID_INVD;
ac146235 805#endif
9d88fca7 806
9f8fe504 807 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 808 kvm_mmu_sync_roots(vcpu);
77c3913b 809 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 810 return 0;
d835dfec
AK		 811 }
812
a03490ed 813 if (is_long_mode(vcpu)) {
d9f89b88
JK		 814 if (cr3 & CR3_L_MODE_RESERVED_BITS)
815 return 1;
816 } else if (is_pae(vcpu) && is_paging(vcpu) &&
817 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 818 return 1;
a03490ed 819
0f12244f 820 vcpu->arch.cr3 = cr3;
aff48baa 821 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 822 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 823 return 0;
824}
2d3ad1f4 825EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 826
eea1cff9 827int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 828{
0f12244f
GN		 829 if (cr8 & CR8_RESERVED_BITS)
830 return 1;
35754c98 831 if (lapic_in_kernel(vcpu))
a03490ed
CO		 832 kvm_lapic_set_tpr(vcpu, cr8);
833 else
ad312c7c 834 vcpu->arch.cr8 = cr8;
0f12244f
GN		 835 return 0;
836}
2d3ad1f4 837EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 838
2d3ad1f4 839unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 840{
35754c98 841 if (lapic_in_kernel(vcpu))
a03490ed
CO		 842 return kvm_lapic_get_cr8(vcpu);
843 else
ad312c7c 844 return vcpu->arch.cr8;
a03490ed 845}
2d3ad1f4 846EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 847
ae561ede
NA		 848static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
849{
850 int i;
851
852 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
853 for (i = 0; i < KVM_NR_DB_REGS; i++)
854 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
855 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
856 }
857}
858
73aaf249
JK		 859static void kvm_update_dr6(struct kvm_vcpu *vcpu)
860{
861 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
862 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
863}
864
c8639010
JK		 865static void kvm_update_dr7(struct kvm_vcpu *vcpu)
866{
867 unsigned long dr7;
868
869 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
870 dr7 = vcpu->arch.guest_debug_dr7;
871 else
872 dr7 = vcpu->arch.dr7;
873 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 874 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
875 if (dr7 & DR7_BP_EN_MASK)
876 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 877}
878
6f43ed01
NA		 879static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
880{
881 u64 fixed = DR6_FIXED_1;
882
883 if (!guest_cpuid_has_rtm(vcpu))
884 fixed |= DR6_RTM;
885 return fixed;
886}
887
338dbc97 888static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 889{
890 switch (dr) {
891 case 0 ... 3:
892 vcpu->arch.db[dr] = val;
893 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
894 vcpu->arch.eff_db[dr] = val;
895 break;
896 case 4:
020df079
GN		 897 /* fall through */
898 case 6:
338dbc97
GN		 899 if (val & 0xffffffff00000000ULL)
900 return -1; /* #GP */
6f43ed01 901 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 902 kvm_update_dr6(vcpu);
020df079
GN		 903 break;
904 case 5:
020df079
GN		 905 /* fall through */
906 default: /* 7 */
338dbc97
GN		 907 if (val & 0xffffffff00000000ULL)
908 return -1; /* #GP */
020df079 909 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 910 kvm_update_dr7(vcpu);
020df079
GN		 911 break;
912 }
913
914 return 0;
915}
338dbc97
GN		 916
917int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
918{
16f8a6f9 919 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 920 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 921 return 1;
922 }
923 return 0;
338dbc97 924}
020df079
GN		 925EXPORT_SYMBOL_GPL(kvm_set_dr);
926
16f8a6f9 927int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 928{
929 switch (dr) {
930 case 0 ... 3:
931 *val = vcpu->arch.db[dr];
932 break;
933 case 4:
020df079
GN		 934 /* fall through */
935 case 6:
73aaf249
JK		 936 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
937 *val = vcpu->arch.dr6;
938 else
939 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 940 break;
941 case 5:
020df079
GN		 942 /* fall through */
943 default: /* 7 */
944 *val = vcpu->arch.dr7;
945 break;
946 }
338dbc97
GN		 947 return 0;
948}
020df079
GN		 949EXPORT_SYMBOL_GPL(kvm_get_dr);
950
022cd0e8
AK		 951bool kvm_rdpmc(struct kvm_vcpu *vcpu)
952{
953 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
954 u64 data;
955 int err;
956
c6702c9d 957 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 958 if (err)
959 return err;
960 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
961 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
962 return err;
963}
964EXPORT_SYMBOL_GPL(kvm_rdpmc);
965
043405e1
CO		 966/*
967 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
968 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
969 *
970 * This list is modified at module load time to reflect the
e3267cbb 971 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 972 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
973 * may depend on host virtualization features rather than host cpu features.
043405e1 974 */
e3267cbb 975
043405e1
CO		 976static u32 msrs_to_save[] = {
977 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 978 MSR_STAR,
043405e1
CO		 979#ifdef CONFIG_X86_64
980 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
981#endif
b3897a49 982 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 983 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
043405e1
CO		 984};
985
986static unsigned num_msrs_to_save;
987
62ef68bb
PB		 988static u32 emulated_msrs[] = {
989 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
990 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
991 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
992 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
e7d9513b
AS		 993 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
994 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 995 HV_X64_MSR_RESET,
11c4b1ca 996 HV_X64_MSR_VP_INDEX,
9eec50b8 997 HV_X64_MSR_VP_RUNTIME,
5c919412 998 HV_X64_MSR_SCONTROL,
1f4b34f8 999 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB		 1000 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1001 MSR_KVM_PV_EOI_EN,
1002
ba904635 1003 MSR_IA32_TSC_ADJUST,
a3e06bbe 1004 MSR_IA32_TSCDEADLINE,
043405e1 1005 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1006 MSR_IA32_MCG_STATUS,
1007 MSR_IA32_MCG_CTL,
c45dcc71 1008 MSR_IA32_MCG_EXT_CTL,
64d60670 1009 MSR_IA32_SMBASE,
043405e1
CO		 1010};
1011
62ef68bb
PB		 1012static unsigned num_emulated_msrs;
1013
384bb783 1014bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1015{
b69e8cae 1016 if (efer & efer_reserved_bits)
384bb783 1017 return false;
15c4a640 1018
1b2fd70c
AG		 1019 if (efer & EFER_FFXSR) {
1020 struct kvm_cpuid_entry2 *feat;
1021
1022 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1023 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 1024 return false;
1b2fd70c
AG		 1025 }
1026
d8017474
AG		 1027 if (efer & EFER_SVME) {
1028 struct kvm_cpuid_entry2 *feat;
1029
1030 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 1031 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 1032 return false;
d8017474
AG		 1033 }
1034
384bb783
JK		 1035 return true;
1036}
1037EXPORT_SYMBOL_GPL(kvm_valid_efer);
1038
1039static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1040{
1041 u64 old_efer = vcpu->arch.efer;
1042
1043 if (!kvm_valid_efer(vcpu, efer))
1044 return 1;
1045
1046 if (is_paging(vcpu)
1047 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1048 return 1;
1049
15c4a640 1050 efer &= ~EFER_LMA;
f6801dff 1051 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1052
a3d204e2
SY		 1053 kvm_x86_ops->set_efer(vcpu, efer);
1054
aad82703
SY		 1055 /* Update reserved bits */
1056 if ((efer ^ old_efer) & EFER_NX)
1057 kvm_mmu_reset_context(vcpu);
1058
b69e8cae 1059 return 0;
15c4a640
CO		 1060}
1061
f2b4b7dd
JR		 1062void kvm_enable_efer_bits(u64 mask)
1063{
1064 efer_reserved_bits &= ~mask;
1065}
1066EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1067
15c4a640
CO		 1068/*
1069 * Writes msr value into into the appropriate "register".
1070 * Returns 0 on success, non-0 otherwise.
1071 * Assumes vcpu_load() was already called.
1072 */
8fe8ab46 1073int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1074{
854e8bb1
NA		 1075 switch (msr->index) {
1076 case MSR_FS_BASE:
1077 case MSR_GS_BASE:
1078 case MSR_KERNEL_GS_BASE:
1079 case MSR_CSTAR:
1080 case MSR_LSTAR:
1081 if (is_noncanonical_address(msr->data))
1082 return 1;
1083 break;
1084 case MSR_IA32_SYSENTER_EIP:
1085 case MSR_IA32_SYSENTER_ESP:
1086 /*
1087 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1088 * non-canonical address is written on Intel but not on
1089 * AMD (which ignores the top 32-bits, because it does
1090 * not implement 64-bit SYSENTER).
1091 *
1092 * 64-bit code should hence be able to write a non-canonical
1093 * value on AMD. Making the address canonical ensures that
1094 * vmentry does not fail on Intel after writing a non-canonical
1095 * value, and that something deterministic happens if the guest
1096 * invokes 64-bit SYSENTER.
1097 */
1098 msr->data = get_canonical(msr->data);
1099 }
8fe8ab46 1100 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1101}
854e8bb1 1102EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1103
313a3dc7
CO		 1104/*
1105 * Adapt set_msr() to msr_io()'s calling convention
1106 */
609e36d3
PB		 1107static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1108{
1109 struct msr_data msr;
1110 int r;
1111
1112 msr.index = index;
1113 msr.host_initiated = true;
1114 r = kvm_get_msr(vcpu, &msr);
1115 if (r)
1116 return r;
1117
1118 *data = msr.data;
1119 return 0;
1120}
1121
313a3dc7
CO		 1122static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1123{
8fe8ab46
WA		 1124 struct msr_data msr;
1125
1126 msr.data = *data;
1127 msr.index = index;
1128 msr.host_initiated = true;
1129 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1130}
1131
16e8d74d
MT		 1132#ifdef CONFIG_X86_64
1133struct pvclock_gtod_data {
1134 seqcount_t seq;
1135
1136 struct { /* extract of a clocksource struct */
1137 int vclock_mode;
a5a1d1c2
TG		 1138 u64 cycle_last;
1139 u64 mask;
16e8d74d
MT		 1140 u32 mult;
1141 u32 shift;
1142 } clock;
1143
cbcf2dd3
TG		 1144 u64 boot_ns;
1145 u64 nsec_base;
55dd00a7 1146 u64 wall_time_sec;
16e8d74d
MT		 1147};
1148
1149static struct pvclock_gtod_data pvclock_gtod_data;
1150
1151static void update_pvclock_gtod(struct timekeeper *tk)
1152{
1153 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1154 u64 boot_ns;
1155
876e7881 1156 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1157
1158 write_seqcount_begin(&vdata->seq);
1159
1160 /* copy pvclock gtod data */
876e7881
PZ		 1161 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1162 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1163 vdata->clock.mask = tk->tkr_mono.mask;
1164 vdata->clock.mult = tk->tkr_mono.mult;
1165 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1166
cbcf2dd3 1167 vdata->boot_ns = boot_ns;
876e7881 1168 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1169
55dd00a7
MT		 1170 vdata->wall_time_sec = tk->xtime_sec;
1171
16e8d74d
MT		 1172 write_seqcount_end(&vdata->seq);
1173}
1174#endif
1175
bab5bb39
NK		 1176void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1177{
1178 /*
1179 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1180 * vcpu_enter_guest. This function is only called from
1181 * the physical CPU that is running vcpu.
1182 */
1183 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1184}
16e8d74d 1185
18068523
GOC		 1186static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1187{
9ed3c444
AK		 1188 int version;
1189 int r;
50d0a0f9 1190 struct pvclock_wall_clock wc;
87aeb54f 1191 struct timespec64 boot;
18068523
GOC		 1192
1193 if (!wall_clock)
1194 return;
1195
9ed3c444
AK		 1196 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1197 if (r)
1198 return;
1199
1200 if (version & 1)
1201 ++version; /* first time write, random junk */
1202
1203 ++version;
18068523 1204
1dab1345
NK		 1205 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1206 return;
18068523 1207
50d0a0f9
GH		 1208 /*
1209 * The guest calculates current wall clock time by adding
34c238a1 1210 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1211 * wall clock specified here. guest system time equals host
1212 * system time for us, thus we must fill in host boot time here.
1213 */
87aeb54f 1214 getboottime64(&boot);
50d0a0f9 1215
4b648665 1216 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1217 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1218 boot = timespec64_sub(boot, ts);
4b648665 1219 }
87aeb54f 1220 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1221 wc.nsec = boot.tv_nsec;
1222 wc.version = version;
18068523
GOC		 1223
1224 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1225
1226 version++;
1227 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1228}
1229
50d0a0f9
GH		 1230static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1231{
b51012de
PB		 1232 do_shl32_div32(dividend, divisor);
1233 return dividend;
50d0a0f9
GH		 1234}
1235
3ae13faa 1236static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1237 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1238{
5f4e3f88 1239 uint64_t scaled64;
50d0a0f9
GH		 1240 int32_t shift = 0;
1241 uint64_t tps64;
1242 uint32_t tps32;
1243
3ae13faa
PB		 1244 tps64 = base_hz;
1245 scaled64 = scaled_hz;
50933623 1246 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1247 tps64 >>= 1;
1248 shift--;
1249 }
1250
1251 tps32 = (uint32_t)tps64;
50933623
JK		 1252 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1253 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1254 scaled64 >>= 1;
1255 else
1256 tps32 <<= 1;
50d0a0f9
GH		 1257 shift++;
1258 }
1259
5f4e3f88
ZA		 1260 *pshift = shift;
1261 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1262
3ae13faa
PB		 1263 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1264 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH		 1265}
1266
d828199e 1267#ifdef CONFIG_X86_64
16e8d74d 1268static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1269#endif
16e8d74d 1270
c8076604 1271static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1272static unsigned long max_tsc_khz;
c8076604 1273
cc578287 1274static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1275{
cc578287
ZA		 1276 u64 v = (u64)khz * (1000000 + ppm);
1277 do_div(v, 1000000);
1278 return v;
1e993611
JR		 1279}
1280
381d585c
HZ		 1281static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1282{
1283 u64 ratio;
1284
1285 /* Guest TSC same frequency as host TSC? */
1286 if (!scale) {
1287 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1288 return 0;
1289 }
1290
1291 /* TSC scaling supported? */
1292 if (!kvm_has_tsc_control) {
1293 if (user_tsc_khz > tsc_khz) {
1294 vcpu->arch.tsc_catchup = 1;
1295 vcpu->arch.tsc_always_catchup = 1;
1296 return 0;
1297 } else {
1298 WARN(1, "user requested TSC rate below hardware speed\n");
1299 return -1;
1300 }
1301 }
1302
1303 /* TSC scaling required - calculate ratio */
1304 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1305 user_tsc_khz, tsc_khz);
1306
1307 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1308 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1309 user_tsc_khz);
1310 return -1;
1311 }
1312
1313 vcpu->arch.tsc_scaling_ratio = ratio;
1314 return 0;
1315}
1316
4941b8cb 1317static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1318{
cc578287
ZA		 1319 u32 thresh_lo, thresh_hi;
1320 int use_scaling = 0;
217fc9cf 1321
03ba32ca 1322 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1323 if (user_tsc_khz == 0) {
ad721883
HZ		 1324 /* set tsc_scaling_ratio to a safe value */
1325 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1326 return -1;
ad721883 1327 }
03ba32ca 1328
c285545f 1329 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1330 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1331 &vcpu->arch.virtual_tsc_shift,
1332 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1333 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1334
1335 /*
1336 * Compute the variation in TSC rate which is acceptable
1337 * within the range of tolerance and decide if the
1338 * rate being applied is within that bounds of the hardware
1339 * rate. If so, no scaling or compensation need be done.
1340 */
1341 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1342 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1343 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1344 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1345 use_scaling = 1;
1346 }
4941b8cb 1347 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1348}
1349
1350static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1351{
e26101b1 1352 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1353 vcpu->arch.virtual_tsc_mult,
1354 vcpu->arch.virtual_tsc_shift);
e26101b1 1355 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1356 return tsc;
1357}
1358
69b0049a 1359static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1360{
1361#ifdef CONFIG_X86_64
1362 bool vcpus_matched;
b48aa97e
MT		 1363 struct kvm_arch *ka = &vcpu->kvm->arch;
1364 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1365
1366 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1367 atomic_read(&vcpu->kvm->online_vcpus));
1368
7f187922
MT		 1369 /*
1370 * Once the masterclock is enabled, always perform request in
1371 * order to update it.
1372 *
1373 * In order to enable masterclock, the host clocksource must be TSC
1374 * and the vcpus need to have matched TSCs. When that happens,
1375 * perform request to enable masterclock.
1376 */
1377 if (ka->use_master_clock ||
1378 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1379 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1380
1381 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1382 atomic_read(&vcpu->kvm->online_vcpus),
1383 ka->use_master_clock, gtod->clock.vclock_mode);
1384#endif
1385}
1386
ba904635
WA		 1387static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1388{
3e3f5026 1389 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA		 1390 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1391}
1392
35181e86
HZ		 1393/*
1394 * Multiply tsc by a fixed point number represented by ratio.
1395 *
1396 * The most significant 64-N bits (mult) of ratio represent the
1397 * integral part of the fixed point number; the remaining N bits
1398 * (frac) represent the fractional part, ie. ratio represents a fixed
1399 * point number (mult + frac * 2^(-N)).
1400 *
1401 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1402 */
1403static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1404{
1405 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1406}
1407
1408u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1409{
1410 u64 _tsc = tsc;
1411 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1412
1413 if (ratio != kvm_default_tsc_scaling_ratio)
1414 _tsc = __scale_tsc(ratio, tsc);
1415
1416 return _tsc;
1417}
1418EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1419
07c1419a
HZ		 1420static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1421{
1422 u64 tsc;
1423
1424 tsc = kvm_scale_tsc(vcpu, rdtsc());
1425
1426 return target_tsc - tsc;
1427}
1428
4ba76538
HZ		 1429u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1430{
ea26e4ec 1431 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1432}
1433EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1434
a545ab6a
LC		 1435static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1436{
1437 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1438 vcpu->arch.tsc_offset = offset;
1439}
1440
8fe8ab46 1441void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1442{
1443 struct kvm *kvm = vcpu->kvm;
f38e098f 1444 u64 offset, ns, elapsed;
99e3e30a 1445 unsigned long flags;
b48aa97e 1446 bool matched;
0d3da0d2 1447 bool already_matched;
8fe8ab46 1448 u64 data = msr->data;
c5e8ec8e 1449 bool synchronizing = false;
99e3e30a 1450
038f8c11 1451 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1452 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1453 ns = ktime_get_boot_ns();
f38e098f 1454 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1455
03ba32ca 1456 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1457 if (data == 0 && msr->host_initiated) {
1458 /*
1459 * detection of vcpu initialization -- need to sync
1460 * with other vCPUs. This particularly helps to keep
1461 * kvm_clock stable after CPU hotplug
1462 */
1463 synchronizing = true;
1464 } else {
1465 u64 tsc_exp = kvm->arch.last_tsc_write +
1466 nsec_to_cycles(vcpu, elapsed);
1467 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1468 /*
1469 * Special case: TSC write with a small delta (1 second)
1470 * of virtual cycle time against real time is
1471 * interpreted as an attempt to synchronize the CPU.
1472 */
1473 synchronizing = data < tsc_exp + tsc_hz &&
1474 data + tsc_hz > tsc_exp;
1475 }
c5e8ec8e 1476 }
f38e098f
ZA		 1477
1478 /*
5d3cb0f6
ZA		 1479 * For a reliable TSC, we can match TSC offsets, and for an unstable
1480 * TSC, we add elapsed time in this computation. We could let the
1481 * compensation code attempt to catch up if we fall behind, but
1482 * it's better to try to match offsets from the beginning.
1483 */
c5e8ec8e 1484 if (synchronizing &&
5d3cb0f6 1485 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1486 if (!check_tsc_unstable()) {
e26101b1 1487 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1488 pr_debug("kvm: matched tsc offset for %llu\n", data);
1489 } else {
857e4099 1490 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1491 data += delta;
07c1419a 1492 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1493 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1494 }
b48aa97e 1495 matched = true;
0d3da0d2 1496 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1497 } else {
1498 /*
1499 * We split periods of matched TSC writes into generations.
1500 * For each generation, we track the original measured
1501 * nanosecond time, offset, and write, so if TSCs are in
1502 * sync, we can match exact offset, and if not, we can match
4a969980 1503 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1504 *
1505 * These values are tracked in kvm->arch.cur_xxx variables.
1506 */
1507 kvm->arch.cur_tsc_generation++;
1508 kvm->arch.cur_tsc_nsec = ns;
1509 kvm->arch.cur_tsc_write = data;
1510 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1511 matched = false;
0d3da0d2 1512 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1513 kvm->arch.cur_tsc_generation, data);
f38e098f 1514 }
e26101b1
ZA		 1515
1516 /*
1517 * We also track th most recent recorded KHZ, write and time to
1518 * allow the matching interval to be extended at each write.
1519 */
f38e098f
ZA		 1520 kvm->arch.last_tsc_nsec = ns;
1521 kvm->arch.last_tsc_write = data;
5d3cb0f6 1522 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1523
b183aa58 1524 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1525
1526 /* Keep track of which generation this VCPU has synchronized to */
1527 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1528 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1529 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1530
ba904635
WA		 1531 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1532 update_ia32_tsc_adjust_msr(vcpu, offset);
a545ab6a 1533 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1534 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1535
1536 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1537 if (!matched) {
b48aa97e 1538 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1539 } else if (!already_matched) {
1540 kvm->arch.nr_vcpus_matched_tsc++;
1541 }
b48aa97e
MT		 1542
1543 kvm_track_tsc_matching(vcpu);
1544 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1545}
e26101b1 1546
99e3e30a
ZA		 1547EXPORT_SYMBOL_GPL(kvm_write_tsc);
1548
58ea6767
HZ		 1549static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1550 s64 adjustment)
1551{
ea26e4ec 1552 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ		 1553}
1554
1555static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1556{
1557 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1558 WARN_ON(adjustment < 0);
1559 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1560 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 1561}
1562
d828199e
MT		 1563#ifdef CONFIG_X86_64
1564
a5a1d1c2 1565static u64 read_tsc(void)
d828199e 1566{
a5a1d1c2 1567 u64 ret = (u64)rdtsc_ordered();
03b9730b 1568 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 1569
1570 if (likely(ret >= last))
1571 return ret;
1572
1573 /*
1574 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1575 * predictable (it's just a function of time and the likely is
d828199e
MT		 1576 * very likely) and there's a data dependence, so force GCC
1577 * to generate a branch instead. I don't barrier() because
1578 * we don't actually need a barrier, and if this function
1579 * ever gets inlined it will generate worse code.
1580 */
1581 asm volatile ("");
1582 return last;
1583}
1584
a5a1d1c2 1585static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT		 1586{
1587 long v;
1588 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1589
1590 *cycle_now = read_tsc();
1591
1592 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1593 return v * gtod->clock.mult;
1594}
1595
a5a1d1c2 1596static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1597{
cbcf2dd3 1598 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1599 unsigned long seq;
d828199e 1600 int mode;
cbcf2dd3 1601 u64 ns;
d828199e 1602
d828199e
MT		 1603 do {
1604 seq = read_seqcount_begin(&gtod->seq);
1605 mode = gtod->clock.vclock_mode;
cbcf2dd3 1606 ns = gtod->nsec_base;
d828199e
MT		 1607 ns += vgettsc(cycle_now);
1608 ns >>= gtod->clock.shift;
cbcf2dd3 1609 ns += gtod->boot_ns;
d828199e 1610 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1611 *t = ns;
d828199e
MT		 1612
1613 return mode;
1614}
1615
55dd00a7
MT		 1616static int do_realtime(struct timespec *ts, u64 *cycle_now)
1617{
1618 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1619 unsigned long seq;
1620 int mode;
1621 u64 ns;
1622
1623 do {
1624 seq = read_seqcount_begin(&gtod->seq);
1625 mode = gtod->clock.vclock_mode;
1626 ts->tv_sec = gtod->wall_time_sec;
1627 ns = gtod->nsec_base;
1628 ns += vgettsc(cycle_now);
1629 ns >>= gtod->clock.shift;
1630 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1631
1632 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1633 ts->tv_nsec = ns;
1634
1635 return mode;
1636}
1637
d828199e 1638/* returns true if host is using tsc clocksource */
a5a1d1c2 1639static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1640{
d828199e
MT		 1641 /* checked again under seqlock below */
1642 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1643 return false;
1644
cbcf2dd3 1645 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1646}
55dd00a7
MT		 1647
1648/* returns true if host is using tsc clocksource */
1649static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1650 u64 *cycle_now)
1651{
1652 /* checked again under seqlock below */
1653 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1654 return false;
1655
1656 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1657}
d828199e
MT		 1658#endif
1659
1660/*
1661 *
b48aa97e
MT		 1662 * Assuming a stable TSC across physical CPUS, and a stable TSC
1663 * across virtual CPUs, the following condition is possible.
1664 * Each numbered line represents an event visible to both
d828199e
MT		 1665 * CPUs at the next numbered event.
1666 *
1667 * "timespecX" represents host monotonic time. "tscX" represents
1668 * RDTSC value.
1669 *
1670 * VCPU0 on CPU0 | VCPU1 on CPU1
1671 *
1672 * 1. read timespec0,tsc0
1673 * 2. | timespec1 = timespec0 + N
1674 * | tsc1 = tsc0 + M
1675 * 3. transition to guest | transition to guest
1676 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1677 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1678 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1679 *
1680 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1681 *
1682 * - ret0 < ret1
1683 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1684 * ...
1685 * - 0 < N - M => M < N
1686 *
1687 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1688 * always the case (the difference between two distinct xtime instances
1689 * might be smaller then the difference between corresponding TSC reads,
1690 * when updating guest vcpus pvclock areas).
1691 *
1692 * To avoid that problem, do not allow visibility of distinct
1693 * system_timestamp/tsc_timestamp values simultaneously: use a master
1694 * copy of host monotonic time values. Update that master copy
1695 * in lockstep.
1696 *
b48aa97e 1697 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1698 *
1699 */
1700
1701static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1702{
1703#ifdef CONFIG_X86_64
1704 struct kvm_arch *ka = &kvm->arch;
1705 int vclock_mode;
b48aa97e
MT		 1706 bool host_tsc_clocksource, vcpus_matched;
1707
1708 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1709 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1710
1711 /*
1712 * If the host uses TSC clock, then passthrough TSC as stable
1713 * to the guest.
1714 */
b48aa97e 1715 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1716 &ka->master_kernel_ns,
1717 &ka->master_cycle_now);
1718
16a96021 1719 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1720 && !backwards_tsc_observed
1721 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1722
d828199e
MT		 1723 if (ka->use_master_clock)
1724 atomic_set(&kvm_guest_has_master_clock, 1);
1725
1726 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1727 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1728 vcpus_matched);
d828199e
MT		 1729#endif
1730}
1731
2860c4b1
PB		 1732void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1733{
1734 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1735}
1736
2e762ff7
MT		 1737static void kvm_gen_update_masterclock(struct kvm *kvm)
1738{
1739#ifdef CONFIG_X86_64
1740 int i;
1741 struct kvm_vcpu *vcpu;
1742 struct kvm_arch *ka = &kvm->arch;
1743
1744 spin_lock(&ka->pvclock_gtod_sync_lock);
1745 kvm_make_mclock_inprogress_request(kvm);
1746 /* no guest entries from this point */
1747 pvclock_update_vm_gtod_copy(kvm);
1748
1749 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1750 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1751
1752 /* guest entries allowed */
1753 kvm_for_each_vcpu(i, vcpu, kvm)
1754 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1755
1756 spin_unlock(&ka->pvclock_gtod_sync_lock);
1757#endif
1758}
1759
108b249c
PB		 1760static u64 __get_kvmclock_ns(struct kvm *kvm)
1761{
108b249c 1762 struct kvm_arch *ka = &kvm->arch;
8b953440 1763 struct pvclock_vcpu_time_info hv_clock;
108b249c 1764
8b953440
PB		 1765 spin_lock(&ka->pvclock_gtod_sync_lock);
1766 if (!ka->use_master_clock) {
1767 spin_unlock(&ka->pvclock_gtod_sync_lock);
1768 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB		 1769 }
1770
8b953440
PB		 1771 hv_clock.tsc_timestamp = ka->master_cycle_now;
1772 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1773 spin_unlock(&ka->pvclock_gtod_sync_lock);
1774
1775 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1776 &hv_clock.tsc_shift,
1777 &hv_clock.tsc_to_system_mul);
1778 return __pvclock_read_cycles(&hv_clock, rdtsc());
108b249c
PB		 1779}
1780
1781u64 get_kvmclock_ns(struct kvm *kvm)
1782{
1783 unsigned long flags;
1784 s64 ns;
1785
1786 local_irq_save(flags);
1787 ns = __get_kvmclock_ns(kvm);
1788 local_irq_restore(flags);
1789
1790 return ns;
1791}
1792
0d6dd2ff
PB		 1793static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1794{
1795 struct kvm_vcpu_arch *vcpu = &v->arch;
1796 struct pvclock_vcpu_time_info guest_hv_clock;
1797
bbd64115 1798 if (unlikely(kvm_vcpu_read_guest_cached(v, &vcpu->pv_time,
0d6dd2ff
PB		 1799 &guest_hv_clock, sizeof(guest_hv_clock))))
1800 return;
1801
1802 /* This VCPU is paused, but it's legal for a guest to read another
1803 * VCPU's kvmclock, so we really have to follow the specification where
1804 * it says that version is odd if data is being modified, and even after
1805 * it is consistent.
1806 *
1807 * Version field updates must be kept separate. This is because
1808 * kvm_write_guest_cached might use a "rep movs" instruction, and
1809 * writes within a string instruction are weakly ordered. So there
1810 * are three writes overall.
1811 *
1812 * As a small optimization, only write the version field in the first
1813 * and third write. The vcpu->pv_time cache is still valid, because the
1814 * version field is the first in the struct.
1815 */
1816 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1817
1818 vcpu->hv_clock.version = guest_hv_clock.version + 1;
bbd64115
CL		 1819 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1820 &vcpu->hv_clock,
1821 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1822
1823 smp_wmb();
1824
1825 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1826 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1827
1828 if (vcpu->pvclock_set_guest_stopped_request) {
1829 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1830 vcpu->pvclock_set_guest_stopped_request = false;
1831 }
1832
1833 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1834
bbd64115
CL		 1835 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1836 &vcpu->hv_clock,
1837 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 1838
1839 smp_wmb();
1840
1841 vcpu->hv_clock.version++;
bbd64115
CL		 1842 kvm_vcpu_write_guest_cached(v, &vcpu->pv_time,
1843 &vcpu->hv_clock,
1844 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 1845}
1846
34c238a1 1847static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1848{
78db6a50 1849 unsigned long flags, tgt_tsc_khz;
18068523 1850 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1851 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1852 s64 kernel_ns;
d828199e 1853 u64 tsc_timestamp, host_tsc;
51d59c6b 1854 u8 pvclock_flags;
d828199e
MT		 1855 bool use_master_clock;
1856
1857 kernel_ns = 0;
1858 host_tsc = 0;
18068523 1859
d828199e
MT		 1860 /*
1861 * If the host uses TSC clock, then passthrough TSC as stable
1862 * to the guest.
1863 */
1864 spin_lock(&ka->pvclock_gtod_sync_lock);
1865 use_master_clock = ka->use_master_clock;
1866 if (use_master_clock) {
1867 host_tsc = ka->master_cycle_now;
1868 kernel_ns = ka->master_kernel_ns;
1869 }
1870 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1871
1872 /* Keep irq disabled to prevent changes to the clock */
1873 local_irq_save(flags);
78db6a50
PB		 1874 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1875 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 1876 local_irq_restore(flags);
1877 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1878 return 1;
1879 }
d828199e 1880 if (!use_master_clock) {
4ea1636b 1881 host_tsc = rdtsc();
108b249c 1882 kernel_ns = ktime_get_boot_ns();
d828199e
MT		 1883 }
1884
4ba76538 1885 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1886
c285545f
ZA		 1887 /*
1888 * We may have to catch up the TSC to match elapsed wall clock
1889 * time for two reasons, even if kvmclock is used.
1890 * 1) CPU could have been running below the maximum TSC rate
1891 * 2) Broken TSC compensation resets the base at each VCPU
1892 * entry to avoid unknown leaps of TSC even when running
1893 * again on the same CPU. This may cause apparent elapsed
1894 * time to disappear, and the guest to stand still or run
1895 * very slowly.
1896 */
1897 if (vcpu->tsc_catchup) {
1898 u64 tsc = compute_guest_tsc(v, kernel_ns);
1899 if (tsc > tsc_timestamp) {
f1e2b260 1900 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1901 tsc_timestamp = tsc;
1902 }
50d0a0f9
GH		 1903 }
1904
18068523
GOC		 1905 local_irq_restore(flags);
1906
0d6dd2ff 1907 /* With all the info we got, fill in the values */
18068523 1908
78db6a50
PB		 1909 if (kvm_has_tsc_control)
1910 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1911
1912 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1913 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 1914 &vcpu->hv_clock.tsc_shift,
1915 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1916 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 1917 }
1918
1d5f066e 1919 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1920 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1921 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1922
d828199e 1923 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1924 pvclock_flags = 0;
d828199e
MT		 1925 if (use_master_clock)
1926 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1927
78c0337a
MT		 1928 vcpu->hv_clock.flags = pvclock_flags;
1929
095cf55d
PB		 1930 if (vcpu->pv_time_enabled)
1931 kvm_setup_pvclock_page(v);
1932 if (v == kvm_get_vcpu(v->kvm, 0))
1933 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 1934 return 0;
c8076604
GH		 1935}
1936
0061d53d
MT		 1937/*
1938 * kvmclock updates which are isolated to a given vcpu, such as
1939 * vcpu->cpu migration, should not allow system_timestamp from
1940 * the rest of the vcpus to remain static. Otherwise ntp frequency
1941 * correction applies to one vcpu's system_timestamp but not
1942 * the others.
1943 *
1944 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1945 * We need to rate-limit these requests though, as they can
1946 * considerably slow guests that have a large number of vcpus.
1947 * The time for a remote vcpu to update its kvmclock is bound
1948 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1949 */
1950
7e44e449
AJ		 1951#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1952
1953static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1954{
1955 int i;
7e44e449
AJ		 1956 struct delayed_work *dwork = to_delayed_work(work);
1957 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1958 kvmclock_update_work);
1959 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1960 struct kvm_vcpu *vcpu;
1961
1962 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1963 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1964 kvm_vcpu_kick(vcpu);
1965 }
1966}
1967
7e44e449
AJ		 1968static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1969{
1970 struct kvm *kvm = v->kvm;
1971
105b21bb 1972 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1973 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1974 KVMCLOCK_UPDATE_DELAY);
1975}
1976
332967a3
AJ		 1977#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1978
1979static void kvmclock_sync_fn(struct work_struct *work)
1980{
1981 struct delayed_work *dwork = to_delayed_work(work);
1982 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1983 kvmclock_sync_work);
1984 struct kvm *kvm = container_of(ka, struct kvm, arch);
1985
630994b3
MT		 1986 if (!kvmclock_periodic_sync)
1987 return;
1988
332967a3
AJ		 1989 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1990 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1991 KVMCLOCK_SYNC_PERIOD);
1992}
1993
890ca9ae 1994static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1995{
890ca9ae
HY		 1996 u64 mcg_cap = vcpu->arch.mcg_cap;
1997 unsigned bank_num = mcg_cap & 0xff;
1998
15c4a640 1999 switch (msr) {
15c4a640 2000 case MSR_IA32_MCG_STATUS:
890ca9ae 2001 vcpu->arch.mcg_status = data;
15c4a640 2002 break;
c7ac679c 2003 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2004 if (!(mcg_cap & MCG_CTL_P))
2005 return 1;
2006 if (data != 0 && data != ~(u64)0)
2007 return -1;
2008 vcpu->arch.mcg_ctl = data;
2009 break;
2010 default:
2011 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2012 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2013 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 2014 /* only 0 or all 1s can be written to IA32_MCi_CTL
2015 * some Linux kernels though clear bit 10 in bank 4 to
2016 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2017 * this to avoid an uncatched #GP in the guest
2018 */
890ca9ae 2019 if ((offset & 0x3) == 0 &&
114be429 2020 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 2021 return -1;
2022 vcpu->arch.mce_banks[offset] = data;
2023 break;
2024 }
2025 return 1;
2026 }
2027 return 0;
2028}
2029
ffde22ac
ES		 2030static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2031{
2032 struct kvm *kvm = vcpu->kvm;
2033 int lm = is_long_mode(vcpu);
2034 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2035 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2036 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2037 : kvm->arch.xen_hvm_config.blob_size_32;
2038 u32 page_num = data & ~PAGE_MASK;
2039 u64 page_addr = data & PAGE_MASK;
2040 u8 *page;
2041 int r;
2042
2043 r = -E2BIG;
2044 if (page_num >= blob_size)
2045 goto out;
2046 r = -ENOMEM;
ff5c2c03
SL		 2047 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2048 if (IS_ERR(page)) {
2049 r = PTR_ERR(page);
ffde22ac 2050 goto out;
ff5c2c03 2051 }
54bf36aa 2052 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2053 goto out_free;
2054 r = 0;
2055out_free:
2056 kfree(page);
2057out:
2058 return r;
2059}
2060
344d9588
GN		 2061static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2062{
2063 gpa_t gpa = data & ~0x3f;
2064
4a969980 2065 /* Bits 2:5 are reserved, Should be zero */
6adba527 2066 if (data & 0x3c)
344d9588
GN		 2067 return 1;
2068
2069 vcpu->arch.apf.msr_val = data;
2070
2071 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2072 kvm_clear_async_pf_completion_queue(vcpu);
2073 kvm_async_pf_hash_reset(vcpu);
2074 return 0;
2075 }
2076
bbd64115 2077 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu, &vcpu->arch.apf.data, gpa,
8f964525 2078 sizeof(u32)))
344d9588
GN		 2079 return 1;
2080
6adba527 2081 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2082 kvm_async_pf_wakeup_all(vcpu);
2083 return 0;
2084}
2085
12f9a48f
GC		 2086static void kvmclock_reset(struct kvm_vcpu *vcpu)
2087{
0b79459b 2088 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2089}
2090
c9aaa895
GC		 2091static void record_steal_time(struct kvm_vcpu *vcpu)
2092{
2093 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2094 return;
2095
bbd64115 2096 if (unlikely(kvm_vcpu_read_guest_cached(vcpu, &vcpu->arch.st.stime,
c9aaa895
GC		 2097 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2098 return;
2099
0b9f6c46
PX		 2100 vcpu->arch.st.steal.preempted = 0;
2101
35f3fae1
WL		 2102 if (vcpu->arch.st.steal.version & 1)
2103 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2104
2105 vcpu->arch.st.steal.version += 1;
2106
bbd64115 2107 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
35f3fae1
WL		 2108 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2109
2110 smp_wmb();
2111
c54cdf14
LC		 2112 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2113 vcpu->arch.st.last_steal;
2114 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2115
bbd64115 2116 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
35f3fae1
WL		 2117 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2118
2119 smp_wmb();
2120
2121 vcpu->arch.st.steal.version += 1;
c9aaa895 2122
bbd64115 2123 kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.st.stime,
c9aaa895
GC		 2124 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2125}
2126
8fe8ab46 2127int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2128{
5753785f 2129 bool pr = false;
8fe8ab46
WA		 2130 u32 msr = msr_info->index;
2131 u64 data = msr_info->data;
5753785f 2132
15c4a640 2133 switch (msr) {
2e32b719
BP		 2134 case MSR_AMD64_NB_CFG:
2135 case MSR_IA32_UCODE_REV:
2136 case MSR_IA32_UCODE_WRITE:
2137 case MSR_VM_HSAVE_PA:
2138 case MSR_AMD64_PATCH_LOADER:
2139 case MSR_AMD64_BU_CFG2:
2140 break;
2141
15c4a640 2142 case MSR_EFER:
b69e8cae 2143 return set_efer(vcpu, data);
8f1589d9
AP		 2144 case MSR_K7_HWCR:
2145 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2146 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2147 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2148 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2149 if (data != 0) {
a737f256
CD		 2150 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2151 data);
8f1589d9
AP		 2152 return 1;
2153 }
15c4a640 2154 break;
f7c6d140
AP		 2155 case MSR_FAM10H_MMIO_CONF_BASE:
2156 if (data != 0) {
a737f256
CD		 2157 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2158 "0x%llx\n", data);
f7c6d140
AP		 2159 return 1;
2160 }
15c4a640 2161 break;
b5e2fec0
AG		 2162 case MSR_IA32_DEBUGCTLMSR:
2163 if (!data) {
2164 /* We support the non-activated case already */
2165 break;
2166 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2167 /* Values other than LBR and BTF are vendor-specific,
2168 thus reserved and should throw a #GP */
2169 return 1;
2170 }
a737f256
CD		 2171 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2172 __func__, data);
b5e2fec0 2173 break;
9ba075a6 2174 case 0x200 ... 0x2ff:
ff53604b 2175 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2176 case MSR_IA32_APICBASE:
58cb628d 2177 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2178 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2179 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2180 case MSR_IA32_TSCDEADLINE:
2181 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2182 break;
ba904635
WA		 2183 case MSR_IA32_TSC_ADJUST:
2184 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2185 if (!msr_info->host_initiated) {
d913b904 2186 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2187 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2188 }
2189 vcpu->arch.ia32_tsc_adjust_msr = data;
2190 }
2191 break;
15c4a640 2192 case MSR_IA32_MISC_ENABLE:
ad312c7c 2193 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2194 break;
64d60670
PB		 2195 case MSR_IA32_SMBASE:
2196 if (!msr_info->host_initiated)
2197 return 1;
2198 vcpu->arch.smbase = data;
2199 break;
11c6bffa 2200 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2201 case MSR_KVM_WALL_CLOCK:
2202 vcpu->kvm->arch.wall_clock = data;
2203 kvm_write_wall_clock(vcpu->kvm, data);
2204 break;
11c6bffa 2205 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2206 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2207 struct kvm_arch *ka = &vcpu->kvm->arch;
2208
12f9a48f 2209 kvmclock_reset(vcpu);
18068523 2210
54750f2c
MT		 2211 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2212 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2213
2214 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2215 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2216 &vcpu->requests);
2217
2218 ka->boot_vcpu_runs_old_kvmclock = tmp;
2219 }
2220
18068523 2221 vcpu->arch.time = data;
0061d53d 2222 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2223
2224 /* we verify if the enable bit is set... */
2225 if (!(data & 1))
2226 break;
2227
bbd64115 2228 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu,
8f964525
AH		 2229 &vcpu->arch.pv_time, data & ~1ULL,
2230 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2231 vcpu->arch.pv_time_enabled = false;
2232 else
2233 vcpu->arch.pv_time_enabled = true;
32cad84f 2234
18068523
GOC		 2235 break;
2236 }
344d9588
GN		 2237 case MSR_KVM_ASYNC_PF_EN:
2238 if (kvm_pv_enable_async_pf(vcpu, data))
2239 return 1;
2240 break;
c9aaa895
GC		 2241 case MSR_KVM_STEAL_TIME:
2242
2243 if (unlikely(!sched_info_on()))
2244 return 1;
2245
2246 if (data & KVM_STEAL_RESERVED_MASK)
2247 return 1;
2248
bbd64115 2249 if (kvm_vcpu_gfn_to_hva_cache_init(vcpu, &vcpu->arch.st.stime,
8f964525
AH		 2250 data & KVM_STEAL_VALID_BITS,
2251 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2252 return 1;
2253
2254 vcpu->arch.st.msr_val = data;
2255
2256 if (!(data & KVM_MSR_ENABLED))
2257 break;
2258
c9aaa895
GC		 2259 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2260
2261 break;
ae7a2a3f
MT		 2262 case MSR_KVM_PV_EOI_EN:
2263 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2264 return 1;
2265 break;
c9aaa895 2266
890ca9ae
HY		 2267 case MSR_IA32_MCG_CTL:
2268 case MSR_IA32_MCG_STATUS:
81760dcc 2269 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2270 return set_msr_mce(vcpu, msr, data);
71db6023 2271
6912ac32
WH		 2272 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2273 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2274 pr = true; /* fall through */
2275 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2276 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2277 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2278 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2279
2280 if (pr || data != 0)
a737f256
CD		 2281 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2282 "0x%x data 0x%llx\n", msr, data);
5753785f 2283 break;
84e0cefa
JS		 2284 case MSR_K7_CLK_CTL:
2285 /*
2286 * Ignore all writes to this no longer documented MSR.
2287 * Writes are only relevant for old K7 processors,
2288 * all pre-dating SVM, but a recommended workaround from
4a969980 2289 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2290 * affected processor models on the command line, hence
2291 * the need to ignore the workaround.
2292 */
2293 break;
55cd8e5a 2294 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2295 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2296 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2297 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS		 2298 return kvm_hv_set_msr_common(vcpu, msr, data,
2299 msr_info->host_initiated);
91c9c3ed 2300 case MSR_IA32_BBL_CR_CTL3:
2301 /* Drop writes to this legacy MSR -- see rdmsr
2302 * counterpart for further detail.
2303 */
796f4687 2304 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n", msr, data);
91c9c3ed 2305 break;
2b036c6b
BO		 2306 case MSR_AMD64_OSVW_ID_LENGTH:
2307 if (!guest_cpuid_has_osvw(vcpu))
2308 return 1;
2309 vcpu->arch.osvw.length = data;
2310 break;
2311 case MSR_AMD64_OSVW_STATUS:
2312 if (!guest_cpuid_has_osvw(vcpu))
2313 return 1;
2314 vcpu->arch.osvw.status = data;
2315 break;
15c4a640 2316 default:
ffde22ac
ES		 2317 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2318 return xen_hvm_config(vcpu, data);
c6702c9d 2319 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2320 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2321 if (!ignore_msrs) {
ae0f5499 2322 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2323 msr, data);
ed85c068
AP		 2324 return 1;
2325 } else {
796f4687 2326 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
a737f256 2327 msr, data);
ed85c068
AP		 2328 break;
2329 }
15c4a640
CO		 2330 }
2331 return 0;
2332}
2333EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2334
2335
2336/*
2337 * Reads an msr value (of 'msr_index') into 'pdata'.
2338 * Returns 0 on success, non-0 otherwise.
2339 * Assumes vcpu_load() was already called.
2340 */
609e36d3 2341int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2342{
609e36d3 2343 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2344}
ff651cb6 2345EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2346
890ca9ae 2347static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2348{
2349 u64 data;
890ca9ae
HY		 2350 u64 mcg_cap = vcpu->arch.mcg_cap;
2351 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2352
2353 switch (msr) {
15c4a640
CO		 2354 case MSR_IA32_P5_MC_ADDR:
2355 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2356 data = 0;
2357 break;
15c4a640 2358 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2359 data = vcpu->arch.mcg_cap;
2360 break;
c7ac679c 2361 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2362 if (!(mcg_cap & MCG_CTL_P))
2363 return 1;
2364 data = vcpu->arch.mcg_ctl;
2365 break;
2366 case MSR_IA32_MCG_STATUS:
2367 data = vcpu->arch.mcg_status;
2368 break;
2369 default:
2370 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2371 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2372 u32 offset = msr - MSR_IA32_MC0_CTL;
2373 data = vcpu->arch.mce_banks[offset];
2374 break;
2375 }
2376 return 1;
2377 }
2378 *pdata = data;
2379 return 0;
2380}
2381
609e36d3 2382int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2383{
609e36d3 2384 switch (msr_info->index) {
890ca9ae 2385 case MSR_IA32_PLATFORM_ID:
15c4a640 2386 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2387 case MSR_IA32_DEBUGCTLMSR:
2388 case MSR_IA32_LASTBRANCHFROMIP:
2389 case MSR_IA32_LASTBRANCHTOIP:
2390 case MSR_IA32_LASTINTFROMIP:
2391 case MSR_IA32_LASTINTTOIP:
60af2ecd 2392 case MSR_K8_SYSCFG:
3afb1121
PB		 2393 case MSR_K8_TSEG_ADDR:
2394 case MSR_K8_TSEG_MASK:
60af2ecd 2395 case MSR_K7_HWCR:
61a6bd67 2396 case MSR_VM_HSAVE_PA:
1fdbd48c 2397 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2398 case MSR_AMD64_NB_CFG:
f7c6d140 2399 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2400 case MSR_AMD64_BU_CFG2:
0c2df2a1 2401 case MSR_IA32_PERF_CTL:
609e36d3 2402 msr_info->data = 0;
15c4a640 2403 break;
6912ac32
WH		 2404 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2405 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2406 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2407 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2408 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 2409 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2410 msr_info->data = 0;
5753785f 2411 break;
742bc670 2412 case MSR_IA32_UCODE_REV:
609e36d3 2413 msr_info->data = 0x100000000ULL;
742bc670 2414 break;
9ba075a6 2415 case MSR_MTRRcap:
9ba075a6 2416 case 0x200 ... 0x2ff:
ff53604b 2417 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2418 case 0xcd: /* fsb frequency */
609e36d3 2419 msr_info->data = 3;
15c4a640 2420 break;
7b914098
JS		 2421 /*
2422 * MSR_EBC_FREQUENCY_ID
2423 * Conservative value valid for even the basic CPU models.
2424 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2425 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2426 * and 266MHz for model 3, or 4. Set Core Clock
2427 * Frequency to System Bus Frequency Ratio to 1 (bits
2428 * 31:24) even though these are only valid for CPU
2429 * models > 2, however guests may end up dividing or
2430 * multiplying by zero otherwise.
2431 */
2432 case MSR_EBC_FREQUENCY_ID:
609e36d3 2433 msr_info->data = 1 << 24;
7b914098 2434 break;
15c4a640 2435 case MSR_IA32_APICBASE:
609e36d3 2436 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2437 break;
0105d1a5 2438 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2439 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2440 break;
a3e06bbe 2441 case MSR_IA32_TSCDEADLINE:
609e36d3 2442 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2443 break;
ba904635 2444 case MSR_IA32_TSC_ADJUST:
609e36d3 2445 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2446 break;
15c4a640 2447 case MSR_IA32_MISC_ENABLE:
609e36d3 2448 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2449 break;
64d60670
PB		 2450 case MSR_IA32_SMBASE:
2451 if (!msr_info->host_initiated)
2452 return 1;
2453 msr_info->data = vcpu->arch.smbase;
15c4a640 2454 break;
847f0ad8
AG		 2455 case MSR_IA32_PERF_STATUS:
2456 /* TSC increment by tick */
609e36d3 2457 msr_info->data = 1000ULL;
847f0ad8 2458 /* CPU multiplier */
b0996ae4 2459 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2460 break;
15c4a640 2461 case MSR_EFER:
609e36d3 2462 msr_info->data = vcpu->arch.efer;
15c4a640 2463 break;
18068523 2464 case MSR_KVM_WALL_CLOCK:
11c6bffa 2465 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2466 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2467 break;
2468 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2469 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2470 msr_info->data = vcpu->arch.time;
18068523 2471 break;
344d9588 2472 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2473 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2474 break;
c9aaa895 2475 case MSR_KVM_STEAL_TIME:
609e36d3 2476 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2477 break;
1d92128f 2478 case MSR_KVM_PV_EOI_EN:
609e36d3 2479 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2480 break;
890ca9ae
HY		 2481 case MSR_IA32_P5_MC_ADDR:
2482 case MSR_IA32_P5_MC_TYPE:
2483 case MSR_IA32_MCG_CAP:
2484 case MSR_IA32_MCG_CTL:
2485 case MSR_IA32_MCG_STATUS:
81760dcc 2486 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2487 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2488 case MSR_K7_CLK_CTL:
2489 /*
2490 * Provide expected ramp-up count for K7. All other
2491 * are set to zero, indicating minimum divisors for
2492 * every field.
2493 *
2494 * This prevents guest kernels on AMD host with CPU
2495 * type 6, model 8 and higher from exploding due to
2496 * the rdmsr failing.
2497 */
609e36d3 2498 msr_info->data = 0x20000000;
84e0cefa 2499 break;
55cd8e5a 2500 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2501 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2502 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2503 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS		 2504 return kvm_hv_get_msr_common(vcpu,
2505 msr_info->index, &msr_info->data);
55cd8e5a 2506 break;
91c9c3ed 2507 case MSR_IA32_BBL_CR_CTL3:
2508 /* This legacy MSR exists but isn't fully documented in current
2509 * silicon. It is however accessed by winxp in very narrow
2510 * scenarios where it sets bit #19, itself documented as
2511 * a "reserved" bit. Best effort attempt to source coherent
2512 * read data here should the balance of the register be
2513 * interpreted by the guest:
2514 *
2515 * L2 cache control register 3: 64GB range, 256KB size,
2516 * enabled, latency 0x1, configured
2517 */
609e36d3 2518 msr_info->data = 0xbe702111;
91c9c3ed 2519 break;
2b036c6b
BO		 2520 case MSR_AMD64_OSVW_ID_LENGTH:
2521 if (!guest_cpuid_has_osvw(vcpu))
2522 return 1;
609e36d3 2523 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2524 break;
2525 case MSR_AMD64_OSVW_STATUS:
2526 if (!guest_cpuid_has_osvw(vcpu))
2527 return 1;
609e36d3 2528 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2529 break;
15c4a640 2530 default:
c6702c9d 2531 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2532 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2533 if (!ignore_msrs) {
ae0f5499
BD		 2534 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2535 msr_info->index);
ed85c068
AP		 2536 return 1;
2537 } else {
609e36d3
PB		 2538 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2539 msr_info->data = 0;
ed85c068
AP		 2540 }
2541 break;
15c4a640 2542 }
15c4a640
CO		 2543 return 0;
2544}
2545EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2546
313a3dc7
CO		 2547/*
2548 * Read or write a bunch of msrs. All parameters are kernel addresses.
2549 *
2550 * @return number of msrs set successfully.
2551 */
2552static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2553 struct kvm_msr_entry *entries,
2554 int (*do_msr)(struct kvm_vcpu *vcpu,
2555 unsigned index, u64 *data))
2556{
f656ce01 2557 int i, idx;
313a3dc7 2558
f656ce01 2559 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2560 for (i = 0; i < msrs->nmsrs; ++i)
2561 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2562 break;
f656ce01 2563 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2564
313a3dc7
CO		 2565 return i;
2566}
2567
2568/*
2569 * Read or write a bunch of msrs. Parameters are user addresses.
2570 *
2571 * @return number of msrs set successfully.
2572 */
2573static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2574 int (*do_msr)(struct kvm_vcpu *vcpu,
2575 unsigned index, u64 *data),
2576 int writeback)
2577{
2578 struct kvm_msrs msrs;
2579 struct kvm_msr_entry *entries;
2580 int r, n;
2581 unsigned size;
2582
2583 r = -EFAULT;
2584 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2585 goto out;
2586
2587 r = -E2BIG;
2588 if (msrs.nmsrs >= MAX_IO_MSRS)
2589 goto out;
2590
313a3dc7 2591 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2592 entries = memdup_user(user_msrs->entries, size);
2593 if (IS_ERR(entries)) {
2594 r = PTR_ERR(entries);
313a3dc7 2595 goto out;
ff5c2c03 2596 }
313a3dc7
CO		 2597
2598 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2599 if (r < 0)
2600 goto out_free;
2601
2602 r = -EFAULT;
2603 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2604 goto out_free;
2605
2606 r = n;
2607
2608out_free:
7a73c028 2609 kfree(entries);
313a3dc7
CO		 2610out:
2611 return r;
2612}
2613
784aa3d7 2614int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2615{
2616 int r;
2617
2618 switch (ext) {
2619 case KVM_CAP_IRQCHIP:
2620 case KVM_CAP_HLT:
2621 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2622 case KVM_CAP_SET_TSS_ADDR:
07716717 2623 case KVM_CAP_EXT_CPUID:
9c15bb1d 2624 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2625 case KVM_CAP_CLOCKSOURCE:
7837699f 2626 case KVM_CAP_PIT:
a28e4f5a 2627 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2628 case KVM_CAP_MP_STATE:
ed848624 2629 case KVM_CAP_SYNC_MMU:
a355c85c 2630 case KVM_CAP_USER_NMI:
52d939a0 2631 case KVM_CAP_REINJECT_CONTROL:
4925663a 2632 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2633 case KVM_CAP_IOEVENTFD:
f848a5a8 2634 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2635 case KVM_CAP_PIT2:
e9f42757 2636 case KVM_CAP_PIT_STATE2:
b927a3ce 2637 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2638 case KVM_CAP_XEN_HVM:
3cfc3092 2639 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2640 case KVM_CAP_HYPERV:
10388a07 2641 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2642 case KVM_CAP_HYPERV_SPIN:
5c919412 2643 case KVM_CAP_HYPERV_SYNIC:
ab9f4ecb 2644 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2645 case KVM_CAP_DEBUGREGS:
d2be1651 2646 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2647 case KVM_CAP_XSAVE:
344d9588 2648 case KVM_CAP_ASYNC_PF:
92a1f12d 2649 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2650 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2651 case KVM_CAP_READONLY_MEM:
5f66b620 2652 case KVM_CAP_HYPERV_TIME:
100943c5 2653 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2654 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2655 case KVM_CAP_ENABLE_CAP_VM:
2656 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2657 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2658 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2659 case KVM_CAP_IMMEDIATE_EXIT:
018d00d2
ZX		 2660 r = 1;
2661 break;
e3fd9a93
PB		 2662 case KVM_CAP_ADJUST_CLOCK:
2663 r = KVM_CLOCK_TSC_STABLE;
2664 break;
6d396b55
PB		 2665 case KVM_CAP_X86_SMM:
2666 /* SMBASE is usually relocated above 1M on modern chipsets,
2667 * and SMM handlers might indeed rely on 4G segment limits,
2668 * so do not report SMM to be available if real mode is
2669 * emulated via vm86 mode. Still, do not go to great lengths
2670 * to avoid userspace's usage of the feature, because it is a
2671 * fringe case that is not enabled except via specific settings
2672 * of the module parameters.
2673 */
2674 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2675 break;
774ead3a
AK		 2676 case KVM_CAP_VAPIC:
2677 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2678 break;
f725230a 2679 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2680 r = KVM_SOFT_MAX_VCPUS;
2681 break;
2682 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2683 r = KVM_MAX_VCPUS;
2684 break;
a988b910 2685 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2686 r = KVM_USER_MEM_SLOTS;
a988b910 2687 break;
a68a6a72
MT		 2688 case KVM_CAP_PV_MMU: /* obsolete */
2689 r = 0;
2f333bcb 2690 break;
890ca9ae
HY		 2691 case KVM_CAP_MCE:
2692 r = KVM_MAX_MCE_BANKS;
2693 break;
2d5b5a66 2694 case KVM_CAP_XCRS:
d366bf7e 2695 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2696 break;
92a1f12d
JR		 2697 case KVM_CAP_TSC_CONTROL:
2698 r = kvm_has_tsc_control;
2699 break;
37131313
RK		 2700 case KVM_CAP_X2APIC_API:
2701 r = KVM_X2APIC_API_VALID_FLAGS;
2702 break;
018d00d2
ZX		 2703 default:
2704 r = 0;
2705 break;
2706 }
2707 return r;
2708
2709}
2710
043405e1
CO		 2711long kvm_arch_dev_ioctl(struct file *filp,
2712 unsigned int ioctl, unsigned long arg)
2713{
2714 void __user *argp = (void __user *)arg;
2715 long r;
2716
2717 switch (ioctl) {
2718 case KVM_GET_MSR_INDEX_LIST: {
2719 struct kvm_msr_list __user *user_msr_list = argp;
2720 struct kvm_msr_list msr_list;
2721 unsigned n;
2722
2723 r = -EFAULT;
2724 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2725 goto out;
2726 n = msr_list.nmsrs;
62ef68bb 2727 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2728 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2729 goto out;
2730 r = -E2BIG;
e125e7b6 2731 if (n < msr_list.nmsrs)
043405e1
CO		 2732 goto out;
2733 r = -EFAULT;
2734 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2735 num_msrs_to_save * sizeof(u32)))
2736 goto out;
e125e7b6 2737 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2738 &emulated_msrs,
62ef68bb 2739 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2740 goto out;
2741 r = 0;
2742 break;
2743 }
9c15bb1d
BP		 2744 case KVM_GET_SUPPORTED_CPUID:
2745 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2746 struct kvm_cpuid2 __user *cpuid_arg = argp;
2747 struct kvm_cpuid2 cpuid;
2748
2749 r = -EFAULT;
2750 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2751 goto out;
9c15bb1d
BP		 2752
2753 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2754 ioctl);
674eea0f
AK		 2755 if (r)
2756 goto out;
2757
2758 r = -EFAULT;
2759 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2760 goto out;
2761 r = 0;
2762 break;
2763 }
890ca9ae 2764 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2765 r = -EFAULT;
c45dcc71
AR		 2766 if (copy_to_user(argp, &kvm_mce_cap_supported,
2767 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 2768 goto out;
2769 r = 0;
2770 break;
2771 }
043405e1
CO		 2772 default:
2773 r = -EINVAL;
2774 }
2775out:
2776 return r;
2777}
2778
f5f48ee1
SY		 2779static void wbinvd_ipi(void *garbage)
2780{
2781 wbinvd();
2782}
2783
2784static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2785{
e0f0bbc5 2786 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2787}
2788
2860c4b1
PB		 2789static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
2790{
2791 set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
2792}
2793
313a3dc7
CO		 2794void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2795{
f5f48ee1
SY		 2796 /* Address WBINVD may be executed by guest */
2797 if (need_emulate_wbinvd(vcpu)) {
2798 if (kvm_x86_ops->has_wbinvd_exit())
2799 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2800 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2801 smp_call_function_single(vcpu->cpu,
2802 wbinvd_ipi, NULL, 1);
2803 }
2804
313a3dc7 2805 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2806
0dd6a6ed
ZA		 2807 /* Apply any externally detected TSC adjustments (due to suspend) */
2808 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2809 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2810 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2811 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2812 }
8f6055cb 2813
48434c20 2814 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2815 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2816 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2817 if (tsc_delta < 0)
2818 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2819
c285545f 2820 if (check_tsc_unstable()) {
07c1419a 2821 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2822 vcpu->arch.last_guest_tsc);
a545ab6a 2823 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2824 vcpu->arch.tsc_catchup = 1;
c285545f 2825 }
e12c8f36
WL		 2826 if (kvm_lapic_hv_timer_in_use(vcpu) &&
2827 kvm_x86_ops->set_hv_timer(vcpu,
498f8162 2828 kvm_get_lapic_target_expiration_tsc(vcpu)))
e12c8f36 2829 kvm_lapic_switch_to_sw_timer(vcpu);
d98d07ca
MT		 2830 /*
2831 * On a host with synchronized TSC, there is no need to update
2832 * kvmclock on vcpu->cpu migration
2833 */
2834 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2835 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2836 if (vcpu->cpu != cpu)
2837 kvm_migrate_timers(vcpu);
e48672fa 2838 vcpu->cpu = cpu;
6b7d7e76 2839 }
c9aaa895 2840
c9aaa895 2841 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2842}
2843
0b9f6c46
PX		 2844static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2845{
2846 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2847 return;
2848
2849 vcpu->arch.st.steal.preempted = 1;
2850
bbd64115 2851 kvm_vcpu_write_guest_offset_cached(vcpu, &vcpu->arch.st.stime,
0b9f6c46
PX		 2852 &vcpu->arch.st.steal.preempted,
2853 offsetof(struct kvm_steal_time, preempted),
2854 sizeof(vcpu->arch.st.steal.preempted));
2855}
2856
313a3dc7
CO		 2857void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2858{
cc0d907c 2859 int idx;
931f261b
AA		 2860 /*
2861 * Disable page faults because we're in atomic context here.
2862 * kvm_write_guest_offset_cached() would call might_fault()
2863 * that relies on pagefault_disable() to tell if there's a
2864 * bug. NOTE: the write to guest memory may not go through if
2865 * during postcopy live migration or if there's heavy guest
2866 * paging.
2867 */
2868 pagefault_disable();
cc0d907c
AA		 2869 /*
2870 * kvm_memslots() will be called by
2871 * kvm_write_guest_offset_cached() so take the srcu lock.
2872 */
2873 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 2874 kvm_steal_time_set_preempted(vcpu);
cc0d907c 2875 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 2876 pagefault_enable();
02daab21 2877 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2878 kvm_put_guest_fpu(vcpu);
4ea1636b 2879 vcpu->arch.last_host_tsc = rdtsc();
313a3dc7
CO		 2880}
2881
313a3dc7
CO		 2882static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2883 struct kvm_lapic_state *s)
2884{
76dfafd5 2885 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS		 2886 kvm_x86_ops->sync_pir_to_irr(vcpu);
2887
a92e2543 2888 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 2889}
2890
2891static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2892 struct kvm_lapic_state *s)
2893{
a92e2543
RK		 2894 int r;
2895
2896 r = kvm_apic_set_state(vcpu, s);
2897 if (r)
2898 return r;
cb142eb7 2899 update_cr8_intercept(vcpu);
313a3dc7
CO		 2900
2901 return 0;
2902}
2903
127a457a
MG		 2904static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
2905{
2906 return (!lapic_in_kernel(vcpu) ||
2907 kvm_apic_accept_pic_intr(vcpu));
2908}
2909
782d422b
MG		 2910/*
2911 * if userspace requested an interrupt window, check that the
2912 * interrupt window is open.
2913 *
2914 * No need to exit to userspace if we already have an interrupt queued.
2915 */
2916static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
2917{
2918 return kvm_arch_interrupt_allowed(vcpu) &&
2919 !kvm_cpu_has_interrupt(vcpu) &&
2920 !kvm_event_needs_reinjection(vcpu) &&
2921 kvm_cpu_accept_dm_intr(vcpu);
2922}
2923
f77bc6a4
ZX		 2924static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2925 struct kvm_interrupt *irq)
2926{
02cdb50f 2927 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 2928 return -EINVAL;
1c1a9ce9
SR		 2929
2930 if (!irqchip_in_kernel(vcpu->kvm)) {
2931 kvm_queue_interrupt(vcpu, irq->irq, false);
2932 kvm_make_request(KVM_REQ_EVENT, vcpu);
2933 return 0;
2934 }
2935
2936 /*
2937 * With in-kernel LAPIC, we only use this to inject EXTINT, so
2938 * fail for in-kernel 8259.
2939 */
2940 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 2941 return -ENXIO;
f77bc6a4 2942
1c1a9ce9
SR		 2943 if (vcpu->arch.pending_external_vector != -1)
2944 return -EEXIST;
f77bc6a4 2945
1c1a9ce9 2946 vcpu->arch.pending_external_vector = irq->irq;
934bf653 2947 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 2948 return 0;
2949}
2950
c4abb7c9
JK		 2951static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2952{
c4abb7c9 2953 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2954
2955 return 0;
2956}
2957
f077825a
PB		 2958static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2959{
64d60670
PB		 2960 kvm_make_request(KVM_REQ_SMI, vcpu);
2961
f077825a
PB		 2962 return 0;
2963}
2964
b209749f
AK		 2965static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2966 struct kvm_tpr_access_ctl *tac)
2967{
2968 if (tac->flags)
2969 return -EINVAL;
2970 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2971 return 0;
2972}
2973
890ca9ae
HY		 2974static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2975 u64 mcg_cap)
2976{
2977 int r;
2978 unsigned bank_num = mcg_cap & 0xff, bank;
2979
2980 r = -EINVAL;
a9e38c3e 2981 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 2982 goto out;
c45dcc71 2983 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 2984 goto out;
2985 r = 0;
2986 vcpu->arch.mcg_cap = mcg_cap;
2987 /* Init IA32_MCG_CTL to all 1s */
2988 if (mcg_cap & MCG_CTL_P)
2989 vcpu->arch.mcg_ctl = ~(u64)0;
2990 /* Init IA32_MCi_CTL to all 1s */
2991 for (bank = 0; bank < bank_num; bank++)
2992 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR		 2993
2994 if (kvm_x86_ops->setup_mce)
2995 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 2996out:
2997 return r;
2998}
2999
3000static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3001 struct kvm_x86_mce *mce)
3002{
3003 u64 mcg_cap = vcpu->arch.mcg_cap;
3004 unsigned bank_num = mcg_cap & 0xff;
3005 u64 *banks = vcpu->arch.mce_banks;
3006
3007 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3008 return -EINVAL;
3009 /*
3010 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3011 * reporting is disabled
3012 */
3013 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3014 vcpu->arch.mcg_ctl != ~(u64)0)
3015 return 0;
3016 banks += 4 * mce->bank;
3017 /*
3018 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3019 * reporting is disabled for the bank
3020 */
3021 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3022 return 0;
3023 if (mce->status & MCI_STATUS_UC) {
3024 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3025 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3026 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3027 return 0;
3028 }
3029 if (banks[1] & MCI_STATUS_VAL)
3030 mce->status |= MCI_STATUS_OVER;
3031 banks[2] = mce->addr;
3032 banks[3] = mce->misc;
3033 vcpu->arch.mcg_status = mce->mcg_status;
3034 banks[1] = mce->status;
3035 kvm_queue_exception(vcpu, MC_VECTOR);
3036 } else if (!(banks[1] & MCI_STATUS_VAL)
3037 || !(banks[1] & MCI_STATUS_UC)) {
3038 if (banks[1] & MCI_STATUS_VAL)
3039 mce->status |= MCI_STATUS_OVER;
3040 banks[2] = mce->addr;
3041 banks[3] = mce->misc;
3042 banks[1] = mce->status;
3043 } else
3044 banks[1] |= MCI_STATUS_OVER;
3045 return 0;
3046}
3047
3cfc3092
JK		 3048static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3049 struct kvm_vcpu_events *events)
3050{
7460fb4a 3051 process_nmi(vcpu);
03b82a30
JK		 3052 events->exception.injected =
3053 vcpu->arch.exception.pending &&
3054 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3055 events->exception.nr = vcpu->arch.exception.nr;
3056 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3057 events->exception.pad = 0;
3cfc3092
JK		 3058 events->exception.error_code = vcpu->arch.exception.error_code;
3059
03b82a30
JK		 3060 events->interrupt.injected =
3061 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3062 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3063 events->interrupt.soft = 0;
37ccdcbe 3064 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3065
3066 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3067 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3068 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3069 events->nmi.pad = 0;
3cfc3092 3070
66450a21 3071 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3072
f077825a
PB		 3073 events->smi.smm = is_smm(vcpu);
3074 events->smi.pending = vcpu->arch.smi_pending;
3075 events->smi.smm_inside_nmi =
3076 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3077 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3078
dab4b911 3079 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3080 | KVM_VCPUEVENT_VALID_SHADOW
3081 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3082 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3083}
3084
6ef4e07e
XG		 3085static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3086
3cfc3092
JK		 3087static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3088 struct kvm_vcpu_events *events)
3089{
dab4b911 3090 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3091 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3092 | KVM_VCPUEVENT_VALID_SHADOW
3093 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3094 return -EINVAL;
3095
78e546c8 3096 if (events->exception.injected &&
28d06353
JM		 3097 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3098 is_guest_mode(vcpu)))
78e546c8
PB		 3099 return -EINVAL;
3100
28bf2888
DH		 3101 /* INITs are latched while in SMM */
3102 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3103 (events->smi.smm || events->smi.pending) &&
3104 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3105 return -EINVAL;
3106
7460fb4a 3107 process_nmi(vcpu);
3cfc3092
JK		 3108 vcpu->arch.exception.pending = events->exception.injected;
3109 vcpu->arch.exception.nr = events->exception.nr;
3110 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3111 vcpu->arch.exception.error_code = events->exception.error_code;
3112
3113 vcpu->arch.interrupt.pending = events->interrupt.injected;
3114 vcpu->arch.interrupt.nr = events->interrupt.nr;
3115 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3116 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3117 kvm_x86_ops->set_interrupt_shadow(vcpu,
3118 events->interrupt.shadow);
3cfc3092
JK		 3119
3120 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3121 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3122 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3123 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3124
66450a21 3125 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3126 lapic_in_kernel(vcpu))
66450a21 3127 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3128
f077825a 3129 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3130 u32 hflags = vcpu->arch.hflags;
f077825a 3131 if (events->smi.smm)
6ef4e07e 3132 hflags |= HF_SMM_MASK;
f077825a 3133 else
6ef4e07e
XG		 3134 hflags &= ~HF_SMM_MASK;
3135 kvm_set_hflags(vcpu, hflags);
3136
f077825a
PB		 3137 vcpu->arch.smi_pending = events->smi.pending;
3138 if (events->smi.smm_inside_nmi)
3139 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3140 else
3141 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
bce87cce 3142 if (lapic_in_kernel(vcpu)) {
f077825a
PB		 3143 if (events->smi.latched_init)
3144 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3145 else
3146 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3147 }
3148 }
3149
3842d135
AK		 3150 kvm_make_request(KVM_REQ_EVENT, vcpu);
3151
3cfc3092
JK		 3152 return 0;
3153}
3154
a1efbe77
JK		 3155static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3156 struct kvm_debugregs *dbgregs)
3157{
73aaf249
JK		 3158 unsigned long val;
3159
a1efbe77 3160 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3161 kvm_get_dr(vcpu, 6, &val);
73aaf249 3162 dbgregs->dr6 = val;
a1efbe77
JK		 3163 dbgregs->dr7 = vcpu->arch.dr7;
3164 dbgregs->flags = 0;
97e69aa6 3165 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3166}
3167
3168static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3169 struct kvm_debugregs *dbgregs)
3170{
3171 if (dbgregs->flags)
3172 return -EINVAL;
3173
d14bdb55
PB		 3174 if (dbgregs->dr6 & ~0xffffffffull)
3175 return -EINVAL;
3176 if (dbgregs->dr7 & ~0xffffffffull)
3177 return -EINVAL;
3178
a1efbe77 3179 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3180 kvm_update_dr0123(vcpu);
a1efbe77 3181 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3182 kvm_update_dr6(vcpu);
a1efbe77 3183 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3184 kvm_update_dr7(vcpu);
a1efbe77 3185
a1efbe77
JK		 3186 return 0;
3187}
3188
df1daba7
PB		 3189#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3190
3191static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3192{
c47ada30 3193 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3194 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3195 u64 valid;
3196
3197 /*
3198 * Copy legacy XSAVE area, to avoid complications with CPUID
3199 * leaves 0 and 1 in the loop below.
3200 */
3201 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3202
3203 /* Set XSTATE_BV */
00c87e9a 3204 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3205 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3206
3207 /*
3208 * Copy each region from the possibly compacted offset to the
3209 * non-compacted offset.
3210 */
d91cab78 3211 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3212 while (valid) {
3213 u64 feature = valid & -valid;
3214 int index = fls64(feature) - 1;
3215 void *src = get_xsave_addr(xsave, feature);
3216
3217 if (src) {
3218 u32 size, offset, ecx, edx;
3219 cpuid_count(XSTATE_CPUID, index,
3220 &size, &offset, &ecx, &edx);
3221 memcpy(dest + offset, src, size);
3222 }
3223
3224 valid -= feature;
3225 }
3226}
3227
3228static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3229{
c47ada30 3230 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB		 3231 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3232 u64 valid;
3233
3234 /*
3235 * Copy legacy XSAVE area, to avoid complications with CPUID
3236 * leaves 0 and 1 in the loop below.
3237 */
3238 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3239
3240 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3241 xsave->header.xfeatures = xstate_bv;
782511b0 3242 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3243 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 3244
3245 /*
3246 * Copy each region from the non-compacted offset to the
3247 * possibly compacted offset.
3248 */
d91cab78 3249 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB		 3250 while (valid) {
3251 u64 feature = valid & -valid;
3252 int index = fls64(feature) - 1;
3253 void *dest = get_xsave_addr(xsave, feature);
3254
3255 if (dest) {
3256 u32 size, offset, ecx, edx;
3257 cpuid_count(XSTATE_CPUID, index,
3258 &size, &offset, &ecx, &edx);
3259 memcpy(dest, src + offset, size);
ee4100da 3260 }
df1daba7
PB		 3261
3262 valid -= feature;
3263 }
3264}
3265
2d5b5a66
SY		 3266static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3267 struct kvm_xsave *guest_xsave)
3268{
d366bf7e 3269 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 3270 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3271 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3272 } else {
2d5b5a66 3273 memcpy(guest_xsave->region,
7366ed77 3274 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3275 sizeof(struct fxregs_state));
2d5b5a66 3276 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3277 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 3278 }
3279}
3280
3281static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3282 struct kvm_xsave *guest_xsave)
3283{
3284 u64 xstate_bv =
3285 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3286
d366bf7e 3287 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 3288 /*
3289 * Here we allow setting states that are not present in
3290 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3291 * with old userspace.
3292 */
4ff41732 3293 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3294 return -EINVAL;
df1daba7 3295 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3296 } else {
d91cab78 3297 if (xstate_bv & ~XFEATURE_MASK_FPSSE)
2d5b5a66 3298 return -EINVAL;
7366ed77 3299 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3300 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 3301 }
3302 return 0;
3303}
3304
3305static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3306 struct kvm_xcrs *guest_xcrs)
3307{
d366bf7e 3308 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 3309 guest_xcrs->nr_xcrs = 0;
3310 return;
3311 }
3312
3313 guest_xcrs->nr_xcrs = 1;
3314 guest_xcrs->flags = 0;
3315 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3316 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3317}
3318
3319static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3320 struct kvm_xcrs *guest_xcrs)
3321{
3322 int i, r = 0;
3323
d366bf7e 3324 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 3325 return -EINVAL;
3326
3327 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3328 return -EINVAL;
3329
3330 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3331 /* Only support XCR0 currently */
c67a04cb 3332 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3333 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3334 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3335 break;
3336 }
3337 if (r)
3338 r = -EINVAL;
3339 return r;
3340}
3341
1c0b28c2
EM		 3342/*
3343 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3344 * stopped by the hypervisor. This function will be called from the host only.
3345 * EINVAL is returned when the host attempts to set the flag for a guest that
3346 * does not support pv clocks.
3347 */
3348static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3349{
0b79459b 3350 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3351 return -EINVAL;
51d59c6b 3352 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3353 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3354 return 0;
3355}
3356
5c919412
AS		 3357static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3358 struct kvm_enable_cap *cap)
3359{
3360 if (cap->flags)
3361 return -EINVAL;
3362
3363 switch (cap->cap) {
3364 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 3365 if (!irqchip_in_kernel(vcpu->kvm))
3366 return -EINVAL;
5c919412
AS		 3367 return kvm_hv_activate_synic(vcpu);
3368 default:
3369 return -EINVAL;
3370 }
3371}
3372
313a3dc7
CO		 3373long kvm_arch_vcpu_ioctl(struct file *filp,
3374 unsigned int ioctl, unsigned long arg)
3375{
3376 struct kvm_vcpu *vcpu = filp->private_data;
3377 void __user *argp = (void __user *)arg;
3378 int r;
d1ac91d8
AK		 3379 union {
3380 struct kvm_lapic_state *lapic;
3381 struct kvm_xsave *xsave;
3382 struct kvm_xcrs *xcrs;
3383 void *buffer;
3384 } u;
3385
3386 u.buffer = NULL;
313a3dc7
CO		 3387 switch (ioctl) {
3388 case KVM_GET_LAPIC: {
2204ae3c 3389 r = -EINVAL;
bce87cce 3390 if (!lapic_in_kernel(vcpu))
2204ae3c 3391 goto out;
d1ac91d8 3392 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3393
b772ff36 3394 r = -ENOMEM;
d1ac91d8 3395 if (!u.lapic)
b772ff36 3396 goto out;
d1ac91d8 3397 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3398 if (r)
3399 goto out;
3400 r = -EFAULT;
d1ac91d8 3401 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3402 goto out;
3403 r = 0;
3404 break;
3405 }
3406 case KVM_SET_LAPIC: {
2204ae3c 3407 r = -EINVAL;
bce87cce 3408 if (!lapic_in_kernel(vcpu))
2204ae3c 3409 goto out;
ff5c2c03 3410 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3411 if (IS_ERR(u.lapic))
3412 return PTR_ERR(u.lapic);
ff5c2c03 3413
d1ac91d8 3414 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3415 break;
3416 }
f77bc6a4
ZX		 3417 case KVM_INTERRUPT: {
3418 struct kvm_interrupt irq;
3419
3420 r = -EFAULT;
3421 if (copy_from_user(&irq, argp, sizeof irq))
3422 goto out;
3423 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3424 break;
3425 }
c4abb7c9
JK		 3426 case KVM_NMI: {
3427 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3428 break;
3429 }
f077825a
PB		 3430 case KVM_SMI: {
3431 r = kvm_vcpu_ioctl_smi(vcpu);
3432 break;
3433 }
313a3dc7
CO		 3434 case KVM_SET_CPUID: {
3435 struct kvm_cpuid __user *cpuid_arg = argp;
3436 struct kvm_cpuid cpuid;
3437
3438 r = -EFAULT;
3439 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3440 goto out;
3441 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3442 break;
3443 }
07716717
DK		 3444 case KVM_SET_CPUID2: {
3445 struct kvm_cpuid2 __user *cpuid_arg = argp;
3446 struct kvm_cpuid2 cpuid;
3447
3448 r = -EFAULT;
3449 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3450 goto out;
3451 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3452 cpuid_arg->entries);
07716717
DK		 3453 break;
3454 }
3455 case KVM_GET_CPUID2: {
3456 struct kvm_cpuid2 __user *cpuid_arg = argp;
3457 struct kvm_cpuid2 cpuid;
3458
3459 r = -EFAULT;
3460 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3461 goto out;
3462 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3463 cpuid_arg->entries);
07716717
DK		 3464 if (r)
3465 goto out;
3466 r = -EFAULT;
3467 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3468 goto out;
3469 r = 0;
3470 break;
3471 }
313a3dc7 3472 case KVM_GET_MSRS:
609e36d3 3473 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3474 break;
3475 case KVM_SET_MSRS:
3476 r = msr_io(vcpu, argp, do_set_msr, 0);
3477 break;
b209749f
AK		 3478 case KVM_TPR_ACCESS_REPORTING: {
3479 struct kvm_tpr_access_ctl tac;
3480
3481 r = -EFAULT;
3482 if (copy_from_user(&tac, argp, sizeof tac))
3483 goto out;
3484 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3485 if (r)
3486 goto out;
3487 r = -EFAULT;
3488 if (copy_to_user(argp, &tac, sizeof tac))
3489 goto out;
3490 r = 0;
3491 break;
3492 };
b93463aa
AK		 3493 case KVM_SET_VAPIC_ADDR: {
3494 struct kvm_vapic_addr va;
7301d6ab 3495 int idx;
b93463aa
AK		 3496
3497 r = -EINVAL;
35754c98 3498 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 3499 goto out;
3500 r = -EFAULT;
3501 if (copy_from_user(&va, argp, sizeof va))
3502 goto out;
7301d6ab 3503 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3504 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3505 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 3506 break;
3507 }
890ca9ae
HY		 3508 case KVM_X86_SETUP_MCE: {
3509 u64 mcg_cap;
3510
3511 r = -EFAULT;
3512 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3513 goto out;
3514 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3515 break;
3516 }
3517 case KVM_X86_SET_MCE: {
3518 struct kvm_x86_mce mce;
3519
3520 r = -EFAULT;
3521 if (copy_from_user(&mce, argp, sizeof mce))
3522 goto out;
3523 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3524 break;
3525 }
3cfc3092
JK		 3526 case KVM_GET_VCPU_EVENTS: {
3527 struct kvm_vcpu_events events;
3528
3529 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3530
3531 r = -EFAULT;
3532 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3533 break;
3534 r = 0;
3535 break;
3536 }
3537 case KVM_SET_VCPU_EVENTS: {
3538 struct kvm_vcpu_events events;
3539
3540 r = -EFAULT;
3541 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3542 break;
3543
3544 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3545 break;
3546 }
a1efbe77
JK		 3547 case KVM_GET_DEBUGREGS: {
3548 struct kvm_debugregs dbgregs;
3549
3550 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3551
3552 r = -EFAULT;
3553 if (copy_to_user(argp, &dbgregs,
3554 sizeof(struct kvm_debugregs)))
3555 break;
3556 r = 0;
3557 break;
3558 }
3559 case KVM_SET_DEBUGREGS: {
3560 struct kvm_debugregs dbgregs;
3561
3562 r = -EFAULT;
3563 if (copy_from_user(&dbgregs, argp,
3564 sizeof(struct kvm_debugregs)))
3565 break;
3566
3567 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3568 break;
3569 }
2d5b5a66 3570 case KVM_GET_XSAVE: {
d1ac91d8 3571 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3572 r = -ENOMEM;
d1ac91d8 3573 if (!u.xsave)
2d5b5a66
SY		 3574 break;
3575
d1ac91d8 3576 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3577
3578 r = -EFAULT;
d1ac91d8 3579 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3580 break;
3581 r = 0;
3582 break;
3583 }
3584 case KVM_SET_XSAVE: {
ff5c2c03 3585 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3586 if (IS_ERR(u.xsave))
3587 return PTR_ERR(u.xsave);
2d5b5a66 3588
d1ac91d8 3589 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3590 break;
3591 }
3592 case KVM_GET_XCRS: {
d1ac91d8 3593 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3594 r = -ENOMEM;
d1ac91d8 3595 if (!u.xcrs)
2d5b5a66
SY		 3596 break;
3597
d1ac91d8 3598 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3599
3600 r = -EFAULT;
d1ac91d8 3601 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3602 sizeof(struct kvm_xcrs)))
3603 break;
3604 r = 0;
3605 break;
3606 }
3607 case KVM_SET_XCRS: {
ff5c2c03 3608 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3609 if (IS_ERR(u.xcrs))
3610 return PTR_ERR(u.xcrs);
2d5b5a66 3611
d1ac91d8 3612 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3613 break;
3614 }
92a1f12d
JR		 3615 case KVM_SET_TSC_KHZ: {
3616 u32 user_tsc_khz;
3617
3618 r = -EINVAL;
92a1f12d
JR		 3619 user_tsc_khz = (u32)arg;
3620
3621 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3622 goto out;
3623
cc578287
ZA		 3624 if (user_tsc_khz == 0)
3625 user_tsc_khz = tsc_khz;
3626
381d585c
HZ		 3627 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3628 r = 0;
92a1f12d 3629
92a1f12d
JR		 3630 goto out;
3631 }
3632 case KVM_GET_TSC_KHZ: {
cc578287 3633 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3634 goto out;
3635 }
1c0b28c2
EM		 3636 case KVM_KVMCLOCK_CTRL: {
3637 r = kvm_set_guest_paused(vcpu);
3638 goto out;
3639 }
5c919412
AS		 3640 case KVM_ENABLE_CAP: {
3641 struct kvm_enable_cap cap;
3642
3643 r = -EFAULT;
3644 if (copy_from_user(&cap, argp, sizeof(cap)))
3645 goto out;
3646 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3647 break;
3648 }
313a3dc7
CO		 3649 default:
3650 r = -EINVAL;
3651 }
3652out:
d1ac91d8 3653 kfree(u.buffer);
313a3dc7
CO		 3654 return r;
3655}
3656
5b1c1493
CO		 3657int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3658{
3659 return VM_FAULT_SIGBUS;
3660}
3661
1fe779f8
CO		 3662static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3663{
3664 int ret;
3665
3666 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3667 return -EINVAL;
1fe779f8
CO		 3668 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3669 return ret;
3670}
3671
b927a3ce
SY		 3672static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3673 u64 ident_addr)
3674{
3675 kvm->arch.ept_identity_map_addr = ident_addr;
3676 return 0;
3677}
3678
1fe779f8
CO		 3679static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3680 u32 kvm_nr_mmu_pages)
3681{
3682 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3683 return -EINVAL;
3684
79fac95e 3685 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3686
3687 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3688 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3689
79fac95e 3690 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3691 return 0;
3692}
3693
3694static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3695{
39de71ec 3696 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3697}
3698
1fe779f8
CO		 3699static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3700{
90bca052 3701 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3702 int r;
3703
3704 r = 0;
3705 switch (chip->chip_id) {
3706 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3707 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 3708 sizeof(struct kvm_pic_state));
3709 break;
3710 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3711 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 3712 sizeof(struct kvm_pic_state));
3713 break;
3714 case KVM_IRQCHIP_IOAPIC:
33392b49 3715 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3716 break;
3717 default:
3718 r = -EINVAL;
3719 break;
3720 }
3721 return r;
3722}
3723
3724static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3725{
90bca052 3726 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 3727 int r;
3728
3729 r = 0;
3730 switch (chip->chip_id) {
3731 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 3732 spin_lock(&pic->lock);
3733 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3734 sizeof(struct kvm_pic_state));
90bca052 3735 spin_unlock(&pic->lock);
1fe779f8
CO		 3736 break;
3737 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 3738 spin_lock(&pic->lock);
3739 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3740 sizeof(struct kvm_pic_state));
90bca052 3741 spin_unlock(&pic->lock);
1fe779f8
CO		 3742 break;
3743 case KVM_IRQCHIP_IOAPIC:
33392b49 3744 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3745 break;
3746 default:
3747 r = -EINVAL;
3748 break;
3749 }
90bca052 3750 kvm_pic_update_irq(pic);
1fe779f8
CO		 3751 return r;
3752}
3753
e0f63cb9
SY		 3754static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3755{
34f3941c
RK		 3756 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3757
3758 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3759
3760 mutex_lock(&kps->lock);
3761 memcpy(ps, &kps->channels, sizeof(*ps));
3762 mutex_unlock(&kps->lock);
2da29bcc 3763 return 0;
e0f63cb9
SY		 3764}
3765
3766static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3767{
0185604c 3768 int i;
09edea72
RK		 3769 struct kvm_pit *pit = kvm->arch.vpit;
3770
3771 mutex_lock(&pit->pit_state.lock);
34f3941c 3772 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3773 for (i = 0; i < 3; i++)
09edea72
RK		 3774 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3775 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3776 return 0;
e9f42757
BK		 3777}
3778
3779static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3780{
e9f42757
BK		 3781 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3782 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3783 sizeof(ps->channels));
3784 ps->flags = kvm->arch.vpit->pit_state.flags;
3785 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3786 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3787 return 0;
e9f42757
BK		 3788}
3789
3790static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3791{
2da29bcc 3792 int start = 0;
0185604c 3793 int i;
e9f42757 3794 u32 prev_legacy, cur_legacy;
09edea72
RK		 3795 struct kvm_pit *pit = kvm->arch.vpit;
3796
3797 mutex_lock(&pit->pit_state.lock);
3798 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 3799 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3800 if (!prev_legacy && cur_legacy)
3801 start = 1;
09edea72
RK		 3802 memcpy(&pit->pit_state.channels, &ps->channels,
3803 sizeof(pit->pit_state.channels));
3804 pit->pit_state.flags = ps->flags;
0185604c 3805 for (i = 0; i < 3; i++)
09edea72 3806 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3807 start && i == 0);
09edea72 3808 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3809 return 0;
e0f63cb9
SY		 3810}
3811
52d939a0
MT		 3812static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3813 struct kvm_reinject_control *control)
3814{
71474e2f
RK		 3815 struct kvm_pit *pit = kvm->arch.vpit;
3816
3817 if (!pit)
52d939a0 3818 return -ENXIO;
b39c90b6 3819
71474e2f
RK		 3820 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3821 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3822 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3823 */
3824 mutex_lock(&pit->pit_state.lock);
3825 kvm_pit_set_reinject(pit, control->pit_reinject);
3826 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3827
52d939a0
MT		 3828 return 0;
3829}
3830
95d4c16c 3831/**
60c34612
TY		 3832 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3833 * @kvm: kvm instance
3834 * @log: slot id and address to which we copy the log
95d4c16c 3835 *
e108ff2f
PB		 3836 * Steps 1-4 below provide general overview of dirty page logging. See
3837 * kvm_get_dirty_log_protect() function description for additional details.
3838 *
3839 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3840 * always flush the TLB (step 4) even if previous step failed and the dirty
3841 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3842 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3843 * writes will be marked dirty for next log read.
95d4c16c 3844 *
60c34612
TY		 3845 * 1. Take a snapshot of the bit and clear it if needed.
3846 * 2. Write protect the corresponding page.
e108ff2f
PB		 3847 * 3. Copy the snapshot to the userspace.
3848 * 4. Flush TLB's if needed.
5bb064dc 3849 */
60c34612 3850int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3851{
60c34612 3852 bool is_dirty = false;
e108ff2f 3853 int r;
5bb064dc 3854
79fac95e 3855 mutex_lock(&kvm->slots_lock);
5bb064dc 3856
88178fd4
KH		 3857 /*
3858 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3859 */
3860 if (kvm_x86_ops->flush_log_dirty)
3861 kvm_x86_ops->flush_log_dirty(kvm);
3862
e108ff2f 3863 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3864
3865 /*
3866 * All the TLBs can be flushed out of mmu lock, see the comments in
3867 * kvm_mmu_slot_remove_write_access().
3868 */
e108ff2f 3869 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3870 if (is_dirty)
3871 kvm_flush_remote_tlbs(kvm);
3872
79fac95e 3873 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3874 return r;
3875}
3876
aa2fbe6d
YZ		 3877int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3878 bool line_status)
23d43cf9
CD		 3879{
3880 if (!irqchip_in_kernel(kvm))
3881 return -ENXIO;
3882
3883 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3884 irq_event->irq, irq_event->level,
3885 line_status);
23d43cf9
CD		 3886 return 0;
3887}
3888
90de4a18
NA		 3889static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3890 struct kvm_enable_cap *cap)
3891{
3892 int r;
3893
3894 if (cap->flags)
3895 return -EINVAL;
3896
3897 switch (cap->cap) {
3898 case KVM_CAP_DISABLE_QUIRKS:
3899 kvm->arch.disabled_quirks = cap->args[0];
3900 r = 0;
3901 break;
49df6397
SR		 3902 case KVM_CAP_SPLIT_IRQCHIP: {
3903 mutex_lock(&kvm->lock);
b053b2ae
SR		 3904 r = -EINVAL;
3905 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
3906 goto split_irqchip_unlock;
49df6397
SR		 3907 r = -EEXIST;
3908 if (irqchip_in_kernel(kvm))
3909 goto split_irqchip_unlock;
557abc40 3910 if (kvm->created_vcpus)
49df6397 3911 goto split_irqchip_unlock;
637e3f86 3912 kvm->arch.irqchip_mode = KVM_IRQCHIP_INIT_IN_PROGRESS;
49df6397 3913 r = kvm_setup_empty_irq_routing(kvm);
637e3f86
DH		 3914 if (r) {
3915 kvm->arch.irqchip_mode = KVM_IRQCHIP_NONE;
3916 /* Pairs with smp_rmb() when reading irqchip_mode */
3917 smp_wmb();
49df6397 3918 goto split_irqchip_unlock;
637e3f86 3919 }
49df6397
SR		 3920 /* Pairs with irqchip_in_kernel. */
3921 smp_wmb();
49776faf 3922 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 3923 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 3924 r = 0;
3925split_irqchip_unlock:
3926 mutex_unlock(&kvm->lock);
3927 break;
3928 }
37131313
RK		 3929 case KVM_CAP_X2APIC_API:
3930 r = -EINVAL;
3931 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
3932 break;
3933
3934 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
3935 kvm->arch.x2apic_format = true;
c519265f
RK		 3936 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
3937 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 3938
3939 r = 0;
3940 break;
90de4a18
NA		 3941 default:
3942 r = -EINVAL;
3943 break;
3944 }
3945 return r;
3946}
3947
1fe779f8
CO		 3948long kvm_arch_vm_ioctl(struct file *filp,
3949 unsigned int ioctl, unsigned long arg)
3950{
3951 struct kvm *kvm = filp->private_data;
3952 void __user *argp = (void __user *)arg;
367e1319 3953 int r = -ENOTTY;
f0d66275
DH		 3954 /*
3955 * This union makes it completely explicit to gcc-3.x
3956 * that these two variables' stack usage should be
3957 * combined, not added together.
3958 */
3959 union {
3960 struct kvm_pit_state ps;
e9f42757 3961 struct kvm_pit_state2 ps2;
c5ff41ce 3962 struct kvm_pit_config pit_config;
f0d66275 3963 } u;
1fe779f8
CO		 3964
3965 switch (ioctl) {
3966 case KVM_SET_TSS_ADDR:
3967 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3968 break;
b927a3ce
SY		 3969 case KVM_SET_IDENTITY_MAP_ADDR: {
3970 u64 ident_addr;
3971
3972 r = -EFAULT;
3973 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3974 goto out;
3975 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3976 break;
3977 }
1fe779f8
CO		 3978 case KVM_SET_NR_MMU_PAGES:
3979 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3980 break;
3981 case KVM_GET_NR_MMU_PAGES:
3982 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3983 break;
3ddea128 3984 case KVM_CREATE_IRQCHIP: {
3ddea128 3985 mutex_lock(&kvm->lock);
09941366 3986
3ddea128 3987 r = -EEXIST;
35e6eaa3 3988 if (irqchip_in_kernel(kvm))
3ddea128 3989 goto create_irqchip_unlock;
09941366 3990
3e515705 3991 r = -EINVAL;
557abc40 3992 if (kvm->created_vcpus)
3e515705 3993 goto create_irqchip_unlock;
09941366
RK		 3994
3995 r = kvm_pic_init(kvm);
3996 if (r)
3ddea128 3997 goto create_irqchip_unlock;
09941366
RK		 3998
3999 r = kvm_ioapic_init(kvm);
4000 if (r) {
09941366 4001 kvm_pic_destroy(kvm);
3ddea128 4002 goto create_irqchip_unlock;
09941366
RK		 4003 }
4004
637e3f86 4005 kvm->arch.irqchip_mode = KVM_IRQCHIP_INIT_IN_PROGRESS;
399ec807
AK		 4006 r = kvm_setup_default_irq_routing(kvm);
4007 if (r) {
637e3f86
DH		 4008 kvm->arch.irqchip_mode = KVM_IRQCHIP_NONE;
4009 /* Pairs with smp_rmb() when reading irqchip_mode */
4010 smp_wmb();
72bb2fcd 4011 kvm_ioapic_destroy(kvm);
09941366 4012 kvm_pic_destroy(kvm);
71ba994c 4013 goto create_irqchip_unlock;
399ec807 4014 }
49776faf 4015 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4016 smp_wmb();
49776faf 4017 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4018 create_irqchip_unlock:
4019 mutex_unlock(&kvm->lock);
1fe779f8 4020 break;
3ddea128 4021 }
7837699f 4022 case KVM_CREATE_PIT:
c5ff41ce
JK		 4023 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4024 goto create_pit;
4025 case KVM_CREATE_PIT2:
4026 r = -EFAULT;
4027 if (copy_from_user(&u.pit_config, argp,
4028 sizeof(struct kvm_pit_config)))
4029 goto out;
4030 create_pit:
250715a6 4031 mutex_lock(&kvm->lock);
269e05e4
AK		 4032 r = -EEXIST;
4033 if (kvm->arch.vpit)
4034 goto create_pit_unlock;
7837699f 4035 r = -ENOMEM;
c5ff41ce 4036 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 4037 if (kvm->arch.vpit)
4038 r = 0;
269e05e4 4039 create_pit_unlock:
250715a6 4040 mutex_unlock(&kvm->lock);
7837699f 4041 break;
1fe779f8
CO		 4042 case KVM_GET_IRQCHIP: {
4043 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4044 struct kvm_irqchip *chip;
1fe779f8 4045
ff5c2c03
SL		 4046 chip = memdup_user(argp, sizeof(*chip));
4047 if (IS_ERR(chip)) {
4048 r = PTR_ERR(chip);
1fe779f8 4049 goto out;
ff5c2c03
SL		 4050 }
4051
1fe779f8 4052 r = -ENXIO;
826da321 4053 if (!irqchip_kernel(kvm))
f0d66275
DH		 4054 goto get_irqchip_out;
4055 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4056 if (r)
f0d66275 4057 goto get_irqchip_out;
1fe779f8 4058 r = -EFAULT;
f0d66275
DH		 4059 if (copy_to_user(argp, chip, sizeof *chip))
4060 goto get_irqchip_out;
1fe779f8 4061 r = 0;
f0d66275
DH		 4062 get_irqchip_out:
4063 kfree(chip);
1fe779f8
CO		 4064 break;
4065 }
4066 case KVM_SET_IRQCHIP: {
4067 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4068 struct kvm_irqchip *chip;
1fe779f8 4069
ff5c2c03
SL		 4070 chip = memdup_user(argp, sizeof(*chip));
4071 if (IS_ERR(chip)) {
4072 r = PTR_ERR(chip);
1fe779f8 4073 goto out;
ff5c2c03
SL		 4074 }
4075
1fe779f8 4076 r = -ENXIO;
826da321 4077 if (!irqchip_kernel(kvm))
f0d66275
DH		 4078 goto set_irqchip_out;
4079 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4080 if (r)
f0d66275 4081 goto set_irqchip_out;
1fe779f8 4082 r = 0;
f0d66275
DH		 4083 set_irqchip_out:
4084 kfree(chip);
1fe779f8
CO		 4085 break;
4086 }
e0f63cb9 4087 case KVM_GET_PIT: {
e0f63cb9 4088 r = -EFAULT;
f0d66275 4089 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4090 goto out;
4091 r = -ENXIO;
4092 if (!kvm->arch.vpit)
4093 goto out;
f0d66275 4094 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 4095 if (r)
4096 goto out;
4097 r = -EFAULT;
f0d66275 4098 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 4099 goto out;
4100 r = 0;
4101 break;
4102 }
4103 case KVM_SET_PIT: {
e0f63cb9 4104 r = -EFAULT;
f0d66275 4105 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 4106 goto out;
4107 r = -ENXIO;
4108 if (!kvm->arch.vpit)
4109 goto out;
f0d66275 4110 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 4111 break;
4112 }
e9f42757
BK		 4113 case KVM_GET_PIT2: {
4114 r = -ENXIO;
4115 if (!kvm->arch.vpit)
4116 goto out;
4117 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4118 if (r)
4119 goto out;
4120 r = -EFAULT;
4121 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4122 goto out;
4123 r = 0;
4124 break;
4125 }
4126 case KVM_SET_PIT2: {
4127 r = -EFAULT;
4128 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4129 goto out;
4130 r = -ENXIO;
4131 if (!kvm->arch.vpit)
4132 goto out;
4133 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 4134 break;
4135 }
52d939a0
MT		 4136 case KVM_REINJECT_CONTROL: {
4137 struct kvm_reinject_control control;
4138 r = -EFAULT;
4139 if (copy_from_user(&control, argp, sizeof(control)))
4140 goto out;
4141 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4142 break;
4143 }
d71ba788
PB		 4144 case KVM_SET_BOOT_CPU_ID:
4145 r = 0;
4146 mutex_lock(&kvm->lock);
557abc40 4147 if (kvm->created_vcpus)
d71ba788
PB		 4148 r = -EBUSY;
4149 else
4150 kvm->arch.bsp_vcpu_id = arg;
4151 mutex_unlock(&kvm->lock);
4152 break;
ffde22ac
ES		 4153 case KVM_XEN_HVM_CONFIG: {
4154 r = -EFAULT;
4155 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4156 sizeof(struct kvm_xen_hvm_config)))
4157 goto out;
4158 r = -EINVAL;
4159 if (kvm->arch.xen_hvm_config.flags)
4160 goto out;
4161 r = 0;
4162 break;
4163 }
afbcf7ab 4164 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4165 struct kvm_clock_data user_ns;
4166 u64 now_ns;
afbcf7ab
GC		 4167
4168 r = -EFAULT;
4169 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4170 goto out;
4171
4172 r = -EINVAL;
4173 if (user_ns.flags)
4174 goto out;
4175
4176 r = 0;
395c6b0a 4177 local_irq_disable();
108b249c
PB		 4178 now_ns = __get_kvmclock_ns(kvm);
4179 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
395c6b0a 4180 local_irq_enable();
2e762ff7 4181 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4182 break;
4183 }
4184 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4185 struct kvm_clock_data user_ns;
4186 u64 now_ns;
4187
e3fd9a93
PB		 4188 local_irq_disable();
4189 now_ns = __get_kvmclock_ns(kvm);
108b249c 4190 user_ns.clock = now_ns;
e3fd9a93
PB		 4191 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
4192 local_irq_enable();
97e69aa6 4193 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4194
4195 r = -EFAULT;
4196 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4197 goto out;
4198 r = 0;
4199 break;
4200 }
90de4a18
NA		 4201 case KVM_ENABLE_CAP: {
4202 struct kvm_enable_cap cap;
afbcf7ab 4203
90de4a18
NA		 4204 r = -EFAULT;
4205 if (copy_from_user(&cap, argp, sizeof(cap)))
4206 goto out;
4207 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4208 break;
4209 }
1fe779f8 4210 default:
ad6260da 4211 r = -ENOTTY;
1fe779f8
CO		 4212 }
4213out:
4214 return r;
4215}
4216
a16b043c 4217static void kvm_init_msr_list(void)
043405e1
CO		 4218{
4219 u32 dummy[2];
4220 unsigned i, j;
4221
62ef68bb 4222 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4223 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4224 continue;
93c4adc7
PB		 4225
4226 /*
4227 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4228 * to the guests in some cases.
93c4adc7
PB		 4229 */
4230 switch (msrs_to_save[i]) {
4231 case MSR_IA32_BNDCFGS:
4232 if (!kvm_x86_ops->mpx_supported())
4233 continue;
4234 break;
9dbe6cf9
PB		 4235 case MSR_TSC_AUX:
4236 if (!kvm_x86_ops->rdtscp_supported())
4237 continue;
4238 break;
93c4adc7
PB		 4239 default:
4240 break;
4241 }
4242
043405e1
CO		 4243 if (j < i)
4244 msrs_to_save[j] = msrs_to_save[i];
4245 j++;
4246 }
4247 num_msrs_to_save = j;
62ef68bb
PB		 4248
4249 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4250 switch (emulated_msrs[i]) {
6d396b55
PB		 4251 case MSR_IA32_SMBASE:
4252 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4253 continue;
4254 break;
62ef68bb
PB		 4255 default:
4256 break;
4257 }
4258
4259 if (j < i)
4260 emulated_msrs[j] = emulated_msrs[i];
4261 j++;
4262 }
4263 num_emulated_msrs = j;
043405e1
CO		 4264}
4265
bda9020e
MT		 4266static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4267 const void *v)
bbd9b64e 4268{
70252a10
AK		 4269 int handled = 0;
4270 int n;
4271
4272 do {
4273 n = min(len, 8);
bce87cce 4274 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4275 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4276 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4277 break;
4278 handled += n;
4279 addr += n;
4280 len -= n;
4281 v += n;
4282 } while (len);
bbd9b64e 4283
70252a10 4284 return handled;
bbd9b64e
CO		 4285}
4286
bda9020e 4287static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4288{
70252a10
AK		 4289 int handled = 0;
4290 int n;
4291
4292 do {
4293 n = min(len, 8);
bce87cce 4294 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 4295 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4296 addr, n, v))
4297 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4298 break;
4299 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4300 handled += n;
4301 addr += n;
4302 len -= n;
4303 v += n;
4304 } while (len);
bbd9b64e 4305
70252a10 4306 return handled;
bbd9b64e
CO		 4307}
4308
2dafc6c2
GN		 4309static void kvm_set_segment(struct kvm_vcpu *vcpu,
4310 struct kvm_segment *var, int seg)
4311{
4312 kvm_x86_ops->set_segment(vcpu, var, seg);
4313}
4314
4315void kvm_get_segment(struct kvm_vcpu *vcpu,
4316 struct kvm_segment *var, int seg)
4317{
4318 kvm_x86_ops->get_segment(vcpu, var, seg);
4319}
4320
54987b7a
PB		 4321gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4322 struct x86_exception *exception)
02f59dc9
JR		 4323{
4324 gpa_t t_gpa;
02f59dc9
JR		 4325
4326 BUG_ON(!mmu_is_nested(vcpu));
4327
4328 /* NPT walks are always user-walks */
4329 access |= PFERR_USER_MASK;
54987b7a 4330 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4331
4332 return t_gpa;
4333}
4334
ab9ae313
AK		 4335gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4336 struct x86_exception *exception)
1871c602
GN		 4337{
4338 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4339 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4340}
4341
ab9ae313
AK		 4342 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4343 struct x86_exception *exception)
1871c602
GN		 4344{
4345 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4346 access |= PFERR_FETCH_MASK;
ab9ae313 4347 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4348}
4349
ab9ae313
AK		 4350gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4351 struct x86_exception *exception)
1871c602
GN		 4352{
4353 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4354 access |= PFERR_WRITE_MASK;
ab9ae313 4355 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4356}
4357
4358/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4359gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4360 struct x86_exception *exception)
1871c602 4361{
ab9ae313 4362 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4363}
4364
4365static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4366 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4367 struct x86_exception *exception)
bbd9b64e
CO		 4368{
4369 void *data = val;
10589a46 4370 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4371
4372 while (bytes) {
14dfe855 4373 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4374 exception);
bbd9b64e 4375 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4376 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4377 int ret;
4378
bcc55cba 4379 if (gpa == UNMAPPED_GVA)
ab9ae313 4380 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4381 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4382 offset, toread);
10589a46 4383 if (ret < 0) {
c3cd7ffa 4384 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4385 goto out;
4386 }
bbd9b64e 4387
77c2002e
IE		 4388 bytes -= toread;
4389 data += toread;
4390 addr += toread;
bbd9b64e 4391 }
10589a46 4392out:
10589a46 4393 return r;
bbd9b64e 4394}
77c2002e 4395
1871c602 4396/* used for instruction fetching */
0f65dd70
AK		 4397static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4398 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4399 struct x86_exception *exception)
1871c602 4400{
0f65dd70 4401 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4402 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4403 unsigned offset;
4404 int ret;
0f65dd70 4405
44583cba
PB		 4406 /* Inline kvm_read_guest_virt_helper for speed. */
4407 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4408 exception);
4409 if (unlikely(gpa == UNMAPPED_GVA))
4410 return X86EMUL_PROPAGATE_FAULT;
4411
4412 offset = addr & (PAGE_SIZE-1);
4413 if (WARN_ON(offset + bytes > PAGE_SIZE))
4414 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4415 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4416 offset, bytes);
44583cba
PB		 4417 if (unlikely(ret < 0))
4418 return X86EMUL_IO_NEEDED;
4419
4420 return X86EMUL_CONTINUE;
1871c602
GN		 4421}
4422
064aea77 4423int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4424 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4425 struct x86_exception *exception)
1871c602 4426{
0f65dd70 4427 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4428 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4429
1871c602 4430 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4431 exception);
1871c602 4432}
064aea77 4433EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4434
0f65dd70
AK		 4435static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4436 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4437 struct x86_exception *exception)
1871c602 4438{
0f65dd70 4439 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4440 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4441}
4442
7a036a6f
RK		 4443static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4444 unsigned long addr, void *val, unsigned int bytes)
4445{
4446 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4447 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4448
4449 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4450}
4451
6a4d7550 4452int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4453 gva_t addr, void *val,
2dafc6c2 4454 unsigned int bytes,
bcc55cba 4455 struct x86_exception *exception)
77c2002e 4456{
0f65dd70 4457 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4458 void *data = val;
4459 int r = X86EMUL_CONTINUE;
4460
4461 while (bytes) {
14dfe855
JR		 4462 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4463 PFERR_WRITE_MASK,
ab9ae313 4464 exception);
77c2002e
IE		 4465 unsigned offset = addr & (PAGE_SIZE-1);
4466 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4467 int ret;
4468
bcc55cba 4469 if (gpa == UNMAPPED_GVA)
ab9ae313 4470 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4471 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4472 if (ret < 0) {
c3cd7ffa 4473 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4474 goto out;
4475 }
4476
4477 bytes -= towrite;
4478 data += towrite;
4479 addr += towrite;
4480 }
4481out:
4482 return r;
4483}
6a4d7550 4484EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4485
0f89b207
TL		 4486static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4487 gpa_t gpa, bool write)
4488{
4489 /* For APIC access vmexit */
4490 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4491 return 1;
4492
4493 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4494 trace_vcpu_match_mmio(gva, gpa, write, true);
4495 return 1;
4496 }
4497
4498 return 0;
4499}
4500
af7cc7d1
XG		 4501static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4502 gpa_t *gpa, struct x86_exception *exception,
4503 bool write)
4504{
97d64b78
AK		 4505 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4506 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4507
be94f6b7
HH		 4508 /*
4509 * currently PKRU is only applied to ept enabled guest so
4510 * there is no pkey in EPT page table for L1 guest or EPT
4511 * shadow page table for L2 guest.
4512 */
97d64b78 4513 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4514 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4515 vcpu->arch.access, 0, access)) {
bebb106a
XG		 4516 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4517 (gva & (PAGE_SIZE - 1));
4f022648 4518 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4519 return 1;
4520 }
4521
af7cc7d1
XG		 4522 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4523
4524 if (*gpa == UNMAPPED_GVA)
4525 return -1;
4526
0f89b207 4527 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 4528}
4529
3200f405 4530int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4531 const void *val, int bytes)
bbd9b64e
CO		 4532{
4533 int ret;
4534
54bf36aa 4535 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4536 if (ret < 0)
bbd9b64e 4537 return 0;
0eb05bf2 4538 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4539 return 1;
4540}
4541
77d197b2
XG		 4542struct read_write_emulator_ops {
4543 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4544 int bytes);
4545 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4546 void *val, int bytes);
4547 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4548 int bytes, void *val);
4549 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4550 void *val, int bytes);
4551 bool write;
4552};
4553
4554static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4555{
4556 if (vcpu->mmio_read_completed) {
77d197b2 4557 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4558 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4559 vcpu->mmio_read_completed = 0;
4560 return 1;
4561 }
4562
4563 return 0;
4564}
4565
4566static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4567 void *val, int bytes)
4568{
54bf36aa 4569 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4570}
4571
4572static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4573 void *val, int bytes)
4574{
4575 return emulator_write_phys(vcpu, gpa, val, bytes);
4576}
4577
4578static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4579{
4580 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4581 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4582}
4583
4584static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4585 void *val, int bytes)
4586{
4587 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4588 return X86EMUL_IO_NEEDED;
4589}
4590
4591static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4592 void *val, int bytes)
4593{
f78146b0
AK		 4594 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4595
87da7e66 4596 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4597 return X86EMUL_CONTINUE;
4598}
4599
0fbe9b0b 4600static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4601 .read_write_prepare = read_prepare,
4602 .read_write_emulate = read_emulate,
4603 .read_write_mmio = vcpu_mmio_read,
4604 .read_write_exit_mmio = read_exit_mmio,
4605};
4606
0fbe9b0b 4607static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4608 .read_write_emulate = write_emulate,
4609 .read_write_mmio = write_mmio,
4610 .read_write_exit_mmio = write_exit_mmio,
4611 .write = true,
4612};
4613
22388a3c
XG		 4614static int emulator_read_write_onepage(unsigned long addr, void *val,
4615 unsigned int bytes,
4616 struct x86_exception *exception,
4617 struct kvm_vcpu *vcpu,
0fbe9b0b 4618 const struct read_write_emulator_ops *ops)
bbd9b64e 4619{
af7cc7d1
XG		 4620 gpa_t gpa;
4621 int handled, ret;
22388a3c 4622 bool write = ops->write;
f78146b0 4623 struct kvm_mmio_fragment *frag;
0f89b207
TL		 4624 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4625
4626 /*
4627 * If the exit was due to a NPF we may already have a GPA.
4628 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4629 * Note, this cannot be used on string operations since string
4630 * operation using rep will only have the initial GPA from the NPF
4631 * occurred.
4632 */
4633 if (vcpu->arch.gpa_available &&
4634 emulator_can_use_gpa(ctxt) &&
4635 vcpu_is_mmio_gpa(vcpu, addr, exception->address, write) &&
4636 (addr & ~PAGE_MASK) == (exception->address & ~PAGE_MASK)) {
4637 gpa = exception->address;
4638 goto mmio;
4639 }
10589a46 4640
22388a3c 4641 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4642
af7cc7d1 4643 if (ret < 0)
bbd9b64e 4644 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4645
4646 /* For APIC access vmexit */
af7cc7d1 4647 if (ret)
bbd9b64e
CO		 4648 goto mmio;
4649
22388a3c 4650 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4651 return X86EMUL_CONTINUE;
4652
4653mmio:
4654 /*
4655 * Is this MMIO handled locally?
4656 */
22388a3c 4657 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4658 if (handled == bytes)
bbd9b64e 4659 return X86EMUL_CONTINUE;
bbd9b64e 4660
70252a10
AK		 4661 gpa += handled;
4662 bytes -= handled;
4663 val += handled;
4664
87da7e66
XG		 4665 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4666 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4667 frag->gpa = gpa;
4668 frag->data = val;
4669 frag->len = bytes;
f78146b0 4670 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4671}
4672
52eb5a6d
XL		 4673static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4674 unsigned long addr,
22388a3c
XG		 4675 void *val, unsigned int bytes,
4676 struct x86_exception *exception,
0fbe9b0b 4677 const struct read_write_emulator_ops *ops)
bbd9b64e 4678{
0f65dd70 4679 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4680 gpa_t gpa;
4681 int rc;
4682
4683 if (ops->read_write_prepare &&
4684 ops->read_write_prepare(vcpu, val, bytes))
4685 return X86EMUL_CONTINUE;
4686
4687 vcpu->mmio_nr_fragments = 0;
0f65dd70 4688
bbd9b64e
CO		 4689 /* Crossing a page boundary? */
4690 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4691 int now;
bbd9b64e
CO		 4692
4693 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4694 rc = emulator_read_write_onepage(addr, val, now, exception,
4695 vcpu, ops);
4696
bbd9b64e
CO		 4697 if (rc != X86EMUL_CONTINUE)
4698 return rc;
4699 addr += now;
bac15531
NA		 4700 if (ctxt->mode != X86EMUL_MODE_PROT64)
4701 addr = (u32)addr;
bbd9b64e
CO		 4702 val += now;
4703 bytes -= now;
4704 }
22388a3c 4705
f78146b0
AK		 4706 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4707 vcpu, ops);
4708 if (rc != X86EMUL_CONTINUE)
4709 return rc;
4710
4711 if (!vcpu->mmio_nr_fragments)
4712 return rc;
4713
4714 gpa = vcpu->mmio_fragments[0].gpa;
4715
4716 vcpu->mmio_needed = 1;
4717 vcpu->mmio_cur_fragment = 0;
4718
87da7e66 4719 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4720 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4721 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4722 vcpu->run->mmio.phys_addr = gpa;
4723
4724 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4725}
4726
4727static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4728 unsigned long addr,
4729 void *val,
4730 unsigned int bytes,
4731 struct x86_exception *exception)
4732{
4733 return emulator_read_write(ctxt, addr, val, bytes,
4734 exception, &read_emultor);
4735}
4736
52eb5a6d 4737static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4738 unsigned long addr,
4739 const void *val,
4740 unsigned int bytes,
4741 struct x86_exception *exception)
4742{
4743 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4744 exception, &write_emultor);
bbd9b64e 4745}
bbd9b64e 4746
daea3e73
AK		 4747#define CMPXCHG_TYPE(t, ptr, old, new) \
4748 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4749
4750#ifdef CONFIG_X86_64
4751# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4752#else
4753# define CMPXCHG64(ptr, old, new) \
9749a6c0 4754 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4755#endif
4756
0f65dd70
AK		 4757static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4758 unsigned long addr,
bbd9b64e
CO		 4759 const void *old,
4760 const void *new,
4761 unsigned int bytes,
0f65dd70 4762 struct x86_exception *exception)
bbd9b64e 4763{
0f65dd70 4764 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4765 gpa_t gpa;
4766 struct page *page;
4767 char *kaddr;
4768 bool exchanged;
2bacc55c 4769
daea3e73
AK		 4770 /* guests cmpxchg8b have to be emulated atomically */
4771 if (bytes > 8 || (bytes & (bytes - 1)))
4772 goto emul_write;
10589a46 4773
daea3e73 4774 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4775
daea3e73
AK		 4776 if (gpa == UNMAPPED_GVA ||
4777 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4778 goto emul_write;
2bacc55c 4779
daea3e73
AK		 4780 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4781 goto emul_write;
72dc67a6 4782
54bf36aa 4783 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4784 if (is_error_page(page))
c19b8bd6 4785 goto emul_write;
72dc67a6 4786
8fd75e12 4787 kaddr = kmap_atomic(page);
daea3e73
AK		 4788 kaddr += offset_in_page(gpa);
4789 switch (bytes) {
4790 case 1:
4791 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4792 break;
4793 case 2:
4794 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4795 break;
4796 case 4:
4797 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4798 break;
4799 case 8:
4800 exchanged = CMPXCHG64(kaddr, old, new);
4801 break;
4802 default:
4803 BUG();
2bacc55c 4804 }
8fd75e12 4805 kunmap_atomic(kaddr);
daea3e73
AK		 4806 kvm_release_page_dirty(page);
4807
4808 if (!exchanged)
4809 return X86EMUL_CMPXCHG_FAILED;
4810
54bf36aa 4811 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4812 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4813
4814 return X86EMUL_CONTINUE;
4a5f48f6 4815
3200f405 4816emul_write:
daea3e73 4817 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4818
0f65dd70 4819 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4820}
4821
cf8f70bf
GN		 4822static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4823{
4824 /* TODO: String I/O for in kernel device */
4825 int r;
4826
4827 if (vcpu->arch.pio.in)
e32edf4f 4828 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4829 vcpu->arch.pio.size, pd);
4830 else
e32edf4f 4831 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4832 vcpu->arch.pio.port, vcpu->arch.pio.size,
4833 pd);
4834 return r;
4835}
4836
6f6fbe98
XG		 4837static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4838 unsigned short port, void *val,
4839 unsigned int count, bool in)
cf8f70bf 4840{
cf8f70bf 4841 vcpu->arch.pio.port = port;
6f6fbe98 4842 vcpu->arch.pio.in = in;
7972995b 4843 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4844 vcpu->arch.pio.size = size;
4845
4846 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4847 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4848 return 1;
4849 }
4850
4851 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4852 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4853 vcpu->run->io.size = size;
4854 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4855 vcpu->run->io.count = count;
4856 vcpu->run->io.port = port;
4857
4858 return 0;
4859}
4860
6f6fbe98
XG		 4861static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4862 int size, unsigned short port, void *val,
4863 unsigned int count)
cf8f70bf 4864{
ca1d4a9e 4865 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4866 int ret;
ca1d4a9e 4867
6f6fbe98
XG		 4868 if (vcpu->arch.pio.count)
4869 goto data_avail;
cf8f70bf 4870
6f6fbe98
XG		 4871 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4872 if (ret) {
4873data_avail:
4874 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4875 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4876 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4877 return 1;
4878 }
4879
cf8f70bf
GN		 4880 return 0;
4881}
4882
6f6fbe98
XG		 4883static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4884 int size, unsigned short port,
4885 const void *val, unsigned int count)
4886{
4887 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4888
4889 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4890 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4891 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4892}
4893
bbd9b64e
CO		 4894static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4895{
4896 return kvm_x86_ops->get_segment_base(vcpu, seg);
4897}
4898
3cb16fe7 4899static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4900{
3cb16fe7 4901 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4902}
4903
ae6a2375 4904static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4905{
4906 if (!need_emulate_wbinvd(vcpu))
4907 return X86EMUL_CONTINUE;
4908
4909 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4910 int cpu = get_cpu();
4911
4912 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4913 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4914 wbinvd_ipi, NULL, 1);
2eec7343 4915 put_cpu();
f5f48ee1 4916 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4917 } else
4918 wbinvd();
f5f48ee1
SY		 4919 return X86EMUL_CONTINUE;
4920}
5cb56059
JS		 4921
4922int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4923{
6affcbed
KH		 4924 kvm_emulate_wbinvd_noskip(vcpu);
4925 return kvm_skip_emulated_instruction(vcpu);
5cb56059 4926}
f5f48ee1
SY		 4927EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4928
5cb56059
JS		 4929
4930
bcaf5cc5
AK		 4931static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4932{
5cb56059 4933 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4934}
4935
52eb5a6d
XL		 4936static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4937 unsigned long *dest)
bbd9b64e 4938{
16f8a6f9 4939 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4940}
4941
52eb5a6d
XL		 4942static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4943 unsigned long value)
bbd9b64e 4944{
338dbc97 4945
717746e3 4946 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4947}
4948
52a46617 4949static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4950{
52a46617 4951 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4952}
4953
717746e3 4954static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4955{
717746e3 4956 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4957 unsigned long value;
4958
4959 switch (cr) {
4960 case 0:
4961 value = kvm_read_cr0(vcpu);
4962 break;
4963 case 2:
4964 value = vcpu->arch.cr2;
4965 break;
4966 case 3:
9f8fe504 4967 value = kvm_read_cr3(vcpu);
52a46617
GN		 4968 break;
4969 case 4:
4970 value = kvm_read_cr4(vcpu);
4971 break;
4972 case 8:
4973 value = kvm_get_cr8(vcpu);
4974 break;
4975 default:
a737f256 4976 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4977 return 0;
4978 }
4979
4980 return value;
4981}
4982
717746e3 4983static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4984{
717746e3 4985 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4986 int res = 0;
4987
52a46617
GN		 4988 switch (cr) {
4989 case 0:
49a9b07e 4990 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4991 break;
4992 case 2:
4993 vcpu->arch.cr2 = val;
4994 break;
4995 case 3:
2390218b 4996 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4997 break;
4998 case 4:
a83b29c6 4999 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 5000 break;
5001 case 8:
eea1cff9 5002 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 5003 break;
5004 default:
a737f256 5005 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5006 res = -1;
52a46617 5007 }
0f12244f
GN		 5008
5009 return res;
52a46617
GN		 5010}
5011
717746e3 5012static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5013{
717746e3 5014 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 5015}
5016
4bff1e86 5017static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5018{
4bff1e86 5019 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 5020}
5021
4bff1e86 5022static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5023{
4bff1e86 5024 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 5025}
5026
1ac9d0cf
AK		 5027static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5028{
5029 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5030}
5031
5032static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5033{
5034 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5035}
5036
4bff1e86
AK		 5037static unsigned long emulator_get_cached_segment_base(
5038 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5039{
4bff1e86 5040 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 5041}
5042
1aa36616
AK		 5043static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5044 struct desc_struct *desc, u32 *base3,
5045 int seg)
2dafc6c2
GN		 5046{
5047 struct kvm_segment var;
5048
4bff1e86 5049 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5050 *selector = var.selector;
2dafc6c2 5051
378a8b09
GN		 5052 if (var.unusable) {
5053 memset(desc, 0, sizeof(*desc));
2dafc6c2 5054 return false;
378a8b09 5055 }
2dafc6c2
GN		 5056
5057 if (var.g)
5058 var.limit >>= 12;
5059 set_desc_limit(desc, var.limit);
5060 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 5061#ifdef CONFIG_X86_64
5062 if (base3)
5063 *base3 = var.base >> 32;
5064#endif
2dafc6c2
GN		 5065 desc->type = var.type;
5066 desc->s = var.s;
5067 desc->dpl = var.dpl;
5068 desc->p = var.present;
5069 desc->avl = var.avl;
5070 desc->l = var.l;
5071 desc->d = var.db;
5072 desc->g = var.g;
5073
5074 return true;
5075}
5076
1aa36616
AK		 5077static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5078 struct desc_struct *desc, u32 base3,
5079 int seg)
2dafc6c2 5080{
4bff1e86 5081 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 5082 struct kvm_segment var;
5083
1aa36616 5084 var.selector = selector;
2dafc6c2 5085 var.base = get_desc_base(desc);
5601d05b
GN		 5086#ifdef CONFIG_X86_64
5087 var.base |= ((u64)base3) << 32;
5088#endif
2dafc6c2
GN		 5089 var.limit = get_desc_limit(desc);
5090 if (desc->g)
5091 var.limit = (var.limit << 12) | 0xfff;
5092 var.type = desc->type;
2dafc6c2
GN		 5093 var.dpl = desc->dpl;
5094 var.db = desc->d;
5095 var.s = desc->s;
5096 var.l = desc->l;
5097 var.g = desc->g;
5098 var.avl = desc->avl;
5099 var.present = desc->p;
5100 var.unusable = !var.present;
5101 var.padding = 0;
5102
5103 kvm_set_segment(vcpu, &var, seg);
5104 return;
5105}
5106
717746e3
AK		 5107static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5108 u32 msr_index, u64 *pdata)
5109{
609e36d3
PB		 5110 struct msr_data msr;
5111 int r;
5112
5113 msr.index = msr_index;
5114 msr.host_initiated = false;
5115 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5116 if (r)
5117 return r;
5118
5119 *pdata = msr.data;
5120 return 0;
717746e3
AK		 5121}
5122
5123static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5124 u32 msr_index, u64 data)
5125{
8fe8ab46
WA		 5126 struct msr_data msr;
5127
5128 msr.data = data;
5129 msr.index = msr_index;
5130 msr.host_initiated = false;
5131 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 5132}
5133
64d60670
PB		 5134static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5135{
5136 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5137
5138 return vcpu->arch.smbase;
5139}
5140
5141static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5142{
5143 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5144
5145 vcpu->arch.smbase = smbase;
5146}
5147
67f4d428
NA		 5148static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5149 u32 pmc)
5150{
c6702c9d 5151 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 5152}
5153
222d21aa
AK		 5154static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5155 u32 pmc, u64 *pdata)
5156{
c6702c9d 5157 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 5158}
5159
6c3287f7
AK		 5160static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5161{
5162 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5163}
5164
5037f6f3
AK		 5165static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
5166{
5167 preempt_disable();
5197b808 5168 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 5169}
5170
5171static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
5172{
5173 preempt_enable();
5174}
5175
2953538e 5176static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5177 struct x86_instruction_info *info,
c4f035c6
AK		 5178 enum x86_intercept_stage stage)
5179{
2953538e 5180 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5181}
5182
0017f93a 5183static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5184 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5185{
0017f93a 5186 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5187}
5188
dd856efa
AK		 5189static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5190{
5191 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5192}
5193
5194static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5195{
5196 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5197}
5198
801806d9
NA		 5199static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5200{
5201 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5202}
5203
0225fb50 5204static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5205 .read_gpr = emulator_read_gpr,
5206 .write_gpr = emulator_write_gpr,
1871c602 5207 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5208 .write_std = kvm_write_guest_virt_system,
7a036a6f 5209 .read_phys = kvm_read_guest_phys_system,
1871c602 5210 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5211 .read_emulated = emulator_read_emulated,
5212 .write_emulated = emulator_write_emulated,
5213 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5214 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5215 .pio_in_emulated = emulator_pio_in_emulated,
5216 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5217 .get_segment = emulator_get_segment,
5218 .set_segment = emulator_set_segment,
5951c442 5219 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5220 .get_gdt = emulator_get_gdt,
160ce1f1 5221 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5222 .set_gdt = emulator_set_gdt,
5223 .set_idt = emulator_set_idt,
52a46617
GN		 5224 .get_cr = emulator_get_cr,
5225 .set_cr = emulator_set_cr,
9c537244 5226 .cpl = emulator_get_cpl,
35aa5375
GN		 5227 .get_dr = emulator_get_dr,
5228 .set_dr = emulator_set_dr,
64d60670
PB		 5229 .get_smbase = emulator_get_smbase,
5230 .set_smbase = emulator_set_smbase,
717746e3
AK		 5231 .set_msr = emulator_set_msr,
5232 .get_msr = emulator_get_msr,
67f4d428 5233 .check_pmc = emulator_check_pmc,
222d21aa 5234 .read_pmc = emulator_read_pmc,
6c3287f7 5235 .halt = emulator_halt,
bcaf5cc5 5236 .wbinvd = emulator_wbinvd,
d6aa1000 5237 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5238 .get_fpu = emulator_get_fpu,
5239 .put_fpu = emulator_put_fpu,
c4f035c6 5240 .intercept = emulator_intercept,
bdb42f5a 5241 .get_cpuid = emulator_get_cpuid,
801806d9 5242 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5243};
5244
95cb2295
GN		 5245static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5246{
37ccdcbe 5247 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5248 /*
5249 * an sti; sti; sequence only disable interrupts for the first
5250 * instruction. So, if the last instruction, be it emulated or
5251 * not, left the system with the INT_STI flag enabled, it
5252 * means that the last instruction is an sti. We should not
5253 * leave the flag on in this case. The same goes for mov ss
5254 */
37ccdcbe
PB		 5255 if (int_shadow & mask)
5256 mask = 0;
6addfc42 5257 if (unlikely(int_shadow || mask)) {
95cb2295 5258 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5259 if (!mask)
5260 kvm_make_request(KVM_REQ_EVENT, vcpu);
5261 }
95cb2295
GN		 5262}
5263
ef54bcfe 5264static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5265{
5266 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5267 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5268 return kvm_propagate_fault(vcpu, &ctxt->exception);
5269
5270 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5271 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5272 ctxt->exception.error_code);
54b8486f 5273 else
da9cb575 5274 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5275 return false;
54b8486f
GN		 5276}
5277
8ec4722d
MG		 5278static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5279{
adf52235 5280 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5281 int cs_db, cs_l;
5282
8ec4722d
MG		 5283 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5284
adf52235
TY		 5285 ctxt->eflags = kvm_get_rflags(vcpu);
5286 ctxt->eip = kvm_rip_read(vcpu);
5287 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5288 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5289 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5290 cs_db ? X86EMUL_MODE_PROT32 :
5291 X86EMUL_MODE_PROT16;
a584539b 5292 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5293 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5294 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5295 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5296
dd856efa 5297 init_decode_cache(ctxt);
7ae441ea 5298 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5299}
5300
71f9833b 5301int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5302{
9d74191a 5303 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5304 int ret;
5305
5306 init_emulate_ctxt(vcpu);
5307
9dac77fa
AK		 5308 ctxt->op_bytes = 2;
5309 ctxt->ad_bytes = 2;
5310 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5311 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5312
5313 if (ret != X86EMUL_CONTINUE)
5314 return EMULATE_FAIL;
5315
9dac77fa 5316 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5317 kvm_rip_write(vcpu, ctxt->eip);
5318 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5319
5320 if (irq == NMI_VECTOR)
7460fb4a 5321 vcpu->arch.nmi_pending = 0;
63995653
MG		 5322 else
5323 vcpu->arch.interrupt.pending = false;
5324
5325 return EMULATE_DONE;
5326}
5327EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5328
6d77dbfc
GN		 5329static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5330{
fc3a9157
JR		 5331 int r = EMULATE_DONE;
5332
6d77dbfc
GN		 5333 ++vcpu->stat.insn_emulation_fail;
5334 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5335 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5336 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5337 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5338 vcpu->run->internal.ndata = 0;
5339 r = EMULATE_FAIL;
5340 }
6d77dbfc 5341 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5342
5343 return r;
6d77dbfc
GN		 5344}
5345
93c05d3e 5346static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5347 bool write_fault_to_shadow_pgtable,
5348 int emulation_type)
a6f177ef 5349{
95b3cf69 5350 gpa_t gpa = cr2;
ba049e93 5351 kvm_pfn_t pfn;
a6f177ef 5352
991eebf9
GN		 5353 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5354 return false;
5355
95b3cf69
XG		 5356 if (!vcpu->arch.mmu.direct_map) {
5357 /*
5358 * Write permission should be allowed since only
5359 * write access need to be emulated.
5360 */
5361 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5362
95b3cf69
XG		 5363 /*
5364 * If the mapping is invalid in guest, let cpu retry
5365 * it to generate fault.
5366 */
5367 if (gpa == UNMAPPED_GVA)
5368 return true;
5369 }
a6f177ef 5370
8e3d9d06
XG		 5371 /*
5372 * Do not retry the unhandleable instruction if it faults on the
5373 * readonly host memory, otherwise it will goto a infinite loop:
5374 * retry instruction -> write #PF -> emulation fail -> retry
5375 * instruction -> ...
5376 */
5377 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5378
5379 /*
5380 * If the instruction failed on the error pfn, it can not be fixed,
5381 * report the error to userspace.
5382 */
5383 if (is_error_noslot_pfn(pfn))
5384 return false;
5385
5386 kvm_release_pfn_clean(pfn);
5387
5388 /* The instructions are well-emulated on direct mmu. */
5389 if (vcpu->arch.mmu.direct_map) {
5390 unsigned int indirect_shadow_pages;
5391
5392 spin_lock(&vcpu->kvm->mmu_lock);
5393 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5394 spin_unlock(&vcpu->kvm->mmu_lock);
5395
5396 if (indirect_shadow_pages)
5397 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5398
a6f177ef 5399 return true;
8e3d9d06 5400 }
a6f177ef 5401
95b3cf69
XG		 5402 /*
5403 * if emulation was due to access to shadowed page table
5404 * and it failed try to unshadow page and re-enter the
5405 * guest to let CPU execute the instruction.
5406 */
5407 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5408
5409 /*
5410 * If the access faults on its page table, it can not
5411 * be fixed by unprotecting shadow page and it should
5412 * be reported to userspace.
5413 */
5414 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5415}
5416
1cb3f3ae
XG		 5417static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5418 unsigned long cr2, int emulation_type)
5419{
5420 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5421 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5422
5423 last_retry_eip = vcpu->arch.last_retry_eip;
5424 last_retry_addr = vcpu->arch.last_retry_addr;
5425
5426 /*
5427 * If the emulation is caused by #PF and it is non-page_table
5428 * writing instruction, it means the VM-EXIT is caused by shadow
5429 * page protected, we can zap the shadow page and retry this
5430 * instruction directly.
5431 *
5432 * Note: if the guest uses a non-page-table modifying instruction
5433 * on the PDE that points to the instruction, then we will unmap
5434 * the instruction and go to an infinite loop. So, we cache the
5435 * last retried eip and the last fault address, if we meet the eip
5436 * and the address again, we can break out of the potential infinite
5437 * loop.
5438 */
5439 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5440
5441 if (!(emulation_type & EMULTYPE_RETRY))
5442 return false;
5443
5444 if (x86_page_table_writing_insn(ctxt))
5445 return false;
5446
5447 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5448 return false;
5449
5450 vcpu->arch.last_retry_eip = ctxt->eip;
5451 vcpu->arch.last_retry_addr = cr2;
5452
5453 if (!vcpu->arch.mmu.direct_map)
5454 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5455
22368028 5456 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5457
5458 return true;
5459}
5460
716d51ab
GN		 5461static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5462static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5463
64d60670 5464static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5465{
64d60670 5466 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5467 /* This is a good place to trace that we are exiting SMM. */
5468 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5469
c43203ca
PB		 5470 /* Process a latched INIT or SMI, if any. */
5471 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5472 }
699023e2
PB		 5473
5474 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5475}
5476
5477static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5478{
5479 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5480
a584539b 5481 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5482
5483 if (changed & HF_SMM_MASK)
5484 kvm_smm_changed(vcpu);
a584539b
PB		 5485}
5486
4a1e10d5
PB		 5487static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5488 unsigned long *db)
5489{
5490 u32 dr6 = 0;
5491 int i;
5492 u32 enable, rwlen;
5493
5494 enable = dr7;
5495 rwlen = dr7 >> 16;
5496 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5497 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5498 dr6 |= (1 << i);
5499 return dr6;
5500}
5501
6addfc42 5502static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5503{
5504 struct kvm_run *kvm_run = vcpu->run;
5505
5506 /*
6addfc42
PB		 5507 * rflags is the old, "raw" value of the flags. The new value has
5508 * not been saved yet.
663f4c61
PB		 5509 *
5510 * This is correct even for TF set by the guest, because "the
5511 * processor will not generate this exception after the instruction
5512 * that sets the TF flag".
5513 */
663f4c61
PB		 5514 if (unlikely(rflags & X86_EFLAGS_TF)) {
5515 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5516 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5517 DR6_RTM;
663f4c61
PB		 5518 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5519 kvm_run->debug.arch.exception = DB_VECTOR;
5520 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5521 *r = EMULATE_USER_EXIT;
5522 } else {
663f4c61
PB		 5523 /*
5524 * "Certain debug exceptions may clear bit 0-3. The
5525 * remaining contents of the DR6 register are never
5526 * cleared by the processor".
5527 */
5528 vcpu->arch.dr6 &= ~15;
6f43ed01 5529 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5530 kvm_queue_exception(vcpu, DB_VECTOR);
5531 }
5532 }
5533}
5534
6affcbed
KH		 5535int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5536{
5537 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5538 int r = EMULATE_DONE;
5539
5540 kvm_x86_ops->skip_emulated_instruction(vcpu);
5541 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
5542 return r == EMULATE_DONE;
5543}
5544EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5545
4a1e10d5
PB		 5546static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5547{
4a1e10d5
PB		 5548 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5549 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5550 struct kvm_run *kvm_run = vcpu->run;
5551 unsigned long eip = kvm_get_linear_rip(vcpu);
5552 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5553 vcpu->arch.guest_debug_dr7,
5554 vcpu->arch.eff_db);
5555
5556 if (dr6 != 0) {
6f43ed01 5557 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5558 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5559 kvm_run->debug.arch.exception = DB_VECTOR;
5560 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5561 *r = EMULATE_USER_EXIT;
5562 return true;
5563 }
5564 }
5565
4161a569
NA		 5566 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5567 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5568 unsigned long eip = kvm_get_linear_rip(vcpu);
5569 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5570 vcpu->arch.dr7,
5571 vcpu->arch.db);
5572
5573 if (dr6 != 0) {
5574 vcpu->arch.dr6 &= ~15;
6f43ed01 5575 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5576 kvm_queue_exception(vcpu, DB_VECTOR);
5577 *r = EMULATE_DONE;
5578 return true;
5579 }
5580 }
5581
5582 return false;
5583}
5584
51d8b661
AP		 5585int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5586 unsigned long cr2,
dc25e89e
AP		 5587 int emulation_type,
5588 void *insn,
5589 int insn_len)
bbd9b64e 5590{
95cb2295 5591 int r;
9d74191a 5592 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5593 bool writeback = true;
93c05d3e 5594 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5595
93c05d3e
XG		 5596 /*
5597 * Clear write_fault_to_shadow_pgtable here to ensure it is
5598 * never reused.
5599 */
5600 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5601 kvm_clear_exception_queue(vcpu);
8d7d8102 5602
571008da 5603 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5604 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5605
5606 /*
5607 * We will reenter on the same instruction since
5608 * we do not set complete_userspace_io. This does not
5609 * handle watchpoints yet, those would be handled in
5610 * the emulate_ops.
5611 */
5612 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5613 return r;
5614
9d74191a
TY		 5615 ctxt->interruptibility = 0;
5616 ctxt->have_exception = false;
e0ad0b47 5617 ctxt->exception.vector = -1;
9d74191a 5618 ctxt->perm_ok = false;
bbd9b64e 5619
b51e974f 5620 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5621
9d74191a 5622 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5623
e46479f8 5624 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5625 ++vcpu->stat.insn_emulation;
1d2887e2 5626 if (r != EMULATION_OK) {
4005996e
AK		 5627 if (emulation_type & EMULTYPE_TRAP_UD)
5628 return EMULATE_FAIL;
991eebf9
GN		 5629 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5630 emulation_type))
bbd9b64e 5631 return EMULATE_DONE;
6d77dbfc
GN		 5632 if (emulation_type & EMULTYPE_SKIP)
5633 return EMULATE_FAIL;
5634 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5635 }
5636 }
5637
ba8afb6b 5638 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5639 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5640 if (ctxt->eflags & X86_EFLAGS_RF)
5641 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5642 return EMULATE_DONE;
5643 }
5644
1cb3f3ae
XG		 5645 if (retry_instruction(ctxt, cr2, emulation_type))
5646 return EMULATE_DONE;
5647
7ae441ea 5648 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5649 changes registers values during IO operation */
7ae441ea
GN		 5650 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5651 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5652 emulator_invalidate_register_cache(ctxt);
7ae441ea 5653 }
4d2179e1 5654
5cd21917 5655restart:
0f89b207
TL		 5656 /* Save the faulting GPA (cr2) in the address field */
5657 ctxt->exception.address = cr2;
5658
9d74191a 5659 r = x86_emulate_insn(ctxt);
bbd9b64e 5660
775fde86
JR		 5661 if (r == EMULATION_INTERCEPTED)
5662 return EMULATE_DONE;
5663
d2ddd1c4 5664 if (r == EMULATION_FAILED) {
991eebf9
GN		 5665 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5666 emulation_type))
c3cd7ffa
GN		 5667 return EMULATE_DONE;
5668
6d77dbfc 5669 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5670 }
5671
9d74191a 5672 if (ctxt->have_exception) {
d2ddd1c4 5673 r = EMULATE_DONE;
ef54bcfe
PB		 5674 if (inject_emulated_exception(vcpu))
5675 return r;
d2ddd1c4 5676 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5677 if (!vcpu->arch.pio.in) {
5678 /* FIXME: return into emulator if single-stepping. */
3457e419 5679 vcpu->arch.pio.count = 0;
0912c977 5680 } else {
7ae441ea 5681 writeback = false;
716d51ab
GN		 5682 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5683 }
ac0a48c3 5684 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5685 } else if (vcpu->mmio_needed) {
5686 if (!vcpu->mmio_is_write)
5687 writeback = false;
ac0a48c3 5688 r = EMULATE_USER_EXIT;
716d51ab 5689 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5690 } else if (r == EMULATION_RESTART)
5cd21917 5691 goto restart;
d2ddd1c4
GN		 5692 else
5693 r = EMULATE_DONE;
f850e2e6 5694
7ae441ea 5695 if (writeback) {
6addfc42 5696 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5697 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5698 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5699 if (vcpu->arch.hflags != ctxt->emul_flags)
5700 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5701 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5702 if (r == EMULATE_DONE)
6addfc42 5703 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5704 if (!ctxt->have_exception ||
5705 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5706 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5707
5708 /*
5709 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5710 * do nothing, and it will be requested again as soon as
5711 * the shadow expires. But we still need to check here,
5712 * because POPF has no interrupt shadow.
5713 */
5714 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5715 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5716 } else
5717 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5718
5719 return r;
de7d789a 5720}
51d8b661 5721EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5722
cf8f70bf 5723int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5724{
cf8f70bf 5725 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5726 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5727 size, port, &val, 1);
cf8f70bf 5728 /* do not return to emulator after return from userspace */
7972995b 5729 vcpu->arch.pio.count = 0;
de7d789a
CO		 5730 return ret;
5731}
cf8f70bf 5732EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5733
8370c3d0
TL		 5734static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5735{
5736 unsigned long val;
5737
5738 /* We should only ever be called with arch.pio.count equal to 1 */
5739 BUG_ON(vcpu->arch.pio.count != 1);
5740
5741 /* For size less than 4 we merge, else we zero extend */
5742 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5743 : 0;
5744
5745 /*
5746 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5747 * the copy and tracing
5748 */
5749 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5750 vcpu->arch.pio.port, &val, 1);
5751 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5752
5753 return 1;
5754}
5755
5756int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5757{
5758 unsigned long val;
5759 int ret;
5760
5761 /* For size less than 4 we merge, else we zero extend */
5762 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5763
5764 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5765 &val, 1);
5766 if (ret) {
5767 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5768 return ret;
5769 }
5770
5771 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5772
5773 return 0;
5774}
5775EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5776
251a5fd6 5777static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5778{
0a3aee0d 5779 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5780 return 0;
8cfdc000
ZA		 5781}
5782
5783static void tsc_khz_changed(void *data)
c8076604 5784{
8cfdc000
ZA		 5785 struct cpufreq_freqs *freq = data;
5786 unsigned long khz = 0;
5787
5788 if (data)
5789 khz = freq->new;
5790 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5791 khz = cpufreq_quick_get(raw_smp_processor_id());
5792 if (!khz)
5793 khz = tsc_khz;
0a3aee0d 5794 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5795}
5796
c8076604
GH		 5797static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5798 void *data)
5799{
5800 struct cpufreq_freqs *freq = data;
5801 struct kvm *kvm;
5802 struct kvm_vcpu *vcpu;
5803 int i, send_ipi = 0;
5804
8cfdc000
ZA		 5805 /*
5806 * We allow guests to temporarily run on slowing clocks,
5807 * provided we notify them after, or to run on accelerating
5808 * clocks, provided we notify them before. Thus time never
5809 * goes backwards.
5810 *
5811 * However, we have a problem. We can't atomically update
5812 * the frequency of a given CPU from this function; it is
5813 * merely a notifier, which can be called from any CPU.
5814 * Changing the TSC frequency at arbitrary points in time
5815 * requires a recomputation of local variables related to
5816 * the TSC for each VCPU. We must flag these local variables
5817 * to be updated and be sure the update takes place with the
5818 * new frequency before any guests proceed.
5819 *
5820 * Unfortunately, the combination of hotplug CPU and frequency
5821 * change creates an intractable locking scenario; the order
5822 * of when these callouts happen is undefined with respect to
5823 * CPU hotplug, and they can race with each other. As such,
5824 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5825 * undefined; you can actually have a CPU frequency change take
5826 * place in between the computation of X and the setting of the
5827 * variable. To protect against this problem, all updates of
5828 * the per_cpu tsc_khz variable are done in an interrupt
5829 * protected IPI, and all callers wishing to update the value
5830 * must wait for a synchronous IPI to complete (which is trivial
5831 * if the caller is on the CPU already). This establishes the
5832 * necessary total order on variable updates.
5833 *
5834 * Note that because a guest time update may take place
5835 * anytime after the setting of the VCPU's request bit, the
5836 * correct TSC value must be set before the request. However,
5837 * to ensure the update actually makes it to any guest which
5838 * starts running in hardware virtualization between the set
5839 * and the acquisition of the spinlock, we must also ping the
5840 * CPU after setting the request bit.
5841 *
5842 */
5843
c8076604
GH		 5844 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5845 return 0;
5846 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5847 return 0;
8cfdc000
ZA		 5848
5849 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5850
2f303b74 5851 spin_lock(&kvm_lock);
c8076604 5852 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5853 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5854 if (vcpu->cpu != freq->cpu)
5855 continue;
c285545f 5856 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5857 if (vcpu->cpu != smp_processor_id())
8cfdc000 5858 send_ipi = 1;
c8076604
GH		 5859 }
5860 }
2f303b74 5861 spin_unlock(&kvm_lock);
c8076604
GH		 5862
5863 if (freq->old < freq->new && send_ipi) {
5864 /*
5865 * We upscale the frequency. Must make the guest
5866 * doesn't see old kvmclock values while running with
5867 * the new frequency, otherwise we risk the guest sees
5868 * time go backwards.
5869 *
5870 * In case we update the frequency for another cpu
5871 * (which might be in guest context) send an interrupt
5872 * to kick the cpu out of guest context. Next time
5873 * guest context is entered kvmclock will be updated,
5874 * so the guest will not see stale values.
5875 */
8cfdc000 5876 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5877 }
5878 return 0;
5879}
5880
5881static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5882 .notifier_call = kvmclock_cpufreq_notifier
5883};
5884
251a5fd6 5885static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 5886{
251a5fd6
SAS		 5887 tsc_khz_changed(NULL);
5888 return 0;
8cfdc000
ZA		 5889}
5890
b820cc0c
ZA		 5891static void kvm_timer_init(void)
5892{
c285545f 5893 max_tsc_khz = tsc_khz;
460dd42e 5894
b820cc0c 5895 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5896#ifdef CONFIG_CPU_FREQ
5897 struct cpufreq_policy policy;
758f588d
BP		 5898 int cpu;
5899
c285545f 5900 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5901 cpu = get_cpu();
5902 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5903 if (policy.cpuinfo.max_freq)
5904 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5905 put_cpu();
c285545f 5906#endif
b820cc0c
ZA		 5907 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5908 CPUFREQ_TRANSITION_NOTIFIER);
5909 }
c285545f 5910 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 5911
73c1b41e 5912 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 5913 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 5914}
5915
ff9d07a0
ZY		 5916static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5917
f5132b01 5918int kvm_is_in_guest(void)
ff9d07a0 5919{
086c9855 5920 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5921}
5922
5923static int kvm_is_user_mode(void)
5924{
5925 int user_mode = 3;
dcf46b94 5926
086c9855
AS		 5927 if (__this_cpu_read(current_vcpu))
5928 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5929
ff9d07a0
ZY		 5930 return user_mode != 0;
5931}
5932
5933static unsigned long kvm_get_guest_ip(void)
5934{
5935 unsigned long ip = 0;
dcf46b94 5936
086c9855
AS		 5937 if (__this_cpu_read(current_vcpu))
5938 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5939
ff9d07a0
ZY		 5940 return ip;
5941}
5942
5943static struct perf_guest_info_callbacks kvm_guest_cbs = {
5944 .is_in_guest = kvm_is_in_guest,
5945 .is_user_mode = kvm_is_user_mode,
5946 .get_guest_ip = kvm_get_guest_ip,
5947};
5948
5949void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5950{
086c9855 5951 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5952}
5953EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5954
5955void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5956{
086c9855 5957 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5958}
5959EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5960
ce88decf
XG		 5961static void kvm_set_mmio_spte_mask(void)
5962{
5963 u64 mask;
5964 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5965
5966 /*
5967 * Set the reserved bits and the present bit of an paging-structure
5968 * entry to generate page fault with PFER.RSV = 1.
5969 */
885032b9 5970 /* Mask the reserved physical address bits. */
d1431483 5971 mask = rsvd_bits(maxphyaddr, 51);
885032b9 5972
885032b9 5973 /* Set the present bit. */
ce88decf
XG		 5974 mask |= 1ull;
5975
5976#ifdef CONFIG_X86_64
5977 /*
5978 * If reserved bit is not supported, clear the present bit to disable
5979 * mmio page fault.
5980 */
5981 if (maxphyaddr == 52)
5982 mask &= ~1ull;
5983#endif
5984
5985 kvm_mmu_set_mmio_spte_mask(mask);
5986}
5987
16e8d74d
MT		 5988#ifdef CONFIG_X86_64
5989static void pvclock_gtod_update_fn(struct work_struct *work)
5990{
d828199e
MT		 5991 struct kvm *kvm;
5992
5993 struct kvm_vcpu *vcpu;
5994 int i;
5995
2f303b74 5996 spin_lock(&kvm_lock);
d828199e
MT		 5997 list_for_each_entry(kvm, &vm_list, vm_list)
5998 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5999 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6000 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6001 spin_unlock(&kvm_lock);
16e8d74d
MT		 6002}
6003
6004static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6005
6006/*
6007 * Notification about pvclock gtod data update.
6008 */
6009static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6010 void *priv)
6011{
6012 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6013 struct timekeeper *tk = priv;
6014
6015 update_pvclock_gtod(tk);
6016
6017 /* disable master clock if host does not trust, or does not
6018 * use, TSC clocksource
6019 */
6020 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6021 atomic_read(&kvm_guest_has_master_clock) != 0)
6022 queue_work(system_long_wq, &pvclock_gtod_work);
6023
6024 return 0;
6025}
6026
6027static struct notifier_block pvclock_gtod_notifier = {
6028 .notifier_call = pvclock_gtod_notify,
6029};
6030#endif
6031
f8c16bba 6032int kvm_arch_init(void *opaque)
043405e1 6033{
b820cc0c 6034 int r;
6b61edf7 6035 struct kvm_x86_ops *ops = opaque;
f8c16bba 6036
f8c16bba
ZX		 6037 if (kvm_x86_ops) {
6038 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 6039 r = -EEXIST;
6040 goto out;
f8c16bba
ZX		 6041 }
6042
6043 if (!ops->cpu_has_kvm_support()) {
6044 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 6045 r = -EOPNOTSUPP;
6046 goto out;
f8c16bba
ZX		 6047 }
6048 if (ops->disabled_by_bios()) {
6049 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 6050 r = -EOPNOTSUPP;
6051 goto out;
f8c16bba
ZX		 6052 }
6053
013f6a5d
MT		 6054 r = -ENOMEM;
6055 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6056 if (!shared_msrs) {
6057 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6058 goto out;
6059 }
6060
97db56ce
AK		 6061 r = kvm_mmu_module_init();
6062 if (r)
013f6a5d 6063 goto out_free_percpu;
97db56ce 6064
ce88decf 6065 kvm_set_mmio_spte_mask();
97db56ce 6066
f8c16bba 6067 kvm_x86_ops = ops;
920c8377 6068
7b52345e 6069 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6070 PT_DIRTY_MASK, PT64_NX_MASK, 0,
f160c7b7 6071 PT_PRESENT_MASK, 0);
b820cc0c 6072 kvm_timer_init();
c8076604 6073
ff9d07a0
ZY		 6074 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6075
d366bf7e 6076 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 6077 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6078
c5cc421b 6079 kvm_lapic_init();
16e8d74d
MT		 6080#ifdef CONFIG_X86_64
6081 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6082#endif
6083
f8c16bba 6084 return 0;
56c6d28a 6085
013f6a5d
MT		 6086out_free_percpu:
6087 free_percpu(shared_msrs);
56c6d28a 6088out:
56c6d28a 6089 return r;
043405e1 6090}
8776e519 6091
f8c16bba
ZX		 6092void kvm_arch_exit(void)
6093{
cef84c30 6094 kvm_lapic_exit();
ff9d07a0
ZY		 6095 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6096
888d256e
JK		 6097 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6098 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6099 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6100 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 6101#ifdef CONFIG_X86_64
6102 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6103#endif
f8c16bba 6104 kvm_x86_ops = NULL;
56c6d28a 6105 kvm_mmu_module_exit();
013f6a5d 6106 free_percpu(shared_msrs);
56c6d28a 6107}
f8c16bba 6108
5cb56059 6109int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 6110{
6111 ++vcpu->stat.halt_exits;
35754c98 6112 if (lapic_in_kernel(vcpu)) {
a4535290 6113 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 6114 return 1;
6115 } else {
6116 vcpu->run->exit_reason = KVM_EXIT_HLT;
6117 return 0;
6118 }
6119}
5cb56059
JS		 6120EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6121
6122int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6123{
6affcbed
KH		 6124 int ret = kvm_skip_emulated_instruction(vcpu);
6125 /*
6126 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6127 * KVM_EXIT_DEBUG here.
6128 */
6129 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6130}
8776e519
HB		 6131EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6132
8ef81a9a 6133#ifdef CONFIG_X86_64
55dd00a7
MT		 6134static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6135 unsigned long clock_type)
6136{
6137 struct kvm_clock_pairing clock_pairing;
6138 struct timespec ts;
80fbd89c 6139 u64 cycle;
55dd00a7
MT		 6140 int ret;
6141
6142 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6143 return -KVM_EOPNOTSUPP;
6144
6145 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6146 return -KVM_EOPNOTSUPP;
6147
6148 clock_pairing.sec = ts.tv_sec;
6149 clock_pairing.nsec = ts.tv_nsec;
6150 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6151 clock_pairing.flags = 0;
6152
6153 ret = 0;
6154 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6155 sizeof(struct kvm_clock_pairing)))
6156 ret = -KVM_EFAULT;
6157
6158 return ret;
6159}
8ef81a9a 6160#endif
55dd00a7 6161
6aef266c
SV		 6162/*
6163 * kvm_pv_kick_cpu_op: Kick a vcpu.
6164 *
6165 * @apicid - apicid of vcpu to be kicked.
6166 */
6167static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6168{
24d2166b 6169 struct kvm_lapic_irq lapic_irq;
6aef266c 6170
24d2166b
R		 6171 lapic_irq.shorthand = 0;
6172 lapic_irq.dest_mode = 0;
6173 lapic_irq.dest_id = apicid;
93bbf0b8 6174 lapic_irq.msi_redir_hint = false;
6aef266c 6175
24d2166b 6176 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6177 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 6178}
6179
d62caabb
AS		 6180void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6181{
6182 vcpu->arch.apicv_active = false;
6183 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6184}
6185
8776e519
HB		 6186int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6187{
6188 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6189 int op_64_bit, r;
8776e519 6190
6affcbed 6191 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6192
55cd8e5a
GN		 6193 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6194 return kvm_hv_hypercall(vcpu);
6195
5fdbf976
MT		 6196 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6197 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6198 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6199 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6200 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6201
229456fc 6202 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6203
a449c7aa
NA		 6204 op_64_bit = is_64_bit_mode(vcpu);
6205 if (!op_64_bit) {
8776e519
HB		 6206 nr &= 0xFFFFFFFF;
6207 a0 &= 0xFFFFFFFF;
6208 a1 &= 0xFFFFFFFF;
6209 a2 &= 0xFFFFFFFF;
6210 a3 &= 0xFFFFFFFF;
6211 }
6212
07708c4a
JK		 6213 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6214 ret = -KVM_EPERM;
6215 goto out;
6216 }
6217
8776e519 6218 switch (nr) {
b93463aa
AK		 6219 case KVM_HC_VAPIC_POLL_IRQ:
6220 ret = 0;
6221 break;
6aef266c
SV		 6222 case KVM_HC_KICK_CPU:
6223 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6224 ret = 0;
6225 break;
8ef81a9a 6226#ifdef CONFIG_X86_64
55dd00a7
MT		 6227 case KVM_HC_CLOCK_PAIRING:
6228 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6229 break;
8ef81a9a 6230#endif
8776e519
HB		 6231 default:
6232 ret = -KVM_ENOSYS;
6233 break;
6234 }
07708c4a 6235out:
a449c7aa
NA		 6236 if (!op_64_bit)
6237 ret = (u32)ret;
5fdbf976 6238 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6239 ++vcpu->stat.hypercalls;
2f333bcb 6240 return r;
8776e519
HB		 6241}
6242EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6243
b6785def 6244static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6245{
d6aa1000 6246 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6247 char instruction[3];
5fdbf976 6248 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6249
8776e519 6250 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6251
ce2e852e
DV		 6252 return emulator_write_emulated(ctxt, rip, instruction, 3,
6253 &ctxt->exception);
8776e519
HB		 6254}
6255
851ba692 6256static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6257{
782d422b
MG		 6258 return vcpu->run->request_interrupt_window &&
6259 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 6260}
6261
851ba692 6262static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6263{
851ba692
AK		 6264 struct kvm_run *kvm_run = vcpu->run;
6265
91586a3b 6266 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6267 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6268 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6269 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 6270 kvm_run->ready_for_interrupt_injection =
6271 pic_in_kernel(vcpu->kvm) ||
782d422b 6272 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 6273}
6274
95ba8273
GN		 6275static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6276{
6277 int max_irr, tpr;
6278
6279 if (!kvm_x86_ops->update_cr8_intercept)
6280 return;
6281
bce87cce 6282 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 6283 return;
6284
d62caabb
AS		 6285 if (vcpu->arch.apicv_active)
6286 return;
6287
8db3baa2
GN		 6288 if (!vcpu->arch.apic->vapic_addr)
6289 max_irr = kvm_lapic_find_highest_irr(vcpu);
6290 else
6291 max_irr = -1;
95ba8273
GN		 6292
6293 if (max_irr != -1)
6294 max_irr >>= 4;
6295
6296 tpr = kvm_lapic_get_cr8(vcpu);
6297
6298 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6299}
6300
b6b8a145 6301static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6302{
b6b8a145
JK		 6303 int r;
6304
95ba8273 6305 /* try to reinject previous events if any */
b59bb7bd 6306 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6307 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6308 vcpu->arch.exception.has_error_code,
6309 vcpu->arch.exception.error_code);
d6e8c854
NA		 6310
6311 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6312 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6313 X86_EFLAGS_RF);
6314
6bdf0662
NA		 6315 if (vcpu->arch.exception.nr == DB_VECTOR &&
6316 (vcpu->arch.dr7 & DR7_GD)) {
6317 vcpu->arch.dr7 &= ~DR7_GD;
6318 kvm_update_dr7(vcpu);
6319 }
6320
b59bb7bd
GN		 6321 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6322 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6323 vcpu->arch.exception.error_code,
6324 vcpu->arch.exception.reinject);
b6b8a145 6325 return 0;
b59bb7bd
GN		 6326 }
6327
95ba8273
GN		 6328 if (vcpu->arch.nmi_injected) {
6329 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6330 return 0;
95ba8273
GN		 6331 }
6332
6333 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6334 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6335 return 0;
6336 }
6337
6338 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6339 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6340 if (r != 0)
6341 return r;
95ba8273
GN		 6342 }
6343
6344 /* try to inject new event if pending */
c43203ca
PB		 6345 if (vcpu->arch.smi_pending && !is_smm(vcpu)) {
6346 vcpu->arch.smi_pending = false;
ee2cd4b7 6347 enter_smm(vcpu);
c43203ca 6348 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 6349 --vcpu->arch.nmi_pending;
6350 vcpu->arch.nmi_injected = true;
6351 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6352 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6353 /*
6354 * Because interrupts can be injected asynchronously, we are
6355 * calling check_nested_events again here to avoid a race condition.
6356 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6357 * proposal and current concerns. Perhaps we should be setting
6358 * KVM_REQ_EVENT only on certain events and not unconditionally?
6359 */
6360 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6361 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6362 if (r != 0)
6363 return r;
6364 }
95ba8273 6365 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6366 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6367 false);
6368 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6369 }
6370 }
ee2cd4b7 6371
b6b8a145 6372 return 0;
95ba8273
GN		 6373}
6374
7460fb4a
AK		 6375static void process_nmi(struct kvm_vcpu *vcpu)
6376{
6377 unsigned limit = 2;
6378
6379 /*
6380 * x86 is limited to one NMI running, and one NMI pending after it.
6381 * If an NMI is already in progress, limit further NMIs to just one.
6382 * Otherwise, allow two (and we'll inject the first one immediately).
6383 */
6384 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6385 limit = 1;
6386
6387 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6388 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6389 kvm_make_request(KVM_REQ_EVENT, vcpu);
6390}
6391
660a5d51
PB		 6392#define put_smstate(type, buf, offset, val) \
6393 *(type *)((buf) + (offset) - 0x7e00) = val
6394
ee2cd4b7 6395static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 6396{
6397 u32 flags = 0;
6398 flags |= seg->g << 23;
6399 flags |= seg->db << 22;
6400 flags |= seg->l << 21;
6401 flags |= seg->avl << 20;
6402 flags |= seg->present << 15;
6403 flags |= seg->dpl << 13;
6404 flags |= seg->s << 12;
6405 flags |= seg->type << 8;
6406 return flags;
6407}
6408
ee2cd4b7 6409static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6410{
6411 struct kvm_segment seg;
6412 int offset;
6413
6414 kvm_get_segment(vcpu, &seg, n);
6415 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6416
6417 if (n < 3)
6418 offset = 0x7f84 + n * 12;
6419 else
6420 offset = 0x7f2c + (n - 3) * 12;
6421
6422 put_smstate(u32, buf, offset + 8, seg.base);
6423 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6424 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6425}
6426
efbb288a 6427#ifdef CONFIG_X86_64
ee2cd4b7 6428static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 6429{
6430 struct kvm_segment seg;
6431 int offset;
6432 u16 flags;
6433
6434 kvm_get_segment(vcpu, &seg, n);
6435 offset = 0x7e00 + n * 16;
6436
ee2cd4b7 6437 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 6438 put_smstate(u16, buf, offset, seg.selector);
6439 put_smstate(u16, buf, offset + 2, flags);
6440 put_smstate(u32, buf, offset + 4, seg.limit);
6441 put_smstate(u64, buf, offset + 8, seg.base);
6442}
efbb288a 6443#endif
660a5d51 6444
ee2cd4b7 6445static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6446{
6447 struct desc_ptr dt;
6448 struct kvm_segment seg;
6449 unsigned long val;
6450 int i;
6451
6452 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6453 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6454 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6455 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6456
6457 for (i = 0; i < 8; i++)
6458 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6459
6460 kvm_get_dr(vcpu, 6, &val);
6461 put_smstate(u32, buf, 0x7fcc, (u32)val);
6462 kvm_get_dr(vcpu, 7, &val);
6463 put_smstate(u32, buf, 0x7fc8, (u32)val);
6464
6465 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6466 put_smstate(u32, buf, 0x7fc4, seg.selector);
6467 put_smstate(u32, buf, 0x7f64, seg.base);
6468 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6469 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6470
6471 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6472 put_smstate(u32, buf, 0x7fc0, seg.selector);
6473 put_smstate(u32, buf, 0x7f80, seg.base);
6474 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6475 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 6476
6477 kvm_x86_ops->get_gdt(vcpu, &dt);
6478 put_smstate(u32, buf, 0x7f74, dt.address);
6479 put_smstate(u32, buf, 0x7f70, dt.size);
6480
6481 kvm_x86_ops->get_idt(vcpu, &dt);
6482 put_smstate(u32, buf, 0x7f58, dt.address);
6483 put_smstate(u32, buf, 0x7f54, dt.size);
6484
6485 for (i = 0; i < 6; i++)
ee2cd4b7 6486 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 6487
6488 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6489
6490 /* revision id */
6491 put_smstate(u32, buf, 0x7efc, 0x00020000);
6492 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6493}
6494
ee2cd4b7 6495static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 6496{
6497#ifdef CONFIG_X86_64
6498 struct desc_ptr dt;
6499 struct kvm_segment seg;
6500 unsigned long val;
6501 int i;
6502
6503 for (i = 0; i < 16; i++)
6504 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6505
6506 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6507 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6508
6509 kvm_get_dr(vcpu, 6, &val);
6510 put_smstate(u64, buf, 0x7f68, val);
6511 kvm_get_dr(vcpu, 7, &val);
6512 put_smstate(u64, buf, 0x7f60, val);
6513
6514 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6515 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6516 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6517
6518 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6519
6520 /* revision id */
6521 put_smstate(u32, buf, 0x7efc, 0x00020064);
6522
6523 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6524
6525 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6526 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6527 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6528 put_smstate(u32, buf, 0x7e94, seg.limit);
6529 put_smstate(u64, buf, 0x7e98, seg.base);
6530
6531 kvm_x86_ops->get_idt(vcpu, &dt);
6532 put_smstate(u32, buf, 0x7e84, dt.size);
6533 put_smstate(u64, buf, 0x7e88, dt.address);
6534
6535 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6536 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6537 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 6538 put_smstate(u32, buf, 0x7e74, seg.limit);
6539 put_smstate(u64, buf, 0x7e78, seg.base);
6540
6541 kvm_x86_ops->get_gdt(vcpu, &dt);
6542 put_smstate(u32, buf, 0x7e64, dt.size);
6543 put_smstate(u64, buf, 0x7e68, dt.address);
6544
6545 for (i = 0; i < 6; i++)
ee2cd4b7 6546 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB		 6547#else
6548 WARN_ON_ONCE(1);
6549#endif
6550}
6551
ee2cd4b7 6552static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6553{
660a5d51 6554 struct kvm_segment cs, ds;
18c3626e 6555 struct desc_ptr dt;
660a5d51
PB		 6556 char buf[512];
6557 u32 cr0;
6558
660a5d51
PB		 6559 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6560 vcpu->arch.hflags |= HF_SMM_MASK;
6561 memset(buf, 0, 512);
6562 if (guest_cpuid_has_longmode(vcpu))
ee2cd4b7 6563 enter_smm_save_state_64(vcpu, buf);
660a5d51 6564 else
ee2cd4b7 6565 enter_smm_save_state_32(vcpu, buf);
660a5d51 6566
54bf36aa 6567 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6568
6569 if (kvm_x86_ops->get_nmi_mask(vcpu))
6570 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6571 else
6572 kvm_x86_ops->set_nmi_mask(vcpu, true);
6573
6574 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6575 kvm_rip_write(vcpu, 0x8000);
6576
6577 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6578 kvm_x86_ops->set_cr0(vcpu, cr0);
6579 vcpu->arch.cr0 = cr0;
6580
6581 kvm_x86_ops->set_cr4(vcpu, 0);
6582
18c3626e
PB		 6583 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6584 dt.address = dt.size = 0;
6585 kvm_x86_ops->set_idt(vcpu, &dt);
6586
660a5d51
PB		 6587 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6588
6589 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6590 cs.base = vcpu->arch.smbase;
6591
6592 ds.selector = 0;
6593 ds.base = 0;
6594
6595 cs.limit = ds.limit = 0xffffffff;
6596 cs.type = ds.type = 0x3;
6597 cs.dpl = ds.dpl = 0;
6598 cs.db = ds.db = 0;
6599 cs.s = ds.s = 1;
6600 cs.l = ds.l = 0;
6601 cs.g = ds.g = 1;
6602 cs.avl = ds.avl = 0;
6603 cs.present = ds.present = 1;
6604 cs.unusable = ds.unusable = 0;
6605 cs.padding = ds.padding = 0;
6606
6607 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6608 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6609 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6610 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6611 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6612 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6613
6614 if (guest_cpuid_has_longmode(vcpu))
6615 kvm_x86_ops->set_efer(vcpu, 0);
6616
6617 kvm_update_cpuid(vcpu);
6618 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6619}
6620
ee2cd4b7 6621static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 6622{
6623 vcpu->arch.smi_pending = true;
6624 kvm_make_request(KVM_REQ_EVENT, vcpu);
6625}
6626
2860c4b1
PB		 6627void kvm_make_scan_ioapic_request(struct kvm *kvm)
6628{
6629 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6630}
6631
3d81bc7e 6632static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6633{
5c919412
AS		 6634 u64 eoi_exit_bitmap[4];
6635
3d81bc7e
YZ		 6636 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6637 return;
c7c9c56c 6638
6308630b 6639 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6640
b053b2ae 6641 if (irqchip_split(vcpu->kvm))
6308630b 6642 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6643 else {
76dfafd5 6644 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6645 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6646 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6647 }
5c919412
AS		 6648 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6649 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6650 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 6651}
6652
a70656b6
RK		 6653static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6654{
6655 ++vcpu->stat.tlb_flush;
6656 kvm_x86_ops->tlb_flush(vcpu);
6657}
6658
4256f43f
TC		 6659void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6660{
c24ae0dc
TC		 6661 struct page *page = NULL;
6662
35754c98 6663 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 6664 return;
6665
4256f43f
TC		 6666 if (!kvm_x86_ops->set_apic_access_page_addr)
6667 return;
6668
c24ae0dc 6669 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6670 if (is_error_page(page))
6671 return;
c24ae0dc
TC		 6672 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6673
6674 /*
6675 * Do not pin apic access page in memory, the MMU notifier
6676 * will call us again if it is migrated or swapped out.
6677 */
6678 put_page(page);
4256f43f
TC		 6679}
6680EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6681
fe71557a
TC		 6682void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6683 unsigned long address)
6684{
c24ae0dc
TC		 6685 /*
6686 * The physical address of apic access page is stored in the VMCS.
6687 * Update it when it becomes invalid.
6688 */
6689 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6690 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6691}
6692
9357d939 6693/*
362c698f 6694 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6695 * exiting to the userspace. Otherwise, the value will be returned to the
6696 * userspace.
6697 */
851ba692 6698static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6699{
6700 int r;
62a193ed
MG		 6701 bool req_int_win =
6702 dm_request_for_irq_injection(vcpu) &&
6703 kvm_cpu_accept_dm_intr(vcpu);
6704
730dca42 6705 bool req_immediate_exit = false;
b6c7a5dc 6706
3e007509 6707 if (vcpu->requests) {
a8eeb04a 6708 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6709 kvm_mmu_unload(vcpu);
a8eeb04a 6710 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6711 __kvm_migrate_timers(vcpu);
d828199e
MT		 6712 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6713 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6714 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6715 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6716 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6717 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6718 if (unlikely(r))
6719 goto out;
6720 }
a8eeb04a 6721 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6722 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6723 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6724 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6725 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6726 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6727 r = 0;
6728 goto out;
6729 }
a8eeb04a 6730 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6731 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6732 r = 0;
6733 goto out;
6734 }
af585b92
GN		 6735 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6736 /* Page is swapped out. Do synthetic halt */
6737 vcpu->arch.apf.halted = true;
6738 r = 1;
6739 goto out;
6740 }
c9aaa895
GC		 6741 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6742 record_steal_time(vcpu);
64d60670
PB		 6743 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6744 process_smi(vcpu);
7460fb4a
AK		 6745 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6746 process_nmi(vcpu);
f5132b01 6747 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6748 kvm_pmu_handle_event(vcpu);
f5132b01 6749 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6750 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 6751 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6752 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6753 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6754 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 6755 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6756 vcpu->run->eoi.vector =
6757 vcpu->arch.pending_ioapic_eoi;
6758 r = 0;
6759 goto out;
6760 }
6761 }
3d81bc7e
YZ		 6762 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6763 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6764 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6765 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 6766 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6767 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6768 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6769 r = 0;
6770 goto out;
6771 }
e516cebb
AS		 6772 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6773 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6774 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6775 r = 0;
6776 goto out;
6777 }
db397571
AS		 6778 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6779 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6780 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6781 r = 0;
6782 goto out;
6783 }
f3b138c5
AS		 6784
6785 /*
6786 * KVM_REQ_HV_STIMER has to be processed after
6787 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6788 * depend on the guest clock being up-to-date
6789 */
1f4b34f8
AS		 6790 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6791 kvm_hv_process_stimers(vcpu);
2f52d58c 6792 }
b93463aa 6793
b463a6f7 6794 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 6795 ++vcpu->stat.req_event;
66450a21
JK		 6796 kvm_apic_accept_events(vcpu);
6797 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6798 r = 1;
6799 goto out;
6800 }
6801
b6b8a145
JK		 6802 if (inject_pending_event(vcpu, req_int_win) != 0)
6803 req_immediate_exit = true;
321c5658 6804 else {
c43203ca
PB		 6805 /* Enable NMI/IRQ window open exits if needed.
6806 *
6807 * SMIs have two cases: 1) they can be nested, and
6808 * then there is nothing to do here because RSM will
6809 * cause a vmexit anyway; 2) or the SMI can be pending
6810 * because inject_pending_event has completed the
6811 * injection of an IRQ or NMI from the previous vmexit,
6812 * and then we request an immediate exit to inject the SMI.
6813 */
6814 if (vcpu->arch.smi_pending && !is_smm(vcpu))
6815 req_immediate_exit = true;
321c5658
YS		 6816 if (vcpu->arch.nmi_pending)
6817 kvm_x86_ops->enable_nmi_window(vcpu);
6818 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
6819 kvm_x86_ops->enable_irq_window(vcpu);
6820 }
b463a6f7
AK		 6821
6822 if (kvm_lapic_enabled(vcpu)) {
6823 update_cr8_intercept(vcpu);
6824 kvm_lapic_sync_to_vapic(vcpu);
6825 }
6826 }
6827
d8368af8
AK		 6828 r = kvm_mmu_reload(vcpu);
6829 if (unlikely(r)) {
d905c069 6830 goto cancel_injection;
d8368af8
AK		 6831 }
6832
b6c7a5dc
HB		 6833 preempt_disable();
6834
6835 kvm_x86_ops->prepare_guest_switch(vcpu);
bd7e5b08 6836 kvm_load_guest_fpu(vcpu);
b95234c8
PB		 6837
6838 /*
6839 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
6840 * IPI are then delayed after guest entry, which ensures that they
6841 * result in virtual interrupt delivery.
6842 */
6843 local_irq_disable();
6b7e2d09
XG		 6844 vcpu->mode = IN_GUEST_MODE;
6845
01b71917
MT		 6846 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6847
0f127d12 6848 /*
b95234c8
PB		 6849 * 1) We should set ->mode before checking ->requests. Please see
6850 * the comment in kvm_make_all_cpus_request.
6851 *
6852 * 2) For APICv, we should set ->mode before checking PIR.ON. This
6853 * pairs with the memory barrier implicit in pi_test_and_set_on
6854 * (see vmx_deliver_posted_interrupt).
6855 *
6856 * 3) This also orders the write to mode from any reads to the page
6857 * tables done while the VCPU is running. Please see the comment
6858 * in kvm_flush_remote_tlbs.
6b7e2d09 6859 */
01b71917 6860 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6861
b95234c8
PB		 6862 /*
6863 * This handles the case where a posted interrupt was
6864 * notified with kvm_vcpu_kick.
6865 */
6866 if (kvm_lapic_enabled(vcpu)) {
6867 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
6868 kvm_x86_ops->sync_pir_to_irr(vcpu);
6869 }
32f88400 6870
6b7e2d09 6871 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6872 || need_resched() || signal_pending(current)) {
6b7e2d09 6873 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6874 smp_wmb();
6c142801
AK		 6875 local_irq_enable();
6876 preempt_enable();
01b71917 6877 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6878 r = 1;
d905c069 6879 goto cancel_injection;
6c142801
AK		 6880 }
6881
fc5b7f3b
DM		 6882 kvm_load_guest_xcr0(vcpu);
6883
c43203ca
PB		 6884 if (req_immediate_exit) {
6885 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 6886 smp_send_reschedule(vcpu->cpu);
c43203ca 6887 }
d6185f20 6888
8b89fe1f
PB		 6889 trace_kvm_entry(vcpu->vcpu_id);
6890 wait_lapic_expire(vcpu);
6edaa530 6891 guest_enter_irqoff();
b6c7a5dc 6892
42dbaa5a 6893 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6894 set_debugreg(0, 7);
6895 set_debugreg(vcpu->arch.eff_db[0], 0);
6896 set_debugreg(vcpu->arch.eff_db[1], 1);
6897 set_debugreg(vcpu->arch.eff_db[2], 2);
6898 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6899 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6900 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6901 }
b6c7a5dc 6902
851ba692 6903 kvm_x86_ops->run(vcpu);
b6c7a5dc 6904
c77fb5fe
PB		 6905 /*
6906 * Do this here before restoring debug registers on the host. And
6907 * since we do this before handling the vmexit, a DR access vmexit
6908 * can (a) read the correct value of the debug registers, (b) set
6909 * KVM_DEBUGREG_WONT_EXIT again.
6910 */
6911 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 6912 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6913 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 6914 kvm_update_dr0123(vcpu);
6915 kvm_update_dr6(vcpu);
6916 kvm_update_dr7(vcpu);
6917 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 6918 }
6919
24f1e32c
FW		 6920 /*
6921 * If the guest has used debug registers, at least dr7
6922 * will be disabled while returning to the host.
6923 * If we don't have active breakpoints in the host, we don't
6924 * care about the messed up debug address registers. But if
6925 * we have some of them active, restore the old state.
6926 */
59d8eb53 6927 if (hw_breakpoint_active())
24f1e32c 6928 hw_breakpoint_restore();
42dbaa5a 6929
4ba76538 6930 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 6931
6b7e2d09 6932 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6933 smp_wmb();
a547c6db 6934
fc5b7f3b
DM		 6935 kvm_put_guest_xcr0(vcpu);
6936
a547c6db 6937 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6938
6939 ++vcpu->stat.exits;
6940
f2485b3e 6941 guest_exit_irqoff();
b6c7a5dc 6942
f2485b3e 6943 local_irq_enable();
b6c7a5dc
HB		 6944 preempt_enable();
6945
f656ce01 6946 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6947
b6c7a5dc
HB		 6948 /*
6949 * Profile KVM exit RIPs:
6950 */
6951 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6952 unsigned long rip = kvm_rip_read(vcpu);
6953 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6954 }
6955
cc578287
ZA		 6956 if (unlikely(vcpu->arch.tsc_always_catchup))
6957 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6958
5cfb1d5a
MT		 6959 if (vcpu->arch.apic_attention)
6960 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6961
851ba692 6962 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6963 return r;
6964
6965cancel_injection:
6966 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6967 if (unlikely(vcpu->arch.apic_attention))
6968 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6969out:
6970 return r;
6971}
b6c7a5dc 6972
362c698f
PB		 6973static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6974{
bf9f6ac8
FW		 6975 if (!kvm_arch_vcpu_runnable(vcpu) &&
6976 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 6977 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6978 kvm_vcpu_block(vcpu);
6979 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 6980
6981 if (kvm_x86_ops->post_block)
6982 kvm_x86_ops->post_block(vcpu);
6983
9c8fd1ba
PB		 6984 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6985 return 1;
6986 }
362c698f
PB		 6987
6988 kvm_apic_accept_events(vcpu);
6989 switch(vcpu->arch.mp_state) {
6990 case KVM_MP_STATE_HALTED:
6991 vcpu->arch.pv.pv_unhalted = false;
6992 vcpu->arch.mp_state =
6993 KVM_MP_STATE_RUNNABLE;
6994 case KVM_MP_STATE_RUNNABLE:
6995 vcpu->arch.apf.halted = false;
6996 break;
6997 case KVM_MP_STATE_INIT_RECEIVED:
6998 break;
6999 default:
7000 return -EINTR;
7001 break;
7002 }
7003 return 1;
7004}
09cec754 7005
5d9bc648
PB		 7006static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7007{
0ad3bed6
PB		 7008 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7009 kvm_x86_ops->check_nested_events(vcpu, false);
7010
5d9bc648
PB		 7011 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7012 !vcpu->arch.apf.halted);
7013}
7014
362c698f 7015static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 7016{
7017 int r;
f656ce01 7018 struct kvm *kvm = vcpu->kvm;
d7690175 7019
f656ce01 7020 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7021
362c698f 7022 for (;;) {
58f800d5 7023 if (kvm_vcpu_running(vcpu)) {
851ba692 7024 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7025 } else {
362c698f 7026 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 7027 }
7028
09cec754
GN		 7029 if (r <= 0)
7030 break;
7031
7032 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
7033 if (kvm_cpu_has_pending_timer(vcpu))
7034 kvm_inject_pending_timer_irqs(vcpu);
7035
782d422b
MG		 7036 if (dm_request_for_irq_injection(vcpu) &&
7037 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 7038 r = 0;
7039 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7040 ++vcpu->stat.request_irq_exits;
362c698f 7041 break;
09cec754 7042 }
af585b92
GN		 7043
7044 kvm_check_async_pf_completion(vcpu);
7045
09cec754
GN		 7046 if (signal_pending(current)) {
7047 r = -EINTR;
851ba692 7048 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7049 ++vcpu->stat.signal_exits;
362c698f 7050 break;
09cec754
GN		 7051 }
7052 if (need_resched()) {
f656ce01 7053 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7054 cond_resched();
f656ce01 7055 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7056 }
b6c7a5dc
HB		 7057 }
7058
f656ce01 7059 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 7060
7061 return r;
7062}
7063
716d51ab
GN		 7064static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7065{
7066 int r;
7067 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7068 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7069 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7070 if (r != EMULATE_DONE)
7071 return 0;
7072 return 1;
7073}
7074
7075static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7076{
7077 BUG_ON(!vcpu->arch.pio.count);
7078
7079 return complete_emulated_io(vcpu);
7080}
7081
f78146b0
AK		 7082/*
7083 * Implements the following, as a state machine:
7084 *
7085 * read:
7086 * for each fragment
87da7e66
XG		 7087 * for each mmio piece in the fragment
7088 * write gpa, len
7089 * exit
7090 * copy data
f78146b0
AK		 7091 * execute insn
7092 *
7093 * write:
7094 * for each fragment
87da7e66
XG		 7095 * for each mmio piece in the fragment
7096 * write gpa, len
7097 * copy data
7098 * exit
f78146b0 7099 */
716d51ab 7100static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 7101{
7102 struct kvm_run *run = vcpu->run;
f78146b0 7103 struct kvm_mmio_fragment *frag;
87da7e66 7104 unsigned len;
5287f194 7105
716d51ab 7106 BUG_ON(!vcpu->mmio_needed);
5287f194 7107
716d51ab 7108 /* Complete previous fragment */
87da7e66
XG		 7109 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7110 len = min(8u, frag->len);
716d51ab 7111 if (!vcpu->mmio_is_write)
87da7e66
XG		 7112 memcpy(frag->data, run->mmio.data, len);
7113
7114 if (frag->len <= 8) {
7115 /* Switch to the next fragment. */
7116 frag++;
7117 vcpu->mmio_cur_fragment++;
7118 } else {
7119 /* Go forward to the next mmio piece. */
7120 frag->data += len;
7121 frag->gpa += len;
7122 frag->len -= len;
7123 }
7124
a08d3b3b 7125 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7126 vcpu->mmio_needed = 0;
0912c977
PB		 7127
7128 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7129 if (vcpu->mmio_is_write)
716d51ab
GN		 7130 return 1;
7131 vcpu->mmio_read_completed = 1;
7132 return complete_emulated_io(vcpu);
7133 }
87da7e66 7134
716d51ab
GN		 7135 run->exit_reason = KVM_EXIT_MMIO;
7136 run->mmio.phys_addr = frag->gpa;
7137 if (vcpu->mmio_is_write)
87da7e66
XG		 7138 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7139 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 7140 run->mmio.is_write = vcpu->mmio_is_write;
7141 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7142 return 0;
5287f194
AK		 7143}
7144
716d51ab 7145
b6c7a5dc
HB		 7146int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7147{
c5bedc68 7148 struct fpu *fpu = &current->thread.fpu;
b6c7a5dc
HB		 7149 int r;
7150 sigset_t sigsaved;
7151
c4d72e2d 7152 fpu__activate_curr(fpu);
e5c30142 7153
ac9f6dc0
AK		 7154 if (vcpu->sigset_active)
7155 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
7156
a4535290 7157 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 7158 kvm_vcpu_block(vcpu);
66450a21 7159 kvm_apic_accept_events(vcpu);
d7690175 7160 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 7161 r = -EAGAIN;
7162 goto out;
b6c7a5dc
HB		 7163 }
7164
b6c7a5dc 7165 /* re-sync apic's tpr */
35754c98 7166 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 7167 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7168 r = -EINVAL;
7169 goto out;
7170 }
7171 }
b6c7a5dc 7172
716d51ab
GN		 7173 if (unlikely(vcpu->arch.complete_userspace_io)) {
7174 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7175 vcpu->arch.complete_userspace_io = NULL;
7176 r = cui(vcpu);
7177 if (r <= 0)
7178 goto out;
7179 } else
7180 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7181
460df4c1
PB		 7182 if (kvm_run->immediate_exit)
7183 r = -EINTR;
7184 else
7185 r = vcpu_run(vcpu);
b6c7a5dc
HB		 7186
7187out:
f1d86e46 7188 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 7189 if (vcpu->sigset_active)
7190 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
7191
b6c7a5dc
HB		 7192 return r;
7193}
7194
7195int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7196{
7ae441ea
GN		 7197 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7198 /*
7199 * We are here if userspace calls get_regs() in the middle of
7200 * instruction emulation. Registers state needs to be copied
4a969980 7201 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 7202 * that usually, but some bad designed PV devices (vmware
7203 * backdoor interface) need this to work
7204 */
dd856efa 7205 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 7206 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7207 }
5fdbf976
MT		 7208 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7209 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7210 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7211 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7212 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7213 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7214 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7215 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7216#ifdef CONFIG_X86_64
5fdbf976
MT		 7217 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7218 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7219 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7220 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7221 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7222 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7223 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7224 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 7225#endif
7226
5fdbf976 7227 regs->rip = kvm_rip_read(vcpu);
91586a3b 7228 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7229
b6c7a5dc
HB		 7230 return 0;
7231}
7232
7233int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7234{
7ae441ea
GN		 7235 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7236 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7237
5fdbf976
MT		 7238 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7239 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7240 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7241 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7242 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7243 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7244 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7245 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7246#ifdef CONFIG_X86_64
5fdbf976
MT		 7247 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7248 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7249 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7250 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7251 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7252 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7253 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7254 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 7255#endif
7256
5fdbf976 7257 kvm_rip_write(vcpu, regs->rip);
91586a3b 7258 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 7259
b4f14abd
JK		 7260 vcpu->arch.exception.pending = false;
7261
3842d135
AK		 7262 kvm_make_request(KVM_REQ_EVENT, vcpu);
7263
b6c7a5dc
HB		 7264 return 0;
7265}
7266
b6c7a5dc
HB		 7267void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7268{
7269 struct kvm_segment cs;
7270
3e6e0aab 7271 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 7272 *db = cs.db;
7273 *l = cs.l;
7274}
7275EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7276
7277int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7278 struct kvm_sregs *sregs)
7279{
89a27f4d 7280 struct desc_ptr dt;
b6c7a5dc 7281
3e6e0aab
GT		 7282 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7283 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7284 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7285 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7286 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7287 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7288
3e6e0aab
GT		 7289 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7290 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7291
7292 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7293 sregs->idt.limit = dt.size;
7294 sregs->idt.base = dt.address;
b6c7a5dc 7295 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7296 sregs->gdt.limit = dt.size;
7297 sregs->gdt.base = dt.address;
b6c7a5dc 7298
4d4ec087 7299 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7300 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7301 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7302 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7303 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7304 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7305 sregs->apic_base = kvm_get_apic_base(vcpu);
7306
923c61bb 7307 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7308
36752c9b 7309 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7310 set_bit(vcpu->arch.interrupt.nr,
7311 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7312
b6c7a5dc
HB		 7313 return 0;
7314}
7315
62d9f0db
MT		 7316int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7317 struct kvm_mp_state *mp_state)
7318{
66450a21 7319 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7320 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7321 vcpu->arch.pv.pv_unhalted)
7322 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7323 else
7324 mp_state->mp_state = vcpu->arch.mp_state;
7325
62d9f0db
MT		 7326 return 0;
7327}
7328
7329int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7330 struct kvm_mp_state *mp_state)
7331{
bce87cce 7332 if (!lapic_in_kernel(vcpu) &&
66450a21
JK		 7333 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7334 return -EINVAL;
7335
28bf2888
DH		 7336 /* INITs are latched while in SMM */
7337 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7338 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7339 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7340 return -EINVAL;
7341
66450a21
JK		 7342 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7343 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7344 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7345 } else
7346 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7347 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7348 return 0;
7349}
7350
7f3d35fd
KW		 7351int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7352 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7353{
9d74191a 7354 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7355 int ret;
e01c2426 7356
8ec4722d 7357 init_emulate_ctxt(vcpu);
c697518a 7358
7f3d35fd 7359 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7360 has_error_code, error_code);
c697518a 7361
c697518a 7362 if (ret)
19d04437 7363 return EMULATE_FAIL;
37817f29 7364
9d74191a
TY		 7365 kvm_rip_write(vcpu, ctxt->eip);
7366 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7367 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7368 return EMULATE_DONE;
37817f29
IE		 7369}
7370EXPORT_SYMBOL_GPL(kvm_task_switch);
7371
b6c7a5dc
HB		 7372int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7373 struct kvm_sregs *sregs)
7374{
58cb628d 7375 struct msr_data apic_base_msr;
b6c7a5dc 7376 int mmu_reset_needed = 0;
63f42e02 7377 int pending_vec, max_bits, idx;
89a27f4d 7378 struct desc_ptr dt;
b6c7a5dc 7379
6d1068b3
PM		 7380 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7381 return -EINVAL;
7382
89a27f4d
GN		 7383 dt.size = sregs->idt.limit;
7384 dt.address = sregs->idt.base;
b6c7a5dc 7385 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7386 dt.size = sregs->gdt.limit;
7387 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7388 kvm_x86_ops->set_gdt(vcpu, &dt);
7389
ad312c7c 7390 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7391 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7392 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7393 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7394
2d3ad1f4 7395 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7396
f6801dff 7397 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7398 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7399 apic_base_msr.data = sregs->apic_base;
7400 apic_base_msr.host_initiated = true;
7401 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7402
4d4ec087 7403 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7404 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7405 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7406
fc78f519 7407 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7408 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7409 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7410 kvm_update_cpuid(vcpu);
63f42e02
XG		 7411
7412 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7413 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7414 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7415 mmu_reset_needed = 1;
7416 }
63f42e02 7417 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7418
7419 if (mmu_reset_needed)
7420 kvm_mmu_reset_context(vcpu);
7421
a50abc3b 7422 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7423 pending_vec = find_first_bit(
7424 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7425 if (pending_vec < max_bits) {
66fd3f7f 7426 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7427 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7428 }
7429
3e6e0aab
GT		 7430 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7431 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7432 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7433 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7434 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7435 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7436
3e6e0aab
GT		 7437 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7438 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7439
5f0269f5
ME		 7440 update_cr8_intercept(vcpu);
7441
9c3e4aab 7442 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7443 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7444 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7445 !is_protmode(vcpu))
9c3e4aab
MT		 7446 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7447
3842d135
AK		 7448 kvm_make_request(KVM_REQ_EVENT, vcpu);
7449
b6c7a5dc
HB		 7450 return 0;
7451}
7452
d0bfb940
JK		 7453int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7454 struct kvm_guest_debug *dbg)
b6c7a5dc 7455{
355be0b9 7456 unsigned long rflags;
ae675ef0 7457 int i, r;
b6c7a5dc 7458
4f926bf2
JK		 7459 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7460 r = -EBUSY;
7461 if (vcpu->arch.exception.pending)
2122ff5e 7462 goto out;
4f926bf2
JK		 7463 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7464 kvm_queue_exception(vcpu, DB_VECTOR);
7465 else
7466 kvm_queue_exception(vcpu, BP_VECTOR);
7467 }
7468
91586a3b
JK		 7469 /*
7470 * Read rflags as long as potentially injected trace flags are still
7471 * filtered out.
7472 */
7473 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7474
7475 vcpu->guest_debug = dbg->control;
7476 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7477 vcpu->guest_debug = 0;
7478
7479 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7480 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7481 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7482 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7483 } else {
7484 for (i = 0; i < KVM_NR_DB_REGS; i++)
7485 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7486 }
c8639010 7487 kvm_update_dr7(vcpu);
ae675ef0 7488
f92653ee
JK		 7489 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7490 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7491 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7492
91586a3b
JK		 7493 /*
7494 * Trigger an rflags update that will inject or remove the trace
7495 * flags.
7496 */
7497 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7498
a96036b8 7499 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7500
4f926bf2 7501 r = 0;
d0bfb940 7502
2122ff5e 7503out:
b6c7a5dc
HB		 7504
7505 return r;
7506}
7507
8b006791
ZX		 7508/*
7509 * Translate a guest virtual address to a guest physical address.
7510 */
7511int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7512 struct kvm_translation *tr)
7513{
7514 unsigned long vaddr = tr->linear_address;
7515 gpa_t gpa;
f656ce01 7516 int idx;
8b006791 7517
f656ce01 7518 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7519 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7520 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7521 tr->physical_address = gpa;
7522 tr->valid = gpa != UNMAPPED_GVA;
7523 tr->writeable = 1;
7524 tr->usermode = 0;
8b006791
ZX		 7525
7526 return 0;
7527}
7528
d0752060
HB		 7529int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7530{
c47ada30 7531 struct fxregs_state *fxsave =
7366ed77 7532 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7533
d0752060
HB		 7534 memcpy(fpu->fpr, fxsave->st_space, 128);
7535 fpu->fcw = fxsave->cwd;
7536 fpu->fsw = fxsave->swd;
7537 fpu->ftwx = fxsave->twd;
7538 fpu->last_opcode = fxsave->fop;
7539 fpu->last_ip = fxsave->rip;
7540 fpu->last_dp = fxsave->rdp;
7541 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7542
d0752060
HB		 7543 return 0;
7544}
7545
7546int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7547{
c47ada30 7548 struct fxregs_state *fxsave =
7366ed77 7549 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7550
d0752060
HB		 7551 memcpy(fxsave->st_space, fpu->fpr, 128);
7552 fxsave->cwd = fpu->fcw;
7553 fxsave->swd = fpu->fsw;
7554 fxsave->twd = fpu->ftwx;
7555 fxsave->fop = fpu->last_opcode;
7556 fxsave->rip = fpu->last_ip;
7557 fxsave->rdp = fpu->last_dp;
7558 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7559
d0752060
HB		 7560 return 0;
7561}
7562
0ee6a517 7563static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7564{
bf935b0b 7565 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7566 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7567 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7568 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7569
2acf923e
DC		 7570 /*
7571 * Ensure guest xcr0 is valid for loading
7572 */
d91cab78 7573 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7574
ad312c7c 7575 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7576}
d0752060
HB		 7577
7578void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7579{
2608d7a1 7580 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7581 return;
7582
2acf923e
DC		 7583 /*
7584 * Restore all possible states in the guest,
7585 * and assume host would use all available bits.
7586 * Guest xcr0 would be loaded later.
7587 */
d0752060 7588 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7589 __kernel_fpu_begin();
003e2e8b 7590 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state);
0c04851c 7591 trace_kvm_fpu(1);
d0752060 7592}
d0752060
HB		 7593
7594void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7595{
3d42de25 7596 if (!vcpu->guest_fpu_loaded)
d0752060
HB		 7597 return;
7598
7599 vcpu->guest_fpu_loaded = 0;
4f836347 7600 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
b1a74bf8 7601 __kernel_fpu_end();
f096ed85 7602 ++vcpu->stat.fpu_reload;
0c04851c 7603 trace_kvm_fpu(0);
d0752060 7604}
e9b11c17
ZX		 7605
7606void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7607{
bd768e14
IY		 7608 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7609
12f9a48f 7610 kvmclock_reset(vcpu);
7f1ea208 7611
e9b11c17 7612 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7613 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX		 7614}
7615
7616struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7617 unsigned int id)
7618{
c447e76b
LL		 7619 struct kvm_vcpu *vcpu;
7620
6755bae8
ZA		 7621 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7622 printk_once(KERN_WARNING
7623 "kvm: SMP vm created on host with unstable TSC; "
7624 "guest TSC will not be reliable\n");
c447e76b
LL		 7625
7626 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7627
c447e76b 7628 return vcpu;
26e5215f 7629}
e9b11c17 7630
26e5215f
AK		 7631int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7632{
7633 int r;
e9b11c17 7634
19efffa2 7635 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT		 7636 r = vcpu_load(vcpu);
7637 if (r)
7638 return r;
d28bc9dd 7639 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7640 kvm_mmu_setup(vcpu);
e9b11c17 7641 vcpu_put(vcpu);
26e5215f 7642 return r;
e9b11c17
ZX		 7643}
7644
31928aa5 7645void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7646{
8fe8ab46 7647 struct msr_data msr;
332967a3 7648 struct kvm *kvm = vcpu->kvm;
42897d86 7649
31928aa5
DD		 7650 if (vcpu_load(vcpu))
7651 return;
8fe8ab46
WA		 7652 msr.data = 0x0;
7653 msr.index = MSR_IA32_TSC;
7654 msr.host_initiated = true;
7655 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7656 vcpu_put(vcpu);
7657
630994b3
MT		 7658 if (!kvmclock_periodic_sync)
7659 return;
7660
332967a3
AJ		 7661 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7662 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7663}
7664
d40ccc62 7665void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7666{
9fc77441 7667 int r;
344d9588
GN		 7668 vcpu->arch.apf.msr_val = 0;
7669
9fc77441
MT		 7670 r = vcpu_load(vcpu);
7671 BUG_ON(r);
e9b11c17
ZX		 7672 kvm_mmu_unload(vcpu);
7673 vcpu_put(vcpu);
7674
7675 kvm_x86_ops->vcpu_free(vcpu);
7676}
7677
d28bc9dd 7678void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7679{
e69fab5d
PB		 7680 vcpu->arch.hflags = 0;
7681
c43203ca 7682 vcpu->arch.smi_pending = 0;
7460fb4a
AK		 7683 atomic_set(&vcpu->arch.nmi_queued, 0);
7684 vcpu->arch.nmi_pending = 0;
448fa4a9 7685 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7686 kvm_clear_interrupt_queue(vcpu);
7687 kvm_clear_exception_queue(vcpu);
448fa4a9 7688
42dbaa5a 7689 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7690 kvm_update_dr0123(vcpu);
6f43ed01 7691 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7692 kvm_update_dr6(vcpu);
42dbaa5a 7693 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7694 kvm_update_dr7(vcpu);
42dbaa5a 7695
1119022c
NA		 7696 vcpu->arch.cr2 = 0;
7697
3842d135 7698 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7699 vcpu->arch.apf.msr_val = 0;
c9aaa895 7700 vcpu->arch.st.msr_val = 0;
3842d135 7701
12f9a48f
GC		 7702 kvmclock_reset(vcpu);
7703
af585b92
GN		 7704 kvm_clear_async_pf_completion_queue(vcpu);
7705 kvm_async_pf_hash_reset(vcpu);
7706 vcpu->arch.apf.halted = false;
3842d135 7707
64d60670 7708 if (!init_event) {
d28bc9dd 7709 kvm_pmu_reset(vcpu);
64d60670
PB		 7710 vcpu->arch.smbase = 0x30000;
7711 }
f5132b01 7712
66f7b72e
JS		 7713 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7714 vcpu->arch.regs_avail = ~0;
7715 vcpu->arch.regs_dirty = ~0;
7716
d28bc9dd 7717 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7718}
7719
2b4a273b 7720void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7721{
7722 struct kvm_segment cs;
7723
7724 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7725 cs.selector = vector << 8;
7726 cs.base = vector << 12;
7727 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7728 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7729}
7730
13a34e06 7731int kvm_arch_hardware_enable(void)
e9b11c17 7732{
ca84d1a2
ZA		 7733 struct kvm *kvm;
7734 struct kvm_vcpu *vcpu;
7735 int i;
0dd6a6ed
ZA		 7736 int ret;
7737 u64 local_tsc;
7738 u64 max_tsc = 0;
7739 bool stable, backwards_tsc = false;
18863bdd
AK		 7740
7741 kvm_shared_msr_cpu_online();
13a34e06 7742 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7743 if (ret != 0)
7744 return ret;
7745
4ea1636b 7746 local_tsc = rdtsc();
0dd6a6ed
ZA		 7747 stable = !check_tsc_unstable();
7748 list_for_each_entry(kvm, &vm_list, vm_list) {
7749 kvm_for_each_vcpu(i, vcpu, kvm) {
7750 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7751 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7752 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7753 backwards_tsc = true;
7754 if (vcpu->arch.last_host_tsc > max_tsc)
7755 max_tsc = vcpu->arch.last_host_tsc;
7756 }
7757 }
7758 }
7759
7760 /*
7761 * Sometimes, even reliable TSCs go backwards. This happens on
7762 * platforms that reset TSC during suspend or hibernate actions, but
7763 * maintain synchronization. We must compensate. Fortunately, we can
7764 * detect that condition here, which happens early in CPU bringup,
7765 * before any KVM threads can be running. Unfortunately, we can't
7766 * bring the TSCs fully up to date with real time, as we aren't yet far
7767 * enough into CPU bringup that we know how much real time has actually
108b249c 7768 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA		 7769 * variables that haven't been updated yet.
7770 *
7771 * So we simply find the maximum observed TSC above, then record the
7772 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7773 * the adjustment will be applied. Note that we accumulate
7774 * adjustments, in case multiple suspend cycles happen before some VCPU
7775 * gets a chance to run again. In the event that no KVM threads get a
7776 * chance to run, we will miss the entire elapsed period, as we'll have
7777 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7778 * loose cycle time. This isn't too big a deal, since the loss will be
7779 * uniform across all VCPUs (not to mention the scenario is extremely
7780 * unlikely). It is possible that a second hibernate recovery happens
7781 * much faster than a first, causing the observed TSC here to be
7782 * smaller; this would require additional padding adjustment, which is
7783 * why we set last_host_tsc to the local tsc observed here.
7784 *
7785 * N.B. - this code below runs only on platforms with reliable TSC,
7786 * as that is the only way backwards_tsc is set above. Also note
7787 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7788 * have the same delta_cyc adjustment applied if backwards_tsc
7789 * is detected. Note further, this adjustment is only done once,
7790 * as we reset last_host_tsc on all VCPUs to stop this from being
7791 * called multiple times (one for each physical CPU bringup).
7792 *
4a969980 7793 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7794 * will be compensated by the logic in vcpu_load, which sets the TSC to
7795 * catchup mode. This will catchup all VCPUs to real time, but cannot
7796 * guarantee that they stay in perfect synchronization.
7797 */
7798 if (backwards_tsc) {
7799 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7800 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7801 list_for_each_entry(kvm, &vm_list, vm_list) {
7802 kvm_for_each_vcpu(i, vcpu, kvm) {
7803 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7804 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7805 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7806 }
7807
7808 /*
7809 * We have to disable TSC offset matching.. if you were
7810 * booting a VM while issuing an S4 host suspend....
7811 * you may have some problem. Solving this issue is
7812 * left as an exercise to the reader.
7813 */
7814 kvm->arch.last_tsc_nsec = 0;
7815 kvm->arch.last_tsc_write = 0;
7816 }
7817
7818 }
7819 return 0;
e9b11c17
ZX		 7820}
7821
13a34e06 7822void kvm_arch_hardware_disable(void)
e9b11c17 7823{
13a34e06
RK		 7824 kvm_x86_ops->hardware_disable();
7825 drop_user_return_notifiers();
e9b11c17
ZX		 7826}
7827
7828int kvm_arch_hardware_setup(void)
7829{
9e9c3fe4
NA		 7830 int r;
7831
7832 r = kvm_x86_ops->hardware_setup();
7833 if (r != 0)
7834 return r;
7835
35181e86
HZ		 7836 if (kvm_has_tsc_control) {
7837 /*
7838 * Make sure the user can only configure tsc_khz values that
7839 * fit into a signed integer.
7840 * A min value is not calculated needed because it will always
7841 * be 1 on all machines.
7842 */
7843 u64 max = min(0x7fffffffULL,
7844 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
7845 kvm_max_guest_tsc_khz = max;
7846
ad721883 7847 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 7848 }
ad721883 7849
9e9c3fe4
NA		 7850 kvm_init_msr_list();
7851 return 0;
e9b11c17
ZX		 7852}
7853
7854void kvm_arch_hardware_unsetup(void)
7855{
7856 kvm_x86_ops->hardware_unsetup();
7857}
7858
7859void kvm_arch_check_processor_compat(void *rtn)
7860{
7861 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB		 7862}
7863
7864bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
7865{
7866 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
7867}
7868EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
7869
7870bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
7871{
7872 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 7873}
7874
54e9818f 7875struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 7876EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 7877
e9b11c17
ZX		 7878int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7879{
7880 struct page *page;
7881 struct kvm *kvm;
7882 int r;
7883
7884 BUG_ON(vcpu->kvm == NULL);
7885 kvm = vcpu->kvm;
7886
d62caabb 7887 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv();
6aef266c 7888 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7889 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7890 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7891 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7892 else
a4535290 7893 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7894
7895 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7896 if (!page) {
7897 r = -ENOMEM;
7898 goto fail;
7899 }
ad312c7c 7900 vcpu->arch.pio_data = page_address(page);
e9b11c17 7901
cc578287 7902 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7903
e9b11c17
ZX		 7904 r = kvm_mmu_create(vcpu);
7905 if (r < 0)
7906 goto fail_free_pio_data;
7907
7908 if (irqchip_in_kernel(kvm)) {
7909 r = kvm_create_lapic(vcpu);
7910 if (r < 0)
7911 goto fail_mmu_destroy;
54e9818f
GN		 7912 } else
7913 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7914
890ca9ae
HY		 7915 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7916 GFP_KERNEL);
7917 if (!vcpu->arch.mce_banks) {
7918 r = -ENOMEM;
443c39bc 7919 goto fail_free_lapic;
890ca9ae
HY		 7920 }
7921 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7922
f1797359
WY		 7923 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7924 r = -ENOMEM;
f5f48ee1 7925 goto fail_free_mce_banks;
f1797359 7926 }
f5f48ee1 7927
0ee6a517 7928 fx_init(vcpu);
66f7b72e 7929
ba904635 7930 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7931 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7932
7933 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7934 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7935
5a4f55cd
EK		 7936 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7937
74545705
RK		 7938 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7939
af585b92 7940 kvm_async_pf_hash_reset(vcpu);
f5132b01 7941 kvm_pmu_init(vcpu);
af585b92 7942
1c1a9ce9
SR		 7943 vcpu->arch.pending_external_vector = -1;
7944
5c919412
AS		 7945 kvm_hv_vcpu_init(vcpu);
7946
e9b11c17 7947 return 0;
0ee6a517 7948
f5f48ee1
SY		 7949fail_free_mce_banks:
7950 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7951fail_free_lapic:
7952 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7953fail_mmu_destroy:
7954 kvm_mmu_destroy(vcpu);
7955fail_free_pio_data:
ad312c7c 7956 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7957fail:
7958 return r;
7959}
7960
7961void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7962{
f656ce01
MT		 7963 int idx;
7964
1f4b34f8 7965 kvm_hv_vcpu_uninit(vcpu);
f5132b01 7966 kvm_pmu_destroy(vcpu);
36cb93fd 7967 kfree(vcpu->arch.mce_banks);
e9b11c17 7968 kvm_free_lapic(vcpu);
f656ce01 7969 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7970 kvm_mmu_destroy(vcpu);
f656ce01 7971 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7972 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 7973 if (!lapic_in_kernel(vcpu))
54e9818f 7974 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7975}
d19a9cd2 7976
e790d9ef
RK		 7977void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7978{
ae97a3b8 7979 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7980}
7981
e08b9637 7982int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7983{
e08b9637
CO		 7984 if (type)
7985 return -EINVAL;
7986
6ef768fa 7987 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7988 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7989 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7990 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7991 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7992
5550af4d
SY		 7993 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7994 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7995 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7996 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7997 &kvm->arch.irq_sources_bitmap);
5550af4d 7998
038f8c11 7999 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8000 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8001 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT		 8002 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8003
108b249c 8004 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8005 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8006
7e44e449 8007 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8008 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8009
0eb05bf2 8010 kvm_page_track_init(kvm);
13d268ca 8011 kvm_mmu_init_vm(kvm);
0eb05bf2 8012
03543133
SS		 8013 if (kvm_x86_ops->vm_init)
8014 return kvm_x86_ops->vm_init(kvm);
8015
d89f5eff 8016 return 0;
d19a9cd2
ZX		 8017}
8018
8019static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8020{
9fc77441
MT		 8021 int r;
8022 r = vcpu_load(vcpu);
8023 BUG_ON(r);
d19a9cd2
ZX		 8024 kvm_mmu_unload(vcpu);
8025 vcpu_put(vcpu);
8026}
8027
8028static void kvm_free_vcpus(struct kvm *kvm)
8029{
8030 unsigned int i;
988a2cae 8031 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 8032
8033 /*
8034 * Unpin any mmu pages first.
8035 */
af585b92
GN		 8036 kvm_for_each_vcpu(i, vcpu, kvm) {
8037 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8038 kvm_unload_vcpu_mmu(vcpu);
af585b92 8039 }
988a2cae
GN		 8040 kvm_for_each_vcpu(i, vcpu, kvm)
8041 kvm_arch_vcpu_free(vcpu);
8042
8043 mutex_lock(&kvm->lock);
8044 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8045 kvm->vcpus[i] = NULL;
d19a9cd2 8046
988a2cae
GN		 8047 atomic_set(&kvm->online_vcpus, 0);
8048 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 8049}
8050
ad8ba2cd
SY		 8051void kvm_arch_sync_events(struct kvm *kvm)
8052{
332967a3 8053 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8054 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8055 kvm_free_pit(kvm);
ad8ba2cd
SY		 8056}
8057
1d8007bd 8058int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8059{
8060 int i, r;
25188b99 8061 unsigned long hva;
f0d648bd
PB		 8062 struct kvm_memslots *slots = kvm_memslots(kvm);
8063 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 8064
8065 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 8066 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8067 return -EINVAL;
9da0e4d5 8068
f0d648bd
PB		 8069 slot = id_to_memslot(slots, id);
8070 if (size) {
b21629da 8071 if (slot->npages)
f0d648bd
PB		 8072 return -EEXIST;
8073
8074 /*
8075 * MAP_SHARED to prevent internal slot pages from being moved
8076 * by fork()/COW.
8077 */
8078 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8079 MAP_SHARED | MAP_ANONYMOUS, 0);
8080 if (IS_ERR((void *)hva))
8081 return PTR_ERR((void *)hva);
8082 } else {
8083 if (!slot->npages)
8084 return 0;
8085
8086 hva = 0;
8087 }
8088
8089 old = *slot;
9da0e4d5 8090 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8091 struct kvm_userspace_memory_region m;
9da0e4d5 8092
1d8007bd
PB		 8093 m.slot = id | (i << 16);
8094 m.flags = 0;
8095 m.guest_phys_addr = gpa;
f0d648bd 8096 m.userspace_addr = hva;
1d8007bd 8097 m.memory_size = size;
9da0e4d5
PB		 8098 r = __kvm_set_memory_region(kvm, &m);
8099 if (r < 0)
8100 return r;
8101 }
8102
f0d648bd
PB		 8103 if (!size) {
8104 r = vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
8105 WARN_ON(r < 0);
8106 }
8107
9da0e4d5
PB		 8108 return 0;
8109}
8110EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8111
1d8007bd 8112int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 8113{
8114 int r;
8115
8116 mutex_lock(&kvm->slots_lock);
1d8007bd 8117 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB		 8118 mutex_unlock(&kvm->slots_lock);
8119
8120 return r;
8121}
8122EXPORT_SYMBOL_GPL(x86_set_memory_region);
8123
d19a9cd2
ZX		 8124void kvm_arch_destroy_vm(struct kvm *kvm)
8125{
27469d29
AH		 8126 if (current->mm == kvm->mm) {
8127 /*
8128 * Free memory regions allocated on behalf of userspace,
8129 * unless the the memory map has changed due to process exit
8130 * or fd copying.
8131 */
1d8007bd
PB		 8132 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8133 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8134 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8135 }
03543133
SS		 8136 if (kvm_x86_ops->vm_destroy)
8137 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 8138 kvm_pic_destroy(kvm);
8139 kvm_ioapic_destroy(kvm);
d19a9cd2 8140 kvm_free_vcpus(kvm);
af1bae54 8141 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8142 kvm_mmu_uninit_vm(kvm);
2beb6dad 8143 kvm_page_track_cleanup(kvm);
d19a9cd2 8144}
0de10343 8145
5587027c 8146void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 8147 struct kvm_memory_slot *dont)
8148{
8149 int i;
8150
d89cc617
TY		 8151 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8152 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8153 kvfree(free->arch.rmap[i]);
d89cc617 8154 free->arch.rmap[i] = NULL;
77d11309 8155 }
d89cc617
TY		 8156 if (i == 0)
8157 continue;
8158
8159 if (!dont || free->arch.lpage_info[i - 1] !=
8160 dont->arch.lpage_info[i - 1]) {
548ef284 8161 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8162 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8163 }
8164 }
21ebbeda
XG		 8165
8166 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 8167}
8168
5587027c
AK		 8169int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8170 unsigned long npages)
db3fe4eb
TY		 8171{
8172 int i;
8173
d89cc617 8174 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8175 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 8176 unsigned long ugfn;
8177 int lpages;
d89cc617 8178 int level = i + 1;
db3fe4eb
TY		 8179
8180 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8181 slot->base_gfn, level) + 1;
8182
d89cc617
TY		 8183 slot->arch.rmap[i] =
8184 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
8185 if (!slot->arch.rmap[i])
77d11309 8186 goto out_free;
d89cc617
TY		 8187 if (i == 0)
8188 continue;
77d11309 8189
92f94f1e
XG		 8190 linfo = kvm_kvzalloc(lpages * sizeof(*linfo));
8191 if (!linfo)
db3fe4eb
TY		 8192 goto out_free;
8193
92f94f1e
XG		 8194 slot->arch.lpage_info[i - 1] = linfo;
8195
db3fe4eb 8196 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8197 linfo[0].disallow_lpage = 1;
db3fe4eb 8198 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8199 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 8200 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8201 /*
8202 * If the gfn and userspace address are not aligned wrt each
8203 * other, or if explicitly asked to, disable large page
8204 * support for this slot
8205 */
8206 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8207 !kvm_largepages_enabled()) {
8208 unsigned long j;
8209
8210 for (j = 0; j < lpages; ++j)
92f94f1e 8211 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 8212 }
8213 }
8214
21ebbeda
XG		 8215 if (kvm_page_track_create_memslot(slot, npages))
8216 goto out_free;
8217
db3fe4eb
TY		 8218 return 0;
8219
8220out_free:
d89cc617 8221 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8222 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 8223 slot->arch.rmap[i] = NULL;
8224 if (i == 0)
8225 continue;
8226
548ef284 8227 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8228 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 8229 }
8230 return -ENOMEM;
8231}
8232
15f46015 8233void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8234{
e6dff7d1
TY		 8235 /*
8236 * memslots->generation has been incremented.
8237 * mmio generation may have reached its maximum value.
8238 */
54bf36aa 8239 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 8240}
8241
f7784b8e
MT		 8242int kvm_arch_prepare_memory_region(struct kvm *kvm,
8243 struct kvm_memory_slot *memslot,
09170a49 8244 const struct kvm_userspace_memory_region *mem,
7b6195a9 8245 enum kvm_mr_change change)
0de10343 8246{
f7784b8e
MT		 8247 return 0;
8248}
8249
88178fd4
KH		 8250static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8251 struct kvm_memory_slot *new)
8252{
8253 /* Still write protect RO slot */
8254 if (new->flags & KVM_MEM_READONLY) {
8255 kvm_mmu_slot_remove_write_access(kvm, new);
8256 return;
8257 }
8258
8259 /*
8260 * Call kvm_x86_ops dirty logging hooks when they are valid.
8261 *
8262 * kvm_x86_ops->slot_disable_log_dirty is called when:
8263 *
8264 * - KVM_MR_CREATE with dirty logging is disabled
8265 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8266 *
8267 * The reason is, in case of PML, we need to set D-bit for any slots
8268 * with dirty logging disabled in order to eliminate unnecessary GPA
8269 * logging in PML buffer (and potential PML buffer full VMEXT). This
8270 * guarantees leaving PML enabled during guest's lifetime won't have
8271 * any additonal overhead from PML when guest is running with dirty
8272 * logging disabled for memory slots.
8273 *
8274 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8275 * to dirty logging mode.
8276 *
8277 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8278 *
8279 * In case of write protect:
8280 *
8281 * Write protect all pages for dirty logging.
8282 *
8283 * All the sptes including the large sptes which point to this
8284 * slot are set to readonly. We can not create any new large
8285 * spte on this slot until the end of the logging.
8286 *
8287 * See the comments in fast_page_fault().
8288 */
8289 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8290 if (kvm_x86_ops->slot_enable_log_dirty)
8291 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8292 else
8293 kvm_mmu_slot_remove_write_access(kvm, new);
8294 } else {
8295 if (kvm_x86_ops->slot_disable_log_dirty)
8296 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8297 }
8298}
8299
f7784b8e 8300void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8301 const struct kvm_userspace_memory_region *mem,
8482644a 8302 const struct kvm_memory_slot *old,
f36f3f28 8303 const struct kvm_memory_slot *new,
8482644a 8304 enum kvm_mr_change change)
f7784b8e 8305{
8482644a 8306 int nr_mmu_pages = 0;
f7784b8e 8307
48c0e4e9
XG		 8308 if (!kvm->arch.n_requested_mmu_pages)
8309 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8310
48c0e4e9 8311 if (nr_mmu_pages)
0de10343 8312 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8313
3ea3b7fa
WL		 8314 /*
8315 * Dirty logging tracks sptes in 4k granularity, meaning that large
8316 * sptes have to be split. If live migration is successful, the guest
8317 * in the source machine will be destroyed and large sptes will be
8318 * created in the destination. However, if the guest continues to run
8319 * in the source machine (for example if live migration fails), small
8320 * sptes will remain around and cause bad performance.
8321 *
8322 * Scan sptes if dirty logging has been stopped, dropping those
8323 * which can be collapsed into a single large-page spte. Later
8324 * page faults will create the large-page sptes.
8325 */
8326 if ((change != KVM_MR_DELETE) &&
8327 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8328 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8329 kvm_mmu_zap_collapsible_sptes(kvm, new);
8330
c972f3b1 8331 /*
88178fd4 8332 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8333 *
88178fd4
KH		 8334 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8335 * been zapped so no dirty logging staff is needed for old slot. For
8336 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8337 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8338 *
8339 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8340 */
88178fd4 8341 if (change != KVM_MR_DELETE)
f36f3f28 8342 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8343}
1d737c8a 8344
2df72e9b 8345void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8346{
6ca18b69 8347 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8348}
8349
2df72e9b
MT		 8350void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8351 struct kvm_memory_slot *slot)
8352{
ae7cd873 8353 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 8354}
8355
5d9bc648
PB		 8356static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8357{
8358 if (!list_empty_careful(&vcpu->async_pf.done))
8359 return true;
8360
8361 if (kvm_apic_has_events(vcpu))
8362 return true;
8363
8364 if (vcpu->arch.pv.pv_unhalted)
8365 return true;
8366
8367 if (atomic_read(&vcpu->arch.nmi_queued))
8368 return true;
8369
73917739
PB		 8370 if (test_bit(KVM_REQ_SMI, &vcpu->requests))
8371 return true;
8372
5d9bc648
PB		 8373 if (kvm_arch_interrupt_allowed(vcpu) &&
8374 kvm_cpu_has_interrupt(vcpu))
8375 return true;
8376
1f4b34f8
AS		 8377 if (kvm_hv_has_stimer_pending(vcpu))
8378 return true;
8379
5d9bc648
PB		 8380 return false;
8381}
8382
1d737c8a
ZX		 8383int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8384{
5d9bc648 8385 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8386}
5736199a 8387
b6d33834 8388int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8389{
b6d33834 8390 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8391}
78646121
GN		 8392
8393int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8394{
8395 return kvm_x86_ops->interrupt_allowed(vcpu);
8396}
229456fc 8397
82b32774 8398unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8399{
82b32774
NA		 8400 if (is_64_bit_mode(vcpu))
8401 return kvm_rip_read(vcpu);
8402 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8403 kvm_rip_read(vcpu));
8404}
8405EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8406
82b32774
NA		 8407bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8408{
8409 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8410}
8411EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8412
94fe45da
JK		 8413unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8414{
8415 unsigned long rflags;
8416
8417 rflags = kvm_x86_ops->get_rflags(vcpu);
8418 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8419 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8420 return rflags;
8421}
8422EXPORT_SYMBOL_GPL(kvm_get_rflags);
8423
6addfc42 8424static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8425{
8426 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8427 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8428 rflags |= X86_EFLAGS_TF;
94fe45da 8429 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8430}
8431
8432void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8433{
8434 __kvm_set_rflags(vcpu, rflags);
3842d135 8435 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8436}
8437EXPORT_SYMBOL_GPL(kvm_set_rflags);
8438
56028d08
GN		 8439void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8440{
8441 int r;
8442
fb67e14f 8443 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8444 work->wakeup_all)
56028d08
GN		 8445 return;
8446
8447 r = kvm_mmu_reload(vcpu);
8448 if (unlikely(r))
8449 return;
8450
fb67e14f
XG		 8451 if (!vcpu->arch.mmu.direct_map &&
8452 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8453 return;
8454
56028d08
GN		 8455 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8456}
8457
af585b92
GN		 8458static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8459{
8460 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8461}
8462
8463static inline u32 kvm_async_pf_next_probe(u32 key)
8464{
8465 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8466}
8467
8468static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8469{
8470 u32 key = kvm_async_pf_hash_fn(gfn);
8471
8472 while (vcpu->arch.apf.gfns[key] != ~0)
8473 key = kvm_async_pf_next_probe(key);
8474
8475 vcpu->arch.apf.gfns[key] = gfn;
8476}
8477
8478static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8479{
8480 int i;
8481 u32 key = kvm_async_pf_hash_fn(gfn);
8482
8483 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8484 (vcpu->arch.apf.gfns[key] != gfn &&
8485 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8486 key = kvm_async_pf_next_probe(key);
8487
8488 return key;
8489}
8490
8491bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8492{
8493 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8494}
8495
8496static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8497{
8498 u32 i, j, k;
8499
8500 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8501 while (true) {
8502 vcpu->arch.apf.gfns[i] = ~0;
8503 do {
8504 j = kvm_async_pf_next_probe(j);
8505 if (vcpu->arch.apf.gfns[j] == ~0)
8506 return;
8507 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8508 /*
8509 * k lies cyclically in ]i,j]
8510 * | i.k.j |
8511 * |....j i.k.| or |.k..j i...|
8512 */
8513 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8514 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8515 i = j;
8516 }
8517}
8518
7c90705b
GN		 8519static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8520{
bbd64115
CL		 8521 return kvm_vcpu_write_guest_cached(vcpu, &vcpu->arch.apf.data, &val,
8522 sizeof(val));
7c90705b
GN		 8523}
8524
af585b92
GN		 8525void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8526 struct kvm_async_pf *work)
8527{
6389ee94
AK		 8528 struct x86_exception fault;
8529
7c90705b 8530 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8531 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8532
8533 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8534 (vcpu->arch.apf.send_user_only &&
8535 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8536 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8537 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8538 fault.vector = PF_VECTOR;
8539 fault.error_code_valid = true;
8540 fault.error_code = 0;
8541 fault.nested_page_fault = false;
8542 fault.address = work->arch.token;
8543 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8544 }
af585b92
GN		 8545}
8546
8547void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8548 struct kvm_async_pf *work)
8549{
6389ee94
AK		 8550 struct x86_exception fault;
8551
f2e10669 8552 if (work->wakeup_all)
7c90705b
GN		 8553 work->arch.token = ~0; /* broadcast wakeup */
8554 else
8555 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8556 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b
GN		 8557
8558 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8559 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8560 fault.vector = PF_VECTOR;
8561 fault.error_code_valid = true;
8562 fault.error_code = 0;
8563 fault.nested_page_fault = false;
8564 fault.address = work->arch.token;
8565 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8566 }
e6d53e3b 8567 vcpu->arch.apf.halted = false;
a4fa1635 8568 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8569}
8570
8571bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8572{
8573 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8574 return true;
8575 else
8576 return !kvm_event_needs_reinjection(vcpu) &&
8577 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8578}
8579
5544eb9b
PB		 8580void kvm_arch_start_assignment(struct kvm *kvm)
8581{
8582 atomic_inc(&kvm->arch.assigned_device_count);
8583}
8584EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8585
8586void kvm_arch_end_assignment(struct kvm *kvm)
8587{
8588 atomic_dec(&kvm->arch.assigned_device_count);
8589}
8590EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8591
8592bool kvm_arch_has_assigned_device(struct kvm *kvm)
8593{
8594 return atomic_read(&kvm->arch.assigned_device_count);
8595}
8596EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8597
e0f0bbc5
AW		 8598void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8599{
8600 atomic_inc(&kvm->arch.noncoherent_dma_count);
8601}
8602EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8603
8604void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8605{
8606 atomic_dec(&kvm->arch.noncoherent_dma_count);
8607}
8608EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8609
8610bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8611{
8612 return atomic_read(&kvm->arch.noncoherent_dma_count);
8613}
8614EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8615
14717e20
AW		 8616bool kvm_arch_has_irq_bypass(void)
8617{
8618 return kvm_x86_ops->update_pi_irte != NULL;
8619}
8620
87276880
FW		 8621int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8622 struct irq_bypass_producer *prod)
8623{
8624 struct kvm_kernel_irqfd *irqfd =
8625 container_of(cons, struct kvm_kernel_irqfd, consumer);
8626
14717e20 8627 irqfd->producer = prod;
87276880 8628
14717e20
AW		 8629 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8630 prod->irq, irqfd->gsi, 1);
87276880
FW		 8631}
8632
8633void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8634 struct irq_bypass_producer *prod)
8635{
8636 int ret;
8637 struct kvm_kernel_irqfd *irqfd =
8638 container_of(cons, struct kvm_kernel_irqfd, consumer);
8639
87276880
FW		 8640 WARN_ON(irqfd->producer != prod);
8641 irqfd->producer = NULL;
8642
8643 /*
8644 * When producer of consumer is unregistered, we change back to
8645 * remapped mode, so we can re-use the current implementation
bb3541f1 8646 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 8647 * int this case doesn't want to receive the interrupts.
8648 */
8649 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8650 if (ret)
8651 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8652 " fails: %d\n", irqfd->consumer.token, ret);
8653}
8654
8655int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8656 uint32_t guest_irq, bool set)
8657{
8658 if (!kvm_x86_ops->update_pi_irte)
8659 return -EINVAL;
8660
8661 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8662}
8663
52004014
FW		 8664bool kvm_vector_hashing_enabled(void)
8665{
8666 return vector_hashing;
8667}
8668EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8669
229456fc 8670EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8671EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 8672EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8673EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8674EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8675EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8676EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8677EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8678EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8679EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8680EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8681EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8682EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8683EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8684EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8685EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8686EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 8687EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8688EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)