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kvm: x86: Introduce APICv inhibit reason bits
[linux-2.6-block.git] / arch / x86 / kvm / x86.c
CommitLineData
20c8ccb1 1// SPDX-License-Identifier: GPL-2.0-only
043405e1
CO		 2/*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
9611c187 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 17 */
18
edf88417 19#include <linux/kvm_host.h>
313a3dc7 20#include "irq.h"
1d737c8a 21#include "mmu.h"
7837699f 22#include "i8254.h"
37817f29 23#include "tss.h"
5fdbf976 24#include "kvm_cache_regs.h"
26eef70c 25#include "x86.h"
00b27a3e 26#include "cpuid.h"
474a5bb9 27#include "pmu.h"
e83d5887 28#include "hyperv.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
1767e931
PG		 35#include <linux/export.h>
36#include <linux/moduleparam.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
87276880
FW		 51#include <linux/kvm_irqfd.h>
52#include <linux/irqbypass.h>
3905f9ad 53#include <linux/sched/stat.h>
0c5f81da 54#include <linux/sched/isolation.h>
d0ec49d4 55#include <linux/mem_encrypt.h>
3905f9ad 56
aec51dc4 57#include <trace/events/kvm.h>
2ed152af 58
24f1e32c 59#include <asm/debugreg.h>
d825ed0a 60#include <asm/msr.h>
a5f61300 61#include <asm/desc.h>
890ca9ae 62#include <asm/mce.h>
f89e32e0 63#include <linux/kernel_stat.h>
78f7f1e5 64#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 65#include <asm/pvclock.h>
217fc9cf 66#include <asm/div64.h>
efc64404 67#include <asm/irq_remapping.h>
b0c39dc6 68#include <asm/mshyperv.h>
0092e434 69#include <asm/hypervisor.h>
bf8c55d8 70#include <asm/intel_pt.h>
b3dc0695 71#include <asm/emulate_prefix.h>
dd2cb348 72#include <clocksource/hyperv_timer.h>
043405e1 73
d1898b73
DH		 74#define CREATE_TRACE_POINTS
75#include "trace.h"
76
313a3dc7 77#define MAX_IO_MSRS 256
890ca9ae 78#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR		 79u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
80EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 81
0f65dd70
AK		 82#define emul_to_vcpu(ctxt) \
83 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
84
50a37eb4
JR		 85/* EFER defaults:
86 * - enable syscall per default because its emulated by KVM
87 * - enable LME and LMA per default on 64 bit KVM
88 */
89#ifdef CONFIG_X86_64
1260edbe
LJ		 90static
91u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 92#else
1260edbe 93static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 94#endif
313a3dc7 95
b11306b5
SC		 96static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
97
833b45de
PB		 98#define VM_STAT(x, ...) offsetof(struct kvm, stat.x), KVM_STAT_VM, ## __VA_ARGS__
99#define VCPU_STAT(x, ...) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU, ## __VA_ARGS__
417bc304 100
c519265f
RK		 101#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
102 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 103
cb142eb7 104static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 105static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 106static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 107static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
01643c51
KH		 108static void store_regs(struct kvm_vcpu *vcpu);
109static int sync_regs(struct kvm_vcpu *vcpu);
674eea0f 110
893590c7 111struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 112EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 113
893590c7 114static bool __read_mostly ignore_msrs = 0;
476bc001 115module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 116
fab0aa3b
EM		 117static bool __read_mostly report_ignored_msrs = true;
118module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
119
4c27625b 120unsigned int min_timer_period_us = 200;
9ed96e87
MT		 121module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
122
630994b3
MT		 123static bool __read_mostly kvmclock_periodic_sync = true;
124module_param(kvmclock_periodic_sync, bool, S_IRUGO);
125
893590c7 126bool __read_mostly kvm_has_tsc_control;
92a1f12d 127EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 128u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 129EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ		 130u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
131EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
132u64 __read_mostly kvm_max_tsc_scaling_ratio;
133EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ		 134u64 __read_mostly kvm_default_tsc_scaling_ratio;
135EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 136
cc578287 137/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 138static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA		 139module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
140
c3941d9e
SC		 141/*
142 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
143 * adaptive tuning starting from default advancment of 1000ns. '0' disables
144 * advancement entirely. Any other value is used as-is and disables adaptive
145 * tuning, i.e. allows priveleged userspace to set an exact advancement time.
146 */
147static int __read_mostly lapic_timer_advance_ns = -1;
0e6edceb 148module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
d0659d94 149
52004014
FW		 150static bool __read_mostly vector_hashing = true;
151module_param(vector_hashing, bool, S_IRUGO);
152
c4ae60e4
LA		 153bool __read_mostly enable_vmware_backdoor = false;
154module_param(enable_vmware_backdoor, bool, S_IRUGO);
155EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
156
6c86eedc
WL		 157static bool __read_mostly force_emulation_prefix = false;
158module_param(force_emulation_prefix, bool, S_IRUGO);
159
0c5f81da
WL		 160int __read_mostly pi_inject_timer = -1;
161module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
162
18863bdd
AK		 163#define KVM_NR_SHARED_MSRS 16
164
165struct kvm_shared_msrs_global {
166 int nr;
2bf78fa7 167 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 168};
169
170struct kvm_shared_msrs {
171 struct user_return_notifier urn;
172 bool registered;
2bf78fa7
SY		 173 struct kvm_shared_msr_values {
174 u64 host;
175 u64 curr;
176 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 177};
178
179static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 180static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 181
139a12cf
AL		 182static u64 __read_mostly host_xss;
183
417bc304 184struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 185 { "pf_fixed", VCPU_STAT(pf_fixed) },
186 { "pf_guest", VCPU_STAT(pf_guest) },
187 { "tlb_flush", VCPU_STAT(tlb_flush) },
188 { "invlpg", VCPU_STAT(invlpg) },
189 { "exits", VCPU_STAT(exits) },
190 { "io_exits", VCPU_STAT(io_exits) },
191 { "mmio_exits", VCPU_STAT(mmio_exits) },
192 { "signal_exits", VCPU_STAT(signal_exits) },
193 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 194 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 195 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 196 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 197 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 198 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 199 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 200 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 201 { "request_irq", VCPU_STAT(request_irq_exits) },
202 { "irq_exits", VCPU_STAT(irq_exits) },
203 { "host_state_reload", VCPU_STAT(host_state_reload) },
ba1389b7
AK		 204 { "fpu_reload", VCPU_STAT(fpu_reload) },
205 { "insn_emulation", VCPU_STAT(insn_emulation) },
206 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 207 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 208 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 209 { "req_event", VCPU_STAT(req_event) },
c595ceee 210 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK		 211 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
212 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
213 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
214 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
215 { "mmu_flooded", VM_STAT(mmu_flooded) },
216 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 217 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 218 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 219 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
833b45de 220 { "largepages", VM_STAT(lpages, .mode = 0444) },
b8e8c830 221 { "nx_largepages_splitted", VM_STAT(nx_lpage_splits, .mode = 0444) },
f3414bc7
DM		 222 { "max_mmu_page_hash_collisions",
223 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB		 224 { NULL }
225};
226
2acf923e
DC		 227u64 __read_mostly host_xcr0;
228
b666a4b6
MO		 229struct kmem_cache *x86_fpu_cache;
230EXPORT_SYMBOL_GPL(x86_fpu_cache);
231
b6785def 232static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 233
af585b92
GN		 234static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
235{
236 int i;
237 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
238 vcpu->arch.apf.gfns[i] = ~0;
239}
240
18863bdd
AK		 241static void kvm_on_user_return(struct user_return_notifier *urn)
242{
243 unsigned slot;
18863bdd
AK		 244 struct kvm_shared_msrs *locals
245 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 246 struct kvm_shared_msr_values *values;
1650b4eb
IA		 247 unsigned long flags;
248
249 /*
250 * Disabling irqs at this point since the following code could be
251 * interrupted and executed through kvm_arch_hardware_disable()
252 */
253 local_irq_save(flags);
254 if (locals->registered) {
255 locals->registered = false;
256 user_return_notifier_unregister(urn);
257 }
258 local_irq_restore(flags);
18863bdd 259 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 260 values = &locals->values[slot];
261 if (values->host != values->curr) {
262 wrmsrl(shared_msrs_global.msrs[slot], values->host);
263 values->curr = values->host;
18863bdd
AK		 264 }
265 }
18863bdd
AK		 266}
267
2bf78fa7
SY		 268void kvm_define_shared_msr(unsigned slot, u32 msr)
269{
0123be42 270 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 271 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK		 272 if (slot >= shared_msrs_global.nr)
273 shared_msrs_global.nr = slot + 1;
18863bdd
AK		 274}
275EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
276
277static void kvm_shared_msr_cpu_online(void)
278{
05c19c2f
SC		 279 unsigned int cpu = smp_processor_id();
280 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
281 u64 value;
282 int i;
18863bdd 283
05c19c2f
SC		 284 for (i = 0; i < shared_msrs_global.nr; ++i) {
285 rdmsrl_safe(shared_msrs_global.msrs[i], &value);
286 smsr->values[i].host = value;
287 smsr->values[i].curr = value;
288 }
18863bdd
AK		 289}
290
8b3c3104 291int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 292{
013f6a5d
MT		 293 unsigned int cpu = smp_processor_id();
294 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 295 int err;
18863bdd 296
de1fca5d
PB		 297 value = (value & mask) | (smsr->values[slot].host & ~mask);
298 if (value == smsr->values[slot].curr)
8b3c3104 299 return 0;
8b3c3104
AH		 300 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
301 if (err)
302 return 1;
303
de1fca5d 304 smsr->values[slot].curr = value;
18863bdd
AK		 305 if (!smsr->registered) {
306 smsr->urn.on_user_return = kvm_on_user_return;
307 user_return_notifier_register(&smsr->urn);
308 smsr->registered = true;
309 }
8b3c3104 310 return 0;
18863bdd
AK		 311}
312EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
313
13a34e06 314static void drop_user_return_notifiers(void)
3548bab5 315{
013f6a5d
MT		 316 unsigned int cpu = smp_processor_id();
317 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 318
319 if (smsr->registered)
320 kvm_on_user_return(&smsr->urn);
321}
322
6866b83e
CO		 323u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
324{
8a5a87d9 325 return vcpu->arch.apic_base;
6866b83e
CO		 326}
327EXPORT_SYMBOL_GPL(kvm_get_apic_base);
328
58871649
JM		 329enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
330{
331 return kvm_apic_mode(kvm_get_apic_base(vcpu));
332}
333EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
334
58cb628d
JK		 335int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
336{
58871649
JM		 337 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
338 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
d6321d49
RK		 339 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
340 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 341
58871649 342 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
58cb628d 343 return 1;
58871649
JM		 344 if (!msr_info->host_initiated) {
345 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
346 return 1;
347 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
348 return 1;
349 }
58cb628d
JK		 350
351 kvm_lapic_set_base(vcpu, msr_info->data);
352 return 0;
6866b83e
CO		 353}
354EXPORT_SYMBOL_GPL(kvm_set_apic_base);
355
2605fc21 356asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 357{
358 /* Fault while not rebooting. We want the trace. */
b4fdcf60 359 BUG_ON(!kvm_rebooting);
e3ba45b8
GL		 360}
361EXPORT_SYMBOL_GPL(kvm_spurious_fault);
362
3fd28fce
ED		 363#define EXCPT_BENIGN 0
364#define EXCPT_CONTRIBUTORY 1
365#define EXCPT_PF 2
366
367static int exception_class(int vector)
368{
369 switch (vector) {
370 case PF_VECTOR:
371 return EXCPT_PF;
372 case DE_VECTOR:
373 case TS_VECTOR:
374 case NP_VECTOR:
375 case SS_VECTOR:
376 case GP_VECTOR:
377 return EXCPT_CONTRIBUTORY;
378 default:
379 break;
380 }
381 return EXCPT_BENIGN;
382}
383
d6e8c854
NA		 384#define EXCPT_FAULT 0
385#define EXCPT_TRAP 1
386#define EXCPT_ABORT 2
387#define EXCPT_INTERRUPT 3
388
389static int exception_type(int vector)
390{
391 unsigned int mask;
392
393 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
394 return EXCPT_INTERRUPT;
395
396 mask = 1 << vector;
397
398 /* #DB is trap, as instruction watchpoints are handled elsewhere */
399 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
400 return EXCPT_TRAP;
401
402 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
403 return EXCPT_ABORT;
404
405 /* Reserved exceptions will result in fault */
406 return EXCPT_FAULT;
407}
408
da998b46
JM		 409void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu)
410{
411 unsigned nr = vcpu->arch.exception.nr;
412 bool has_payload = vcpu->arch.exception.has_payload;
413 unsigned long payload = vcpu->arch.exception.payload;
414
415 if (!has_payload)
416 return;
417
418 switch (nr) {
f10c729f
JM		 419 case DB_VECTOR:
420 /*
421 * "Certain debug exceptions may clear bit 0-3. The
422 * remaining contents of the DR6 register are never
423 * cleared by the processor".
424 */
425 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
426 /*
427 * DR6.RTM is set by all #DB exceptions that don't clear it.
428 */
429 vcpu->arch.dr6 |= DR6_RTM;
430 vcpu->arch.dr6 |= payload;
431 /*
432 * Bit 16 should be set in the payload whenever the #DB
433 * exception should clear DR6.RTM. This makes the payload
434 * compatible with the pending debug exceptions under VMX.
435 * Though not currently documented in the SDM, this also
436 * makes the payload compatible with the exit qualification
437 * for #DB exceptions under VMX.
438 */
439 vcpu->arch.dr6 ^= payload & DR6_RTM;
440 break;
da998b46
JM		 441 case PF_VECTOR:
442 vcpu->arch.cr2 = payload;
443 break;
444 }
445
446 vcpu->arch.exception.has_payload = false;
447 vcpu->arch.exception.payload = 0;
448}
449EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
450
3fd28fce 451static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4 452 unsigned nr, bool has_error, u32 error_code,
91e86d22 453 bool has_payload, unsigned long payload, bool reinject)
3fd28fce
ED		 454{
455 u32 prev_nr;
456 int class1, class2;
457
3842d135
AK		 458 kvm_make_request(KVM_REQ_EVENT, vcpu);
459
664f8e26 460 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 461 queue:
3ffb2468
NA		 462 if (has_error && !is_protmode(vcpu))
463 has_error = false;
664f8e26
WL		 464 if (reinject) {
465 /*
466 * On vmentry, vcpu->arch.exception.pending is only
467 * true if an event injection was blocked by
468 * nested_run_pending. In that case, however,
469 * vcpu_enter_guest requests an immediate exit,
470 * and the guest shouldn't proceed far enough to
471 * need reinjection.
472 */
473 WARN_ON_ONCE(vcpu->arch.exception.pending);
474 vcpu->arch.exception.injected = true;
91e86d22
JM		 475 if (WARN_ON_ONCE(has_payload)) {
476 /*
477 * A reinjected event has already
478 * delivered its payload.
479 */
480 has_payload = false;
481 payload = 0;
482 }
664f8e26
WL		 483 } else {
484 vcpu->arch.exception.pending = true;
485 vcpu->arch.exception.injected = false;
486 }
3fd28fce
ED		 487 vcpu->arch.exception.has_error_code = has_error;
488 vcpu->arch.exception.nr = nr;
489 vcpu->arch.exception.error_code = error_code;
91e86d22
JM		 490 vcpu->arch.exception.has_payload = has_payload;
491 vcpu->arch.exception.payload = payload;
da998b46
JM		 492 /*
493 * In guest mode, payload delivery should be deferred,
494 * so that the L1 hypervisor can intercept #PF before
f10c729f
JM		 495 * CR2 is modified (or intercept #DB before DR6 is
496 * modified under nVMX). However, for ABI
497 * compatibility with KVM_GET_VCPU_EVENTS and
498 * KVM_SET_VCPU_EVENTS, we can't delay payload
499 * delivery unless userspace has enabled this
500 * functionality via the per-VM capability,
501 * KVM_CAP_EXCEPTION_PAYLOAD.
da998b46
JM		 502 */
503 if (!vcpu->kvm->arch.exception_payload_enabled ||
504 !is_guest_mode(vcpu))
505 kvm_deliver_exception_payload(vcpu);
3fd28fce
ED		 506 return;
507 }
508
509 /* to check exception */
510 prev_nr = vcpu->arch.exception.nr;
511 if (prev_nr == DF_VECTOR) {
512 /* triple fault -> shutdown */
a8eeb04a 513 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 514 return;
515 }
516 class1 = exception_class(prev_nr);
517 class2 = exception_class(nr);
518 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
519 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL		 520 /*
521 * Generate double fault per SDM Table 5-5. Set
522 * exception.pending = true so that the double fault
523 * can trigger a nested vmexit.
524 */
3fd28fce 525 vcpu->arch.exception.pending = true;
664f8e26 526 vcpu->arch.exception.injected = false;
3fd28fce
ED		 527 vcpu->arch.exception.has_error_code = true;
528 vcpu->arch.exception.nr = DF_VECTOR;
529 vcpu->arch.exception.error_code = 0;
c851436a
JM		 530 vcpu->arch.exception.has_payload = false;
531 vcpu->arch.exception.payload = 0;
3fd28fce
ED		 532 } else
533 /* replace previous exception with a new one in a hope
534 that instruction re-execution will regenerate lost
535 exception */
536 goto queue;
537}
538
298101da
AK		 539void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
540{
91e86d22 541 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
298101da
AK		 542}
543EXPORT_SYMBOL_GPL(kvm_queue_exception);
544
ce7ddec4
JR		 545void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
546{
91e86d22 547 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
ce7ddec4
JR		 548}
549EXPORT_SYMBOL_GPL(kvm_requeue_exception);
550
f10c729f
JM		 551static void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
552 unsigned long payload)
553{
554 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
555}
556
da998b46
JM		 557static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
558 u32 error_code, unsigned long payload)
559{
560 kvm_multiple_exception(vcpu, nr, true, error_code,
561 true, payload, false);
562}
563
6affcbed 564int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 565{
db8fcefa
AP		 566 if (err)
567 kvm_inject_gp(vcpu, 0);
568 else
6affcbed
KH		 569 return kvm_skip_emulated_instruction(vcpu);
570
571 return 1;
db8fcefa
AP		 572}
573EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 574
6389ee94 575void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 576{
577 ++vcpu->stat.pf_guest;
adfe20fb
WL		 578 vcpu->arch.exception.nested_apf =
579 is_guest_mode(vcpu) && fault->async_page_fault;
da998b46 580 if (vcpu->arch.exception.nested_apf) {
adfe20fb 581 vcpu->arch.apf.nested_apf_token = fault->address;
da998b46
JM		 582 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
583 } else {
584 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
585 fault->address);
586 }
c3c91fee 587}
27d6c865 588EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 589
ef54bcfe 590static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 591{
6389ee94
AK		 592 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
593 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 594 else
44dd3ffa 595 vcpu->arch.mmu->inject_page_fault(vcpu, fault);
ef54bcfe
PB		 596
597 return fault->nested_page_fault;
d4f8cf66
JR		 598}
599
3419ffc8
SY		 600void kvm_inject_nmi(struct kvm_vcpu *vcpu)
601{
7460fb4a
AK		 602 atomic_inc(&vcpu->arch.nmi_queued);
603 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 604}
605EXPORT_SYMBOL_GPL(kvm_inject_nmi);
606
298101da
AK		 607void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
608{
91e86d22 609 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
298101da
AK		 610}
611EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
612
ce7ddec4
JR		 613void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
614{
91e86d22 615 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
ce7ddec4
JR		 616}
617EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
618
0a79b009
AK		 619/*
620 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
621 * a #GP and return false.
622 */
623bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 624{
0a79b009
AK		 625 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
626 return true;
627 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
628 return false;
298101da 629}
0a79b009 630EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 631
16f8a6f9
NA		 632bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
633{
634 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
635 return true;
636
637 kvm_queue_exception(vcpu, UD_VECTOR);
638 return false;
639}
640EXPORT_SYMBOL_GPL(kvm_require_dr);
641
ec92fe44
JR		 642/*
643 * This function will be used to read from the physical memory of the currently
54bf36aa 644 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 645 * can read from guest physical or from the guest's guest physical memory.
646 */
647int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
648 gfn_t ngfn, void *data, int offset, int len,
649 u32 access)
650{
54987b7a 651 struct x86_exception exception;
ec92fe44
JR		 652 gfn_t real_gfn;
653 gpa_t ngpa;
654
655 ngpa = gfn_to_gpa(ngfn);
54987b7a 656 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 657 if (real_gfn == UNMAPPED_GVA)
658 return -EFAULT;
659
660 real_gfn = gpa_to_gfn(real_gfn);
661
54bf36aa 662 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 663}
664EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
665
69b0049a 666static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 667 void *data, int offset, int len, u32 access)
668{
669 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
670 data, offset, len, access);
671}
672
16cfacc8
SC		 673static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
674{
675 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63) | rsvd_bits(5, 8) |
676 rsvd_bits(1, 2);
677}
678
a03490ed 679/*
16cfacc8 680 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
a03490ed 681 */
ff03a073 682int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 683{
684 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
685 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
686 int i;
687 int ret;
ff03a073 688 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 689
ff03a073
JR		 690 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
691 offset * sizeof(u64), sizeof(pdpte),
692 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 693 if (ret < 0) {
694 ret = 0;
695 goto out;
696 }
697 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 698 if ((pdpte[i] & PT_PRESENT_MASK) &&
16cfacc8 699 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
a03490ed
CO		 700 ret = 0;
701 goto out;
702 }
703 }
704 ret = 1;
705
ff03a073 706 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
cb3c1e2f
SC		 707 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
708
a03490ed 709out:
a03490ed
CO		 710
711 return ret;
712}
cc4b6871 713EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 714
9ed38ffa 715bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 716{
ff03a073 717 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
3d06b8bf
JR		 718 int offset;
719 gfn_t gfn;
d835dfec
AK		 720 int r;
721
bf03d4f9 722 if (!is_pae_paging(vcpu))
d835dfec
AK		 723 return false;
724
cb3c1e2f 725 if (!kvm_register_is_available(vcpu, VCPU_EXREG_PDPTR))
6de4f3ad
AK		 726 return true;
727
a512177e
PB		 728 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
729 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR		 730 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
731 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec 732 if (r < 0)
7f7f0d9c 733 return true;
d835dfec 734
7f7f0d9c 735 return memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 736}
9ed38ffa 737EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 738
49a9b07e 739int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 740{
aad82703 741 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 742 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 743
f9a48e6a
AK		 744 cr0 |= X86_CR0_ET;
745
ab344828 746#ifdef CONFIG_X86_64
0f12244f
GN		 747 if (cr0 & 0xffffffff00000000UL)
748 return 1;
ab344828
GN		 749#endif
750
751 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 752
0f12244f
GN		 753 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
754 return 1;
a03490ed 755
0f12244f
GN		 756 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
757 return 1;
a03490ed
CO		 758
759 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
760#ifdef CONFIG_X86_64
f6801dff 761 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 762 int cs_db, cs_l;
763
0f12244f
GN		 764 if (!is_pae(vcpu))
765 return 1;
a03490ed 766 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 767 if (cs_l)
768 return 1;
a03490ed
CO		 769 } else
770#endif
ff03a073 771 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 772 kvm_read_cr3(vcpu)))
0f12244f 773 return 1;
a03490ed
CO		 774 }
775
ad756a16
MJ		 776 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
777 return 1;
778
a03490ed 779 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 780
d170c419 781 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 782 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 783 kvm_async_pf_hash_reset(vcpu);
784 }
e5f3f027 785
aad82703
SY		 786 if ((cr0 ^ old_cr0) & update_bits)
787 kvm_mmu_reset_context(vcpu);
b18d5431 788
879ae188
LE		 789 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
790 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
791 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG		 792 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
793
0f12244f
GN		 794 return 0;
795}
2d3ad1f4 796EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 797
2d3ad1f4 798void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 799{
49a9b07e 800 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 801}
2d3ad1f4 802EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 803
139a12cf 804void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
42bdf991 805{
139a12cf
AL		 806 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
807
808 if (vcpu->arch.xcr0 != host_xcr0)
809 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
810
811 if (vcpu->arch.xsaves_enabled &&
812 vcpu->arch.ia32_xss != host_xss)
813 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
814 }
42bdf991 815}
139a12cf 816EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
42bdf991 817
139a12cf 818void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
42bdf991 819{
139a12cf
AL		 820 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
821
822 if (vcpu->arch.xcr0 != host_xcr0)
823 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
824
825 if (vcpu->arch.xsaves_enabled &&
826 vcpu->arch.ia32_xss != host_xss)
827 wrmsrl(MSR_IA32_XSS, host_xss);
828 }
829
42bdf991 830}
139a12cf 831EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
42bdf991 832
69b0049a 833static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 834{
56c103ec
LJ		 835 u64 xcr0 = xcr;
836 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 837 u64 valid_bits;
2acf923e
DC		 838
839 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
840 if (index != XCR_XFEATURE_ENABLED_MASK)
841 return 1;
d91cab78 842 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 843 return 1;
d91cab78 844 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 845 return 1;
46c34cb0
PB		 846
847 /*
848 * Do not allow the guest to set bits that we do not support
849 * saving. However, xcr0 bit 0 is always set, even if the
850 * emulated CPU does not support XSAVE (see fx_init).
851 */
d91cab78 852 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 853 if (xcr0 & ~valid_bits)
2acf923e 854 return 1;
46c34cb0 855
d91cab78
DH		 856 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
857 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ		 858 return 1;
859
d91cab78
DH		 860 if (xcr0 & XFEATURE_MASK_AVX512) {
861 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 862 return 1;
d91cab78 863 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP		 864 return 1;
865 }
2acf923e 866 vcpu->arch.xcr0 = xcr0;
56c103ec 867
d91cab78 868 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 869 kvm_update_cpuid(vcpu);
2acf923e
DC		 870 return 0;
871}
872
873int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
874{
764bcbc5
Z		 875 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
876 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 877 kvm_inject_gp(vcpu, 0);
878 return 1;
879 }
880 return 0;
881}
882EXPORT_SYMBOL_GPL(kvm_set_xcr);
883
345599f9
SC		 884#define __cr4_reserved_bits(__cpu_has, __c) \
885({ \
886 u64 __reserved_bits = CR4_RESERVED_BITS; \
887 \
888 if (!__cpu_has(__c, X86_FEATURE_XSAVE)) \
889 __reserved_bits |= X86_CR4_OSXSAVE; \
890 if (!__cpu_has(__c, X86_FEATURE_SMEP)) \
891 __reserved_bits |= X86_CR4_SMEP; \
892 if (!__cpu_has(__c, X86_FEATURE_SMAP)) \
893 __reserved_bits |= X86_CR4_SMAP; \
894 if (!__cpu_has(__c, X86_FEATURE_FSGSBASE)) \
895 __reserved_bits |= X86_CR4_FSGSBASE; \
896 if (!__cpu_has(__c, X86_FEATURE_PKU)) \
897 __reserved_bits |= X86_CR4_PKE; \
898 if (!__cpu_has(__c, X86_FEATURE_LA57)) \
899 __reserved_bits |= X86_CR4_LA57; \
900 __reserved_bits; \
901})
a03490ed 902
b11306b5
SC		 903static u64 kvm_host_cr4_reserved_bits(struct cpuinfo_x86 *c)
904{
345599f9 905 u64 reserved_bits = __cr4_reserved_bits(cpu_has, c);
2acf923e 906
87382003 907 if (cpuid_ecx(0x7) & feature_bit(LA57))
345599f9 908 reserved_bits &= ~X86_CR4_LA57;
c68b734f 909
345599f9
SC		 910 if (kvm_x86_ops->umip_emulated())
911 reserved_bits &= ~X86_CR4_UMIP;
97ec8c06 912
b11306b5
SC		 913 return reserved_bits;
914}
74dc2b4f 915
3ca94192 916static int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 917{
b11306b5 918 if (cr4 & cr4_reserved_bits)
3ca94192 919 return -EINVAL;
b9baba86 920
345599f9 921 if (cr4 & __cr4_reserved_bits(guest_cpuid_has, vcpu))
3ca94192
WL		 922 return -EINVAL;
923
924 return 0;
925}
926
927int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
928{
929 unsigned long old_cr4 = kvm_read_cr4(vcpu);
930 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
931 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
932
933 if (kvm_valid_cr4(vcpu, cr4))
ae3e61e1
PB		 934 return 1;
935
a03490ed 936 if (is_long_mode(vcpu)) {
0f12244f
GN		 937 if (!(cr4 & X86_CR4_PAE))
938 return 1;
a2edf57f
AK		 939 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
940 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 941 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
942 kvm_read_cr3(vcpu)))
0f12244f
GN		 943 return 1;
944
ad756a16 945 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 946 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ		 947 return 1;
948
949 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
950 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
951 return 1;
952 }
953
5e1746d6 954 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 955 return 1;
a03490ed 956
ad756a16
MJ		 957 if (((cr4 ^ old_cr4) & pdptr_bits) ||
958 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 959 kvm_mmu_reset_context(vcpu);
0f12244f 960
b9baba86 961 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 962 kvm_update_cpuid(vcpu);
2acf923e 963
0f12244f
GN		 964 return 0;
965}
2d3ad1f4 966EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 967
2390218b 968int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 969{
ade61e28 970 bool skip_tlb_flush = false;
ac146235 971#ifdef CONFIG_X86_64
c19986fe
JS		 972 bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
973
ade61e28 974 if (pcid_enabled) {
208320ba
JS		 975 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
976 cr3 &= ~X86_CR3_PCID_NOFLUSH;
ade61e28 977 }
ac146235 978#endif
9d88fca7 979
9f8fe504 980 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
956bf353
JS		 981 if (!skip_tlb_flush) {
982 kvm_mmu_sync_roots(vcpu);
ade61e28 983 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
956bf353 984 }
0f12244f 985 return 0;
d835dfec
AK		 986 }
987
d1cd3ce9 988 if (is_long_mode(vcpu) &&
a780a3ea 989 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 63)))
d1cd3ce9 990 return 1;
bf03d4f9
PB		 991 else if (is_pae_paging(vcpu) &&
992 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 993 return 1;
a03490ed 994
ade61e28 995 kvm_mmu_new_cr3(vcpu, cr3, skip_tlb_flush);
0f12244f 996 vcpu->arch.cr3 = cr3;
cb3c1e2f 997 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
7c390d35 998
0f12244f
GN		 999 return 0;
1000}
2d3ad1f4 1001EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 1002
eea1cff9 1003int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 1004{
0f12244f
GN		 1005 if (cr8 & CR8_RESERVED_BITS)
1006 return 1;
35754c98 1007 if (lapic_in_kernel(vcpu))
a03490ed
CO		 1008 kvm_lapic_set_tpr(vcpu, cr8);
1009 else
ad312c7c 1010 vcpu->arch.cr8 = cr8;
0f12244f
GN		 1011 return 0;
1012}
2d3ad1f4 1013EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 1014
2d3ad1f4 1015unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 1016{
35754c98 1017 if (lapic_in_kernel(vcpu))
a03490ed
CO		 1018 return kvm_lapic_get_cr8(vcpu);
1019 else
ad312c7c 1020 return vcpu->arch.cr8;
a03490ed 1021}
2d3ad1f4 1022EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 1023
ae561ede
NA		 1024static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1025{
1026 int i;
1027
1028 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1029 for (i = 0; i < KVM_NR_DB_REGS; i++)
1030 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1031 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
1032 }
1033}
1034
73aaf249
JK		 1035static void kvm_update_dr6(struct kvm_vcpu *vcpu)
1036{
1037 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1038 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
1039}
1040
c8639010
JK		 1041static void kvm_update_dr7(struct kvm_vcpu *vcpu)
1042{
1043 unsigned long dr7;
1044
1045 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1046 dr7 = vcpu->arch.guest_debug_dr7;
1047 else
1048 dr7 = vcpu->arch.dr7;
1049 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 1050 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1051 if (dr7 & DR7_BP_EN_MASK)
1052 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 1053}
1054
6f43ed01
NA		 1055static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1056{
1057 u64 fixed = DR6_FIXED_1;
1058
d6321d49 1059 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA		 1060 fixed |= DR6_RTM;
1061 return fixed;
1062}
1063
338dbc97 1064static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079 1065{
ea740059
MP		 1066 size_t size = ARRAY_SIZE(vcpu->arch.db);
1067
020df079
GN		 1068 switch (dr) {
1069 case 0 ... 3:
ea740059 1070 vcpu->arch.db[array_index_nospec(dr, size)] = val;
020df079
GN		 1071 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1072 vcpu->arch.eff_db[dr] = val;
1073 break;
1074 case 4:
020df079
GN		 1075 /* fall through */
1076 case 6:
338dbc97
GN		 1077 if (val & 0xffffffff00000000ULL)
1078 return -1; /* #GP */
6f43ed01 1079 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 1080 kvm_update_dr6(vcpu);
020df079
GN		 1081 break;
1082 case 5:
020df079
GN		 1083 /* fall through */
1084 default: /* 7 */
b91991bf 1085 if (!kvm_dr7_valid(val))
338dbc97 1086 return -1; /* #GP */
020df079 1087 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 1088 kvm_update_dr7(vcpu);
020df079
GN		 1089 break;
1090 }
1091
1092 return 0;
1093}
338dbc97
GN		 1094
1095int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1096{
16f8a6f9 1097 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 1098 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 1099 return 1;
1100 }
1101 return 0;
338dbc97 1102}
020df079
GN		 1103EXPORT_SYMBOL_GPL(kvm_set_dr);
1104
16f8a6f9 1105int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079 1106{
ea740059
MP		 1107 size_t size = ARRAY_SIZE(vcpu->arch.db);
1108
020df079
GN		 1109 switch (dr) {
1110 case 0 ... 3:
ea740059 1111 *val = vcpu->arch.db[array_index_nospec(dr, size)];
020df079
GN		 1112 break;
1113 case 4:
020df079
GN		 1114 /* fall through */
1115 case 6:
73aaf249
JK		 1116 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1117 *val = vcpu->arch.dr6;
1118 else
1119 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 1120 break;
1121 case 5:
020df079
GN		 1122 /* fall through */
1123 default: /* 7 */
1124 *val = vcpu->arch.dr7;
1125 break;
1126 }
338dbc97
GN		 1127 return 0;
1128}
020df079
GN		 1129EXPORT_SYMBOL_GPL(kvm_get_dr);
1130
022cd0e8
AK		 1131bool kvm_rdpmc(struct kvm_vcpu *vcpu)
1132{
de3cd117 1133 u32 ecx = kvm_rcx_read(vcpu);
022cd0e8
AK		 1134 u64 data;
1135 int err;
1136
c6702c9d 1137 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK		 1138 if (err)
1139 return err;
de3cd117
SC		 1140 kvm_rax_write(vcpu, (u32)data);
1141 kvm_rdx_write(vcpu, data >> 32);
022cd0e8
AK		 1142 return err;
1143}
1144EXPORT_SYMBOL_GPL(kvm_rdpmc);
1145
043405e1
CO		 1146/*
1147 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1148 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1149 *
7a5ee6ed
CQ		 1150 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features)
1151 * extract the supported MSRs from the related const lists.
1152 * msrs_to_save is selected from the msrs_to_save_all to reflect the
e3267cbb 1153 * capabilities of the host cpu. This capabilities test skips MSRs that are
7a5ee6ed 1154 * kvm-specific. Those are put in emulated_msrs_all; filtering of emulated_msrs
62ef68bb 1155 * may depend on host virtualization features rather than host cpu features.
043405e1 1156 */
e3267cbb 1157
7a5ee6ed 1158static const u32 msrs_to_save_all[] = {
043405e1 1159 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1160 MSR_STAR,
043405e1
CO		 1161#ifdef CONFIG_X86_64
1162 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1163#endif
b3897a49 1164 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
32ad73db 1165 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
2bdb76c0 1166 MSR_IA32_SPEC_CTRL,
bf8c55d8
CP		 1167 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1168 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1169 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1170 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1171 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1172 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
6e3ba4ab
TX		 1173 MSR_IA32_UMWAIT_CONTROL,
1174
e2ada66e
JM		 1175 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1176 MSR_ARCH_PERFMON_FIXED_CTR0 + 2, MSR_ARCH_PERFMON_FIXED_CTR0 + 3,
1177 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1178 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1179 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1180 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1181 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1182 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1183 MSR_ARCH_PERFMON_PERFCTR0 + 8, MSR_ARCH_PERFMON_PERFCTR0 + 9,
1184 MSR_ARCH_PERFMON_PERFCTR0 + 10, MSR_ARCH_PERFMON_PERFCTR0 + 11,
1185 MSR_ARCH_PERFMON_PERFCTR0 + 12, MSR_ARCH_PERFMON_PERFCTR0 + 13,
1186 MSR_ARCH_PERFMON_PERFCTR0 + 14, MSR_ARCH_PERFMON_PERFCTR0 + 15,
1187 MSR_ARCH_PERFMON_PERFCTR0 + 16, MSR_ARCH_PERFMON_PERFCTR0 + 17,
e2ada66e
JM		 1188 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1189 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1190 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1191 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1192 MSR_ARCH_PERFMON_EVENTSEL0 + 8, MSR_ARCH_PERFMON_EVENTSEL0 + 9,
1193 MSR_ARCH_PERFMON_EVENTSEL0 + 10, MSR_ARCH_PERFMON_EVENTSEL0 + 11,
1194 MSR_ARCH_PERFMON_EVENTSEL0 + 12, MSR_ARCH_PERFMON_EVENTSEL0 + 13,
1195 MSR_ARCH_PERFMON_EVENTSEL0 + 14, MSR_ARCH_PERFMON_EVENTSEL0 + 15,
1196 MSR_ARCH_PERFMON_EVENTSEL0 + 16, MSR_ARCH_PERFMON_EVENTSEL0 + 17,
043405e1
CO		 1197};
1198
7a5ee6ed 1199static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_all)];
043405e1
CO		 1200static unsigned num_msrs_to_save;
1201
7a5ee6ed 1202static const u32 emulated_msrs_all[] = {
62ef68bb
PB		 1203 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1204 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1205 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1206 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1207 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS		 1208 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1209 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1210 HV_X64_MSR_RESET,
11c4b1ca 1211 HV_X64_MSR_VP_INDEX,
9eec50b8 1212 HV_X64_MSR_VP_RUNTIME,
5c919412 1213 HV_X64_MSR_SCONTROL,
1f4b34f8 1214 HV_X64_MSR_STIMER0_CONFIG,
d4abc577 1215 HV_X64_MSR_VP_ASSIST_PAGE,
a2e164e7
VK		 1216 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1217 HV_X64_MSR_TSC_EMULATION_STATUS,
1218
1219 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
62ef68bb
PB		 1220 MSR_KVM_PV_EOI_EN,
1221
ba904635 1222 MSR_IA32_TSC_ADJUST,
a3e06bbe 1223 MSR_IA32_TSCDEADLINE,
2bdb76c0 1224 MSR_IA32_ARCH_CAPABILITIES,
043405e1 1225 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 1226 MSR_IA32_MCG_STATUS,
1227 MSR_IA32_MCG_CTL,
c45dcc71 1228 MSR_IA32_MCG_EXT_CTL,
64d60670 1229 MSR_IA32_SMBASE,
52797bf9 1230 MSR_SMI_COUNT,
db2336a8
KH		 1231 MSR_PLATFORM_INFO,
1232 MSR_MISC_FEATURES_ENABLES,
bc226f07 1233 MSR_AMD64_VIRT_SPEC_CTRL,
6c6a2ab9 1234 MSR_IA32_POWER_CTL,
99634e3e 1235 MSR_IA32_UCODE_REV,
191c8137 1236
95c5c7c7
PB		 1237 /*
1238 * The following list leaves out MSRs whose values are determined
1239 * by arch/x86/kvm/vmx/nested.c based on CPUID or other MSRs.
1240 * We always support the "true" VMX control MSRs, even if the host
1241 * processor does not, so I am putting these registers here rather
7a5ee6ed 1242 * than in msrs_to_save_all.
95c5c7c7
PB		 1243 */
1244 MSR_IA32_VMX_BASIC,
1245 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1246 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1247 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1248 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1249 MSR_IA32_VMX_MISC,
1250 MSR_IA32_VMX_CR0_FIXED0,
1251 MSR_IA32_VMX_CR4_FIXED0,
1252 MSR_IA32_VMX_VMCS_ENUM,
1253 MSR_IA32_VMX_PROCBASED_CTLS2,
1254 MSR_IA32_VMX_EPT_VPID_CAP,
1255 MSR_IA32_VMX_VMFUNC,
1256
191c8137 1257 MSR_K7_HWCR,
2d5ba19b 1258 MSR_KVM_POLL_CONTROL,
043405e1
CO		 1259};
1260
7a5ee6ed 1261static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
62ef68bb
PB		 1262static unsigned num_emulated_msrs;
1263
801e459a
TL		 1264/*
1265 * List of msr numbers which are used to expose MSR-based features that
1266 * can be used by a hypervisor to validate requested CPU features.
1267 */
7a5ee6ed 1268static const u32 msr_based_features_all[] = {
1389309c
PB		 1269 MSR_IA32_VMX_BASIC,
1270 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1271 MSR_IA32_VMX_PINBASED_CTLS,
1272 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1273 MSR_IA32_VMX_PROCBASED_CTLS,
1274 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1275 MSR_IA32_VMX_EXIT_CTLS,
1276 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1277 MSR_IA32_VMX_ENTRY_CTLS,
1278 MSR_IA32_VMX_MISC,
1279 MSR_IA32_VMX_CR0_FIXED0,
1280 MSR_IA32_VMX_CR0_FIXED1,
1281 MSR_IA32_VMX_CR4_FIXED0,
1282 MSR_IA32_VMX_CR4_FIXED1,
1283 MSR_IA32_VMX_VMCS_ENUM,
1284 MSR_IA32_VMX_PROCBASED_CTLS2,
1285 MSR_IA32_VMX_EPT_VPID_CAP,
1286 MSR_IA32_VMX_VMFUNC,
1287
d1d93fa9 1288 MSR_F10H_DECFG,
518e7b94 1289 MSR_IA32_UCODE_REV,
cd283252 1290 MSR_IA32_ARCH_CAPABILITIES,
801e459a
TL		 1291};
1292
7a5ee6ed 1293static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all)];
801e459a
TL		 1294static unsigned int num_msr_based_features;
1295
4d22c17c 1296static u64 kvm_get_arch_capabilities(void)
5b76a3cf 1297{
4d22c17c 1298 u64 data = 0;
5b76a3cf 1299
4d22c17c
XL		 1300 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1301 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, data);
5b76a3cf 1302
b8e8c830
PB		 1303 /*
1304 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1305 * the nested hypervisor runs with NX huge pages. If it is not,
1306 * L1 is anyway vulnerable to ITLB_MULTIHIT explots from other
1307 * L1 guests, so it need not worry about its own (L2) guests.
1308 */
1309 data |= ARCH_CAP_PSCHANGE_MC_NO;
1310
5b76a3cf
PB		 1311 /*
1312 * If we're doing cache flushes (either "always" or "cond")
1313 * we will do one whenever the guest does a vmlaunch/vmresume.
1314 * If an outer hypervisor is doing the cache flush for us
1315 * (VMENTER_L1D_FLUSH_NESTED_VM), we can safely pass that
1316 * capability to the guest too, and if EPT is disabled we're not
1317 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1318 * require a nested hypervisor to do a flush of its own.
1319 */
1320 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1321 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1322
0c54914d
PB		 1323 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1324 data |= ARCH_CAP_RDCL_NO;
1325 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1326 data |= ARCH_CAP_SSB_NO;
1327 if (!boot_cpu_has_bug(X86_BUG_MDS))
1328 data |= ARCH_CAP_MDS_NO;
1329
e1d38b63 1330 /*
c11f83e0
PB		 1331 * On TAA affected systems:
1332 * - nothing to do if TSX is disabled on the host.
1333 * - we emulate TSX_CTRL if present on the host.
1334 * This lets the guest use VERW to clear CPU buffers.
e1d38b63 1335 */
cbbaa272 1336 if (!boot_cpu_has(X86_FEATURE_RTM))
c11f83e0 1337 data &= ~(ARCH_CAP_TAA_NO | ARCH_CAP_TSX_CTRL_MSR);
cbbaa272
PB		 1338 else if (!boot_cpu_has_bug(X86_BUG_TAA))
1339 data |= ARCH_CAP_TAA_NO;
e1d38b63 1340
5b76a3cf
PB		 1341 return data;
1342}
5b76a3cf 1343
66421c1e
WL		 1344static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1345{
1346 switch (msr->index) {
cd283252 1347 case MSR_IA32_ARCH_CAPABILITIES:
5b76a3cf
PB		 1348 msr->data = kvm_get_arch_capabilities();
1349 break;
1350 case MSR_IA32_UCODE_REV:
cd283252 1351 rdmsrl_safe(msr->index, &msr->data);
518e7b94 1352 break;
66421c1e
WL		 1353 default:
1354 if (kvm_x86_ops->get_msr_feature(msr))
1355 return 1;
1356 }
1357 return 0;
1358}
1359
801e459a
TL		 1360static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1361{
1362 struct kvm_msr_entry msr;
66421c1e 1363 int r;
801e459a
TL		 1364
1365 msr.index = index;
66421c1e
WL		 1366 r = kvm_get_msr_feature(&msr);
1367 if (r)
1368 return r;
801e459a
TL		 1369
1370 *data = msr.data;
1371
1372 return 0;
1373}
1374
11988499 1375static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1376{
1b4d56b8 1377 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
11988499 1378 return false;
1b2fd70c 1379
1b4d56b8 1380 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
11988499 1381 return false;
d8017474 1382
0a629563
SC		 1383 if (efer & (EFER_LME | EFER_LMA) &&
1384 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1385 return false;
1386
1387 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1388 return false;
d8017474 1389
384bb783 1390 return true;
11988499
SC		 1391
1392}
1393bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1394{
1395 if (efer & efer_reserved_bits)
1396 return false;
1397
1398 return __kvm_valid_efer(vcpu, efer);
384bb783
JK		 1399}
1400EXPORT_SYMBOL_GPL(kvm_valid_efer);
1401
11988499 1402static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
384bb783
JK		 1403{
1404 u64 old_efer = vcpu->arch.efer;
11988499 1405 u64 efer = msr_info->data;
384bb783 1406
11988499 1407 if (efer & efer_reserved_bits)
66f61c92 1408 return 1;
384bb783 1409
11988499
SC		 1410 if (!msr_info->host_initiated) {
1411 if (!__kvm_valid_efer(vcpu, efer))
1412 return 1;
1413
1414 if (is_paging(vcpu) &&
1415 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1416 return 1;
1417 }
384bb783 1418
15c4a640 1419 efer &= ~EFER_LMA;
f6801dff 1420 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1421
a3d204e2
SY		 1422 kvm_x86_ops->set_efer(vcpu, efer);
1423
aad82703
SY		 1424 /* Update reserved bits */
1425 if ((efer ^ old_efer) & EFER_NX)
1426 kvm_mmu_reset_context(vcpu);
1427
b69e8cae 1428 return 0;
15c4a640
CO		 1429}
1430
f2b4b7dd
JR		 1431void kvm_enable_efer_bits(u64 mask)
1432{
1433 efer_reserved_bits &= ~mask;
1434}
1435EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1436
15c4a640 1437/*
f20935d8
SC		 1438 * Write @data into the MSR specified by @index. Select MSR specific fault
1439 * checks are bypassed if @host_initiated is %true.
15c4a640
CO		 1440 * Returns 0 on success, non-0 otherwise.
1441 * Assumes vcpu_load() was already called.
1442 */
f20935d8
SC		 1443static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1444 bool host_initiated)
15c4a640 1445{
f20935d8
SC		 1446 struct msr_data msr;
1447
1448 switch (index) {
854e8bb1
NA		 1449 case MSR_FS_BASE:
1450 case MSR_GS_BASE:
1451 case MSR_KERNEL_GS_BASE:
1452 case MSR_CSTAR:
1453 case MSR_LSTAR:
f20935d8 1454 if (is_noncanonical_address(data, vcpu))
854e8bb1
NA		 1455 return 1;
1456 break;
1457 case MSR_IA32_SYSENTER_EIP:
1458 case MSR_IA32_SYSENTER_ESP:
1459 /*
1460 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1461 * non-canonical address is written on Intel but not on
1462 * AMD (which ignores the top 32-bits, because it does
1463 * not implement 64-bit SYSENTER).
1464 *
1465 * 64-bit code should hence be able to write a non-canonical
1466 * value on AMD. Making the address canonical ensures that
1467 * vmentry does not fail on Intel after writing a non-canonical
1468 * value, and that something deterministic happens if the guest
1469 * invokes 64-bit SYSENTER.
1470 */
f20935d8 1471 data = get_canonical(data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1472 }
f20935d8
SC		 1473
1474 msr.data = data;
1475 msr.index = index;
1476 msr.host_initiated = host_initiated;
1477
1478 return kvm_x86_ops->set_msr(vcpu, &msr);
15c4a640
CO		 1479}
1480
313a3dc7 1481/*
f20935d8
SC		 1482 * Read the MSR specified by @index into @data. Select MSR specific fault
1483 * checks are bypassed if @host_initiated is %true.
1484 * Returns 0 on success, non-0 otherwise.
1485 * Assumes vcpu_load() was already called.
313a3dc7 1486 */
edef5c36
PB		 1487int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1488 bool host_initiated)
609e36d3
PB		 1489{
1490 struct msr_data msr;
f20935d8 1491 int ret;
609e36d3
PB		 1492
1493 msr.index = index;
f20935d8 1494 msr.host_initiated = host_initiated;
609e36d3 1495
f20935d8
SC		 1496 ret = kvm_x86_ops->get_msr(vcpu, &msr);
1497 if (!ret)
1498 *data = msr.data;
1499 return ret;
609e36d3
PB		 1500}
1501
f20935d8 1502int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
313a3dc7 1503{
f20935d8
SC		 1504 return __kvm_get_msr(vcpu, index, data, false);
1505}
1506EXPORT_SYMBOL_GPL(kvm_get_msr);
8fe8ab46 1507
f20935d8
SC		 1508int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1509{
1510 return __kvm_set_msr(vcpu, index, data, false);
1511}
1512EXPORT_SYMBOL_GPL(kvm_set_msr);
1513
1edce0a9
SC		 1514int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
1515{
1516 u32 ecx = kvm_rcx_read(vcpu);
1517 u64 data;
1518
1519 if (kvm_get_msr(vcpu, ecx, &data)) {
1520 trace_kvm_msr_read_ex(ecx);
1521 kvm_inject_gp(vcpu, 0);
1522 return 1;
1523 }
1524
1525 trace_kvm_msr_read(ecx, data);
1526
1527 kvm_rax_write(vcpu, data & -1u);
1528 kvm_rdx_write(vcpu, (data >> 32) & -1u);
1529 return kvm_skip_emulated_instruction(vcpu);
1530}
1531EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
1532
1533int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
1534{
1535 u32 ecx = kvm_rcx_read(vcpu);
1536 u64 data = kvm_read_edx_eax(vcpu);
1537
1538 if (kvm_set_msr(vcpu, ecx, data)) {
1539 trace_kvm_msr_write_ex(ecx, data);
1540 kvm_inject_gp(vcpu, 0);
1541 return 1;
1542 }
1543
1544 trace_kvm_msr_write(ecx, data);
1545 return kvm_skip_emulated_instruction(vcpu);
1546}
1547EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
1548
1e9e2622
WL		 1549/*
1550 * The fast path for frequent and performance sensitive wrmsr emulation,
1551 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
1552 * the latency of virtual IPI by avoiding the expensive bits of transitioning
1553 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
1554 * other cases which must be called after interrupts are enabled on the host.
1555 */
1556static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
1557{
1558 if (lapic_in_kernel(vcpu) && apic_x2apic_mode(vcpu->arch.apic) &&
1559 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
1560 ((data & APIC_MODE_MASK) == APIC_DM_FIXED)) {
1561
1562 kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32));
1563 return kvm_lapic_reg_write(vcpu->arch.apic, APIC_ICR, (u32)data);
1564 }
1565
1566 return 1;
1567}
1568
1569enum exit_fastpath_completion handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
1570{
1571 u32 msr = kvm_rcx_read(vcpu);
1572 u64 data = kvm_read_edx_eax(vcpu);
1573 int ret = 0;
1574
1575 switch (msr) {
1576 case APIC_BASE_MSR + (APIC_ICR >> 4):
1577 ret = handle_fastpath_set_x2apic_icr_irqoff(vcpu, data);
1578 break;
1579 default:
1580 return EXIT_FASTPATH_NONE;
1581 }
1582
1583 if (!ret) {
1584 trace_kvm_msr_write(msr, data);
1585 return EXIT_FASTPATH_SKIP_EMUL_INS;
1586 }
1587
1588 return EXIT_FASTPATH_NONE;
1589}
1590EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
1591
f20935d8
SC		 1592/*
1593 * Adapt set_msr() to msr_io()'s calling convention
1594 */
1595static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1596{
1597 return __kvm_get_msr(vcpu, index, data, true);
1598}
1599
1600static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1601{
1602 return __kvm_set_msr(vcpu, index, *data, true);
313a3dc7
CO		 1603}
1604
16e8d74d 1605#ifdef CONFIG_X86_64
53fafdbb
MT		 1606struct pvclock_clock {
1607 int vclock_mode;
1608 u64 cycle_last;
1609 u64 mask;
1610 u32 mult;
1611 u32 shift;
1612};
1613
16e8d74d
MT		 1614struct pvclock_gtod_data {
1615 seqcount_t seq;
1616
53fafdbb
MT		 1617 struct pvclock_clock clock; /* extract of a clocksource struct */
1618 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
16e8d74d 1619
53fafdbb 1620 u64 boot_ns_raw;
cbcf2dd3
TG		 1621 u64 boot_ns;
1622 u64 nsec_base;
55dd00a7 1623 u64 wall_time_sec;
53fafdbb 1624 u64 monotonic_raw_nsec;
16e8d74d
MT		 1625};
1626
1627static struct pvclock_gtod_data pvclock_gtod_data;
1628
1629static void update_pvclock_gtod(struct timekeeper *tk)
1630{
1631 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
53fafdbb 1632 u64 boot_ns, boot_ns_raw;
cbcf2dd3 1633
876e7881 1634 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
53fafdbb 1635 boot_ns_raw = ktime_to_ns(ktime_add(tk->tkr_raw.base, tk->offs_boot));
16e8d74d
MT		 1636
1637 write_seqcount_begin(&vdata->seq);
1638
1639 /* copy pvclock gtod data */
876e7881
PZ		 1640 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1641 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1642 vdata->clock.mask = tk->tkr_mono.mask;
1643 vdata->clock.mult = tk->tkr_mono.mult;
1644 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1645
53fafdbb
MT		 1646 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->archdata.vclock_mode;
1647 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
1648 vdata->raw_clock.mask = tk->tkr_raw.mask;
1649 vdata->raw_clock.mult = tk->tkr_raw.mult;
1650 vdata->raw_clock.shift = tk->tkr_raw.shift;
1651
cbcf2dd3 1652 vdata->boot_ns = boot_ns;
876e7881 1653 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1654
55dd00a7
MT		 1655 vdata->wall_time_sec = tk->xtime_sec;
1656
53fafdbb
MT		 1657 vdata->boot_ns_raw = boot_ns_raw;
1658 vdata->monotonic_raw_nsec = tk->tkr_raw.xtime_nsec;
1659
16e8d74d
MT		 1660 write_seqcount_end(&vdata->seq);
1661}
1662#endif
1663
bab5bb39
NK		 1664void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1665{
bab5bb39 1666 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
4d151bf3 1667 kvm_vcpu_kick(vcpu);
bab5bb39 1668}
16e8d74d 1669
18068523
GOC		 1670static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1671{
9ed3c444
AK		 1672 int version;
1673 int r;
50d0a0f9 1674 struct pvclock_wall_clock wc;
87aeb54f 1675 struct timespec64 boot;
18068523
GOC		 1676
1677 if (!wall_clock)
1678 return;
1679
9ed3c444
AK		 1680 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1681 if (r)
1682 return;
1683
1684 if (version & 1)
1685 ++version; /* first time write, random junk */
1686
1687 ++version;
18068523 1688
1dab1345
NK		 1689 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1690 return;
18068523 1691
50d0a0f9
GH		 1692 /*
1693 * The guest calculates current wall clock time by adding
34c238a1 1694 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1695 * wall clock specified here. guest system time equals host
1696 * system time for us, thus we must fill in host boot time here.
1697 */
87aeb54f 1698 getboottime64(&boot);
50d0a0f9 1699
4b648665 1700 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB		 1701 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1702 boot = timespec64_sub(boot, ts);
4b648665 1703 }
87aeb54f 1704 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH		 1705 wc.nsec = boot.tv_nsec;
1706 wc.version = version;
18068523
GOC		 1707
1708 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1709
1710 version++;
1711 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1712}
1713
50d0a0f9
GH		 1714static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1715{
b51012de
PB		 1716 do_shl32_div32(dividend, divisor);
1717 return dividend;
50d0a0f9
GH		 1718}
1719
3ae13faa 1720static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1721 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1722{
5f4e3f88 1723 uint64_t scaled64;
50d0a0f9
GH		 1724 int32_t shift = 0;
1725 uint64_t tps64;
1726 uint32_t tps32;
1727
3ae13faa
PB		 1728 tps64 = base_hz;
1729 scaled64 = scaled_hz;
50933623 1730 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1731 tps64 >>= 1;
1732 shift--;
1733 }
1734
1735 tps32 = (uint32_t)tps64;
50933623
JK		 1736 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1737 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1738 scaled64 >>= 1;
1739 else
1740 tps32 <<= 1;
50d0a0f9
GH		 1741 shift++;
1742 }
1743
5f4e3f88
ZA		 1744 *pshift = shift;
1745 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9
GH		 1746}
1747
d828199e 1748#ifdef CONFIG_X86_64
16e8d74d 1749static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1750#endif
16e8d74d 1751
c8076604 1752static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1753static unsigned long max_tsc_khz;
c8076604 1754
cc578287 1755static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1756{
cc578287
ZA		 1757 u64 v = (u64)khz * (1000000 + ppm);
1758 do_div(v, 1000000);
1759 return v;
1e993611
JR		 1760}
1761
381d585c
HZ		 1762static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1763{
1764 u64 ratio;
1765
1766 /* Guest TSC same frequency as host TSC? */
1767 if (!scale) {
1768 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1769 return 0;
1770 }
1771
1772 /* TSC scaling supported? */
1773 if (!kvm_has_tsc_control) {
1774 if (user_tsc_khz > tsc_khz) {
1775 vcpu->arch.tsc_catchup = 1;
1776 vcpu->arch.tsc_always_catchup = 1;
1777 return 0;
1778 } else {
3f16a5c3 1779 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
381d585c
HZ		 1780 return -1;
1781 }
1782 }
1783
1784 /* TSC scaling required - calculate ratio */
1785 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1786 user_tsc_khz, tsc_khz);
1787
1788 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
3f16a5c3
PB		 1789 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1790 user_tsc_khz);
381d585c
HZ		 1791 return -1;
1792 }
1793
1794 vcpu->arch.tsc_scaling_ratio = ratio;
1795 return 0;
1796}
1797
4941b8cb 1798static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1799{
cc578287
ZA		 1800 u32 thresh_lo, thresh_hi;
1801 int use_scaling = 0;
217fc9cf 1802
03ba32ca 1803 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1804 if (user_tsc_khz == 0) {
ad721883
HZ		 1805 /* set tsc_scaling_ratio to a safe value */
1806 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1807 return -1;
ad721883 1808 }
03ba32ca 1809
c285545f 1810 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1811 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA		 1812 &vcpu->arch.virtual_tsc_shift,
1813 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1814 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA		 1815
1816 /*
1817 * Compute the variation in TSC rate which is acceptable
1818 * within the range of tolerance and decide if the
1819 * rate being applied is within that bounds of the hardware
1820 * rate. If so, no scaling or compensation need be done.
1821 */
1822 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1823 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB		 1824 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1825 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA		 1826 use_scaling = 1;
1827 }
4941b8cb 1828 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA		 1829}
1830
1831static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1832{
e26101b1 1833 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1834 vcpu->arch.virtual_tsc_mult,
1835 vcpu->arch.virtual_tsc_shift);
e26101b1 1836 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1837 return tsc;
1838}
1839
b0c39dc6
VK		 1840static inline int gtod_is_based_on_tsc(int mode)
1841{
1842 return mode == VCLOCK_TSC || mode == VCLOCK_HVCLOCK;
1843}
1844
69b0049a 1845static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1846{
1847#ifdef CONFIG_X86_64
1848 bool vcpus_matched;
b48aa97e
MT		 1849 struct kvm_arch *ka = &vcpu->kvm->arch;
1850 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1851
1852 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1853 atomic_read(&vcpu->kvm->online_vcpus));
1854
7f187922
MT		 1855 /*
1856 * Once the masterclock is enabled, always perform request in
1857 * order to update it.
1858 *
1859 * In order to enable masterclock, the host clocksource must be TSC
1860 * and the vcpus need to have matched TSCs. When that happens,
1861 * perform request to enable masterclock.
1862 */
1863 if (ka->use_master_clock ||
b0c39dc6 1864 (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
b48aa97e
MT		 1865 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1866
1867 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1868 atomic_read(&vcpu->kvm->online_vcpus),
1869 ka->use_master_clock, gtod->clock.vclock_mode);
1870#endif
1871}
1872
ba904635
WA		 1873static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1874{
e79f245d 1875 u64 curr_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
ba904635
WA		 1876 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1877}
1878
35181e86
HZ		 1879/*
1880 * Multiply tsc by a fixed point number represented by ratio.
1881 *
1882 * The most significant 64-N bits (mult) of ratio represent the
1883 * integral part of the fixed point number; the remaining N bits
1884 * (frac) represent the fractional part, ie. ratio represents a fixed
1885 * point number (mult + frac * 2^(-N)).
1886 *
1887 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1888 */
1889static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1890{
1891 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1892}
1893
1894u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1895{
1896 u64 _tsc = tsc;
1897 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1898
1899 if (ratio != kvm_default_tsc_scaling_ratio)
1900 _tsc = __scale_tsc(ratio, tsc);
1901
1902 return _tsc;
1903}
1904EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1905
07c1419a
HZ		 1906static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1907{
1908 u64 tsc;
1909
1910 tsc = kvm_scale_tsc(vcpu, rdtsc());
1911
1912 return target_tsc - tsc;
1913}
1914
4ba76538
HZ		 1915u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1916{
e79f245d
KA		 1917 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
1918
1919 return tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ		 1920}
1921EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1922
a545ab6a
LC		 1923static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1924{
326e7425 1925 vcpu->arch.tsc_offset = kvm_x86_ops->write_l1_tsc_offset(vcpu, offset);
a545ab6a
LC		 1926}
1927
b0c39dc6
VK		 1928static inline bool kvm_check_tsc_unstable(void)
1929{
1930#ifdef CONFIG_X86_64
1931 /*
1932 * TSC is marked unstable when we're running on Hyper-V,
1933 * 'TSC page' clocksource is good.
1934 */
1935 if (pvclock_gtod_data.clock.vclock_mode == VCLOCK_HVCLOCK)
1936 return false;
1937#endif
1938 return check_tsc_unstable();
1939}
1940
8fe8ab46 1941void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1942{
1943 struct kvm *kvm = vcpu->kvm;
f38e098f 1944 u64 offset, ns, elapsed;
99e3e30a 1945 unsigned long flags;
b48aa97e 1946 bool matched;
0d3da0d2 1947 bool already_matched;
8fe8ab46 1948 u64 data = msr->data;
c5e8ec8e 1949 bool synchronizing = false;
99e3e30a 1950
038f8c11 1951 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1952 offset = kvm_compute_tsc_offset(vcpu, data);
9285ec4c 1953 ns = ktime_get_boottime_ns();
f38e098f 1954 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1955
03ba32ca 1956 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP		 1957 if (data == 0 && msr->host_initiated) {
1958 /*
1959 * detection of vcpu initialization -- need to sync
1960 * with other vCPUs. This particularly helps to keep
1961 * kvm_clock stable after CPU hotplug
1962 */
1963 synchronizing = true;
1964 } else {
1965 u64 tsc_exp = kvm->arch.last_tsc_write +
1966 nsec_to_cycles(vcpu, elapsed);
1967 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1968 /*
1969 * Special case: TSC write with a small delta (1 second)
1970 * of virtual cycle time against real time is
1971 * interpreted as an attempt to synchronize the CPU.
1972 */
1973 synchronizing = data < tsc_exp + tsc_hz &&
1974 data + tsc_hz > tsc_exp;
1975 }
c5e8ec8e 1976 }
f38e098f
ZA		 1977
1978 /*
5d3cb0f6
ZA		 1979 * For a reliable TSC, we can match TSC offsets, and for an unstable
1980 * TSC, we add elapsed time in this computation. We could let the
1981 * compensation code attempt to catch up if we fall behind, but
1982 * it's better to try to match offsets from the beginning.
1983 */
c5e8ec8e 1984 if (synchronizing &&
5d3cb0f6 1985 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
b0c39dc6 1986 if (!kvm_check_tsc_unstable()) {
e26101b1 1987 offset = kvm->arch.cur_tsc_offset;
f38e098f 1988 } else {
857e4099 1989 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1990 data += delta;
07c1419a 1991 offset = kvm_compute_tsc_offset(vcpu, data);
f38e098f 1992 }
b48aa97e 1993 matched = true;
0d3da0d2 1994 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1995 } else {
1996 /*
1997 * We split periods of matched TSC writes into generations.
1998 * For each generation, we track the original measured
1999 * nanosecond time, offset, and write, so if TSCs are in
2000 * sync, we can match exact offset, and if not, we can match
4a969980 2001 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 2002 *
2003 * These values are tracked in kvm->arch.cur_xxx variables.
2004 */
2005 kvm->arch.cur_tsc_generation++;
2006 kvm->arch.cur_tsc_nsec = ns;
2007 kvm->arch.cur_tsc_write = data;
2008 kvm->arch.cur_tsc_offset = offset;
b48aa97e 2009 matched = false;
f38e098f 2010 }
e26101b1
ZA		 2011
2012 /*
2013 * We also track th most recent recorded KHZ, write and time to
2014 * allow the matching interval to be extended at each write.
2015 */
f38e098f
ZA		 2016 kvm->arch.last_tsc_nsec = ns;
2017 kvm->arch.last_tsc_write = data;
5d3cb0f6 2018 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 2019
b183aa58 2020 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 2021
2022 /* Keep track of which generation this VCPU has synchronized to */
2023 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2024 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2025 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2026
d6321d49 2027 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 2028 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 2029
a545ab6a 2030 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 2031 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 2032
2033 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 2034 if (!matched) {
b48aa97e 2035 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 2036 } else if (!already_matched) {
2037 kvm->arch.nr_vcpus_matched_tsc++;
2038 }
b48aa97e
MT		 2039
2040 kvm_track_tsc_matching(vcpu);
2041 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 2042}
e26101b1 2043
99e3e30a
ZA		 2044EXPORT_SYMBOL_GPL(kvm_write_tsc);
2045
58ea6767
HZ		 2046static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2047 s64 adjustment)
2048{
326e7425
LS		 2049 u64 tsc_offset = kvm_x86_ops->read_l1_tsc_offset(vcpu);
2050 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
58ea6767
HZ		 2051}
2052
2053static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2054{
2055 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
2056 WARN_ON(adjustment < 0);
2057 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 2058 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ		 2059}
2060
d828199e
MT		 2061#ifdef CONFIG_X86_64
2062
a5a1d1c2 2063static u64 read_tsc(void)
d828199e 2064{
a5a1d1c2 2065 u64 ret = (u64)rdtsc_ordered();
03b9730b 2066 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT		 2067
2068 if (likely(ret >= last))
2069 return ret;
2070
2071 /*
2072 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 2073 * predictable (it's just a function of time and the likely is
d828199e
MT		 2074 * very likely) and there's a data dependence, so force GCC
2075 * to generate a branch instead. I don't barrier() because
2076 * we don't actually need a barrier, and if this function
2077 * ever gets inlined it will generate worse code.
2078 */
2079 asm volatile ("");
2080 return last;
2081}
2082
53fafdbb
MT		 2083static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2084 int *mode)
d828199e
MT		 2085{
2086 long v;
b0c39dc6
VK		 2087 u64 tsc_pg_val;
2088
53fafdbb 2089 switch (clock->vclock_mode) {
b0c39dc6
VK		 2090 case VCLOCK_HVCLOCK:
2091 tsc_pg_val = hv_read_tsc_page_tsc(hv_get_tsc_page(),
2092 tsc_timestamp);
2093 if (tsc_pg_val != U64_MAX) {
2094 /* TSC page valid */
2095 *mode = VCLOCK_HVCLOCK;
53fafdbb
MT		 2096 v = (tsc_pg_val - clock->cycle_last) &
2097 clock->mask;
b0c39dc6
VK		 2098 } else {
2099 /* TSC page invalid */
2100 *mode = VCLOCK_NONE;
2101 }
2102 break;
2103 case VCLOCK_TSC:
2104 *mode = VCLOCK_TSC;
2105 *tsc_timestamp = read_tsc();
53fafdbb
MT		 2106 v = (*tsc_timestamp - clock->cycle_last) &
2107 clock->mask;
b0c39dc6
VK		 2108 break;
2109 default:
2110 *mode = VCLOCK_NONE;
2111 }
d828199e 2112
b0c39dc6
VK		 2113 if (*mode == VCLOCK_NONE)
2114 *tsc_timestamp = v = 0;
d828199e 2115
53fafdbb 2116 return v * clock->mult;
d828199e
MT		 2117}
2118
53fafdbb 2119static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
d828199e 2120{
cbcf2dd3 2121 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 2122 unsigned long seq;
d828199e 2123 int mode;
cbcf2dd3 2124 u64 ns;
d828199e 2125
d828199e
MT		 2126 do {
2127 seq = read_seqcount_begin(&gtod->seq);
53fafdbb
MT		 2128 ns = gtod->monotonic_raw_nsec;
2129 ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
d828199e 2130 ns >>= gtod->clock.shift;
53fafdbb 2131 ns += gtod->boot_ns_raw;
d828199e 2132 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 2133 *t = ns;
d828199e
MT		 2134
2135 return mode;
2136}
2137
899a31f5 2138static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
55dd00a7
MT		 2139{
2140 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2141 unsigned long seq;
2142 int mode;
2143 u64 ns;
2144
2145 do {
2146 seq = read_seqcount_begin(&gtod->seq);
55dd00a7
MT		 2147 ts->tv_sec = gtod->wall_time_sec;
2148 ns = gtod->nsec_base;
53fafdbb 2149 ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
55dd00a7
MT		 2150 ns >>= gtod->clock.shift;
2151 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2152
2153 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2154 ts->tv_nsec = ns;
2155
2156 return mode;
2157}
2158
b0c39dc6
VK		 2159/* returns true if host is using TSC based clocksource */
2160static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
d828199e 2161{
d828199e 2162 /* checked again under seqlock below */
b0c39dc6 2163 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
d828199e
MT		 2164 return false;
2165
53fafdbb 2166 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
b0c39dc6 2167 tsc_timestamp));
d828199e 2168}
55dd00a7 2169
b0c39dc6 2170/* returns true if host is using TSC based clocksource */
899a31f5 2171static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
b0c39dc6 2172 u64 *tsc_timestamp)
55dd00a7
MT		 2173{
2174 /* checked again under seqlock below */
b0c39dc6 2175 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
55dd00a7
MT		 2176 return false;
2177
b0c39dc6 2178 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
55dd00a7 2179}
d828199e
MT		 2180#endif
2181
2182/*
2183 *
b48aa97e
MT		 2184 * Assuming a stable TSC across physical CPUS, and a stable TSC
2185 * across virtual CPUs, the following condition is possible.
2186 * Each numbered line represents an event visible to both
d828199e
MT		 2187 * CPUs at the next numbered event.
2188 *
2189 * "timespecX" represents host monotonic time. "tscX" represents
2190 * RDTSC value.
2191 *
2192 * VCPU0 on CPU0 | VCPU1 on CPU1
2193 *
2194 * 1. read timespec0,tsc0
2195 * 2. | timespec1 = timespec0 + N
2196 * | tsc1 = tsc0 + M
2197 * 3. transition to guest | transition to guest
2198 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2199 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2200 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2201 *
2202 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2203 *
2204 * - ret0 < ret1
2205 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2206 * ...
2207 * - 0 < N - M => M < N
2208 *
2209 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2210 * always the case (the difference between two distinct xtime instances
2211 * might be smaller then the difference between corresponding TSC reads,
2212 * when updating guest vcpus pvclock areas).
2213 *
2214 * To avoid that problem, do not allow visibility of distinct
2215 * system_timestamp/tsc_timestamp values simultaneously: use a master
2216 * copy of host monotonic time values. Update that master copy
2217 * in lockstep.
2218 *
b48aa97e 2219 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 2220 *
2221 */
2222
2223static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2224{
2225#ifdef CONFIG_X86_64
2226 struct kvm_arch *ka = &kvm->arch;
2227 int vclock_mode;
b48aa97e
MT		 2228 bool host_tsc_clocksource, vcpus_matched;
2229
2230 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2231 atomic_read(&kvm->online_vcpus));
d828199e
MT		 2232
2233 /*
2234 * If the host uses TSC clock, then passthrough TSC as stable
2235 * to the guest.
2236 */
b48aa97e 2237 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 2238 &ka->master_kernel_ns,
2239 &ka->master_cycle_now);
2240
16a96021 2241 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 2242 && !ka->backwards_tsc_observed
54750f2c 2243 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 2244
d828199e
MT		 2245 if (ka->use_master_clock)
2246 atomic_set(&kvm_guest_has_master_clock, 1);
2247
2248 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 2249 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2250 vcpus_matched);
d828199e
MT		 2251#endif
2252}
2253
2860c4b1
PB		 2254void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2255{
2256 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2257}
2258
2e762ff7
MT		 2259static void kvm_gen_update_masterclock(struct kvm *kvm)
2260{
2261#ifdef CONFIG_X86_64
2262 int i;
2263 struct kvm_vcpu *vcpu;
2264 struct kvm_arch *ka = &kvm->arch;
2265
2266 spin_lock(&ka->pvclock_gtod_sync_lock);
2267 kvm_make_mclock_inprogress_request(kvm);
2268 /* no guest entries from this point */
2269 pvclock_update_vm_gtod_copy(kvm);
2270
2271 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 2272 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 2273
2274 /* guest entries allowed */
2275 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 2276 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT		 2277
2278 spin_unlock(&ka->pvclock_gtod_sync_lock);
2279#endif
2280}
2281
e891a32e 2282u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 2283{
108b249c 2284 struct kvm_arch *ka = &kvm->arch;
8b953440 2285 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 2286 u64 ret;
108b249c 2287
8b953440
PB		 2288 spin_lock(&ka->pvclock_gtod_sync_lock);
2289 if (!ka->use_master_clock) {
2290 spin_unlock(&ka->pvclock_gtod_sync_lock);
9285ec4c 2291 return ktime_get_boottime_ns() + ka->kvmclock_offset;
108b249c
PB		 2292 }
2293
8b953440
PB		 2294 hv_clock.tsc_timestamp = ka->master_cycle_now;
2295 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
2296 spin_unlock(&ka->pvclock_gtod_sync_lock);
2297
e2c2206a
WL		 2298 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
2299 get_cpu();
2300
e70b57a6
WL		 2301 if (__this_cpu_read(cpu_tsc_khz)) {
2302 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
2303 &hv_clock.tsc_shift,
2304 &hv_clock.tsc_to_system_mul);
2305 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
2306 } else
9285ec4c 2307 ret = ktime_get_boottime_ns() + ka->kvmclock_offset;
e2c2206a
WL		 2308
2309 put_cpu();
2310
2311 return ret;
108b249c
PB		 2312}
2313
0d6dd2ff
PB		 2314static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
2315{
2316 struct kvm_vcpu_arch *vcpu = &v->arch;
2317 struct pvclock_vcpu_time_info guest_hv_clock;
2318
4e335d9e 2319 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB		 2320 &guest_hv_clock, sizeof(guest_hv_clock))))
2321 return;
2322
2323 /* This VCPU is paused, but it's legal for a guest to read another
2324 * VCPU's kvmclock, so we really have to follow the specification where
2325 * it says that version is odd if data is being modified, and even after
2326 * it is consistent.
2327 *
2328 * Version field updates must be kept separate. This is because
2329 * kvm_write_guest_cached might use a "rep movs" instruction, and
2330 * writes within a string instruction are weakly ordered. So there
2331 * are three writes overall.
2332 *
2333 * As a small optimization, only write the version field in the first
2334 * and third write. The vcpu->pv_time cache is still valid, because the
2335 * version field is the first in the struct.
2336 */
2337 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
2338
51c4b8bb
LA		 2339 if (guest_hv_clock.version & 1)
2340 ++guest_hv_clock.version; /* first time write, random junk */
2341
0d6dd2ff 2342 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB		 2343 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2344 &vcpu->hv_clock,
2345 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2346
2347 smp_wmb();
2348
2349 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
2350 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
2351
2352 if (vcpu->pvclock_set_guest_stopped_request) {
2353 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
2354 vcpu->pvclock_set_guest_stopped_request = false;
2355 }
2356
2357 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
2358
4e335d9e
PB		 2359 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2360 &vcpu->hv_clock,
2361 sizeof(vcpu->hv_clock));
0d6dd2ff
PB		 2362
2363 smp_wmb();
2364
2365 vcpu->hv_clock.version++;
4e335d9e
PB		 2366 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
2367 &vcpu->hv_clock,
2368 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB		 2369}
2370
34c238a1 2371static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 2372{
78db6a50 2373 unsigned long flags, tgt_tsc_khz;
18068523 2374 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 2375 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 2376 s64 kernel_ns;
d828199e 2377 u64 tsc_timestamp, host_tsc;
51d59c6b 2378 u8 pvclock_flags;
d828199e
MT		 2379 bool use_master_clock;
2380
2381 kernel_ns = 0;
2382 host_tsc = 0;
18068523 2383
d828199e
MT		 2384 /*
2385 * If the host uses TSC clock, then passthrough TSC as stable
2386 * to the guest.
2387 */
2388 spin_lock(&ka->pvclock_gtod_sync_lock);
2389 use_master_clock = ka->use_master_clock;
2390 if (use_master_clock) {
2391 host_tsc = ka->master_cycle_now;
2392 kernel_ns = ka->master_kernel_ns;
2393 }
2394 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 2395
2396 /* Keep irq disabled to prevent changes to the clock */
2397 local_irq_save(flags);
78db6a50
PB		 2398 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
2399 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT		 2400 local_irq_restore(flags);
2401 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
2402 return 1;
2403 }
d828199e 2404 if (!use_master_clock) {
4ea1636b 2405 host_tsc = rdtsc();
9285ec4c 2406 kernel_ns = ktime_get_boottime_ns();
d828199e
MT		 2407 }
2408
4ba76538 2409 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 2410
c285545f
ZA		 2411 /*
2412 * We may have to catch up the TSC to match elapsed wall clock
2413 * time for two reasons, even if kvmclock is used.
2414 * 1) CPU could have been running below the maximum TSC rate
2415 * 2) Broken TSC compensation resets the base at each VCPU
2416 * entry to avoid unknown leaps of TSC even when running
2417 * again on the same CPU. This may cause apparent elapsed
2418 * time to disappear, and the guest to stand still or run
2419 * very slowly.
2420 */
2421 if (vcpu->tsc_catchup) {
2422 u64 tsc = compute_guest_tsc(v, kernel_ns);
2423 if (tsc > tsc_timestamp) {
f1e2b260 2424 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 2425 tsc_timestamp = tsc;
2426 }
50d0a0f9
GH		 2427 }
2428
18068523
GOC		 2429 local_irq_restore(flags);
2430
0d6dd2ff 2431 /* With all the info we got, fill in the values */
18068523 2432
78db6a50
PB		 2433 if (kvm_has_tsc_control)
2434 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
2435
2436 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 2437 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA		 2438 &vcpu->hv_clock.tsc_shift,
2439 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 2440 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA		 2441 }
2442
1d5f066e 2443 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 2444 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 2445 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 2446
d828199e 2447 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 2448 pvclock_flags = 0;
d828199e
MT		 2449 if (use_master_clock)
2450 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
2451
78c0337a
MT		 2452 vcpu->hv_clock.flags = pvclock_flags;
2453
095cf55d
PB		 2454 if (vcpu->pv_time_enabled)
2455 kvm_setup_pvclock_page(v);
2456 if (v == kvm_get_vcpu(v->kvm, 0))
2457 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2458 return 0;
c8076604
GH		 2459}
2460
0061d53d
MT		 2461/*
2462 * kvmclock updates which are isolated to a given vcpu, such as
2463 * vcpu->cpu migration, should not allow system_timestamp from
2464 * the rest of the vcpus to remain static. Otherwise ntp frequency
2465 * correction applies to one vcpu's system_timestamp but not
2466 * the others.
2467 *
2468 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 2469 * We need to rate-limit these requests though, as they can
2470 * considerably slow guests that have a large number of vcpus.
2471 * The time for a remote vcpu to update its kvmclock is bound
2472 * by the delay we use to rate-limit the updates.
0061d53d
MT		 2473 */
2474
7e44e449
AJ		 2475#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2476
2477static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 2478{
2479 int i;
7e44e449
AJ		 2480 struct delayed_work *dwork = to_delayed_work(work);
2481 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2482 kvmclock_update_work);
2483 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 2484 struct kvm_vcpu *vcpu;
2485
2486 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2487 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 2488 kvm_vcpu_kick(vcpu);
2489 }
2490}
2491
7e44e449
AJ		 2492static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2493{
2494 struct kvm *kvm = v->kvm;
2495
105b21bb 2496 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 2497 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2498 KVMCLOCK_UPDATE_DELAY);
2499}
2500
332967a3
AJ		 2501#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2502
2503static void kvmclock_sync_fn(struct work_struct *work)
2504{
2505 struct delayed_work *dwork = to_delayed_work(work);
2506 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2507 kvmclock_sync_work);
2508 struct kvm *kvm = container_of(ka, struct kvm, arch);
2509
630994b3
MT		 2510 if (!kvmclock_periodic_sync)
2511 return;
2512
332967a3
AJ		 2513 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2514 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2515 KVMCLOCK_SYNC_PERIOD);
2516}
2517
191c8137
BP		 2518/*
2519 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
2520 */
2521static bool can_set_mci_status(struct kvm_vcpu *vcpu)
2522{
2523 /* McStatusWrEn enabled? */
2524 if (guest_cpuid_is_amd(vcpu))
2525 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
2526
2527 return false;
2528}
2529
9ffd986c 2530static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2531{
890ca9ae
HY		 2532 u64 mcg_cap = vcpu->arch.mcg_cap;
2533 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL		 2534 u32 msr = msr_info->index;
2535 u64 data = msr_info->data;
890ca9ae 2536
15c4a640 2537 switch (msr) {
15c4a640 2538 case MSR_IA32_MCG_STATUS:
890ca9ae 2539 vcpu->arch.mcg_status = data;
15c4a640 2540 break;
c7ac679c 2541 case MSR_IA32_MCG_CTL:
44883f01
PB		 2542 if (!(mcg_cap & MCG_CTL_P) &&
2543 (data || !msr_info->host_initiated))
890ca9ae
HY		 2544 return 1;
2545 if (data != 0 && data != ~(u64)0)
44883f01 2546 return 1;
890ca9ae
HY		 2547 vcpu->arch.mcg_ctl = data;
2548 break;
2549 default:
2550 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2551 msr < MSR_IA32_MCx_CTL(bank_num)) {
6ec4c5ee
MP		 2552 u32 offset = array_index_nospec(
2553 msr - MSR_IA32_MC0_CTL,
2554 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2555
114be429
AP		 2556 /* only 0 or all 1s can be written to IA32_MCi_CTL
2557 * some Linux kernels though clear bit 10 in bank 4 to
2558 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2559 * this to avoid an uncatched #GP in the guest
2560 */
890ca9ae 2561 if ((offset & 0x3) == 0 &&
114be429 2562 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2563 return -1;
191c8137
BP		 2564
2565 /* MCi_STATUS */
9ffd986c 2566 if (!msr_info->host_initiated &&
191c8137
BP		 2567 (offset & 0x3) == 1 && data != 0) {
2568 if (!can_set_mci_status(vcpu))
2569 return -1;
2570 }
2571
890ca9ae
HY		 2572 vcpu->arch.mce_banks[offset] = data;
2573 break;
2574 }
2575 return 1;
2576 }
2577 return 0;
2578}
2579
ffde22ac
ES		 2580static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2581{
2582 struct kvm *kvm = vcpu->kvm;
2583 int lm = is_long_mode(vcpu);
2584 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2585 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2586 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2587 : kvm->arch.xen_hvm_config.blob_size_32;
2588 u32 page_num = data & ~PAGE_MASK;
2589 u64 page_addr = data & PAGE_MASK;
2590 u8 *page;
2591 int r;
2592
2593 r = -E2BIG;
2594 if (page_num >= blob_size)
2595 goto out;
2596 r = -ENOMEM;
ff5c2c03
SL		 2597 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2598 if (IS_ERR(page)) {
2599 r = PTR_ERR(page);
ffde22ac 2600 goto out;
ff5c2c03 2601 }
54bf36aa 2602 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 2603 goto out_free;
2604 r = 0;
2605out_free:
2606 kfree(page);
2607out:
2608 return r;
2609}
2610
344d9588
GN		 2611static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2612{
2613 gpa_t gpa = data & ~0x3f;
2614
52a5c155
WL		 2615 /* Bits 3:5 are reserved, Should be zero */
2616 if (data & 0x38)
344d9588
GN		 2617 return 1;
2618
2619 vcpu->arch.apf.msr_val = data;
2620
2621 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2622 kvm_clear_async_pf_completion_queue(vcpu);
2623 kvm_async_pf_hash_reset(vcpu);
2624 return 0;
2625 }
2626
4e335d9e 2627 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2628 sizeof(u32)))
344d9588
GN		 2629 return 1;
2630
6adba527 2631 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2632 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN		 2633 kvm_async_pf_wakeup_all(vcpu);
2634 return 0;
2635}
2636
12f9a48f
GC		 2637static void kvmclock_reset(struct kvm_vcpu *vcpu)
2638{
0b79459b 2639 vcpu->arch.pv_time_enabled = false;
49dedf0d 2640 vcpu->arch.time = 0;
12f9a48f
GC		 2641}
2642
f38a7b75
WL		 2643static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa)
2644{
2645 ++vcpu->stat.tlb_flush;
2646 kvm_x86_ops->tlb_flush(vcpu, invalidate_gpa);
2647}
2648
c9aaa895
GC		 2649static void record_steal_time(struct kvm_vcpu *vcpu)
2650{
b0431382
BO		 2651 struct kvm_host_map map;
2652 struct kvm_steal_time *st;
2653
c9aaa895
GC		 2654 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2655 return;
2656
b0431382
BO		 2657 /* -EAGAIN is returned in atomic context so we can just return. */
2658 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT,
2659 &map, &vcpu->arch.st.cache, false))
c9aaa895
GC		 2660 return;
2661
b0431382
BO		 2662 st = map.hva +
2663 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
2664
f38a7b75
WL		 2665 /*
2666 * Doing a TLB flush here, on the guest's behalf, can avoid
2667 * expensive IPIs.
2668 */
b382f44e 2669 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
b0431382
BO		 2670 st->preempted & KVM_VCPU_FLUSH_TLB);
2671 if (xchg(&st->preempted, 0) & KVM_VCPU_FLUSH_TLB)
f38a7b75 2672 kvm_vcpu_flush_tlb(vcpu, false);
0b9f6c46 2673
a6bd811f 2674 vcpu->arch.st.preempted = 0;
35f3fae1 2675
b0431382
BO		 2676 if (st->version & 1)
2677 st->version += 1; /* first time write, random junk */
35f3fae1 2678
b0431382 2679 st->version += 1;
35f3fae1
WL		 2680
2681 smp_wmb();
2682
b0431382 2683 st->steal += current->sched_info.run_delay -
c54cdf14
LC		 2684 vcpu->arch.st.last_steal;
2685 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2686
35f3fae1
WL		 2687 smp_wmb();
2688
b0431382 2689 st->version += 1;
c9aaa895 2690
b0431382 2691 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, false);
c9aaa895
GC		 2692}
2693
8fe8ab46 2694int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2695{
5753785f 2696 bool pr = false;
8fe8ab46
WA		 2697 u32 msr = msr_info->index;
2698 u64 data = msr_info->data;
5753785f 2699
15c4a640 2700 switch (msr) {
2e32b719 2701 case MSR_AMD64_NB_CFG:
2e32b719
BP		 2702 case MSR_IA32_UCODE_WRITE:
2703 case MSR_VM_HSAVE_PA:
2704 case MSR_AMD64_PATCH_LOADER:
2705 case MSR_AMD64_BU_CFG2:
405a353a 2706 case MSR_AMD64_DC_CFG:
0e1b869f 2707 case MSR_F15H_EX_CFG:
2e32b719
BP		 2708 break;
2709
518e7b94
WL		 2710 case MSR_IA32_UCODE_REV:
2711 if (msr_info->host_initiated)
2712 vcpu->arch.microcode_version = data;
2713 break;
0cf9135b
SC		 2714 case MSR_IA32_ARCH_CAPABILITIES:
2715 if (!msr_info->host_initiated)
2716 return 1;
2717 vcpu->arch.arch_capabilities = data;
2718 break;
15c4a640 2719 case MSR_EFER:
11988499 2720 return set_efer(vcpu, msr_info);
8f1589d9
AP		 2721 case MSR_K7_HWCR:
2722 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2723 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2724 data &= ~(u64)0x8; /* ignore TLB cache disable */
191c8137
BP		 2725
2726 /* Handle McStatusWrEn */
2727 if (data == BIT_ULL(18)) {
2728 vcpu->arch.msr_hwcr = data;
2729 } else if (data != 0) {
a737f256
CD		 2730 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2731 data);
8f1589d9
AP		 2732 return 1;
2733 }
15c4a640 2734 break;
f7c6d140
AP		 2735 case MSR_FAM10H_MMIO_CONF_BASE:
2736 if (data != 0) {
a737f256
CD		 2737 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2738 "0x%llx\n", data);
f7c6d140
AP		 2739 return 1;
2740 }
15c4a640 2741 break;
b5e2fec0
AG		 2742 case MSR_IA32_DEBUGCTLMSR:
2743 if (!data) {
2744 /* We support the non-activated case already */
2745 break;
2746 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2747 /* Values other than LBR and BTF are vendor-specific,
2748 thus reserved and should throw a #GP */
2749 return 1;
2750 }
a737f256
CD		 2751 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2752 __func__, data);
b5e2fec0 2753 break;
9ba075a6 2754 case 0x200 ... 0x2ff:
ff53604b 2755 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2756 case MSR_IA32_APICBASE:
58cb628d 2757 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2758 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2759 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2760 case MSR_IA32_TSCDEADLINE:
2761 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2762 break;
ba904635 2763 case MSR_IA32_TSC_ADJUST:
d6321d49 2764 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2765 if (!msr_info->host_initiated) {
d913b904 2766 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2767 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA		 2768 }
2769 vcpu->arch.ia32_tsc_adjust_msr = data;
2770 }
2771 break;
15c4a640 2772 case MSR_IA32_MISC_ENABLE:
511a8556
WL		 2773 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
2774 ((vcpu->arch.ia32_misc_enable_msr ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
2775 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
2776 return 1;
2777 vcpu->arch.ia32_misc_enable_msr = data;
2778 kvm_update_cpuid(vcpu);
2779 } else {
2780 vcpu->arch.ia32_misc_enable_msr = data;
2781 }
15c4a640 2782 break;
64d60670
PB		 2783 case MSR_IA32_SMBASE:
2784 if (!msr_info->host_initiated)
2785 return 1;
2786 vcpu->arch.smbase = data;
2787 break;
73f624f4
PB		 2788 case MSR_IA32_POWER_CTL:
2789 vcpu->arch.msr_ia32_power_ctl = data;
2790 break;
dd259935
PB		 2791 case MSR_IA32_TSC:
2792 kvm_write_tsc(vcpu, msr_info);
2793 break;
864e2ab2
AL		 2794 case MSR_IA32_XSS:
2795 if (!msr_info->host_initiated &&
2796 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
2797 return 1;
2798 /*
2799 * We do support PT if kvm_x86_ops->pt_supported(), but we do
2800 * not support IA32_XSS[bit 8]. Guests will have to use
2801 * RDMSR/WRMSR rather than XSAVES/XRSTORS to save/restore PT
2802 * MSRs.
2803 */
2804 if (data != 0)
2805 return 1;
2806 vcpu->arch.ia32_xss = data;
2807 break;
52797bf9
LA		 2808 case MSR_SMI_COUNT:
2809 if (!msr_info->host_initiated)
2810 return 1;
2811 vcpu->arch.smi_count = data;
2812 break;
11c6bffa 2813 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2814 case MSR_KVM_WALL_CLOCK:
2815 vcpu->kvm->arch.wall_clock = data;
2816 kvm_write_wall_clock(vcpu->kvm, data);
2817 break;
11c6bffa 2818 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2819 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT		 2820 struct kvm_arch *ka = &vcpu->kvm->arch;
2821
54750f2c
MT		 2822 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2823 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2824
2825 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2826 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT		 2827
2828 ka->boot_vcpu_runs_old_kvmclock = tmp;
2829 }
2830
18068523 2831 vcpu->arch.time = data;
0061d53d 2832 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2833
2834 /* we verify if the enable bit is set... */
49dedf0d 2835 vcpu->arch.pv_time_enabled = false;
18068523
GOC		 2836 if (!(data & 1))
2837 break;
2838
49dedf0d 2839 if (!kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2840 &vcpu->arch.pv_time, data & ~1ULL,
2841 sizeof(struct pvclock_vcpu_time_info)))
0b79459b 2842 vcpu->arch.pv_time_enabled = true;
32cad84f 2843
18068523
GOC		 2844 break;
2845 }
344d9588
GN		 2846 case MSR_KVM_ASYNC_PF_EN:
2847 if (kvm_pv_enable_async_pf(vcpu, data))
2848 return 1;
2849 break;
c9aaa895
GC		 2850 case MSR_KVM_STEAL_TIME:
2851
2852 if (unlikely(!sched_info_on()))
2853 return 1;
2854
2855 if (data & KVM_STEAL_RESERVED_MASK)
2856 return 1;
2857
c9aaa895
GC		 2858 vcpu->arch.st.msr_val = data;
2859
2860 if (!(data & KVM_MSR_ENABLED))
2861 break;
2862
c9aaa895
GC		 2863 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2864
2865 break;
ae7a2a3f 2866 case MSR_KVM_PV_EOI_EN:
72bbf935 2867 if (kvm_lapic_enable_pv_eoi(vcpu, data, sizeof(u8)))
ae7a2a3f
MT		 2868 return 1;
2869 break;
c9aaa895 2870
2d5ba19b
MT		 2871 case MSR_KVM_POLL_CONTROL:
2872 /* only enable bit supported */
2873 if (data & (-1ULL << 1))
2874 return 1;
2875
2876 vcpu->arch.msr_kvm_poll_control = data;
2877 break;
2878
890ca9ae
HY		 2879 case MSR_IA32_MCG_CTL:
2880 case MSR_IA32_MCG_STATUS:
81760dcc 2881 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2882 return set_msr_mce(vcpu, msr_info);
71db6023 2883
6912ac32
WH		 2884 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2885 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2886 pr = true; /* fall through */
2887 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2888 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2889 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2890 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2891
2892 if (pr || data != 0)
a737f256
CD		 2893 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2894 "0x%x data 0x%llx\n", msr, data);
5753785f 2895 break;
84e0cefa
JS		 2896 case MSR_K7_CLK_CTL:
2897 /*
2898 * Ignore all writes to this no longer documented MSR.
2899 * Writes are only relevant for old K7 processors,
2900 * all pre-dating SVM, but a recommended workaround from
4a969980 2901 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2902 * affected processor models on the command line, hence
2903 * the need to ignore the workaround.
2904 */
2905 break;
55cd8e5a 2906 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 2907 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2908 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2909 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 2910 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2911 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2912 case HV_X64_MSR_TSC_EMULATION_STATUS:
e7d9513b
AS		 2913 return kvm_hv_set_msr_common(vcpu, msr, data,
2914 msr_info->host_initiated);
91c9c3ed 2915 case MSR_IA32_BBL_CR_CTL3:
2916 /* Drop writes to this legacy MSR -- see rdmsr
2917 * counterpart for further detail.
2918 */
fab0aa3b
EM		 2919 if (report_ignored_msrs)
2920 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2921 msr, data);
91c9c3ed 2922 break;
2b036c6b 2923 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2924 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2925 return 1;
2926 vcpu->arch.osvw.length = data;
2927 break;
2928 case MSR_AMD64_OSVW_STATUS:
d6321d49 2929 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO		 2930 return 1;
2931 vcpu->arch.osvw.status = data;
2932 break;
db2336a8
KH		 2933 case MSR_PLATFORM_INFO:
2934 if (!msr_info->host_initiated ||
db2336a8
KH		 2935 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2936 cpuid_fault_enabled(vcpu)))
2937 return 1;
2938 vcpu->arch.msr_platform_info = data;
2939 break;
2940 case MSR_MISC_FEATURES_ENABLES:
2941 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2942 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2943 !supports_cpuid_fault(vcpu)))
2944 return 1;
2945 vcpu->arch.msr_misc_features_enables = data;
2946 break;
15c4a640 2947 default:
ffde22ac
ES		 2948 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2949 return xen_hvm_config(vcpu, data);
c6702c9d 2950 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2951 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2952 if (!ignore_msrs) {
ae0f5499 2953 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2954 msr, data);
ed85c068
AP		 2955 return 1;
2956 } else {
fab0aa3b
EM		 2957 if (report_ignored_msrs)
2958 vcpu_unimpl(vcpu,
2959 "ignored wrmsr: 0x%x data 0x%llx\n",
2960 msr, data);
ed85c068
AP		 2961 break;
2962 }
15c4a640
CO		 2963 }
2964 return 0;
2965}
2966EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2967
44883f01 2968static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
15c4a640
CO		 2969{
2970 u64 data;
890ca9ae
HY		 2971 u64 mcg_cap = vcpu->arch.mcg_cap;
2972 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2973
2974 switch (msr) {
15c4a640
CO		 2975 case MSR_IA32_P5_MC_ADDR:
2976 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2977 data = 0;
2978 break;
15c4a640 2979 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2980 data = vcpu->arch.mcg_cap;
2981 break;
c7ac679c 2982 case MSR_IA32_MCG_CTL:
44883f01 2983 if (!(mcg_cap & MCG_CTL_P) && !host)
890ca9ae
HY		 2984 return 1;
2985 data = vcpu->arch.mcg_ctl;
2986 break;
2987 case MSR_IA32_MCG_STATUS:
2988 data = vcpu->arch.mcg_status;
2989 break;
2990 default:
2991 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2992 msr < MSR_IA32_MCx_CTL(bank_num)) {
6ec4c5ee
MP		 2993 u32 offset = array_index_nospec(
2994 msr - MSR_IA32_MC0_CTL,
2995 MSR_IA32_MCx_CTL(bank_num) - MSR_IA32_MC0_CTL);
2996
890ca9ae
HY		 2997 data = vcpu->arch.mce_banks[offset];
2998 break;
2999 }
3000 return 1;
3001 }
3002 *pdata = data;
3003 return 0;
3004}
3005
609e36d3 3006int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 3007{
609e36d3 3008 switch (msr_info->index) {
890ca9ae 3009 case MSR_IA32_PLATFORM_ID:
15c4a640 3010 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 3011 case MSR_IA32_DEBUGCTLMSR:
3012 case MSR_IA32_LASTBRANCHFROMIP:
3013 case MSR_IA32_LASTBRANCHTOIP:
3014 case MSR_IA32_LASTINTFROMIP:
3015 case MSR_IA32_LASTINTTOIP:
60af2ecd 3016 case MSR_K8_SYSCFG:
3afb1121
PB		 3017 case MSR_K8_TSEG_ADDR:
3018 case MSR_K8_TSEG_MASK:
61a6bd67 3019 case MSR_VM_HSAVE_PA:
1fdbd48c 3020 case MSR_K8_INT_PENDING_MSG:
c323c0e5 3021 case MSR_AMD64_NB_CFG:
f7c6d140 3022 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 3023 case MSR_AMD64_BU_CFG2:
0c2df2a1 3024 case MSR_IA32_PERF_CTL:
405a353a 3025 case MSR_AMD64_DC_CFG:
0e1b869f 3026 case MSR_F15H_EX_CFG:
609e36d3 3027 msr_info->data = 0;
15c4a640 3028 break;
c51eb52b 3029 case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5:
6912ac32
WH		 3030 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3031 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3032 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3033 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 3034 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB		 3035 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
3036 msr_info->data = 0;
5753785f 3037 break;
742bc670 3038 case MSR_IA32_UCODE_REV:
518e7b94 3039 msr_info->data = vcpu->arch.microcode_version;
742bc670 3040 break;
0cf9135b
SC		 3041 case MSR_IA32_ARCH_CAPABILITIES:
3042 if (!msr_info->host_initiated &&
3043 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
3044 return 1;
3045 msr_info->data = vcpu->arch.arch_capabilities;
3046 break;
73f624f4
PB		 3047 case MSR_IA32_POWER_CTL:
3048 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
3049 break;
dd259935
PB		 3050 case MSR_IA32_TSC:
3051 msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;
3052 break;
9ba075a6 3053 case MSR_MTRRcap:
9ba075a6 3054 case 0x200 ... 0x2ff:
ff53604b 3055 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 3056 case 0xcd: /* fsb frequency */
609e36d3 3057 msr_info->data = 3;
15c4a640 3058 break;
7b914098
JS		 3059 /*
3060 * MSR_EBC_FREQUENCY_ID
3061 * Conservative value valid for even the basic CPU models.
3062 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
3063 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
3064 * and 266MHz for model 3, or 4. Set Core Clock
3065 * Frequency to System Bus Frequency Ratio to 1 (bits
3066 * 31:24) even though these are only valid for CPU
3067 * models > 2, however guests may end up dividing or
3068 * multiplying by zero otherwise.
3069 */
3070 case MSR_EBC_FREQUENCY_ID:
609e36d3 3071 msr_info->data = 1 << 24;
7b914098 3072 break;
15c4a640 3073 case MSR_IA32_APICBASE:
609e36d3 3074 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 3075 break;
0105d1a5 3076 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 3077 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 3078 break;
a3e06bbe 3079 case MSR_IA32_TSCDEADLINE:
609e36d3 3080 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 3081 break;
ba904635 3082 case MSR_IA32_TSC_ADJUST:
609e36d3 3083 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 3084 break;
15c4a640 3085 case MSR_IA32_MISC_ENABLE:
609e36d3 3086 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 3087 break;
64d60670
PB		 3088 case MSR_IA32_SMBASE:
3089 if (!msr_info->host_initiated)
3090 return 1;
3091 msr_info->data = vcpu->arch.smbase;
15c4a640 3092 break;
52797bf9
LA		 3093 case MSR_SMI_COUNT:
3094 msr_info->data = vcpu->arch.smi_count;
3095 break;
847f0ad8
AG		 3096 case MSR_IA32_PERF_STATUS:
3097 /* TSC increment by tick */
609e36d3 3098 msr_info->data = 1000ULL;
847f0ad8 3099 /* CPU multiplier */
b0996ae4 3100 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 3101 break;
15c4a640 3102 case MSR_EFER:
609e36d3 3103 msr_info->data = vcpu->arch.efer;
15c4a640 3104 break;
18068523 3105 case MSR_KVM_WALL_CLOCK:
11c6bffa 3106 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 3107 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 3108 break;
3109 case MSR_KVM_SYSTEM_TIME:
11c6bffa 3110 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 3111 msr_info->data = vcpu->arch.time;
18068523 3112 break;
344d9588 3113 case MSR_KVM_ASYNC_PF_EN:
609e36d3 3114 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 3115 break;
c9aaa895 3116 case MSR_KVM_STEAL_TIME:
609e36d3 3117 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 3118 break;
1d92128f 3119 case MSR_KVM_PV_EOI_EN:
609e36d3 3120 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 3121 break;
2d5ba19b
MT		 3122 case MSR_KVM_POLL_CONTROL:
3123 msr_info->data = vcpu->arch.msr_kvm_poll_control;
3124 break;
890ca9ae
HY		 3125 case MSR_IA32_P5_MC_ADDR:
3126 case MSR_IA32_P5_MC_TYPE:
3127 case MSR_IA32_MCG_CAP:
3128 case MSR_IA32_MCG_CTL:
3129 case MSR_IA32_MCG_STATUS:
81760dcc 3130 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
44883f01
PB		 3131 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
3132 msr_info->host_initiated);
864e2ab2
AL		 3133 case MSR_IA32_XSS:
3134 if (!msr_info->host_initiated &&
3135 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3136 return 1;
3137 msr_info->data = vcpu->arch.ia32_xss;
3138 break;
84e0cefa
JS		 3139 case MSR_K7_CLK_CTL:
3140 /*
3141 * Provide expected ramp-up count for K7. All other
3142 * are set to zero, indicating minimum divisors for
3143 * every field.
3144 *
3145 * This prevents guest kernels on AMD host with CPU
3146 * type 6, model 8 and higher from exploding due to
3147 * the rdmsr failing.
3148 */
609e36d3 3149 msr_info->data = 0x20000000;
84e0cefa 3150 break;
55cd8e5a 3151 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS		 3152 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3153 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 3154 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
a2e164e7
VK		 3155 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3156 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3157 case HV_X64_MSR_TSC_EMULATION_STATUS:
e83d5887 3158 return kvm_hv_get_msr_common(vcpu,
44883f01
PB		 3159 msr_info->index, &msr_info->data,
3160 msr_info->host_initiated);
55cd8e5a 3161 break;
91c9c3ed 3162 case MSR_IA32_BBL_CR_CTL3:
3163 /* This legacy MSR exists but isn't fully documented in current
3164 * silicon. It is however accessed by winxp in very narrow
3165 * scenarios where it sets bit #19, itself documented as
3166 * a "reserved" bit. Best effort attempt to source coherent
3167 * read data here should the balance of the register be
3168 * interpreted by the guest:
3169 *
3170 * L2 cache control register 3: 64GB range, 256KB size,
3171 * enabled, latency 0x1, configured
3172 */
609e36d3 3173 msr_info->data = 0xbe702111;
91c9c3ed 3174 break;
2b036c6b 3175 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 3176 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 3177 return 1;
609e36d3 3178 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 3179 break;
3180 case MSR_AMD64_OSVW_STATUS:
d6321d49 3181 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 3182 return 1;
609e36d3 3183 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 3184 break;
db2336a8 3185 case MSR_PLATFORM_INFO:
6fbbde9a
DS		 3186 if (!msr_info->host_initiated &&
3187 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
3188 return 1;
db2336a8
KH		 3189 msr_info->data = vcpu->arch.msr_platform_info;
3190 break;
3191 case MSR_MISC_FEATURES_ENABLES:
3192 msr_info->data = vcpu->arch.msr_misc_features_enables;
3193 break;
191c8137
BP		 3194 case MSR_K7_HWCR:
3195 msr_info->data = vcpu->arch.msr_hwcr;
3196 break;
15c4a640 3197 default:
c6702c9d 3198 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 3199 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 3200 if (!ignore_msrs) {
ae0f5499
BD		 3201 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
3202 msr_info->index);
ed85c068
AP		 3203 return 1;
3204 } else {
fab0aa3b
EM		 3205 if (report_ignored_msrs)
3206 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
3207 msr_info->index);
609e36d3 3208 msr_info->data = 0;
ed85c068
AP		 3209 }
3210 break;
15c4a640 3211 }
15c4a640
CO		 3212 return 0;
3213}
3214EXPORT_SYMBOL_GPL(kvm_get_msr_common);
3215
313a3dc7
CO		 3216/*
3217 * Read or write a bunch of msrs. All parameters are kernel addresses.
3218 *
3219 * @return number of msrs set successfully.
3220 */
3221static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
3222 struct kvm_msr_entry *entries,
3223 int (*do_msr)(struct kvm_vcpu *vcpu,
3224 unsigned index, u64 *data))
3225{
801e459a 3226 int i;
313a3dc7 3227
313a3dc7
CO		 3228 for (i = 0; i < msrs->nmsrs; ++i)
3229 if (do_msr(vcpu, entries[i].index, &entries[i].data))
3230 break;
3231
313a3dc7
CO		 3232 return i;
3233}
3234
3235/*
3236 * Read or write a bunch of msrs. Parameters are user addresses.
3237 *
3238 * @return number of msrs set successfully.
3239 */
3240static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
3241 int (*do_msr)(struct kvm_vcpu *vcpu,
3242 unsigned index, u64 *data),
3243 int writeback)
3244{
3245 struct kvm_msrs msrs;
3246 struct kvm_msr_entry *entries;
3247 int r, n;
3248 unsigned size;
3249
3250 r = -EFAULT;
0e96f31e 3251 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
313a3dc7
CO		 3252 goto out;
3253
3254 r = -E2BIG;
3255 if (msrs.nmsrs >= MAX_IO_MSRS)
3256 goto out;
3257
313a3dc7 3258 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 3259 entries = memdup_user(user_msrs->entries, size);
3260 if (IS_ERR(entries)) {
3261 r = PTR_ERR(entries);
313a3dc7 3262 goto out;
ff5c2c03 3263 }
313a3dc7
CO		 3264
3265 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
3266 if (r < 0)
3267 goto out_free;
3268
3269 r = -EFAULT;
3270 if (writeback && copy_to_user(user_msrs->entries, entries, size))
3271 goto out_free;
3272
3273 r = n;
3274
3275out_free:
7a73c028 3276 kfree(entries);
313a3dc7
CO		 3277out:
3278 return r;
3279}
3280
4d5422ce
WL		 3281static inline bool kvm_can_mwait_in_guest(void)
3282{
3283 return boot_cpu_has(X86_FEATURE_MWAIT) &&
8e9b29b6
KA		 3284 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
3285 boot_cpu_has(X86_FEATURE_ARAT);
4d5422ce
WL		 3286}
3287
784aa3d7 3288int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2 3289{
4d5422ce 3290 int r = 0;
018d00d2
ZX		 3291
3292 switch (ext) {
3293 case KVM_CAP_IRQCHIP:
3294 case KVM_CAP_HLT:
3295 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 3296 case KVM_CAP_SET_TSS_ADDR:
07716717 3297 case KVM_CAP_EXT_CPUID:
9c15bb1d 3298 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 3299 case KVM_CAP_CLOCKSOURCE:
7837699f 3300 case KVM_CAP_PIT:
a28e4f5a 3301 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 3302 case KVM_CAP_MP_STATE:
ed848624 3303 case KVM_CAP_SYNC_MMU:
a355c85c 3304 case KVM_CAP_USER_NMI:
52d939a0 3305 case KVM_CAP_REINJECT_CONTROL:
4925663a 3306 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 3307 case KVM_CAP_IOEVENTFD:
f848a5a8 3308 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 3309 case KVM_CAP_PIT2:
e9f42757 3310 case KVM_CAP_PIT_STATE2:
b927a3ce 3311 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 3312 case KVM_CAP_XEN_HVM:
3cfc3092 3313 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 3314 case KVM_CAP_HYPERV:
10388a07 3315 case KVM_CAP_HYPERV_VAPIC:
c25bc163 3316 case KVM_CAP_HYPERV_SPIN:
5c919412 3317 case KVM_CAP_HYPERV_SYNIC:
efc479e6 3318 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 3319 case KVM_CAP_HYPERV_VP_INDEX:
faeb7833 3320 case KVM_CAP_HYPERV_EVENTFD:
c1aea919 3321 case KVM_CAP_HYPERV_TLBFLUSH:
214ff83d 3322 case KVM_CAP_HYPERV_SEND_IPI:
2bc39970 3323 case KVM_CAP_HYPERV_CPUID:
ab9f4ecb 3324 case KVM_CAP_PCI_SEGMENT:
a1efbe77 3325 case KVM_CAP_DEBUGREGS:
d2be1651 3326 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 3327 case KVM_CAP_XSAVE:
344d9588 3328 case KVM_CAP_ASYNC_PF:
92a1f12d 3329 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 3330 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 3331 case KVM_CAP_READONLY_MEM:
5f66b620 3332 case KVM_CAP_HYPERV_TIME:
100943c5 3333 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 3334 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18 3335 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 3336 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 3337 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 3338 case KVM_CAP_IMMEDIATE_EXIT:
66bb8a06 3339 case KVM_CAP_PMU_EVENT_FILTER:
801e459a 3340 case KVM_CAP_GET_MSR_FEATURES:
6fbbde9a 3341 case KVM_CAP_MSR_PLATFORM_INFO:
c4f55198 3342 case KVM_CAP_EXCEPTION_PAYLOAD:
018d00d2
ZX		 3343 r = 1;
3344 break;
01643c51
KH		 3345 case KVM_CAP_SYNC_REGS:
3346 r = KVM_SYNC_X86_VALID_FIELDS;
3347 break;
e3fd9a93
PB		 3348 case KVM_CAP_ADJUST_CLOCK:
3349 r = KVM_CLOCK_TSC_STABLE;
3350 break;
4d5422ce 3351 case KVM_CAP_X86_DISABLE_EXITS:
b5170063
WL		 3352 r |= KVM_X86_DISABLE_EXITS_HLT | KVM_X86_DISABLE_EXITS_PAUSE |
3353 KVM_X86_DISABLE_EXITS_CSTATE;
4d5422ce
WL		 3354 if(kvm_can_mwait_in_guest())
3355 r |= KVM_X86_DISABLE_EXITS_MWAIT;
668fffa3 3356 break;
6d396b55
PB		 3357 case KVM_CAP_X86_SMM:
3358 /* SMBASE is usually relocated above 1M on modern chipsets,
3359 * and SMM handlers might indeed rely on 4G segment limits,
3360 * so do not report SMM to be available if real mode is
3361 * emulated via vm86 mode. Still, do not go to great lengths
3362 * to avoid userspace's usage of the feature, because it is a
3363 * fringe case that is not enabled except via specific settings
3364 * of the module parameters.
3365 */
bc226f07 3366 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 3367 break;
774ead3a
AK		 3368 case KVM_CAP_VAPIC:
3369 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
3370 break;
f725230a 3371 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 3372 r = KVM_SOFT_MAX_VCPUS;
3373 break;
3374 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 3375 r = KVM_MAX_VCPUS;
3376 break;
a86cb413
TH		 3377 case KVM_CAP_MAX_VCPU_ID:
3378 r = KVM_MAX_VCPU_ID;
3379 break;
a68a6a72
MT		 3380 case KVM_CAP_PV_MMU: /* obsolete */
3381 r = 0;
2f333bcb 3382 break;
890ca9ae
HY		 3383 case KVM_CAP_MCE:
3384 r = KVM_MAX_MCE_BANKS;
3385 break;
2d5b5a66 3386 case KVM_CAP_XCRS:
d366bf7e 3387 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 3388 break;
92a1f12d
JR		 3389 case KVM_CAP_TSC_CONTROL:
3390 r = kvm_has_tsc_control;
3391 break;
37131313
RK		 3392 case KVM_CAP_X2APIC_API:
3393 r = KVM_X2APIC_API_VALID_FLAGS;
3394 break;
8fcc4b59
JM		 3395 case KVM_CAP_NESTED_STATE:
3396 r = kvm_x86_ops->get_nested_state ?
be43c440 3397 kvm_x86_ops->get_nested_state(NULL, NULL, 0) : 0;
8fcc4b59 3398 break;
344c6c80 3399 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5a0165f6
VK		 3400 r = kvm_x86_ops->enable_direct_tlbflush != NULL;
3401 break;
3402 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
3403 r = kvm_x86_ops->nested_enable_evmcs != NULL;
344c6c80 3404 break;
018d00d2 3405 default:
018d00d2
ZX		 3406 break;
3407 }
3408 return r;
3409
3410}
3411
043405e1
CO		 3412long kvm_arch_dev_ioctl(struct file *filp,
3413 unsigned int ioctl, unsigned long arg)
3414{
3415 void __user *argp = (void __user *)arg;
3416 long r;
3417
3418 switch (ioctl) {
3419 case KVM_GET_MSR_INDEX_LIST: {
3420 struct kvm_msr_list __user *user_msr_list = argp;
3421 struct kvm_msr_list msr_list;
3422 unsigned n;
3423
3424 r = -EFAULT;
0e96f31e 3425 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
043405e1
CO		 3426 goto out;
3427 n = msr_list.nmsrs;
62ef68bb 3428 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
0e96f31e 3429 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
043405e1
CO		 3430 goto out;
3431 r = -E2BIG;
e125e7b6 3432 if (n < msr_list.nmsrs)
043405e1
CO		 3433 goto out;
3434 r = -EFAULT;
3435 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
3436 num_msrs_to_save * sizeof(u32)))
3437 goto out;
e125e7b6 3438 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 3439 &emulated_msrs,
62ef68bb 3440 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 3441 goto out;
3442 r = 0;
3443 break;
3444 }
9c15bb1d
BP		 3445 case KVM_GET_SUPPORTED_CPUID:
3446 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 3447 struct kvm_cpuid2 __user *cpuid_arg = argp;
3448 struct kvm_cpuid2 cpuid;
3449
3450 r = -EFAULT;
0e96f31e 3451 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
674eea0f 3452 goto out;
9c15bb1d
BP		 3453
3454 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
3455 ioctl);
674eea0f
AK		 3456 if (r)
3457 goto out;
3458
3459 r = -EFAULT;
0e96f31e 3460 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
674eea0f
AK		 3461 goto out;
3462 r = 0;
3463 break;
3464 }
890ca9ae 3465 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 3466 r = -EFAULT;
c45dcc71
AR		 3467 if (copy_to_user(argp, &kvm_mce_cap_supported,
3468 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY		 3469 goto out;
3470 r = 0;
3471 break;
801e459a
TL		 3472 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
3473 struct kvm_msr_list __user *user_msr_list = argp;
3474 struct kvm_msr_list msr_list;
3475 unsigned int n;
3476
3477 r = -EFAULT;
3478 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
3479 goto out;
3480 n = msr_list.nmsrs;
3481 msr_list.nmsrs = num_msr_based_features;
3482 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
3483 goto out;
3484 r = -E2BIG;
3485 if (n < msr_list.nmsrs)
3486 goto out;
3487 r = -EFAULT;
3488 if (copy_to_user(user_msr_list->indices, &msr_based_features,
3489 num_msr_based_features * sizeof(u32)))
3490 goto out;
3491 r = 0;
3492 break;
3493 }
3494 case KVM_GET_MSRS:
3495 r = msr_io(NULL, argp, do_get_msr_feature, 1);
3496 break;
890ca9ae 3497 }
043405e1
CO		 3498 default:
3499 r = -EINVAL;
3500 }
3501out:
3502 return r;
3503}
3504
f5f48ee1
SY		 3505static void wbinvd_ipi(void *garbage)
3506{
3507 wbinvd();
3508}
3509
3510static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
3511{
e0f0bbc5 3512 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 3513}
3514
313a3dc7
CO		 3515void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
3516{
f5f48ee1
SY		 3517 /* Address WBINVD may be executed by guest */
3518 if (need_emulate_wbinvd(vcpu)) {
3519 if (kvm_x86_ops->has_wbinvd_exit())
3520 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
3521 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
3522 smp_call_function_single(vcpu->cpu,
3523 wbinvd_ipi, NULL, 1);
3524 }
3525
313a3dc7 3526 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 3527
0dd6a6ed
ZA		 3528 /* Apply any externally detected TSC adjustments (due to suspend) */
3529 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
3530 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
3531 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 3532 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 3533 }
8f6055cb 3534
b0c39dc6 3535 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
6f526ec5 3536 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 3537 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 3538 if (tsc_delta < 0)
3539 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 3540
b0c39dc6 3541 if (kvm_check_tsc_unstable()) {
07c1419a 3542 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 3543 vcpu->arch.last_guest_tsc);
a545ab6a 3544 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 3545 vcpu->arch.tsc_catchup = 1;
c285545f 3546 }
a749e247
PB		 3547
3548 if (kvm_lapic_hv_timer_in_use(vcpu))
3549 kvm_lapic_restart_hv_timer(vcpu);
3550
d98d07ca
MT		 3551 /*
3552 * On a host with synchronized TSC, there is no need to update
3553 * kvmclock on vcpu->cpu migration
3554 */
3555 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 3556 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 3557 if (vcpu->cpu != cpu)
1bd2009e 3558 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 3559 vcpu->cpu = cpu;
6b7d7e76 3560 }
c9aaa895 3561
c9aaa895 3562 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 3563}
3564
0b9f6c46
PX		 3565static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
3566{
b0431382
BO		 3567 struct kvm_host_map map;
3568 struct kvm_steal_time *st;
3569
0b9f6c46
PX		 3570 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3571 return;
3572
a6bd811f 3573 if (vcpu->arch.st.preempted)
8c6de56a
BO		 3574 return;
3575
b0431382
BO		 3576 if (kvm_map_gfn(vcpu, vcpu->arch.st.msr_val >> PAGE_SHIFT, &map,
3577 &vcpu->arch.st.cache, true))
3578 return;
3579
3580 st = map.hva +
3581 offset_in_page(vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS);
0b9f6c46 3582
a6bd811f 3583 st->preempted = vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
0b9f6c46 3584
b0431382 3585 kvm_unmap_gfn(vcpu, &map, &vcpu->arch.st.cache, true, true);
0b9f6c46
PX		 3586}
3587
313a3dc7
CO		 3588void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
3589{
cc0d907c 3590 int idx;
de63ad4c
LM		 3591
3592 if (vcpu->preempted)
3593 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
3594
931f261b
AA		 3595 /*
3596 * Disable page faults because we're in atomic context here.
3597 * kvm_write_guest_offset_cached() would call might_fault()
3598 * that relies on pagefault_disable() to tell if there's a
3599 * bug. NOTE: the write to guest memory may not go through if
3600 * during postcopy live migration or if there's heavy guest
3601 * paging.
3602 */
3603 pagefault_disable();
cc0d907c
AA		 3604 /*
3605 * kvm_memslots() will be called by
3606 * kvm_write_guest_offset_cached() so take the srcu lock.
3607 */
3608 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3609 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3610 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3611 pagefault_enable();
02daab21 3612 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3613 vcpu->arch.last_host_tsc = rdtsc();
efdab992 3614 /*
f9dcf08e
RK		 3615 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3616 * on every vmexit, but if not, we might have a stale dr6 from the
3617 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
efdab992 3618 */
f9dcf08e 3619 set_debugreg(0, 6);
313a3dc7
CO		 3620}
3621
313a3dc7
CO		 3622static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3623 struct kvm_lapic_state *s)
3624{
fa59cc00 3625 if (vcpu->arch.apicv_active)
d62caabb
AS		 3626 kvm_x86_ops->sync_pir_to_irr(vcpu);
3627
a92e2543 3628 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO		 3629}
3630
3631static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3632 struct kvm_lapic_state *s)
3633{
a92e2543
RK		 3634 int r;
3635
3636 r = kvm_apic_set_state(vcpu, s);
3637 if (r)
3638 return r;
cb142eb7 3639 update_cr8_intercept(vcpu);
313a3dc7
CO		 3640
3641 return 0;
3642}
3643
127a457a
MG		 3644static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3645{
3646 return (!lapic_in_kernel(vcpu) ||
3647 kvm_apic_accept_pic_intr(vcpu));
3648}
3649
782d422b
MG		 3650/*
3651 * if userspace requested an interrupt window, check that the
3652 * interrupt window is open.
3653 *
3654 * No need to exit to userspace if we already have an interrupt queued.
3655 */
3656static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3657{
3658 return kvm_arch_interrupt_allowed(vcpu) &&
3659 !kvm_cpu_has_interrupt(vcpu) &&
3660 !kvm_event_needs_reinjection(vcpu) &&
3661 kvm_cpu_accept_dm_intr(vcpu);
3662}
3663
f77bc6a4
ZX		 3664static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3665 struct kvm_interrupt *irq)
3666{
02cdb50f 3667 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3668 return -EINVAL;
1c1a9ce9
SR		 3669
3670 if (!irqchip_in_kernel(vcpu->kvm)) {
3671 kvm_queue_interrupt(vcpu, irq->irq, false);
3672 kvm_make_request(KVM_REQ_EVENT, vcpu);
3673 return 0;
3674 }
3675
3676 /*
3677 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3678 * fail for in-kernel 8259.
3679 */
3680 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3681 return -ENXIO;
f77bc6a4 3682
1c1a9ce9
SR		 3683 if (vcpu->arch.pending_external_vector != -1)
3684 return -EEXIST;
f77bc6a4 3685
1c1a9ce9 3686 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3687 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX		 3688 return 0;
3689}
3690
c4abb7c9
JK		 3691static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3692{
c4abb7c9 3693 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 3694
3695 return 0;
3696}
3697
f077825a
PB		 3698static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3699{
64d60670
PB		 3700 kvm_make_request(KVM_REQ_SMI, vcpu);
3701
f077825a
PB		 3702 return 0;
3703}
3704
b209749f
AK		 3705static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3706 struct kvm_tpr_access_ctl *tac)
3707{
3708 if (tac->flags)
3709 return -EINVAL;
3710 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3711 return 0;
3712}
3713
890ca9ae
HY		 3714static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3715 u64 mcg_cap)
3716{
3717 int r;
3718 unsigned bank_num = mcg_cap & 0xff, bank;
3719
3720 r = -EINVAL;
a9e38c3e 3721 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3722 goto out;
c45dcc71 3723 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY		 3724 goto out;
3725 r = 0;
3726 vcpu->arch.mcg_cap = mcg_cap;
3727 /* Init IA32_MCG_CTL to all 1s */
3728 if (mcg_cap & MCG_CTL_P)
3729 vcpu->arch.mcg_ctl = ~(u64)0;
3730 /* Init IA32_MCi_CTL to all 1s */
3731 for (bank = 0; bank < bank_num; bank++)
3732 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71 3733
92735b1b 3734 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY		 3735out:
3736 return r;
3737}
3738
3739static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3740 struct kvm_x86_mce *mce)
3741{
3742 u64 mcg_cap = vcpu->arch.mcg_cap;
3743 unsigned bank_num = mcg_cap & 0xff;
3744 u64 *banks = vcpu->arch.mce_banks;
3745
3746 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3747 return -EINVAL;
3748 /*
3749 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3750 * reporting is disabled
3751 */
3752 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3753 vcpu->arch.mcg_ctl != ~(u64)0)
3754 return 0;
3755 banks += 4 * mce->bank;
3756 /*
3757 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3758 * reporting is disabled for the bank
3759 */
3760 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3761 return 0;
3762 if (mce->status & MCI_STATUS_UC) {
3763 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3764 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3765 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 3766 return 0;
3767 }
3768 if (banks[1] & MCI_STATUS_VAL)
3769 mce->status |= MCI_STATUS_OVER;
3770 banks[2] = mce->addr;
3771 banks[3] = mce->misc;
3772 vcpu->arch.mcg_status = mce->mcg_status;
3773 banks[1] = mce->status;
3774 kvm_queue_exception(vcpu, MC_VECTOR);
3775 } else if (!(banks[1] & MCI_STATUS_VAL)
3776 || !(banks[1] & MCI_STATUS_UC)) {
3777 if (banks[1] & MCI_STATUS_VAL)
3778 mce->status |= MCI_STATUS_OVER;
3779 banks[2] = mce->addr;
3780 banks[3] = mce->misc;
3781 banks[1] = mce->status;
3782 } else
3783 banks[1] |= MCI_STATUS_OVER;
3784 return 0;
3785}
3786
3cfc3092
JK		 3787static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3788 struct kvm_vcpu_events *events)
3789{
7460fb4a 3790 process_nmi(vcpu);
59073aaf 3791
664f8e26 3792 /*
59073aaf
JM		 3793 * The API doesn't provide the instruction length for software
3794 * exceptions, so don't report them. As long as the guest RIP
3795 * isn't advanced, we should expect to encounter the exception
3796 * again.
664f8e26 3797 */
59073aaf
JM		 3798 if (kvm_exception_is_soft(vcpu->arch.exception.nr)) {
3799 events->exception.injected = 0;
3800 events->exception.pending = 0;
3801 } else {
3802 events->exception.injected = vcpu->arch.exception.injected;
3803 events->exception.pending = vcpu->arch.exception.pending;
3804 /*
3805 * For ABI compatibility, deliberately conflate
3806 * pending and injected exceptions when
3807 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
3808 */
3809 if (!vcpu->kvm->arch.exception_payload_enabled)
3810 events->exception.injected |=
3811 vcpu->arch.exception.pending;
3812 }
3cfc3092
JK		 3813 events->exception.nr = vcpu->arch.exception.nr;
3814 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
3815 events->exception.error_code = vcpu->arch.exception.error_code;
59073aaf
JM		 3816 events->exception_has_payload = vcpu->arch.exception.has_payload;
3817 events->exception_payload = vcpu->arch.exception.payload;
3cfc3092 3818
03b82a30 3819 events->interrupt.injected =
04140b41 3820 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
3cfc3092 3821 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3822 events->interrupt.soft = 0;
37ccdcbe 3823 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3824
3825 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3826 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3827 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3828 events->nmi.pad = 0;
3cfc3092 3829
66450a21 3830 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3831
f077825a
PB		 3832 events->smi.smm = is_smm(vcpu);
3833 events->smi.pending = vcpu->arch.smi_pending;
3834 events->smi.smm_inside_nmi =
3835 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3836 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3837
dab4b911 3838 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3839 | KVM_VCPUEVENT_VALID_SHADOW
3840 | KVM_VCPUEVENT_VALID_SMM);
59073aaf
JM		 3841 if (vcpu->kvm->arch.exception_payload_enabled)
3842 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3843
97e69aa6 3844 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3845}
3846
c5833c7a 3847static void kvm_smm_changed(struct kvm_vcpu *vcpu);
6ef4e07e 3848
3cfc3092
JK		 3849static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3850 struct kvm_vcpu_events *events)
3851{
dab4b911 3852 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3853 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a 3854 | KVM_VCPUEVENT_VALID_SHADOW
59073aaf
JM		 3855 | KVM_VCPUEVENT_VALID_SMM
3856 | KVM_VCPUEVENT_VALID_PAYLOAD))
3cfc3092
JK		 3857 return -EINVAL;
3858
59073aaf
JM		 3859 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3860 if (!vcpu->kvm->arch.exception_payload_enabled)
3861 return -EINVAL;
3862 if (events->exception.pending)
3863 events->exception.injected = 0;
3864 else
3865 events->exception_has_payload = 0;
3866 } else {
3867 events->exception.pending = 0;
3868 events->exception_has_payload = 0;
3869 }
3870
3871 if ((events->exception.injected || events->exception.pending) &&
3872 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
78e546c8
PB		 3873 return -EINVAL;
3874
28bf2888
DH		 3875 /* INITs are latched while in SMM */
3876 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3877 (events->smi.smm || events->smi.pending) &&
3878 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3879 return -EINVAL;
3880
7460fb4a 3881 process_nmi(vcpu);
59073aaf
JM		 3882 vcpu->arch.exception.injected = events->exception.injected;
3883 vcpu->arch.exception.pending = events->exception.pending;
3cfc3092
JK		 3884 vcpu->arch.exception.nr = events->exception.nr;
3885 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3886 vcpu->arch.exception.error_code = events->exception.error_code;
59073aaf
JM		 3887 vcpu->arch.exception.has_payload = events->exception_has_payload;
3888 vcpu->arch.exception.payload = events->exception_payload;
3cfc3092 3889
04140b41 3890 vcpu->arch.interrupt.injected = events->interrupt.injected;
3cfc3092
JK		 3891 vcpu->arch.interrupt.nr = events->interrupt.nr;
3892 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3893 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3894 kvm_x86_ops->set_interrupt_shadow(vcpu,
3895 events->interrupt.shadow);
3cfc3092
JK		 3896
3897 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3898 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3899 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3900 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3901
66450a21 3902 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3903 lapic_in_kernel(vcpu))
66450a21 3904 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3905
f077825a 3906 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
c5833c7a
SC		 3907 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
3908 if (events->smi.smm)
3909 vcpu->arch.hflags |= HF_SMM_MASK;
3910 else
3911 vcpu->arch.hflags &= ~HF_SMM_MASK;
3912 kvm_smm_changed(vcpu);
3913 }
6ef4e07e 3914
f077825a 3915 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL		 3916
3917 if (events->smi.smm) {
3918 if (events->smi.smm_inside_nmi)
3919 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3920 else
f4ef1910 3921 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
ff90afa7
LA		 3922 }
3923
3924 if (lapic_in_kernel(vcpu)) {
3925 if (events->smi.latched_init)
3926 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3927 else
3928 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
f077825a
PB		 3929 }
3930 }
3931
3842d135
AK		 3932 kvm_make_request(KVM_REQ_EVENT, vcpu);
3933
3cfc3092
JK		 3934 return 0;
3935}
3936
a1efbe77
JK		 3937static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3938 struct kvm_debugregs *dbgregs)
3939{
73aaf249
JK		 3940 unsigned long val;
3941
a1efbe77 3942 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3943 kvm_get_dr(vcpu, 6, &val);
73aaf249 3944 dbgregs->dr6 = val;
a1efbe77
JK		 3945 dbgregs->dr7 = vcpu->arch.dr7;
3946 dbgregs->flags = 0;
97e69aa6 3947 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3948}
3949
3950static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3951 struct kvm_debugregs *dbgregs)
3952{
3953 if (dbgregs->flags)
3954 return -EINVAL;
3955
d14bdb55
PB		 3956 if (dbgregs->dr6 & ~0xffffffffull)
3957 return -EINVAL;
3958 if (dbgregs->dr7 & ~0xffffffffull)
3959 return -EINVAL;
3960
a1efbe77 3961 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3962 kvm_update_dr0123(vcpu);
a1efbe77 3963 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3964 kvm_update_dr6(vcpu);
a1efbe77 3965 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3966 kvm_update_dr7(vcpu);
a1efbe77 3967
a1efbe77
JK		 3968 return 0;
3969}
3970
df1daba7
PB		 3971#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3972
3973static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3974{
b666a4b6 3975 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
400e4b20 3976 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB		 3977 u64 valid;
3978
3979 /*
3980 * Copy legacy XSAVE area, to avoid complications with CPUID
3981 * leaves 0 and 1 in the loop below.
3982 */
3983 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3984
3985 /* Set XSTATE_BV */
00c87e9a 3986 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB		 3987 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3988
3989 /*
3990 * Copy each region from the possibly compacted offset to the
3991 * non-compacted offset.
3992 */
d91cab78 3993 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 3994 while (valid) {
abd16d68
SAS		 3995 u64 xfeature_mask = valid & -valid;
3996 int xfeature_nr = fls64(xfeature_mask) - 1;
3997 void *src = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 3998
3999 if (src) {
4000 u32 size, offset, ecx, edx;
abd16d68 4001 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 4002 &size, &offset, &ecx, &edx);
abd16d68 4003 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 4004 memcpy(dest + offset, &vcpu->arch.pkru,
4005 sizeof(vcpu->arch.pkru));
4006 else
4007 memcpy(dest + offset, src, size);
4008
df1daba7
PB		 4009 }
4010
abd16d68 4011 valid -= xfeature_mask;
df1daba7
PB		 4012 }
4013}
4014
4015static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
4016{
b666a4b6 4017 struct xregs_state *xsave = &vcpu->arch.guest_fpu->state.xsave;
df1daba7
PB		 4018 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
4019 u64 valid;
4020
4021 /*
4022 * Copy legacy XSAVE area, to avoid complications with CPUID
4023 * leaves 0 and 1 in the loop below.
4024 */
4025 memcpy(xsave, src, XSAVE_HDR_OFFSET);
4026
4027 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 4028 xsave->header.xfeatures = xstate_bv;
782511b0 4029 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 4030 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB		 4031
4032 /*
4033 * Copy each region from the non-compacted offset to the
4034 * possibly compacted offset.
4035 */
d91cab78 4036 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7 4037 while (valid) {
abd16d68
SAS		 4038 u64 xfeature_mask = valid & -valid;
4039 int xfeature_nr = fls64(xfeature_mask) - 1;
4040 void *dest = get_xsave_addr(xsave, xfeature_nr);
df1daba7
PB		 4041
4042 if (dest) {
4043 u32 size, offset, ecx, edx;
abd16d68 4044 cpuid_count(XSTATE_CPUID, xfeature_nr,
df1daba7 4045 &size, &offset, &ecx, &edx);
abd16d68 4046 if (xfeature_nr == XFEATURE_PKRU)
38cfd5e3
PB		 4047 memcpy(&vcpu->arch.pkru, src + offset,
4048 sizeof(vcpu->arch.pkru));
4049 else
4050 memcpy(dest, src + offset, size);
ee4100da 4051 }
df1daba7 4052
abd16d68 4053 valid -= xfeature_mask;
df1daba7
PB		 4054 }
4055}
4056
2d5b5a66
SY		 4057static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
4058 struct kvm_xsave *guest_xsave)
4059{
d366bf7e 4060 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB		 4061 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
4062 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 4063 } else {
2d5b5a66 4064 memcpy(guest_xsave->region,
b666a4b6 4065 &vcpu->arch.guest_fpu->state.fxsave,
c47ada30 4066 sizeof(struct fxregs_state));
2d5b5a66 4067 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 4068 XFEATURE_MASK_FPSSE;
2d5b5a66
SY		 4069 }
4070}
4071
a575813b
WL		 4072#define XSAVE_MXCSR_OFFSET 24
4073
2d5b5a66
SY		 4074static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
4075 struct kvm_xsave *guest_xsave)
4076{
4077 u64 xstate_bv =
4078 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 4079 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 4080
d366bf7e 4081 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB		 4082 /*
4083 * Here we allow setting states that are not present in
4084 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
4085 * with old userspace.
4086 */
a575813b
WL		 4087 if (xstate_bv & ~kvm_supported_xcr0() ||
4088 mxcsr & ~mxcsr_feature_mask)
d7876f1b 4089 return -EINVAL;
df1daba7 4090 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 4091 } else {
a575813b
WL		 4092 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
4093 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 4094 return -EINVAL;
b666a4b6 4095 memcpy(&vcpu->arch.guest_fpu->state.fxsave,
c47ada30 4096 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY		 4097 }
4098 return 0;
4099}
4100
4101static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
4102 struct kvm_xcrs *guest_xcrs)
4103{
d366bf7e 4104 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY		 4105 guest_xcrs->nr_xcrs = 0;
4106 return;
4107 }
4108
4109 guest_xcrs->nr_xcrs = 1;
4110 guest_xcrs->flags = 0;
4111 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
4112 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
4113}
4114
4115static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
4116 struct kvm_xcrs *guest_xcrs)
4117{
4118 int i, r = 0;
4119
d366bf7e 4120 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY		 4121 return -EINVAL;
4122
4123 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
4124 return -EINVAL;
4125
4126 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
4127 /* Only support XCR0 currently */
c67a04cb 4128 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 4129 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 4130 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 4131 break;
4132 }
4133 if (r)
4134 r = -EINVAL;
4135 return r;
4136}
4137
1c0b28c2
EM		 4138/*
4139 * kvm_set_guest_paused() indicates to the guest kernel that it has been
4140 * stopped by the hypervisor. This function will be called from the host only.
4141 * EINVAL is returned when the host attempts to set the flag for a guest that
4142 * does not support pv clocks.
4143 */
4144static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
4145{
0b79459b 4146 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 4147 return -EINVAL;
51d59c6b 4148 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 4149 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4150 return 0;
4151}
4152
5c919412
AS		 4153static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
4154 struct kvm_enable_cap *cap)
4155{
57b119da
VK		 4156 int r;
4157 uint16_t vmcs_version;
4158 void __user *user_ptr;
4159
5c919412
AS		 4160 if (cap->flags)
4161 return -EINVAL;
4162
4163 switch (cap->cap) {
efc479e6
RK		 4164 case KVM_CAP_HYPERV_SYNIC2:
4165 if (cap->args[0])
4166 return -EINVAL;
b2869f28
GS		 4167 /* fall through */
4168
5c919412 4169 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL		 4170 if (!irqchip_in_kernel(vcpu->kvm))
4171 return -EINVAL;
efc479e6
RK		 4172 return kvm_hv_activate_synic(vcpu, cap->cap ==
4173 KVM_CAP_HYPERV_SYNIC2);
57b119da 4174 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5158917c
SC		 4175 if (!kvm_x86_ops->nested_enable_evmcs)
4176 return -ENOTTY;
57b119da
VK		 4177 r = kvm_x86_ops->nested_enable_evmcs(vcpu, &vmcs_version);
4178 if (!r) {
4179 user_ptr = (void __user *)(uintptr_t)cap->args[0];
4180 if (copy_to_user(user_ptr, &vmcs_version,
4181 sizeof(vmcs_version)))
4182 r = -EFAULT;
4183 }
4184 return r;
344c6c80
TL		 4185 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4186 if (!kvm_x86_ops->enable_direct_tlbflush)
4187 return -ENOTTY;
4188
4189 return kvm_x86_ops->enable_direct_tlbflush(vcpu);
57b119da 4190
5c919412
AS		 4191 default:
4192 return -EINVAL;
4193 }
4194}
4195
313a3dc7
CO		 4196long kvm_arch_vcpu_ioctl(struct file *filp,
4197 unsigned int ioctl, unsigned long arg)
4198{
4199 struct kvm_vcpu *vcpu = filp->private_data;
4200 void __user *argp = (void __user *)arg;
4201 int r;
d1ac91d8
AK		 4202 union {
4203 struct kvm_lapic_state *lapic;
4204 struct kvm_xsave *xsave;
4205 struct kvm_xcrs *xcrs;
4206 void *buffer;
4207 } u;
4208
9b062471
CD		 4209 vcpu_load(vcpu);
4210
d1ac91d8 4211 u.buffer = NULL;
313a3dc7
CO		 4212 switch (ioctl) {
4213 case KVM_GET_LAPIC: {
2204ae3c 4214 r = -EINVAL;
bce87cce 4215 if (!lapic_in_kernel(vcpu))
2204ae3c 4216 goto out;
254272ce
BG		 4217 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
4218 GFP_KERNEL_ACCOUNT);
313a3dc7 4219
b772ff36 4220 r = -ENOMEM;
d1ac91d8 4221 if (!u.lapic)
b772ff36 4222 goto out;
d1ac91d8 4223 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 4224 if (r)
4225 goto out;
4226 r = -EFAULT;
d1ac91d8 4227 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 4228 goto out;
4229 r = 0;
4230 break;
4231 }
4232 case KVM_SET_LAPIC: {
2204ae3c 4233 r = -EINVAL;
bce87cce 4234 if (!lapic_in_kernel(vcpu))
2204ae3c 4235 goto out;
ff5c2c03 4236 u.lapic = memdup_user(argp, sizeof(*u.lapic));
9b062471
CD		 4237 if (IS_ERR(u.lapic)) {
4238 r = PTR_ERR(u.lapic);
4239 goto out_nofree;
4240 }
ff5c2c03 4241
d1ac91d8 4242 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 4243 break;
4244 }
f77bc6a4
ZX		 4245 case KVM_INTERRUPT: {
4246 struct kvm_interrupt irq;
4247
4248 r = -EFAULT;
0e96f31e 4249 if (copy_from_user(&irq, argp, sizeof(irq)))
f77bc6a4
ZX		 4250 goto out;
4251 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 4252 break;
4253 }
c4abb7c9
JK		 4254 case KVM_NMI: {
4255 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 4256 break;
4257 }
f077825a
PB		 4258 case KVM_SMI: {
4259 r = kvm_vcpu_ioctl_smi(vcpu);
4260 break;
4261 }
313a3dc7
CO		 4262 case KVM_SET_CPUID: {
4263 struct kvm_cpuid __user *cpuid_arg = argp;
4264 struct kvm_cpuid cpuid;
4265
4266 r = -EFAULT;
0e96f31e 4267 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
313a3dc7
CO		 4268 goto out;
4269 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 4270 break;
4271 }
07716717
DK		 4272 case KVM_SET_CPUID2: {
4273 struct kvm_cpuid2 __user *cpuid_arg = argp;
4274 struct kvm_cpuid2 cpuid;
4275
4276 r = -EFAULT;
0e96f31e 4277 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4278 goto out;
4279 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 4280 cpuid_arg->entries);
07716717
DK		 4281 break;
4282 }
4283 case KVM_GET_CPUID2: {
4284 struct kvm_cpuid2 __user *cpuid_arg = argp;
4285 struct kvm_cpuid2 cpuid;
4286
4287 r = -EFAULT;
0e96f31e 4288 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
07716717
DK		 4289 goto out;
4290 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 4291 cpuid_arg->entries);
07716717
DK		 4292 if (r)
4293 goto out;
4294 r = -EFAULT;
0e96f31e 4295 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
07716717
DK		 4296 goto out;
4297 r = 0;
4298 break;
4299 }
801e459a
TL		 4300 case KVM_GET_MSRS: {
4301 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 4302 r = msr_io(vcpu, argp, do_get_msr, 1);
801e459a 4303 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4304 break;
801e459a
TL		 4305 }
4306 case KVM_SET_MSRS: {
4307 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 4308 r = msr_io(vcpu, argp, do_set_msr, 0);
801e459a 4309 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 4310 break;
801e459a 4311 }
b209749f
AK		 4312 case KVM_TPR_ACCESS_REPORTING: {
4313 struct kvm_tpr_access_ctl tac;
4314
4315 r = -EFAULT;
0e96f31e 4316 if (copy_from_user(&tac, argp, sizeof(tac)))
b209749f
AK		 4317 goto out;
4318 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
4319 if (r)
4320 goto out;
4321 r = -EFAULT;
0e96f31e 4322 if (copy_to_user(argp, &tac, sizeof(tac)))
b209749f
AK		 4323 goto out;
4324 r = 0;
4325 break;
4326 };
b93463aa
AK		 4327 case KVM_SET_VAPIC_ADDR: {
4328 struct kvm_vapic_addr va;
7301d6ab 4329 int idx;
b93463aa
AK		 4330
4331 r = -EINVAL;
35754c98 4332 if (!lapic_in_kernel(vcpu))
b93463aa
AK		 4333 goto out;
4334 r = -EFAULT;
0e96f31e 4335 if (copy_from_user(&va, argp, sizeof(va)))
b93463aa 4336 goto out;
7301d6ab 4337 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 4338 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 4339 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4340 break;
4341 }
890ca9ae
HY		 4342 case KVM_X86_SETUP_MCE: {
4343 u64 mcg_cap;
4344
4345 r = -EFAULT;
0e96f31e 4346 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
890ca9ae
HY		 4347 goto out;
4348 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
4349 break;
4350 }
4351 case KVM_X86_SET_MCE: {
4352 struct kvm_x86_mce mce;
4353
4354 r = -EFAULT;
0e96f31e 4355 if (copy_from_user(&mce, argp, sizeof(mce)))
890ca9ae
HY		 4356 goto out;
4357 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
4358 break;
4359 }
3cfc3092
JK		 4360 case KVM_GET_VCPU_EVENTS: {
4361 struct kvm_vcpu_events events;
4362
4363 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
4364
4365 r = -EFAULT;
4366 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
4367 break;
4368 r = 0;
4369 break;
4370 }
4371 case KVM_SET_VCPU_EVENTS: {
4372 struct kvm_vcpu_events events;
4373
4374 r = -EFAULT;
4375 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
4376 break;
4377
4378 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
4379 break;
4380 }
a1efbe77
JK		 4381 case KVM_GET_DEBUGREGS: {
4382 struct kvm_debugregs dbgregs;
4383
4384 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
4385
4386 r = -EFAULT;
4387 if (copy_to_user(argp, &dbgregs,
4388 sizeof(struct kvm_debugregs)))
4389 break;
4390 r = 0;
4391 break;
4392 }
4393 case KVM_SET_DEBUGREGS: {
4394 struct kvm_debugregs dbgregs;
4395
4396 r = -EFAULT;
4397 if (copy_from_user(&dbgregs, argp,
4398 sizeof(struct kvm_debugregs)))
4399 break;
4400
4401 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
4402 break;
4403 }
2d5b5a66 4404 case KVM_GET_XSAVE: {
254272ce 4405 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
2d5b5a66 4406 r = -ENOMEM;
d1ac91d8 4407 if (!u.xsave)
2d5b5a66
SY		 4408 break;
4409
d1ac91d8 4410 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4411
4412 r = -EFAULT;
d1ac91d8 4413 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 4414 break;
4415 r = 0;
4416 break;
4417 }
4418 case KVM_SET_XSAVE: {
ff5c2c03 4419 u.xsave = memdup_user(argp, sizeof(*u.xsave));
9b062471
CD		 4420 if (IS_ERR(u.xsave)) {
4421 r = PTR_ERR(u.xsave);
4422 goto out_nofree;
4423 }
2d5b5a66 4424
d1ac91d8 4425 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 4426 break;
4427 }
4428 case KVM_GET_XCRS: {
254272ce 4429 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
2d5b5a66 4430 r = -ENOMEM;
d1ac91d8 4431 if (!u.xcrs)
2d5b5a66
SY		 4432 break;
4433
d1ac91d8 4434 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4435
4436 r = -EFAULT;
d1ac91d8 4437 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 4438 sizeof(struct kvm_xcrs)))
4439 break;
4440 r = 0;
4441 break;
4442 }
4443 case KVM_SET_XCRS: {
ff5c2c03 4444 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
9b062471
CD		 4445 if (IS_ERR(u.xcrs)) {
4446 r = PTR_ERR(u.xcrs);
4447 goto out_nofree;
4448 }
2d5b5a66 4449
d1ac91d8 4450 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 4451 break;
4452 }
92a1f12d
JR		 4453 case KVM_SET_TSC_KHZ: {
4454 u32 user_tsc_khz;
4455
4456 r = -EINVAL;
92a1f12d
JR		 4457 user_tsc_khz = (u32)arg;
4458
4459 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
4460 goto out;
4461
cc578287
ZA		 4462 if (user_tsc_khz == 0)
4463 user_tsc_khz = tsc_khz;
4464
381d585c
HZ		 4465 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
4466 r = 0;
92a1f12d 4467
92a1f12d
JR		 4468 goto out;
4469 }
4470 case KVM_GET_TSC_KHZ: {
cc578287 4471 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 4472 goto out;
4473 }
1c0b28c2
EM		 4474 case KVM_KVMCLOCK_CTRL: {
4475 r = kvm_set_guest_paused(vcpu);
4476 goto out;
4477 }
5c919412
AS		 4478 case KVM_ENABLE_CAP: {
4479 struct kvm_enable_cap cap;
4480
4481 r = -EFAULT;
4482 if (copy_from_user(&cap, argp, sizeof(cap)))
4483 goto out;
4484 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
4485 break;
4486 }
8fcc4b59
JM		 4487 case KVM_GET_NESTED_STATE: {
4488 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4489 u32 user_data_size;
4490
4491 r = -EINVAL;
4492 if (!kvm_x86_ops->get_nested_state)
4493 break;
4494
4495 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
26b471c7 4496 r = -EFAULT;
8fcc4b59 4497 if (get_user(user_data_size, &user_kvm_nested_state->size))
26b471c7 4498 break;
8fcc4b59
JM		 4499
4500 r = kvm_x86_ops->get_nested_state(vcpu, user_kvm_nested_state,
4501 user_data_size);
4502 if (r < 0)
26b471c7 4503 break;
8fcc4b59
JM		 4504
4505 if (r > user_data_size) {
4506 if (put_user(r, &user_kvm_nested_state->size))
26b471c7
LA		 4507 r = -EFAULT;
4508 else
4509 r = -E2BIG;
4510 break;
8fcc4b59 4511 }
26b471c7 4512
8fcc4b59
JM		 4513 r = 0;
4514 break;
4515 }
4516 case KVM_SET_NESTED_STATE: {
4517 struct kvm_nested_state __user *user_kvm_nested_state = argp;
4518 struct kvm_nested_state kvm_state;
ad5996d9 4519 int idx;
8fcc4b59
JM		 4520
4521 r = -EINVAL;
4522 if (!kvm_x86_ops->set_nested_state)
4523 break;
4524
26b471c7 4525 r = -EFAULT;
8fcc4b59 4526 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
26b471c7 4527 break;
8fcc4b59 4528
26b471c7 4529 r = -EINVAL;
8fcc4b59 4530 if (kvm_state.size < sizeof(kvm_state))
26b471c7 4531 break;
8fcc4b59
JM		 4532
4533 if (kvm_state.flags &
8cab6507
VK		 4534 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
4535 | KVM_STATE_NESTED_EVMCS))
26b471c7 4536 break;
8fcc4b59
JM		 4537
4538 /* nested_run_pending implies guest_mode. */
8cab6507
VK		 4539 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
4540 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
26b471c7 4541 break;
8fcc4b59 4542
ad5996d9 4543 idx = srcu_read_lock(&vcpu->kvm->srcu);
8fcc4b59 4544 r = kvm_x86_ops->set_nested_state(vcpu, user_kvm_nested_state, &kvm_state);
ad5996d9 4545 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8fcc4b59
JM		 4546 break;
4547 }
2bc39970
VK		 4548 case KVM_GET_SUPPORTED_HV_CPUID: {
4549 struct kvm_cpuid2 __user *cpuid_arg = argp;
4550 struct kvm_cpuid2 cpuid;
4551
4552 r = -EFAULT;
4553 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4554 goto out;
4555
4556 r = kvm_vcpu_ioctl_get_hv_cpuid(vcpu, &cpuid,
4557 cpuid_arg->entries);
4558 if (r)
4559 goto out;
4560
4561 r = -EFAULT;
4562 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4563 goto out;
4564 r = 0;
4565 break;
4566 }
313a3dc7
CO		 4567 default:
4568 r = -EINVAL;
4569 }
4570out:
d1ac91d8 4571 kfree(u.buffer);
9b062471
CD		 4572out_nofree:
4573 vcpu_put(vcpu);
313a3dc7
CO		 4574 return r;
4575}
4576
1499fa80 4577vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
5b1c1493
CO		 4578{
4579 return VM_FAULT_SIGBUS;
4580}
4581
1fe779f8
CO		 4582static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
4583{
4584 int ret;
4585
4586 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 4587 return -EINVAL;
1fe779f8
CO		 4588 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
4589 return ret;
4590}
4591
b927a3ce
SY		 4592static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
4593 u64 ident_addr)
4594{
2ac52ab8 4595 return kvm_x86_ops->set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 4596}
4597
1fe779f8 4598static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
bc8a3d89 4599 unsigned long kvm_nr_mmu_pages)
1fe779f8
CO		 4600{
4601 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
4602 return -EINVAL;
4603
79fac95e 4604 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 4605
4606 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 4607 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 4608
79fac95e 4609 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 4610 return 0;
4611}
4612
bc8a3d89 4613static unsigned long kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1fe779f8 4614{
39de71ec 4615 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 4616}
4617
1fe779f8
CO		 4618static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4619{
90bca052 4620 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4621 int r;
4622
4623 r = 0;
4624 switch (chip->chip_id) {
4625 case KVM_IRQCHIP_PIC_MASTER:
90bca052 4626 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO		 4627 sizeof(struct kvm_pic_state));
4628 break;
4629 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 4630 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO		 4631 sizeof(struct kvm_pic_state));
4632 break;
4633 case KVM_IRQCHIP_IOAPIC:
33392b49 4634 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4635 break;
4636 default:
4637 r = -EINVAL;
4638 break;
4639 }
4640 return r;
4641}
4642
4643static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
4644{
90bca052 4645 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO		 4646 int r;
4647
4648 r = 0;
4649 switch (chip->chip_id) {
4650 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH		 4651 spin_lock(&pic->lock);
4652 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 4653 sizeof(struct kvm_pic_state));
90bca052 4654 spin_unlock(&pic->lock);
1fe779f8
CO		 4655 break;
4656 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH		 4657 spin_lock(&pic->lock);
4658 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 4659 sizeof(struct kvm_pic_state));
90bca052 4660 spin_unlock(&pic->lock);
1fe779f8
CO		 4661 break;
4662 case KVM_IRQCHIP_IOAPIC:
33392b49 4663 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 4664 break;
4665 default:
4666 r = -EINVAL;
4667 break;
4668 }
90bca052 4669 kvm_pic_update_irq(pic);
1fe779f8
CO		 4670 return r;
4671}
4672
e0f63cb9
SY		 4673static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4674{
34f3941c
RK		 4675 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
4676
4677 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
4678
4679 mutex_lock(&kps->lock);
4680 memcpy(ps, &kps->channels, sizeof(*ps));
4681 mutex_unlock(&kps->lock);
2da29bcc 4682 return 0;
e0f63cb9
SY		 4683}
4684
4685static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
4686{
0185604c 4687 int i;
09edea72
RK		 4688 struct kvm_pit *pit = kvm->arch.vpit;
4689
4690 mutex_lock(&pit->pit_state.lock);
34f3941c 4691 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 4692 for (i = 0; i < 3; i++)
09edea72
RK		 4693 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
4694 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4695 return 0;
e9f42757
BK		 4696}
4697
4698static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4699{
e9f42757
BK		 4700 mutex_lock(&kvm->arch.vpit->pit_state.lock);
4701 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
4702 sizeof(ps->channels));
4703 ps->flags = kvm->arch.vpit->pit_state.flags;
4704 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 4705 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 4706 return 0;
e9f42757
BK		 4707}
4708
4709static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
4710{
2da29bcc 4711 int start = 0;
0185604c 4712 int i;
e9f42757 4713 u32 prev_legacy, cur_legacy;
09edea72
RK		 4714 struct kvm_pit *pit = kvm->arch.vpit;
4715
4716 mutex_lock(&pit->pit_state.lock);
4717 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK		 4718 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
4719 if (!prev_legacy && cur_legacy)
4720 start = 1;
09edea72
RK		 4721 memcpy(&pit->pit_state.channels, &ps->channels,
4722 sizeof(pit->pit_state.channels));
4723 pit->pit_state.flags = ps->flags;
0185604c 4724 for (i = 0; i < 3; i++)
09edea72 4725 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 4726 start && i == 0);
09edea72 4727 mutex_unlock(&pit->pit_state.lock);
2da29bcc 4728 return 0;
e0f63cb9
SY		 4729}
4730
52d939a0
MT		 4731static int kvm_vm_ioctl_reinject(struct kvm *kvm,
4732 struct kvm_reinject_control *control)
4733{
71474e2f
RK		 4734 struct kvm_pit *pit = kvm->arch.vpit;
4735
71474e2f
RK		 4736 /* pit->pit_state.lock was overloaded to prevent userspace from getting
4737 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
4738 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
4739 */
4740 mutex_lock(&pit->pit_state.lock);
4741 kvm_pit_set_reinject(pit, control->pit_reinject);
4742 mutex_unlock(&pit->pit_state.lock);
b39c90b6 4743
52d939a0
MT		 4744 return 0;
4745}
4746
95d4c16c 4747/**
60c34612
TY		 4748 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4749 * @kvm: kvm instance
4750 * @log: slot id and address to which we copy the log
95d4c16c 4751 *
e108ff2f
PB		 4752 * Steps 1-4 below provide general overview of dirty page logging. See
4753 * kvm_get_dirty_log_protect() function description for additional details.
4754 *
4755 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4756 * always flush the TLB (step 4) even if previous step failed and the dirty
4757 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4758 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4759 * writes will be marked dirty for next log read.
95d4c16c 4760 *
60c34612
TY		 4761 * 1. Take a snapshot of the bit and clear it if needed.
4762 * 2. Write protect the corresponding page.
e108ff2f
PB		 4763 * 3. Copy the snapshot to the userspace.
4764 * 4. Flush TLB's if needed.
5bb064dc 4765 */
60c34612 4766int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4767{
8fe65a82 4768 bool flush = false;
e108ff2f 4769 int r;
5bb064dc 4770
79fac95e 4771 mutex_lock(&kvm->slots_lock);
5bb064dc 4772
88178fd4
KH		 4773 /*
4774 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4775 */
4776 if (kvm_x86_ops->flush_log_dirty)
4777 kvm_x86_ops->flush_log_dirty(kvm);
4778
8fe65a82 4779 r = kvm_get_dirty_log_protect(kvm, log, &flush);
198c74f4
XG		 4780
4781 /*
4782 * All the TLBs can be flushed out of mmu lock, see the comments in
4783 * kvm_mmu_slot_remove_write_access().
4784 */
e108ff2f 4785 lockdep_assert_held(&kvm->slots_lock);
8fe65a82 4786 if (flush)
2a31b9db
PB		 4787 kvm_flush_remote_tlbs(kvm);
4788
4789 mutex_unlock(&kvm->slots_lock);
4790 return r;
4791}
4792
4793int kvm_vm_ioctl_clear_dirty_log(struct kvm *kvm, struct kvm_clear_dirty_log *log)
4794{
4795 bool flush = false;
4796 int r;
4797
4798 mutex_lock(&kvm->slots_lock);
4799
4800 /*
4801 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4802 */
4803 if (kvm_x86_ops->flush_log_dirty)
4804 kvm_x86_ops->flush_log_dirty(kvm);
4805
4806 r = kvm_clear_dirty_log_protect(kvm, log, &flush);
4807
4808 /*
4809 * All the TLBs can be flushed out of mmu lock, see the comments in
4810 * kvm_mmu_slot_remove_write_access().
4811 */
4812 lockdep_assert_held(&kvm->slots_lock);
4813 if (flush)
198c74f4
XG		 4814 kvm_flush_remote_tlbs(kvm);
4815
79fac95e 4816 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 4817 return r;
4818}
4819
aa2fbe6d
YZ		 4820int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4821 bool line_status)
23d43cf9
CD		 4822{
4823 if (!irqchip_in_kernel(kvm))
4824 return -ENXIO;
4825
4826 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 4827 irq_event->irq, irq_event->level,
4828 line_status);
23d43cf9
CD		 4829 return 0;
4830}
4831
e5d83c74
PB		 4832int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4833 struct kvm_enable_cap *cap)
90de4a18
NA		 4834{
4835 int r;
4836
4837 if (cap->flags)
4838 return -EINVAL;
4839
4840 switch (cap->cap) {
4841 case KVM_CAP_DISABLE_QUIRKS:
4842 kvm->arch.disabled_quirks = cap->args[0];
4843 r = 0;
4844 break;
49df6397
SR		 4845 case KVM_CAP_SPLIT_IRQCHIP: {
4846 mutex_lock(&kvm->lock);
b053b2ae
SR		 4847 r = -EINVAL;
4848 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4849 goto split_irqchip_unlock;
49df6397
SR		 4850 r = -EEXIST;
4851 if (irqchip_in_kernel(kvm))
4852 goto split_irqchip_unlock;
557abc40 4853 if (kvm->created_vcpus)
49df6397
SR		 4854 goto split_irqchip_unlock;
4855 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4856 if (r)
49df6397
SR		 4857 goto split_irqchip_unlock;
4858 /* Pairs with irqchip_in_kernel. */
4859 smp_wmb();
49776faf 4860 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4861 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR		 4862 r = 0;
4863split_irqchip_unlock:
4864 mutex_unlock(&kvm->lock);
4865 break;
4866 }
37131313
RK		 4867 case KVM_CAP_X2APIC_API:
4868 r = -EINVAL;
4869 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4870 break;
4871
4872 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4873 kvm->arch.x2apic_format = true;
c519265f
RK		 4874 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4875 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK		 4876
4877 r = 0;
4878 break;
4d5422ce
WL		 4879 case KVM_CAP_X86_DISABLE_EXITS:
4880 r = -EINVAL;
4881 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
4882 break;
4883
4884 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
4885 kvm_can_mwait_in_guest())
4886 kvm->arch.mwait_in_guest = true;
766d3571 4887 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
caa057a2 4888 kvm->arch.hlt_in_guest = true;
b31c114b
WL		 4889 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
4890 kvm->arch.pause_in_guest = true;
b5170063
WL		 4891 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
4892 kvm->arch.cstate_in_guest = true;
4d5422ce
WL		 4893 r = 0;
4894 break;
6fbbde9a
DS		 4895 case KVM_CAP_MSR_PLATFORM_INFO:
4896 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
4897 r = 0;
c4f55198
JM		 4898 break;
4899 case KVM_CAP_EXCEPTION_PAYLOAD:
4900 kvm->arch.exception_payload_enabled = cap->args[0];
4901 r = 0;
6fbbde9a 4902 break;
90de4a18
NA		 4903 default:
4904 r = -EINVAL;
4905 break;
4906 }
4907 return r;
4908}
4909
1fe779f8
CO		 4910long kvm_arch_vm_ioctl(struct file *filp,
4911 unsigned int ioctl, unsigned long arg)
4912{
4913 struct kvm *kvm = filp->private_data;
4914 void __user *argp = (void __user *)arg;
367e1319 4915 int r = -ENOTTY;
f0d66275
DH		 4916 /*
4917 * This union makes it completely explicit to gcc-3.x
4918 * that these two variables' stack usage should be
4919 * combined, not added together.
4920 */
4921 union {
4922 struct kvm_pit_state ps;
e9f42757 4923 struct kvm_pit_state2 ps2;
c5ff41ce 4924 struct kvm_pit_config pit_config;
f0d66275 4925 } u;
1fe779f8
CO		 4926
4927 switch (ioctl) {
4928 case KVM_SET_TSS_ADDR:
4929 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4930 break;
b927a3ce
SY		 4931 case KVM_SET_IDENTITY_MAP_ADDR: {
4932 u64 ident_addr;
4933
1af1ac91
DH		 4934 mutex_lock(&kvm->lock);
4935 r = -EINVAL;
4936 if (kvm->created_vcpus)
4937 goto set_identity_unlock;
b927a3ce 4938 r = -EFAULT;
0e96f31e 4939 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
1af1ac91 4940 goto set_identity_unlock;
b927a3ce 4941 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH		 4942set_identity_unlock:
4943 mutex_unlock(&kvm->lock);
b927a3ce
SY		 4944 break;
4945 }
1fe779f8
CO		 4946 case KVM_SET_NR_MMU_PAGES:
4947 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 4948 break;
4949 case KVM_GET_NR_MMU_PAGES:
4950 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4951 break;
3ddea128 4952 case KVM_CREATE_IRQCHIP: {
3ddea128 4953 mutex_lock(&kvm->lock);
09941366 4954
3ddea128 4955 r = -EEXIST;
35e6eaa3 4956 if (irqchip_in_kernel(kvm))
3ddea128 4957 goto create_irqchip_unlock;
09941366 4958
3e515705 4959 r = -EINVAL;
557abc40 4960 if (kvm->created_vcpus)
3e515705 4961 goto create_irqchip_unlock;
09941366
RK		 4962
4963 r = kvm_pic_init(kvm);
4964 if (r)
3ddea128 4965 goto create_irqchip_unlock;
09941366
RK		 4966
4967 r = kvm_ioapic_init(kvm);
4968 if (r) {
09941366 4969 kvm_pic_destroy(kvm);
3ddea128 4970 goto create_irqchip_unlock;
09941366
RK		 4971 }
4972
399ec807
AK		 4973 r = kvm_setup_default_irq_routing(kvm);
4974 if (r) {
72bb2fcd 4975 kvm_ioapic_destroy(kvm);
09941366 4976 kvm_pic_destroy(kvm);
71ba994c 4977 goto create_irqchip_unlock;
399ec807 4978 }
49776faf 4979 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4980 smp_wmb();
49776faf 4981 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT		 4982 create_irqchip_unlock:
4983 mutex_unlock(&kvm->lock);
1fe779f8 4984 break;
3ddea128 4985 }
7837699f 4986 case KVM_CREATE_PIT:
c5ff41ce
JK		 4987 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4988 goto create_pit;
4989 case KVM_CREATE_PIT2:
4990 r = -EFAULT;
4991 if (copy_from_user(&u.pit_config, argp,
4992 sizeof(struct kvm_pit_config)))
4993 goto out;
4994 create_pit:
250715a6 4995 mutex_lock(&kvm->lock);
269e05e4
AK		 4996 r = -EEXIST;
4997 if (kvm->arch.vpit)
4998 goto create_pit_unlock;
7837699f 4999 r = -ENOMEM;
c5ff41ce 5000 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 5001 if (kvm->arch.vpit)
5002 r = 0;
269e05e4 5003 create_pit_unlock:
250715a6 5004 mutex_unlock(&kvm->lock);
7837699f 5005 break;
1fe779f8
CO		 5006 case KVM_GET_IRQCHIP: {
5007 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 5008 struct kvm_irqchip *chip;
1fe779f8 5009
ff5c2c03
SL		 5010 chip = memdup_user(argp, sizeof(*chip));
5011 if (IS_ERR(chip)) {
5012 r = PTR_ERR(chip);
1fe779f8 5013 goto out;
ff5c2c03
SL		 5014 }
5015
1fe779f8 5016 r = -ENXIO;
826da321 5017 if (!irqchip_kernel(kvm))
f0d66275
DH		 5018 goto get_irqchip_out;
5019 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 5020 if (r)
f0d66275 5021 goto get_irqchip_out;
1fe779f8 5022 r = -EFAULT;
0e96f31e 5023 if (copy_to_user(argp, chip, sizeof(*chip)))
f0d66275 5024 goto get_irqchip_out;
1fe779f8 5025 r = 0;
f0d66275
DH		 5026 get_irqchip_out:
5027 kfree(chip);
1fe779f8
CO		 5028 break;
5029 }
5030 case KVM_SET_IRQCHIP: {
5031 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 5032 struct kvm_irqchip *chip;
1fe779f8 5033
ff5c2c03
SL		 5034 chip = memdup_user(argp, sizeof(*chip));
5035 if (IS_ERR(chip)) {
5036 r = PTR_ERR(chip);
1fe779f8 5037 goto out;
ff5c2c03
SL		 5038 }
5039
1fe779f8 5040 r = -ENXIO;
826da321 5041 if (!irqchip_kernel(kvm))
f0d66275
DH		 5042 goto set_irqchip_out;
5043 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
f0d66275
DH		 5044 set_irqchip_out:
5045 kfree(chip);
1fe779f8
CO		 5046 break;
5047 }
e0f63cb9 5048 case KVM_GET_PIT: {
e0f63cb9 5049 r = -EFAULT;
f0d66275 5050 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 5051 goto out;
5052 r = -ENXIO;
5053 if (!kvm->arch.vpit)
5054 goto out;
f0d66275 5055 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 5056 if (r)
5057 goto out;
5058 r = -EFAULT;
f0d66275 5059 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 5060 goto out;
5061 r = 0;
5062 break;
5063 }
5064 case KVM_SET_PIT: {
e0f63cb9 5065 r = -EFAULT;
0e96f31e 5066 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
e0f63cb9
SY		 5067 goto out;
5068 r = -ENXIO;
5069 if (!kvm->arch.vpit)
5070 goto out;
f0d66275 5071 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 5072 break;
5073 }
e9f42757
BK		 5074 case KVM_GET_PIT2: {
5075 r = -ENXIO;
5076 if (!kvm->arch.vpit)
5077 goto out;
5078 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
5079 if (r)
5080 goto out;
5081 r = -EFAULT;
5082 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
5083 goto out;
5084 r = 0;
5085 break;
5086 }
5087 case KVM_SET_PIT2: {
5088 r = -EFAULT;
5089 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
5090 goto out;
5091 r = -ENXIO;
5092 if (!kvm->arch.vpit)
5093 goto out;
5094 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 5095 break;
5096 }
52d939a0
MT		 5097 case KVM_REINJECT_CONTROL: {
5098 struct kvm_reinject_control control;
5099 r = -EFAULT;
5100 if (copy_from_user(&control, argp, sizeof(control)))
5101 goto out;
cad23e72
ML		 5102 r = -ENXIO;
5103 if (!kvm->arch.vpit)
5104 goto out;
52d939a0 5105 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 5106 break;
5107 }
d71ba788
PB		 5108 case KVM_SET_BOOT_CPU_ID:
5109 r = 0;
5110 mutex_lock(&kvm->lock);
557abc40 5111 if (kvm->created_vcpus)
d71ba788
PB		 5112 r = -EBUSY;
5113 else
5114 kvm->arch.bsp_vcpu_id = arg;
5115 mutex_unlock(&kvm->lock);
5116 break;
ffde22ac 5117 case KVM_XEN_HVM_CONFIG: {
51776043 5118 struct kvm_xen_hvm_config xhc;
ffde22ac 5119 r = -EFAULT;
51776043 5120 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES		 5121 goto out;
5122 r = -EINVAL;
51776043 5123 if (xhc.flags)
ffde22ac 5124 goto out;
51776043 5125 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES		 5126 r = 0;
5127 break;
5128 }
afbcf7ab 5129 case KVM_SET_CLOCK: {
afbcf7ab
GC		 5130 struct kvm_clock_data user_ns;
5131 u64 now_ns;
afbcf7ab
GC		 5132
5133 r = -EFAULT;
5134 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
5135 goto out;
5136
5137 r = -EINVAL;
5138 if (user_ns.flags)
5139 goto out;
5140
5141 r = 0;
0bc48bea
RK		 5142 /*
5143 * TODO: userspace has to take care of races with VCPU_RUN, so
5144 * kvm_gen_update_masterclock() can be cut down to locked
5145 * pvclock_update_vm_gtod_copy().
5146 */
5147 kvm_gen_update_masterclock(kvm);
e891a32e 5148 now_ns = get_kvmclock_ns(kvm);
108b249c 5149 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 5150 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC		 5151 break;
5152 }
5153 case KVM_GET_CLOCK: {
afbcf7ab
GC		 5154 struct kvm_clock_data user_ns;
5155 u64 now_ns;
5156
e891a32e 5157 now_ns = get_kvmclock_ns(kvm);
108b249c 5158 user_ns.clock = now_ns;
e3fd9a93 5159 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 5160 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 5161
5162 r = -EFAULT;
5163 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
5164 goto out;
5165 r = 0;
5166 break;
5167 }
5acc5c06
BS		 5168 case KVM_MEMORY_ENCRYPT_OP: {
5169 r = -ENOTTY;
5170 if (kvm_x86_ops->mem_enc_op)
5171 r = kvm_x86_ops->mem_enc_op(kvm, argp);
5172 break;
5173 }
69eaedee
BS		 5174 case KVM_MEMORY_ENCRYPT_REG_REGION: {
5175 struct kvm_enc_region region;
5176
5177 r = -EFAULT;
5178 if (copy_from_user(&region, argp, sizeof(region)))
5179 goto out;
5180
5181 r = -ENOTTY;
5182 if (kvm_x86_ops->mem_enc_reg_region)
5183 r = kvm_x86_ops->mem_enc_reg_region(kvm, &region);
5184 break;
5185 }
5186 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
5187 struct kvm_enc_region region;
5188
5189 r = -EFAULT;
5190 if (copy_from_user(&region, argp, sizeof(region)))
5191 goto out;
5192
5193 r = -ENOTTY;
5194 if (kvm_x86_ops->mem_enc_unreg_region)
5195 r = kvm_x86_ops->mem_enc_unreg_region(kvm, &region);
5196 break;
5197 }
faeb7833
RK		 5198 case KVM_HYPERV_EVENTFD: {
5199 struct kvm_hyperv_eventfd hvevfd;
5200
5201 r = -EFAULT;
5202 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
5203 goto out;
5204 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
5205 break;
5206 }
66bb8a06
EH		 5207 case KVM_SET_PMU_EVENT_FILTER:
5208 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
5209 break;
1fe779f8 5210 default:
ad6260da 5211 r = -ENOTTY;
1fe779f8
CO		 5212 }
5213out:
5214 return r;
5215}
5216
a16b043c 5217static void kvm_init_msr_list(void)
043405e1 5218{
24c29b7a 5219 struct x86_pmu_capability x86_pmu;
043405e1 5220 u32 dummy[2];
7a5ee6ed 5221 unsigned i;
043405e1 5222
e2ada66e 5223 BUILD_BUG_ON_MSG(INTEL_PMC_MAX_FIXED != 4,
7a5ee6ed 5224 "Please update the fixed PMCs in msrs_to_saved_all[]");
24c29b7a
PB		 5225
5226 perf_get_x86_pmu_capability(&x86_pmu);
e2ada66e 5227
6cbee2b9
XL		 5228 num_msrs_to_save = 0;
5229 num_emulated_msrs = 0;
5230 num_msr_based_features = 0;
5231
7a5ee6ed
CQ		 5232 for (i = 0; i < ARRAY_SIZE(msrs_to_save_all); i++) {
5233 if (rdmsr_safe(msrs_to_save_all[i], &dummy[0], &dummy[1]) < 0)
043405e1 5234 continue;
93c4adc7
PB		 5235
5236 /*
5237 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 5238 * to the guests in some cases.
93c4adc7 5239 */
7a5ee6ed 5240 switch (msrs_to_save_all[i]) {
93c4adc7 5241 case MSR_IA32_BNDCFGS:
503234b3 5242 if (!kvm_mpx_supported())
93c4adc7
PB		 5243 continue;
5244 break;
9dbe6cf9
PB		 5245 case MSR_TSC_AUX:
5246 if (!kvm_x86_ops->rdtscp_supported())
5247 continue;
5248 break;
bf8c55d8
CP		 5249 case MSR_IA32_RTIT_CTL:
5250 case MSR_IA32_RTIT_STATUS:
5251 if (!kvm_x86_ops->pt_supported())
5252 continue;
5253 break;
5254 case MSR_IA32_RTIT_CR3_MATCH:
5255 if (!kvm_x86_ops->pt_supported() ||
5256 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
5257 continue;
5258 break;
5259 case MSR_IA32_RTIT_OUTPUT_BASE:
5260 case MSR_IA32_RTIT_OUTPUT_MASK:
5261 if (!kvm_x86_ops->pt_supported() ||
5262 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
5263 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
5264 continue;
5265 break;
5266 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: {
5267 if (!kvm_x86_ops->pt_supported() ||
7a5ee6ed 5268 msrs_to_save_all[i] - MSR_IA32_RTIT_ADDR0_A >=
bf8c55d8
CP		 5269 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)
5270 continue;
5271 break;
cf05a67b 5272 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + 17:
7a5ee6ed 5273 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_PERFCTR0 >=
24c29b7a
PB		 5274 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5275 continue;
5276 break;
cf05a67b 5277 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 17:
7a5ee6ed 5278 if (msrs_to_save_all[i] - MSR_ARCH_PERFMON_EVENTSEL0 >=
24c29b7a
PB		 5279 min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp))
5280 continue;
bf8c55d8 5281 }
93c4adc7
PB		 5282 default:
5283 break;
5284 }
5285
7a5ee6ed 5286 msrs_to_save[num_msrs_to_save++] = msrs_to_save_all[i];
043405e1 5287 }
62ef68bb 5288
7a5ee6ed
CQ		 5289 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
5290 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs_all[i]))
bc226f07 5291 continue;
62ef68bb 5292
7a5ee6ed 5293 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
62ef68bb 5294 }
801e459a 5295
7a5ee6ed 5296 for (i = 0; i < ARRAY_SIZE(msr_based_features_all); i++) {
801e459a
TL		 5297 struct kvm_msr_entry msr;
5298
7a5ee6ed 5299 msr.index = msr_based_features_all[i];
66421c1e 5300 if (kvm_get_msr_feature(&msr))
801e459a
TL		 5301 continue;
5302
7a5ee6ed 5303 msr_based_features[num_msr_based_features++] = msr_based_features_all[i];
801e459a 5304 }
043405e1
CO		 5305}
5306
bda9020e
MT		 5307static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
5308 const void *v)
bbd9b64e 5309{
70252a10
AK		 5310 int handled = 0;
5311 int n;
5312
5313 do {
5314 n = min(len, 8);
bce87cce 5315 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5316 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
5317 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 5318 break;
5319 handled += n;
5320 addr += n;
5321 len -= n;
5322 v += n;
5323 } while (len);
bbd9b64e 5324
70252a10 5325 return handled;
bbd9b64e
CO		 5326}
5327
bda9020e 5328static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 5329{
70252a10
AK		 5330 int handled = 0;
5331 int n;
5332
5333 do {
5334 n = min(len, 8);
bce87cce 5335 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN		 5336 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
5337 addr, n, v))
5338 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 5339 break;
e39d200f 5340 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK		 5341 handled += n;
5342 addr += n;
5343 len -= n;
5344 v += n;
5345 } while (len);
bbd9b64e 5346
70252a10 5347 return handled;
bbd9b64e
CO		 5348}
5349
2dafc6c2
GN		 5350static void kvm_set_segment(struct kvm_vcpu *vcpu,
5351 struct kvm_segment *var, int seg)
5352{
5353 kvm_x86_ops->set_segment(vcpu, var, seg);
5354}
5355
5356void kvm_get_segment(struct kvm_vcpu *vcpu,
5357 struct kvm_segment *var, int seg)
5358{
5359 kvm_x86_ops->get_segment(vcpu, var, seg);
5360}
5361
54987b7a
PB		 5362gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
5363 struct x86_exception *exception)
02f59dc9
JR		 5364{
5365 gpa_t t_gpa;
02f59dc9
JR		 5366
5367 BUG_ON(!mmu_is_nested(vcpu));
5368
5369 /* NPT walks are always user-walks */
5370 access |= PFERR_USER_MASK;
44dd3ffa 5371 t_gpa = vcpu->arch.mmu->gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 5372
5373 return t_gpa;
5374}
5375
ab9ae313
AK		 5376gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
5377 struct x86_exception *exception)
1871c602
GN		 5378{
5379 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 5380 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5381}
5382
ab9ae313
AK		 5383 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
5384 struct x86_exception *exception)
1871c602
GN		 5385{
5386 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5387 access |= PFERR_FETCH_MASK;
ab9ae313 5388 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5389}
5390
ab9ae313
AK		 5391gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
5392 struct x86_exception *exception)
1871c602
GN		 5393{
5394 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
5395 access |= PFERR_WRITE_MASK;
ab9ae313 5396 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 5397}
5398
5399/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 5400gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
5401 struct x86_exception *exception)
1871c602 5402{
ab9ae313 5403 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 5404}
5405
5406static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5407 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 5408 struct x86_exception *exception)
bbd9b64e
CO		 5409{
5410 void *data = val;
10589a46 5411 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 5412
5413 while (bytes) {
14dfe855 5414 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 5415 exception);
bbd9b64e 5416 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 5417 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 5418 int ret;
5419
bcc55cba 5420 if (gpa == UNMAPPED_GVA)
ab9ae313 5421 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 5422 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
5423 offset, toread);
10589a46 5424 if (ret < 0) {
c3cd7ffa 5425 r = X86EMUL_IO_NEEDED;
10589a46
MT		 5426 goto out;
5427 }
bbd9b64e 5428
77c2002e
IE		 5429 bytes -= toread;
5430 data += toread;
5431 addr += toread;
bbd9b64e 5432 }
10589a46 5433out:
10589a46 5434 return r;
bbd9b64e 5435}
77c2002e 5436
1871c602 5437/* used for instruction fetching */
0f65dd70
AK		 5438static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
5439 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5440 struct x86_exception *exception)
1871c602 5441{
0f65dd70 5442 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 5443 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 5444 unsigned offset;
5445 int ret;
0f65dd70 5446
44583cba
PB		 5447 /* Inline kvm_read_guest_virt_helper for speed. */
5448 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
5449 exception);
5450 if (unlikely(gpa == UNMAPPED_GVA))
5451 return X86EMUL_PROPAGATE_FAULT;
5452
5453 offset = addr & (PAGE_SIZE-1);
5454 if (WARN_ON(offset + bytes > PAGE_SIZE))
5455 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 5456 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
5457 offset, bytes);
44583cba
PB		 5458 if (unlikely(ret < 0))
5459 return X86EMUL_IO_NEEDED;
5460
5461 return X86EMUL_CONTINUE;
1871c602
GN		 5462}
5463
ce14e868 5464int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
0f65dd70 5465 gva_t addr, void *val, unsigned int bytes,
bcc55cba 5466 struct x86_exception *exception)
1871c602
GN		 5467{
5468 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 5469
353c0956
PB		 5470 /*
5471 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5472 * is returned, but our callers are not ready for that and they blindly
5473 * call kvm_inject_page_fault. Ensure that they at least do not leak
5474 * uninitialized kernel stack memory into cr2 and error code.
5475 */
5476 memset(exception, 0, sizeof(*exception));
1871c602 5477 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 5478 exception);
1871c602 5479}
064aea77 5480EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 5481
ce14e868
PB		 5482static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
5483 gva_t addr, void *val, unsigned int bytes,
3c9fa24c 5484 struct x86_exception *exception, bool system)
1871c602 5485{
0f65dd70 5486 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5487 u32 access = 0;
5488
5489 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5490 access |= PFERR_USER_MASK;
5491
5492 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
1871c602
GN		 5493}
5494
7a036a6f
RK		 5495static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
5496 unsigned long addr, void *val, unsigned int bytes)
5497{
5498 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5499 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
5500
5501 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
5502}
5503
ce14e868
PB		 5504static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
5505 struct kvm_vcpu *vcpu, u32 access,
5506 struct x86_exception *exception)
77c2002e
IE		 5507{
5508 void *data = val;
5509 int r = X86EMUL_CONTINUE;
5510
5511 while (bytes) {
14dfe855 5512 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
ce14e868 5513 access,
ab9ae313 5514 exception);
77c2002e
IE		 5515 unsigned offset = addr & (PAGE_SIZE-1);
5516 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
5517 int ret;
5518
bcc55cba 5519 if (gpa == UNMAPPED_GVA)
ab9ae313 5520 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 5521 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 5522 if (ret < 0) {
c3cd7ffa 5523 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 5524 goto out;
5525 }
5526
5527 bytes -= towrite;
5528 data += towrite;
5529 addr += towrite;
5530 }
5531out:
5532 return r;
5533}
ce14e868
PB		 5534
5535static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
3c9fa24c
PB		 5536 unsigned int bytes, struct x86_exception *exception,
5537 bool system)
ce14e868
PB		 5538{
5539 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3c9fa24c
PB		 5540 u32 access = PFERR_WRITE_MASK;
5541
5542 if (!system && kvm_x86_ops->get_cpl(vcpu) == 3)
5543 access |= PFERR_USER_MASK;
ce14e868
PB		 5544
5545 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
3c9fa24c 5546 access, exception);
ce14e868
PB		 5547}
5548
5549int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
5550 unsigned int bytes, struct x86_exception *exception)
5551{
c595ceee
PB		 5552 /* kvm_write_guest_virt_system can pull in tons of pages. */
5553 vcpu->arch.l1tf_flush_l1d = true;
5554
541ab2ae
FH		 5555 /*
5556 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
5557 * is returned, but our callers are not ready for that and they blindly
5558 * call kvm_inject_page_fault. Ensure that they at least do not leak
5559 * uninitialized kernel stack memory into cr2 and error code.
5560 */
5561 memset(exception, 0, sizeof(*exception));
ce14e868
PB		 5562 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
5563 PFERR_WRITE_MASK, exception);
5564}
6a4d7550 5565EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 5566
082d06ed
WL		 5567int handle_ud(struct kvm_vcpu *vcpu)
5568{
b3dc0695 5569 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
6c86eedc 5570 int emul_type = EMULTYPE_TRAP_UD;
6c86eedc
WL		 5571 char sig[5]; /* ud2; .ascii "kvm" */
5572 struct x86_exception e;
5573
5574 if (force_emulation_prefix &&
3c9fa24c
PB		 5575 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
5576 sig, sizeof(sig), &e) == 0 &&
b3dc0695 5577 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
6c86eedc 5578 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
b4000606 5579 emul_type = EMULTYPE_TRAP_UD_FORCED;
6c86eedc 5580 }
082d06ed 5581
60fc3d02 5582 return kvm_emulate_instruction(vcpu, emul_type);
082d06ed
WL		 5583}
5584EXPORT_SYMBOL_GPL(handle_ud);
5585
0f89b207
TL		 5586static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5587 gpa_t gpa, bool write)
5588{
5589 /* For APIC access vmexit */
5590 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5591 return 1;
5592
5593 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
5594 trace_vcpu_match_mmio(gva, gpa, write, true);
5595 return 1;
5596 }
5597
5598 return 0;
5599}
5600
af7cc7d1
XG		 5601static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
5602 gpa_t *gpa, struct x86_exception *exception,
5603 bool write)
5604{
97d64b78
AK		 5605 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
5606 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 5607
be94f6b7
HH		 5608 /*
5609 * currently PKRU is only applied to ept enabled guest so
5610 * there is no pkey in EPT page table for L1 guest or EPT
5611 * shadow page table for L2 guest.
5612 */
97d64b78 5613 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 5614 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
871bd034 5615 vcpu->arch.mmio_access, 0, access)) {
bebb106a
XG		 5616 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
5617 (gva & (PAGE_SIZE - 1));
4f022648 5618 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 5619 return 1;
5620 }
5621
af7cc7d1
XG		 5622 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
5623
5624 if (*gpa == UNMAPPED_GVA)
5625 return -1;
5626
0f89b207 5627 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG		 5628}
5629
3200f405 5630int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 5631 const void *val, int bytes)
bbd9b64e
CO		 5632{
5633 int ret;
5634
54bf36aa 5635 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 5636 if (ret < 0)
bbd9b64e 5637 return 0;
0eb05bf2 5638 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 5639 return 1;
5640}
5641
77d197b2
XG		 5642struct read_write_emulator_ops {
5643 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
5644 int bytes);
5645 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
5646 void *val, int bytes);
5647 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5648 int bytes, void *val);
5649 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
5650 void *val, int bytes);
5651 bool write;
5652};
5653
5654static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
5655{
5656 if (vcpu->mmio_read_completed) {
77d197b2 5657 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 5658 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG		 5659 vcpu->mmio_read_completed = 0;
5660 return 1;
5661 }
5662
5663 return 0;
5664}
5665
5666static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5667 void *val, int bytes)
5668{
54bf36aa 5669 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 5670}
5671
5672static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
5673 void *val, int bytes)
5674{
5675 return emulator_write_phys(vcpu, gpa, val, bytes);
5676}
5677
5678static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
5679{
e39d200f 5680 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG		 5681 return vcpu_mmio_write(vcpu, gpa, bytes, val);
5682}
5683
5684static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5685 void *val, int bytes)
5686{
e39d200f 5687 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG		 5688 return X86EMUL_IO_NEEDED;
5689}
5690
5691static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
5692 void *val, int bytes)
5693{
f78146b0
AK		 5694 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
5695
87da7e66 5696 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 5697 return X86EMUL_CONTINUE;
5698}
5699
0fbe9b0b 5700static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 5701 .read_write_prepare = read_prepare,
5702 .read_write_emulate = read_emulate,
5703 .read_write_mmio = vcpu_mmio_read,
5704 .read_write_exit_mmio = read_exit_mmio,
5705};
5706
0fbe9b0b 5707static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 5708 .read_write_emulate = write_emulate,
5709 .read_write_mmio = write_mmio,
5710 .read_write_exit_mmio = write_exit_mmio,
5711 .write = true,
5712};
5713
22388a3c
XG		 5714static int emulator_read_write_onepage(unsigned long addr, void *val,
5715 unsigned int bytes,
5716 struct x86_exception *exception,
5717 struct kvm_vcpu *vcpu,
0fbe9b0b 5718 const struct read_write_emulator_ops *ops)
bbd9b64e 5719{
af7cc7d1
XG		 5720 gpa_t gpa;
5721 int handled, ret;
22388a3c 5722 bool write = ops->write;
f78146b0 5723 struct kvm_mmio_fragment *frag;
0f89b207
TL		 5724 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5725
5726 /*
5727 * If the exit was due to a NPF we may already have a GPA.
5728 * If the GPA is present, use it to avoid the GVA to GPA table walk.
5729 * Note, this cannot be used on string operations since string
5730 * operation using rep will only have the initial GPA from the NPF
5731 * occurred.
5732 */
5733 if (vcpu->arch.gpa_available &&
5734 emulator_can_use_gpa(ctxt) &&
618232e2
BS		 5735 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
5736 gpa = vcpu->arch.gpa_val;
5737 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
5738 } else {
5739 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
5740 if (ret < 0)
5741 return X86EMUL_PROPAGATE_FAULT;
0f89b207 5742 }
10589a46 5743
618232e2 5744 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 5745 return X86EMUL_CONTINUE;
5746
bbd9b64e
CO		 5747 /*
5748 * Is this MMIO handled locally?
5749 */
22388a3c 5750 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 5751 if (handled == bytes)
bbd9b64e 5752 return X86EMUL_CONTINUE;
bbd9b64e 5753
70252a10
AK		 5754 gpa += handled;
5755 bytes -= handled;
5756 val += handled;
5757
87da7e66
XG		 5758 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
5759 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
5760 frag->gpa = gpa;
5761 frag->data = val;
5762 frag->len = bytes;
f78146b0 5763 return X86EMUL_CONTINUE;
bbd9b64e
CO		 5764}
5765
52eb5a6d
XL		 5766static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
5767 unsigned long addr,
22388a3c
XG		 5768 void *val, unsigned int bytes,
5769 struct x86_exception *exception,
0fbe9b0b 5770 const struct read_write_emulator_ops *ops)
bbd9b64e 5771{
0f65dd70 5772 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 5773 gpa_t gpa;
5774 int rc;
5775
5776 if (ops->read_write_prepare &&
5777 ops->read_write_prepare(vcpu, val, bytes))
5778 return X86EMUL_CONTINUE;
5779
5780 vcpu->mmio_nr_fragments = 0;
0f65dd70 5781
bbd9b64e
CO		 5782 /* Crossing a page boundary? */
5783 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 5784 int now;
bbd9b64e
CO		 5785
5786 now = -addr & ~PAGE_MASK;
22388a3c
XG		 5787 rc = emulator_read_write_onepage(addr, val, now, exception,
5788 vcpu, ops);
5789
bbd9b64e
CO		 5790 if (rc != X86EMUL_CONTINUE)
5791 return rc;
5792 addr += now;
bac15531
NA		 5793 if (ctxt->mode != X86EMUL_MODE_PROT64)
5794 addr = (u32)addr;
bbd9b64e
CO		 5795 val += now;
5796 bytes -= now;
5797 }
22388a3c 5798
f78146b0
AK		 5799 rc = emulator_read_write_onepage(addr, val, bytes, exception,
5800 vcpu, ops);
5801 if (rc != X86EMUL_CONTINUE)
5802 return rc;
5803
5804 if (!vcpu->mmio_nr_fragments)
5805 return rc;
5806
5807 gpa = vcpu->mmio_fragments[0].gpa;
5808
5809 vcpu->mmio_needed = 1;
5810 vcpu->mmio_cur_fragment = 0;
5811
87da7e66 5812 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 5813 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
5814 vcpu->run->exit_reason = KVM_EXIT_MMIO;
5815 vcpu->run->mmio.phys_addr = gpa;
5816
5817 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 5818}
5819
5820static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
5821 unsigned long addr,
5822 void *val,
5823 unsigned int bytes,
5824 struct x86_exception *exception)
5825{
5826 return emulator_read_write(ctxt, addr, val, bytes,
5827 exception, &read_emultor);
5828}
5829
52eb5a6d 5830static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 5831 unsigned long addr,
5832 const void *val,
5833 unsigned int bytes,
5834 struct x86_exception *exception)
5835{
5836 return emulator_read_write(ctxt, addr, (void *)val, bytes,
5837 exception, &write_emultor);
bbd9b64e 5838}
bbd9b64e 5839
daea3e73
AK		 5840#define CMPXCHG_TYPE(t, ptr, old, new) \
5841 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
5842
5843#ifdef CONFIG_X86_64
5844# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
5845#else
5846# define CMPXCHG64(ptr, old, new) \
9749a6c0 5847 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 5848#endif
5849
0f65dd70
AK		 5850static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
5851 unsigned long addr,
bbd9b64e
CO		 5852 const void *old,
5853 const void *new,
5854 unsigned int bytes,
0f65dd70 5855 struct x86_exception *exception)
bbd9b64e 5856{
42e35f80 5857 struct kvm_host_map map;
0f65dd70 5858 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73 5859 gpa_t gpa;
daea3e73
AK		 5860 char *kaddr;
5861 bool exchanged;
2bacc55c 5862
daea3e73
AK		 5863 /* guests cmpxchg8b have to be emulated atomically */
5864 if (bytes > 8 || (bytes & (bytes - 1)))
5865 goto emul_write;
10589a46 5866
daea3e73 5867 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 5868
daea3e73
AK		 5869 if (gpa == UNMAPPED_GVA ||
5870 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
5871 goto emul_write;
2bacc55c 5872
daea3e73
AK		 5873 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
5874 goto emul_write;
72dc67a6 5875
42e35f80 5876 if (kvm_vcpu_map(vcpu, gpa_to_gfn(gpa), &map))
c19b8bd6 5877 goto emul_write;
72dc67a6 5878
42e35f80
KA		 5879 kaddr = map.hva + offset_in_page(gpa);
5880
daea3e73
AK		 5881 switch (bytes) {
5882 case 1:
5883 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
5884 break;
5885 case 2:
5886 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
5887 break;
5888 case 4:
5889 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
5890 break;
5891 case 8:
5892 exchanged = CMPXCHG64(kaddr, old, new);
5893 break;
5894 default:
5895 BUG();
2bacc55c 5896 }
42e35f80
KA		 5897
5898 kvm_vcpu_unmap(vcpu, &map, true);
daea3e73
AK		 5899
5900 if (!exchanged)
5901 return X86EMUL_CMPXCHG_FAILED;
5902
0eb05bf2 5903 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 5904
5905 return X86EMUL_CONTINUE;
4a5f48f6 5906
3200f405 5907emul_write:
daea3e73 5908 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 5909
0f65dd70 5910 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 5911}
5912
cf8f70bf
GN		 5913static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
5914{
cbfc6c91 5915 int r = 0, i;
cf8f70bf 5916
cbfc6c91
WL		 5917 for (i = 0; i < vcpu->arch.pio.count; i++) {
5918 if (vcpu->arch.pio.in)
5919 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5920 vcpu->arch.pio.size, pd);
5921 else
5922 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5923 vcpu->arch.pio.port, vcpu->arch.pio.size,
5924 pd);
5925 if (r)
5926 break;
5927 pd += vcpu->arch.pio.size;
5928 }
cf8f70bf
GN		 5929 return r;
5930}
5931
6f6fbe98
XG		 5932static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5933 unsigned short port, void *val,
5934 unsigned int count, bool in)
cf8f70bf 5935{
cf8f70bf 5936 vcpu->arch.pio.port = port;
6f6fbe98 5937 vcpu->arch.pio.in = in;
7972995b 5938 vcpu->arch.pio.count = count;
cf8f70bf
GN		 5939 vcpu->arch.pio.size = size;
5940
5941 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5942 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5943 return 1;
5944 }
5945
5946 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5947 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 5948 vcpu->run->io.size = size;
5949 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5950 vcpu->run->io.count = count;
5951 vcpu->run->io.port = port;
5952
5953 return 0;
5954}
5955
6f6fbe98
XG		 5956static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5957 int size, unsigned short port, void *val,
5958 unsigned int count)
cf8f70bf 5959{
ca1d4a9e 5960 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5961 int ret;
ca1d4a9e 5962
6f6fbe98
XG		 5963 if (vcpu->arch.pio.count)
5964 goto data_avail;
cf8f70bf 5965
cbfc6c91
WL		 5966 memset(vcpu->arch.pio_data, 0, size * count);
5967
6f6fbe98
XG		 5968 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5969 if (ret) {
5970data_avail:
5971 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5972 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5973 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 5974 return 1;
5975 }
5976
cf8f70bf
GN		 5977 return 0;
5978}
5979
6f6fbe98
XG		 5980static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5981 int size, unsigned short port,
5982 const void *val, unsigned int count)
5983{
5984 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5985
5986 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5987 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 5988 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5989}
5990
bbd9b64e
CO		 5991static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5992{
5993 return kvm_x86_ops->get_segment_base(vcpu, seg);
5994}
5995
3cb16fe7 5996static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5997{
3cb16fe7 5998 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 5999}
6000
ae6a2375 6001static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 6002{
6003 if (!need_emulate_wbinvd(vcpu))
6004 return X86EMUL_CONTINUE;
6005
6006 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 6007 int cpu = get_cpu();
6008
6009 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6010 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
6011 wbinvd_ipi, NULL, 1);
2eec7343 6012 put_cpu();
f5f48ee1 6013 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 6014 } else
6015 wbinvd();
f5f48ee1
SY		 6016 return X86EMUL_CONTINUE;
6017}
5cb56059
JS		 6018
6019int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
6020{
6affcbed
KH		 6021 kvm_emulate_wbinvd_noskip(vcpu);
6022 return kvm_skip_emulated_instruction(vcpu);
5cb56059 6023}
f5f48ee1
SY		 6024EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
6025
5cb56059
JS		 6026
6027
bcaf5cc5
AK		 6028static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
6029{
5cb56059 6030 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 6031}
6032
52eb5a6d
XL		 6033static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
6034 unsigned long *dest)
bbd9b64e 6035{
16f8a6f9 6036 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 6037}
6038
52eb5a6d
XL		 6039static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
6040 unsigned long value)
bbd9b64e 6041{
338dbc97 6042
717746e3 6043 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 6044}
6045
52a46617 6046static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 6047{
52a46617 6048 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 6049}
6050
717746e3 6051static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 6052{
717746e3 6053 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 6054 unsigned long value;
6055
6056 switch (cr) {
6057 case 0:
6058 value = kvm_read_cr0(vcpu);
6059 break;
6060 case 2:
6061 value = vcpu->arch.cr2;
6062 break;
6063 case 3:
9f8fe504 6064 value = kvm_read_cr3(vcpu);
52a46617
GN		 6065 break;
6066 case 4:
6067 value = kvm_read_cr4(vcpu);
6068 break;
6069 case 8:
6070 value = kvm_get_cr8(vcpu);
6071 break;
6072 default:
a737f256 6073 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 6074 return 0;
6075 }
6076
6077 return value;
6078}
6079
717746e3 6080static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 6081{
717746e3 6082 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 6083 int res = 0;
6084
52a46617
GN		 6085 switch (cr) {
6086 case 0:
49a9b07e 6087 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 6088 break;
6089 case 2:
6090 vcpu->arch.cr2 = val;
6091 break;
6092 case 3:
2390218b 6093 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 6094 break;
6095 case 4:
a83b29c6 6096 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 6097 break;
6098 case 8:
eea1cff9 6099 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 6100 break;
6101 default:
a737f256 6102 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 6103 res = -1;
52a46617 6104 }
0f12244f
GN		 6105
6106 return res;
52a46617
GN		 6107}
6108
717746e3 6109static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 6110{
717746e3 6111 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 6112}
6113
4bff1e86 6114static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 6115{
4bff1e86 6116 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 6117}
6118
4bff1e86 6119static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 6120{
4bff1e86 6121 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 6122}
6123
1ac9d0cf
AK		 6124static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6125{
6126 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
6127}
6128
6129static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
6130{
6131 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
6132}
6133
4bff1e86
AK		 6134static unsigned long emulator_get_cached_segment_base(
6135 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 6136{
4bff1e86 6137 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 6138}
6139
1aa36616
AK		 6140static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
6141 struct desc_struct *desc, u32 *base3,
6142 int seg)
2dafc6c2
GN		 6143{
6144 struct kvm_segment var;
6145
4bff1e86 6146 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 6147 *selector = var.selector;
2dafc6c2 6148
378a8b09
GN		 6149 if (var.unusable) {
6150 memset(desc, 0, sizeof(*desc));
f0367ee1
RK		 6151 if (base3)
6152 *base3 = 0;
2dafc6c2 6153 return false;
378a8b09 6154 }
2dafc6c2
GN		 6155
6156 if (var.g)
6157 var.limit >>= 12;
6158 set_desc_limit(desc, var.limit);
6159 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 6160#ifdef CONFIG_X86_64
6161 if (base3)
6162 *base3 = var.base >> 32;
6163#endif
2dafc6c2
GN		 6164 desc->type = var.type;
6165 desc->s = var.s;
6166 desc->dpl = var.dpl;
6167 desc->p = var.present;
6168 desc->avl = var.avl;
6169 desc->l = var.l;
6170 desc->d = var.db;
6171 desc->g = var.g;
6172
6173 return true;
6174}
6175
1aa36616
AK		 6176static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
6177 struct desc_struct *desc, u32 base3,
6178 int seg)
2dafc6c2 6179{
4bff1e86 6180 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 6181 struct kvm_segment var;
6182
1aa36616 6183 var.selector = selector;
2dafc6c2 6184 var.base = get_desc_base(desc);
5601d05b
GN		 6185#ifdef CONFIG_X86_64
6186 var.base |= ((u64)base3) << 32;
6187#endif
2dafc6c2
GN		 6188 var.limit = get_desc_limit(desc);
6189 if (desc->g)
6190 var.limit = (var.limit << 12) | 0xfff;
6191 var.type = desc->type;
2dafc6c2
GN		 6192 var.dpl = desc->dpl;
6193 var.db = desc->d;
6194 var.s = desc->s;
6195 var.l = desc->l;
6196 var.g = desc->g;
6197 var.avl = desc->avl;
6198 var.present = desc->p;
6199 var.unusable = !var.present;
6200 var.padding = 0;
6201
6202 kvm_set_segment(vcpu, &var, seg);
6203 return;
6204}
6205
717746e3
AK		 6206static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
6207 u32 msr_index, u64 *pdata)
6208{
f20935d8 6209 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
717746e3
AK		 6210}
6211
6212static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
6213 u32 msr_index, u64 data)
6214{
f20935d8 6215 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
717746e3
AK		 6216}
6217
64d60670
PB		 6218static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
6219{
6220 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6221
6222 return vcpu->arch.smbase;
6223}
6224
6225static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
6226{
6227 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6228
6229 vcpu->arch.smbase = smbase;
6230}
6231
67f4d428
NA		 6232static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
6233 u32 pmc)
6234{
98ff80f5 6235 return kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA		 6236}
6237
222d21aa
AK		 6238static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
6239 u32 pmc, u64 *pdata)
6240{
c6702c9d 6241 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK		 6242}
6243
6c3287f7
AK		 6244static void emulator_halt(struct x86_emulate_ctxt *ctxt)
6245{
6246 emul_to_vcpu(ctxt)->arch.halt_request = 1;
6247}
6248
2953538e 6249static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 6250 struct x86_instruction_info *info,
c4f035c6
AK		 6251 enum x86_intercept_stage stage)
6252{
2953538e 6253 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 6254}
6255
e911eb3b
YZ		 6256static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
6257 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 6258{
e911eb3b 6259 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB		 6260}
6261
5ae78e95
SC		 6262static bool emulator_guest_has_long_mode(struct x86_emulate_ctxt *ctxt)
6263{
6264 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_LM);
6265}
6266
6267static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
6268{
6269 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
6270}
6271
6272static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
6273{
6274 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
6275}
6276
dd856efa
AK		 6277static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
6278{
6279 return kvm_register_read(emul_to_vcpu(ctxt), reg);
6280}
6281
6282static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
6283{
6284 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
6285}
6286
801806d9
NA		 6287static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
6288{
6289 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
6290}
6291
6ed071f0
LP		 6292static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
6293{
6294 return emul_to_vcpu(ctxt)->arch.hflags;
6295}
6296
6297static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
6298{
c5833c7a 6299 emul_to_vcpu(ctxt)->arch.hflags = emul_flags;
6ed071f0
LP		 6300}
6301
ed19321f
SC		 6302static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt,
6303 const char *smstate)
0234bf88 6304{
ed19321f 6305 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smstate);
0234bf88
LP		 6306}
6307
c5833c7a
SC		 6308static void emulator_post_leave_smm(struct x86_emulate_ctxt *ctxt)
6309{
6310 kvm_smm_changed(emul_to_vcpu(ctxt));
6311}
6312
02d4160f
VK		 6313static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
6314{
6315 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
6316}
6317
0225fb50 6318static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 6319 .read_gpr = emulator_read_gpr,
6320 .write_gpr = emulator_write_gpr,
ce14e868
PB		 6321 .read_std = emulator_read_std,
6322 .write_std = emulator_write_std,
7a036a6f 6323 .read_phys = kvm_read_guest_phys_system,
1871c602 6324 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 6325 .read_emulated = emulator_read_emulated,
6326 .write_emulated = emulator_write_emulated,
6327 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 6328 .invlpg = emulator_invlpg,
cf8f70bf
GN		 6329 .pio_in_emulated = emulator_pio_in_emulated,
6330 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 6331 .get_segment = emulator_get_segment,
6332 .set_segment = emulator_set_segment,
5951c442 6333 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 6334 .get_gdt = emulator_get_gdt,
160ce1f1 6335 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 6336 .set_gdt = emulator_set_gdt,
6337 .set_idt = emulator_set_idt,
52a46617
GN		 6338 .get_cr = emulator_get_cr,
6339 .set_cr = emulator_set_cr,
9c537244 6340 .cpl = emulator_get_cpl,
35aa5375
GN		 6341 .get_dr = emulator_get_dr,
6342 .set_dr = emulator_set_dr,
64d60670
PB		 6343 .get_smbase = emulator_get_smbase,
6344 .set_smbase = emulator_set_smbase,
717746e3
AK		 6345 .set_msr = emulator_set_msr,
6346 .get_msr = emulator_get_msr,
67f4d428 6347 .check_pmc = emulator_check_pmc,
222d21aa 6348 .read_pmc = emulator_read_pmc,
6c3287f7 6349 .halt = emulator_halt,
bcaf5cc5 6350 .wbinvd = emulator_wbinvd,
d6aa1000 6351 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 6352 .intercept = emulator_intercept,
bdb42f5a 6353 .get_cpuid = emulator_get_cpuid,
5ae78e95
SC		 6354 .guest_has_long_mode = emulator_guest_has_long_mode,
6355 .guest_has_movbe = emulator_guest_has_movbe,
6356 .guest_has_fxsr = emulator_guest_has_fxsr,
801806d9 6357 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP		 6358 .get_hflags = emulator_get_hflags,
6359 .set_hflags = emulator_set_hflags,
0234bf88 6360 .pre_leave_smm = emulator_pre_leave_smm,
c5833c7a 6361 .post_leave_smm = emulator_post_leave_smm,
02d4160f 6362 .set_xcr = emulator_set_xcr,
bbd9b64e
CO		 6363};
6364
95cb2295
GN		 6365static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
6366{
37ccdcbe 6367 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 6368 /*
6369 * an sti; sti; sequence only disable interrupts for the first
6370 * instruction. So, if the last instruction, be it emulated or
6371 * not, left the system with the INT_STI flag enabled, it
6372 * means that the last instruction is an sti. We should not
6373 * leave the flag on in this case. The same goes for mov ss
6374 */
37ccdcbe
PB		 6375 if (int_shadow & mask)
6376 mask = 0;
6addfc42 6377 if (unlikely(int_shadow || mask)) {
95cb2295 6378 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 6379 if (!mask)
6380 kvm_make_request(KVM_REQ_EVENT, vcpu);
6381 }
95cb2295
GN		 6382}
6383
ef54bcfe 6384static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 6385{
6386 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 6387 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 6388 return kvm_propagate_fault(vcpu, &ctxt->exception);
6389
6390 if (ctxt->exception.error_code_valid)
da9cb575
AK		 6391 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
6392 ctxt->exception.error_code);
54b8486f 6393 else
da9cb575 6394 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 6395 return false;
54b8486f
GN		 6396}
6397
8ec4722d
MG		 6398static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
6399{
adf52235 6400 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 6401 int cs_db, cs_l;
6402
8ec4722d
MG		 6403 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
6404
adf52235 6405 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB		 6406 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
6407
adf52235
TY		 6408 ctxt->eip = kvm_rip_read(vcpu);
6409 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
6410 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 6411 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 6412 cs_db ? X86EMUL_MODE_PROT32 :
6413 X86EMUL_MODE_PROT16;
a584539b 6414 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 6415 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
6416 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 6417
dd856efa 6418 init_decode_cache(ctxt);
7ae441ea 6419 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 6420}
6421
9497e1f2 6422void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 6423{
9d74191a 6424 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 6425 int ret;
6426
6427 init_emulate_ctxt(vcpu);
6428
9dac77fa
AK		 6429 ctxt->op_bytes = 2;
6430 ctxt->ad_bytes = 2;
6431 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 6432 ret = emulate_int_real(ctxt, irq);
63995653 6433
9497e1f2
SC		 6434 if (ret != X86EMUL_CONTINUE) {
6435 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6436 } else {
6437 ctxt->eip = ctxt->_eip;
6438 kvm_rip_write(vcpu, ctxt->eip);
6439 kvm_set_rflags(vcpu, ctxt->eflags);
6440 }
63995653
MG		 6441}
6442EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
6443
e2366171 6444static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
6d77dbfc 6445{
6d77dbfc
GN		 6446 ++vcpu->stat.insn_emulation_fail;
6447 trace_kvm_emulate_insn_failed(vcpu);
e2366171 6448
42cbf068
SC		 6449 if (emulation_type & EMULTYPE_VMWARE_GP) {
6450 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
60fc3d02 6451 return 1;
42cbf068 6452 }
e2366171 6453
738fece4
SC		 6454 if (emulation_type & EMULTYPE_SKIP) {
6455 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6456 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6457 vcpu->run->internal.ndata = 0;
60fc3d02 6458 return 0;
738fece4
SC		 6459 }
6460
22da61c9
SC		 6461 kvm_queue_exception(vcpu, UD_VECTOR);
6462
a2b9e6c1 6463 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 6464 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6465 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6466 vcpu->run->internal.ndata = 0;
60fc3d02 6467 return 0;
fc3a9157 6468 }
e2366171 6469
60fc3d02 6470 return 1;
6d77dbfc
GN		 6471}
6472
736c291c 6473static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
991eebf9
GN		 6474 bool write_fault_to_shadow_pgtable,
6475 int emulation_type)
a6f177ef 6476{
736c291c 6477 gpa_t gpa = cr2_or_gpa;
ba049e93 6478 kvm_pfn_t pfn;
a6f177ef 6479
384bf221 6480 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
991eebf9
GN		 6481 return false;
6482
6c3dfeb6
SC		 6483 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6484 return false;
6485
44dd3ffa 6486 if (!vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6487 /*
6488 * Write permission should be allowed since only
6489 * write access need to be emulated.
6490 */
736c291c 6491 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
a6f177ef 6492
95b3cf69
XG		 6493 /*
6494 * If the mapping is invalid in guest, let cpu retry
6495 * it to generate fault.
6496 */
6497 if (gpa == UNMAPPED_GVA)
6498 return true;
6499 }
a6f177ef 6500
8e3d9d06
XG		 6501 /*
6502 * Do not retry the unhandleable instruction if it faults on the
6503 * readonly host memory, otherwise it will goto a infinite loop:
6504 * retry instruction -> write #PF -> emulation fail -> retry
6505 * instruction -> ...
6506 */
6507 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 6508
6509 /*
6510 * If the instruction failed on the error pfn, it can not be fixed,
6511 * report the error to userspace.
6512 */
6513 if (is_error_noslot_pfn(pfn))
6514 return false;
6515
6516 kvm_release_pfn_clean(pfn);
6517
6518 /* The instructions are well-emulated on direct mmu. */
44dd3ffa 6519 if (vcpu->arch.mmu->direct_map) {
95b3cf69
XG		 6520 unsigned int indirect_shadow_pages;
6521
6522 spin_lock(&vcpu->kvm->mmu_lock);
6523 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
6524 spin_unlock(&vcpu->kvm->mmu_lock);
6525
6526 if (indirect_shadow_pages)
6527 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
6528
a6f177ef 6529 return true;
8e3d9d06 6530 }
a6f177ef 6531
95b3cf69
XG		 6532 /*
6533 * if emulation was due to access to shadowed page table
6534 * and it failed try to unshadow page and re-enter the
6535 * guest to let CPU execute the instruction.
6536 */
6537 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 6538
6539 /*
6540 * If the access faults on its page table, it can not
6541 * be fixed by unprotecting shadow page and it should
6542 * be reported to userspace.
6543 */
6544 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 6545}
6546
1cb3f3ae 6547static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
736c291c 6548 gpa_t cr2_or_gpa, int emulation_type)
1cb3f3ae
XG		 6549{
6550 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
736c291c 6551 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
1cb3f3ae
XG		 6552
6553 last_retry_eip = vcpu->arch.last_retry_eip;
6554 last_retry_addr = vcpu->arch.last_retry_addr;
6555
6556 /*
6557 * If the emulation is caused by #PF and it is non-page_table
6558 * writing instruction, it means the VM-EXIT is caused by shadow
6559 * page protected, we can zap the shadow page and retry this
6560 * instruction directly.
6561 *
6562 * Note: if the guest uses a non-page-table modifying instruction
6563 * on the PDE that points to the instruction, then we will unmap
6564 * the instruction and go to an infinite loop. So, we cache the
6565 * last retried eip and the last fault address, if we meet the eip
6566 * and the address again, we can break out of the potential infinite
6567 * loop.
6568 */
6569 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
6570
384bf221 6571 if (!(emulation_type & EMULTYPE_ALLOW_RETRY))
1cb3f3ae
XG		 6572 return false;
6573
6c3dfeb6
SC		 6574 if (WARN_ON_ONCE(is_guest_mode(vcpu)))
6575 return false;
6576
1cb3f3ae
XG		 6577 if (x86_page_table_writing_insn(ctxt))
6578 return false;
6579
736c291c 6580 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
1cb3f3ae
XG		 6581 return false;
6582
6583 vcpu->arch.last_retry_eip = ctxt->eip;
736c291c 6584 vcpu->arch.last_retry_addr = cr2_or_gpa;
1cb3f3ae 6585
44dd3ffa 6586 if (!vcpu->arch.mmu->direct_map)
736c291c 6587 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
1cb3f3ae 6588
22368028 6589 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 6590
6591 return true;
6592}
6593
716d51ab
GN		 6594static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
6595static int complete_emulated_pio(struct kvm_vcpu *vcpu);
6596
64d60670 6597static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 6598{
64d60670 6599 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 6600 /* This is a good place to trace that we are exiting SMM. */
6601 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
6602
c43203ca
PB		 6603 /* Process a latched INIT or SMI, if any. */
6604 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 6605 }
699023e2
PB		 6606
6607 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6608}
6609
4a1e10d5
PB		 6610static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
6611 unsigned long *db)
6612{
6613 u32 dr6 = 0;
6614 int i;
6615 u32 enable, rwlen;
6616
6617 enable = dr7;
6618 rwlen = dr7 >> 16;
6619 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
6620 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
6621 dr6 |= (1 << i);
6622 return dr6;
6623}
6624
120c2c4f 6625static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
663f4c61
PB		 6626{
6627 struct kvm_run *kvm_run = vcpu->run;
6628
c8401dda
PB		 6629 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6630 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
6631 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
6632 kvm_run->debug.arch.exception = DB_VECTOR;
6633 kvm_run->exit_reason = KVM_EXIT_DEBUG;
60fc3d02 6634 return 0;
663f4c61 6635 }
120c2c4f 6636 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
60fc3d02 6637 return 1;
663f4c61
PB		 6638}
6639
6affcbed
KH		 6640int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
6641{
6642 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
f8ea7c60 6643 int r;
6affcbed 6644
f8ea7c60 6645 r = kvm_x86_ops->skip_emulated_instruction(vcpu);
60fc3d02 6646 if (unlikely(!r))
f8ea7c60 6647 return 0;
c8401dda
PB		 6648
6649 /*
6650 * rflags is the old, "raw" value of the flags. The new value has
6651 * not been saved yet.
6652 *
6653 * This is correct even for TF set by the guest, because "the
6654 * processor will not generate this exception after the instruction
6655 * that sets the TF flag".
6656 */
6657 if (unlikely(rflags & X86_EFLAGS_TF))
120c2c4f 6658 r = kvm_vcpu_do_singlestep(vcpu);
60fc3d02 6659 return r;
6affcbed
KH		 6660}
6661EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
6662
4a1e10d5
PB		 6663static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
6664{
4a1e10d5
PB		 6665 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
6666 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 6667 struct kvm_run *kvm_run = vcpu->run;
6668 unsigned long eip = kvm_get_linear_rip(vcpu);
6669 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6670 vcpu->arch.guest_debug_dr7,
6671 vcpu->arch.eff_db);
6672
6673 if (dr6 != 0) {
6f43ed01 6674 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 6675 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 6676 kvm_run->debug.arch.exception = DB_VECTOR;
6677 kvm_run->exit_reason = KVM_EXIT_DEBUG;
60fc3d02 6678 *r = 0;
4a1e10d5
PB		 6679 return true;
6680 }
6681 }
6682
4161a569
NA		 6683 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
6684 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 6685 unsigned long eip = kvm_get_linear_rip(vcpu);
6686 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 6687 vcpu->arch.dr7,
6688 vcpu->arch.db);
6689
6690 if (dr6 != 0) {
1fc5d194 6691 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
6f43ed01 6692 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5 6693 kvm_queue_exception(vcpu, DB_VECTOR);
60fc3d02 6694 *r = 1;
4a1e10d5
PB		 6695 return true;
6696 }
6697 }
6698
6699 return false;
6700}
6701
04789b66
LA		 6702static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
6703{
2d7921c4
AM		 6704 switch (ctxt->opcode_len) {
6705 case 1:
6706 switch (ctxt->b) {
6707 case 0xe4: /* IN */
6708 case 0xe5:
6709 case 0xec:
6710 case 0xed:
6711 case 0xe6: /* OUT */
6712 case 0xe7:
6713 case 0xee:
6714 case 0xef:
6715 case 0x6c: /* INS */
6716 case 0x6d:
6717 case 0x6e: /* OUTS */
6718 case 0x6f:
6719 return true;
6720 }
6721 break;
6722 case 2:
6723 switch (ctxt->b) {
6724 case 0x33: /* RDPMC */
6725 return true;
6726 }
6727 break;
04789b66
LA		 6728 }
6729
6730 return false;
6731}
6732
736c291c
SC		 6733int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
6734 int emulation_type, void *insn, int insn_len)
bbd9b64e 6735{
95cb2295 6736 int r;
9d74191a 6737 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 6738 bool writeback = true;
93c05d3e 6739 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 6740
c595ceee
PB		 6741 vcpu->arch.l1tf_flush_l1d = true;
6742
93c05d3e
XG		 6743 /*
6744 * Clear write_fault_to_shadow_pgtable here to ensure it is
6745 * never reused.
6746 */
6747 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 6748 kvm_clear_exception_queue(vcpu);
8d7d8102 6749
571008da 6750 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 6751 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 6752
6753 /*
6754 * We will reenter on the same instruction since
6755 * we do not set complete_userspace_io. This does not
6756 * handle watchpoints yet, those would be handled in
6757 * the emulate_ops.
6758 */
d391f120
VK		 6759 if (!(emulation_type & EMULTYPE_SKIP) &&
6760 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB		 6761 return r;
6762
9d74191a
TY		 6763 ctxt->interruptibility = 0;
6764 ctxt->have_exception = false;
e0ad0b47 6765 ctxt->exception.vector = -1;
9d74191a 6766 ctxt->perm_ok = false;
bbd9b64e 6767
b51e974f 6768 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 6769
9d74191a 6770 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 6771
e46479f8 6772 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 6773 ++vcpu->stat.insn_emulation;
1d2887e2 6774 if (r != EMULATION_OK) {
b4000606 6775 if ((emulation_type & EMULTYPE_TRAP_UD) ||
c83fad65
SC		 6776 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
6777 kvm_queue_exception(vcpu, UD_VECTOR);
60fc3d02 6778 return 1;
c83fad65 6779 }
736c291c
SC		 6780 if (reexecute_instruction(vcpu, cr2_or_gpa,
6781 write_fault_to_spt,
6782 emulation_type))
60fc3d02 6783 return 1;
8530a79c 6784 if (ctxt->have_exception) {
c8848cee
JD		 6785 /*
6786 * #UD should result in just EMULATION_FAILED, and trap-like
6787 * exception should not be encountered during decode.
6788 */
6789 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
6790 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8530a79c 6791 inject_emulated_exception(vcpu);
60fc3d02 6792 return 1;
8530a79c 6793 }
e2366171 6794 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6795 }
6796 }
6797
42cbf068
SC		 6798 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
6799 !is_vmware_backdoor_opcode(ctxt)) {
6800 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
60fc3d02 6801 return 1;
42cbf068 6802 }
04789b66 6803
1957aa63
SC		 6804 /*
6805 * Note, EMULTYPE_SKIP is intended for use *only* by vendor callbacks
6806 * for kvm_skip_emulated_instruction(). The caller is responsible for
6807 * updating interruptibility state and injecting single-step #DBs.
6808 */
ba8afb6b 6809 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 6810 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 6811 if (ctxt->eflags & X86_EFLAGS_RF)
6812 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
60fc3d02 6813 return 1;
ba8afb6b
GN		 6814 }
6815
736c291c 6816 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
60fc3d02 6817 return 1;
1cb3f3ae 6818
7ae441ea 6819 /* this is needed for vmware backdoor interface to work since it
4d2179e1 6820 changes registers values during IO operation */
7ae441ea
GN		 6821 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
6822 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 6823 emulator_invalidate_register_cache(ctxt);
7ae441ea 6824 }
4d2179e1 6825
5cd21917 6826restart:
0f89b207 6827 /* Save the faulting GPA (cr2) in the address field */
736c291c 6828 ctxt->exception.address = cr2_or_gpa;
0f89b207 6829
9d74191a 6830 r = x86_emulate_insn(ctxt);
bbd9b64e 6831
775fde86 6832 if (r == EMULATION_INTERCEPTED)
60fc3d02 6833 return 1;
775fde86 6834
d2ddd1c4 6835 if (r == EMULATION_FAILED) {
736c291c 6836 if (reexecute_instruction(vcpu, cr2_or_gpa, write_fault_to_spt,
991eebf9 6837 emulation_type))
60fc3d02 6838 return 1;
c3cd7ffa 6839
e2366171 6840 return handle_emulation_failure(vcpu, emulation_type);
bbd9b64e
CO		 6841 }
6842
9d74191a 6843 if (ctxt->have_exception) {
60fc3d02 6844 r = 1;
ef54bcfe
PB		 6845 if (inject_emulated_exception(vcpu))
6846 return r;
d2ddd1c4 6847 } else if (vcpu->arch.pio.count) {
0912c977
PB		 6848 if (!vcpu->arch.pio.in) {
6849 /* FIXME: return into emulator if single-stepping. */
3457e419 6850 vcpu->arch.pio.count = 0;
0912c977 6851 } else {
7ae441ea 6852 writeback = false;
716d51ab
GN		 6853 vcpu->arch.complete_userspace_io = complete_emulated_pio;
6854 }
60fc3d02 6855 r = 0;
7ae441ea 6856 } else if (vcpu->mmio_needed) {
bc8a0aaf
SC		 6857 ++vcpu->stat.mmio_exits;
6858
7ae441ea
GN		 6859 if (!vcpu->mmio_is_write)
6860 writeback = false;
60fc3d02 6861 r = 0;
716d51ab 6862 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 6863 } else if (r == EMULATION_RESTART)
5cd21917 6864 goto restart;
d2ddd1c4 6865 else
60fc3d02 6866 r = 1;
f850e2e6 6867
7ae441ea 6868 if (writeback) {
6addfc42 6869 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 6870 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 6871 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
38827dbd 6872 if (!ctxt->have_exception ||
75ee23b3
SC		 6873 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
6874 kvm_rip_write(vcpu, ctxt->eip);
60fc3d02 6875 if (r && ctxt->tf)
120c2c4f 6876 r = kvm_vcpu_do_singlestep(vcpu);
38827dbd 6877 __kvm_set_rflags(vcpu, ctxt->eflags);
75ee23b3 6878 }
6addfc42
PB		 6879
6880 /*
6881 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
6882 * do nothing, and it will be requested again as soon as
6883 * the shadow expires. But we still need to check here,
6884 * because POPF has no interrupt shadow.
6885 */
6886 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
6887 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 6888 } else
6889 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 6890
6891 return r;
de7d789a 6892}
c60658d1
SC		 6893
6894int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
6895{
6896 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
6897}
6898EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
6899
6900int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
6901 void *insn, int insn_len)
6902{
6903 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
6904}
6905EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
de7d789a 6906
8764ed55
SC		 6907static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
6908{
6909 vcpu->arch.pio.count = 0;
6910 return 1;
6911}
6912
45def77e
SC		 6913static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
6914{
6915 vcpu->arch.pio.count = 0;
6916
6917 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
6918 return 1;
6919
6920 return kvm_skip_emulated_instruction(vcpu);
6921}
6922
dca7f128
SC		 6923static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
6924 unsigned short port)
de7d789a 6925{
de3cd117 6926 unsigned long val = kvm_rax_read(vcpu);
ca1d4a9e
AK		 6927 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
6928 size, port, &val, 1);
8764ed55
SC		 6929 if (ret)
6930 return ret;
45def77e 6931
8764ed55
SC		 6932 /*
6933 * Workaround userspace that relies on old KVM behavior of %rip being
6934 * incremented prior to exiting to userspace to handle "OUT 0x7e".
6935 */
6936 if (port == 0x7e &&
6937 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
6938 vcpu->arch.complete_userspace_io =
6939 complete_fast_pio_out_port_0x7e;
6940 kvm_skip_emulated_instruction(vcpu);
6941 } else {
45def77e
SC		 6942 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
6943 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
6944 }
8764ed55 6945 return 0;
de7d789a 6946}
de7d789a 6947
8370c3d0
TL		 6948static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
6949{
6950 unsigned long val;
6951
6952 /* We should only ever be called with arch.pio.count equal to 1 */
6953 BUG_ON(vcpu->arch.pio.count != 1);
6954
45def77e
SC		 6955 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
6956 vcpu->arch.pio.count = 0;
6957 return 1;
6958 }
6959
8370c3d0 6960 /* For size less than 4 we merge, else we zero extend */
de3cd117 6961 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6962
6963 /*
6964 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
6965 * the copy and tracing
6966 */
6967 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
6968 vcpu->arch.pio.port, &val, 1);
de3cd117 6969 kvm_rax_write(vcpu, val);
8370c3d0 6970
45def77e 6971 return kvm_skip_emulated_instruction(vcpu);
8370c3d0
TL		 6972}
6973
dca7f128
SC		 6974static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
6975 unsigned short port)
8370c3d0
TL		 6976{
6977 unsigned long val;
6978 int ret;
6979
6980 /* For size less than 4 we merge, else we zero extend */
de3cd117 6981 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
8370c3d0
TL		 6982
6983 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
6984 &val, 1);
6985 if (ret) {
de3cd117 6986 kvm_rax_write(vcpu, val);
8370c3d0
TL		 6987 return ret;
6988 }
6989
45def77e 6990 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
8370c3d0
TL		 6991 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
6992
6993 return 0;
6994}
dca7f128
SC		 6995
6996int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
6997{
45def77e 6998 int ret;
dca7f128 6999
dca7f128 7000 if (in)
45def77e 7001 ret = kvm_fast_pio_in(vcpu, size, port);
dca7f128 7002 else
45def77e
SC		 7003 ret = kvm_fast_pio_out(vcpu, size, port);
7004 return ret && kvm_skip_emulated_instruction(vcpu);
dca7f128
SC		 7005}
7006EXPORT_SYMBOL_GPL(kvm_fast_pio);
8370c3d0 7007
251a5fd6 7008static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 7009{
0a3aee0d 7010 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 7011 return 0;
8cfdc000
ZA		 7012}
7013
7014static void tsc_khz_changed(void *data)
c8076604 7015{
8cfdc000
ZA		 7016 struct cpufreq_freqs *freq = data;
7017 unsigned long khz = 0;
7018
7019 if (data)
7020 khz = freq->new;
7021 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7022 khz = cpufreq_quick_get(raw_smp_processor_id());
7023 if (!khz)
7024 khz = tsc_khz;
0a3aee0d 7025 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 7026}
7027
5fa4ec9c 7028#ifdef CONFIG_X86_64
0092e434
VK		 7029static void kvm_hyperv_tsc_notifier(void)
7030{
0092e434
VK		 7031 struct kvm *kvm;
7032 struct kvm_vcpu *vcpu;
7033 int cpu;
7034
0d9ce162 7035 mutex_lock(&kvm_lock);
0092e434
VK		 7036 list_for_each_entry(kvm, &vm_list, vm_list)
7037 kvm_make_mclock_inprogress_request(kvm);
7038
7039 hyperv_stop_tsc_emulation();
7040
7041 /* TSC frequency always matches when on Hyper-V */
7042 for_each_present_cpu(cpu)
7043 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
7044 kvm_max_guest_tsc_khz = tsc_khz;
7045
7046 list_for_each_entry(kvm, &vm_list, vm_list) {
7047 struct kvm_arch *ka = &kvm->arch;
7048
7049 spin_lock(&ka->pvclock_gtod_sync_lock);
7050
7051 pvclock_update_vm_gtod_copy(kvm);
7052
7053 kvm_for_each_vcpu(cpu, vcpu, kvm)
7054 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
7055
7056 kvm_for_each_vcpu(cpu, vcpu, kvm)
7057 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
7058
7059 spin_unlock(&ka->pvclock_gtod_sync_lock);
7060 }
0d9ce162 7061 mutex_unlock(&kvm_lock);
0092e434 7062}
5fa4ec9c 7063#endif
0092e434 7064
df24014a 7065static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
c8076604 7066{
c8076604
GH		 7067 struct kvm *kvm;
7068 struct kvm_vcpu *vcpu;
7069 int i, send_ipi = 0;
7070
8cfdc000
ZA		 7071 /*
7072 * We allow guests to temporarily run on slowing clocks,
7073 * provided we notify them after, or to run on accelerating
7074 * clocks, provided we notify them before. Thus time never
7075 * goes backwards.
7076 *
7077 * However, we have a problem. We can't atomically update
7078 * the frequency of a given CPU from this function; it is
7079 * merely a notifier, which can be called from any CPU.
7080 * Changing the TSC frequency at arbitrary points in time
7081 * requires a recomputation of local variables related to
7082 * the TSC for each VCPU. We must flag these local variables
7083 * to be updated and be sure the update takes place with the
7084 * new frequency before any guests proceed.
7085 *
7086 * Unfortunately, the combination of hotplug CPU and frequency
7087 * change creates an intractable locking scenario; the order
7088 * of when these callouts happen is undefined with respect to
7089 * CPU hotplug, and they can race with each other. As such,
7090 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
7091 * undefined; you can actually have a CPU frequency change take
7092 * place in between the computation of X and the setting of the
7093 * variable. To protect against this problem, all updates of
7094 * the per_cpu tsc_khz variable are done in an interrupt
7095 * protected IPI, and all callers wishing to update the value
7096 * must wait for a synchronous IPI to complete (which is trivial
7097 * if the caller is on the CPU already). This establishes the
7098 * necessary total order on variable updates.
7099 *
7100 * Note that because a guest time update may take place
7101 * anytime after the setting of the VCPU's request bit, the
7102 * correct TSC value must be set before the request. However,
7103 * to ensure the update actually makes it to any guest which
7104 * starts running in hardware virtualization between the set
7105 * and the acquisition of the spinlock, we must also ping the
7106 * CPU after setting the request bit.
7107 *
7108 */
7109
df24014a 7110 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 7111
0d9ce162 7112 mutex_lock(&kvm_lock);
c8076604 7113 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 7114 kvm_for_each_vcpu(i, vcpu, kvm) {
df24014a 7115 if (vcpu->cpu != cpu)
c8076604 7116 continue;
c285545f 7117 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0d9ce162 7118 if (vcpu->cpu != raw_smp_processor_id())
8cfdc000 7119 send_ipi = 1;
c8076604
GH		 7120 }
7121 }
0d9ce162 7122 mutex_unlock(&kvm_lock);
c8076604
GH		 7123
7124 if (freq->old < freq->new && send_ipi) {
7125 /*
7126 * We upscale the frequency. Must make the guest
7127 * doesn't see old kvmclock values while running with
7128 * the new frequency, otherwise we risk the guest sees
7129 * time go backwards.
7130 *
7131 * In case we update the frequency for another cpu
7132 * (which might be in guest context) send an interrupt
7133 * to kick the cpu out of guest context. Next time
7134 * guest context is entered kvmclock will be updated,
7135 * so the guest will not see stale values.
7136 */
df24014a 7137 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
c8076604 7138 }
df24014a
VK		 7139}
7140
7141static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
7142 void *data)
7143{
7144 struct cpufreq_freqs *freq = data;
7145 int cpu;
7146
7147 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
7148 return 0;
7149 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
7150 return 0;
7151
7152 for_each_cpu(cpu, freq->policy->cpus)
7153 __kvmclock_cpufreq_notifier(freq, cpu);
7154
c8076604
GH		 7155 return 0;
7156}
7157
7158static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 7159 .notifier_call = kvmclock_cpufreq_notifier
7160};
7161
251a5fd6 7162static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 7163{
251a5fd6
SAS		 7164 tsc_khz_changed(NULL);
7165 return 0;
8cfdc000
ZA		 7166}
7167
b820cc0c
ZA		 7168static void kvm_timer_init(void)
7169{
c285545f 7170 max_tsc_khz = tsc_khz;
460dd42e 7171
b820cc0c 7172 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 7173#ifdef CONFIG_CPU_FREQ
7174 struct cpufreq_policy policy;
758f588d
BP		 7175 int cpu;
7176
c285545f 7177 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 7178 cpu = get_cpu();
7179 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 7180 if (policy.cpuinfo.max_freq)
7181 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 7182 put_cpu();
c285545f 7183#endif
b820cc0c
ZA		 7184 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
7185 CPUFREQ_TRANSITION_NOTIFIER);
7186 }
460dd42e 7187
73c1b41e 7188 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 7189 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA		 7190}
7191
dd60d217
AK		 7192DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
7193EXPORT_PER_CPU_SYMBOL_GPL(current_vcpu);
ff9d07a0 7194
f5132b01 7195int kvm_is_in_guest(void)
ff9d07a0 7196{
086c9855 7197 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 7198}
7199
7200static int kvm_is_user_mode(void)
7201{
7202 int user_mode = 3;
dcf46b94 7203
086c9855
AS		 7204 if (__this_cpu_read(current_vcpu))
7205 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 7206
ff9d07a0
ZY		 7207 return user_mode != 0;
7208}
7209
7210static unsigned long kvm_get_guest_ip(void)
7211{
7212 unsigned long ip = 0;
dcf46b94 7213
086c9855
AS		 7214 if (__this_cpu_read(current_vcpu))
7215 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 7216
ff9d07a0
ZY		 7217 return ip;
7218}
7219
8479e04e
LK		 7220static void kvm_handle_intel_pt_intr(void)
7221{
7222 struct kvm_vcpu *vcpu = __this_cpu_read(current_vcpu);
7223
7224 kvm_make_request(KVM_REQ_PMI, vcpu);
7225 __set_bit(MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT,
7226 (unsigned long *)&vcpu->arch.pmu.global_status);
7227}
7228
ff9d07a0
ZY		 7229static struct perf_guest_info_callbacks kvm_guest_cbs = {
7230 .is_in_guest = kvm_is_in_guest,
7231 .is_user_mode = kvm_is_user_mode,
7232 .get_guest_ip = kvm_get_guest_ip,
8479e04e 7233 .handle_intel_pt_intr = kvm_handle_intel_pt_intr,
ff9d07a0
ZY		 7234};
7235
16e8d74d
MT		 7236#ifdef CONFIG_X86_64
7237static void pvclock_gtod_update_fn(struct work_struct *work)
7238{
d828199e
MT		 7239 struct kvm *kvm;
7240
7241 struct kvm_vcpu *vcpu;
7242 int i;
7243
0d9ce162 7244 mutex_lock(&kvm_lock);
d828199e
MT		 7245 list_for_each_entry(kvm, &vm_list, vm_list)
7246 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 7247 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 7248 atomic_set(&kvm_guest_has_master_clock, 0);
0d9ce162 7249 mutex_unlock(&kvm_lock);
16e8d74d
MT		 7250}
7251
7252static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
7253
7254/*
7255 * Notification about pvclock gtod data update.
7256 */
7257static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
7258 void *priv)
7259{
7260 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
7261 struct timekeeper *tk = priv;
7262
7263 update_pvclock_gtod(tk);
7264
7265 /* disable master clock if host does not trust, or does not
b0c39dc6 7266 * use, TSC based clocksource.
16e8d74d 7267 */
b0c39dc6 7268 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
16e8d74d
MT		 7269 atomic_read(&kvm_guest_has_master_clock) != 0)
7270 queue_work(system_long_wq, &pvclock_gtod_work);
7271
7272 return 0;
7273}
7274
7275static struct notifier_block pvclock_gtod_notifier = {
7276 .notifier_call = pvclock_gtod_notify,
7277};
7278#endif
7279
f8c16bba 7280int kvm_arch_init(void *opaque)
043405e1 7281{
b820cc0c 7282 int r;
6b61edf7 7283 struct kvm_x86_ops *ops = opaque;
f8c16bba 7284
f8c16bba
ZX		 7285 if (kvm_x86_ops) {
7286 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 7287 r = -EEXIST;
7288 goto out;
f8c16bba
ZX		 7289 }
7290
7291 if (!ops->cpu_has_kvm_support()) {
7292 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 7293 r = -EOPNOTSUPP;
7294 goto out;
f8c16bba
ZX		 7295 }
7296 if (ops->disabled_by_bios()) {
7297 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 7298 r = -EOPNOTSUPP;
7299 goto out;
f8c16bba
ZX		 7300 }
7301
b666a4b6
MO		 7302 /*
7303 * KVM explicitly assumes that the guest has an FPU and
7304 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
7305 * vCPU's FPU state as a fxregs_state struct.
7306 */
7307 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
7308 printk(KERN_ERR "kvm: inadequate fpu\n");
7309 r = -EOPNOTSUPP;
7310 goto out;
7311 }
7312
013f6a5d 7313 r = -ENOMEM;
ed8e4812 7314 x86_fpu_cache = kmem_cache_create("x86_fpu", sizeof(struct fpu),
b666a4b6
MO		 7315 __alignof__(struct fpu), SLAB_ACCOUNT,
7316 NULL);
7317 if (!x86_fpu_cache) {
7318 printk(KERN_ERR "kvm: failed to allocate cache for x86 fpu\n");
7319 goto out;
7320 }
7321
013f6a5d
MT		 7322 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
7323 if (!shared_msrs) {
7324 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
b666a4b6 7325 goto out_free_x86_fpu_cache;
013f6a5d
MT		 7326 }
7327
97db56ce
AK		 7328 r = kvm_mmu_module_init();
7329 if (r)
013f6a5d 7330 goto out_free_percpu;
97db56ce 7331
f8c16bba 7332 kvm_x86_ops = ops;
920c8377 7333
7b52345e 7334 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 7335 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 7336 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 7337 kvm_timer_init();
c8076604 7338
ff9d07a0
ZY		 7339 perf_register_guest_info_callbacks(&kvm_guest_cbs);
7340
d366bf7e 7341 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC		 7342 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
7343
c5cc421b 7344 kvm_lapic_init();
0c5f81da
WL		 7345 if (pi_inject_timer == -1)
7346 pi_inject_timer = housekeeping_enabled(HK_FLAG_TIMER);
16e8d74d
MT		 7347#ifdef CONFIG_X86_64
7348 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
0092e434 7349
5fa4ec9c 7350 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434 7351 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
16e8d74d
MT		 7352#endif
7353
f8c16bba 7354 return 0;
56c6d28a 7355
013f6a5d
MT		 7356out_free_percpu:
7357 free_percpu(shared_msrs);
b666a4b6
MO		 7358out_free_x86_fpu_cache:
7359 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7360out:
56c6d28a 7361 return r;
043405e1 7362}
8776e519 7363
f8c16bba
ZX		 7364void kvm_arch_exit(void)
7365{
0092e434 7366#ifdef CONFIG_X86_64
5fa4ec9c 7367 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
0092e434
VK		 7368 clear_hv_tscchange_cb();
7369#endif
cef84c30 7370 kvm_lapic_exit();
ff9d07a0
ZY		 7371 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
7372
888d256e
JK		 7373 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
7374 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
7375 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 7376 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT		 7377#ifdef CONFIG_X86_64
7378 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
7379#endif
f8c16bba 7380 kvm_x86_ops = NULL;
56c6d28a 7381 kvm_mmu_module_exit();
013f6a5d 7382 free_percpu(shared_msrs);
b666a4b6 7383 kmem_cache_destroy(x86_fpu_cache);
56c6d28a 7384}
f8c16bba 7385
5cb56059 7386int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 7387{
7388 ++vcpu->stat.halt_exits;
35754c98 7389 if (lapic_in_kernel(vcpu)) {
a4535290 7390 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 7391 return 1;
7392 } else {
7393 vcpu->run->exit_reason = KVM_EXIT_HLT;
7394 return 0;
7395 }
7396}
5cb56059
JS		 7397EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
7398
7399int kvm_emulate_halt(struct kvm_vcpu *vcpu)
7400{
6affcbed
KH		 7401 int ret = kvm_skip_emulated_instruction(vcpu);
7402 /*
7403 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
7404 * KVM_EXIT_DEBUG here.
7405 */
7406 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 7407}
8776e519
HB		 7408EXPORT_SYMBOL_GPL(kvm_emulate_halt);
7409
8ef81a9a 7410#ifdef CONFIG_X86_64
55dd00a7
MT		 7411static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
7412 unsigned long clock_type)
7413{
7414 struct kvm_clock_pairing clock_pairing;
899a31f5 7415 struct timespec64 ts;
80fbd89c 7416 u64 cycle;
55dd00a7
MT		 7417 int ret;
7418
7419 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
7420 return -KVM_EOPNOTSUPP;
7421
7422 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
7423 return -KVM_EOPNOTSUPP;
7424
7425 clock_pairing.sec = ts.tv_sec;
7426 clock_pairing.nsec = ts.tv_nsec;
7427 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
7428 clock_pairing.flags = 0;
bcbfbd8e 7429 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
55dd00a7
MT		 7430
7431 ret = 0;
7432 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
7433 sizeof(struct kvm_clock_pairing)))
7434 ret = -KVM_EFAULT;
7435
7436 return ret;
7437}
8ef81a9a 7438#endif
55dd00a7 7439
6aef266c
SV		 7440/*
7441 * kvm_pv_kick_cpu_op: Kick a vcpu.
7442 *
7443 * @apicid - apicid of vcpu to be kicked.
7444 */
7445static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
7446{
24d2166b 7447 struct kvm_lapic_irq lapic_irq;
6aef266c 7448
150a84fe 7449 lapic_irq.shorthand = APIC_DEST_NOSHORT;
c96001c5 7450 lapic_irq.dest_mode = APIC_DEST_PHYSICAL;
ebd28fcb 7451 lapic_irq.level = 0;
24d2166b 7452 lapic_irq.dest_id = apicid;
93bbf0b8 7453 lapic_irq.msi_redir_hint = false;
6aef266c 7454
24d2166b 7455 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 7456 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 7457}
7458
d62caabb
AS		 7459void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
7460{
f7589cca
PB		 7461 if (!lapic_in_kernel(vcpu)) {
7462 WARN_ON_ONCE(vcpu->arch.apicv_active);
7463 return;
7464 }
7465 if (!vcpu->arch.apicv_active)
7466 return;
7467
d62caabb
AS		 7468 vcpu->arch.apicv_active = false;
7469 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
7470}
7471
4e19c36f
SS		 7472bool kvm_apicv_activated(struct kvm *kvm)
7473{
7474 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
7475}
7476EXPORT_SYMBOL_GPL(kvm_apicv_activated);
7477
7478void kvm_apicv_init(struct kvm *kvm, bool enable)
7479{
7480 if (enable)
7481 clear_bit(APICV_INHIBIT_REASON_DISABLE,
7482 &kvm->arch.apicv_inhibit_reasons);
7483 else
7484 set_bit(APICV_INHIBIT_REASON_DISABLE,
7485 &kvm->arch.apicv_inhibit_reasons);
7486}
7487EXPORT_SYMBOL_GPL(kvm_apicv_init);
7488
71506297
WL		 7489static void kvm_sched_yield(struct kvm *kvm, unsigned long dest_id)
7490{
7491 struct kvm_vcpu *target = NULL;
7492 struct kvm_apic_map *map;
7493
7494 rcu_read_lock();
7495 map = rcu_dereference(kvm->arch.apic_map);
7496
7497 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
7498 target = map->phys_map[dest_id]->vcpu;
7499
7500 rcu_read_unlock();
7501
266e85a5 7502 if (target && READ_ONCE(target->ready))
71506297
WL		 7503 kvm_vcpu_yield_to(target);
7504}
7505
8776e519
HB		 7506int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
7507{
7508 unsigned long nr, a0, a1, a2, a3, ret;
6356ee0c 7509 int op_64_bit;
8776e519 7510
696ca779
RK		 7511 if (kvm_hv_hypercall_enabled(vcpu->kvm))
7512 return kvm_hv_hypercall(vcpu);
55cd8e5a 7513
de3cd117
SC		 7514 nr = kvm_rax_read(vcpu);
7515 a0 = kvm_rbx_read(vcpu);
7516 a1 = kvm_rcx_read(vcpu);
7517 a2 = kvm_rdx_read(vcpu);
7518 a3 = kvm_rsi_read(vcpu);
8776e519 7519
229456fc 7520 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 7521
a449c7aa
NA		 7522 op_64_bit = is_64_bit_mode(vcpu);
7523 if (!op_64_bit) {
8776e519
HB		 7524 nr &= 0xFFFFFFFF;
7525 a0 &= 0xFFFFFFFF;
7526 a1 &= 0xFFFFFFFF;
7527 a2 &= 0xFFFFFFFF;
7528 a3 &= 0xFFFFFFFF;
7529 }
7530
07708c4a
JK		 7531 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
7532 ret = -KVM_EPERM;
696ca779 7533 goto out;
07708c4a
JK		 7534 }
7535
8776e519 7536 switch (nr) {
b93463aa
AK		 7537 case KVM_HC_VAPIC_POLL_IRQ:
7538 ret = 0;
7539 break;
6aef266c
SV		 7540 case KVM_HC_KICK_CPU:
7541 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
266e85a5 7542 kvm_sched_yield(vcpu->kvm, a1);
6aef266c
SV		 7543 ret = 0;
7544 break;
8ef81a9a 7545#ifdef CONFIG_X86_64
55dd00a7
MT		 7546 case KVM_HC_CLOCK_PAIRING:
7547 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
7548 break;
1ed199a4 7549#endif
4180bf1b
WL		 7550 case KVM_HC_SEND_IPI:
7551 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
7552 break;
71506297
WL		 7553 case KVM_HC_SCHED_YIELD:
7554 kvm_sched_yield(vcpu->kvm, a0);
7555 ret = 0;
7556 break;
8776e519
HB		 7557 default:
7558 ret = -KVM_ENOSYS;
7559 break;
7560 }
696ca779 7561out:
a449c7aa
NA		 7562 if (!op_64_bit)
7563 ret = (u32)ret;
de3cd117 7564 kvm_rax_write(vcpu, ret);
6356ee0c 7565
f11c3a8d 7566 ++vcpu->stat.hypercalls;
6356ee0c 7567 return kvm_skip_emulated_instruction(vcpu);
8776e519
HB		 7568}
7569EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
7570
b6785def 7571static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 7572{
d6aa1000 7573 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 7574 char instruction[3];
5fdbf976 7575 unsigned long rip = kvm_rip_read(vcpu);
8776e519 7576
8776e519 7577 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 7578
ce2e852e
DV		 7579 return emulator_write_emulated(ctxt, rip, instruction, 3,
7580 &ctxt->exception);
8776e519
HB		 7581}
7582
851ba692 7583static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 7584{
782d422b
MG		 7585 return vcpu->run->request_interrupt_window &&
7586 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB		 7587}
7588
851ba692 7589static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 7590{
851ba692
AK		 7591 struct kvm_run *kvm_run = vcpu->run;
7592
91586a3b 7593 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 7594 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 7595 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 7596 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG		 7597 kvm_run->ready_for_interrupt_injection =
7598 pic_in_kernel(vcpu->kvm) ||
782d422b 7599 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB		 7600}
7601
95ba8273
GN		 7602static void update_cr8_intercept(struct kvm_vcpu *vcpu)
7603{
7604 int max_irr, tpr;
7605
7606 if (!kvm_x86_ops->update_cr8_intercept)
7607 return;
7608
bce87cce 7609 if (!lapic_in_kernel(vcpu))
88c808fd
AK		 7610 return;
7611
d62caabb
AS		 7612 if (vcpu->arch.apicv_active)
7613 return;
7614
8db3baa2
GN		 7615 if (!vcpu->arch.apic->vapic_addr)
7616 max_irr = kvm_lapic_find_highest_irr(vcpu);
7617 else
7618 max_irr = -1;
95ba8273
GN		 7619
7620 if (max_irr != -1)
7621 max_irr >>= 4;
7622
7623 tpr = kvm_lapic_get_cr8(vcpu);
7624
7625 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
7626}
7627
b6b8a145 7628static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 7629{
b6b8a145
JK		 7630 int r;
7631
95ba8273 7632 /* try to reinject previous events if any */
664f8e26 7633
1a680e35
LA		 7634 if (vcpu->arch.exception.injected)
7635 kvm_x86_ops->queue_exception(vcpu);
664f8e26 7636 /*
a042c26f
LA		 7637 * Do not inject an NMI or interrupt if there is a pending
7638 * exception. Exceptions and interrupts are recognized at
7639 * instruction boundaries, i.e. the start of an instruction.
7640 * Trap-like exceptions, e.g. #DB, have higher priority than
7641 * NMIs and interrupts, i.e. traps are recognized before an
7642 * NMI/interrupt that's pending on the same instruction.
7643 * Fault-like exceptions, e.g. #GP and #PF, are the lowest
7644 * priority, but are only generated (pended) during instruction
7645 * execution, i.e. a pending fault-like exception means the
7646 * fault occurred on the *previous* instruction and must be
7647 * serviced prior to recognizing any new events in order to
7648 * fully complete the previous instruction.
664f8e26 7649 */
1a680e35
LA		 7650 else if (!vcpu->arch.exception.pending) {
7651 if (vcpu->arch.nmi_injected)
664f8e26 7652 kvm_x86_ops->set_nmi(vcpu);
1a680e35 7653 else if (vcpu->arch.interrupt.injected)
664f8e26 7654 kvm_x86_ops->set_irq(vcpu);
664f8e26
WL		 7655 }
7656
1a680e35
LA		 7657 /*
7658 * Call check_nested_events() even if we reinjected a previous event
7659 * in order for caller to determine if it should require immediate-exit
7660 * from L2 to L1 due to pending L1 events which require exit
7661 * from L2 to L1.
7662 */
664f8e26
WL		 7663 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7664 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7665 if (r != 0)
7666 return r;
7667 }
7668
7669 /* try to inject new event if pending */
b59bb7bd 7670 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 7671 trace_kvm_inj_exception(vcpu->arch.exception.nr,
7672 vcpu->arch.exception.has_error_code,
7673 vcpu->arch.exception.error_code);
d6e8c854 7674
1a680e35 7675 WARN_ON_ONCE(vcpu->arch.exception.injected);
664f8e26
WL		 7676 vcpu->arch.exception.pending = false;
7677 vcpu->arch.exception.injected = true;
7678
d6e8c854
NA		 7679 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
7680 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
7681 X86_EFLAGS_RF);
7682
f10c729f
JM		 7683 if (vcpu->arch.exception.nr == DB_VECTOR) {
7684 /*
7685 * This code assumes that nSVM doesn't use
7686 * check_nested_events(). If it does, the
7687 * DR6/DR7 changes should happen before L1
7688 * gets a #VMEXIT for an intercepted #DB in
7689 * L2. (Under VMX, on the other hand, the
7690 * DR6/DR7 changes should not happen in the
7691 * event of a VM-exit to L1 for an intercepted
7692 * #DB in L2.)
7693 */
7694 kvm_deliver_exception_payload(vcpu);
7695 if (vcpu->arch.dr7 & DR7_GD) {
7696 vcpu->arch.dr7 &= ~DR7_GD;
7697 kvm_update_dr7(vcpu);
7698 }
6bdf0662
NA		 7699 }
7700
cfcd20e5 7701 kvm_x86_ops->queue_exception(vcpu);
1a680e35
LA		 7702 }
7703
7704 /* Don't consider new event if we re-injected an event */
7705 if (kvm_event_needs_reinjection(vcpu))
7706 return 0;
7707
7708 if (vcpu->arch.smi_pending && !is_smm(vcpu) &&
7709 kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 7710 vcpu->arch.smi_pending = false;
52797bf9 7711 ++vcpu->arch.smi_count;
ee2cd4b7 7712 enter_smm(vcpu);
c43203ca 7713 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS		 7714 --vcpu->arch.nmi_pending;
7715 vcpu->arch.nmi_injected = true;
7716 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 7717 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 7718 /*
7719 * Because interrupts can be injected asynchronously, we are
7720 * calling check_nested_events again here to avoid a race condition.
7721 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
7722 * proposal and current concerns. Perhaps we should be setting
7723 * KVM_REQ_EVENT only on certain events and not unconditionally?
7724 */
7725 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
7726 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
7727 if (r != 0)
7728 return r;
7729 }
95ba8273 7730 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 7731 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
7732 false);
7733 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 7734 }
7735 }
ee2cd4b7 7736
b6b8a145 7737 return 0;
95ba8273
GN		 7738}
7739
7460fb4a
AK		 7740static void process_nmi(struct kvm_vcpu *vcpu)
7741{
7742 unsigned limit = 2;
7743
7744 /*
7745 * x86 is limited to one NMI running, and one NMI pending after it.
7746 * If an NMI is already in progress, limit further NMIs to just one.
7747 * Otherwise, allow two (and we'll inject the first one immediately).
7748 */
7749 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
7750 limit = 1;
7751
7752 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
7753 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
7754 kvm_make_request(KVM_REQ_EVENT, vcpu);
7755}
7756
ee2cd4b7 7757static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB		 7758{
7759 u32 flags = 0;
7760 flags |= seg->g << 23;
7761 flags |= seg->db << 22;
7762 flags |= seg->l << 21;
7763 flags |= seg->avl << 20;
7764 flags |= seg->present << 15;
7765 flags |= seg->dpl << 13;
7766 flags |= seg->s << 12;
7767 flags |= seg->type << 8;
7768 return flags;
7769}
7770
ee2cd4b7 7771static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7772{
7773 struct kvm_segment seg;
7774 int offset;
7775
7776 kvm_get_segment(vcpu, &seg, n);
7777 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
7778
7779 if (n < 3)
7780 offset = 0x7f84 + n * 12;
7781 else
7782 offset = 0x7f2c + (n - 3) * 12;
7783
7784 put_smstate(u32, buf, offset + 8, seg.base);
7785 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 7786 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7787}
7788
efbb288a 7789#ifdef CONFIG_X86_64
ee2cd4b7 7790static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB		 7791{
7792 struct kvm_segment seg;
7793 int offset;
7794 u16 flags;
7795
7796 kvm_get_segment(vcpu, &seg, n);
7797 offset = 0x7e00 + n * 16;
7798
ee2cd4b7 7799 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB		 7800 put_smstate(u16, buf, offset, seg.selector);
7801 put_smstate(u16, buf, offset + 2, flags);
7802 put_smstate(u32, buf, offset + 4, seg.limit);
7803 put_smstate(u64, buf, offset + 8, seg.base);
7804}
efbb288a 7805#endif
660a5d51 7806
ee2cd4b7 7807static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB		 7808{
7809 struct desc_ptr dt;
7810 struct kvm_segment seg;
7811 unsigned long val;
7812 int i;
7813
7814 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
7815 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
7816 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
7817 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
7818
7819 for (i = 0; i < 8; i++)
7820 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
7821
7822 kvm_get_dr(vcpu, 6, &val);
7823 put_smstate(u32, buf, 0x7fcc, (u32)val);
7824 kvm_get_dr(vcpu, 7, &val);
7825 put_smstate(u32, buf, 0x7fc8, (u32)val);
7826
7827 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7828 put_smstate(u32, buf, 0x7fc4, seg.selector);
7829 put_smstate(u32, buf, 0x7f64, seg.base);
7830 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 7831 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7832
7833 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7834 put_smstate(u32, buf, 0x7fc0, seg.selector);
7835 put_smstate(u32, buf, 0x7f80, seg.base);
7836 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 7837 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB		 7838
7839 kvm_x86_ops->get_gdt(vcpu, &dt);
7840 put_smstate(u32, buf, 0x7f74, dt.address);
7841 put_smstate(u32, buf, 0x7f70, dt.size);
7842
7843 kvm_x86_ops->get_idt(vcpu, &dt);
7844 put_smstate(u32, buf, 0x7f58, dt.address);
7845 put_smstate(u32, buf, 0x7f54, dt.size);
7846
7847 for (i = 0; i < 6; i++)
ee2cd4b7 7848 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB		 7849
7850 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
7851
7852 /* revision id */
7853 put_smstate(u32, buf, 0x7efc, 0x00020000);
7854 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
7855}
7856
b68f3cc7 7857#ifdef CONFIG_X86_64
ee2cd4b7 7858static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51 7859{
660a5d51
PB		 7860 struct desc_ptr dt;
7861 struct kvm_segment seg;
7862 unsigned long val;
7863 int i;
7864
7865 for (i = 0; i < 16; i++)
7866 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
7867
7868 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
7869 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
7870
7871 kvm_get_dr(vcpu, 6, &val);
7872 put_smstate(u64, buf, 0x7f68, val);
7873 kvm_get_dr(vcpu, 7, &val);
7874 put_smstate(u64, buf, 0x7f60, val);
7875
7876 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
7877 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
7878 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
7879
7880 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
7881
7882 /* revision id */
7883 put_smstate(u32, buf, 0x7efc, 0x00020064);
7884
7885 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
7886
7887 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
7888 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 7889 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7890 put_smstate(u32, buf, 0x7e94, seg.limit);
7891 put_smstate(u64, buf, 0x7e98, seg.base);
7892
7893 kvm_x86_ops->get_idt(vcpu, &dt);
7894 put_smstate(u32, buf, 0x7e84, dt.size);
7895 put_smstate(u64, buf, 0x7e88, dt.address);
7896
7897 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
7898 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 7899 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB		 7900 put_smstate(u32, buf, 0x7e74, seg.limit);
7901 put_smstate(u64, buf, 0x7e78, seg.base);
7902
7903 kvm_x86_ops->get_gdt(vcpu, &dt);
7904 put_smstate(u32, buf, 0x7e64, dt.size);
7905 put_smstate(u64, buf, 0x7e68, dt.address);
7906
7907 for (i = 0; i < 6; i++)
ee2cd4b7 7908 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51 7909}
b68f3cc7 7910#endif
660a5d51 7911
ee2cd4b7 7912static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 7913{
660a5d51 7914 struct kvm_segment cs, ds;
18c3626e 7915 struct desc_ptr dt;
660a5d51
PB		 7916 char buf[512];
7917 u32 cr0;
7918
660a5d51 7919 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 7920 memset(buf, 0, 512);
b68f3cc7 7921#ifdef CONFIG_X86_64
d6321d49 7922 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 7923 enter_smm_save_state_64(vcpu, buf);
660a5d51 7924 else
b68f3cc7 7925#endif
ee2cd4b7 7926 enter_smm_save_state_32(vcpu, buf);
660a5d51 7927
0234bf88
LP		 7928 /*
7929 * Give pre_enter_smm() a chance to make ISA-specific changes to the
7930 * vCPU state (e.g. leave guest mode) after we've saved the state into
7931 * the SMM state-save area.
7932 */
7933 kvm_x86_ops->pre_enter_smm(vcpu, buf);
7934
7935 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 7936 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 7937
7938 if (kvm_x86_ops->get_nmi_mask(vcpu))
7939 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
7940 else
7941 kvm_x86_ops->set_nmi_mask(vcpu, true);
7942
7943 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
7944 kvm_rip_write(vcpu, 0x8000);
7945
7946 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
7947 kvm_x86_ops->set_cr0(vcpu, cr0);
7948 vcpu->arch.cr0 = cr0;
7949
7950 kvm_x86_ops->set_cr4(vcpu, 0);
7951
18c3626e
PB		 7952 /* Undocumented: IDT limit is set to zero on entry to SMM. */
7953 dt.address = dt.size = 0;
7954 kvm_x86_ops->set_idt(vcpu, &dt);
7955
660a5d51
PB		 7956 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
7957
7958 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
7959 cs.base = vcpu->arch.smbase;
7960
7961 ds.selector = 0;
7962 ds.base = 0;
7963
7964 cs.limit = ds.limit = 0xffffffff;
7965 cs.type = ds.type = 0x3;
7966 cs.dpl = ds.dpl = 0;
7967 cs.db = ds.db = 0;
7968 cs.s = ds.s = 1;
7969 cs.l = ds.l = 0;
7970 cs.g = ds.g = 1;
7971 cs.avl = ds.avl = 0;
7972 cs.present = ds.present = 1;
7973 cs.unusable = ds.unusable = 0;
7974 cs.padding = ds.padding = 0;
7975
7976 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7977 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
7978 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
7979 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
7980 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
7981 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
7982
b68f3cc7 7983#ifdef CONFIG_X86_64
d6321d49 7984 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51 7985 kvm_x86_ops->set_efer(vcpu, 0);
b68f3cc7 7986#endif
660a5d51
PB		 7987
7988 kvm_update_cpuid(vcpu);
7989 kvm_mmu_reset_context(vcpu);
64d60670
PB		 7990}
7991
ee2cd4b7 7992static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB		 7993{
7994 vcpu->arch.smi_pending = true;
7995 kvm_make_request(KVM_REQ_EVENT, vcpu);
7996}
7997
7ee30bc1
NNL		 7998void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
7999 unsigned long *vcpu_bitmap)
8000{
8001 cpumask_var_t cpus;
7ee30bc1
NNL		 8002
8003 zalloc_cpumask_var(&cpus, GFP_ATOMIC);
8004
db5a95ec
MW		 8005 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC,
8006 vcpu_bitmap, cpus);
7ee30bc1
NNL		 8007
8008 free_cpumask_var(cpus);
8009}
8010
2860c4b1
PB		 8011void kvm_make_scan_ioapic_request(struct kvm *kvm)
8012{
8013 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
8014}
8015
3d81bc7e 8016static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 8017{
dcbd3e49 8018 if (!kvm_apic_present(vcpu))
3d81bc7e 8019 return;
c7c9c56c 8020
6308630b 8021 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 8022
b053b2ae 8023 if (irqchip_split(vcpu->kvm))
6308630b 8024 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 8025 else {
fa59cc00 8026 if (vcpu->arch.apicv_active)
d62caabb 8027 kvm_x86_ops->sync_pir_to_irr(vcpu);
e97f852f
WL		 8028 if (ioapic_in_kernel(vcpu->kvm))
8029 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 8030 }
e40ff1d6
LA		 8031
8032 if (is_guest_mode(vcpu))
8033 vcpu->arch.load_eoi_exitmap_pending = true;
8034 else
8035 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
8036}
8037
8038static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8039{
8040 u64 eoi_exit_bitmap[4];
8041
8042 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
8043 return;
8044
5c919412
AS		 8045 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
8046 vcpu_to_synic(vcpu)->vec_bitmap, 256);
8047 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ		 8048}
8049
93065ac7
MH		 8050int kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
8051 unsigned long start, unsigned long end,
8052 bool blockable)
b1394e74
RK		 8053{
8054 unsigned long apic_address;
8055
8056 /*
8057 * The physical address of apic access page is stored in the VMCS.
8058 * Update it when it becomes invalid.
8059 */
8060 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
8061 if (start <= apic_address && apic_address < end)
8062 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
93065ac7
MH		 8063
8064 return 0;
b1394e74
RK		 8065}
8066
4256f43f
TC		 8067void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
8068{
c24ae0dc
TC		 8069 struct page *page = NULL;
8070
35754c98 8071 if (!lapic_in_kernel(vcpu))
f439ed27
PB		 8072 return;
8073
4256f43f
TC		 8074 if (!kvm_x86_ops->set_apic_access_page_addr)
8075 return;
8076
c24ae0dc 8077 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 8078 if (is_error_page(page))
8079 return;
c24ae0dc
TC		 8080 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
8081
8082 /*
8083 * Do not pin apic access page in memory, the MMU notifier
8084 * will call us again if it is migrated or swapped out.
8085 */
8086 put_page(page);
4256f43f 8087}
4256f43f 8088
d264ee0c
SC		 8089void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
8090{
8091 smp_send_reschedule(vcpu->cpu);
8092}
8093EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
8094
9357d939 8095/*
362c698f 8096 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 8097 * exiting to the userspace. Otherwise, the value will be returned to the
8098 * userspace.
8099 */
851ba692 8100static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 8101{
8102 int r;
62a193ed
MG		 8103 bool req_int_win =
8104 dm_request_for_irq_injection(vcpu) &&
8105 kvm_cpu_accept_dm_intr(vcpu);
1e9e2622 8106 enum exit_fastpath_completion exit_fastpath = EXIT_FASTPATH_NONE;
62a193ed 8107
730dca42 8108 bool req_immediate_exit = false;
b6c7a5dc 8109
2fa6e1e1 8110 if (kvm_request_pending(vcpu)) {
671ddc70
JM		 8111 if (kvm_check_request(KVM_REQ_GET_VMCS12_PAGES, vcpu)) {
8112 if (unlikely(!kvm_x86_ops->get_vmcs12_pages(vcpu))) {
8113 r = 0;
8114 goto out;
8115 }
8116 }
a8eeb04a 8117 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 8118 kvm_mmu_unload(vcpu);
a8eeb04a 8119 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 8120 __kvm_migrate_timers(vcpu);
d828199e
MT		 8121 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
8122 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 8123 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
8124 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 8125 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
8126 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 8127 if (unlikely(r))
8128 goto out;
8129 }
a8eeb04a 8130 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 8131 kvm_mmu_sync_roots(vcpu);
6e42782f
JS		 8132 if (kvm_check_request(KVM_REQ_LOAD_CR3, vcpu))
8133 kvm_mmu_load_cr3(vcpu);
a8eeb04a 8134 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
c2ba05cc 8135 kvm_vcpu_flush_tlb(vcpu, true);
a8eeb04a 8136 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 8137 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 8138 r = 0;
8139 goto out;
8140 }
a8eeb04a 8141 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 8142 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 8143 vcpu->mmio_needed = 0;
71c4dfaf
JR		 8144 r = 0;
8145 goto out;
8146 }
af585b92
GN		 8147 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
8148 /* Page is swapped out. Do synthetic halt */
8149 vcpu->arch.apf.halted = true;
8150 r = 1;
8151 goto out;
8152 }
c9aaa895
GC		 8153 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
8154 record_steal_time(vcpu);
64d60670
PB		 8155 if (kvm_check_request(KVM_REQ_SMI, vcpu))
8156 process_smi(vcpu);
7460fb4a
AK		 8157 if (kvm_check_request(KVM_REQ_NMI, vcpu))
8158 process_nmi(vcpu);
f5132b01 8159 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 8160 kvm_pmu_handle_event(vcpu);
f5132b01 8161 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 8162 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR		 8163 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
8164 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
8165 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 8166 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR		 8167 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
8168 vcpu->run->eoi.vector =
8169 vcpu->arch.pending_ioapic_eoi;
8170 r = 0;
8171 goto out;
8172 }
8173 }
3d81bc7e
YZ		 8174 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
8175 vcpu_scan_ioapic(vcpu);
e40ff1d6
LA		 8176 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
8177 vcpu_load_eoi_exitmap(vcpu);
4256f43f
TC		 8178 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
8179 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS		 8180 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
8181 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8182 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
8183 r = 0;
8184 goto out;
8185 }
e516cebb
AS		 8186 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
8187 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
8188 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
8189 r = 0;
8190 goto out;
8191 }
db397571
AS		 8192 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
8193 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
8194 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
8195 r = 0;
8196 goto out;
8197 }
f3b138c5
AS		 8198
8199 /*
8200 * KVM_REQ_HV_STIMER has to be processed after
8201 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
8202 * depend on the guest clock being up-to-date
8203 */
1f4b34f8
AS		 8204 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
8205 kvm_hv_process_stimers(vcpu);
2f52d58c 8206 }
b93463aa 8207
b463a6f7 8208 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 8209 ++vcpu->stat.req_event;
66450a21
JK		 8210 kvm_apic_accept_events(vcpu);
8211 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
8212 r = 1;
8213 goto out;
8214 }
8215
b6b8a145
JK		 8216 if (inject_pending_event(vcpu, req_int_win) != 0)
8217 req_immediate_exit = true;
321c5658 8218 else {
cc3d967f 8219 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 8220 *
cc3d967f
LP		 8221 * SMIs have three cases:
8222 * 1) They can be nested, and then there is nothing to
8223 * do here because RSM will cause a vmexit anyway.
8224 * 2) There is an ISA-specific reason why SMI cannot be
8225 * injected, and the moment when this changes can be
8226 * intercepted.
8227 * 3) Or the SMI can be pending because
8228 * inject_pending_event has completed the injection
8229 * of an IRQ or NMI from the previous vmexit, and
8230 * then we request an immediate exit to inject the
8231 * SMI.
c43203ca
PB		 8232 */
8233 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP		 8234 if (!kvm_x86_ops->enable_smi_window(vcpu))
8235 req_immediate_exit = true;
321c5658
YS		 8236 if (vcpu->arch.nmi_pending)
8237 kvm_x86_ops->enable_nmi_window(vcpu);
8238 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
8239 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 8240 WARN_ON(vcpu->arch.exception.pending);
321c5658 8241 }
b463a6f7
AK		 8242
8243 if (kvm_lapic_enabled(vcpu)) {
8244 update_cr8_intercept(vcpu);
8245 kvm_lapic_sync_to_vapic(vcpu);
8246 }
8247 }
8248
d8368af8
AK		 8249 r = kvm_mmu_reload(vcpu);
8250 if (unlikely(r)) {
d905c069 8251 goto cancel_injection;
d8368af8
AK		 8252 }
8253
b6c7a5dc
HB		 8254 preempt_disable();
8255
8256 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB		 8257
8258 /*
8259 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
8260 * IPI are then delayed after guest entry, which ensures that they
8261 * result in virtual interrupt delivery.
8262 */
8263 local_irq_disable();
6b7e2d09
XG		 8264 vcpu->mode = IN_GUEST_MODE;
8265
01b71917
MT		 8266 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
8267
0f127d12 8268 /*
b95234c8 8269 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 8270 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8 8271 *
81b01667 8272 * 2) For APICv, we should set ->mode before checking PID.ON. This
b95234c8
PB		 8273 * pairs with the memory barrier implicit in pi_test_and_set_on
8274 * (see vmx_deliver_posted_interrupt).
8275 *
8276 * 3) This also orders the write to mode from any reads to the page
8277 * tables done while the VCPU is running. Please see the comment
8278 * in kvm_flush_remote_tlbs.
6b7e2d09 8279 */
01b71917 8280 smp_mb__after_srcu_read_unlock();
b6c7a5dc 8281
b95234c8
PB		 8282 /*
8283 * This handles the case where a posted interrupt was
8284 * notified with kvm_vcpu_kick.
8285 */
fa59cc00
LA		 8286 if (kvm_lapic_enabled(vcpu) && vcpu->arch.apicv_active)
8287 kvm_x86_ops->sync_pir_to_irr(vcpu);
32f88400 8288
2fa6e1e1 8289 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 8290 || need_resched() || signal_pending(current)) {
6b7e2d09 8291 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8292 smp_wmb();
6c142801
AK		 8293 local_irq_enable();
8294 preempt_enable();
01b71917 8295 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 8296 r = 1;
d905c069 8297 goto cancel_injection;
6c142801
AK		 8298 }
8299
c43203ca
PB		 8300 if (req_immediate_exit) {
8301 kvm_make_request(KVM_REQ_EVENT, vcpu);
d264ee0c 8302 kvm_x86_ops->request_immediate_exit(vcpu);
c43203ca 8303 }
d6185f20 8304
8b89fe1f 8305 trace_kvm_entry(vcpu->vcpu_id);
6edaa530 8306 guest_enter_irqoff();
b6c7a5dc 8307
2620fe26
SC		 8308 fpregs_assert_state_consistent();
8309 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8310 switch_fpu_return();
5f409e20 8311
42dbaa5a 8312 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 8313 set_debugreg(0, 7);
8314 set_debugreg(vcpu->arch.eff_db[0], 0);
8315 set_debugreg(vcpu->arch.eff_db[1], 1);
8316 set_debugreg(vcpu->arch.eff_db[2], 2);
8317 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 8318 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 8319 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 8320 }
b6c7a5dc 8321
851ba692 8322 kvm_x86_ops->run(vcpu);
b6c7a5dc 8323
c77fb5fe
PB		 8324 /*
8325 * Do this here before restoring debug registers on the host. And
8326 * since we do this before handling the vmexit, a DR access vmexit
8327 * can (a) read the correct value of the debug registers, (b) set
8328 * KVM_DEBUGREG_WONT_EXIT again.
8329 */
8330 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB		 8331 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
8332 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB		 8333 kvm_update_dr0123(vcpu);
8334 kvm_update_dr6(vcpu);
8335 kvm_update_dr7(vcpu);
8336 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB		 8337 }
8338
24f1e32c
FW		 8339 /*
8340 * If the guest has used debug registers, at least dr7
8341 * will be disabled while returning to the host.
8342 * If we don't have active breakpoints in the host, we don't
8343 * care about the messed up debug address registers. But if
8344 * we have some of them active, restore the old state.
8345 */
59d8eb53 8346 if (hw_breakpoint_active())
24f1e32c 8347 hw_breakpoint_restore();
42dbaa5a 8348
4ba76538 8349 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 8350
6b7e2d09 8351 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 8352 smp_wmb();
a547c6db 8353
1e9e2622 8354 kvm_x86_ops->handle_exit_irqoff(vcpu, &exit_fastpath);
b6c7a5dc 8355
d7a08882
SC		 8356 /*
8357 * Consume any pending interrupts, including the possible source of
8358 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
8359 * An instruction is required after local_irq_enable() to fully unblock
8360 * interrupts on processors that implement an interrupt shadow, the
8361 * stat.exits increment will do nicely.
8362 */
8363 kvm_before_interrupt(vcpu);
8364 local_irq_enable();
b6c7a5dc 8365 ++vcpu->stat.exits;
d7a08882
SC		 8366 local_irq_disable();
8367 kvm_after_interrupt(vcpu);
b6c7a5dc 8368
f2485b3e 8369 guest_exit_irqoff();
ec0671d5
WL		 8370 if (lapic_in_kernel(vcpu)) {
8371 s64 delta = vcpu->arch.apic->lapic_timer.advance_expire_delta;
8372 if (delta != S64_MIN) {
8373 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, delta);
8374 vcpu->arch.apic->lapic_timer.advance_expire_delta = S64_MIN;
8375 }
8376 }
b6c7a5dc 8377
f2485b3e 8378 local_irq_enable();
b6c7a5dc
HB		 8379 preempt_enable();
8380
f656ce01 8381 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 8382
b6c7a5dc
HB		 8383 /*
8384 * Profile KVM exit RIPs:
8385 */
8386 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 8387 unsigned long rip = kvm_rip_read(vcpu);
8388 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 8389 }
8390
cc578287
ZA		 8391 if (unlikely(vcpu->arch.tsc_always_catchup))
8392 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 8393
5cfb1d5a
MT		 8394 if (vcpu->arch.apic_attention)
8395 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 8396
618232e2 8397 vcpu->arch.gpa_available = false;
1e9e2622 8398 r = kvm_x86_ops->handle_exit(vcpu, exit_fastpath);
d905c069
MT		 8399 return r;
8400
8401cancel_injection:
8402 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 8403 if (unlikely(vcpu->arch.apic_attention))
8404 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 8405out:
8406 return r;
8407}
b6c7a5dc 8408
362c698f
PB		 8409static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
8410{
bf9f6ac8
FW		 8411 if (!kvm_arch_vcpu_runnable(vcpu) &&
8412 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB		 8413 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
8414 kvm_vcpu_block(vcpu);
8415 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW		 8416
8417 if (kvm_x86_ops->post_block)
8418 kvm_x86_ops->post_block(vcpu);
8419
9c8fd1ba
PB		 8420 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
8421 return 1;
8422 }
362c698f
PB		 8423
8424 kvm_apic_accept_events(vcpu);
8425 switch(vcpu->arch.mp_state) {
8426 case KVM_MP_STATE_HALTED:
8427 vcpu->arch.pv.pv_unhalted = false;
8428 vcpu->arch.mp_state =
8429 KVM_MP_STATE_RUNNABLE;
b2869f28 8430 /* fall through */
362c698f
PB		 8431 case KVM_MP_STATE_RUNNABLE:
8432 vcpu->arch.apf.halted = false;
8433 break;
8434 case KVM_MP_STATE_INIT_RECEIVED:
8435 break;
8436 default:
8437 return -EINTR;
8438 break;
8439 }
8440 return 1;
8441}
09cec754 8442
5d9bc648
PB		 8443static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
8444{
0ad3bed6
PB		 8445 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8446 kvm_x86_ops->check_nested_events(vcpu, false);
8447
5d9bc648
PB		 8448 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8449 !vcpu->arch.apf.halted);
8450}
8451
362c698f 8452static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 8453{
8454 int r;
f656ce01 8455 struct kvm *kvm = vcpu->kvm;
d7690175 8456
f656ce01 8457 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
c595ceee 8458 vcpu->arch.l1tf_flush_l1d = true;
d7690175 8459
362c698f 8460 for (;;) {
58f800d5 8461 if (kvm_vcpu_running(vcpu)) {
851ba692 8462 r = vcpu_enter_guest(vcpu);
bf9f6ac8 8463 } else {
362c698f 8464 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW		 8465 }
8466
09cec754
GN		 8467 if (r <= 0)
8468 break;
8469
72875d8a 8470 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN		 8471 if (kvm_cpu_has_pending_timer(vcpu))
8472 kvm_inject_pending_timer_irqs(vcpu);
8473
782d422b
MG		 8474 if (dm_request_for_irq_injection(vcpu) &&
8475 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB		 8476 r = 0;
8477 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 8478 ++vcpu->stat.request_irq_exits;
362c698f 8479 break;
09cec754 8480 }
af585b92
GN		 8481
8482 kvm_check_async_pf_completion(vcpu);
8483
09cec754
GN		 8484 if (signal_pending(current)) {
8485 r = -EINTR;
851ba692 8486 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 8487 ++vcpu->stat.signal_exits;
362c698f 8488 break;
09cec754
GN		 8489 }
8490 if (need_resched()) {
f656ce01 8491 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 8492 cond_resched();
f656ce01 8493 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 8494 }
b6c7a5dc
HB		 8495 }
8496
f656ce01 8497 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 8498
8499 return r;
8500}
8501
716d51ab
GN		 8502static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
8503{
8504 int r;
60fc3d02 8505
716d51ab 8506 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
0ce97a2b 8507 r = kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
716d51ab 8508 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
60fc3d02 8509 return r;
716d51ab
GN		 8510}
8511
8512static int complete_emulated_pio(struct kvm_vcpu *vcpu)
8513{
8514 BUG_ON(!vcpu->arch.pio.count);
8515
8516 return complete_emulated_io(vcpu);
8517}
8518
f78146b0
AK		 8519/*
8520 * Implements the following, as a state machine:
8521 *
8522 * read:
8523 * for each fragment
87da7e66
XG		 8524 * for each mmio piece in the fragment
8525 * write gpa, len
8526 * exit
8527 * copy data
f78146b0
AK		 8528 * execute insn
8529 *
8530 * write:
8531 * for each fragment
87da7e66
XG		 8532 * for each mmio piece in the fragment
8533 * write gpa, len
8534 * copy data
8535 * exit
f78146b0 8536 */
716d51ab 8537static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 8538{
8539 struct kvm_run *run = vcpu->run;
f78146b0 8540 struct kvm_mmio_fragment *frag;
87da7e66 8541 unsigned len;
5287f194 8542
716d51ab 8543 BUG_ON(!vcpu->mmio_needed);
5287f194 8544
716d51ab 8545 /* Complete previous fragment */
87da7e66
XG		 8546 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
8547 len = min(8u, frag->len);
716d51ab 8548 if (!vcpu->mmio_is_write)
87da7e66
XG		 8549 memcpy(frag->data, run->mmio.data, len);
8550
8551 if (frag->len <= 8) {
8552 /* Switch to the next fragment. */
8553 frag++;
8554 vcpu->mmio_cur_fragment++;
8555 } else {
8556 /* Go forward to the next mmio piece. */
8557 frag->data += len;
8558 frag->gpa += len;
8559 frag->len -= len;
8560 }
8561
a08d3b3b 8562 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 8563 vcpu->mmio_needed = 0;
0912c977
PB		 8564
8565 /* FIXME: return into emulator if single-stepping. */
cef4dea0 8566 if (vcpu->mmio_is_write)
716d51ab
GN		 8567 return 1;
8568 vcpu->mmio_read_completed = 1;
8569 return complete_emulated_io(vcpu);
8570 }
87da7e66 8571
716d51ab
GN		 8572 run->exit_reason = KVM_EXIT_MMIO;
8573 run->mmio.phys_addr = frag->gpa;
8574 if (vcpu->mmio_is_write)
87da7e66
XG		 8575 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
8576 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 8577 run->mmio.is_write = vcpu->mmio_is_write;
8578 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
8579 return 0;
5287f194
AK		 8580}
8581
c9aef3b8
SC		 8582static void kvm_save_current_fpu(struct fpu *fpu)
8583{
8584 /*
8585 * If the target FPU state is not resident in the CPU registers, just
8586 * memcpy() from current, else save CPU state directly to the target.
8587 */
8588 if (test_thread_flag(TIF_NEED_FPU_LOAD))
8589 memcpy(&fpu->state, &current->thread.fpu.state,
8590 fpu_kernel_xstate_size);
8591 else
8592 copy_fpregs_to_fpstate(fpu);
8593}
8594
822f312d
SAS		 8595/* Swap (qemu) user FPU context for the guest FPU context. */
8596static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
8597{
5f409e20
RR		 8598 fpregs_lock();
8599
c9aef3b8
SC		 8600 kvm_save_current_fpu(vcpu->arch.user_fpu);
8601
822f312d 8602 /* PKRU is separately restored in kvm_x86_ops->run. */
b666a4b6 8603 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu->state,
822f312d 8604 ~XFEATURE_MASK_PKRU);
5f409e20
RR		 8605
8606 fpregs_mark_activate();
8607 fpregs_unlock();
8608
822f312d
SAS		 8609 trace_kvm_fpu(1);
8610}
8611
8612/* When vcpu_run ends, restore user space FPU context. */
8613static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
8614{
5f409e20
RR		 8615 fpregs_lock();
8616
c9aef3b8
SC		 8617 kvm_save_current_fpu(vcpu->arch.guest_fpu);
8618
d9a710e5 8619 copy_kernel_to_fpregs(&vcpu->arch.user_fpu->state);
5f409e20
RR		 8620
8621 fpregs_mark_activate();
8622 fpregs_unlock();
8623
822f312d
SAS		 8624 ++vcpu->stat.fpu_reload;
8625 trace_kvm_fpu(0);
8626}
8627
b6c7a5dc
HB		 8628int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
8629{
8630 int r;
b6c7a5dc 8631
accb757d 8632 vcpu_load(vcpu);
20b7035c 8633 kvm_sigset_activate(vcpu);
5663d8f9
PX		 8634 kvm_load_guest_fpu(vcpu);
8635
a4535290 8636 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS		 8637 if (kvm_run->immediate_exit) {
8638 r = -EINTR;
8639 goto out;
8640 }
b6c7a5dc 8641 kvm_vcpu_block(vcpu);
66450a21 8642 kvm_apic_accept_events(vcpu);
72875d8a 8643 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 8644 r = -EAGAIN;
a0595000
JS		 8645 if (signal_pending(current)) {
8646 r = -EINTR;
8647 vcpu->run->exit_reason = KVM_EXIT_INTR;
8648 ++vcpu->stat.signal_exits;
8649 }
ac9f6dc0 8650 goto out;
b6c7a5dc
HB		 8651 }
8652
01643c51
KH		 8653 if (vcpu->run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) {
8654 r = -EINVAL;
8655 goto out;
8656 }
8657
8658 if (vcpu->run->kvm_dirty_regs) {
8659 r = sync_regs(vcpu);
8660 if (r != 0)
8661 goto out;
8662 }
8663
b6c7a5dc 8664 /* re-sync apic's tpr */
35754c98 8665 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP		 8666 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
8667 r = -EINVAL;
8668 goto out;
8669 }
8670 }
b6c7a5dc 8671
716d51ab
GN		 8672 if (unlikely(vcpu->arch.complete_userspace_io)) {
8673 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
8674 vcpu->arch.complete_userspace_io = NULL;
8675 r = cui(vcpu);
8676 if (r <= 0)
5663d8f9 8677 goto out;
716d51ab
GN		 8678 } else
8679 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 8680
460df4c1
PB		 8681 if (kvm_run->immediate_exit)
8682 r = -EINTR;
8683 else
8684 r = vcpu_run(vcpu);
b6c7a5dc
HB		 8685
8686out:
5663d8f9 8687 kvm_put_guest_fpu(vcpu);
01643c51
KH		 8688 if (vcpu->run->kvm_valid_regs)
8689 store_regs(vcpu);
f1d86e46 8690 post_kvm_run_save(vcpu);
20b7035c 8691 kvm_sigset_deactivate(vcpu);
b6c7a5dc 8692
accb757d 8693 vcpu_put(vcpu);
b6c7a5dc
HB		 8694 return r;
8695}
8696
01643c51 8697static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8698{
7ae441ea
GN		 8699 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
8700 /*
8701 * We are here if userspace calls get_regs() in the middle of
8702 * instruction emulation. Registers state needs to be copied
4a969980 8703 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 8704 * that usually, but some bad designed PV devices (vmware
8705 * backdoor interface) need this to work
8706 */
dd856efa 8707 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 8708 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8709 }
de3cd117
SC		 8710 regs->rax = kvm_rax_read(vcpu);
8711 regs->rbx = kvm_rbx_read(vcpu);
8712 regs->rcx = kvm_rcx_read(vcpu);
8713 regs->rdx = kvm_rdx_read(vcpu);
8714 regs->rsi = kvm_rsi_read(vcpu);
8715 regs->rdi = kvm_rdi_read(vcpu);
e9c16c78 8716 regs->rsp = kvm_rsp_read(vcpu);
de3cd117 8717 regs->rbp = kvm_rbp_read(vcpu);
b6c7a5dc 8718#ifdef CONFIG_X86_64
de3cd117
SC		 8719 regs->r8 = kvm_r8_read(vcpu);
8720 regs->r9 = kvm_r9_read(vcpu);
8721 regs->r10 = kvm_r10_read(vcpu);
8722 regs->r11 = kvm_r11_read(vcpu);
8723 regs->r12 = kvm_r12_read(vcpu);
8724 regs->r13 = kvm_r13_read(vcpu);
8725 regs->r14 = kvm_r14_read(vcpu);
8726 regs->r15 = kvm_r15_read(vcpu);
b6c7a5dc
HB		 8727#endif
8728
5fdbf976 8729 regs->rip = kvm_rip_read(vcpu);
91586a3b 8730 regs->rflags = kvm_get_rflags(vcpu);
01643c51 8731}
b6c7a5dc 8732
01643c51
KH		 8733int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8734{
8735 vcpu_load(vcpu);
8736 __get_regs(vcpu, regs);
1fc9b76b 8737 vcpu_put(vcpu);
b6c7a5dc
HB		 8738 return 0;
8739}
8740
01643c51 8741static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
b6c7a5dc 8742{
7ae441ea
GN		 8743 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
8744 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
8745
de3cd117
SC		 8746 kvm_rax_write(vcpu, regs->rax);
8747 kvm_rbx_write(vcpu, regs->rbx);
8748 kvm_rcx_write(vcpu, regs->rcx);
8749 kvm_rdx_write(vcpu, regs->rdx);
8750 kvm_rsi_write(vcpu, regs->rsi);
8751 kvm_rdi_write(vcpu, regs->rdi);
e9c16c78 8752 kvm_rsp_write(vcpu, regs->rsp);
de3cd117 8753 kvm_rbp_write(vcpu, regs->rbp);
b6c7a5dc 8754#ifdef CONFIG_X86_64
de3cd117
SC		 8755 kvm_r8_write(vcpu, regs->r8);
8756 kvm_r9_write(vcpu, regs->r9);
8757 kvm_r10_write(vcpu, regs->r10);
8758 kvm_r11_write(vcpu, regs->r11);
8759 kvm_r12_write(vcpu, regs->r12);
8760 kvm_r13_write(vcpu, regs->r13);
8761 kvm_r14_write(vcpu, regs->r14);
8762 kvm_r15_write(vcpu, regs->r15);
b6c7a5dc
HB		 8763#endif
8764
5fdbf976 8765 kvm_rip_write(vcpu, regs->rip);
d73235d1 8766 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 8767
b4f14abd
JK		 8768 vcpu->arch.exception.pending = false;
8769
3842d135 8770 kvm_make_request(KVM_REQ_EVENT, vcpu);
01643c51 8771}
3842d135 8772
01643c51
KH		 8773int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
8774{
8775 vcpu_load(vcpu);
8776 __set_regs(vcpu, regs);
875656fe 8777 vcpu_put(vcpu);
b6c7a5dc
HB		 8778 return 0;
8779}
8780
b6c7a5dc
HB		 8781void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
8782{
8783 struct kvm_segment cs;
8784
3e6e0aab 8785 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 8786 *db = cs.db;
8787 *l = cs.l;
8788}
8789EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
8790
01643c51 8791static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8792{
89a27f4d 8793 struct desc_ptr dt;
b6c7a5dc 8794
3e6e0aab
GT		 8795 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
8796 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
8797 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
8798 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
8799 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
8800 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 8801
3e6e0aab
GT		 8802 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
8803 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 8804
8805 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 8806 sregs->idt.limit = dt.size;
8807 sregs->idt.base = dt.address;
b6c7a5dc 8808 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 8809 sregs->gdt.limit = dt.size;
8810 sregs->gdt.base = dt.address;
b6c7a5dc 8811
4d4ec087 8812 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 8813 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 8814 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 8815 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 8816 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 8817 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 8818 sregs->apic_base = kvm_get_apic_base(vcpu);
8819
0e96f31e 8820 memset(sregs->interrupt_bitmap, 0, sizeof(sregs->interrupt_bitmap));
b6c7a5dc 8821
04140b41 8822 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 8823 set_bit(vcpu->arch.interrupt.nr,
8824 (unsigned long *)sregs->interrupt_bitmap);
01643c51 8825}
16d7a191 8826
01643c51
KH		 8827int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
8828 struct kvm_sregs *sregs)
8829{
8830 vcpu_load(vcpu);
8831 __get_sregs(vcpu, sregs);
bcdec41c 8832 vcpu_put(vcpu);
b6c7a5dc
HB		 8833 return 0;
8834}
8835
62d9f0db
MT		 8836int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
8837 struct kvm_mp_state *mp_state)
8838{
fd232561 8839 vcpu_load(vcpu);
f958bd23
SC		 8840 if (kvm_mpx_supported())
8841 kvm_load_guest_fpu(vcpu);
fd232561 8842
66450a21 8843 kvm_apic_accept_events(vcpu);
6aef266c
SV		 8844 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
8845 vcpu->arch.pv.pv_unhalted)
8846 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
8847 else
8848 mp_state->mp_state = vcpu->arch.mp_state;
8849
f958bd23
SC		 8850 if (kvm_mpx_supported())
8851 kvm_put_guest_fpu(vcpu);
fd232561 8852 vcpu_put(vcpu);
62d9f0db
MT		 8853 return 0;
8854}
8855
8856int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
8857 struct kvm_mp_state *mp_state)
8858{
e83dff5e
CD		 8859 int ret = -EINVAL;
8860
8861 vcpu_load(vcpu);
8862
bce87cce 8863 if (!lapic_in_kernel(vcpu) &&
66450a21 8864 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
e83dff5e 8865 goto out;
66450a21 8866
27cbe7d6
LA		 8867 /*
8868 * KVM_MP_STATE_INIT_RECEIVED means the processor is in
8869 * INIT state; latched init should be reported using
8870 * KVM_SET_VCPU_EVENTS, so reject it here.
8871 */
8872 if ((kvm_vcpu_latch_init(vcpu) || vcpu->arch.smi_pending) &&
28bf2888
DH		 8873 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
8874 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
e83dff5e 8875 goto out;
28bf2888 8876
66450a21
JK		 8877 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
8878 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
8879 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
8880 } else
8881 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 8882 kvm_make_request(KVM_REQ_EVENT, vcpu);
e83dff5e
CD		 8883
8884 ret = 0;
8885out:
8886 vcpu_put(vcpu);
8887 return ret;
62d9f0db
MT		 8888}
8889
7f3d35fd
KW		 8890int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
8891 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 8892{
9d74191a 8893 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 8894 int ret;
e01c2426 8895
8ec4722d 8896 init_emulate_ctxt(vcpu);
c697518a 8897
7f3d35fd 8898 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 8899 has_error_code, error_code);
1051778f
SC		 8900 if (ret) {
8901 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8902 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
8903 vcpu->run->internal.ndata = 0;
60fc3d02 8904 return 0;
1051778f 8905 }
37817f29 8906
9d74191a
TY		 8907 kvm_rip_write(vcpu, ctxt->eip);
8908 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 8909 kvm_make_request(KVM_REQ_EVENT, vcpu);
60fc3d02 8910 return 1;
37817f29
IE		 8911}
8912EXPORT_SYMBOL_GPL(kvm_task_switch);
8913
3140c156 8914static int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
f2981033 8915{
37b95951 8916 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT		 8917 /*
8918 * When EFER.LME and CR0.PG are set, the processor is in
8919 * 64-bit mode (though maybe in a 32-bit code segment).
8920 * CR4.PAE and EFER.LMA must be set.
8921 */
37b95951 8922 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT		 8923 || !(sregs->efer & EFER_LMA))
8924 return -EINVAL;
8925 } else {
8926 /*
8927 * Not in 64-bit mode: EFER.LMA is clear and the code
8928 * segment cannot be 64-bit.
8929 */
8930 if (sregs->efer & EFER_LMA || sregs->cs.l)
8931 return -EINVAL;
8932 }
8933
3ca94192 8934 return kvm_valid_cr4(vcpu, sregs->cr4);
f2981033
LT		 8935}
8936
01643c51 8937static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
b6c7a5dc 8938{
58cb628d 8939 struct msr_data apic_base_msr;
b6c7a5dc 8940 int mmu_reset_needed = 0;
c4d21882 8941 int cpuid_update_needed = 0;
63f42e02 8942 int pending_vec, max_bits, idx;
89a27f4d 8943 struct desc_ptr dt;
b4ef9d4e
CD		 8944 int ret = -EINVAL;
8945
f2981033 8946 if (kvm_valid_sregs(vcpu, sregs))
8dbfb2bf 8947 goto out;
f2981033 8948
d3802286
JM		 8949 apic_base_msr.data = sregs->apic_base;
8950 apic_base_msr.host_initiated = true;
8951 if (kvm_set_apic_base(vcpu, &apic_base_msr))
b4ef9d4e 8952 goto out;
6d1068b3 8953
89a27f4d
GN		 8954 dt.size = sregs->idt.limit;
8955 dt.address = sregs->idt.base;
b6c7a5dc 8956 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 8957 dt.size = sregs->gdt.limit;
8958 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 8959 kvm_x86_ops->set_gdt(vcpu, &dt);
8960
ad312c7c 8961 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 8962 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 8963 vcpu->arch.cr3 = sregs->cr3;
cb3c1e2f 8964 kvm_register_mark_available(vcpu, VCPU_EXREG_CR3);
b6c7a5dc 8965
2d3ad1f4 8966 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 8967
f6801dff 8968 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 8969 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 8970
4d4ec087 8971 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 8972 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 8973 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 8974
fc78f519 8975 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
c4d21882
WH		 8976 cpuid_update_needed |= ((kvm_read_cr4(vcpu) ^ sregs->cr4) &
8977 (X86_CR4_OSXSAVE | X86_CR4_PKE));
b6c7a5dc 8978 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
c4d21882 8979 if (cpuid_update_needed)
00b27a3e 8980 kvm_update_cpuid(vcpu);
63f42e02
XG		 8981
8982 idx = srcu_read_lock(&vcpu->kvm->srcu);
bf03d4f9 8983 if (is_pae_paging(vcpu)) {
9f8fe504 8984 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 8985 mmu_reset_needed = 1;
8986 }
63f42e02 8987 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 8988
8989 if (mmu_reset_needed)
8990 kvm_mmu_reset_context(vcpu);
8991
a50abc3b 8992 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 8993 pending_vec = find_first_bit(
8994 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
8995 if (pending_vec < max_bits) {
66fd3f7f 8996 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 8997 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 8998 }
8999
3e6e0aab
GT		 9000 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
9001 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
9002 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
9003 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
9004 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
9005 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 9006
3e6e0aab
GT		 9007 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
9008 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 9009
5f0269f5
ME		 9010 update_cr8_intercept(vcpu);
9011
9c3e4aab 9012 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 9013 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 9014 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 9015 !is_protmode(vcpu))
9c3e4aab
MT		 9016 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9017
3842d135
AK		 9018 kvm_make_request(KVM_REQ_EVENT, vcpu);
9019
b4ef9d4e
CD		 9020 ret = 0;
9021out:
01643c51
KH		 9022 return ret;
9023}
9024
9025int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
9026 struct kvm_sregs *sregs)
9027{
9028 int ret;
9029
9030 vcpu_load(vcpu);
9031 ret = __set_sregs(vcpu, sregs);
b4ef9d4e
CD		 9032 vcpu_put(vcpu);
9033 return ret;
b6c7a5dc
HB		 9034}
9035
d0bfb940
JK		 9036int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
9037 struct kvm_guest_debug *dbg)
b6c7a5dc 9038{
355be0b9 9039 unsigned long rflags;
ae675ef0 9040 int i, r;
b6c7a5dc 9041
66b56562
CD		 9042 vcpu_load(vcpu);
9043
4f926bf2
JK		 9044 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
9045 r = -EBUSY;
9046 if (vcpu->arch.exception.pending)
2122ff5e 9047 goto out;
4f926bf2
JK		 9048 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
9049 kvm_queue_exception(vcpu, DB_VECTOR);
9050 else
9051 kvm_queue_exception(vcpu, BP_VECTOR);
9052 }
9053
91586a3b
JK		 9054 /*
9055 * Read rflags as long as potentially injected trace flags are still
9056 * filtered out.
9057 */
9058 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 9059
9060 vcpu->guest_debug = dbg->control;
9061 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
9062 vcpu->guest_debug = 0;
9063
9064 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 9065 for (i = 0; i < KVM_NR_DB_REGS; ++i)
9066 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 9067 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 9068 } else {
9069 for (i = 0; i < KVM_NR_DB_REGS; i++)
9070 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 9071 }
c8639010 9072 kvm_update_dr7(vcpu);
ae675ef0 9073
f92653ee
JK		 9074 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
9075 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
9076 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 9077
91586a3b
JK		 9078 /*
9079 * Trigger an rflags update that will inject or remove the trace
9080 * flags.
9081 */
9082 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 9083
a96036b8 9084 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 9085
4f926bf2 9086 r = 0;
d0bfb940 9087
2122ff5e 9088out:
66b56562 9089 vcpu_put(vcpu);
b6c7a5dc
HB		 9090 return r;
9091}
9092
8b006791
ZX		 9093/*
9094 * Translate a guest virtual address to a guest physical address.
9095 */
9096int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
9097 struct kvm_translation *tr)
9098{
9099 unsigned long vaddr = tr->linear_address;
9100 gpa_t gpa;
f656ce01 9101 int idx;
8b006791 9102
1da5b61d
CD		 9103 vcpu_load(vcpu);
9104
f656ce01 9105 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 9106 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 9107 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 9108 tr->physical_address = gpa;
9109 tr->valid = gpa != UNMAPPED_GVA;
9110 tr->writeable = 1;
9111 tr->usermode = 0;
8b006791 9112
1da5b61d 9113 vcpu_put(vcpu);
8b006791
ZX		 9114 return 0;
9115}
9116
d0752060
HB		 9117int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9118{
1393123e 9119 struct fxregs_state *fxsave;
d0752060 9120
1393123e 9121 vcpu_load(vcpu);
d0752060 9122
b666a4b6 9123 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060
HB		 9124 memcpy(fpu->fpr, fxsave->st_space, 128);
9125 fpu->fcw = fxsave->cwd;
9126 fpu->fsw = fxsave->swd;
9127 fpu->ftwx = fxsave->twd;
9128 fpu->last_opcode = fxsave->fop;
9129 fpu->last_ip = fxsave->rip;
9130 fpu->last_dp = fxsave->rdp;
0e96f31e 9131 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
d0752060 9132
1393123e 9133 vcpu_put(vcpu);
d0752060
HB		 9134 return 0;
9135}
9136
9137int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
9138{
6a96bc7f
CD		 9139 struct fxregs_state *fxsave;
9140
9141 vcpu_load(vcpu);
9142
b666a4b6 9143 fxsave = &vcpu->arch.guest_fpu->state.fxsave;
d0752060 9144
d0752060
HB		 9145 memcpy(fxsave->st_space, fpu->fpr, 128);
9146 fxsave->cwd = fpu->fcw;
9147 fxsave->swd = fpu->fsw;
9148 fxsave->twd = fpu->ftwx;
9149 fxsave->fop = fpu->last_opcode;
9150 fxsave->rip = fpu->last_ip;
9151 fxsave->rdp = fpu->last_dp;
0e96f31e 9152 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
d0752060 9153
6a96bc7f 9154 vcpu_put(vcpu);
d0752060
HB		 9155 return 0;
9156}
9157
01643c51
KH		 9158static void store_regs(struct kvm_vcpu *vcpu)
9159{
9160 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
9161
9162 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
9163 __get_regs(vcpu, &vcpu->run->s.regs.regs);
9164
9165 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
9166 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
9167
9168 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
9169 kvm_vcpu_ioctl_x86_get_vcpu_events(
9170 vcpu, &vcpu->run->s.regs.events);
9171}
9172
9173static int sync_regs(struct kvm_vcpu *vcpu)
9174{
9175 if (vcpu->run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)
9176 return -EINVAL;
9177
9178 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
9179 __set_regs(vcpu, &vcpu->run->s.regs.regs);
9180 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
9181 }
9182 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
9183 if (__set_sregs(vcpu, &vcpu->run->s.regs.sregs))
9184 return -EINVAL;
9185 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
9186 }
9187 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
9188 if (kvm_vcpu_ioctl_x86_set_vcpu_events(
9189 vcpu, &vcpu->run->s.regs.events))
9190 return -EINVAL;
9191 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
9192 }
9193
9194 return 0;
9195}
9196
0ee6a517 9197static void fx_init(struct kvm_vcpu *vcpu)
d0752060 9198{
b666a4b6 9199 fpstate_init(&vcpu->arch.guest_fpu->state);
782511b0 9200 if (boot_cpu_has(X86_FEATURE_XSAVES))
b666a4b6 9201 vcpu->arch.guest_fpu->state.xsave.header.xcomp_bv =
df1daba7 9202 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 9203
2acf923e
DC		 9204 /*
9205 * Ensure guest xcr0 is valid for loading
9206 */
d91cab78 9207 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 9208
ad312c7c 9209 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 9210}
d0752060 9211
897cc38e 9212int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
e9b11c17 9213{
897cc38e
SC		 9214 if (kvm_check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
9215 pr_warn_once("kvm: SMP vm created on host with unstable TSC; "
9216 "guest TSC will not be reliable\n");
7f1ea208 9217
897cc38e 9218 return 0;
e9b11c17
ZX		 9219}
9220
e529ef66 9221int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
e9b11c17 9222{
95a0d01e
SC		 9223 struct page *page;
9224 int r;
c447e76b 9225
95a0d01e
SC		 9226 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
9227 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
9228 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
9229 else
9230 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
c447e76b 9231
95a0d01e 9232 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c447e76b 9233
95a0d01e
SC		 9234 r = kvm_mmu_create(vcpu);
9235 if (r < 0)
9236 return r;
9237
9238 if (irqchip_in_kernel(vcpu->kvm)) {
95a0d01e
SC		 9239 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
9240 if (r < 0)
9241 goto fail_mmu_destroy;
4e19c36f
SS		 9242 if (kvm_apicv_activated(vcpu->kvm))
9243 vcpu->arch.apicv_active = true;
95a0d01e
SC		 9244 } else
9245 static_key_slow_inc(&kvm_no_apic_vcpu);
9246
9247 r = -ENOMEM;
9248
9249 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
9250 if (!page)
9251 goto fail_free_lapic;
9252 vcpu->arch.pio_data = page_address(page);
9253
9254 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
9255 GFP_KERNEL_ACCOUNT);
9256 if (!vcpu->arch.mce_banks)
9257 goto fail_free_pio_data;
9258 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
9259
9260 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
9261 GFP_KERNEL_ACCOUNT))
9262 goto fail_free_mce_banks;
9263
9264 vcpu->arch.user_fpu = kmem_cache_zalloc(x86_fpu_cache,
9265 GFP_KERNEL_ACCOUNT);
9266 if (!vcpu->arch.user_fpu) {
9267 pr_err("kvm: failed to allocate userspace's fpu\n");
9268 goto free_wbinvd_dirty_mask;
9269 }
9270
9271 vcpu->arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache,
9272 GFP_KERNEL_ACCOUNT);
9273 if (!vcpu->arch.guest_fpu) {
9274 pr_err("kvm: failed to allocate vcpu's fpu\n");
9275 goto free_user_fpu;
9276 }
9277 fx_init(vcpu);
9278
9279 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
9280
9281 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
9282
9283 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
9284
9285 kvm_async_pf_hash_reset(vcpu);
9286 kvm_pmu_init(vcpu);
9287
9288 vcpu->arch.pending_external_vector = -1;
9289 vcpu->arch.preempted_in_kernel = false;
9290
9291 kvm_hv_vcpu_init(vcpu);
9292
9293 r = kvm_x86_ops->vcpu_create(vcpu);
9294 if (r)
9295 goto free_guest_fpu;
e9b11c17 9296
0cf9135b 9297 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
e53d88af 9298 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
19efffa2 9299 kvm_vcpu_mtrr_init(vcpu);
ec7660cc 9300 vcpu_load(vcpu);
d28bc9dd 9301 kvm_vcpu_reset(vcpu, false);
e1732991 9302 kvm_init_mmu(vcpu, false);
e9b11c17 9303 vcpu_put(vcpu);
ec7660cc 9304 return 0;
95a0d01e
SC		 9305
9306free_guest_fpu:
9307 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
9308free_user_fpu:
9309 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9310free_wbinvd_dirty_mask:
9311 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9312fail_free_mce_banks:
9313 kfree(vcpu->arch.mce_banks);
9314fail_free_pio_data:
9315 free_page((unsigned long)vcpu->arch.pio_data);
9316fail_free_lapic:
9317 kvm_free_lapic(vcpu);
9318fail_mmu_destroy:
9319 kvm_mmu_destroy(vcpu);
9320 return r;
e9b11c17
ZX		 9321}
9322
31928aa5 9323void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 9324{
8fe8ab46 9325 struct msr_data msr;
332967a3 9326 struct kvm *kvm = vcpu->kvm;
42897d86 9327
d3457c87
RK		 9328 kvm_hv_vcpu_postcreate(vcpu);
9329
ec7660cc 9330 if (mutex_lock_killable(&vcpu->mutex))
31928aa5 9331 return;
ec7660cc 9332 vcpu_load(vcpu);
8fe8ab46
WA		 9333 msr.data = 0x0;
9334 msr.index = MSR_IA32_TSC;
9335 msr.host_initiated = true;
9336 kvm_write_tsc(vcpu, &msr);
42897d86 9337 vcpu_put(vcpu);
2d5ba19b
MT		 9338
9339 /* poll control enabled by default */
9340 vcpu->arch.msr_kvm_poll_control = 1;
9341
ec7660cc 9342 mutex_unlock(&vcpu->mutex);
42897d86 9343
630994b3
MT		 9344 if (!kvmclock_periodic_sync)
9345 return;
9346
332967a3
AJ		 9347 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
9348 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 9349}
9350
d40ccc62 9351void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 9352{
4cbc418a 9353 struct gfn_to_pfn_cache *cache = &vcpu->arch.st.cache;
95a0d01e 9354 int idx;
344d9588 9355
4cbc418a
PB		 9356 kvm_release_pfn(cache->pfn, cache->dirty, cache);
9357
50b143e1 9358 kvmclock_reset(vcpu);
e9b11c17
ZX		 9359
9360 kvm_x86_ops->vcpu_free(vcpu);
50b143e1 9361
50b143e1
SC		 9362 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
9363 kmem_cache_free(x86_fpu_cache, vcpu->arch.user_fpu);
9364 kmem_cache_free(x86_fpu_cache, vcpu->arch.guest_fpu);
95a0d01e
SC		 9365
9366 kvm_hv_vcpu_uninit(vcpu);
9367 kvm_pmu_destroy(vcpu);
9368 kfree(vcpu->arch.mce_banks);
9369 kvm_free_lapic(vcpu);
9370 idx = srcu_read_lock(&vcpu->kvm->srcu);
9371 kvm_mmu_destroy(vcpu);
9372 srcu_read_unlock(&vcpu->kvm->srcu, idx);
9373 free_page((unsigned long)vcpu->arch.pio_data);
9374 if (!lapic_in_kernel(vcpu))
9375 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17
ZX		 9376}
9377
d28bc9dd 9378void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 9379{
b7e31be3
RK		 9380 kvm_lapic_reset(vcpu, init_event);
9381
e69fab5d
PB		 9382 vcpu->arch.hflags = 0;
9383
c43203ca 9384 vcpu->arch.smi_pending = 0;
52797bf9 9385 vcpu->arch.smi_count = 0;
7460fb4a
AK		 9386 atomic_set(&vcpu->arch.nmi_queued, 0);
9387 vcpu->arch.nmi_pending = 0;
448fa4a9 9388 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 9389 kvm_clear_interrupt_queue(vcpu);
9390 kvm_clear_exception_queue(vcpu);
448fa4a9 9391
42dbaa5a 9392 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 9393 kvm_update_dr0123(vcpu);
6f43ed01 9394 vcpu->arch.dr6 = DR6_INIT;
73aaf249 9395 kvm_update_dr6(vcpu);
42dbaa5a 9396 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 9397 kvm_update_dr7(vcpu);
42dbaa5a 9398
1119022c
NA		 9399 vcpu->arch.cr2 = 0;
9400
3842d135 9401 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 9402 vcpu->arch.apf.msr_val = 0;
c9aaa895 9403 vcpu->arch.st.msr_val = 0;
3842d135 9404
12f9a48f
GC		 9405 kvmclock_reset(vcpu);
9406
af585b92
GN		 9407 kvm_clear_async_pf_completion_queue(vcpu);
9408 kvm_async_pf_hash_reset(vcpu);
9409 vcpu->arch.apf.halted = false;
3842d135 9410
a554d207
WL		 9411 if (kvm_mpx_supported()) {
9412 void *mpx_state_buffer;
9413
9414 /*
9415 * To avoid have the INIT path from kvm_apic_has_events() that be
9416 * called with loaded FPU and does not let userspace fix the state.
9417 */
f775b13e
RR		 9418 if (init_event)
9419 kvm_put_guest_fpu(vcpu);
b666a4b6 9420 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9421 XFEATURE_BNDREGS);
a554d207
WL		 9422 if (mpx_state_buffer)
9423 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
b666a4b6 9424 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu->state.xsave,
abd16d68 9425 XFEATURE_BNDCSR);
a554d207
WL		 9426 if (mpx_state_buffer)
9427 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR		 9428 if (init_event)
9429 kvm_load_guest_fpu(vcpu);
a554d207
WL		 9430 }
9431
64d60670 9432 if (!init_event) {
d28bc9dd 9433 kvm_pmu_reset(vcpu);
64d60670 9434 vcpu->arch.smbase = 0x30000;
db2336a8 9435
db2336a8 9436 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL		 9437
9438 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 9439 }
f5132b01 9440
66f7b72e
JS		 9441 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
9442 vcpu->arch.regs_avail = ~0;
9443 vcpu->arch.regs_dirty = ~0;
9444
a554d207
WL		 9445 vcpu->arch.ia32_xss = 0;
9446
d28bc9dd 9447 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 9448}
9449
2b4a273b 9450void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 9451{
9452 struct kvm_segment cs;
9453
9454 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
9455 cs.selector = vector << 8;
9456 cs.base = vector << 12;
9457 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
9458 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 9459}
9460
13a34e06 9461int kvm_arch_hardware_enable(void)
e9b11c17 9462{
ca84d1a2
ZA		 9463 struct kvm *kvm;
9464 struct kvm_vcpu *vcpu;
9465 int i;
0dd6a6ed
ZA		 9466 int ret;
9467 u64 local_tsc;
9468 u64 max_tsc = 0;
9469 bool stable, backwards_tsc = false;
18863bdd
AK		 9470
9471 kvm_shared_msr_cpu_online();
13a34e06 9472 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 9473 if (ret != 0)
9474 return ret;
9475
4ea1636b 9476 local_tsc = rdtsc();
b0c39dc6 9477 stable = !kvm_check_tsc_unstable();
0dd6a6ed
ZA		 9478 list_for_each_entry(kvm, &vm_list, vm_list) {
9479 kvm_for_each_vcpu(i, vcpu, kvm) {
9480 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 9481 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9482 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
9483 backwards_tsc = true;
9484 if (vcpu->arch.last_host_tsc > max_tsc)
9485 max_tsc = vcpu->arch.last_host_tsc;
9486 }
9487 }
9488 }
9489
9490 /*
9491 * Sometimes, even reliable TSCs go backwards. This happens on
9492 * platforms that reset TSC during suspend or hibernate actions, but
9493 * maintain synchronization. We must compensate. Fortunately, we can
9494 * detect that condition here, which happens early in CPU bringup,
9495 * before any KVM threads can be running. Unfortunately, we can't
9496 * bring the TSCs fully up to date with real time, as we aren't yet far
9497 * enough into CPU bringup that we know how much real time has actually
9285ec4c 9498 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
0dd6a6ed
ZA		 9499 * variables that haven't been updated yet.
9500 *
9501 * So we simply find the maximum observed TSC above, then record the
9502 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
9503 * the adjustment will be applied. Note that we accumulate
9504 * adjustments, in case multiple suspend cycles happen before some VCPU
9505 * gets a chance to run again. In the event that no KVM threads get a
9506 * chance to run, we will miss the entire elapsed period, as we'll have
9507 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
9508 * loose cycle time. This isn't too big a deal, since the loss will be
9509 * uniform across all VCPUs (not to mention the scenario is extremely
9510 * unlikely). It is possible that a second hibernate recovery happens
9511 * much faster than a first, causing the observed TSC here to be
9512 * smaller; this would require additional padding adjustment, which is
9513 * why we set last_host_tsc to the local tsc observed here.
9514 *
9515 * N.B. - this code below runs only on platforms with reliable TSC,
9516 * as that is the only way backwards_tsc is set above. Also note
9517 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
9518 * have the same delta_cyc adjustment applied if backwards_tsc
9519 * is detected. Note further, this adjustment is only done once,
9520 * as we reset last_host_tsc on all VCPUs to stop this from being
9521 * called multiple times (one for each physical CPU bringup).
9522 *
4a969980 9523 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 9524 * will be compensated by the logic in vcpu_load, which sets the TSC to
9525 * catchup mode. This will catchup all VCPUs to real time, but cannot
9526 * guarantee that they stay in perfect synchronization.
9527 */
9528 if (backwards_tsc) {
9529 u64 delta_cyc = max_tsc - local_tsc;
9530 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 9531 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA		 9532 kvm_for_each_vcpu(i, vcpu, kvm) {
9533 vcpu->arch.tsc_offset_adjustment += delta_cyc;
9534 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 9535 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 9536 }
9537
9538 /*
9539 * We have to disable TSC offset matching.. if you were
9540 * booting a VM while issuing an S4 host suspend....
9541 * you may have some problem. Solving this issue is
9542 * left as an exercise to the reader.
9543 */
9544 kvm->arch.last_tsc_nsec = 0;
9545 kvm->arch.last_tsc_write = 0;
9546 }
9547
9548 }
9549 return 0;
e9b11c17
ZX		 9550}
9551
13a34e06 9552void kvm_arch_hardware_disable(void)
e9b11c17 9553{
13a34e06
RK		 9554 kvm_x86_ops->hardware_disable();
9555 drop_user_return_notifiers();
e9b11c17
ZX		 9556}
9557
9558int kvm_arch_hardware_setup(void)
9559{
9e9c3fe4
NA		 9560 int r;
9561
9562 r = kvm_x86_ops->hardware_setup();
9563 if (r != 0)
9564 return r;
9565
b11306b5
SC		 9566 cr4_reserved_bits = kvm_host_cr4_reserved_bits(&boot_cpu_data);
9567
35181e86
HZ		 9568 if (kvm_has_tsc_control) {
9569 /*
9570 * Make sure the user can only configure tsc_khz values that
9571 * fit into a signed integer.
273ba457 9572 * A min value is not calculated because it will always
35181e86
HZ		 9573 * be 1 on all machines.
9574 */
9575 u64 max = min(0x7fffffffULL,
9576 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
9577 kvm_max_guest_tsc_khz = max;
9578
ad721883 9579 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 9580 }
ad721883 9581
139a12cf
AL		 9582 if (boot_cpu_has(X86_FEATURE_XSAVES))
9583 rdmsrl(MSR_IA32_XSS, host_xss);
9584
9e9c3fe4
NA		 9585 kvm_init_msr_list();
9586 return 0;
e9b11c17
ZX		 9587}
9588
9589void kvm_arch_hardware_unsetup(void)
9590{
9591 kvm_x86_ops->hardware_unsetup();
9592}
9593
f257d6dc 9594int kvm_arch_check_processor_compat(void)
e9b11c17 9595{
f1cdecf5
SC		 9596 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
9597
9598 WARN_ON(!irqs_disabled());
9599
9600 if (kvm_host_cr4_reserved_bits(c) != cr4_reserved_bits)
9601 return -EIO;
9602
f257d6dc 9603 return kvm_x86_ops->check_processor_compatibility();
d71ba788
PB		 9604}
9605
9606bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
9607{
9608 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
9609}
9610EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
9611
9612bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
9613{
9614 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX		 9615}
9616
54e9818f 9617struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 9618EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 9619
e790d9ef
RK		 9620void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
9621{
b35e5548
LX		 9622 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
9623
c595ceee 9624 vcpu->arch.l1tf_flush_l1d = true;
b35e5548
LX		 9625 if (pmu->version && unlikely(pmu->event_count)) {
9626 pmu->need_cleanup = true;
9627 kvm_make_request(KVM_REQ_PMU, vcpu);
9628 }
ae97a3b8 9629 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 9630}
9631
e08b9637 9632int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 9633{
e08b9637
CO		 9634 if (type)
9635 return -EINVAL;
9636
6ef768fa 9637 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 9638 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
10605204 9639 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
1aa9b957 9640 INIT_LIST_HEAD(&kvm->arch.lpage_disallowed_mmu_pages);
4d5c5d0f 9641 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 9642 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 9643
5550af4d
SY		 9644 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
9645 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 9646 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
9647 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
9648 &kvm->arch.irq_sources_bitmap);
5550af4d 9649
038f8c11 9650 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 9651 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 9652 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
9653
9285ec4c 9654 kvm->arch.kvmclock_offset = -ktime_get_boottime_ns();
d828199e 9655 pvclock_update_vm_gtod_copy(kvm);
53f658b3 9656
6fbbde9a
DS		 9657 kvm->arch.guest_can_read_msr_platform_info = true;
9658
7e44e449 9659 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 9660 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 9661
cbc0236a 9662 kvm_hv_init_vm(kvm);
0eb05bf2 9663 kvm_page_track_init(kvm);
13d268ca 9664 kvm_mmu_init_vm(kvm);
0eb05bf2 9665
92735b1b 9666 return kvm_x86_ops->vm_init(kvm);
d19a9cd2
ZX		 9667}
9668
1aa9b957
JS		 9669int kvm_arch_post_init_vm(struct kvm *kvm)
9670{
9671 return kvm_mmu_post_init_vm(kvm);
9672}
9673
d19a9cd2
ZX		 9674static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
9675{
ec7660cc 9676 vcpu_load(vcpu);
d19a9cd2
ZX		 9677 kvm_mmu_unload(vcpu);
9678 vcpu_put(vcpu);
9679}
9680
9681static void kvm_free_vcpus(struct kvm *kvm)
9682{
9683 unsigned int i;
988a2cae 9684 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 9685
9686 /*
9687 * Unpin any mmu pages first.
9688 */
af585b92
GN		 9689 kvm_for_each_vcpu(i, vcpu, kvm) {
9690 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 9691 kvm_unload_vcpu_mmu(vcpu);
af585b92 9692 }
988a2cae 9693 kvm_for_each_vcpu(i, vcpu, kvm)
4543bdc0 9694 kvm_vcpu_destroy(vcpu);
988a2cae
GN		 9695
9696 mutex_lock(&kvm->lock);
9697 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
9698 kvm->vcpus[i] = NULL;
d19a9cd2 9699
988a2cae
GN		 9700 atomic_set(&kvm->online_vcpus, 0);
9701 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 9702}
9703
ad8ba2cd
SY		 9704void kvm_arch_sync_events(struct kvm *kvm)
9705{
332967a3 9706 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 9707 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 9708 kvm_free_pit(kvm);
ad8ba2cd
SY		 9709}
9710
1d8007bd 9711int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB		 9712{
9713 int i, r;
25188b99 9714 unsigned long hva;
f0d648bd
PB		 9715 struct kvm_memslots *slots = kvm_memslots(kvm);
9716 struct kvm_memory_slot *slot, old;
9da0e4d5
PB		 9717
9718 /* Called with kvm->slots_lock held. */
1d8007bd
PB		 9719 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
9720 return -EINVAL;
9da0e4d5 9721
f0d648bd
PB		 9722 slot = id_to_memslot(slots, id);
9723 if (size) {
b21629da 9724 if (slot->npages)
f0d648bd
PB		 9725 return -EEXIST;
9726
9727 /*
9728 * MAP_SHARED to prevent internal slot pages from being moved
9729 * by fork()/COW.
9730 */
9731 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
9732 MAP_SHARED | MAP_ANONYMOUS, 0);
9733 if (IS_ERR((void *)hva))
9734 return PTR_ERR((void *)hva);
9735 } else {
9736 if (!slot->npages)
9737 return 0;
9738
9739 hva = 0;
9740 }
9741
9742 old = *slot;
9da0e4d5 9743 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 9744 struct kvm_userspace_memory_region m;
9da0e4d5 9745
1d8007bd
PB		 9746 m.slot = id | (i << 16);
9747 m.flags = 0;
9748 m.guest_phys_addr = gpa;
f0d648bd 9749 m.userspace_addr = hva;
1d8007bd 9750 m.memory_size = size;
9da0e4d5
PB		 9751 r = __kvm_set_memory_region(kvm, &m);
9752 if (r < 0)
9753 return r;
9754 }
9755
103c763c
EB		 9756 if (!size)
9757 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 9758
9da0e4d5
PB		 9759 return 0;
9760}
9761EXPORT_SYMBOL_GPL(__x86_set_memory_region);
9762
1aa9b957
JS		 9763void kvm_arch_pre_destroy_vm(struct kvm *kvm)
9764{
9765 kvm_mmu_pre_destroy_vm(kvm);
9766}
9767
d19a9cd2
ZX		 9768void kvm_arch_destroy_vm(struct kvm *kvm)
9769{
27469d29
AH		 9770 if (current->mm == kvm->mm) {
9771 /*
9772 * Free memory regions allocated on behalf of userspace,
9773 * unless the the memory map has changed due to process exit
9774 * or fd copying.
9775 */
6a3c623b
PX		 9776 mutex_lock(&kvm->slots_lock);
9777 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
9778 0, 0);
9779 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
9780 0, 0);
9781 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
9782 mutex_unlock(&kvm->slots_lock);
27469d29 9783 }
03543133
SS		 9784 if (kvm_x86_ops->vm_destroy)
9785 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX		 9786 kvm_pic_destroy(kvm);
9787 kvm_ioapic_destroy(kvm);
d19a9cd2 9788 kvm_free_vcpus(kvm);
af1bae54 9789 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
66bb8a06 9790 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
13d268ca 9791 kvm_mmu_uninit_vm(kvm);
2beb6dad 9792 kvm_page_track_cleanup(kvm);
cbc0236a 9793 kvm_hv_destroy_vm(kvm);
d19a9cd2 9794}
0de10343 9795
5587027c 9796void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 9797 struct kvm_memory_slot *dont)
9798{
9799 int i;
9800
d89cc617
TY		 9801 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
9802 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 9803 kvfree(free->arch.rmap[i]);
d89cc617 9804 free->arch.rmap[i] = NULL;
77d11309 9805 }
d89cc617
TY		 9806 if (i == 0)
9807 continue;
9808
9809 if (!dont || free->arch.lpage_info[i - 1] !=
9810 dont->arch.lpage_info[i - 1]) {
548ef284 9811 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 9812 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9813 }
9814 }
21ebbeda
XG		 9815
9816 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY		 9817}
9818
5587027c
AK		 9819int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
9820 unsigned long npages)
db3fe4eb
TY		 9821{
9822 int i;
9823
d89cc617 9824 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 9825 struct kvm_lpage_info *linfo;
db3fe4eb
TY		 9826 unsigned long ugfn;
9827 int lpages;
d89cc617 9828 int level = i + 1;
db3fe4eb
TY		 9829
9830 lpages = gfn_to_index(slot->base_gfn + npages - 1,
9831 slot->base_gfn, level) + 1;
9832
d89cc617 9833 slot->arch.rmap[i] =
778e1cdd 9834 kvcalloc(lpages, sizeof(*slot->arch.rmap[i]),
254272ce 9835 GFP_KERNEL_ACCOUNT);
d89cc617 9836 if (!slot->arch.rmap[i])
77d11309 9837 goto out_free;
d89cc617
TY		 9838 if (i == 0)
9839 continue;
77d11309 9840
254272ce 9841 linfo = kvcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
92f94f1e 9842 if (!linfo)
db3fe4eb
TY		 9843 goto out_free;
9844
92f94f1e
XG		 9845 slot->arch.lpage_info[i - 1] = linfo;
9846
db3fe4eb 9847 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9848 linfo[0].disallow_lpage = 1;
db3fe4eb 9849 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 9850 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY		 9851 ugfn = slot->userspace_addr >> PAGE_SHIFT;
9852 /*
9853 * If the gfn and userspace address are not aligned wrt each
9854 * other, or if explicitly asked to, disable large page
9855 * support for this slot
9856 */
9857 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
9858 !kvm_largepages_enabled()) {
9859 unsigned long j;
9860
9861 for (j = 0; j < lpages; ++j)
92f94f1e 9862 linfo[j].disallow_lpage = 1;
db3fe4eb
TY		 9863 }
9864 }
9865
21ebbeda
XG		 9866 if (kvm_page_track_create_memslot(slot, npages))
9867 goto out_free;
9868
db3fe4eb
TY		 9869 return 0;
9870
9871out_free:
d89cc617 9872 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 9873 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 9874 slot->arch.rmap[i] = NULL;
9875 if (i == 0)
9876 continue;
9877
548ef284 9878 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 9879 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 9880 }
9881 return -ENOMEM;
9882}
9883
15248258 9884void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
e59dbe09 9885{
91724814
BO		 9886 struct kvm_vcpu *vcpu;
9887 int i;
9888
e6dff7d1
TY		 9889 /*
9890 * memslots->generation has been incremented.
9891 * mmio generation may have reached its maximum value.
9892 */
15248258 9893 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
91724814
BO		 9894
9895 /* Force re-initialization of steal_time cache */
9896 kvm_for_each_vcpu(i, vcpu, kvm)
9897 kvm_vcpu_kick(vcpu);
e59dbe09
TY		 9898}
9899
f7784b8e
MT		 9900int kvm_arch_prepare_memory_region(struct kvm *kvm,
9901 struct kvm_memory_slot *memslot,
09170a49 9902 const struct kvm_userspace_memory_region *mem,
7b6195a9 9903 enum kvm_mr_change change)
0de10343 9904{
f7784b8e
MT		 9905 return 0;
9906}
9907
88178fd4
KH		 9908static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
9909 struct kvm_memory_slot *new)
9910{
9911 /* Still write protect RO slot */
9912 if (new->flags & KVM_MEM_READONLY) {
9913 kvm_mmu_slot_remove_write_access(kvm, new);
9914 return;
9915 }
9916
9917 /*
9918 * Call kvm_x86_ops dirty logging hooks when they are valid.
9919 *
9920 * kvm_x86_ops->slot_disable_log_dirty is called when:
9921 *
9922 * - KVM_MR_CREATE with dirty logging is disabled
9923 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
9924 *
9925 * The reason is, in case of PML, we need to set D-bit for any slots
9926 * with dirty logging disabled in order to eliminate unnecessary GPA
0a03cbda 9927 * logging in PML buffer (and potential PML buffer full VMEXIT). This
88178fd4 9928 * guarantees leaving PML enabled during guest's lifetime won't have
bdd303cb 9929 * any additional overhead from PML when guest is running with dirty
88178fd4
KH		 9930 * logging disabled for memory slots.
9931 *
9932 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
9933 * to dirty logging mode.
9934 *
9935 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
9936 *
9937 * In case of write protect:
9938 *
9939 * Write protect all pages for dirty logging.
9940 *
9941 * All the sptes including the large sptes which point to this
9942 * slot are set to readonly. We can not create any new large
9943 * spte on this slot until the end of the logging.
9944 *
9945 * See the comments in fast_page_fault().
9946 */
9947 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
9948 if (kvm_x86_ops->slot_enable_log_dirty)
9949 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
9950 else
9951 kvm_mmu_slot_remove_write_access(kvm, new);
9952 } else {
9953 if (kvm_x86_ops->slot_disable_log_dirty)
9954 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
9955 }
9956}
9957
f7784b8e 9958void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 9959 const struct kvm_userspace_memory_region *mem,
8482644a 9960 const struct kvm_memory_slot *old,
f36f3f28 9961 const struct kvm_memory_slot *new,
8482644a 9962 enum kvm_mr_change change)
f7784b8e 9963{
48c0e4e9 9964 if (!kvm->arch.n_requested_mmu_pages)
4d66623c
WY		 9965 kvm_mmu_change_mmu_pages(kvm,
9966 kvm_mmu_calculate_default_mmu_pages(kvm));
1c91cad4 9967
3ea3b7fa
WL		 9968 /*
9969 * Dirty logging tracks sptes in 4k granularity, meaning that large
9970 * sptes have to be split. If live migration is successful, the guest
9971 * in the source machine will be destroyed and large sptes will be
9972 * created in the destination. However, if the guest continues to run
9973 * in the source machine (for example if live migration fails), small
9974 * sptes will remain around and cause bad performance.
9975 *
9976 * Scan sptes if dirty logging has been stopped, dropping those
9977 * which can be collapsed into a single large-page spte. Later
9978 * page faults will create the large-page sptes.
319109a2
SC		 9979 *
9980 * There is no need to do this in any of the following cases:
9981 * CREATE: No dirty mappings will already exist.
9982 * MOVE/DELETE: The old mappings will already have been cleaned up by
9983 * kvm_arch_flush_shadow_memslot()
3ea3b7fa 9984 */
319109a2 9985 if (change == KVM_MR_FLAGS_ONLY &&
3ea3b7fa
WL		 9986 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
9987 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
9988 kvm_mmu_zap_collapsible_sptes(kvm, new);
9989
c972f3b1 9990 /*
88178fd4 9991 * Set up write protection and/or dirty logging for the new slot.
c126d94f 9992 *
88178fd4
KH		 9993 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
9994 * been zapped so no dirty logging staff is needed for old slot. For
9995 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
9996 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 9997 *
9998 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 9999 */
88178fd4 10000 if (change != KVM_MR_DELETE)
f36f3f28 10001 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 10002}
1d737c8a 10003
2df72e9b 10004void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 10005{
7390de1e 10006 kvm_mmu_zap_all(kvm);
34d4cb8f
MT		 10007}
10008
2df72e9b
MT		 10009void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
10010 struct kvm_memory_slot *slot)
10011{
ae7cd873 10012 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT		 10013}
10014
e6c67d8c
LA		 10015static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
10016{
10017 return (is_guest_mode(vcpu) &&
10018 kvm_x86_ops->guest_apic_has_interrupt &&
10019 kvm_x86_ops->guest_apic_has_interrupt(vcpu));
10020}
10021
5d9bc648
PB		 10022static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
10023{
10024 if (!list_empty_careful(&vcpu->async_pf.done))
10025 return true;
10026
10027 if (kvm_apic_has_events(vcpu))
10028 return true;
10029
10030 if (vcpu->arch.pv.pv_unhalted)
10031 return true;
10032
a5f01f8e
WL		 10033 if (vcpu->arch.exception.pending)
10034 return true;
10035
47a66eed
Z		 10036 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10037 (vcpu->arch.nmi_pending &&
10038 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB		 10039 return true;
10040
47a66eed
Z		 10041 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
10042 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB		 10043 return true;
10044
5d9bc648 10045 if (kvm_arch_interrupt_allowed(vcpu) &&
e6c67d8c
LA		 10046 (kvm_cpu_has_interrupt(vcpu) ||
10047 kvm_guest_apic_has_interrupt(vcpu)))
5d9bc648
PB		 10048 return true;
10049
1f4b34f8
AS		 10050 if (kvm_hv_has_stimer_pending(vcpu))
10051 return true;
10052
5d9bc648
PB		 10053 return false;
10054}
10055
1d737c8a
ZX		 10056int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
10057{
5d9bc648 10058 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 10059}
5736199a 10060
17e433b5
WL		 10061bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
10062{
10063 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
10064 return true;
10065
10066 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
10067 kvm_test_request(KVM_REQ_SMI, vcpu) ||
10068 kvm_test_request(KVM_REQ_EVENT, vcpu))
10069 return true;
10070
10071 if (vcpu->arch.apicv_active && kvm_x86_ops->dy_apicv_has_pending_interrupt(vcpu))
10072 return true;
10073
10074 return false;
10075}
10076
199b5763
LM		 10077bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
10078{
de63ad4c 10079 return vcpu->arch.preempted_in_kernel;
199b5763
LM		 10080}
10081
b6d33834 10082int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 10083{
b6d33834 10084 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 10085}
78646121
GN		 10086
10087int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
10088{
10089 return kvm_x86_ops->interrupt_allowed(vcpu);
10090}
229456fc 10091
82b32774 10092unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 10093{
82b32774
NA		 10094 if (is_64_bit_mode(vcpu))
10095 return kvm_rip_read(vcpu);
10096 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
10097 kvm_rip_read(vcpu));
10098}
10099EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 10100
82b32774
NA		 10101bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
10102{
10103 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 10104}
10105EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
10106
94fe45da
JK		 10107unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
10108{
10109 unsigned long rflags;
10110
10111 rflags = kvm_x86_ops->get_rflags(vcpu);
10112 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 10113 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 10114 return rflags;
10115}
10116EXPORT_SYMBOL_GPL(kvm_get_rflags);
10117
6addfc42 10118static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 10119{
10120 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 10121 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 10122 rflags |= X86_EFLAGS_TF;
94fe45da 10123 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 10124}
10125
10126void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
10127{
10128 __kvm_set_rflags(vcpu, rflags);
3842d135 10129 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 10130}
10131EXPORT_SYMBOL_GPL(kvm_set_rflags);
10132
56028d08
GN		 10133void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
10134{
10135 int r;
10136
44dd3ffa 10137 if ((vcpu->arch.mmu->direct_map != work->arch.direct_map) ||
f2e10669 10138 work->wakeup_all)
56028d08
GN		 10139 return;
10140
10141 r = kvm_mmu_reload(vcpu);
10142 if (unlikely(r))
10143 return;
10144
44dd3ffa
VK		 10145 if (!vcpu->arch.mmu->direct_map &&
10146 work->arch.cr3 != vcpu->arch.mmu->get_cr3(vcpu))
fb67e14f
XG		 10147 return;
10148
736c291c 10149 vcpu->arch.mmu->page_fault(vcpu, work->cr2_or_gpa, 0, true);
56028d08
GN		 10150}
10151
af585b92
GN		 10152static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
10153{
10154 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
10155}
10156
10157static inline u32 kvm_async_pf_next_probe(u32 key)
10158{
10159 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
10160}
10161
10162static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10163{
10164 u32 key = kvm_async_pf_hash_fn(gfn);
10165
10166 while (vcpu->arch.apf.gfns[key] != ~0)
10167 key = kvm_async_pf_next_probe(key);
10168
10169 vcpu->arch.apf.gfns[key] = gfn;
10170}
10171
10172static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
10173{
10174 int i;
10175 u32 key = kvm_async_pf_hash_fn(gfn);
10176
10177 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 10178 (vcpu->arch.apf.gfns[key] != gfn &&
10179 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 10180 key = kvm_async_pf_next_probe(key);
10181
10182 return key;
10183}
10184
10185bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10186{
10187 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
10188}
10189
10190static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
10191{
10192 u32 i, j, k;
10193
10194 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
10195 while (true) {
10196 vcpu->arch.apf.gfns[i] = ~0;
10197 do {
10198 j = kvm_async_pf_next_probe(j);
10199 if (vcpu->arch.apf.gfns[j] == ~0)
10200 return;
10201 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
10202 /*
10203 * k lies cyclically in ]i,j]
10204 * | i.k.j |
10205 * |....j i.k.| or |.k..j i...|
10206 */
10207 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
10208 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
10209 i = j;
10210 }
10211}
10212
7c90705b
GN		 10213static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
10214{
4e335d9e
PB		 10215
10216 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
10217 sizeof(val));
7c90705b
GN		 10218}
10219
9a6e7c39
WL		 10220static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
10221{
10222
10223 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
10224 sizeof(u32));
10225}
10226
1dfdb45e
PB		 10227static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
10228{
10229 if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu))
10230 return false;
10231
10232 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
10233 (vcpu->arch.apf.send_user_only &&
10234 kvm_x86_ops->get_cpl(vcpu) == 0))
10235 return false;
10236
10237 return true;
10238}
10239
10240bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
10241{
10242 if (unlikely(!lapic_in_kernel(vcpu) ||
10243 kvm_event_needs_reinjection(vcpu) ||
10244 vcpu->arch.exception.pending))
10245 return false;
10246
10247 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
10248 return false;
10249
10250 /*
10251 * If interrupts are off we cannot even use an artificial
10252 * halt state.
10253 */
10254 return kvm_x86_ops->interrupt_allowed(vcpu);
10255}
10256
af585b92
GN		 10257void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
10258 struct kvm_async_pf *work)
10259{
6389ee94
AK		 10260 struct x86_exception fault;
10261
736c291c 10262 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
af585b92 10263 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b 10264
1dfdb45e
PB		 10265 if (kvm_can_deliver_async_pf(vcpu) &&
10266 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 10267 fault.vector = PF_VECTOR;
10268 fault.error_code_valid = true;
10269 fault.error_code = 0;
10270 fault.nested_page_fault = false;
10271 fault.address = work->arch.token;
adfe20fb 10272 fault.async_page_fault = true;
6389ee94 10273 kvm_inject_page_fault(vcpu, &fault);
1dfdb45e
PB		 10274 } else {
10275 /*
10276 * It is not possible to deliver a paravirtualized asynchronous
10277 * page fault, but putting the guest in an artificial halt state
10278 * can be beneficial nevertheless: if an interrupt arrives, we
10279 * can deliver it timely and perhaps the guest will schedule
10280 * another process. When the instruction that triggered a page
10281 * fault is retried, hopefully the page will be ready in the host.
10282 */
10283 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7c90705b 10284 }
af585b92
GN		 10285}
10286
10287void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
10288 struct kvm_async_pf *work)
10289{
6389ee94 10290 struct x86_exception fault;
9a6e7c39 10291 u32 val;
6389ee94 10292
f2e10669 10293 if (work->wakeup_all)
7c90705b
GN		 10294 work->arch.token = ~0; /* broadcast wakeup */
10295 else
10296 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
736c291c 10297 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
7c90705b 10298
9a6e7c39
WL		 10299 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
10300 !apf_get_user(vcpu, &val)) {
10301 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
10302 vcpu->arch.exception.pending &&
10303 vcpu->arch.exception.nr == PF_VECTOR &&
10304 !apf_put_user(vcpu, 0)) {
10305 vcpu->arch.exception.injected = false;
10306 vcpu->arch.exception.pending = false;
10307 vcpu->arch.exception.nr = 0;
10308 vcpu->arch.exception.has_error_code = false;
10309 vcpu->arch.exception.error_code = 0;
c851436a
JM		 10310 vcpu->arch.exception.has_payload = false;
10311 vcpu->arch.exception.payload = 0;
9a6e7c39
WL		 10312 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
10313 fault.vector = PF_VECTOR;
10314 fault.error_code_valid = true;
10315 fault.error_code = 0;
10316 fault.nested_page_fault = false;
10317 fault.address = work->arch.token;
10318 fault.async_page_fault = true;
10319 kvm_inject_page_fault(vcpu, &fault);
10320 }
7c90705b 10321 }
e6d53e3b 10322 vcpu->arch.apf.halted = false;
a4fa1635 10323 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 10324}
10325
10326bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
10327{
10328 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
10329 return true;
10330 else
9bc1f09f 10331 return kvm_can_do_async_pf(vcpu);
af585b92
GN		 10332}
10333
5544eb9b
PB		 10334void kvm_arch_start_assignment(struct kvm *kvm)
10335{
10336 atomic_inc(&kvm->arch.assigned_device_count);
10337}
10338EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
10339
10340void kvm_arch_end_assignment(struct kvm *kvm)
10341{
10342 atomic_dec(&kvm->arch.assigned_device_count);
10343}
10344EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
10345
10346bool kvm_arch_has_assigned_device(struct kvm *kvm)
10347{
10348 return atomic_read(&kvm->arch.assigned_device_count);
10349}
10350EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
10351
e0f0bbc5
AW		 10352void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
10353{
10354 atomic_inc(&kvm->arch.noncoherent_dma_count);
10355}
10356EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
10357
10358void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
10359{
10360 atomic_dec(&kvm->arch.noncoherent_dma_count);
10361}
10362EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
10363
10364bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
10365{
10366 return atomic_read(&kvm->arch.noncoherent_dma_count);
10367}
10368EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
10369
14717e20
AW		 10370bool kvm_arch_has_irq_bypass(void)
10371{
92735b1b 10372 return true;
14717e20
AW		 10373}
10374
87276880
FW		 10375int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
10376 struct irq_bypass_producer *prod)
10377{
10378 struct kvm_kernel_irqfd *irqfd =
10379 container_of(cons, struct kvm_kernel_irqfd, consumer);
10380
14717e20 10381 irqfd->producer = prod;
87276880 10382
14717e20
AW		 10383 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
10384 prod->irq, irqfd->gsi, 1);
87276880
FW		 10385}
10386
10387void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
10388 struct irq_bypass_producer *prod)
10389{
10390 int ret;
10391 struct kvm_kernel_irqfd *irqfd =
10392 container_of(cons, struct kvm_kernel_irqfd, consumer);
10393
87276880
FW		 10394 WARN_ON(irqfd->producer != prod);
10395 irqfd->producer = NULL;
10396
10397 /*
10398 * When producer of consumer is unregistered, we change back to
10399 * remapped mode, so we can re-use the current implementation
bb3541f1 10400 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW		 10401 * int this case doesn't want to receive the interrupts.
10402 */
10403 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
10404 if (ret)
10405 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
10406 " fails: %d\n", irqfd->consumer.token, ret);
10407}
10408
10409int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
10410 uint32_t guest_irq, bool set)
10411{
87276880
FW		 10412 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
10413}
10414
52004014
FW		 10415bool kvm_vector_hashing_enabled(void)
10416{
10417 return vector_hashing;
10418}
52004014 10419
2d5ba19b
MT		 10420bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
10421{
10422 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
10423}
10424EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
10425
6441fa61
PB		 10426u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu)
10427{
10428 uint64_t bits = SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD;
10429
10430 /* The STIBP bit doesn't fault even if it's not advertised */
10431 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
10432 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))
10433 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10434 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
10435 !boot_cpu_has(X86_FEATURE_AMD_IBRS))
10436 bits &= ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP);
10437
10438 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL_SSBD) &&
10439 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
10440 bits &= ~SPEC_CTRL_SSBD;
10441 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
10442 !boot_cpu_has(X86_FEATURE_AMD_SSBD))
10443 bits &= ~SPEC_CTRL_SSBD;
10444
10445 return bits;
10446}
10447EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits);
2d5ba19b 10448
229456fc 10449EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 10450EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT		 10451EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
10452EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
10453EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
10454EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 10455EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 10456EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 10457EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 10458EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
5497b955 10459EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
ec1ff790 10460EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 10461EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 10462EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 10463EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
4f75bcc3 10464EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
843e4330 10465EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 10466EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS		 10467EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
10468EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
Linux 6.x block layer and io_uring tree(s)